1981 I APX 86 88 Users Manual
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iAPX 86, 88 USER'S MANUAL
AUGUST 1981
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or
disclosure is subject to restrictions stated in Intel's software license, or as defjned in ASPR 7-1 04.9 (a) (9). Intel Corporation
assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit
patent licenses are implied.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of
Intel Corporation.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
BXP
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i
ICE
ICS
im
Insite
Intel
Intelevision
Intellec
iSBC
iSBX
Library Manager
MCS
Megachassis
Micromainframe
Micromap
MULTIBUS
MUL TIMODULE
Plug-A-Bubble
PROMPT
Promware
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MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk
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Additional copies of this manual or other Intel literature may be obtained from:
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© INTEL CORPORATION. 1981
ii
AFN·01300C·1
Table of Contents
CHAPTER 1
Introduction
Manual Organization ...................
iAPX Nomenclature ....................
iAPX 86 and iAPX 88 Architecture .......
Memory Segmentation ..................
Addressing Structure ...................
Operation Register Set ..................
Instruction Set ........................ 2-30
Data Transfer Instructions .............. 2-31
Arithmetic Instructions ................. 2-33
Bit Manipulation Instructions ........... 2-38
String Instructions ..................... 2-40
Program Transfer Instructions .......... 2-43
Processor Control Instructions ......... 2-47
Instruction Set Reference
Information ............................ 2-48
Addressing Modes .................... 2-68
Register and Immediate Operands ...... 2-68
Memory Addressing Modes ............. 2-68
I/O Port Addressing .................... 2-72
Programming Facilities ................ 2-72
Software Development Overview ....... 2-73
PL/M-86 ................................ 2-75
ASM-86 ............................... 2-83
L1NK-86 ............................... 2-90
LOC-86 ............................... 2-90
LI B-86 ................................ 2-91
OH-86 ................................. 2-91
CONV-86 .............................. 2-92
Sample Programs ..................... 2-92
Programming Guidelines .............. 2-96
Programming Examples .............. 2-100
1-1
1-1
1-2
1-2
1-2
1-4
CHAPTER 2
iAPX 86, 88 Central Processing Units
Processor Overview .................... 2-1
Processor Architecture ................. 2-3
Execution Unit .......................... 2-5
Bus Interface Unit ...................... 2-5
General Registers ....................... 2-6
Segment Registers ...................... 2-7
Instruction Pointer ...................... 2-7
Flags .................................. 2-7
8080/8085 Register and Flag
Correspondence ............ ; .. ; ........ 2-8
Mode Selection ......................... 2-8
Memory ................................ 2-8
Storage Organization ................... 2-8
Segmentation ......................... 2-10
Physical Add ress Generation ........... 2-11
Dynamically Relocatable Code .......... 2-13
Stack Implementation .................. 2-14
Dedicated and Reserved
Memory Locations ..................... 2-14
8086/8088 Memory Access
Differences ............................ 2-15
Input/Output .......................... 2-15
Input/Output Space .................... 2-16
Restricted I/O Locations ................ 2-16
8086/8088 Memory Access
Differences ............................ 2-16
Memory-Mapped I/O ................... 2-16
Direct Memory Access ................. 2-17
8089 Input/Output Processor (lOP) ...... 2-17
Multiprocessing Features ............. 2-17
Bus Lock ............................. 2-17
WAITandTEST ........................ 2-18
Escape ................................ 2-19
Request/Grant Lines ................... 2-20
Multibus™ Architecture ................ 2-21
8289 Bus Arbiter ........................ 2-22
Process Control and Monitoring ....... 2-22
Interrupts ............................. 2-22
System Reset .......................... 2-29
Instruction Queue Status ............... 2-29
Processor Halt ......................... 2-29
Status Lines ........................... 2-30
CHAPTER 3
The 8089 Input/Output Processor
Processor Overview .................... 3-1
Evolution ............................... 3-1
Principles of Operation ................. 3-2
Applications ........................... 3-12
Processor Architecture ................ 3-13
Common Control Unit (CCU) ........... 3-13
Arithmetic/Logic Unit (ALU) ............ : 3-13
Assembly/Disassembly Registers ........ 3-14
Instruction Fetch Unit .................. 3-14
Bus Interface Unit (BIU) ................ 3-16
Channels .............................. 3-16
Memory .............................. 3-21
Storage Organization .................. 3-22
Dedicated and Reserved
Memory Locations ..................... 3-23
Dynamic Relocation ................... 3-23
Memory Access ........................ 3-24
Input/Output .......................... 3-25
Programmed I/O ....................... 3-25
DMA Transfers ......................... 3-27
Multiprocessing Features ............. 3-34
Bus Arbitration ........................ 3-34
Bus Load Limit ........................ 3-36
Bus Lock ............................. 3-37
iii
CHAPTER 3 (Continued)
APPENDIX A
The 8089 Input/Output Processor
Processor Control and
Monitoring ............................ 3-37
Initialization ........................... 3-37
Channel Commands ................... 3-40
DRO (DMA Request) ........... ; ....... 3-43
EXT (External Terminate) ............... 3-43
Interrupts ............................. 3-43
Status Lines ........................... 3-43
Instruction Set ........................ 3-44
Data Transfer Instructions .............. 3-44
Arithmetic Instructions ................. 3-45
Logical and Bit Manipulation
Instructions ........................... 3-46
Program Transfer Instructions .......... 3-48
Processor Control Instructions ......... 3-49
Instruction Set Reference
Information ............................ 3-51
Addressing Modes .................... 3-59
Register and Immediate Operands ...... 3-59
Memory Addressing Modes ............. 3-59
Programming Facilities ................ 3-63
ASM-89 ............................... 3-63
Linking and Locating ASM-89
Modules .............................. 3-76
Programming Guidelines .............. 3-79
Programming Examples ............... 3-81
Application Notes
AP-67 8086 System Design .............. A-3
AP-61 Multitasking for the 8086 ........ A-67
AP-50 Debugging Strategies and
Considerations for 8089 Systems ....... A-85
AP-51 Designing 8086, 8088, 8089
Multiprocessing Systems with the 8289
Bus Arbiter ........................... A-lll
AP-59 Using the 8259A Programmable
Interrupt Controller ................... A-135
AP-28A Intel® Multibus™ Interfacing ... A-175
APPENDIX B
Device Specifications
iAPX 86/10 ............................. B-1
Military iAPX 86/10 .................... B-25
18086 ................................. B-26
iAPX 88/10 ............................ B-27
8089 HMOS I/O ........................ B-53
8259N8259A-2/8259A-8 ................ B-67
8282/8283 ............................. B-84
18282/8283 ............................ B-89
8284A ............. ; .................. B-90
M8284 ... ; ............................ B-98
18284 ................................. B-99
18286/8287 ........................... B-1 00
8288 ., ............................... B-l0l
18288 ................................ B-1 08
8289 ................................. B-l09
Intellec Series II ...................... B-120
Intellec Series III ..................... B-124
PUM 86,88 .......................... 8-131
FORTRAN 86,88 ...................... 8-136
PASCAL 86,88 ...... , ................. B-139
8086/8088 Software .................. B-142
8087 Software Support ............... 8-152
8089 Assembler Support Pack ......... 8-155
ICE 86A ............................... 8-157
ICE 86/88A ........................... 8-165
CHAPTER 4
Hardware Reference Information
Introduction ............................ 4-1
8086 and 8088 CPUs .................... 4-1
CPU Architecture ........ ; .............. 4-1
Bus Operation .......................... 4-5
Clock Circuit .......................... 4-10
Minimum/Maximum Mode .............. 4-10
External Memory Addressing ........... 4-14
I/O Interfacing .......... , .............. 4-15
Interrupts ............................. 4-16
Machine Instruction Encoding and
Decoding ............................. 4-18
8086 Instruction Sequence ............. 4-37
8089 I/O Processor .................... 4-38
System Configuration .................. 4-39
Bus Operation ......................... 4-41
Initialization ........................... 4-44
I/O Dispatching ........................ 4-46
DMA Transfers ......................... 4-47
DMA Termination ....................... 4-50
Peripheral Interfacing .................. 4-50
Instruction Encoding .................. 4-52
SUPPLEMENT
iAPX 86/20, 88/20 Numerics Supplement
Table of Contents
Processor Overview ............... ; .... S-l
Processor Architecture .................. S-7
Computation Fundamentals ............ S-11
Memory ............................... S-21
Multiprocessing Features .............. S-22
Processor Control and Monitoring ...... S-26
Instruction Set ........................ S-29
Programming Facilities ................ S-58
iv
SUPPLEMENT
A-1.
A-2.
Instruction Encoding ............. A-1
Machine Instruction Decoding
Guide ........................... A-2
Figures
S-1 8087 Numeric Data Processor
Pin Diagram ...................... S-2
S-2 8087 Evolution and Relative
Performance ...................... S-2
8-3 NDP Interconnect ................. 8-7
8-4 8087 Block Diagram ............... S-8
8-5 Register Structure ................ S-9
S-6 Status Word Format .............. S-10
S-7 Control Word Format ............. S-11
S-8 Tag Word Format ................. S-12
S-9 Exception Pointers Format ....... S-12
8-10 8087 Number System ............. S-13
S-11 Data Formats .................... S-14
8-12 Projective Versus Affine
Closure ......................... 8-18
8-13 Storage of Integer Data Types ..... 8-21
8-14 8torage of Real Data Types ....... S-21
8-15 8ynchronizing Execution
With WAIT ....................... S-24
S-16 Interrupt Request Logic .......... S-27
8-17 Interrupt Request Path ........... S-29
8-18 FSAVE/FR8TOR Memory
Layout .......................... S-41
S-19 FSTENV/FLDENV Memory
Layout .......................... 8-41
8-20 8ample 8087 Constants .......... 8-43
S-21 8tatus Word RECORD
Definition ........................ 8-62
8-22 8tructure Definition .............. S-62
8-23 Sample PUM-86 Program ........ S-64
S-24 Sample A8M-86 Program ......... 8-65
S-25 Instructions and Register
8tack ........................... 8-68
S-26 Conditional Branching
for Compares .................... 8-82
8-27 Conditional Branching for
FXAM ........................... S-83
8-28 Full 8tate Exception Handler ..... S-86
S-29 Latency Exception Handler ....... S-87
8-30 Reentrant Exception Handler ..... S-87
IAPX 86/20, 88/20 Numerics Supplement
(Continued)
Special Topics ......................... S-66
Programming Examples ............... S-82
86/20, 88/20 Device Specifications ...... S-89
Tables
S-1 8087/Emulator Speed
Comparison ...................... S-3
S-2 Data Types ........................ S-6
S-3 Principal Instructions .............. S-6
S-4 Real Number Notation ............ 8-15
S-5 Rounding Modes ................ 8-17
S-6 Exception and Response
Summary ........................ S-20
S-7 Processor State
Following Initialization ........... S-26
S-8 Bus Cycle Status Signals ......... S-28
S-9 Data Transfer Instructions ......... S-30
S-10 Arithmetic Instructions ........... 8-32
8-11 Basic Arithmetic Instructions
and Operands ................... 8-33
S-12 Comparison Instructions ......... 8-36
S-13 FXAM Condition Code Setting .... 8-37
S-14 Transcendental Instructions ....... 8-37
8-15 Constant Instructions ............ 8-38
S-16 Processor Control Instructions .... 8-39
S-17 Key to Operand Types ............ 8-42
S-18 Execution Penalties .............. S-43
S-19 Instruction Set
Reference Data .................. S-44
S-20 PUM-86 Built-in Procedures ...... 8-59
8-21 8torage Allocation Directives ..... S-60
S-22 Addressing Mode Examples ...... S-62
S-23 Denormalization Process ......... 8-68
8-24 Exceptions Due to Denormal
Operands ........................ 8-69
S-25 Unnormal Operands and
Results .......................... 8-70
8-26 Zero Operands and Results ....... 8-71
S-27 Infinity Operands and Results .... S-72
S-28 Binary Integer Encodings ........ 8-75
S-29 Packed Decimal Encodings ....... S-76
S-30 Real and Long Real
Encodings ....................... S-76
S-31 Temporary Real Encodings ....... 8-77
S-32 Exception Conditions and
Masked Responses .............. 8-79
8-33 Masked Overflow Response for
Directed Rounding ............... 8-81
8087 INSTRUCTIONS, ENCODING
AND DECODING ......................... S-109
v
Introduction
1
INTRODUCTION
Successful microcomputer-based designs are judicious
blends of hardware and software. The User's Manual
addresses both subjects in varying degrees of detail.
This publication is the definitive source of information
describing the iAPX 86 components. Software topics
are given moderately detailed CQverage. The manual
serves as a reference source during system design and
implementation.
Intel's Literature Guide, updated bi-monthly and available at no cost, lists all other manuals and reference
material. Of particular interest to iAPX 86,88 designers
are: AP-I13, Getting Started with the Numeric Data
Processor; AP-I06, Multiprogramming with iAPX
86,88 Microsystems;The Peripheral Design Handbook,
and the iAPX 88 Book.
MANUAL ORGANIZATION
The manual contains four chapters, two appendices,
and a numerics supplement. The remainder of this
chapter describes the architecture of the iAPX 86
and 88.
Chapter 2 describes the iAPX 86 and iAPX 88 Central
Processing Units. Chapter 3 describes the 8089 Input!
Output Processor. These two chapters are identically
organized and focus on providing a functional description of the iAPX 86,88 and 89, plus related Intel
products.
Hardware reference information-electrical characteristics, timing and physical interfacing-for the iAPX
86,88 processors is concentrated in Chapter 4.
Appendix A is a collection of iAPX 86 application
notes; these provide design and debugging examples.
Additional application notes are available through Intel's Literature Department (see Literature Guide).
Appendix B contains iAPX component data sheets and
several systems data sheets. The entire Intel catalog of
data sheets is available in: 1981 Component Data Catalog and 1981 Systems Data Catalog.
The Numerics Supplement provides detailed information on the 8087 numeric processor extension to the
iAPX 86/10 and 88/10 CPUs.
MICROSYSTEM 80
NOMENCLATURE
The increase in microcomputer system and software
complexity has prompted Intel to introduce a new family of microprocessor products to reduce application
complexity and cost. This new generation of Intel
microprocessors is powerful and flexible and includes
many processor enhancements. These include CPUs,
numeric floating point extensions, I/O processors, and
all the support chips required for a full function system.
As Intel's product line has evolved, its componentbased product numbering system has become inappropriate for all the possible VLSI computer solutions
offered. While the components retain their names, Intel
has moved to a new system-based naming scheme to
accommodate these new VLSI systems.
We have adopted the following prefixes for our product
lines, all of them under the general heading of
Microsystem 80:
iAPX
- Processor Series
- Operating Systems
iRMX
- Single Board Computers
iSBC
iSBX
- MULTIMODULE Boards·
Concentrating on the iAPX Series, two processor lines
are currently defined:
iAPX 86
iAPX 88
- 8086 CPU-based system
- 8088 CPU-based system
Configuration options within each iAPX system are
identified by adding a suffix, for example:
iAPX 86/10 iAPX 86/11 iAPX 88/20 -
CPU Alone (8086)
CPU + IOP (8086 + 8089)
CPU with Math Extension
(8088, 8087)
iAPX 88121 - CPU with Math Extension + lOP
(8088, 8087 + 8089)
This improved numbering system will enable us to provide you with a more meaningful view of the capabilities of our evolving Microsystem 80.
INTRODUCTION
erally share common data when needed. Ideally, these intermodule communication paths are well structured and
disciplined.
iAPX 86 AND iAPX 88 ARCHITECTURE THE FOUNDATION FOR THE FUTURE
Overview
The iAPX 86,88 segmentation scheme is optimized for the
reference patterns of computer programs. Four segment
registers are provided in a segment register file. Memory
references are relative to automatically selected code segment (CS) and data segment (DS) registers. The module
shares a stack segment (SS) with all other modules of the
process (task). The module may share a global data segment
with other modules in the process; for example, to send and
receive messages between modules. This segment is accessed
explicitly with the extra segment (ES) register.
iAPX .86,88 is an evolving family of microprocessors and
peripherals. The family partitions processing functions among
general data processors (8086 and 8088), specialized coprocessors like the 8087 numeric data processor, and 110 channel
processors (the 8089).
Four key architectural concepts shaped the data processor
designs. All four reflect the family's role as vehicles for
modular, high level language programming (in addition to
assembly language programming). The four architectural
concepts are memory segmentation, the operand addressing
structure, the operation register set, and the instruction
encoding scheme. They are distinct departures from the
minicomputer architectural styles of the 1960's and 1970's.
This scheme is highly efficient because constant program
references to code and data, as well as the stack, have
automatic segment selection. This results in minimized
instruction length. Only 16 bits are required to address anywhere in the full megabyte address range. Only infrequent
inter-module communications require the extra prefix bits to
explicitly override the automatic segment selection.
These earlier architectures (minicomputers) were designed
for assembly language programming which emphasizes register based data and linear programs. Over the last decade,
large software development projects shifted their programming to high level languages which employ modular. programming and memory based data. The iAPX 86,88
memory segmentation scheme is intended for modular programs. It supports the static and dynamic memory requirements of program modules, as well as their communication
needs. The iAPX 86,88 registers are designed for fast high
level language execution. The scheme employs specialized
registers and implicit register usage. You will derive significant performance and memory utilization improvements
directly from these architectural features.
There are two other significant advantages to the segment
register concept. First, it separates segment base addresses
from offset addresses which are relative to the segment base.
Only offset addresses are used within object modules. This
supports position-independent, dynamically relocatable modules. You merely have to alter the CS and DS register contents
to move a module, rather than relinking the whole task and
reloading. This structure employs short addresses (16 rather
than 20-bit) for efficient use of memory.
The second advantage of iAPX 86,88 segmentation is that it
can be extended to include memory management and multilevel protection. The contents and width of segmentation
registers are independent of the rest of the instruction set.
The architecture can be made to address additional memory
and provide access rights and limit checking. Using the
mainframe concept of memory based segment tables, this
structure can also support virtual memory. Further, since
only four registers are active in the file at a time, these
features can be accomplished on the CPU chip itself, avoiding the access delays of off-chip memory management.
The four concepts are discussed in the following sections.
They are:
• Memory segmentatipn for modular programming,
evolution to memory management and protection
• Addressing structure for high level programming
languages
• Operation register set for computation
In summary, memory segmentation has several ultimate
benefitsfor the end user. It provides for simplified hardware
and faster, modular software development, more easily
maintainable code, and provides an orderly way for the
architecture to grow.
• Instruction set encoding for memory efficiency
and executi()n speed
Memory Segmentation for Modular Programming
Large programs (1 0-100K bytes) are not generally written in
assembly language. They are developed in individually compiled modules in high level languages. Modular program
development techniques, program libraries, compatible linking, and project management tools are often requirements in
such an environment. A complex application program
might be composed of multiple processes, with each process
constructed from mUltiple modules. Processes send messages to each other for communication, while modules gen-
Addressing Structure for High Level
Programming Languages
The iAPX 86,88 architecture employs an operand addressing scheme complementing the memory segmentation
scheme. There are four components in an address. They are
the segment, base, index, and displacement. The segment
component was just described. A base register is dedicated to
both the data and stack segments. These base registers may
1-2
INTRODUCTION
ACCUMULATOR
AX
AH
AL
BX
BH,
,BL
CX
CH
CL,
OX
DH
"DL'
BASE
COUNT
DATA
SP
~
BP
....
FLAGSH
s
SOURCE INDEX
01
DESTINATION INDEX
INSTRUCTION POINTER
J
~
STACK POINTER
BASE POINTER
SI
t
OS
,
STATUS FLAGS
CODE SEGMENT
DATA SEGMENT
SS
STACK SEGMENT
ES
EXTRA SEGMENT
Figure 2. lAP X 86/10, 88/10 Register Model
also be used when accessing the extra (global) segment. They
are used for holding the base address of a data structure.
Block and string data are extensions to this scheme. They use
different assumptions for source and destination segments,
but the segments are still implicitly accessed. Immediate
operands are also supported.
Two index registers are provided for use with the base
registers to dynamically select any element from a based data
structure. Eight or sixteen-bit fixed displacements may be
added to any of these address forms. The complete register file is shown in Figure 2 and the addressing structure is
shown in Figure 3.
The iAPX 86,88 is a two operand machine (source and
destination). It supports source/ destination operand combinations of register/memory, memory/register, memory/
memory (string operations only), immediate/ register, and
immediate/memory. The various address combinations of
S, B, I, and d correspond to common data structures used in
high level language programming. Such data structures can
therefore be implemented easily in assembly language as
well.
Referring to Figure 3, an iAPX 86,88 operand address contains up to four components: a segment (S), a base (B), an
index (I), and a displacement (d). The segment component is
automatically selected for the code, data, and stack segments. An explicit segment selection is required for data
references in the extra segment. Any combination of the
remaining three address components.is permitted in virtually
all memory reference instructions, with at least one always
being present.
Figure 3 shows the correspondence between the most common iAPX 86,88 address modes and various data types in
high level programming languages. The S comportent is
DESCRIPTION
COMPONENT
'--__
S_~I
~J
{~¢J;K
SEGMENT
Selects 64K Add ress
Range (Segment)
EXTRA
B
+
+
+
r--D]
d
~___
S+B+I+d I
DATA
STACK
BASE
{
INDEX
(SOURCE
l.DESTINATION
DISPLACEMENT
{
EFFECTIVE ADDRESS
Selects Data
Structure within
Segment
Selects Element
within Data
Structure
8 - BIT
16- BIT
Fixed Offset
Selects Sub-E lements
(20 - BIT)
One Mega-Byte
Address Range
Figure 3. iAPX 86,88 Four Component Addressing Structure
1-3
INTRODUCTION
implicit; the stack base (BP) assumes the stack segment; no B
component, or use of the data base (BX), assumes the data
segment. The less commonly used address modes are not
shown.
Instruction Set Encoding for Memory Efficiency
and Execution Speed
The iAPX 86 uses a byte oriented instruction stream while
operating with a 16-bit data bus. Toaccomplish this, the
processor is subdivided into two independent parallel processors called the bus interface unit (BIU) and the execution
unit (EU). The iAPX 88 employs an identical execution
unit and is 100% code compatible with iAPX 86, yet it
interfaces to an 8-bit wide data bus BIU. The bus interface
unit is an independent processor that prefetches instruc~
tions. Instruction fetch time is therefore mostly over~
lapped with other iAPX 86,88 processor activity. The bus
interface unit permits either instructions or data to be
placed in memory without regard to word boundaries.
(An array of five byte records in PASCAL can be referenced without requiring an additional byte of padding to
word align the records.) Processor subdivision into the
BIU and EU has the additional benefit of minimizing the
effect of wait states and bus hold time on CPU efficiency.
The stack base (BP) is a concept borrowed from the family of
P-machines "developed" as ideal PASCAL vehicles. Pmachines term this register the "mark pointer". It always
points to the base of the current local data area in the stack
segment. This permits efficient local addressing in blockstructured languages such as PASCAL and PLI M. In these
languages, procedures are invoked by pushing their parameters on the stack, calling the procedure, and then allocating
their local data area on the stack. The iAPX 86,88 return
instruction then removes the parameters froni the stack, as is
done in the P-machines.
Operation Register Set for Computation
The Intel iAPX 86,88 line is truly a complete family of
microprocessors. The iAPX 861 JO and iAPX 881 10 are the
general data processor members ofthefamily, while the8089
is the 110 processor family member. In addition, the CPU
itself has an interface for attaching coprocessors. Coprocessors provide specialized operation set extensions that benefit
the application by performing special purpose logic to
increase performance.
Instruction set encoding is substantially improved when
instructions are composed in byte multiples .instead of
words. Instructions in the iAPX 86,88 vary from one to six
bytes in length (not counting optional prefix bytes). The
average instruction is three bytes long; In a word aligned
machine the same information would occupy four bytes.
This and the features described above give the iAPX 86,88
roughly a· 30% program space savings over other architectures.
The iAPX 86/20 Numeric Data Processor is an example of
this concept. Using an 8086 with an 8087 coprocessor (CPU
extension) it provides a one hundred-jold peiformance boost
over the iAPX 861 JO for a wide range of numeric operations.
The full computational capability of the iAPX 86,88 family
can therefore span a much broader range than is possible with
a single microprocessor. This technique has been used successfully in the mainframe and minicomputer industries to provide
instruction set options for scientific, commercial, text processiIlg, or other special purpose applications.
PROCESSOR PARTITIONING
Beyond efficient support for high level languages, the
iAPX 86 and iAPX 88 establish the foundation for the
family to build on in the 1980's. The family uses increasing
levels of integration to significantly reduce software, hardware, and development investment.
An 8087 extends the iAPX 86 or iAPX 88 architecture to
include additional data types, registers, and instructions. The
8086 or 8088, with an 8087 coprocessor, operates on 16, 32,
and 64-bit integers, 32, 64 and 80-bitfloating point
numbers, and up to 18 digit packed BCD numbers. Data
conversions and calculations are performed in the 8087
and are transparent to the programmer.
The iAPX 86 I 10 and iAPX 88 I 10 general purpose processors employ external module integration. Specialized system functions are distributed among optimized components and removed from the host processor. The CPU is
freed to become the system manager and resource allocator
rather than doing "all things for all programs". The family
also includes the 8087 Numeric Data Processor and the
8089 110 Channel Processor.
The iAPX 861 10 and iAPX 881 JO CPUs alone can perform
arithmetic operations on signed and unsigned 8 and 16-bit
binary integers as well as packed and unpacked decimal
integers. The full complement of logical operations are provided as well. Interesting new features are the string operations. Six primitive string instructions (move, skip, search,
compare, set, and translate) are standard. When combined
with special control operators, complex string manipulations are possible with two or three instructions.
These processors are optimized to address the three main
functions in a computer environment: data processing and
control, arithmetic computation, and input/output. The
8087 and 8089 are described below.
The 8087 Numeric Processor Extension (NPX) adds over
50 numeric opcodes and eight 80-bit registers to the host
processor to provide more extensive data and numeric
processing capability. It performs floating point and trans-
1-4
INTRODUCTION
HOST CPU (8086 or 8088)
EXECUTION
UNIT
NUMERIC DATA PROCESSOR (8087)
BUS INTERFACE UNIT
BUS
INTERFACE
I
I
FLOATING POINT EXECUTION UNIT
~
UNIT
INSTRUCTIONS
DATA
I
DATA
BLOCK
<==:)
ADDRESS/STATUS
ADDRESSING
AND
BUS TRACKING
CONTROL
UNIT
OPERAND
QUEUE
I
I
I
I
I
I
A
""
I
I
~
AlU
Figure 4. Numeric Data Processor Block Diagram
cendental (trigonometric) functions, processes decimal
operands up to 18 digits without roundoff, and performs
exact arithmetic on integers up to 64 bits long. Another
feature of the NDP, with important benefits to you, is that
it is compatible with the proposed IEEE floating point
standards. It can be used in applications requiring high
speed computation such as numerical analysis, accounting
and financial applications, the sciences, and engineering.
Throughput increases in such applications up to JOO times
current speeds are typical (See Figure 4.)
done at rates up to 1.25 megabytes per second. The lOP
therefore combines the attributes of both a CPU and a
DMA controller to provide a powerful II 0 subsystem. An
important feature of the lOP is that it can be physically
isolated from the application CPU. The advantage to you
is that 110 subsystem changes or upgrades can be made
without any impact to application software. (See Figure 5.)
Summarizing, there are several advantages to external
module integration:
• System tasks may be allocated to special purpose processors designed for optimal task handling
The 8089 Input/ Output Processor (lOP) is an independent
microprocessor that optimizes inputloutput operations.
The objective of the lOP is to remove all 110 detailsfrom
application software. It responds to CPU direction but
executes its own instruction stream in parallel with other
processors. 110 transfers of either 8 or 16-bit data can be
• Simultaneous operation (parallel processing) provides
highest system performance
• Isolated system functions minimize the effect of modifications, localfailures, or errors on the restofthe system
HOST CPU (8086 or 8088)
EXECUTION
UNIT
I
PERIPHERALS
BASE
INTERFACE
110 PROCESSOR (8089)
CRT'S
UNIT
PRINTERS
DISKETTES
PRIVATE MEMORY
PUBLIC MEMORY
CHANNEL 1 PROGRAM
PROGRAM
CHANNEL 2 PROGRAM
DATA
Figure 5. I/O Processor Block Diagram
1-5
INTRODUCTION
High Level Languages
• The iAPX 86,88 family of processors allows diVision of
the application into small, manageable tasks for parallel
development, while providing built-in hardware facilities for coordinating processor interaction. With the
iAPX 86,88 approach you can implement high performance systems far more quickly and easily than would
otherwise be possible.
Programming languages are the key to developing an application. Intel programming languages serve three purposes in
your design. First, they are your primary design tool. Intel's
breadth of languages and extended features give you the
maximum ability to properly design and plan your program.
Second, Intel languages are a communication vehicle between
programmers during implementation and later during modification. Standard high level languages allow programmers to
better communicate what the programs do. Third, Intel Ianguages are designed in conjunction with Intel microsystetns to
provide the greatest code efficiency and execution speed. Intel
languages speed implementation of your design and reduce
maintenance costs.
DEVELOPMENT TOOLS
Development Systems
Development systems are a unique combination of hardware
and software tools which increase your product development
productiVity. With Intel development products, you will
shorten the development cycle and reduce your time to
market.
MDS-311 is a set of software development tools for iAPX 86
and iAPX 88 applications. It is a complete set of software
products that run on the Intellec Model-800 and Series-II
development systems. The software tools provided include
PLI M-86, high level programming language, and the ASM86 assembler. Two utilities, LINK86 and LOC86, are supplied
to link separately compiled or assembled program modules
into executable tasks. The Library Manager, LIB86, lets you
maintain a library of iAPX 86 or iAPX 88 ()bject modules.
These modules can then be linked in with new programs
without being recompiled. This simplifies and speeds. your
development. Common code (e.g. a subroutine) ouly has to be
developed and compiled once. Intel code converters~ such as
CONV86, are very useful tools for migrating 8080 or 8085,
Z80, and 6809 assembly language programs to the iAPX 86 or
iAPX 88. They. convert assembly source· code to ASM86
source code. This will help you make a rapid transition and cut
redevelopment costs substantially.
Development systems from Intel proVide an upgradable spectrum of tools ranging from stand alone development systems
to future networks of specialized work stations. Intel eliminates your risk of development system obsolescence by guaranteeing product upgradability and compatibility. This guarantee protects your capital investment.
For small to medium size projects, the IntellecT" development
system is available in many configurations at low cost. For
small projects, these systems have nominal program memory
with floppy disks as peripheral storage deVices. Minimum
configurations may be upgraded to proVide increased performance, increased. memory, and increased· mass storage via
hard disk. These more powerful configurations support
medium sized projects.
The Intellec Series 11/85 is a good example of such a system.
It is a complete microcomputer development system integrated into one compact package. The Model 225 includes a
CPU with 64K bytes of RAM, 4K bytes of ROM, a 2000
character CRT, detachable full ASCII keyboard, and a 250K
byte floppy disk drive. The powerful ISIS-II Disk Operating
System software allows you to efficiently develop and debug
iAPX 86,88 programs. Optional storage peripherals proVide
over 2 million and 7.3 million bytes of storage on floppy and
hard disk, respectively.
Intel will proVide a variety of languages f()r both systems and
applications to facilitate development of your product. You
can choose the language (or languages) which best suits your
product needs and the expertise of your staff. ASM86, the
assembly language, and PLI M-86, the systems oriented high
level language, are both currently available. PASCAL, FORTRAN, and BASIC will be offered in the near future, and
COBOL is planned after that.
Intel's languages also run on your final product, Your product's function is significantly increased when packaged with
language translators. They allow your customers to tailor your
products for their environment. Intel's languages will save
implementation time and free resources to work on the valueadded portion of your product.
..
Distributed development configurations address the range of
,medium to large sized projects. These configurations connect
multiple standalone development systems to more powerful
support resources such as mainframes and their peripherals.
In addition to the Intellec® development system, Intel offers
several products to help you debug and test your hardware and
software. In-Circuit-Emulators, such as ICE-86T" and ICE88T", are available to emulate your product environment. They
increase development productiVity substantially. Another
software tool, RBF-89, helps you debug 8089 software under
.ICE control. With these tools, software development time
can be reduced dramatically - lowering your total investment.
SINGLE BOARD COMPUTERS
ACCELERATE YOUR
MICROSYSTEM SUCCESS
In addition to the increased integration of functions in
VLSI components, there is a strong trend today to implement microsystem applications with single board compu-
1-6
INTRODUCTION
ters. This ~lIows the design engineer to:
Experience shows that the first company that gets its
product to the marketplace usually dominates that
market. You can get your product to the market months
earlier using standard off-the-shelf iSBC, iSBX and
Real-Time Executive (iRMX) Software modules.
Intel's large board manufacturing and distribution capability enables you to respond to your market demand
rapidly and in a cost-effective manner.
• Easily configure reliable and cost-effective systems
using iSBC and iSBX standard products.
• Overcome the shortage of qualified engineers and
technicians.
• Get the end product to market quickly.
• Focus on the application.
3. Solution Completeness and Project Credibility
• Offset the increasing cost of capital.
Microprocessor based solutions for today's problems
are commonplace and are expected to succeed. A broad
spectrum of compatible system components in the
iSBC, iSBX, and iRMX product line increase the probability of being right the first time. General purpose
iSBC board solutions are easy to customize through the
use of iSBX modules from Intel, or your own design.
In addition, using iSBC single board computers and iSBX
expansion products in your design reduces the number of
risks that you must face in all phases of the product life
cycle. The four major risk areas that Intel iSBC and iSBX
products will help you overcome are as follows:
1. Limited Resources
4. Coping with the Technology/Complexity
Avalanche
Using a fully tested board computer, which incorporates the key elements of processor, memory and 1/0,
helps overcome today's critical shortage of engineers,
programmers and technicans. Implementing iSBC
boards and iSBX MULTIMODULES in your design
reduces increasing capital costs in production, QC, and
test. It is estimated that using iSBC boards can save up
to $200,000 per board design.
iSBC and iSBX products incorporate the latest in VLSI
shortly after their initial introduction. With increasing
system complexity Intel's design process and testing
reduces the risk of "gremlin" bugs which multiply with
complexity and evade diagnosis. Standards used throughout the product family such as the de facto industry
standard MULTIBUS, EIA, IEEE etc. provide a
smooth transition for your product to new and changing processor, memory and 110 technologies.
2. Time to Market Dictates Success or Fallure
With inflation running at its current rate, the amount of
time it takes to get a product from an idea to the market
becomes critical. A delay of a few months can collapse
your return on investment.
Intel's single board computer product family is continuing
to reduce your risk and protect your investment in the
future by expanding iSBC and iSBX products in three
dimensions: processors, memory, and 1/0.
ISBX" MULTIMODULE AND
MULTIMODULE'"
_________ MEMORY EXPANSION
RMX"
REAL-TIME
MULTIPROGRAMMING
EXECUTIVE
SOFTWARE
RAPID VLSI
INFUSION
L======~~s:::-----
","'0
--------- MULTI BUS" STANDARD ARCHITECTURE
Figure 6. Single Board Computer (iSBC 86/12T")
1-7
INTRODUCTION
SUMMARY
Intel's iAPX 86,88 multiple· processor family is designed
for modular programming in high level as well as assembly
languages.
• Its memory segmentation scheme is optimized for the
reference needs of computer programs, and is separate
from the operand addressing structure.
• The structure for addressing operands within segments
directly supports the· various data types found in high
level programming languages.
• The family provides an operation register set to support
general computation requirements. It also provides for
optimized operation register sets to do specialized data
processing functious with its inherent multi- and cflprocessor support.
• The family uses optimized instruction encoding for
high performance and memory efficiency
• The family is well supported with development tools
and single board computer products.
This architecture provides the foundation for solving the
application needs in the 1980's. It makes a noted departure
from architectures of the 1960's and 1970's "'-- based on
Intel's intent to minimize software and hardware product
costs for you, the end user.
1-8
The iAPX 86 and
iAPX 88 Central
Processing Units
2
CHAPTER2
THE 8086 AND 8088
CENTRAL PROCESSING UNITS
This chapter describes the mainstays of the 8086
microprocessor family: the 8086 and 8088 central
processing units (CPUs). The material is divided
into ten sections and generally proceeds from
hardware to software topics as follows:
I. Processor Overview
2. Processor Architecture
3. Memory
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6. Processor Control and Monitoring
7. Instruction Set
8. Addressing Modes
9. Programming Facilities
10. Programming Guidelines and Examples
The chapter describes the internal operation of
the CPUs in detail. The interaction of the processors with other devices is discussed in functional terms; electrical characteristics, timing, and
other information needed to actually interface
other devices with the 8086 and 8088 are provided
in Chapter 4.
2.1 Processor Overview
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The 8086 and 8088 are closely related thirdgeneration microprocessors. The 8088 is designed
with an 8-bit external data path to memory and
I/O, while the 8086 can transfer 16 bits at a time.
In almost every other respect the processors are
identical; software written for one CPU will
execute on the other without alteration. The chips
are contained in standard 40-pin dual in-line
packages (figure 2-1) and operate from a single
+5V power source.
The 8086 and 8088 are suitable for an exceptionally wide spectrum of microcomputer applications, and this flexibility is one of their most
outstanding char'acteristics. Systems can range
from uniprocessor minimal-memory designs
implemented with a handful of chips (figure 2-2),
to multiprocessor systems with up to a megabyte
of memory (figure 2-3).
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Figure 2-1.8086 and 8088 Central Processing
Units
2-1
8086 AND 8088 CENTRAL PROCESSING UNITS
..
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4
8155
.,
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4ADDRESS/DATA
8088
CPU
CONTROL
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4
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CLOCK
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Figure 2-2. Sma1l8088-Based System
liD DEVICES
t
I·
1/0 BUS
8088
OR
8089
. lOP
8088
CPU
MULTIBUS'" CONTROLS
MULTIBUS'" CONTROLS
Figure 2;3. 8086/8088/8089 Multiprocessing System
2-2
8086 AND 8088 CENTRAL PROCESSING UNITS
The large application domain of the 8086 and
8088 is made possible primarily by the processors'
dual operating modes (minimum and maximum
mode) and built-in multiprocessing features.
Several of the 40 CPU pins have dual functions
that are selected by a strapping pin. Configured
in minimum mode, these pins transfer control
signals directly to memory and input/output
devices. In maximum mode these same pins take
on different functions that are helpful in medium
to large ystems, especially systems with multiple
processors. The control· functions assigned to
these pins in minimum mode are assumed by a
support chip, the 8288 Bus Controller.
The 8086's advantage over the 8088 is attributable
to its 16-bit external data bus. In applications that
manipulate 8-bit quantities extensively, or that
are execution-bound, the 8088 can approach to
within 100/0 of the 8086's processing throughput.
The high performance of the 8086 and 8088 is
realized by combining a 16-bit internal data path
with a pipelined architecture that allows instructions to be prefetched during spare bus cycles.
Also contributing to performance is a compact
instruction format that enables more instructions
to be fetched in a given amount of time.
Software for high-performance 8086 and 8088
systems need not be written in assembly language.
The CPUs are designed to provide direct hardware support for programs written in high-level
languages such as Intel's PLlM-86. Most highlevel languages store variables in memory; the
8086/8088 symmetrical instruction set supports
direct operation on memory· operands, including
operands on the stack. The hardware addressing
modes provide efficient, straightforward
implementations of based variables, arrays, arrays of structures and other high-level language
data constructs. A powerful set of memory-tomemory string operations is available for efficient
character data manipulation. Finally, routines
with critical performance requirements that cannot be met with PL/M-86 may be written in
ASM-86 (the 8086/8088 assembly language) and
linked with PLlM-86 code.
The CPUs are designed to operate with the 8089
Input/Output Processor (lOP) and other processors in multiprocessing and distributed processing systems. When used in conjunction with
one or more 8089s, the 8086 and 8088 expand
the applicability of microprocessors into I/O~
intensive data processing systems. Built-in coordinating signals and instructions, and electrical
compatibility with Intel's Multibus™ shared bus
architecture, simplify and reduce the cost of
developing multiple-processor designs.
Both CPUs are substantially more powerful than
any microprocessor previously offered by Intel.
Actual performance, of course, varies from
application to application, but comparisons to the
industry standard 2-MHz 8080A are instructive.
The 8088 is from four to six times more powerful
than the 8080A; the 8086 provides seven to ten
times the 8080A's performance (see figure 2-4).
While the 8086 and 8088 are totally new designs,
they make the most of users' existing investments
in systems designed around the 8080/8085
microprocessors. Many of the standard Intel
memory, peripheral control and communication
chips are compatible with the 8086 and the 8088.
Software is developed in the familiar Intellec®
Microcomputer Development System environment, and most existing programs, whether written in ASM-80 or PLlM-80, can be directly converted to run on the 8086 and 8088.
100
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10
2.2 Processor Architecture
~
Microprocessors generally execute a program by
repeatedly cycling through the steps shown below
(this description is somewhat simplified):
I. Fetch the next instruction from memory.
2. Read an operand (if required by the
instruction).
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1977 1978 1979
YEAR INTRODUCED
Figure 2-4. Relative Performance of the
8086 and 8088
2-3
8086 AND 8088 CENTRAL·PROCESSING UNITS
3.
4.
Execute the instruction.
Write the result (if
instruction).
required
by
The two units can· operate independently of one
another and are able, under most circumstances,
to extensively overlap instruction fetch with execution. The result is that, in most cases, the time
normally required to. fetch instructions "disappears" because the EU .executes instructions
that have already been fetched by the BIU. Figure
2-5 illustrates this overlap and compares it with
traditional microprocessor operation. In. the
example, overlapping reduces the elapsed time
required to execute three instructions, and allows
two additional instructions to be pre fetched as
well.
the
In previous CPUs, most of these steps have been
performed serially, or with only a single bus cycle
fetch overlap. The architecture of the 8086 and
8088 CPUs, while performing the same steps,
allocates them to two separate processing units
within the CPU. The execution unit (EU) .executes
instructions; the bus interface unit (BIU) fetches
instructions, reads operands and writes results.
f-~---~~-,-------ELASPEDTIME---------~--..
~
'"co"' { c'" L\~~'0¥l ~1\t~
GENERATION
MICROPROCESSOR
.
BUS:
EU:
EJ
~~~~~J~~
Fttfwl ~~~~
11:~~~Whlll
a
IIEI
8
EJ
E~#;t9f{~
I :~~~s HJ~: I
8086/8088
MICROPROCESSOR
INSTRUCTION STREAM
1S11NSTRUCTION (ALREADY FETCHED):
EXECUTE AND WRITE RESULT
2nd INSTRUCTION:
EXECUTE ONLY
3rd INSTRUCTION:
READ OPERAND AND EXECUTE
4th INSTRUCTION:
(UNDEFINED)
5th INSTRUCTION:
(UNDEFINED)
Figure 2-5. Overlapped Instruction Fetch and Execution
2-4
II~~:~~:~~~II
8086 AND 8088 CENTRAL PROCESSING UNITS
Execution Unit
Bus Interface Unit
The execution units of the 8086 and 8088 are identical (figure 2-6). A 16-bit arithmetic/logic unit
(ALU) in the EU maintains the CPU status and
control flags, and manipulates the general
registers and instruction operands. All registers
and data paths in the EU are 16 bits wide for fast
internal transfers.
The BIUs of the 8086 and 8088 are functionally
identical, but are implemented differently to
match the structure and performance
characteristics of their respective buses.
The BIU performs all bus operations for the EU.
Data is transferred between the CPU and memory
or 110 devices upon demand from the EU. Sections 2.3 and 2.4 describe the interaction of the
BIU with memory and 110 devices.
The EU has no connection to the system bus, the
"outside world." It obtains instructions from a
queue maintained by the BIU. Likewise, when an
instruction requires access to memory or to a
peripheral device, the EU requests the BIU to
obtain or store the data. All addresses
manipulated by the EU are 16 bits wide. The BIU,
however, performs an address relocation that
gives the EU access to the full megabyte of
memory space (see section 2.3).
.... ....
In addition, during periods when the EU is busy
executing instructions, the BIU "looks ahead"
and fetches more instructions from memory. The
instructions are stored in an internal RAM array
called the instruction stream queue. The 8088
instruction queue holds up to four bytes of the
can store.
instruction stream, while the 8086 queue
.
EXECUTION UNIT (EU)
BUS INTERFACE UNIT (BIU)
GENERAL
REGISTERS
SEGMENT
REGISTERS
It It
I
OPERANDS
t
Dt
ALU
I.
t
I
INSTRUCTION
POINTER
I
I
I
I
I
I
t
ADDRESS
GENERATION
AND BUS
CONTROL
""Ii
,..
INSTRUCTION
QUEUE
I
FLAGS
Figure 2-6. Execution and Bus Interface Units (EU and BIU)
2-5
MULTIPLEXED BUS
8086 AND 8088 CENTRAL PROCESSING UNITS
up to six instruction bytes. These queue sizes
allow the BIU to keep the EU supplied with prefetched instructions under most conditions
without monopolizing the system bus. The 8088
BIU fetches another instruction byte whenever
one byte in its queue is empty and there is no
active request for bus access from the EU. The
8086 BIU operates similarly except that it does
not initiate a fetch until there are two empty bytes
in its queue. The 8086 BIU normally obtains two
instruction bytes per fetch; if a program transfer
forces fetching from an odd address, the 8086
BIU automatically reads one byte from the odd
address and then resumes fetching two-pyte
words from the subsequent even addresses.
DATA
GROUP
{
1~ A~ ad _ ~ _
_
_
-----~---BH
BL
BASE
CX
- -:- cit - -r- --D'H -
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DATA
o·
SP
POINTER
AND {
INDEX
GROUP
COUNT
~-DL--
15
Under most circumstances the queues contain at
least one byte of the instruction stream and the
EU does not have to wait for instructions to be
fetched. The instructions in the queue are those
stored in the memory locations immediately adjacent to and higher than the instruction currently
being executed. That is, they are the next logical
instructions so long as execution proceeds serially. If the EU executes an instruction that
transfers control to another location, the BIU
resets the queue, fetches the instruction from the
new address, passes it immediately to the EU, and
then begins refilling the queue from the new location. In addition, the BIU suspends instruction
fetching whenever the EU requests a memory or
110 read or write (except that a fetch already in
progress is completed before executing the EU's
bus request).
._0 ACCUMULATOR
~~~~R
BP
~~~JTER
SI
SOURCE
INDEX
01
DESTINATION
.
I NDEX
Figure 2-7 ..General Registers.
some instructions use certain registers implicitly
(see table 2-1) thus allowing compact yet powerful
encoding.
Table 2-1. Implicit Use of General Registers
REGISTER
General Registers
Both CPUs have the same complement of eight
16-bit general registers (figure 2-7). The general
registers are subdivided into two sets of four
registers each: the data registers (sometimes called
the H & L group for "high" and "low"), and the
pointer and index registers (sometimes called the
P & I group).
The data registers are unique in that their upper
(high) and lower halves are separately
addressable. This means that each data register
can be used interchangeably as a 16-bit register,
or as two 8-bit registers. The other CPU registers
always are accessed as 16-bit units only. The data
registers can be used without constraint in most
arithmetic and logic operations. In addition,
OPERATIONS
AX
Word Multiply, Word Divide,
Word 1/0
AL
Byte Multiply, Byte Divide, Byte
1/0, Translate, Decimal Arithmetic
AH
Byte Multiply, Byte Divide
BX
Translate
CX
String Operations, Loops
CL
Variable Shift and Rotate
DX
Word Multiply, Word Divide,
Indirect 1/0
SP
Stack Operations
SI
String Operations
DI
String Operations
The pointer and index registers can also participate in most arithmetic and logic operations.
In fact, all eight generlil registers fit the definition
of "accumulator" as used in fir·st and second
generation microprocessors. The P & I registers
(except for BP) also are used implicitly in some
instructions as shown in table 2-1.
2-6
8086 AND 8088 CENTRAL PROCESSING UNITS
Segment Registers
Flags
The megabyte of SOS6 and 80SS memory space is
divided into logical segments of up to 64k bytes
each. (Memory segmentation is described in section 2.3.) The CPU has direct access to four
segments at a time; their base addresses (starting
locations) are contained in the segment registers
(see figure 2-8), The CS register points to the current code segment; instructions are fetched from
this segment. The SS register points to the current
stack segment; stack operations are performed on
locations in this segment. The DS register points
to the current data segment; it generally contains
program variables. The ES register points to the
current extra segment, which also is typically used
for data storage.
The S086 and 80SS have six I-bit status flags
(figure 2-9) that the EU posts to reflect certain
properties of the result of an arithmetic or logic
m
F
E1~CARRV
~PARITV
AUXILIARY CARRY
'--------ZERO
'--------SIGN
'----------OVERFLOW
'------------INTERRUPT-ENABLE
The segment registers are accessible to programs
and can be manipulated with several instructions.
Good programming practice and consideration of
compatibility with future Intel hardware and software products dictate that the segment registers
be used in a disciplined fashion. Section 2.10 provides guidelines for segment register use.
'-------------DIRECTION
'--------------TRAP
Figure 2-9. Flags
operation. A group of instructions is available
that allows a program to alter its execution
depending on the state of these flags, that is, on
the result of a prior operation. Different instructions affect the status flags differently; in general,
however, the flags reflect the following
conditions:
15
CS
CODE
SEGMENT
DS
DATA
SEGMENT
SS
STACK
SEGMENT
ES
EXTRA
SEGMENT
1.
If AF (the auxiliary carry flag) is set, there
has been a carry out of the low nibble into
the high nibble or a borrow from the high
nibble into the low nibble of an 8-bit quantity
(low-order byte of a 16-bit quantity). This
flag is used by decimal arithmetic
instructions.
Figure 2-S. Segment Registers
Instruction Pointer
The I6-bit instruction pointer (IP) is analogous to
the program counter (PC) in the 8080/S0S5
CPUs. The instruction pointer is updated by the
BIU so that it contains the offset (distance in
bytes) of the next instruction from the beginning
of the current code segment; i.e., IP points to the
next instruction. During normal execution, IP
contains the offset of the next instruction to be
fetched by the BIU; whenever IP is saved on the
stack, however, it first is automatically adjusted
to point to the next instruction to be executed.
Programs do not have direct access to the instruction pointer, but instructions cause it to change
and to be saved on and restored from the stack.
2-7
2.
If CF (the carry flag) is set, there has been a
carry out of, or a borrow into, the high-order
bit of the result (S- or 16-bit). The flag is used
by instructions that add and subtract
multibyte numbers. Rotate instructions can
also isolate a bit in memory or a register by
placing it in the carry flag.
3.
If OF (the overflow flag) is set, an arithmetic
overflow has occurred; that is, a significant
digit has been lost because the size of the
result exceeded the capacity of its destination
location. An Interrupt On Overflow instruction is available that will generate an interrupt in this situation.
8086 AND 8088 CENTRAL PROCESSING UNITS
4.
If SF (the sign flag) is set, the high-order bit
The AF, CF, PF, SF, and ZF flags are the same in
both CPU families. The remaining flags and
registers are unique to the 8086 and 8088. This
8080/8085 to 8086 mapping allows most existing
8080/8085 program code to be directly translated
into 8086/8088 code.
of the result is a 1. Since negative binary
numbers are represented in the 8086 and 8088
in standard two's complement notation, SF
indicates the sign of the result (0 = positive,
1 = negative).
5.
6.
If PF (the parity flag) is set, the result has
even parity, an even number of I-bits. This
flag can be used to check for data transmission errors.
If ZF (the zero flag) is set, the result of the
operation is O.
Mode Selection
Both processors have a strap pin (MN/MX) that
defines the function of eight CPU pins in the 8086
and nine pins in the 8088. Connecting MN/MX to
+5V places the CPU in minimum mode. In this
configuration, which is designed for small
systems (roughly one or two boards), the CPU
itself provides the bus control signals needed by
memory and peripherals. When MN/MX is
strapped to ground, the CPU is configured in
maximum mode. In this configuration the CPU
encodes control signals on three lines. An 8288
Bus Controller is added to decode the signals
from the CPU and to provide an expanded set of
control signals to the rest of the system. The CPU
uses the remaining free lines for a new set of
signals designed to help coordinate the activities
of other processors in the system. Sections 2.5
and 2.6 describe the functions of these signals.
Three additional control flags (figure 2-9) can be
set and cleared by programs to alter processor
operations:
1. Setting DF (the direction flag) causes string
instructions to auto-decrement; that is, to
process strings from high addresses to low
addresses, or from "right to left." Clearing
DF causes string instructions to autoincrement, or to process strings from "left to
right. "
2. Setting IF (the interrupt-enable flag) allows
the CPU to recognize external (maskable)
interrupt requests. Clearing IF disables these
interrupts. IF has no affect on either nonmaskable external or internally generated
interrupts.
3. Setting TF (the trap flag) puts the processor
into single-step mode for debugging. In this
mode, the CPU automatically generates an
internal interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction. Section 2.10
contains an example showing the use of TF in
a single-step and breakpoint routine.
2.3 Memory
The 8086 and 8088 can accommodate up to
1,048,576 bytes of memory in both minimum and
maximum mode. This section describes how
memory is functionally organized and used.
There are substantial differences in the way
memory components are actually accessed by the
two processors; these differences, which are invisible to programs, are covered in section 4.2,
External Memory Addressing.
8080/8085 Registers and Flag
Correspondence
Storage Organization
The registers, flags and program counter in the
8080/8085 CPUs all have counterparts in the 8086
and 8088 (see figure 2-10). The A register (accumulator) in the 8080/8085 corresponds to the
AL register in the 8086 and 8088. The 8080/8085
H & L, B & C, and D & E registers correspond to
registers BH, BL, CH, CL, DH and DL, respectively, in the 8086 and 8088. The 8080/8085 SP
(stack pointer) and PC (program counter) have
their counterparts in the 8086/8088 SP and IP.
From a storage point of view, the 8086 and 8088
memory spaces are organized as identical arrays
of 8-bit bytes (see figure 2-11). Instructions, byte
data and word data may be freely stored at any
byte address without regard for alignment thereby
saving memory space by allowing code to be
densely packed in memory (see figure 2-12). Oddaddressed (unaligned) word variables, however,
2-8
8086 AND 8088 CENTRAL PROCESSING UNITS
SP
BP
BASE
POINTER
SI
SOURCE
INDEX
DI
DESTINATION
INDEX
CS
CODE
SEGMENT
DS
DATA
SEGMENT
SS
STACK
SEGMENT
ES
EXTRA
SEGMENT
Figure 2-10.8080/8085 Register Subset (Shaded)
HIGH MEMORY
LOW MEMORY
OOOOOH
00001H
00002H
5
{FFFEH FFFFFH
I111111111 II 111111111 115 SUIIIIIIII I I III
7
I..
07
07
1 MEGABYTE
07
0
..
I
Figure 2-11. Storage Organization
Figure 2-12. Instruction and Variable Storage
2-9
8086 AND 8088 CENTRAL PROCESSING UNITS
do not take advantage of the 8086's ability to
transfer 16-bits at a time. Instruction alignment
does not materially affect the performance of
either processor.
.
Segmentation
8086 and 8088 programs "view" the megabyte of
memory space as a group of segments that are
defined by the application. A segment is a logical
unit of memory that may be up to 64k bytes long.
Each segment is made up of contiguous memory
locations and is an independent, separatelyaddressable unit. Every segment is assigned (by
software) a base address, which is its starting
location in the memory space. All segments begin
on 16-bytememory boundaries. There are no
other restrictions on segment locations; segments
may be adjacent, disjoint, partially overlapped,
or fully overlapped (see figure 2-15). A physical
memory location may be mapped into (contained
in) one or more logical segments.
Following Intel convention, word data always is
stored with the most-significant byte in the higher
memory location (see figure 2-13). Most of the
time this storage convention is "invisible" to
anyone working with the processors; exceptions
may occur when monitoring the system bus or
when reading memory dumps.
A special class of data is stored as doublewords;
i.e., two consecutive words. These are called
pointers and are used to address data and code
that are outside the currently-addressable
segments. The lower-addressed word of a pointer
contains an offset value, and the higher-addressed
word contains a segment base address. Each word
is stored conventionally with the higher-addressed
byte containing the most-significant eight bits of
the word (see figure 2-14).
The segment registers point to (contain the base
address values of) the four currently addressable
segments (see figure 2-16). Programs obtain
access to code and data in other segments by
changing the segment registers to point to the
desired segments.
Every application will define and use segments
differently. The currently addressable segments
provide a generous work space: 64k bytes for
code, a 64k byte stack and 128k bytes of data
storage. Many applications can be written to
simply initialize the segment registers and then
forget them. Larger applications should be
designed with careful consideration given to segment definition.
VALUE OF WORD STORED AT 724H: 5502H
Figure 2-13. Storage of Word Variables
VALUE OF POINTER STORED AT 4H:
SEGMENT BASE ADDRESS: 3B4CH
OFFSET:65H
Figure 2-14. Storage of Pointer Variables
2-10
8086 AND 8088 CENTRAL PROCESSING UNITS
FULLY
OVERLAP~I
SEGMENT D
:;~m~p~1
CONTIGUOUS~~
1 SEGMENT A
I
-!
----r-DISJOINT
SEGMENT B 1
I
I
SEGMENT C ,
1 SEGMENT E
LOGICAL
SEGMENTS
1
I
1~___-!I~__. . . .fI___-+I____17.., }~~1S6~~L
t
t
OH
10000H
t
20000H
t
30000H
Figure 2-15. Segment Locations in Physical Memory
The segmented structure of the 8086/8088
memory space supports modular software design
by discouraging huge, monolithic programs. The
segments also can be used to advantage in many
programming situations. Take, for example, the
case of an editor for several on-line terminals. A
64k text buffer (probably an extra segment) could
be assigned to each terminal. A single program
could maintain all the buffers by simply changing
register ES to point to the buffer of the terminal
requiring service.
FFFFFH
DATA:
Ds:1
B
CODE:
cs:1
E
STACK: SS:
1
EXTRA: ES:
1
H
~-~-I
D
~I I
I
h II I
I I
1
I L
I
Physical Address Generation
It is useful to think of every memory location as
having two kinds of addresses, physical and
logical. A physical address is the 20-bit value that
uniquely identifies each byte location in the
megabyte memory space. Physical addresses may
range from OH through FFFFFH. All exchanges
between the CPU and memory components use
this physical address.
L_
Programs deal with logical, rather than physical
addresses and allow code to be developed without
prior knowledge of where the code is to be located
in memory and facilitate dynamic management of
memory resources. A logical address consists of a
segment base value and an offset value. For any
given memory location, the segment base value
OH
Figure 2-16. Currently Addressable Segments
2-11
8086 AND 8088 CENTRAL PROCESSING UNITS
locates the first byte of the containing segment
and the offset value is the distance, in bytes, of
the target location from the beginning of the
segment. Segment base and offset values are
unsigned 16-bit quantities; the lowest-addressed
byte in a segment has an offset of O. Many different logical addresses can map to the same
physical location as shown in figure 2-17. In
figure 2-17, physical memory location 2C3 H is
contained in two different overlapping segments,
one beginning at 2BOH and the other at 2COH.
2-2). Instructions always are fetched from the current code segment; IP contains the offset of the
target instruction from the beginning of the segment. Stack instructions always operate on the
current stack segment; SP contains the offset of
the top of the stack; Most variables (memory
operands) are assumed to reside in the current
data segment, although a program can instruct
the BIU to access a variable in one of the other
currently addressable segments. The offset of a
memory variable is calculated by the EU. This
calculation is based on the addressing mode
specified in the instruction; the result is called the
operand's effective address (EA). Section 2.8
covers addressing modes and effective address
calculation in detail.
Whenever the BIU accesses memory-to fetch an
instruction or to obtain or store a variable-it
generates a physical address from a logical
address. This is done by shifting the segment base
value four bit positions and adding the offset as
illustrated in figure 2-18. Note that this addition
process provides for modulo 64k addressing
(addresses wrap around from the end of a segment to the beginning of the same segment).
Strings are addressed differently than other
variables. The source operand of a string instruction is assumed to lie in the current data segment,
but another currently addressable segment may be
specified. Its offset is taken from register SI, the
source index register. The destination operand of
a string instruction always resides in the current
The BIU obtains the logical address of a memory
location from different sources depending on the
type of reference that is being made (see table
r
PHYSICAL
ADDRESS
2C4H
2C3H
2C2H
2C1H
2COH
2 BFH
2BEH
2BDH
2BCH
2BBH
2BAH
2B9H
2B8H
2B7H
2B6H
2B5H
2B4H
2B3H
2B2H
2B1H
2BOH
..
r
OF!SET
(3H)
SEGMENT
BASE
LOGICAL
ADDRESSES
.. I
OFFSET
(13H)
~
'- SEGMENT
BASE
r-
Figure 2-17. Logical and Physical Addresses
2-12
'r'
r-
8086 AND 8088 CENTRAL PROCESSING UNITS
SHIFT LEFT 4 BITS
11
2
3
19
10
+
,
f
15
11
0
4
,
2
6
2
19
+
i I
I
1 2
3 4
0
1
0
o
0
2
2
BASE
LOGICAL
ADDRESS
IOFFSET
0
15
21_
I"GM"'}
o
15
0
21
PHYSICAL ADDRESS
0
TO MEMORY
Figure 2-18. Physical Address Generation
Table 2-2. Logical Address Sources
TYPE OF MEMORY REFERENCE
Instruction Fetch
Stack Operation
Variable (except following)
String Source
String Destination
BP Used As Base Register
DEFAULT
SEGMENT
BASE
ALTERNATE
SEGMENT
BASE
OFFSET
CS
SS
OS
OS
ES
SS
NONE
NONE
CS,ES,SS
CS,ES,SS
NONE
CS,OS,ES
IP
SP
Effective Address
SI
01
Effective Address
extra segment; its offset is taken from DI, the
destination index register. The string instructions
automatically adjust SI and DI as they process the
strings one byte or word at a time.
Dynamically Relocatable Code
The segmented memory structure of the 8086 and
8088 makes it possible to write programs that are
position-independent, or dynamically relocatable.
Dynamic relocation allows a multiprogramming
or multitasking system to make particularly effective use of available memory. Inactive programs
can be written to disk and the space they occupied
allocated to other programs. If a disk-resident
program is needed later, it can be read back into
any available memory location and restarted.
Similarly, if a program needs a large contiguous
block of storage, and the total amount is available
only in nonadjacent fragments, other program
segments can be compacted to free up a continuous space. This process is shown graphically
in figure 2-19.
When register BP, the base pointer register, is
designated as a base register in an instruction, the
variable is assumed to reside in the current stack
segment. Register BP thus provides a convenient
way to address data on the stack; BP can be used,
however, to access data.in any of the other currently addressable segments.
In most cases, the BIU's segment assumptions are
a convenience to programmers. It is possible,
however, for a programmer to explicitly direct the
BIU to access a variable in any of the currently
addressable segments (the only exception is the
destination operand of a string instruction which
must be in the extra segment). This is done by
preceding an instruction with a segment override
prefix. This one-byte machine instruction tells the
BIU which segment register to use to access a
variable referenced in the following instruction.
In order to be dynamically relocatable, a program
must not load or alter its segment registers and
must not transfer directly to a location outside the
current code segment. In other words, all offsets
in the program must be relative to fixed values
2-13
8086 AND 8088 CENTRAL PROCESSING UNITS
BEFORE RELOCATION
AFTER RELOCATION
CODE
SEGMENT
'j
CS
STACK
SEGMENT
I
CS
SS
SS
.---
DS
DS
f----
.--
ES
ES
f-
CODE
SEGMENT
STACK
SEGMENT
DATA
SEGMENT
EXTRA
SEGMENT
DATA
SEGMENT
EXTRA
SEGEMENT
~FREESPACE
Figure 2-19. Dynamic Code Relocation
stack segment's base address. Note, however, that
the stack's base address (contained in SS) is not
the "bottom" of the stack.
contained in the segment registers. This allows the
program to be moved anywhere in memory as
long as the segment registers are updated to point
to the new base addresses. Section 2.10 contains
an example that illustrates dynamic code
relocation.
8086 and 8088 stacks are 16 bits wide; instructions
that operate on a stack add and remove stack
items one word at a time. An item is pushed onto
the stack (see figure 2-20) by decrementing SP by
2 and writing the item at the new TOS. An item is
popped off the stack by copying it from TOS and
then incrementing SP by 2. In other words, the
stack grows down in memory toward its base
address. Stack operations never .move items on
the stack, l).or do they erase them. The top of the
stack changes only as a result of updating the
.
stack pointer.
Stack Implementation
Stacks in the 8086 and 8088 are implemented in
memory and are located by the stack segment
register (SS) and the stack pointer register (SP). A
system may have an unlimited number of stacks,
and a stack may be up to 64k bytes long, the maximum length of a segment. (An attempt to expand
a stack beyond 64k bytes overwrites the beginning
of the stack.) One stack is directly addressable at
a time; this is the current stack, often referred to
simply as "the" stack. SS contains the base
address of the current stack and SP points to the
top of the stack (TOS). In other words, SP contains the offset of the top of the stack from the
Dedicated and Reserved Memory
Locations
Two areas in extreme low and high memory. are
dedicated, to specific processor functions or are
reserved by Intel Corporation for use by Intel
2-14
8086 AND 8088 CENTRAL PROCESSING UNITS
POPAX
POPBX
AxG:I:EI-l
PUSH AX
EXISTING
STACK
1062
00
11
1060
22
33
105E 44
55
66
77
10SA 88
99
105B
TOS
r
i
1062
00
11
1060
22
33
::;;0
0<
105E
44
55
I-tn
0"-
105B
66
77
105A
88
99
1
1058
AA BB
.J
~
1-1-
IDO
AA BB
TOS
01
23
1056
34
12
45
67
1054
45
67
89
AB
1052
89
AB
CD
EF
CD
EF
00
08
Bxl!ill!1-1 :
AxI12 1341-1
r
1050
: 10 : 50
00
SP
06
00
11
1060 22
33
105E
55
1062
1
1
I.
TOS
44'
105C 66
77
105A 88
99
105B AA BB
1056
34
12
1054
45
67
1052
89
AB
I I
II
I I
I :
JI
_--1
r1050~
Iss
SP
~SS
00
OA SP
STACK OPERATION FOR CODE SEQUENCE
PUSH AX
POPAX
POPBX
Figure 2-20. Stack Operation
hardware and software products. As shown in
figure 2-21, the location are: OH throgh 7FH (128
bytes) and FFFFOH through FFFFFH (16 bytes).
These areas are used for interrupt and system
reset processing 8086 and 8088 application
systems should not use these areas for any other
purpose. Doing so may make these systems
incompatible with future Intel products.
totally transparent to software. This allows maximum data packing where memory space is
constrained.
8086/8088 Memory Access
Differences
The 8086 always fetches the instruction stream in
words from· even addresses except that the first
fetch after a program transfer to an odd address
obtains a byte. The instruction stream is
disassembled inside the processor and instruction
alignment will not materially affect the performance of most systems.
The 8086 can access either 8 or 16 bits of memory
at a time. If an instruction refers to a word
variable and that variable is located at an evennumbered address, the 8086 accesses the complete
word in one bus cycle. If the word is located at an
odd-numbered address, the 8086 accesses the
word one byte at a time in two consecutive bus
cycles.
The 8088 always accesses inemory in bytes. Word
operands are accessed in two bus cycles regardless
of their alignment. Instructions also are fetched
one byte at a time. Although alignment of word
operands does not affect the performance of the
8088, locating 16-bit data on even addresses will
insure maximum throughput if the system is ever
transferred to an 8086.
To maximize throughput in 8086-based systems,
16-bit data should be stored at even addresses
(should be word-aligned). This is particularly true
of stacks. Unaligned stacks can slow a system's
response to interrupts. Nevertheless, except for
the performance penalty, word alignment is
2.4 Input/Output
The 8086 and 8088 have a versatil.~ se( of input/output facilities. Both processors provide a
large I/O space that is, separate from the memory
2-15
Mn,emonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Restricted 1/0 Locations
Locations F8H through FFH (eight of the 64k
locations) in the I/O space are reserved by Intel
Corporation for use by future Intel hardware and
software products. Usirig these locations for any
other purpose may inhibit compatibility with
future Intel products.
8086/80881/0 Access Differences
The 8086 can transfer either 80r 16 bits at a time
to a device located in the I/O space. A 16-bit
device should be located at an even address so
that the word will be transferred in a single bus
cycle. An 8-bit device may be located at either an
even or odd address; however, the internal
registers in a given device must be assigned alleven or all-odd addresses.
The 8088 transfers one byte per bus cycle. If a
16-bit device is used in the 8088 I/O space, it must
be capable of transferring words in the same
fashion, Le., eight bits at a time in two bus cycles.
(The 8089 Input/Output Processor can provide a
straightforward interface between the 8088 and a
16-bit I/O device.) An 8-bit device may be located
at odd or even addresses in the 8088 I/O space
and internal registers may be assigned consecutive
addresses (e.g., IH, 2H, 3H). Assigning all-odd
or all-even addresses to these registers, however,
will'simplify transferring the system to an 8086
CPU.'
Figure 2-21. Reserved and Dedicated Memory
and 110 Locations
space, and instructions that transfer data between
the CPU and devices located in the I/O space.
I/O devices also may be placed in the memory
space to bring the power of the full instruction set
and addressing modes to input/output pro~
cessing. For high-s'peed transfers, the CPUs may
be used with traditional direct memory' access
controllers or the 8089 Input/Output Processor.
Memory-Mapped 1/0
I/O devices also may be placed in the 8086/8088
memory space. As long as the devices respond like
memory components, the CPU does not know the
difference.
InputlOutput Space
The 8086/8088 I/O space can accommodate up to
64k 8-bit ports or up to 32k 16-bit ports. The IN
and OUT (input and output) instructions transfer
data between the accumulator (AL for byte
transfers, AX for word transfers) and ports
located in the I/O space.
Memory-mapped I/O provides additional programming flexibility. Any instruction that
references memory may be used to access an I/O
port located in the memory space. For example,
the MOV (move) instruction can transfer' data
between any 8086/8088 register and a port, or the
AND, OR and TEST instructions may be used to
manipulate bits in I/O device registers. In addition, memory-mapped I/O can take advantage of
the 8086/8088 memory addressing modes. A
group of terminals, for example, could be treated
as an array in memory with an index register
The I/O space is not segmented; to access a port,
the BIU simply places the port address (0-64k) on
the lower 16 lines of the address bus. Different
forms of the I/O instructions allow the address to
be specified as a fixed value in the instruction or
as a variable taken from register OX:
Mnemonics © Intel, 1978
2-16
8086 AND 8088 CENTRAL PROCESSING UNITS
2.5 Multiprocessing Features
selecting a terminal in the array. Sectian 2.10 pravides examples af using the instructian set and
addressing mades with memory-mapped 110.
As micropracessor prices have declined,
multiprocessing (using two or more coardinated
processors in a system) has become an increasingly attractive design alternative. Performance
can be substantially improved by distributing
system tasks among separate, concurrently executing processors. In addition, multiprocessing
encourages a modular appraach to design, usually
resulting in systems that are more easily maintained and enhanced. For example, figure 2-22
shows a multiprocessor system in which 110
activities have been delegated to an 8089 lOP.
Should an 110 device in the system be changed
(e.g., a hard disk substituted for a floppy), the
impact af the modification is confined to the 110
subsystem and is transparent to the CPU and to
the application software.
.
Of course, a price must be paid for the added programming flexibility that memory-mapped 110
provides. Dedicating part of the ni.emory space to
I/O devices reduces the number of addresses
available for memory, althaugh with a megabyte
af memory space this should rarely be a constraint. Memary reference instructions also take
langer to. execute and are samewhat less compact
than the simpler IN and OUT instructions.
Direct Memory Access
When configured in minimum mode, the 8086
and 8088 pravide HOLD (hold) and HLDA (hald
acknowledge) signals that are campatible with
traditianal DMA controllers such as the 8257 and
8237. A DMA controller can request use af the
bus for direct transfer af data between an 110
device and memory by activating HOLD. The
CPU will complete the current bus cycle, if one is
in progress, and then issue HLDA, granting the
bus to the DMA controller. The CPU will not
attempt to use the bus until HOLD goes inactive.
The 8086 and 8088 are designed for the
multiprocessing environment. They have built-in
features that help solve the coordination problems that have discouraged multipracessing
system develapment in the past.
Bus Lock
The 8086 addresses memory that is physically
organized in two separate banks, ane containing
evencaddressed bytes and ane containing odd-addressed. bytes. An 8-bit DMA controller must
alternately select these banks to access logically
adjacent bytes in memory. The 8089 provides a
simple way to interface a high-speed 8-bit device
to. an 8086-based system (see Chapter 3).
When configured in maximum mode, the 8086
and 8088 provide the LOCK (bus lock) signal.
The BIU activates LOCK when the EU executes
the one-byte LOCK prefix instruction. The
LOCK signal remains active throughout executian of the instruction that follows the LOCK
prefix. Interrupts are not affected by the LOCK
prefix. If anather processar requests use of the
bus (via the request/grant lines, which are
discussed shortly), the CPU records the request,
but does not honor it until execution of the locked
instruction has been completed.
8089 Input/Output Processor (lOP)
The 8086 and 8088 are designed. to be used with
the 8089 in high-performance 110 applications.
The 8089 conceptually resembles a
microprocessor with two DMA channels and an
instruction set specifically tailored for I/O operations. Unlike simple DMA controllers, the 8089
can service II 0 devices directly, removing this
task from the CPU. In addition,it can transfer
data on its own bus or on the system bus, can
match 8- or 16-bit peripherals to 8- or 16-bit
buses, and can transfer data from· memory to
memory and from 110 device to 110 device.
Chapter 3 describes the 8089 in detail.
Note that the LOCK signal remains active for the
duration af a single instruction. If two consecutive instructions are each preceded by a
LOCK prefix, there will still be an unlocked
periad between these instructions. In the case of a
locked repeated string instruction, LOCK does
remain active for the duration of the block
operation.
When the 8086 or 8088 is canfigured in minimum
mode, the LOCK signal is not available. The
LOCK prefix can be used, however, to delay the
2-17
Mnemonics @ Intel, 1978
8086ANO 8088 CENTRAL PROCESSING UNITS
1/0 BUFFERS
DATA
8086
OR
8088
CPU
4
1
, SYSTEM BUS
~Il~~ I~
•
Figure 2-22. Multiprocessing System
generation of an HLDA response to a HOLD
request until execution of the locked instruction is
completed.
that it is available. They likewise agree to set the
semaphore when they are using the resource and
to clear it when they are finished.
The LOCK signal provides information only. It is
the, responsibility of other processors on the
shared bus to not attempt to obtain the bus while
LOCK is active. If the system uses 8289 Bus
Arbiters to control access to the shared bus, the
8289's accept LOCK as an input and do not relinquish the bus while this signal is active.
The XCHG instruction can obtain the current
value of the semaphore and set it to "busy" in a
single instruction. The instruction, however,
requires two bus cycles to swap 8-bit values. It is
possible for another processor to obtain the bus
between these two cycles and to gain access to the
partially-updated semaphore. This can be
prevented by preceding the XCHG instruction
with a LOCK prefix, as illustrated in figure 2-25.
The bus lock establishes control over access to the
semaphore and thus to the shared resource.
LOCK may be used in multipr~cessing systems to
coordinate access to a common resource, such as
a buffer or a pointer. If access to the resource is
not controlled, one processor can read an
erroneous value from the resource when another
processor is updating it (see figure 2-23).
WAIT and TEST
The 8086 and 8088 (in either maximum or
minimum mode) can be synchronized to an external event with the WAIT (wait for TEST) instruction and the TEST input signal. When the EU
executes aWAIT instruction, the result depends
on the, state of the TEST input line. If TEST is
inactive, the processor enters' an idle state and
repeatedly retests the TEST line at five-clock
intervals. If TEST is active, execution continues
with the instruction following the WAIT.
Access can be controlled (see figure 2-24) by using
the LOCK prefix in conjunction with the XCHG
(exchange register with memory) instruction. The
basis for controlling access to a given resource is a
semaphore, a software-settable flag or switch that
indicates whether the resource is "available"
(semaphore=O) or "busy" (semaphore=I). Processorsthat share the bus agree by convention not
to use 'the resource unless the semaphore indicates
Mnemonics © Intel, 1978
2-18
8086 AND 8088 CENTRAL PROCESSING UNITS
Escape
BUS CYCLE
0
2
SHARED POINTER
IN MEMORY
The ESC (escape) instruction provides a way for
another processor to obtain an instruction and lor
a memory operand from an 8086/8088 program.
When used in conjunction with WAIT and TEST,
ESC can initiate a "subroutine" that executes
concurrently in another processor (see figure
2-26).
PROCESSOR ACTIVITIES
105 I 2214C I 18 1
1C2 1 5914C , 1B 1
1C2 1 5914C ,I B 1
IC21 59131, 05 1
"A" UPDATES 1 WORD
Six bits in the ESC instruction may be specified by
the programmer when the instruction is written.
By monitoring the 8086/8088 bus and control
lines, another processor can capture the ESC
instruction when it is fetched by the BIU. The six
bits may then direct the external processor to perform some predefined activity.
"8" READS PARTIALLY
UPDATED VALUE
"A" COMPLETES UPDATE
If the 8086/8088 is configured in maximum
mode, the external processor, having determined
that an ESC has been fetched, can monitor QSO
Figure 2-23. Uncontrolled Access to Shared
Resource
SHARED POINTER
IN MEMORY
PROCESSOR ACTIVITIES
I
I
"A" OBTAINS EXCLUSIVE
USE
IC21 5914C 118
"A" UPDATES 1 WORD
IC2 1S914C 118
"B" TESTS SEMAPHORE
AND WAITS
I C2 1 59 1 31 '1 05
"A" COMPLETES UPDATE
IC2159131105
"B" TESTS SEMAPHORE
AND WAITS
IC21 59.131 105
"A" RELEASES RESOURCE
7
IC2159131 105
"B" OBTAINS
EXCLUSIVE USE
8
I C2 1 59 1 31
I 05
"B" READS
UPDATED VALUE
I C2 I 59 131
I 05
"B" RELEASES RESOURCE
BUSCYCLE
SEMAPHORE
0
05 I 2214C 11 B
05 I 2214C 11 B
2
4
6
9
0
0
Figure 2-24. Controlled Access to Shared Resource
2-19
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
MOV
GETSEMA·
PHORE&
SET "BUSY"
and QSl (the queue status lines, discussed in section 2.6) and determine when the ESC instruction
is executed. If the instruction references memory
the external processor can then monitor the bus
and capture the operand's physical address
and I or the operand itself.
AL,l
. WAIT: LOCK XCHG AL, SEMAPHORE
BUSY(l)
Note that fetching an Esci~struction is not tan'~
tamount to executing iL .Tile ESC may be preceded by a jump that·,causes the queue to be
reinitialized. This event also can be determined
from the queue status lines.
TEST AL,AL
JNZ
WAIT
Request/Grant Lines
SET
SEMAPHORE
"AVAILABLE"
(
When the 8086 or 8088 is configured in maximum
mode, the HOLD and HLDA lines evolve into
two more sophisticated signals called RQ/GTO
and RQ/GTI. These are bidirectional lines that
can be used to share a local bus between an 8086
or 8088 and two other processors via ahandshake
sequence.
MOV SEMAPHORE,O
The request/grant sequence is a three-phase cycle:
request, grant and release. First, the processor
desiring the bus pulses a request/grant line. The
CPU returns a pulse on the same line indicating
that it is entering the "hold acknowledge" state
and is relinquishing the bus. The BIU is logically
disconnected from the bus during this period. The
EXIT)
Figure 2-25. Using XCHG and LOCK
PROCESSOR
"A"
Figure 2-26. Using ESC with WAIT and TEST
Mnemonics © Intel, 1978
2-20
8086 AND 8088 CENTRAL PROCESSING UNITS
EU, however, will continue to execute instructions until an instruction requires bus access or
the queue is emptied, whichever occurs first.
When the other processor has finished with the
bus, it sends a final pulse to the 8086/8088 indicating that the request has ended and that the
CPU may reclaim the bus.
time, and to obtain compatibility with the wide
variety of boards available in the iSBC product
line.
The Multibus architecture provides a versatile
communications channel that can be used to coordinate a wide variety of computing modules (see
figure 2-27). Modules in a Multibus system are
designated as masters or slaves. Masters may
obtain use of the bus and initiate data transfers on
it. Slaves are the objects of data transfers only.
The Multibus architecture allows both 8- and 16bit masters to be intermixed in a system. In addition to 16 data lines, the bus design provides 20
address lines, eight multilevel interrupt lines, and
control and arbitration lines. An auxiliary power
bus also is provided to route standby power to
memories if the normal supply fails.
RQ/GTO has higher priority than RQ/GTI. If
requests arrive simultaneously on both lines, the
~nt~es to the processor on RQ/GTO and
RQ/GTl is acknowledged after the bus has been
returned to the CPU. If, however, a request
arrives on RQ/GTO while the CPU is processing a
prior request on RQ/GTl, the second r~est is
not honored until the processor on RQ/GTl
releases the bus.
Multibus™ Architecture
The Multibus architecture maintains its own
clock, independent of the clocks of the modules it
links together. This allows different speed masters
to share the bus and allows masters to operate
asynchronously with respect to each other. The
arbitration logic of the bus permit slow-speed
masters to compete equably for use of the bus.
Once a module has obtained the bus, however,
transfer speeds are dependent only on the
capabilities of the transmitting and receiving
modules. Finally, the Multibus standard defines
the form factors and physical requirements of
modules that communicate on this bus. For a
complete description of the Multibus architec-
Intel has designed a general-purpose
mUltiprocessing bus called the Multibus. This is
the standard design used in iSBCTM single-board
microcomputer products. Many other manufacturers offer products that are compatible with the
Multibus architecture as well. When the 8086 and
8088 are configured in maximum mode, the 8288
Bus Controller outputs signals that are electrically
compatible with the Multibus protocol. Designers
of mUltiprocessing systems may want to consider
using the Multibus architecture in the design of
their products to reduce development cost and
MASTER
MASTER
WITH
BUS-ACCESSIBLE
MEMORY
MEMORY SLAVE
MUlTIBUSTM INTERFACE
Figure 2-27. MultibusTM-Based System
2-21
I/O SLAVE
8086 AND 8088 CENTRAL PROCESSING UNITS
ture, refer to the Intel Multibus Specification
(document number 9800683) and Application
Note 28A, "Intel Multibus Interfacing."
and 8088 can handle up to 256 different interrupt
types. Interrupts may be initiated by devices
external to the CPU; in addition, they also maybe
triggered by software interrupt instructions and,
under certain conditions, by the CPU itself (see
figure 2-28). Figure 2-29 illustrates the basic
response of the 8086 and 8088 to an interrupt.
The next sections elaborate on the information
presented in this drawing.
8289 Bus Arbiter
Multiprocessor systems require a means of coordinating the processors' use of the shared bus.
The 8289 Bus Arbiter works in conjunction with
the 8288 Bus Controller to provide this control
for 8086- and 8088-based systems. It is compatiblewith the Multibus architecture and can be used
in other shared-bus designs as well.
External Interrupts
The 8086 and 8088 have two lines that external
devices may use to signal interrupts (INTR and
NMI). The INTR (Interrupt Request) line is
usually driven by an Intel® 8259A Programmable
Interrupt Controller (PIC), which is in turn connected to the devices that need interrupt services.
The 8259A is a very flexible circuit that is controlled by software commands from the 8086 or
8088 (the PIC appears as a set of I/O ports to the
software). Its main job is to accept interrupt
requests from the devices attached to it, determine which requesting device has the highest
priority, and then activate the 8086/8088 INTR
line if the selected device has higher priority than
the device currently being serviced (if there is
one).
The 8289 eliminates race conditions, resolves bus
contention and matches processors operating
asynchronously with respect to each bther. Each
processor on the bus is assigned a different priority. When simultaneous requests for the bus
arrive, the 8289 resolves the contention and grants
the bus to the processor with,the highest priority;
three different prioritizing techniques may be
used. Chapter 4 discusses the 8289 in more detail.
2.6 Processor Control and
Monitoring
Interrupts
When INTR is active, the CPU takes different
action depending on the state of the interruptenable flag (IF). No action takes place, however,
until the currently-executing instruction has been
The 8086 and 8088 have a simple and versatile
interrupt system.' Every interrupt is assigned a
type code that identifies it to the CPU. The 8086
I
I
NON·MASKABLE
INTERRUPT
REQUEST
NMI
r - - - - - - - - ---------,
I
I
I
I
I
I
I
I
I
I
I
INTERRUPT
LOGIC
Lt
INTn
INSTR.
INTO
INSTR.
t+
DIVIDE
ERROR
INTR
8259A
I
I
SINGLE·
STEP
(TF=1)
I
I
I
I
I
I
I
I
L 80S6/S08S CPU
I
-----------------~
Figure 2-28. Interrupt Sources
2-22
-----
-
MASKABLE
INTERRUPT
REQUESTS
8086 AND 8088 CENTRAL PROCESSING UNITS
Figure 2-29. Interrupt Processing Sequence
2-23
8086 AND 8088 CENTRAL PROCESSING UNITS
completed. * Then, if IF is clear (meaning that
interrupts signaled on INTR are masked or disabled), the CPU ignores the interrupt request and
processes the next instruction. The INTR signal is
not latched by the CPU, so it must be held active
until a response is received or the request is
withdrawn. If interrupts on INTR are enabled (if
IF is set), then the CPU recognizes the interrupt
request and processes it. Interrupt requests arriving on INTR can be enabled by executing an STI
(set interrupt-enable flag) instruction, and disabled by executing a CLI (clear interrupt-enable
flag) instruction. They also may be selectively
masked (some types enabled, some disabled) by
writing commands to the 8259A. It should be
noted that in order to reduce the likelihood of
excessive stack buildup, the STI and IRET
instructions will reenable interrupts only after
the end of the following instruction.
An external interrupt request also may arrive on
another CPU line, NMI (non-maskable interrupt). This line is edge-triggered (lNTR is leveltriggered) and is generally used to signal the CPU
of a "catastrophic" event, such as the imminent
loss of power, memory error detection or bus
parity error. Interrupt requests arriving on NMI
cannot be disabled, are latched by the CPU, and
have higher priority than an interrupt request on
INTR. If an interrupt request arrives on both
lines during the execution of an instruction, NMI
will be recognized first. Non-maskable interrupts
are predefined as type 2; the processor does not
need to be supplied with a type code to call the
NMI procedure, and it does not run the INT A bus
cycles in response to a request on NMI.
The time required for the CPU to recognize an
external interrupt request (interrupt latency)
depends on how many clock periods remain in the
execution of the current instruction. On the
average, the longest latency occurs when a
multiplication, division or variable-bit shift or
rotate instruction is executing when the interrupt
request arrives (see section 2.7 for detailed
instruction timing data). As mentioned previously, in a few cases, worst-case latency will
span two instructions rather than one.
The CPU acknowledges the interrupt request by
executing two consecutive interrupt acknowledge
(lNT A) bus cycles. If a bus hold request arrives
(via the HOLD or request/grant lines) during the
INT A cycles, it is not honored until the cycles
have been completed. In addition, if the CPU is
configured in maximum mode, it activates the
LOCK signal during these cycles to indicate to
other processors that they should not attempt to
obtain the bus. The first cycle signals the 8259A
that the request has been honored. During the
second INT A cycle, the 8259A responds by placing a byte on the data bus that contains the interrupt type (0-255) associated with the device
requesting service. (The type assignment is made
when the 8259A is initialized by software in the
8086 or 8088.) The CPU reads this type code and
uses it to call the corresponding interrupt
procedure.
Internal Interrupts
An INT (interrupt) instruction generates an interrupt immediately upon completion of its execution. The interrupt type coded into the instruction
supplies the CPU with the type code needed to
call the procedure to process the interrupt. Since
any type code may be specified, software interrupts may be used to test interrupt procedures
written to service external devices.
"There are a few cases in which an interrupt request is not recognized until after the following instruction. Repeat, LOCK
and segment override prefixes are considered "part of" the instructions they prefix; no interrupt is recognized between
execution of a prefix and an instruction. A MOV (move) to segment register instruction and a POP segment register
instruction are treated similarly: no interrupt is recognized until after the following instruction. This mechanism protects
a program that is changing to a new stack (by updating SS and SP). If an interrupt were recognized after SS had be€n
changed, but before SP had been altered, the processor would push the flags, CS and IP into the wrong area of memory.
It follows from this that whenever a segment register and another value must be updated together, the segment register
should be changed first, followed immediately by the instruction that changes the other value. There are also two cases,
WAIT and repeated string instructions, where an interrupt request is recognized in the middle of an instruction. In these
cases, interrupts are accepted after any completed primitive operation or wait test cycle.
Mnemonics © Intel, 1978
2-24
8086 AND 8088 CENTRAL PROCESSING UNITS
If the overflow flag (OF) is set, an INTO (interrupt on overflow) instruction generates a type 4
interrupt immediately upon completion of its
execution.
2.
3.
4.
The CPU itself generates a type 0 interrupt
immediately following execution of a DIV or
IDIV (divide, integer divide) instruction if the
calculated quotient is larger than the specified
destination.
If the trap flag (TF) is set, the CPU automatically
generates a type 1 interrupt following every
instruction. This is called single-step execution
and is a powerful debugging tool that is discussed
in more detail shortly.
Interrupt Pointer Table
The interrupt pointer (or interrupt vector) table
(figure 2-30) is the link between an interrupt type
code and the procedure that has been designated
to service interrupts associated with that code.
The interrupt pointer table occupies up to the first
1k bytes of low memory. There may be up to 256
entries in the table, one for each interrupt type
All internal interrupts (INT, INTO, divide error,
and single-step) share these characteristics:
1. The interrupt type code is either contained in
the instruction or is predefined.
AVAILABLE
INTERRUPT
POINTERS
1224)
r
I-
TYPE 33 POINTER:
(AVAILABLE)
I-
TYPE 32 POINTER:
(AVAILABLE)
I-
TYPE 31 POINTER:
(RESERVED)
084H
080H
07FH
-
RESERVED
INTERRUPT
POINTERS
(27)
"I"
014H
010H
DEDICATED
INTERRUPT
POINTERS
(5)
No INT A bus cycles are run.
Internal interrupts cannot be disabled, except
for single-step.
Any internal interrupt (except single-step)
has higher priority than any external interrupt (see table 2-3). If interrupt requests
arrive on NMI and/or INTR during execution of an instruction that causes an internal
interrupt (e.g., divide error), the internal
interrupt is processed first.
OOCH
008H
004H
-
TYPE 5 POINTER:
(RESERVED)
-
-
TYPE 4 POINTER:
OVERFLOW
-
...,
TYPE 3 POINTER: .•7'
I-BYTE INT INSTRUCTION
-
TYPE 2 POINTER:
NON-MASKABLE
-
-
TYPE 1 POINTER:
SINGLE-STEP
-
-
TYPE 0 POINTER:
DIVIDE ERROR
-
CS BASE ADDRESS
IP OFFSET
Figure 2-30. Interrupt Pointer Table
2-25
Mnemonics © Intel, 1978
8086ANO 8088 CENTRAL PROCESSING UNITS
that can occur in the system. Each entry in the
table is a doubleword pointer .containing the
address of the procedure thatis to service interrupts of that type. The higher-addressed word of
the pointer contains the base address of the segment containing the procedure. The lower-addressed word contains the procedure's offset
from the beginning of the seginenL Since each
entry is four bytes long, the CPU can calculate the
location of the correct entry for a given interrupt
type by simply multiplying(type*4).
are recognized in turn, in the order of their
priorities except for INTR. INTR is notrecognized until after the following instruction because
recognition of the earlier interrupts cleared IF. Of
couse interrupts could be reenabled in any of the
interrupt response routines if earlier response to
INTR is desired.
As 'figure 2c 31 shows, all main-line .code is exe"
cuted in single-step mode. Also, because of the
order of interrupt processing, the opportunity
exists in each occurrence of the single-step routine
to select whether· pending interrupt routines
(divide error and INTR routines in this example)
are executed at full speed orin sirigle-stepmode.
Table 2-3. Interrupt Priorities
INTERRUPT
Divide error, INT n, INTO
NMI
INTR
Single-step
PRIORITY
highest
Interrupt Procedures
lowest
When an interrupt service procedure is entered,
.the flags, CS, and IP are pushed onto the stack
and TF and IF are cleared. The procedure may
reenable external interrupts with the STI (set
interrupt-enable flag) instruction, thus allowing
itself to be interrupted by a request on INTR.
(Note, however, that interrupts are not actually
enabled until the instruction following STI has
ex'ecuted.) An interrupt procedure always may be
interrupted by a request arriving on NMI.
Software- or processor-initiated interrupts
occurring within the procedure also will interrupt
the procedure. Care must be taken in interrupt
procedures that the type of interrupt being serviced by the procedure does not itself inadvertently occur within the procedure. For example,
an attempt to divide by 0 in the divide error (type
0) interrupt procedure may result in the procedure
being reentered endlessly. Enough stack space
must be available to accommodate the maximum
depth of interrupt nesting that can occur in the
system.
Space at the high end of the table that would be
occupied by entries for interrupt types that cannot
occur in a given application may be used for other
purposes. The dedicated and reserved portions of
the interrupt pointer table (locations OH through
7FH), however, should not be used for any other
purpose to insure proper system operation and to
preserve compatibility with future Intel hardware
and software products.
After pushing the flags onto the stack, the 8086 or
8088 activates an interrupt procedure by executing the equivalent of an intersegment indirect
CALL instruction. The target of the "CALL" is
the address contained in the interrupt pointer
table element located at (type*4). The CPU saves
the address of the next instruction by pushing CS
and IP onto the stack. These are then replaced by
the second and first words of the table element,
thus transferring control to the procedure.
If mUltiple interrupt requests arrive simulta-
neously, the processor activates the interrupt procedures in priority order. Figure 2-31 shows how
procedures would be activated in an extreme case.
The processor is running in single-step mode with
external interrupts enabled. During execution of a
divide instruction, INTR is activated. Furthermore the instruction generates a divide error
interrupt. Figure 2-31 shows that the interrupts
Mnemonics © Intel, 1978
Like all procedures, interrupt procedures should
save any registers they use before updating them,
imdrestore them before terminating. It is good
practice for an interrupt procedure to enable
external interrupts for all but "critical sections"
of code (those sections that cannot be interrupted
., without risking erroneous results). If external
interrupts are disabled for too long in a procedure, interrupt requests on INTR can potentially be lost.
2-26
8086 AND 8088 CENTRAL PROCESSING UNITS
~
~
DIVIDE
INSTRUCTION
INTR
~
DIVIDE ERROR RECOGNIZED
~
PUSH FLAGS
PUSH CS& IP
CLEAR IF &TF
EXECUTE NEXT
INSTRUCTION
I
SINGLE STEP RECOGNIZED
~
~
PUSH FLAGS
PUSH CS & IP
CLEAR IF &TF
DIVIDE ERROR
PROCEDURE
I
I
SINGLE STEP
PROCEDURE'
POPCS&IP
POP FLAGS
TF=1,IF=1
I
I
POP CS& IP
POP FLAGS
INTR RECOGNIZED
~
TF=O,IF=O
I
PUSH FLAGS
PUSH CS& IP
CLEAR IF &TF
EXECUTE NEXT
INSTRUCTION
l
SINGLE STEP RECOGNIZED
I
I
I
I
I
I
I
I
I
~
~
PUSH FLAGS
PUSH CS & IP
CLEAR IF &TF
INTR
PROCEDURE
I
I
I
SINGLE STEP
PROCEDURE'
POP CS & IP
POP FLAGS
TF=1,IF=1
J
, TF CAN BE SET IN THE
SINGLE STEP PROCEDURE
IF SINGLE STEPPING OF
THE DIVIDE ERROR OR INTR
PROCEDURE IS DESIRED.
I
POPCS&IP
POP FLAGS
TF=O,IF=O
I
Figure 2-31. Processing Simultaneous Interrupts
2-27
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Single-stepping is a valuable debugging tool. It
allows the single-step procedure to act as a "window" into the system through which operation
can be observed instruction-by-instruction. A
single-step interrupt procedure, for example, can
print or display register contents, the value of the
instruction pointer (it is on the stack), key
memory variables, etc., as they change after each
instruction. In this way the exact flow of a program can be traced in detail, and the point at
which discrepancies occur can be determined.
Other possible services that could be provided by
a single-step routine include:
All interrupt procedures should be terminated
with an IRET (interrupt return) instruction. The
IRET instruction assumes that the stack is in the
same condition as it was when the procedure was
entered. It pops the top three stack words into IP,
CS and the flags, thus returning to the instruction
that was about to be executed when the interrupt
procedure was activated.
The actual processing done by the procedure is
dependent upon the application. If the procedure
is servicing an external device, it should output a
command to the device instructing it to remove its
interrupt request. It might then read status
information from the device, determine the cause
of the interrupt and then take action accordingly.
Section 2.10 contains three typical interrupt procedure examples.
Software-initiated interrupt procedures may be
used as service routines ("supervisor calls") for
other programs in the system. In this case, the
interrupt procedure is activated when a program,
rather than an external device, needs attention.
(The "attention" might be to search a file for a
record, send a message to another program,
request an allocation of free memory, etc.) Software interrupt procedures can be advantageous in
systems that dynamically relocate programs during execution. Since the interrupt pointer table is
at a fixed storage location, procedures may
"call" each other through the table by issuing
software interrupt instructions. This provides a
stable communication "exchange" that is
independent of procedure addresses. The interrupt procedures may themselves be moved so long
as the interrupt pointer table always is updated to
provide the linkage from the "calling" program
via the interrupt type code.
Writing a message when a specified memory
location or I/O port changes value (or equals
a specified value).
•
Providing diagnostics selectively (only for
certain instruction addresses for instance).
•
Letting a routine execute a number of times
before providing diagnostics.
The 8086 and 8088 do not have instructions for
setting or clearing TF directly. Rather, TF can be
changed by modifying the flag-image on the
stack. The PUSHF and POPF instructions are
available for pushing and popping the flags
directly (TF can be set by ORing the flag-image
with OIOOH and cleared by ANDing it with
FEFFH). After TF is set in this manner, the first
single-step interrupt occurs after the first
instruction following the IRET from the singlestep procedure.
If the processor is single-stepping, it processes an
interrupt (either i~ternal or external) as follows.
Control is passed normally (flags, CS and IP are
pushed) to the procedure designated to handle the
type of interrupt that has occurred. However,
before the first instruction of that procedure is
executed, the single-step interrupt is "recognized" and control is passed normally (flags, CS
and IP are pushed) to the type 1 interrupt procedure. When single-step procedure terminates,
control returns to the previous interrupt procedure. Figure 2-31 illustrates this process in a
case where two interrupts occur when the processor is in single-step mode.
Single-Step (Trap) Interrupt
When TF (the trap flag) is set, the 8086 or 8088 is
said to be in single-step mode. In this mode, the
processor automatically generates a type 1 interrupt after each instruction. Recall that as part of
its interrupt processing, the CPU automatically
pushes the flags onto the stack and then clears TF
and IF. Thus the processor is not. in single-step
mode when the single-step interrupt procedure is
entered; it runs normally. When the single-step
procedure terminates, the old flag image is
restored from the stack, placing the CPU back
into single-step mode.
Mnemonics © Intel, 1978
•
Breakpoint Interrupt
A type 3 interrupt is.dedicated to the breakpoint
interrupt. A breakpoint is generally any place in a
program where normal execution is arrested so
2-28
8086 AND 8088 CENTRAL PROCESSING UNITS
that some sort of special processing may be performed. Breakpoints typically are inserted into
programs during debugging as a way of displaying registers, memory locations, etc., at crucial
points in the program.
rupts are disabled by system reset, the system
software should reenable interrupts as soon as the
system is initialized to the point where they can be
processed.
Table 2-4. CPU State Following RESET
The INT 3 (breakpoint) instruction is one byte
long. This makes it easy to "plant" a breakpoint
anywhere in a program. Section 2.10 contains an
example that shows how a breakpoint may be set
and how a breakpoint procedure may be used to
place the processor into single-step mode.
The breakpoint instruction also may be used to
"patch" a program (insert new instructions)
without recompiling or reassembling it. This may
be done by saving an instruction byte, and replacing it with an INT 3 (CCH) machine instruction.
The breakpoint procedure would contain the new
machine instructions, plus code to restore the
saved instruction byte and decrement IP on the
stack before returning, so that the displaced
instruction would be executed after the patch
instructions. The breakpoint example in section
2.10 illustrates these principles.
CPU COMPONENT
CONTENT
Flags
Instruction Pointer
CS Register
OS Register
SS Register
ES Register
Queue
Clear
OOOOH
FFFFH
OOOOH
OOOOH
OOOOH
Empty
Instruction Queue Status
When configured in maximum mode, the 8086
and 8088 provide information about instruction
queue operations on lines QSO and QS 1. Table 2-5
interprets the four states that these lines can
represent.
The queue status lines are provided for external
processors that receive instructions and/or
operands via the 8086/8088 ESC (escape) instruction (see sections 2.5 and 2.8). Such a processor
may monitor the bus to see when an ESC instruction is fetched and then track the instruction
through the queue to determine when (and if) the
instruction is executed.
Note that patching a program requires machineinstruction programming and should be undertaken with considerable caution; it is easy to add
new bugs to a program in an attempt to correct
existing ones. Note also that a patch is only a temporary measure to be used in exceptional conditions. The affected code should be updated and
retranslated as soon as possible.
Table 2-5. Queue Status Signals
(Maximum Mode Only)
System Reset
as O aS 1
The 8086/8088 RESET line provides an orderly
way to start or restart an executing system. When
the processor detects the positive-going edge of a
pulse on RESET, it terminates all activities until
the signal goes low, at which time it initializes the
system as shown in table 2-4.
Since the code segment register contains FFFFH
and the instruction pointer contains OH, the processor executes its first instruction following
system reset from absolute memory location
FFFFOH. This location normally contains an
inter segment direct JMP instruction whose target
is the actual beginning of the system program.
The LOC-86 utility supplies this JMP instruction
from information in the program that identifies
its first instruction. As external (mask able) inter-
QUEUE OPERATION IN LAST
CLKCYCLE
0
0
No operation; default value
0
1
First byte of an instruction was
taken from the queue
1
0
Queue was reinitialized
1
1
Subsequent byte of an instruction
was taken from the queue
Processor Halt
When the HL T (halt) instruction (see section 2.7)
is executed, the 8086 or 8088 enters the halt state.
This condition may be interpreted as "stop all
2-29
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
operations until an external interrupt occurs or
the system is reset." No signals are floated during
the halt state, and the contentof.the.address and
data buses is undefined. A bus hold request
arriving on the HOLD line (minimum mode) or
either request! grant line (maximum mode) is
acknowledged normally while the processor is
halted.
The halt state can be used when an event prevents
the system from functioning correctly. An example might be a power-fail interrupt. After
recognizing that loss of power is imminent, the
CPU could use the remaining time to move
registers, flags and vital variables to (for example)
a battery-powered CMOS RAM area and then
halt until the return of power was signaled by an
interrupt or system reset.
Status Lines
When configured in maximum mode, the 8086
and 8088 emit eight status signals that can be used
by external devices. Lines SO, S1 and S2 identify
the type of bus cycle that the CPU is starting to
execute (table 2-6). These lines are typically
decoded by the 8288 Bus Controller. S3 and S4
indicate which segment register was used to construct the physical address being used in this bus
cycle (see table 2-7). Line S5 reflects the state of
the interrupt-enable flag. S6 is always o. S7 is a
spare line whose content is undefined.
Table 2-6. Bus Cycle Status Signals
S2
0
0
0
0
1
1
1
1
S1
TYPES OF BUS CYCLE
So
a
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
Interrupt Acknowledge
Read I/O
Write I/O
HALT
Instruction Fetch
Read Memory
Write Memory
Passive; no bus cycle
Table 2-7. Segment Register Status Lines
S4
S3
0
0
1
1
1
0
0
1
SEGMENT REGISTER
ES
SS
CSor none (I/O or Interrupt Vector)
OS
MnerT)onics © Intel, 1978
2.7 Instruction Set
The 8086 and 8088 execute exactly the same
instructions. This· instruction set includes
equivalents to the instructions typically found in
previous microprocessors, such as the 8080/8085.
Significant new operations include:
•
multiplication and division of signed and
unsigned binary numbers as well as unpacked
decimal numbers,
•
move, scan and compare operations for
strings up to 64k bytes in length,
•
•
non-destructive bit testing,
byte translation from one code to another,
•
software-generated interrupts, and
•
a group of instructions that can help
coordinate the activities of multiprocessor
systems.
These instructions treat different types· of
operands uniformly. Nearly every instruction can
operate on either byte or word data. Register,
memory and immediate operands may be
specified interchangeably.in most instructions (except, of course, that immediate values may only
serve as "source" and not "destination"
operands). In particular, memory variables can be
added tO,subtracted from, shifted, compared,
and so on, in place, without moving them in and
out of registers. This saves instructions, registers,
and execution time in assembly language programs. In high-level languages, where most
variables are memory based, compilers, such as
PL/M-86, can produce faster and shorter object
programs.
The 8086/8088 instruction set can be viewed as
existing at two levels: the assembly level and the
machine level. To the assembly language programmer, the 8086 and 8088 appear to have a
repertoire of about 100 instructions. One MOY
(move) instruction,· for example, transfers a byte
or a word from a register or a memory location or
an immediate value to either a register ora
memory location. The 8086 and 8088 CPUs,
however, recognize 28 different MOY machine
instructions ("move byte register to memory,"
"move word immediate to register," etc.). The
ASM-86 assembler translates the assembly-level
instructions written by a programmer into the
2-30
8086 AND 8088 CENTRAL PROCESS.ING UNITS
machine-level instructions that are actually executed by the 8086 or 8088. Compilers such as
PLlM-86 translate high-level language statements
directly into machine-level instructions.
The two levels of the instruction set address two
different requirements: efficiency and simplicity.
The numerous-there are about 300 in all-forms
of machine-level instructions allow these instructions to make very efficient use of storage .. For
example, the machine instruction that increments
a memory operand is three or four bytes long
because the address of the operand must be
encoded in the instruction. To increment a
register, however, does not require as much
information, so the instruction can be shorter. In
fact, the 8086 and 8088 have eight different
machine-level instnlctions that increment a different 16-bit register; these instructions are only
one byte long.
.
.
If a programmer had to write one instruction to
increment a register, another to increment a
memory variable, etc., the benefit of compact
instructions would be offset by the difficulty of
programming. The assembly-level instructions
simplify the programmer's view of the instruction
set. The programmer writes one form of the INC
(increment) instruction and the ASM-86
assembler examines the operand to determine
which machine-level instruction to generate.
This section presents the 8086/8088 instruction
set from two perspectives. First, the assemblylevel instructions are described in functional
terms. The assembly-level instructions are then
presented in a reference table that breaks out all
permissible operand combinations with execution
times and machine instruction length, plus· the
effect that tpe instruction has on the CPU flags.
Machine-level instruction encoding and decoding
.
are covered in section 4.2.
Table 2-8. Data Transfer Instructions
GENERAL PURPOSE
MOV
PUSH
POP
XCHG
XLAT
Move byte or word
Push word on.to stack
Pop word off stack
Exchange byte or word
Translate byte
INPUT /OUTPUT
IN
OUT
Input byte or word
Output byte or word
ADDRESS OBJECT
LEA
LOS
LES
Load effective address
Load pointer using OS
Load pOinter using ES
FLAG TRANSFER
LAHF
SAHF
PUSHF
POPF
Load AH register from flags
Store AH register in flags
Push flags onto stack
Pop flags off stack
General Purpose Data Transfers
MOV destination, source
MOV transfers a byte or a word from the source
operand to the destination operand.
PUSH source
PUSH decrements SP (the stack pointer) by two
and then transfers a word from the source
operand to the top of stack now pointed to by SP.
PUSH often is used to place parameters on the
stack before calling a procedure; more generally,
it is the basic means of storing temporary data on
the stack.
Data Transfer Instructions
POP destination
The 14 data transfer instructions (table 2-8) move
single bytes and words between memory and
registers as well as between register AL or AX and
110 ports. The stack manipulation instructions
are included in this group as are instructions for
transferring flag contents and for loading segment registers.
POP transfers the word at the current top of stack
(pointed to by SP) to the destination operand,
and then increments SP by two to point to the
new top of stack. POP can be used to move temporary variables from the stack to registers or
memory.
Mnemonics © Inlel. 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
XCHG destination, source
LEA destination,source
XCHG (exchange) switches the contents of the
source and destination (byte or word) operands.
When used in conjunction with the LOCK prefix,
XCHG can test and set a semaphore that controls
access to a resource shared by multiple processors
(see section 2.5).
LEA (load effective address) transfers the offset
of the source operand (rather than its value) to the
destination operand. The source operand must be
a memory operand, and the destination operand
must be a 16-bit general register. LEA does not
affect any flags. The XLAT and string instructions assume that certain registers point to
operands; LEA can be used to load these registers
(e.g., loading BX with the address of the translate
table used by the XLAT instruction).
XLAT translate-table
XLAT (translate) replaces a byte in the AL
register with a byte from a 256-byte, user-coded
translation table. Register BX is assumed to point
to the beginning of the table. The byte in AL is
used as an index into the table and is replaced by
the byte at the offset in the table corresponding to
AL's binary value. The first byte in the table has
an offset of O. For example, if AL contains 5H,
and the sixth element of the translation table contains 33H, then AL will contain 33H following
the instruction. XLAT is useful for translating
characters from one code to another, the classic
example being ASCII to EBCDIC or the reverse.
LOS destination,source
LDS (load pointer using DS) transfers a 32-bit
pointer variable from the source operand, which
must be a memory operand, to the destination
operand and register DS. The offset word of the
pointer is transferred to the destination operand,
which may be any 16-bit general register. The segment word of the pointer is transferred to register
DS. Specifying SI as the destination operand is a
convenient way to prepare to process a source
string that is not in the current data segment
(string instructions assume that the source string
is located in the current data segment and that SI
contains the offset of the string).
IN accumulator,port
IN transfers a byte or a word from an input port
to the AL register or the AX register, respectively.
The port number may be specified either with an
immediate byte constant, allowing access to ports
numbered 0 through 255, or with a number
previously placed in the DX register, allowing
variable access (by changing the value in DX) to
ports numbered from 0 through 65,535.
LES destination, source
LES (load pointer using ES) transfers a 32-bit
pointer variable from the source operand, which
must be a memory operand, to the destination
operand and register ES. The offset word of the
pointer is transferred to the destination operand,
which may be any 16-bit general register. The segment word of the pointer is transferred to register
ES. Specifying DI as the destination operand is a
convenient way to prepare to process a destination string that is not in the current extra segment.
(The destination string must be located in the
extra segment, and DI must contain the offset of
the string.)
OUT port,accumulator
OUT transfers a byte or a word from the AL
register or the AX register, respectively, to an output port. The port number may be specified either
with an immediate byte constant, allowing access
to ports numbered 0 through 255, or with a
number previously placed in register DX, allowing variable access (by changing the value in DX)
to ports numbered from 0 through 65,535.
Flag Transfers
Address Object Transfers
LAHF
These instructions manipulate the addresses of
variables rather than the contents or values of
variables. They are most useful for list process·
ing, based variables, and string operations.
Mnemonics © Intel, 1978
LAHF (load register AH from flags) copies SF,
ZF, AF, PF and CF (the 8080/8085 flags) into
bits 7, 6, 4, 2 and 0, respectively, of register AH
2-32
8086 AND 8088 CENTRAL PROCESSING UNITS
setting of TF (there is no instruction for updating
this flag directly). The change is accomplished by
pushing the flags, altering bit S of the memoryimage and then popping the flags.
(see figure 2-32). The content of bits 5, 3 and 1 is
undefined; the flags themselves are not affected.·
LAHF is provided primarily for converting
SOSO/SOS5 assembly language programs to run on
an SOS6 or SOSS.
SAHF
Arithmetic Instructions
SAHF (store register AH into flags) transfers bits
7,6,4,2 and 0 from register AH into SF, ZF, AF,
PF and CF, respectively, replacing whatever
values these flags previously had .. OF, OF, IF and
TF are not affected. This instruction is provided
for SOSO/SOS5 compatibility.
Arithmetic Data Formats
SOS6 and SOSS arithmetic operations (table 2-9)
may be performed on four types of numbers:
unsigned binary, signed binary. (integers),
unsigned packed decimal and unsigned unpacked
decimal (see table 2-10). Binary numbers may be S
or 16 bits long. Decimal numbers are stored in
bytes, two digits per byte for packed decimal and
one digit per byte for unpacked decimal. The processor always assumes that the operands specified
in arithmetic instructions contain data that represent valid numbers for the type of instruction
being performed. Invalid data may produce
unpredictable results.
PUSHF
PUSHF decrements SP (the stack pointer) by two
and then transfers all flags to the word at the top
of stack pointed to by SP (see figure 2-32). The
flags themselves are not affected.
POPF
,
. '
,
Table 2-9. Arithmetic Instructions
POPF transfers specific bits from the word at the
current top of stack (pointed to by register SP)
into the SOS6/S0SS flags, replacing whatever
values the flags previously contained (see figure
2-32). SP is then incremented by two to point to
the new top of stack. PUSHFandPOPF allow a
procedure to save and restore a calling program's
flags. They also allow a program to change the
ADDITION
ADD
ADC
INC
AAA
DAA
Add byte orword
Add byte or word with carry
Increment byte or word by 1
ASCII adjustfor addition
Decimal adjust for addition
SUB
SBB
DEC
NEG
CMP
AAS
DAS
Subtract byte or word
Subtract byte or word with
borrow
Decrement byte or word by 1
Negate byte or word
Compare byte or word
ASCII adjust for subtraction
Decimal adjust for subtraction
MUL
IMUL
AAM
Multiply byte or word unsigned
Integer multiply byte or word
ASCII adjust for multiply
DIV
IDIV
AAD
CBW
CWO
Divide byte or word unsigned
Integer divide byte or word
ASCII adjust for division
Convert byte to word
Convert word to doubleword
SUBTRACTION
LAHF,
,SAHF
I5
I
J Z ,u I.A I U , P , U ,c
(76543210(
1_8080/8085 FLAGS_I
I
I
I
I
~g~~F 'I U I U I U I U I 0 I D I
I I TIS I Z I U I A I U I P I U I C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
MULTIPLICATION
U = UNDEFINED;VALUE IS INDETERMINATE·
o = OVERFLOW FLAG
D=
I.
T =
5=
Z
A=
P=
C=
DIRECTION FLAG
=INTERRUPT
ENABLE FLA.G
TRAP FLAG
DIVISION
SIGN FLAG
=ZERO
FLAG
AUXILIARY CARRY FLAG
PARITY FLAG
CARRY FLAG
Figure 2-32. Fhlg Storage Formats
2-33
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-10. Arithmetic Interpretation of 8-BitNumbers
HEX
BIT PATTERN
UNSIGNED
BINARY
SIGNED
BINARY
UNPACKED
DECIMAL
PACKED
DECIMAL
+7
7
7
07
00000111
7
89
10001001
137
-119
invalid
89
C5
11000101
197
-59
invalid
invalid
Unsigned binary numbers may be either 80r 16
bits long; all bits are considered in determining a
number's magnitude. The value range of an 8-bit
unsigned binary number is ·0-255; 16 bits can
represent values from 0 through 65,535. Addition, subtraction, multiplication and division
operations are available for unsigned binary
numbers.
Unpacked decimal numbers are stored as unsigned byte quantities. The magnitude of the
number is determined from the low-order halfbyte; hexadecimal values 0-9 are valid and are
interpreted as decimal numbers. The high-order
half-byte must be zero for multiplication and division; it may contain any value for addition and
subtraction. Arithmetic on unpacked decimal
numbers is performed intwo steps. The unsigned
binary addition, subtraction and multiplication
operations are used to produce an intermediate
result in register AL. An adjustment instruction
then changes the value in AL to a final correct
unpacked decimal number. Division is performed
similarly, except that the adjustment is carried out
on the numerator operand in register AL first,
then a following unsigned binary division instruction produces a correct result.
Signed binary numbers (integers) may be either 8
or 16 bits long. The high-order (leftmost) bit is
interpreted as the number's sign: 0 = positive and
1 = negative. Negative numbers are represented
in standard two's complement notation. Since
the high-order bit is used for a sign, the range of
a.n 8-bit integer is ""'"128 through + 127; 16-bit
integers may range. from -32,768 through
+32,767. The value zero has a positive sign.
Multiplication and division operations are provided for signed binary numbers. Addition and
subtraction are performed with the unsigned
binary instructions. Conditional jump instructions, as well as an "interrupt on overflow"
instruction, can be used following an unsigned
operation on an integer to detect overflow into
the sign bit.
Unpacked decimal numbers are similar to the
ASClIcharacter representations of the digitsO-9.
Note, however, that the high-order half-byte of
an ASCII numeral is always 3H. Unpacked
decimal arithmetic may be performed on ASCII
numeric characters under the following
conditions:
Packed decimal numbers are stored as unsigned
byte quantities. The byte is treated as having one
decimal digit in each half-byte (nibble); the digit
in the high-order half-byte is the most significant.
Hexadecimal values 0-9 are valid in each half~
byte, and the range of a packed decimal number is
0-99. Addition and subtraction are performed iIi
two steps. First an unsigned binary instruction is
used to produce an intermediate result in register
AL. Thenan adjustment operation is performed
which changes the· intermediate value in AL to a
final correct packed decimal result. Multiplica.;
tion and division adjustments are not available
for packed decimal numbers.
Mnemonics © Intel, 1978
•
the high-order half-byte of an ASCII
numeral must be set to OH prior to
multiplication or division.
•
unpacked decimal arithmetic leaves the
high-order half-byte set to OH; it must be set
to 3H to produce a valid ASCII numeral.
Arithmetic Instructions and Flags
The 8086/8088 arithmetic instructions post certain characteristics of the result of the operation
to six flags. Most of these flags can be tested by
following the arithmetic instruction with a conditional jump instruction; the INTO (interrupt on
overflow) instruction also may be used. The
2-34
8086 AND 8088 CENTRAL PROCESSING UNITS
various instructions affect the flags differently, as
explained in the instruction descriptions.
However, they follow these general rules:
•
•
•
•
•
•
CF (carry flag): If an addition results in a
carry out of the high-order bit of the result,
then CF is set; otherwise CF is cleared. If a
subtraction results in a borrow into the highorder bit of the result, then CF is set; otherwise CF is cleared. Note that a signed carry is
indicated by CF '" OF. CF can be used to
detect an unsigned overflow. Two instructions, ADC (add with carry) and SBB (subtract with borrow), incorporate the carry flag
in their operations and can be used to perform multibyte (e.g., 32-bit, 64-bit) addition
and subtraction.
OF (overflow flag): If the result of an
operation is too large a positive number, or
too small a negative number to fit in the
destination operand (excluding the sign bit),
then OF is set; otherwise OF is cleared. OF
thus indicates signed arithmetic overflow; it
can be tested with a conditional jump or the
INTO (interrupt on overflow) instruction.
OF may be ignored when performing
unsigned arithmetic.
Addition
ADD destination,source
The sum of the two operands, which may be bytes
or words, replaces the destination operand. Both
operands may be signed or unsigned binary
numbers (see AAA and DAA). ADD updates AF,
CF, OF, PF, SF and ZF.
AF (auxiliary carry flag): If an addition
results in a carry out of the low-order halfbyte of the result, then AF is set; otherwise
AF is cleared. If a subtraction results in a
borrow into the low-order half-byte of the
result, then AF is set; otherwise AF is
cleared. The auxiliary carry flag is provided
for the decimal adjust instructions and
ordinarily is not used for any other purpose.
ADC destination, source
ADC (Add with Carry) sums the operands, which
may be bytes or words, adds one if CF is set and
replaces the destination operand with the result.
Both operands may be signed or unsigned binary
numbers (see AAA and DAA). ADC updates AF,
CF, OF, PF, SF and ZF. Since ADC incorporates
a carry from a previous operation, it can be used
to write routines to add numbers longer than 16
bits.
SF (sign flag): Arithmetic and logical
instructions set the sign flag equal to the
high-order bit (bit 7 or 15) of the result. For
signed binary numbers, the sign flag will be 0
for positive results and 1 for negative results
(so long as overflow does not occur). A conditional jump instruction can be used following addition or subtraction to alter the flow
of the program depending on the sign of the
result. Programs performing unsigned opera~
tions typically ignore SF since the high-order
bit of the result is interpreted as a digit rather
than a sign.
INC destination
INC (Increment) adds one to the destination
operand. The operand may be a byte or a word
and is treated as an unsigned binary number (see
AAA and DAA). INC updates AF, OF, PF, SF
and ZF; it does not affect CF.
ZF (zero flag): If the result of an arithmetic
or logical operation is zero, then ZF is set;
otherwise ZF is cleared. A conditional jump
instruction can be used to alter the flow of
the program if the result is or is not zero.
PF (parity flag): If the low-order eight bits of
an arithmetic or logical result contain an
even number of I-bits, then the parity flag is
set; otherwise it is cleared. PF is provided for
8080/8085 compatibility; it also can be used
to check ASCII characters for correct parity.
AAA
AAA (ASCII Adjust for Addition) changes the
contents of register AL to a valid unpacked
decimal number; the high-order half-byte is
zeroed. AAA updates AF and CF; the content of
OF, PF, SF and ZF is undefined following execution of AAA.
2-35
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
DAA
-32,768 causes no change to the operand and sets
OF. NEG updates AF, CF, OF, PF, SF and ZF.
CF is always set except when the operand is zero,
in which case it is cleared.
DAA (Decimal Adjust for. Addition) corrects the
result of previously, adding two valid packed
decimal operands (the destination operand must
have been registerAL). DAA changes the content
of AL to a pair of valid packed decimal digits. It
updatesAF, CF, PF, SF and ZF; the content of
OF is undefined following execution of DAA.
CMP destination, source
CMP (Compare) subtracts the source from the
destination, which may be bytes or words, but
does not return the result. The operands are
unchanged, but the flags are updated and can be
tested by a subsequent conditional jump instruction. CMP updates AF, CF, OF, PF, SF and ZF.
The comparison reflected in the flags is that of the
destination to the source. If a CMP instruction is
followed by a JG (jump if greater) instruction, for
example, the jump is taken if the destination
operand is greater than the source operand.
Subtraction
SUB destination,source
The source operand is ~ubtracted from the
destination operand, and the result replaces the
destination operand. The operands may be bytes
or words. Both operands may be ·signed or
unsigned binary numbers (see AAS and DAS).
SUB updates AF, CF ,OF, PF, SF and ZF.
AAS
AAS (ASCII Adjust for Subtraction) corrects the
result of a previous subtraction of two valid
unpacked decimal operands (the destination
operand must have been specified as register AL).
AAS changes the content of AL to a valid
unpacked decimal number; the high-order halfbyte is zeroed. AAS updates AF and CF; the content of OF, PF, SF and ZF is undefined following
execution of AAs.
SBB destination, source
SBB (Subtract with Borrow) subtracts the source
frbm the destination, subtracts one if CF is set,
and returns the result to the destination operand.
Both operands maybe bytes or 'words. Both
operands may be signed or unsigned binary
numbers (see AAS and DAS). SBB updates AF,
CF, OF, PF, SF and ZF. Since it incorporates a
borrow from a previous operation, SBB'may be
used to write routines that subtract numbers
longer than 16 bits.
DAS
DAS (Decimal Adjust for Subtraction)' corrects
the res.ult of a previous subtraction of two valid
packed decimal operands (the destination
operand must have been specified as register AL).
DAS changes the content of AL to a pair of valid
packed decimal digits. DAS updatesAF, eF, PF,
SF and ZF; the content of OF is undefined
following execution of DAS.
DEC destination
DEC (Decrement) subtracts one from the destination, which may ,be a byte or a word. DEC
updates AF, OF, PF, SF, and ZF; it does not
affect CF.
NEG destination
Multiplication
NEG (Negate) subtracts the destination operand,
which may be a· byte or a word, from 0 and
returns the result to the destination.' This forms
the two's complement of the number, effectively
reversing the sign of an integer. Iftheoperand is
zero, its sign is not changed. Attempting to negate
a byte containing -128 or a word containing
Mnemonics © Intel, 1978
MULsource
MUL (Multiply) performs an unsigned multiplication of the source operand and the
accumulator. If the source is a byte, then it is
mUltiplied by register. AL, 'and the double-length
2-36
8086 AND 8088 CENTRAL PROCESSING UNITS
divided into the double-length dividend assumed
to be in registers AL and AH. The single-length
quotient is returned in AL, and the single-length
remainder is returned in AH. If the source
operand is a word, it is divided into the doublelength dividend in registers AX and DX. The
single-length quotient is returned in AX, and the
single-length remainder is returned in DX. If the
quotient exceeds the capacity of its destination
register (FFH for byte source, FFFFFH for word
source), as when division by zero is attempted, a
type 0 interrupt is generated, and the quotient and
remainder are undefined. Nonintegral quotients
are truncated to integers. The content of AF, CF,
OF, PF, SF and ZF is undefined following execution of DlV.
result is returned in AH and AL. If the source
operand is a word, then it is multiplied by register
AX, and the double-length result is returned in
registers DX and AX. The operands are treated as
unsigned binary numbers (see AAM). If the upper
half of the result (AH for byte source, DX for
word source) is nonzero, CF and OF are set;
otherwise they are cleared. When CF and OF are
set, they indicate that AH or DX contains significant digits of the result. The content of AF, PF,
SF and ZF is undefined following execution of
MUL.
lMULsource
IMUL (Integer Multiply) performs a signed
multiplication of the source operand and the
accumulator. If the source is a byte, then it is
multiplied by register AL, and the double-length
result is returned in AH and AL. If the source is a
word, then it is multiplied by register AX, and the
double-length result is returned in registers DX
and AX. If the upper half of the result (AH for
byte source, DX for word source) is not the sign
extension of the lower half of the result, CF and
OF are set; otherwise they are cleared. When CF
and OF are set, they indicate that AH or DX contains significant digits of the result. The content
of AF, PF, SF and ZF is undefined following
execution of IMUL.
IDIV source
IDIV (Integer Divide) performs a signed division
of the accumulator (and its extension) by the
source operand. If the source operand is a byte, it
is divided into the double-length dividend
assumed to be in registers AL and AH; the singlelength quotient is returned in AL, and the singlelength remainder is returned in AH. For byte integer division, the maximum positive quotient is
+ 127 (7FH) and the minimum negative quotient is
-127 (81H). If the source operand is a word, it is
divided into the double-length dividend in
registers AX and DX; the single-length quotient is
returned in AX, and the single-length remainder
is returned in DX. For word integer division, the
maximum positive quotient is +32,767 (7FFFH)
and the minimum negative quotient is -32,767
(8001H). If the quotient is positive and exceeds
the maximum, or is negative and is less than the
minimum, the quotient and remainder are
undefined, and a type 0 interrupt is generated. In
particular, this occurs if division by 0 is
attempted. Nonintegral quotients are truncated
(toward 0) to integers, and the remainder has the
same sign as the dividend. The content of AF,
CF, OF, PF, SF and ZF is undefined following
IDIV.
AAM
AAM (ASCII Adjust for Multiply) corrects the
result of a previous multiplication of two valid
unpacked decimal operands. A valid 2-digit
unpacked decimal number is derived from the
content of AH and AL and is returned to AH and
AL. The high-order half-bytes of the multiplied
operands must have been OH for AAM to produce a correct result. AAM updates PF, SF and
ZF; the content of AF, CF and OF is undefined
following execution of AAM.
Division
AAD
DIV source
AAD (ASCII Adjust for Division) modifies the
numerator in AL before dividing two valid
unpacked decimal operands so that the quotient
produced by the division will bea valid unpacked
decimal number. AH must be zero for the subse-
DlV (divide) performs an unsigned division of the
accumulator (and its extension) by the source
operand. If the source operand is a byte, it is
2-37
Mnemonics © Intel, 1978
8086 AND 8088 CENTRALPROCESSING UNITS
Logical
quentDIV to produce the correct result. The quotient is returned in AL, and the remainder is
returned in AH; both high-order half-bytes are
zeroed. AAD updates PF, SF and ZF; the content
of AF, CF and OF is undefined following execution of AAD.
The logical instructions. include the boolean
operators "not," "and," "inclusive or," and
"exclusive or," plus a TEST instruction that sets
the flags, but does not alter either of its operands.
CBW
AND, OR, XOR and TEST affect the flags as
follows: The overflow (OF) and carry (CF) flags
are always cleared by logical instructions, and the
content of the auxiliary carry (AF) flag is· always
undefined following execution of a logical
instruction. The sign (SF), zero (ZF) and parity
(PF) flags are always posted to reflect the result of
the operation and can be tested by conditional
jump instructions. The interpretation of these
flags is the same as for arithmetic instructions. SF
is set if the result is negative (high-order bit is I),
and is cleared if the result is positive (high-order
bit is 0). ZF is set if the result is zero, cleared
otherwise. PF is set if the result contains an even
number of I-bits (has even parity) and is cleared if
the number of I-bits is odd (the result has odd
parity). Note that NOT has no effect on the flags.
CBW (Convert Byte to Word) extends the sign of
the byte in register AL throughout register AH.
CBW does not affect any flags. CBW can be used
to produce a double-length (word) dividend from
a byte priorto performing byte division.
CWD
CWD (Convert Word to Doubleword) extends the
sign of the word in register AX throughout
register DX. CWD does not affect any flags.
CWD can be used to produce a double-length
(doubleword) dividend from a word prior to performing word division.
Bit Manipulation Instructions
NOT destination
The 8086 and 8088 provide three groups of
instructions (table 2-11) for manipulating bits
within both bytes and words: logical, shifts and
rotates.
NOT inverts the bits (forms the one's complement) of the byte or word operand.
AND destination, source
Table 2-11. Bit Manipulation Instructions
AND performs the logical "and" of the two
operands (byte or word) and returns the result to
the destination operand. A bit in the result is set if
both corresponding bits of the original operands
are set; otherwise the bit is cleared.
LOGICALS
NOT
AND
OR
XOR
TEST
"Not" byte or word
"And" byte or word
"Inclusive or" byte or word
"Exclusive or" byte or word
"Test" byte or word
OR destination,source
SHIFTS
SHLISAL
SHR
SAR
ROL
ROR
RCL
RCR
Shift logical! arithmetic left
byte or word
Shift logical right byte or word
Shift arithmetic right byte or
word
OR performs the logical "inclusive or" of the two
operands (byte or word) and returns the result to
the destination operand. A bit in the result is set if
either or both corresponding bits in the original
operands are set; otherwise the result bit is
cleared.
ROTATES
Rotate left byte or word
Rotate right byte or word
Rotate through carry left byte
or word
Rotate through carry right byte
orword
Mnemonics © Intel, 1978
XOR destination, source
XOR (Exclusive Or) performs the logical "exclusive .or" of the two operands and returns the
result to the destination operand. A bit in the
2-38
8086 AND 8088 CENTRAL PROCESSING UNITS
result is set if the corresponding bits of the
original operands contain opposite values (one is
set, the other is cleared); otherwise the result bit is
cleared.
the number of bits specified in the count operand.
Zeros are shifted in on the left. If the sign bit
retains its original value, then OF is cleared.
TEST destination,source
SAR destination, count
SAR (Shift Arithmetic Right) shifts the bits in the
destination operand (byte or word) to the right by
the number of bits specified in the count operand.
Bits equal to the original high-order (sign) bit are
shifted in on the left, preserving the sign of the
original value. Note that SAR does not produce
the same result as the dividend of an
"equivalent" IDIV instruction if the destination
operand is negative and l-bits are shifted out. For
example, shifting -5 right by one bit yields -3,
while integer division of -5 by 2 yields -2. The
difference in the instructions is that IDIV truncates all numbers toward zero, while SAR truncates positive numbers toward zero and negative
numbers toward negative infinity.
TEST performs the logical "and" of the two
operands (byte or word), updates the flags, but
does not return the result, Le., neither operand is
changed. If a TEST instruction is followed by a
JNZ (jump if not zero) instruction, the jump will
be taken if there are any corresponding l-bits in
both operands.
Shifts
The bits in bytes and words may be shifted
arithmetically or logically. Up to 255 shifts may
be performed, according to the value of the count
operand coded in the instruction. The count may
be specified as the constant l, or as register CL,
allowing the shift count to be a variable supplied
at execution time. Arithmetic shifts may be used
to multiply and divide binary numbers by powers
of two (see note in description of SAR). Logical
shifts can be used to isolate bits in bytes or words.
Rotates
Bits in bytes and words also may be rotated. Bits
rotated out of an operand are not lost as in a
shift, but are "circled" back into the other "end"
of the operand. As in the shift instructions, the
number of bits to be rotated is taken from the
count operand, which may specify either a constant of l, or the CL register. The carry flag may
act as an extension of the operand in two of the
rotate instructions, allowing a bit to be isolated in
CF and then tested by a JC (jump if carry) or JNC
(jump if not carry) instruction.
Shift instructions affect the flags as follows. AF is
always undefined following a shift operation. PF,
SF and ZF are updated normally, as in the logical
instructions. CF always contains the value of the
last bit shifted out of the destination operand.
The content of OF is always undefined following
a multibit shift. In a single-bit shift, OF is set if
the value of the high-order (sign) bit was changed
by the operation; if the sign bit retains its original
value, OF is cleared.
SHL/SAL destination, count
Rotates affect only the carry and overflow flags.
CF always contains the value of the last bit
rotated out. On multibit rotates, the value of OF
is always undefined. In single-bit rotates, OF is
set if the operation changes the high-order (sign)
bit of the destination operand. If the sign bit
retains its original value, OF is cleared.
SHL and SAL (Shift Logical Left and Shift
Arithmetic Left) perform the same operation and
are physically the same instruction. The destination byte or word is shifted left by the number of
bits specified in the count operand. Zeros are
shifted in on the right. If the sign bit retains its
original value, then OF is cleared.
ROL destination, count
SHR destination, source
ROL (Rotate Left) rotates the destination byte or
word left by the number of bits specified in the
count operand.
SHR (Shift Logical Right) shifts the bits in the
destination operand (byte or word) to the right by
2-39
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
ROR destination, count
operands to determine if the elements of the
strings are bytes or words. The assembler does
not, however, use the operand names to address
the strings. Rather, the content of register Sl
(source index) is used as an offset to address the
current element of the source string, and the content of register DI (destination index) is taken as
the offset of the current destination string element. These registers must be initialized to point
to the source/destination strings before executing
the string instruction; the LDS, LES and LEA
instructions are useful in this regard.
ROR (Rotate Right) operates similar to ROL
except that the bits in the destination byte or word
are rotated right instead of left.
RCL destination,count
RCL(Rotate through Carry Left) rotates the bits
in the byte or word destination operand to the left
by the number of bits specified in the count
operand. The carry flag (CF) is treated as "part
of" the destination operand; that is, its value is
rotated into the low-order bit of the destination,
and itself is replaced by the high-order bit of the
destination.
Table 2-12. String Instructions
RCR destination, count
RCR (Rotate through Carry Right) operates
exactly like RCL except that the bits are rotated
right instead of left.
String Instructions
Five basic string operations, called primitives,
allow strings of bytes or words to be operated on,
one element (byte or word) at a time. Strings of
up to 64k bytes may be manipulated with these
instructions. Instructions are available to move,
compare and scan for a value, as well as for.moving string elements to and from the accumulator
(see table 2-12). These basic operations may be
preceded by a special one-byte prefix that causes
the instruction to be repeated by the hardware,
allowing long strings to be processed much faster
than would be possible with a software loop. The
repetitions can be terminated by a variety of conditions, and a repeated operation may be interrupted and resumed.
Repeat
REPE/REPZ
Repeat wh ile eq uall zero
REPNE/REPNZ
Repeat while not
equal I not zero
MOVS
Move byte or word string
MOVSB/MOVSW
Move byte or word string
CMPS
Compare byte or word
string
SCAS
Scan byte or word string
LODS
Load byte or word string
STOS
Store byte or word string
Table 2-13. String Instruction Register and
Flag Use .
The string instructions operate quite similarly in
many respects; the common characteristics are
covered here and in table 2-13 and figure 2-33
rather than in the descriptions of the individual
instructions. A string instruction may have a
source operand, a destination operand, or both.
The hardware assumes that a source string resides
in the current data segment; a segment prefix byte
may be used to override this assumption. A
destination string must be in the current extra segment. The assembler checks the attributes of the
Mnemonics © Intel, 1978
REP
2-40
SI
Index (offset) for source string
DI
Index (offset) for destination
string
CX
Repetition counter
ALiAX
Scan value
Destination for LODS
Source for STOS
DF
0= auto-increment SI, DI
1 = auto-decrement SI, DI
ZF
Scan I compare terminator
8086 AND 8088 CENTRAL PROCESSING UNITS
SI/DI,CX
{ AND OF WOULD
TYPICALLY BE
INITIALIZED HERE
DECREMENT
CX BY 1
STRING
OF
DELTA
BYTE
BYTE
WORD
WORD
0
1
0
1
1
-1
2
-2
PREFIX
Z
REPE
REPZ
REPNE
REPNZ
0
0
1
1
PRESENT
I-----l
INST~~~~ION I
L _____ J
I
Figure 2-33. String Operation Flow
2-41
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
The string instructions automatically update SI
and/or DI in anticipation of processing the next
- string element. The setting of DF (the direction
flag) determines whether the index registers are
auto-incremented (DF = 0) or auto-decremented
(DF = I). If byte strings are being processed, SI
and/ or DI is adjusted by!; the adjustment is 2 for
word strings.
if a second or third prefix (Le., segment override
or LOCK) has been specified in addition to any of
the repeat prefixes. The processor "remembers"
only one prefix in effect at the time of the interrupt, the prefix that immediately precedes the
string instruction. After returning from the interrupt, processing resumes at this point, but any
additional prefixes specified are not in effect. If
more than one prefix must be used with a string
instruction, interrupts may be disabled for the
duration of the repeated execution. However, this
will not prevent a non-maskable interrupt from
being. recognized. Also, the time that the system is
unable to respond to interrupts may be unacceptable iflong strings are being processed.
If a Repeat prefix has been coded, then register
CX (count register) is decremented by 1 after each
repetition of the string instruction; therefore, CX
must be initialized to the number of repetitions
desired before the string instruction is executed. If
CX is 0, the string instruction is not executed, and
control goes to the following instruction.
Section 2.10 contains examples that illustrate the
use of all the string instructions.
MOVS destination-string, source-string
MOVS (Move String) transfers a byte or a word
from the source string (addressed by SI) to the
destination string (addressed by DI) and updates
SI and DI to point to the next string element.
When used in conjunction with REP, MOVS performs a memory-to-memory block transfer.
REP/REPE/REPZ/REPNE/REPNZ
Repeat, Repeat While Equal, Repeat While Zero,
Repeat While Not Equal and Repeat While Not
Zero are five mnemonics for two forms of the
prefix byte that controls repetition ofa subsequent string instruction. The different mnemonics
are provided to improve program clarity. The
repeat prefixes do not affect the flags.
MOVSB/MOVSW
These are alternate mnemonics for the move
string instruction. These mnemonics are coded
without operands; they explicitly tell the
assembler that a byte string (MOVSB) or a word
string (MOVSW) is to be moved (when MOVS is
coded, the assembler determines the string type
from the attributes of the operands). These
mnemonics are useful when the assembler cannot
determine the attributes of a string, e.g., a section
of code is being moved.
REP is used in conjunction with the MOVS
(Move String) and STOS (Store String) instructions and is interpreted as "repeat while not endof-string" (CX not 0). REPE and REPZ operate
identically and are physically the same prefix byte
as REP. These instructions are used with the
CMPS (Compare String) and SCAS (Scan String)
instructions and require ZF (posted by these
instructions) to be set before initiating the next
repetition. REPNE and REPNZ. are two
mnemonics for the same prefix byte. These
instructions function the same as REPE and
REPZ except that the zero flag must be cleared or
the repetition is terminated. Note that ZF does
not need to be initialized before executing the
repeated string instruction.
CMPS destination-string, source-string
CMPS (Compare String) subtracts the destination
byte or word (addressed by DI) from the source
byte or word (addressed by SI). CMPS affects the
flags but does not alter either operand, updates SI
and DI to point to the next string element and
updates AF, CF, OF, PF, SF and ZF to reflect the
relationship of the destination element to the
source element. For example, if a JG (Jump if
Greater) instruction follows CMPS, the jump is
taken if the destination element is greater than the
source element. If CMPS is prefixed with REPE
Repeated string sequences are interruptable; the
processor will recognize the interrupt before processing the next string element. System interrupt
processing is not affected in any way. Upon
return from the interrupt, the repeated operation
is resumed from the point of interruption. Note,
however, that execution does not resume properly
MnemoniCS © Inlel,1978
2-42
8086 AND 8088 CENTRAL PROCESSING UNITS
or REPZ, the operation is interpreted as "compare while not end-of-string (CX not zero) and
strings are equal (ZF = 1)." If CMPS is preceded
by REPNE or REPNZ, the operation is interpreted as "compare while not end-of-string (CX
not zero) and strings are not equal (ZF = 0)."
Thus, CMPS can be used. to find matching or differing string elements.
Program Transfer Instructions
The sequence of execution of instructions in an
8086/8088 program is determined by the content
of the code segment register (CS) and the instruction pointer (IP). The. CS register contains the
base address of the current code segment, the 64k
portion of memory from which instructions are
presently being fetched. The IP is used as an offset from the beginning of the code segment; the
combination of CS and IP points to the memory
location from which the. next instruction is to be
fetched. (Recall that under most operating conditions, the next instruction to be executed has
already been fetched from memory and is waiting
in the CPU instruction queue.) The program
transfer instructions operate on the instruction
pointer and on the CS register; changing the con~
tent of these causes normal sequential execution
to be altered. When a program transfer occurs,
the queue no longer contains the correct instruction, and the BIU obtains the next instruction
from memory using the new IP and CS values,
passes the instruction directly to the EU, and then
begins refilling the queue from the new location.
SCAS destination-string
SCAS (Scan String) subtracts the destination
string element (byte or word) addressed by DI
from the content of AL (byte string)or AX (word
string) and updates the flags, but does not alter
the destination string or the accumulator. SCAS
also updates DI to point to the next string element
and AF, CF, OF, PF, SF and ZF to reflect the
relationship of the scan value in ALI AX to the
string element. If SCASis prefixed with REPE or
REPZ, the operation is interpreted as "scan while
not end-of-string (CX not 0) and string-element =
scan-value (ZF = 1)." This form may be used to
scan for departure from a given value. If SCAS is
prefixed with REPNE or REPNZ, the operation
is interpreted as "scan while not end-of-string
(CX not 0) and string-element is not equal to
scan-value (ZF = 0)." This form may be used to
locate a value in a string.
Four groups of program transfers are available in
the 8086/8088 (see table 2-14): unconditional
transfers, conditional transfers, iteration control
instructions and interrupt-related instructions.
Only the interrupt-related instructions affect any
CPU flags. As will be seen, however, the execution of many of the program transfer instructions
is affected by the states of the flags.
LODS source-string
LODS (Load String) transfers the byte or word
string element addressed by SI to register AL or
AX, and updates SI to point to the next element
in the string. This instruction is not ordinarily
repeated since the accumulator would be overwritten by each repetition, and only the last element would be retained. However, LODS is very
useful in software loops as part of a more complex string function built up from string
primitives and other instructions.
Unconditional Transfers.
The unconditional transfer instructions may
transfer control to a target instruction within the
current code segment (intrasegment transfer) or
to a different code segment (intersegment
transfer). (The ASM-86 assembler terms an
intrasegment target NEAR and an intersegment
target FAR.) The transfer is made unconditionally any time the instruction is executed.
STOS destination-string
CALL procedure-name
STOS (Store String) transfers a byte or word from
registerAL or AX to the string element addressed
by DI and updates DI topoint to the next location
in the string. As a repeated operation, STOS provides a convenient way to initialize a string to a
constant value (e.g., to blank out a print line).
CALL activates an out-of-line procedure, saving
information on the stack to permit a RET (return)
instruction in the procedure to transfer control
back to the instruction following the CALL. The
2-43
Mnemonics ('lintel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
assemblergenerates'.a.'different"type of CALL
instruction. depending on whether the. programmerhasdeflned·fhe procedure name as NEAR or
FAR. For control toteturn properly,the type of
CALL instruction must match the type of RET
instruction that exits from the proc.edure. (The
potential .fotamismatchexists if the procedure
and the CALL are contained in separately
assembled programs.) Different forms of the
CALL instruction allow the addtess of the target
procedure to be obtai~ed from. the. instructipp
itself (direct CALL) or from a memory location
or. register referenced. by. the instruction (indirect
CALL), In the following descriptions, bear.ill
mind that the pro,'iessor automatically8.djusts II'
to point to .thenext instruction to be executed
before saving it onthi!stack.
.,
'
Table 2-14. Program Transfer Instructions'
UNCOND.ITIONAL TRANSFERS
CALL
RET
JMP
Call procedure
Return from procedure '.
Jump
CONDITIONAL TRANSFERS
Jump if above/not below
nor equal
Jump if above or
equal/not below
Jump if below/not above
nor equal
Jump if below or
equal! not above
Jump if carry .
Jump if equal/zero
Jump if greater/not less
norequal'
JiJmp if greater or '
equal/not less' .
Jump if less/not greater
nor equal
Jump if lessor equal/not
greater
Jumpif not carry·
Jumpif not equal/not
zero'
Jump if not overflow
Jump if not parity/parity
odd
Jump if not sign
Jump if overflow
Jump if parity/parity"
even
Jump if sign
JA/JNBE'
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JLlJNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS
For an intrasegmentdirec~CAU~; SP ,(the. sta~k
pointer) is decremented by two. and. IP is pushed
onto the stack,The relative displacement (up to
±32k) of the target procedure. from. the CALL
instruction is then· added to': the instruction
pointer. This forI!1.' of the CALL instruction is
"self-relative" and is appropriate for position- independent (dynamically.relocatable) routiIies in
which the .. CALL aIld its target.arein. the ,same
segmeIlt and are moved together. .
.
A.n intrasegment indirect CALL may bi! .tTI,~de
through memory or through a register. SP is
decremented by two and IP is pushed onto the
stack. The offset of the target procedure is
obtained from the memory word or 16-bit general
register referenced in the instruction and replaces
IP.
' .
. ...
....,....
For an intersegmertt direct CALL; ;'SPis
decremented by two, and CS is pushed onto the
stack.CS is replaced by' the segment word' contained in the instruction. SP again'is decremented
by two. IP is pushed ()nto the stack and is
replaced by the offset wordcontairied in the
instruction.
' .
ITERATION CONTROLS
LOOP
Loop
LOOPE/LOOPZ
Loop if equal/zero
LOOPNE/LOOPNZ Loop if not equal/ not
zero
JCXZ
Jump if register CX = 0
For an inter segment indirect CALL (which only
may be made through memory), SP is
decremented by two, and'CS is pushed onto the
stack. CS is then replaced by the content of the
second word of the doubleword memory pointer
referenced by the. instruction. SP again is
decremented by ,two,. and IP ; is pushed onto the
stack and is replaced bY.the conteniof the first
word· of the.doubleword pointer referenc.ed. by the
instruction .. '
.', ;., '
.. '
INTERRUPTS
INT
INTO
IRET
Mnemonics © intel, 1978
Interrupt
Interrupt if overflOW
Interrupt return
2-44
8086 AND 8088 CENTRAL PROCESSING UNITS
RET optional-pap-value
An intersegment indirect JMP may be made only
through memory. The first word of the
doubleword pointer referenced by the instruction
replaces IP, and the second word replaces CS.
RET (Return) transfers control from a procedure
back to the instruction following the CALL that
activated the procedure. The assembler generates
an intrasegment RET if the programmer has
defined the procedure NEAR, or an intersegment
RET if the procedure has been defined as FAR.
RET pops the word at the top of the stack
(pointed to by register SP) into the instruction
pointer and increments SP by two. If RET is
intersegment, the word at the new top of stack is
popped into the CS register, and SP is again
incremented by two. If an optional pop value has
been specified, RET adds that value to SP. This
feature may be used to discard parameters pushed
onto the stack before the execution of the CALL
instruction.
Conditional Transfers
The conditional transfer instructions are jumps
that mayor may not transfer control depending
on the state of the CPU flags at the time the
instruction is executed. These 18 instructions (see
table 2-15) each test a different combination of
flags for a condition. If the condition is "true,"
then control is transferred to the target specified
in the instruction. If the condition is "false,"
then control passes to the instruction that follows
the conditional jump. All conditional jumps are
SHORT, that is, the target must be in the current
code segment and within -128 to +127 bytes of
the first byte of the next instruction (JMP OOH
jumps to the first byte of the next instruction).
Since the jump is made by adding the relative
displacement of the target to the instruction
pointer, all conditional jumps are self-relative and
are appropriate for position-independent
routines.
JMP target
JMP unconditionally transfers control to the
target location. Unlike a CALL instruction, JMP
does not save any information on the stack, and
no return to the instruction following the JMP is
expected. Like CALL, the address of the target
operand may be obtained from the instruction
itself (direct JMP) or from memory or a register
referenced by the instruction (indirect JMP).
Iteration Control
An intrasegment direct JMP changes the instruction pointer by adding the relative displacement
of the target from the JMP instruction. If the
assembler can determine that the target is within
127 bytes of the JMP, it automatically generates a
two-byte form of this instruction called a SHORT
JMP; otherwise, it generates a NEAR JMP that
can address a target within ±32k. Intrasegment
direct JMPS are self-relative and are appropriate
in position-independent (dynamically relocatable)
routines in which the JMP and its target are in the
same segment and are moved together.
The iteration control instructions can be used to
regulate the repetition of software loops. These
instructions use the CX register as a counter. Like
the conditional transfers, the iteration control
instructions are self-relative and may only
transfer to targets that are within -128 to + 127
bytes of themselves, i.e., they are SHORT
transfers.
LOOP short-label
LOOP decrements CX by 1 and transfers control
to the target operand if ex is not 0; otherwise the
instruction following LOOP is executed.
An intrasegment indirect JMP may be made
either through memory or through a 16-bit
general register. In the first case, the content of
the word referenced by the instruction replaces
the instruction pointer. In the second case, the
new IP value is taken from the register named in
the instruction.
LOOPE/LOOPZ short-label
LOOPE and LOOPZ (Loop While Equal and
Loop While Zero) are different mnemonics for
the same instruction (similar to the REPE and
An intersegment direct JMP replaces IP and CS
with values contained in the instruction.
2-45
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-15. Interpretation of Conditional Transfers
MNEMONIC
,
JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG1JNLE
JGE/JNL
JLlJNGE
JLE/JNG
JNC
JNE/JNZ
JNO·
JNP/JPO
JNS
JO
JP/JPE
. JS
CONDITION TESTED· .
.'
(CFORZF)=O
CF=O
CF=1
(CF oRZF)=1
CF=1
ZF=1
((SF XOR OF) OR ZF)=O
(SF XOR OF)=O
(SF XOR OF)=1
((SF XOR OF).OR ZF)=1
CF=O.
ZF=O
OF=O
PF=O
SF=O
OF=1
PF=1
SF=1
"JUMPIF ... "
. above/ not below nor equal
. above or equal/not below
below / not above nor equal
below or equal/not above':
carry ,
equal/zero
greater/not less nor equal
greater or equal/ not less
. less/notgreater nor equal
',less or equal/ not greater
" notcarry
"not equal! not zero
not overflow
not parity / parity odd
not sign
overflow
parity / parity equal
sign
.,
.
Note: "above" and·"below"refer to the relationship of twounsigned!Values; .
"greater" and' 'less" refer to the relationsh ip of two sig ned ,val ues.
external hard~a~e devices~The effect of software
interrupts is. similar to .hardware"initiated interrupts. However, the processor does not execute
an interrupt acknowledge bus cycle if the interrupt originates in software or with an NMI. The
effect of the interrupt instructions on the flags. is
covered in the description of each instruction.
.
REPZ repeat prefixes). CX is decremented by 1,
and control is transferred to the target operand if
CX is not 0 and if ZF is set; otherwise the instruction following LOOPE/LOOPZ is executed.
LOOPNE/LOOPNZ short-label
LOOPNE and LOOPNZ (Loop While Not Equal
and ,Loop While Not Zero) are also synonyms for
the same instruction. CX isdecremenfed by 1,
and control is transferred tothe target operand if
CX.is not 0 and if ZF is clear; otherwise the next
sequential instruction is executed.
INT interrupt-type
'.
JCXZ short-label
JCXZ (Jump If CX Zero) transfers control to the
target operand if CX is O. This instruction is
useful at the beginning ofa loop; to bypass the
loop if CX has a zero value, i.e., to execute the
loop zero times.
Interrupt Instructions
The interrupt instructions allow interrupt service
routines to be activated by programs as well as,.by
Mnemonics © Intel, 1978
.
.
.:
.
INT (Interrupt) activates the interrupt procedure
specified by the interrupt-type operand. INT
decrements the stack pointer by· two, pushes the
flags onto the stack, and clears the trap (TF) and
interrupt-enable (IF) flags to disable single-step
and maskable interrupts. The flags are stored in
the format used by the PUSHF instruction. SP is
decremented again by two, and the cS register is
pushed onto the stack. The .address of the interrupt pointer ..is calculated py mUltiplying
interrupHype by four; thesecondword of the in~
terrupt: pointer replaces CS. SP; again is
decremented by two, and IP is pushed onto the
stack and is replaced by the first word oftheinter"
rupt pointer. If interrupt-type = 3, the assembler
generates a short (1 byte) form of the instruction,
known as the breakpoint interrupt.
2-46
8086 AND 8088 CENTRAL PROCESSING UNITS
Software interrupts can be used as "supervisor
calls," i.e., requests for service from an operating
system. A different interrupt-type can be used for
each type of service that the operating system
could supply for an application program. Software interrupts also may be used to check out
interrupt service procedures written for hardwareinitiated interrupts.
Table 2-16. Processor Control Instructions
FLAG OPERATIONS
Set carry flag
Clear carry flag
Complement carry flag
Set direction flag
Clear direction flag
Set interrupt enable flag
Clear interrupt enable flag
STC
CLC
CMC
STD
CLD
STI
CLI
INTO
INTO (Interrupt on Overflow) generates a software interrupt if the overflow flag (OF) is set;
otherwise control proceeds to the following
instruction without activating an interrupt procedure. INTO addresses the target interrupt procedure (its type is 4) through the interrupt pointer
at location lOH; it clears the TF and IF flags and
otherwise operates like INT. INTO may be written following an arithmetic or logical operation to
activate an interrupt procedure if overflow
occurs.
EXTERNAL SYNCHRONIZATION
HLT
WAIT
ESC
LOCK
Halt until interrupt or reset
Wait for TEST pin active
Escape to external processor
Lock bus during next
instruction
NO OPERATION
Nap
No operation
IRET
IRET (Interrupt Return) transfers control back to
the point of interruption by popping IP, CS and
the flags from the stack. IRET thus affects all
flags by restoring them to previously saved
values. IRET is used to exit any interrupt
procedure, whether activated by hardware or
software.
CMC
CMC (Complement Carry flag) "toggles" CF to
its opposite state and affects no other flags.
STC
Processor Control Instructions
STC (Set Carry flag) sets CF to 1 and affects no
other flags.
.
These instructions (see table 2-16) allow programs
to control various CPU functions. One group of
instructions updates flags, and another group is
used primarily for synchronizing the 8086 or 8088
with external events. A final instruction causes
the CPU to do nothing. Except for the flag operations, none of the processor control instructions
affect the flags.
CLD
CLD (Clear Direction flag) zeroes DF causing the
string instructions to auto-increment the SI
and/or DI index registers. CLD does not affect
any other flags.
Flag Operations
CLC
STD
CLC (Clear Carry flag) zeroes the carry flag (CF)
and affects no other flags. It (and CMC and STC)
is useful in conjunction with the RCL and RCR
instructions.
STD (Set Direction flag) sets DF to 1 causing the
string instructions to auto-decrement the SI
and/or DI index registers. STD does not affect
any other flags.
2-47
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Cli
it builds (see table 2-26). An external processor
may monitor the system bus and capture this
opcode when the ESC is fetched. If the source
operand is a register, the processor does nothing.
If the source operand is a memory variable, the
processor obtains the operand from memory and
discards it. An external processor may capture the
memory operand when the processor reads it
from memory.
CLI (Clear Interrupt-enable flag) zeroes IF.
When the interrupt-enable flag is cleared, the
8086 and 8088 do not recognize an external interrupt request that appears on the INTR line; in
other words mask able interrupts are disabled. A
non-mask able interrupt appearing on the NMI
line, however, is honored, as is a software interrupt. CLI does. not affect any other flags.
lOCK
STI
LOCK is a one-byte prefix that causes the
STI (Set Interrupt-enable flag) sets IF to 1, enabling processor recognition of maskable interrupt requests appearing on the INTR line. Note
however, that a pending interrupt will not actually be recognized until the instruction following
STI has executed. STI does not affect any other
flags.
8086/8088 (configured in maximum mode) to
assert its bus LOCK signal while the following
instruction executes. LOCK does not affect any
flags. See section 2.5 for more information on
LOCK.
No Operation
External Synchronization
NOP
HlT
NOP (No Operation) causes the CPU to do
nothing. NOP does not affect any flags.
HL T (Halt) causes the 8086/8088 to enter the halt
state. The processor leaves the halt state upon
activation of the RESET line, upon receipt of a
non-maskable interrupt request on NMI, or, if
interrupts are enabled, upon receipt of a
mask able interrupt request on INTR. HLT does
not affect any flags. It may be used as an alternative to an endless software loop in situations
where a program must wait for an interrupt.
Instruction Set Reference Information
Table 2-21 provides detailed operational information for the 8086/8088 instruction set. The
information is presented from the point of view
of utility to the assembly language programmer.
Tables 2-17, 2-18 and 2-19 explain the symbols
used in table 2-21. Machine language instruction
encoding and decoding information is given in
Chapter 4.
WAIT
WAIT causes the CPU to enter the wait state
while its TEST line is not active. WAIT does not
affect any flags. This instruction is .described
more completely in section 2.5.
Instruction timings are presented as the number
of clock periods required to execute a particular
form (register-to-register, immediate-to-memory,
etc.) of the instruction. If a system is running with
a 5 MHz maximum clock, the maximum clock
period is 200 ns; at 8 MHz, the clock period is 125
ns. Where memory operands are used, "+EA"
denotes a variable number of additional clock
periods needed to calculate the operand's effective address (discussed in section 2.8). Table 2-20
lists all effective address calculation times.
ESC exfernal-opcode, source
ESC (Escape) provides a means for an external
processor to obtain an opcode and possibly a
memory operand from the 8086 or 8088. The
external opcode is a 6-bit immediate constant that
the assembler encodes in the machine instruction
Mnemonics © Intel, 1978
2-48
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-17. Key to Instruction Coding Formats
EXPLANATION
IDENTIFIER
USED.IN
destination
data transfer,
bit manipulation
A register or memory location that may contain data
operated on by the instruction, and which receives (is
replaced by) the result of the operation.
source
data transfer,
arithmetic,
bit manipulation
A register, memory location or immediate value that is
used in the operation, but is not altered by the instruction.
source-table
XLAT
Name of memory translation table addressed by register
BX.
target
JMP, CALL
A label to which control is to be transferred directly, or a
register or memory location whose content is the
address of the location to which control is to be transferred indirectly.
short-label
condo transfer,
iteration control
A label to which control is to be conditionally
transferred; must lie within -128 to +127 bytes of the first
byte of the next instruction.
accumulator
IN,OUT
Register AX for word transfers, AL for bytes.
port
IN,OUT
An I/O port number; specified as an immediate value of
0-255, or register OX (which contains port number in
range 0-64k).
source-string
string ops.
Name of a string in memory that is addressed by register
SI; used only to identify string as byte or word and
specify segment override, if any. This string is used in
the operation, but is not altered.
dest-string
string ops.
Name of string in memory that is addressed by register
01; used only to identify string as byte or word. This
string receives (is replaced by) the result of the operation.
count
shifts, rotates
Specifies number of bits to shift or rotate; written as
immediate value 1 or register CL (which contains the
count in the range 0-255).
i nterru pt-type
INT
Immediate value of 0-255 identifying interrupt pointer
number.
optional-pop-value
RET
Number of bytes (0-64k, ordinarily an even number) to
discard from stack.
external-opcode
ESC
Immediate value (0-63) that is encoded in the instruction
for use by an external processor.
2-49
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-18. Key to Flag Effects
IDENTIFIER
Table 2-19. Key to Operand Types
EXPLANATION
(blank)
not altered
0
cleared to 0
1
set to 1
X
set or cleared according
to result
U
undefined-contains no
reliable value
R
restored from previouslysaved value
IDENTIFIER
(no operands)
register
reg 16
seg-reg
accumulator
immediate
immed8
memory
mem8
mem16
source-table
For control transfer instructions, the timings
given include any additional clocks required to
reinitialize the instruction queue as well as the
time required to fetch the target instruction. For
instructions executing on an 8086, four clocks
should be added for each instruction reference to
a word operand located at an odd memory
address to reflect any additional operand bus
cycles required. Similarly for instructions executing on an 8088, four clocks should be added to
each instruction reference to a 16-bit memory
operand; this includes all stack operations. The
required number of data references is listed in
table 2-21 for each instruction to aid in this
calculation.
source-string
dest-string
DX
short-label
near-label
far-label
near-proc
far-proc
Several additional factors can increase actual
execution time over the figures shown in table
2-21. The time provided assumes that the instruction has already been prefetched and that it is
waiting in the instruction queue, an assumption
that is valid under most, but not all, operating
conditions. A series of fast executing (fewer than
two clocks per opcode byte) instructions can drain
the queue and increase execution time. Execution
time also is slightly impacted by the interaction of
the EU and BIU when memory operands must be
read or written. If the EU needs access to
memory, it may have to wait for up to one clock if
the BIU has already started an instruction fetch
bus cycle. (The EU can detect the need for a
memory operand and post a bus request far
enough in advance of its need for this operand to
avoid waiting a full 4-clock bus cycle). Of course
the EU does not have to wait if the queue is full,
because the BIU is idle. (This discussion assumes
Mnemonics © Intel, 1978
memptr16
memptr32
regptr16
repeat
EXPLANATION
No operands are written
An 8- or 16-bit general register
A 16-bit general register
A segment register
Register AX or AL
A constant in the range
O-FFFFH
A constant in the range O-FFH
An 8- or 16-bit memory
location(1)
An 8-bit memory location(1)
A 16-bit memory location(1)
Name of 256-byte translate
table
Name of string addressed by
register 51
Name of string addressed by
register 01
Register DX
A label within -128 to +127
bytes of the end of the instruction
A label in current code
segment
A label in another code
segment
A procedure in current code
segment
A procedure in another code
segment
A word containing the offset of
the location in the current code
segment to which control is to
be transferred(1)
A doubleword containing the
offset and the segment base
address of the location in
another code segment to which
control is to be transferred(1)1
A 16-bit general register
containing the offset of the
location in the current code
segment to which control is to
be transferred
A string instruction repeat
prefix
(1)Any addressing mode-direct, register indirect, based, indexed, or based
indexed-may be used (see section 2.8).
2-50
8086 AND 8088 CENTRAL PROCESSING UNITS
that the BIU can obtain the bus on demand, i.e.,
that no other processors are competing for the
bus.)
Table 2-20. Effective Address Calculation
Time
CLOCKS·
EA COMPONENTS
Dis~lacement
Onlv
Base or Index Only
Displacement
+
Base or Index
Base
+
Index
Displacement
+
Base
+
Index
(BX,BP,SI,DI)
With typical instruction mixes, the time actually
required to execute a sequence of instructions will
typically be within 5-100/0 of the sum of the
individual timings given in table 2-21. Cases can
be constructed, however, in which execution time
may be much higher than the sum of the figures
provided in the table. The execution time for a
given sequence of instructions, however, is always
repeatable, assuming comparable external conditions (interrupts, coprocessor activity, etc.). If the
execution time for a given series of instructions
must be determined exactly, the instructions
should be run on an execution vehicle such as the
SDK-86 or the iSBC 86112™ board .
6
5
9
(BX,BP,SI,DI)
BP+DI, BX+SI
BP+SI, BX+DI
BP+DI+DISP
BX+SI+DISP
BP+SI+DISP
BX+DI+DISP
7
8
11
12
• Add 2 clocks for segment override
Table 2-21. Instruction Set Reference Data
I
AAA
AAA (no operands)
ASCII adjust for addition
Operands
(no operands)
Clocks
Transfers·
Bytes
4
-
1
IAAD
(no operands)
ASCII adjust for division
AAD
Operands
(no operands)
Clocks
Transfers·
Bytes
60
-
2
AAM (no operands)
ASCII adjust for multiply
Operands
(no operands)
Transfers·
Bytes
83
-
1
I
AAS (no operands)
ASCII adjust for subtraction
AAS
Operands
AAA
AAD
Transfers·
Bytes
4
-
1
ODITSZAPC
U
X X UX U
Coding Example
AAM
FI
Clocks
ODITSZAPC
U
XXUXU
Coding Example
Flags
Clocks
ODITSZAPC
U
UU X U X
Coding Example
Flags
I
AAM
(no operands)
Flags
0 D ITS ZAP C
ags U
U U X U X
Coding Example
AAS
'For the 8086, add four clocks for each 16-blt word transfer with an odd address. Forthe 8088, add four clocks for each 16·blt word transfer.
2-51
Mnemonics © Intel, 1978
8086 AND 8088.CENTRALPROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
ADC
IADC destination,source
Add with carry
Flags
. Operands
Clocks
Transfers·
register, register
register,. memory
memory, register
register, immediate
memory, immediate
accumulator, immediate
3
9+EA
16+EA
-
4
-
17+EA
4
-
ADD
1
2
2
Bytes
2
2-4
2-4
··3-4
3-6
2-3
I ADD destination,source
Addition
Operands
Clocks
Transfers·
Bytes
3
9+EA
16+EA
4
17+EA
4
-
2
2-4
2-4
3-4
3-6
2-3
AND
1
2
-
2
-
lAND destination,source
Logical and
Clocks
Transfers·
Bytes
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate
3
9+EA
16+EA
4
17+EA
4
-
2
2-4
2-4
.3-4
3-6
2"3
1
2
2
-
I,CALL target
Call a procedure
Operands
near-proc
far-proc
memptr16
regptr 16
memptr32
Transfers·
Clocks
1.
2
2
1
4
r
3
5
2-4
2
2-4
Operands
CX, DX·
DI, [BX].ALPHA
TEMP, CL
CL,2
ALPHA,2
AX, 200
Transfers·
Bytes
2
-
1
ODITSZAPC
X'XU X 0
0
Coding Example
AND
AND
AND
AND
AND
AND
AL,BL
CX,FLAG_WORD
ASCII [DI],AL
CX,OFOH
BETA,01H
AX,01010000B
ODITSZAPC'
Coding Examples
CALL
CALL
CALL
CALL
CALL
NEAR_PROC
FAR_PROC
PROC_TABLE [SI]
AX
[BX].TASK [SI]
Flags
Clocks
ODITSZAPC
X
XXXXX
Coding Example
ADD
ADD
ADD
ADD
ADD
ADD
Bytes
I,CBW (no operands)
Convert byte to word
(no operands)
AX, SI
DX, BETA [SI]
ALPHA [BX] [SI], DI
BX,256
GAMMA,30H
AL,5
Flags
19
28
21+EA
16
37+EA
CBW
ADC
ADC
ADC
ADC
ADC
ADC
Flags
Operands
CALL
Coding Example
Flags
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate
ODITSZAPC
X
XXXXX
ODITSZAPC
..
Coding Example
CBW
'For the 8086, add four clocks for each 16-blt word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.
Mnemonics © Intel, 1978
2-52
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
CLC (no operands)
Clear carry flag
CLC
Operands
(no operands)
Flags
Clocks
Transfers·
Bytes
2
-
1
I
CLD (no operands)
Clear direction flag
CLD
Operands
(no operands)
Transfers·
Bytes
2
-
1
I
CLI (no operands)
Clear interrupt flag
CLI
Operands
(no operands)
Clocks
Transfers·
Bytes
2
-
1
CMC (no operands)
Complement carry flag
Operands
(no operands)
Clocks
Transfers·
Bytes
2
-
1
CMP destination,source
Compare destination to source
Clocks
Transfers·
Bytes
register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate
3
9+EA
9+EA
4
10+EA
4
-
2
2-4
2-4
3-4
3-6
2-3
1
1
-
1
-
I
,CMPS dest-string,source-string
Compare string
CMPS
Operands
dest-string, source-string
(repeat) dest-string, source-string
CLD
Coding Example
Transfers·
Bytes
22
9+22/rep
2
2/rep
1
1
ODIT5ZAPC
X
Coding Example
CMC
o
X
D IT 5 Z A PC
XXXXX
Coding Example
CMP
CMP
CMP
CMP
CMP
CMP
BX, CX
DH, ALPHA
[BP+2], 51
BL,02H
[BX].RADAR [DI], 3420H
AL,00010000B
Flags
Clocks
ODIT5ZAPC
0
CLI
Flags
Operands
ODIT5ZAPC
0
Coding Example
Flags
I
CMP
CLC
Flags
I
CMC
Coding Example
Flags
Clocks
ODIT5ZAPC
0
ODIT5ZAPC
XXXXX
X
Coding Example
CMP5 BUFF1, BUFF2
REPE CMP5 ID, KEY
'For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.
2-53
Mnemonics © intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
CWD (no operands)
Convert word to doubleword
CWD
Operands
(no operands)
Flags
Clocks
Transfers·
Bytes
5
-
1
I
DAA (no operands)
Decimal adjust for addition
DAA
Operands
(no operands)
Transfers·
Bytes
4
-
1
I
DAS (no operands)
Decimal adjust for subtraction
DAS
Operands
(no operands)
Clocks
Transfers·
Bytes
4
-
1
DEC destination
Decrement by 1
Operands
reg16
regS
memory
Clocks
Transfers·
Bytes
2
3
15+EA
..,..
-
1
2
2-4
2
DIV source
Division, unsigned
Operands
regS
reg16
mem8
mem16
immediate, memory
immediate, register
ODITSZAPC
U
XXXXX
Coding Example
DAS
ODITSZAPC
X
XXXX
Coding Example
DEC AX
DEC AL
DEC ARRAY [SI]
Transfers·
Bytes
80-90
144-162
(86-96)
+EA
(150-168)
+EA
1
2
2
2-4
DIV CL
DIV BX
DIV ALPHA
1
2-4
DIV TABLE [SI]
-
Clocks
Transfers·
S+EA
2
-
1
Coding Example
Flags
Bytes
. 2-4
2
..
ODITSZAPC
U
U U UU U
Clocks
ESC external-opcode,source
Escape
Operands
DAA
Flags
I
ESC
ODITSZAPC
X
X X X XX
Coding Example
Flags
I
DIV
CWD
Flags
I
DEC
Coding Example
Flags
Clocks
ODITSZAPC.
o
D IT S ZAP C
Coding Example
ESC 6,ARRA Y [SI]
ESC 20,AL
'For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.
Mnemonics © Intel, 1978
2-54
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I HLT (no operands)
Halt
HLT
Operands
(no operands)
Clocks
Transfers·
Bytes
2
-
1
IIDIV source
Integer division
IDIV
Operands
reg8
reg16
mem8
Clocks
Operands
reg8
reg16
mem8
-
1
2
2
2-4
IDIV BL
IDIV CX
IDIV DIVISOR_BYTE [SI]
1
2-4
IDIV [BX].DIVISOR_WORD
-
accumulator, immed8
accumulator, OX
Transfers·
Bytes
80-98
1
2
2
2-4
IMUL CL
IMUL BX
IMUL RATE_BYTE
1
2-4
IMUL RATLWORD [BP] [01]
Clocks
Operands
Coding Example
FI ags
Transfers·
Bytes
2
10
8
1
INC destination
Increment by 1
INC
ODITSZAPC
X
UUUUX
Clocks
IN accumulator,port
Input byte or word
Operands
Coding Example -
Flags
(86-104)
+EA
(134-160)
+EA
IN
ODITSZAPC
U
U U UU U
Bytes
128~154
mem16
HLT
Transfers·
IIMUL source
Integer multiplication
IMUL
ODITSZAPC
Coding Example
Flags
101-112
165-184
(107-118)
+EA
(171-190)
+EA
mem16
reg16
reg8
memory,
Flags
Coding Example
IN AL,OFFEAH
IN AX, OX
Flags
Clocks
Transfers·
Bytes
2
3
15+EA
-
1
2
2-4
2
0 0 ITS ZAP C
ODITSZAPC
X
XXXX
Coding Example
INC CX
INC BL
INC ALPHA [01] [BX]
"For the 8086, add four clocks for each 16-bIt word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.
2-55
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
liNT interrupt-type
Interrupt
INT
Operands
immed8 (type = 3)
immed8 (type *" 3)
Flags
Clocks
Transfers·
Bytes
52
51
5
5
1
2
INTR (external maskable interrupt)
Interrupt if INTR and IF=1
INTRt
Operands
(no operands)
Transfers·
Bytes
61
7
N/A
IINTO (no operands)
Interrupt if overflow
INTO
Operands
(no operandl:!)
Transfers·
Bytes
53 or 4
5
1
IIRET (no operands)
Interrupt Return
IRET
Operands
(no operands)
Clocks
Transfers·
Bytes
24
3
1
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
I
JAEI J NB short-label
Jump if above or equal/Jump if not below
JAE/JNB
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
I
JB/JNAE short-label
Jump if below/Jump if not above nor equal
JB/JNAE
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
ODITSZAPC
o0
Coding Example
N/A
ODITSZAPC
o0
Coding Example
INTO
Flags
I JAlJNBE short-label
Jump if above/Jump if not below nor equal
JA/JNBE
Coding Example
Flags
Clocks
o0
INT 3
INT 67
Flags
Clocks
ODITSZAPC
ODITSZAPC
RRRRRRRRR
Coding Example
IRET
Flags
ODITSZAPC
Coding Example
JA ABOVE
Flags
ODITSZAPC
Coding Example
JAE ABOVE_EQUAL
Flags
ODITSZAPC
Coding Example
JB BELOW
"For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
tlNTR is not an instruction; it is included in table 2-21 only for timing information.
Mnemonics © Intel, 1978
2-56
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I JBEI JNA short-label
Jump if below or equal/Jump if not above
JBE/JNA
Operands
short-label
Transfers·
Bytes
16 or 4
-
2
I JC short-label
Jump if carry
JC
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
Operands
short-label
Transfers·
Bytes
18 or 6
-
2
I JEI JZ short-label
Jump if equal/Jump if zero
JE/JZ
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
I JGE/JNL short-label
Jump if greater or equal/ Jump if not less
JGE/JNL
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
IJL/JNGE short-label
Jump if less/Jump if not greater nor equal
JL/JNGE
Operands
Clocks
Transfers·
Bytes
16or4
-
2
ODITSZAPC
Coding Example
JC CARRY_SET
ODITSZAPC
Coding Example
JCXZ COUNT_DONE
Flags
IJG/JNLE short-label
Jump if greater/Jump if not less nor equal
JG/JNLE
JNA NOT_ABOVE
Flags
Clocks
ODITSZAPC
Coding Example
Flags
I JCXZ short-label
Jump if CX is zero
JCXZ
short-label
Clocks
Flags
ODITSZAPC
Coding Example
JZ ZERO
Flags
ODITSZAPC
Coding Example
JG GREATER
Flags
ODITSZAPC
Coding Example
JGE GREATER_EQUAL
Flags
ODITSZAPC
Coding Example
JL LESS
'For the BOB6, add four clocks for each 16-bit word transfer with an odd address. For the BOBB, add four clocks for each 16-bit word transfer.
2-57
Mnemonics © Intel, 197B
8086 AND 8088 CENTRAL PROCESSING UNITS
,Table 2"21. Instruction Set Reference Data (Cont'd.)
IJLE/JNG short-label
Jump if less or equal/Jump if not greater
JLE/JNG
Operands
Clocks
Transfers·
Bytes
16 or 4
-
2
short-label
IJMP target
Jump
JMP
Operands
short-label
near-label
far-label
.memptr16
regptr16
memptr32
Clocks
Transfers·
15
15
15
1B+EA
11
24+EA
-
Operands
short-label
2
3
5
2-4
2 •
2-4
-
1
2
Clocks
Transfers·
Bytes
16 or 4
-
2
Operands
short-label
Transfers •
Bytes
16or4
-
2
·1 JNOshort-label
JNO
Operands
Clocks
Transfers·
Bytes
16or4
-
2
1JNP/JPO short-label
Jump if not parity/Jump if parity odd
JNP/JPO
Operands
short-label
Operands
short-label
FAR_LABEL
[BX].TARGET
CX
OTHER.SEG [SI]
Clocks
Transfers·
Bytes
16or4
-
2
JNC
NOT~CARRY
Transfers·
Bytes
16or4
-
2
ODITSZAPC
Coding Example
JNE NOT_EQUAL
ODITSZAPC
Coding Example
JNO NO_OVERFLOW
0 D ITS ZAP C
Coding Example
JPO ODD_PARITY
Flags
Clocks
ODITSZAPC
Coding Example
Flags
I JNS short-label
Jump if not sign
JNS
SHORT
WITHIN~SEGMENT
Flags
Jump if not overflow
short~label
JMP
JMP
JMP
JMP
JMP
JMP
Flags
Clocks
ODITSZAPC
Coding Example
Flags
I JNE/JNZ short-label
Jump if not equal/Jump ifnot zero
JNE/JNZ
Coding Example
Bytes
-
ODITSZAPC
JNG NOT_GREATER
Flags
. IJNC short-label
Jump if not carry
JNC
Flags
ODITSZAPC
Coding Example
JNS POSITIVE
'For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.
Mnemonics © Intel, 1978
2-58
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
JO short-label
Jump if overflow
JO
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
I
JP/JPE short-label
Jump if parity/Jump if parity even
JP/JPE
Operands
short-label
Clocks
Transfers·
Bytes
16 or 4
-
2
Operands
short-label
Transfers·
Bytes
16 or 4
-
2
I
LAHF (no operands)
Load AH from flags
LAHF
Operands
(no operands)
Clocks
Transfers·
Bytes
4
-
1
LOS destination,source
Load pointer using OS
Operands
reg16, mem32
Transfers
Bytes
16+EA
2
2-4
I
LEA destination,source
Load effective address
LEA
Operands
reg16, mem16
Clocks
Transfers·
Bytes
2+EA
-
2-4
LES destination,source
Load pointer using ES
Operands
JS NEGATIVE
Clocks
Transfers·
Bytes
2
2-4
OOITSZAPC
Coding Example
LAHF
OOITSZAPC
Coding Example
LOS SI,OATA.SEG [01]
OOITSZAPC
Coding Example
LEA BX, [BP] [01]
Flags
16+EA
OOITSZAPC
Coding Example
Flags
I
LES
Coding Example
Flags
Clocks
OOITSZAPC
JPE EVEN_PARITY
Flags
I
LOS
JO SIGNEO_OVRFLW
Flags
Clocks
OOITSZAPC
Coding Example
Flags
IJS short-label
Jump if sign
JS
reg16, mem32
Flags
OOITSZAPC
Coding Example
LES 01, [BX].TEXT_BUFF
'For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
2-59
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
LOCK (no operands)
Lock bus
LOCK
Operands
(no operands)
Flags
Clocks
Transfers·
Bytes
2
-
1
I
LODS source-string
Load string
.
LODS
Operands
source-string
(repeat) source-string
Transfers·
Bytes
12
9+13/rep
1
1/rep
1
1
I
LOOP short-label
Loop
LOOP
Operands
short-label
LOOPE/LOOPZ
Transfers·
Bytes
17/5
-
2
I
LOOPE/LOOPZ short-label
Loop if equal/Loop if zero
Operands
short-label
Clocks
Transfers·
Bytes
180r6
-
2
I
short-label
Clocks
Transfers·
Bytes
190r5
-
2
I
NMI (external nonmaskable interrupt)
Interrupt if NMI = 1
.
NMlt
Operands
(no operands)
LOOS CUSTOMER_NAME'
REP LOOS NAME ..
Clocks
Transfers·
Bytes
50'
5
N/A
OOITSZAPC
Coding Example
LOOP AGAIN
o
0 ITS ZA P C,
Coding Example
LOOPE AGAIN
Fla.gs..
Loop If not equal/Loop If not zero
OOITSZAPC
Coding Example
Flags
LOOPN E/LOO PNZ LOO~NE/LOOPNZ sho.rt-Iabel
Operands
LOCK XCHG FLAG,AL
Flags
Clocks
0 ITS ZAP ,C
Coding Example
Flags
Clocks
o
o
0 ITS ZAP· C
'coding Example
LOOPNE AGAIN
Flags
OSITSZAPC
o0
Coding Example
N/A
'Forthe 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.
tNMI is not an instruction; it is included in table 2-21 only for timing information.
Mnemonics © Intel, 1978
2-60
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
MOV destination,source
Move
MOV
Operands
memory, accumulator
accumulator, memory
register, register
register, memory
memory, register
register, immediate
memory, immediate
seg-reg, reg16
seg-reg, mem16
reg16, seg-reg
memory, seg-reg
Transfers·
Bytes
10
10
2
8+EA
9+EA
4
10+EA
2
8+EA
2
9+EA
1
1
3
3
2
2-4
2-4
2-3
3-6
2
2-4
2
2-4
1
1
1
1
1
MOVS dest-string,source-string
Move string
Operands
dest-string, source-string
(repeat) dest-string, source-string
MOVSB/MOVSW
ODITSZAPC
Bytes
Coding Example
18
9+17/rep
2
2/rep
1
1
MOVS LINE EDIT_DATA
REP MOVS SCREEN, BUFFER
Flags
Clocks
Transfers·
Bytes
18
9+17/rep
2
2/rep
1
1
MUL source
Multiplication, unsigned
Operands
ARRAY [SI], AL
AX, TEMP _RESULT
AX,CX
BP, STACK_TOP
COUNT [DI], CX
CL,2
MASK [BX] [SI], 2CH
ES,CX
DS, SEGMENT_BASE
BP,SS
[BX].SEG_SAVE, CS
Transfers·
I
MUL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Clocks
MOVSB/MOVSW (no operands)
Move string (byte/word)
(no operands)
(repeat) (no operands)
ODITSZAPC
Coding Example
Flags
I
Operands
mem16
Clocks
I
MOVS
reg8
reg16
mem8
Flags
ODITSZAPC
Coding Example
MOVSB
REP MOVSW
Flags
ODITSZAPC
U U UU X
X
Clocks
Transfers·
Bytes
70-77
118-133
(76-83)
+EA
(124-139)
+EA
-
1
2
2
2-4
MUL BL
MUL CX
MUL MONTH [SI]
1
2-4
MUL BAUD_RATE
-
Coding Example
'For the 8086, add four clocks for each 16·bit word transfer with an odd address. For the 8088, add four clocks for each 16·bit word transfer.
2-61
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
NEG destination
Negate
NEG
Operands
register
memory
'0 if destination
=
Flags
Clocks
Transfers'
Bytes
3
16+EA
-
2
2-4
2
Coding Example
NEG AL
NEG MULTIPLIER
0
/ NOP (no operands)
No Operation
Nap
Operands
(no operands)
Flags
Clocks
Transfers'
Bytes
3
-
1
J
NOT destination
Logical not
NOT
Operands
register.
memory
Clocks
Transfers'
Bytes
3
16+EA
-
2
2-4
2
Clocks
Transfers'
Bytes
register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate
3
9+EA.
16+EA
4
4
17+EA
-.
2
2-4
2-4
2-3
3-4
3-6.
1
2
-
2 ,
./ OUT port,accumulator
Output byte or word
OUT
Operands
immed8, accumulator
OX, accumulator
Clocks
Transfers'
Bytes
10
1
1
2
1
8
POP destination
Pop word off stack
Operands
register
seg-reg (CS illegal)
memory
NOT .AX
NOT CHARACTER
Transfers'
Bytes
8
8
1
1
2
1
1
2-4
17+EA
OOITSZAPC
0
X X U X 0
Coding Example
OR AL, BL
OR OX, PORT _10 [01]
OR FLAG_BYTE, CL
OR AL,01101100B
OR CX,OlH
OR [BX].CMO_WORO,OCFH
ODITSZAPC
Coding Example
OUT 44, AX
OUT OX, AL
Flags
Clocks
OOITSZApC
Coding Example
Flags
I
POP
NOP
Flags
Operands
OOITSZAPC
Coding Example
Flags
lOR destination,source
Logical inclusive or
OR
,
OOITSZAPC
X
XXXX.1·
OOITSZAPC
Coding Example
POP OX
POP OS
POP PARAMETER
'For the 8086, add four clocks for each l6-bit word transfer with an odd address. For the 8088, add four clocks for each l6-bit word transfer.
Mnemonics © Intel, 1978
2-62
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
POPF (no operands) .
Pop flags off stack
POPF
Operands
(no operands)
Clocks
Transfers·
Bytes
B
1
1
I
PUSH
PUSH source
Push word onto stack
Operands
register
seg-reg (CS legal)
memory
Clocks
Transfers·
Bytes
11
10
16+EA
1
1
2
1
1
2-4
PUSHF (no operands)
Push flags onto stack
Operands
(no operands)
Transfers·
Bytes
10
1
1
I~CL
destination,count
Rotate left through carry
RCL
Operands
register, 1
register, CL
memory, 1
memory, CL
Transfers·
Bytes
2
B+4/bit
15+EA
20+EA+
4/bit
-
2
2
2-4
2-4
2
2
I~CR
designation,count
Rotate right through carry
RCR
Operands
Clocks
register, 1
register, CL
memory, 1
memory, CL
Bytes
-
2
2
2-4
2-4
2
B+4/bit
15+EA
20+EA+
4/bit
2
2
I
REP
REP (no operands) "
Repeat string operation
Operands
Transfers·
Bytes
2
-
1
o
D IT S ZAP C
Coding Example
PUSHF
ODITSZAPC
X
X
Coding Example
RCLCX,1
RCL AL,CL
RCL ALPHA,1
RCL [BP].PARM, CL
OD ITS ZAP C
X
X
Coding Example
RCR
RCR
RCR
RCR
BX,1
BL,CL
[BX].STATUS,1
ARRAY [DI], CL
Flags
Clocks
D ITS Z AP C
PUSH SI
PUSH ES
PUSH RETURN_CODE [SI]
Flags
. Transfers·
o
Coding Example
Flags
. Clocks
D ITS Z A PC
R RR R R R R R R
Coding Example
Flags
Clocks
o
POPF
Flags
I
PUSHF
(no operands)
Flags
o
'.
D ITS Z AP C
Coding Example
REP MOVS DEST, SRCE
'For the 8086, add four clocks for each 16-bit word transfer with an odd address,For the 8088, add four clocks for each 16-bit word transfer.
2-63
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
REPE/REPZ
I
REPE/REPZ (no operands)
Repeat string operation while equal/while zero
Operands
(no operands)
REPNEIREPNZ
Clocks
Transfers·
Bytes
2
-
1
\IREPNE/REPNZ (no operands)
Repeat string operation while not equal/ not zero
Operands
(no operands)
Clocks
Transfers·
Bytes
2
-
1
I
RET
RET optional-pop-value
Return from procedure
Operands
(intra-segment, no pop)
(intra-segment, pop)
(inter-segment, no pop)
(inter-segment, pop)
Clocks
Transfers·
Bytes
8
12
18
17
1
1
2
2
1
3
1
3
ROL destination,count
Rotate left
Operands
register, 1
register, CL
memory, 1
memory, CL
Transfers
2
8+4/bit
15+EA
20+EA+
4/bit
Operand
register, 1
register, CL
memory, 1
memory, CL
2
2
2
2
2-4
2-4
Clocks
Transfers·
Bytes
2
8+4/bit
15+EA
20+EA+
4/bit
-
2
2
2-4
2-4
2
2
Operands
(no operands)
Coding Example
Transfers·
Bytes
4
-
1
ODITSZAPC
Coding Example
RET
RET 4
RET
RET 2
ODITSZAPC
X
X
Coding Examples
ROL
ROL
ROL
ROL
BX,1
DI, CL
FLAG_BYTE [01],1
ALPHA, CL
ODITSZAPC
X
X
Coding Example
ROR
ROR
ROR
ROR
AL,1
BX,CL
PORT_STATUS, 1
CMD_WORD, CL
Flags
Clocks
ODITSZAPC
REPNE SCAS INPUT_LINE
Flags
\SAHF (no operands)
Store AH into flags
SAHF
Flags
Bytes
\ ~OR destination,count
Rotate right
ROR
REPE CMPS DATA, KEY
Flags
Clocks
ODITSZAPC
Coding Example
Flags
I
ROL
Flags
ODITSZAPC
RRR R R
Coding Example
SAHF
·For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
Mnemonics © Intel, 1978
2-64
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
SAL/SHL destination,count
Shift arithmetic leftl Shift logical left
SAL/SHL
Operands
register,1
register, CL
memorY,1
memory, CL
Flags
Clocks
Transfers·
Bytes
2
8+4lbit
15+EA
20+EA+
41bit
-
2
2
2-4
2-4
2
2
I
SAR destination,source
Shift arithmetic right
SAR
Operands
register, 1
register, CL
memory, 1
memory, CL
Transfers·
Bytes
2
8+4lbit
15+EA
20+EA+
41bit
-
2
2
2-4
2-4
2
2
I
SBB destination, source
Subtract with borrow
SBB
Operands
..
register, register
register, memory
memory, register
accumulator, immediate .
register, immediate
memory, immediate
Transfers·
Bytes
3
9+EA
16+EA
4
4
17+EA
-
2
2-4
2-4
2-3
3-4
3-6
1
2
2
ISCAS
dest-string
Scan string
seAS
Operands
dest-string
(repeat) dest-string
SEGMENTt
Operands
(no operands)
SAL
SHL
SHL
SAL
Transfers·
Bytes
15
9+151rep
1
11rep
1
1
I
SI;G MENT override prefix
Override to specified segment
OX,1
01, CL
N_BLOCKS, 1
N_BLOCKS, CL
Transfers·
Bytes
2
-
1
OolTSZAPC
X
X X X X X
Coding Example
SBB
SBB
SBB
SBB
SBB
SBB
BX,CX
01, [BX].PAYMENT
I;lALANCE, AX
AX,2
CL,1
COUNT [SI], 10
OolTSZAPC
XXXXX
.x
Coding Example
SCAS INPUT_LINE
REPNE SCAS BUFFER
Flags
Clocks
OolTSZAPC
X
X X U X X
Coding Example
SAR
SAR
SAR
SAR
Flags
Clocks
X
AL,1
01, CL
[BX].OVERoRAW,1
STORE_COUNT, CL
Flags
Clocks
X
Coding Examples
Flags
Clocks
00 ITS ZAP C
OolTSZAPC
Coding Example
MOV SS:PARAMETER, AX
'For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
tASM-86 incorporates the segment override prefix into the operand specification and not as a separate instruction. SEGMENT is included in table
2-21 only for timing information.
Mnemonics © Intel, 1978
2-65
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
SHR destination,count
Shift logical right
SHR
Operands
Clocks
register, 1
register, CL
memory, 1
memory, CL
Flags
Transfers·
Bytes
-
2
2
2-4
2-4
2
8+4/bit
15+EA
20+EA+
4lbit
SINGLE STEPt
-
2
2
I
SINGLE STEP (Trap flag interrupt)
Interrupt if TF = 1
Operands
(no operands)
Transfers·
Bytes
50
5
N/A
I
STC (no operands)
Set carry flag
STC
Operands
(no operands)
. Transfers·
Bytes
2
-
1
I
STD (no operands)
Set direction flag
. STD
Operands
(no operands)
Clocks
Transfers·
Bytes
2
-
1
STI(no operands)
Set interrupt enable flag
Operands
(no operands)
Transfers·
Bytes
2
-
1
I
STOS dest-string
Store byte or word string
STOS
Operands
dest-string
(repeat) dest-string .
N/A
Transfers·
Bytes
11
9+10/rep
1
1/rep
1
1
ODITSZAPC
1
Coding Example
STC
ODITSZAPC
1
Coding Example
STD
ODITSZAPC
1
Coding Example
STI
Flags
Clocks
ODITSZAPC
o0
Coding Example
Flags
Clocks
D ITS ZA PC
X
SI,1
SI, CL
ID_BYTE [SI] [BX], 1
INPUT_WORD, CL
Flags
I
STI
SHR
SHR
SHR
SHR
Flags
Clocks
X
Coding Example
Flags
Clocks
o
ODITSZAPC
Coding Example
STOS PRINT_LINE
REP STOS DISPLAY
• For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
tSINGLE STEP is no, an instruction; it is included in table 2-21 only for timing information.
Mnemonics © Intel, 1978
2-66
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
IsUB destination, source
Subtraction
SUB
Flags
Operands
Clocks
Transfers·
Bytes
register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate
3
9+EA
16+EA
4
4
17+EA
-
2
2-4
2-4
2-3
3-4
3-6
1
2
2
I TEST destination,source
Test or non-destructive logical and
TEST
Clocks
Transfers·
Bytes
register, register
register, memory
accumulator, immediate
register, immediate
memory, immediate
3
9+EA
4
5
11 +EA
-
2
2-4
2-3
3-4
3-6
-
-
I WAIT (no operands)
Wait while TEST pin not asserted
WAIT
Operands
(no operands)
XCHG
accumulator, reg16
memory, register
register, register
Clocks
Transfers·
Bytes
3 + 5n
-
1
Clocks
Transfers·
Bytes
3
17+EA
4
-
1
2-4
2
2
-
Operands
TEST
TEST
TEST
TEST
TEST
51,01
51, END_COUNT
AL,00100000B
BX, OCC4H
RETURN_CODE,01H
Transfers·
Bytes
11
1
1
ODITSZAPC
Coding Example
WAIT
ODITSZAPC
Coding Example
XCHG AX, BX
XCHG SEMAPHORE, AX
XCHG AL, BL
Flags
Clocks
ODITSZAPC
0
X X U X 0
Coding Example
Flags
IXLAT source-table
Translate
XLAT
CX, BX
OX, MATH_TOTAL [SI]
[BP+2], CL
AL r 10
SI,5280
[BP].BALANCE,1000
Flags
IXCHG destination,source
Exchange
Operands
source-table
1
Coding Example
SUB
SUB
SUB
SUB
SUB
SUB
Flags
Operands
ODITSZAPC
X
XXXXX
ODITSZAPC
Coding Example
XLAT ASCILTAB
·For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
2-67
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-21. Instruction Set Reference Data (Cont'd.)
I
XOR destination,source
Logical exclusive or
XOR
Flags
Operands
Clocks
Transfers·
Bytes
register, register
register, memory
memory, register
accumulator, immediate
register, immediate
memory, immediate
3
9+EA
16+EA
4
4
17+EA
-
2
2-4
2-4
2-3
3-4
3-6
1
2
2
ODITSZAPC
X X U X 0
0
Coding Example
XOR
XOR
XOR
XOR
XOR
XOR
CX, BX
CL, MASK_BYTE
ALPHA [SI], DX
AL,01000010B
SI,00C2H
RETURN_CODE,OD2H
• For the 8086, add four clocks for each 16-bit word transfer with an odd address. Forthe 8088, add four clocks for each 16-bit word transfer.
2.8 Addressing Modes
Memory Addressing Modes
The 8086 and 8088 provide many different ways
to access instruction operands. Operands may be
contained in registers, within the instruction
itself, in memory or in 1/0 ports. In addition, the
addresses of memory and 110 port operands can
be calculated in several different ways. These
addressing modes greatly extend the flexibility
and convenience of the instruction set. This section briefly describes register and immediate
operands and then covers the 8086/8088 memory
and 110 addressing modes in detail.
Whereas the EU has direct access to register and
immediate operands, memory operands must be
transferred to or from the CPU over the bus.
When the EU needs to read or write a memory
operand, it must pass an offset value to the BIU.
The BIU adds the offset to the (shifted) content of
a segment register producing a 20-bit physical
address and then executes the bus cycle(s) needed
to access the operand.
The Effective Address
The offset that the EU calculates for a memory
operand is called the operand's effective address
or EA. It is an unsigned J6-bit number that
expresses the operand's distance in bytes from the
beginning of the segment in which it resides. The
EU can calculate the effective address in several
different ways. Information encoded in the
second byte of the instruction tells the EU how to
calculate the effective address of each memory
operand. A compiler or assembler derives this
information from the stateme.nt or instruction
written by the programmer. Assembly language
programmers have access to. all addressing modes.
Register and Immediate Operands
Instructions that specify only register operands
are generally the most compact and fastest
executing of all instruction forms. This is because
the register "addresses" are encoded in instructions in just a few bits, and because these operations are performed entirely within the CPU (no
bus cycles are ·run). Registers may serve as source
operands, destination operands, or both.
Immediate operands are constant data contained
in an instruction. The data may be. either 8 or 16
bits in length. Immediate operands can be
accessed quickly because they are available
directly from the instruction queue; like a register
operand, no bus cycles need to be rUn to obtain an
immediate operand. The limitations of immediate
operands are that they may only serve as source
operands and that they are constant values.
Mnemonics © Intel, 1978
Figure 2-34 shows that the execution unit
calculates the EA by summing a displacement, the
content of a base register and the content of an
index register. The fact that any combination of
these three components may be present in a given
instruction gives rise to the variety of 8086/8088
memory addressing modes.
2-68
8086 AND 8088 CENTRAL PROCESSING UNITS
DOUBLE INDEX
SINGLE INDEX
ENCODED
INTHE
INSTRUCTION
EU
EXPLICIT
{
INTHE
INSTRUCTION
l
ASSUMED
UNLESS
OVERRIDDEN
BY PREFIX
BIU
Figure 2-34. Memory Address Computation
The displacement element is an 8- or 16-bit
number that is contained in the instruction. The
displacement generally is derived from the position of the operand name (a variable or label) in
the program. It also is possible for a programmer
to modify this value or to specify the displacement explicitly.
Table 2-20 shows how much time is required to
compute an effective address for any combination
of displacement, base register and index register.
Direct Addressing
Direct addressing (see figure 2-35) is the simplest
memory addressing mode. No registers are involved; the EA is taken directly from the displacement field of the instruction. Direct addressing
typically is used to access simple variables
(scalars).
A programmer may specify that either BX or BP
is to serve as a base register whose content is to be
used in the EA computation. Similarly, either SI
or DI may be specified as an index register.
Whereas the displacement value is a constant, the
contents of the base and index registers may
change during execution. This makes it possible
for one instruction to access different, memory
locations as determined by the current values in
the base and/or index registers.
Register Indirect Addressing
The effective address of a memory operand may
be taken directly from one of the base or index
registers as shown in figure 2-36. One instruction
can operate on many different memory locations
if the value in the base or index register is updated
It takes time for the EU to calculate a memory
operand's effective address. In general, the more
elements in the calculation, the longer it takes.
2-69
8086 AND 8088 CENTRAL PROCESSING UNITS
appropriately. The LEA (load effective address)
and arithmetic instructions might be used to
change the register value:
ment (unless a segment override prefix is present).
This makes based addressing with BP a very convenient way to access stack data (see section 2.10
for examples),
Note that any 16-bit general register may be used
for register indirect addressing with the JMP or
CALL instructions.
Based addressing also provides a straightforward
way to address structures which may be located at
different places in memory (see figure 2-38). A
base register can be pointed at the base of the
structure and elements of the structure addressed
by their displacements from the base. Different
copies of the same structure can be accessed by
simply changing the base register.
EA
HIGH ADDRESS
DISPLACEMENT
t
Figure 2-35. Direct Addressing
ISTATUS
RATE
VAC
DEPT
1 BASE REGISTER I
L
-
AGE
t
EA
i
I
I
I
SICK
DIV
EMPLOYEE
T
I BASE REGISTER h
'" ",,",:J~i
I
RATE
BX
VAC
OR
EA
BP ___~.[:::!~::]
D~;PLOY~~
~.I--OR
51
I
SICK
______
.J
OR
01
LOW ADDRESS
Figure 2-38. Accessing a Structure With Based
Addressing
Figure 2-36. Register Indirect Addressing
Based Addressing
Indexed Addressing
In based addressing (figure 2-37), the effective
address is the sum of a displacement value and the
content of register BX or register BP. Recall that
specifying BP as a base register directs theBiU to
obtain the operand from the current stack seg-
In indexed addressing, the effective address is
calculated from the sum of a displacement plus
the content of an index register(SI or DI) as
shown in figure 2-39. Indexed addressing often is
E~~---+-EA
Figure 2-39. Indexed Addressing
Figure 2-37. Based Addressing
Mnemonics © Intel, 1978
2-70
8086 AND 8088 CENTRAL PROCESSING UNITS
used to access elements in an array (see figure
2-40). The displacement locates the beginning of
the array, and the value of the index register
selects one element (the first element is selected if
the index register contains 0). Since all array
elements are the same length, simple arithmetic
on the index register will select any element.
Based indexed addressing provides a convenient
way for a procedure to address an array allocated
on a stack (see figure 2-42). Register BP can contain the offset of a reference point on the stack,
typically the top of the stack after the procedure
has saved registers and allocated local storage.
The offset of the beginning of the array from the
reference point can be expressed by a displacement value, and an index register can be used to
access individual array elements.
Based Indexed AddreSSing
Based indexed addressing generates an effective
address that is the sum of a base register, an
index register and a displacement (see figure
2-41). Based indexed addressing is a very flexible
mode because two address components can be
varied at execution time.
Arrays contained in structures and matrices (twodimension arrays) also could be accessed with
based indexed addressing.
HIGH ADDRESS
ARRAY (8)
ri
DISPLACEMENT
I
I INDEX
I
I
I I
I
~GISTER
,
14
EA
I
r+
ARRAY (7)
1
ARRAY (6)
I
ARRAY (5)
I
ARRAY (3)
2
ARRAY (2)
t
I-
ARRAY (1)
L --------..
ARRAY (0)
--t
I
EA
Hd-j
I
I
I
I
ARRAY (4)
Eg~:+r
_-------.J
I
~1WORD~
EA
LOW ADDRESS
Figure 2-40. Accessing an Array With Indexed
Addressing
Figure 2-41. Based Indexed Addressing
HIGH ADDRESS
DISPLACEMENT
PARM __ 2
6
PARM_1
~
IP
..
t BASE REGISTERJ(BP)
I
I
I
I
I
INDEX !GISTER
I
I I
I
I
+
L
12
t
EA
I
.-
I
ARRAY (6)
I
1
ARRAY (5)
4
ARRAY (3)
--t
ARRAY (2)
_______i.._
1
(BP)
OLD_BX
OLD _AX
ARRAY (4)
.-
-------1
OLD_BP
ARRAY (0)
COUNT
TEMP
I
EA
1
1
ARRAY (1)
STATUS
1
t
-.1------""1"':
.. 1 ______ -1
..-1WORO ......
LOWER ADDRESS
Figure 2-42. Accessing a Stack Array With Based Indexed Addressing
2-71
8086 AND 8088 CENTRAL PROCESSING UNITS
operand. This allows fixed access to ports
numbered 0~255. Indirect port addressing is
similar to register indirect addressing of memory
operarids. The port number is taken from register
DX and can range from 0 to 65,535. By previously adjusting the content of register DX, one
instruction can access arty port in the I/O space.
A group of adjacent ports can be accessed using a
simple software loop that adjusts the value in DX.
String Addressing
String instructions do not use the normal memory
addressing modes to access their operands.
Instead, the index registers are used implicitly as
shown in figure 2-43. When a string instruction is
executed, SI is assumed to point to the first byte
or word of the source string, and DI is assumed to
point to the first byte or word of the destination
string. In a repeated string operation, the CPUs
automatically adjust SI and DI to obtain subsequent bytes or words.
I/O Port Addressing
2.9 Programming Facilities
If an I/O port is memory mapped, any of the
A comprehensive integrated set of tools supports
8086/8088 software development. These tools are
programs that run on Intellec® 800 or Series II
Microcomputer Development Systems under. the
ISIS-II operating system, the same hardware and
operating system used to develop software for the
8080 and the 8085. Since the 8086 and 8088 are
software-compatible with one another, the same
tools are used for both processors to provide
programmers with a uniform development
environment.
memory operand addressing modes may be used
to access the port. For example, a group of terminals can be accessed as an "array." String
instructions also can be used to transfer data to
memory-mapped ports with an appropriate hardware interface. Section 2.10 contains examples of
addressing memory-mapped I/O ports.
Two different addressing modes can be used to
access ports located in the I/O space; these are
illustrated in figure 2-44. In direct port addressing, the port number is an 8-bit immediate
DIRECT PORT ADDRESSING
SI
f..--..I.
01
1--1 DESTINATION EA 1
SOURCE EA
INDIRECT PORT ADDRESSING
Figure 2-44. i/o Port Addressing
Figure 2-43. String Operand Addressing
2-72
8086 AND 8088 CENTRAL PROCESSING UNITS
S086 and 80S8 modules can be written in either
PLlM-S6 or ASM-86 (see table 2-22). PLlM-86 is
a high-level language suitable for most
microprocessor applications. It is easy to use,
even by programmers who have little experience
with microprocessors. Because it reduces software
development time, PL/M-S6 is ideal for most of
the programming in any application, especially
applications that must get to market quickly.
Software Development Overview
A program that will ultimately execute on an
SOS6- or SOSS-based system is developed in steps
(see figure 2-45). The overall program is composed of functional units called modules. For
purposes of this discussion, a module is a section
of code that is separately created, edited, and
compiled or assembled. A very small program
might consist of a single module; a large program
could be comprised of 100 or more modules. The
SOS6/S0SS LINK-86 utility binds modules
together into a single program. (The module
structure of a program is critical to its successful
development and maintenance; see section 2.10
for guidelines.)
ASM-86 is the S086/808S assembly language.
provides the programmer who is familiar
with the CPU architecture, access to all processor
features. For critical code segments within programs that make sophisticated use of the hardware, have extremely demanding performance or
memory constraints, ASM-86 is the best choice.
ASM~86
Figure 2-45. Software Development Process
2-73
8086 AND 8088 CENTRAL PROCESSING UNITS
Table 2-22. PLlM-86/ ASM-86 Characteristics
ASM-86
PL/M-86
• Fast Development
• Fastest Execution Speed
• Less Programmer Training
• Smallest Memory Requirements
• Detailed Hardware Knowledge Not Required
• Access To All Processor Facilities
The languages are completely compatible, and a
judicious combination of the two often makes
good sense. Prototype software can be developed
rapidly with PLlM-S6. When the system is
operating correctly, it can be analyzed to see
which sections can pest profit from being written
in ASM-S6. Since the logic of these sections
already has been debugged, selective rewriting can
be done quickly and with low risk.
addresses in every system, or separate versions
with different addresses would have to be maintained for each system. When locating is deferred,
a single version of a common routine can be used
by any number of systems. Finally, the locations
of modules typically change as a system is
developed, maintained and enhanced. Separating
the location process from the translation process
means that as modifications are made, unchanged
modules only need to be relocated, not
retranslated.
Each PLlM-S6 or ASM-S6 module (called a
source moduel) is keyed into the Intellec® system
using the ISIS-II text editor and is stored as a
diskette file. This source file is then input to the
appropriate language translator (ASM-S6
assembler or PL/M-S6 compiler). The language
translator creates a diskette file from the source
file, which is called a relocatable object module.
The translator also lists the program and flags any
errors detected during the translation. The
relocatable object module contains the SOS6/S0SS
machine instructions that the translator created
from the statements in the source module. The
term "relocatable" refers to the fact that all
references to memory locations in the module are
relative, rather than being absolute memory
addresses. The module generally is not executable
until the relative references are changed to the
actual memory locations where the module will
reside in the execution system's memory. The process of changing the relative references to
absolute memory locations is called locating.
Relocatable object modules may be placed into
special files called libraries, using the LIB-S6
library manager program. Libraries provide a
convenient means of collecting groups of related
modules so that they can be accessed automatically by the LINK-S6 program.
When enough relocatable object modules have
been created to test the system, or part of it, the
modules are linked and located. Linking combines all the separate modules into a single program. Locating changes the relative memory
references in the program to the actual memory
locations where the program will be loaded in the
execution system. The link and locate process also
is referred to as R & L, for relocation and linkage.
Two other programs round out the software
development tools available for the SOS6 and
SOSS. OH-S6 converts an absolute object file into
a hexadecimal format used by some PROM programmers and system loaders (for example, the
SDK-S6 and iSBC 957™ loaders). CONV-S6 can
do most of the conversion work required to
translate SOSO/SOS5 assembly language source
modules into ASM-86 source modules.
There are very good reasons for not locating
modules when they are translated. First, the execution system's physical memory configuration
(where RAM and ROM/PROM segments are
actually located in the megabyte memory space)
may not be known at the time the modules are
written. Second, it is desirable to be able to use a
common module (e.g., a square root routine) in
more than one system. If absolute addresses were
assigned at translation time, the common module
would either have to occupy the same physical
The S086/S0SS software development facilities
are covered in more detail in the remainder of this
section. However, these are only introductions to
2-74
8086 AND 8088 CENTRAL PROCESSING UNITS
the use of these tools. Complete documentation is
available in the following publications available
from Intel's Literature Department:
PLlM-S6 programmer. Instead, the processors
appear to respond to simple commands and
familiar algebraic expressions. The responsibility
for translating these source statements into the
machine instructions ultimately required to execute on the SOS6/S0SS is assumed by the PLlM-S6
c()mpiler. By "hiding" the details of the machine
architecture, PL/M-S6 encourages programmers
to concentrate on solving the problem at hand.
Furthermore, because PL/M-S6 is closer to
natural language, it is easier to "think in
PLlM-S6" than it is to "think in assembly
language." This speeds up the expression of a
program solution, and, equally important, makes
that solution easier for someone other than the
original programmer to understand. PL/M-S6
also contains all the constructs necessary for
structured programming.
ISIS-II:
ISIS-II System User's Guide, Order No. 9S00306
ASM-86:
MCS-86 Assembly Language Reference Manual,
Order No. 9S00640
MCS-86 Assembler Operating Instructions for
ISIS-II Users, Order No. 9S00641
PL/M-86:
PLIM-86 Programming Manual, Order No.
9S00466
ISIS-II PLIM-86 Compiler Operator's Manual,
Order No. 980047S
LINK-86, LOC-86, LIB-86, OH-86:
Statements and Comments
MCS-86 Software Development Utilities
Operating Instructions for ISIS-II Users, Order
No.9S00639
A programmer builds a PLlM-S6 program by
writing statements and comments (see figure
2-46). There are several different types of
statements in PLlM-S6; they always end with a
semicolon. Blanks can be used freely before,
within, and after statements to improve readability. A statement also may span more than one
line.
CONV-86:
MCS-86 A$sembly Language Converter
Operating Instructions for ISIS-II Users, Order
No.9S00642
The characters "1*" start a comment, and the
characters "*1" end it; any characters may be
used in between. Comments do not affect the execution of a PLlM-S6 program, but all good programs are thoughtfully commented. Comments
are notes that document and clarify the program's
operation; they may be written virtually anywhere
in a PLlM-S6 program.
PL/M-86
PLlM-S6 is a general-purpose, high-level
language for programming the SOS6 and SOSS
microprocessors. It is an extension of PL/M-SO,
the most widely-used, high-level programming
language for microprocessors. (PL/M-SO source
programs can be processed by the PL/M-S6 compiler; the resulting object program is generally
reduced by 15-300/0 in size.) PLlM-S6 is suitable
for all types of microprocessor software from
operating systems to application programs.
Data Definition
Most PLlM-S6 programs begin by defining the
data items (variables) with which they are going to
work. An individual PLlM-S6 data element is
called a scalar. Every scalar variable has a
programmer-supplied name up to 31 characters
long, and a type. PLlM-S6 supports five types of
scalars: byte, word, integer, real, and pointer.
Table 2-23 lists the characteristics of these
PLlM-S6 data types.
PLlM-S6's purpose is simple: to reduce the time
and cost of developing and maintaining software
for the SOS6 and SOSS. It accomplishes this by
creating a programming environment that, for the
most part, is distinct from the architecture of the
CPUs. Registers, segments, addressing modes,
stacks, etc., are effectively "invisible" to the
2-75
8086 AND 8088 CENTRAL PROCESSING.UNITS
'".TRAFFIC DATA RECORDER CONTROL PROGRAM"
. "VERSION 2.2, RELEASE 5,. 23APR79."
"THIS RELEASE FIXES THREE BUGS"
"DOCUMENTED IN PROBLEM REPORT #16."'
"~COMPUTETOTAL
PAYMENT DUE"'
TOTAL = PRINCIPAL + INTEREST;
IF TERMINAL$READY
THEN CALL FILL$BUFFER;
.
....... . .
,
ELSE CALL WAIT (50);
'"WArt 50 MS FOR R'ESPONSE",
Figure 2-46. pLlM-86 Statements and Comments
Table 2-23. PLlM-86 Data Types
TYPE
BYTES
RANGE
US.AGE
1
oto 255
Unsigned Integer, Charact~r
WORD
2
oto 65,535
Unsigned Integer
INTEGER
2
-32,768to .
+32,767
Signed Integer
REAL
4
1 x 10-38 to
3.37 x 10+38
Floating Point
N'A
Address ManipulatiOn
BYTE
.
"
POINTER
.
2'4
.
example, monthly rainfall samples could be
represented as an array of 12 elements; one for
each month:
Variables are defined by writing a DECLARE
statement of this form:
DECLAREscalar~name type;
DECLARERAINFALL (12)REAL;
Options of the DECLARE statement can be used
to specify an initial value for the scalar and to
define a series of items in a shorthand form.
Each element in. an array' isaccessibie by a
number called .a subscript which is the element's
relative location in the array. In Pt/M~86, the
first element in an array has a s).lbscrlpt of O;.it is'
considered the "Otl:l"element. Thus, Ri\INFAL.L
(11) refers to December's sample. The subscript
need not be aconsta~t; variables and expressions
also maybe. ~sed as subscripts.
.
,"".
Besides scalar variables, scalar constants may be
used in .PLlM-86 programs (see figure 2-47).
Constants may be written "as is"or may be given
names to improve pr()gram clarity. .
.
,
Sca.lars can be aggregated into named collections
of data such as arrays and structures. An array is
a . collection of scalars of the same type (all
integer, all real, etc.). Arrays are useful for
representing data that has a repetitive nature. For
Strings of character data are typically. defined as
byte arrays. Characters can be accessed with
subscripts or with powerful string-handling functions built into PLlM-86.
2-76
8086 AND 8088 CENTRAL PROCESSING UNITS
10
OAH
120
00001010B
10.0
1.0E1
'A'
'*DECIMAL NUMBER*'
'*HEXADECIMAL NUMBER*'
'*OCTALNUMBER*'
'*BINARY NUMBER*'
'*FLOATING POINT NUMBER* I
'*FLOATING POINT NUMBER*'
'*CHARACTER*'
'*CONSTANTS MAY BE GIVEN NAMES*'
DECLARE STATUS$PORT LITERALLY 'OFFEH';
DECLARE THRESHOLD LITERALLY '98.6';
Figure 2-47. PL/M-86 Constants
A structure is a collection of related data elements
that do not necessarily have the same type. The
elements are related by virtue of "belonging" to
the entity represented by the structure. Here is a
simple structure declaration:
• structures in arrays may themselves contain
arrays.
Figure 2-48 provides sample PLlM-86 data
declarations.
Assignment Statement
DECLARE BRIDGE STRUCTURE
(SPAN
YR$BUILT
Data that has been defined can be operated on
with PLlM-86 executable statements. The fundamental executable statement is the assignment
statement, written in this form:
WORD,
BYTE,
AVG$TRAFFIC REAL);
. variable-name = expression;
The year the bridge was built could be accessed by
writing BRIDGE. YR$BUIL T; the structure element name is "qualified" by the dot and the
. structure name. This allows structures with the
same element names to be distinguished from
each other (e.g., HIGHWAY.YR$BUILT).
This means "evaluate the expression and assign
(move) the result to the variable."
There are three basic classes of expressions in
PLlM-86; arithmetic, relational and logical (see
table 2-24 and figure 2-49). All expressions are
combinations of operands and operators,
although an expression can consist of a single
operand. Operands are variables and constants;
operators vary according to the type of expression. Evaluation of an expression always yields a
single result; different classes of expressions yield
different types of results.
Arrays and structures can be combined into more
complex data aggregates:
• array elements may be structures rather than
scalars,
• a structure element may be an array,
Table 2-24. Characteristics of PL/M-86 Expressions
EXPRESSION
ARITHMETIC
OPERATORS
+, -, *,', MOD
NUMBER
RELATIONAL
>,<,"',>"',<'"
"TRUE"-FFH
"FALSE"-OH
LOGICAL
AND, OR, XOR, NOT
8/16-BIT STRING
2-77
RESULT
8086 AND 8088 CENTRAL PROCESSING UNITS
,····SCALARS····'
DECLARE SWITCH
DECLARE COUNT
INDEX
DECLARE(NET,GROSS,
BYTE; ,
WORD,
INTEGER;
TOTAL) . REAL;'
'····ARRAYS····,
DECLARE MONTH (12)
BYTE;
DECLARE TERMINAL_LINE (80t:
'····STRUCTURE····'
DECLARE EMPLOYEE STRUCTURE
(lD_NUMBER
DEPARTMENT
RATE
'·1 SCALAR·'
'*1 SCALAR·'
'·3 SCALARS·'
,'BYTE; :
WORD,
BYTE·
REAL);
, •••• ARRAY OF STRUCTURES····'
DECLARE INVENTORY_ITEM (100)
STRUCTURE
(PART_NUMBER
WORD,
ON_HAND
WORD, .'
RE_ORDER
BYTE); . '
, •••• ARRAY WITHIN STRUCTURE····'
DECLARE COUNTY_DATA
STRUCTURE
BYTE,
(NAME (20)
TENc- YR~RAINFALL(10)
BYTE,
PER CAPITA_INCOME
REAL);
"
Figure 2-48. PLlM-86 Data Declarations'
,. ARITHMETIC·'
A=2; B=3;
B=B+1;
C = (A·B) -2;
C = «A·B) + 3) MOD 3;
, '·RELATIONAL·'
A=2;B=3
C=B>A;
C=B<>A;
C= B = (A+1);
'·LOGICAL .,
A = 0011$0001 B;
B = 1000$0001 B;
C= NOTB;
'C=AAND B;
C =; A OR B;
'C= BXORA;
C =,(A ANDB) OR OFOH;
'·BCONTAINS4·1'
,·C CONTAINS
,·C CONTAINS 2·'
6·'
,·C CONTAINS OFFH·'
,·C CONTAINS OFFH ~ ,
,·C CONTAINS OFFH·'
'·$IS FOR RE,ADABILlTY·'
,·C CONTAINS 0111$1110B·'
,·C CON-rAIN.S 0000$0001.8* /' ,
'·CCONTAINS1011$0001B·' .
,·C CONTAINS 1011$0000B·' .
,·C CONTAINS 1111$0001 B·'
Figure 2-49. Expressions in PLlM-86 Assignmerit Statements
.',
,:.
8086 AND 8088 CENTRAL PROCESSING UNITS
A DO block begins with a DO statement and ends
with' an ,.END statement. All intervening
statements are part of the block. A DO block can
appear anywhere in a program that an executable
statement can appear. There are four kinds of DO
statements in PLlM-86: simple DO, DO CASE,
interative DO, and DO WHILE. .
.
Program Flow Statements
Simple PLlM-86 programs can be written with
just DECLARE and assignment statements. Such
programs, however, execute exactly the same
sequence of statements every time they are run
and would not prove very useful. PL/M-86 provides statements that change the flow of control
through a program. These statements allow sections of the program to be executed selectively,
repeated, skipped entirely, etc.
A simple DO statement (figure 2-51) causes all the
statements in the block to be treated as though
they were a single statement. Simple DOs enable it
single IF statement to cause. multiple. statements
to be executed (the alternative would be to repeat
the IF statement for every .statement to· be
executed).
The IF statement (figure 2-50) selects one or the
other of two statements for execution depending
on the result of a relational expression. The IF
~tatementis written:
'"SIMPLE DO"'
A=5; 8=9;
IF (A+2)< 8 THEN DO;
X=X-1;
Y(X)=O;
END;.
ELSE DO;
X=X+1;
Y(X)=1 ;
END;
IF relational-expression
THEN statement1;
ELSE statement2;
Statement1 is executed if the expression is "true";
statement2 is not executed in this case. If the relation is "false," statement! is skipped and statement2 is executed. In determining the "truth" of
an expression, the IF statement only examines the
low-order bit of the result (1="true"). Ti).erefore,
arithmetic and logical expressions also may be
used in an IF statement.
A=3; 8=5;
IFA<8
THEN MINIMUM = 1;
ELSE MINIMUM = 2;
MORE_DATA = OFFH;
IF NOT MORE_DATA
THEN DONE = 1;
ELSE DONE = 0;
'"SKIPPED"'
'"SKIPPED"'
'"DO CASE"'
A=2;
DO CASE (A);
X=X+1;
'"SKIPPED"'
X=X+2;
'*SKIPPED"'
X=X+3.; •• '*EXECUTED"'
X=X+4;
''''SKIPPED* ,
. END;
Figure 2-51. PLlM-86 Simple DO
and DO CASE
'"EXECUTED"'
'"SKIPPED"'
'"SKIPPED"'
'"EXECUTED"'
'"EXECUTED"'
'"EXECUTED"'
.DO CASE (figure 2-51) causes one statement in
the DO block to be selected and executed depending on the result of the expression (usually
arithmetic) written immediately following DO
CASE:
'"NESTED IF STATEMENTS"'
CLOCK_ON = 1; HOU R=24; ALARM=OFF; .
IF CLOCK_ON
THEN IF HOUR = 24
THEN IF ALARM = OFF
THEN HOUR = 0; '"EXECUTED"'
DO CASE arithmetic-expression;
If the expression yields 0, the first statement in the
DO block is executed; if the expression yields 1,
the second statement is executed, etc. A statement
in the DO block may be null (consist of only a
semicolon) to cause no action for selected cases.
DO CASE provides a rapid and easily-understood
. way to respond to data like "transaction codes"
Figure 2-50. PLlM-86. IF Statements
2-79
8086 AND 8088 CENTRAL PROCESSING UNITS
where a different action is required for· each of
many values a code might assume (an alternative
would be an IF statement for every value the code
could assume).
stop-expr again, etc. (The iterative DO is quite
flexible-this is a simplified explanation.)
Iterative DOs are handy for "stepping through"
an array. For example, an array of 10 elements
could be zeroed by:
An iterative DO block (figures 2-52 and 2-53) is
executed from 0 to an infinite number of times
based on the relationship of an index variable to
an expression that terminates execution. The
general form is:
DO I=OT09;
ARRAY(I) = 0;
END;
DO index = start~expr TO stop-expr BY step-expr;
The "BY step-expr" is optional, and the step is
assumed to be 1 if not supplied (the typical case).
When control first reaches the DO statement,
start-expr is evaluated and is assigned to index.
Then index is compared to stop-expr; if index
exceeds stop-expr, control goes to the statement
following the DO block, otherwise the block is
executed. At the end of the block, the result of
step-expr is added to index, and it is compared to
In a DO WHILE (figures 2-52 and 2-54), the
statements are executed repeatedly as long as the
expression following WHILE evaluates to
"true." DO WHILE often can be applied in
situations where an interative DO will not work,
or is clumsy, such as where repetition must be
controlled by a non-integer value. Like an
iterative DO, DO WHILE may be executed from
o times to an infinite number of times.
'*ITERATIVE DO*'
DOI=OT05;
ARRA Y(I)= I;
TOTAL = TOTAL +1 ;
END;
'*1 = 6 ATTHIS POINT*'
'*EXECUTED 6 TIMES* I
'*EXECUTED 6 TIMES*'
'*DOWHILE*'
MORE = 0; SPACE_OK =1;
DO WHILE (MORE AND SPACE_OK);
ITEMS = ITEMS + 1;
'*SKIPPED*'
N TRACKS =
N_TRACKS + 10;
I*SKIPPED* I
IF N_TRACKS >= 999
'*SKIPPED*'
THEN SPACE_OK = 0;
END;
'*DO WHILE*'
CODE = 'A';
DO WHILE (CODE = 'A');
TEMP = TEMP' STEP;
1* EXECUTION STOPS* I
IF TEMP> 98.6
'* AFTER TEMP*'
THEN CODE = '8';
'*EXCEEDS 98.6* I
N_STEPS = N_STEPS + 1;
END;
Figure 2-52. PL/M-86 Iterative DO and DO WHILE
2-80
8086AN08088 CENTRAL PROCESSING UNITS
INDEX-START.
FALSE
OUTOF
RANGE
EXECUTE
BLOCK
EXECUTE
BLOCK
INDEX-INDEX+STEP
Figure 2-54. PLlM-86 DO WHILE Flowchart
activates a procedure defined earlier in the program. The variables listed in "parm-lisi" are
passed to the' procedure, the procedure is
executed, .and then .control returns to the statement following the CALL. Thus, unlike a GOTO,
a CALL· brings control back to the point of
departure.
Figure 2-53. PL/M-86 Iterative DO Flowchart
A GOTO written in the form
GOTO target;
causes an unconditional transfer (branch) to
another statement in the program. The statement
receiving control would be written
target: statement;
where "target" is a label identifying the
statement.
A CALL statement written in the form
CALL proc-name (parm-list);
Procedures
Procedures are "subprograms" that make it
possible to simplify the design of complex programs and to share a single copy of a routine
among programs. A procedure usually is designed
to perform one function; i.e.,to solve one part of
the total problem with which the program is dealing. For example, a program to calculate
paychecks could be broken down into separate
procedures for calculating gross pay, income tax,
Social Security and net pay. The organization of
the "main" program then could be understood at
a glance:
CALL GROSS_PAY;
CALL INCOME_TAX;
CALL SOCIAL_SECURITY;
CALL NET_PAY;
8086 AND 8088 CENTRAL PROCESSING UNITS
Furthermore, the income tax procedure could be
divided into separate procedures for calCulating
state and federal taxes. Procedures, then, provide
a mechanism by which a large, complex problem
can be attacked with a "divide and conquer"
strategy.
a value. Untyped procedures are activated by
CALL statements. Figure 2-55 shows how simple
typed and untyped procedures may be declared
and then activated.
The statements forming the body o{ a procedure
need not exist within the module that activates the
procedure. The activating module can declare the
procedure EXTERNAL, and the LINK-86 utility
will connect the two modules.
A procedure usually is defined early in a program,
but it is only executed when it is referred to by
name in a later PL/M-86 statement. A procedure
can accept a list of variables, called parameters,
that it will use in performing its function. These
parameters may assume different values each time
the procedure is executed.
PLlM-86 procedures can be written to handle
interrupts. Procedures also may be declared
REENTRANT, making them concurrently usable
by different tasks in a multitasking system.
PLlM-86 also has about 50 procedures built into
the language, including facilities for:
PL/M-86 provides two classes of procedures,
typed and untyped. A typed procedure returns a
value to the statement that activates it and, in
addition, may accept parameters from that statement. A typed procedure is activated whenever its
name appears in a statement; the value it returns
effectively takes the place of the procedure name
in the statement. Typed procedures can be used in
all kinds of PLlM"86 expressions. Untyped procedures may accept parameters, but do not return
•
•
•
•
•
converting variables from one type to another
shifting and rotating bits
performing input and output
manipulating strings
activating the CPU LOCK signal.
'"DECLARATION OF A TYPED PROCEDURE THAT
ACCEPTS TWO REAL PARAMETERS AND RETURNS A REAL VALUE"'
AVG: PROCEDURE (X,Y) REAL;
DECLARE (X,Y) REAL;
RETURN (X+Y)'2.0;
END AVG;
'" ACTIVATING A TYPED PROCEDU RE"'
LOW=2.0;
HIGH=3.0;
TOTAL = TOTAL + AVG (LOW,HIGH); '"2.5IS ADDED TO TOTAL"'
'"DECLARATION OF AN UNTYPED PROCEDURE
THAT ACCEPTS ONE PARAMETER"'
TEST: PROCEDURE (X);
DECLARE X BYTE;
IFX=OH THEN
COUNT=COUNT+1;
END TEST;
'"ACTIVATING AN UNTYPED PROCEDURE"'
CALL TEST (ALPHA); '"COUNT IS INCREMENTED
IF ALPHA = 0"'
Figure 2-55. PL/M-86 Procedures
2-82
8086 AND 8088 CENTRAL PROCESSING UNITS
languages. ASM-S6 also simplifies the programmer's "view" of the SOS6/S088 machine instruction set. For example, although there are 2S. different types of· MOV machine instructions, the
programmer always writes a single form of the
instruction:
ASM-86
Programmers who are familiar with the CPU
architecture can obtain complete access to all processor facilities with ASM-S6. Since the execution
unit on both the SOS6 and the SOSS is identical,
both processors use the same assembly language.
Examples of processor features not accessible
through PLlM-S6 that can be utilized in ASM-S6
programs include: software interrupts, the WAIT
and ESC instructions and explicit control of the
segment registers.
MOV destination-operand, source-operand
The assembler generates the correct machineinstruction form based on the attributes of the
source and destination operands (attributes are
covered later in this section). Finally, the ASM-86
assembler performs extensive checks on the consistency of operand definition versus operand use
in instructions, catching many common types of
clerical errors.
An ASM-S6 program often can be written to
execute faster and/or to use less memory than the
same program written in PLlM-S6. This is
because the compiler has a limited "knowledge"
of the entire program and must generate a
generalized set of machine instructions that will
work in all situations,but may not be optimal in a
particular situation. For example, assume that the
elements of an array are to be summed and the
result placed in a variable in memory. The
machine instructions generated by the PLlM-S6
compiler would move the next array element to a
register and then add the register to the sum
variable in memory. An ASM-S6 programmer,
knowing that a register will be "safe" while the
array is summed, could instead add all the array
elements to a register and then move the register
to the sum variable, saving one instruction .execution per array element.
Statements
Compared to many assemblers, ASM-86 accepts a
relaxed statement format (see figure 2-56). This
helps to. reduce clerical errors and allows programmers to format their programs for better
readability. Variable and label names may be up
to 31 characters long and .are not restricted to
alphabetic and numeric characters. In particular,
the underscore (_) may be used to improve\ the
readability oflong names. Blanks may be inserted
freely between identifiers (there are no "column"
requirements), and statements also may span
multiple lines.
It is easier to write assembly language programs in
ASM-S6 than it is in many assembly languages.
ASM-S6 contains powerful data structuring
facilities that are usually found only in high-level
All ASM-S6 statements are classified as instructions or directives. A clear distinction must be
made here between ASM-86 instructions and
; THIS STATEMENT CONTAINS A COMMENT ONLY
AX, [BX + 3]
MOV AX,
[BX + 3]
MOV
AX,
&
[BX+3]
MOV
; TYPICAL ASM-86INSTRIjCTION
; BLANKS NOT SIGNIFICANT
; CONTINUED STATEMENTS
EQU
0
; SIMPLE ASM-86 DIRECTIVE
ZERO
CUR_PROJ EQU
PROJECT [BX] [SI]
; MORE COMPLEX DIRECTIVE
THE_STACK_STARTS_HERE SEGMENT; LONG IDENTIFIER
TIG HT_LOOP: J M P TIG HT_LOOP
; LABELLED ST ATEM ENT
MOV ES: DATLSTRING [SI], AL
; SEGMENT OVERRIDE PREFIX
WAIT: LOCK XCHG AX,SEMAPHORE
; LABEL & LOCK PREFIX
Figure 2-56. ASM-86 Statements
2-S3
Mnemonics © Intel, 1978
8086ANO 8088 CENTRAL PROCESSING UNITS
improve its clarity; all good ASM-86 programs
are thoughtfully commented.
8086/8088 machine instructions. The assembler
generates machine instructions from ASM-86
instructions· written· by a programmer. Each
ASM-86 instruction produces one machine
instruction, but the form of the generated
machine instruction will vary according to the
operands written in the ASM-86 instruction. For
example, writing
.
Writing a directive gives ASM-86 information to
use in generating instructions, but does not itself
produce a machine instruction. About 20 different directives are available in ASM-86. Directives are written like this:
(name) mnemonic (operand(s)) (;comment)
·Mov BL,1
Some directives require a name to be present,
while others prohibit a name. ASM-86 recognizes
the directive from the mnemonic keyword written
in the next field. Any operands required by the
directive are written next, separated by commas.
A comment may be written as the last field of a
directive.
produces a byte-immediate-to-register MOV,
while writing
MOV TERMINAL_NO,BX
produces a word-register-to-memory MOV. To
the programmer, though, there is simply a MOV
source-to-destination instruction.
Some of the more commonly used directives
define procedures (PROC), allocate storage for
variables (DB, OW, DO) give a descriptive name
to a number or an expression (EQU), define the
bounds of segments (SEGMENT and ENDS),
and force instructions and data to be aligned at
word boundaries (EVEN).
ASM-86 instructions are written in the form:
(label:) (prefix) mnemonic (operand(s)) (;comment)
where parentheses denote optional fields (the
parentheses are not actually written by programmers). The label field names the storage location
containing the machine instruction so that it can
be referred to symbolically as the target of a JMP
instruction elsewhere in the program. Writing a
prefix causes ASM-86 to generate one of the
special prefix bytes (segment override, bus lockor
repeat) immediately preceding the machine
instruction. The mnemonic identifies the type of
instruction (MOV for move, ADD for add, etc.)
that is to be generated. Zero, one or two operands
may be· written next, separated by commas,
according to the requirements of the instruction.
Finally, writing a semicolon signifies that what
follows is a comment. Comments do not affect
the execution of a program, but they can greatly
MOV
MOV
ADD
OCTAL_8
OCTAL_9
ALL_ONES
MINUS_5
MINUS_6
STRING [SI], 'A'
STRING [SI], 41 H
AX,OC4H
EQU 100
EQU 10Q
EQU 11111111B
EQU -5
EQU -6D
Constants
Binary, decimal, octal and hexadecimal numeric
constants (see figure 2-57) may be written in
ASM-86 statements; the assembler can perform
basic arithmetic operations on these as well. All
numbers must, however, be integers and must be
representable in 16 bits including a sign bit.
Negative numbers are assembled in standard
two's complement notation.
Character constants are enclosed in single quotes
and may be up to 255 characters long when used
; CHARACTER
; EQUIVALENT IN HEX
; HEX CONSTANT MUST START WITH NUMERAL
; OCTAL
; OCTAL ALTERNATE
; BINARY
.
; DECIMAL
; DECIMAL ALTERNATE
Figure 2-57. ASM-86 Constants
Mnemonics © Intel, 1978
2-84
8086 AND 8088 CENTRAL PROCESSING UNITS
ing segment. Type identifies the variable's allocation unit (1 = byte, 2 = word, 4 = doubleword).
When a variable is referenced in an instruction,
ASM-86 uses these attributes to determine what
form of the instruction to generate. If the
variable's attributes conflict with its usage in an
instruction, ASM-86 produces an error message.
For example, attempting to add a variable defined
as a word to a byte register is an error. There are
cases where the assembler must be explicitly told
an operand's type. For example, writing MOVE
[BX],5 will produce an error message because the
assembler does not know if [BX] refers to a byte,
a word or a doubleword. The following operators
can be used to provide this information: BYTE
PTR, WORD PTR and DWORD PTR. In the
previous example, a word could be moved to the
location referenced by [BX] by writing MOVE
WORD PTR [BX],5.
to initialize storage. When used as immediate
operands, character constants may be one or two
bytes long to match the length of the destination
operand.
Defining Data
Most ASM-86 programs begin by defining the
variables with which they will work. Three directives, DB, DW and DD, are used to allocate and
name data storage locations in ASM-86 (see
figure 2-58). The directives are used to define
storage in three different units: DB means
"define byte," DW means "define word," and
DD means "define doubleword." The operands
of these directives tell the assembler how many
storage units to allocate and what initial values, if
any, with which to fill the locations.
A_SEG
ALPHA
BETA
GAMMA
DELTA
EPSILON
A_SEG
SEGMENT
DB
?
DW
?
DD
'1
DB
?
DW
5
ENDS
B_SEG
IOTA
KAPPA
LAMBDA
MU
B_SEG
SEGMENT AT 55H ; SPECIFYING BASE ADDRESS
DB
'HELLO'
; CONTAINS 48454C4C4F H
DW
'AB'
; CONTAINS 42 41 H
DD
B_SEG
; CONTAINS 0000 5500 H
100DUPO ;CONTAINS(100X)00H
DB
ENDS
ASM-86 also provides two built-in operators,
LENGTH and SIZE, that can be written in
ASM-86 instructions along with attribute
information. LENGTH causes the assembler to
return the number of storage units (bytes, words
or doublewords) occupied by an array. SIZE
causes ASM-86 to return the total number of
bytes occupied by a variable or an array. These
operators and attributes make it possible to write
generalized instruction sequences that need not be
changed (only reassembled) if the attributes of the
variables change (e.g., a byte array is changed fo a
word array). See figure 2-59 for an example of
using the attributes and attribute operators.
; NOT INITIALIZED
; NOT INITIALIZED
; NOT INITIALIZED
; NOT INITIALIZED
; CONTAINS 05H'
ATTRIBUTES
OPERATORS
VARIABLE
SEGMENT
OFFSET
TY.PE
LENGTH
SIZE
ALPHA
BETA
GAMMA
DELTA
EPSILON
IOTA
KAPPA
LAMBDA
MU
A_SEG
A_SEG
A_SEG
A_SEG
A_SEG
B_SEG
B_SEG
B_SEG
B_SEG
0
1
2
4
1
1
1
1
1
5
1
1
2
4
1
2
5
2
4
100
1
3
7
8
0
5
7
11
1
2
1
2
4
1
1
100
Records
ASM-86 provides a means of symbolically defining individual bits and strings of bits within a byte
or a word. Such' a definition is called a record,
and each named bit string (which may consist of a
single bit) in a record is called a field. Records
promote efficient use of storage while at the same
time improving the readability of the program
and reducing the likelihood of clerical errors.
Defining a record does not allocate storage;
rather, a record is a template that tells the
assembler the name and location of each bit field
within the byte or word. When a field name is
written later in an instruction, ASM-86 uses the
record to generate an immediate mask for instructions like TEST, AND, OR, etc., or an immediate
count for shifts and rotates. See figure 2-60 for an
example of using a record.
Figure 2-58. ASM-86 Data Definitions
For every variable in an ASM-86 program, the
assembler keeps track of three attributes: segment, offset and type. Segment identifies the segment that contains the variable (segment control
is covered shortly). Offset is the distance in bytes
of the variable from the beginning of its contain2-85
8086 AND 8088 CENTRAL PROCESSING UNITS
; SUM THE CONTENTS OF TABLE INTO AX
TABLE
DW
50 DUP(?)
; NOTE SAME INSTRUCTIONS WOULD WORK FOR
; TABLE
DB
25 DUP(?)
; TABLE
DW
118 DUP(?), ETC.
SUB
MOV
MOV
AX,AX
; CLEAR SUM
CX, LENGTH TABLE; LOOP TERMINATOR
;POINT SUBSCRIPT
SI, SIZE TABLE
; TO END OF TABLE
ADD_NEXT: SUB
SI, TYPE TABLE
; BACK UP ONE ELEMENT
ADD
. AX, TABLE [SI]
; ADD ELEMENT
LOOP
ADD_NEXT
; UNTIL CX = 0
; AX CONTAINS SUM
Figure 2-59. Using ASM-86 Attributes and Attribute Operators
EMP _BYTE DB ?
; 1 BYTE, UNINITIALIZED
; BIT DEFINITIONS:
7-2
: YEARS EMPLOYED
1
: SEX (1 = FEMALE)
o : STATUS (1 = EXEMPT)
;RECORD DEFINED HERE
EMP _BITSRECORD
&
YRS_EMP : 6,
&
SEX: 1,
&
STATUS: 1
..
; SELECT NONEXEMPT FEMALES EMPLOYED 10 + YEARS
AL, EMP _BYTE
; KEEP ORIGINAL INTACT
MOV
TEST
AL, MASK SEX
; FEMALE?
JZ
REJECT
; NO, QUITE
AL, MASK STATUS ; NONEXEMPT?
TEST
JNZ
REJECT
;NO, QUIT
SHR
AL, CL
; ISOLATE YEARS
AL,11
; >=10 YEARS?
CMP
JL
REJECT
; NO, QUIT
; PROCESS SELECTED EMPLOYEE
.REJECT: ; PROCESS REJECTED EMPLOYEE
; RECORD USED HERE
; GET SHIFT COUNT
MOV
Figure 2-60. Using an ASM-86 RECORD Definition
Mnemonics © Intel, 1978
2-86
8086 AND 8088 CENTRAL PROCESSING UNITS
Structures
Addressing Modes
An ASM-86 structure is a map, or template, that
gives names and attributes (length, type, etc.) to a
collection of fields. Each field in a structure is
defined using DB, DW and DD directives;
however, no storage is allocated to the structure.
Instead, the structure becomes associated with a
particular area of memory when a field name is
referenced in an instruction along with a base
value. The base value "locates" the structure; it
may be a variable name or a base register (BX or
BP). The structure may be associated with
another area of memory by specifying a different
base value. Figure 2-61 shows how a simple structure may be defined and used. Note that a structure field may itself be a structure, allowing much
more complex organizations to be laid out.
Figure 2-62 provides sample ASM-86 coding for
each of the 8086/8088 addressing modes. The
assembler interprets a bracketed reference to BX,
BP, SI or DI as a base or index register to be used
to construct the effective address of a memory
operand. An unbracketed reference means the
register itself is the operand.
The following cases illustrate typical ASM-86
coding for accessing arrays and structures, and
show which addressing mode the assembler
specifies in the machine instruction it generates:
o
the element indexed by SI, and ALPHA
lSI + 1] is the following byte (indexed).
o
Structures are particularly useful in situations
where the same storage format is at multiplelocations, where the location of a collection of
variables is not known at assembly-time, and
where the location of a collection of variables
changes during execution. Applications include
multiple buffers for a single file, list processing
and stack addressing.
If ALPHA is the base address of a structure
and BETA is a field in the structure, then
ALPHA.BET A selects the BETA. field
(direct).
o
If register BX contains the base address of a
structure and BETA is a field in the structure, then [BX].BET A refers to the BETA
field (based).
EMPLOYEE
SSN
RATE
DEPT
YR_HIRED
EMPLOYEE
STRUC
DB 9
DB 1
DW 1
DB 1
ENDS
DUP(?)
DUP(?)
DUP(?)
DUP(?)
MASTER
TXN
DB
DB
DUP(?)
DUP(?)
12
12
If ALPHA is an array, then ALPHA lSI] is
; CHANGE RATE IN MASTER TO VALUE IN TXN.
MOV
AL, TXN:RATE
MOV
MASTER~RATE, AL
; ASSUME BX POINTS TO AN AREA CONTAINING
DATA IN THESAME FORMATASTHE EMPLOYEE
STRUCTURE. ZERO THE SECOND DIGIT
OFSSN
MOV
SI,1; INDEX VALUE OF 2ND DIGIT
MOV
[BX].SSN[SI],O
Figure 2-61. Using an ASM-86 Structure
2-87
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
IN
OUT
AX,BX
AL,5
CX, ALPHA
ALPHA,6
ALPHA,DX
BL, [BX]
[SI], BH
[PP].ALPHA, AH
CX, ALPHA [SI]
ALPHA [DI+2], 10
[BX].ALPHA [SI], AL
SI, [BP+4] [DI]
AL,30
DX,AX
; REGISTER - REGISTER
; REGISTER -IMMEDIATE
; REGISTER - MEMORY (DIRECT)
; MEMORY (DIRECT) -IMMEDIATE
; MEMORY (DIRECT) - REGISTER
; REGISTER - MEMORY (REGISTER INDIRECT)
; MEMORY (REGISTER INDIRECT) -IMMEDIATE
; MEMORY (BASED) - REGISTER
; REGISTER - MEMORY (INDEXED)
; MEMORY (INDEXED) -IMMEDIATE
; MEMORY (BASED INDEXED) - REGISTER
; REGISTER - MEMORY (BASED INDEXED)
; DIRECT PORT
; INDIRECT PORT
Figure 2-62. ASM-86 Addressing Mode Examples
•
If register BX contains the address of an
array, then [BX] lSI] refers to the element
indexed by SI (based indexed).
•
If register BX points to a structure whose
instructions written between SEGMENT and
ENDS are part of the named segment. In small
programs, variables often are defined in one or
two segment(s), stack space is allocated in another
segment, and instructions are writteri in a third or
fourth segment. It is perfectly possible, however,
to write a complete program in one segment; if
this is done, all the segment registers will contain
the same base address; that is, the memory
segments will completely overlap. Large programs may be divided into dozens of segments.
ALPHA field is an array, then [BX]
.ALPHA lSI] selects the element indexed by
SI (based indexed).
•
If register BX points to a structure whose
ALPHA field is itself a structure, then
[BX].ALPHA.BETA refers to the BETA
field of the ALPHA substructure (based).
•
The first instructions in a program usually
establish the correspondence between segment
names and segment registers, and then load each
segment register with the base address of its corresponding segment. The ASSUME directive tells
the assembler what addresses will be in the segment registers at execution time. The assembler
checks each memory instruction operand, determines which segment it is in and which segment
register contains the address of that segment. If
the assumed register is the register expected by the
hardware for that instruction type, then the
assembler generates the machine instruction normally. If, however, the hardware expects one segment register to be used, and the operand is not in
the segment pointed to by that register, then the
assembler automatically precedes the machine
instruction with a segment override prefix byte.
(If the segment cannot be overridden, the
assembler produces an error message.) An example may clarify this. If register BP is used in an
instruction, the 8086 and 8088 CPUs expect, as a
default, that the memory operand will be located
in the segment pointed to by SS-in the current
If register BX points to a structure and the
ALPHA field of the structure is an array and
each element of ALPHA is a structure, then
[BX].ALPHA[SI + 3].BETA refers to the
field BET A in the element of ALPHA
indexed by lSI + 3] (based indexed).
Note that DI may be used in place of SI in these
cases and that BP may be substituted for BX.
Without a segment override prefix, expressions
containing BP refer to the current stack segment,
and expressions containing BX refer to the current data segment.
Segment Control
An ASM-86 program is organized into a series of
named segments. These are "logical" segments;
they are eventually mapped into 8086/8088
memory segments, but this usually is not done
until the program is located. A SEGMENT directive starts a segment, and an ENDS directive ends
the segment (see figure 2-63). All data and
Mnemonics © Intel. 1978
2-88
8086 AND 8088 CENTRAL PROCESSING UNITS
DATA_SEG
SEGMENT
; DATA DEFINITIONS GO HERE
DATA_SEG
ENDS
STACK_SEG SEGMENT
; ALLOCATE 100 WORDS FOR A STACK AND
LABEL THE INITIAL TOS FOR LOADING SP.
DW 100 DUP(?)
ST ACK TOP LABEL WORD
STACK_SEG
ENDS
CODE_SEG
SEGMENT
; GIVE ASSEMBLER INITIAL REGISTER-TO-SEGMENT
; CORRESPONDENCE. NOTE THAT IN THIS
; PROGRAM THE EXTRA SEGMENT INITIALLY
; OVERLAPS THE DATA SEGMENT ENTIRELY.
ASSUME CS: CODE_SEG,
&
DS: DATA_SEG,
&
ES: DATA_SEG,
&
SS: STACK_SEG
START:
; THIS IS THE BEGINNING OFTHE PROGRAM.
; LOC-86 WILL PLACE A JMP TO THIS
; LOCATION AT ADDRESS FFFFOH.
; LOAD THE SEGMENT REGISTERS. CS DOES NOT
HAVE TO BE LOADED BECAUSE SYSTEM
RESET SETS IT TO FFFFH, AND THE
LONG JMP INSTRUCTION AT THAT ADDRESS
U PDATES.IT TO TH E ADDRESS OF CODE_SEG.
SEGMENT REGISTERS ARE LOADED FROM AX
BECAUSE THERE IS NO IMMEDIATE-TOSEGMENT_REGISTER FORM OF THE MOV
INSTRUCTION.
MOV AX, DATA_SEG
MOV DS, AX
MOV ES, AX
MOV AX, STACK_SEG
MOV SS, AX
. ; SET STACK POINTER TO INITIAL TOS.
MOV SP, OFFSET STACK_TOP
; SEGMENTS ARE NOW ADDRESSABLE.
; MAIN PROGRAM CODE GOES HERE.
CODE_SEG
ENDS
; NEXT STATEMENT ENDS ASSEMBLY ANDTELLS
LOC-86 THE PROGRAMS STARTING ADDRESS.
END
START
Figure 2-63. Setting Up ASM-86 Segments
2-89
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
stack segment. A programmer may, however,
choose to use BP to address a variable in the current data segment-the segment pointed to by
DS. The ASSUME directive enables the assembler
to detect this situation and to automatically
generate the needed override prefix.
PLlM-86. Figure 2-64 shows how procedures
may be defined and called in ASM-86. Section
2-10 contains examples of procedures that accept
parameters on the stack.
LlNK-86
It also is possible for a programmer to explicitly
code segment override prefixes rather than relying
on the assembler. This may result in a somewhat
better-documented program since attention is
called to the override. The disadvantage of
explicit segment overrides is that the assembler
does not check whether the operand is in fact
addressable through the overriding segment
register.
Fundamentally, LINK-86 combines separate
relocatable object modules into a single program.
This process· consists primarily of combining
(logical) segments of the same name into single
segments, adjusting relative addresses when
segments are combined, and resolving external
references.
A programmer can use a procedure that is actually contained in another module by naming the
procedure in an ASM-86 EXTRN directive, or
declaring the procedure to be EXTERNAL in
PLlM-86. The procedure is defined or declared
PUBLIC in the module where it actually resides,
meaning that it can be used by other modules.
When LINK-86 encounters such an external
reference, it searches through the other modules
in its input, trying to find the matching PUBLIC
declaration. If it finds the referenced object, it
links it to the reference, "satisfying" the external
reference. If it cannot satisfy the reference,
LINK-86 prints a diagnostic message. LINK-86
also checks PLlM-86 procedure calls and functioh references to insure that the parameters
passed to a procedure are the type expected by the
procedure.
ASM-86, in conjunction with the relocation and
linkage facilities, provides much more
sophisticated segment handling capabilities than
have been described in this introduction. For
example, different logical segments may be combined into the same physical segment, and
segments may be assigned the same physicallocations (allowing a "common" area to be accessed
by different programs using different variable
and label names).
Procedures
Procedures may be written in ASM-86 as well as
in PL/M-86. In fact, procedures written in one
language are callable from the other, provided
that a few simple conventions are observed in the
ASM-86 program. The purpose of ASM-86 procedures is the same as in PLlM-86: to simplify the
design of complex programs and to make a single
copy of a commonly-used routine accessible from
. anywhere in the program.
LINK -86 gives the programmer, particularly the
ASM-86 programmer, great control over
segments (segments may be combined end to end,
renamed, assigned the same locations, etc.).
LINK-86 also produces a map that summarizes
the link process and lists any unusual conditions
encountered. While the output of LINK-86 is
generally input to LOC-86, it also may again be
input to LINK-86 to permit modules to be linked
in incremental groups.
An ASM-86 program activates a procedure with a
CALL instruction. The procedure terminates with
a RET instruction, which transfers control to the
instruction following the CALL. Parameters may
be passed in registers or pushed onto the stack
before calling the procedure. The RET instruction
can discard stack parameters before returning to
the caller.
LOC-86
LOC-86 accepts the single relocatable object
module produced by LINK-86 and binds the
memory references in the module to actual
memory addresses. Its output is an absolute
object module ready for loading into the memory
of an execution vehicle. LOC-86 also inserts a
Unlike PL/M-86 procedures, ASM-86 procedures
are executable where they are coded, as well as by
a CALL instruction. Therefore, ASM-86 procedures often are defined following the main program logic, rather than preceding it as in
Mnemonics © Intel, 1978
2-90
8086 AND 8088 CENTRAL PROCESSING UNITS
FREQUENCY
DB
256 DUP (0)
USART_DATA
USART_STAT
EQU
EQU
OFFOH
OFF2H
NEXT:
CALL
CALL
JMP
CHAR_IN
COUNT_IT
NEXT
; DATA PORT ADDRESS
; STATUS PORT ADDRESS
CHAR_IN
PROC
; THIS PROCEDURE DOES NOTTAKE PARAMETERS.
IT SAMPLES THE USART STATUS PORT
UNTIL A CHARACTER IS READY, AND
THEN READS THE CHARACTER INTO AL
MOV
DX, USART_STAT
IN
AL, DX
; READ STATUS
AGAIN:
AND
AL,2
; CHARACTER PRESENT?
JZ
AGAIN
; NO, TRY AGAIN
MOV
DX, USART_DATA
IN
AL, DX
; YES, READ CHARACTER
RET
CHAR_IN
ENDP
COUNT_IT
PROC
; THIS PROCEDURE EXPECTS A CHARACTER IN AL.
IT INCREMENTS A COUNTER IN A FREQUENCY
TABLE BASED ON THE BINARY VALUE OF
THE CHARACTER.
AH, AH
; CLEAR HIGH BYTE
XOR
MOV
SI, AL
; INDEX INTO TABLE
INC
FREQUENCY [S1; BUMP THE COUNTER.
RET
ENDP
Figure 2-64. ASM-86 Procedures
are a convenient way to make collections of
modules available to L1NK-86. When a module
being linked refers to "external" data or instruc~
tions, L1NK-86 can automatically search a series
of libraries, find the referenced module, and
include it in the program being created.
direct inter segment JMP instruction at location
FFFFOH. The target of the JMP instruction is the
logical beginning of the program. When the 8086
or 8088 is. reset, this instruction is automatically
executed to restart the system. LOC-86 produces
a memory map of the absolute object module and
a table showing the address of every symbol
defined in the program.
OH·86
OH-86 converts an absolute object module into
Intel's standard hexadecimal format. This format
is used by some PROM programmers and system
loaders, such as the iSBC 957™ and SDK-86
loaders.
LIB·86
L1B-86 is a valuable adjunct to the R & L programs. It is used to maintain relocatable object
modules in special files called libraries. Libraries
2-91
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
CONV-86
Users who have developed substantial, fullytested assembly language programs for the
8080/8085 microprocessors may want to use
CONV-86 to automatically convert large amounts
of this code into ASM-86 source code (see figure
2-65). CONV-86 accepts an ASM-80 source program as input and produces an ASM-86 source
program as output, plus a print file that
documents the conversion and lists any diagnostic
messages.
CONV·86
,-,
- - __ (
_"'I~.a
Some programs cannot be completely converted
by CON V-86. Exceptions include:
•
•
•
•
self-modifying code,
software timing loops,
8085 RIM and SIM instructions,
interrupt code, and
•
macros.
1----I.
~
)
1.J
rEDiTE57
---.l ASM·86
.., SOURCE
I
~~~~
ASM-86
ASSEMBLER
By using the diagnostic messages produced by
CONV-86, the converted ASM-86 source file can
be manually edited to clean up any sections not
converted. A converted program is typically
10-20070 larger than the ASM-80 version and does
not take full advantage of the 8086/8088 architecture. However, the development time saved by
using CONY -86 can make it an attractive alternative to rewriting working programs from
scratch.
Figure 2-65. ASM-80/ ASM-86 Conversion
The dice program runs on an SDK-86 that is connected to an Intellec® Microcomputer Development System. The program displays two continuously changing digits in the upper left corner
of the Intellec display. The digits are random
numbers in the range 1-6. A roll is started by
entering a monitor GO command. Pressing the
INTR key on the SDK-86 keypad stops the roll.
Sample Programs
There are two procedures in the PL/M-86 version
of the dice program. The first is called CO for
console output. This is an untyped PUBLIC procedure that is supplied on an SDK-C86 diskette.
CO is written in PLlM-86 and outputs one
character to the Intellec console. It is declared
EXTERNAL in the dice program because it exists
in another module .. LINK-86 searches the
SDK-C86 library for CO and includes it in the
single relocatable object module it builds.
Figures 2-66 and 2-67 show how a simple program
might be written in PLlM-86 and ASM-86. The
program simulates a pair of rolling dice and
executes on an Intel SDK-86 System Design Kit.
The SDK-86 is an 8086-based computer with
memory, parallel and serial I/O ports, a keypad
and a display. The SDK-86is implemented on a
single PC board which includes a large prototype
area for system expansion and experimentation.
A ROM-based monitor program provides a user
interface to the system; commands are entered
through the keypad and monitor responses are
written on the display. With the addition of a
cable and software interface (called SDK-C86),
the SDK-86 may be connected to an Intellec®
Microcomputer Development· System. In this
mode, the user enters monitor commands from
the Intellec keyboard and receives replies on the
Intellec CRT display.
Mnemonics © Intel, 1978
EDIT
RANDOM is an internal typed procedure; it is
contained in the dice module and returns a word
value that is a random number between 1 and 6.
RANDOM does not use any parameters and is
activated in the parameter list passed to CO.
When CO is called like this, first RANDOM is activated, then 30 is added to the number it returns
and the sum is pa.ssed to CO.
2-92
8086 AND 8088 CENTRAL PROCESSING UNITS,
PL/M-86 COMPILER
DICE
ISIS-II PL/M-86 Vl.2 COMPILATION OF MODULE DICE
OBJECT MODULE PLACED IN :Fl:DICE.OBJ
COMPILER INVOKED BY: PLM86 :Fl:DICE.P86 XREF
DICE: DO;
I" THIS PROGRAM SIMULATES THE HOLL OF A PAIR OF CICE "I
I" GIVE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
2
3
ij
5
6
NAMES TO CONSTANTS "I
CLEAR$CRTl
LITERALLY
CLEAR$CRT2
LITERALLY
HOME$CURSORl
LITERALLY
HOME$CURSOR2
LITERALLY
SPACE
LITERALLY
I" PROGRAM VARIABLES "I
DECLARE (RANDOM$NUMBER,SAVE)
8
1
9
10
2
2
'OlBH';
'Oij5H';
'OlBH';
'Oij8H';
'020H';
I" INTELLEC "I
CRT
"I
CONTROL "/
CODES
"/
I"ASCII BLANK"/
I~
I"
I"
WORD;
I" CONSOLE OUTPUT PROCEDURE "I
CO:
PROCEDURE(X) EXTERNAL;
DECLARE X
BYTE;
END CO;
I" RANDOM NUMBER GENERATOR PROCEDURE
I" ALGORITHM FOR 16-BIT RANDOM NUMBER FROM:
"I
"I
"A GUIDE TO PL/M PROGRAMMING FOR
"I
MICROCOMPUTER APPLICATIONS,"
*1
I"
DANIEL D. MCCRACKEN,
"I
I"
ADDISON-WESLEY, 1978
*1
RANDOM: PROCEDURE WORD;
RANDOM$NUMBER = SAVE;
I"START WITH OLD NUMBER"I
RANDOM$NUMBER = 2053 " RANDOM$NUMBER + 138ij9;
SAVE = RANDOM$NUMBER;
I"SAVE FOR NEXT TIME"I
I"FORCE 16-BIT NUMBER INTO RANGE 1-6"1
RANDOM$NUMBER = RANDOM$NUMBER MOD 6 + 1;
RETURN RANDOM$NUMBER;
END RANDOM;
1*
I"
11
12
13
lij
1
2
2
2
15
16
17
2
2
2
I" MAIN ROUTINE *1
1* CLEAR THE SCREEN*I
18
19
CALL CO(CLEAR$CRT1);
CALL CO(CLEAR$CRT2);
1* ROLL THE DICE UNTIL INTERRUPTED "I
DO WHlhE 1;
I*"DO FOREVER""I
I"NOTE THAT ADDING 30 TO THE DIE VALUE "I
I" CONVERTS IT TO ASCII.
"I
CALL CO(RANDOM + 030H);
1"1ST DIE"I
CALL CO (SPACE) ;
I*BLANK"I
CALL CO(RANDOM + 030H);
1*2ND DIE"I
I" HOME THE CURSOR *1
CALL CO(HOME$CURSOR1);
CALL CO(HOME$CURSOR2);
END;
20
21
22
23
2
2
2
2ij
25
26
2
2
2
27
END DICE;
CROSS-REFERENCE LISTING
DEFN
ADDR
SIZE
NAME, ATTRIBUTES, AND REFERENCES
--------------------------------
2
CLEARCRTl
LITERALLY
18
3
CLEARCRT2
LITERALLY
19
CO
PROCEDURE EXTERNAL(O) STACK=OOOOH
2ij
21
22
18
25
19
23
OOOOH
0002H
11
00ij9H
71
ijij
DICE
PROCEDURE STACK=OOOijH
HOMECURSORl
LITERALLY
2ij
HOMECURSOR2
LITERALLY
25
RANDOM
PROCEDURE WORD STACK=0002H
21
23
Figure 2-66. Sample PL/M-86 Program
2-93
8086 AND 8088 CENTRAL PROCESSING UNITS
OOOOH
2
0002H
2
OOOOH
RANDOMNUMBER
WORD
12
13
SAVE
WORD
12
14
SPACE
LITERALLY
2,2
X
BYTE PARAMETER
9
14
15
16
MODULE INFORMATION:
CODE ,AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
51 LINES RE~D
o PROGRAM ERROR(S)
0075H
OOOOH
0004H
0004H
1170
00
40
40
END OF PL/M-86 COMPILATION
Figure 2-66. Sample PL/M-86 Program (Cont'd.)
MCS-86 MACRO ASSEMBLER
DICE
ISIS-II MCS-86 MACRO ASSEMBLER V2.0 ASSEMBLY OF MODULE DICE
OBJECT MODULE PLACED IN :Fl:DICE.OBJ
ASSEMBLER INVOKED BY: ASM86 :fl:DICE.A86 XREF
LOC
OBJ
LINE
1
2
3
4
5
6
7
8
9
10
1,1
0000
0002
0004
0006
0008
OOOA
lBOO
4500
lBOO
4800
2000
????
0000 (20
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SOURCE
THIS PROGRAM ,SIMULATES THE ROLL OF A PAIR OF DICE
CONSOLE OUTPUT PROCEDURE
EXTRN
CO: NEAR
; SEGMENT GROUP DEFINITIONS NEEDED FOR PL/M-86 COMPATIBILITY
CGROUP GROUP
CODE
DGROUP GROUP
DATA,STACK
INFORM ASSEMBLER OF SEGMENT REGISTER CONTENTS.
ASSUME CS:CGROUP,Di:DGROUP,SS:DGROUP,ES:NOTHING
; ALLOCATE DATA
DATA
SEGMENT PUBLIC 'DATA'
NOTE THAT THE FOLLOWING ARE PASSED ON THE STACK TO THE PL/M-86
PROCEDURE 'CO'. BY CONVENTION, A BYTE PARAMETER IS PASSED IN
THE LOW-ORDER 8-BITS,OF A WORD ON THE STACK. HENCE, THESE ARE
; DEFINED AS WORD VALUES, THOUGH THEY OCCUPY 1 BYTE ONLY.
CLEAR CRTl
OW
01 BH
INTELLEC
CLEAR-CRT2
OW
045H
CRT
HOME CURSOR 1
OW
01 BH
CONTROL
HOMCCURSOR2
OW
048H
CODES
SPACE
OW
020H
ASCII BLANK
SAVE
OW
HOLDS LAST 16-BIT RANDOM NUMBER
DATA
ENDS
; ALLOCATE STACK SPACE
STACK
SEGMENT STACK
'STACK'
DW
20 DUP (?)
????
0028
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0000
0000 Al0AOO
45
46
47
; LABEL INITIAL TOS: FOR LATER USE.
STACK TOP
LABEL
WORD
STACK- ENDS
; PROGRAM CODE
CODE
SEGMENT PUBLIC
'CODE'
RANDOM NUMBER GENERATOR PROCEDURE
ALGORITHM FOR 16-BIT RANDOM NUMBER FROM:
"A GUIDE TO PL/M PROGRAMMING FOR
MICROCOMPUTER APPLICATIONS,"
DANIEL D. MCCRACKEN
;
ADDISON-WESLEY, 1978
RANDOM PROC
MOV
AX,SAVE
; NEW NUMBER
Figure 2-67. ASM-86 Sample Program
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
MCS-86 MACRO ASSEMBLER
DICE
LOC
OBJ
LINE
0003
0006
0008
OOOB
B90508
F7El
051936
A30AOO
OOOE
0010
0013
0015
0017
0018
2BD2
B90600
F7Fl
8BC2
40
C3
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
0019 B8---001C 8ED8
001E 8EDO
0020 BC2800
0023
0027
002A
002E
FF360000
E80000
FF360200
E80000
0031
0034
0036
0037
003A
003E
0041
0044
0046
0047
E8CCFF
0430
50
E80000
FF360800
E80000
E8BCFF
0430
50
E80000
004A
004E
0051
0055
FF360400
E80000
FF360600
E80000
R
E
R
E
0058 EBD7
SOURCE
RANDOM
MOV
CX, 2053
OLD NUMBER • 2053
MUL
CX
+ 13849
ADD
AX,13849
MOV
SAVE,AX
SAVE FOR NEXT TIME
; FORCE 16-BIT NUMBER INTO RANGE 1 - 6
, BY MODULO 6 DIVISION + 1
SUB
OX, OX
CLEAR UPPER DIVIDEND
MOV
CX,6
SET DIVISOR
CX
DIVIDE BY 6
DIV
MOV
AX, OX
REMAINDER TO AX
AX
ADD 1
INC
RESULT IN AX
RET
ENDP
MAIN PROGRAM
LOAD SEGMENT REGISTERS
NOTE PROGRAM DOES NOT USE ES; CS IS INITIALIZED BY HARDWARE RESET;
DATA & STACK ARE MEMBERS OF SAME GROUP, SO ARE TREATED AS A SINGLE
; MEMORY SEGMENT POINTED TO BY BOTH OS & SS.
START: MOV
AX,DGROUP
MOV
DS,AX
MOV
SS ,AX'
INITIALIZE STACK POINTER
MOV
SP,OFFSET DGROUP:STACK_TOP
CLEAR THE SCREEN
PUSH
CLEAR CRTl
CALL
CO
PUSH
CLEAR CRT2
CALL
CO
; ROLL THE DICE UNTIL INTERRUPTE
ROLL:
CALL
RANDOM
ADD
AL,030H
PUSH
AX
CALL
CO
PUSH
SPACE
CALL
CO
CALL
RANDOM
ADD
AL,030H
PUSH
AX
CALL
CO
HOME THE CURSOR
PUSH
HOME CURSORl
CALL
CO
PUSH
HOME CURSOR2
CALL
CO
CONTINUE FOREVER
JMP
ROLL
CODE
ENDS
GET 1ST DIE IN AL
CONVERT TO ASCII
PASS IT TO
CONSOLE ,OUTPUT
OUTPUT
A BLANK
GET 2ND DIE IN AL
CONVERT TO ASCII
PASS IT TO
CONSOLE OUTPUT
XREF SYMBOL TABLE LISTING
NAME
TYPE
SEGMENT
GROUP
V WORD
V WORD
co.
L NEAR
CODE.
SEGMENT
SEGMENT
DATA.
DGROUP.
GRODP
flOME CURSOR 1. V WORD'
HOMCCURSOR2. V WORD
RANDOM.
L NEAR
L NEAR
ROLL.
V WORD
SAVE.
SPACE
V WORD
SEGMENT
STACK
STACK TOP
V WORD
START-.
L NEAR
??SEG
CGROUP.
CLEAR CRT 1.
CLEAR:::CRT2.
VALUE
OOOOH
0002H
OOOOH
0004H
0006H
00 DOH
0031H
OOOAH
0008H
0028H
0019H
ATTRIBUTES, XREFS
SIZE=OOOOH PARA
CODE
711 11
DATA 1911 77
DATA 2011 79
EXTRN 411 78 80
SIZE=005AH PARA
SIZE=OOOCH PARA
DATA STACK
811
DATA 2111 94
DATA 2211 96
CODE 4611 60 83
CODE 8311 99
DATA 2411 47 51
DATA 2311 87
SIZE=0028H PARA
STACK 3211 74
CODE 6911 104
PUBLIC
86 88 92 95 97
PUBLIC 'CODE' '(II 37 100
PUBLIC 'DATA' 811 14 25
.11 11 69 74
89
STACK 'STACK'
ASSEMBLY COMPLETE, NO ERRORS FOUND
Figure 2-67. ASM-86 Sample Program (Cont'd.)
2-95
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
The ASM-86 version of the dice program operates
like the PL/M-86 version. Since the program uses
the PLlM-86 CO procedure for writing data to
the Intellec console, it adheres to certain conventions established by the PLlM-86 compiler. The
program's logical segments (called CODE,
DATA and STACK-the program does not use
an extra segment) are organized into two groups
called CGROUP and DGROUP. All the members
of a group of logical segments are located in the
same 64k byte physical memory segment.
Physically, the program's DATA and STACK
segments can be viewed as "subsegments" of
DGROUP.
take advantage of new hardware and software
products that are constantly being introduced
by Intel.
Segments and Segment Registers
Segments should be considered as independent
logical units whose physical locations in memory
happen to be defined by the contents of the segment registers. Programs should be independent
of the actual contents of the segment registers and
of the physical locations of segments in memory.
For example, a program should not take
advantage of the "knowledge" that two segments
are physically adjacent to each other in memory.
The single exception to this fully-independent
treatment of segments is that a program may set
up more than one segment register to point to the
same segment in memory, thereby obtaining
address ability through more than one segment
register. For example, if both DS and ES point to
the same segment, a string located in that segment
may be used as a source operand in one string
instruction and as a destination string in another
instruction (recall that a destination string must
be located in the extra segment).
PL/M-86 procedures expect parameters to be
passed on the stack, so the program pushes each
character before calling CO. Note that the stack
will be "cleaned up" by the PLlM-86 procedure
before returning (i.e., the parameter will be
removed from the stack by CO).
2.10 Programming Guidelines
and Examples
This section addresses 8086/8088 programming
from two different perspectives. A series of
general guidelines is presented first. These
guidelines apply to all types of systems and are
intended to make software easier to write, and
particularly, easier to maintain and enhance. The
second part contains a number of specific programming examples. Written primarily in
ASM-86, these examples illustrate how the
instruction set and addressing modes may be utilized in various, commonly encountered programming situations.
Any data aggregate or construct such as an array,
a structure, a string or a stack should be restricted
to 64k bytes in length and should be wholly contained in one segment (i.e., should not cross a segment boundary).
Segment registers should only contain values supplied by the relocation and linkage facilities. Segment register values may be moved to and from
memory, pushed onto the stack and popped from
the stack. Segment registers should never be used
to hold temporary variables nor should they be
altered in any other way.
Programming Guidelines
As an additional guideline, code should not be
written within six bytes of the end of physical
memory (or the end of the code segment if this
segment is dynamically relocatable). Failure to
observe this guideline could result in an attempted
opcode prefetch from non-existent memory,
hanging the CPU if READY is not returned.
These guidelines encourage the development of
8086/8088 software that is adaptable to change.
Some of the guidelines refer to specific processor
features and others suggest approaches to general
software design issues. PL/M-86 programmers
need not be concerned with the discussions that
deal with specific hardware topics; they should,
however, give careful attention to the system
design subjects. Systems that are designed in
accordance with these recommendations
should be less costly to modify or extend. In
addition, they should be better-positioned to
Self-Modifying Code
It is possible to write a program that deliberately
changes some of its own machine instructions
2-96
8086ANO 8088 CENTRAL PROCESSING UNITS
during execution. While this technique may save a
few bytes or machine cycles, it does so at the
expense of program clarity. This is particularly
true if the program is being examined at the·
machine instruction level; the machine instructions shown in the assembly listing may not match
those found in memory or monitored from the
bus. It also precludes executing the code from
ROM. Also, because of the prefetch queue within
the 8086 and 8088, cqde that is self-modified
within six bytes of the current point of execution
cannot be guaranteed to execute as intended.
(This code may already have been fetched.) Finally, a self-modifying program may Prove
incompatible with future Intel products that
assume that the content of·· a code segment
remains constant during execution.
that reads a disk file, for example, should have no
knowledge of where the file is located on the disk,
what size the disk sectors are, etc. This allows
these characteristics to change without affecting
the application module. To an application
module, the I/O system appears to be a series of
file-oriented commands (e.g., Open, Close, Read,
Write). An application module would typically
issue a command by calling a file system
procedure.
The file system processes I/O command requests,
perhaps checking for gross errors, and calls a procedure in the 110 supervisor. The 110 supervisor
is a bridge between the functional 110 request of
the application module and the physical I/O performed by the lowest-level modules in the hierarchy. There should be separate modules in the
supervisor for different types of devices and some
device-dependent code may be unavoidable at this
level. The 110 supervisor would typically perform
overhead activities such as maintaining disk
directories.
A corrollary to this requirement is that variable
data should not be placed in a code segment. Constant data may be written in a code segment, but
this is not recommended for two reasons. First,
programs are simpler to understand if they are
uniformly subdivided into segments of code, data
and stack. Second, placing data in a code segment
can restrict the segment's position independence.
This is because, in general, the segment base
address of a data item may be changed, butthe
offset (displacement) of the data item may not.
This means that the entire segment must be
moved as a unit to avoid changing the offset of
the constant data. If the constant data were
located in a data segment or an extra segment,
individual procedures within the code segment
could be moved independently.
The modules that actually communicate with the
110 devices (ortheir controllers) are at the lowest
level in the hierarchy. These modules contain the
bulk of the system's device-dependent code that
will have to be modified in the event that a device
is changed.
The 8089 Input/Output Processor is specifically
designed to encourage. the development of
modular, hierarchical 110 systems. The 8089
allows knowledge of device characteristics to be
"hidden" from not only application programs,
but also from the operating system that controls
the CPU. The CPU's I/O supervisor can simply
prepare a message in memory that describes the
nature of the operation to be performed, and then
activate the 8089. The 8089 independently performs all physical 110 and notifies the CPU when
the operation has been completed.
Input/Output
Since 110 devices vary so widely in their
capabilities and their interface designs, 110 software is inevitably device dependent. Substituting
a hard disk for a floppy disk, for example,
necessitates software changes eVen though the
disks are functionally identical. 110 software can,
however, be designed to minimize the effect of
device changes or). programs.
Operating Systems
Operating systems also should be organized in a
hierarchy simiHu to the concept illustrated in
figure 2-69. Application modules should "see"
only the upper level of the operating system. This
level might provide services like sending messages
between application modules, providing time
delays, etc. An intermediate level might consist of
housekeeping routines that dispatch tasks, alter
Figure 2-68 illustrates a design concept that structures an I/O system into a hierarchy of separately
compiled/assembled modules. This approach
isolates application modules that use the
input/output devices from all physical
characteristics of the hardware with which they
ultimately communicate. An application module
2-97
'8086 AND 8088 CENTRAL PROCESSING UNITS
"':: ...
1_~_.........
'---~I
,I..._ _. . . - _.......1APPLICATION
MODULES
I
...--.,--...,..-...,.--r---.,....-...,...-.
..
.......
-...-......,~,...,..,..-.,.....,-..,..loooo-or--
IIOSUPERVISOR
..,..~I""'1"",... MODULES
n
DEVICE CONTROL
THARDWARE
Q
1/0 DEVICES"
Figure 2·68. 110 System Hierarchy Concept
APPLICATION MODULES
""""-_.....11..._ .......
OPERATING SYSTEM
II
-
-
-
-' -' -
'-:- -F-;;:;S-;V;;-S- - ' -
I I I I I I I I
I I
-;Y;;;;;R~~ -,-
I
-
I' II
II I
PRIMITIVE OPERATIONS,
I I
I I
.
I I
' "
Figure 2·69. Operating System Hierarchy
2·98
-
--1
; ,,'
HOUSEKEEPING
PHYSICAL 110
I
-
I II I I I
1/0 SUPERVISOR
I
-
I
INVISIBLE TO
APPLICATION MODULES
I
8086 AND 8088 CENTRAL PROCESSING UNITS
priorities, manage memory, etc. At the lowest
level would be the modules that implement
primitive operations such as adding and removing
tasks or messages from lists, servicing timer interrupts, etc.
ferent interrupt procedure. When the number of
interrupt sources is not too large, this can be
accomplished by assigning a different type code
and corresponding service procedure to each
source. In systems where a large number of
similar sources can generate closely spaced interrupts (e.g., 500 communication lines), an
approach similar to that illustrated in figure 2-70,
may be used to insure that the interrupt service
procedure is not reentered, and yet, interrupts
arriving in bursts are not missed. The basic
technique is to divide the code required to service
an interrupt into two parts. The interrupt service
procedure itself is kept as short as possible; it performs the absolute minimum amount of processing necessary to service the device. It then builds a
message that contains enough information to permit another task, the interrupt message processor,
to complete the interrupt service. It adds the
message to a queue (which might be implemented
as a linked list), and terminates so that it is
available to service the next interrupt. The interrupt message processor, which is not reentrant,
obtains a message from the queue, finishes processing the interrupt associated with that message,
obtains the next message (if there is one), etc.
When a burst of interrupts occurs, the queue will
lengthen, but interrupts will not be missed so long
as there is time for the interrupt service procedure
to be activated and run between requests.
Interrupt Service Procedures
Procedures that service external interrupts should
be considered differently than those that service
internal interrupts. A service procedure that is
activated by an internal interrupt, may, and often
should, be made reentrant. External interrupt
procedures, on the other hand, should be viewed
as temporary tasks. In this sense, a task is a single
sequential thread of execution; it should not be
reentered. The processor's response to an external
interrupt may be viewed as the following sequence
of events:
•
•
the running (active) task is suspended,
a new task, the interrupt service procedure, is
created and becomes the running task,
•
•
the interrupt task ends, and is deleted,
the suspended task is reactived and
becomes the running task from the point
where it was suspended.
An external interrupt procedure should only be
interruptable by a request that activates a dif-
MULTIPLE INTERRUPT SOURCES
lliUfllU
INTERRUPT
SERVICE
PROCEDURE
ADD MESSAGE TO QUEUE
,-1--,
r----j
f-- - - - -1 g~~~fJ~WJ~T
f-- - - - -j ~~"d;~ES
f------j
L-f_.....J
OBTAIN NEXT MESSAGE
FROM QUEUE
INTERRUPT
MESSAGE
PROCESSOR
Figure 2-70. Interrupt Message Processor
2-99
8086ANO 8088 CENTRAL PROCESSING UNITS
to examine the memory mapped I/O and
interrupt handling examples" since the concepts
illustrated are generally applicable; one of the
interrupt procedures is wdtten in PLlM-S6.
Stack-Based Parameters
Parameters are frequently passed, to procedures
on a stack. Results produced by the procedure,
however, should be returned ,in other memory
locations or.in registers. ,In other wonis, the called
procedure, should "clean up" .the stack by discarding the parameters before returning. The,
RET instruction can per~orm this function.
PL/M-S6 procedures, always follow this
convention.
The examples are intended to show one way to use'
the instruction set, addressing molies and features
of ASM-S6. They do riot demonstrate the "best"
way to solve any particular proplem. The flexibility of the SOS6 and S088, application differences
plus variations in programming style usually ,add
up to a number of ways to implement a program~ing solution.
Fiag-Images
Procedures
Programs.shQuldmake no assumptions about the
contents of. tlW undefined bits in the flag-images
stored in memory, py the PUSHF and SAHF
ip.structions. These bits always should be masked
out of any comparisons or tests that use these
flag-images" The umlefined bits of the, w,ord flagimage can be cleared by ANDing the word with
FD5H. The undefined bits of. the byte flag:image
can be cleared by ANDing the byte with D5H.
The code in figure 2-71 illustrates, several techniques that are typicallyused in writing A~M-86
procedures. In this example a calling program
invokes a procedure (called EXAMPLE) twice,
passing it a different byte array each time. Two
parameters are passed on the stack; the first contains the number of elements in the array, and the
second ,contains the address (offset in
DAT LSEG) of the first array' element. This
same technique can be used to pass a variablelength parameter list to a procedure (the "array"
could be any series of parameters or parameter
addresses). Thus, although the procedure always
receives two parameters; these can be used to
indirectly access any number of variables 'in
memory.
Programming, Examples
These ex~m~les clemonst~ate theSOS6/S0S8
instruction set and addressing modes in common
programming situations. The following tOPIcs are
addressed:
• procedures (parameters, reentrancy)
• various forms of JMP and CALL
instructions
bit
manipulation with the ASM-S6 RECORD
•
facility
• dynamic code relocation
• memory mapped I/O
• breakpoints
• interrupt handling
•
string operations
Any results returned by a procedure should be
placed in registers 'or in memory, but not on the
stack. AX or AI. is often used to hold a single
word or byte result: Alternatively, the calling program can pass the address (or addresses) of a
result area to,the procedure as a parameter. It is
good practice for ASM-86 programs to follow the
calling conventions, ,used by PLlM-S6; these are
documented in MCS-86 Assembler Operating
Instructions For ISIS-II Users, Order No.
9S00641.
EXAMPLE is defined as aFAR procedure,
meaning it is in a different segment than the calling program. The calling program must use an
inter segment CALL to activate the procedure.
Note that this type of CALL saves CS and IP on
the stack. If EXAMPLE were defined as NEAR
(in the same segment as the caller) then an intrasegment CALL would be used, and only IP would
be saved on the stack. It is the responsibility of
the calling program to know how the procedure is
,defined and to issue the correct type of CALL.
These examples are written primarily in ASM-86
and will be of most interest to assembly language
programmers. The PL/M-S6 compiler generates
code that handles many of these situations
automatically for PL/M-S6 programs.'PorexampIe, the compiler takes care of the stack in
PL/M-S6 procedures, allowing the programmer
to concentrate on solving the application problem. PLlM-S6 programmers, how~~er, may want
Mnemonics © Intel, 1978
2-100
8086 AND 8088 CENTRAL PROCESSING UNITS
STACK_SEG
SEGMENT
20 DUP (?)
DW
STACK_TOP
STACK_SEG
LABEL
ENDS
WORD
DATA_SEG
ARRAY_1
SEGMENT
10 DUP (?)
DB
ARRAY_2
DB
DATA_SEG
ENDS
; ALLOCATE 20-WORD STACK
; LABEL INITIAL TOS
5 DUP (?)
; 10-ELEMENT BYTE ARRAY
; 5-ELEMENT BYTE ARRAY
PROC_SEG
SEGMENT
ASSUME CS:PROC_SEG,DS:DATA_SEG,SS:STACK_SEG,ES:NOTHING
EXAMPLE
PROC
FAR
; MUST BE ACTIVATED BY
INTERSEGMENT CALL
; PROCEDURE PROLOG
BP
; SAVE BP
PUSH
; ESTABLISH BASE POINTER
MOV
BP, SP
CX
; SAVE CALLER'S
PUSH
BX
REGISTERS
PUSH
;
AND FLAGS
PUSHF
SUB
SP,6
; ALLOCATE 3 WORDS LOCAL STORAGE
; END OF PROLOG
; PROCEDURE BODY
CX,[BP+B)
;GETELEMENTCOUNT
MOV
MOV
BX, [BP+6)
; GET OFFSET OF 1ST ELEMENT
; PROCEDURE CODE GOES HERE
; FIRST PARAMETER CAN BE ADDRESSED:
; [BX)
; LOCAL STORAGE CAN BE ADDRESSED:
;
[BP-BJ, [BP-10J, [BP-12)
;ENDOFPROC~DUREBODY
; PROCEDURE EPILOG
ADD
SP,6
POPF
POP
BX
POP
CX
POP
BP
; END OF EPILOG
; PROCEDURE RETURN
RET
4
EXAMPLE
; DE-ALLOCATE LOCAL STORAGE
; RESTORE CALLER'S
REGISTERS
AND
FLAGS
; DISCARD 2 PARAMETERS
ENDP
; END OF PROCEDURE "EXAMPLE"
Figure 2-71. Procedure Example 1
2-101
Mnemonics
@
Intel, 1978
·8086 AND 8088 CENTRAL PROCESSING UNITS
CALLER_SEG
SEGMENT
; GIVE ASSEMBLER SEGMENT IREGISTER CORRESPONDENCE
ASSUME
CS:CALLER_SEG,
&
DS:DATA_SEG,
&
SS:STACK_SEG,
&
ES:NOTHING
; NO EXTRA SEGMENT IN THIS PROGRAM
; INITIALIZE SEGMENT REGISTERS
START:
MOV
AX,DATA_SEG
MOV
DSjAX
MOV
AX,ST ACK_SEG
MOV
SS,AX
MOV
SP ,OFFSET STACK_TOP ; POINT SP TO TOS
; ASSUME ARRAY _1 IS INITIALIZED
,
; CALL "EXAMPLE", PASSING ARRAY_1, THAT IS, THE NUMBER OF ELEMENTS
IN THE ARRAY, ANDTHE LOCATION OFTHE FIRST ELEMENT.
MOV
AX,SIZE ARRAY _1
PUSH
AX
MOV
AX,OFFSET ARRAY_1'
PUSH
AX
CALL
EXAM PLE
; ASSUME ARRAY_2IS INITIALIZED
,
; CALL "EXAMPLE" AGAIN WITH DIFFERENT SIZE ARRAY.
MOV
AX,SIZE ARRAY_2
AX
PUSH
MOV
AX,OFFSET ARRAY_2
PUSH
AX
CALL
EXAMPLE
ENDS
END
START
Figure 2-71. Procedure Example 1 (Cont'd.)
Figure 2-72 shows the stack before the caller
pushes the parameters onto it. Figure 2-73 shows
the stack as the procedure receives it after the
CALL has been executed.
it existed when the procedure was activated. This
is done by pushing any registers used by the procedure (only CX and BP in this case) onto the
stack. If the procedure changes the flags, and the
caller expects the flags to be unchanged following
execution of the procedure, they also may be
saved on the stack. The last instruction in the prolog allocates three words on the stack for the procedure to use as local temporary storage. Figure
2-74 shows the stack at the end of the prolog.
Note that PL/M-86 procedures assume that all
registers except SP and BP can be used without
saving and restoring.
EXAMPLE is divided into four sections. The
"prolog" sets up register BP so it can be used to
address data on the stack (recall that specifying
BP as a base register in an instruction automatically refers to the stack segment unless a segment override prefix is coded). The next step in
the prolog is to save the "state of the machine" as
Mnemonics © Intel, 1978
2-102
8086 AND 8088 CENTRAL PROCESSING UNITS
I - - - - - - - - - t - SP(TOS)
HIGH ADDRESSES
PARAMETER 1
PARAMETER 2
OLDCS
OLD IP
OLD BP
_BP
OLDCX
OLDBX
OLD FLAGS
BP-8_
LOCAL 1
BP-10_
LOCAL2
BP-12_
LOCAL3
_SP(TOS)
LOW ADDRESSES
Figure 2-74. Stack Following Procedure Prolog
Figure 2-72. Stack Before Pushing Parameters
The procedure "body" does the actual processing
(none in the example). The parameters on the
stack are addressed relative to BP. Note that if
EXAMPLE were a NEAR procedure, CS would
not be on the stack and the parameters would be
two bytes "closer" to BP. BP also is used to
address the local variables on the stack. Local
constants are best stored in a data or extra
segment.
HIGH ADDRESSES
PARAMETER 1
PARAMETER 2
OLDCS
OLDIP
_SP(TOS)
The procedure "epilog" reverses the activities of
the prolog, leaving the stack as it was when the
procedure was entered (see figure 2-75).
r
HIGHER ADDRESSES
f'
PARAMETER 1
PARAMETER 2
RETURN ADDRESS
OLDBP
LOW ADDRESSES
h
_
BP & SP (TOS)
h
LOWER ADDRESSES
Figure 2-75. Stack Following Procedure Epilog
Figure 2-73. Stack at Procedure Entry
2-103
8086 AND 8088 CENTRAL PROCESSING UNITS
Figure 2-79 shows a different approach to using
an ASM-86 structure to define the stack layout.
As shown in figure 2-80, register BP is pointed at
the middle of the structure (at OLD_BP) rather
than at the base of the structure. Parameters and
the return address are thus located at positive
displacements (high addresses) from BP, while
local variables are at negative displacements
(lower addresses) from BP. This means that the
local variables will be "closer" to the beginning
of the stack segment and increases the likelihood
that the assembler will be able to produce shorter
instructions to access these variables, i.e., their
offsets from SS may be 255 bytes or less and can
be expressed as a I-byte value rather than a 2-byte
value. Exit from the subroutine also is slightly
faster because a MOV instruction can be used to
deallocate the local storage instead of an ADD
(compare figure 2-71).
The procedure "return" restores CS and IP from
the stack and discards the parameters. As figure
2-76 shows, when the calling program is resumed,
the stack is in the same state as it was before any
parameters were pushed onto it.
HIGH ADDRESSES
t--------i
_SP(TOS)
It is possible for a procedure to be activated a second time before it has returned from its first
activation. For example, procedure A may call
procedure B, and an interrupt may occur while
procedure B is executing. If the interrupt service
procedure calls B, then procedure B is reentered
and must be written to handle this situation correctly, i.e., the procedure must be made
reentrant.
In PLlM-86 this can be done by simply writing:
B: PROCEDURE (PARM1, PARM2) REENTRANT;
An ASM-86 procedure will be reentrant if it uses
the stack for storing all local variables. When the
procedure is reentered, a new "generation" of
variables will be allocated on the stack. The stack
will grow, but the sets of variables (and the
parameters and return addresses as well) will
automatically be kept straight. The stack must be
large enough to accommodate the maximum
"depth" of procedure activation that can occur
under actual running conditions. In addition, any
procedure called by a reentrant procedure must
itself be reentrant.
LOW ADDRESSES
Figure 2-76. Stack Following Procedure Return
Figure 2-77 shows a simple procedure that uses an
ASM-86 structure to address the stack. Register
BP is pointed to the base of the structure, which is
the top of the stack since the stack grows toward
lower addresses (see figure 2-78). Any structure
element can then be addressed by specifying BP as
a base register:
A related situation that also requires reentrant
procedures is recursion. The following are
examples of recursion:
•
•
•
[BP).structure_element.
Mnemonics © Intel, 1978
2-104
A calls A (direct recursion),
A calls B, B calls A (indirect recursion),
A calls B, B calls C, C calls A (indirect
recursion).
8086 AND 8088 CENTRAL PROCESSING UNITS
CODE
SEGMENT
ASSUME CS:CODE
MAX
PROC
; THIS PROCEDURE IS CALLED BY THE FOLLOWING
SEQUENCE:
..
PUSH PARM1
PUSH PARM2
CALL MAX
; IT RETURNS THE MAXIMUM OFTHETWO WORD
PARAMETERS IN AX.
; DEFINE THE STACK LAYOUT AS A STRUCTURE.
STACK_LAYOUT STRUC
OLD_BP
DW?
; SAVED BPVALUE-BASEOFSTRUCTURE
RETURN_ADDR DW.?
; RETURN ADDRESS
PARM_2
DW?
; SECOND PARAMETER
PARM_1
DW?
; FIRST PARAMETER
STACK_LAYOUT ENDS
; PROLOG
PUSH
MOV
; SAVE IN OLD_BP
; POINTTOOLD_BP
BP
BP,SP
; BODY
MOV
CMP
JG
MOV
; EPILOG
FIRST_IS_MAX: POP
; RETURN
RET
MAX
ENDP
CODE
AX, [BPJ.PARM_1 ; IF FIRST
. AX, [BPJ.PARM_2 . ; >SECOND
.
FIRST_IS_MAX·
; THEN RETURN FIRST
AX, [BPJ.PARM_2 ; ELSE RETURN SECOND
BP
; RESTORE BP (& SP)
4
; DISCARD PARAMETERS
ENDS
END
Figure 2-77. Procedure Example 2
HIGHER ADDRESSES
"
Jumps and Calls
lor
The 8086/8088 instruction set contains many different types of JMPand CALL instructions (e.g.,
direct, indirect through register, indirect through
memory, etc.). These varying types of transfer
provide efficient use of space and execution time
in different programming situations. Figure 2-81
illustrates typical use of the different forms of
these instructions. Note that the ASM-86
assembler uses the terms "NEAR" and "FAR"
to denote intrasegment and intersegment transfers, respectively.
PARAMETER 1
PARAMETER 2
RETURN ADDRESS
OLD BP
h
LOWER ADDRESSES
____ BP & SP (TOS)
"
Figure 2-78. Procedure Example 2 Stack Layout
2-105
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
EXTRA
SEGMENT
; CONTAINS STRUCTURE TEMPLATE THAT "NEARPROC"
;
USES TO ADDRESS AN ARRAY PASSED BY ADDRESS.
DUMMY
STRUC
PARM_ARRAY
DB
256 DUP?
DUMMY
ENDS
EXTRA
ENDS
CODE
SEGMENT
ASSUME CS:CODE,ES:EXTRA
NEARPROC
PROC
; LAY OUT THE STACK (THE DYNAMIC STORAGE AREA OR DSA).
DSASTRUC
STRUC
DW
?
; LOCALVARIABLES FIRST
I
10 DUP (?)
LOC_ARRA Y
DW
,
OLD_BP
DW
?
; ORIGINAL BP VALUE
RETADDR
DW
?
; RETURN ADDRESS
POINTER
DD
?
; 2ND PARM-POINTERTO "PARM_ARRAY"
?
COUNT
DB
; 1ST PARM-A BYTE OCCUPIES
?
DB
A WORD ON THE STACK
DSASTRUC
ENDS
; USE AN EQU TO DEFINE THE BASE ADDRESS OF THE
DSA. CANNOT SIMPLY USE BP BECAUSE IT WILL
BE POINTING TO "OLD_BP" IN THE MIDDLE OF
;
THE DSA.
DSA
EQU
[BP - OFFSET OLD_BP)
; PROCEDURE ENTRY
PUSH
MOV
SUB
BP
; SAVE BP
BP, SP
; POINT BP AT OLD_BP
SP, OFFSET OLD_BP; ALLOCATE LOC_ARRAY & I
; PROCEDURE BODY
; ACCESS LOCAL VARIABLE I
MOV
AX,DSA.I
; ACCESS LOCAL ARRAY (3) I.E., 4TH ELEMENT
MOV
SI,6
; WORD ARRAY-INDEX IS 3*2
MOV
AX,DSA.LOC_ARRAY [SI)
; LOAD POINTER TO ARRAY PASSED BY ADDRESS
LES
BX,DSA.POINTER
; ES:BX NOW POINTS TO PARM_ARRAY (0)
; ACCESS SI'TH ELEMENT OF PARM_ARRAY
MOV
AL,ES:[BX).PARM_ARRAY [SI)
; ACCESS THE BYTE PARAMETER
MOV
AL,DSA.COUNT
Figure 2-79. Procedure Example 3
Mnemonics © Intel, 1978
2-106
8086 AND 8088 CENTRAL PROCESSING UNITS
; PROCEDURE EXIT
MOV
SP,BP
; DE-ALLOCATE LOCALS
POP
BP
; RESTORE BP
; STACK NOW AS RECEIVED FROM CALLER ,
,
RET
6
; DISCARD PARAMETERS
ENDP
ENDS
END
NEARPROC
CODE
Figure 2-79. Procedure Example 3 (Cont'd.)
'f'
HIGHER ADDRESSES
I
,
The procedure in figure .2-81 illustrates how a
PLlM-86 DO CASE construction may be
implemented in ASM-86.It also shows:
COUNT
r---POINTER
•
an indirect CALL 'through memory to a
procedure located in another segment,
•
a direct JMP to a label in another segment,
•
an indirect JMP though memory to a label in
the same segment,'
'
•
an indirect JIvlP through a register to a label
in the same segment,
RETADDR
OLD
BP
_BP
LOCJRRAY (9)
LOC_ARRAY (8)
LOC_ARRAY (7)
LOC_ARRAY (8)
LOC_ARRAY (5)
LOC_ARRAY (4)
LOC_ARRAY (3)
LOC_ARRAY (2)
LOCJRRAY(1)
,
LOC_ARRAY (0)
I
"
.
_SP
,.,
LOWER ADDRESSES
Figure 2-80. Procedure Example
3 Stack Layout
2-107
a direct CALL to· a procedure in another
segment,
•
a direct CALL to a procedure in the same
segment,
•
direct JMPs to labels in the same segment,
within -128 to +127 bytes ("SHORT") and
farther than -128 to +127 bytes ("NEAR").
Mnemonics @ Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
DATA
SEGMENT
; DEFINE THE CASE TABLE (JUMP TABLE) USED BY PROCEDURE
"DO_CASE." THE OFFSET OF EACH LABEL WILL
;
BE PLACED IN THE TABLE BY THE ASSEMBLER.
CASE_TABLE
DW
ACTIONO, ACTION1, ACTION2,
&
ACTION3, ACTION4, ACTION5 .
DATA
ENDS
; DEFINE TWO EXTERNAL (NOT PRESENT IN THIS' .
. ASSEMBLY BUT SUPPLIED BY R & L FACILITY)
PROCEDURES. ONE IS IN THIS CODE SEGMENT
(NEAR) AND ONE IS IN ANOTHER SEGMENT (FAR).
NEAR_PROC: NEAR, FAR_PROC: FAR
EXTRN
; DEFINE AN EXTERNAL LABEL (JUMP TARGET) THAT
IS IN ANOTHER SEGMENT.
EXTRN
ERR_EXIT: FAR
CODE
SEGMENT
ASSUME
CS: CODE, DS: DATA
; ASSUME DS HAS BEEN SET UP
BY CALLERTOPOINTTO "DATA" SEGMENT.
DO_CASE
PROC
NEAR
; THIS EXAMPLE PROCEDURE RECEIVES TWO
PARAMETERS ON THE STACK. THE FIRST
PARAMETER IS THE "CASE NUMBER" OF
A ROUTINE TO BE EXECUTED (0-5). THE SECOND
PARAMETER IS A POINTER TO AN ERROR
PROCEDURE THAT IS EXECUTED IF AN INVALID
CASE NUMBER (>5) IS RECEIVED .
. ; LAY OUT THE STACK.
ST ACK_LA YOUTSTRUC
OLD_BP
DW?
RETADDR
DW?
ERR_PROC_ADDR DD
CASE_NO
DB?
DB
?
STACK_LAYOUT ENDS
?
; SET UP PARAMETER ADDRESSING
BP
, " PUSH
MOV
BP,SP
; CODE TO SAVE CALLER'S REGISTERS COULD GO HERE.
; CHECK THE CASE NUMBER
MOV
MOV
CMP
JLE
BH,O
BL, [BPj.CASE_NO
BX, LENGTH CASE_TABLE
OK
; ALL CONDITIONAL JUMPS
; ARE SHORT DIRECT
Figure 2-81. JMP and CALL Examples
Mnemonics © Intel, 1978
2-108
8086 AND 8088 CENTRAL PROCESSING UNITS
; CALL THE ERROR ROUTINE WITH A FAR
INDIRECT CALL. A FAR INDIRECT CALL
IS INDICATED SINCE THE OPERAND HAS
TYPE "DOUBLEWORD."
CALL
[BP].ERR_PROC_ADDR
; JUMP DIRECTLY TO A LABEL IN ANOTHER SEGMENT.
A FAR DIRECT JUMP IS INDICATED SINCE
THE OPERAND HAS TYPE "FAR."
JMP
ERR_EXIT
OK:
; MULTIPLY CASE NUMBER BY 2TOGETOFFSET
INTO CASE_TABLE (EACH ENTRY IS 2 BYTES).
SHL
BX,1 .
; NEAR INDIRECT JUMP THROUGH SELECTED
ELEMENT OF CASE_TABLE. A NEAR
INDIRECT JUMP IS INDICATED SINCE THE
OPERAND HAS TYPE "WORD."
JMP
CASE-'-.TABLE [BX]
ACTIONO:
; EXECUTED IF CASE_NO = 0
. ; CODE TO PROCESS THE ZERO CASE GOES HERE.
; FOR ILLUSTRATION PURPOSES, USE A
NEAR INDIRECT JUMP THROUGH A
REGISTER TO BRANCH TO THE POINT
WHERE ALL CASES CONVERGE.
A DIRECT JUMP (JMP ENDCASE) IS
ACTUALLY MORE APPROPRIATE HERE.
MOV
AX, OFFSET ENDCASE
JMP
AX
ACTION1:
; EXECUTED IF CASE_NO = 1
; CALL A FAR EXTERNAL PROCEDURE. A FAR
DIRECT CALL IS INDICATED SINCE OPERAND
HAS TYPE "FAR."
CALL
FAR_PROC
; CALLA NEAR EXTERNAL PROCEDURE.
CALL
NEAR_PROC
; BRANCH TO CONVERGENCE POINT USING NEAR
DIRECT JUMP. NOTE THAT "ENDCASE"
IS MORE THAN 127 BYTES AWAY
SO A NEAR DIRECT JUMP WILL BE USED.
JMP
ENDCASE
ACTION2:
; EXECUTED IF CASE_NO = 2
; CODE GOES HERE
JMP
ENDCASE; NEAR DIRECT JUMP
Figure 2-81. JMP and CALL Examples (Cont'd.)
2-109
Mnemonics © Intel. 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
ACTION3:
; EXECUTED IF CASE_NO = 3
; CODE GOES HERE
JMP
ENDCASE; NEAR DIRECT JMP
; ARTIFICIALLY FORCE "ENDCASE" FURTHER AWAY
SO THAT ABOVE JUMPS CANNOT BE "SHORT."
ORG
500
ACTION4:
; EXECUTED IF CASE_NO = 4
; CODE GOES HERE
JMP
ENDCASE; NEAR DIRECT JUMP
; EXECUTED IF CASE_NO ~ 5
ACTION5:
; CODE GOES HERE.
; BRANCH TO CONVERGENCE POINT USING
SHORT DIRECTJUMP SINCE TARGET IS
WITHIN 127 BYTES. MACHINE INSTRUCTION
HAS 1-BYTE DISPLACEMENT RATHER THAN
2-BYTE DISPLACEMENT REQUIRED FOR
NEAR DIRECT JUMPS. "SHORT" IS
WRITTEN BECAUSE"ENDCASE" IS A FORWARD
REFERENCE, WHICH ASSEMBLER ASSUMESIS
"NEAR." IF "ENDCASE" APPEARED PRIOR
TO THE JUMP, THE ASSEMBLER WOULD
AUTOMATICALLY DETERMINEIFIT WERE REACHABLE
WITH A SHORT JUMP.
SHORTENDCASE
JMP
ENDCASE:
; ALL CASES CONVERGE HERE.
; POP CALLER'S REGISTERS HERE.
; RESTORE BP & SP, DISCARDPARAMETERS
AND RETURN TO CALLER.
MOV
SP, BP
POP
BP
RET
6
ENDP
ENDS
END
; OF ASSEMBLY
Figure 2-81. JMP and CALL Examples (Cont'd.)
Records
Figure 2-82 shows how the ASM-86 RECORD
facility may be used to manipulate bit data. The
example shows how to:
•
•
•
assign a constant known at assembly time,
right-justify a bit field,
•
assign a variable,
test for a value,
•
set or clear a bit field.
Mnemonics © Intel, 1978
2-110
8086 AND 8088 CENTRAL PROCESSING UNITS
DATA
SEGMENT
; DEFINE A WORD ARRAY
XREF
DW 3000 DUP (?)
; EACH ELEMENT OF XREF CONSISTS OF 3 FIELDS:;
A 2-BIT TYPE CODE,
A 1-BIT FLAG,
;
A 13-BIT NUMBER.
; DEFINE A RECORDTO LAyqUTTHIS ORGANIZATION.
LlNE_REC
RECORD
LINE_TYPE: 2,
&
VISIBLE: 1,
&
LlNE_NUM: 13
DATA
ENDS
CODE
SEGMENT
ASSUME CS: CODE, DS: DATA
; ASSUME SEGMENT REGISTERS ARE SET UP PROPERLY
AND THAT SIINDEXES AN ELEMENT OF XREF ..
; A RECORD FIELD-NAME USED BY ITSELF RETURNS
THE SHIFT COUNT REQUIRED TO RIGHT-JUSTIFY
; THE FIELD. ISOLATE "LINE_TYPE" IN THIS
; MANNER.
MOV
AL, XREF [SI)
CL, LINE_TYPE
.MOV
SHR
AX, CL
; THE "MASK" OPERATOR APPLIED TO A RECORD
FIELD-NAME RETURNS THE BIT MASK
,
REQUIRED TO ISOLATE THE FIELD WITHIN
THE RECORD. CLEAR ALL BITS EXCEPT
. "LlNE_NUM."
MOV
DX, XREF[SI)
AND
DX, MASK LlNE_NUM
; DETERMINE THE VALU E OF THE "VISIBLE" FIELD
TEST
XREF[SIJ, MASK VISIBLE
JZ
NOT_VISIBLE
; NO JUMP IF VISIBLE = 1
NOT_VISIBLE:
; JUMP HERE IF VISIBLE = 0
; ASSIGN A CONSTANT KNOWN AT ASSEMBLY-TIME
TO A FIELD, BY FIRST CLEARING THE BITS
AND THEN OR'ING IN THE VALUE. IN
THIS CASE "LINE_TYPE" IS SETTO 2 (10B).
AND
XREF[SIJ,NOT MASK LINE_TYPE
OR
XREF[SI) ,2 SH L LIN E_TYPE
; THE ASSEMBLER DOES THE MASKING AND SHIFTING ..
; THE RESULT IS THE SAME AS:
.
AND
XREF[SIJ, 3FFFH
OR
XREF[SIJ, 8000H
BUT IS MORE READABLE AND LESS SUBJECT
TO CLERICAL ERROR.
Figure 2-82. RECORD Example
2-111
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
; ASSIGN A VARIABLE (THE CONTENT OF AX)
TO LINE_TYPE.
MOV
CL, LINE_TYPE ; SHIFT COUNT
SHL
AX, CL ; SHIFT TO "LINE UP" BITS
AND
XREF[SIJ, NOT MASK LINE_TYPE ; CLEAR BITS
OR
XREF[SIJ, AX ; OR IN NEW VALUE
; NO SHIFT IS REQUIRED TO ASSIGN TO THE
RIGHT-MOST FIELD. ASSUMING AX CONTAINS
A VALID NUMBER (HIGH 3 BITS ARE 0),
ASSIGN AX TO "L1NE_NUM."
AND
XREF[SIJ, NOT MASK L1NE_NUM
OR
XREF[SIJ, AX
; A FIELD MAY BE SET OR CLEARED WITH
ONE INSTRUCTION. CLEAR THE "VISIBLE"
FLAG AND THEN SET IT.
AND
XREF[SIJ, NOT MASK VISIBLE
XREF[SIJ, MASK VISIBLE
OR
CODE
ENDS
END
; OF ASSEMBLY
Figure 2-82. RECORD Example (Cont'd.)
The following considerations apply to positionindependent code sequences:
•
A label that is referenced by a direct FAR
(inter segment) transfer is not moveable.
•
A label that is referenced by an indirect
transfer (either NEAR or FAR) is moveable
so long as the register or memory pointer to
the label contains the label's current address.
•
A label that is referenced by a SHORT (e.g.,
conditional jump) or a direct NEAR (intrasegment) transfer is moveable so long as
the referencing instruction is moved with the
label as a unit. These transfers are selfrelative; that is they require only that the
label maintain the same distance from the
referencing instruction, and actual addresses
are immaterial.
•
•
Data is segment-independent, but not offsetindependent. That is, a data item may be
moved to a different segment, but it must
maintain the same offset from the beginning
of the segment. Placing constants in a unit
of code also effectively makes the code
offset-dependent, and therefore is not
recommended.
A procedure should not be moved while it is
active or while any procedure it has called is
active.
Mnemonics
© Intel, 1978
2-112
•
A section of code that has been interrupted
should not be moved.
The segment that is receiving a section of code
must have "room" for the code. If the MOVS (or
MOVSB or MOVSW) instruction attempts to
auto-increment DI past 64k, it wraps around to 0
and causes the beginning of the segment to be
overwritten. If a segment override is needed for
the source operand, code similar to the following
can be used to properly resume the instruction if it
is interrupted:
RESUME:
REP
MOVS
DESTINATION, ES:SOURCE
;IF CX NOT = 0 THEN INTERRUPT HAS OCCURRED
AND
CX,CX
JNZ
RESUME
; CX=O?
;NO, FINISH EXECUTION
;CONTROL COMES HERE WHEN STRING HAS BEEN MOVED.
the MOVS is interrupted, the CPU
"remembers" the segment override, but
"forgets" the presence of the REP prefix when
execution resumes. Testing CX indicates whether
the instruction is completed or not. Jumping back
to the instruction resumes it where it left off. Note
that a segment override cannot be specified with
MOVSB or MOVSW.
If
8086 AND 8088 CENTRAL PROCESSING UNITS
Dynamic Code Relocation
calls the procedure through this pointer. The
supervisor also has access to the procedure's
length in bytes. The procedure is moved with the
MOVSB instruction. After the procedure is
moved, its pointer is updated with the new location. The ASM-86 WORD PTR operator is written to inform the assembler that one word of the
doubleword pointer is being updated at a time.
Figure 2-83 illustrates one approach to moving
programs in memory at execution time. A "supervisor" program (which is not moved) keeps
a pointer variable that contains the current location (offset and segment base) of a positionindependent procedure. The supervisor always
MAIN_DATA
SEGMENT
; SET UP POINTERS TO POSITION-INDEPENDENT PROCEDURE
AND FREE SPACE.
PIP_PTA
DD
EXAMPLE
FREE_PTA
DD
TARGET_SEG
; SET UP SIZE OF PROCEDURE IN BYTES
PIP_SIZE
DW
EXAMPLE_LEN
MAIN_DATA
ENDS
STACK
STACK_TOP
STACK
SEGMENT
DW
20 DUP(?)
LABEL
ENDS
WORD
,'or
; 20 WORDS FOR STACK
; TOS BEGINS HERE
SOURCE_SEG
SEGMENT
; THE POSITION-INDEPENDENT PROCEDURE IS INITIALLY IN THIS SEGMENT.
; OTHER CODE MAY PRECEDE IT; I.E., ITS OFFSET NEED NOT BE ZERO.
ASSUME
CS:SOURCE_SEG
EXAMPLE
PROC
FAR
; THIS PROCEDURE READS AN 8-BIT PORT UNTIL
; BIT 3 OFTHE VALUE READ IS FOUND SET. IT
; THEN READS ANOTHER PORT. IF THE VALUE READ
; IS GREATER THAN 10H IT WRITES THEVALUE TO
; A THIRD PORT AND RETURNS; OTHERWISE IT STARTS
; OVER.
STATUS_PORT EQU
ODOH
PORT_READY
EQU
008H
INPUT_PORT
EQU
OD2H
010H.
THRESHOLD
EQU
OUTPUT_PORT EQU
OD4H
AL,STATUS_PORT
CHECK_AGAIN: IN
; GET STATUS
AL,PORT_READY
TEST
; DATA READY?
CHECK_AGAIN
JNE
; NO, TRY AGAIN
AL,INPUT_PORT
IN
; YES, GETDATA
AL,THRESHOLD
CMP
;>10H?
JLE
CHECK_AGAIN
; NO, TRY AGAIN
OUT
OUTP UT_PORT ,AL ; YES, WRITE IT
Figure 2-83. Dynamic Code Reiocati9D Example.
2-113
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
RET
;GETPROCEDURELENGTH
EXAMPLE_LEN EQU
ENDP
SOURCE_SEG
ENDS
; RETURN TO CALLER
(OFFSET THIS BYTE)-(OFFSET CHECK_AGAIN)
EXAMPLE ENDP
TARGET_SEG
SEGMENT
; THE POSITION-INDEPENDENT PROCEDURE
IS MOVED TO THIS SEGMENT, WHICH IS
;
INITIALLY "EMPTY."
; IN TYPICAL SYSTEMS, A "FREE SPACE MANAGER" WOULD
; MAINTAIN A POOL OF AVAILABLE MEMORY SPACE
; FOR ILLUSTRATION PURPOSES, ALLOCATE ENOUGH
SPACE TO HOLD IT
DB
EXAMPLE_LEN DUP (?)
TARGET_SEG
ENDS
MAIN_CODE
SEGMENT
; THIS ROUTINE CALLS THE EXAMPLE PROCEDURE
; AT ITS INITIAL LOCATION, MOVES IT, AND
; CALLS IT AGAIN ATTHE NEW LOCATION.
ASSUME
&
CS:MAIN_CODE,SS:STACK,
DS:MAIN_DAT A,ES:NOTHING
; INITIALIZE SEGMENT REGISTERS & STACK POINTER.
START:
MOV
AX,MAIN_DATA
MOV
DS,AX
AX,STACK
MOV
MOV
SS,AX
MOV
SP ,OFFSET STACK_TOP
; CALL EXAMPLE AT INITIAL LOCATION.
CALL
PIP_PTR
; SET UP CX WITH COUNT OF BYTES TO MOV
MOV
CX,PIP_SIZE
; SAVE DS, SET UP DS/SI AND ESIDI TO
POINT TO THE SOURCE AND DESTINATION
ADDRESSES.
PUSH
DS
DI,FREE_PTR
LES
SI,PIP_PTR
LDS
; MOVE THE PROCEDURE.
CLD
REP MOVSB
; AUTO INCREMENT
; RESTORE OLD ADDRESSABILITY.
MOV
AX,DS
; HOLD TEMPORARILY
POP
DS
; UPDATE POINTER TO POSITION-INDEPENDENT PROCEDURE
MOV
WORD PTR PIP _PTR+2,ES
SUB
DI,PIP _SIZE
; PRODUCES OFFSET
MOV
WORD PTR PIP _PTR,DI
Figure 2-83. Dynamic Code Relocation Example (Cont'd.)
Mnemonics © Intel, 1978
2-114
8086 AND 8088 CENTRAL PROCESSING UNITS
; UPDATE POINTER TO FREE SPACE
MOV
WORD PTR FREE_PTR+2,AX
SUB
SI,PIP_SIZE
; PRODUCES OFFSET
MOV
WORD PTR FREE_PTR,SI
; CALL POSITION-INDEPENDENT PROCEDURE AT
NEW LOCATION AND STOP
CALL
PIP_PTA
MAIN_CODE
ENDS
END
START
Figure 2-83. Dynamic Code Relocation Example (Cont'd.)
Memory-Mapped I/O
instruction transfers characters to successive
memory addresses, the decoding logic must select
the line printer if any of these locations is written.
One way of accomplishing this is to have the chip
select logic decode only the upper 12 lines of the
address bus (AI9-A8), ignoring the contents of
the lower eight lines (A7-AO). When data is written to any address in this 256-byte block, the
upper 12 lines will not change, so the printer will
be selected.
Figure 2-84 shows how memory-mapped 110 can
be used to address a group of communication
lines as an "array." In the example, indexed
addressing is used to poll the array of status ports,
one port at a time. Any of the other 8086/8088
memory addressing modes may be used in conjunction with memory-mapped 110 devices as
well.
In figure 2-85 a MOVS instruction is used to perform a high-speed transfer to a memory-mapped
line printer. Using this technique requires the
hardware to be set up as follows. Since the MOVS
If an 8086 is being used with an 8-bit printer, the
8086's 16-bit data bus must be mapped into 8-bits
by external hardware. Using an 8088 provides a
more direct interface.
COM_LINES
SEGMENT AT 800H
; THE FOLLOWING IS A MEMORY MAPPED "ARRAY"
OF EIGHT 8-BIT COMMUNICATIONS CONTROLLERS
(E.G.,8251 USARTS). PORTS HAVE ALL-ODD
OR ALL-EVEN ADDRESSES (EVERY OTHER BYTE
IS SKIPPED) FOR 8086-COMPATIBILITY.
COM_DATA
COM_STATUS
COM_LINES
DB
DB
DB
DB
DB
ENDS.
?
?
?
?
28
; SKIP THIS ADDRESS
DUP (?)
; SKIP THIS ADDRESS
; REST OF "ARRAY"
CODE
SEGMENT
; ASSUME STACK IS SET UP, AS ARE SEGMENT
REGISTERS (DS POINTING TO COM_LINES).
FOLLOWING CODE POLLS THE LINES.
CHAFLRDY
START_POLL:
EQU
MOV
SUB
00000010B
CX,8
SI,SI
; CHARACTER PRESENT
; POLL 8 LINES ZERO
; ARRAY INDEX
Figure 2-84. Memory Mapped 1/0 "Array"
2-115
Mnemonics © Intel, 1978
8086 AN08088 CENTRAL PROCESSING UNITS
POLL_NEXT:
READ_CHAR:
; ETC.
CODE
TEST
JE
ADD
LOOP
JMP
COM_STATUS [SI], CHAR_RDY
READ_CHAR; READ IFPRESENT
SI,4
; ELSE BUMP TO NEXT LINE
POLL. :_NEXT ; CONTINUE POLLING UNTIL
;
ALL8 HAVE BEEN CHECKED
ST ART_POLL; START OVER
MOV
AL,COM_DATA [SI]
;GETTHE DATA
ENDS
END
Figure 2~84. Memory Mapped 1/0 "Array" (Cont'd.)
PRINTER
SEGMENT
; THIS SEGMENTCONTAINS A "STRING"THAT
ISACTUALLY A MEMORY-MAPPED LINE PRINTER ..
THE SEGMENT (PRINTER) MUST BE ASSIGNED (LOCATED)
TO ABLOCK OF THE ADDRESS SPACE SUCH
THAT WRITING TO ANY ADDRESS IN THE
BLOCK SELECTS THE PRINTER.
PRINT_SELECT
PRINTER
DB133
DB 123
ENDS
DUP (?)
DUP (?)
; "STRING" REPRESENTING PRINTER.
; REST OF256-BYTE BLOCK
DATA
SEGMENT
DB133
DUP(?)
. PRINT_BUF
PRINT_COUNT DB 1
?
; OTHER PROGRAM DATA
DATA
ENDS
; LINE TO BE PRINTED
; LINE LENGTH
CODE
SEGMENT
; ASSUME STACK AND SEGMENT REGISTERS HAVE
BEEN SET UP (DS POINTS TO DATA SEGMENT).
FOLLOWING CODE TRANSFERS A LINE TO
THE PRINTER.
REP
CODE
ASSUME
MOV
MOV
SUB
SUB
MOV
CLD
MOVS
; ETC.
ENDS
END
ES: PRINTER
; PREVENT SEGMENT OVERRIDE
. AX, PRINTER
ES,AX
DI, DI
; CLEAR SOURCE AND
SI, SI
DESTINATION POINTERS
CX, PRINT_COUNT
; AUTO-INCREMENT
PRINT_SELECT, PRINT_BUF
Figure 2-85. Memory Mapped Block Transfer Example
Mnemonics © Inlel, 1978
2-116
8086 AND 8088 CENTRAL PROCESSING UNITS
that saves the byte located at that address and
replaces it with an INT 3 (breakpoint) instruction.
When the CPU encounters the breakpoint
instruction, it calls the type 3 interrupt procedure.
In the example, this procedure places the processor into single-step mode starting with the
instruction where the breakpoint was placed.
Breakpoints
Figure 2-86 illustrates how a program may set a
breakpoint. In the example, the breakpoint
routine puts the processor into single-step mode,
but the same general approach could be used for
other purposes as well. A program passes the
address where the break is to occur to a procedure
INT_PTR_TAB SEGMENT
; INTERRUPT POINTER TABLE-LOCATE AT OH
TYPE_O
DO
?
TYPE_1
DO
SINGLE_STEP
TYPE_2
DO
?
TYPE_3
DO
BREAKPOINT
INT_PTR_TAB ENDS
SAVE_SEG
SAVE_INSTR
SEGMENT
DB 1
SAVE_SEG
ENDS
DUP (?)
; NOT DEFINED IN EXAMPLE
; NOT DEFINED IN EXAMPLE
; INSTRUCTION REPLACED
; BY BREAKPOINT
MAIN_CODE
SEGMENT
; ASSUME STACK AND SEGMENT REGISTERS ARE SET UP.
; ENABLE SINGLE-STEPPING WITH INSTRUCTION AT
LABEL "NEXT" BY PASSING SEGMENT AND
OFFSET OF "NEXT" TO "SET_BREAK" PROCEDURE
PUSH
CS
LEA
AX,CS:NEXT
PUSH
AX
CALL
FAR SET_BREAK
; ETC.
NEXT:
IN
; ETC.
MAIN_CODE
EN OS
AL,OFFFH
; BREAKPOINT SET HERE
BREAK
SEGMENT
SET_BREAK
PROC
FAR
; THIS PROCEDURE SAVES AN INSTRUCTION BYTE (WHOSE
ADDRESS IS PASSED BY THE CALLER) AND WRITES
AN INT 3 (BREAKPOINT) MACHINE INSTRUCTION
ATTHETARGETADDRESS.
TARGET
EQU
DWORD PTR [BP+6]
Figure 2-86. Breakpoint Example
2-117
Mnemonics © Intel, 1978
8086 AN08088 CENTRAL PROCESSING UNITS
; SETUP BP F,OR PARM ADDRESSING & SAVE REGISTERS
BP
PUSH
MOV
BP, SP
PUSH
DS
PUSH
ES
'. PUSH
AX
.
. .
PUSH
BX
; POINT DS/BX TO THE TARGET INSTRUCTION
LDS
BX, TARGET
; POINT ES TO THE SAVE AREA
MOV
AX, SAVE_SEG
MOV
ES, AX
; SWAP THE TARGET INSTRUCTION FOR INT 3 (OCCH)
MOV
AL,OCCH
XCHG
AL, DS: [BXJ .
; SAVE THE TARGET INSTRUCTION
MOV
ES: SAVE_INSTR, AL
;~ESTOREANDRETURN
SET_BREAK
POP
POP
POP
POP
POP'
RET
ENDP
BX
AX
ES
DS
BP
4
BREAKPOINT
PROC
FAR
; THE CPU WILL ACTIVATE THIS PROCEDURE WHEN IT
EXECUTES THE INT 3 INSTRUCTION SET BY THE
SET_BREAK PROCEDURE. THIS PROCEDURE
RESTORES THE SAVED INSTRUCTION BYTE TO ITS
ORIGINAL LOCATION AND BACKS UP THE
INSTRUCTION POINTER IMAGE ON THE STACK
SO THAT EXECUTION WILL RESUME WITH
THE RESTORED INSTRUCTION. IT THEN SETS
TF (THE TRAP FLAG) IN THE FLAG-IMAGE
ON THE STACK. THIS PUTS THE PROCESSOR
IN SINGLE-STEP MODE WHEN EXECUTION
RESUMES.
FLAG_IMAGE
EQU
WORD PTR [BP + 6J
IP _IMAGE
EQU
WORD PTR [BP + 2J
NEXT_INSTR
EQU
DWORD PTR [BP+2J
; SET UP BPTO ADDRESS STACK AND SAVE REGISTERS
BP
PUSH
MOV
BP, SP
PUSH
DS
PUSH
ES .
AX
PUSH
PUSH
BX
; POINT ES AT THE SAVE AREA
MOV
AX, SAVE_SEG
MOV
ES, AX
; GET THE SAVED BYTE
MOV
AL, ES: SAVE_INSTR
Figure 2-86. Breakpoint Example (Cont'd.)
Mnemonics ©Intel, 1978
2-118
8086 AND 8088 CENTRAL PROCESSING UNITS
; GET THE ADDRESS OF THE TARGET + 1
(INSTRUCTION FOLLOWING THE BREAKPOINT)
BX, NEXT_INSTR
LDS
; BACK UP IP-IMAGE (IN BX) AND REPLACE ON STACK
DEC
BX
MOV
IP _IMAGE, BX
; RESTORE THE SAVED INSTRUCTION
MOV
DS: [BX], AL
; SET TF ON STACK
AND
FLAG_IMAGE,0100H
; RESTORE EVERYTHING AND EXIT
POP
BX
POP
AX
POP
ES
POP
DS
POP
BP
IRET
BREAKPOINT
ENDP
SINGLE STEP
PROC
FAR
; ONCE SINGLE-STEP MODE HAS BEEN ENTERED,
THE CPU "TRAPS" TO THIS PROCEDURE
AFTER EVERY INSTRUCTION THAT IS NOT IN
AN INTERRUPT PROCEDURE. IN THE CASE
OF THIS EXAMPLE, THIS PROCEDURE WILL
BE EXECUTED IMMEDIATELY FOLLOWING THE
"IN AL, OFFFH" INSTRUCTION (WHERE THE
BREAKPOINT WAS SET) AND AFTER EVERY
SUBSEQUENT INSTRUCTION. THE PROCEDURE
COULD "TURN ITSELF OFF" BY CLEARING
TF ON THE STACK.
; SINGLE-STEP CODE GOES HERE.
; SINGLE_STEP ENDP
BREAK
ENDS
END
Figure 2-86. Breakpoint Example (Cont'd.)
In this hypothetical system, an 8253 Programmabie Interval Timer is used to generate a tirrie
base. One of the three tirriers on the 8253 is programmed to repeatedly generate interrupt
requests at 50 millisecond intervals. The output
from this timer is tied to one of the eight interrupt
request lines of an 8259A Programmable Interrupt Controller. The 8259A, in turn, is connected
to the INTR line of an 8086 or 8088.
.
Interrupt Procedures
Figure 2~87 is a block diagram of a hypothetical
system that is used to illustrate three different
examples of interrupt handling: an external
(maskable) interrupt,· an external non-mask able
interrupt and a software interrupt.
2-119
Mnemonics © Intel. 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
i
T
COLD START-11-
~
r--l
+5V
BATTERY
I
POWER DOWN
CIRCUITS
MPRO
RESET
I
BATTERY
POWERED
RAM
l~
IE1
I
DECODER
PF1
t
PFSR
(PULSE)
PFS
~
I
NMI
EO
INTR
8259A
8086/8085
I
ADDRESS BUS
!
DATA BUS
CONTROL BUS
I
I
I
I
I
-
CS
DECODER
I
!
I
II
EPROM
I
I
I I
I
I
I
I
1
I
I
DECODER
I
CS
E2
PORTS
I I I
I
I
1
I
CTR1
8253
IR3
I
I
II
RAM
I
I
I
J
~
I
Figure 2-87. Interrupt Example Block Diagram
A power-down circuit is used in the system to
illustrate one application of the 8086/8088 NMI
(non-mask able interrupt) line. If the ac line
voltage drops below a certain threshold, the
power supply activates ACLO. The power-down
circuit then sends a power-fail interrupt (PFI)
pulse to the CPU's NMI input. After 5
milliseconds, the power-down circuit activates
MPRO (memory protect) to disable reading
from and writing to the system's battery-powered
RAM. This protects the RAM from fluctuations
that may occur when power is actually lost 7.5
milliseconds after the power failure is detected.
The system software must save all vital information in the battery-powered RAM segment within
5 milliseconds of the activation of NMI.
connected to the low-order bit of port EO, identifies the source of the RESET. If the bit is set, the
software executes a "warm start" to restore the
information saved by the power-fail routine. If
the PFS bit is cleared, the software executes a
"cold start" from the beginning of the program.
In either case, the software writes a "one" to the
low-order bit of port E2. This line is connected to
the power-down circuit's PFSR (power fail status
reset) signal and is used to enable the batterypowered RAM segment.
A software interrupt is used to update a simple
real-time clock. This procedure is written in
PLlM-86, while the rest of the system is written in
ASM-86 to demonstrate the interrupt handling
capability of both languages. The system's main
program simply initializes. the system following
receipt of a RESET and then waits for an
interrupt. An example of this interrupt procedure
is given in figure 2-88.
When power returns, the power-down circuit
activates the system RESET line. Pressing the
"cold start" switch also produces a system
RESET. The PFS (power fail status) line, whichis
2-120
8086ANO 8088 CENTRAL PROCESSING UNITS
INT_POINTERS
SEGMENT
; INTERRUPT POINTER TABLE, LOCATE AT OH, ROM-BASED
TYPE_O
DO?
; DIVIDE-ERROR NOT SUPPLIED IN EXAMPLE.
TYPE_1
DO?
; SINGLE-STEP NOT SUPPLIED IN EXAMPLE.
TYPE_2
DO
POWER_FAIL; NON-MASKABLE INTERRUPT
TYPE_3
DO?
; BREAKPOINT NOT SUPPLIED IN EXAMPLE.
TYPE_4
DO?
; OVERFLOW NOT SUPPLIED IN EXAMPLE.
; SKIP RESERVED PART OF EXAMPLE
ORG
32'4
TYPE_32
; 8259A IRO - AVAILABLE
DO
?
TYPE_33
DO
?
; 8259A IR1 - AVAILABLE
TYPE_34
DO
?
; 8259A IR2 - AVA I LA BLE
TYPE_35
DO
TIMER_PULSE
; 8259A IR3
TYPE_36
DO
?
; 8259A IR4 - AVAILABLE
TYPE_37
DO
?
; 8259A IR5 - AVAILABLE
.
DO
?
TYPE_38
; 8259A IR6 - AVAILABLE
TYPE_39
DO
?
; 8259A IR7 - AVAILABLE
,
; POINTER FOR TYPE 40 SUPPLIED BY PLlM-86 COMPILER
INT_POINTERS
ENDS
SEGMENT
BATTERY
; THIS RAM SEGMENT IS BATTERY-POWERED. IT CONTAINS VITAL DATA
THAT MUST BE MAINTAINED DURING POWER OUTAGES.
;
STACK_PTR
OW
?'
; SP SAVE AREA
STACK_SEG
OW?
;SSSAVEAREA
; SPACE FOR OTHER VARIABLES COULD BE DEFINED HERE.
BATTERY
ENDS
DATA
SEGMENT
; RAM SEGMENT THAT.lS NOT BACKED UP BY BATTERY
N_PULSES
DB
1DUP{O)
; ETC.
DATA
ENDS
STACK
SEGMENT
; LOCATED IN BATTERY-POWERED RAM
OW
100 DUP (?)
STACK_TOP
STACK
;#TlMERPULSES
LABEL
; THIS IS AN ARBITRARY STACKSIZE
WORD
ENDS
; LABEL THE INITIAL TOS
INTERRUPT_HANDLERS
SEGMENT
; INTERRUPT PROCEDURES EXCEPT TYPE 40 (PLlM-86)
ASSUME:
CS:INTERRUPT_HANDLERS,DS:DA T A,SS:ST ACK, ES:BA TTERY
POWER_FAIL
PROC
; TYPE 2 INTERRUPT
; POWER FAIL DETECT CIRCUIT ACTIVATES NMI LINE ON CPU IF POWER IS
ABOUTTO BE LOST. THIS PROCEDURE SAVES THE PROCESSOR STATE IN
RAM (ASSUMED TO BE POWERED BY AN AUXILIARY SOURCE) SOTHAT IT
CAN BE RESTORED BY A WARM START ROUTINE IF POWER RETURNS
Figure 2-88. Interrupt Procedures Example
2-121
Mnemonics © Inl"I,1978
8086 AND 8088 CENTRAL PROCESSING UNITS
; IP, CS, AND FLAGS ARE ALREADY
SAVE THE OTHER REGISTERS.
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
ON THE STACK.
AX
BX
CX
OX
SI
01
BP
OS
ES
; CRITICAL MEMORY VARIABLES COULD ALSO BE SAVED ON THE STACK ATTHIS
POINT. ALTERNATIVELY, THEY COULD BE DEFINED IN THE "BATTERY"
SEGMENT, WHERE THEY WILL AUTOMATICALLY BE PROTECTED IF MAIN POWER
IS LOST.
; SAVE SP AND SS IN FIXED LOCATIONS THAT ARE KNOWN BY WARM START ROUTINE.
AX,BATTERY
MOV
MOV
ES,AX
MOV
ES:STACK_PTR,SP
MOV
ES:STACK~SEG,SS
; STOP GRACEFULLY
HLT
ENDP
TIMER_PULSE
PROC
; TYPE 35 INTERRUPT
; THIS PROCEDURE HANDLES THE 50MS INTERRUPTS GENERATED BY THE 8253.
IT COUNTS THE INTERRUPTS AND ACTIVATES THE TYPE 40 INTERRUPT
PROCEDURE ONCE PER SECOND.
,
; OS IS ASSUMED TO BE POINTING TOTHE DATA SEGMENT
,
; THE 8253 IS RUNNING FREE, AND AUTOMATICALLY LOWERS ITS INTERRUPT
REQUEST. IF A DEVICE REQUIRED ACKNOWLEDGEMENT,THE CODE MIGHT GO HERE.
,
; NOW PERFORM PROCESSING THAT MUST NOT BE INTERRUPTED (EXCEPT FOR NMI).
INC
N_PULSES
; ENABLE HIGHER-PRIORITY INTERRUPTS AND DO LESS CRITICAL PROCESSING
STI
N_PULSES,200; 1 SECOND PASSED?
CMP
JBE
DONE
; NO, GO ON.
; YES, RESET COUNT.
MOV
N_PULSES,O
INT
40
; UPDATE CLOCK
; SEND NON-SPECIFIC END-OF-INTERRUPT COMMAND TO 8259A, ENABLING EQUAL
;
OR LOWER PRIORITY INTERRUPTS.
DONE:
MOV
AL,020H
; EOI COMMAND
OUT
OCOH,AL
; 8259A pORT .
IRET
TIMER_PULSE
ENDP
INTERRUPT_HANDLERS
ENDS
CODE
SEGMENT
; THIS SEGMENT WOULD NORMALLY RESIDE IN ROM.
ASSUME
CS:CODE,DS:DATA,SS:STACK,ES:NOTHING
Figure 2-88_ Interrupt Procedures Example (Cont'd.)
Mnemonics © Intel, 1978
2-122
8086 AND 8088 CENTRAL PROCESSING UNITS
INIT
PROC
NEAR
; THIS PROCEDURE IS CALLED FOR BOTH WARM AND COLD STARTS TO INITIALIZE
THE 8253 AND THE 8259A. THIS ROUTINE DOES NOT USE STACK, DATA, OR
EXTRA SEGMENTS, AS THEY ARE NOT SET PREDICTABLY DURING A WARM START.
INTERRUPTS ARE DISABLED BY VIRTUE OFTHE SYSTEM RESET.
; INITIALIZE 8253 COUNTER 1 - OTHER COUNTERS NOT USED.
; CLK INPUT TO COUNTER IS ASSUMED TO BE 1.23 MHZ.
L050MS
HI50MS
CONTROL
COUNT_1
MODE2
EQU
EQU
EQU
EQU
EQU
OOOH
OFOH
OD6H
OD2H
01110100B
; COUNT VALUE IS
;
61440 DECIMAL.
; CONTROL PORT ADDRESS
; COUNTER 1 ADDRESS
; MODE 2, BINARY
; LOAD CONTROL BYTE
MOV
DX,CONTROL
MOV
AL,MODE2
OUT
DX,AL
MOV
DX,COUNT_1
; LOAD 50MS DOWNCOUNT
MOV
AL,L050MS
OUT
DX,AL
MOV
AL,HI50MS
DX,AL
OUT
; COUNTER NOW RUNNING, INTERRUPTS STILL DISABLED.
; INITIALIZE 8259A TO: SINGLE INTERRUPT CONTROLLER, EDGE-TRIGGERED,
; INTERRUPT TYPES 32-40 (DECIMAL) TO BE SENT TO CPU FOR INTERRUPT
; REQUESTS 0-7 RESPECTIVELY, 8086 MODE, NON-AUTOMATIC END-OF-INTERRU PT.
; MASK OFF UNUSED INTERRUPT REQUEST LINES.
ICW1
ICW2
ICW4
OCW1
PORT_A
PORT_B
EQU
EQU
EQU
EQU
EQU
EQU
; EDGE-TRIGGERED, SINGLE 8259A, ICW4 REQUIRED.
; TYPE 20H, 32 - 400
; 8086 MODE, NORMAL EOI
; MASK ALL BUT IR3
; ICW1 WRITTEN HERE
; OTHER ICW'S WRITTEN HERE
00010011B
00100000B
00000001B
11110111B
OCOH
OC2H
MOV
DX,PORT_A
; WRITE 1ST ICW
MOV
AL,ICW1
DX,AL
OUT
MOV
DX,PORT_B
; WRITE 2ND ICW
MOV
AL,ICW2
DX,AL
OUT
MOV
AL,ICW4
; WRITE 4TH ICW
OUT
DX,AL
MOV
AL,OCW1
; MASK UNl,ISED IR'S
OUT
DX,AL
; INITIALIZATION COMPLETE, INTERRUPTS STILL DISABLED
RET
INIT
ENDP
USER_PGM:
; "REAL" CODE WOULD GO HERE. THE EXAMPLE EXECUTES AN ENDLESS LOOP
UNTIL AN INTERRUPT OCCURS.
JMP
USER_PGM
; EXECUTION STARTS HERE WHEN CPU IS RESET.
POWER_FAILSTATUS
EQU
OEOH
ENABLE_RAM
EQU
OE2H
; PORT ADDRESS
; PORT ADDRESS
Figure 2-88. Interrupt Procedures Example (Cont'd.)
2-123
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
; ENABLE BATTERY-POWERED RAM SEGMENT
START:
MOV
AL,001H
ENABLE_RAM,AL
OUT
; DETERMINE WARM OR COLD START
IN
AL,POWER_FAIL-,-STATUS
RCR
AL,1
; ISOLATE LOW BIT
JC
WARM_START
COLD_START:
; INITIALIZE SEGMENT REGISTERS AND STACK POINTER.
ASSUME CS:CODE,DS:DATA,SS:STACK,ES:NOTHING
; RESET TAKES CARE OF CS AND IP.
AX,DATA
MOV
MOV
DS,AX
MOV
AX,STACK
MOV
SS,AX
MOV
SP ,OFFSET STACK_TOP
; INITIALIZE 8253 AND 8259A.
CALL
INIT
; ENABLE INTERRUPTS
STI
; START MAIN PROCESSING
JMP
WARM_START:
; INITIALIZE 8253 AND 8259A.
CALL
INIT
; RESTORE SYSTEM TO STATE AT THE TIME POWER FAILED
; MAKE BATTERY SEGMENT ADDRESSABLE
MOV
AX,BATTERY
MOV
DX,AX
; VARIABLES SAVED IN THE "BATTERY" SEGMENT WOULD BE MOVED
BACK TO UNPROTECTED RAM NOW. SEGMENT REGISTERS AND
"ASSUME" DIRECTIVES WOULD HAVE TO BE WRITTEN TO GAIN
ADDRESSABILITY.
; RESTORE THE OLD STACK
SS,DS:STACK_SEG
MOV
MOV
SP,DS:STACK_PTR
CODE
; RESTORE THE OTHER REGISTERS
ES
POP
POP
DS
POP
BP
POP
DI
POP
SI
POP
DX
POP
CX
POP
BX
POP
AX
; RESUME THE ROUTINE THAT WAS EXECUTING WHEN NMI WAS ACTIVATED.
I.E., POP CS,IP, & FLAGS; EFFECTIVELY "RETURNING" FROM THE
NMI PROCEDURE.
IRET
ENDS
; TERMINATE ASSEMBLY AND MARK BEGINNING OF THE PROGRAM.
END
START
Figure 2-88. Interrupt Procedures Example (Cont'd.)
Mnemonics © Intel, 1978
2-124
8086 AND 8088 CENTRAL PROCESSING UNITS
TYPE$40: DO;
DECLARE (HOUR, MIN, SEC) BYTE PUBLIC;
UPDATE$TOD: PROCEDURE INTERRUPT 40;
"THE PROCESSOR ACTIVATES THIS PROCEDURE
'TO HANDLE THE SOFTWARE INTERRUPT
'GENERATED EVERY SECOND BY THE TYPE 35
'EXTERNAL INTERRUPT PROCEDURE. THIS
'PROCEDURE UPDATES A REAL-TIME CLOCK.
'IT DOES NOT PRETEND TO BE "REALISTIC"
'AS THERE IS NO WAYTO SETTHE CLOCK."
SEC=SEC + 1;
IF SEC = 60 THEN DO;
SEC=O;
MIN=MIN + 1;
IF MIN = 60 THEN DO;
MIN =0;
HOUR=HOUR
1;
IF HOUR = 24 THEN DO;
HOUR = 0;
END;
END;
END;
END UPDATE$TOD;
END;
+
Figure 2-88. Interrupt Procedures Example (Cont'd_)
String Operations
(the index register is auto-decremented) to find
the last period (". ") in the string. Finally a byte
string of EBCDIC characters is translated to
ASCII. The translation is stopped at the end of
the string or when a carriage return character is
encountered, whichever occurs first. This is an
example of using the string primitives in combination with other instructions to build up more complex string processing operations.
Figure 2-89 illustrates typical use of string instructions and repeat prefixes. The XLAT instruction
also is demonstrated. The first example simply
moves 80 words of a string using MOVS. Then
two byte strings are compared to find the
alphabetically lower string, as might be done in a
sort. Next a string is scanned from right to left
ALPHA
SEGMENT
; THIS IS THE DATA THE STRING INSTRUCTIONS WILL USE
OUTPUT
DW 100
DUP (?)
INPUT
DW 100
DUP (?)
NAME_1
DB 'JONES, JON A'
NAME_2
DB 'JONES, JOHN'
SENTENCE
DB 80
DUP (?)
EBCDIC_CHARS DB 80
DUP (?)
ASCILCHARS
DB 80
DUP (?)
CONV_TAB
DB64
DUP(OH)
; EBCDIC TO ASCII
Figure 2-89. String Examples
2-125
Mnemonics © Intel, 1978
8086 AND 8088 CENTRAL PROCESSING UNITS
; ASCII NULLS ARE SUBSTITUTED FOR "UNPRINTABLE" CHARS
DB 1
20H
DB 9
DUP (OH)
DB7
'Q:','.','<~,'(','+',OH,'&'·
DB 9
DUP (OH)
DBB
'I', '$', '*', I)', ';',' ','-", 'I'
DB 8
DUP (OH)
DB6
",',','%','~','>','?'
DB 9
DUP (OH)
~
",':','#','@','''','=','''',
D817
OH, 'a', 'b', Ie', 'd', 'e', 'f', 'g', 'h', Ii'
DUP (OH)
'j', 'k', 'I', 'm', In', '0', 'P',.'q', 'r'
DUP (OH)
'~', '5', It', 'u', 'v', 'w', 'x', 'y', IZ'
DUP (OH)
, ','A', '8', 'e', '0', 'E', 'F', 'G', 'l-i' , 'I'
DUP (OH)
, " 'J', 'K', 'L', 'M', 'N', '0', 'P', '0', 'R'
DUP (OH)
DB7
DB9
DB7
DB9
DB22
DB 10
DB6
DB 10
DB6
DB 10
DB6
DB 10
DB6
, ',OH, IS', 'T', lU', 'V', 'W', 'X', IV"~, 'Z'
DUP (OH)
'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'
DUP (OH)
ALPHA
ENDS
STACK
SEGMENT
DW 100
DUP (?)
; THIS IS AN ARBITRARY STACK SIZE
; FOR ILLUSTRATION ONLY.
; INITIAL TOS
STACK_BASE
STACK
LABEL
ENDS
CODE
BEGIN:
SEGMENT
; SET UP SEGMENT REGISTERS. NOTICE THAT
; ES & DS POINTTO THE SAME SEGMENT, MEANING
; THAT THE CURRENT EXTRA & DATA
; SEGMENTS FULLY OVERLAP. THIS ALLOWS
; ANY STRJNG IN "ALPHA" TO BE USED
; AS A SOURCE OR A DESTINATION.
ASSUME CS: CODE, SS: STACK,
DS:ALPHA,ES:ALPHA
MOV
AX, STACK
MOV
SS, AX
MOV
SP, OFFSET STACK_BASE; INITIAL TOS
AX, ALPHA
MOV
MOV
DS,AX
MOV
ES,AX
&
WORD
; MOVE THE FIRST 80 WORDS OF "INPUT" TO
THE LAST 80 WORDS OF "OUTPUT".
LEA
SI, INPUT
LEA
DI, OUTPUT 4-20
; INITIALIZE
; INDEX REGISTERS
Figure 2-89. String Examples (Cont'd.)
Mnemonics © Intel, 1978
2-126
8086 AND 8088 CENTRAL PROCESSING UNITS
REP
MOV
CLD
MOVS
; REPETITION COUNT
; AUTO-INCREMENT
CX,80
OUTPUT, INPUT
; FIND THE ALPHABETICALLY
MOV
MOV
MOV
CLD
REPE CMPS
JB
NAME_1_LOW:
NAME_2_LOW:
LOWER OF 2 NAMES.
SI, OFFSET NAME_1 ; ALTERNATIVE
01, OFFSET NAME_2 ; TO LEA
CX, SIZE NAME_2
; CHAR. COUNT
; AUTO-INCREMENT
NAME_2, NAME_1
"WHILE EQUAL"
NAME_2_LOW
; NOT IN THIS EXAMPLE
; CONTROL COMES HERE IN THIS EXAMPLE.
; 01 POINTS TO BYTE ('H') THAT
; COMPARED UNEQUAL.
; FIND THE LAST PERIOD (' .') IN A TEXT STRING.
01, OFFSET SENTENCE +
MOV
&
LENGTH SENTENCE ; START AT END
MOV
CX, SIZE SENTENCE
STD
; AUTO-DECREMENT
MOV
AL, '.'
; SEARCH ARGUMENT
REPNE
SCAS
SENTENCE
; "WHILE NOT ="
JCXZ
NO_PERIOD
; IF CX=O, NO PERIOD FOUND
; IF CONTROL COMES HERE THEN
PERIOD:
; 01 POINTS TO LAST PERIOD IN SENTENCE.
NO_PERIOD:
; ETC.
; TRANSLATE A STRING OF EBCDIC CHARACTERS
TO ASCII, STOPPING IF A CARRIAGE RETURN
(ODH ASCII) IS ENCOUNTERED.
MOV
BX, OFFSET CONV __ TAB ; POINTTO TRANSLATE TABLE
MOV
SI, OFFSET EBCDIC__ CHARS ; INITIALIZE
01, OFFSET ASCII_CHARS
INDEX REGISTERS
MOV
CX, SIZE ASCII_CHARS
;
AND COUNTER
MOV
CLD
; AUTO-INCREMENT
NEXT:
LODS
EBCDIC_CHARS
; NEXT EBCDIC CHAR IN AL
XLAT
CONV_TAB
; TRANSLATE TO ASCII
ASCII_CHARS
; STORE FROM AL
STOS
AL,ODH
; IS IT CARRIAGE RETURN?
TEST
LOOPNE
NEXT
; NO, CONTINUE WHILE CX NOT 0
JE
CR_FOUND
; YES, JUMP
; CONTROL COMES HERE IF ALL CHARACTERS
HAVE BEEN TRANSLATED BUT NO
;
CARRIAGE RETURN IS PRESENT.
; ETC.
; 01-1 POINTS TO THE CARRIAGE RETURN
IN ASCII_CHARS.
CODE
ENDS
END
Figure 2-89. String Examples (Cont'd.)
2-12712-128
Mnemonics © Intel, 1978
The iAPX 8089
Input/Output
Processor
3
CHAPTER 3
THE 8089 INPUT/OUTPUT PROCESSOR
This chapter describes the 8089 Input/Output
Processor (lOP). Its organization parallels
Chapter 2; that is, sections generally proceed
from hardware to software topics as follows: .
v,,
1. Processor Overview
2. Processor Architecture
3. Memory
4.
5.
6.
7.
8.
9.
10.
Input/Output
Multiprocessing Features
Processor Control and Monitoring
Instruction Set
Addressing Modes
Programming Facilities
Programming Guidelines and Examples
A1S/D1S
Al31D13
Al61S3
Al2JD12
AU/S4
All1Dll
Al61SS
Al0/Dl0
A1B/S8
AB/DB
BHE
A6ID8
EXT 1
A7/D7
EXT2
A6ID8
DRQl
AS/DS
DRQ2
A4ID4
lOCK
A3ID3
A2JD2
52
51
Al/Dl
so
AO/DO
As in Chapter 2, the discussion is confined to
covering the hardware in functional terms; timing, electrical characteristics and other physical
interfacing data are provided in Chapter 4.
Vee
Al41D14
RQ/GT
SINTR·l
SEL
SINTR·2
CA
ClK
READY
V,,
RESET
Figure 3-1.8089 Input/Output Processor
Pin Diagram
3.1 Processor Overview
Evolution
The 8089 Input/Output Processor is a highperformance, general-purpose I/O system
implemented on a single chip. Within the 8089 are
two independent I/O channels, each of which
combines attributes of a CPU with those of a very
flexible DMA (direct memory access) controller.
For example, channels can execute programs like
CPUs; the lOP instruction set has about 50 different types of instructions specifically designed
for efficient input/output processing. Each channel also can perform high-speed DMA transfers; a
variety of optional operations allow the data to be
manipulated (e.g., translated or searched) as it is
transferred. The 8089 is contained in a 40-pin
dual in-line package (figure 3-1) and operates
from a single + 5V power source. An integral
member of the 8086 family, the lOP is directly
compatible with both the 8086· and 8088 when
these processors are configured in maximum
mode. The lOP also may be used in any system
that incorporates Intel's Multibus™ shared bus
architecture, or a superset of the Multibus™
design.
Figure 3-2 depicts the general trend in CPU and
I/O device relationships in the first three generations of microprocessors. First generation CPUs
were forced to deal directly with substantial
numbers of TTL components, often performing
transfers at the bit level. Only a very limited
number of relatively slow devices could be
supported.
Single-chip interface controllers were introduced
in the second generation. These devices removed
the lowest level of device control from the CPU
and let the CPU transfer whole bytes at once.
With the introduction of DMA controllers, highspeed devices could be added to a system, and
whole blocks of data could be transferred without
CPU intervention. Compared to the previous
generation, I/O device and DMA controllers
allowed microprocessors to be applied to problems that required moderate levels of I/O, both in
terms of the numbers of devices that could be supported and the transfer speeds of those devices.
3-1
8089 INPUT IOUTPUT PROCESSOR
..
.
The controllers themselves;' however, still
required a considerable amount of attention from
the CPU, and in many cases the CPU had to
respond to an interrupt with every byte read or
written. The CPU also had to stop while DMA
transfers were performed.
Principles of Operation
Since the 8089 is a new concept in microprocessor
components, this section surveys the basic operation of the lOP as background to the. detailed
descriptions provide9,. in the rest of the chapter.
This summary deliberately omits some operating
details in order to provide an integrated over:view
of basic concepts.
.
,
The 8089 introduces the third generation of
inputloutputprocessing. It continues the trend of
simplifying the CPU's "view",.ofIlO devices by
removing another level of control from the CPU.
The CPU performs an I/O op~ration by building
a message in memory that describes the function
to be performed; the lOP reads the message, carries out the operation and notifies'the CPU when
it has finished. AllI/O devices appear to the CPU
as transmitting and receiving whole blocks of
data; the lOP can make both byte- and word-level
transfers invisible to the CPU; The lOP assumes
all device controller overhead, performs both programmed and DMA transfers; and can recover
from "soft" I/O errors withoutC,PU intervention; all of these activities may be performed
while the CPU is attending to other tasks.
CPU/IOP Communications
A CPU communicates with-an lOP in two distinct
modes: initialization and command. The
initialization sequence is typically performed
when the system is powered-up or reset. The CPU
initializes the lOP by preparing a series of linked
message bloc'ks in memory. Ona signal from the
CPU, the lOP reads these blocks and determines
from them how the data buses are configured and
how access to the buses is to be controlled.
HOLC/SOLC
PROTOCOL
CONTROLLER
(FUTURE CONTROLLER)
I
... ,r~.;;;~,
-I
I
? }---
'" A.... ,/
'" '" FLOPPY DISK
CONTROLLER
Figure 3-2. lOP Evolution
3-2
I/O
L ~E~C': .J
8089 INPUT /OUTPUT PROCESSOR
Following initialization, the CPU directs all communications to either of the lOP's two channels;
indeed, during normal operation the lOP appears
to be two separate devices-channel 1 and channel2. All CPU-to-channel communications center
on the channel control block (CB) illustrated in
figure 3-3. The CB is located in the CPU's
memory space, and its address is passed to the
lOP during initialization. Half of the block is
dedicated to each channel. The channel maintains
the BUSY flag that indicates whether it is in the
midst of an operation or is available for a new
command. The CPU sets the CCW (channel command word) to indicate what kind of operation
the lOP is. to perform. Six different commands
allow the CPU to start and stop programs,
remove interrupt requests, etc.
tain space for variables (results) that the channel
is to return to the CPU. Except for the first two
words, the format and size of a parameter block
are completely open; the PB may be set up to
exchange any kind of information between the
CPU and the channel program.
A task block is a channel program-a sequence of
8089 instructions that will perform an operation.
A typical channel program might use parameter
block data to set up the lOP and a device controller for a transfer, perform the transfer, return
the results, and then halt. However, there are no
restrictions on what a channel program can do; its
function may be simple or elaborate to suit the
needs of the application.
Before the CPU starts a channel program, it links
the program (TB) to the parameter block and the
parameter block to the CB as shown in figure 3-3.
The links are standard 8086/8088 doubleword
pointer variables; the lower-addressed word contains an offset, and the higher-addressed word
contains a segment base value. A system may
have many different parameter and task blocks;
however, only one of each is ever linked to a
channel at any given time.
If the CPU is dispatching a channel to run a program, it directs the channel to a parameter block
(PB) and a task block (TB); these are also shown
in figure 3-3. The parameter block is analogous to
a parameter list passed by a program to a
subroutine; it contains variable data that the
channel program is to use in carrying out its
assignment. The parameter block also may con-
CHANNEL CONTROL BLOCK (CB)
(RESERVED)
r--
I
I
I
I
I
I
I
I
I
~
-{
-p(~~~r:,i1ETRB~LS~C&Kci~~~~i)R-
I
BUSY
}CHANNEL2
ccw
(RESERVED)
~
}CHANNELl
ccw
BUSY
L
~
1
"-P~~~~~1~rBBA~~C&K6~~~Jf)R- ~
87
_ _15
______
_________________ ,
CHANNEL 1 PARAMETER BLOCK (PS)
CHANNEl2 PARAMETER BLOCK (PS)
r
CHANNEL PROGRAM PARAMETERS
(APPLICATION.DEFINED)
i
{
1
TASK BLOCK POINTER
",:,:-_(S_EG_M_EN_T_BA_S_E&_O_F_FS_ET_l~ 0 - '
I
I
CHANNEL 2 TASK BLOCK (TB)
(CHANNEL PROGRAM)
I
I
I
I
r
INSTR68~~IONS
(APPLICATIONDEFINED)
r
~-L---------I
I
I
I
I
I
I
I
CHANNEL 1 TASK BLOCK (TB)
(CHANNEL PROGRAM)
J
INSTR88g~IONS
(APPLICATIONDEFINED)
J
L_L...--_
Figure 3-3. Command Communication Blocks
3-3
80891NPUT/OUTPUT PROCESSOR
Channels
After the CPU has filled in the CCW and has
linked the CB to a parameter block and a task
block, if appropriate, it issues a channel attention
(CA). This is done by activating the lOP's CA
(channel attention) and SEL (channel select) pins.
The state of SEL at the falling edge of CA directs
the channel attention to channell or channel 2. If
the lOP is located in the CPU's 110 space, it
appears to the CPU as two consecutive 110 ports
(one for each channel), and an OUT instruction
to the port functions as a CA. If the lOP is
memory-mapped, the channels appear as two
consecutive memory locations, and any memory
reference instruction (e.g., MOV) to these locations causes a channel attention.
Each of the two lOP channels operates
independently, and each has its own. register set,
channel attention, interrupt request and DMA
control signals. At a given point in time, a chan~
nel may be idle, executing a program, performing
a DMA transfer, or responding to a channel
attention. Although only one channel actually
runs at a time, thechannels can be active .concurrently, alternating their operations (e.g., .channel
1 may execute instructions in the periods between
successive DMA transfer cycles run by channel 2).
A built-in priority system allows high-priority
activities on one channel to preempt less critica]
operations on the other channel. The CPU is able
to further adjust priorities to handle special cases.
The CPU starts the channel and can halt it, suspend it, or cause it to resume a s·uspended< operation by placing different values in the CCW.
An lOP channel attention is functionally similar
to a CPU interrupt. When the channel recognizes
the CA, it stops what it is doing (it will typically
be idle) and examines the command in the CCW.
If it is to start a program, the channel loads the
addresses of the parameter and task blocks into
internal registers, sets its BUSY flag and starts
executing the channel program. After it has issued
the CA, the CPU is free to perform other processing; the channel can perform its function in
parallel, subject to limitations imposed by bus
configurations (discussed shortly).
Channel Programs (Task Blocks)
Channel programs are written in ASM-89, the
8089 assembly language. About 50 basic instructions are available. These instructions operate on
bit, byte, word and doubleword (pointer) variable
types; a 20-bit physical address variable type (not
used by the 8086/8088) can also be manipulated.
Data may be taken from registers, immediate constants and memory. Four memory addressing
modes allow flexible access to both memory
variables and I/O devices located anywhere in
either the CPU's megabyte memory space or in
the 8089's 64k 110 space.
When the channel has completed its program, it
notifies the CPU by clearing its BUSY flag in the
CB. Optionally, it may issue an interrupt request
to the CPU.
The CPU/lOP communication structure is summarized in figure 3-4. Most communication takes
place via "message areas" shared in common
memory. The only direct hardware communications between the devices are channel attentions
and interrupt requests.
The lOP instruction set contains general purpose
instructions similar to those found in CPUs as
well as instructions specifically tailored for 110
CHANNEL ATTENTION
CPU
MESSAGES
IN
MEMORY
INTERRUPT
Figure 3-4. CPU/lOP Communication
3-4
lOP
8089 INPUT/OUTPUT PROCESSOR
operations. Data transfer, simple arithmetic,
logical and address manipulation operations are
available. Unconditional jump and call instructions also are provided so that channel programs
can link to each other. An individual bit may be
set or cleared with a single instruction. Conditional jumps can test a bit and jump if it is set (or
cleared), or can test a value and jump if it is zero
(or non-zero). Other instructions initiate DMA
transfers, perform a locked test-and-set
semaphore operation, and issue an interrupt
request to the CPU.
Between the fetch and store cycles, the lOP can
operate on the data. A byte may be translated to
another code (e.g., EBCDIC to ASCII), or compared to a search value, or both, if desired.
A transfer can be terminated by several
programmer-specified conditions. The channel
can stop the transfer when a specified number (up
to 64k) of bytes has been transferred. An external
device may stop a transfer by signaling on the
channel's external terminate pin. The channel can
stop the transfer when a byte (possibly translated)
compares equal, or unequal, to a search value.
Single-cycle termination, which stops unconditionally after one byte or word has been stored, is
also available.
DMA Transfers
The 8089 XFER (transfer) instruction prepares
the channel for a DMA transfer. It executes one
additional instruction, then suspends program
execution and enters the DMA transfer mode.
The transfer is governed by channel registers
setup by the program prior to executing the
XFER instruction.
When the transfer terminates, the channel
automatically resumes program execution. The
channel program can determine the cause of the
termination in situations where multiple terminations are possible (e.g., terminating when 80 bytes
are transferred or a carriage return character is
encountered, whichever occurs first). As an example of post-transfer processing, the channel program could read a result register from the I/O
device controller to determine if the transfer was
performed successfully. If not (e.g., a CRC error
was detected by the controller), the channel program could retry the operation without CPU
intervention.
Data is transferred from a source to a destination.
The source and destination may be any locations
in the CPU's memory space or in the lOP's I/O
space; the lOP makes no distinction between
memory components and I/O devices. Thus
transfers may be made from I/O device to
memory, memory to I/O device, memory to
memory and I/O device to I/O device. The lOP
automatically matches 8- and 16-bit components
to each other.
A channel program typically ends by posting the
result of the operation to a field supplied in the
parameter block, optionally interrupting the
CPU, and then halting. When the channel halts,
its BUSY flag in the channel control block is
cleared to indicate its availability for another
operation. As an alternative to being interrupted
by the channel, the CPU can poll this flag to
determine when the operation has been
completed.
Individual transfer cycles (i.e., the movement of a
byte or a word) may be synchronized by a signal
(DMA request) from the source or from the
destination. In the synchronized mode, the channel waits for the synchronizing signal before starting the next transfer cycle. The transfer also may
be unsynchronized, in which case the channel
begins the next transfer cycle immediately upon
completion of the previous cycle.
Bus Configurations
A transfer cycle is performed in two steps: fetching a byte or word from the source into the lOP
and then storing it from the lOP into the destination. The lOP automatically optimizes the
transfer to make best use of the available data bus
widths. For example, if data is being transferred
from an 8-bit device to memory that resides on a
16-bit bus (e.g., 8086 memory), the lOP will normally run two one-byte fetch cycles and then store
the full word in a single cycle.
As shown in figure 3-5, the lOP can access
memory or ports (I/O devices) located in a
I-megabyte system space and memory or ports
located in a 64-kilobyte I/O space. Although the
lOP only has one physical data bus, it is useful to
think of the lOP as accessing the system space via
a system data bus and the I/O space over an I/O
data bus. The distinction between the "two"
buses is based on the type-of-cycle signals output
3-5
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSOR
by the 8288 Bus Controller. Components in the
system space respond to the memory read and
memory write signals, whether they are memory
or I/O devices. Components in the I/O space
respond to the I/O read and I/O write signals.
Thus I/O devices located in the system space are
memory-mapped and memory in the I/O space is
I/O-mapped. The two basic configuration options differ in the degree to which the lOP shares
these buses with the CPU. Both configurations require an 8086/8088 CPU to be strapped in maximummode.
8088 or 16 bits if the CPU is an 8086). The lOP
system space corresponds to the CPU memory
space, and the lOP I/O space corresponds to the
CPU I/O space. Channel programs are located in
the system space; I/O devices may be located in
either space. The lOP requests use of the bus for
channel program instruction fetches as well as for
DMA and programmed transfers. In the local
configuration, either the lOP or the CPU may use
the buses, but not both simultaneously. The
advantage of the local configuration is that
intelligent DMA may be added to a system with
no additional components beyond the lOP. The
disadvantage is that parallel operation of the processors is limited to cases in which the CPU has
instruction in its queue that can be executed
without using the bus.
In the local configuration, shown in figure 3-6,
the lOP (or lOPs if two are used) shares both
buses with the CPU. The system bus and the I/O
bus are the same width (8 bits if the CPU is an
MEMORY
MEMORY
SYSTEM SPACE (1 MBYTE)
1/0 SPACE (64 KBYTES)
SYSTEM
DATA
BUS
1/0
DATA
BUS
lOP
Figure 3-5. lOP Data Buses
3-6
8089 INPUT IOUTPUT PROCESSOR
8089 lOP
.... -
EJ
. SYSTEM SPACE
Figure 3-6. Local Configuration
In the remote configuration (figure 3-7), the lOP
(or lOPs) shares a common system bus with the
CPU. Access to this bus is controlled by 8289 Bus
Arbiters. The lOP's I/O bus, however, is
physically separated from the CPU in the remote
configuration. Two lOPs can share the local I/O
bus. Any number of remote lOPs may be contained in a system, configured in remote clusters
of one or two. The local I/O bus need not be the
same physical width as the shared system bus,
allowing an lOP, for example, to interface 8-bit
peripherals to an 8086. hi the remote configuration, the lOP can access local I/O devices and
memory without using the shared system bus,
thereby reducing bus contention with the CPU.
Contention can further be reduced by locating the
lOP's channel programs in the local I/O space.
The lOP can then also fetch instructions without
accessing the system bus; Parameter, channel
control and other CPUIIOP communication
blocks must be located in system memory,
however, so that both processors can access them.
The remote configuration thus increases the
degree to which an lOP and a CPU can operate in
parallel and thereby increases a system's
throughput potential. The price paid for this is
that additional hardware must be added to
arbitrate use of the shared bus, and to separate
the shared and local buses (see Chapter'4 for
details).
.
It is also possible to configure an lOP remote to
one CPU, and local to another CPU (see figure
3-8). The local CPU could be used to perform
heavy computational routines for the lOP.
3-7
8089 INPUT /OUTPUT PROCESSOR
r-----------,
I
, . - - , '---7 I
I
I
(1/0 DEVICE)
.... __ ~
11/0 DEVICEI
~
__
~
!+I
80861
8088
CPU
8289
BUS
ARBITER
L _ .2!'!!.O~UO.£.A.!;.I/.2.S~~ _ ..J
NOT ACCESSIBLE TO lOPs
SYSTEM SPACE
8089
lOP
'"::>
EJ
III
0
:::
8289
BUS
ARBITER
LOCAL BUS
I ARBITRATION
-'
. If
DMA is to be terminated when a specific number
of bytes has been transferred, BC should be
loaded with the desired byte count before
initiating the transfer. During DMA, BC is
decremented for each byte transferred, whether
byte count termination has been selected or not.
If BC reaches zero, the transfer is stopped only if
byte count termination has been specified. If byte
count termination has not been selected, BC
"wraps around" from OH to FFFFH and continues to be decremented.
Program Status Word (PsW)
Mask/Compare (MC). A channel program may
use MC for a general register. This register also
may be used in either a channel program or in a
DMA transfer to perform a masked compare of a
byte value. To use MC in this way, the program
loads a compare value in the low-order eight bits
of the register and a mask value in the upper eight
bits (see figure 3-15). A "1" in a mask bit selects
the bit in the corresponding position in the compare value; a "0" in a mask bit masks the cor-
Each channel maintains its own program status
word (PSW) as shown in figure 3-17. Channel
programs do not have access to the PSW. The
PSW records the state of the the channel so that
channel operation may be suspended and then
resumed later. When the CPU issues a "suspend"
command, the. channel saves the PSW, task
pointer, and task pointer tag bit in the first four
bytes of the channel's parameter block as shown
in figure 3-18. Upon. receipt of a subsequent
3-18
8089 INPUT /OUTPUT PROCESSOR
15
I
7
F
I
0
ITRI SYN I S I L I C ITSI TX I TBC I
-,.-
I
-r-
TT
I
I
TMC
I
I
I
L
TERMINATE ON MASKED COMPARE
TERMINATE ON BYTE COUNT
TERMINATE ON EXTERNAL SIGNAL
TERMINATE AFTER SINGLE TRANSFER
CHAINED CHANNEL PROGRAM
EXECUTION
LOCK BUS DURING TRANSFER
SOURCE/DESTINATION
SYNCHRONIZATION
TRANSLATE
FUNCTION (PORT TO PORT,
PORT TO MEMORY, ETC.)
Figure 3-16.
Channe~
"resume" command, the PSW, TP, and TP tag
bit are restored from the parameter block save
area and execution resumes.
Control Register
°
7
1+,1
BII*ITBI slDI
I
~~~
Two conditions override the normal channel
priority mechanism. If one channel is performing
DMA (priority 1) and the channel receives a channel attention (priority 2), the channel attention is
serviced at the end of the current DMA transfer
cycle. This override prevents a synchronized
DMA transfers from "shutting out" a channel
attention. DMA terminations and chained channel programs postpone recognition of a CA on
the other channel; the CA is latched, however,
and is serviced as soon as priorities permit.
L
L
DESTINATIONBUSLOGICALWIDTHIO",l'18)
SOURCE BUS LOGICAL WIDTH (0 "8,1 " 16)
TASK BLOCK (CHANNEL PROGRAM) IN PROGRESS
INTERRUPT CONTROL (0 = DISABLED, 1 " ENABLED)
INTERRUPT SERVICE (0 "SINTR N INACTIVE 1 " SINTAN ACTIVE)
BUS LOAD LIMIT
TRANSFER IN PROGRESS
PRIORITY BIT
Figure 3-17. Program Status Word
The lOP's LOCK (bus lock) signal also
supersedes channel switching. A running channel
will not relinquish control of the processor while
LOCK is active, regardless of the priorities of the
activities on the two channels. This is consistent
with the purpose of the LOCK signal: to
guarantee exclusive access to a shared resource in
a multiprocessing system. Refer to sections 3.5
and 3.7 for futher information on the LOCK
signal and the TSL instruction.
8 7
15
TP 15-8
PSW
;:::
IL
1
_PP
TP7·0
1TP 19-161 TAG 10
0 0
REMAINDER OF PARAMETER BLOCK
_________________
-
PP + 2
~
I
~
Tag Bits
Registers GA, GB, GC, and TP are called pointer
registers because they may be used to access, or
Figure 3-18. Channel State Save Area
3-19
80891NPUT/OUTPUTPROCESSOR
each internal cycle, the CCU lets one channel or
the other execute the next internal cycle. No extra
overhead is incurred by this channel switching.
The basis for making the determination is a
priority mechanism built into the lOP. This
mechanism recognizes that some kinds of
activities (e.g., DMA) are more important than
others. Each activity that a channel can perform
has a priority that reflects its relative importance
(see table 3-3).
point to, addresses in either the system space or
the I/O space. The pointer registers may address
either memory or I/O devices (lOP instructions
do not distinguish between memory and I/O
devices since the latter are memory-mapped). The
tag bit associated with each register (figure 3-14)
determines whether the register points to an
address in the system. space (tag=O) or the I/O
space (tag::,I).
The CCU sets or clears TP's tag bit depending on
whether the command it receives from the CPU is
"start channel program in system space," or
"start channel program in I/O space." Channel
programs alter the tag bits of GA, GB,GC, and
TP by using different instructions for loading the
registers. Briefly, a "load pointer" instruction
clears a tag bit, a "move" instruction sets a tag
bit, and a "move pointer" instruction moves a
memory value (either 0 or 1) to a tag bit. Section
3.9 covers these instructions in detail.
Concurrent Channel Operation
Two new activities are introduced in table 3-3.
When a DMA transfer terminates, the channel
executes a short internal channel program. This
DMA termination program adjusts TP so that the
user's program resumes at the instruction
specified when the transfer was setup (this is
discussed in detail in section 3.4). Similarly, when
a channel attention is recognized, the channel
executes an internal program that examines the
CCWand carries out its command. Both of these
programs consist of standard 8089 instructions
that are fetched from internal ROM. Intel
Application Note AP-50, Debugging Strategies
and Considerations for 8089 Systems, lists the
instructions in these programs. Users monitoring
the bus during debugging may see operands read
or written by the termination or channel attention
programs. The instructions themselves, however,
will not appear on the bus as they are resident in
the chip.
Both channels may be active concurrently, but
only one can actually run at a time. At the end of
Notice also that, according to table 3-3, a channel
program may run at priority 3 or at priority 1.
If a register points to the system space, all 20 bits
are placed on the address lines to allow the full
megabyte to be directly addressed. If a register
points to the I/O space, the upper four bits of the
address lines are undefined; the lower 16 bits are
sufficient to access any location in the 64k byte
I/O space.
Table 3-3. Channel Priorities and Interleave Boundaries
Channel Activity
Priority
(1 = highest)
Interleave Boundary
ByDMA
By Instruction
DMA transfer
1
Bus cycle'
DMA termination sequence
1
Internal cycle
None
Channel program (chained)
1
Internal cycle 2
Instruction
Channel attention sequence
2
Internal cycle
None
Channel program (not chained)
3
Internal cycle 2
Instruction
Idle
4
Two clocks
Two clocks
I DMA is not interleaved while LOCK is active.
2Except TSL instruction; see section 3.. 7.
3-20
Bus cycle'
80891NPUT/OUTPUTPROCESSOR
Channel program priority is determined by the
chain bit in the channel control register. If this bit
is cleared, the program runs at normal priority
(3); if it is set, the program is said to be chained,
and it runs at the same priority as DMA. Thus,
the chain bit provides a way to raise the priority
of a critical channel program.
instruction boundaries: a program on channel B
will not run until channel A reaches the end of an
instruction. Note that a DMA termination
sequence or channel attention sequence on channel A cannot be interleaved by instructions on
channel B, regardless of channel B's priority.
These internal programs are short, however, and
will not delay channel B for long (see Chapter 4
for timing infurmation).
The CCU lets the channel with the highest priority
run. If both channels are running activities with
the same priority, the CCU examines the priority
bits in the PSWs. If the priority bits are unequal,
the channel with the higher value (1) runs. Thus,
the priority bit serves as a "tie breaker" when the
channels are otherwise at the same priority level.
The value of the priority bit in the PSW is loaded
from a corresponding bit in the CCW; therefore,
the CPU can control which channel will run when
the channels are at the same priority level. The
priority bit has no effect when the channel
priorities are different. If both channels are at the
same priority level and if both priority bits are
equal, the channels run alternately without any
additional overhead.
Table 3-4 summarizes the channel switching
mechanism with several examples. It is important
to remember that channel switching occurs only
when both channels are ready to run. In typical
applications, one of the channels will be idle
much of the time, either because it is waiting to be
. dispatched by the CPU or because it is waiting for
a DMA request in a synchronized transfer. (During a synchronized transfer, the channel is idle
between DMA requests; for many peripherals, the
channel will spend much more time idling than
executing DMA cycles.) The real potential for one
channel "shutting out" a priority 1 activity on the
other channel is largely limited to unsynchronized
DMA transfers and locked transfers (synchronized or unsynchronized). Long, chained channel
programs and high-speed synchronized DMA will
slow a priority 1 activity on the other channel, but
will not shut it out because the channels will alternate (assuming their priority bits are equal). A
chained channel program will shut out any lower
priority activity on the other channel, including a
channel attention. (The channel attention is
latched by the lOP, however, so it will execute
when the other channel drops to a lower priority.)
Chained channel programs should therefore be
used with discretion and should be made as short
as possible.
The CCU switches channels only at certain points
called interleave boundaries; these vary according
to the type of activity running in each channel and
are shown in· table 3-3. In table 3-3 and in the
following .discussion, the terms "channel A" and
"channel B" are used to identify two active channels that are bidding for control of an lOP.
"Channel A" is the channel that last ran and will
run again unless the CCU switches to "channel
B." Where the CCU switches from one channel
(channel A) to another (channel B) depends on
whether channel B is performing DMA or is
executing instructions. For this determination,
instructions in the internal ROM are considered
the same as instructions executed in user-written
channel programs (chained or not chained). Table
3-3 shows that a switch from channel A to channel B will occur sooner if channel B is running
DMA. DMA, then, interleaves instruction execution at internal cycle boundaries. Since instructions are often composed of several internal
cycles, instruction execution on channel A can be
suspended by DMA on channel B (when channel
A next runs, the instruction is resumed from the
point of suspension). DMA on channel A is
interleaved by DMA on channel B after any bus
cycle (when channel A runs again, the DMA
transfer sequence is resumed from the point of
suspension). If both channels are executing programs, the interleave boundaries are extended to
3.3 Memory
The 8089 can access memory components located
in two different address spaces. The system space,
which coincides with the CPU's memory space,
may contain up to 1,048,576 bytes. The 110
space, which may either coincide with the CPU's
110 space or be local (private) to the lOP, may
contain up to 65,536 bytes. Memory components
in the system space should respond to the memory
read and write commands issued by the 8288 Bus
Controller. Memory components in the I/O space
must respond to 8288 I/O read and write commands. Memory in either space may be
3-21
8089 INPUT /OUTPUT PROCESSOR
Table 3-4. Channel Switching Examples
Channel.A (Ran Last)
Channel B
Result
Activity
Chain
Bit
Priority
LOCK
Bit
Activity
Chain
Bit
Priority
Bit
DMA transfer
DMA transfer
X
X
X
X
Inactive
Inactive
Idle
Channel attention
X
X
X
X
Channel program
Channel program
X
X
0
0
Inactive
Inactive
Channel program
Channel program
X
X
1
0
Channel program
DMA transfer
1
X
X
1
Inactive
Inactive
Channel program
Channel program
0
1
X
1
Channel attention
X
X
Inactive
Channel program
1
X
DMA transfer
Channel program
(TSL instruction)
X
0
X
X
Active
Active
Channel attention
DMA transfer
X
X
X
X
A runs.
A runs until end of current
transfer cycle; then Bruns.
Bruns.
A and B alternate by
instruction.
A runs.
B runs one bus or internal
cycle following each bus cycle
run by A.'
A runs if it has started the
sequence; otherwise Bruns.
A runs until DMA terminates.
A completes TSL instruction,
LOCK goes inactive and B
runs.
'If transfer is synchronized, B also runs when A goes idle between transfer cycles.
implemented like 8086 memory (l6-bit words split
into even- and odd-addressed 8-bit banks) or 8088
memory (a single 8-bit bank). See Chapter 4 for
physical implementation considerations.
LOW MEMORY
OOOOOH
SYSTEM
SPACE
L
HIGH MEMORY
00001H
00002H
I.
07
07
07
L
7
0
HIGH MEMORY
0000H0001H
From a software point of view, both 8089
memory spaces are organized as unsegmented
arrays of individually addressable 8-bit bytes
(figure 3-19). Instructions and data may be stored
at any address without regard for alignment
(figure 3-20).
J
-I
1 MEGABYTE
LOW MEMORY
I/O
SPACE
/FFFEH FFFFFH
1111111111111,11111115 51111111111111
7
Storage Organization
5
0002H
5· fFFFEH
FFFFH
1111111111111111111115 5k111111111111:
I.
07
07
07
64K BYTES
I
0
-I
Figure 3-19. Storage Organization
The lOP views the system space differently from
the 8086 or 8088 with which it typically shares the
space. The 8086 and 8088 differentiate between a
location's logical (segment and offset) address
and its physical (20-bit) address.
The 8089 does not "see" the logically segmented
structure of the memory space; it uses its 20-bit
pointer registers to access all locations in the
system space by their physical addresses. Memory
in the 8089 I/O space is treated similarly except
that only 16 bits are needed to address any
location.
1AH 1BH
1CH 1DH
1EH 1FH
20H
21H
Figure 3-20. Instruction and Variable Storage
3-22
8089 INPUT /OUTPUT PROCESSOR
Following Intel convention, word data is stored
with the most-significant byte in the higher
address (see figure 3-21). The 8089 recognizes the
doubleword pointer variable used by the 8086 and
8088 (figure 3-22). The lower-addressed word of
the pointer contains an offset value, and the
higher-addressed word contains a segment base
address. Each word is stored conventionally, with
the higher-addressed byte containing the mostsignificant eight bits of the word. The 8089 can
convert a doubleword pointer into a 20-bit
physical address when it is loaded into a pointer
register to address system memory; A special 3byte variable, called a physical address pointer
(figure 3-23), is used to save and restore pointer
registers and their associated tag bits.
ware and software products; the locations are OH
through 7FH (128 bytes) and FFFFOH through
FFFFFH (16 bytes), as shown in figure 3-24. The
low addresses are used for part of the 8086/8088
interrupt pointer table. Locations FFFFOHFFFFBH are used for 8086, 8088 and 8089 startup
sequences; the remaining locations are reserved
by Intel.
If an lOP is configured locally, its I/O space coincides with the CPU's I/O space, and it must
respect the reserved addresses F8H-FFH. The
entire I/O space of a remotely-configured lOP
may be used without restriction.
Using any dedicated or reserved addresses may
inhibit the compatibility of a system with current
or future Intel hardware and software products.
Dedicated and Reserved Memory
Locations
Dynamic Relocation
The extreme low and high addresses of the system
space are dedicated to specific processor functions or are reserved for use by other Intel hard-
The 8089 is very well-suited to environments in
which programs do not occupy static memory
locations, but are moved about during execution.
Dynamic code relocation allows systems to make
efficient use of limited memory resources by
transferring programs between external storage
and memory, and by combining scattered free
areas of memory into larger, more useful, continuous spaces.
lOP channel programs are inherently positionindependent, the only restriction being that channel programs that transfer to each other or
share data must be moved as a unit. Since the lOP
VALUE OF WORD STORED AT 724H: 5502H
Figure 3-21; Storage of Word Variables
VALUEOF DOUBLEWORD POINTER STORED AT 4H:
SEGMENT BASE ADDRESS: 3B4CH
OFFSET:65H
Figure 3-22. Storage of Doubleword Pointer Variables
.3-23
8089 INPUT /OUTPUT PROCESSOR
FFFFFH
POINTER
REGISTER
RESERVED
FFFFCH
FFFFBH
DEDICATED
FFFFOH
FFFEFH
I
..,
OPEN
101H
102H
HEX
[""
OPEN
r
I--------I~~~
MEMORY
BINARY
RESERVED
I--~R~ES~E~R~VE~D~~}~~
1--~i.:2.!~:!!..._-I F8H
1-------I1~~
VALUE OF PHYSICAL ADDRESS PDINTER AT 100H:
ADDRESS: 26SF3H
TAG: 0
F7H
OPEN
...._ _ _ _ _.JOH
DEDICATED
...._ _ _ _ _... OH
SYSTEM SPACE
Figure 3-23. Storage of Physical Address
Pointer Variables
1/0 SPACE
(LOCAL CONFIGURATION ONLY)
Figure 3-24. Reserved Memory Locations
register are used for I/O space locations; all 20
bits are used for system space addresses. Different
types of memory accesses use base registers as
shown in table 3-5. The 8089 addressing modes
allow the base address of a memory operand to be
modified by other registers and constant values to
yield the effective address of the operand (see section 3.8).
receives the address of a channel program and its
associated parameter block when it is dispatched
by the CPU, the location of these blocks is
immaterial and can change from one dispatch to
the next. (Note, however, that the channel control
block cannot be moved without reinitializing the
lOP.) Typically, then, the CPU would direct the
movement of lOP channel programs and
parameter blocks. These blocks, of course, cannot be moved while they are in use.
Notice that table 3-5 indicates that memory
operands may be addressed using register PP in
addition to GA, GB, and GC. PP is maintained
by the lOP and can neither be read nor written by
a channel program; it can be used, however, to
access data in the parameter block. PP has no
associated tag bit; a reference to it implies the
system space, where a parameter block always
resides.
While the CPU may be in charge of relocation,
the lOP is an excellent vehicle for performing the
actual transfer of channel programs, parameter
blocks, and CPU programs as well. A very simple
channel program can transfer code between
memory locations by DMA much faster than the
equivalent CPU instructions, and transfers
between disk and memory also can be performed
more efficiently.
Table 3-5. Base Register Use in Memory Access
Memory Access
Base Register
Memory Access
Instruction Fetch
DMASource
DMA Destination
DMATranslate Table
Memory Operand
Memory accesses are always performed using a
pointer register and its associated tag bit. The tag
bit indicates whether the access is to the system
space (tag=O) or the I/O space (tag=I). The
pointer register contains the base address of the
location; i.e., the pointer register is used as a base
register. Only the low-order 16 bits of the pointer
TP
GAorGB'
GAorGB'
GC
GA or GB or GC or PP'
'As specified in CC register
'As specified in instruction
3-24
8089 INPUT /OUTPUT PROCESSOR
The lOP is told the physical widths of the system
and 110 buses when it is initialized. If a bus is
eight bits wide, the lOP accesses memory on this
bus likj': an 8088. Instruction fetches and operand
reads and writes are performed one byte at a time;
one bus cycle is run for each memory access.
Word operands are accessed in two cycles, completely transparent to software. Instruction
fetches are made as needed, and the instruction
stream is not queued.
into a given address is actually memory or 110 is
immaterial. All addresses in both the system and
I/O spaces are equally accessible, and transfers
may be made between the two spaces as well as
within either address space.
Programmed I/O
A channel program performs 110 similar to the
way a CPU communicates with memory-mapped
1/0 devices. Memory reference instructions perform the transfer rather than "dedicated" I/O
instructions, such as the 8086/8088 IN and OUT
instructions. Programmed 1/0 is typically used to
prepare a device controller for a DMA transfer
and to obtain statuslresult information from the
controller following termination of the transfer.
It may be used, however, with any device whose
transfer rate does not require DMA.
The lOP accesses memory on a 16-bit bus like an
8086. As mentioned in the previous section, the
instruction stream is generally fetched in words
from even addresses with the second byte held in
the one-byte queue. If a word operand is aligned
(i.e., located at an even address), the 8089 will
access it in a single 16-bit bus cycle. If a word
operand is unaligned (i.e., located at an odd
address), the word will be accessed in two consecutive 8-bit bus cycles. Byte operands are
always accessed in 8-bit bus cycles.
I/O Instructions
For memory on 16-bit buses, performance is
improved and bus contention is reduced if word
operands are stored at even addresses. The
instruction queue tends to reduce the effect of
alignment on instructions fetched on a 16-bit bus,
In tight loops, performance can be increased by
word-aligning transfer targets.
Since the 8089 does not distinguish between
memory components and 110 devices, any
instruction that accepts a byte or word· memory
operand can be used to access an 110 device.
Most memory reference instructions take a source
operand or a destination operand, or both. The
instructions generally obtain data from the source
operand, operate on the data, and then place the
result of the operation in the destination operand.
Therefore, when a source operand refers to an
address where an 110 device is located, data is
input from the device. Similarly, when a destination operand refers to an 1/0 device address, data
is output to the device.
Notice that the correct operation of a program is
completely independent of memory bus width. A
channel program written for one system that uses
an 8-bit memory bus will execute without
modification if the bus is increased to 16 bits. It is
good practice, though, to write all programs as
though they are to run on 16-bit systems; i.e., to
align word operands. Such programs will then
make optimal use of the bus in whatever system
they are run.
Most 1/0 device controllers have one or more
internal registers that accept commands and
supply status or result information. Working with
these registers typically involves:
3.4 Input/Output
• reading or writing the entire register;
• setting or clearing some bits in a register while
leaving others alone; or
• testing a single bit in a register.
The 8089 combines the programmed 1/0
capabilities of a CPU with the high-speed block
transfer facility of a DMA controller. It also provides additional features (e.g., compare and
translate during DMA) and is more flexible than a
typical CPU or DMA controller. The 8089
transfers data from a source address to a destination address. Whether the component mapped
Table 3-6 shows some of the 8089 instructions
that are useful for performing these kinds of
operations. Sectian 3.7 covers- the 8089 instruction set in detail.
3-25
8089 INPUT /OUTPUT PROCESSOR
with the corresponding address spaces of. the
other 8086 family processors.
Table 3-6. Memory Reference Instructions
Used for I/O
Instruction
Effect on I/O Device
I/O Bus Transfers
MOV/MOVB Read or write word / byte
AND/ANDB
Clear multiple bits in word/byte
OR/ORB
Set multiple bits in word/byte
CLR
Clear' single bit (in byte)
SET
Set single bit (in byte)
JBT
Read (byte) and jump if
single bit =1
JNBT
Read (byte) and jump if
single bit =0
Table 3-7 shows the number of bus cycles the lOP
runs for all combinations of bus size, transfer size
(byte or word), and transfer address (even or
odd). Bus width refers to the physical bus
implementation; the instruction mnemonic determines whether a byte or a word is transferred.
Both.8- and 16-bit devices may reside on a 16-bit
bus. All 16-bit devices should be located at even
addresses so that transfers will be performed in
one bus cycle. The 8-bit devices on a 16-bit bus
may be located at odd or even addresses. The
internal registers in an 8-bit device on a 16-bit bus
must be assigned all-odd or all-even addresses
that are two bytes apart (e.g., IH, 3H, 5H, or 2H,
4H, 6H). All 8-bit peripherals should be referenced with byte instructions, and 16-bit devices
should be referenced with word instructions.
Odd-addressed 8-bit devices must be able to
transfer data on the upper eight bits of the 16-bit
physical data bus.
Device Addressing
Since memory reference instructions are used to
perform programmed I/O, device addressing. is
very similar to memory addressing. An operand
that refers to an I/O device always specifies one
of the pointer registers GA, GB, or GC (PP is
legal, but an I/O device would not normally be
mapped into a parameter block). The base
address of the device is taken from the specified
pointer register. Any of the memory addressing
modes (see section 3.8) may be used to modify the
base address to produce the effective (actual)
address of the device. The pointer register's tag
bit locates the device in the system space (tag=O)
or in the I/O space (tag=I). If the device is in
the I/O space, only the low-order 16 bits of the
pointer register are used for the base address; all
20 bits are used for a system space address. The
lOP's system and I/O spaces are fully compatible
Only 8-bit devices should be connected to an 8-bit
bus, . and these should only be referenced with
byte instructions. An 8-bit device on an 8-bit bus
may be located at an odd or even address, and its
internal registers may be assigned consecutive
addresses (e.g., IH, 2H, 3H). Assigning all-odd
or all-even addresses, however, will simplify conversion to a 16-bit bus at a later date.
Table 3-7. Programmed I/O Bus Transfers
BusWidth:
8
Instruction:
Device Address:
Bus Cycles:
16
byte
word
even
odd
even
odd
even
odd
even
odd'
1
1
2
2
1
1
1
2
, not normally used
Mnemonics © Intel, 1979
byte.
word'
3-26
8089 INPUT /OUTPUT PROCESSOR
parameters. If this type of controller is being
used, the channel program instruction that sends
the last parameter should follow the 8089 XFER
instruction. (The XFER instruction places the
channel in DMA mode after the next instruction;
this is explained in more detail later in this
section.)
DMA Transfers
In addition to byte- and word-oriented programmed I/O, the 8089 can transfer blocks of
data by direct memory access. A block may be
transferred between any two addresses; memoryto-memory transfers are performed as easily as
memory-to-port, port-to-memory or port-to-port
exchanges. There is no limitation on the size of
the block that can be transferred except that the
block cannot exceed 64k bytes if byte count termination is used. A channel program typically
prepares for a DMA transfer by writing commands to a device controller and initializing channel registers that are used during the transfer. No .
instructions are executed during the transfer,
however, and very high throughput speeds can be
achieved.
Preparing the Channel
For a channel to perform a DMA transfer, it must
be provided with information that describes the
operation. The channel program provides this
information by loading values into channel
registers and, in one case, by executing a special
instruction (see table 3-8).
Source and . Destination Pointers. One
register is loaded to point to the transfer source;
the other points to the destination. A bit in the
channel control register is set to indicate which
register is the source pointer. If a register is
pointed at a memory location, it should contain
the address where the transfer is to begin - i.e.,
the lowest address in the buffer. The channel
automatically increments a memory pointer as the
transfer proceeds. If the tag bit selects the I/O
space, the upper four bits of the register are
ignored; if the tag selects the system space, all 20
bits are used. The source and destination may be
located in the same or in different address spaces.
Preparing the Device Controller
Most controllers that can peform DMA transfers
are quite flexible in that they can perform several
different types of operations. For example, an
8271 Floppy Disk Controller can read a sector,
write a sector, seek to track 0, etc. The controller
typically has one or more internal registers that
are "programmed" to perform a given operation.
Often, certain registers will contain status
information that can be read to determine if the
controller is busy, if it has detected an error, etc.
An 8089 channel program views these device
registers as a series of memory locations. The
channel program typically places the device's base
address in a pointer register and uses programmed
I/O to communicate with the registers.
Translate Table Pointer. If the data is to be
translated as it is transferred, GC should be
pointed at the first (lowest-addressed) byte in a
256-byte translation table. The table may be
10Gated in either the system or I/O space, and GC
Some controllers start a DMA transfer
immediately upon receiving the last of a series of
Table 3-8. DMA Transfer Control Information
Information
Source Pointer
Destination Pointer
Translate Table Pointer
Byte Count
Mask/Compare Values
Logical Bus Width
Channel Control
Register or Instruction
Required or Optional
GAorGB
GAorGB
GC
BC
MC
WID
CC
Required
Required
Optional
Optional
Optional
Optional"
Required
"Must be executed once following processor RESET.
3-27
Mnemonics © Intel, 1979
8089 INPUT IOUTPUT PROCESSOR
ference between BC's value before and after the
transfer does not accurately reflect the number of
bytes transferred tothe destination.
should be loaded by an instruction that sets or
clears its tag bit as appropriate. The translate
operation is only defined for byte data; source
and destination logical bus widths must both be
set to eight bits.
Mask/Compare Values. If the transfer is to be
terminated when a byte (possibly translated) is
found equal or unequal to a search value, MC
should be loaded as described in section 3.2. MC
isnot altered during the transfer. Normally, the
logical destination bus width is set to eight bits
when transferred data. is being compared. If the
logical destination width is 16 bits, only the loworder byte of each word is compared.
The channel translates a byte by treating it as an
unsigned 8-bit binary number. This number is
added to the content of register GC to form a
memory address; GC is not altered by the operation. If GC points to the 110 space, its upper four
bits are ignored in the operation. The byte at this
address (which is in the translate table) is then
fetched from memory, replacing the source byte.
Figure 3-25 illustrates the translate process.
Logical Bus Width. The 8089 WID (logical bus
width) instruction is used to set the logical width
of the source and destination buses for a DMA
transfer. Any bus whose physical width is eight
bits can only have a logical width ofeight bits. A
16 cbit physical bus,however, .can have a logical
width of 8 or.16 bits; i.e., it can be. used as.either
an 8-bit or 16-bit bus in any given transfer.
Logical bus widths are set independently for each
channel.
Byte Count. If the transfer is to be terminated
on byte count~ i.e., after a specific number of
bytes have been transferred-the desired count
should be loaded into register BC as an unsigned
16-bit number. The channel decrements BC as the
transfer proceeds, whether or not byte count termination .has been specifi~d. There are cases
(discussed later in. this section) where the dif-
TRANSLATE TABLE
IN SYSTEM OR 1/0 SPACE
00200
+
=
I-~
3F
4C
1.66119
GC
•
SOURCE BYTE
I
B
00202
:
~ ______ J
TRANSLATE ADDRESS
TO DESTINATION
TRANSLATED BYTE
Figure 3-25. Translate Operation
Mnemonics © Intel. 1979
3-28
87
1(
8089 INPUT /OUTPUT PROCESSOR
ability to execute a synchronized transfer: in
effect, the peripheral synchronizes the transfer
through theuse of wait states. Chapter 4 discusses
synchronization in more detail.
For a transfer to or from an I/O device on a
16-bit physical bus, the logical bus width should
be set equal to the peripheral's width; Le., 8 or 16
bits. Transfers to or from 16-bit'memory will run
at maximum speed if the logical bus width is set to
16 since the channel will fetch/store words. In the
following cases, however, the logical width
should be set to 8:
•
the data is being translated,
•
the data is being compared under mask, and
the 16-bit memory is the destination of the
transfer.
Source synchronization is typically selected when
the source is an I/O device and the destination is
memory. The I/O device starts the next transfer
cycle by activating the channel's DRQ (DMA
request) line. The channel then runs one transfer
cycle and waits for the next DRQ.
Destination synchronization is most often used
,when the source is memory and the destination is
an I/O device. Again, the I/O device controls the
transfer frequency by signaling on DRQ when it is
ready to receive the next byte or word.
The WID instruction sets both logical widths and
remains in effect until another WID instruction is
execu ted. Following processor reset, the, settings
of the logical bus widths are unprecrictable.
Therefore, the WID instruction must be executed
before the first DMA transfer.
The source field (bit 10) identifies register GA or
GB as the source pointer (and the other as the
destination pointer).
Channel Control. The 16 bits of the CC register
are divided into 10 fields that specify how the
DMA transfer is to be executed (see figure 3-26).
A channel program typically sets these fields by
loading a word into the register.
The lock field (bit 9) may be used to instruct the
channel to assert the processor's bus lock (LOCK)
signal during the transfer. In a sourcesynchronized transfer, LOCK is active from the
time the first DMA request is received until the
channel enters the termination sequence. In a
destination-synchronized transfer LOCK is active
from the first fetch (which precedes the first
.DMA request) until the channel enters the termination sequence.
The function field (bits 15-14) identifies the
source and destination as memory or ports (1)0
devices). During the transfer, the channel
increments source/destination, poirtter registers
that refer to memory so that the data will be
placed in successive locations. Pointers that refer
to I/O devices remain constant throughout the
transfer.
The chain field (bit 8) is not used during the
transfer. As, discussed previously, setting this
bit raises channel program execution to priority
level I.
The translate field (bit 13) controls data translation. If it is set, each incomiilgbyte is translated
using the table pointed to by register ,Oe.
Translate is defined only for byte transfers; the
destination bus must have a logical width ofeight.
The synchronization field (bits 12-11) specifies
how the transfer is to be synchronized.
Un synchronized ("free running") transfers al'e
typically used in memory-to-memory moves. The
channel begins the next transfer cycle immediately
upon completion of the current cycle (assuming it
has the bus). Slow memories, which cannot run as
fast as the channel, can extend bus cycles by
signaling "not ready" to the 8284 Clock,
Generator, which will insert wait states into the '
bus cycle. A similar technique may be used with
peripherals whose speed excecds the channel's
3-29
rhe terminate on single transfer field (bit 7) can
be used to cause the chaimel to run one complete
transfer cycle only-:-i.e., to transfer one byte or
word and immediately resume channel program
execution. When single transfer is specified, any
other termination conditions are ignored. Single
transfer termination can be used with low-speed
devices, such as keyboards and communication
lines, to translate and/or compare one byte as it
transferred.
The thre,e low-order fields in register CC instruct
the channel when to terminate the transfer,
ussumingthat single transfer has not been
selected. Three termination conditions may be
specified singly or in combination.
Mnemonics © Inlel, 1979
8089 INPUT /OUTPUT PROCESSOR
15
7
Ir
ITRI STNI S I Lie ITsl Tf I
£.
0
T~C I TM~
00
01
10
11
FUNCTION
PORT TO PORT
MEMORY TO PORT
PORT TO MEMORY
MEMORY TO MEMORY
TR
o
1
TRANSLATE
NO TRANSLATE
TRANSLATE
SYN
00
01
10
11
SYNCHRONIZATION
NO SYNCHRONIZATION
SYNCHRONIZE ON SOURCE
SYNCHRONIZE ON DESTINATION
RESERVED BY INTEL
.
S
o
1
SOURCE
GA POINTS TO SOURCE
GB POINTS TO SOURCE
L
o
1
LOCK
NO LOCK
ACTUATE LOCK DURING TRANSFER
~
.2
o
1
. NO CHAINING
. CHAINED: RAISE TB TO PRIORITY 1
TS
o
1
TERMINATE ON SINGLE TRANSFER
NO·SINGLE TRANSFER TERMINATION
. TERMINATE AFTER SINGLE TRANSFER
TX
00
01
10
11
TERMINATE ON EXTERNAL SIGNAL
NO EXTERNAL TERMINATION
TERMINATE ON EXT ACTIVE; OFFSET
TERMINATE ON EXT ACTIVE; OFFSET
TERMINATE ON EXT ACTIVE; OFFSET
TBC
00
01
10
11
TERMINATE ON BYTE COUNT
NO BYTE COUNT TERMINATION
TERMINATE ON BC 0; OFFSET
TERMINATE ON BC 0; OFFSET
TERMINATE ON BC 0; OFFSET
TMC
000
001
010
011
100
101
110
111
TERMINATE ON MASKED COMPARE
NO MASK/COMPARE TERMINATION
TERMINATE ON MATCH; OFFSET 0
TERMINATE ON MATCH; OFFSET::: 4
TERMINATE ON MATCH; OFFSET 8
(NO EFFECT)
TERMINATE ON NON-MATCH; OFFSET
TERMINATE ON NON-MATCH; OFFSET
TERMINATE ON NON-MATCH; OFFSET
=
=
=
=0
=4
=8
.
=0
=4
=8
=
=
=0
=4
=8
Figure 3-26. Channel Control Register Fields
3-30
I
8089 INPUT/OUTPUT PROCESSOR
External termination allows an I/O device
(typically, the one that is synchronizing the
transfer) to stop the transfer by activating the
channel's EXT (external terminate) line. If byte
count termination is selected, the channel will
stop when BC=O. If masked compare termination
is specified, the channel will stop the transfer
when a byte is found that is equal or unequal (two
options are available) to the low-order byte in MC
as masked by MC's high-order byte. The byte that
stops the termination is transferred. If translate
has been specified, the translated byte is
compared.
~
-(COULD DE A. DIFFERENT INSTRUCTION)
L-.-r.:P~ER~FORM TRANSFER
(TP POINTS TO 1ST LJMP INSTRUCTION) _
When a DMA transfer ends, the channel adds a
value called the termination offset to the task
pointer and resumes channel program execution
at that point in the program. The termination offset may assume a value of 0, 4, or 8. Single
transfer termination always results in a termination offset of O. Figure 3-27 shows how the termination offsets can be used as indices into a
three-element "jump table" that identifies the
condition that caused the termination.
OFFSET_O_COOE:!
T
EXECUTED IFTERMINATION
OFFseT. 0
OFFSET
_4_COOE:1
EXECUTED IF TERMINATION
OFFSET. •
8_CODE:1
'
T
EXECUTED IF TERMINATION
OFFSET. 1
As an example of using the jump table, consider a
case in which a transfer is to terminate when 80
bytes have been transferred or a linefeed
character is detected, whichever occurs first. The
program would load 80H into BC and OOOAH
into MC (ASCII line feed, no bits masked). The
channel program could assign byte count termination an offset of 0 and masked compare termination an offset of 4. If the transfer is terminated by
byte count (no linefeed is found), the instruction
at location TP + 0 will be executed first after the
termination. If the linefeed is found before the
byte count expires, the instruction at TP + 4 will
be executed first. The LJMP (long unconditional
jump, see section 3.7) instruction is four bytes
long and can be placed at TP + 0 and TP + 4 to
cause the channel program to jump to a different
routine, depending on how the transfer
terminates.
1
T
1
T' ,
OFFSET __
......_ " ,
J
1
T
Figure 3-27. Termination Jump Table
the preceding example, this would occur if the
80th character were a !inefeed. When multiple terminations occur simultaneously, the channel
indicates that termination resulted from the condition with the largest offset value. In the
preceding example, if byte count and search termination occur at the same time, the channel pro.
gram resumes at TP + 4.
Beginning the Transfer
The 8089 XFER (transfer) instruction puts the
channel into DMA transfer mode after the
following instruction has been executed. This
technique gives the channel time to set itself up
when it is used with device controllers, such as the
8271 Floppy Disk Controller, that begin transferring immediately upon receipt of the last in a
series of parameters or commands. If the transfer
is to or from such a device, the last parameter
should be sent to the device after the XFER
instruction. If this type of device is ·not being
used, the instruction following XFER would
If the transfer can only terminate in one way and
that condition is assigned an offset of 0, there is
no need for the jump table. Code which is to be
unconditionally executed when. the transfer ends
can immediately follow the instruction after
XFER. This is also the case when single transfer is
specified (execution always resumes at TP + 0).
It is possible, however, for two, or even three, termination conditions to arise at the same time. In
3-31
Mnemonics © Intel, 1979
80891NPUTJOUTPUT PROCESSOR
Table 3-9. DMA Transfer
Assembly/Disassembly'
typically 'send a "start" command to the controller. If a memory-to-memory transfer is being
made, any instruction may follow XFER except
one that alters GA; GB, or CC. The HL T instruction should normally not . be. coded after the
XFER; doing so clears the channel's BUSY flag,
but allows the DMA,transfer to proceed.
Address
. (Sou,rce- ,
Destination)
EVEN-EVEN
EVEN-ODD
ODD-EVEN
ODD-ODD
DMA Transfer Cycle
A DMA transfer cycle is illustrated in figure 3-28;
a complete transfer isaseries ofthese cycles run
until a termination condition is encountered. The
figure is deliberateiy simplified to explain the
general operation of .a DMA· transfer; in particular, the updating of the souJce. and destination
pointers (GA and GB) can be more complex than
the figure indicates: Notice'that it is possible to
start an unending transfcrr by rwtspecifying atermination condition in CC or by specifying a condition that never occurs; it is the programmer's
responsibility to ensure that the transfer eventu.
ally stops~
B-B
B-B
B-B
B-B
B/B-W
B-B.
B/B-W
B-B
W-B/B
W-B/B
B-B
B-B
W-W
W-B/B
B/B-W
B-+B
.B= Byte Fetched or Stored in 1 Bus Cycle
W= Word Fetched or Stored in 1 Bus Cycle
B/B= 2 Bytes Fetched or Stored in 2 Bus Cycles
type of synchronization may be specified for a
giventnlnsfer), the channel waits for DRQ before
ruiminga .store cycle. It' 'stores .a word or the
lower-addressed byte (which may be the only byte
or the first of two bytes). Table 3-9 shows the
possible combinations of even/odd addresses and
lo-gical bus widths that define the store cycle.
Whenever stores are to memory on a 16-bit logical
bus, the channel stores words; except that bytes
may be stored on the first and last cycles.
If the transfer is source-synchronized, the channel
waits until the synchronizing device activates the
channd!sDRQ line. The other channel is free to
run during this idle period. The channel fetches a
byte or a word, depending on the source address
(contained in GA or GB) and. the Jogical bus
width. Table 3-9 shows how a. channeJperforms
the fetch/store sequence for all.combinations of
addresses and bus widths. If the destination is on
a 16-bit iogical bus. and' the source is on an 8-bit
logical bus, and the transfer is to an even address,
the channel fetches a second byte and asserribles a
word internally. During each fetch, the channel
decrements BC according to whether a byte or
word is obtained. Thus BC always indicates the
number of bytes fetched.
The channel samples EXT again after the first
store cycle and, if it is active, the channel prevents
the second store cycle from running. If specified
in the Cc register, the low-order byte is compared
to the value in MC. A "hit" on the comparison
(equal or unequal, as indicated in CC) also
prevents the second of two scheduled store cycles
from running. In both of these cases, one byte has
been "overfetched," and this is reflected in BC's
value. It would be unusual, however; for a synchronizing device to issue EXT in the midst of a
DMA cycle. Note 'also that EXT is valid only
when DRQ is inactive. Chapter 4 covers the timing requirements for these two signals in detail.
The channel; samples its EXT lineaftereyery bus
cycle in the trimsfer. If EXT is recognized after
the. first of, two. scheduled fetches, the second
fetch is notruI),.After the fetch sequence has.been
cPrnpleted: the channel translates the data if this
option is' specified in q::: ..
GA and GB are updated next. Only memory
pointers are incremented; pointers to 110 devices
remain constant throughout the transfer ..
If any termination condition has occurred during
this cycle, the channel stops the transfer; It uses
If a word has been fetched or assembled,and
bytes are to be stored (destination bus is eight bits
or transfer is to an odd address), the channel
disassembles the word into two bytes. If the
transfer is destination-synchronized (only one
Mnemonics ©'l'ntel:1979 .
Logical Bus Width
Source-Destination)
8-8 8-16 16-8 16-16
the content of the CC register to assign a value to
the termination offset, to reflect the cause of the
termination. The channel adds this offset to TP
and resumes cliannel program execution at the
location now addressed by TP. This offset will
3-32
8089 INPUT/OUTPUT PROCESSOR
ASSEMBLE
BYTES
(OPTIONAL)
Figure 3-28. Simplified DMA Transfer Flowchart
Following the Transfer·
always be zero, four, or eight bytes past the end
of the instruction following the XFER instruction.
A DMA transfer updates register Be, register GA
(if it points to memory), and register GB (if it
points to memory). If the original contents of
these registers are needed following the transfer,
the contents should be saved in memory prior to
executing the XFER instruction.
If no termination condition is detected and
another byte remains to be stored, the channel
stores this byte, waiting for DRQ -if necessary,
and updates the source and destination pointers.
After the store, it again checks for termination.
3-33
Mnemonics © Intel, 1979
80891NPUT/OUTPUT PROCESSOR
A program may determine the address of the last
byte stored by a DMA transfer by inspecting the
pointer registers as shown in table 3-10. The
number of bytes stored is equal to:
lasLbyte_address - first_byte_address
The 8089's TSL (test and set while locked) instruction enables it to share a resource, such as a
buffer, with other processors by means of
semaphore (see section 2.5 for a discussion of the
use of semaphores to control access to shared
resources). Finally, the 8089 can lock the system
bus for the duration of a DMAtransfer to ensure
that the transfer completes without interference
from other processors on the bus.
+ 1.
For port-to-port transfers, the number of bytes
transferred can be determined by subtracting the
final value of BC from its original value provided
that:
•
the original BC > final BC,
•
a transfer cycle is not "chopped off" before
it completes by a masked compare or external termination.
In the remote configuration, the 8089 is electrically compatible with Intel's Multibus ™ multimaster bus design. This means that the power and
convenience of 8089 I/O processing can be used
in 8080- or 8085-based systems that implement the
Multibus protocol or a superset of it. This
includes single-board computers such as Intel's
iSBC 80120™ and iSBC 80/30™ boards. In addition, the lOP can access other iSBC board
products such as memory and communications
controllers.
In general, programs should not use the contents
of GA, GB and BC following a transfer except as
noted above and in table 3-10. This is because the·
contents of the registers are affeCted by numerous
conditions, particularly when the transfer is terminated by EXT. In particular, when a program
is performing a sequence of transfers, it should
reload these registers before each transfer.
Bus Arbitration
The 8089 shares its system bus with a CPU, and
may also share its I/O bus with an lOP or another
CPU. Only one processor ata time may drive a
bus. When two (or more) processors want to use a
shared bus, the system must provide an arbitration mechanism that will grant the bus to one of
the processors. This section describes the bus
arbitration facilities that may be used with the
8089 and covers their applicability to different
lOP configurations.
3.5 Multiprocessing Features
The 8089 shares the multiprocessing facilities
common to the 8086 family of processors. It has
on-chip logic for arbitrating the use of the local
bus with a CPU or another lOP; system bus
arbitration is delegated to an 8289 Bus Arbiter.
Table 3-10. Address of Last Byte Stored
Termination
Source
Destination
Synchronization
Last Byte Stored
byte count
memory
memory
port
memory
port
memory
any
any
any
destination pointer',
source pointer
destination pOinter
masked compare
memory
memory
port
memory
port
memory
any
any
any
destination pointer
source pointer
destination pOinter
external
memory
memory
port
memory
port
memory
unsynchronized
destination
source
destination pointer
source pointer'
destination pointer
'Source pointer may also be used;
'If transfer is B/B-+W, source pointer must be decremented by 1 to pointto last byte transferred.
Mnemonics © Intel, 1979
3-34
8089 INPUT/OUTPUT PROCESSOR
between two lOPs. In this case, one lOP is
designated the master, and the other is designated
the slave. However, the only difference between a
master and a slave running in mode I is that the
master has the bus at initialization time. Both
processors may request the bus from each other at
any time. The processor that has the bus will
grant it to the requester as soon as one of the
following occurs on either channel:
Request/Grant Line
When an 8089 is directly connected to
another 8089, an 8086 or an 8088, the
RQ/GT (request/grant) lines built into all of
these processors are used to arbitrate use of a
local bus. In the local mode, RQ/GT is used
to control access· to both the system and the
110 bus.
As discussed in section 2.6, the CPU's
request/grant lines (RQ/GTO and RQ/GTl)
operate as follows:
•
•
•
an external processor sends a pulse to the
CPU to request use of the bus;
the CPU finishes its current bus cycle, if one
is in progress, and sends a pulse to the processor to indicate that it has been granted the
bus; and
.
•
an unchained channel program instruction is
completed, or
•
a channel goes idle due to a program halt or
the completion of a synchronized transfer
cycle (the channel waits for a DMA request).
Execution of a chained channel program, a DMA
termination sequence, a channel attention
sequence, or a synchronized DMA transfer (i.e., a
high-priority operation) on either channel
prevents the lOP from granting the bus to the
requesting lOP.
when the external processor is finished with
the bus, it sends a final pulse to the CPU, to
indicate that it is releasing the bus.
The 8089's request/grant circuit can operate in
two modes; the mode is selected when the lOP is
initialized (see section 3.6). Mode 0 is compatible
with the 8086/8088 request/grant circuit and
must be specified when the 8089's RQ/GT line is
connected to RQ/GTO or RQ/GTl of one of
these.£PUs. Mode 0 may ~ s~ified when
RQ/GT of one 8089 is tied to RQ/GT of another
8089. When mode 0 is used with a CPU, the CPU
is designated the master, and the lOP is
designated a slave. When mode 0 is used with
another lOP, one lOP is the master, and the other
is the slave. Master/slave designation also is made
at initialization time as discussed in section 3.6.
The master has the bus when the system is initialized and keeps the bus until it is requested by
the slave. When the slave requests the bus, the
master grants it if the master is idle. In this sense,
the CPU becomes idle at the end of the current
bus cycle. An lOP master, on the other hand,
does not become idle until both channels have
halted program execution or are waiting for DMA
requests. Once granted the bus, the slave (always
an lOP) uses it until both channels are idle, and
then releases it to the master. In mode 0, the
master has no way of requesting the slave to
return the bus.
The handshaking sequence in mode I is:
•
the ~uesting processor pulses once· on
RQ/GT;
•
•
the processor with the bus grants it by
pulsing once; and
if the processor granting the bus wants it
back immediately (for exampl.!2..to~tch the
next instruction), it will pulse RQ/GT again,
two clocks after the grant pulse.
The fundamental difference between the· two
modes is the frequency with which the bus can be
switched between the two processors when both
are active. In mode 0, the processor that has the
bus will tend to keep it for relatively long periods
if it is executing a channel program. Mode I in
effect places unchained channel programs at a
lower priority since the processor will give up the
bus at the end of the next instruction. Therefore,
when both processors are running channel programs or synchronized DMA, they will share the
bus more or less equally. When a processor
changes to what would typically be considered a
higher-priority activity such as chained program
execution or DMA termination, it will generally
be able to obtain the bus quickly and keep the bus
for the duration of the more critical activity.
Mode I operation of the request/grant lines may
only be used to arbitrate use of a private I/O bus
3-35
8089 INPUT /OUTPUT PROCESSOR
8289 Bus Arbiter
Table 3-11 summarizes the bus arbitration
requirements and options by lOP configuration.
In the local configuration, all bus arbitration is
performed by the request/grant lines without
additional hardware. One lOP maybe connected
to each of the CPU's RQ/GT lines. The lOP connected toRQ/OTO will obtain the bus if both processors make simultaneous requests.
When an lOP is configured remotely,an 8289 Bus
Arbiter is used to control its access to the shared
system bus (the CPU also has its own 8289). In a
remote cluster. of two lOPs or an lOP and a CPU,
one 8289 .controls access to the system bus for
both processors in the cluster. The 8289 has
several operating modes; when used with an 8089,
the 8289 is usually strapped in its lOB (110
Peripheral Bus) mode.
Since a si!!gle lOP in a remote configuration does
not use RQ/GT, its mode may be set to 0 or 1
without affect. The single remote lOP, however,
must be initialized as a master. If two remote
lOPs share an 110 bus, one must be a master and
the other a slave; both must be initialized to use
the same request/grant mode. Normally, mode 1
will be selected for its improved responsiveness,
and the designation of master will be arbitrary. If
one lOP must have the I/O bus when the system
comes up, it should be initialized as the master.
The 8289 monitors the lOP's status lines. When
these indicate that the lOP needs a cycle on the
system bus, and the lOP does not presently have
the bus,the8289 activates a bus request signal.
This signal, along with the bus request lines of
other 8289s on the same bus, can be routed to an
external priority-resolving circuit. At the end of
the current bus cycle, this circuit grants the bus to
the requesting 8289 with the highest priority.
Several different prioritizing techniques may be
used; ina typical system, an lOP would have
higher bus priority than a CPU. If the 8289 does
not obtain the bus for its processor, it makes the
bus appear "not ready" as if a slow memory were
being accessed. The processor's clock generator
responds to the. "not ready" condition by inserting wait states into the lOP's bus cycle, thereby
extending the cycle until the bus is acquired.
When a remote lOP shares its 1/0 bus with a
local CPU, it must be a slave and must use
request/grant mode O.
Bus Load Limit
A locally configured lOP effectively has higher
bus priority than the CPU since the CPU will
grant the bus upon request from the lOP. One or
two local lOPs can .potentially monopolize the
bus at the expense of the CPU. Of course, if the
lOP activities are time-critical, this is exactly what
should happen. On the other hand, there may be
low-priority channel programs that have less
demanding performance requirements.
Bus Arbitration for lOP Configurations
When the CPU initializes an lOP, it must inform
the lOP whether it is a master or a. slave, and
which request/grant mode is to be used. This section covers the requirements and options
available for each lOP configuration; section 3.6
describes how the information is communicated
at initialization time.
In such cases, the CPU may set a CCW bit called
bus load limit to constrain the channel's use of the
bus during normal (unchained) channel program
Table 3-11. Bus Arbitration Requirements and Options
Local
Remote With
Local CPU
Remote
.
lOP
Master/
Slave
RQ/GT
Mode
Master/
Slave
RQ/GT
Mode
Master/
Slave
RQ/GT
Mode
IOP1·
Slave
0
Master
Oor 1
Slave
0
IOP2
Slave
0
Slave
Same as
Master
N/A
N/A
3-36
8089 INPUT /OUTPUT PROCESSOR
execution. When this bit is set, the channel
decrements a 7-bit counter from 7F (127) to OH
with each instruction executed. Since the counter
is decremented once per clock period, the channel
waits a minimum of 128 clock cycles before it executes the next instruction. By forcing the execution time of all instructions to 128 clocks, the use
of the bus is reduced to between 3 and 25 percent
of the available bus cycles.
access of multiple processors to a shared
resource.) The instruction activates LOCK and
inspects the value of a byte in memory. If the
value of the byte is OH, it is changed (set) to a
value specified in the instruction and the following instruction is executed. If the byte does not
contain OH, control is transferred to another location specified in the instruction. The bus is locked
from the time the byte is read until it is either written or control is transferred to ensure that another
processor does not access the variable after TSL
has read it, but before it has updated it (i.e.,
between bus cycles). The following line of code
will repeatedly test a semaphore pointed to by GA
until it is found to contain zero:
Setting the bus load limit effectively enables a
CPU to slow the execution of a normal channel
program, thus freeing up bus cycles. This is of
most use in local configurations, but also may be
effective in remote configurations, particularly
when channel programs are executed from system
memory. Bus load limit has noeffect on chained
channel programs, DMA transfers, DMA termination, or channel attention sequences.
TEST_FLAG: TSL [GAJ, OFFH, TEST_FLAG
When the semaphore is found to be zero, it is set
to FFH and the program continues with the next
instruction.
Bus Lock
Like the 8086 and 8088, the 8089 has a LOCK
(bus lock) signal which can be activated by software. The LOCK output is normally connected to
the LOCK input of an 8289 Bus Arbiter. When
LOCK is active, the bus arbiter will not release the
bus to another processor regardless of its priority.
A channel automatically locks the bus during execution of the TSL (test and set while locked)
instruction and may lock the bus for the duration
of a DMA transfer.
3.6 Processor Control and
Monitoring
If bit 9 of register CC is set, the 8089 activates its
This section focuses on lOP/CPU interaction,
i.e., how the CPU initializes the lOP and subsequently sends commands to channels, and how
the channels may interrupt the CPU. It also
covers the channels' DMA control signals and the
status signals that external devices can use to
monitor lOP activities.
LOCK output during a DMA transfer on that
channel. If the transfer is synchronized, LOCK is
active from the time that the first DRQ is
recognized. If the transfer is unsynchronized,
LOCK is active throughout the entire transfer
(there are no idle periods in an unsynchronized
transfer). LOCK goes inactive when the channel
begins the DMA termination sequence.
Initialization
A locked transfer ensures that the transfer will be
completed in the shortest possible time and that
the transferring channel has exclusive use of the
bus. Once the channel obtains the bus and starts a
locked transfer, the channel, in effect, becomes
the highest-priority processor on that bus.
Before the 8089 channels can be dispatched to
perform I/O tasks, the lOP must be initialized.
The initialization sequence (figure 3-29) provides
the lOP with a definition of the system environment: physical bus widths, request/grant mode,
and the location of the channel control block.
The 8089 TSL (test and set while locked)
instruction can be used to implement a
semaphore. (See section 2.5 for a discussion of
how a semaphore may be used to control the
The sequence begins when the lOP's RESET line
is activated. This halts any operation in progress,
but does not affect any registers. Upon the first
3-37
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSOR
CPU
lOP
RESET_
l
l
HALT
PREPARE
INITIALIZATION
CONTROL
BLOCKS
J
CH1 BUSY-FFH
1
CH2 BUSY-OH
J
WAIT FOR
CHANNEL
ATTENTION
CA+SEL
ISSUE
CHANNEL
ATTENTION
I
0/
READ
INITIALIZATION
CONTROL
BLOCKS
CH1 BUSY
~
OH
lOP IS READY;
CPU MAY INITIALIZE
ANOTHER lOP
CH1 BUSY-OH
WAIT FOR
CHANNEL
ATTENTION
Figure 3-29. Initialization Sequence
RESET after power-up, the content of all lOP
registers is undefined. Register contents are
preserved if the lOP is subsequently RESET,
except that RESET always clears the chain bit in
register CC.
the SCP and the SCB may be in RAM or ROM. It
is the CPU's responsibility to properly setup the
control blocks.
The CPU starts the initialization sequence by issuing a channel attention to channell (SEL low) or
to channel 2 (SEL high). The CPU typically
accesses the channels as two consecutive addresses
in its I/O or memory space. An OUT instruction
(for an I/O-mapped lOP) or a memory reference
instruction (such as MOV) then issues the channel
attention.
The lOP initializes itself by reading information
from initialization control blocks located in the
system space (see figure 3-30). The three blocks
are the SCP (system configuration pointer), SCB
(system configuration block) and the CB (channel
control block). The CB is normally RAM-based;
Mnemonics © Inlel, 1979
3-38
8089 INPUT /OUTPUT PROCESSOR
HIGH SYSTEM MEMORY
FFFFEH
(RESERVED)
F FFFCH
SYSTEM
CONFIGURATION
POINTER
(FIXED LOCATION)
}-
SCB SEGMENT BASE
SCB OFFSET
(RES"RVED)
I
SYSBUS
F FFFAH
F.F.FF8H
FFFF6H
FF FF4H
8086/8088
RESET LOCATION
FF FF2H
FF FFOH
}-
CB SEGMENT BASE
SYSTEM
CONFIGURATION
BLOCK
(USER-DEFINED LOCATION)
r-
CB OFFSET
(RESERVED)
I
SOC
I-
e
(RESERVED)
C
CHANNEL
CONTROL
BLOCK
(USER-DEFINED LOCATION)
H
A
N
N
E
L
2
C
H
A
N
PB SEGMENT BASE
PB OFFSET
CCW
(RESERVED)
PB SEG MENT BASE
N
E
L
1
I
BUSY
}---
PB OFFSET
BUSY
I
}--
CCW
LOW SYSTEM MEMORY
Figure 3-30. Initialization Control Blocks
If channel 1 is selected (SEL=low), the lOP considers itself a master (as discussed in section 3.5).
If channel 2 is selected (SEL=high), the lOP
operates as a slave. The lOP ignores, and does
not latch, any subsequent channel attentions that
occur during initialization.
If the lOP is a master, it assumes that it has the
bus immediately. If it is a slave, it pulses RQ/GT
to request the bus from the CPU (local configuration) or the other lOP (remote configuration).
When the lOP has obtained the bus, it assumes
that the system bus is eight bits wide and reads the
3-39
8089 INPUT /OUTPUT PROCESSOR
programs and is only loaded during initialization.
The CB, therefore, cannot be moved during execution except by reinitializing the lOP.
SYSBUS field (figure 3-31) from location
FFFF6H in system memory. This byte rells the
lOP the actual physical width of the system bus;
all subsequent accesses take advantage of a 16-bit
bus if it is available; i.e., even-addressed words
are fetched in single bus cycles. It is therefore
advantageous to word-align the control blocks.
After loading the address of the CB, the lOP
clears the channell BUSY flag to OH. The other
fields in the CB are used when a channel is dispatched and are not read or altered in the
initialization sequence.
After the CPU has started the initialization
sequence, it should monitor channell's BUSY
flag in the CB to determine when the sequence has
been completed. When the BUSY flag has been
cleared, the CPU can dispatch either channel. It
also can begin the initialization of another lOP.
Since each lOP normally has a separate CB, the
CPU must allocate the CB and update the pointer
in the SCB before initializing the next lOP. Alternatively, multiple SCBs could be employed, each
pointing to a different CB area. In this case the
CPU would update the pointer in the SCP before
initializing the next lOP. It follows from this that
in multi-lOP systems, either the SCB or SCP, or
both, must be RAM-based. When all lOPs have
been initialized, the CPU may use RAM occupied
by the SCB for another purpose.
o
7
o
o
W =0
W =1
o
o
o
o
w
=a-BIT SYSTEM BUS
=16-BIT SYSTEM BUS
Figure 3-31. SYSBUS Encoding
Next, the lOP reads the SCB address located at
FFFF8H. This is a standard doubleword pointer,
and the lOP constructs a 20-bit physical address
from it by shifting the segment base left four bits
and adding the offset word of the pointer.
Having obtained the SCB address, the lOP reads
the SOC (system operation command). This byte
(see figure 3-32) tells the lOP the request/grant
mode and the width of the I/O bus.
Channel Commands
After initialization, any channel attention is
interpreted as a command to channel 1
(SEL=low) or to channel 2 (SEL=high). As
discussed in section 3.2, the channel attention,
depending on the activities of both channels, may
not be recognized immediately. The channel
attention is latched, however, so that it will be
serviced as soon as priorities allow.
o
7
o
o
o
o
o
R
When the channel recognizes the CA, it sets its
BUSY flag in the CB to FFH. This does not prevent the CPU from issuing another CA, but provides status information only. In its response to a
CA, the channel reads various control fields from
system memory. It is the responsibility of the
CPU to ensure that the appropriate fields are
properly initialized before issuing the CA.
R = REQUESTIGRANT MODE
I =0 =a-BIT 1/0 BUS
I = 1 = 16-BIT 1/0 BUS
Figure 3-32. SOC Encoding
After setting its BUSY flag, the channel reads its
CCW from the CB. It examines the command
field (see figure 3-33) and executes the command
encoded there by the CPU.
Then the lOP reads the doubleword pointer to the
channel control block, converts the pointer into a
20-bit physical address, and stores it in an internal
register. This register is not accessible to channel
3-40
80891NPUT/OUTPUT PROCESSOR
o
7
CF
CF
000
001
010
011
100
101
110
111
COMMAND FIELD
UPDATE PSW
START CHANNEL PROGRAM LOCATED IN I/O SPACE.
(RESERVED)
START CHANNEL PROGRAM LOCATED IN SYSTEM SPACE.
(RESERVED)
RESUME SUSPENDED CHANNEL OPERATION
SUSPEND CHANNEL OPERATION
HALT CHANNEL OPERATION
ICF
00
01
10
11
INTERRUPT CONTROL FIELD
IGNORE, NO EFFECT ON INTERRUPTS.
REMOVE INTERRUPT REQUEST; INTERRUPT IS ACKNOWLEDGED.
ENABLE INTERRUPTS.
DISABLE INTERRUPTS.
B
o
1
BUS LOAD LIMIT
NO BUS LOAD LIMIT
BUS LOAD LIMIT
P
PRIORITY BIT
Figure 3-33. Channel Command Word Encoding
The CPU may suspend a channel operation
(either program execution or DMA transfer) by
setting CF to 110. The channel saves its state (TP,
its tag bit, and PSW) in the first two words of the
parameter block (see figure 3-18 for format) and
clears its BUSY flag to OH. Note the following in
regard to a suspended <>peration:
Figure 3-34 illustrates the channel's response to
each type of command. Note that if CF contains a
reserved value (010 or 100), the channel's
response is unpredictable.
The CPU can use the "update PSW" command
to alter the bus load limit and priority bits in the
PSW (see figure 3-17) without otherwise affecting
the channel. This command also allows the CPU
to control interrupts originating in the channel;
this topic is discussed in more detail later in this
section.
The two "start program" commands differ only
in their affect on the TP tag bit. If CF=OOI, the
channel sets the tag to 1 to indicate that the program resides in the I/O space. If CF=Oll, the tag
is cleared to 0, and the program is assumed to be
in the system space. The channel converts the
doubleword parameter block pointer to a 20-bit
physical address and loads this into PP. It loads
the doubleword task block (channel program)
pointer into TP, updates the PSW as specified by
the ICF, Band P fields of the CCW and starts the
program with the instruction pointed to by TP.
3-41
•
The content of the doubleword pointer to the
beginning of the channel program is replaced
by the channel state save data. Therefore, a
suspended operation may be resumed, but
cannot be started from the beginning without
recreating the doubleword pointer.
•
TP is the only register saved by this
operation. If another channel program is
started on this channel, the other registers,
including PP, are subject to being overwritten. In general, suspend is used to temporarily halt a channel, not to "interrupt" it
with another program. Section 3.10 provides
an example of a program that can be used to
save another program's registers.
8089 INPUT IOUTPUT PROCESSOR
COMMAND
CHANNEL
CONTROL
BLOCK
CHANNEL
PI'
I
(RESERVED)
PARAMETER
I- BLOCK POINTER
Tp
UPDATEPSW
(CF = 000)
BUSY
CCW
6.
4
2
6
PARAMETER
BLOCK
POINTER
4
2
0
PI'
T
SUSPEND OPERATION
(CR=110)
A
G
1
(RESERVED)
6
PARAMETER
·BLOCK
POINTER
4
2
(RESERVED)
6
PARAMETER
BLOCK
POINTER
4
2
BUSY
CCW
0
(RESERVED)
6
PARAMETER
BLOCK POINTER
4
PP
T·
RESUME OPERATION
(CF=101)
A
G
pp.
'I
I-
HALT OPERATION
(CF=111)
Tp
BUSY
I CCW
Figure 3-34. Channel Commands
3-42
TB POINTER
OR
CHANNEL STATE
2
'I"
{
~
TASK
BLOCK POINTER
{ r- CHANNEL
STATE
_
1"
'-- CHANNEL _
STATE
J
2
0
1
1r
{
0
~
1
2
0
1
2
0
!
2
TB POINTER
OR
.CHANNELSTATE 0
j--.:..
0
2
~
o
(RESE,:!VED)
PI'
START PROGRAM
(CF=001/011)
I
PARAMETER
BLOCK
8089 INPUT /OUTPUT PROCESSOR
•
Suspending a DMA transfer does not affect
any 110 devices (an 110 device will act as
though the transfer is proceeding). The CPU
must provide for conditions that may arise if,
for example, a device requests a DMA
transfer, but the channel does not
acknowledge the request because it has been
suspended. Similarly, an 110 device may be
in a different condition when the operation is
resumed.
of DRQ following the last transfer cycle. If EXT
is activated during a transfer cycle, a fetched byte
may not be stored as explained in section 3.4.
A channel does not recognize EXT if it is not performing a DMA transfer. If EXTI and EXT2 are
activated simultaneously, EXT! is recognized
first.
A suspended operation may be resumed by setting
CF to 101. This command causes the channel to
reload TP, its tag bit, and the PSW from the first
two words of PB. Resuming an operation that has
not been suspended will give unpredictable results
since the first two words of PB will not contain
the required channel state data. A resume command does not affect any channel registers other
than TP.
Interrupts
Each channel has a separate system interrupt line
(SINTRI and SINTR2). A channel program may
generate a CPU interrupt request by executing a
SINTR instruction. Whether this instruction
actually activates the SINTR line, however,
depends upon the state of the interrupt control bit
(bit 3 of the PSW; see figure 3-17). If this bit is
set, interrupts from the channel are enabled, and
execution of the SINTR instruction activates
SINTR. If the interrupt control bit is cleared, the
SINTR instruction has no effect; intcrrupts from
the channel are disabled.
The CPU may abort a channel operation by
issuing a "halt" command (CF=111). The channel clears its BUSY flag to OH and then idles.
Again, the CPU must be prepared for the effect
aborting a DMA transfer may have on an 110
device.
The CPU can alter a channel's interrupt control
bit by sending any command to the channel with
the value of ICF (interrupt control field) in the
CCW set to 10 (enable) or 11 (disable). Thus, the
CPU can prevent interrupts from either channel.
ORO (OMA Request)
The synchronizing device in a DMA transfer uses
the DRQ line to indicate when it is ready to send
or receive the next byte or word. The channel
recognizes a signal on this line only during a
DMA transfers, i.e., after the instruction following XFER has been executed and before a termination condition has occurred. The channels
have separate DMA request lines (DRQl and
DRQ2).
Once activated, SINTR remains active until the
CPU sends a channel command with lCF set to 01
(interrupt acknowledge). When the channel
receives this command, it clears the interrupt service bit in the PSW (figure 3-17) and removes the
interrupt request. Disabling interrupts also clears
the interrupt service bit and lowers SINTR.
EXT (External Terminate)
Status Lines
An external device (typically the synchronizing
device) can terminate a DMA transfer by signaling on this line. Each channel has its own external
terminate line (EXT! and EXT2). The channel
stops the transfer as soon as the current fetch or
store cycle is completed. An external terminate in
an unsynchronized transfer could result in a loss
of data, although this would not be a typical use
of EXT. In a synchronized transfer, the synchronizing device will normally issue EXT instead
The lOP emits signals on the 8o-S2 status lines to
indicate to external devices the type of bus cycle
the processor is starting. Table 3-12 shows the
signals that are output for each type of cycle.
These status lines are connected to an 8288 Bus
Controller. The bus controller decodes these lines
and outputs the signals that control components
attached to the bus. The lOP indicates "instruction fetch" on these lines when it is reading and
writing memory operands as well as when it is fet-
3-43
Mnemonics © Intel, 1979
8089 INPUT/OUTPUT PROCESSOR
ched instructions. In the remote configuration, an
8289 Bus Arbiter monitors the so-Si status lines
to determine when a system bus access is required.
The ',description of each instruction in these,
categories explains how the instruction operates
and how it may:. be used in channel programs.
Instructions that perform essentially the same
operation (e.g., ADD and ADDB, which add
words and bytes respectively), are ,described
together; A reference table at the end:of the section lists every instruction alphabetically and provides execution time"encoded length, and sample
ASM-89 coding for each permissable operand
combination. For information on how the 8089
machine instructions, are encoded in memory, see
section 4.3 . , ' , '
,
Table 3-12. Status Signals SO-S2
82 81 50
Type of Bus Cycle
0
0
0
Instruction fetch from 110 space
0
0
1
Data fetch from 110 space
0
1
0
Data store to 110 space
0
1
1
(not used)
1
0
0
Instruction fetch from system
space
1
0
'1
Data fetch from system space
1
1
0
Data store to system space,
1
1
1
Passive; no bus cycle run
In reading this secti~n, .it is important .to recall
that the instruction set does not differentiate
betweenmeI)1ory ,addresses and I/O device
addresses. Instructions that are described as
accepting, byte and word memory operands may
also be used to read and write I/O devices.
Status lines S3-S6 indicate whether the bus cycle is
DMA or non-DMA, and which channel is running the cycle (see table 3-i3)~ Note that when the
lOP is not running a bus cycle (e.g., when it is idle
or when it is executing an internal cycle that does
not use the bus),the status lines reflect the last
bus cycle run.
Data Transfei'lnstructions
These instructions move data between memory
and channel registers. Traditional byte and word
moves (including memory-to-memory) are
available, as are special, instructions that' load
addresses into pointer registers and update tag
bits in the process.
Table 3-13. Status Signals S3-S6
86 55 84 83
1
1
1
1
1
Bus Cycle
0
0
DMA cycle on channel 1
1
0
1
DMA cycle on channel 2
1
1
0
Non-DMA cycle on channel 1
1
1
1
Non-DMA cycle on channel 2
MOV , destination, source
MOV transfers abyt~orwordJrom the source,to
the destination. Four instruction,S ,are provided:
MOV
MOVB
MOVI
MOVBI
3.7 Instruction Set
This section divides the lOP's 53 instructions into
five functional categories:
1. data transfer,
2. arithmetic,
3. logic and bit manipulation,
4. program transfer,
5. processor control.
Mnemonics © Intel, 1979
Move Word Variable,
Move Byte Variable,
Move Word Immediate,
Move Byte Immediate.
Figure 3-35 shows how these, instructions affect
register, operands. Notice that when a pointer
registeris specified as the destination of a MOV,
its tag 'bit is unconditionally set to 1. MOV
instructions 'are therefore ,used to load I/O space
addresses into pointer registers.,
3-44
8089 INPUT /OUTPUT PROCESSOR
Register is Destination
Tag 19
Byte
Operation
r l r. - -
15
7
Register is Source
0
Tag 19
---r-----,...--------,
L1JLS~~SISSSSSSSSIRRRRRRRR
Word
rlr-Operation L- 1J LS~ ~ SiR R R R R R R R I R R R R R R R R
I
15
7
o
~x.J0~~xlx X X X X X X XIT T T T T T TTl
I [xJG~~XITTTTTTTTITTTTTTTT I
T = bit is transferred to destination operand
R = bit is replaced by source operand
S = bit is sign extension of high-order bit transferred
X = bit is ignored
1 = bit is unconditionally set
Figure 3-35. Register Operands in MOV Instructions
MOVP
destination, source
An 8086 or 8088 can pass any address in its
megabyte memory space to a channel program in
the form of a doubleword pointer. The channel
program can access the location by using LPD to
load the location address into a pointer register.
MOVP (move pointer) transfers a physical
address variable between a pointer register and
memory. If the source is a pointer register, its
content and tag bit are converted to a physical
address pointer (see figure 3-23). If the source is a
memory location, the three bytes are converted to
a20-bitphysicaladdress and a tag value, and are
loaded into the pointer register and its tag bit.
MOVP is typically used to save and restore
pointer registers.
LPD
Arithmetic Instructions
The arithmetic instructions interpret all operands
as unsigned binary numbers of 8, 16 or 20 bits.
Signed values may be represented in standard
two's complement notation with the high-order
bit representing the sign (O=positive, 1=negative).
The processor, however, has no way of detecting
an overflow into a sign bit so this possibility must
be provided for in the user's software.
destination, source
LPD (load pointer with doubleword) converts a
doubleword pointer (see figure 3-22) to a 20-bit
physical address and loads it into the destination,
which must be a pointer register. The pointer
register's tag bit is unconditionally cleared to 0,
indicating a system address. Two instructions are
provided:
LPD
LPDI
The 8089 performs arithmetic operations to 20
significant bits as follows. Byte and word
operands are sign-extended to 20 bits (e.g., bit 7
of a byte operand is propagated through bits 8-19
of an internal register). Sign extension does not
affect the magnitude of the operand. The operation is then performed, and the 20-bit result is
Load Pointer With Doubleword
Variable
Load Pointer With Doubleword
Immediate
3-45
Mnemonics © Intel, 1979
8089 INPUT IOUTPUT PROCESSOR
returned to the destination operand. High-order
bits are truncated as necessary to fit the result in
the available space. A carry out of, or borrow
into, the high-order bit of the result is not
detected. However, if the destination is a register
that is larger than the source operand, carries will
be reflected in the upper register bits, up to the
size of the register.
INC
The destination is incremented by 1. Two instructions are available:
'
INC
INCB
Figure 3-36 shows how the arithmetic instructions
treat registers when they are specified as source
and destination operands.
ADD
DEC
Increment Word
Increment Byte
destination
The destination is decremented by 1. Word and
byte instructions are provided:
DEC
DECB
destination, source
The sum of the two operands replaces the destination operand. Four addition instructions are
provided:
ADD
ADDB
ADD!
ADDBI
destination
Decrement Word
Decrement Byte
Logical and Bit Manipulation
Instructions
Add Word Variable
Add Byte Variable
Add Word Immediate
Add Byte Immediate
The logical instructions include the boolean
operators AND, OR and NOT. Two bit manipulation instructions are provided for setting or
Register is Source
Register is Destination
Tag 19
15
7
Tag 19
0
Byte
1"':;' r - Operation I.x.J~~~RIRRRRRRRRIRRRRRRRR
I
Word
r;,r-Operation LXJ~~~RIRRRRRRRRIRRRRRRRR
I
15
Figure 3-36. Register Operands in Arithmetic Instructions
3-46
o
~xJ~~~xlxxxxxxxxlpppppppp
x = bit is ignored in operation
R = bit is replaced by operation result
p = bit participates in operation
'Mnemonics © Intel, 1979
7
I
80891NPUT/OUTPUT PROCESSOR
clearing a single bit in memory or in an 110 device
register. As shown in figure 3-37, the logical
operations always leave the upper four bits of
20-bit destination registers undefined. These bits
should not be assumed to contain reliable values
or the same values from one operation to the
next. Notice also that when a register is specified
as the destination of a byte operation, bits 8-15
are overwritten by bit 7 of the result. Bits 8-15 can
be preserved in AND and OR instructions by
using word operations in which the upper byte of
the source operand is FFH or OOH, respectively.
AND is useful when more than one bit of a device
register must be cleared while leaving the remaining bits intact. For example, ANDing an 8-bit
register with EEH only clears bits o and 4.
The two operands are logically ORed, and the
result replaces the destination operand. A bit in
the result is set if either or both of the corresponding bits of the operands are set; if both operand
bits are cleared, the result bit is cleared. Four
types of OR instructions are provided:
AND destination, source
The two operands are logically ANDed and the
result replaces the destination operand. A bit in
the result is set if the bits in the corresponding
positions of the operands are both set, otherwise
the result bit. is cleared. The following AND
instructions are available:
AND
ANDB
AND!
ANDBI
destination, source
OR
OR
ORB
ORI
ORBI
Logical AND Word Variable
Logical AND Byte Variable
Logical AND Word Immediate
Logical AND Byte Immediate
OR can be used to selectively set multiple bits in a
device register. For example, ORing an 8-bit
register with 30H sets bits 4 and 5, but docs not
affect the other bits.
Register is Destination
Tag 19
15
Logical OR Word Variable
Logical OR Byte Variable
Logical OR Word Immediate
Logical OR Byte Immediate
Register is Source
7
0
Byte
r ::l r. - - Operation L ~ LU~~ uis S S S S S S siR R R R R R R R
Tag 19
I
15
7
o
[xJ0~~ xlxxxxxxxxip p p p p p p p I
[~~~~ xlp p p p p p P plpp P P P P P P I
x=
U
R
S
P
bit is ignored in operation
= bit is undefined following operation
bit participates in operation and is replaced by result
bit is sign-extension of high-order result bit
= .bit participates in operation, but is unchanged
=
=
Figure 3-37. Register Operands in Logical' Instructions
3-47
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSOR
NOT destination/destination, source
any location within -32,768 through +32,767
bytes. An instruction containing an 8-bit displacement is called a short transfer and an instruction
containing a 16-bit displacement is called a long
transfer.
NOT inverts the bits of an operand. If a single
operand is coded, the inverted result replaces the
original value. If two operands are coded, the
inverted bits of the source replace the destination
value (which must be a register), but the source
retains its original value. In addition to these two
operand forms, separate mnemonics are provided
for word and byte values:
NOT
NOTB
The program transfer instructions have alternate
mnemonics. If the mnemonic begins with.the letter "L," the transfer is long, and the distance to
the transfer target is expressed as a 16-bit
displacement regardless of how far away the
target is located. If the mnemonic does not begin
with "L," the ASM-89 assembler may build a
short or long displacement according to rules
discussed in section 3.9.
Logical NOT Word
Logical NOT Byte
NOT followed by INC will negate (create the
two's complement of) a positive number.
The "self-relative" addressing technique used by
program transfer instructions has two important
consequences. First, it promotes positionindependent code, i.e., code that can be moved in
memory and still execute correctly. The only
restriction here is that the entire program must be
moved as a unit so that the distance between the
transfer instruction and its target does not
change. Second, the limited addressing range of
these instructions must be kept in mind when
designing large (over 32k bytes of code) channel
programs.
SETB destination, bit-select
The bit-select operand specifies one bit in the
destination, which must be a memory byte, that is
unconditionally set to 1. A bit-select value of 0
specifies the low-order bit of the destination while
the high-order bit is set if bit-select is 7. SETB is
handy for. setting a single bit in an 8-bit device
register.
CLR destination, bit-select
CLR operates exactly like SETB except that the
selected bit is unconditionally cleared to O.
CALL/LCALL
CALL invokes an out-of-line routine, saving the
value of TP so that the subroutine can transfer
back to the instruction following the CALL. The
instruction stores TP and its tag bit in the TPsave
operand, which must be a physical address
variable, and then transfers to the target address
formed by adding the target operand's displacement to TP. The subroutine can return to the
instruction following the CALL by using a
MOVP instruction to load TPsave back into TP.
Program Transfer Instructions
Register TP controls the sequencejn which channel program instructions are executed. As each
instruction is executed, the length of the instruction is added to TP so that it. points to the next
sequential instruction. The program transfer
instructions can alter this sequential execution by
adding a signed displacement value to TP. The
displacement is contained in the program transfer
instruction and may be either 8 or 16 bits long.
The displacement is encoded in two's complement
notation, and the high-order bit indicates the sign
(O=positive displacement, 1=negative displacement). An 8-bit displacement may cause a
transfer to a location in the range -128 through
+ 127 bytes from the end of the transfer instruction, while a 16-bit displacement can transfer to
Mnemonics © Intel, 1979
TPsave, target
Notice that the 8089's facilities for implementing
subroutines, or procedures, is less sophisticated
than its couriterparts in the 8086/8088. The principal difference is that the 8089 does not have a
built in stack mechanism. 8089 programs can
implement a stack using a base register as a stack
pointer. On the other hand, since channel programs are not subject to interrupts, a stack will
not be required for most channel programs.
3-48
8089 INPUT IOUTPUT PROCESSOR
target
JMP/LJMP
JMCNE/LJMCNE
source, target
JMP causes an unconditional transfer (jump) to
the target location. Since the task pointer is not
saved, no return to the instruction following the
JMP is implied.
This instruction causes a jump to the target location if the source is not equal to the mask/
compare value in MC. It otherwise operates identically to JMCE.
JZ/LJZ source, target
JBT ILJBT source, bit-select, target
JZ (jump if zero) effects a transfer to the target
location if the source operand is zero; otherwise
the instruction following JZ is executed. Word
and byte values may be tested by alternate
instructions:
JBT (jump if bit true) tests a single bit in the
source operand and jumps to the target if the bit
is a 1. The source must be a byte in memory or in
an 110 device register. The bit-select value may
range from 0 through 7, with 0 specifying the loworder bit. This instruction may be used to test a
bit in an 8-bit device register. If the target is the
JBT instruction itself, the operation effectively
becomes "wait until bit is 0."
JZ/LJZ
JZB/LJZB
Jump/Long Jump if Word Zero
Jump/Long Jump if Byte Zero
If the source operand is a register, only the loworder 16 bits are tested; any additional high-order
bits in the register are ignored. To test the loworder byte of a register, clear bits 8-15 and then
use the word form of the instruction.
JNZlLJNZ
J NBT ILJ NBT
source, bit-select, target
This instruction operates exactly like JBT, except
that the transfer is made if the bit is not true, i.e.,
if the bit is O.
source, target
Processor Control Instructions
JNZ operates exactly like JZ except that control is
transferred to the target if the source operand
does not contain all O-bits. Word and byte sources
may be tested using these mnemonics:
JNZ/LJNZ
JNZB/LJNZB
These instructions enable channel programs to
control lOP hardware facilities such as the LOCK
and SINTRI-2 pins, logical bus width selection,
and the initiation of a DMA transfer.
Jump/Long Jump if Word Not
Zero
Jump/Long Jump if Byte Not
Zero.
TSL
destination, set-value, target
Figure 3-38 illustrates the operation of the TSL
(test and set while locked) instruction. TSL can be
used to implement a semaphore variable that
controls access to a shared resource in .a
multiprocessor system (see section 2.5). If the
target operand specifies the address of the TSL
instruction, the instruction is repetively executed
until the semaphore (destination) is found to contain zero. Thus the channel program does not
proceed until the resource is free.
JMCE/LJMCE . source, target
This instruction (jump if masked compare equal)
effects a transfer to the target location if the
source (a memory byte) is equal to the lower byte
in register MC as masked by the upper byte in
MC. Figure 3-15 illustrates how O-bits in the
upper half of MC cause the corresponding bits in
the lower half of MC and the source operand to
compare equal, regardless of their actual values.
For example, if bits 8-15 of MC contain the value
01H, then the transfer will occur if bit 0 of the
source and register MC are equal. This instruction
is useful for testing multiple bits in 8-bit device
registers.
WID
source-width, dest-width
WID (set logical bus widths) alters bits 0 and 1 of
the PSW, thus specifying logical bus widths for a
DMA transfer. The operands maybe specified as
3-49
Mnemonics © Intel, 1979
8089 INPUT/OUTPUT PROCESSOR
ACTIVATE
mcK
FETCH
DESTINA TION
*OH
DE·ACTIVATE
LOCK
ASSIGN·
SET·VALUETO
DESTINA TION
STORE
DESTINA TION
DE·ACTIVATE
~
NEXT SEQUENTIAL INSTRUCTION
Figure 3-38. Operation of TSL Instruction
8 or 16 (bits), with the,restriction that the logical
width of a bus cannot exceed its physical width.
The logical bus widths are undefined following a
processor RESET; therefore the WID instruction
must be executed before the first transfer.
Thereafter the logical widths retain their values
until the next WID instruction or processor
RESET.
the instruction following XFER may ready· the
synchronizing device (e.g., send a "start" command or the last of a series of parameters). Any
instruction, including NOP and WID, may follow
XFER, except an instruction that alters GA, GB
orGC.·
XFER (no operands)
SINTR
XFER (enter DMA transfer mode after following
instruction) prepares the channel for a DMA
transfer operation. In a synchronized transfer,
This instruction sets the interrupt service bitin the
PSW and activates the channel's SINTR line if
the interrupt control bit in the PSW is set. If the
Mnemonics © Intel, 1979
3-50
(no operands)
8089 INPUT /OUTPUT PROCESSOR
with the instruction name. For every combination
of operand types (see table 3-15 for key), the
instruction's execution time and its length in
bytes, and a coding example are provided.
interrupt control bit is cleared (interrupts from
this channel are disabled), the interrupt service bit
is set, but SINTRI-2 is not activated. A channel
program may use this instruction to interrupt a
CPU.
NOP
The instruction timing figures are the number of
clock periods required to execute the instruction
with the given combination of operands. At
5 MHz, one clock period is 200 ns; at 8 MHz a
clock period is 125 ns. Two timings are provided
when an instruction operates on a memory word.
The first (lower) figure indicates execution time
when the word is aligned on an even address and
is accessed over a 16-bit bus. The second figure is
for odd-addressed words on 16-bit buses and any
word accessed via an 8-bit bus.
(nooperands)
This instruction consumes clock cycles but performs no operation. As such, it is useful in timing
loops.
HLT (no operands)
This instruction concludes a channel program.
The channel clears its BUSY flag and then idles.
Instruction fetch time is shown in table 3-17 and
should be added to the execution times shown in
table 3-16 to determine how long a sequence of
instructions will take to run. (Section 3.2 explains
the effect of the instruction queue on 16-bit
instruction fetches.) External delays such as bus
arbitration, wait states and activity on the other
channel will increase the elapsed time over the
figures shown in tables 3-16 and 3-17. These
delays are application dependent.
Instruction Set Reference Information
Table 3-16 lists every 8089 instruction
alphabetically by its ASM-89 mnemonic. The
ASM-89 coding format is shown (see table 3-14
for an explanation of operand identifiers) along
Table 3-14. Key to ASM-89 Operand Identifiers
IDENTIFIER
USEDIN
EXPLANATION
destination
data transfer,
arithmetic,
bit manipulation
A register or memory location that may contain data operated on
by the instruction, and which receives (is replaced by) the result
of the operation.
source
data transfer,
arithmetic,
bit manipulation
A register, memory location, or immediate value that is used in
the operation, but is not altered'by the instruction.
target
program transfer
Location to which control is to be transferred.
TPsave
program transfer
A 24-bit memory location where the address'of the next sequential instruction is to be saved.
bit-select
bit manipulation
Specification of a. bit location within a byte; Q=least-significant
(rightmost) bit, 7=most-significant (leftmost) bit.
set-value
TSL
Value to which destination is set if it is found O.
source-width
WID
Logical width of source bus.
dest-width
WID
Logical width of destination bus.
3-51
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSOR
Table 3-15. Key to Operand Types
IDENTIFIER
(no operands)
EXPLANATION
.
No operands are written
register
Any general register
ptr-reg
A pointer register
immed8
A constant in the range O-FFH
immed16
A constant in the range O-FFFFH
mem8
An 8-bitmemory location (byte)
mem16
A 16-bit memory location (word)
mem24
A 24-bit memory location (physical address pointer)
mem32
A 32-bit memory location (doubleword pOinter)
label
A label within -32,768 to +32,767 bytes of the end of the instruction
short-label
A label within -128 to +127 bytes of the end of the instruction
0-7
A constant in the range: 0-7
8/16
The constant 8 or the constant 16
Table 3-16. Instruction Set Reference Data
ADD
Add Word Variable
destination, source
Operands
register, mem16
mem16, register
Clocks
Bytes
11/15
16/26
2-3
2-3
Coding Example
ADD BC, [GAj.LENGTH
ADD [GBj,GC
"
ADDB
Operands
register, ll)em8
mem8, register
ADDBI
Clocks
Bytes
11
16
2-3
2-3
register, immed8
mem8, immed8
Clocks
Bytes
'3
16
3
3-4
register, immed16
mem16, immed16
Mnemonics © Intel, 1979
ADDB GC, [GAj.N_CHARS
ADDB [PPj.ERRORS, MC
Coding Example
ADDBI MC,10
ADDBI [PP+IX+j.RECORDS,2CH
AddWord Immediate
destination, source
Operands
Coding Example
Add Byte Immediate
destination, source
Operands
ADDI
Add Byte Variable
destination, source
Clocks
Bytes
3
16/26
4
4-5
3-52
Coding Example
ADDI GB,OC25BH
ADDI [GBj.POINTER,5899
8089 INPUT /OUTPUT PROCESSOR
Table 3-16. Instruction Set Reference Data (Cont'd.)
AND
Operands
register, mem16
mem16, register
ANDB
Clocks
Bytes
11115
16126
2-3
2-3
register, memB
memB, register
ANDBI
register, immedB
memB, immedB
ANDI
Clocks
Bytes
11
16
2-3
2-3
Clocks
Bytes
3
16
3
3-4
. destination, source
Operands
register, immed16
mem16, immed16
CALL
mem24, label
Clocks
Bytes
3
16126
4
4-5
memB,0-7
AND BC, [GC)
AND [GA+IX).RESULT, GA
..
Coding Example
GA ,01100000 B
[GC+IX], 2CH
Coding Example
IX,OH
[GB+IX).TAB,40H
Call
Clocks
Bytes
17123
3-5
Coding Example
CALL [GC+IX).SAVE, GET_NEXT
Clear Bit To Zero
destination, bit select
Operands
Coding Example
Logical AND Word Immediate
TPsave, target
Operands
AND MC, [GA).FLAG_WORD
AND [GC).STATUS, BC
Logical AND Byte Immediate
destination, source
Operands
Coding Example
Logical AND Byte Variable
destination, source
Operands
CLR
Logical AND Word Variable
destination, source
Clocks
Bytes
. 16
2-3
Coding Example
CLR [GA], 3
-
DEC
Operands
register
mem16
Decrement Word By 1
destination
Clocks
Bytes
3
16126
"2
2-3
3-53
Coding Example
DEC [PP).RETRY
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSOR
Table 3-16. Instruction Set Reference Data (Cant'd.)
DECB
destination
Operands
mem8
HLT
(no operands)
register
mem16
INCB
16
2-3
mem8
Clocks
Bytes
11
2
mem8, 0-7, label
JMCE
Clocks
Bytes
3
16/26
2
2-3
mem8, label
JMCNE
Clocks
Bytes
16
2-3
mem8, label
Clocks
Bytes
14
3-5
label
Mnemonics © Intel, 1979
INC GA
INC [GA].COUNT
Coding Example
INCB [GBl.POINTER
Coding Example
JBT [GA].RESULLREG,3,DATLVALID
Jump if Masked Compare Equal
Clocks
Bytes
14
3-5
Coding Example
JMCE [GB].FLAG, STOP_SEARCH
Jump if Masked Compare Not Equal
Clocks
Bytes
14
3-5
target
Operands
Coding Example
Jump if Bit True (1)
source, target
Operands
HLT
Increment Byte by 1
source, target
Operands
Coding Example
Increment Word by 1
source, bit-select, target
Operands
Coding Example
DECB [GA+IX+].TAB
Halt Channel Program
destination
Operands
JMP
Bytes
destination
Operands
JBT
Clocks
(no operands)
Operands
INC
Decrement Byte By 1
Coding Example
JMCNE [GB+IX], NEXT_ITEM
Jump Unconditionally
Clocks
Bytes
3
3-4
3-54
Coding Example
JMP READ_SECTOR
8089 INPUT /OUTPUT PROCESSOR
Table 3-16. Instruction Set Reference Data (Cont'd.)
JNBT
source, bit-select, target
Operands
memS, 0-7, label
JNZ
Clocks
Bytes
14
3-5
source, target
Operands
register, label
mem16, label
JNZB
memS, label
register, label
mem16, label
JZB
Bytes
Coding Example
5
12/16
3-4
3-5
JNZ BC, WRITE_LINE
JNZ [PP].NUM~CHARS, PUT_BYTE
Jump if Byte Not Zero
Clocks
Bytes
12
3-5
memS, label
LCALL
Clocks
Bytes
5
12/16
3-4
3-5
mem24, label
LJBT
Clocks
Bytes
12
3-5
Clocks
LJMCE
memS, label
Coding Example
JZB [PP].LlNES_LEFT, RETURN
Bytes
Coding Example
4-5
LCALL [GC].RETURN_SAVE,INIT_S279
Clocks
Bytes
14
4-5
Coding Example
.
LJBT [GA].RESULT, 1, DATA_OK
Long jump if Masked Compare Equal
source, target
Operands
JZ BC, NEXT_LINE
JZ [GC+IX].lNDEX, BUF_EMPTY
Long Jump if Bit True (1)
source, bit-select, target
memS, 0-7, label
Coding Example
Long Call .
17/23
Operands
JNZB [GA], MORE_DATA
Jump if Byte Zero
TPsave, target
Operands
Coding Example
Jump if Word is Zero
source, target
Operands
JNBT [GCl. 3, RE_READ
Clocks
source, target
Operands
Coding Example
Jump if Word Not Zero
source, target
Operands
JZ
Jump if Bit Not True (0)
Clocks
Bytes
14
4-5
3-55
Coding Example
LJMCE [GB], BYTE_FOUND
Mnemonics © Intel, 1979
·. 8089 INPUT /OUTPUT PROCESSOR
'table 3~16. Instruction Set Reference Data (Cont'd.)
LJMCNE
source, target
Operands
memB, label
LJMP
Long jump if Masked Compare Not Equal
Clocks
Bytes
14
4-5
target
label
Clocks
Bytes
3
4
memB, 0-7, label
Clocks
Bytes
14
4-5
register, label
mem16, label
LJMP GET_CURSOR
Coding Example
LJNBT [GC], 6, CRCC_ERROR
Long Jump if Word Not Zero
source, target
Operands
Coding Example
Long Jump if Bit Not True (0)
source, bit-select, target
Operands
LJNZ
LJMCNE [GC+IX+], SCAN_NEXT
Long Jump Unconditional
Operands
LJNBT
Coding Example
Clocks
Bytes
5
12/16
4
4-5
Coding Example
LJNZ BC, PARTIALXMIT
LJNZ [GA+IX].N_LEFT, PUT_DATA
.
LJNZB
Operands
memB, label
LJZ
h
Operands
Bytes
Coding Example
12
4-5
LJNZB [GB+lX+].ITEM, BUMP_COUNT
Long Jump if Word Zero
Clocks
memB, label
Operands
4
4-5
Clocks
Bytes
12
4-5
Coding Example
LJZB [GA], RETURN_LINE
Load Pointer With Doubleword Variable
Clocks
Bytes
20/2B*
2-3
*20 clocks if operand is on even address; 2B if on odd address
Mnemonics © Intel, 1979
Coding Example
LJZ IX, FIRST_ELEMENT
LJZ [GB].XMIT_COUNT,NO_DATA
Long Jump if Byte Zero
destination, source
ptr-reg, mem32
Bytes
5
12/16 .
source, target
Operands
LPD
Clocks
source, target
register, label
mem16, label
LJZB
Long Jump if Byte Not Zero
source, target
3-56
Coding Example
LPD GA, [PP].BUF_START
8089 INPUT/OUTPUT PROCESSOR
Table 3-16. Instruction Set Reference Data (Cont'd.)
LPDI
destination, source
Operands
ptr-reg, immed32
Load Pointer With Doubleword Immediate
Clocks
Bytes
12/16'
6
Coding Example
LPDI GB, DISK_ADDRESS
'12 clocks if instruction is on even address; 16 if onodd address
MOV
Operands
register, mem16
mem16, register
mem16, mem16
MOVB
register, mem8
mem8, register
mem8, mem8
MOVBI
Bytes
8/12
10/16
18/28
2-3
2-3
4-6
register, immed8
mem8, immed8
Bytes
8
10
18
2-3
2-3
4-6
Operands
Clocks
Bytes
3
12
3
3-4
ptr-reg, mem24
mem24, ptr-reg
Coding Example
MOVB BC, [PP].TRAN_COUNT
MOVB [PP].RETURN_GODE, GC
MOVB [GB+IX+], [GA+IX+]
Coding Example
MOVBI MG, 'A'
MOVBI [PP].RESULT,O
Move Word Immediate
Clocks
Bytes
3
12/18
4
4-5
Coding Example
MOVI BC,O
MOVI [GB], OFFFFH
Move Pointer
destination, source
Operands
MOV IX, [GC]
MOV [GA].COUNT, BC
MOV [GA].READING, [GB]
Move Byte Immediate
destination, source
register, immed16
mem16, immed16
Coding Example
Move Byte
Clocks
destination, source
Operands
MOVP
Clocks
destination, source
Operands
MOVI
Move Word
destination, source
Clocks
Bytes
19/27'
16/22'
2-3
2-3
Coding Example
MOVP TP, [GG+IX]
MOVP [GB].SAVE_ADDR, GG
'First figure is for operand on even address; second is for odd-addressed operand.
NOP
(no operands) .
Operands
(no operands)
No Operation
Clocks
Bytes
4
2
3-57
Coding Example
NOP
Mnemonics © Intel, 1979
8089 INPUT/OUTPUT PROCESSOR
Table 3-16. Instruction Set Reference Data (Cont'd.)
NOT
destination 1destination, source
Operands
register
mem16
register, mem16
NOTB
mem8
register, mem8
3
16/26
11/15
2
2-3
2-3
Operands
ORB
Clocks
Bytes
16
11
2-3
2-3
register, mem8
mem8, register
ORBI
Clocks
Bytes
11/15
16/26
2-3
2-3
register, immed8
mem8, immed8
Clocks
Bytes
11
16
2-3
2-3
Operands
SETB
Bytes
3
16
3
3-4
mem8,0-7
SINTR
Clocks
Bytes
3
16/26
4
4-5
(no operands)
Mnemonics © Intel, 1979
Coding Example
ORB IX, [PP).POINTER
ORB [GA+IX+l. GB
Coding Example
ORBI IX, 00010001 B
ORBI [GB).COMMAND,OCH
Coding Example
ORI MC, OFFODH
ORI [GAl. 1000H
Set Bit to 1
Clocks
Bytes
16
2-3
(no operands)
Operands
Coding Example
OR MC, [GC).MASK
OR [GCl. BC
Logical OR Word Immediate
destination, bit-select
Operands
NOTB [GA).PARM_REG
NOTB IX, [GB).STATUS
Logical OR Byte Immediate
Clocks
destination, source
register, immed16
mem16,immed16
Coding Example
Logical OR Byte
destination, source
Operands
NOT MC
NOT [GA).PARM
NOT BC, [GA+IX).LlNES_LEFT
Logical OR Word
destination, source
Operands
Coding Example
Logical NOT Byte
destination, source
register, mem16
mem16, register
ORI
Bytes
desti nation 1desti nation, sou rce
Operands
OR
Logical NOT Word
Clocks
Coding Example
SETB [GA).PARM_REG,2
Set Interrupt Service Bit
Clocks
Bytes
4
2
3-58
Coding Example
SINTR
8089 INPUT /OUTPUT PROCESSOR
Table 3-16. Instruction Set Reference Data (Cont'd.)
TSL
destination, set-value, target
Operands
mem8, immed8, short-label
Test and Set While Locked
Clocks
Bytes
14116'
4-5
Coding Example
TSL [GAl.FLAG, OFFH, NOT_READY
'14 clocks if destination f. 0; 16 clocks if destination = 0
WID
source-width, dest-width
Set Logical Bus Widths
Operands
Clocks
Bytes
4
2
8116,8116
XFER
(no operands)
WID 8,8
Enter DMA Transfer Mode After Next Instruction
Operands
Clocks
Bytes
4
2
(no operands)
BUSWIDTH
16
8
Coding Example
XFER
nel processes different types of operands and how
it calculates addresses using its addressing modes.
Section 3.9 describes the ASM c 89 conventions
that programmers use to specify these operands
and addressing modes.
Table 3-17. Instruction Fetch Timings
(Clock Periods)
INSTRUCTION
LENGTH
(BYTES)
Coding Example
(1 )
(2)
7
14
14
18
11
11
15
15
Register and Immediate Operands
2
3
4
5
14
18
22
26
(1)
First byte of instruction is on an even
address.
(2)
First byte of instruction is on an odd address.
Add 3 clocks if first byte is not in queue (e.g.,
first instruction following program transfer).
Registers may be specified as source or destination operands in many instructions. Instructions
that operate on registers are generally both
shorter and faster than instructions that specify
immediate or memory operands.
Immediate operands are data contained in
instructions rather than in registers or in memory.
The data may be either 8 or 16 bits in length. The
limitations of immediate operands are that they
may only serve as source operands and that they
are constant values.
3.8 Addressing Modes
Memory Addressing Modes
8089 instruction operands may reside in registers,
Whereas the channel has direct access to register
and immediate operands, operands in the system
and 110 space must be transferred to or from the
lOP over the bus. To do this, the lOP must
calculate the address of the operand, called its
in the instruction itself or in the system or I/O
address spaces. Operands in the system and I/O
spaces may be either memory locations or 110
device registers and may be addressed in four different ways. This section describes how the chan3-59
Mnemonics © Intel, 1979
8089 IN PUT/OUTPUT PROCESSOR
effective address (EA). The programmer may
specify that an operand's address be calculated in
any of four different ways; these are the 8089's
memory addressing modes.
Based Addressing
In based addressing (figure 3-39), the effective
address is taken directly from the content of GA;
GB, GC or PP. Using this iiddressing mode, one
instruction may access different locations if the
register isupdated before the instruction exec~tes.
LPD, MOV,MOVP or arithmetic instructions
might be used to change the value of the base
register.
The Effective Address
An operand in the system space has a 20-bit effective address, and an operand in the IIO space has
a 16-bit effective address. These addresses are
unsigned numbers that represent the distance (in
bytes) of the low-order byte of the operand from
the beginning of the.address space. Since the 8089
does not "see" the segmented structure of the
system space that it may share with an 8086 or
8088, 8089 effective addresses are equivalent to
8086/8088 physical addresses.
Offset Addressing
In this mode (figure 3-40) an 8-bit unsigned value
contained in the instruction is added to the content of a base register to form the effective
address. The offset mode provides a convenient
way to address elements in structures· (a
parameter block is a typical example of a struc"
ture). As shown in figure 3-41, a base register can
be pointed at the base (first element) in the struc"
ture, and then different offsets can be used to
access the elements within the structure. By
changing the base address, the same structure can
be relocated elsewhere in memory.
All memory addressing modes use the content of
one of the pointer registers, and the state of that
register's tag bit determines whetherthe operand
lies in the system,or theIlO space. If the operand
is in the IIO space (tag = 1), bits 16-19 of the
pointer register are ignored in the effective
address calculation. Section 4.3 describes the t~o
fields (AA and MM) in the encoded machine
instruction that specify addressing mode and base
(pointer) register.
MM
Indexed Addressing
An indexed address is formed by adding the content of register IX (interpreted as an unsigned
quantity) to a base register as shown in figure
3-42. Indexed addressing is often used to access
MACHINE INSTRUCTION FORMAT
GA
OR
GB
OR
GC
OR
pp
Figure 3-39. Based Addressing
3-60
EA
BOB91NPUT /OUTPUT PROCESSOR
MACHINE INSTRUCTION FORMAT
MM
GA
OR
GB
OR
---11---.( +
GC
OR
PP
Figure 3-40. Offset Addressing
,
OFFSET
'r
Y
6
HIGH ADDRESSES
ERROR
+4
l
LlNECT
BUFF_PTR
+2 POSITIONI CURSOR
rI
...................,..-_......
r-~+O
I
I
I
I
I
I
I
I
I
..,
LOW ADDRESSES
..,
I
EA
I __________
L
END_BUS
~
____ I
~
Figure 3-41. Accessing a Structure with Offset Addressing
array elements (see figure 3-43). A base register
locates the beginning of the array and the value in
IX selects one element, i.e., it acts as the array
subscript. The ith element of a byte array is
selected when IX contains (i '-1):To access the
ith element of a word array, IX should contain
Indexed Auto-Increment Addressing
In this variation of indexed addressing, the effective address is formed by summing IX and a base
register, and then IX is incremented automatically. (See figure 3-44.) The addition takes place
((i-l)*2).
3-61
80891NPUT /OUTPUT PROCESSOR
mode is very useful for "stepping through" successive elements of an array (e.g., a program loop
that sums an array).
after the EA is calculated. IX is incremented by 1
for a byte operation, by 2 for a word operation
and by 3 for a M0 VP instruction. This addressing
R/B/P WB AA W
OPCODE
MACHINE INSTRUCTION FORMAT
MM
GA
OR
GB
OR
GC
OR
PP
Figure 3-42. Indexed Addressing
HIGH ADDRESSES
IX
I
~ r-
ARRAY (9)
ARRAY (8)
ARR,AY(7)
I
I
I
I
'l
I
r
ARRAY (6)
ARRAY (5)
EA
I
I
I
I
•
ARRAY (4)
ARRAY (3)
"
r
ARRAY (2)
I
ARRAY (1)
r
IL...
_ _ _ . ...,;.. _ _ _ _ _
----'-
..
ARRAY (0)
!-1WORD_
h
'
LOW ADDRESSES
, , Figure 3-43. Accessing a Word Array with Indexed Addressing
3-62
0009 INPUT/OUTPUT PROCESSOR
R/B/P WB AA W
OPCODE
MM
MACHINE INSTRUCTION FORMAT
GA
OR
GB
J~
OR
GC
OR
PP
EA
IX
•
I
I
I
I
I
I
I
IX
J.0-I
DELTA
Figure 3-44. Indexed Auto-Increment Addressing
3.9 Programming Facilities
ASM-09
The ASM-89 assembler reads a disk file containing 8089 assembly language statements, translates
these statements into 8089 machine instructions,
and writes the result into a second disk file. The
assembly input is called a source module, and the
principal output is a relocatable object module.
The assembler also produces a file that lists the
module and flags any errors detected during the
assembly.
The compatibility of the 8089 with the 8086 and
8088 extends beyond the hardware interface.
Comparing figure 3-45, with figure 2-45, one can
see that, except for the translate step, the software
development process is identical for both
8086/8088 and 8089 programs. The ASM-89
assembler produces a relocatable object module
that is compatible with the 8086 family software
development utilities LIB-86, LINK-86, LOC-86
and OH-86, described in section 2.9. All of these
development tools run on an Intellec® 800 or
Series II microcomputer development system.
Statements
Statements are the building blocks of ASM-89
programs. Figure 3-46 shows several examples of
ASM-89 statements. The ASM-89 assembler gives
programmers considerable flexibility in formatting program statements. Variable names and
labels (identifiers) may be up to 31 characters
long, the underscore (_) character may be used
to improve the readability of longer names (e.g.,
This section surveys the facilities of the ASM-89
assembler and discusses how LINK-86 and
LOC-86 can be used in 8089 software development. For a complete description of the 8089
assembly language, consult 8089 Assembly
Language User's Guide, Order No. 9800938,
available from Intel's Literature Department.
3-63
80891NPUT/OUTPUT PROCESSOR
WAIT_UNTIL_READY). The component
parts of statements (fields) need not be located at
particular "columns" of the statement. Any
number of blank characters may separate fields
and multiple identifiers within the operand field.
Long statements may be continued onto the next
link by coding an ampersand (&) as the first
character of the continued line.
(FROM PL/M·B6 &ASM-86 TRANSLATORS)
UPDATE
LIBRARIES
LlB-86
Figure 3-45.8089 Software Development Process
; THIS STATEMENT CONTAINS ACOMMENT FIELD ONLY
; TYPICAL ASM89 INSTRUCTION
ADDI BC,5
BC,
5
; NO "COLUMN" REQUIREMENTS
ADDI
[GAl.STATUS,
MOV
&
6
; A CONTINUED STATEMENT
SOURCE
EQU GA
; A SIMPLE ASM89 DIRECTIVE
L1NE_BUFFER_ADDRESS DO ; A LONG IDENTIFIER
Figure 3-46. ASM-89 Statements
Mnemonics © Intel, 1979
3-64
8089 INPUT/OUTPUT PROCESSOR
A statement whose first non-blank character is a
semicolon is a comment statement. Comments
have no affect on program execution and, in fact,
are ignored by the ASM-89 assembler. Nevertheless, carefully selected comments are included
in all well written ASM-89 programs. They summarize, annotate and clarify the logic of the program where the instructions are too
"microscopic" to make the operation of the program self-evident.
tion as long as bit 3 of the byte addressed by
[GA].ST ATUS is not true. The mnemonic field of
an instruction statement specifies the type of 8089
machine instruction that the assembler is to build.
An ASM-89 instruction statement (figure 3-47)
directs the assembler to build an 8089 machine
instruction. The optional label field assigns a
symbolic identifier to the address where the
instruction will be stored in memory. A labelled
instruction can be the target of a program
transfer; the transferring instruction specifies the
label for its target operand. In figure 3-47 the
labelled instruction conditionally transfers to
itself; the program will loop on this one instruc-
An ASM-89 directive statement (figure 3-48) does
not produce an 8089 machine instruction. Rather,
a directive gives the assembler information to use
during the assembly. For example, the DS (define
storage) directive in figure 3-48 tells the assembler
to reserve 80 bytes of storage and to assign a symbolic identifier (INPUT_BUFFER) to the first
(lowest-addressed) byte of this area. The ASM-89
assembler accepts 14. directives; the more commonly used directives are discussed in this section.
The operand field may contain no operands or
one or more operands as required by the instruction. Multiple operands are separated by commas
and, optionally, by blanks. Any instruction statement may contain a comment field (comment
fields are initiated by a semicolon).
;WAIT UNTIL READY
[
I
COMMENT (OPTIONAL)
OPERANDS (REQUIRED/PROHIBITED)
' - - - - - - - - - - - - - - - - - MNEMONIC (REQUIRED)
.......- - - - - - - - - - - - - - - - - - - LABEL (OPTIONAL)
Figure 3-47. ASM-89 Instruction Format
INPUT_BUFFER:
OS
80
COMMENT (OPTIONAL)
.......- - - - - - OPERANDS (REQUIRED/PROHIBITED)
.......- - - - - - - - - MNEMONIC (REQUIRED)
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _
LABEL/NAME (REQUIRED/PROHIBITED)
Figure 3-48. ASM-89 Directive Format
3-65
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSO.R
The first field in a directive may be a label ora
name; individual directives may require or prohibit names, while labels are optional Jor directives that accept them. A label ends in a colon like
an instruction statement label. However, a directive label cannot be specified .as the target of a
program transfer. A name does not have a colon.
The second field is the directive mnemonic, and
the assembler distinguishes between instructions
and directives by this field.' Any operands
required by the directive are written next; multiple
operands are separated by commas and, optionally, by blanks. A comment may be included in
any directive by beginning the text with a
semicolon.
As an aid to program clarity, The EQU (equate)
directive may be used to give names to constants
(e.g., DISK-STATUS EQU OFF20H).
Defining Data
Fotir ASM-89 directives reserve space for memory
variables in the ASM-89 program (see figure
3-50): The DB, DW and DD directives allocate
units of bytes, words and doublewords, respectively, initialize the locations, and optionally label
them so that they may be referred to by name in
instruction statements. The label of a storage
directive always refers to the first (lowestaddressed)· byte of the area reserved by the
qirective.
"
.
The DB and DW directives may be used to define
byte- and word-constant scalars (individual data
items) and arrays (sequences of the same type of
item). For example, a character string constant
could be defined as a byte array:
Constants
Binary, decimal, octal and hexadecimal numeric
constants (figure 3-49) may be writtcm in ASM-89
instructions and directives. The assembler can
add and subtract constants at assembly .time.
Numeric constants; including theresufis of
arithmetic operations, must be representable in 16
bits. Positive numbers cannot exceed 65,535
(decimal); negative numbers, which the assembler
represents in two's complement notation, cannot
be "more negative" than -32,76& (decimal).
SIGN_ON_MSG: DB 'PLEASE ENTER PASSWORD'
The DD directive is typically used to define the
address ofa location in the" system space, i.e., a
doubleword pointer variable. The address may be
loaded into a pointer register with the LPD
instruction.
The DS directive reserves, and optionally names,
storage in units of bytes, but does not initialize
a11Y of the reserved bytes. DS is typically used for
RAM-based variables such as buffers. As there is
no special directive for defining a physical address
pointer, DS is typically used to reserve the three
bytes used by the MOVP instruction.
Character constants are enclqsed in single quote
marks as shown in figure 3-49. Strings of
characters up to 255 bytes long may be written
when initializing storage. Instruction operands,
however, can only be one or two characters long
(for byte and word instructions respectively).
MOVBI
GA, 'A'
; CHARACTER
MOVBI
GA,41 H
; HEXADECIMAL
MOVBI
GA,65
; DECIMAL
"
MOVBI
GA,65D
; DECIMAL ALTERNATIVE
MOVBI
GA,101Q
; OCTAL
GA,1010
; OCTAL ALTERNATIVE
MOVBI
MOVBr
GA, 01000001 B ; BINARY
; NEXT TWO STATEMENTS ARE EQUIVALENT AND
ILLUSTRATE TWO'S COMPLEMENT REPRESENTATION
;
;
"OF NEGATIVE NUMBERS
GA,-5
MOVBI
MOVBI
GA,11111011B
Figure.3-49. ASM89 Constants
Mnemonics © Intel, 1979
"3-66
8089 INPUT/OUTPUT PROCESSOR
; ASM89 DIRECTIVE
ALPHA: DB
1
-2
DB
DB
'A', 'B'
BETA:
DW
1
-5
DW
DW
'AB'
DW
400,500
DW
400H,500H
gamma: DW
BETA
DELTA
DD
GAMMA
ZETA:
DS
80
; MEMORY C.oNTENT(HEX)
; 01
; FE (TW.o'S C.oMPLEMENT)
; 4142
; 0100
; FAFF
; 4241
; 2410F401
; 00040005
; .oFFSET .oF BET A AB.oVE,
; FR.oM BEGINNING .oF PR.oGRAM
; ADDRESS (SEGMENT & .oFFSET)
;.oFGAMMA
; 80 BYTES, UNINITIALIZED
Figure 3-50. ASM-89 Storage Directives
Structures
assembler uses the structure element name to produce an offset value (structures are used with the
offset. addressing mode). Compared to "hard·
coded" offsets, structures improve program clarity and simplify maintenance. If the layout of a
memory block changes, only the structure definition must be modified. When the program is
reassembled, all symbolic references to the structure are automatically adjusted. When multiple
areas of memory are laid out identically, a single
structure can be used to address any area by
changing the content of the pointer (base) register
that specifies the structure's "starting address."
An ASM-89 structure is a map or template that
gives names and relative locations to a collection
of related variables that are called structure
elements or members. Defining a structure,
however, does not allocate storage. The structure
is, in effect, overlaid on a particular area of
memory when one of its elements is used as an
instruction operand. Figure 3-51 shows how a
structure representing a parameter block could be
defined and then used in a channel program. The
MEMORY MAP
OFFSETS,
+10
+8
,
HIGHER ADDRESSES
STRUCTURE DEFINITION
BUFFER_LEN
PARM_BLOCK
TP_RESERVED:
COMMAND:
RESULT:
BUFFER_START:
BUFFER_LEN:
PARM_BLOCK
BUFFER_START
+6
+4
,
COMMAND
I
RESULT
STRUC
OS
4
OS
1
OS
1
OS
4
OS
2
ENDS
+2
TP _RESERVED
PP- -
.+0
LOWER ADDRESSES
h
USING "HARD·CODED" OFFSETS
USING STRUCTURE ELEMENT NAMES
LPD GA, [PPj.6
MOVBI [PPj.5,0
LPD GA, [PPj.BUFFER_START
MOVBI [PPj.RESULT,O
Figure 3-51. ASM-89 Structure Definition and Use
3-67
Mnemonics © Intel, 1979
80891NPutiOUTPUT PROCESSOR
Addressing Modes
Note that any pointer register could have been
substituted for GA in ihe'p,revious examples.
Table 3-18 summarizes the notation a programmer uses to specify how the effective address of a'
memory operand is to be computed. Examples of
typical ASM-89 coding for each addressing mode,
as well as register and immediate operands, are'., '
provided in figure 3-5LNotice that a bracketed, .::
reference to a register indicates that the content of
the register is to be usedu>'form'the effective
address of a' memory operand; 'while" ari
unbracketed register reference' specifies that the'"
register itself is the operand,
,: ' ,
Table,3-18. ASM-89,~mory Addressing
,
ModeNotation
',",
Notation
[ptr-reg]
[ptr-reg ].offset
[ptr-reg + IX]
[ptr-reg + IX +]
The following examples summarize how the,
memory addressing modes can be used to access'
simple variables, structures and arrays. '"
If GA contains the address of a memory
"', ?perand, then [GA] refers to that operand.
41' "II. oK!' cdrttilins 'the base, address of a
~trudfu~e.. '1h:ebJGA].i)ATA refers ,to the
DAT Ael~m~nt (fie!d)' iii thaI struct~re. If
DATA is sixbytes'from the beginning of the
structure, then [GA].6 r32,768
>32,767
~128
Backward
Forward
BaCkward
Forward
Backward· .
Forward
~127
~32,768
~32,767
>32,768
>32,767
3-69
Displacement
Sign Bytes
-
...
1
+ 1
- 2:
.,
Error
::. Error·
Error
-
2
2
.... - . 2
+ 2
Error;
Error·
+
',.
':.:'
Mnemonics © Intel.l~7~
8089 INPUT IOUTPUt PROCESSOR
CALL SAVE:
.
DS
3
; TP SAVE AREA
; SET UPTP SAVE AREA
NOTE: EXAMPLE ASSUMES PROGRAM
IS IN 1/0 SPACE. USE LPDI
IF IN SYSTEM SPACE.
,
MOVI . GC, CALLSAVE
; LOAD ADDRESS TO GC .' .
; CALLlT ..
. LCALL [GC),DEMO
HLT
; LOGICAL END OF PROGRAM
; DEFINE THE PROCEDURE.
DEMO:
; PROCEDURE INSTRUCTIONS GO HERE.
; NOTE: PROCEDURE MUST NOT UPDATE GC,
;.
AS IT POINTS TO THE RETURN ADDRESS.
'; RETURN TO CALLER.
MOVp· TP, [GC)
Figure 3-53. ASM-89 Procedure Example
; START OF SEGMENT "
SEGMENT
ASM89 SOURCE STATEMENTS
CHANNEL1
ENDS
END
; END OF SEGMENT
;END OFASSEMBLY
Figure 3-54. ASM-89 SEGMENT and ENDS Directives
figure shows, the segment can then be located so
that instructions and constants fall into the ROM
portion of memory, while the variable part of the
segment is located in RAM. The entire segment,
including any "unused" portions, of cours!;!, cannot exceed 64k bytes.
Intermodule Communication
An ASM-89 module can make some of its
addresses available to other modules by defining
symbols with the PUBLIC directive. At a
Mnemonics © Intel, 1979
minimum, a channel program must make the
. address of. its first instruction available to the
CPU module that starts the channel program.
Figure 3-56 shows an ASM-89 module that contains . three channel programs labelled READ,
WRITE and DELETE. The example shows how a
. PL/M-86 program and an ASM-86 program
could define these "entry points" as EXTERNAL and EXTRN symbols respectively. When
the modules are linked together, LINK-86 will
match the externals with the publics, thus providing the CPU programs with the addresses they
need.
3-70
8089 INPUT /OUTPUT PROCESSOR
DEMO: SEGMENT
;CONSTANT DATA
HIGHER ADDRESSES
;INSTRUCTIONS
(AVAILABL E)
-----VARIABLES
ORG 2000H
;VARIABLE DATA
2000H
t-------t
(UNUSED)
DEMO ENDS
END
t
RAM
ROM
INSTRUCTIONS
CONSTANTS
(AVAILABLE)
LOWER ADDRESSES
Figure 3-55. Using the ASM-89 ORO Directive
ASM-89 MODULE DEFINES THREE PUBLIC SYMBOLS
PUBLIC
READ, WRITE, DELETE
READ:
; ASM89 INSTRUCTIONS FOR "READ" OPERATION
WRITE:
HLT
; ASM89 INSTRUCTIONS FOR "WRITE" OPERATION
DELETE:
HLT
; ASM89 INSTRUCTIONS FOR "DELETE" OPERATION
HLT
Figure 3-56. ASM-89 PUBLIC Directive
3-71
Mnemonics © Intel, 1979
8089 INPUT /OUTPUT PROCESSOR
PLlM-86 MODULE USES "WRITE" SYMBOL
DECLARE
DECLARE
(READ,WRITE,DELETE) POINTER EXTERNAL;
PARM$BLOCK STRUCTURE
(TP$START
POINTER,
BUFFER$ADDR
POINTER,
BUFFER$LEN
WORD);
'*SET UP "WRITE" CHANNEL OPERATION*'
PARM$BLOCK. TP$START = WRITE;
ASM-86
MODULE USES "READ" SYMBOL
EXTRN
READ,WRITE,DELETE
READ_PTR
WRITE_PTR
DELETE_PTR
DD
DD
DD
READ
WRITE
DELETE
; PARM_BLOCK
EVEN
TP _START
DD ?
BUFFER_ADDRDD ?
BUFFER_LEN DW?
; FORCE TO EVEN ADDRESS
; SET UP "READ" CHANNEL OPERATION
MOV AX, WORD PTR READ_PTR
MOV WORD PTRTP _START, AX
MOV AX, WORD PTR READ_PTR
MOV WORD PTR TP_START + 2, AX
; 1ST WORD
; 2ND WORD
Figure 3-56. ASM-89 PUBLIC Directive (Cont'd.)
Conversely, an ASM-89 module can obtain the
address of a public symbol in another module by
defining it with the EXTRN directive. An external
symbol, however, can only appear as the initial
value operand of a DD directive (see figure 3-57).
This effectively means that an ASM-89 program's
Mnemonics © Intel. 1979
use of external symbols is limited to obtaining the
addresses of data located in the system space.
Another way of doing this, which may be
preferable in many cases, is to have the CPU program place system space addresses in the
parameter block.
3-72
8089 INPUT IOUTPUTPROCESSOR
PLlM-86 PROGRAM DECLARES PUBLIC SYMBOL "BUFFER"
DECLARE BUFFER (80) BYTE PUBLIC;
ASM-89 PROGRAM OBTAINS ADDRESS OF PUBLIC SYMBOL "BUFFER"
EXTRN BUFFER
BUF_ADDRESS
LPD
DD
BUFFER
GA, BUF_ADDRESS
; POINT TO SYSTEM BUFFER
Figure 3-57. ASM-89 EXTRN Directive
Sample Program
Figure 3-58 diagrams the logic of a simple
ASM-89 program; the code is shown in figure
3-59. The program reads one physical record (sector) from a diskette drive controlled by an 8271
Floppy Disk Controller. No particular system
configuration is implied by the program, except
that the 8271 resides in the lOP's I/O space.
Hardware address decoding logic is assumed to be
set up as follows:
•
•
•
•
•
reading location FFOOH selects the 8271
status register,
writing location FFOOH selects the 8271
command register,
reading location FFOIH selects the 8271·
result register
writing location FFOIH selects the 8271
parameter register
decoding the address FF04H provides the
8271 DACK (DMA acknowledge) signal.
Figure 3~58. ASM-89 Sample Program Flow
3-73
Mnemonlcs.© Inlel, 1979
8089 INPUT/OUTPUT PROCESSOR
The program uses structures to address the
parameter block and the 8271 registers. Register
PP contains the address of the parameter block,
and the program loads GC with FFOOH to point
to the 8271 registers. The program's entry point
(the label START) is defined as a PUBLIC symbol so that the CPU program can place its address
in the parameter block when it starts the program.
,Register IX is used asa retry counter. If the
transfer is not completed successfully (bit 3 of the
8271 result register 0), the program retries the
transfer up to 10 times.
*'
Since the 8271 automatically requests a DMA
transfer upon receipt of the last parameter, this
parameter is sent immediately following the
XFER command.
8089 ASSEMBLER
ISIS-II 8089 ASSEMBLER V1.0 ASSEMBLY OF MODULE FLOPPY
OBJECT MODULE PLACED IN : FO: FLOPPY. OBJ
ASSEMBLER INVOKED BY ASM89 FLOPPY.A89
1
0000
.1.
SEGMENT
2 FLOPPY
3 ;
4 ; ••• 8089 PROGRAM TO READ SECTOR FROM FLOPPY DISK
5 .•••
'6 '.'
7 .••• LAY OUT PARAMETER BLOCK.
8 PARM BLOCK
STRUC
9
RESERVED TP:
DS
4
10
BUFF PTR:
DS
4
11
TRACK:
OS
1
12
SECTOR:
uS
1
13
RETURN CODE:
DS
1
14
PARM BL'OCK
ENDS
15
16 ;"'LAY OUT 8271 DEVI CE REGISTERS.
STRUC
17 FLOPPY REGS
18
COMMAND STAT:
DS
DS
19
PARM RESULT:
20
FLOPPY REGS
ENDS
21
22 ; ••• 8271 ADDRESSES.
23 FLOPPY REG ADDR EQU
OFFOOH
;LOW-ADDRESSED REGISTER
24 DACK 8271
EQU
OFF04H
;DMA ACKNOWLEDGE
25
26 ; ••• MAKE PROGRAM ENTRY POINT ADDRESS
~~ PUBLIC AVAILABLE ~~A~iHERMODULES.
0000
0004
0008
0009
OOOA
OOOB
0000
0001
0002
HOD
FF04
0000
OA4F OA 00
0004
B130 DADO
0008
5130 DOFF
OOOC
EABA 00 FC
0010
OA4E 00 12
0014
0293 08 02CE 01
001A
D130 2088
29
30
31
32
33
34
35
30
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
;·.·CLEAR RETURN CODE IN PARAMETER BLOCK.
START:
MOVBI
[PPJ.RETURN CODE,O
;".INITIALIZE RETRY COUNT.
. MOVI
IX,10
; ···POINT GC AT LOW-ORDER 8271 REGISTER.
MOVI
GC, FLOPPY REG ADDR
;1t**SEND COMMAND SEQUENCE TO 8271, HOLDING FINAL PARM.
····WAIT UNTIL 8271 IS NOT BUSY.
RETRY:
JNBT
[GCj.COMMAND STAT,7,RETRY
;···SEND "READ SECTOR, DRIVE 0" COMMAND.
MOVBI
[GCj.COMMAND STAT,012H
;'.'SEND TRACK ADDRESS PARAMETER.
MOVB
[GCj.PARM RESULT,[PPJ.TRACK,
; ••• LOAD CHANNEL CONTROL REGISTER SPECIFYING:
FROM PORT TO MEMORY,
SYNCHRONIZE ON SOURCE,
GA POINTS TO SOURCE,
TERMINATE ON EXT,
TERMINATION OFFSET
O.
MOVI
CC,08820H
Figure 3-59. ASM-89 Sample Program
Mnemonics © Intel, 1979'
3-74
8089 INPUT /OUTPUT PROCESSOR
001E
AOOO
0020
0023
238B 04
1130 04FF
0027
AABA 00 FC
002B
6000
002D
0293 09 02CE 01
0033
6ABE 01 05
0037
A03C
0039
A840 DO
003C
EABA 00 FC
0040
OA4E 00 2C
0044
8ABA 00 FC
0048
0292 01 02CF OA
004E
4000
0050
2048
55 i"IISET SOURCE BUS = 8, DEST BUS = 16.
56
WID
8,16
57
~8 ; ""POINT GB AT DESTINATION, GA AT SOURCE.
LPD
UB,[PP].BUFF PTR
59
MOVI
GA, DACK~827160
01
b2 i .IIINSURE THAT 8271 IS READY FOR -LAST PARAMETER.
63 WAIT1:
JNBT
[GC].COMMAND_STAT,5,WAITl
64
05 i"IIPREPARE FOR DMA.
06
XFER
67
b8 i"I.START DMA BY SENDING FINAL PARAMETER TO 8271.
09
MOVB
[GCJ.PARM_RESULT,[PP].SECTOR
70
71 i"IIPROGRAM RESUMES HERE FOLLOWING EXT.
72
73 i '''IF TRANSFER IS OK THEN EXIT ,ELSE TRY AGAIN.
74
JBT
[GCJ.PARM_RESULT,3,EXIT
75
76 i"IIDECREMENT RETRY COUNT.
77
DEC
IX
78
79 i·I·TRY AGAIN IF COUNT NOT EXHAUSTED.
80
JNZ
IX, RETRY
81
ll2 i'''WAIT UNTIL 8271 IS NOT BUSY.
83 EXIT:
JNBT
[GCJ.COMMAND_STAT,7,EXIT
84
85 i".ISEND "READ RESULT" COMMAND TO 8271.
86
MOVBI
[GCJ.CUMMAND_STAT,02CH
87
88 ;"".WAIT FOR RESULT.
89 WAIT2:
JNBT
[GCJ.COMMAND_STAT,4,WAIT2
90
91 i ···POST RESULT IN PARAMETER BLOCK FOR CPU.
92
MOVB
[PP].RETURN __ CODE,[GCJ.PARM_RESULT
93
94 i· •• INTERRUPT CPU.
95
SINTR
96
97 i"IISTOP EXECUTION.
98
HLT
99
100 FLOPPY
ENDS
101
END
0052
SYMBOL TABLE
-----------DEFN VALUE TYPE
10
18
24
83
2
17
23
8
19
9
41
13
12
31
11
63
89
0004
0000
FF04
003C
0000
0000
FFOO
0000
0001
0000
OOOC
OOOA
0009
0000
0008
0027
0044
NAME
SYM BUFF PTR
SYM COMMAND STAT
SYM DACK 8271
SYM EXITSYM FLOPPY
STR FLOPPY REGS
SYM FLOPPY-REG ADDR
STR PARM B[OCK-SYM PARM-RESULT
SYM RESERVED TP
SYM RETRY
SYM RETURN_CODE
SYM SECTOR
PUB START
SYM TRACK
SYM WAITl
SYM WAIT2
ASSEMBLY COMPLETEi NO ERRORS FOUND
Figure 3-59. ASM-89 Sample Program (Cont'd.)
Mnemonics © Intel, 1979
3-75
8089.INPUTIOUTPUTPROCESSOR
exter.nal symbol (see figure 3-56), LINK-86 will
obtain the address from the ASM-89 channel program when the two are linked together. (The
ASM-89. program must, of course, define' the
~ymbol in a PUBLIC directive.) . '.
Linking and Locating ASM-89 Modules
The LINK-86 utility program combines multiple
relocatable ()bject modules into a single.
relocatable module. The input m9dules may con~
sist of modules produced by any of the 8086 family language translators: ASM-89, ASM-86, or
PLlM-86. LINK-86's principal function is to
satisfy external references made in the moduies~
Any symbol that is defined with the EXTRN
directive in ASM-89 or ASM-86 oris declared
EXTERNAL in,PLlM-86' is an external.
reference, i.e., a' reference to ari address contained in another module. Whenever LINK-86
encounters an external reference, it searches the
other modules for a PUBLIC symbol of the Same
name. If it finds the matching symbol, it replaces
the external reference with the address .of. the
object.
The most common' occurrence of an external
reference in a system that employs one or .more
8089s is the channel 'program' address. Inorder
for a CPU program to start a channel program I it
must erisure that the address of the first channel
program instruction is contained in the first two
words of the parameter block. Since the channel
program is assembled separately, the translator
that processes the CPU program will not typically
know its address. If this address is defined as an
Figure3~60.
Other external references may arise when one
module. uses data (e.g., a buffer) that is contained
in another module, and (in PLlM-86 and
ASM-86 modules) when oI).e module executes
another module, typically by a CALL statement
. :or instruction.
When an 8089 module (or modules) is to be
located in the system space, it may be linked
together with PLlM-86 or ASM-86 modules as
described above and shown in figure 3-60.
LINK-86 resolves external references 'and combines the input modules into a single relocatable
object module. This module' caw,be input to
LOC-86 (LOC-86 assigns final absolute memory
addresses to all of the instructions and data). This
, . absolute object module may, in turn, be processed by the OH-86 utility to translate the
module into the hexadecimal format. This format
makes the module readable (the records are written ill ASCII characters) and is required by some
PROM programmers and RAM loaders. Intel's
Universal PROM Programmer (UPP) and iSBC
957™ Execution Package (loader) use thehexadecimal format.
Creating. a Single Absolute Object Module
3-76
80891NPUT/OUTPUT !P'ROCESSOR
If the 8089 code is to reside in its 1/0 space, a different technique is required since separate
absolute object modules must be produced for the
system and 110 spaces. Figure 3-61 shows how to
link and locate when there are exter'nal references
between 110 space modules and system space
modules.
segment conflict messages from LOC-86. It
reoluires, however, that modules in the two spaces
n,ot llse the EXTRN/PUBLIC mechanism to refer
to each other. Modules in the same space can
deJiil.1e external and public symbols, however.
Ex temal references from 1I0space,modul(,!s to
sYf';tem space modules can' be eliminated if the
CPU programs pass ,all system space addresses in
paralmeter blocks. In oth(,!r words, a channel progranll can obtain any address in the system space if
the :address is in the parameter block. Using this
apptoach allows the system space addresses to be
changed during execution. If the addresses are
constant values, they may also, be altered as
sysltt:m development proceeds without relinking
the'c'hannel programs.'
The normal link and locate sequence is followed
and culminates in the production of an absolute
module in hexadecimal format. Since the records
in this file are human-readable, the file can' be
edited using the ISIS-II text editor. The editing
task involves finding the 8089 110 space records
in the file, writing them to one file, and then
writing the 8086/8088 records (destined for the
system space) to another file. MCS-86 Absolute
Object File Formats, Order No. 9800921,
available from Intel's Literature Department,
describes the records in absolute (including hexadecimal) object modules.
External references from system space modules to
ad,dresses in the 1/0 space may be eliminated by
assig, ning these addresses values that are known at
assembly or compilation time. Figure 3-63
illust ,rates how the ASM-89 ORO directive can be
used to force the first instruction (entry point) of
a chU,nnel program to an absolute address. In the
case of' the example,()ne module contains two
entr), points labelled "READ" and "WRITE."
Assnming the module is located at absolute
address OH in the 110 space, the channel program IS will begin at 2001land 600H respectively.
In n Ie example, these values have been chosen
arb it rarily; in a typical application they would be
base( j on the length of the programs and the location I)f RAM and ROM areas. By starting the programls at fixed addresses that are known to the
CPU programs that activate them, the channel
proglrams can be reassembled without needing to
relin],~ the CPU programs.
When using the previous method, it is likely that
LOC-86 will issue messages warning that
segments overlap. For example, the 8089 code
would typically be located starting at absolute
location OH of the 110 space. However, the
8086/8088 interrupt pointer table occupies these
low memory addresses in the system space. Since
LOC-86 has no way to know that the segment will
ultimately be located in different address spaces,
it will warn of the conflict; the warning may be
ignored.
An alternative to linking the modules together
and then separating them is to link system space
modules separately from 110 space modules as
shown in figure 3-62. This approach avoids the
manual edit of the absolute object module and the
TO SYSTEM
SPACE
FROM
ASM-86
TallO
SPACE
,
I
'
Figure 3-61. Creating Separate Absolute Object ModuVes-External References in Relocatable
,
'"
,
Modules. "
3-77
80891NPUTlOUTPUT PROCESSOR
-------------------------------,~----------------------------------------
rOSYSTEM
SPACE
TO 110
FROM
ASM-8a
SPACE
, Figure 3-62. Creating Separate Absolute Object Modules-No External References in Relocatable
Modules
ASM-89 ENTRY POIN'T DEFINITION'S
, ORG 200H
READ:
;JNSTRUCTIONS FCIR"READ" CHANNEL PROGRAM
ORG600H
WRITE:
; INSTRUCTIONS FOR "WRITE" CHANNEL PROGRAM
ASM-86 DEFINITION' OF ENTRY POINT ADDRESSES
DD 200H
DD 600H
PLlM-86 DECLARAtiON OF ENTRY POINT ADDRESSES
DECLARE READ$ADDR POINTER;
DECLARE WRITE$PIDDR POINTER;
READ$ADDR = 200H ;
WRITE$ADDR = 60011rf;
Figure 3-63. Using Absolute Entry Point Addresses
------------------------~..~------------------------~-------3-78
8089 INPUT IOUTPUT PROCESSOR
3.10 Programming Guidelines
and Examples
memory if it is on an odd address. The processor
will thus execute a partially-modified instruction
with unpredictable results.
This section provides two types of 8089 programming information. A series of general guidelines,
which apply to system and program design, is
presented first. These guidelines are followed by
specific coding examples that illustrate programming techniques that may be applied to many different types of applications.
I/O System Design
Section 2.10 notes that I/O systems should be
designed hierarchically. Application programs
"see" only the topmost level of the structure; all
details pertaining to the physical characteristics
and operation of I/O devices are relegated to
lower levels. Figure 3-64 shows how this design
approach might be employed in a system that uses
an 8089 to perform I/O. The same concept can be
expanded to larger systems with multiple lOPs.
Programming Guidelines
The practices in this section are recommended to
simplify system development and, particularly,
for system maintenance and enhancement. Software that is designed in accordance with these
guidelines will be adaptable to the changing
environment in which most systems operate,
and will be in the best position to take
advantage of new intel hardware and software
products.
The application system is clearly separated from
the I/O system. No application programs perform I/O; instead they send an I/O request to the
I/O supervisor. (In systems with file-oriented
I/O, the request might be senUo a file system that
would then invoke the I/O supervisor.) The I/O
request should be expressed in terms of a logical
block ·of data-a record, a line, a message, etc. It
should also be devoid of any device-dependent
information such as device address, sector size,
etc.
Segments
Although the lOP does not "see"the segmented
organization of system memory, it should respect
this logical structure. The lOP should only
address the system space through pointers passed
by the CPU in the parameter block. It should not
perform arithmetic on these addresses or otherwise manipulate them except for the automatic
incrementing that occurs during DMA transfers.
It is the responsibility of the CPU to pass
addresses such that transfer operations do not
cross segment boundaries.
The I/O supervisor transforms the application
program's request for service into it parameter
block and dispatches a channel program to carry
out the operation. The I/O supervisor controls
the channels; therefore, it knows the correspondence between channels and I/O devices,
the locations of CBs and channel programs, and
the format of all of the parameter blocks. The
I/O supervisor also coordinates channel
"events," monitoring BUSY flags and responding to channel-generated interrupt requests. The
I/O supervisor does not, however, communicate
with I/O devices that are controlled by the channels. If the CPU performs some I/O itself (this
should be restricted to devices other than those
run by the channels), the I/O supervisor invokes
the equivalent of a channel program in the CPU
to do the physical I/O. Note that although the
I/O supervisor is drawn as a single box in figure
3-64, it is likely to be structured as a hierarchy
itself, with separate modules perforining its many
functions.
Self-Modifying Code
Programs that alter their own instructions are difficult to understand and modify, and preclude
placing the code in ROM. They may also inhibit
compatibility with future Intel hardware and software products.
Note also that when the 8089 is on a 16-bit bus, its
instruction fetch queue can interfere with the
attempt of one instruction to modify the next
sequential instruction. Although the instruction
may be changed in memory, its unmodified first
byte will be fetched from the queue rather than
The software interface between the CPU's I/O
supervisor and an lOP channel program should
be completely and explicitly defined in the
3-79
8089 INPUT /OUTPUT PROCESSOR
1 i
APPLICATION I
SYSTEM
I
! :
---'-----1
I
I
I
I
I
APPLICATION
MODULE
1
CPU DOMAIN
t
APPLICATION
MODULE
1
APPLICATION
MODULE
t
J
I/O
SUPERVISOR
~----------------~----~--------:
i
CPU/lOP INTERFACE
~
~
~
:------------'- ---- ------,----,- -~ --t--------I
I
I
CHANNEL
SUPERVISOR
~I
I/O SYSTEM
CHANNEL
FUNCTION
CHANNEL
FUNCTION
CHANNEL
FUNCTION
lOP DOMAIN
I
I
DEVICE
CONTROLLER
I
I
I
I
I
DEVICE
CONTROLLER
I
I
I
I
I
I
I
I
CHANNELl
I
I
Figure 3-64. 8089-Based I/O System Design
3-80
CHANNEL2
CHANNEL
FUNCTION
8089 INPUT /OUTPUT PROCESSOR
parameter block. For example, the 110 supervisor
should pass the addresses of all system memory
areas that the channel program will use. The
channel program should not be written so that it
"knows" any of these addresses, even if they are
constants. Concentrating the interface into one
place like this makes the system easier to understand and reduces the likelihood of an undesirable
side effect if it is modified. It also generalizes the
design so that it may be used in other application
systems.
IFor
FIXED
o
TP/CHANNEL STATE
SAVE AREA
2
FIXED PARM11 FUNCTION
CODE
4
FIXEDPARM2
6
FIXEDPARM3
8
I
Figure 3-64 shows a simple channel program running on channel 1 and a more complex program
running on channel 2. Channell's program performs a single function and is therefore designed
as a simple program. The program on channel 2
performs three functions (e.g., "read," "write,"
"delete") and is structured to separate its functions. The functions might be implemented as
procedures called by the "channel supervisor"
depending on the content of the parameter block.
Notice that to the 110 supervisor, both programs
appear alike; in particular, both have a single
entry point.
10
RESERVED FOR
FUTURE USE
12
VARIABLE
For
,"
VARIABLE PARAMETER
FORMAT AND SIZE
GOVERNED BY
FUNCTION CODE
1
,h
1
Figure 3-65. Variable Format Parameter Block
In some channel programs, different functions
will need different information passed to them in
the parameter block. Figure 3-65 shows one
technique that accommodates different formats
while still allowing the channel supervisor to
determine which procedure to call from the PB.
The parameter block is divided into fixed and
variable portions, and a function code in the fixed
area indicates the type of operation that is to be
performed. Part of the fixed area has been set
aside so that additional parameters can be added
in the future.
Initialization and Dispatch
The PLlM-86 code in figure 3-66 initializes two
lOPs and dispatches two channel programs on
one of the lOPs. The same general technique can
be used to initialize any number of lOPs. The
hypothetical system that this code runs on is configured as follows:
•
8086 CPU (16-bit system bus);
•
two remote lOPs share an 8-bit local 1/0 bus
via the request/grant lines operating in
mode 1;
•
8089 channel attentions are mapped into four
port addresses in the CPU's 110 space;
Programming Examples
The first example in this section illustrates how a
CPU can initialize a group of lOPs and then
dispatch channel programs. This code is written
inPLlM-86.
•
channel programs reside in the 8089 110
space;
The remaining examples, written in ASM-89,
demonstrate the 8089 instruction set and addressing modes in various commonly-encountered programming situations. These include:
•
one 8089 controls a CRT terminal, one
channel running the display, the other scanning the keyboard and building input
messages;
•
•
•
the function of the second 8089 is not defined
in the example.
memory-to-memory transfers
saving and restoring registers
3-81
8089 INPUT IOUTPUT PROCESSOR
The code declares one CB (channel control block)
for each 8089. The. CBs are declared as twoelement arrays, each element defining the structure of one channel's portion of the CB. The SCB
(system. configuration block) and SCP (system
configuration pointer) are also declared as structures. The SCP is located at its dedicated system
space address of FFFF6H. The other structures
are not located at specific addresses since they are
all linked together by a chain of pointers
"anchored" at the SCP.
.
rop were on a different I/O bus, the SOC field
would have been altered if a different
request/grant mode were being used or if the lOP
had a 16-bit I/O bus. The second lOP is a slave so
its initialization is started by issuing a CA to channel2 rather than channell.
After both lOPs are ready, the code dispatches
two channel programs (not coded in the example);
one program is dispatched to each channel of one
of the lOPs. To avoid external references, the
system has been set up so that the PL/M-86 code
"knows" .the starting addresses of these channel
programs (200H and 600H). The code uses the
PLlM-86 LOCKSET function to:
Two simple parameter blocks define messages to
be transmitted between the PL/M-86 program
and theCRT. Each PB contains a pointer to the
beginning of the message area and the length of
the message. In the case of the keyboard (input)
message, the channel program builds the message
in the buffer pointed to by the pointer in the PB
and returns the length of the message in the.PB.
The code initializes one lOP at a time since the
chain of control blocks read by the lOP during
initialization must remain static until the process
is complete. To initialize the first lOP, the code
fills in the SYSBUS and SOC fields and links the
blocks to each other using the PLlM-86 @
(address) operator. It sets channell's BUSY flag
to FFH so that it can monitor the flag to determine when the initialization has been completed
(the rop clears the flag to OH when it has
finished). Channel 2's BUSY flag is cleared,
although this could just as well have been done
after the initialization (the rop does not alter
channel 2's BUSY flag during initialization). The
code starts the lOP by issuing a channel.attention
to channel 1 to indicate that the rop is a bus
master. PLlM-86's OUT function is used to select
the port address to which the rop's CA and SEL
lines have been mapped. The data placed on the
bus (OH) is ignored by the lOP. It then waits until
the lOP clears the channell BUSY flag.
•
•
•
lock the system bus;
read the BUSY flag;
set the BUSY flag to FFH jfit is clear;
•
unlock the system bus.
This operation continues until the BUSY flag is
found to be clear (indicating that the channel is
available). Setting the flag immediately to FFH
prevents another processor (or another task in
this program activated as a result of an interrupt)
from using the channel. The code fills in the
parameter block with the address and length of
the message to be displayed, sets the CCW and
then links the channel program (task block) start
address to the parameter block and links the
parameter block to the CB. The channel is dispatched with the OUT function that effects a
channel attention for channell.
A similar procedure is followed to start channel 2
scanning the terminal keyboard. In this case, the
code allows channel 2 to generate an interrupt
request (which it might do to signal that a message
h~s been assembled). An interrupt procedure
would then handle the interruptrequest.
The second rop is initialized in the same manner,
first changing the pointer in the SCB to point to
the second lOP's channel control block. If this
I*ASSIGN NAMES TO CONSTANTS* I
DECLARE
CHANNEL$BUSY
DECLARE
CHANNEL$CLEAR
CR/*CARR. RET.* I
DECLARE
DECLARE
LF 1*L1NE FEED* I
DECLARE
DISPLA Y$TB
DECLARE
KEYBD$TB
L1TERALLY'OFFH';
L1TERALLY'OH';
L1TERALLY'ODH';
L1TERALLY'OAH';
LITERALLY '200H';
LITERALLY '600H';
Figure 3-66. Initialization and Dispatch Example
3-82
8089 INPUT /OUTPUT PROCESSOR
DECLARE '"lOP CHANNEL ATTENTION ADDRESSES"'
IOP$A$CH1
LITERALLY
'OFFEOH', .
IOP$A$CH2
LITERALLY
'OFFE1 H',
IOP$B$CH1
LITERALLY
'OFFE2H',
IOP$B$CH2
LITERALLY
'OFFE3H';
DECLARE
'"CHANNEL CONTROL BLOCK FOR 10P$A)
CB$A(2)
STRUCTURE
BYTE,
(BUSY
CCW
BYTE,
POINTER,
PB$PTR
RESERVED
WORD);
DECLARE
'"CHANNEL CONTROL BLOCK FOR 10P$B" j
STRUCTURE
CB$B(2)
BYTE,
(BUSY
CCW
BYTE,
POINTER,
PB$PTR
RESERVED
WORD);
DECLARE
'"SYSTEM CONFIGURATION BLOCK"'
SCB
STRUCTURE
BYTE,
(SOC
RESERVED
BYTE,
POINTER);
CB$PTR
DECLARE
'"SYSTEM CONFIGURATION POINTER"'
SCP
STRUCTURE
BYTE, .
(SYSBUS
SCB$PTR
POINTER) AT (OFFFF~H);
DECLARE
MESSAGE$PB STRUCTURE
(TB$PTR
POINTER,
MSG$PTR
POINTER,
MSG$LENGTH WORD);
DECLARE
KEYBD$PB STRUCTUE
(TP$PTR
POINTER,
BUFF_PTR
POINTER,
MSG$SIZE
WORD);
DECLARE
SIGN$ON BYTE (") DATA
(CR, LF, 'PLEASE ENTER USER ID');
DECLARE
KEYBD$BUFF BYTE (256);
,"
"INITIALIZE 10P$A, THEN 10P$B
"'
'"PREPARE CONTROL BLOCKS FOR 10P$A"'
SCP .SCB$PTR = @ SCB; .
SCP.SYSBUS = 01 H; '"16-BIT SYSTEM BUS"'
SCB.SOC = 02H; '"RQ'GT MODE1, 8-BIT 1'0 BUS"'
SCB.CB$PTR = @ CB$A(O);
CB$A(O).BUSY = CHANNEL$BUSY
CB$A(1).BUSY = CHANNEL$CLEAR;
Figure 3-66. Initializatio.n and Dispatch Example (Cont'd.)
3-83
8089 INPUT /OUTPUT PROCESSOR
I*ISSUE CA FOR CHANNEL1, INDICATING lOP IS MASTER* I
OUT (IOP$A$CH1) = OH;
.
I*WAIT UNTIL FINISHED* I
DO WHILE CB$A(O).BUSY = CHANNEL$BUSY;
END;
I*PREPARE CONTROL BLOCKS FOR 10P$B* I
SCB.CB$PTR = @CB$B(O);
CB$B(O).BUSY = CHANNEL$BUSY;
CB$B(1). BUSY = CHAN N EL$CLEAR;
I*ISSUE CA FOR CHANNEL2, INDICATING SLAVE STATUS* I
OUT (IOP$B$CH2) = OH;
I*WAIT UNTIL lOP IS READY* I
DO WHILE CB$B(O).BUSY = CHANNEL$BUSY;
END;
1*
*SEND SIGN ON MESSAGE TO CRT CONTROLLED
*BY CHANNEL 1 OF 10P$A
*1
I*WAIT UNTIL CHANNEL IS CLEAR, THEN SETTO BUSY* I
DO WHILE LbCKSET (@CB$A(O).BUSY, CHANNEL$BUSY);
END;
.
I*SETCCWAS FOLLOWS:
*
PRIORITY = 1,
NO BUS LOAD LIMIT,
DISABLE INTERRUPTS,
START CHANNEL PROGRAM IN 1/0 SPACE* I
CB$A(O).CCW = 10011001 B;
I*LlNK MESSAGE PARAMETER BLOCK TOCB* I
CB$A(O).PB$PTR =@ MESSAGE$PB;
I*FILL IN PARAMETER BLOCK* I
MESSAGE$PB.TB$PTR = DISPLAY$TB;
MESSAGE$PB.MSG$PTR = @SIGN$ON;
MESSAGE$PB. MSB$LENGTH = LENGTH (SIGN$ON);
I*DISPATCH THE CHANNEL"I
OUT (IOP$A$CH1) = OH;
1*
*DISPATCH CHANNEL 2 OF 10P$A TO
*CONTINUOUSLY SCAN KEYBOARD, INTERRUPTING
*WHEN A COMPLETE MESSAGE IS READY
*1
I*WAIT UNTIL CHANNELIS CLEAR, THEN SET TO BUSY* I
DO WHILE LOCKSET (@ CB$A(1).BUSY, CHANNEL$BUSY);
END;
Figure3-66. Initialization and Dispatch Example (Cont'd.)
3-84
8089 INPUT /OUTPUT PROCESSOR
I*SET CCW AS FOLLOWS:
*
PRIORITY = 0
BUS LOAD LIMIT,
ENABLE INTERRUPTS,
START CHANNEL PROGRAM IN 1/0 SPACE* I
CB$A(1 ).CCW = 00110001 B;
1*L1NK KEYBOARD PARAMETER BLOCK TO CB* I
CB$A(1).PB$PTR = @KEYBD$PB;
I*FILL IN PARAMETER BLOCK* I
KEYBD$PB.TB$PTR = KEYBD$TB;
KEYBD$PB.BUFF$PTR = @ KEYBD$BUFF;
KEYBD$PB.MSG$SIZE = OH;
I*DISPATCH THE CHANNEL * I
OUT (IOP$A$CH2) = OH;
Figure3-66.Initialization and Dispatch Example (Cont'd,)
Memory-to-Memory Transfer
The channel responds to this command by saving
the task pointer and PSW -in the first two words
of the parameter block. The suspended program
can be restarted by issuing a "resume" command
that loads TP and the PSW from the save area.
Figure 3-67 shows a channel program that performs a memory-to-ip.emory block transfer in
seven instructions. The program moves up to 64k
bytes between any two locations in the system
space. A 16-bit system bus is assumed, and the
CPU is assumed to be monitoring the channel's
BUSY flag to determine when the program has
finished.
If the CPU wants to execute another channel program between the suspend and resume operations, the suspended program's registers will
usually have to be saved first. If the "interrupting" program -"knows" that the registers must be
saved, it can pedorm the operation and also
restore the registers before it halts.
To attain maximum transfer speed, the program
locks the bus during each transfer cycle. This
ensures that another processor does not acquire
the bus in the interval between the DMA fetch
and store operations. By setting this channel's
priority bit in the CCW to 1 and the other channel's to 0, the CPU could effectively prevent the
other channel from running during the transfer.
Byte count termination is selected so that the
transfer will stop when the number of bytes
specified by the CPU has been moved. Since there
is only a single termination condition,a termination offset of 0 is specified. The transfer begins
after the WID instruction, and the HLT instruction is executed immediately upon termination.
A more general solution is shown in figure 3-68.
This is a program that does nothing but save the
contents of the channel registers. The registers are
saved in the parameter block because PP is the
only register that is known to point to an available
area of memory. A similar program could be written to restore registers from the same parameter
block.
Using this approach, the CPU would "interrupt"
a running program as follows:
•
suspend the running program,
•
run the register save program,
Saving and Restoring Registers
•
run the "interrupting" program,
A CPU program can "interrupt" a channel program by issuing a "suspend" channel command.
•
run the register restore program,
•
resume the suspended program.
3-85
8089 INPUT /OUTPUT PROCESSOR
MEMEXAMP
SEGMENT
;""MEMORY-TO-MEMORY TRANSFER PROGRAM""
PB
STRUC
TP _RESERVED:
DS
4
FROM_ADDR:
DS
4
TO_ADDR:
DS
4
SIZE:
DS
2
ENDS
PB
;POINT GA AT SOURCE, GB AT DESTINATION.
LPD
.
GA, [PPl.FROM_ADDR
LPD
GB, [PP .TO_ADDR
;LOAD BYTE COUNT INTO BC.
MOV
BC, [PPj.SIZE
;LOAD CC SPECIFYING:
;
MEMORYTO MEMORY,
;
NOTRANSLATE,
;
UNSYNCHRONIZED,
;
GA POINTS TO SOURCE,
;
LOCK BUS DURING TRANSFER,
;
NO CHAINING,
;
TERMINATING ON BYTE COUNT,OFFSET = O.
MOV
CC, OC208H
;PREPARE CHANNEL FOR TRANSFER.
XFER
;SET LOGICAL BUS WIDTH.
WID'
16,16
;STOP EXECUTION AFTER DMA.
HLT
ENDS
MEMEXAMP
END
Figure 3-67. Memory-to-Memory Transfer Example
SAVEREGS
SEGMENT
;SAVE ANOTHER CHANNEL'S REGISTERS IN PB
PB
STRUC
TP_RESERVED:
DS
4
GA_SAVE:
DS
3
GB_SAVE:
DS
3
GC_SAVE:
DS
3
IX_SAVE:
DS
2
BC_SAVE:
DS
2
MC_SAVE:
DS
2
CC_SAVE:
DS
2
PB
ENDS
SAVEREGS
MOVP
MOVP
MOVP
MOV
MOV
MOV
MOV
HLT
ENDS
END
PP
PP
PP
PP
PP
PP
PP
.GA_SAVE, GA
.GB_SAVE, GB
.GC_SAVE, GC .
.IX_SAVE, IX
.BC_SAVE, BC
.MC_SAVE, MC
.CC_SAVE, CC
Figure 3-68. Register Save Example
Mnemonics © Intel, 1979
3-86
Hardware Reference
Information
4
CHAPTER4
HARDWARE REFERENCE INFORMATION
4.1 Introduction
Unit or "BIU." The EU for each processor is
identical. The BIU for the 8086 incorporates a 16bit data bus and a 6-byte instruction queue
whereas the 8088 incorporates an 8-bit data bus
and a 4-byte instruction queue.
This chapter presents specific hardware information regarding the operation and functions of the
8086 family processors: the 8086 and 8088 Central
Processing Units (CPUs) and the 8089 I/O Processor (lOP). Abbreviated descriptions of the
8086 family support circuits and their circuit
functions appear where appropriate within the
processor descriptions. For more specific
information on any of the 8086 family support
circuits, refer to the corresponding data sheets in
Appendix B.
The EU is responsible for the execution of all
instructions, for providing data and addresses to
the BIU, and for manipulating the general
registers and the flag register. Except for a few
control pins, the EU is completely isolated from
the "outside world." The BIU is responsible for
executing all external bus cycles and consists of
the segment and communications registers, the
instruction pointer and the instruction object
code queue. The BIU combines segment and offset values in its dedicated adder to derive 20-bit
addresses, transfers data to and from the EU on
the ALU data bus and loads or "prefetches"
instructions into the queue from which they are
fetched by the EU.
4.2 8086 and 8088 CPUs
The 8086 and 8088 CPUs are characterized by a
20-bit (1 megabyte) address bus and an identical
instruction/function format, and differ essentially from one another by their respective data bus
widths (the 8086 uses a 16-bit data bus, and the
8088 uses an 8-bit data bus). Except where
expressly noted, the ensuing descriptions are
applicable to both CPUs.
The EU, when it is ready to execute an instruction, fetches the instruction object code byte from
the BIU's instruction queue and then executes the
instruction. If the queue is empty when the EU is
ready to fetch at). instruction byte, the EU waits
for the instruction byte to be fetched. In the
course of instruction execution, if a memory location or 110 port must be accessed, the EU
requests the BIU to perform the required bus
cycle.
Both the 8086 and 8088 feature a combined or
"time-multiplexed" address and data bus that
permits a number of the pins to serve dual functions and consequently allows the complete CPU
to be incorporated into a single, 40~pin package.
As explained later in this chapter, a number of the
CPU's control pins are defined according to the
strapping of a single input pin (the MN/MX pin).
In the "minimum mode," the CPU is configured
for small, single-processor systems, and the CPU
itself provides all control signals. In the "maximum mode," an Intel® 8288 Bus Controller,
rather than the CPU, provides the control signal
outputs and allows a number of the pins previously delegated to these control functions to be
redefined in order to support multiprocessing
applications. Figures 4-1 and 4~2 describe the pin
assignments and signal definitions for the 8086
and 8088, respectively.
The two processing sections of the CPU operate
independently. In the 8086 CPU, when two or
more bytes of the 6-byte instruction queue are
empty and the EU does not require the BIU to
perform a bus cycle, the BIU executes instruction
fetch cycles to refill the queue. In the 8088 CPU,
when one byte of the 4-byte instruction queue is
empty, the BIU executes an instruction fetch
cycle. Note that the 8086 CPU, since it has a 16bit data bus, can access two instruction object
code bytes in a single bus cycle, while the 8088
CPU, since it has an 8-bit data bus, accesses one
instruction object code byte per bus cycle. If the
EU issues a request for bus access while the BIU is
in the process of an instruction fetch bus cycle,
the BIU completes the cycle before honoring the
EU's request.
CPU Architecture
As shown in figures 4-3 and 4-4, both CPUs
incorporate two separate processing units: the
Execution Unit or "EU" and the Bus Interface
4-1
HARDWARE REFERENCE INFORMATION
Common Signals
Name
Function
Type
AD15-ADO
Address/Data Bus
A19/S6A16/S3
Address/Status
Bidirectional,
3·State
Output,
3·State
Output,
3·State
BHE/S7
MN/MX
AD
TEST
READY
RESET
NMI
INTR
ClK
Vee
GND
Bus High Enable/
Status
Minimum/Maximum
Mode Control
Read Control
Wait On Test Control
Wait State Control
System Reset
Non·Maskable
Interrupt Request
Interrupt Request
System Clock
+5V
Ground
Input
Output,
3·State
Input
Input
Input
AD12
A17/s4
Input
AD11
A1B/sS
Input
Input
Input
AD10
A19/s6
Function
Type
HOLD
HlDA
Hold Request
Hold Acknowledge
Input
Output
Output,
3·State
Output,
3·State
Output,
3·State
Output,
3·State
M/IO
MemoryllO Control
DT/R
Data Transmit/
Receive
DEN
Data Enable
ALE
Address latch
Enable
Interrupt Acknowledge
INTA
Function
RQ/GT1,0
Request/Grant Bus
Access Control
Bus Priority lock
Control
lOCK
Output
Bus Cycle Status
Q81, QSO
Instruction Queue
Status
AD9
BHE/s7
ADB
MN/MX
AD
8086
HOLD
(RO/GTO)
HlDA
(RO/GT1)
AD4
WR
(lOCK)
AD3
M/iO
(52)
AD2
DT/R
(51)
AD1
DEN
(So)
ADO
ALE
(050)
NMI
INTA
(051)
INTR
TEST
CPU
ClK
READY
GND
RESET
Output
Type
82-S0
A16/S3
ADS
Maximum Mode Signals (MN/MX = GND)
Name
AD1S
AD13
AD7
Name
Write Control
vcc
AD6
Minimum Mode Signals (MN/MX=VCc)
WR
GND
AD14
MAXIMUM MODE PIN FUNCTIONS (e.g.,lOCK)
ARE SHOWN IN PARENTHESES
Bidirectional
Output,
3·State
Output,
3·State
Output
Figure 4-1. 8086 Pin Definitions
4-2
HARDWARE REFERENCE II NFORMATION
Common Signals
Name
Function
Type
AD7-ADO
Address/Data Bus
A15-A8
Address Bus
A19/S6A16/S3
Address/Status
Bidirectional,
3·State
Output,
3·State
Output,
3·State
MN/MX
Minimum/Maximum
Mode Control
Input
RD
Read Control
TEST
READY
RESET
Wait On Test Control
Wait State Control
System Reset
Non·Maskable
Interrupt Request
Interrupt Request
System Clock
+5V
Ground
Output,
3·State
Input
Input
Input
NMI
INTR
ClK
Vee
GND
Input
Input
Input
Input
Minimum Mode Signals (MN/MX
Function
Type
HOLD
HlDA
Hold Request
Hold Acknowledge
WR
Write Control
Input
Output
Output,
3·State
Output,
3·State
Output,
3,State
Output,
3·State
10/M
10/Memory Control
DT/R
Data Transmit/
Receive
DEN
Data Enable
ALE
INTA
Address latch
Enable
Interrupt Acknowledge
SSO
SO Status
vcc
A14
A15
A13
A16/S3
A12
Al71S4
All
A18/S5
A19/S6
Al0
A9
SSO
A8
MN/MX
8088
AD6
Output
(HIGH)
iii)
AD7
=Vee>
Name
GND
CPU
HOLD
(iffi/GTii)
AD5
HLDA
(RO/GT1)
AD4
Viii
(LOCK)
AD3
IO/M
(52)
AD2
DTIR
($1)
ADl
DEN
(SO)
ADO
ALE
(OSO)
NMI
iNTA
(OSl)
INTR
'fEST
CLK
READY
• GND
RESET
Output
Output,
3·State
Maximum MQdeSignals (MN/MX
=GND)
Name
Function
Type
RQ/GT1,0
Bidirectional
'CO'Ci<
Request/Grant Bus
Access Control
Bus Priority lock
Control
S2-S0
Bus Cycle Status
Output,
3·State
Output,
3·State
QS1, QSO
Instruction Queue
Status
Output
MAXIMUM MODE PIN FUNCTIONS (e.g.,LOCK)
ARE SHOWN IN PARENTHESES
Figure 4-2.8088 Pin De::finitions
4-3
HARDWARE FtEFERENCE INFORMATION
I
AH
ADDRESS BUS
I
BL
I
DL
GENERAL
REGISTERS
I
DATA BUS
(16 BITS)
BP
I
I
I
I r'I---'NTERNAL~
COMMUNICATIONS
REGISTERS
ALU DATA BUS
BUS
. CONTROL
lOGIC
(16 BITS)
BUS INTERFACE UNIT
(BIU),
E' XECUTION UNIT
(EU)
Figure 4-3. 80815 Elementary Block Diagram
AH
AL
OL
GENERAL
REGISTERS
SP
DP
01
so
.
J\LU DATA BUS
(16 BITS)
I
I
I
I
I
I
I
I ..
Ir
I
I
I
I
INTERNAL
COMMUNICATIONS
REGISTERS
I
El (ECUlION UNIT·
I
Figure 4-4.
8011~8
------------------------------------1
(EU)
I
6US INTERFACE UNIT
(BIU)
Elementary Block Diagram
4-4
8086
BUS
HARDWARE REFERENCE INFORMATION
and T 4' and the multiplexed address/data bus is
floated in state T2 to allow the CPU to change
from the write mode (output address) to the read
mode (input data).
Bus Operation
To explain the operation of the time"multiplexed
bus, the BIU's bus cycle must be examined.
Essentially, a bus cycle is an asynchronous event
in which the address' of an 1I0 peripheral or
memory location is presented,followed by either
a read control signal (to capture or "read" the
data from the addressed device) or a write control
signal and the associated data (to transmit or
"write" the data to the addressed device). The
selected. device (memory or 1I0 ;Jeripheral)
accepts the data on the bus during a write cycle or
places the requested data on the bus during aread
cycle. On termination of the' cycle, the device
latches the data written or removes the'data read.
It is important to note that the BIU executes a bus
cycle only when a bus cycle is requested by the EU
as part of instruction execution or when it must
fill the instruction queue. Consequently, clock
periods in which there is no BIU activity can
occur between bus cycles. These inactive clock
periods are referred to as idle states (T I): While
idle clock states result from several conditions
(e.g., bus access granted to a coprocessor), as an
example, consider the case of the execution of a
"long" instruction. In the following example; an
8-bit register multiply (MUL) instruction (which
requires between 70 and 77 clock, cycles) is executed by the 8086. Assuming that the multiplication routine is entered as a result of a program
jump (which causes the instruction queue to be
reinitialized when the jump is executed) and, as
will be explained later in this chapter, that the
object code bytes are aligned on even-byte boundaries, the BIU's bus cycle sequence would appear
as shown in figure 4-6.
As shown ih figure 4-5, all bus cycles consist of a
minimum of four clock cycles' or "T -states" identifiedas Tl, T2' T3 and T4.The CPU places the
address of the memory location orliO device on
the bus during state T 1. DUring a write bus cycle,
the CPU places the data on the bus from state T2
until stateT 4. During a read bus cycle, the CPU
accepts the data present on the bus in states T3
- - - - 6 U S CyClE---- -----6US CyClE-----l
Figure 4-5. Typical BIU Bus Cycles
r"\
I
r.,
,..,
.J
I
2
EU
ACTIVITY
3
4
5
7
10
11
EU FETCHES THE FIRST TWO BYTES FROM THE QUEUE (THE MUL INSTRUCTION) AND
COMPLETES INSTRUCTION EXECUTION IN 70 TO 77 CLOCK. CYCLES.
AS A RESULT OF THE JMP
INSTRUCTION, THE EU
REINITIALIZES THE QUEUE
DURING EXECUTION OF
THE JUMP.
61U
ACTIVITY
SINCE THE QUEUE 15
EMPTY, THE BIU FETCHES
TWO OBJECT CODE BYTES
(THE MUL INSTRUCTION) IN
ONE BUS CYCLE AND
COMPLETES A seCOND
BUS CYCLE. THE QUEUE
CONTAINS FOUR BYTES.
BIU FETCHES TWO OBJECT
CODE BYTES. QUEUE
AGAIN CONTAINS FOUR
BYTES.
I
BIU FETCHES TWO MORE
OBJECT CODE BYTES.
QUEUE IS NOW FULL lSI X
81U IS IDLE FO'R 62-69 CLOCK CYCLES
WHILE THE EU COMPLETES EXECUTION OF
THE MUL INSTRUCTION.
BYTES).
Figure 4-6.BIUIdle States
4-5
EU FETCHES THE NEXT
OBJECT CODE BYTES
FROM THE QUEUE AND
BEGINS EXECUTING THE
NEXT INSTRUCTION.
BIU FETCHES TWO OBJECT
CODE BYTES TO REFILL
THE QUEUE. THE QUEUE IS
AGAIN FULL.
HARDWARE REFERENCE INFORMATION
(figure 4-S). At this time, bus cycle status is
available on the address/status lines. During state
T 3, bus cycle status is maintained on the
address/status lines and either the write data is
maintained or read data is sampled on the lower
16 address/data lines. The bus cycle is terminated
in state T 4 (control lines are disabled and the
addressed device deselects from the bus).
In addition to the idle state previously described,
both theSOS6 and SOSS CPUs include a
mechanism for .inserting additional T -states in the
bus cycle to compensate for devices (memory Or
110) that cannot transfer data at the maximum
rate. These extra T -states are called wait states
(TW) and, when required, are inserted between
states T 3 and T 4, During a wait state,the data on
the bus remains unchanged. When the device can
complete the transfer (present or accept the data),
it signals the CPU to exit the wait state and to
enter state T 4,
The SOSS CPU, like the S086, places a 20-bit
address on the multiplexed address/data bus during state T 1 as shown in figures 4-9 and 4-10.
Unlike the SOS6, the SOSS maintains the address
on the address lines (A 15-AS) for the entire bus
cycle. During state T2' the CPU removes the
address on the address/data lines (ADrADo) and
either floats these lines in preparation for a read
cycle (figure 4.-9) or places write data on these
lines (figure 4-10). Atthis time, bus cycle status is
available on the address/status lines. During.state
T 3, bus cycle status is maintained on .the
address/status lines and either write data is maintained or. read data is sampled on the
address/data lines. The bus cycle is terminated in
state T 4 (control lines are disabled and the
addressed device deselects from the bus).
As shown in .the following timing diagrams, the
actual bus cycle timing differs between a read and
a write .bus cycle and varies between. the two
CPUs. Note that the timing diagrams illustrated
are for the minimum mode. (Maximum mode
timing is described later in this chapter.)
Referring to figures 4-7 and 4-S, the SOS6 CPU
places a 20-bit address on the multiplexed
address/ data bus during state T l' During state
T2' the CPU removes the address from the bus
and either three-states (floats) the lower 16
address/data lines in preparation for a read cycle
(figure 4-7) or places write data on these lines
I---------oNE BUSCYClE--------!
ClK
A19/SS-A16/Sa
ANDIIil!/S7
~
~
ADDRESS, BHE OUT
AD15-ADO
-----«
ADDRESS OUT
ALE
/
X
~TATUS OUT
}-
. '. - -_ _ _ _....;..._ _ _ _ _--'.
)~----('__~DA~TA~IN~__J)r----
\'---_ _ _ _ _--JI
L
MliO
~'--_ _ _ _ _lO_W_=_'/O_R_EA_D_,H_'G_H=_M_E_MO_R_YR_E_AD_ _ _ _ _ _
DT/.
---,
___
\\-----------'/
,-..,-
\
~'
DEN - - - -
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-L'I __. _
-j..-------'---.....\
____ I
Figure 4-7. S086 Read Bus Cycle
4-6
jr---'-""",...\-\ __
---J.
1...._ _ _ _ _ _ _
HARDWARE REFERENCE INFORMATION
elK
A19/SS-A16/S3
~
ANOBlffi/S7
~
AD15-ADO
~
ALE
M/iO
/
_---1
ADDRESS, BHE OUT
ADDRESS OUT
X
.
STATUS OUT
---J
1 . . . . ._ _ _ _ _ _ _ _ _ _ _
X'-_____
DA_J_AO_U_T_ _ _ _- - - J
\~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J
~'--_ _ _ _ _"_OW_=_'_/O_W_R'_TE_."_'G_"_=M_E_M_OR_V_W_R'_TE_ _ _ _ __
\ \ -_ _ _ _ _ _ _ _ _ _ _- 1
DTIR
----7'---------------------,
___ J
I
DEN - - - - - - . , ' - - - - - - - \
____
~
---J
1 . . . . ._ _ _ _ _ _ _ _ _ _ _ _ _
Figure 4-8.8086 Write Bus Cycle
A majority of system memories and peripherals
require a stable address for the duration of the
bus cycle (certain MCS-85™ components can
operate with a multiplexed address/data bus).
During state T 1 of every bus cycle, the ALE
(Address Latch Enable) control signal is output
(either directly from the microprocessor in the
minimum mode or indirectly through an 8288 Bus
Controller in the maximum mode) to permit the
address to be latched (the .address is valid on the
trailing-edge of ALE). This "demultiplexing" of
the address/data bus can be done remotely at
each device in the system or locally at the CPU
and distributed throughout the system as a
separate address bus. For optimum system performance and for compatibility with multiprocessor systems or' with the Intel Multibus
architecture, the locally-demultiplexed address
bus is recommended. To latch the address, Intel ®
8282 (non-inverting) or 8283 (inverting) Octal
Latches are offered as part of the 8086 product
family and are implemented as shown in figure
4-11. These circuits, in addition to providing the
desired latch function, provide increased current
drive capability and capacitive load immunity.
The data bus cannot be demultiplexed due to the
timing differences between read and write cycles
and the various read response times among
peripherals and memories. Consequently, the
multiplexed data bus either can be buffered or
used directly. When memory and 110 peripherals
are connected directly to an unbuffered bus, it is
essential that during a read cycle, a device is
prevented from corrupting the address present on
the bus during state T l' To ensure that the
address is not corrupted, a device's output drivers
should be enabled by an output enable function
(rather than the device's chip select function) controlled by the CPU's read signal. (The MCS-86
family processors guarantee that the read signal
will not be valid until after the address has been
latched by ALE.) Many Intel peripheral,
ROM/EPROM, and RAM circuits provide an
output enable function to allow interface to an
unbuffered multiplexed address/data bus. The
alternative of using a buffered data bus should be
considered since it simplifies the interfacing
requirements and offers both increased drive current capability and ca.pacitive load immunity. The
Intel® 8286 (non-inverting) and 8287 (inverting)
4-7
HARDWARE REFERENCE INFORMATION
1 - - - - - - - - - - ONE BUS CYCLE - - - - - - - - - - 1
ClK
A19/S6~A161S3 ~
A15-Aa
~
. . . .----------I~
X
STATUS OUT
~
AD7-ADO
)-
ADDRESS OUT
ADDRESS OUT
DATA IN
\. . . .________~----~r-
I
ALE
-----'
'Mil
ADDRESS OUT
C
~'--_ _ _ _ _ _lO_W_=_M_E_M_O_RY_R_E_A_D,_H_'G_H_=_"O_RE_A_D_ _ _ _ _ _ _ _
---------',
\.......
---,
,---
DTIA ____....
'' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......
/ ___ _
. .________. . .,r---""TL~=
1mT =~~~-JT/-------------;\
Figure 4-9.8088 Read Bus Cycle
I - - - - - - - - - - O N E BUS C Y C l E - - - - - - - - - - _
T2
T3
T4
ClK
X~
A'S·A8
S_T_M_U_S_OU_T_ _ _ _
~~r-----
~'-._ _ _ _ _ _ _ _ _A_DD_R_ES_S_O_U_T_ _.,.-_ _ _ _ _~r_____
AD7-AD~ ~
I
ALE
-----'
'OIM
_____
ADDRESS OUT
X
...______D-'AT_A_O_U_T_ _~_ _
___'r_____
\'--_____-----'r---'C
.~......_ _ _ _ _ _l_OW_=_ME_M_O_RY_W_R'_TE_,H_'_GH_=_'_'O_W_R_'T_E_ _ _ _ _ _
\'-------',
~,--..,..------,.,.----------------_,ir,--~~
___
I
,
~L
1mT - - - - ' / - - - - - - ' \
_ _ _ _ oJ
,-
\-.._ _ _ _ _- - ' ,
Figure 4-10.8088 Write Bus Cycle
4-8
__ -'
HARDWARE REFERENCE INFORMATION
Octal Bus Transceivers, shown in figure 4-12, are
expressly designed to buffer the data bus. These
transceivers use the CPU's DEN (Data Enable)
and DT lir (Data Transmit/Receive) control
signals to enable and control the direction of data
on the bus. These signals provide the proper timing relationship to guarantee isolation of the
address that is present on the multiplexed bus
during state T l'
ro11
8284
RES
CLOCK
GENERATOR
Except where noted, all subsequent discussions
and examples in this chapter assume a locally
demultiplexed address bus and a buffered data
bus. The resultant address and data buses from
the address latches and data transceivers to the
memory and I/O devices will be referred to collectively as the "system" bus.
VCC
1
MN/MX
~
ClK
~
READY
r---
RESET
Rii
WR
101M
8088
CPU
ALE
ST.
ADDRESS
A19-A16
ADDRESS
A15-Aa
... ADDRESS/DATA
A07- ADo
ADDRESS BUS
.
8282
8283
(20R 3)
~
~
!J,. !
OR
OE
!!
SEL ROWR
MEMORY
110 PERIPHERAL
DATA
DATA
X
X
-i-
Figure 4-11. Minimum Mode 8088 Demultiplexed Address Bus
roIi
VCC
>--+
1
m
8284
CLOCK
GENERATOR
VCC
l
MN/Ml1
I-I--
ClK
f----
RESET
READY
Rii
iVA
MfiO
8086
CPU
ALE
ADDRESS
A19-A16
BilE
AD15-ADO
DEN
"'/ii
.
BilE
ST.
I
"
"
OR
8283
... ADDRESS/DATA ..
.,
ADDRESS BUS
8282
m;
!
jj
jjj
Ito"
110 PERIPHERAL
MEMORY
DATA
~
8286
T
.......
OR
I
DATA
DATA BUS
8287
OE
Figure 4-12. Minimum Mode 8086 Buffered Data Bus
4-9
1
HARDWARE REFERENCE INFORMATION
The insertion of wait states in the CPU's bus cycle
is accomplished by deactivating one of the 8284's
RDY inputs (RDYI or RDY2). Either of these
inputs, when enabled by its corresponding AEN 1
or AEN2 input, can be deactivated directly by a
peripheral device when it must extend the CPU's
bus cycle (when it is not ready to present or accept
data) or by a· "wait state generator" circuit (a
logic circuit that holds the RDY input inactive for
a given number of clock cycles).
Clock Circuit
To establish the bus cycle time, the CPU requires
an external clock signal. As an integral part of the
8086 family,. Intel offers· the 8284 Clock
Generator/Driver for this purpose. In addition to
providing the primary (system) clock signal, this
device provides both the hardware reset interface
and the mechanism for the insertion of wait states
in the bus cycle.
The clock generator/driver requires an external
series-resonant crystal input (or external frequency source) at three times the required system clock
frequency (Le., to operate the CPU at 5 MHz, a
15 MHz fundamental frequency source is
required). The divided-by-three output (CLK)
from the 8284 is routed directly to the CPU's
CLK input. Thedock generator/driver provides a
second clock output called PCLK (Peripheral
Clock) at one half the frequency of the CLK output and a buffered TTL level OSC (oscillator)
output at the applied crystal input frequency.
These outputs are available for use by. system
devices.
The READY output, which is synchronized to the
CLK signal is coupled directly to the CPU's
READY input. As shown in figure 4-13, when the
addressed. device needs to insert one or more wait
states in a bus cycle, it deactivates the 8284's RDY
input prior to the end of state T2 which causes the
READY output to be deactivated at the end of
stateT2. Theresultant wait state (TW) is inserted
between states T 3 and T 4. To exit the wait state,
the device activates the 8284's RDY input which
causes the READY input to the CPU to go active
at the end of the current wait state and allows the
CPU to enter state T 4.
The 8284's hardware reset function is accomplished with an internal Schmitt trigger circuit
that is activated by the RES (Reset) input. When
this input is pulled low (i.e., a contact closure to
ground), the RESET output is activated synchronously with the CLK signal. This signafmust
be active for four clock cycles and causes the CPU
to fetch and execute the instruction at location
FFFFOH. An external RC circuit is connected to
the RES input to provide the power-on reset function (on power-on, the RES input mustbe active
for 50 microseconds). The RESET output is
coupled directly to the RESET input of the CPU
as well as being available to system peripherals as
the system reset signaL
Minimum/Maximum Mode
A unique feature of the 8086 and 8088 CPUs is
the ability of a user to define a subset of the
CPU's controisignal outputs in order to tailor the
CPU to its intended system environment. This
"system tailoring" is accoI!!lWshed by the strapping of the CPU's MN/MX(minimum/maximum) input pin. Table 4-1 defines the 8086 and
8088 pin assignments in both the minimum and
maximum modes.
elK
""""""==
ROY INPUT _ _ _ _ _
~
iii
READY OUTPUT _ _ _ _ _ _ _. ,
\I....-_ _---J!
Figure 4-13. Wait State Timing
4-10
HARDWARE REFERENCE INFORMATION
Table 4-1. Minimum/Maximum Mode Pin Assignments
8088
8086
Mode
Mode
Pin
Pin
31
30
29
28
27
26
25
24
Minimum
Maximum
HOLD
HLDA
RQ/GTO
RQ/GT1
WR
LOCK
MilO
S2
S1
SO
QSO
QS1
DT/R
DEN
ALE
INTA
Minimum
Maximum
HOLD
HLDA
RQ/GTO
RQ/G'fi
LOCK
S2
S1
SO
QSO
aS1
High State
31
30
29
28
27
26
25
24
34
WR
101M
DTiA"
DEN
ALE
INTA
SSO
8-bit device, compatibility with existing
MCS-85™ systems and specific MCS-85™ family
devices (e.g., the Intel® 8155156).
Minimum Mode
In the minimum mode (MN/MX pin strapped to
+5V), the CPU supports small, single-processor
systems that consist of a few devices and that use
the system bus rather than support the
Multibus™ architecture. In the minimum mode,
the CPU itse!.L.Aenerates all bus cQ.!!!rol
signals (DT/R, DEN, ALE and. either MilO or
101M) and the command output signal (RD, WR
or INT A), and provides a mechanism for
requesting bus access (HOLD/HLDA) that is
compatible with bus master type controllers (e.g.,
the Intel® 8237 and 8257 DMA Controllers).
Maximum Mode
In the maximum mode (MN/MX pin strapped to
ground), an Intel® 8288 Bus Controller is added
to provide a sophisticated bus control function
and compatibility with the Multibus architecture
(combining an Intel® 8289 Arbiter with the 8288
permits the CPU to support multiple processors
on the system bus). As shown in figure 4-15, the
bus controller, rather than the CPU, provides all
bus control and command outputs, and allows the
pins previously delegated to these functions to be
redefined to support multiprocessing functions.
In the. minimum mode, when a bus master
requires bus access, it activates the HOLD input
to the CPU (through its request logic). The CPU,
in response to the "hold" request, activates
HLDA as an acknowledgement to the bus master
requesting the bus and simultaneously floats the
system bus and control lines. Since a bus request
is asynchronous, the CPU samples the HOLD
input on the positive transition of each CLK
signal and, as shown in figure 4-14, activates
HLDA at the end of either the current bus cycle
. (if a bus cycle is in progress) or idle clock period.
The hold state is maintained until the bus master
inactivates the HOLD input at which time the
CPU regains control of the system bus. Note that
during a "hold" state, the CPU will continue to
execute instructions until a bus cycle is required.
S2, S1 and SO
Referrin&..!o.l!gure 4-15, the 8288 Bus Controller
uses the S2, SI and SO status bit outputs from the
CPU (and the 8089 lOP) to generate all bus. control and command output signals required for a
bus cycle. The status bit outputs are decoded as
outlined in table 4-2. (For a detailed description
of the operation of the 8288 Bus Controller, refer
to the associated data sheet in Appendix B.)
The 8088 CPU, in the minimum mode, provides
an SSO status output. This output is equivalent to
SO in the maximum mode and can be decoded
with DT IR: and 101M (inverted), which are
equivalent to Si and' S2 respectively, to provide
the same CPU cycle status information defiried in
table 4-2. This type of decoding could be used in a
minimum mode 8088-based system to allow
dynamic RAM refresh during passive CPU cycles.
Note that in the minimum mode, the I/O-memory
control line for the 8088 CPU is the converse of
the corresponding control line for the 8086 CPU
(MilO on the 8086 and 101M on the 8088). This
was done to provide the 8088 CPU, since it is an
4-11
HARDWARE REFERENCE INFORMATION
\
Figure 4-14. HOLD/HLDA Timing
VCC
8288
ClK BUS
CONTROLLER
I-------.~ So
1--------.·1 §j
11m(
~----'----------
~~----~------------~~--------~~-------------
1--':-----...152
DEN
____----~4--------4--.--
~~_------~4--------.--
DT/I'i
~~--
ALE
STB
8282
OR
8283
MEMORY
110 PERIPHERAL
Figure 4-15. Elementary Maximum Mode System
Table 4-2. Status Bit Decoding
Status Inputs
S2
I
. 0 ..
S1
SO
0
0
1
0
1
.0
0
,0
0
1
0
0
.1
1
1
1
1
.1
1
I
CPU Cycle
-:
0
1
0
.1
Interrupt Acknowledge
Read 1/0 Port
.
Write 1/0 Port
Halt
Instruction Fetch
Read Memory
. lNrite Memory
Passive
4-12
8288 Command
INTA
10RC ...
10WC,AIOWC
None
MRDC
MRDC
MWTC,AMWC
None
HARDWARE REFERENCE INFORMATION
RQ/GT1, RQ/GTO
The Request/Grant signal lines (RQ/GTO and
RQ/GTl) provide the CPU's bus access
mechanism in the maximum mode (replacing the
HOLD/HLDA function available in the
minimum mode) and are designed expressly for
multiprocessor applications using the 8089 I/O
Processor in its local mode or other processors
that can support this function. These lines are
unique in that the request/grant function is
accomplished over a single line (RQ/GTO
or RQ/GTl) rather than the two-line
HOLD/HLDA function.
As shown in figure 4-16, the request/grant
sequence is a three-phase cycle: request, grant and
release. The sequence is initiated by another processor on the system .bus when it outputs a pulse
on one of the RQ/GT lines to request bus access
.(request phase). In response, the CPU outputs a
pulse (on the same line) at the end of either the
current bus cycle (if a bus cycle is in progress) or
idle clock period to indicate to the requesting processor that it has floated the system bus and that it
will logically disconnect. from the bus controller
on the next clock cycle (grant phase) and enter a
I
T4 OR TI
"hold" state. Note that the CPU's execution unit
(EU) continues to execute the instructions in. the
queue until an instruction requiring bus access is
encountered .or until the queue is empty. In, the
third (release) phase, the request~ processor
again outputs a pulse on the RQ/GT line. This
pulse alerts the CPU that the processor is ready to
release the bus. The CPU regains bus access on its
next clock cycle. Note that the exchange of pulses
is synchronized and, accordingly, both the CPU
and requesting processor must be referenced to
the same clock signal.
The request/grant lines are prioritized with
RQ/GTO taking precedence over RQ/GTl. If, a
request arrives--2!l both lines simultaneously, the
processor on RQ/GTO is granted the bus (the
request on RQ/GTl is granted when the bus. is
released by the first processor following'!..2,ne.-2!:,
two clock channel transfer delay). Both. RQ/GT
lines (and the HOLD line in minimum mode) have
a higher priority than a.pending interrupt.
Request/grant latency (the time interval between
the receipt of a request pulse and the return of a
grant pulse) for several conditions is given in table
4-3.
I
JLl\L
ClK
RQIGr
5-\
COPROCESSOR REQUESTS
BUS ACCESS
CPU GRANTS BUS
TO COPROCESSOR
(
r
COPROCESSOR RELEASES
BUS
Figure 4-16. RequestiGrantTiming
Table 4-3. Request/Grant Latency
Operating Condition
Normal Instruction Processing-LOCK inactive
INTA Cycle Executing-LOCK active
. Locked XCHGlnstruction Processing-:-LOCK active
Request/Grant Delay
8086
8088
3-6(10*) clock.s
3-10 clocks
15clocks
15 clocks
24-31 (39*) clocks
24-39 clocks
~The number of clocks in parentheses applies when the instruction being .executed.references a word
operand at an odd address boundary.
HARDWARE REFERENCE INFORMATION
sion processing by a coprocessor. (The
corresponding Intel ICE modules use these status
bits during "trace" operations.) The encoding of
the QSI and QSO bits is shown in table 4-4.
Latency during normal instruction processing
(LOCK inactive) can be as short as three clock
cycles (e.g., during execution of an instruction
that does not reference memory) and no· more
than ten clock cycles. Whenever the LOCK output is active (LOCK is activated during an interrupt acknowledge cycle or during execution of an
instruction with a Lock prefix), latency is
increased. In the case of the execution of a locked
XCHG instruction (used during· semaphore
examination), maximum latency is limited to 39
clock cycles. Greater latencies occur when a
"long" instruction is locked. This, however, is
neither necessary nor recommended.
Table 4~4. Queue Status Bit Decoding
At the end of processor activity, the 8086 or
8088 will not redirve its control and data buses
until two clock cycles following receipt of the
release pulse (or two clock cycles after HOLD
goes inactive in the minimum mode).
QS1
QSO
Queue Status
o(low)
0
No Operation. During the last
clock cycle, nothing was taken
from the queue.
0
1
First Byte. The byte taken from the
queue was the first byte of the
instruction.
1 (high)
0
Queue Empty. The queue has
been reinitializedas a result of the
execution of a transfer instruction.
.1
1
Subsequent Byte. The byte taken
from the queue was a subsequent
byte of the instruction.
A Hold request is honored immediately following
CPU reset if the HOLD line is active when the
RESET line goes inactive. This action facilitates
the downloading of programs and, more
specificallY, the setting of memory location
FFFFOH prior to CPU activation. Note that the
same result can be effected in the maximum mode
through the RQ/GT line by generating the request
pulse in the first or second clock cycle after
RESET goes inactive.
The queue status is valid during the clock cycle
after the indicated activity has occurred.
LOCK
External Memory Addressing
The LOCK output is used in conjunction with an
Intel 8289® Bus Arbiter .to guarantee exclusive
access of a shared system bus for the duration of
an instruction. This output is software controlled
and is effected by preceding the instruction
requiring exclusive access with a one byte "lock"
prefix (see instruction set description in Chapter
The 8086 and 8088 CPUs have a 20-bit address
bus and are capable of accessing one megabyte of
memory address space.
The 8086 memory address space consists of a
sequence of up to one million individual bytes in
which any two consecutive bytes can be accessed
as a 16-bit data word. As shown in figure 4-17,
the memory address space is physically divided
into two banks of up to 512k bytes each.
2).
When the lock prefix is decoded by the EU, the
EU informs the BIU to activate the LOCK output
during the next clock cycle. This signal remains
active until one clock cycle after the executi6n of
the associated instruction is concluded.
One bank is associated with the lower half of the
CPU'sI6-bit data bus (data bits D7-DO),and the
other bank is associated with the upper half of the
data bus (data bits DI5-D8). Address bits A19
through Al are used to simultaneously address a
specific byte location in both the upper and lower
banks, and the AO address bit is not used in
memory addressing. Instead, AO is used in
memory bank selection. The lower bank, which
QS1, QSO
The QSI and QSO (Queue Status) outputs permit
external monitoring of the CPU's internal
instruction queue to allow instruction set exten4-14
HARDWARE REFERENCE INFORMATION
order byte is in the lower bank), the word is said
to be "aligned" and can be accessed in a single
operation (a single bus cycle). As with the byte
transfers previously described, address bits Al9
through Al address both banks, except that now
BHE is active (selecting the upper bank) and AO is
inactive (selecting the lower bank) to access both
bytes.
ADDRESS BUS
AO
iiHE
1
... ,..
+ AO-A18
SEL
SEL
UPPER
(ODD)
BANK
512K x 8
LOWER
(EVEN)
BANK
512K x 8
00-07
00-07
!
,..
When the low-order byte of the word to be
accessed is on an odd address boundary (when the
low-order byte is in the upper bank), the word is
"not aligned" and must be accessed in two bus
cycles. During the first cycle; the low-order byte
of the word is transferred to or from the upper
bank as described for a byte access at an odd
address (AO and BHE active). The memory
address is then incremented, which causes AO to
shift to an inactive level (selecting the lower
bank), and a byte access at an even address is performed during the next bus cycle to transfer the
word's high-order byte to or from the lower bank.
The above sequence is initiated automatically by
the 8086 whenever, a word access at an odd
address is performed. Also, the directing of .the
high- and low-order bytes of the 8086's internal
word registers to the appropriate halves of the
data bus is performed automatically and, except
for the additional four clock cycles required to
execute the second bus cycle, the entire operation
is transparent to the program.
T
--*;..-~
015-08 ----.i!u=!P!"!PE!!''R"!'!H"!'!AL"'!'F"'!'O"!"FO!"!A;"'!'TA""!B!"!U"!"S
0 7- 0 0
...
AO-A18
----""!L"'!'OW!!!E!!!R~H"'!'AL!"'!F!"'!O'!!'F'!!'OA;!'!!TA'!"'!!'!'BU!!"S-....;;~--·~§
Figure 4-17. 8086 Memory Interface
contains even-address bytes, is selected when
AO=O. The upper bank, containing odd address
bytes (AO=I), is selected by a separate signal, Bus
High Enable (BHE). Table 4-5 defines the
BHE-AO bank selection mechanism.
Table 4-5. Memory Bank Selection
BHE
AO
Byte Transferred
Both bytes
Upper byte to/from odd address
Lower byte to/from even address
None
o(low)
0
0
1
1 (high)
1
0
1
The 8088 memory address space is logically
organized as a linear array of up to one million
bytes. Since the 8088 uses an 8-bit-wide data bus,
memory consists of a single bank. Address bit AO
is used to address memory, and a BHE signal is
not provided.
When accessing a data byte at an even address,
the byte is transferred to or from the lower bank
on the lower half of the data bus (D7-DO). In this
case, the inactive level of the AO address bit
enables the addressed byte in the lower bank, and
the inactive level of the BHE signal disables the
addressed byte in the. upper bank. Conversely,
when performing a byte access at an odd address,
the data byte is transferred to or from the upper
bank on the upper half of the data bus (DI5-D8).
The active level of the BHE signal enables the
upper bank; and the active level of the AO address
bit disables the lower bank.
Word (16-bit) operands can be located at odd- or
even-address boundaries. The low-order byte of
the word is stored in the lower-valued address
location, and the high-order byte is stored in the
next, higher-valued address location. The 8088
automatically executes two bus cycles when
accessing word operands.
As indicated in table 4-5, the 8086 can access a
byte in both the' upper and lower banks
simultaneously as a 16-bit word. When the loworder byte of the word to be accessed is on an
even address boundary (that is, when the low-
The 8086 and 8088 CPUs support both 1/0
mapped 110 and memory mapped 110. 110
mapped 1/0 permits an 110 device to reside ina
separate address space (first 64k of address
space), and the standard 110 instruction set is
I/O Interfacing
4-15
HARDWARE REFERENCE INFORMATION
available for device communications.
mapped 110 permits an 110 device
anywhere in memory and allows the
CPU instruction set to be used
operations.
When the 110 and memory address spaces
overlap, device selection is determined by the
appropriate read/write command set.
Memory
to reside
complete
for 110
Interrupts
The 8086 supports both 8-bit and 16-bit 110
devices. An 8-bit 110 device may be associated
with either the upper or lower half of the data
bus. (Assigning an equal number of devices to
each half of the data bus distributes bus loading.)
When an 110 device is assigned to the lower half
of the bus (D7-DO), all I/O addresses must be
even (AO equal "0"), and when an 110 device is
assigned to the upper half of the bus, all 110
addresses must be odd (AO equal" 1"). Note that
since AO always will be either a "1" or a "0" for
a specific device, it cannot be used as an address
input to select registers within the 110 device.
When an 110 device on the upper half of the bus
and an 110 device on the lower half of the bus are
assigned addresses that differ only by the state of
AO (adjacent odd and even addresses), AO and
BHE both must be conditions of device selection
to 'prevent a write operation to one device from
overwriting data in the other device.
CPU interrupts can be software or hardware
initiated. Software interrupts originate directly
from program execution (i.e., execution of a
breakpointed instruction) or indirectly through
program logic (Le., attempting to divide by zero).
Hardware interrupts originate from external logic
and are classified as either non-maskable or
maskable. All interrupts, whether software or
hardware initiated, result in the transfer of control to a new program location. A 256-entry vector table, which contains address pointers to the
interrupt routines, resides in absolute locations 0
. through 3FFH. Each entry in this table consists of
two 16-bit address values (four bytes) that are
loaded into the code segment (CS) and the
instruction pointer (lP) registers as the interrupt
routine address when an interrupt is accepted.
Figure 4-18 illustrates the organization of the 256entry vector table.
Memory
Address
To permit data transfers to 16-bit I/O devices to
be performed in a single bus cycle, the device is
assigned an even address. To ensure that the 110
device is selected only for word transfers, AO and
BHE both must be conditions of device selection.
Table
Entry
::: I----~-:-::-:----II}
Vector
Definition
Vector 255,.
I
82
The 8088, since its data bus is eight bits wide, is
designed to support 8-bit 110 devices and places
no restrictions on odd or even addresses.
When the 8086 or the 8088 is operated in the
minimum mode, the CPU's read and write commands (RD and WR) are common for memory
and 110 devices. If the memory and 110 address
spaces overlap, device selection must be. qualified
by M/IO (8086) or 10/M (8088) to determine if
the device is memory or 110. This restriction does
not apply to systems in which 110 and memory
addresses do not overlap or to systems that use
memory-mapped 110 exclusively. In the maximum mode, the CPU generates (through the bus
controller) separate memory read/write an~U/O
read/write commands in place of the MilO or
10/M signal. In a maximum mode system, an 110
device is assigned to an 110 address or to a
memory address (memory mapped 110) by connecting either the memory or 110 read/write command lines to the device's command inputs.
I
User Available
I
Reserved
eS32
80
IP32
7E
eS31
7e
IP31
16
ess
14
IPS
12
eS4
10
IP4
DE
eS3
Oe
IP3
OA
eS2
08
IP2
06
eS1
04
IP1
02
CS Value - Vector 0 (CS 0)
00
IP Value - Vector 0 (IP 0)
r Vector 5
r Vector 4 -
Overflow
I'
r Vector 3 -
Breakpoint
-<
r Vector 2 -
NMI
~
r Vector 1 -
Slngle·Step
I~
r Vector 0 -
Divide Error
1 - 2 Bytes_I
Figure 4-18. Interrupt Vector Table
4-16
HARDWARE REFERENCE INFORMATION
The CPU provides a single interrupt request input
(INTR) that can be software masked by clearing
the interrupt enable bit in the flags register
through the execution of a CLI instruction. The
INTR input is level triggered and is synchronized
internally to the positive transition of the CLK
signal. In order to be accepted before the next
instruction, INTR must be active during the clock
period preceding the end of the current instruction (and the interrupt enable bit must be set).
As shown in figure 4-18, the first five interrupt
vectors are associated with the software-initiated
interrupts and the hardware non-maskable interrupt (NMI). The next 27 interrupt vectors are
reserved by Intel and should not be used if compatibility with future Intel products is to be maintained. The remaining interrupt vectors (vectors
32 thorugh 255) are available for user interrupt
routines.
The non-mask able interrupt (NMI) occurs as a
result of a positive transition at the CPU's NMI
input pin. This input is asynchronous and, in
order to ensure that it is recognized, is required to
have a minimum duration of two clock cycles.
NMI is typically used with power fail circuitry,
.error correcting memory or bus parity detection
logic to allow fast response to these fault conditions. When NMI is activated, control is transferred to the interrupt service routine pointed to
by vector 2 following execution of the current
instruction. When a non-maskable interrupt is
acknowledged, the current contents. of the flags
register are pushed onto the stack (the stack
pointer is decremented by two), the interrupt
enable and trap bits in. the flags register are
cleared (disabling maskable and single-step interrupts), and the vector 2 CS and IP address
pointers are loaded into the CS and IP registers as
the interrupt service routine address.
As shown in figure 4~19, when a maskable interrupt is acknowledged, the CPU executes two
interrupt acknowledge bus cycles ..
During the first bus cycle, the CPU floats the
address/ data bus and activates the INT A (Interrupt Acknowledge) command output during
states T 2 through T 4' In the minim urn mode, the
CPU will not recognize a hold request from
another bus master until the full interrupt
acknowledge sequence is completed. In the maximum mode, the CPU activates the LOCK output
from state T2 of the first bus cycle until stateT2
of the second bus cycle to signal all 8289 Bus
Arbiters in the system that the bus should not be
accessed by any other processor. During the
second bus cycle, the CPU again activates its
INT A command output. In response to the
CLK
n
ALEJ\
'LOCK
INTA
AD7-ADO
r
I
\
\,--_.,...---.<1
\'--_ _--11
---------------------~( VECTOR TYPE )>----
'MAXIMUM MODE ONLY
"SEVERAL (3 TYPICAL) IDLE CLOCK STATES OCCUR BETWEEN THE FIRST AND SECOND
INTERRUPT ACKNOWLEDGE BUS CYCLES IN THE 8086 CPU (DURING THIS INTERVAL THE
BUS IS DRIVEN). INTERRUPT ACKNOWLEDGE BUS CYCLES OCCUR BACK·TO·BACK IN
THE 8088 CPU.
Figure 4-19. Interrupt Acknowledge Sequence
4-17
Mnemonics © Intel, 1978
HARDWARE REFERENCE INFORMATION
second INTA, the external interrupt system (e.g.,
an Intel® 8259A Programmable Interrupt Controller) places a byte on the data bus that identifies the source of the interrupt (the vector
number or Vector "type"). This byte is read by
the CPU and then multiplied by four with the
resultant value used as a pointer into the interrupt
vector table. Before calling the corresponding
interrupt routine, the CPU saves the machine
status by pushing the current contents of the flags
register onto the stack. The CPU then clears the
interrupt enable and trap bits in the flags register
to prevent subsequent maskable and single-step
interrupts, and establishes the interrupt routine
return linkage by pushing the current CS and IP
register contents onto the stack before loading the
new CSand IP register values from the vector
table.
The four classes of interrupts are prioritized with
software-initiated interrupts having the highest
priority and with maskable and single-step interrupts sharing the lowest priority (see section 2.6).
Since the CPU disables maskable and single-step
. interrupts when acknowledging any interrupt, if
recognition of mask able interrupts or single-step
operation is required as part of the interrupt
routine, the routine first must set these bits.
The processing times for the various classes of
interrupts are given in table 4-6. (These times also
are included with the 8086/8088 instruction times
cited in section 2.7.)
Table 4-6. Interrupt Processing Time
Interrupt Class
Processing Time
External Maskable Interrupt
(lNTR)
61 clocks
Non-Maskable Interrupt (NMI)
50 clocks
INT (with vector)
INTType3
INTO
51 clocks
52 clocks
53 clocks
Single Step
50 clocks
Note that the times shown in table 4-6 represent
only the time required to process the interrupt
request after it has been recognized. To determine
interrupt latency (the time interval between the
posting of the interrupt request and the execution
of "useful" instructions within the interrupt
Mnemonics © Intel, 1978
routine), additional time must be included for the
completion on an instruction being executed when
the interrupt is posted (interrupts are generally
processed only at instruction boundaries), for
saving the contents of any additional registers
prior to interrupt processing (interrupts
automatically save only CS,IP and Flags) and for
any wait states that may be incurred during interrupt processing.
Machine Instruction Encoding and
Decoding
Writing a MOV instruction in ASM-86 in the
form:
MOV destination, source
will cause the assembler to generate 1 of 28 possible forms of the MOV machine instruction. A
programmer rarely needs to know the details of
machine instruction formats or encoding. An
exception may occur during debugging when it
may be necessary to monitor instructions fetched
on the bus, read unformatted memory dumps,
etc. This section provides the information
necessary to translate or decode an 8086 or 8088
machine instruction.
To pack instructions into memory as densely as
possible, the 8086 and 8088 CPUs utilize an efficient coding technique. Machine instructions vary
from one to six bytes in length. One-byte instructions, which generally operate on single registers
or flags, are simple to identify. The keys to
decoding longer instructions are in the first two
bytes. The format of these bytes can vary, but
most instructions follow the format shown in
figure 4-20.
The first six bits of a multibyte instruction
generally contain an opcode that identifies the
basic instruction type: ADD, XOR, etc. The
following bit, called the 0 field, generally
specifies the "direction" of the operation: 1 = the
REG field in the second byte identifies the
destination operand, 0 = the REG. field identifies
the source operand. The W field distinguishes
between byte and word operations: 0 = byte, 1 =
word.
One of three additional single-bit fields, S, V or
Z, appears in some instruction formats. S is used
in conjunction with W to indicate sign extension
HARDWARE REFERENCE INFORMATION
the zero flag in conditional repeat and loop
instructions. All single-bit field settings are summarized in table 4-7.
of immediate fields in arithmetic instructions. V
distinguishes between single- and variable-bit
shifts and rotates. Z is used as a compare bit with
BYTE 1
II II
OPCODE
BYTE 2
BYTE 3
I II II
ow MOD
REG
BYTE 4
BYTE 5
BYTE 6
------r-----r-----~------l
I
I
I
I
I HIGH DISP/DATA I LOW DATA I HIGH DATA I
I _ _ _ _ _ ...l.I _ _ _ _ _ _ I,_ _ _ _ _ _ I
______
LOW DISP/DATA
R/M
~
~
REGISTER OPERAND/REGISTERS TO USE IN EA CALCULATION
REGISTER OPERAND/EXTENSION OF OPCODE
REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
WORD/BYTE OPERATION
DIRECTION IS TO REGISTER/DIRECTION IS FROM REGISTER
OPERATION (INSTRUCTION) CODE
Figure 4-20. TypicalSOS6/S0SS Machine Instruction Format
Table 4-7. Single-Bit Field Encoding
Field
S
W
D
V
Z
Function
Value
0
1
0
1
0
1
0
1
0
1
No sign extension
Sign extend a-bit immediate data to 16 bits if W=1
Instruction operates on byte data
Instruction operates on word data
Instruction source is specified in REG field
Instruction destination is specified in REG field
Shift/rotate count is one
Shift/rotatecount is specified in CL register
Repeatlloop while zero flag is clear
Repeatlloop while zero flag is set
4-19
HARDWARE REFERENCEJNFORMATION
The second byte of the instruction,usually identifies the instruction's operands. The, MOD
(mode) field indicates whether one of the
operands is in memory or whether both operands
are registers (see table 4-8). The REG (register)
field identifies a register that is one of the instruction operands (see table 4-9). In a number of
instructions, chiefly the immediate-to-memory
variety,' REG is used as an extension of the
opcode to identify the type of operation. The
encoding of the R/M (register/memory) field (see
table 4-10) depends on how the mode field is set.
If MOD = 11 (register-to-register mode), then
R/M identifies· the second register operand. If
MOD selects memory mode, then R/M indicates
how the effective a.ddress of the memory operand
is to be calculated. Effective address calculation
is covered in detail in section 2.8.
Table 4-9. REG (Register) Field Ellcoding
REG \
00
Memory Mode, no displacement
follows*
01
Memory Mode, 8-bit
displacement follows
10
Memory Mode, 16-bit
displacement follows
11
Register Mode (no
displacement)
AL
CL
OL
BL
AH
CH
OH
BH
AX
CX
OX
BX
SP
BP
SI
01
Theremaybe o~eor two displacement bytes; the
language translators generate one byte whenever
possible. The MOD field indicates 'how many
displacement bytes are present. Following Intel
convention, if the <;lisplacement is two bytes, the
most-significant byte is stored second in the
instruction. If the displacement is only a single
byte, the 8086 or 8088automatically sign-extends
this quantity to 16-bits before using the information in further address calculations. Immediate
values always follow any displacement values that
may be present. The second byte of a two-byte
immediate value is the most significant.
Table 4-8. MOD (Mode) Field Encoding'
EXPLANATION
W,=1,
000
001
010
011
100
101
110
111
Bytes 3 through 6 of an instruction are optional
fields that usually contain the displacement value
of a memory operand and/or the actual value of
an immediate constant operand.
CODE
w=o
Table 4-12 lists the instruction encodings for all
8086/8088 instructions. This table can be used to
predict the machine encoding of any ASM-86
instruction. Table 4-13 lists the 8086/8088
machine instructions in order by the binary value
of their first byte. This table can be used to
decode any machine instruction from its binary
representation. Table 4-11 is a key to the
abbreviations used in tables 4-12 and 4-13. Table
4-14 is a more compact instructi()n decoding
guide.
*Except when RIM = 110,then16-bit
displacement follows
Table 4-10. RIM (Register/Memory) Field Encoding
'EFFECTIVE ADDRESS CALCULATION
MOD=11
RIM
W=O
W=1
R/M
000
001
010
011
100
101
110
111
AL
CL
OL
BL
AH
CH
OH
BH
AX
CX
OX
BX
SP
BP
SI
01
000
001
010
011
100
101
110
111
MOD=OO
(BX)+(SI) "
(BX) + (01)
(BP)+(SI)
(BP)+(OI)
(SI)
(01)
OIRECTAOORESS
(BX)
4-20
MOD=01
(BX) + (SI) + 08
(BX) + (01) + 08
(BP) + (SI) + 08
(BP) + (01) + 08
(SI)+08
(01)+08
(BP)+ 08
(BX)+ 08 ,
MOD=1~
(BX)+(SI)+016
(BX) + (01) + 016
(BP) + (SI) + 016
(BP) + (01) + 016
(SI)+016
(01)+016
(BP)+016
(BX)+ 016
HARDWARE REFERENCE INFORMATION
Table 4-11. Key to Machine Instruction Encoding and Decoding
IDENTIFIER
EXPLANATION
MOD
Mode field; described in this chapter.
REG
Register field; described in this chapter.
R/M
Register/Memory field; described in this chapter.
SR
Segment register code: OO;=ES, 01=CS,10=SS, 11 =DS.
W, S, D, V,Z
Single-bit instruction fields; described in this chapter.
DATA-8
8-bit immediate constant.
DATA-SX
8-bit immediate value that is automatically sign-extended to 16-bits
before use.
DATA-LO
Low-order byte of 16-bit immediate constant.
DATA-HI
High-order byte of 16-bit immediate constant.
(DISP-LO)
Low-order byte of optional 8- or 16-bit unsigned displacement; MOD
indicates if present.
(DISP-HI)
High-order byte of optional 16-bit unsigned displacement; MOD
indicates if present.
IP-LO
Low-order byte of new IP value.
IP-HI
High-order byte of new IP value
CS-LO
Low-order byte of new CS value.
CS-HI
High-order byte of new CS value.
IP-INC8
8-bit signed increment to instruction pointer.
IP-INC-LO
Low-order byte of signed 16-bit instruction pointer increment.
IP-INC-HI
High-order byte of signed 16-bit instruction pointer increment.
ADDR-LO
Low-order byte of direct address (offset) of memory operand; EA not
calculated.
ADDR-HI
High-order byte of direct address (offset) of memory operand; EA not
calculated.
Bits may contain any value.
xxx
First 3 bits of ESC opcode.
YYY
Second 3 bits of ESC opcode.
REG8
8-bit general register operand.
REG16
16-bit general register operand.
MEM8
8-bit memory operand (any addressing mode).
MEM16
16-bit memory operand (any addressing mode).
IMMED8
8-bit immediate operand.
IMMED16
16-bit immediate operand.
SEGREG
Segment register operand.
OEST-STR8
Byte string addressed by 01.
4-21
HARDWARE REFERENCE INFORMATION
Table 4-11. Key to Machine Instruction Encoding and Decoding (Cont'd.)
IDENTIFIER
EXPLANATION
SRC-STR8
Byte string addressed by SI.
OEST-STR16
Word string addressed by 01.
SRC-STR16
Word string addressed by SI.
SHORT-LABEL
Label within ±127 bytes of instruction.
NEAR-PROC
Procedure in current code segment.
FAR-PROC
Procedure in another code segment.
NEAR-LABEL
Label in current code segment but farther than -128 to +127 bytes
from instruction.
FAR-LABEL
Label in another code segment.
SOURCE-TABLE
XLAT translation table addressed by BX.
OPCOOE
ESC opcode operand.
SOURCE
ESC register or memory operand.
Table 4-12.8086 Instruction Encoding
DATA TRANSFER
MOV = Move:
765432107654321076543210765432107654321076543210
Register/memory to/from register
1 0 0 0 1 Od w
mod
rim
(DISP-LOI
(DISP-HII
Immediate to register/memory
1 1 0 0 0 1 1 w
mod o 0 0 rim
(DISP-LOI
(DISP-HI)
Immediate to register
1 0 1 1 w reg
data
data If w= 1
Memory to accumulator
1Ql0000w
addr-Io
addr-hl
Accumulator to memory
1010001w
addr-l0
addr-hi
Register/memory to segment register
1 0 0 0 1 1 1 0
mod o SA rim
(DISP-LOI
(DISP-HII
, Segment register to register/memory
10001100
mod o SA rim
(DISP-LOI
(DISP-HII
I
Registerlmemory
11111111
mod 1 1 0 rIm
I
Register
01010reg
Segment register
000reg110
mod 0 0 0 r/f!l
I
PUSH
reg
I
I
I
= Push:
(DISP-LOI
I
(DISP-HII
I
(DISP-LOI
I
(DISP-HII
I
POP = Pop:
Register/memory
1 0 0 0 1 1 1 1
Register
o 1 0 1 1 reg
Segment register
000reg111
Mnemonics © Intel, 1978
4-22
data
I
dataifw'"1
I
HARDWARE REFERENCE INFORMATION
Table 4-12.8086 Instruction Encoding (Cont'd.)
DATA TRANSFER (Conl'd.)
XCHG = Exchange:
76543210
76543210
76543210
76543210
76543210
76543210
Aeglsterfmemory with register
Register with accumulator
IN = Input from:
Fixed port
Variable port
OUT = Output to:
w
Fixed port
1 1 1 0 0 1 1
Variable port
1 1 1 01 1 1 w
XLAT
= Translate byte to AL
11
o1
DATA-S
0 1 11
LEA = Load EA to register
100011
o1
LOS = Load pOinter to OS
mod
reg
rim
(DISP·LD)
(DISP-HI)
110001
o1
mod
reg
rim
(DISP-LD)
(DISP-HI)
Load pOinter to ES
1 1 0 0 0 1
o0
mod
reg
rim
(DISP-LD)
(DISP-HI)
LAHF
= Load AH with flags
1 0 0 1 11 11
SAHF
= Store AH into flags
1 0 0 1 11 1 0
reg
rim
(DISP-LD)
(DISP-HI)
0 0 rim
(DISP-LD)
(DISP-HI)
LES
=
PUSHF
POPF
= Push flags
= Pop flags
1 0 0 11 1 0 0
1
a0
1 1 1 0 1
ARITHMETIC
ADD = Add:
Reg {memory with register to either
OOOOOOdw
mod
Immediate to register/memory
100000sw
mod
Immediate to accumulator
0OOOO10w
ADe
I
data
I
data If s: w=Ql
I
data
I
data If s: w"'Ol
I
= Add with carry:
Reg/memory with register to either
0OO100dw
mod
100000sw
mod
Immediate to accumulator
0OO1010w
rim
(DISP·LD)
(DISP-HI)
1 0 rim
(DISP-LD)
(DISP-HI)
reg
o
I
I
datalfw"l
data
= Increment:
Register/memory
1 1 1 1 1 1 1 w
Register
01000reg
AAA = ASCII adjust for add
o0
1 1 0 1 11
o0
1
DAA
I
data If w=l
data
Immediate to register/memory
INC
o
= Decimal adjust for add
o0
mod' 0 0 0
rim
I
(DISP-LO)
I
(DISP-HI)
I
1 11
4-23
Mnemonics © )nlel,1978
HARDWARE REFERENCE INFORMATION
Table 4-12. 8086 Instruction Encoding (Cont'd.)
ARITHMETIC (Conl'd.)
76543210
76543210
Reg/memoryand register to either
001010dw
mod
Immediate from register/memory
100000sw
Immediate from accumulator
0010110w
SUB
= Subtract:
76543210
76543210
(DISP-LO)
(DISP-HI)
mod 1 o 1 rim
IDISP-LO)
(DISP-HI)
data
data Ifw=l
reg
rim
76543210
76543210
data
I
data if s: w=Ol
I
data
I
data if s: w=Ol
I
data
I
data if s: w=l
J
saa = Subtract with borrow:
Reg/memoryand register to either
0OO110dw
mod
Immediate from register/memory
100000sw
mod 011
Immediate from accumulator
o0
0 1 1 lOw
reg
rim
(DISP-LO)
IDISP-HI)
rIm
(DISP-LO)
(DISP-HI)
I
I
data If w=l
data
DEC Decrement:
mod 0 0 1 rIm
i
1 1 1 1 0 1 1 w
mod 0 1 1 rim
I
Reglsterl memory and register
o 0 1 1 1 0 d w
mod
rim
(DISP-LO)
IDISP-HI)
immediate with register/memory
100000sw
mod 1 1 1 rim
(DISP-LO)
(DISP-HI)
Immediate with accumulator
o 0 1 1 1 1 0 w
data
Register/memory
1111111 w
Register
o1
NEG Change sign
CMP
IDISP-LO)
I
IDISP-HI)
IDISP-LO)
J
IDISP-HI)
I
0 0 1 reg
J
= Compare:
AAS ASCII adjust for subtract
o 0 1 111 11
CAS Decimal adjust for subtract
o 0 1 011 11
reg
MUl Multiply (unsigned)
1 1 1 1 0 1 1 w
mod 1 o 0 rIm
IDISP·LO)
IDISP-HI)
IMUL integer multiply (signed)
1111011 w
mod 1 o 1 rim
(DISP-LO)
IDISP-HI)
AAM ASCII adjust for multiply
1 1 0 1 0 1 '0 0
o 0 0 0 1 0 1 0
IDISP-LO)
IDISP-HI)
DIV Oivide (unsigned)
1111011
w
mod 1 1 o rIm
(DISp·LO)
IDISP-HI)
IDIV Integer divide (Signed)
1 1 1 1 0 1 1
w
mod 11 1 rim
IDISP-LO)
IDISP-HI)
AAD ASCII adjust for divide
1101 o 1 0 1
o 0 0 0 1 0 1 0
IDISP-LO)
(DISP-HI)
caw Convert byte to word
1001 1 0 0 0
CWO Convert word to double word
1 0 0 1 1 0 01
LOGIC
NOT Invert
11 1 1 01 1 w
mod o 1 0 rim
IDISP-LO)
(DISP-HI)
SHl/SAl Shilt logicallarlthmetic leU
1 1 0 1 0 0 v w
mod 1 o 0 rim
IDISP-LO)
IDISP-HI)
SHR Shift logical right
1 1 0 1 0 0 v w
mod 1 o 1 rim
IDISP-LO)
IDISP·HI)
SAR Shift arithmetic right
1 1 0 1 0 0 v w
mod 1 11 rim
IDISP-LO)
IDISP-HI)
ROl Rotate left
1 1 0 1 0 0 v w
mod 0 o 0 rim
IDISP-LO)
IDISP-HI)
Mnemonics © Intel, 1978
4-24
HARDWARE REFERENCE INFORMATION
Table 4-12.8086 Instruction Encoding (Cont'd.)
LOGIC (Conl'd.)
76543210
76543210
76543210
76543210
ROR Rotate right
11010Qvw
mod 0 o 1 rim
(DISp·LOI
(DISP·HII
RCL Rotate through carry flag left
1 1 0 1 0 0 v w
mod o 1
rim
(DISp·LOI
(DISp·HII
RCR Rotate through carry right
110100vw
mod 0 11
rim
(DISP·LOI
(DISP·HII
Reg/memory with register to either
001000dw
mod
rim
(DISP·LOI
(DISp·HII
Immediate to regl.ster/memory
1000000w
mod 1 0 0 rim
(DISp·LO)
(DISP·HII
Immediate to accumulator
0010010w
data
dataifw=1
AND
o
76543210
76543210
= And:
reg
I
I
data
I
data if w.. 1
I
data
I
dataifw",,1
I
da1a
I
datalfw=1
I
data
I
dataifw-1
I
TEST = And function to flags no result:
Register/memory and register
0OO100dw
mod
reg
rim
(DISP-LOI·
(DISP·LO)
Immediate data and register/memory
1 1 1 1 01 1 w
mod o 0 0 rim
Immediate data and accumulator
1010·100w
data
I
I
(DISP·HII
(DlSP·HII
I
I
OR = Or:
Reg/memory and register to either
0OOO10dw
mod
rIm
(DISp·LO)
(DISp·HII
Immediate to register/memory
1000000w
mod o 0 1 rIm
(DISP·Lci)
(DISp·HII
Immediate to accumulator
0OOO110w
da1a
dataifw=1
reg
I
I
XOR = Exclusive or:
Reg/memory and register to either
001100dw
Immediate to register/memory
0011010w
Immediate to accumulator
0011010w
mod
(DlSP·LO)
(DlSP·HI)
data
(DISP'LO)
(DISP-HI)
data
data If w=1
reg
rim
I
I
STRING MANIPULATION
REP=Repeat
1 1 1 1 0 0 1 z
MOVSa Move byte/word
1 0 I 0 0 I Ow
CMPS=Compare byte/word
1 o 1 0 0 I 1 w
SCAS=$can byte/word
1 0 1 0 1 1 1 w
LODS=Load byle/wd 10 ALIAX
1 0 1 0 1 1 0 w
STDS=Slor byle/wd from ALIA
1 0 1 0 1 0 1 w
4-25
Mnemonics © Inlel, 1978
HARDWARE REFERENCE INFORMATION
Table 4-12. 8086 Instruction Encoding (Cont'd.)
CONTROL TRANSFER
CALL
= Call:
76543210765432107654321076543210765432107654321.0
o1 o0
Direct within segment
111
Indirect within segment
1111 1111
Direct Intersegment
1 0 0 1 1
o1
0
IP-INC-LO
mod
o
1 0 rim
IP-Io
0
JMP
11111111
mod
o
(DISP-LOI
IDISP-HII
I
IDISP-HII
I
IDISP-HII
I
IDISP-HII
I
IP-hi
CS-l0
Indirect intersegment
IP-INC-HI
CS-hl
1 1 rim
(DISP-LOI
= Uncondltional,Jump:
o1 o0
1
IP-INC-LO
o1
1
IP-INC8
Direct within segment
111
Direct within segment-short
1 1 1 0 1
Indirect within segment
11111 111
Direct Intersegment
11 1 0 1
indirect intersegment
o1
0
11111111
IP-INC-HI
I
mod 1 0 0 rim
(DISP-LOI
IP-Io
IP-hi
CS-Io
CS-hl
mod 1 0 1 rim
(DISP-LOI
data-Io
data-hi
I
data-hi
I
RET = Return from CALL:
Within segment
1 1 0 0 0 0 1 1
Within seg adding immed to SP
1 1 0 0 0 0 1 0
Intersegment
1 1 0 0 1
o1
1
lntersegment adding immediate to SP
1 1 0 0 1
o1
0
data-Io
JE/JZ=Jumpon equallzero
o1
1 1 0 1
o0
IP-INC8
JL/JNGE=Jumpon lesslnot greater or equal
o1
111 1 0 0
IP-INC8
JLE/JNG =Jumpon less or equalfno! greater
o1
111 1 1 0
IP-INC8
JB/JNAE=Jumpon below/not above orequa!
o1
1 1 0 -0.1 0
IP-INC8
JBE/JNA=Jump'on beloworequal/not above
o1
1 1
o1
1 0
IP-INC8
JP I JPE = Jump on parity I parity even
o1
1 1 1 0 1 0
IP-INC8
JO =Jump on overflow
o1
1 1 0 0 0 0
IP-INC8
JS=Jump on sign
o1
1 1 1 0 0 0
IP-INC8
JNE/JNZ= Jump on not equal/not zerO
o1
1 1 0 1
o1
IP-INC8
JNL/JGE=Jump on not lesslgreateror equal
o1
1111
o1
IP-INC8
JNLE/JG =Jump on not less or equal/greater
o1
11 11 11
IP-INC8
JNB/JAE:;:;Jump on not belowfabove orequal
o1
1 1 0 0 1 1
Ip·1NC8
JNBE/JA=Jump on not below orequal/above
o1
1 1 011 1
IP~INC8
JNP/JPO=Jump on not parI par odd
o1
1 1 1 0 1 1
IP-INC6
JNO=Jump on not overflow
o1
11
o0
IP-INC6
Mnemonics © Intel, 1978
0 1
4-26
HARDWARE REFERENCE INFORMATION
Table 4-12. 8086 Instruction Encoding (Cont'd.)
CONTROL TRANSFER (Cont'd.)
RET
= Return from CALL;
76543210
JNS=Jump on not sign
o1
1 1 1 0 0 1
a0
76543210
76543210
76543210
76543210
78543210
Ip·INCB
LOOP = Loop ex times
1 1 1
0 1 0
IP-INCB
LOOPZlLOOPE = Loop while zero/equal
1 1 1 0 0 0 0 1
IP-INCB
LOOPNZ/lOOPNE=Loop while not zero/aquaI 11100000
lp·INCS
JCXZ=Jump on ex zero
1 1 1 0 0 0 1 1
IP-INCB
Type specified
1 1 0 0 1 1 0 1
DATA-a
Type3
1 1 0 0 1 1 0 0
INTO = Interrupt on overflow
1 1 0 0 1 1 1 0
IRET = Interrupt return
1 1
INT" = Interrupt:
aa1
I
1 1 1
PROCESSOR CONTROL
a0
elC = Clear carry
1 1 1 1 1 0
CMC=Complement carry
1 1 1 1
STC = Set carry
1 1 1 1 1 0 0 1
a1 a1
eLO =Clear direction
1 1 1 1 1 1
a0
STO = Set direction
1 1 1 1 1"
0 1
eLi = Clear Interrupt
1 1 1 1 1 0 1 0
STI=Set Interrupt
1 1 1 1 1 0 1 1
HLT=Halt
1 1 1 1 0 1 0 0
WAIT = Walt
1 0 0 1 1 0 , 1
ESC = Escape (to extern/ill device)
1 1 0 1 1
LOCK= Bus lock prefix
1 1 1 1 0 0 0 0
SEGMENT=Overrlde prefix
001reg110
xx x
modyyyr/m
I
(DISP-LOI
I
(DISP-HII
I
Table 4-13. Machine Instruction Decoding Guide
1ST BYTE
HEX
BINARY
00
01
02
03
04
05
06
07
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0010
0011
0100
0101
0110
0111
2ND BYTE
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO
RIM
RIM
RIM
RIM
BYTES 3, 4, 5, 6
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
4-27
ASM·86 INSTRUCTION FORMAT
ADD
ADD
ADD
ADD
ADD
ADD
PUSH
POP
REG81 MEM8, REG8
REG161 M EM16, REG16
REG8, REG81 M EM8
REG16,REG16/MEM16
AL,IMMEDB
AX,IMMED16
ES
ES
Mnemonics © Intel, 1978
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
BINARY
HEX
2ND BYTE
1E
1F
20
21
22
23
24
25
26
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
27
28
29
2A
2B
2C
2D
2E
0010
0010
0010
0010
0010
0010
0010
0010
0111
1000
1001
1010
1011
1100
1101
1110
2F
30
31
32
33
34
35
36
00.10
0011
0011
0011
0011
0011
0011
0011
1111
0000 MOD REG
0001 MOD REG
0010 MOD REG
0011 .MOD REG
0100 DATA-8
0101 DATA-LO
0110
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1C
10
Mnemonics © Intel, 1978
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO
RIM
RIM
RIM
RIM
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO
RIM
RIM
RIM
RIM
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO
RIM
RIM
RIM
RIM
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO
RIM
RIM
RIM
RIM
BYTES 3,4,5,6
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
ASM-86 INSTRUCTION FORMAT
OR
OR
OR
OR
OR
OR
PUSH
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
CS
(not used)
MOD
MOD
MOD
MOD
REG
REG
REG
REG
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
RIM
RIM
RIM
RIM
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO,(DISP-HI)
DATA~8
DATA-LO
DATA-HI
RIM
RIM
RIM
RIM
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
4-28
ADC
ADC
ADC
ADC
ADC
ADC
PUSH
POP
SSS
SSB
SBB
SBS
SBB
SSS
PUSH
POP
AND
AND
AND
AND
AND
AND
ES:
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
SS
SS
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
DS
OS
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
(segment override
prefix)
DAA
SUS
SUB
SUB
SUB
SUB
SUB
CS:
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG81 MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
DAS
XOR
XOR
XOR
XOR
XOR
XOR
SS:
REG8/MEM8,REG8
REG161 MEM16,REG16
REG8, REG81 M EM8
REG16,REG161 MEM16
AL,IMMED8
AX,IMMED16
(segment override
prefix)
(segment override
prefix)
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY
.
.
37
38
39
3A
3B
3C
3D
3E
0011
0011
0011
0011
0011
0011
0011
0011
0110
1000
1001
1010
1011
1100
1101
1110
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
0011
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
·0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
2ND BYTE
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO
RIM
RIM
RIM
RIM
BYTES 3,4,5,6
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI
ASM~86
AAA
CMP
CMP
CMP
CMP
CMP
CMP
DS:
AAS
INC
INC
INC
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
PUSH
PUSH
·PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
POP
POP
POP
POP
. POP
POP
POP
POP
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
4-29
INSTRUCTION FORMAT
REG8/MEM8,REG8
REG161 MEM16,REG1.6
REG8, REGSI M EM8
REG16,REG16/MEM16
AL,IMMEDS
AX,IMMED16
(segment override
prefix)
AX
CX
DX
BX
SP
BP
SI
DI
AX
CX
DX
BX
SP
BP
SI
DI·
AX
CX
DX
BX
SP·
BP
SI
DI
AX
CX
DX
BX
SP
BP
SI
DI
.
Mnemonics © Intel, 1978
HARDWAREREFERENCEJNFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY
68
69
6A
6B
6C
60
6E
6F
70
71
2ND.BYTE
72
0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111
1000
1001
1010
1011
1100
1101
1110
11.11
0000 IP-INC8
0001 IP-INC8
0010 IP-INC8
73
0111
0011
IP-INC8
74
75
76
78
79
7A
7B
7C
70
7E
7F
80
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
1000
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
MOD 000 RIM
80
1000
0000 MOD 001 RIM
80
1000
0000
MOD010 RIM
80
1000
0000
MOD 011 RIM
80
1000
0000
MOD100 RIM
80
1000
0000
MOD 101 RIM
80
1000
0000 MOD110 RIM
80
1000
0000
MOD 111 RIM
81
1000
0001
MODOOO RIM
81
1000
0001
MOD 001 RIM
81
1000
0001
MOD010 RIM
81
1000
0001
MODOll RIM
77
Mnemonics © Intel, 1978
BYTES 3,4,5,6
ASM-86 INSTRUCTION FORMAT
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(DISP-LO),(OISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
OATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(OISP-HI),
DATA-8
(DISP-LO),(OISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(OISP-HI),
DATA-LO,DATA-HI
4-30
JO
JNO
JB/JNAEI
JC
JNB/JAEI
JNC
JE/JZ
JNE/JNZ
JBE/JNA
JNBE/JA
JS
JNS
JP/JPE
JNP/JPO
JLlJNGE
JNLlJGE
JLE/JNG
JNLE/JG
ADD
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
OR
REG8/MEM8,IMMED8
ADC
REG8/MEM8,IMMED8
SBB
REG8/MEM8,IMMED8
AND
REG8/MEM8,IMMED8
SUB
REG8/MEM8,IMMED8
XOR
REG8/MEM8,IMMED8
CMP
REG8/MEM8,IMMED8
ADD
REG16/MEM16,IMMED16
OR
REG16/MEM16,IMMED16
AOC
REG16/MEM16,IMMED16
SBB
REG16/MEM16,IMMED16
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
REG8/MEM8,IMMED8
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
BINARY
HEX
2ND BYTE.
81
1000
0001
MOD100 RIM
81
1000
0001
MOD 101 RIM
81
1000
0001
MOD110R/M
81
1000
0001
MOD111 RIM
82
1000
0010 MODOOOR/M
82
82
1000
1000
0010 MOD 001 RIM
0010 MOD 010 RIM
82
1000
0010
82
82
1000
1000
0010 MOD 100 RIM
0010 MOD 101 RIM
82
82
1000
1000
0010 MOD110 RIM
0010 MOD111 RIM
83
1000
0011
MOD 000 RIM
83
83
1000
1000
0011
0011
MOD 001 RIM
MOD 010 RIM
83
1000
0011
MOD011 RIM
83
83
1000
1000
0011
0011
MOD100 RIM
MOD101 RIM
83
83
1000
1000
0011
0011
MOD110 RIM
MOD 111 RIM
84
85
86
87
88
89
8A
8B
8C
8C
8D
8E
8E
8F
8F
8F
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
0100
0101
0110
0111
1000
1001
1010
1011
1100
1100
1101
1110
1110
1111
1111
1111
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
.MOD REG RIM
MOD REG RIM
MOD REG RIM
MODOSRR/M
MOD1-R/M
MOD REG RIM
MODOSRR/M
MOD1-R/M
MOD 000 RIM
MOD 001 RIM
MOD 010 RIM
MOD 011 RIM
BYTES 3,4,5,6
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-8
ASM-86 INSTRUCTION FORMAT
AND
REG16/MEM16,IMMED16
SUB
REG16/MEM16,IMMED16
XOR
REG16/MEM16,IMMED16
CMP
REG16/MEM16,IMMED16
ADD
REG8/MEM8,IMMED8
(not used)
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP.HI),
DATA-8
ADC
REG8/MEM8,IMMED8
SBB
REG8/MEM8,IMMED8
(not used)
(DISP-LO),(DISP-HI),
DATA-8
SUB
REG8/MEM8,IMMED8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-SX
CMP
REG8/MEM8,IMMED8
ADD
REG16/MEM16,IMtylED8
(DISP-LO), (DISP-HI),
DATA-SX
(DISP-LO),(DISP-HI),
DATA-SX
ADC
REG16/MEM16,IMMED8
SBB
REG16/MEM16,IMMED8
(not used)
(not used)
(not used)
(DISP-LO),(DISP-HI),
DATA-SX
SUB
REG16/MEM16,IMMED8
(DISP-LO),(DISP-HI),
DATA-SX
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
CMP
REG16/MEM16,IMMED8
TEST
TEST
XCHG
XCHG
MOV
MOV
MOV
MOV
MOV
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
REG8/MEM8,REG8
REG16/MEM16/REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
REG16/MEM16,SEGREG·
(not used)
(not used)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
LEA
MOV
REG16,MEM16
SEGREG,REG16/MEM16
(not used)
(DISP-LO),(DISP-HI)
POP
REG16/MEM16
(not used)
(not used)
4-31
Mnemonics © Inlel,1978
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY
BF
BF
BF
BF
BF
90
91
92
93
94
95
96
97
9B
99
9A
1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1111
1111
1111
1111
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
9B
1001
9C
1001
90
1001
9E
1001
9F
1001
AD
1010
A1
1010
A2
1010
A3
1010
A4
1010
A5
1010
A6
1010
A7
1010
AB
1010
A9
1010
AA
1010
AB
1010
1010
AC
AO
1010
1010
AE
AF
1010
BO
1011
B1
1011
B2
1011
B3
1011
B4 . 1011
B5
1011
B6
1011
B7
1011
BB
1011
B9
1011
BA
1011
BB
1011
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
1011
0100
0101
0110
0111
1000
1001
1010
1011
Mnemonics © Intel, 1978
2ND BYTE
MOD 011
MOD100
MOD 101
MOD110
MOD 111
BYTES 3,4,5,6
RIM
RIM
RIM
RIM
RIM
DISP-LO
DISP-HI,SEG-LO,
SEG-HI
ADDR-LO
ADDR-LO
ADDR-LO
ADDR-LO
ADDR-HI
ADDR-HI
ADDR-HI
ADDR-HI
DATA-B
DATA-LO
DATA-HI
DATA-B
DATA-B
DATA-B
DATA-B
DATA-B
DATA-B
DATA-B
DATA-B
DATA-LO
DATA-LO
DATA-LO
DATA-LO
DATA-HI
DATA-HI
DATA-HI
DATA-HI
ASM-86 INSTRUCTION FORMAT
(not used)
(not used)
(not used)
(not used)
(not used)
NOP
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
CBW
CWO
CALL
WAIT
PUSHF
POPF
SAHF
LAHF
MOV
MOV
MOV
MOV
MOVS
MOVS
CMPS
CMPS
TEST
TEST
STOS
STOS
LODS
LODS
SCAS
SCAS
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
4-32
(exchange AX,AX)
AX,CX
AX,DX
AX,BX
AX,SP
AX,BP
AX,SI
AX,DI
FAR_PROC
AL,MEMB
AX,MEM16
MEMB,AL
MEM16,AL
DEST-STRB,SRC-STRB
DEST -STR16,SRC-STR16
DEST-STRB,SRC-STRB
DEST-STR16,SRC-STR16
AL,IMMEDB
AX,IMMED16
DEST-STAB
DEST-STR16
SRC-STAB
SRC-STR16
DEST-STRB
DEST-STR16
AL,IMMEDB
CL,IMMEDB
DL,IMMEOB
BL,IMMEDB
AH,IMMEDB
CH,IMMEDB
DH,IMMEDB
BH,IMMEDB
AX,IMMED16
CX,IMMED16
DX,IMMED16
BX,IMMED16
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY
2ND BYTE
BYTES 3,4,5,6
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
1011
1011
1011
1011
1100
1100
1100
1100
1100
1100
1100
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
DATA-LO
DATA-LO
DATA-LO
DATA-LO
DATA-HI
DATA-HI
DATA-HI
DATA-HI
DATA-LO
DATA-HI
MOD REG RIM
MOD REG RIM
MODOOO RIM
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI),
. DATA-8
C6
C6
C6
C6
C6
C6
C6
C7
1100
1100
1100
1100
1100
1100
1100
1100
0110
0110
0110
0110
0110
0110
0110
0111
MOD001 RIM
MOD010 RIM
MOD 011 RIM
MOD100 RIM
MOD101 RIM
MOD110 RIM
MOD 111 RIM
MODOOO RIM
C7
C7
C7
C7
C7
C7
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
DO
DO
DO
DO
DO
DO
DO
01
01
01
01
01
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
0111
0111
0111
0111
0111
0111
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
MOD001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101R/M
MOD 110 RIM
MOD111 RIM
DATA-LO
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
DATA-HI
DATA-8
MOD 000 RIM
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD 100 RIM
MOD101 RIM
MOD110R/M
MOD111 RIM
MODOOOR/M
MOD 001 RIM
MOD 010 RIM
MOD011 RIM
MOD 100 RIM
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
4-33
ASM-86 INSTRUCTION FORMAT
MOV
MOV
MOV
MOV
(not used)
(not used)
RET
RET
LES
LOS
MOV
SP,IMMED16
BP,IMMED16
SI,IMMED16
DI,IMMED16
IMMED16 (intraseg)
(intrasegment)
REG16,MEM16
REG16,MEM16
MEM8,IMMED8
. (not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
MOV
MEM16,IMMED16
(not used)
(not used).
(not used)
(not used)
(not used)
(not used)
(not used
(not used)
(not used)
RET
RET
INT
INT
INTO
IRET
ROL
ROR
RCL
RCR
SALISHL
SHR
(not used)
SAR
ROL
ROR
RCL
RCR
SALISHL
IMMED16 (intersegment)
(intersegment)
3
IMMED8
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG16/MEM16,1
REG16/MEM16,1
REG16/MEM16,1
REG16/MEM16,1
REG16/MEM16,1
Mnemonics © Intel, 1978
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd:)
1ST BYTE
HEX
BINARY
2NO.BYTE
DF
EO
1101 0001 MOD101 RIM
1101 0001 MOD 110 RIM
1101 0001 MOD111 RIM
1101 0010 MOD 000 RIM
1101 0010 MOD001 RIM
1101 0010 MOD010 RIM
1101 ·0010 MOD011 RIM
1101 0010 MOD100 RIM
1101 0010 MOD101 RIM
1101 0010 MOD110 RIM
1101 0010 MOD11t RIM
1101 0011 MOD 000 RIM
1101 0011 MOD 001 RIM
1101 0011 MOD010 RIM
1101 0011 MOD011 RIM
1101 0011 MOD100 RIM
1101 0011 MOD101 RIM
1101 0011 MOD110 RIM
1101 0011 MOD 111 RIM
1101 0100 00001010
1101 0101 00001010
1101 0110
1101 0111
1101 1000 MOD 000 RIM
1XXX MODYYYR/M
1101 1111 MOD 111 RIM
1110 0000 IP-INC-8
E1
1110
0001
IP-INC-8
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
IP-INC-B
IP-INC-8
DATA-8
DATA-8
DATA-8
DATA-8
IP-INC-LO
IP-INC-LO
IP-LO
IP-INC8
01
01
01
02
02
D2
D2
D2
D2
D2
D2
D3
D3
D3
03
03
03
03
03
04
D5
D6
D7
D8
Mnemonics © Intel, 1978
BYTES 3,4,5,6
(DISP-LO),(DISP-HI)
ASM-86 INSTRUCTION FORMAT
SHR
REG16/MEM16,1
(not used)
(DISP-LO),(DISP-HI)
. (DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP~LO),(DISP~HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
SAR
ROL
ROR
RCL
RCR
SALISHL
SHR
REG16/MEM16,1
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
(not used)
(DISP-LO) ,(DISP-H I)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP~LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
SAR
ROL
ROR
RCL
RCR
SALISHL
SHR
REG8/MEM8,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
(not used) .
(DISP~LO),(DISP-HI)
SAR
AAM
AAD
REG16/MEM16,CL
(not used) .
XLAT
(DISP-LO), (DISP-HI)
IP-INC-HI
IP-INC-HI
I P-H I, CS-LO, CS-H I
ESC
. SOURCE-TABLE
OPCODE;SOURCE
LOOPNEI SHORT~ABEL
LOOPNZ
LOOPEI SHORT-LABEL
LOOPZ
SHORT-LABEL
LOOP
SHORT-LABEL
JCXZ
IN
AL,IMMED8
IN
AX,IMMED8
OUT
AL,IMMED8
OUT
AX,IMMED8
. NEAR-PROC
CALL
JMP
NEAR-LABEL
FAR-LABEL
JMP
JMP
. SHORT-LABEL
IN
AL,DX
AX,DX
IN
OUT
AL,DX
OUT
AX,DX
(prefix)
LOCK
(not used)
REPNEJREPNZ
REP/REPE/REPZ
HLT
CMC
4-34
.,
HARDWARE REFERENCE INFORMATION
Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY
2ND BYTE
F6
1111
0110 MOD 000 RIM
F6
F6
F6
F6
F6
F6
F6
F7
1111
1111
1111
1111
1111
1111
1111
1111
0110
0110
0110
0110
0110
0110
0110
0111
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD110 RIM
MOD 111 RIM
MODOOOR/M
F7
F7
F7
F7
F7
F7
F7
FB
F9
FA
FB
FC
FD
FE
FE
FE
FE
FE
FE
FE
FE
FF
FF
FF
FF
FF
FF
FF
FF
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
0111
0111
0111
0111
0111
0111
0111
1000
1001
1010
1,011
1100
1101
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
MOD 001 RIM
MOD010R/M
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD110 RIM
MOD111 RIM
MOD 000 RIM
MOD 001 RIM
MOD010R/M
MOD011 RIM
MOD100R/M
MOD101 RIM
MOD110R/M
MOD111 RIM
MODOOOR/M
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD 110 RIM
MOD 111 RIM
BYTES 3,4,5,6
(DISP-LO),(DISP-HI),
DATA-B
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO) ,(DISP-H I)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO).(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO).(DISP-HI)
(DISP-LO).(DISP-HI)
4-35
ASM-86 INSTRUCTION FORMAT
TEST
REGBI M EMB,IM M EDB
(not used)
NOT
NEG
MUL
IMUL
DIV
IDIV
TEST
REGB/MEMB
REGB/MEMB
REGB/MEMB
REGB/MEMB
REGB/MEMB
REGB/MEMB
REG16/MEM16.IMMED16
(not used)
NOT
NEG
MUL
IMUL
DIV
IDIV
CLC
STC
CLI
STI
CLD
STD
INC
DEC
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
INC
DEC
CALL
CALL
JMP
JMP
PUSH
(not used)
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REGB/MEMB
REGB/MEMB
MEM16
MEM16
REG16/MEM16 (intra)
MEM16 (intersegment)
REG16/MEM16 (intra)
MEM16 (intersegment)
MEM16
Mnemonics © Inlel, 1978·
HARDWARE REFERENCE INFORMATION
Table 4-14. Machine Instruction Encoding Matrix
Lo
HI
0
1
2
3
4
5
0
ADD
b,t,r/m
ADC
b.f,r/m
AND
b.f,r/m
XOR
b.f,r/m
INC
AX
PUSH
AX
I
ADD
w,t,r/m
ADC
w.f,r/m
AND
w.f.r/m
XOR
w.f,r/m
INC
CX
PUSH
CX
2
3
ADD
b,t,r/m
ADC
b,t.r/m
AND
b,t.r/m
XOR
b,t,r/m
INC
DX
PUSH
OX
ADD
w,t.r/m
,ADC
w,t,r/m
AND
w,t,r/m
XOR
w,t,r/m
INC
BX
PUSH,
BX
4
ADD
b, ia
ADC
b,i
AND
b,i
XOR
b,i
INC
SP
PUSH
SP
AND
w.i
XOR
w,i
INC
BP
PUSH
BP
JO
JNO
JBI
JNBI
JEI
JNEI
5
ADD
w.ia
ADC
w,i
6
PUSH
ES
PUSH
SS
SEG
"ES
SEG
"SS
INC
SI
PUSH
SI
INC
01
PUSH
01
JBEI
JNA
XCHG
b,r/m
XCHG
SI
JNBEI
JA
XCHG
w,r/m
XCHG
01
CBW
CWO
TEST
b,l,a
7
POP
ES
POP
SS
DAA
AAA
8
OR
b,t.r/m
SBB
b,t,r/m
SUB
b.f.r/m
CMP
b,t,r/m
DEC
AX
POP
AX
9
OR
w.f.r/m
SBB
w,t,r/m
SUB
w.f,r/m
CMP
w.f.r/m
DEC
CX
POP
CX
JS
JNS
MOV
b.f,r/m
MDV
w.f,r/m
A
OR
b,t,r/m
SBB
b,t,r/m
SUB
b.t,rim
CMP
b,t,r/m
DEC
OX
POP
OX
8
OR
w,t,r/m
SBB
w,t,r/m
SUB
w,t.r/m
CMP
wHim
DEC
BX
POP
BX
C
OR
b.i
SBB
b,1
SUB
b,i
CMP
b,i
DEC
SP
POP
SP
0
OR
w,j
SBB
w.i
SUB
w.i
CMP
w,i
DEC
BP
POP
BP
E
PUSH
CS
PUSH
OS
SEG
"CS
SEG
"OS
DEC
SI
POP
SI
F
"
POP
OS
DAS
AAS
DEC
or
POP
01
6
7
Immed
b,r/m
XCHG
AX
A MOV
m - AL
B
MOV
i _ AL
8
9
C
Shift
b
E LOOPNZI
LOOPNE
F
LOCK
0
JNAE
JAE
JZ
Immed Immed Immed
TEST
w.r/m
b,r/m
b,r/m
is.r/m
XCHG
XCHG
XCHG
XCHG
CX
OX
BX
SP
MOV
MDV
MOV
MOVS
m -AX AL - m AX - m
MOV
MOV
MOV
MOV
i - CL i - OL i - BL i - AH
RET,
RET
LES
(i+SP)
Shift
Shift
Shift
AAM
w
b,v
W,V
LOOPZI
IN
LOOP
JCXZ
LOOPE
b
REP
REP
HLT
z
where'
modOr/m
Immed
Shill
Grp 1
Grp2
JNZ
TEST
w,r/m
XCHG
BP
MOVS
CMPS
CMPS
MOV
i - CH
MOV
i - DH
MOV
b,i.r/m
MOV
MOV
i - BH i-AX
MOV
w,i.r/m
ESC
XLAT
0
OUT
CALL
w
d
Grp 1
CLC
LOS
AAD
IN
w
OUT
b
Grp 1
b,r/m
CMC
000
ADD
ROL
TEST
INC
001
OR
ROR
DEC
010
ADC
RCL
NOT
CALL
id
w.r/m
011
SBB
RCR
NEG
CALL
Lid
JNPI
JPO
MOV
wHim
JLI
JNGE
MOV
sr,t,r/m
JNLI
JGE
WAIT
TEST
w,l,a
STOS
MOV
i - CX
ESC
1
JMP
d
MOV
i-OX
RET,
1.(i+SP)
ESC
2
JMP
I,d
STC
' CLI
101
SUB
SHR
IMUL'
JMP
110
XDR
DlV
PUSH
I.id
z = zero
4-36
LEA
JLEI
JNG
MOV
sr,t,r/m
JNLEI
JG
POP
rim
PUSHF
POPF
SAHF
LAHF
STOS
LOOS
LOOS
SCAS'
SCAS
MOV
i - BX
RET
I
ESC
3
JMP
si.d
MOV
i - SP
INT
Type 3
ESC
4
IN
v,b
MOV
i - BP
INT
(Any)
ESC
MOV
i - SI
MOV
i _ 01
INTO
IRET
ESC
7
OUT
STI
CLD
STO
ESC
6
OUT
v,b
Grp 2
b,r/m
111
CMP
SAR
IDIV
m = memory
rim = EA is second byte
si = short intrasegment
sr = segment register
t = to CPU reg
v = variable
w = word operation
b = byte operation
d = direct
t = from CPU reg
i = immediate
ia = immed, to accum.
id = indirect
is = immed. byte, sign ext.
I = long ie. intersegment
Mnemonics © Intel, 1978
100
AND
SHLISAL
MUL
JMP
id
JPI
JPE
MOV
b,t,r/m
CALL
I,d
5
IN
v,w
v,w
Grp 2
w,r/m
HARDWARE REFERENCE INFORMATION
Keeping these guidelines in mind, the instruction
sequence depicted in figure 4-22 can. be described
as follows. Starting the loop arbitrarily in clock
cycle I with the queue reinitialization that occurs
as part of the JMP instruction, JMP instruction
execution is completed by the EU, while the BIU
performs an opcode fetch to begin refilling the
queue. (Note that a shorthand notation has been
used in the figure to represent the ,two queue
status lines and the three status lines-active
periods on any of these lines are noted and the
binary value of the lines is indicated above each
active region.)
8086 Instruction Sequence
Figure 4-22 illustrates the internal operation and
bus activity that occur as an 8086 CPU executes a
sequence of instructions. This figure presents the
signals and timing relationships that are important in understanding 8086 operation. The following discussion is intended to help in the interpretation of the figure.
Figure 4-22 shows the repeated execution of an
instruction loop. This loop is defined in both
machine code and assembly language by figure
4-21. A loop was chosen both to demonstrate the
effects of a program jump on the queue and to
make the instruction sequence easy to follow. The
program sequence shown was selected for several
reasons. First, consisting of seven instructions
and 16 bytes, the sequence is typical of the tight
loops found in many application programs.
Second, this particular sequence contains several
short, fast-executing instructions that
demonstrate both the effect of the queue on CPU
performance and the interaction between the execution unit (EU) fetching code from the queue
and the bus interface unit (BIll) filling the queue
and performing the requested bus cycles. Last,
for the purpose of this discussion, code, stack,
and memory data references were arranged to be
aligned on even word boundaries.
ASSEMBLY LANGUAGE
MACHINE CODE
MOV AX, OF802H
PUSH AX
MOVCX, BX
MOVDX,CX
ADD AX, [51]
ADD 51, 8086H
JMP $ -14
8802F8
In clock cycle 8, the queue status lines indicate
that the first byte of the MOV immediate instruction has been removed from the queue (one clock
cycle after it was placed there by the BIU fetch)
and that execution of this instruction has begun.
The second byte of this instruction is taken from
the queue in clock cycle 10 and then, in clock
cycle 12, the EU pauses to wait one clock cycle for
the BIU's second opcode fetch to be completed
and for the third byte of the MOV immediate
instruction to be available for execution
(remember the queue status lines indicate queue
activity that h~s occurred in the previous clock
'
cycle).
Clock cycle 13 begins the execution of the PUSH
AX instruction, and in clock cycle 15, the BIU
begins the fourth opcode fetch. The BIU finishes
the fourth fetch in clock cycle 18 and prepares for
another fetch when it receives a request from the
EU for a memory write (the stack push). Instead
of completing the opcode fetch and forcing the
EU to wait four additional clock cycles, the BIU
immediately aborts the fetch cycle (resulting in
two idle clock cycles (TI) in clock cycles 19 and
20) and performs the required memory write. This
interaction between the EU and BIU results in a
Single clock extension to the execution time of the
PUSH AX instruction, the maximum delay 'that
can occur in response to an EU bus cycle request.
50 '
8BGB
8BD1
0304
,81C68680
EBFQ
Figure 4-21. Instruction Loop Sequence
Figure 4-22 can be more easily interpreted- by
keeping the following guidelines in mind.
,
'
•
The queue status lines (QSO, QSl) are the key
indicators of EU activity.
•
Status .lines S2 through SO are the main
indicators or 8086/8088 bus activity.
•
Interaction of the BIU and EU is via the
queue for pre fetched opcodes and via the EU
for requested bus cycles for data operands.
Execution continues in clock cycle 24 with the
execution of back-to-back, register-to-register
MOV instructions. The first of these instructions
takes full advantage of the pre fetched opcode to
complete this operation in two clock cycles. The
second MOV instruction, however, depletes the
queue and requires two additional clock cycles
(clock cycles 28 and 29).
4-37
Mnemonics © Intel, 1978
HARDWARE REFERENCE INFORMATION
eLK
T, I T, IT,
."
otg:cus:" ------,
EU
T2
f3'
FETCHBl02
T4
I
Tl
~
T2
TS
FETCHFISO
.~
r..
I
Tl
fa
T2
mCH II CI
~ ~~~
MOW"'' ' '
.,.
T2
fa
T2
fS
WRITE FI020NTO
mCH •• D1
r4
I
"
Tl
FETCMDO
STACK
~
.,
II
~~~
01
11
FI"'T I NEXT I FIRST I N
IYTE
PUIHAX
I BYTf linE I •
1·lIovci n
+-.
Figure 4-22. Sample.lnstruction Sequence Execution
In clock cycle 30, the ADD memory indirect to
AX instruction begins. In the time required to
execute this instruction, the BIU completes two
opcode fetch cycles and a memory read and
begins a fourth opcode fetch cycle, Note that in
the case of the memory read, the EU's request for
a bus cycle occurs at a point in the BIU fetch cycle
where it can be incorporated directly (idle states
are not required and no EU delay is imposed).
code sequences, however, use a higher proportion
of more complex, longer-executing instructions
and addressing modes, and therefore tend to be
execution limited. In this case, less BlU-EU
interaction is required, the queue more often is
full, and more idle states occur on the bus.
The previous example sequence can be easily
extended to incorporate wait. states in the bus
access cycles. In the case of a single wait state,
each bus cycle would be lengthened to five clock
cycles with a wait state (TW) inserted between
every T 3 and T4 state of the bus cycle. As a first
approximation, the instruction sequence exection
time would appear to be lengthened by 10 .clock
cycles, one cycle for each useful read or write bus
cycle that occurs. Actually, this approximation
for the number of wait states inserted is incorrect
since the queue can compensate for wait states by
making use of previously idle bus time. For the
example sequence, this compensation reduced the
actual execution time by one wait state, and the
sequence was completed in 64 clock cycles, one
less than the approximated 65 clock cycles.
In clock cycle 44, the EU begins the ADD
immediate instruction, taking four bytes from the
queue and completing instruction execution in
four clock cycles. Also during this time, the BIU
senses a full queue in clock cycle 45 and enters a
series of bus idle states (five or six bytes constitute
,a full queue in the 8086; the BIU waits until it can
fetch a full word of opcode before accessing the
bus) ..
At clock cycle 47, the BIU again begins a bus
cycle, sequence, one that is destined to be an
"overfetch" since the EU is executing a JMP
instruction. As part of the JMP instruction, the
queue reinitialization (which began the instruction sequence) occurs.
4.3 8089 I/O Processor
The entire sequence of instructions has taken 55
clock cycles. Eighteen opcode bytes.were fetched,
one word memory read occurred, and one word
stack write was performed.
The Intel® 8089 I/O Processor (lOP) combines
the functions of a DMA controller with the processing capabilities of a microprocessor. In addition to the normal DMA function of transferring
data, the 8089 is capable of dynamically
translating and comparing the data as it is
This example was, by design, partially bus limited
and indicates the types of EU and BIU interaction
that can occur in this situation. Most application
Mnemonics ©.Intel. 1978
4-38
HAftDWAREREFERENCE INFORMATION
• I • I
»
I • I " I • I
U
I
UUUUlJlJl
.------------ -- --,
._I
" "
FETCH II CI
T4
ITt
~~~
" "
FETCHllao
T4
IT'
" "
READ DATA AT
ADDRESSISq
T4
I
T1
T.
"
FETCHEBn
~
T.
I" I" I" I"
"
T.
FETCH IlX IIX
h
I 1"·1" I" I
TI
I~~~~ ~~
CI
.
II
1...-_ _..,.-_ _ _ _ _ _ _ _ _ _ _ _---..1
FIRST I NEXT I NEXT I NEXT I FIRST
BYTE IIYTE IIYTE I Inl IIYTE
.
--,I
L------,--;....;....---IQU£UI 1- -
__
EMPTIED
- - - - - - - -.. D D A X , l s q > - - - - - - - - - - _ J - - - " O D S l , I D M H _......~-----JMP ,4----------
~f-I
•.
Figure 4-22. Sample Instruction Sequence Execution
System Configuration
transferred arid of supporting a number of terminate conditions including byte count expired,
data compare or miscompare and the occurrence
of an external event. The 8089 contains two
separate DMA channels, each with its own
register set. Depending on the established
priorities (both inherent and program determined), the two channels can alternate
(interleave) their respective operations.
The 8089 can be implemented in one of two
system configurations: a "local" mode in which
the 8089 shares the system bus with an 8086 or
8088 CPU and a "remote" mode in which the
8089 has exclusive access to its own dedicated bus
as well as access to the system bus. Note that in
either the local or remote mode, the 8089 can
address a full megabyte of system memory and
64k bytes of I/O space.
Designed expressly to relieve the 8086 or 8088
CPU of the overhead associated with I/O operations, the 8089, when configured in the remote
mode, can perform a complete I/O task while the
CPU is performing data processing tasks. The
8089, when it has completed its I/O task, can then
interrupt the CPU.
Local Mode
In the local mode, the 8089 acts as a slave to an
8086 or 8088 CPU that is operating in the maximum mode. In this configuration, the 8089
shares the system address latches, data
transceivers and bus controller with the CPU as
shown in figure 4-23.
.
Transfer flexibility is an integral part of the
8089's design. In addition to routine transfers
between an I/O peripheral and memory, transfers
can be performed between two I/O devices or
between two areas of memory. Transfers between
dissimilar bus widths are automatically handled
by the 8089. When data is transferred from an
8-bit peripheral bus to a.16-bit memory bus,. the
8089 reads two .bytes from the peripheral,
assembles the bytes into a 16-bit word and then
writes the single word to the addressed memory
location. Also; both 8- and 16-bit peripherals can
reside on the same (16-bit) bus; byte transfers are
performed with the 8-bit peripheral, and word
transfers are performed with the 16-bit
peripheral.
Since the lOP and CPU share the system bus,
either the.IOP or the CPU will have access to the
bus at anyone time. When one processor is using
the bus, the other processor floats its
address/ data and control lines. Bus access
between the lOP and CPU is determined through
the request/grant function. Recalling the CPU's
request/grant sequence, the lOP requests the bus
from the CPU, the CPU grants the bus to the
lOP, and the lOP relinquishes the bus to the CPU
when its operation is complete. Remember that
the CPU cannot request the bus from the lOP
(the CPU is only capable of granting the bus and
4-39
HARDWARE REFERENCE INFORMATION
~
r;:
-
ClK
UN/Vi
READY
RESET
....
Si-!ii
A'I-AD
.7-Do
-..II
~
'-1: eLK
INTl
DEN
UW'I'l!
r-
....ClK
orift
ALE
sya
READY
RESET
--,--
..!''''''ii-IO
~ RESET
READY
--------r;::
ClK
....
EK"
ORO 2
EKT 1
r"" oR01CA
f
-
n
[~
, ADDRESS BUS
••
•
r~-;
: O:6':OE :
.
I
I
I
I
I
I
I
I
I~
RAM
(2142)
0. I
c,
I A~gg~~~~5L 1I
I
~~:2)
I
___
-r--r"
ATABU
+
~,
· ~
••
.--Y_-,
:
I
I
+
A15-A,
O:~O~E
I
I
--.:..-
t
:
--r-
A11-AD
El
••
•
r~-.
-:-r-
82..
ADDRESS/DATA
--=v
DE
DE
Dr-Do
.-
.1 -.4- =
Rc5/GTo
D
-
S2-!O~
I
I
I
I
I
I
I
I
I
I
I
+
IIF rI
I
I
I
~
0' II 110 PERIPHERAL
C~.Ac,KI r:'·ACK
.. ~
110 PERIPHERAL
IOvIO
ORO
tNT
ORO
I~
1S81T1IO
ADDRESS DECODE
--
I
I
I
I
INT
~
ACK
tiD
.. W>
PE.RIP~ERAL
ORO
tNT
I
~
Figure 4-23. TypicaiSOSS/SOS9 Local Mode Configuration
must wait for the lOP to release the bus). Also,
since the request/grant pulse exchange must be
synchronized, both the CPU and lOP must be
referenced to the same clock signal.
The 8089 lOP, when used in the local mode, can
be ad_ded to an 8086 or 8088 maximum mode configuration with little affect on component count
(channel attention decoding logic asrequired) and
offers the benefits of intelligent DMA
(scan/match,- translate, variable termination conditions), modular programming in a full
megabyte of memory address space and a set of
optimized I/O instructions that are unavailable to
the 8086 and 8088 CPUs. The major disadvantage
to the local configuration is that since the system
bus is shared, bus contention always exists
between the CPU and lOP. The use of the bus
load limit field in the channel control word can
help reduce lOP bus access during task block program execution (bus load limiting has no affect on
DMA transfers) although, for I/O intensive
systems, the remote mode should be considered.
Remote Mode
The 8089,whenused in the 'remote mode, provides a multiprocessor system with true parallel
processing. In this mode, the 8089 has a separate
(local) bus and memory for 110 peripheral communications, and the system bus is completely
isolated from the 110 peripheral(s). Accordingly,
I/O transfers between an I/O peripheral and the
lOP's local memory can occur simultaneously
with CPU operations on the system bus.
As shown in figure 4-24, to interface the 8089 to
the system -bus, data transceivers and address
latches are used to separate the lOP's local bus
from the system bus, an 8288 Bus Controller is
used to generate the bus control signals for both
the local and system buses as well-as to govern the
operationofthe transceivers/latches, and an 8289
Bus Arbiter is used to control access to the system
bus (each processor in the system would have an
associated 8289 Bus Arbiter). To interface the
8089 to its local bus, another set of address
HARDWARE REFERENCE INFORMATION
AO FROM CPU
IIOPOll1
LOCAL
"DORESS
l
WAIT STATE
_O~
MEMORY WRITE
IIOyt
ONEoSHOT
pF WAIT STATES
"OADORESS
I
I.L
DECODE
~r.DACK
'--DRO
'NT
110
PERIPHERAL
~1~AeK
I
I
-
L2.E~~
~
eLK
110
PERIPHERAL
A015-ADo
8282183
AEN
IN'fA
MEMORY READ COMMAND
MEMORY WRITE COMMAND
I O B I - Vee
ALE
Iffi~
1<
§
~
III
r--Hr4
I--
r---
Ilm"e " ..
lOWe
~dlJ
l
T
8285187
M'iiDc
MWiC
eLK
8212/83
-
Of
MULl'lMASTEA
CONTROL BUS
s,.§ij
~
~
LOCAL ADDRESS BUS (A15-AoI
LOCAL DATA BUS
.... H
r..!ii
m
Ri5,Gr
or !
~
k
eLK
~
Em
a=
I
I..
(I.E •• XACK)
r-iEiii
::22A1a-AlIrii -r;o
INT
SYSTE'!.!LESET
TRANSFER ACKNOWLEDGE
READY
TO/FROM
ANOTHEA'OP
DRO
es
SEL
DROt
A'5-A1 FROM CPU
110 WRITE COMMAND
(I.E.,INITI
ROn
BOO.
eA
,
-
RESET
LOGIC
es
II
RST
~ 1!
REQUIRED)
I~I
DECODE
LOGIC
r--;;;-
OEN~'lATOR
MULl'MASTER
ADDRESSBUS
I A19-Ao.BtiE)
.
ULTIMASTEA
•
'--
8288187
DATABUS
I 015-001
L--
Figure 4-24. Typical 8089 Remote Mode Configuration
Bus Operation
latches is required (unless MCS-85™ multiplexed
address components are exclusively interfaced)
and, depending on the bus loading demands, one
(8-bit bus) or two (16-bit bus) data transceivers
would be used.
The 8089 utilizes the same bus structure as an
8086 or 8088 CPU that is configured in the maximum mode and performs a bus cycle only on demand (e.g., to fetch an instruction during task
block execution or to perform a data transfer).
The bus cycle itself is identical to an 8086 or 8088
CPU's bus cycle in that all cycles consist of four
T -states and use the same time-multiplexing
technique of the addressdata lines. As shown in
the following timing diagrams, the address (and
ALE signal) is output during state T 1 for either a
read or write cycle. Depending on the type of
cycle indicated, the addressl data lines are floated
during state T2 for a read cycle (figure 4-25) or
data is output on these lines during a write cycle
(figure 4-26). During state T3, write data is maintained or read data is sampled, and the busy cycle
is concluded in state T 4.
In the remote mode, the lOP's local bus is treated
as 1/0 space (up to 64k bytes), and the system bus
is treated as memory space (1 megabyte). The
8288 Bus Controller's 1/0 command outputs control the local (110) bus, and its memory command
outputs control the system (memory) bus. The
8289 Bus Arbiter, which is operated in its lOB
(110 ~ripheral bus) mode, also decodes the
lOP's S2 through SO status outputs. In this mode,
the 8289 will not request the multimaster system
bus when the lOP indicates an operation on its
local bus. If the lOP's bus arbiter currently has
access to the system bus, the CPU's arbiter (or
any other arbiter in the system) can acquire use of
the system bus at this time (a bus arbiter maintains bus access until another arbiter requests the
bus).
Since the 8089 is capable of transferring data to or
from both 8-bit and 16-bit buses, when an 8-bit
physical bus is specified (bus width is specified
4-41
HARDWARE REFERENCE INFORMATION
elK
~-S6
ADDRESS/STATUS
-""T\------.,--"T"",-----r,---52-SO ACTIVE
52-SO INACTIVE
\
'----
==~~L-_A_'_'-_A'_'_....JX,~_______S'_-_S'_ _ _ _ _ _ _J~
(AA~~~:g:) ---~r------------------------------------.
___ ....J~
A15-A8
}----
DATA IN 07-00
r----l.
'AlE
,'-------------
_----"
\1-_-------',
"MORC or 'IORC
..J
,
- - -71- - - - - - - . . \
·DTlR __
'DEN
,-----
I
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J
'8288 BUS CONTROLLER OUTPUTS
Figure 4-25. Read Bus Cycle (8-Bit Bus)
elK
52-.SO
ADDRESS/STATUS
SHE
-""T\----------"r----------,-'
---I...._ _ _ _ _ _
52-SO ACTIVE
==~~~\,.
__
--.J
52-SO INACTIVE
\' -
__ _
A_'_9-_A'_.__y
. ._______S_.-_S,_ _ _ _ _ ___I~
----.,
SHE LOW FOR DATA TRANSFER ON HIGH ORDER Byre (015-08)
----.I
X_ _ _ _ _ _ _ _ _ _ _ _..-_...J.
(AD15-ADO) ----~
____
_ _ _ _ _-'.1...
ADDRESS/DATA
.~I...
A15-AO
DATA QUT 015-00
r----l.
"ALE
I
_ _ _---J
,
,I....-------~~---
\
·~OR·AiOWC
}---
\'--------',
'~OR''IQiRe
---,
'DEN,
,
___ .....
' ---,-.,--_----1
'8288 BUS CONTROLLER OUTPUTS
Figure 4-26. Write Bus Cycle (16-Bit Bus)
4-42
HARDWARE REFERENCE INFORMATION
The 8089 operates identically to the 8086 CPU
with respect to the use of the low- and high-order
halv!!s of the data bus. Table 4-14 defines the data
bus use for the various combinations of bus width
and address boundary.
during the initialization sequence), the address
present on the AD 15 through AD8 address/data
lines is maintained for the entire bus cycle as
shown in figure 4-25 and, unless added drive
capability is required, the associated address latch
can be eliminated. An 8-bit data bus is compatible
with the 8088 CPU and with the MCS-85™
multiplexed address peripherals (8155, 8185,
etc.).
The S2 through SO status lines define the bus cycle
to be performed. These lines are used by an 8288
Bus Controller to generate all memory and 110
command and control signals, and are decoded
according to table 4-15.
Table 4-14. Data Bus Usage
Physical Bus Width'
Address
Logical
BusWidth'
Boundary
16
8
Byte Transfer
Word Transfer
Even
AD7-ADO = DATA
(SHE not used)
AD7-ADO= DATA
(SHE high)
N/A
Odd
AD7-ADO = DATA
(SHE not used)
AD15-AD8 = DATA
(SHE low)
N/A
Even
Illegal
AD7-ADO = DATA
(SHE high)
AD15-ADO = DATA
(BHE low)
Odd
Illegal
AD15-AD8 = DATA
(SHE low)
N/A'
8
16
Notes:
1.
Logical bus width is specified by the WID instruction prior to the DMA transfer.
2.
Physical bus width is specified when the 8089 is initialized.
3.
A word transfer to or from an odd boundary is performed as two byte transfers. The first byte transferred is the low-order byte on the high-order data bus (AD15-AD8), and the second byte is the highorder byte on the low-order data bus (AD7-ADO). The 8089 automatically assembles the two bytes in
their proper order.
Table 4-15. Bus Cycle Decoding
Status Output
S2
S1
SO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bus Cycle Indicated
Instruction fetch from I/O space
Data read from I/O space
Data write to I/O space
Not used
Instruction fetch from system memory
Data read from system memory
Data write to system memory
Passive
4-43
Bus Controller
Command Output
INTA
10RC
10WC,AIOWC
None
MRDC
MRDC
MWTC,AMWC
None
HARDWARE REFERENCE INFORMATION
Note that the 8089 indicates an instruction fetch
from I/O space as a status of zero (S2, SI and SO
equal 0). Since the 8288 Bus Controller decodes
an input status value of zero as an interrupt
acknowledge bus cycle, the bus controller's INTA
output must be OR'ed with its 10RC output to
permit fetching of task block instructions from
!ocal8089memory (remote configuration) or
system 110 space (local and remote
configurations).
(RDYI or RDY2). Either of these inputs, when
enabled by its corresponding AEN lor AEN2
input, can be deactivated directly by the memory
or I/O device when it must extend the 8089's bus
cycle (when the addressed device is not ready to
present or accept data). The 8284's READY output, which is synchronized to the CLK signal, is
directly connected to the 8089's READY input.
As shown in figure 4-27, when the addressed
device requires one or more wait states to be
inserted into a bus cycle, it deactivates the 8284's
RDY input prior to the end of state T2. The
READY output from the 8284 is subsequently
deactivated at the end of state T2 which causes the
8089 to insert wait states following state T3. To
exit the wait state, the device activates the 8284's
RDY input which causes the READY input to the
8089 to go active on the next clock cycle and
allows the 8089 to enter state T 4.
The S2 through SO status lines become active in
state T4 if a subsequent bus cycle is to be performed. These lines are setto the passive state (all
· "ones") in the state immediately prior to state T 4
of the current bus cycle (state T 3 or T w) and are
floated when the 8089 does not have access to the
bus.
The S6 through S3 status lines are multiplexed
with the high-order address bits (AI9-AI6f and,
· accordingly, become valid in state T2 of the bus
cycle. The S4 and S3 status lines reflect the type of
bus cycle being performed on the corresponding
· channel as indicated in taple 4-16. .
ClK
TRWc,·_II_
ROY INPUT
-----"."""=
TR1vcl·_11- _I !--TClR1X·
•
Table 4-16. Type of Cycle Decoding
READY
READY
OUTPUT
Status Output
S4
S3
Type of Cycle
\'--_ _
No_T_RE_Ao_y_---I1
READY
"REFER TO THE 8284 CLOCK GENERATOR/DRIVER DATA SHEET IN APPENDIX B FOR
TIMING INFORMATION
Figure 4-27. Wait State Timing
0
0
0
1
1
0
1
1
DMA on Channel 1
DMA on Channel 2
Non-OMA on Channel1
Non-DMA on Channel 2
Periods of inactivity can occur between bus
cycles. These inactive periods are referred to as
idle states (Tl) and, as with the 8086 and 8088
CPUs, can result from the execution of a "long"
instruction or the loss of the bus to another processor during task block instruction execution.
Additionally, the 8089 can experience idle states
when it is in the DMA mode and it is waiting for a
DMA request from the addressed I/O device or
when the bus load limit (BLL) function is enabled
for a channel performing task block instruction
execution and the other channel is idle.
The S6 and S5 status lines are always" 1" on the
8089. Since these lines are not both" I" on the
other processors in: the 8086 family (S6 is always
"0" on the 8086 and 8088 CPUs), these status
lines can be used as a "signature" in a
multiprocessor environment to identify the. type
of processor performing the bus cycle.
The 8089 includes the same provision as do the
8086 and 8088 CPUs for the .insertion of wait
states (T w) in a bus cycle when the associated
memory or I/O device cannot respond within the
.allotediime interval or when, in the remote mode,
,the 8089 must wait for access to the system bus.
An 8284 Clock Generator/Driver is used to control the insertion of wait states which, when
,required, are inserted between states T 3 and T 4.
The actual insertion of wait states is accomplished
'by deactivating one of the 8284's RDY inputs
Initialization
Initialization of the lOP is generally the responsibility of the host processor which,· as stated in
Chapter 3, prepares the communications data
structure in shared memory. Initialization of the
lOP itself begins with the activation of its RESET
input. This input (originating typically from an
4-44
HARDWARE REFERENCE INFORMATION
8284 Clock Generator/Driver) must be held active
for at least five clock cycles to allow the 8089's
internal reset sequence to be completed. Note that
like the 8086 and 8088 CPUs, the RESET input
must be held active for at least 50 microseconds
when power is first applied. Following the reset
interval, the host processor signals the lOP to
begin its initialization sequence by activating the
8089's CA (Channel Attention) input. The 8089
will not recognize a pulse at its CA input until one
clock cycle after the RESET input returns to an
inactive level. Note that the minimum width for a
CA pulse is one clock cycle and that this pulse
may go active prior to RESET returning to an
inactive level provided that the negative-going,
trailing-edge of the CA pulse does not occur prior
to one clock cycle after RESET goes inactive.
Figure 4-28 illustrates the timing for this portion
of the initialization sequence.
and an 8089 share a common bus, the 8089 must
be designated the slave. Also, when the RQ/GT
line is not used (Le., a single 8089 in the remote
configuration), the 8089 must be designated a
master.
In addition to determining master/slave status,
the CA pulse also causes the 8089 to begin execution of its internal ROM initialization sequence;
Note that since the 8089 must have access to the
system bus in order to perform this sequence, the
8089 immediately initiates a request/grant
sequence (if designated a slave) and, if required,
then requests the bus through the 8289 Arbiter.
(If designated a master, the 8089 requests the bus
through the 8289 Arbiter.) In the execution of the
initialization sequence, the 8089 first fetches the
SYSBUS byte from location FFFF6H. The W bit
(bit 0) of this byte specifies the physical bus width
of the system bus. ,Depending on the bus width
specified, the 8089 then fetches the address of the
system configuration block (SCB) contained in
locations FFFF8H through FFFFBH in either two
bus cycles (16-bit bus, Wbit equal 1) .or four bus
cycles (8-bit bus, W bit equal 0). The SCB offset
and segment address values fetched are combined
into a 20-bit physical address that is stored in an
internal register. Using this address, the 8089 next
fetches the system operation command (SOC)
byte. As explained in Chapter 3, this byte
specifies both the request/grant operational mode
(R bit) and the physical width of the 110 bus (I
bit). After reading the SOC byte, the 8089 fetches
the channel control block (CB) offset and segment address values. These values are combined
into a 20-bit physical address and are stored in
another internal register. To inform the host CPU
that it has completed the initialization sequence,
the 8089 clears the Channel. 1 Busy flag in the
channel control block by writing an all "zeroes"
byte to CB + 1.
elK
RESET
~J~~I~~ ~~~~~ \1---_ _ _ __
CYCLES
1-1 MIN-I
eLK
-----------~~~~~CA
CA
-----------J~-,
C-LK-M-1N~~~~ RECOGNIZED
Figure 4-28. RESET -CA Initialization Timing
Coincident with the trailing edge of the first
CA pulse following reset, the 8089 samples its
SEL (Select) input from the host processor to
determine master/slave status for its
request/grant circuity. If the SEL input is low,
the 8089 is designated a "master," and if the SEL
input is high, the 8089 is designated a "slave." As
a master, the 8089 assumes that it has the bus
initially, and it will subsequently grant the bus to
a requesting slave when the bus becomes available
(i.e., the 8089 will respond to a "request" pulse
on its RQ/GT line with a "grant" pulse). A single
8089 in the remote configuration (or one of two
8089s in a remote configuration) would be
designated a master. As a slave, the 8089 can only
request the bus from a master processor (Le., the
8089 initiates the request/grant sequence by outputting a "request" pulse on its RQ/GT line). An
8089 that shares a bus with an 8086 or 8088 (or
one of two 8089s in a remote configuration)
would be designated a slave. Note that since the
8086 and 8088 CPUs can grant the bus only in
response to a request, whenever an 8086 or 8088
After the lOP has been initialized, the system
configuration block may be altered in order to initialize another lOP. Once an lOP has been initialized, its channel control block in system
memory cannot be moved since the CB address,
which is internally stored by the lOP during the
initialization sequence, is automatically accessed
on every subsequent CA pulse.
4-45
HARDWARE REFERENCE INFORMATION
parameter block and writing the address of
the parameter block in the channel control
block.
As previously stated, the generation of the CA
and SEL inputs to the lOP are the responsibility
of the host CPU. Typically, these signals result
from the CPU's execution of an 110 write
instruction to one of two adjacent 110 ports (110
port addresses that only differ by AD). Figure 4-29
illustrates a simple decoding circuit that could be
used to generate the CA and SEL signals. Note
that by qualifying the CA output with 10WC, the
SEL output, since it is latched for the entire 110
bus cycle, is guaranteed to be stable on the trailing
edge of the CA pulse. .
•
Issue a channel attention (CA) to the
specified channel.
In response to the CA, the 8089 interrupts any
current activity at its first opportunity (see "Concurrent Channel Operation" in section 3.2) and
begins execution of an internal instruction
sequence that fetches and decodes the channel
command word (CCW) and then performs the
operation indicated (i.e., start, halt or continue
channel program execution).
A7
If the CCW specifies start channel program (start
AS
task block execution), the address of the
parameter block is fetched from the channel
control block, the address of the first channel
program instruction (contained in the first four
bytes of the parameter block) is fetched and then
loaded into the TP (task pointer) register and,
finally, task block execution is initiated from
either system or 110 space. Task block execution
continues, subject to the activity on the other
channel as described in "Concurrent Channel
Operation," until a XFER instruction is
executed. Following execution of this instruction,
the next sequential channel program instruction is
executed before the channel enters the DMA
transfer mode.
As
A4
S30
A3
A2
AI
CA
iOWC
.. SEL
Au
PORT FC=CHANNEL I CA
PORT FD = CHANNEL 2 CA
Figure 4-29. Channel Attention Decoding Circuit
1/0 Dispatching
If the CCW specifies halt channel, the current
operation on the specified channel is halted. If the
channel is performing task block execution (either
chained or not chained), channel operation is
stopped at an instruction boundary, and if the
channel is performing a DMA transfer, channel
operation is stopped at a DMA transfer cycle
boundary. Note that a channel will not stop a
locked DMA transfer until the operation is completed. There are two unique halt channel commands. One command simply halts the channel
and clears the busy flag in the channel control
block. This command is used when the halted
operation is to be discarded. The other command
halts the channel, saves the task pointer and program status word (PSW) byte, and clears the busy
flag. This command is used when the halted
operation is to be resumed. Note that this halt
command will not affect the integrity of resumed
task block execution or a memory-to-memory
DMA transfer, but could affect the integrity of a
synchronized DMA transfer (a DMA request
occuring while the channel is halted could be
missed).
During normal operation, the 110 supervisory
program running in the host CPU will receive a
request to perform a specific 110 operation on
one of the 8089's channels. In response to this
request, the supervisory program will typically
perform the following sequence of operations:
•
Check the availability of the specified
channel by examining the channel's busy flag
in the Channel Control Block. If it is possible
for another processor to access the channel, a
semaphore operation (implemented by a
locked XCHG instruction) is used to check
channel availability.
•
Load the variable parameters required for
the intended operation into the channel's
parameter block.
•
Load the channel command word (CCW)
into the channel control block.
•
Establish the necessary linkages by writing
the starting address of the channel program
(task block) in the first four bytes of the
Mnemonics © Intel, 1979
4-46
HARDWARE REFERENCE INFORMATION
If the CCW specifies continue channel, an operation that has been previously halted is resumed
(and the busy flag is set). Since this command
restores the task pointer and. PS W, it should be
used only if the task pointer and PSW have been
saved by a previous halt command.
address boundary (odd or even address). The
8089 performsDMA transfers between dissimilar
bus widths by assembling bytes or disassembling
words in its internal assembly register file. As
explained in Chapter 3, the DMA source and
destination bus widths are defined by the execution of a WID instruction during task block
(channel command) execution. Note that the bus
widths specified remain in force until changed by
a subsequent WID instruction. Table 4-18 defines
the various byte (B) and word (W)
source/ destination transfer combinations based
on address boundary and bus width specified.
Table 4-17 outlines the various CCW command
execution times. Note that the times listed in the
table for the halt commands do not include the
time required to complete any current channel
activity when the channel attention is received
(completion of the current DMA transfer cycle or
task block instruction).
DMA Transfers
The 8089 additionally optimizes bus accesses during transfers between dissimilar bus widths
whenever possible. When either the source or
destination is a 16-bit memory bus (autoincrementing) that is initially aligned on an odd
The number of bytes transferred during a single
DMA cycle is determined by both the source and
destination logical bus widths as well as by the
Table 4-17. CCW Command Execution Times
CCWCommand
Minimum Time·
Maximum Time··
CANOP
CA Halt (no save)
CA Halt (with save)
CA Start (memory)
CA Start (110)
CA Continue
48 + 2n clocks
48 + 2n clocks
94 + 5n clocks
108 + 6n clocks
96 + 5n clocks
95 + 5n clocks
48 + 2n clocks
48 + 2n clocks
100 + 6n clocks
124 + 10n clocks
108 + 8n clocks
103 + 6n clocks
Notes:
n is the number of wait states per bus cycle.
*
Minimum time occurs when both the channel control block and parameter block addresses are aligned on
an even address boundary and a 16-bit bus is used.
Maximum time occurs when both the channel control block and parameter block addresses are aligned
on an odd address boundary on a 16-bit bus or when an 8-bit bus is used.
Table 4-18. DMA Assembly Register Operation
Logical Bus Width
(Source - Destination)
Address Boundary
(Source - Destination)
Even Even Odd Odd -
Even
Odd
Even
Odd
4-47
8-8
8-16
16 - 8
16-16
B-B
B-B
B-B
B-B
BIB - W
B-B
B/B-W
B-B
W-B/B
W- BIB
B-B
B-B
W-W
W- BIB
B/B-W
B-B
Mnemonics © Intel, 1979
HARDWARE REFERENCE INFORMATION
address boundary (causing the first transfer cycle
to be byte-to-byte), following the first transfer
cycle, the memory address will be aligned on an
even address boundary, and word transfers will
subsequently occur. For example, when performing a memory-to-port transfer from a 16-bit bus
to· an 8-bit bus with the source beginning on an
odd address boundary, the first transfer cycle will
be byte-to-byte (B --- B) as indicated in table 4-18,
but subsequent transfers will be word-tobytelbyte (W --- BIB).
The DRQ input is asynchronous and usually
originates from an I/O device controller rather
than from a memory circuit. This input is latched
on the positive transition of the clock (CLK)
signal and therefore must remain active for more
than one clock period (more than 200
nanoseconds when using a 5 MHz clock) in order
to guarantee that it is recognized.
During state T 1 of the associated fetch bus cycle
(source synchronized) or store bus cycle (destination synchronized), the lOP outputs the address
of the 1/0 device (the port address). This address
must be decoded (by external circuitry) to
generate the DMA acknowledge (DACK) signal
to the 1/0 controller as the response to the controller's DMA request. An I/O controller will
typically use DACK as a conditional input for the
removal of DRQ. (After receipt of the DACK
signal, most Intel peripheral controllers deactivate DRQ following receipt of the corresponding read or write signal.) Figures 4-30 and 4-31
illustrate the DRQ/DACK timing for both source
synchronized (i.e., port-to-memory) and destination synchronized (i.e., memory-to-port)
transfers.
All DMA transfer cycles consist of at least two
bus cycles; one bus cycle to fetch (read) the data
form the source into the lOP, and one bus cycle
to store (write) the data previously fetched from
the lOP into the destination. Note that in all
transfers, the data passes through the lOP to
allow maskl compare and translate operations to
be optionally performed during the transfer as
well as to allow the data to be assembled or
disassembled.
The lOP performs DMA transfers in one of three
modes: unsynchronized, source synchronized or
destination synchronized (the transfer mode is
specified in the channel control register). The unsynchronized mode is used when both the source
and destination devices do not provide a data request (DRQ) signal to the lOP as in the case of a
memory-to-memory transfer. In the synchronized
transfer modes, the source (source synchronized)
or destination (destination synchronized) device
initiates the transfer cycle by activating the lOP's
DRQl (channell) or DRQ2 (channel 2) input.
I
Table 4-19 defines the DMA transfer cycles in
terms of the number of bus and clock cycles required. Note that the number of clocks required
to complete a transfer cycle does not take into account the effects of possible concurrent operations on the other channel or wait states within
any of the bus cycles.
.
TRANSFER CYCLE
--FETCH BUS C Y C L E - - I - - ' STORE BUS CYCLE-~
q
~
~
~
q
~
~
I
ClK
DRO HOLD
FROM READ
DRQ 2
(FROM 110 DEVICE)
(DECODED I/O
I
I
-1-1
I-
2 IDLE
I
I
I
I
4 IDLE
I
SIDLE
,---------------------\\\\\\~\\\\\\\\ ! .
ClOCKS'--CLOCKS'- -ClOCKS'DRO FOR NEXT TRANSFER CYCLE
ADD~~~:) ~ VALID 110 ADDRESS PRESENT \ _ _ _ _ _ _ _ _ _ __
NOTES:
1. INDICATES THE NUMBER OF IDLE CLOCK CYCLES INSERTED BEFORE THE NEXT
TRANSFER CYCLE BEGINS. IF ORO IS RECEIVED PRIOR TO STATE T4 OF THE CURRENT
FETCH CYCLE, THE NEXT FETCH CYCLE BEGINS IMMEDIATELY FOLLOWING THE
CURRENT STORE CYCLE.
2. IF THE 8089 IS IDLE WHEN ORO IS RECOGNIZED, FIVE IDLE CLOCK CYCLES OCCUR
BEFORE THE ASSOCIATED TRANSFER CYCLE IS INITIATED.
Figure 4-30. Source Synchronized Transfer Cycle
4-48
HARDWARE REFERENCE INFORMATION
elK
i--I
ORO HOLD
__________
FR_O_M_W_RIT_E-m=:m '
AOO~~~~
CLOCKS l
CLOCKS]
~
,f~;a~~;N_;XT TRANSFER CYCLE
~ _
ORO·
(fROM 110 DEVICE)
(DECODED I/O
1_2 'DLE~I_4 IDLE-I_S
......J! VALID
_________
NOTES:
IDLE CLOCKS J -
_
-t-------~=
I .
~
~
•
,r-----
_
L
...JI
1/0 ADDRESS PRESENT \\.. _ _ _ _ _ _ _ _ _ _ _
1. FIRST DMA FETCH CYCLE OCCURS IMMEDIATELY AFTER THE LAST TASK BLOCK
INSTRUCTION 15 EXECUTED.
2. FETCH BUS CYCLE 2 BEGINS IMMEDIATELY FOLLOWING STORE BUS CYCLE 1.
3. INDICATES THE NUMBER OF IDLE CLOCK CYCLES INSERTED BEFORE STORE BUS
CYCLE 2 BEGINS. IF ORO IS RECEIVED PRIOR TO STATE 14 OF STORE BUS CYCLE 1,
STORE BUS CYCLE 2 BEGINS IMMEDIATELY FOLLOWING FETCH BUS CYCLE 2.
4. IF THE 8089 IS IDLE WHEN ORO IS RECOGNIZED, FIVE IDLE CLOCK CYCLES OCCUR
BEFORE THE ASSOCIATED STORE BUS CYCLE IS INITIATED.
Figure 4-31. Destination Synchronized Transfer Cycle
Table 4-19. DMA Transfer Cycles
Transfer Mode
Logical Bus Width
Unsynchronized
Source Destination
8
8
16'
16'
8
16'
8
16'
Bus Cycles
Required
2 (1 fetch,
3 (2 fetch,
3 (1 fetch,
2 (1 fetch,
1 store)
1 store)
2 store)
1 store)
Source Synchronized
Total '
Clocks
8'
12
12
8
Bus Cycles
Required
2 (1 fetch,
3 (2 fetch,
3 (1 fetch,
2 (1 fetch,
1 store)
1 store)
2 store)
1 store)
Total'
Clocks
8'
16'
12
8
Destination Synchronized
BusCycles
Required
2 (1 fetch,
3 (2 fetch,
3 (1 fetch,
2 (1 fetch,
1 store)
1 store)
2 store)
1 store)
Total'
Clocks
8'
12
16'
8
Notes:
1. The "Total Clocks Required" does not include wait states. One clock cycle per wait state must be
added to each fetch and/or store bus cycle in which a wait state is inserted. When performing a
memory-to-memory transfer, three additional clocks must be added to the total clocks required (the
first fetch cycle of any memory-to-memory transfer requires seven clock cycles).
2.
When performing a translate operation, one additional 7-clock bus cycle must be added to the values
specified in the table.
3.
Word transfers in the table assume an even address word boundary. Word transfers to or from odd
address boundaries are performed as indicated in table 4-18 and are subject to the bus cycle/clock
requirements for byte-to-byte transfers.
4.
Transfer cycles that include two synchronized bus cycles (i.e., synchronous transfers between
dissimilar logical bus widths) insert four idle clock cycles between the two synchronized bus cycles
to allow additional time for the synchronzing device to remove its initial DMA request.
4-49
HARDWARE REFERENCE INFORMATION
more than one terminate condition is possible,
displacements (which are added to the task
pointer register value) are specified to cause task
block execution to resume at a unique entry point
for each condition. Three reentry points are
available: TP, TP + 4 and TP + 8. The time interval between the occurrence of a terminate condition and the resumption of task block execution is
12 clock cycles for reentry point TP and 15 clock
cycles for reentry points TP + 4 and TP + 8.
DACK latency is defined as the time required for
the 8089 to acknowledge, by outputting the
device's corresponding port address, a DMA
request at its PRQ input. This response latency is
dependent on a number of factors including the
transfer cycle being performed, activity on the
other channel, memory address boundaries, wait
states present in either bus cycle and bus arbitration times.
Generally, when the other channel is idle, the'
maximum DACK latency is five clock cycles (l
microsecond at 5 MHz), excluding wait states and
bus arbitration times. An exception occurs when
performing a word transfer to or from an' odd.
memory address boundary. This operation, since
two store (source synchronized) or two fetch
(destination synchronized) bus cycles are required
to access memory, has a maximum possible latency of nine clock cycles. When the other channel is
performing DMA transfers of equal priority
("P" bits equal), interleaving occurs at bus cycle
boundaries, and the maximum latency is either
nine clock cycles when the other channel is performing a normal 4-clock fetch or store bus cycle.
or twelve, clock cycles when the other channel is
performing the first fetch cycle of a memory-tomemory transfer. If the other channeUs performing "chained" task block instruction execution of
equal priority, maximum latency can be as high as
12 clock cycles (channel command instruction
execution is interrupted at machine cycle boundaries which range from two to eight clock
cycles).
DMA Termination
As stated in Chapter 3, a channel can exit the
DMA transfer mode (and return to task block
execution) on any of the following terminate
conditions:
•
•
•
Single cycle transfer
Byte count expired
Mask/ compare match or mismatch
•
External event
Peripheral Interfacing
When interfacing a peripheral to an 8-bit physical
data bus, the 8089 uses only the lower half of the
address/data lines (AD7-ADO) as the bidirectional data bus, and the upper half of the address/ data lines (AD 15-AD8) maintain address
information for the entire bus cycle. Consequently, with this bus configuration, only one octal
latch (e.g., an Intel® 8282/83 Octal Latch) is required since only the lower half of the address/data lines is time-multiplexed (unless the
address bus requires the increased current drive
capability and capacitive load immunity provided
by the latch).
When interfacing a peripheral to a 16-bit data
bus, both the lower and upper halves of the address/ data lines are time-multipelxed, and two octal latches are required. Note that unlike the 8086
and 8088 CPUs, the 8089 does not time-multiplex
. BHE (this signal is valid for the entire bus cycle).
Both 8- and 16-bit peripherals can be interfaced to
a 16-bit bus. An 8-bit peripheral can be connected
to either the upper or lower half of the bus. An 8bit peripheral on the lower half of the bus must
use an even source/destination address, and an 8bit peripheral on the upper half of the bus must
use an odd source/destination address. TO.take
advantage of word transfers, a 16-bit peripheral
must use an even source/ destination address.
To prepare a peripheral device for a DMA
transfer, command and parameter data is written
to the device's command/status port. This is
usually. accomplished using pointer register GC.
Recalling that the 8089 executes one additional
task block instruction following execution of the
XFER instruction (the XFER instruction causes
the 8089 to enter the DMA mode), this additional
instruction is used to access the command port of
an· I/O device that' immediately begins DMA
The terminate conditions are. specified by individual fields in the channel control register.
More than one terminate condition can be
specified for a transfer (e.g., a transfer can be terminated when a specific byte count is reached or
on the occurrence of an external event). When
Mnemonics © Intel, 1979
4-50
HARDWARE REFERENCE INFORMATION
operation on receipt of the last command (the
8271 Floppy Disk Controller begins its DMA
transfer on receipt of the last command
parameter). Since a translate DMA operation requires the use of all three pointer registers (GA
and GB specify the source and destination addresses; GC specifies the base address of the
translation table), when it is necessary to use the
last task block instruction to start the device,
command port access can be accomplished
relative to one of the pointer registers or relative
to the PP register. If the device's data port address (GA or GB) is below the device's command
port address, either an offset or an indexed
reference can be used to access the command
port.
individual DMA acknowledge (DACK) is returned to only the active device. DACK decoding can
be accomplished with an Intel ® 8205 Binary
Decoder or a ROM circuit. Note that the 8089 can
only determine which device has requested service
or terminated by the context of the task block
program.
Most peripheral devices interfaced to the 8089 will
use the decoded DMA acknowledge signal
(DACK) as the "chip select" input. Peripheral
devices that do not follow this convention must
use DACK as a conditional input of chip select. .
While most interrupts associated with the 8089
will be DMA requests or external terminates, nonDMA related interrupts can additionally be
supported.
A peripheral's (or peripheral controller's) DMA
communication protocol with the 8089 is as
follows:
•
The peripheral (when source or destination
synchronized) initiates a DMA transfer cycle
by activating the 8089's DRQ (DMA request)
input.
•
The 8089 acknowledges the request by
placing the peripheral's assigned data port
address on the bus during state T 1 of the corresponding fetch (source synchronized) or
store (destination synchronized) bus cycle.
The peripheral is responsible for decoding
this address as the DMA acknowledge
(DACK) to its request.
•
The data is transferred between the
peripheral and the 8089 during the T 2
through T4 state interval of the bus cycle.
The peripheral must remove its DMA request
during this interval.
•
The peripheral, when ready, requests another
DMA transfer cycle by again activating the
DRQ input, and the above sequence is
repeated.
•
The peripheral can, as an option, end the
DMA transfer by activating the 8089's EXT
(external terminate) input.
One technique that would be used when an 8089 is
the local configuration (or when an 8086 or 8088
and an 8089 are locally connected as a remote
module) is to allow the CPU to accept the interrupt and then direct the 8089 to the interrupt service routine. Another technique is to allow the
8089 to "poll" the device to determine when an
interrupt has occurred (most peripheral controllers have an interrupt pending bit in a status
word). The 8089's bit testing instructions are
ideally suited for polling.
When the 8089 is in a remote configuration, nonDMA related interrupts can be supported with the
addition of an Intel® 8259A Programmable
Interrupt Controller. Systems that require this
type of interrupt structure would dedicate one of
the 8089's channels to interrupt servicing. In
implementing this structure, the interrupt output
from the 8259A is directly connected to the channel's external terminate (EXT) input, and the
channel's DMA request (DRQ) input is not used.
A task block program is initially executed to perform a source-synchronized DMA transfer (with
an external terminate) on the "interrupt" channel
to "arm" the interrupt mechanism. Since the
DRQ input is not used, when the channel enters
the DMA transfer mode, the channel idles while
waiting for the first DMA request (which never
occurs). The other channel, since the interrupt
channel is idle, operates at maximum throughput.
When an interrupt occurs, the "pseudo" DMA
transfer is immediately terminated, and task
block instruction execution is resumed. The task
block program would write a "poll" command to
the 8259A's command port and then read the
I
The 8089 can support mulitple peripheral devices
on a single channel provided that only one device
is in the active transfer mode at anyone time. To
interface mUltiple devices, the DMA request
(DRQ) lines are OR'ed together as are the external terminate (EXT) lines. Unique port addresses
are, however, assigned to each device so that an
4-51
HARDWARE REFERENCE INFORMATION
8259A's data port to acknowledge the interrupt
and to determine the device responsible for the
interrupt (the device is identified by a 3-bit binary
number in the associated data byte). The device
number read would be used by the task block program as a vector into a jump table for the device's
interrupt service routine. Pertinent interrupt data
could be written into the associated parameter
block for subsequent examination by the host
(table 4-24) and a table to "disassemble" any
machine instruction back into its associated
assembly language equivalent (table 4~26).
Figure 4-32 shows the format of a typical 8089
machine instruction. Except for the LPDI and
memory-to-memory forms of the MOV and
MOVB instructions that are six bytes long, all
8089 machine instructions consist of from two to
five bytes. The first two bytes are always present
and are generally formatted as shown· in . figure
4"32 (table 4-24 contains the exact encoding of
every instuction).
processor~
The interrupt mechanism previously described,
since it uses the 8089's external terminate function, provides an extremely fast interrupt
response time.
.
Bits 5 through 7 of the first byte of an instruction
comprise the R/B/P field. This field identifies a
register, bit select or pointer register operand as
outlined in table 4-20.
Note that when using dynamic RAM memory
with the 8089, an Intel® 8202 Dynamic RAM
Controller can be used to simplify the interface
and to perform the RAM refresh cycle. When
maximum transfer rates are required, the RAM
refresh cycle can be externally initiated by the
8089. By connecting the decoded DACK (DMA
acknowledge) signal to the 8202's REFRQ
(refresh request) input, the refresh cycle will occur
coincident with the I/O device bus cycle and
therefore will not impose wait states in the
memory bus cycle.
Table 4-20. R/B/P Field Encoding
Instruction Encoding
Most 8089 programming will be performed atthe
assembly language level using ASM-89,the 8089
assembler. During program debugging, however,
it may be necessary to work directly with machine
instructions when monitoring the bus, reading unformatted memory dumps, etc. This section contains both a table to encode any ASM-89 instruction into its corresponding machine instruction
BYTE 1
I I I
R/B/PI WB I AA
Iw
III II II
OPCODE
Register
Bit
Pointer
000
001
010
011
100
101
110
111
GA
GB
GC
BC
TP
0
1
2
3
4
5
6
7
GA
GB
GC
N/A
TP
N/A
N/A
N/A
IX
CC
MC
The WB field (bits 3 and 4 of the first byte) indicates how many displacement! data bytes are
present in the instruction as outlined in table 4-21.
The displacement bytes are used in program
transfers; one byte is present for short transfers,
while long transfers contain a two-byte (word)
displacement. As mentioned in Chapter 3, the
- ~Y~:" - 4- - ~~ ~ - -I- - ~~ ~ - -I
BY TE 2
I I I
Code
1
IMM
L
I
I
I
I
OFFSET
I
I LOW DISP/DATA I HIGH DISP/DATA I
_____ L
_____
~~----~
BASE REGISTER FOR MEMORY OPERAND
OPERATION (INSTRUCTION) CODE
WIDTH (BYTE OR WORD OPERANDS)
MEMORY ADDRESSING MODE
NUMBER OF DISPLACEMENTIDATA BYTES
REGISTER, BIT, POINTERSELECT
Figure 4-32. Typical 8089 Machine Instruction Format
Mnemonics © Inlel, 1979
I
11~111+111Ll11+111Ll11~
4-52
HARDWARE REFERENCE INFORMATION
displacement is stored in two's complement notation with the high-order bit indicating the sign.
Data bytes contain the value of an immediate constant operand. A byte immediate instruction
(e.g., MOVBI) will have one data byte, and a
word immediate instruction (e.g., ADDI) will
have two bytes (a word) of immediate data. An
instruction may contain either displacement or
data bytes, but not both (the TSL instruction is an
exception and contains one byte of displacement
and one byte of data). If an offset byte is present,
the displacement/data byte(s) always follow the
offset byte.
Bits 7 through 2 of the second instruction byte
specify the instruction opcode. The opcode, in
conjunction with the W field of the first byte,
identifies the instruction. For example, theopcode "1110 11" denotes the decrement instruction; if W=O, the assembly language instruction is
DECB, while if W=I, the instruction is DEC.
Table 4-26 lists, in hexadecimal order, the opcode
of every assembly language instruction.
The MM field (bits 0 and 1) indicates which
pointer (base) register is to be used to construct
the effective address of a memory operand. Table
4-23 defines the MM field encoding. (Memory
operand addressing is described in section 3.8.)
Table 4-21. WB Field Encoding
Table 4-23. MM Field Encoding
Interpretation
Code
No displacement/data bytes
One displacement/data byte
Two displacement/data bytes
TSL instruction only
00
01
10
11
The AA field specifies the addressing mode that
the processor is to use in order to construct the effective address of a memory operand. Four ad~
dressing modes are available as outlined in table
4-22. (Address modes are described in detail in
section 3.8.)
Code
Base Register
00
01
10
11
GA
GB
GC
pp
When the AA field value is "01" (base register
+ offset addressing), the third byte of the instruction contains the offset value. This unsigned value
is added to the content of the base register
specified by the MM field to form the effective
address of the memory operand.
Table 4-22. AA Field Encoding
Code
00
01
10
11
When the AA field value is "10," the IX register
value is added to the content of the base register
specified by the MM field to provide a 64k range
of effective addresses. (Note that the upper four
bits of the IX register are not sign-extended.)
Interpretation
Base register only
Base register plus offset
Base register plus IX
Base register plus IX,
auto-increment
When the AA field value is "11," the IX register
value is added to the base register value to form
the effective address as described for an AA field
value of "10." In this addressing mode, however;
the IX register value is incremented by one after
every byte accessed.
Bit 0 of the first instruction byte indicates whether
the instruction operates on a byte (W=O) or a
word (W=I).
Table 4-24. 8089 Instruction Encoding
DATA TRANSFER INSTRUCTIONS
MOV ;:; Move word variable
76543210
76543210
76543210
Memory to register
RRROOAAl
100000MM
offset if AA=01
Register to memory
RRROOAAl
100001MM
offset if AA=01
Memory to memory
OOOOOAAl
100100MM
offset if AA=01
4-53
76543210
76543210
OOOOOAA11110011MM
76543210
I
offset if AA=01
I
Mnemonics © Intel, 1979
HARDWARE REFERENCE INFORMATION
Table 4-24.8089 Instruction Encoding (Cont'd.)
DATA TRANSFER INSTRUCTIONS (Conl'd.)
Mova = Move byte variable
76543210765.4321076543210765432107654321076543210
Memory to register
RRROOAAO
100000MM
offset If AA""01
Reglsterto memory
RRROOAAO
100001MM
olls.ll1 AA=Ol
Memory to memory
OOOOOAAO
100100MM
offset if AA-01
MOYBI = Move byte Immedla~e
Immediate to register
Immediate to memory
= Move word immediate
MOVI
Immediate to register
Immediate to memory
MOVP
:III
Move pointer
Memory to pointer register
Pointer register to memory
LPD
= load pointer with doubleword variable
LPDI
offset if AA=01
= Loa'd pointer. with doubleword immediate
ARITHMETIC INSTRUCTIONS
ADD
= Add word variable
Memory to register.
off'.111 AA=Ol
Reglsterto memory
offset if AA=01
ADDB
= Add byte variable
Memory to register
Register to memory
ADDI
= Add word immediate
Immediate to register
Immediate to memory
Mnemonics © Intel, 1979
4-54
o0
0 O. 0 A A
~
11 1 a 0 11M M
I
offset If AA .. 01
J
HARDWARE REFERENCE INFORMATION
Table 4-24.8089 Instruction Encoding (Cont'd.)
ARITHMETIC INSTRUCTIONS (Cont'd.)
AD OBI = Add byte Immediate
76543210
76543210
76543210
76543210
76543210
76543210
Immedaite to register
Immediate to memory
INC = Increment word by 1
Register
Memory
INCB
= Increment byte by 1
1000 a 0 A
A 0
1111 0 10M M
offset If AA=Ol
11
offsetlf AA=Ol
DEC = Decrement word by 1
Register
Memory
CECB = Decrement byte by 1
I
0 0 0 :0 0' A A 0
1 1 0 1·1 M M
LOGICAL AND BIT MANIPULATION INSTRUCTIONS
AND
=
AND word variable
Memory to register
Register to memory
ANDB = AND byte variable
Memory to register
Register to memory
ANDI
= AND word immediate
Immediate to register
Immediate to memory
ANDBI
= AND byte Immediate
Immediate to register
Immediate to memory
OR
= OR word variable
Memory to register
Register to memory
Mnemonics © Intel, 1979
HARDWARE REFERENCE INFORMATION
Table 4-24.8089 Instruction Encoding (Cont'd.)
LOGICALANO BIT MANIPULATION INSTRUCTIONS (Cont'd.)
ORB = OR byte variable
78543210
78543210
78543210
78543210
Memory to register
Reglsterto memory
ORI
= OR word immediate
Immediate to register
Immediate to memory
ORBI = OR byte immediate
Immediate to register
Immediate to memory
NOT = NOT word variable
Register
RRROOOOO
00101100
Memory
OOOOOAAI
110111MM
offset If AA=01
Memory to register
RRROOAAI
101011MM
offset If AA=01
I
I
= NOT byte variable
NOTS
Memory
Memory to register
= Set bit to 1
offset If AA=01
= Clear bit to 0
offset If AA=01
SETB
CLR
PROGRAM TRANSFER INSTRUCTIONS
'CALL
= Call
LCALL
= Long call
= Jump unconditional
l'
LJMP = Long Jump unconditional
l'
"JMP
0001000 10
0010001
I
0
a1 aaaaa
disp-6
a1 aaaaa
dlsp-iO
*The ASM-89 Assembler will automatically generate the long form of a program transfer instruction when the
target is known to be beyond the byte·displacement range.
Mnemonics © Inlel, 1979
4-56
dlsp-hl
78543210
78543210
HARDWARE REFERENCE INFORMATION
Table 4-24. 8089 Instruction Encoding (Cont'd.)
PROGRAM TRANSFER INSTRUCTIONS (Cont'd.1
*JZ
= Jump If word is 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6' 5 4 3 2 1 0
1 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Label to register
Label to memory
LJZ
= Long jump if word Is 0
Label to register
Label to memory
*JZB
= Jump if byte is 0
LJZB = Long jump if byte Is 0
*JNZ
= Jump If word natO
Label to register
Label to memory
LJNZ
= Long Jump If word notO
Label to register
Label to memory
*JNZB
= Jump if byte not 0
LJNZB = Long Jump if byte not 0
*JMCE = Jump If masked compare equal
LJMCE = Long Jump If masked compare equal
*JMCNE = Jump if masked compare not equal
LJMCNE = Long jump If masked compare notequai
~
______
~
______-L______-L______
~
______
~
·JeT = Jump if bit is 1
*The ASM-89 Assembler will
a~tomatically
generate the long form of a program transfer instruction when the
target is known to be beyond the byte-displacement range.
4-57
Mnemonics © Intel, 1979
HARDWARE REFERENCE INFORMATION
Table 4-24; 8089 Instruction Encoding (Cont'd.)
PROGRAM TRANSFER INSTRUCTIONS (Conl'd.)
7 6 5 4 3 2 1 0
LJBT
7 6 5 4 3 21 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 I 0
7 6 5 4 3 2 1 0
7 6 5 43 2 1 0
= long Jump If bit Is 1
·JNBT
=Jump if bit Is not 1
LJNBT = Long jump if bit Is not 1
PROCESSOR CONTROL INSTRUCTIONS
TSL
= Test and set while locked
WID
= Set logical bus widths
l' s
D'
I
aaaaa a a a a a a a a
·S=source width, D=destination width; 0=8 bits, 1=16 bits
XFER
SINTR
= Enter DMA mode
=Set interrupt service bit
Ia
1 1
a a a a 01 a a a a 0 a 00
101000000100000000
HLT = Halt channel program
100100000 101 001 000
NOP = No operation
10
aaaaaaa
100
aaaaaa
·The ASM·89 Assembler will automatically generate the long ~orm of a program transfer Instruction when the
target is known to be beyond the byte·displacement range.
assembled machine instruction into its ASM-89
symbolic form. The preceding table (table 4-25)
defines the notation used in table 4-26.
Table 4-26 lists all of the 8089 machine instructions in hexadecimal/binary order by their second
byte. This table may be used to "decode" an
Mnemonics © Intel, 1979
4-58
HARDWARE REFERENCE INFORMATION
Table 4-25. Key to 8089Machine Instruction Decoding Guide
Identifier
Explanation
S
0
PPP
RRR
AA
BBB
offset-Io
offset-hi
segment-Io
segment-hi
data-8
data-Io
data-hi
disp-8
disp-Io
disp-hi
(offset)
Logical width of source bus; 0=8, 1=16
Logical width of destination bus; 0=8, 1=16
Pointer register encoded in R/BIP field
Register encoded in R/BI P field
AA (addressing mode) field
Bit select encoded in R/B/P field
Low-order byte of offset word in doubleword pOinter
High-order byte of offset word in doubleword pointer
Low-order byte of segment word in doubleword pointer
High-order byte of segment word in doubleword pOinter
8-bit immediate constant
Low-order byte of 16-bit immediate constant
High-order byte of 16-bit immediate constant
8-bit signed displacement
Low-order byte of 16-bit signed displacement
High-order byte of 16-bit signed displacement
Optional 8-bit offset used in offset addressing
Table 4~26. 8089 Machine Instruction Decoding Guide
Byte 2
Byte 1
00000000
01000000
15000000
01100000
Hex
Binary
00
00
00
00
01
00000000
00000000
00000000
00000000
00000001
+
PPP10001
07
08
09
RRR01000
RRR10001
10001000
10010001
1F
20
20
20
20
21
RRR01000
RRR10001
23
24
24
25
+
+
+
RRR01000
27
28
Bytes 3, 4, 5, 6
NOP
SINTR
WID source-width,dest-width
XFER
}
+
00000111
00001000
00001001
offset-Io,offset-hi,segment-Io,segment-hi
}
data-8
data-Io,data-hi
not used
notused
ORBI register,immed8
ORI register,immed16
}
+
00100111
00101000
ptr-reg,immed32
ADDBI register,immed8
ADDI register, immed16
JMP short-label
LJMP long-label
data-8
data-Io,data-hi
disp-8
disp-Io,disp-hi
+
00100011
·00100100
00100100
00100101
not used
LPDI
}
+
00011111
00100000
00100000
00100000
00100000
00100001
ASM89 Instruction Format
data-8
not used
ANDBI
4-59
register,immed8
Mnemonics ©lntel; 1979
HARDWARE REFERENCE INFORMATION
Table 4-26. 8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1
RRR10001
Byte2
Hex
28
29
+
RRR01000
, RRR10001
2F
30
30
31
RRROOOOO
37
38
39
00110111
00111000
00111001
RRROOOOO
3B
3C
3D
00111011
00111100
00111101
RRR01000
RRR10000
3F
40
40
41
RRR01000
RRR10000
43
44
44
45
00100000 .
47
48
49
+
+
+
+
+
00001AAO
+
00001AAO
00010AA1
t
00010AA1
4B
4C
+
.4F
4C
+
4F
50
+
RRROOAAO
7F
80
RRROOAAO
83
+
MnemOnics © Intel, 1979
ANDI
}
+
RRROOOOO
+
ASM89 Instruction Format
00101000 data-Io,data"hi
00101001
2B
2C
20
+
Bytes 3, 4, 5, 6
Binary
00101011
00101100
00101101
+
not used
NOT
}
,
00101111
00110000 data-8
00110000 data-Io,data-hi
00110001
}
}
}
disp-8
disp-Io,disp-hi
}
+
}
-. ,
(offset),data-8
,
}
(offset),data-Io,data-hi
_.
+
01111111
100000MM
100000MM
not used
not used.
..
'.
not used
..
HLT
+
+
register
JZ reg ister,short-Iabel
LJZ register,short-Iabel,.
01000111
01001000
01001001
010011MM
01010000
not used
JNZ register,short-Iabel
LJNZ register, long-label
t
+
register
DEC
+
010011MM
010011MM
not used
}
00111111
01000000 disp-8
01000000 disp-Io,disp-hi
01000001
01001011
010011MM
not used
INC
+
01000011
01000100
01000100
01000101
register·
MOVBI register,immed8
MOVI register,immed16
+
+
register,immed16
}
}
not used
}
MOVBI
}
MOVI
}
}
(offset)
4-60
mem8,immed8
,
mem16,immed16
,not used
:
MOVB register,mem8
HARDWARE REFERENCE INFORMATION
Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte2
Byte1
RRROOAA1
+
..
RRROOAA1
RRROOAAO
+
RRROOAAO
RRROOAA1
+
RRROOAA1
PPPOOAA1
+
PPPOOAA1
PPPOOAA1
+
PPPOOAA1
OOOOOAAO
+
OOOOOAAO
00000AA1
t
00000AA1
00011AAD
t
00011AAO
PPPOOAA1
t
PPPOOAA1
10001AA1
t
10001AA1
10010AA1
+
10010AA1
RRROOAAO
t
RRROOAAO
RRROOAA1
+
RRROOAA1
RRROOAAO
t
RRROOAAO
RRROOAA1
+
RRROOAA1
RRROOAAO
+
RRROOAAO
Hex
Binary
80
100000MM
+
+
83
84
100000MM
100001 MM
87
84
100001 MM
100001 MM
t
+
87
88
+
8B
8C
+
8F
90
t
93
90
t
93
94
t
97
98
t
9B
9C
t
9F
9C
+
9F
AO
+
+
}
(offset)
+
}
(offset)
+
100010MM
100011 MM
+
100011 MM
100100MM
t
100100MM
100100MM
t
100100MM
100101 MM
t
100101 MM
100110MM
t
100110MM
100111MM
t
100111 MM
100111 MM
t
100111MM
101000MM
+
101000MM
101000MM
A3
101000MM
101001 MM
A4
·t
A7
A4
+
A7
A8
+
AB
(offset)
+
+
100001MM
100010MM
A3
AD
t
}
}
}
}
}
}
}
}
}
}
}
}
}
}
+
t
101001MM
101001 MM
101001 MM
101010MM
101010MM
ASM89 Instruction Format
Bytes 3, 4, 5, 6
(offset)
(offset)
(offset)
(offset)
(offset),OOOOOAAD, 110011 M M,(offset)
(offset),OOOOOAA 1,110011 MM ,(offset)
(offset),data-8,disp-8
(offset)
(offset),disp-8
(offset),d isp-Io,disp-h i
(offset)
(offset)
(offset)
} MOV
}
}
}
}
}
}
}
}
}
register, mem16
mem16,register
MOV
ptr-reg, mem32
LPD
MOVP
ptr-reg,mem24
MOVB
mem8,mem8
MOV
mem16,mem16
TSL
}
}
mem8,immed8,short"label
mem24,ptr-reg
MOVP
mem24,short-label
CALL
LCALL
ADDB
} ADD
}
}
}
mem8,register
MOVB
register, mem8
register,mem16
register,mem8
ORB
OR
mem24, long-label
register ,mem16
ANDB
mem8, register
Mnemonics © Intel, 1979
HARDWARE REFERENCE INFORMATION
Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1
Byte 2
Hex
Binary
RRROOAA1
AS
101010MM
+
RRROOAA1
+
AB
RRROOAAO
AC
+
RRROOAAO
RRROOAA1
+
RRROOAA1
00001AAO
+
00001AAO
00010AAO
+
00010AAO
00001AAO
+
00001AAO
00010AAO
+
00010AAO
BBB01AAO
+
BBB01AAO
BBB10AAO
+
BBB10AAO
BBB01AAO
T
BBB01AAO
BBB10AAO
T
BBB10AAO
00001AAO
T
00001AAO
00010AA1
T
00010AA1
00001AAO
T
00001AAO
00010AA1
+
00010AA1
00001AAO
T
00001AAO
+
AF
AC
+
AF
BO
+
B3
BO
+
B3
B4
+
B7
B4
+
B7
BS
+
BB
BS
+
BB
BC
T
BF
BC
T
BF
CO
T
C3
CO
T
C3
C4
T
C7
C4
+
,
}
(offset)
}
+
}
(offset)
} NOTB
+
+
}
}
}
+
}
(offset),disp-S
+
}
(offset),disp-Io,disp-hi
+
}
(offset),disp-S
+
} (offset),disp-Io,disp-hi
}
}
}
}
}
}
}
+
}
}
T
}
,}
T
}
}
}
}
101011 MM
101011MM
101011 MM
101100MM
+
101100MM
101100MM
101100MM
101101 MM
101101 MM
101101 MM
101101 MM
101110MM
101110MM
101110MM
101110MM
101111 MM
101111MM
101111MM
101111MM
110000MM
110000MM
110000MM
'T
110000MM
110001 MM
(offset)
(offset),disp-S
(offset),disp-Io,disp-hi
(offset),disp-S
AND
(offset),data-S
(offset),data-Io,data-hi
memS,short-label
memS,long-label
JMCNE
memS,short-label
LJMCNE
JNBT
mem8,bit-select,long-label
AD OBI
+
}
}
ORBI
(offset), data-I 0, data-h i
(offset),data-8
ORI
memS,immedS
mem16,immed16
ANDBI
4-62
memS,immedS
mem16,immed16
ADDI
}
mem8,bit-select,long-label
memB,bil-select,short-label
LJBT
+
memS,long-label
memB,bit;select,short·label
LJNBT
}
}
110010MM
r,egister,mem16
LJMCE
} (offset),data-S
+
register,memS
JMCE
JBT
(offset),disp-Io,disp-hi
mem16,register
N9T
T
110001 MM
110001 MM
110001MM
110010MM
Mnemonics © Intel, 1979
ASM89 Instruction Format
+
101010MM
101011 MM
C7
C8
CB
Bytes 3, 4, 5, 6
mem8,immedS
HARDWARE REFERENCE INFQRMATION
Table 4-26. 8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1
00010AA1
t
00010AA1
Byte 2
Hex
Binary
CB
110010MM
CC
110010MM
11001100
CF
DO
11001111
110100MM
t
CB
t
RRROOAAO
t
t
t
t
}
(offset)
} ANDB mem8,register
t
} (offset)
} AND mem16,register
t
}
t
J
t
t
}
}
}
}
}
}
}
}
}
}
}
t
}
RRROOAAO
RRROOAA1
07
04
110101 MM
110101MM
RRROOAA1
RRROOAAO
07
DB
110101MM
110110MM
RRROOAAO
RRROOAA1
DB
08
110110MM
110110MM
RRROOAA1
RRROOAAO
DB
DC
110110MM
110111 MM
RRROOAAO
RRROOAA1
OF
DC
110111MM
110111MM
RRROOAA1
00001AAO
OF
EO
110111MM
111000MM
00001AAO
00001AA1
E3
EO
111000MM
111000MM
E3
EO
111000MM
111000MM
00010AAO
00010AA1
E3
EO
111000MM
111000MM
00010AA1
00001AAO
E3
E4
111000MM
111001 MM
00001AAO
00001AA1
E7
E4
111001 MM
111001MM
00001AA1
E7
111001MM
t
t
t
t
t
t
00001AA1
00010AAO
t
t
t
t
t
t
t
t
t
t
t
t
t
t
not used
t
110100MM
110101MM
t
}
mem16,immed16
}
}
03
04
t
ANDI
}
}
RRROOAA1
RRROOAAO
t
}
}
}
110100MM
110100MM
t
ASM89 Instruction Format
}
}
t
03
DO
t
} (offset),data-Io,data-hi
t
RRROOAAO
RRROOAA1
t
Bytes 3, 4, 5, 6
t
t
t
t
t
ADDB
(offset)
ADD
(offset)
ORB
(offset)
OR
(offset)
(offset)
(offset)
(offset),disp-8
(offset),disp-8
(offset),disp-Io,disp-hi
(offset),disp-Io,disp-hi
mem16,register
mem8,register
mem16,register
NOTB mem8,register
NOT mem16,register
JNZB mem8,short-label
JNZ mem16,short-label
LJNZB
mem8,long-label
LJNZ mem16,longlabel
} JZB
(offset),disp-B
memB,register
mem8,short-label
} JZ mem16,short-label
(offset),disp-8
4-63
Mnemonics © Intel, 1979
HARDWARE REFERENCE INFORMATION
Table 4"26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1
Byte 2
Hex
Binary
00010AAO
E4
111001 MM
t
t
00010AAO
00010AA1
t
00010AA1
OOOOOAAO
t
OOOOOAAO
000OOAA1
t
OOOOOAA1
OOOOOAAO
t
OOOOOAAO
OOOOOAA1
t
00000AA1
E7
E4
t
E7
E8
t
EB
E8
t
EB
EC
t
EF
EC
t
EF
FO
t
BBBOOAAO
t
BBBOOAAO
BBBOOAAO
t
BBBOOAAO
F3
F4
t
F7
F8
t
FB
FC
t
FF
Mnemonics © Intel, 1979
Bytes 3, 4, 5, 6
t
}
t
}
111001MM
111001 MM
111001MM
111010MM
t
111010MM
111010MM
t
111010MM
111011 MM
t
111011MM
111011MM
t
(offset) ,d isp-Io,d isp"hi
(offset),d isp-Io,d isp-hi
ASM89 Instruction Format
}
}
LJZB
LJZ
mem8,long-label
mem16,long-label
}
}
}
(offset)
}
(offset)
} INC
(offset)
} DECB
} (offset)
} DEC mem16
INCB
mem8
mem16
mem8
111011MM
11110000
t
} not used
11110000
111101MM
t
} (offset)
} SETB
t
} (offset)
} CLR
mem8,0-7
111101MM
111110MM
mem8,0-7
111110MM
11111100
t
} not used
11111111
4-64
Appendix A
Application Notes
A
APPENDIXA
APPLICATION NOTES
This appendix contains Intel application notes pertinent to the 8086 family microprocessors. The following
application notes, in the order listed, have been included within this appendix:
AP-67
AP-61
AP-50
AP-51
AP-59
AP-28A
AP-43
8086 System Design
Multitasking for the 8086
Debugging Strategies and Considerations for 8089 Systems
Designing 8086, 8088, 8089 Multiprocessing Systems with the 8289 Bus Arbiter
Using the 8259A Programmable Interrupt Controller
Intel® Multibus™ Interfacing
Using the iSBC-957™ Execution Vehicle for Executing 8086 Program Code
A-l/A-2
APPLICATION
NOTE
Ap·67
September 1979
© Intel Corporation 1979
A-3
AP-67
8086 System Design
Contents
1. INTRODUCTION
2. 8086 OVERVIEW AND BASIC SYSTEM
CONCEPTS
A.
B.
C.
D.
Bus Cycle Definition
Address and Data Bus Concepts
System Data Bus Concepts
Multiprocessor Environment
3. 8086 SYSTEM DETAILS
A.
B.
C.
D.
E.
F.
G.
Operating Modes
Clock Generation
Reset
Ready Implementation and Timing
Interrupt. Structure
Interpreting ihe 8086 Bus Timing Diagrams
Bus Control Transfer
4. INTERFACING WITH 1/0
5. INTERFACING WITH MEMORIES
6. APPENDIX
A-4
AP-67
1. INTRODUCTION
guage Reference Guide (9800749A), AP-28A MULTIBUS™ Interfacing (98005876B), INTEL MULTIBUS™
SPECIFICATION (9800683), AP-45 Using the 8202 Dynamic RAM Controller (9/l00809A), AP-51 Designing
8086, 8088, 8089 Multiprocessor Systems with the 8289
Bus Arbiter and Ap·59 Using the 8259A Programmable
Interrupt Controller. References to other Intel publica·
tions will be made throughout this note.
The 8086 family, Intel's new series of microprocessors
and system components, offers the designer an ad·
vanced system architecture which can be structured to
satisfy a broad range of applications. The variety of
speed, configuration and component selections avail·
able within the family enables optimization of a specific
design to both cost and performance objectives. More
Important however, the 8086 family concept allows the
designer to develop a family of systems providing multi·
pie levels of enhancement within a single design and a
growth path for future designs.
2. 8086 OVERVIEW AND BASIC SYSTEM CONCEPTS
2A. 8086 Bus Cycle Definition
The 8086 is a true 16-bit microprocessor with 16-bit internal and external data paths, one megabyte of memory
address space (2**20) and a separate 64K byte (2**16)
1/0 address space. The CPU communicates with its external environment via a twenty-bit time multiplexed address, status and data bus and a command bus. To
transfer data or fetch instructions, the CPU executes a
bus cycle (Fig. 2A 1). The minimum bus cycle consists of
four CPU clock cycles called T states. During the first T
state (T1), the CPU asserts an address on the twenty-bit
This application note is directed toward the implementation of the system hardware and will provide an introduction to a representative sample of the systems
conflgurable with the 8086 CPU member of the family.
Application techniques and timing analysis will be given
to aid the designer in understanding the system requirements, advantages and limitations. Additional Intel
publications the reader may wish to reference are the
8086 User's Manual (9800722A), 8086 Assembly Lan-
-T,-
ClK
----i
~
A 19/56,A 16/S3
X
-
--T,_
r----\
-v----,
-T:V'Tw
1~
.~
X
STATUS
AD DR
-
READY
-
X
T4-
ADDRESS A1S-Ao \
FLOAT
~
--- IX
r--
DATA IN D1swDO
1---
)(F~~
----_.
-----
RD
READ
CYCLE
V
DT/R
1\
DEN
AD1S-ADo
X
ADDRESS
V
~
DATA OUT
WRITE
CYCLE
V
DEN
DT/R
--- ----Figure 2A1. Basic 8086 Bus Cycle
A-S
AP-67
multiplexed address/data/status bus. For the second T
state (T2), the CPU removes the address from the bus
and either three·states its outputs on the lower sixteen
bus lines in preparation for a read cycle or asserts write
data. Data bus transceivers are enabled in either T1 or
T2 depending on the 8086 system configuration and the
direction of the transfer (into or out of the CPU). Read,
write or interrupt acknowledge commands are always
enabled in T2. The maximum mode 8086 configuration
(to be discussed later) also provides a write command
enabled in T3 to guarantee data setup time prior to command activation.
Since the CPU prefetches up to six bytes of the instruction stream for storage and execution from an internal
instruction queue, the relationship of instruction fetch
and associated operand transfers may be skewed in
time and separated by additional instruction fetch bus
cycles. In general, if an instruction is fetched into the
BOB6's internal instruction queue, several additional instructions may be fetched before the instruction is
removed from the queue and executed. If the instruction
being executed from the queue is a jump or other control transfer instruction, any instructions remaining in
the queue are not executed and are discarded with no effect on the CPU's operation. The bus activity observed
during execution of a specific instruction is dependent
on the preceding instructions but is always deterministic within the specific sequence.
DuringT2, the upper four multiplexed bus lines switch
from address (A19-A16) to bus cycle status
(S6,85,S4,S3). The status information (Table 2A1) is
available primarily for diagnostic monitoring. However,
a decode of S3 and S4 could be used to select one of
four banks of memory, one assigned to each segment
register. This technique allows partitioning the memory
by segment to expand the memory addressing beyond
one megabyte. It also provides a degree of protection by
preventing erroneous write operations to one segment
from overlapping into another segment and destroying
information in that segment.
Table 2A1
S3
S4
o
0
Alternate (relative to the ES segment)
1
0
Stack (relative to the SS segment)
o
Code/None (relative to the CS segment or a default of zero)
Data (relative to the DS segment)
The CPU continues to provide status information on the
upper four bus lines during T3 and will either continue
to assert write data or sample read data on the lower sixteen bus lines. If the selected memory or I/O device is
not capable of transferring data at the maximum CPU
transfer rate, the device must signal the CPU "not
ready" and force the CPU to insert additional clock
cycles (Wait states TW) after T3. The 'not ready' indication must be presented to the CPU by the start of T3.
Bus activity during TW is the same as T3. When the
selected device has had sufficient time to complete the
transfer, it asserts "Ready" and allows the CPU to continue from the TW states. The CPU will latch the data on
the bus during the last wait state or during T3 if no wait
states are requested. The bus cycle is terminated in T4
(command lines are disabled and the selected external
device deselects from the bus). The bus cycle appears
to devices in the system as an asynchronous event conSisting of an address to select the device followed by a
read strobe or data and a write strobe. The selected
device accepts bus data during a write cycle and drives
the desired data onto the bus during a read cycle. On termination of the command, the device latches write data
or disables its bus drivers. The only control the device
has on the bus cycle is the insertion of wait cycles.
S5 = IF (interrupt enable flag)
S6 = 0 (indicates the BOB6 is on the bus)
2B. 8086 Address and Data Bus Concepts
Since the majority of system memories and peripherals
require a stable address for the duration of the bus
cycle, the address on the multiplexed address/data bus
during T1 should be latched and the latched address
used to select the desired peripheral or memory location. Since the B086 has a 16-bit data bus, the multiplexed bus components of the B085 family are not applicable to the 8086 (a device on address/data bus lines
B-15 will not be able to receive the byte selection address on lines 0-7). To demuliiplex the bus (Fig. 2B1a),
the BOB6 system provides an Address Latch Enable
signal (ALE) to capture the address in either the 8282 or
82B3 8-bit bi-stable latches (Diag. 2B1). The latches are
either inverting (8283) or non-inverting (8282) and have
outputs driven by three-state buffers that supply 32 mA
drive capability and can switch a 300 pF capacitive load
in 22 ns (inverting) or 30 ns (non-inverting). They propagate the address through to the outputs while ALE is
high and latch the address on the falling edge of ALE.
This only delays address access and chip select
decoding by the propagation delay of the latch. The outputs are enabled through the low active OE input. The
demultiplexing of the multiplexed address/data bus
(Iatchings of the address from the multiplexed bus), can
be done locally at appropriate points in the system or at
the CPU with a separate address bus distributing the address throughout the system (Fig. 2B1b). For optimum
system performance and compatibility with multiprocessor and MULTIBUS™ configurations, the latter technique is strongly recommended over the first. The remainder of this note will assume the bus is demultiplexed at the CPU.
The BOB6 CPU only executes a bus cycle when instructions or operands must be transferred to or from
memory or I/O devices. When not executing a bus cycle,
the bus interface executes idle cycles (TI). During the
idle cycles, the CPU continues to drive status information from the previous bus cycle on the upper address
lines. If the previous bus cycle was a write, the CPU continues to drive the write data onto the multiplexed bus
until the start of the next bus cycle. If the CPU executes
idle cycles following a read cycle, the CPU will not drive
the lower 16 bus lines until the next bus cycle is
required.
A-6
AP-67
The programmer views the 8086 memory address space
as a sequence of one million bytes in which any byte
may contain an eight bit data element and any two consecutive bytes may contain a 16-bit data element. There
is no constraint on byte or word addresses (boundaries).
The address space is physically implemented on a sixteen bit data bus by dividing the address space into two
banks of up to 512K bytes (Fig. 2B2). One bank is connected to the lower half of the sixteen-bit data bus (07-0)
and contains even addressed bytes (AD 0). The other
bank is connected to the upper half of the data bus
(015-8) and contains odd addressed bytes (AD 1). A
specific byte within each bank is selected by address
lines A19-A1. To perform byte transfers to even addresses (Fig. 2B3a), the information is transferred over
the lower half of the data bus (07-0). AD (active low) is
used to enable the bank connected to the lower half of
the data bus to participate in the transfer. Another
signal provided by the 8086, Bus High Enable (BHE), is
used to disable the bank on the upper half of the data
bus from participating in the transfer. This is necessary
to prevent a write operation to the lower bank from
destroying data in the upper bank. Since BHE is a
multiplexed signal with timing identical to the A19-A16
address lines, it also should be latched with ALE to provide a stable signal during the bus cycle. Ouring T2
through T4, the BHE output is multiplexed with status
line S7 which is equal to BHE. To perform byte transfers
to odd addresses (Fig. 2B3b), the information is transferred over the upper half of the data bus (015-08) while
BHE (active low) enables the upper bank and AD
disables the lower bank. Oirecting the data transfer to
the appropriate half of the data bus and activation of
BHE and AD is performed by the 8086, transparent to the
programmer. As an example, consider loading a byte of
data into the CL register (lower half of the CX register)
from an odd addressed memory location (referenced
over the upper half of the 16-bit data bus). The data is
transferred into the 8086 over the upper 8 bits of the
data bus, automatically redirected to the lower half of
the 8086 internal 16-bit data path and stored into the CL
register. This capability also allows byte I/O transfers
with the AL register to be directed to I/O devices connected to either the upper or lower half of the 16-bit data
bus.
8088
=
ADDRESS
BUS
=
Figure 2B1a. Demultlplexlng Ihe 6066 Bus
ADDRESS BUS
8086
CPU
DATA BUS
SEPARATE ADDRESS AND DATA BUSSES
r------,
I
I
I
I
I
:
I
I
I
8086
-_---1
i-'
CPU
1-.---.
ALE
ADDRESSIDATA
BUS
I
I
I
I
I ______ JI
L
MULTIPLEXED BUS WITH lOCAL ADDRESS DEMUlTiPlEXING
To access even addressed sixteen bit words (two consecutive bytes with the least significant byte at an even
Figure 2B1b.
T,
ClK
--'
v----
I
It--\
--
X
ALE
T,
T,
~
'---
f---- X
Tw
rI~
DATA IN OR OUT
T,
r-\
X
---
f-:X==
r---
\
I
Diagram 2B1. ALE Timing
A-7
-
AP-67
byte address), A19-A1 select the appropriate byte within
each bank and AO and BHE (active low) enable both
banks simultaneously (Fig. 2B3c). To access an odd addressed 16-blt word (Fig. 2B3d), the least significant
byte (addressed by A19-A1) is first transferred over the
upper half of the bus (odd addressed byte, upper bank,
BHE low active and AO 1). The most significant byte is
accessed by incrementing the address (A19-AO) which
allows A19-A1to address the next physical word location (remember, AO was equal to one which indicated a
word referenced from an odd byte boundary). A second
bus cycle Is then executed to perform the transfer of the
most significant byte with the lower bank (AO is nowac·
tive low and BHE is high). The sequence Is alitomatically
executed by the 8086 whenever a word transfer Is executed to an odd address. Directing the upper and lower
bytes of the 8086's internal sixteen-bit registers to the
appropriate halves of the data bus is also performed
automatically by the 8086 and is transparent to the pro·
grammer.
...._ _ _...,TRANSFER X+l, X,..._ _...,
=
, 0,,-0.
iiiiE (LOW)
0,-00
A.(LOW)
Figure 2B3c. Even Addressed Word Trensfer
. -_ _.....,FIRST BUS CYCLE.-_ _...,
(8) PHYSICAL IMPLEMENTATION OF THE
ADDRESS SPACE
612K BYTES
512K BYTES
(A) LOBICAL ADDRESS SPACE
FFFFE
FFFFC
FFFFF
. FFFFD
FFFFF
FFFFE
FFFFO
D15-Ds
FFFFC
BHE (LOW)
0,-00
Ao(HIGH)
m
1 MEGABYTE
Figure 2B2. 8086 Memory
TRANSFER X
Y+l
X+l
...}.
-y
.l\
r-v
.--< ;:.:.
Figure 2B3d. Odd Addressed Word Transfer
Y
~(X)~
...
~
...
7.
I
~~I
1
All-A,
0,,-0,
BHE (HIGH)
0,-00
Ao (LOW)
Figure 2B3a. Even Addressed Byle Transfer
TRANSFER X + 1
J\
--V
Y+l
J\
~(X+l)X'l.:
..tS
IV
Y
X
2C. System Data Bus Concepts
When referring to the system data bus, two Implemen·
tation alternatives must be considered; (a) the multi·
plexed address/data bus (Fig. 2C1a) and a data bus buf·
fered from the multiplexed bus by transceivers (Fig.
2C1b).
..".-"?>-
;0..
I
1
"' ~ _I
0,.-0.
BHE (LOW)
During Ii byte read, the CPU floats the entire sixteen-bit
data bus even though data is only expected on the upper
or lower half of the data bus. As will be demonstrated
later, this action simplifies the chip select decoding requirements for read only devices (ROM, EPROM). During
a byte write operation, the 8086 will drive the entire
sixteen-bit data bus. The information on the half of .the
data bus not transferring data is indeterminate. These
concepts also apply to the 1/0 address space. Specific
examples of 1/0 and memory interfacing are considered
In the corresponding sections.
"" 7"
0,-00
Figure 2B3b. Odd Addressed Byle TIBnsfer
A.(HIGH)
If memory .or 1/0 devices are connected directly to the
multiplexed bus, the designer must guarantee the
devices do not corrupt the address on the bus during T1.
A-8
AP-67
To avoid this, device output drivers should not be enabled by the device chip select, but'should have an output
enable controlled by the system read signal (Fig. 2C2).
The 8086 timing guarantees that read Is not valid .until
after the address Is latched by ALE (Dlag. 2C1). All Intel
peripherals, EPROM products and RAM's for microprocessors provide output enable or read Inputs to allow
connection to the multiplexed bus.
MULTIPLEXED DATA BUS
ADDRESS
ALE---_I
ADDRESS BUS
' -_ _ _ _-'A.:::D.:.:15'-'-A.:::D.::.OJ\ MULTIPLEXED
' - - _ - ' -_ _ _ _ _--,/ ADDRESS/DATA
MULTIPLEXED
BUS
Figure 2C1a. Multiplexed Data Bus
WR
BUFFERED DATA BUS
--'-----01
i i D - - - - - - o I RD/OE
Figure 2C2. Devices with Output Enables on the Multiplexed Bus
8282
Several techniques are available for Interfacing devices
without output enables tei the multiplexed bus but each
introduces other restrictions or limitations. Consider
Figure2C3 which has chip select gated with read and
write. Two problems exist with this technique. First, the
chip select access time Is reduced to the read access
time, and may require a faster device If maximum
system performance .(no wait states) is to be achieved
(Diag. 2C2). Second, the designer must verify that chip
select to write setup and hold times for the device are
not violated (Diag. 2C3). Alternate techniques can be extracted from the bus Interfacing techniques given later
in this section but are subject to the associated restrictions. In general, the best solution is obtained with
devices having output enables.
SYSTEM
BUS
A subsequent limitation on the multiplexed bus is the
8086's drive capability of 2.0 mA and capacitive loading
of 100 pF to guarantee the speCified A.C. characteristics. Assuming capacitive . loads of 20 pF per 1/0
device, 12 pF per address latch and 5-12 pF per memory
device, a system mix of three peripherals and two to
four memory devices (per bus line) are close to the
loading limit.
Figure 2C1b. Bullered Data Bus
T1
ALE _ _ _-I--'
T3
T2
T4
.\~~----~--+---------~---------4J,-""-.-
Diagram 2C1. Relationship of ALE to READ
A-9
Ap . .67
ADDRESS
ALE
'----------;;>~-,J MULTIPLEXED BUS
Figure 2C3. Devices without Output Enables on the Multiplexed Bus
ADDRESS---{'-_ _ _ _ _ _ _ _ _ _---.,._ __
, DATA----------+---_---------
.
AP·67
CPU LOCAL
BUS
MEMORY/IO
LOCAL BUS
SYSTEM
BUS
Figure 2C5. Fully Buffered System
828617
"-==-,,
MEMORYIlfO. DEVICES
An alternate technique applicable to devices with and
without output enables is shown in Figure 2C6d. RD
again controls the direction of the transceiver but It Is
not enabled until a command and chip select are active.
The possibility for bus contention still exists but Is
reduced to variations In output enable vs. direction
change time for the transceiver. Full access time from
chip select is now available, but data will not be valid
'prlorto write and will only be held valid after write by the
delay to disable the transceiver.
Figure 2C6a. Controlling System Transceivers with DEN and DT/R
~--------~------------------------,
Wft--------------~~----.
~----------~--------~
RD---------1--~--------~--~
SYSTEM /"'-",,-,,-,-J'
MEMORY/I/O
DEVICE
DATA
BUS
SYSTEM DATA BUS
Figure 2C6b. Buffering Devices with
OEiRD
MEMORY/I/O
DEVICE
Figure 2C6d. Buffering Devices without
or Separate InpuUOutput
MEMORYIllO
DEVICE
Figure 2C6c. Buffering DevlceB without OEtRD and with Common
or Separate InpuUOutput
OEiRD and with Common
One last technique is given for devices with separate in·
puts and outputs (Fig. 2C6e). Separate bus receivers and
drivers are provided rather than a single transceiver. The
receiver is always enabled while the bus driver Is can·
trolled by RD and chip .select. The only possibility for
bus contention in this system occurs as multiple
devices on each line of the local read bus are enabled
and disabled during chip selection changes.
Throughout this note, the multiplexed bus will be considered the local CPU bus and the demultlplexed address and buffered data bus will be the system bus. For
additional Information on bus .. contention and the
system problems associated with It, refer to Appendix 1.
A-t'2
AP-67
strapping options) extend the configuration options
beyond a pure CPU Interface to the multlmaster system
bus for access to shared resources to Include concurrent support of a local CPU bus for private resources.
For specific configurations and additional Information
on the 8289, refer to application note Ap·51.
~~---------------------------.
1Ill--q",..J
WR-------+--------------,
74504
OR
745240
SYSTEM
LOCAL WRITE BUS
DATA ~-------t---1
BUS
LOCAL READ BUS
3. 8086 SYSTEM DETAILS
o
3A. Operating Modes
Possibly the most unique feature of the 8086 Is the ability to select the base machine configuration most suited
to the application. The MN/MX Input to the 8086 Is a
strapping option which allows the deSigner to select
between two functional definitions of a subset of the
8086 outputs.
MEMORY/I/O
DEVICE
745240
Figure 2C6e. Bulferlng Devices without
Input/Output
oEiRii and with Separate
MINIMUM MODE
The minimum mode 8086 (Fig. 3A1) Is optimized for
small to medium (one or two boards), Single CPU
systems. Its system architecture is directed at satisfy·
Ing the requirements of the lower to middle segment of
high performance 16·bit applications. The CPU maintains the full megabyte memory space, 64K byte I/O
space and 16-blt data path. The CPU directly provides all
bus control (DT/A, DEN, ALE, M/iO), commands
(RD,WR,INTA) and a simple CPU preemption mechanism (HOLD, HLDA) compatible with existing DMA
controllers.
20. Multiprocessor Environment
The 8086 architecture supports multiprocessor systems
based on the concept of a shared system bus (Fig. 201).
All CPU's in the system communicate with each other
and share resources via the system bus. The bus may be
either the Intel Multlbus™ system bus or an extension
of the system bus defined in the previous section. The
major addition required to the demultlplexed system
bus is arbitration logic to control access to the system
bus. As each CPU asynchronously requests access to
the shared bus, the arbitration logic resolves priorities
and grants bus access to the highest priority CPU. Hav·
ing gained access to the bus, the CPU completes its
transfer and will either relinquish the bus or wait to be
forced to relinquish the bus. For a discussion on
MultibuS™ arbitration techniques, refer to AP·28A, Intel
MultibuS™ Interfacing.
Figure 201. 8086 Family Multiprocessor System
To support a multimaster interface to the Multibus
system bus for the 8086 family, the 8289 bus arbiter is
included as part of the family. The 8289 is compatible
with the 8086's local bus and in conjunction with the
8288 bus controller, implements the Multibus protocol
for bus arbitration. The 8289 provides a variety of arbitra·
tion and prioritization techniques to allow optimization
of bus availability, throughput and utilization of shared
resources. Additional features (implemented through
MAXIMUM MODE
The maximum mode (Fig. 3A2) extends the system architecture to support multiprocessor configurations,
and local instruction set extension processors (coprocessors). Through addition of the 8288 bipolar bus
controller, the 8086 outputs assigned to bus control and
commands in the minimum mode are redefined to allow
these extensions and enhance general system performance. Specifically, (1) two prioritized levels of processor
preemption (RO/GTO, RO/GT1) allow multiple processors to reside on the 8086's local bus and share its interface to the system bus, (2) Oueue status (OSO,OS1) is
available to allow external devices like ICE™_86 or
special instruction set extension co·processors to track
the CPU instruction execution, (3) access control to
shared resources in multiprocessor systems is supported by a hardware bus lock mechanism and (4)
system command and configuration options are expanded via ancillary devices like the 8288 bus controller
and 8289 bus arbiter.
The queue status indicates what information is being
removed from the internal queue and when the queue is
being reset due to a transfer of control (Table 3A1). By
monitoring the SO,51,52 status lines for instructions
entering the 8086 (1,0,0 indicates code access while AO
and BHE indicate word or byte) and OSO, OS1 for instructions leaving the 8086's internal queue, it is possible to track the instruction execution. Since instructions are executed from the 8086's internal queue, the
queue status is presented each CPU clock cycle and Is
not related to the bus cycle activity. This mechanism (1)
allows a co-processor to detect execution of an
A-13
AP-67
queue. Note that a normal code fetch will transfer two
bytes into the queue so two clock increments are given
to the counter (T201 and T301) unless a single byte Is
loaded over the upper half of the bus (AO·P Is high).
Since the execution unit (EU) is not synchronized to the
bus interface unit (BIU), a fetch from the queue can oc·
cur simultaneously with a transfer into the queue. The
excluslve·or gate driving the ENP input of the first
counter allows these simultaneous operations to cancel
each other and not modify the queue depth.
ESCAPE instruction which directs the co·processor to
perform a specific task arid (2) allows ICE-86 to trap ex·
ecution of a specific memory location. An example of a
circuit used.by ICE Is given In Figure 3A3. The first up
down counter tracks the depth of the queue while the
second captures the queue depth on a match. The sec·
ond counter decrements on further fetches from the
queue until the queue is flushed or the count goes to
zero indicating execution of the match address. The
first counter decrements on felch from the queue
(050=1) and Increments on code fetches Into the
}
Vee
rm~.
-,,~
-':'ENERATOR
RES
MN/MX
f+
ClK
MIlO
~
READY
INTA
RESET
AD
f+
T
RDY
}
COMMAND
BUS
Wii
t
GND
"--Vcc
f----,
- r----, I
IlTiii
DEN
r---'"
II
II
8086 CPU
ALE
GND
I I
1,,1
II
II
IL
>
J
8282
lATCH
20R 3
r
A16-A19
I
OE
t..
ADD-AD" ~DDRIDATA
BHE j - - -
.. I
STB
I I
1 MEGABYTE
ADDRESS BUS
-rr----:1
T---'I
L-..JOE
I
8266
TRAN~~EIVER
II
II ~
~ DATA
16·BIT
BUS
OPTIONAL
FOR INCREASED
DATA BUS DRIVE
Figure 3A1. Minimum Mode 8086
Vee
~
.
T
GND
rD~.
-
CLOCK
t
_
... READY
S,
S,
... RESET
so
So
ROY
t
MRDC
So
So
~NER.ATOR
RES
ClK
MN/MX _ilND
elK
8288
BUS
CTRlR
IORC
LOcK
r
A
N:C•
~
A1S-A19 ~DDRIDATA
BHE j - - -
AIOWC
I--
INTA
I---
ALE
-
GND
. ADo·AD,.
DTiR
-
COMMAND
BUS
I---
IOWC I - - -
r - - DEN
6066
CPU
r---:-
f-AMWC f - MWTC
STB
DE
!
8282
~
LATCH
(20R3)
I'
1 MEGABYTE
ADDRESS BUS
I-
~
T
OE
8266
TRANSCEIVER
(2)
t..
..
r
Figure 3A2. Maximum Mode 8086
A-14
III
I~
.. t..
I
1a.~1T
DATA BUS
AP-67
TABLE 3A1. QUEUE STATUS
aS 1
aSO
a (LOW)
a
a
1 (HIGH)
1
tion of the locked instruction) without Intervention and
possible corruption of the data by another CPU. A
classic use of the mechanism Is the 'TEST and SET
semaphore' during which a CPU must read from a
shared memory location and return data to the location
without allowing another CPU to reference the same
location between the TEST operation (read) and the SET
operation (write). In the 8086 this is accomplished with a
locked exchange instruction.
No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue
1
a
1
The queue status is valid during the CLK cycle after
which the queue operation is performed.
LOCK XCHG reg, MEMORY; reg Is any register
;MEMORY Is the add,,;ss of the
;semaphore
To address the problem of controlling access to shared
resources, the maximum mode 8086 provides a hardware LOCK output. The LOCK output is activated
through the instruction stream by execution of the
LOCK prefix instruction. The LOCK output goes active
In the first CPU clock cycle following execution of the
prefix and .remains active until the clock following the
completion of the Instruction following the LOCK prefix.
To provide bus access control In multiprocessor
systems, the LOCK signal should be incorporated into
the system bus arbitration logic resident to the CPU.
The activity of the LOCK output is shown in Diagram
3A1. Another interesting use of the LOCK for multiproc·
essor systems Is a locked block move which allows high
speed message transfer from one CPU's message buffer to another.
During the locked Instruction, a request for processor
preemption (RQ/Gn is recorded but not acknowledged
until completion of the locked Instruction. The LOCK
has no direct affect on Interrupts. As an exam.£1e, a
locked HALT instruction will cause HOLD (or RQ/Gn requests to be Ignored but will allow the CPU to exit the
HALT state on an Interrupt. In general, prefix bytes are
considered extensions of the Instructions they precede.
Therefore, Interrupts that occur during execution of a
prefix are not acknowledged (assuming interrupts are
enabled) until completion of the Instruction following
the prefixes (except for instructions which allow servicIng interrupts during their execution, i.e., HALT, WAIT
and repeated string primitives). Note that multiple prefix
bytes may precede an Instruction. As another example,
consider a 'string primitive' preceded by the repetition
During normal multiprocessor system operation, priority of the shared system bus is determined by the arbitration circuitry on a cycle by cycle basis. As each
CPU requires a transfer over the system bus, It requests
access to the bus via its resident bus arbitration logic.
When the CPU gains priority (determined by the system
bus arbitration scheme and any associated logic), It
takes control of the bus, performs Its bus cycle and
either maintains bus control, voluntarily releases the
bus or Is forced off the bus by the loss of priority. The
lock mechanism prevents the CPU from losing bus control (either voluntarily or by force) and guarantees a CPU
the ability to execute multiple bus cycles (during execu-
.------1 ">o---~24>CLK
MHBYTEO:::============2!==~
MHBYTE1
74500
______________t-______________~9 LOAD
745169
aCTO
L--'="-=--_______-'q LOAD
745169
-+-----+·'-L;:'O=-+-------------------~__l UP/DOWN
ENP
MHBYTEAND 1 T301,1201
SOLH-S2LH
CACCESS
aCTO
AO·P
-
ClKA
aS1, aso
--------:-r"\
SOLH
SlLH ---------'-L./
MATCH CONDITIONS
CPU CLOCK
CPU QUEUE STATUS
T STATES 13 and T2 (CLOCK LOW TIME",,01)
CPU STATUS SO·S2
CODe ACCESS
QUEUE MATCH
SINGLE BYTE ON UPPER HALF OF THE BUS
)OC13=--_____________________________________________________ C ACCESS
Sffi! _____---'-13,
74504
Figure 3A3. Example Circuit to Track the a086 Queue
A-iS
AP-67
prefix (REP) which Is interruptible after each execution
of the string primitive. This holds even if the REP prefix
Is combined with the lOCK prefix and prevents inter·
rupts from being locked out during a block move or
other repeated string operation. As long as the opera·
tlon Is not interrupted, lOCK remains active. Further In·
formation on the operation of an Interrupted string
operation with multiple prefixes is presented in the sec·
tion dealing with the 8086 Interrupt structure.
Three additional status lines (SO, 51, 52) are defined to
provide communications with the 8288 and 8289. The
status lines tell the 8288 when to initiate a bus cycle,
what type of command to issue and when to terminate
the bus cycle. The 8288 samples the status lines at the
beginning of each CPU clock (ClK). To initiate a bus cy·
cle, the CPU drives the status lines from the passive
state (SO, 51, 52 1) to one of seven possible command
codes (Table 3A2). This occurs on the rising edge of the
clock during T4 of the previous bus cycle or a TI (idle cy·
cle, no current bus activity). The 8288 detects the status
change by sampling the status lines on the high to low
transition of each clock cycle. The 8288 starts a bus cy·
cle by generating ALE and appropriate buffer direction
control in the clock cycle immediately following detec·
tion of the status change (T1). The bus transceivers and
the selected command are enabled in the next clock
cycle (T2) (or T3 for normal write commands). When the
status returns to the passive state, the 8288 will ter·
minate the command as shown in Diagram 3A2. Since
the CPU will not return the status to the passive state
until the 'ready' indication is received, the 8288 will
maintain active command and bus control for any
number of wait cycles. The status lines may also be
used by other processors on the 8086's local bus to
monitor bus activity and control the 8288 if they gain
control of the local bus.
=
TABLE 3A2. STATUS LINE DECODES
52
51
50
o (lOW)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1 (HIGH)
1
1
1
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
The 8288 provides the bus control (DEN, DT/R, ALE) and
commands (INTA, MRDC, 10RC, MWTC, AMWC, iQWC,
AIOWC) removed from the CPU. The command structure
has separate read and write commands for memory and
I/O to provide compatibility with the Multibus command
structure.
The advanced write commands are enabled one clock
period earlier than the normal write to accommodate the
wider write pulse widths often required by peripherals
and static RAMs. The normal write provides data setup
prior to write to accommodate dynamic RAM memories
and I/O devices which strobe data on the leading edge of
write. The advanced write commands do not guarantee
that data is valid prior to the leading edge of the com·
mand. The DEN signal In the maximum mode Is Inverted
from the minimum mode to extend transceiver control
by allowing logical conjunction of DEN with other
signals. While not appearing to be a significant benefit
in the basic maximum mode configuration, introduction
of interrupt control and various system configurations
will demonstrate the usefulness of qualifying DEN.
Diagram 3A3 compares the timing of the minimum and
maximum mode bus transfer commands. Although the
CLK
QSO
~--~~=----~
LOCK
LOCKED INSTRUCTION
NOP BYTE
FROM THE
QUEUE
(LOCKED NOP)
LOCK
PREFIX
BYTE FROM
QUEUE
1
QUEUE STATUS INDICATES FIRST BYTE OF OPCODE FRO~ THE QUEUE.
2
THE LOCK OUTPUT WILL GO INACTIVE BETWEEN SEPARATE LOCKED INSTRUCTIONS.
3
TWO CLOCKS ARE REQUIRED FOR DECODE OF THE LOCK PREFIX AND
ACTIVATION OF THE LOCK SIGNAL.
4
SINCE QUEUE STATUS REFLECTS THE QUEUE OPERATION IN THE PREVIOUS CLOCK
CYCLE, THE LOCK OUTPUT ACTUALLY GOES ACTIVE COINCIDENT WITH THE START
OF THE NEXT INSTRUCTION AND REMAINS ACTIVE FOR ONE CLOCK CYCLE
FOLLOWING THE INSTRUCTION.
S
IF THE INSTRUCTION FOLLOWING THE LOCK PREFIX IS NOT IN THE QUEUE,THE
[OCR OUTPUT STILL GOES ACTIVE AS SHOWN WHILE THE INSTRUCTION IS BEING
FETCHED.
6
THE BIU WILL STILL PERFORM INSTRUCTION FETCH CYCLES DURING EXECUTION
OF A LOCKED INSTRUCTION. THE [OCR MERELY LOCKS THE BUS TO THIS CPU FOR
WHATEVER BUS CYCLES THE CPU PERFORMS DURING THE LOCKED INSTRUCTION.
Diagram 3A1. 8086 Lock Acllvlly
A-16
AP-67
maximum mode configuration Is designed for multiprocessor environments, large single CPU designs
(either Multlbus systems or greater than two PC boards)
should also use the maximum mode. Since the 8288 Is a
bipolar dedicated controller device, Its output drive for
the commands (32 mAl and tolerances on AC characterIstics (timing parameters and worse case delays) provide better large system performance than the minimum
mode 8086.
In addition to assuming the functions removed from the
CPU, the 8288 provides additional strapping options and
controls to support multiprocessor configurations and
peripheral devices on the CPU local bus. These capabilities allow assigning resources (memory or 1/0) as
shared (available on the Multibus system bus) or private
(accessible only by this CPU) to reduce contention for
access to the Multibus system bus and improve multlCPU system performance. Specific configuration possibilities are discussed in AP-51.
ClK
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
ALE
READY
\\~~\\\
READY
o
WAIT
Diagram 3A2. Status Lin. Activation and Termination
ClK (8284 OUTPUT)
MN
MODE
8086
~ -------------------+~
TCVCTXTClMH
MX
MODE
8088
WITH
8288
TClMH- 3 5 _
35 ns
~OR~
35
-----------+,1
-35
TClMl
~ORiljWlj
Diagram 3A3. 8Q86 Minimum and Maximum Mod. Command Timing
A-I7
35 -TCLMH
AP-67
3B. Clock Generation
must not cause the Impedance of the feedback circuit to
reduce the loop gain below one. The impedance of the
capacitor is a ,function of the operating frequency and
can be determined' from the following equation:
The 8086 requires a clock signal with fast rise and fall
times (10 ns max) between low and high voltages of
- 0;5 to + 0.6 low and 3.9 to VCC + 1.0 high. The max·
imum clock frequency of the 8086 Is 5 MHz and 8MHz
for the 8086·2. Since the design of the 8086iricorporates
dynamic cells, a minimum frequency of 2 MHz Is reo
qUln:id to retain the state of the-machine. Due to the
minimum frequency requirement, Single stepping or
cycling of the CPU may not be accomplished by dis·
abllng the clock. The timing and voltage requirements of
the CPU clock are shown In 'Figure 3B1. In general, for
frequencies below the maximum, the CPU clock need
not satisfy the frequency dependent pulse width liml·
tatlons stated' in the 8086 data sheet. The values
specified only reflect the minimum values which must
be satisfied and are stated In terms of the maximum
clock frequency. As the clock frequency approaches the
maximum frequency of the CPU, the clock must con·
form,'to a 33% duty cycle to satisfy the CPU minimum
clock low and high time specifications.
XCl= 1/2n"F"Cl
17
XTAl
CJ
Y
csc
X,
12
8088
8284
18
Cl
13
19 ClK"
ClK
X,
FIll"
'Figure 3B2: 8284 Clock Generalor
It is recommended that the crystal series resistance
plus XCl be kept less than 1K ohms. This capaCitor also
serves to debias the crystal and prevent a DC voltage
bias from straining and perhaps damaging the crystal·
line structure. As the crystal frequency Increases, the
amount of capaCitance should be decreased. For exam·
pie, a 12 MHz crystal may require Cl'" 24 pF while 22
MHz may require Cl '" 8 pF. If very close correlation
with the pure series resonance is not necessary, a
nominal Cl value of 12·15 pF may be used with a 15 MHz
crystal (5 MHz 8086 operation). Board layout and component variances will affect the actual amount of induc·
tance and therefore the series capaCitance required to
cancel it out (thiS Is especially true for wire·wrapped
layouts).
i0n.MAX
Figure 3Bl. 8088 Clock
An optimum 33% duty cycle clock with the required
voltage levels and transition times can be obtained with
the 8284 clock generator (Fig. 3B2). Either an external
frequency source ora series resonant crystal may drive
the 8284. The selected source must oscillate at 3X the
desired CPU frequency. To select the crystal 'Inputs of
the 8284 as the frequency source for clock generation,
the Fie Input to the 8284 must be strapped to ground.
The strapping, option allows selecting either the crystal
or the external frequency Input as the source for clock
generation. Although the 8284 provides an Input for a'
tank circuit to accommodate overtone mode crystals,
fundamental mode crystals are recommended for more
accurate and stable frequency generation. When selec·
tlng a crystal for use with the 8284, the series resistance
should be as low as possible. Since other circuit com·
ponents will tend to shift the operating frequency from
resonance, the operating impedance will typically be,
higher than the specified series resistance. If the at·
tenuatlon of the oscillator's feedback circuit, reduces
the loop gain to less than onEi, the oscillator will fall.
Since, the oscillator delays In the 8284 appear as Induc·
tlve elements to the crystal, causing it to .run at a fre·
quency'beiow that of the pure series resonance" a
capacitor should be placed In series with the crystal and
the X2 input of the 8284. This capacitor serves to cancel
this Inductive element. The value of the capacitor (Cl)
Two of the many vendors which supply crystals for Intel
microprocessors are listed In Table 3B1 along with a list
of crystal part numbers for various frequencies which
may be of interest. For additional information on specl·
fylng crystals for Intel components refer to application
note AP·35.
TABLE 3Bl. CRYSTAL VENDORS
f
15.0MHz
18.432
24.0 MHz
Parallell
Serlel
Cryltek(l)
Corp.
CTS Knlght,12l
Inc.
S
CY15A
CY19B"
CY24A
MP150
MP184*
MP240
S
S
',Inlel also supplies a cryslal numbered 8801 lor Ihls application.
Not••: 1. Address: 1000 Cryslal Driye, Fort Meyers, Florldli 33901
2. Address: 400 Reimann AYe., Sandwich, illinois
If a high accuracy frequency source, externally variable
frequency source or a common source for,driving mul·
tlple 8284's Is desired, the Externai Frequency li}Put
(EFI) of the 8284 can be selected by strapping the F/C in·
put to 5 volts through "'1 K ohms (Fig. 3B3). The external
frequency source should be TIL compatible, have a
50% duty cycle and oscillate at three times the desired
CPU operating frequency. The maximum EFI frequency
the 8284 can accept is Slightly above 24 MHz with
minimum clock low and high times of 13 ns. Although
A-IS
AP-67
no minimum EFI frequency is specified, it should not
violate the CPU minimum clock rate. If a common fre·
quency source is used to drive multiple 8284's
distributed throughout the system, each 8284 should be
driven by its own line from the source. To minimize
noise In the system, each line should be a twisted pair
driven by a buffer like the 74lS04 with the ground of the
twisted pair connecting the grounds of the source and
receiver. To minimize clock skew, the lines to all 8284's
should be of equal length. A simple technique for gen·
erating a master frequency source for additional 8284's
Is shown in Figure 384. One 8284 with a crystal is used
to generate the desired frequency. The oscillator output
of the 8284 (OSC) equals the crystal frequency and is
used to drive the external frequency to all other 8284's
in the system.
The oscillator output Is inverted from the oscillator
signal used to drive the CPU cloc,k generator circuit.
Therefore, the oscillator output of one 8284 should not
drive the EFI Input of a second 8284 If both are driving
clock inputs of separate CPU's that are to be synchronized. The variation on EFI to' ClK delay over a
range of 8284's may approach 35 to 45 ns.lf, however, all
8284's are of the same package type, have the same
relative supply voltage and operate In the same temperature environment, the variation will be reduced to
between 15 and 25 ns.
There are three frequency outputs from the 8284, the
oscillator (OSC) mentioned above, the system clock
(ClK) which drives the CPU, and a peripheral clock
(PClK) that runs at one half the CPU clock frequency.
The oscillator output is only driven by the crystal and Is
not affected by the FIC strapping option. If a crystal Is
not connected to the 8284 when the external frequency
input Is used, the oscillator output is Indeterminate. The
CPU clock is derived from the selected frequency
source by an internal divide by three counter. The
counter generates the 33% duty cycle clock which Is optimum for the CPU at maximum frequency. The
peripheral clock has a 50% duty cycle and is derived
from the CPU clock. Diagram 380 shows the relationship of ClK to OSC and PClK to elK. The maximum
skew is 20 ns between OSC and ClK, and 22 ns between
ClK and PClK.
+5
X,
X.
EXTERNAL
Fie
FREQUENCY---=! EFt
SOURCE
ClK
1-=-_ _..:;19"-1 ClK
8284
8088
Figure 3B3. 8284 with External Frequency Source
14
EFt
ClK
8284
17 Xl
t:I
Y
Fie
OSC
8284
18
13
X.
EF' ClK
8284
FIC
FIC
-=13
EFt ClK
8284
FIC
1K
+5
Since the state of the 8284 divide by three counter is indeterminate at system initialization (power on), an external sync to the counter (CSYNC) is provided to allow
synchronization of the CPU clock to an external event.
When CSYNC is brought high, the ClK and PClK outputs are forced high. When CSYNC returns low, the next
positive clock from the frequency source starts clock
generation. CSYNC must be active for a minimum of two
periods of the frequency source. If CSYNC is asynchronous to the frequency source, the circuit In Figure 385
should be used for synchronization. The two latches
minimize the probability of a meta·stable state in the
latch driving CSYNC. The latches are clocked with the
inverse of the frequency source to guarantee the 8284
setup and hold time of CSYNC to the frequency source
(Diag. 381). If a single 8284 is to be synchronized to an
external event and an external frequency source is not
used, the oscillator output of the 8284 may be used to
Figure 3B4. External Frequency for Multiple 8284s
OSC
ClK
PCLK
Diagram 3BO. OSC - ClK and ClK - PClK Relationships
A-19
AP-67
synchronize CSYNC (Fig. 3B6). Since the oscillator out·
put Is Inverted from the Internal oscillator signal, the In·
verter In the previous example Is not required. If multiple
8284's are to be synchronized, an external frequency
source must drive all 8284's and a single CSYNC syn·
chronlzation circuit must drive the CSYNC Input of all
8284's (Fig. 3B7). Since activation of CSYNC may cause
violation of CPU minimum clock low time, It should only
be enabled during reset or CPU clock high. CSYNC must
also be disabled a minimum of four CPU clocks before
the end of reset to guarantee proper CPU reset.
+5
lK
EXTERNAL
SYNC-----I
Q
CONDITION
EXTERNAL
FREQUENCY
TO
' - - - - - - - - - - - - - - EFI
INPUT
Figure 3B5. Synchronizing CSYNC with EFI
EFI
CaYNe
.J
I
-t
Figure 3B7. Synchronizing Multiple 62848
TO
CSYNC
INPUT
I
I
I-TYHEH
Due to the fast transitions and high drive (5 mAl of the
8284 ClK output, It may be necessary to put a 10 to 100
ohm resistor in series with the clock line to eliminate
ringing (resistor value depending on the amount of drive
required). If multiple sources of ClK are needed with
minimum skew, ClK can be buffered by a high drive
device (74S241) with outputs tied to 5 volts through 100
ohms to guarantee VOH = 3.9 min (8086 minimum clock
input high voltage) (Fig. 3B8). A single 8284 should not
be used to generate the ClK for multiple CPU's that do
not share a common local (multiplexed) bus since the
8284 synchronizes re"qy to the CPU and can only ac·
commodate ready fora single CPU. Ifmultlple CPU's
share a local bus, they should be driven with the same
clock to optimize transfer of bus control. Under these
Circumstances, only one CPU will be using the bus for a
particular bus cycle which allows· sharing a common
READY signal (Fig. 3B9).
"'MAX IS SPEC'ED TO GUARANTEE MAX 8086 CLOCK FREQUENCY
Diagram 3B1. CSYNC Setup and Hold to EFI
l00Q
17 X,
+5
C
8284
Y
18
13
0:-
Q
D
SYNC
74LS74
CLK
CLK
OSC 12
1
100Q
X2
Fie
CSVNC CLK 8
l00Q
74LS74
CLK
Figure 3B6. EFI Irom 8284 Oscillator
Figure 3B8. Bullerlng the 8284 CLK Output
A-20
AP-67
MULTIPLEXED BUS
Figure 3B9. 8086 and Co·Processor on the local Bus Share a
.
Com mon 8284
3C. Reset
The 8086 requires a high active reset with minimum
pulse width of four CPU clocks except after power on
which requires a 50 fls reset pulse. Since the CPU internally synchronizes reset with the clock, the reset is internally active for up to one clock period after the external reset. Non-Maskable Interrupts (NMI) or hold requests on RQ/GT which occur during the internal reset,
are not acknowledged. A minimum mode hold request
or maximum mode RQ pulses active immediately after
the internal reset will be honored before the first instruction fetch.
guarantee the inactive state of these lines in systems
where leakage currents or bus capacitance may cause
the voltage levels to settle below the minimum high
voltage of devices in the system. In maximum mode
systems, the 8288 contains internal pull-ups on the
SO-52 inputs to maintain the inactive state for these
lines when the CPU floats the bus. The high state of the
status lines during reset causes the 8288 to treat the
reset sequence as a passive state. The condition of the
8288 outputs for the passive state are shown in Table
3C2. If the reset occurs during a bus cycle, the return of
the status lines to the passive state will terminate the
bus cycle and return the command lines to the inactive
state. Note that the 8288 does not three-state the command outputs based on the passive state of the status
lines. If the designer needs to three-state the CPU off
the bus during reset in a single CPU system, the reset
signal should also be connected to the 8288's AEN input
and the output enable of the address latches (Fig. 3C2).
This forces the command and address bus interface to
three-state while the inactive state of DEN from the 8288
three-states the transceivers on the data bus.
Table 3C1. 8086 Bus During Reset
From reset, the 8086 will condition the bus as shown in
Table 3Cl. The multiplexed bus will three-state upon
detection of reset by the CPU. Other signals which
three-state will be driven to the inactive state for one
clock low interval prior to entering three-state (Fig. 3Cl).
In the minimum mode, ALE and HLDA are driven inactive and are not three-stated. In the maximum mode
RQ/GT lines are held inactive and the queue status in:
dicates no activity. The queue status will not indicate a
reset of the queue so any user defined ellternal circuits
monitoring the queue should also be reset by the
system reset. 22K ohm pull-up resistors should be connected to the CPU command and bus control lines to
Signals
Condition
AD 1S,()
A19-1s1S6.3
BHE/S 7
S2/(M/IO)
Sl/(DT/R)
SOlD EN
LOCKlWR
RD
INTA
ALE
HLDA
RQ/GTO
RQ/GT1
QSO
QSl
Three-State
Three-State
Three-State
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
0
0
1
1
0
0
CLOCK
RESET INPUT
INTERNAL RESET
BUS
t
LFLOATBUS
~ DRIVE OUTPUT TO INACTIVE STATE
Figure 3C1. 8086 Bus Conditioning on Reset
A-21
Ap·67
If the 8288 command outputs are three-stated during
reset, the command lines should be pulled up to Vee
through 2.2K ohm resistors.
'
TABLE 3C2. 8288 OUTPUTS DURING PASSIVE MODE
o
o
ALE
DEN
1
DTIR
MCElPDEN
COMMANDS
0/1
"
1
~~------------~.IAEN
8288
~+--'lDEN
8284
RESET 1--4--1 RESET
8088
Figure 3C2. Re$et Disable lor ,Max Mode,8086 Bus Interlace
For multiple processor systems using arbitration of a
multlmaster bus, 'the system reset should be connected
to the INIT input of the 8289 bus arbiter in addition to
the 8284 reset Input (Fig. 3C3). The low active INIT input
forces all 8289 outputs to their inactive state. The inactive state of the 8289 AEN output will force the 8288 to
three-state the, command outputs and the address
latches to three-state the address bus interface. DEN inactive from the 8288 wiil three-state the data bus interface. For the multimaster CPU configuration, the reset
should be common to all CPU's (8289's and 8284's) and
satisfy the maximum of either the CPU reset requirements or 3 TBLBL (3 8289 bus clock times)+ 3
TCLCL (3 8086 clock cycle times) to satisfy 8289 reset
requirements.
The reset signal to the 8086 can be generated by the
8284. The 8284 has a schmitt trigger Input (RES) for
generating reset from a low active external reset. The
hysteresis specified In the 8284 data sheet iniplles that
at least .25 volts will separate the 0 and 1 switching
point of the 8284 reset Input. Inputs without hysteresis
will switch from low to high and high to low at approximately the same voltage threshold. The Inputs are
guaranteed to switch at specified low and high voltages
(VIL and VI H) but the actual switching point is anywhere
in-between. Since VIL min Is specified at .8 volts, the
hysteresis guarantees that the reset will be active until
the Input reaches at least 1.05 volts. A reset will not be
recognized until the Input drops at least .25 VOlts' below
the reset Inputs VIHof 2.6 volts.
To guarantee reseUrom power up, the reset Input must
remain below 1.05 volts for 50 microseconds after Vee
has reached the minimum supply vqltage of 4.5 volts.
The hysteresis allows the reset input to be driven by a
simple RC circuit as, shown in Flgure,3C4. The
calculated RC value does not include time, for the power
supply to reach 4.5 volts or the charge accumulateddurIng thlslriterval. Without the hysteresis, the reset output might oscillate as the input voltage passes through
the switching voltage of the input. The calculated RC
value provides the minimum required reset period of 50,
microseconds for 8284's that switch at tlie 1.05 volt
level arid a reset periOd of approximately 162 microseconds for 8284's that switch at the 2.6 volt level. If
tighter tolerance between the minimum and maximum
reset times Is necessary, the reset, circuit shown in
Figure 3C5 might be used rather than the,slmple RC circuit. This circuit provides a constant current source and
a linear charge rate on the capacitor ratherthim the inverse exponential charge rate of the RC ,circuit. The
maximum reset period for this implementatl()n is 124
microseconds.
' ,
+V
11
RESET IN
8284
I
8284
liES
:J
I--
Figure 3C3. Reset Disable 01 for Max Mode 8086 Bus Interlace In
Multi CPU System
Vc
RC
= 188x 10-&
RESET ACTIVE TIME
MAXIMUM RESET ACTIVE TIME
Figure 3C4. 8284 Reset Circuit
A-22
iit)
= 50 ~sec
= 4,5
= 1.05
V
RESET
¥.:l
l.
VeIl) = Jl-e
t
AP-67
3D. Ready Implementation and Timing
Vee
D,
R, R, -
D,
DETERMINES CURRENT TO CHARGE C
VALUE NOT CRITICAL ='OK
le= CHARGE CURRENT= V,dD,
~ D, -
T1I
RESET
IF All SEMICONDUCTORS ARE SILICON, Ic.
,l4'-----
.Vee-.
~
6
dV _ Ie
'iIf~c
T
Figure 3C5. Constant Current Power·On Reset Circuit
The 8284 synchronizes the reset input with the CPU
clock to generate the RESET signal to the CPU (Fig.
3C6). The output is also available as a general reset to
the entire system. The reset has no effect on any clock
circuits in the 8284.'
17
CJ
19
8284
Y
18
+5
13
SYSTEM
RESET
ClK 8
X,
X,
Fie
ClK
8086
RESET 10
21
RESET
"::'
11
As discussed previously, the ready signal Is used In the
system to accommodate memory and 1/0 devices that
cannot transfer Information at the maximum CPU bus
bandwidth. Ready Is also used In multiprocessor
systems to force the CPU to walt for access to the
system bus or Multlbus system bus. To Insert a walt
state In the bus cycle, the READY signal to the CPU
must be Inactive (low) by the end of T2. To avoid Insertion of a walt state, READY must be active (high) within
a specified setup time prior to the positive transition
during T3. Depending on the size and characteristics of
the system, ready Implementation may take one of two
approaches.
The classical ready implementation Is to have the
system 'normally not ready.' When the selected device
receives the command (RDIWR/INTA) and has had sufficient time to complete the command, It activates
READY to the CPU, allowing the CPU to terminate the
bus cycle. This implementation is characteristic of large
multiprocessor, Multibus systems or systems where
propagation delays, bus access delays and device characteristics inherently slow down the system. For maximum system performance, devices that can run with no
wait states must return 'READY' within the· previously
described limit. Failure to respond In time will only
result in the insertion of one or. more walt cycles.
An alternate technique Is to have the system 'norm~lIy
ready.' All devices are assumed to operate at the maximum CPU bus bandwidth. Devices that do not meet the
requirement must disable READY by the end of T2 to
guarantee the Insertion of walt cycles. This implementation is typically applied to small single CPU systems
and reduces the logic required to control the ready
signal. Since the,failure ola device requiring wait states
to disable READY by the end of T2 Will result in premature termination of the bus cycle, the system timing
must be carefully analyzed when using this approach.
The 8086 has two different .timing requirements on
READY depending on the system Implementation. For a
'normally ready' system to insert a wait state, the
READY must be disabled within 8 ns (TRYLCL) after the
end of T2 (start of T3) (Diag. 3D1). To guarantee proper
RES
~
Figure 3C6. 8086 Reset and System Reset
CLOCK
80861\EADY
READY INACTIVE 6 ns
119 ns TO GUARANTEE THE
CYCLE IS T4
Diagram 301. Normally Ready System Inserting a Walt State
A-23
AP-67
positive clock transition during T3 (Diag. 3D2). For both
cases, READY must satisfy a hold time of 30 ns
(TCHRYX) from the T3 or TW positive clock transition.
operation of the 8086, the READY input must not change
from ready to not ready during the clock low time of T3.
For a 'normally not ready' system to avoid wait states,
READY must be active within 119 ns (TRYHCH) of the
CLOCK
8088 READY
Diagram 302. Normally Nol Ready Syslem Avoiding a Wall Slale
To generate a stable READY signal which satisfies the
previous setup and hold times, the 8284 provides two
separate system ready inputs (RDY1, RDY2) and a single
synchronized ready output (READY) for the CPU. The
RDY inputs are qualified with separate access enables
(AEN1,AEN2, low active) to allow selecting one of the
two ready signals (Fig. 3D1). The gated signals are
logically OR'ed and sampled at the beginning of each
ClK cycle to generate READY to the CPU (Diag. 3D3).
The sampled READY signal is valid within 8 ns (TRYlCl)
after ClK to satisfy the CPU timing requirements on
'not ready' and ready. Since READY cannot change until
the next ClK, the hold time requirements are also satis·
fied. The system ready inputs to the 8284 (RDY1,RDY2)
must be valid 35 ns (TRIVCl) before T3 and AEN must be
valid 60 ns before T3. For a system using only one RDY
input, the associated AEN is tied to ground while the
other AEN is connected to 5 volts through "-'1 K ohms
(Fig. 3D2a). If the system generates a low active ready
signal, it can be connected to the 8284 AEN input if the
additional setup time required by the 8284 AEN input is
satisfied. In this case, the associated RDY input would
be tied high (Fig. 3D2b).
17
ClK
X,
D
Y
RESET 10
18
X.
FIC
11
3
:r:
READY
19
21
22
ClK
RESET
READY
8086
8284
RES
AEN1
RDY1
7 AEN2
6 RDY2
Figure 301. Ready Inpuls 10 Ihe 8284 and Oulpullo Ihe 8086
---~~o--T.rrw
CLOCK
8284 READY OUT
(TO 8086)
NOTE: THE 8284 DATA SHEET SPECIFIES READY OUT DELAY (TRYlCl) AS -8
'BEFORE' THE END OF T. WHICH IMPLIES THE TIMING SHOWN.
Diagram 303. 8284 with 8086 Ready Timing
A-24
ns
AP-67
memory. If the access to non-existent memory falls to
enable READY, the system will be caught In an Indefinite walt.
.
8284
SYSTEM
READY
ROY1
7 AEN2
8 ROY2
+5
rC~~~-{>r~~~J
C<
74LS73
K
'Q"
Figure 302a. Using ROYlIROY2 to Generate Ready
RDV TO 12&4
Figure 303. Single Walt State Generator
AEI'IT
:=
3
8284
4 ROY1
1K
3E. Interrupt Structure
+5
Figure 302b. Using AEN1/AEN2 to Generate Ready
The majority of memory and peripheral devices. which
fall to operate at the maximum CPU frequency typically
do not require more than one wait state. The circuit
given in Figure 303 Is an example of a simple walt state
generator. The system ready line Is driven low whenever
a device requiring one walt state Is selected. The flip
flop Is cleared by ALE, enabling ROY to the 8284. If no
walt states are required, the flip flop does not change. If
the system ready Is driven low, the flip flop toggles on
the low to high clock transition of T2 to force one walt
state. The next low to high clock transition toggles the
flip flop again to Indicate ready and allow completion of
the bus cycle. Further changes In the state of the flip
flop will not affect the bus cycle. The circuit allows
approximately 100 ns for chip select decode and conditioning of the system ready (Dlag. 304).
If the system Is 'normally not ready,' the programmer
should not assign executable code to the last six bytes
of physical memory. Since the 8086 prefetches Instructions, the CPU may attempt to access non-existent
memory when executing code at the end of physical
The 8086 Interrupt structure Is based on a table of Inter·
rupt vectors stored In memory locations OH through
003FFH. Each vector consists of two bytes for the In·
struction pOinter and two bytes for the code segment.
These two values combine to form the address of the In·
terrupt service routine. This allows the table to contain
up to 256 interrupt vectors which specify the starting ad·
dress of the service routines anywhere In the one mega·
byte address space of the 8086. If fewer than 256 different Interrupts are defined in the system, the user need
only allocate enough memory for the interrupt vector
table to provide the vectors for the defined Interrupts.
During initial system debug, however, it may be desirable to assign all undefined Interrupt types to a trap
routine to detect erroneous interrupts.
Each vector Is associated with an interrupt type number
which pOints to the vector's location in the interrupt vec·
tor table. The Interrupt type number multiplied by four
gives the displacement of the first byte of the associ·
ated interrupt vector from the beginning of the table. As
an example, interrupt type number 5 points to the sixth
entry In the Interrupt vector table. The contents of this
entry in the table points to the Interrupt service routine
for type 5 (Fig. 3E1). This structure allows the user to
specify the memory address of each service routine by
placing the address (instruction pointer and code seg·
ment values) In the table.location provided for that type
interrupt.
Diagram 304.
A-25
AP-67
INTERRUPT TYPE
r
TYPE 1 - SINGLE STEP
MEMORY
~U~B!.R- ~====~~-=--=--=----I-i'~-ooo~~-~;'.,
1------=::-----1
This interrupt type occurs one instruction after the TF
(Trap Flag) is set in the flag register. It is used to allow
software single stepping through a sequence of code.
Single stepping is initiated by copying the flags onto the
stack, setting the TF bit on the stack and popping the
flags. The interrupt routine should be the single step
routine. The interrupt sequence saves the flags and program counter, then resets the TF flag to allow the single
step routine to execute normally. To return to the
routine under test, an interrupt return restores the IP,
CS and flags with TF set. This allows the execution of
the next instruction in the program under test before
trapping back to the single step routine. Single Step is
not masked by the IF (Interrupt Flag) bit in the flag
register.
004
008
1----=:-----1 ooe
INTERRUPT
VECTOR
TABLE
INTERRUPT
VECTOR TABLE
ADDRESS
TYPE 5 INTERRUPT
SERVICE ROUTINE
L-_ _ _ _- '
TYPE 2 -
FFFFE
Figure 3E1. Direction to Interrupt Service Routine through the
Interrupt Vector Table
All Interrupts in the 8086 must be assigned an Interrupt
type which uniquely identifies each Interrupt. There are
three classes of interrupt types in the 8086; predefined
interrupt types which are Issued by specific functions
within the 8086 and user defined hardware and software
Interrupts. Note that any Interrupt type including the
predefined interrupts can be Issued by the user's hardware and/or software.
TYPE 3 - ONE BYTE INTERRUPT
This is invoked by a special form of the software interrupt instruction which requires a single byte of code
space. Its primary use is as a breakpoint Interrupt for
software debug. With full representation within a single
byte, the instruction can map Into the smallest instruction for absolute resolution in setting breakpOints. The
interrupt Is not maskable.
PREDEFINED INTERRUPTS
The predefined Interrupt types In the 8086 are listed
below with a brief description of how each is Invoked.
When Invoked, the CPU will transfer control to the
memory location specified by the vector associated
with the specific type. The user must provide the interrupt service routine and Initialize the interrupt vector
table with the appropriate service routine address. The
user may additionally Invoke these Interrupts through
hardware or software. If the preassigned function Is not
used In the system, the user may aSSign some other
function to the associated type. However, for compatibility with future Intel hardware and software products for the 8086 family, Interrupt types 0-31 should not
be assigned as user defined interrupts.
TYPE 0 -
NMI (Non-Maskable Interrupt)
This is the highest priority hardware interrupt and is
non-maskable. The input is edge triggered but is synchronized with the CPU clock and must be active for two
clock cycles to guarantee recognition. The interrupt
signal may be removed prior to entry to the service
routine. Since the input must make a low to high transition to generate an interrupt, spurious transitions on the
Input should be suppressed. If the Input is normally
high, the NMI low time to guarantee triggering is two
CPU clock times. This input is typically reserved for
catastrophic failures like power failure or timeout.of a
system watchdog timer.
TYPE 4 -
INTERRUPT ON OVERFLOW
This Interrupt occurs if the overflow flag (OF) is set In
the flag register and the INTO Instruction Is executed.
The Instruction allows trapping to an overflow error service routine. The Interrupt is non-maskable.
Interrupt types 0 and 2 can occur without specific action
by the programmer (except for performing a divide for
Type 0) while types 1,3, and 4 require a conscious act by
the programmer to generate these interrupt types. All
but type 2 are invoked through software activity and are
directly associated with a specific Instruction.
DIVIDE ERROR
This Interrupt type Is Invoked whenever a division operation Is attempted during which the quotient exceeds the
maximum value (ex. division by zero). The interrupt Is
non-maskable and Is entered as part of the execution of
the divide Instruction. If Interrupts are not reenabled by
the divide error interrupt service routine, the service
routine execution time should be included in the worst
case divide instruction execution time (primarily when
conSidering the longest Instruction execution time and
Its effect on latency to servicing hardware interrupts).
USER DEFINED SOFTWARE INTERRUPTS
The user can generate an interrupt through the software
with a two byte Interrupt instruction INT nn. The first
byte Is the INT opcode while the second byte (nn) contains the type number of the Interrupt to be performed.
The INT Instruction Is not maskable by the interrupt
enable flag. This Instruction can be used to transfer control to routines that are dynamically relocatable and
whose location in memory is not known by the calling
A-26
AP-67
program. This technique also saves the flags of the call·
Ing program on the stack prior to transferring control.
The called procedure must return control with an inter·
rupt return (I RET) instruction to remove the flags from
the stack and fully restore the state of the calling program.
All Interrupts Invoked through software (all Interrupts
discussed thus far with the exception of NMI) are not
maskable with the IF flag and initiate the transfer of
control at the end of the instruction in which they occur.
They do not initiate interrupt acknowledge bus cycles
and will disable subsequent maskable interrupts by
resetting the IF and TF flags. The interrupt vector for
these interrupt types is either implied or specified In the
instruction. Since the NMI is an asynchronous event to
the CPU, the point of recognition and Initiation of the
transfer of control Is similar to the maskable hardware
interrupts.
UNINTERRUPTABLE INSTRUCTION SEQUENCE
MOY SS, NEW$STACK$SEGMENT
MOY SP, NEW$STACK$POINTER
Also, s.lnce prefixes are considered part of the instruction they precede, the 8086 will not sample the interrupt
line until completion. of the instruction the preflx(es)
precede(s). An exception to this (other than HALT or
WAIT) is the string primatives preceded by the repeat
(REP) prefix. The repeated string operations will sample
the interrupt line at the completion of each repetition.
This includes repeat string operations which include the
lock prefix. If multiple prefixes precede a repeated
string operation, and the instruction is interrupted, only
the prefix immediately preceding the string primative is
restored. To allow correct resumption of the operation,
the following programming technique may be used:
LOCKED$BLOCK$MOVE: LOCK REP MOVS DEST, CS:SOURCE
AND CX,
CX
USER DEFINED HARDWARE INTERRUPTS
JNZ LOCKED$BLOCK$MOVE
The maskable interrupts initiated by the system hardware are activated through the INTR pin of the 8086 and
are masked by the IF bit of the status register (interrupt
flag). During the last clock cycle of each Instruction, the
state of the INTR pin Is sampled. The 8086 deviates from
this rule when the instruction Is a MOY or POP to a segment register. For this case, the Interrupts are not
sampled until completion of the following Instruction.
This allows a 32-bit pOinter to be loaded to the stack
pointer registers SS and SP without the danger of an Interrupt occurring between the two loads. Another exception is the WAIT Instruction which walts for a low active
input on the TEST pin. This Instruction also continuously samples the interrupt request during Its execution
and allows servicing interrupts during the walt. When an
interrupt Is detected, the WAIT instruction is again
fetched prior to servicing the interrupt to guarantee the
interrupt routine will return to the WAIT Instruction.
I
ALE
T,
I
T2
T3
T4
TI
The code bytes generated by the 8086 assembler for the
MOYS instruction are (in descending order): LOCK
prefix, REP prefix, Segment Override prefix and MOYS.
Upon return from the interrupt, the segment override
prefix Is restored to guarantee one additional transfer is
performed between the correct memory locations. The
Instructions following the move operation test the
repetition count value to determine If the move was
completed and return If not.
If the INTR pin Is high when sampled and the IF bit is set
to enable Interrupts, the 8086 executes an interrupt
acknowledge sequence. To guarantee the interrupt will
be acknowledged, the INTR input must be held active
until the Interrupt acknowledge is issued by the CPU. If
the BIU Is running a bus cycle when the interrupt condition is detected (as would occur if the BIU is fetching an
Instruction when the current instruction completes), the
TI
T,
I
T2
f\'----_~--Jn'------_
\L-_ _ _ _---...JI
FLOAT
ADo-AD15
BY CPU IF QUEUE 15 NOT FULL
Figure 3E2. Interrupt Acknowledge Sequence
A-27
AP-67
Interrupt must be valid at the 8086 2 clock cycles prior to
T4 of the bus cycle if the next cycle is to bean interrupt
acknowledge cycle. If the 2 clock setup is'notsatisfied,
another pending bus cycle will be executed before the
Interrupt acknowledge is issued, If a hold request is also
pending (this might occur if an interrupt and hold request are made during execution of a locked instruction), the interrupt is serviced after the hold request Is
serviced.
Theinterrupt.acknowledge sequence is only generated
In response to an interrupt on the 8086 INTR input. The
associated bus activity is shown in Figure 3E2. The cycle consists of two INTA bus cycles separated by two
Idle clock cycles. During the bus cycles the INTA com·
mand is Issued rather than read. No address is provided
by the 8086 during either bus cycle (BHE and status are
valid), however, ALE is still generated and will load the
address latches' with indeterminate Information. This
condition requires .that devices In the system do not
drive their outputs without being qualified by the Read
Command. As will be shown later, the ALE is useful in
maximum mode systems with multiple 8259A priority In·
terrupt controllers. During the INTA bus cycles, DT/R
and DEN are conditioned to allow the 8086 to receive a
one byte interrupt type number from the interrupt
system. The first INTA bus cycle signals an interrupt
acknowledge cycle Is in progress and allows the system
to prepare to presentthe Interrupt type number on the
next INTA bus cycle. The CPU does not capture informa·
tion on the bus during the first cycle. The type number
must be transferred to the 8086 on the lower half of the
16-blt data bus during the second cycle. This· Implies
that devices which present Interrupt type numbers to
the 8086 must be located on the lower half of the 16·bit
databus. The timing of the INTA bus cycles (with exception of address timing) is similar to read cycle timing.
The 8086 Interrupt acknowledge . sequence deviates
from.the form used on 8080 and 8085 In that no instruction Is issued as part of the sequence. The 8080 and
8085 required either a restart or call instruction be
Issued to affect the transfer of control.
In the minimum mode system, the MilO signal will be
low Indicating I/O during the INTA bus cycles. The 8086
internal LOCK signal will be active from T2 of the first
bus cycle until T2 of the second to prevent the BIU from
honoring a hold request between the two INTA cycles.
In the maximum mode, the status lines SO-52 will request the 8288 to activate the INTA output for each cycle. The LOCK output of the 8086 will be active from T2
of the first cycle until T2 of the second to prevent the
8086 from honoring a hold request on either RQ/GT input and to prevent bus arbitration logic from relinquish·
Ing the bus between INTA's In multi·master systems.
The consequences of READY are Identical to those for
READ and WRITE cycles.
Once the 8086 has the Interrupt type number (from the
bus for hardware Interrupts, from the Instruction stream
for software Interrupts or from· the predefined condition), the type number Is multiplied by four to form the
displacement to the corresponding interrupt vector in
the Interruot vector table. The four bytes of the interrupt
vector are: least significant byte of the instruction
pOinter, most significant byte of the Instruction pointer;
least significant· byte of the code segment register,
most significant byte of the code segment register. Dur·
ing the transfer of control, the CPU pushes the flags and:
current code segment register and instruction pointer
onto the stack. The new code segment and instruction
pointer values are loaded and the single step and interrupt flags are reset.Resetting the interruptflag disables
response to further hardware interrupts in the service
routine unless the flags are specifically re·enabled by
the service routine. The CS and IP values are read from
the interrupt vector table with data read cycles. No segment registers are used when referencing the vector
table during the interrupt context switch. The vector
displacement isadded to zero to form the 20-bit address
and. 54,.53 = 10 indicating no segment register selection.
The actual bus activity associated with the hardware interrupt acknowledge sequence is as follows: Two Interrupt acknowledge bus cycles, read new IP from the interrupt vector table, read new CS from the interrupt vector table, Push flags, Push old CS, Opcode fetch of the
first .instructionof the interrupt service. routine, and
Push old IP. After saving the.old IP, the BIU will resume
normal operation of prefetching instructions Into the
queue and servicing EU requests .for operands. 55 (interrupt enable flag status) will go inactive in the second
clock cycle following reading the new CS.
The number of clock cycles from the end of the instruction during which the interrupt occurred to the start of
interrupt routine execution is 61 clock cycles. For software generated interrupts, the sequence of bus cycles
Is the same except no interrupt acknowledge bus cycles
are executed. This reduces the delay to service routine
execution to 51 clocks for INT nri and single step, 52
clocks for INT3 and 53 clocks for INTO. The same Interrupt setup requirements with respect to the BIU that
were stated for the hardware interrupts also apply to the
software interrupts. If wait states are inserted by either
the memories or the device supplying the interrupt type
number, the given clock times will increase accordingly.
When considering the precedence of interrupts for
multiple simultaneous interrupts, the following guidelines apply: 1.INTR is the only maskable interrupt and if
detected simultaneously with other interrupts, resetting
of IF by the other interrupts will mask INTR. This causes
INTR to be the lowest priority interrupt serviced after all
other interrupts unless the other interrupt service
routines reenable interrupts. 2. Of the nonmaskable Interrupts (NMI, Single Step and software generated), In
general, Single Step has highest priority (will be serviced first) followed by NMI, followed by the software Interrupts. This Implies that a simultaneous NMI and
Single Step trap will cause the NMI service routine to
follow single step; a simultaneous software trap and
Single Step trap will cause the software Interrupt service routine to follow single step and a simultaneous
NMI and software trap will cause the NMI service
routine to be executed followed by the software Interrupt service routine. An exception to this priority structure occurs if all three interrupts are pending. For this
case, transfer of control to the software Interrupt ser-
A-28
AP-67
vice routine followed by the NMI trap will cause both the
NMI and software interrupt service routines to be executed without single stepping_ Single stepping
resumes upon execution of the instruction following the
Instruction causing the software interrupt (the next instruction in the routine being single stepped).
TF=l
IF=l
INTR
If the user does not wish to single step before INTR service routines, the single step routine need only disable
interrupts during execution of the program being single
stepped and reenable interrupts on entry to the single
step routine. Disabling the Interrupts during the program under test prevents entry into the Interrupt service
routine while single step (TF = 1) Is active. To prevent
single stepping before NMI service routines, the single
step routine must check the return address on the stack
for the NMI service routine address and return control to
that routine without single step enabled. As examples,
consider Figures 3E3a and 3E3b. In 3E3a Single Step
and NMI occur simultaneously while in 3E3b, NMI, INTR
and a divide error all occur during a divide Instruction
being single stepped.
TF,IF=l
NMI
CONTINUE TO SINGLE STEP
THE PROGRAM
Figure 3E3b. NMI. INTR. Single Step and Divide Error Simultaneous
Interrupts
NORMAL SINGLE STEP
OPERATION
SYSTEM CONFIGURATIONS
To accommodate the INTA protocol of the maskable
hardware Interrupts, the 8259A Is provided as part of the
8086 family. This component Is programmable to
operate In both 8080/8085 systems and 8086 systems.
The devices are cascadable In master/slave arrangements to allow up to 64 Interrupts In the system. Figures
3E4 and 3E5 are examples of 8259A's In minimum and
maximum mode 8086 systems. The minimum mode configuration (a) shows an 8259A connected to the CPU's
Figure 3E3a. NMI During Single Stepping and Nonnal Single Step
Operallon
A-29
AP·67
the 8086/8288 to control the bus transceivers. To selec.t
the proper slave when servicing a slave .Interrupt, the
master must provide a cascade address to the slave. If
the 8288 is not strappedlnthe 1/0 bu.smode (the 8288
lOB Input connected to ground), the MCE/PDEN output
becomes a MCEor Master Cascade Enable output. This
signal Is only.actlve dur[ng INTA cycles as shown In
Figure 3E6 and enables the master 8259A's cascade ad·
dress onto the 8086's local bus dui'ing ALE: This allows
the address latches to capture the cascade address with
ALE and allows use of the system address bus for
selecting the proper slave 8259A. The MCE Is gated with
LOCK to minimize local bus contention between the
8086 three·statlng Its bus outputs and Hie cascade ad·
dress being enabled onto the bus. The first INTA bus cy·
cle allows the master to resolve internal priorities and
output a cascade address to be transmitted to the.
slaves on the subsequentilii'fA. bus cycle. For ilddltlonaf
information qn the 8259A, reference application· note
AP·59.
.
multiplexed bus. Configuration (b) Illustrates an 8259A
connected to a demultiplexed bus system. These inter·
connects are also applicable to maximum mode
systems. The configuration given for a maximum mode
system shows a master 8259A on theCPU's multiplexed
bus with additional slave 8259A's .out on the buffered
system bus. This configuration demonstrates several
unique features of the maximum mode system Inter·
face. If the master 8259A receives Interrupts from a mix
of slave 8259A's and regular Interrupting devices, the
slaves must provide the type number for devices con·
nected to them while the master provides the type
number for devices directly attached to Its Interrupt in·
puts. The master 8259A is programmable to determine if
an interrupt is from a direct input or a slave 8259A and
will use this information to enable or disable the data
bus transceivers (via .the 'nand' function of DEN and
EN). If the master must provide the type number, It will
disable the data bus transceivers. If the slave provides
the type number, the master will enable the data bus
transceivers. The EN output is normally high to allow
t-__....L._ _ _--I.....L.-'-_-'--'-_ _..... ,
ADDRESS
~--~---~rT---,-r--~/BUS
IJL------....::..::..--....::..::..--...J,
DATA
I \ r - - - - - - - - - - ' - - - - - , / BUS
a.
b.
Figura 3E4. 'Min Mode 8086 ';Ith ·Mastar 8259A on tha Local Bus ·and
A-30
Slav~ 8259As on tha ·Systam Bus
AP-67
ADDRESS
~'-------'--------r,---------,-~------,/BUS
r~----------------~~------~~------~\DATA
BUS
Figure 3E5. Max Mode 8086 with Master 8259A on the Local Bus and Slave 8259As on the System Bus
1
ALE
ADo-AD"
T,
I
_ _---Jn,------,--_
\\..--_ _-------,-_---11
T2
T3
T4
TI
TI
T,
I
T,
T,
J\~
FLOAT
FLOAT
\\..--_ _ _--J/
\\--.--
Figure 3E8. MCE Timing to Gate 8259A CAS Addre •• onto the 8086 Local Bus
A-31
AP-67
3F. Interpreting the 8086 Bus Timing Diagrams
At first glance, the 8086 bus timing diagrams (Diag. 3F1
min mode and Diag. 3F2 max mode) appear rather com·
plex. However, with a few words of explanation on how
to interpret them, they become a powerful tool in deter·
mining system requirements. The timing diagrams for
both the minimum and maximum modes may be divided
into six sections: (1) address and ALE timing; (2) read cy·
cle timing; (3) write cycle timing; (4) interrupt acknowl·
edge timing; (5) ready timing; and (6) HOLD/HLDA or
RQ/GT timing. Since the A.C. characteristics of the
signals are specified relative to the CPU clock, the rela·
tionship between the majority of signals can be de·
duced by simply determining the clock cycles between
the clock edges the signals are relative to and adding or
subtracting the appropriate minimum or maximum
parameter values. One aspect of system timing not com·
pensated for in this approach is the worst case relation·
ship between minimum and maximum parameter values
(also known as tracking relationships). As an example,
consider a signal which has specified minimum and
maximum turn on and turn off delays. Depending on
device characteristics, it may not be possible for the
component to simultaneously demonstrate a maximum
turn·on and minimum turn·off. delay even though worst
case analysis might imply the possibility. This argument
is characteristic of MOS devices and is therefore ap·
plicable to the 8086 A.C. characteristics. The message
is: worst case analysis mixing minimum and maximum
delay parameters will typically exceed the worst case
obtainable and therefore should not be subjected to fur·
ther subjective degradation to obtain worst·worst case
values. This section will provide guidelines for specific
areas of 8086 timing sensitive to tracking relationships.
A. MINIMUM MODE BUS TIMING
1. ADDRESS and ALE
The address/ALE timing relationship is important to
determine the ability to capture a valid address from the
multiplexed bus. Since the 8282 and 8283 latches cap·
ture the address on the trailing edge of ALE, the critical
timing involves the state of the address lines when ALE
terminates. If the address valid delay is assumed to be
maximum TCLAV and ALE terminates at its earliest
point, TCHLLmin (assuming zero minimum delay), the
address would be valid only TCLCHmin·TCLAVmax= 8
ns prior to ALE termination. This result is unrealistic in
the assumption of maximum TCLAV and minimum
TCHLL. To provide an accurate measure of the true
worst case, a separate parameter specifies the
minimum time for address valid prior to the end of ALE
(TAVAL). TAVAL= TCLCH·60 ns overrides the clock
related timings and guarantees 58 ns of address setup
to ALE termination for a 5 MHz 8086. The address is
guaranteed to remain valid beyond the end of ALE by the
TLLAX parameter. This specification overrides the rela·
tionship between TCHLL and TCLAX which might seem
to imply the address may not be valid by the end of the
latest possible ALE. TLLAX holds for the entire address
bus. The TCLAXmin spec on the address indicates the
earliest the bus will go invalid if not restrained by a slow
ALE. TLLAX and TCLAX apply to the entire multiplexed
bus for both read and write cycles. AD15·0 is three·
A-32
stated for read cycles and immediately switched to
write data during write cycles. AD19·16 immediately
switch from address to status for both read and write
cycles. The minimum ALE pulse width is guaranteed by
TLHLLmin which takes precedence over the value obtained by reiating TCLLHmax and TCHLLmin.
To determine the worst case delay to valid address on a
demultiplexed address bus, two paths must be con·
sidered: (1) delay of valid address and (2) delay to ALE.
Since the 8282 and 8283 are flow through latches, a valid
address is not transmitted to the address bus until ALE
is active. A comparison of address valid delay TCLAV·
max with ALE active delay TCLLHmax indicates TCLAVmax is the worst case. Subtracting the latch propagation delay gives the worst case address bus valid
delay from the start of the bus cycle.
2. Read Cycle Timing
Read timing consists of conditioning the bus, activating
the read command and establishing the data transceiver
enable and direction controls. DT/R is established early
in the bus cycie and requires no further consideration.
During read, the DEN signal must allow the transceivers
to propagate data to the CPU with the appropriate data
setup time and continue to do so until the required data
hold time. The DEN turn on delay allows TCLCL+
TCHCLmin - TCVCTVmax - TDVCL= 127 ns transceiver
enable time prior to valid data required by the CPU.
Since the CPU data hold time TCLDXmin and minimum
DEN turnoff delay TCVCTXmin are both 10 ns relative to
the same clock edge, the hold time is guaranteed. Additionally, DEN must disable the transceivers prior to the
CPU redriving the bus with the address for the next bus
cycle. The maximum DEN turn off delay (TCVCTXmax)
compared with the minimum delay for addresses out of
the 8086 (TCLCL+ TCLAVmin) indicates the transceivers are disabled at least 105 ns before the CPU
drives the address onto the multiplexed bus.
If memory or I/O devices are connected directly to the
multiplexed address and data bus, the TAZRL parameter
guarantees the CPU will float the bus before activating
read and allowing the selected device to drive the bus.
At the end of the bus cycle, the TRHAV parameter specifies the bus float delay the device being deselected
must satisfy to avoid contention with the CPU driving
the address for the next bus cycle. The next bus cycle
may start as soon as the cycle following T4 or any
number of clock cycles later.
The minimum delay from read active to valid data at the
CPU is 2TCLCL - TCLRLmax - TDVCL = 205 ns. The
minimum pulse width is 2TCLCL- 75 ns= 325 ns. This
specification (TRLRH) overrides the result which could
be derived from clock relative delays (2TCLCLTCLRLmax + TCLRHmin).
3. Write Cycle Timing
The write cycle involves providing write data to the
system, generating the write command and controlling
data bus transceivers. The transceiver direction control
signal DT/A is conditioned to transmit at the end of each
read cycle and does not change during a write cycle.
AP-67
This allows the transceiver enable signal DEN to be active early In the cycle (while addresses are valid) without
corrupting the address on the multiplexed bus_ The
write data and write command are both enabled from the
leading edge of T2_ Comparing minimum WR active
delay TCVCTVmln with the maximum write data delay
TCLDV Indicates that write data may be not valid until
100 ns after write Is active. The devices in the system
should capture data on the trailing edge of the write
command rather than the leading edge to guarantee
valid data. The data from the 8086 is valid a minimum of
2TCLCL - TCLDVmax + TCVCTXmin = 300 ns before the
trailing edge of write. The minimum write pulse width Is
TWLWH = 2TCLCL- 60 ns=340 ns. The CPU maintains
valid write data TWHDX ns after write. The TWHDZ specIfication overrides the result derived by relating
TCLCHmin and TCHDZmln which Implies write data
may only be valid 18 ns afterWR. The 8086 floats the bus
after write only If being forced off the bus by a HOLD or
RQ Input. Otherwise, the CPU simply switches the output drivers from data to address at the beginning of the
next bus cycle. As with the read cycle, the next bus cycle may start In the clock cycle following T4 or any clock
cycle later.
DEN Is disabled a minimum of TCLCHmln +
TCVCTXmln - TCVCTXmax = 18 ns after write to
guarantee data hold time to the selected device. Since
we are again evaluating a minimum TCVCTX with a maximum TCVCTX, the real minimum delay from the end of
write to transceiver disable Is approximately 60 ns.
4. Interrupt Acknowledge Timing
The Interrupt acknowledge sequence consists of two Interrupt acknowledge bus cycles as previously described. The detailed timing of each cycle is Identical to
the read cycle timing with two exceptions: command
timing and address/data bus timing.
Tw
ClK (8284 OUTPUT)
MOO
I
ALE
TAVAl-
RDY (8284 INPUT)
SEE NOTE4
TAVAL
TClAV
TCLOX-
TClRH-
READ CYCLE
TCHCTV
NOTE 1
TClRll---+o-f--'---f--TRlRH
---r--I
DT/R
TCVCTX-
Figure 3F1. 8086 Bus Timing -
A-33
Minimum Mode System
r--
AP-67
.!
','
CLK (8284 OUTPUT)
M/iO
ALE
AD1S-ADo
WRITE CYCLE
NOTE 1
(iiD,iiffiI,
DTIII.vOHI
INTACYCLE
NOTES163
DTIR
iiD, WII=VOH
IilfE.VoLI
'
SOFTWARE HALT - (DEN =
VOL: RD, WA, iNn DTiii. VOH; AD1S-ADo
TI'S FOLlOWT1, THEN NMI OR INTR
BEGIN A NEW Tl.
INVALID ADDRESS
AD1S-ADo
TClAV
;
NOTES:
1. ALL SIGNALS SWITCH BETWEEN VOH AND VOl UNLESS OTHERWISE
SPECIFIED.
2. RDY IS SAMPLED NEAR THE END OF T., T3, TW TO DETERMINE IF TW
MACHINES STATES ARE TO BE INSERTED.
,
3. BOTH INTA CYCLES' RUN BACK·TO·BACK. THE 8088 LOCAL ADDRIDATA BUS IS
FLOATING DURING THE SECOND INTA CYCLE. CONTROL SIGNALS SHOWN
FOR SECOND INTA CYCLE.
4. SIGNALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.
Figure 3Fl. 8086 Bus Timing -
Minimum Mode System (Con't)
A-34
AP-67
1H ____
----.J
T,
T,
- T C L C L - TCH1CH2
CLK
VCH~
.-1
VCL
TCLAV~
aSo,as,
I-
----
f
~
I-TCL2CL1
TSVLH
TCLLH~
!-TCLCH_
TCHSV
1+ TCLSH
~
Wffi W
SEE NOTE 5
~CLDV
BiiE, A19-A18
1
SEE NOTE8
TCHDX-
fTCLAV
TCLAX-
~
J
ALE (8288 aUTPUT)
I----~
~ TCHCL
s,,"S1,s, (EXCEPT HALT)
-
r~
- .r
57.5 3
TCHLL
'\
1-*1
\
------
'------
t
r
i- T
r-{---
1VCL
~~~,-~~
-
RDY (8284 INPUT)
TRYLCL·_
t'"~
.
READ CYCLE
TCLAV-
-I
LHCH-f
E .•.
-TCLAZ
~
-TCHRYX
-
~DVCL-!-TCLDX-
'~
~"'"
I-'-
TAZRL-
TCHDTL-
TRLRH
-
TCLML-
TCLMH-
8288 aUTPUTS
SEE NOTES 5,8
TCVNVDEN
II-'-
~
TCVNX-
Figure 3F2a. 8086 Bus Timing -
Maximum Made System (Using 8288)
A-35
TRHAV
I\~
TCLRL
{
FL~:J'
TCLRH
V
RD
DT/A
-
A
TCHDTH
AP-67
T,
T,
Tw
ClK
VCl
S;,s"So (EXCEPT HALT)
',""----
WRITE CYCLE
TCHDX-
DATA
AD1S-ADO
TCVNX-
DEN
TCLMH8288 OllTPlO'S
SEE,NOTES 5,6
AMWC OR AIOWC
MWTC OR lowe, ,
INTACYCLE
ACtS-ADo
SEe NOTES 3 & 4
I
MCEI
=
OTIR
SOFTWARE HALT (I!ER _ vOL;IIJ),IfII1rn,=,~,AMWC,Il!WC,AIOWC,INT A,DT/A = VOH)
INVALID ADDRESS
TeLAV
/r-----------.-, -------
~
\'---~
NOTES:
'\._-----
1. ALL SIGNALS SWITCH BETWEEN VOH AND VOL UNLESS OTHERWISE
SPECIFIED.
2. RoY IS SAMPLED NEAR THE END OF 12. T3. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. CASCADE ADDRESS IS VALID BETWEEN FIRST AND SECOND INTA CYCLES.
4. BOTH INTA CYCLES RUN BACK·TO·BACK. THE 8088 LOCAL ADDRIDATA BUS IS
FLOATING DURING THE SECOND INTA CYCLE. CONTROL FOR POINTER ADDRESS
IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNALS AT 8284 OR 8288 ARE SHOWN FOR REFERENCE ONLY,
6. THE ISSUANCE OF THE 8288 COMMAND AND CONTROL SIQNALS~.
1olWTe, AMWe, IOI!C, 10m, AR!\YC, lIlTA AND DEN) LAOS THE ACTIVE HIOH
8288 CEN.
7. ALL TIMINQ MEASUREMENTS ARE MADE AT 1.6V UNLESS OTHERWISE
NOTED.
8. STATUS INACTIVE IN STATE JUST PRIOR TO Te.
Figure 3F2b. 8086 Bus Timing -
Maximum Mode System (Using 8288) (Con'l)
A-36
r--
AP-67
The multiplexed address/data bus floats from the begInning (T1) of the INTA cycle (within TCLAZ ns)_ The upper
four multiplexed address/status lines do not three-state.
The address value on A19-A16 is Indeterminate but the
status Information will be valid (S3=0, S4=0, S5=IF,
S6=0, S7= BHE=O)~ The multiplexed address/data
lines will remain In three-state until the cycle after T4 of
the INTA cycle. This sequence occurs for each of the
INTA bus cycles. The interrupt type number read by the
8086 on the second INTA bus cycle must satisfy the
bame setup and hold times required for data during a
read cycle.
normally ready, devices not requiring walt states do
nothing to ROY while devices needing walt states
should disable ROY via the address decode and use a
combination of address decode and command to activate a delay to re-enable ROY.
The OEN and OT/R signals are enabled for each INTA cycle and do not remain active between the two cycles.
Their timing for each cycle is identical to the read cycle.
6. Other Considerations
If the system requires no walt states for memory and a
fixed number of wait states for RD and WR to all I/O
devices, the M/iO signal can be used as an early Indication of the need for walt cycles. This allows a common
circuit to control ready timing for the entire system
without feedback of address decodes.
Detailed HOLO/HLDA timing Is covered In the next section and is not examined here. One last signal con~
sideration needs to be mentioned for the minimum
mode system. The TEST Input is sampled by the 8086
only during execution of the WAIT Instruction. The TEST
signal should be active for a minimum of 6 clock cycles
during the WAIT instruction to guarantee detection.
The INTA command has the same timing as the write
command. It is active within 110 ns of the start of T2 providing 260 ns of access time from command to data
valid at the 8086. The command is active a minimum of
TCVCTXmln = 10 ns into T4 to satisfy the data hold time
of the 8086. This provides minimum INTA pulse width of
300 ns, however taking signal delay tracking into consideration gives a minimum pulse width of 340 ns. Since
the maximum Inactive delay of INTA is TCVCTXmax=
110 ns and the CPU will not drive the bus until 15 ns
(TCLAVmln) Into the next clock cycle, 105 ns are available for Interrupt devices on the local bus to float their
outputs. If the data bus is buffered, OEN provides the
same amount of time for local bus transceivers to threestate their outputs.
5. Ready Timing
The detailed timing requirements of the 8086 ready
signal and the system ready signal Into the 8284 are
described in Section 30. The system ready signal is
typically generated from either the address decode of
the selected device or the address decode and the command (RO, WR, INTA). For a system which is normally
not ready, the time to generate ready from a valid address and not insert a walt state, is 2TCLCLTCLAVmax- TR1VCLmax= 255 ns. This time Is available for buffer delays and address decoding to determine If the selected device does not require a walt state
and drive the ROY line high. If wait cycles are required,
the user hardware must provide the appropriate ready
delay. Since the address will not change until the next
ALE, the ROY will remain valid throughout the cycle. If
the system Is normally ready, selected devices requiring
walt states also have 255 ns to disable the ROY line. The
user circuitry must delay re-enabling ROY by the appropriate number of walt states.
If the RO command is used to enable the ROY signal,
TCLCL- TCLRLmax- TRIVCLmax= 15 ns are available
for external logic. If the WR command Is used, TCLCLTCVCTVmax - TRIVCLmax = 55 ns are avai lable. Comparison of ROY control by address or command Indicates that address decoding provides the best timing.
If the system Is normally not ready, address decode
alone could be used to provide ROY for devices not requiring wait states while devices requiring wait states
may use a combination of address decode and command to activate a wait state generator. If the system Is
B. MAXIMUM MOOE BUS TIMING
The maximum mode 8086 bus operations are logically
equivalent to the minimum mode operation. Detailed
timing analysis now involves signals generated by the
CPU and the 8288 bus controller. The 8288 also provides
additional control and command signals which expand
the flexibility of the system.
1. ADDRESS and ALE
In the maximum mode, the address information continues to come from the CPU while the ALE strobe is
generated by the 8288. To determine the worst case relationships between ALE and the address, we first must
determine 8288 ALE activation relative to the SO-S2
status from the CPU. The maximum mode timing
diagram specifies two possible delay paths to generate
ALE. The first is TCHSV + TSVLH measured from the rising edge of the clock cycle preceding T1. The second
path is TCLLH measured from the start of T1. Since the
8288 initiates a bus cycle from the status lines leaving
the passive state (SO-52 = 1), if the 8086 is late In issuing
the status (TCHSVmax) while the clock high time is a
minimum (TCHCLmln), the status will not have changed
by the start of T1 and ALE Is Issued TSVLH ns after the
status changes. If the status changes prior to the beginning of T1, the 8288 will not Issue the ALE until TCLLH
ns after the start of T1. The resulting worst case delay to
enable ALE (relative to the start of T1) is TCHSVmax+
TSVLHmax - TCHCLmln = 58 ns_ Note, when calculating signal relationships, be sure to use the proper
maximum mode values rather than equivalent minimum
mode values.
The trailing edge of ALE Is triggered In the 8288 by the
positive clock edge in T1 regardless of the delay to
enable ALE. The resulting minimum ALE pulse width Is
TCLCHmax-58ns=75ns .assuming TCHLL=O.
TCLCHmax must be used since TCHCLmln was assumed to derive the 58 ns ALE enable delay. The address is guaranteed to be valid TCLCHmln +
TCHLLmln- TCLAVmax=8 ns prior to the trailing edge
A-37
AP-67
of ALE to capture the address in the 8282 or 8283
latches. Again we have assumed a very conservative
TCHLL= O. Note, since the address and ALE are driven
by separate devices, no tracking of A.C. characteristics
can be assumed.
The address hold time to the latches is guaranteed by
the address remaining valid until the end of T1 while
ALE is disabled a maximum of 15 ns from the positive
clock transition in T1(TCHCLmin - TCHLLmax = 52 ns
address hold time). The multiplexed bus transitions
from address to status and write data orthree·state (for
read) are identical to the minimum mode timing. Also,
since the address valid delay (TCLAV) remains the
critical path in establishing a valid address, the address
access times to valid data and ready are the same as the
minimum mode system.
2. Read Cycle Timing
The maximum mode system offers read signals
generated by both the 8086 and the 8288. The 8086 RD
output signal timing is identical to the minimum mode
system. Since the A.C. characteristics of thl'! read commandsgenerated by. the 8288 are significantly better
than the 8086 output, access to devices on the demul·
tiplexed buffered system bus should use the 8288 commands. The 8086 RD signal is available for devices
which reside directly on the multiplexed bus. The
following evaluations for read, write and· interrupt
acknowledge only consider the 8288 command timing.
The 8288 provides separate memory and 110 read Signals
which conform to the same A.C. characteristics. The
commands are Issued TCLML ns after the start of T2
and terminate TCLMH· ns after the start of T4. The
minimum command length is 2TCLCL- TCLMLmax +
TCLMLmin = 375 nS.The access time to valid data at the
CPU is 2TCLCL- TCLMLmax - TDVCLmax = 335 ns.
Since the 8288 was designed for systems with buffered
data busses, the commands are enabled before the CPU
has three·stated the multiplexed bus and should not be
used with devices which reside directly on the multi·
plexed bus (to do so could result In bus contention duro
ing 8086 bus float and device turn-on).
The direction control for data bus transceivers Is estab·
lished in T1 while the transceivers are not enabled by
DEN until the positive clock transition of T2. This pro·
vides TCLCH + TCVNVmin = 123 ns for 8086 bus float
delay and TCHCLmin + TCLCL - TCVNVmaxTDVCLmax = 187 ns of transceiver active to data valid at
the CPU. Since both DEN and command are valid a mini·
mum of 10 ns into T4, the CPU data hold time TCLDX is
guaranteed. A maximum DEN disable of 45 ns (TCVNX
max) guarantees the transceivers are disabled by the
start of the next 8086 bus cycle (215 ns minimum from
the same clock edge). On the positive clock transition of
T4, DT/R is returned to transmit in preparation for a
possible write operation on the next bus cycle. Since
the system memory and 110 devices reside on a buffered
system bus, they must three-state their outputs before
the device ·for the next bus cycle is selected (approxi·
mately 2TCLCL) or the transceivers drive write data onto
the bus (approximately 2TCLCL).
3. Write Cycle Timing
Inthe maximum mode, the 8288 provides normal and advanced write commands for memory and 110. The ad·
vanced write commands are active a full clock cycle
ahead of the normal write comniands .and have timing
identical. to the read commands. The advanced write
pulse width is 2TCLCL- TCLMLmax+ TCLMHmln=;375
ns while the normal write pulse width Is TCLCLTCLMLmax+ TCLMHmin = 175 ns. Write data setup
time to the selected device is a function of either the
data valid delay from the 8086 (TCLDV) or the transceiver
enable delay TCVNV. The worst case delay to valid write
data is TCLDV = 110 ns minus transceiver propagation
delays. This implies the data may not be valid until 100
ns after the advanced write command but will be valid
approximately TCLCL - TCLDVmax + TCLMLmin = 100
ns prior to the ·Ieading edge of the normal write command. Data will be valid 2TCLCL- TCLDVmax+
TCLMHmln = 300 nsbefore the trailing edge of either
write command; The data and command overlap for the
advanced command is 300 ns while the overlap with the
normal write command is 175 ns. The transceivers are
disabled a minimum of TCLCHmin - TCLMHmax +
TCVNXmln = 85 nsafter the write command while the
CPU provides valid data a minimum of TCLCHminTCLMHmax + TCHDZmin = 85 ns. This guarantees write
data hold of 85 ns after the write command. The transceivers are disabled TCLCL - TCVNXmax +
TCHDTLmin= 155 ns (assuming TCHDTL=O) prior to
transceiver direction change for a subsequent read
cycle.
4. Interrupt Acknowledge Timing
The maximum modelNTA sequence is logically identical to the minimum mode sequence. The transceiver
control (DEN and DT/R) and INTA command timing of
each interrupt acknowledge cycle is identical to the
read cycle. As In the minimum mode system, the multiplexed address/data bus will float from the leading edge
of T1for each INTA bus cycle and not be driven by the
CPU until after T4 of each INTA cycle. The setup and
hold times on the vector number for the second cycle
are the same as data setup and hold for the read. If the
device providing the interrupt vector number is con·
nected to the local bus, TCLCL - TCLAZmax +
TCLMLmln = 130 nsare available from 8086 bus float.to
INTA command active. The selected device on the local
bus must disable the system data bus transceivers
since DEN is still generated by the 8288.
If the 8288 Is not in the. lOB (110 Bus) mode, the 8288
MCE/PDEN output becomes the MCE output: This output Is active during each INTA cycle and overlaps the
ALE signal during T1. The MCE Is available for gating
cascade addresses from a master 8259A onto three of
the upper AD15-AD8 lines and allowing ALE to latch the
cascade address Into the address latches. The address
lines may then be used to provide CAS address selec·
tlon to slave 8259A's located on the system bus (reference Figure 3E5). MCE Is active within 15 ns of status or
the start of T1 for eachlNTA cycle. MCE should not
enable the CAS lines onto the multiplexed bus during
the first cycle since the CPU does not guarantee to float
A-38
AP-67
the bus until 80 ns Into the first Im"A cycle. The first
MCE can be Inhibited by gating MCE with 05CK". The
8086 LOCK output Is activated during T2 of the first
cycle and disabled during T2 of the second cycle. The
overlap of LOCK with MCE allows the first MCE to be
masked and the second MCE to gate the cascade address onto the local bus. Since the 8259A will not provide a cascade address until the second cycle, no Information Is lost. As with ALE, MCE Is guaranteed valid
within 58 ns of the start of T1 to allow 75 ns CAS address setup to the trailing edge of ALE. MCE remains
active TCHCLmln - TCHLLmax+ TCLMCLmln = 52 ns
after ALE to provide data hold time to the latches.
If the 8288 Is strapped In the lOB mode, the MCE output
becomes PDEN and all 110 references are assumed to be
devices on the local bus rather than the demultlplexed
system bus. Since INTA cycles are considered 110
cycles, all Interrupts are assumed to come from the
local system and cascade addresses are not gated onto
the system address bus. Additionally, the DEN signal Is
not enabled since no 110 transfers occur on the system
bus. If the local 110 bus Is also buffered by transceivers,
the PO EN .signal Is used to enable those transceivers.
PDEN A.C. characteristics are identical to DEN with
PO EN enabled for 110 references and DEN enabled for
instruction or memory data references.
5. Ready Timing
Ready timing based on address valid timing is the same
for maximum anc! minimum mode· systems. The delay
from 8288 command valid to ROY valid at the 8284 is
TCLCL- TCLMLmax- TRIVCLmln= 130 ns. This time is
available for external circuits to determine the need to
Insert wait states and disable ROY or enable ROY to
avoid wait states. INTA, all read commands and ad·
vanced write commands provide this timing. The normal
write command is not valid until after the ROY signal
must be valid. Since both normal and advanced write
commands are generated by the 8288 for all write
cycles, the advanced write may be used to generate a
ROY indication even though the selected device uses
the normal write command.
Since sepa~te commands are provided for memory and
110, no MilO signal is specifically available as in the
minimum mode to allow an early 'wait state required' indication for 110 devices. The S2 status line, however is
logically equivalent to the MilO signal and can be used
for this purpose.
6. Other Considerations
The Ra/GT timing Is covered in the next section and will
not be duplicated here. The only additional signals to be
considered in the maximum mode are the queue status
lines aso, aS1. These signals are changed on the
leading edge of each clock cycle (high to low transition)
Including Idle and walt cycles (the queue status is Independent of the bus activity). External logic may sample the lines on the low to high transition of each clock
cycle. When sampled, the signals Indicate the queue activity In the previous clock cycle and therefore lag the
CPU's activity by one cycle. The TEST input require-
ments are Identical to those stated for the minimum
.
mode.
To Inform the 8288 of HALT status when a HALT Instruction Is executed, the 8086 will Initiate a status transition
from passive to HALT status. The status change will
cause the 8288 to emit an ALE pulse with an Indeterminate address. Since no bus cycle Is Initiated (no command Is Issued), the results of thls.address will not affect CPU operation (I.e., no response such as READY Is
expected from the system). This allows external hardware to latch and decode all transitions In system
status.
3G. Bus Control Transfer (HOLD/HLDA and RQ/GT) .
The 8086 supports protocols for transferring control ~f
the local bus between Itself and other devices capable
of acting as bus masters. The minimum mode config.
uration offers a signal level handshake shnllar to the
8080 and 8085 systems. The maximum mode provides
an enhanced pulse sequence protocol designed to optimize utilization of CPU pins while extending the
system configurations to two prioritized levels of alternate bus masters. These protocols are simply techniques for arbitration of control of the CPU's local bus
and should not be confused with the need for arbitration
of a system bus.
1. MINIMUM MODE
The minimum mode 8086 syste.:n uses a hold request·input (HOLD) to the CPU and a hold acknowledge (HLDA)
output from the CPU. To gain control of the bus,:a
device must assert HOLD to the CPU and wait for the
HLDA before driving the bus. When the 8086 can relinquish the bus, it floats the RD, WR,INTA and M/iOcom·
mand lines, the DEN and DTiRbus control lines and the
multiplexed address/data/status lines. The ALE signal is
not three-stated. The CPU aCknowledges the request
with HLDA to allow the requestor to take control of the
bus. The requestor must maintain the HOLD request active until it no longer requires the bus. The HOLD reo
quest to the 8086 directly affects the bus interface unit
and only indirectiy affects the execution unit. The CPU
will continue to execute from its internal queue until
either more instructions are needed or an operand
transfer Is required. This allows a high degree of overlap
between CPU and auxiliary bus master operation. When
the requestor drops the HOLD signal, the 8086 will respond by dropping HLDA. The CPU will' not re-drive the
bus, command and control signals from tl1ree-state until
it needs to perform a bus transfer. Since the 8086 may
stili be executing from Its Internal quelle when HOLD
drops, there may exist a period of time during which no
device is driving the bus. To prevent the command lines
from drifting below the minimumVIH level during the
transition of bus control, 22K ohm pull up resistors
should be connected to the bus command lines. The
timing diagram in Figure 3G1 shows the handshake sequence and 8086 timing to sample HOLD, float the bus,
and enable/disable HLDA relative to the CPU clock.
To guarantee valid system operation, the designer must
assure that the requesting device does not assert con-
A-39
Ap·67
trol of the bus prior to the 8086 relinquishing control and
that the device relinquishes control of the bus prior to
the 8086 driving the bus. The HOLD request into the
8088 must be stable THVCH ns prior to the CPU's low to
high clock transition. Since this Input 15 not syn·
chronized by the CPU, signals driving the HOLD input
should be synchronized with the CPU clock to
guarantee the setup time Is not violated. Either clock
edge may be used. The maximum delay between HLDA
and the' 8088 floating. the bus Is TCLAZmax':'
TCLHAVmin= 70 ns. If the system cannot tolerate the
70 ns overlap, HLDA active from the 8088 should be
delayed to the device. The minimum delay for the CPU to
drive the control bus from HOLD Inactive 15 THVCHmln
+3TCLCL=835 ns and THVCHmln+3TCLCL+
TCHCL= 701 ns to drive the multiplexed bus. If the
device doesncit satisfy these requirements, HOLD Inac·
tlve to the 8086 should be delayed. The delay from HLDA
inactive to driving the busses Is TCLCL+ TCLCHminTCLHAVmax= 158 ns for the control bus and 2TCLCLTCLHAVmax = 240 ns for the data bus.
1.1 Latency of HLDA to HOLD
The decision to respond to a HOLD request Is made In
the bus Interface unit. The major factors that Influence
the decision are the current bus activity; the state of the
LOCK signal internal to the CPU (activated bY the soft·
ware LOCK prefix) and Interrupts.
If the LOCK Is not active, an interrupt acknowledge cycle Is not in progress and the BIU (Bus Interface Unit) Is
executing a T4 or TI when the HOLD request is received,
the minimum latency to HLDA Is:
35.ns
65 ns
200 ns.
10 ns
THVCH min (Hold setup)
TCHCL min
TCLCL (bus float delay)
TCLHAV min (HLDA delay)
310 ns
@ 5 MHz
The maximum delay under these conditions is:
34 ns
200 ns
82 ns
200 ns
160 ns
Oust missed setup time)
delay to next sample .
TCHCL max
TCLCL.(bus float delay)
TCLHAV max (HLDA delay)
677 ns
@5MHz
If the BIU just initiated a bus cycle when the HOLD Re·
quest was received, the worst case response time is:
34 ns
82 ns
7*200
N*200
160 ns
THVCH Oust missed)
TCHCL max
bus cycle execution
N wait states/bus cycle
TCLHAV max (HLDA delay)
1.676"s
@ .5 MHz, no wait states
Note, the 200 ns delay for just missing Is Included in the
delay for bus cycle execution. If the operand transfer Is
a word transfer to an odd byte boundary, two bus cycles
are executed to perform the transfer. The BIU will not
acknowledge a HOLD request between the two bus
cycles. This type of transfer would extend the above
maximum latency by four additional clocks plus N addi·
tlonal wait states. With no wait states in the bus cycle
the maximum would be 2.476 microseconds.
'
Although the minimum mode 8088 does not have a hard·
ware LOCK output, the software LOCK prefix may still
be included In the instruction stream. The CPU Internally reacts to the LOCK prefix as would the maximum
mode 8088. Therefore, the LOCK does not allow a H()LD
request to be honored until completion of the instruction following the prefix. This allows an instruction
which performs more than one memory reference (ex.
ADD [BX], CX; which adds CX to [BXD to execute without
another bus master gaining control of the bus between
memory references. Since the LOCK signal is active for
one clock longer than the instruction execution, the
maximum latency to HLDA is:
CLK
HOLD
A~~D __~__~1-~~~~--------------~--------~---f------------------f-~
CONTROL
"LDA _ _ _ _ _ _ _ _.oJ
Figure 3G1. HOLD/HLDA Sequence
A-40
AP-67
34 ns
200 ns
82 ns
(M + 1)*200 ns
200 ns
160 ns
THVCH (just miss)
delay to next sample
TCHCL max
LOCK Instruction execution
set up HLDA (internal)
TCLHAV max (HLDA delay)
(M*200 ns)+ 876 ns
@ 5 MHz
A typical use of the HOLD/HLDA signals In the minimum
mode 8086 system Is bus control exchange with DMA
devices like the Intel 8257-5 or 8237 DMA controllers.
Figure 3G2 gives a general Interconnect for this type of
configuration using the 8237-2. The DMA controller
resides on the upper half of the 8086's local bus and
shares the A8·A 1.5 demultlplexlng address latch of the
8086. All registers In the 8237-2 must be assigned odd
addresses to allow Initialization and Interrogation by the
CPU over the upper half of the data bus. The 8086
RDlWR commands must be demultiplexed to provide
separate 1/0 and memory commands which are compatible with the 8237-2 commands. The AEN control from
the 8237-2 must disable the 8086 commands from the
command bus, 'disable the address latches from the
lower (AO·A7) and upper (A19·A16) address bus and
select the 8237-2 address strobe (ADSTB) to the AS-A 15
address latch. If the data bus Is buffered, a pull·up
resistor on the DEN line will keep the buffers disabled.
The DMA controller will only transfer bytes between
If the HOLD request Is made at the beginning of an Inter·
rupt acknowledge sequence, the maximum latency to
HLDA Is:
34 ns
82 ns
2600 ns
160 ns
THVCH (just missed)
TCHCL max
13 clock cycles fo~ INTA
TCLHAV max
2.8761's
@5MHz
1.2 Minimum Mode DMA Configuration
vee
T
DEMULTIPLEX
MIN MODE COMMANDS
~DI:l
I
8284
I
L
r
I
RDIWR/IO/M
iiHE
A10-16
8088
READY
CLK
RESET
HOLD
ALE
AD1S·0
HLDA
-
Em\IILE
COMMAND
BUS
8282
01
STB
DO
EN
T
'(
~
EN
Ub~~R
-
00-
ADDR -
01
-
8282
1/0 PORT
LOADED DURING
8237 INITIALIZATION
LOCAL DATA
BUS
8282
74LS74
CLR
CLK
t
:I
~
01
DO
STB
AD7-(1
8282
DO
-01
STB
EN
(AO)
~
087·0
L..,--
AEN
ADSTB
8237·2
HLDA
HRQ CLK
t
4
Figure 3G2. DMA Using the 8237·2
A-41
~:) 1-
lOW
MEMR
MEMW
RESET
AP-67
2.1 Shared System Bus (RQ/GT Alternative)
memory and 1/0 and requires the 1/0 devices to reside on
an a-bit bus derived from the 16-bit to 8-bit bus multiplex
circuit glvenin Section 4. Address lines A7-AO are driven
directly by th~ 8237 and BHE is generated by inverting
AO.lf A19-A16 are used, they must be provided by an additional port with either a .fixed value or initialized by
software and enabied ontothe address bus by AEN.
The maximum mode RQ/GT sequence is intended to
transfer control of the. CPU local bus between the CPU
and alternate bus masters which reside totally on the
local bus and share the complete CPU interface to the
system bus. The complete interface Includes the address latches, data transceivers, 8288 bus controller and
8289 multi master bus arbiter. If the alternate bus
masters In the system do not reside directly on the 8086
local bus, system bus arbitration is required rather than
local CPU bus arbitration. To satisfy the need for multimaster system bus arbitration at each CPU's system interface, the 8289 bus arbiter should be used rather than
the CPU RQ/GT logic.
Figure 3G3 gives an interconnection for placing the
8257 on the system bus. By using a separate latch to
hold the upper address from the 8257-5. and connecting
the outputs to the address bus as shown, l6-bit DMA
transfers are provided. In this configuration, AEN
simultaneously enables AO and BHE to allow word
transfers. AEN still disables the CPU interface to the
command and address busses.
To allow a device with a simple HOLD/HLDA protocol to
gain control of a single CPU system bus, the circuit in
Figure 3G4 could be used. The design Is effectively a
simple bus arbiter which Isolates the CPU from the
system bus when an alternate bus master' issues a
HOLD request. The output of the circuit, Am (Address
ENable), disables the 8288 and 8284 when the 8086 Indicates idle status (SO,S1,82 1), LOCK Is not active and
a HOLD request Is active. With AEN Inactive, the 8288
three-states the command outputs and disables DEN
2. MAXIMUM MODE (RQ/GT)
The maximum mode 8086 configuration supports a significantly different protocol for transferring bus control.
When viewed with respect to the HOLD/HLDA sequence
of the minimum mode, the protocol appears difficult to
implement externally. However, it is necessary to understand the intent of the protocol and its purpose within
the system architecture.
=
8282
A19-16
A,9·17
DO
ALE
A16
'iIHE
iFiE
OE
CPU
BUS
f--+-~------1I--.--f--------+_-- A,5·&
AD,s_a
INTERFACE
DO
f--~---~---1-~~f-.-------+--~A.
STB
OE
8282
f--+------I-.~--+_____.-----_t_--
AD'.O,--,-+_I 01
A,.,
DO
STB
OE
8257
AEN
DT/R
1/0 PORT
----..........Ao TO GROUND AND
r--±:-----'....;.;.~;;l_....,..::'=,.._-+__;~..., UPPER BITS OF DMA ADDRESS
(FIXED OR REG)
HOLD __- - - - - - j
HLDA-----~~I
CONTROLS ARE SAME AS 8·BIT
TRANSFER CONFIGURATION WITH
MANIPULATION OF THE DATA BUS
Figure 3G3. 8086 Min System, 8257 on System Bus 16·BIt Transfers
A-42
AP-67
which three·states the data bus transceivers. AEN must
also three·state the address latch (8282 or 8283) outputs.
These actions remove the 8086 from the system bus and
allow the requesting device to drive the system bus. The
AEN signal to. the 8284 disables the ready Input and
forces a bus cycle Initiated by the 8086 to walt until the
8086 regains· control of the system bus. The CPU may
actively drive Its local bus during this interval.
The requesting device will not gain control of the bus
during an 8086 Initiated bus cycle, a locked Instruction
or an Interrupt acknowledge cycle. The LOCK signal
from the 8086 Is active between INTAcycles to
guarantee the CPU maintains control of the bus. Unlike
the minimum mode 8086 HOLD response, this arbltra·
tion circuit allows the requestor. to gain control of the
bus between consecutive bus .cycles which transfer a
word operand on an odd address boundary and are not
loc~ed. Depending on the characteristics of the reo
questing device, any of·the 74LS74 outputs can be used
to generate a HLDA to the device.
Upon completion of its bus operations, the alternate bus
master must relinquish control of the system bus and
drop the HOLD request. After AEN goes inactive, the ad·
dress latches and data transceivers are enabled but, If a
CPU initiated bus cycle Is pending, the 8288 will not
drive the command bus until a minimum of 105 ns or
maximum of 275 ns later. If the system is normally not
ready, the 8284 AEN Input may Immediately be enabled
with ready returning to the CPU when the selected
device completes the transfer. If the system Is normally
·ready, the 8284 AEN input must be delayed long enQugh
to provide access time equivalent to a normal bus cycle.
The 74LS74 latches In the design provide a minimum of
TCLCHmin for the alternate device to float the system
bus after releasing HOLD. They also provide 2TCLCL ns
address access and 2TCLCL- TAEVCHmax ns (8288
command enable delay) commarid access prior to ena·
bling 8284 ready detection. If HLDA is generated as
shown In Figure 3G4, TCLCL ns are available for the
8086 to release the bus prior to issuing HLDA while
HLDA is dropped almost Immediately upon loss of
HOLD ..
A circuit configuration for an 8257·5 using this tech·
nique to interface with a maximum mode 8086 can be
derived from Figure 3G3. The 8257·5 has Its own address
latch for buffering the address lines A15·A8and uses its
AEN output to enable the latch onto the address bus.
The maximum latency from HOLD to HLDAfor this clr·
cult is dependent on the state of the system when the
HOLD Is issued. For an Idle system the maximum delay
is the propagation delay through the nand gate and RIS
fllp·flop (TD1) plus 2TCLCL plus TCLCHmax plus prop·
agatlon delay of the 74LS74 and 74LS02 (TD2): For a
locked Instruction it becomes: TD1 + TD2 + (M + 2)
*TCLCL+ TCLCHmax where M is the number of clocks
required for execution of the locked Instruction. For the
interrupt acknowledge cycle the latency·· Is
TD1 + TD2 + 9 *TCLCL + TCLCHmax.
2.2 Shared Local Bus (RQ/GT Usage)
The RQ/GT protocol was developed to allow up to two In·
structlon set extension processors (co'processors) or
other special function processors (like the 8089 1/0
processor in local mode) to reside directly on the 8086
local bus. Each RQ/GT pin of the 8086 supports the full
protocol for exchange of bus control (Fig. 3G5). The se·
quence consists of a request from the alternate bus
master to gain control of the system bus, a grant from
the CPU to indicate the bus has been relinquished and a
release pulse from the alternate master when done. The
two RQ/GT pins (RQ/GTO and RQ/Gn) are prioritized
with RQ/GTO having the highest priority. The prloritlza·
tion only occurs if requests have been received on both
pins before a response has been given ·to either. For ex·
ample, If a request Is received on RQ/Gn followed by a
request on RQ/GTO prior to a grant on RQ/GT1, RQ/GTO
will gain priority over RQ/GT1. However, If RQ/Gn had
already received a grant, a request on RQ/GTO must walt
until a release pulse is received on RQ/GT1.
The requestlgrant sequence interaction with the bus in·
terface unit Is similar to HOLD/HLDA. The CPU con·
tinues to execute until a bus transfer for additional in·
structions or data is required. If the release pulse is
+5
, - - - - - - - - - - - - - A E t i (TO B2BB &828213'0)
So
S,
S2~=~[)
COCK
HOLD
o
Q
C
Q
m'(TO B2B4)
+5
ClK
HlDA
Figure 3G4. Circuit 10 Translale HOLD Inlo AEN Disabl.e·'or Max Mode 8086
A-43
AP·67
recelvedbefo~ the CPU needs the bus; It will hot drive
the bus until a transfer I!) requ IrEi.d.
Upon receipt ·of,a req~est pulse, .the 8086fioats the
multiplexed address, data. and, status bus, the SO,' 51,
and 52 status lines, the LOCK pin and RD. This action
does not disable the 8288 .command. outputs from. drlv·
Il1gthe command bus and does not disable the address
latches f,rom driving the address bus. The 8288 contains
Internal pull,up resistorS on the SO,Sl, andS2 status
lines to maintain the passive siate while the 8086 out,
puts are three·state. The passive state prevents the 8288
from,lnltlating any commands or activating DEN to
enal;l.le the transceivers buffering ,the data bUS. If the
device Issuing the RQdoesnotuseJhe 8288, It must
disable the 8288 command outputs by disabling the
8288 AEN Input. Also, address latches not used by the
requesting device must be disabled.
~cc
GND
AD14
AD15
AD13
Al8/S3
A.D1Z
A17/S4
, AD11
Al81SS
AD10
1118/58
.ADS
BHE/S7
ADB
MN/MX
AD7
iifj
ADa
RO/,GTO
ADS
iiCi/GTi
LOcii
AD4
ADZ
52
Si
AD1
so
ADO
QSO
AD3
2.3 RQ/GT Operation
Detailed timing of .the RQ/GTsEjquence Is given In
Flgure3G6. To request a transfer of bus' control via the
RO/G'i'lines, the device must drive the line low,forno
more thanorie CPU clock Interval to generate a request
p'ulse. The pulse must .be 'synchronized with the CPU
clock to guaranteethe appropriate,setuparid hold times
to the clock edge which samples the RQ/GT lines In'the
CPU. After Issuing a ·request pulse'; the device must
begin sampling for a'grant pulse with the next low to
high clock edge. 5ince the 8086 can respond with a
grant pulse In the clock cycle Immediately following the
request;ttie RQ/GT line may not return to the positive
level between the request and grant pulses. Therefore
edge triggered 'ioglc ·Is not valid for capturing a grant
pulse. It also Implies the circuitry which generates the
request pulse must guarantee the request Is remolied In
time to detect a grant from the CPU. After receiving the
grant pulse, the requesUng device may drive the local
bus. 51nce the 8086 does not float the address and data
bus, I,OCK or RD until the ,high to low clock transition
following the low to high clock transition the requestor
uses to sample for the g'rant, the requestor should 'walt
the float' delay of the 8086 (TCLAZ) before driving the
local bus. This precaution prevents buscontl!ntlon duri ng the access, of bus control by the requestor.
To returnco,iltrcilof the'bus to the 8086, the alternate
bus master relinquishes bus control and issues a
release p'u'lse on the same RQ/GT line. The 8086 may
drive the SO-52 status lines, RD and LOCK, three clock
cycles afier detecting the .release pulse and theaddreSS/data bus TCHCLmln ris {clock high time) after the
status lines. The alternate bus master should be threestated off the local, bus and hav.e other BOB6 interface
circuits (B2BB and address latches) re-enabled within the
80B6 c;telay to regain control cif the bus.
'
NMI
QS1
2.4 RQ/GT LatEmcy
INTR
rEST
elK
READY
GND
RESET
The, RQ to GTlatency for a single RQ/GT line Is similar
to the HOLD to'HLDA latency. The cases given for the
minimum mode BOB6 also apply to the maximum mode.
For each case the delay from RQ detection by the CPU
to GT detection by the requestor is:
(HOLD to HLDA delay)- (THVCH + TCHCL+ TCLHAV)
Figure 3GS, 8086 RQlGT Connections
'''''''
t. THlIOllFLOATSAJ:OZ ..... IliANOasaRONTH .. I!DGlI!
L TMIOTMIR MAlTlR FLOATlJi,Ii."" PIIO.l.1.t aTATlON THIII!DGI
L THI! OTHI" MAtTl!II. 'LOATS Aao. .us, IRr, AND meR ON THlllOOE
t.TKI_IIIDIIIYUntlCONTIIOLLINU
.
LTttI._III0111V11nt1AOoUND
, Figure 3G8. Requeli/Grant Sequence
A-44
AP-67
to a grant on RO/GTO will take two clock cycles and Is a
function of a pending request for transfer of control
from the execution unit. The latency from request to
grant when the Interface is under control of a bus
master on the other RO/GT line is a function of the other
bus master. The protocol embodies no mechanism for
the CPU to force an alternate bus master off the bus. A
watchdog timer should be used to prevent an errant
alternate bus master from 'hanging' the system.
This gives a clock cycle maximum delay for an Idle bus
interface. All other cases are the minimum mode result
minus 476 ns. If the 8086 has previously issued a grant
on one of the RO/GT lines, a request on the other RO/GT
line will not receive a grant until the first device releases
the interface with a release pulse on its RO/GT line. The
delay from release on one RO/GT line to a grant on the
other is typically one clock period as shown In Figure
3G7. Occasionally the delay from a release on RO/GT1
CHANNEL 0 TO 1
CLOCK
RO/GTO
~
RELEASE
~GRANT
RQIGT1
CHANNEL 1 TO 0
CLOCK
RO/GT1
~RELEASE
RO/GTO
\
' - _ - . J ,/
GRANT
OR
\
Figure 3G7. Channel Transfer Delay
A-45
/
GRANT
AP-67
2.5 RQ/GT to· HOLD/HLDA: Conversion
of HLDA, It may be desirable to delay the acknowledge
one clock period. The H LDA is dropped no later than one
clock period after HOLD Is disabled. The HLDA also
drops··at the beginning of the release pulse to provide
2TCLCL+ TCLCH ·for the requestor to relinquish control
of the status lines and 3TCLCL to float. the remaining
signals ..
A clrculf for translating a HOLD/HLDA hand-shake sequence IntoaRQ/GT pulse sequence is given In Figure
3GB. After receiving the grant pulse, the HLDA Is enabled TCHCLmln ns before the CPU has three-stated the
bus. If the requesting circuit drives the bUs within 20 ns
ClOCK------------------------------------,
A
74lS78
}O---_H J
ClK
74S02
Q
I-_+-----'f-.....
HlDA
QH-+-+->
ClR
HOLD
74S02
+5
B
74lS78
)o-~rl---iJ
Q
ClK
K
74LS04
~--------------------------------~
Figure 3GB •. HOLD/HLD~Rci/GT Conversion Circuit
B8.3MIN-1
r-
-1. r-
44.• MIN
,r-
DATA BUS FLOATS
ClK
HLDR
RQ
HLDA
r-----t
------------------~I
Figure 3GBb. HOLD/HLD _ _O/GT Conversion Timing
A-46
AP-67
4. INTERFACING WITH 1/0
The 8086 Is capable of Interfacing with 8· and 16·blt 1/0
devices using either 1/0 Instructions or memory mapped
1/0. The 1/0 Instructions allow the 1/0 devices to reside
In a separate I/0address space while memory mapped
1/0 allows the full power of the Instruction set to be
used for 1/0 operations. Up to 64K bytes of 1/0 mapped
1/0 may be defined In an 8086 system. To the program·
mer, the separate 1/0 address space Is only accessible
with INPUT and OUTPUT commands which transfer data
between 1/0 devices and the AX (for 16·blt data trans·
fers) or AL (for 8-blt data transfers) register. The first 256
bytes of the I/O space (0 to 255) are directly addressable
by the 1/0 Instructions while the entire 64K Is accessible
via register Indirect addressing through the DX register.
The later technique is particularly desirable for service
procedures that handle more than one device by allowIng the desired device address to be passed to the procedure as a parameter. 1/0 devices may be connected to
the local CPU bus or the buffered system bus.
provide full decoding In a Single package and allow Inserting a new PROM to reconfigure the system 1/0 map
without circuit board or wiring modifications (Fig. 4A2).
ADDRESS
EVEN ADDRESSED
WORD OR BYTE
PERIPHERALS
(a)
ADDRESS
4A. Elght·Blt 1/0
EVEN ADDRESSED
BYTE PERIPHERALS
. Ao
Eight-bit 1/0 devices may be connected to either the upper or lower half of the. data bus_ Assigning an equal
number of devices to the upper and lower halves of the
bus will distribute the bus loading. If a device is connected to the upper half of the data bus, all 1/0 addresses assigned to the device must be odd (AO = 1). If
the device is on the lower half of the bus, Its addresses
must be even (AO = 0). The address assignment directs
the eight-bit transfer to the upper (odd byte address) or
lower (even byte address) half of the sixteen-bit data
bus. Since AO will always be a one or zero for a specific
device, AO cannot be used as an address input to select
registers within a specific device. If a device on the
upper half of the bus and one on the lower half are
assigned addresses that differ only in AO (adjacent odd
and even addresses), AO and BHE must be conditions of
chip select decode to prevent a write to one device from
erroneously performing a write to the other. Several
techniques for generating 1/0 device chip selects are
given in Figure 4A1.
BHE
ODD ADDRESSED
BYTE PERIPHERALS
1§
(b)
r----....J\
ADDRESS
Ao
AO·'. 205
EVEN ADDRESSED
0jO
r!~I:~~~~~~
0,
ODD ADDRESSED
PERIPHERALS
(BYTE)
A2
Ei
~
(e)
Figure 4Al. Techniques for I/O Device Chip Selects
The first technique (a) uses separate 8205's to generate
chip selects for odd and even addressed byte peripherals. If a word transfer is performed to an even addressed device, the adjacent odd addressed 1/0 device
is also selected. This allows accessing the devices In·
dlvldually with byte transfers or simultaneously as a
16·blt device with word transfers. Figure 4A 1(b) restricts
the chip selects to byte transfers, however a word
transfer to an odd address will cause the 8086 to run two
byte transfers that the decode technique will not detect.
The third technique simply uses a single 8205 to
generate odd .and even device selects for byte transfers
and will only select the even addressed eight-bit device
on a word transfer to an even address.
If greater than 256 bytes of the 1/0 space or memory
mapped 1/0 Isused, additional decoding beyond what Is
shown In the examples may be necessary. This can be
done with additional TTL, 8205's or bipolar PROMs (In·
tel's 3605A). The bipolar PROMs are slightly slower than
multiple levels of TTL (50 ns vs 30 to 40ns for TTL) but
ODD ADDRESSED
BYTE PERIPHERALS
BHE ---1--01
10
CSl
CS2
Ao
Al
A'2
A,
A,
As
A,
0,
0,
11
12
02 13
3605
A·l
01 14
A,
A,
A,
15
16
17
Figure 4A2_ Bipolar PROM Decoder
One last technique for Interfacing with elght·blt periph·
erals Is considered In Figure 4A3. The sixteen-bit data
bus Is multiplexed onto an eight-bit bus to accommodate byte oriented DMA or bloc.k transfers to memory
mapped eight-bit 1/0. Devices connected to this Inter·
face may be assigned a sequence of odd and even addresses rather than all odd or even.
A-47
AP-67
74LS02
74LS388
iffi--:===t=1::)o--I><>---:IDR
1Ll_ _l\ 8·Blt
PERIPHERAL
DATA BUS
11-BIT
DATA
BUS
DEFINED
EN~:i: - - - - - - - - 4 - - - '
NOTE: IF IT IS NOT NECESSARY TO THREE·STATE THE COMMAND LINES. A
DECODER C8205 OR 74S138) COULD BE USED. THE 74LS257 IS NOT
RECOMMENDED SINCE THE OUTPUTS MAY EXPERIENCE VOLTAGE
SPIKES WHEN ENTERING OR LEAVING THREE·STATE.
Figure 4Cl. Decoding Memory and I/O RD and WR Commands lor
Minimum Mode 8086 Systems
Figure 4A3. 16- to 8·Blt Bus Conversion
4B. Sixteen· Bit ItO
For obvious reasons of efficient bus utilization and sim·
pllclty of devlceselection, slxteen·blt 1/0 devices should
be assigned even addresses. To guarantee the device is
selected only for word operations, AO and BHE should
be conditions of chip select code (Fig. 4B1).
ADDRESS
Ao·.
Ao ---+-01 r;
IRE
~
Eo
Linear select techniques (Fig. 4C2) for 1/0 devices can
only be used with devices that either reside In the I/O address space or require more than one active chip select
(at least one low active and one high active). Devices
with a single chip select Input cannot use linear select If
they are memory mapped. This Is due to the assignment
of memory address space FFFFFOH-FFFFFFH to reset
startup and memory space 00000H-003FFH to Interrupt
vectors.
0.,
82051
ADD~~~~{]
EVEN ADDRESSED
WORD PERIPHERALS
0,
Il5Jm
Iil5
IlWR;
WIi
I/O DEVICE
Ca) SEPARATE I/O COMMANDS
Figure 4Bl. Slxteen·Blt 1/0 Decode
4C. General Design Considerations
a·
AD
DRESS{t]S
LINES
MINIMAX, MEMORY 1/0 MAPPED AND LINEAR SELECT
Iil5
1il5.
Since the minimum mode 8086 has common read and
write commands for memory and 1/0, If the memory and
110 address spaces overlap, the chip selects must be
qualified by MilO to determine which address space the
devices are assigned to. This restriction on chip select
decoding can be removed if the 1/0 and memory addresses in the system do not overlap and are properly
decoded; all 1/0 Is memory mapped; or RD, WR and M/iO
are decoded to provide separate memory and 1/0
readlwrlte commands (Fig. 4C1). The 8288 bus controller
In the maximum mode 8086 system generates separate
1/0 and memory commands In place of a M/iO signal. An
1/0 device Is assigned to the 1/0 space or memory space
(memory mapped 1/0) by connection of either 1/0 or
memory command lines to the command Inputs of the
device. To allow overlap of the memory and 1/0 address
space, the device must not respond to chip select alone
but must require a combination of chip select and a read
or write command.
WIi
W1i..
110 DEVICE
Cb) MULTIPLE CHIP SELECTS
Figure 4C2. Linear Select lor I/O
40. Determining ItO Device Compatibility
This section presents a set of A.C. characteristics which
represent the timing of the asynchronous bus Interface
of the 8086. The equations are expressed in terms of the
CPU clock (when applicable) and are derived for
minimum and maximum modes of the 8086. They represent the bus characteristics at the CPU.
The results can be used to determine 1/0 device requirements for operation on a single CPU local blis or
buffered system bus. These values are not applicable to
A-48
AP-67
a Multlbussystem bus interface. The requirements for a
Multibus system bus are available In the Multlbus Inter·
face specification.
A list o/bus parameters, their definition and how they
relate to the A.C. characteristics of Intel peripherals are
given in Table 401. Cycle dependent values of the
parameters are given In Table 402. For each equation, if
more than one. signal path Is Involved, the equation
reflects the worst case path.
the relaxed device requirements for even a large complex configuration. The analysis assumes all components are exhibiting the specified worst case parameter values and are under the corresponding tem,
perature, voltage and capacitive load .condltlons. If the
capacitive loading on ttie 8282183 or 8286187 Is less than
the maximum, graphs of delay vs. capacitive loading in
the respective data sheets should be used to determine
the appropriate delay values.
ex. TAVRL(address valid before read active) =
(1) Address from CPU to RO active
( or)
(2) ALE (to enable the address through the
address latches) to RO active
TABLE 402. CYCLE DEPENDENT PARAMETER REQUIREMENTS
FOR PERIPHERALS
(a) Minimum Mode
TAVRL= TCLCL+ TCLRLmin - TCLAVmax= TCLCL-l00
TRHAX= TCLCL- TCLRHmax+ TCLLHmin= TCLCL-150
TRLRH = 2TCLCL- 60= 2TCLCL- 60
TRLDV= 2TCLCL- TCLRLmax- TDVCLmin= 2TCLCL-195
TRHDZ=TRHAVmin= 155 ns
TAVDV = 3TCLCL- TDVCLmln- TCLAVmax= 3TCLCL-140
TRLRL= 4TCLCL= 4TCLCL
TAVWL= TCLCL+ TCVCTVmin- TCLAVmax= TCLCL-l00
TWHAX= TCLCL+ TCLLHmin- TCVCTXmax = TCLCL-110
TWLWH = 2TCLCL - 40 = 2TCLCL - 40
TDVWH = 2TCLCL+ TCVCTXmin - TCLDVmax = 2TCLCL- 100
TWHDX = TWHDZmin = 89
TWLCL= 4TCLCL= 4TCLCL
TWHDXB=TCLCHmin+(- TCVCTXmax+ TCVCTXmin)=
TCLCHmin - 50
The worst case delay path Is (1).
For the maximum mode 8086 configurations, TAVWLA,
TWLWHA and TWLCLA are relative to the advanced
write signal while TAVWL, TWLWH and TWLCL are
relative to the normal write signal.
TABLE4Dl. PARAMETERS FOR PERIPHERAL COMPATIBILITY
TAVRl - Address stable before RD leading edge
TRHAX - Address hold after RD trailing edge
TRLRH - Read pulse width
TRLDV - Read to data valid delay
TRHDZ - Read trailing edge to data floating
TAVDV - Address to valid data delay
TRLRL - Read cycle time
TAVWL - Address valid before write leading edge
TAVWLA - Address valid before advanced write
TWHAX - Address hold after write trailing edge
TWLWH - Write pulse width
TWLWHA - Advanced write pulse width
TDVWH - Data set up to write trailing edge
TWHDX - Data hold from write trailing edge
TWLCL - Write recovery time
TWLCLA - Advanced write recovery time
TSVRL - Chip select stable before RD leading edge
TRHSX - Chip select hold after RD trailing edge
TSLDV - Chip select to data valid delay
TSVWL - Chip select stable before WR leading edge
TWHSX - Chip select hold afterWR trailing edge
TSVWLA - Chip select stable before advanced write
(TAR)
(TRA)
(TRR)
(TRD)
(TO F)
(TAD)
(TRCYC)
(TAW)
(TAW)
(TWA)
(TWW)
(TWW)
(TOW)
(TWO)
(TRV)
(TRV)
(TAR)
(TRA)
(TRD)
(TAW)
(TWA)
(TAW)
. Note: Delays relative to chip select are a function of the chip select
decode technique used and are equal to: equivalent delay
from address - chip select decode delay.
(b) Maximum Mode
TAVRL= TCLCL+ TCLMLmin- TCLAVmax= TCLCL-l00
TRHAX= TCLCL- TCLMHmax+ TCLLHmin= TCLCL- 40
TRLRH = 2TCLCL- TCLMLmax+ TCLMHmin= 2TCLCL- 25
TRLDV= 2TCLCL- TCLMLmax- TDVCLmin= 2TCLCL-65
TRHDZ= TRHAVmin = 155
TAVDV= 3TCLCL- TDVCLmin- TCLAVmax= 3TCLCL-140
TRLRL= 4TCLCL= 4TCLCL
TAVWLA=TAVRL=TCLCL-l00
TAWIL = TAVRL+ TCLCL= 2TCLCL-100
TWHAX= TRHAX= TCLCL- 40
TWLWHA= TRLRH = 2TCLCL- 25
TWLWH = TRLRH.., TCLCL= TCLCL- 25
TDVWH = 2TCLCL + TCLMHmin - TCLDVmax = 2TCLCL- 100
TWHDX = TCLCHmin - TCLMHmax + TCHDZmin = TCLCHmin - 30
TWLCL= 3TCLCL= 3TCLCL
TWLCLA= 4TCLCL= 4TCLCL
Symbols In parentheses are equivalent parameters specified for
Intel peripherals.
In the given list of equations, TWHOXB is the data hold
time from the trailing edge of write for the minimum
mode with a buffered data bus. For this equation,
TCVCTX cannot be a minimum for data hold and a maxImum for write Inactive. The maximum difference is 50
ns giving the result TCLCH-50. If the reader wishes to
verify the equations or derive others, refer to Section 3F
for assistance with interpreting the 8086 bus timing
diagrams.
TABLE 403. COMPATIBLE PERIPHERALS (5 MHz 8086)
Configuration
Minimum Mode
8251A
8253·5
8255A·5
8257·5
8259A
8271
8273
8275
8279·5
8041A'
8741A
8291
Figure 401 shows four representative configurations
and the compatible Intel peripherals (Including wait
states If required) for each configuration are given In
Table 403. Configuration 1 and 2 are minimum mode
demultlplexed bus 8086 systems without (1) and with (2)
data bus transceivers. Configurations 3 and 4 are maxImum mode systems with one (3) and two (4) levels of address and data buffering. The last configuration Is
characteristic of a multi-board system with bus buffers
on each board. The 5 MHz parameter values for these
configurations are given in Table 404 and demonstrate
Maximum Mode
Unbuffered
Buffered
Buffered
Fully Buffered
v
v
v
v
v
v
v
v
v
v
v
v
1W
lW
lW
lW
v
lW
1W
1W
lW
1W
1W
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
'Includes other Intel peripherals based on the 8041A (Le., 8292, 8294,
8295).
~
implies full operation with no wait states.
W implies the number of wait states required.
A-49
,
AP-67
Peripheral compatibility is determined from the ,equations given for the CPU by modifying them to account
for additional delays from address latches and data
transceivers In the configuration. Once the system configuration is selected, the system requirements can be
determined at the peripheral Interface and used to
evaluate compatibility of the peripheral to the system.
During this process, two areas must be, considered.
First, can the device operate at maximum bus bandwidth and if not, how many walt states are required. Second, are there any problems that cannot be resolved by
walt states.
TABLE 4D4. PERIPHERAL REQUIREMENTS FOR FULL SPEED
OPERATION WITH 5 MHz 8086
Configuration
Minimum Mode
TAVRL
TRHAX
TRLRH
TRLOV
TRHOZ
TAVOV
TRLRL
TAVWL
TAVWLA
TWHAX
TWLWH
TWLWHA
TOVWH
TWHOX
TWLCL
TWLCLA
TSVRL
TRHSX
TSLOV
TSVWL
TWHSX
TSVWLA
-
Unbuffered
Buffered
70
57
340
205
155
430
800
70
72
27
320
150
158
400
770
72
-
-
97
360
67
340
-
-
300
88
339
15
772
BOO
-
-
52
50
412
52
54
50
382
54
90
90
-
-
Maximum Mode
Buffered
70
169
375 '
305
382
400
800
270
70
169
175
375
270
95
600
800
52
171
382
252
171
52
Fully Buffered
58
141
347
261
360
372
772
258
58
141
147
347
258
13
572
772
40
143
354
240
143
40
Examples of the first are TRLRH (read pulse width) and
TRLDV (read access or RD active to output data valid).
Consider address access time (valid address to valid
data) for the maximum mode fully buffered configuration.
TAVDV=3TCYC-140 ns - address latch delay address buffer delay - chip select decode delay - 2
transceiver delays
Assuming Inverting latches, buffers and transceivers with 22 ns max delays (8283, 8287) and a
bipolar PROM decode with 50 ns delay, the result
Is:
Not applicable.
TAVDV = 322 ns @ 5 MHz
b. MINIMUM MODE BUFFERED DATA AND COMMAND BUSSES
Figure 401. 8086 System C~nligur.tlons
A-50
AP-67
c. MAXIMUM MODE BUFFERED DATA BUS
elK
8284
NOTE: FOR OPTIMUM PERFORMANCE WITH INTEL PERIPHERALS, AIOW (ADVANCED
WRITE) SHOULD BE USED.
d. MAXIMUM MODE DOUBLE BUFFERED SYSTEM
8284
Figure 401. 8086 System Configurations (Can't)
tional hardware, slowing down the CPU (if the parameter
is related to the clock) or not using the device.
The result gives the address to data valid delay required
at the peripheral (in this configuration) to satisfy zero
wait state CPU access time. If the maximum delay
specified for the peripheral is less than the result, this
parameter is compatible with zero wait state CPU operation. If not, wait states must be inserted until TAVDV + n
* TCYC (n is the number of wait states) is greater than
the peripherals maximum delay. If several parameters
require wait states, either the largest number required
should always be used or different transfer cycles can
insert the maximum number required for that cycle.
As an example consider address valid prior to advanced
write low (TAVWLA) for the maximum mode fully buffered system.
TAVWLA=TCYC-100 ns - address latch delay address buffer delay - chip select decode delay +
write buffer delay (minimum)
Assuming inverting latches and buffers with 22 ns
delay (8283, 8287) and an 8205 address decoder with
18 ns delay
The second area of concern includes TAVRL (address
set up to read) and TWHDX (data hold after write).
Incompatibilities in this area cannot be resolved by the
insertion of wait states and may require either add i-
TAVWLA = 38 ns which is the time a 5 MHz 8086
system provides
A-51
AP-67
4E. 110 Example.
1. Consider an Interrupt driven procedure for handling
multiple communication lines. On receiving an Interrupt
from one of the lines, the Invoked procedure polls the
lines (reading the status of each) to determine which
line to service. The procedure does not enable lines but
simply services Input and output requests until the
associated output buffer Is empty (for output requests)
or until an Input line Is terminated (for the example only
EOT Is considered). On detection of the terminate condl·
tlon, the routine will disable the line. Itls assumed that
other routines will fill a lines output buffer and enable
the device to request output or empty the Input buffer
and enable the device to Input additional characters.
The routine begins operation by loading CX with a count
of the number of lines in the system and OX with the 110
address of the first line. The 110 addresses are aSSigned
as shown In Figure 4E1 with 8251A's as the 110 devices.
The status of each line Is read to determine If it needs
service. If yes, the appropriate routine is called to Input
or output a character. After servicing the line or If rio
service Is needed, CX Is decremented and OX Is In·
cremented to test the next line. After all lines have been
tested and serviced, the routine terminates. If all Inter·
rupts from the lines are OR'd together, only one Interrupt Is used for all lines. If the Interrupt Is Input to the
CPU through an 8259A interrupt controller, the 8259A
should be programmed in the level triggered mode to
guarantee all line Interrupts are serviced.
buffers as a displacement Into the data segment, the
base + Index + displacement addressing mode allows
direct access to the appropriate memory location. 8086
code ~or part of this example is shown In Figure 4E2.
,2. As a second example, consider using memory
mapped 110 and the,8086 string prlmatlve instructions to
perform block transfers betwe~n memory and 110. By
aSSigning a block of the memory address space
(equivalent In size to the maximum block to be transferred to the 110 device) and decoding this address
space to generate the 110 device's chip select, the block
transfer capability Is easily Implemented. Figure 4E3
gives an Interconnect for 16-blt 110 devices while Figure
4E4 Incorporates the 16-blt bus to 8-blt bus multiplexing
scheme to support 8-blt 110 devices. A code example to
perform such a transfer Is shown In Figure 4E5.
To service either an input or, output request, the called
routine transfers OX to BX, and shifts BX to form the offset for this device Into the table of input or output buffers. The first entry In the buffer Is an Index to the next
character position In the biJffer and Is loaded Into the 81
register. By specifying tlie base address of the table of
, THIS CODE DEMONSTRATES TESTING DEVICE
, STATUS FOR SERVICE, CONSTRUCTING THE
; APPROPRIATE LINE BUFFER ADDRESS FOR INPUT
, AND OUTPUT AND SERVICING AN INPUT
, REQUEST
MASK EQU OFFFDH
CHECK......STATUS:
INPUT AL. OX
MOY
TEST
JZ
CALL
TEST
AH. READ STATUS
JZ
WRITE..SEAVICE
CALL
TEST
READ
AH. WRITE STATUS
JZ
WRITE-SERVICE: CALL
NEXT_IO:
ADDRESS:
READ:
; GET 8251A STATUS.
AH,AL
AH. READ_OR-WRITE..STATUS
NEXT-'O
ADDRESS
DEC
JNC
AND
ADD
OR
JMP
NEXT_IO
WRITE
ex
EXIT'
DX. MASK
DX. 3
DX. •
CHECILSTATUS
ox. MASK
AND
MOV
BH, DL
INC
SHR
BH
BH
XOR
BL, aL
j TEST IF DONE.
, YES. RESTORE' RETURN.
, REMOVE AI AND
, INCREMENT ADDRESS.
, SELECT STATUS FOR
, NEXT INPUT.
, ,SELECT DATA.
, CONSTRUCT BUFFER
, DISFLACEMENT FOR
, THIS DEVICE.
, BX IS THE DISPLACEIIENT.
RET
INPUT AL, DX
MOV SI. READ_BUFFERS IBX!
MOV READ_BUFFERS IBX +SQ, AL
INC READ_BUFFERS IBX!
CMPAL. EDT
JNZ CONT_READ
, READ CHARACTER.
i GET CHARACTER POINTER.
, STORE CHARACTER.
, INCR CHARACTER POINTER.
, END OF TRANSIII88ION?
, YES, DISABLE RECEIVER.
,SEND IIESSAGE THAT INPUT
CALL DISABLE READ
CONT.JIEAD: RET
jISREADY.
Flgur.4E2.
D".. \,-_ _ _ _ _ _ _ _ _ _ _ _--,
3605
A' •.8
110 CHIP SELECT
A·l
DECODE
. D7.CJ
iii)
BIPOLAR
PROM
Viii
DEVICES ARE CONNECTED TO THE UPPER AND
LOWER HALVES OF THE DATA BUS.
'ADDRESS
'0
1
2
,3
, 4
5
8
7
TRANSFER 256 BYTE BLOCKS TO THE 110 DEVICE
DEVICE 0
DEVICE 1
DEVICE 0 '
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 2
DEVICE 3
DATA
DATA
CONTROUSTATUS
CONTROUSTATUS
DATA
DATA
CONTROUSTATUS
CONTROUSTATUS
THE ADDRESS SPACE ASSIGNED TO THE 110 DEVICE IS
All
FROM
THRU
k-BASE
~BASE
ADDRESS
ADDRESS
Ar
,~Ao
D'.
~
I',
MEMORY DATA NEED'NOT BE ALIGNED TO EVEN ADDRESS BOUNDARIES
ETC.
110 TRANSFERS MUST BE WORD TRANSFERS TO EVEN ADDRESS BOUNDARIES
Figure 4El. De.lce Asslgnmenl
Figure 4E3., Block Trans'.r 10 16'BIII/O Using 8066 SIring Prlmailve.
A-52
AP;'67
number the device can accept, leaving the remaining ad·
dress lines for chip enable/select decoding. To connect
the devices directly to the multiplexed bus, they must
have output enables. The output enable is also
necessary to avoid bus contention in other configura·
tions, Figure 5A1 shows the bus connections for ROM
and EPROM memories. No special decode techniques
are required for generating chip enables/selects. Each
valid decode selects one device on the upper and lower
halves of bus to allow byte and word access. Byte ac·
cess Is achieved by reading the full word onto the bus
with the 8086 only accepting the desired byte. For the
minimum mode 8086, if RD, WR and M/iO are not decod·
ed to form separate commands for memory and 1/.0, and
the I/O space overlaps the memory space assigned to
the EPROM/ROM then M/IO (high active) must be a.con·
dltion of chip enable/select decode. The output enable
is controlled by the system memory read signal.
CHIP SELECT
015·8
\r--.---,/
CS
BHE--;-"""L._
DATA
iiii
-+-----------J)
8·BIT
110
DEVICE
Viii
1
HIGH
BAN~E(~----:----..,------,
ADDRESS ASSIGNMENT SAME AS PREVIOUS EXAMPLE. 18-BIT BUS IS
MULTIPLEXED ONTO AN 8·BIT PERIPHERAL BUS.
ADDRESS _ _ _ _ _-,
Figure 4E4. Block Transfer to 8·BIt 110 Using 8086 String Prlmatlves
; DEFINE THE 1/0 ADDRESS SPACE
110 SEGMENT
ORG BLOCK.....ADDRESS
I/O_BLOCK: OW 128 DUP (?)
1/0 ENDS
CONTROL
. DATA
; ASSUME THE DATA IS FROM THE CURRENT
;. DATA SEGMENT
.
CLD.
; OF = FORWARD
LES 01, I/O_BLOCKJDDRESS ; 1/0 BLOCK ADDRESS
; CONTAINS THE ADDRESS
; OF 1/0 BLOCK
MOV CX, BLOCLLENGTH
MOV 51, SOURCEJDDRESS
MOVS 1/0 BLOCK
; PERFORM WORD TRANSFERS
; END CODE EXAMPLE
NOTE THE CODE IS CAPABLE OF PERFORMING BYTE TRANSFERS BY
CHANGING THE 1/0 BLOCK DEFINITION FROM 128 WORD TO 258 BYTES
Figure 5.1. 8086 Memory Array
Figure 4E5. Code for Block Transfers
5.INTERFACINQ WITH MEMORIES
CHIP SELECT - - - -....----1 CS1
A"
.....-----~-+~
Q
74LS74
CK
Q 6
Q
74LS32
MRDC 1
--2
MWTC
11
74LS74
CK
Q 8
CLR
13
T,
T,
T,
EARLYRo
Figure 5C2.1. Early Read and Write Command Generation
A-62
AP-67
We can now use the slowest 2118 which gives 8202 and
2118 access of 320 ns. Early command to ROY timing Is
TCLCL - TCHLLmax - circuit delays - TR1 VCLmax =
115 ns and provides 35 ns of margin beyond the 8202
command to SACK delay.
The write timing of the 8202 and write data valid timing
of the 8086 do not allow use of an early write command.
However, If the 8202 clock Is redl,lced from 25 MHz to 20
MHz and WE to the RAM's Is gated with CAS, the advanced write command (AMWC) may be used. At 20 MHz
the minimum command to CAS delay Is 148 ns while the
maximum data valid delay is 144 ns.
refresh. Delaying SACK until XACK time causes the
CPU to enter walt states until the cycle is completed. If
the cycle is a read cycle, the XACK timing guarantees
data is valid at the CPU before ROY is issued to the CPU.
The use of the early command signals also solves a
problem not mentioned previously. The cycle rate of the
8202 @ 20 MHz requires that commands (from leading
edge to leading edge) be separated by a minimum of 695
ns. The maximum mode 8086 however may issue a read
command 600 ns after the normal write command. For
the early read command and advanced write command,
725 ns 'ar,e guaranteed between commands.
The reduced 8202 clock frequency stili satisfies no walt
state read operation from early read and will insert no
more than one wait state for write (assuming no conflict
with refresh). 20 MHz 8202 operation will however require using the 2118-4 to satisfy read access time.
EARLVRo
Note that slowing the 8202 to 22.2 MHz guarantees valid
data within 10 ns after CAS and allows using the 2118-7.
Since this analysis is totally based on worst case
minimum and maximum delays, the designer should
evaluate the timing requirements, of his specific implementation.
WElO RAMS
'-----'CAS
It should be noted that the 8202 SACK is equivalent to
XACK timing if the cycle being executed was delayed by
FIgure 5C2.2. Delayed Write to DynamIc RAMs
A-63
AP-67
APPENDIX I
BUS CONTENTION AND ITS EFFECT ON·SYSTEM INTEGRITY
SYSTEM ARCHITECTURE
function, chip select (eS), which is very fast (tco= 120
ns) with respect to the overall access time (tACC = 450
ns) of the 2708. It is this time difference (330 ns) that is
used to perform the decode function, as illustrated in
Figure 2. The scheme works well and does not limit
system performance, but it does lead to the possibility
of bus contention.
As higher performance microprocessors have become
availabl.e, the architecture of microprocessor systems
has been evolving, again placing demands on memory.
For many years, system designers have been plagued
with the problem of bus contention when connecting
multiple memories to a common data bus. There have
been various schemes for avoiding the problem, but
device manufacturers have been unable to design internal circuits that would guarantee that one memory
device would be "off" the bus before another device
was selected. With small memories (512x8 and 1Kx8), it
has been traditional to connect all the system address
lines together and utilize the difference between tACC
and tco to perform a decode to select the correct device
(as shown in Figure 1).
ADDRESS3'--_______""-__-ilc--_
.
1
----'-------1\
cs ----7-
DATA OUT
1_·
I
D~f~~E_I_.·.· 1~_~
Figure 2. Single Line Control Architecture
BUS CONTENTION
Figure 1. Single Control Line Architecture
With the 1702A, the chip select to output delay was only
100 ns shorter than the address access time; or to state
it another way, the tACC time was 1000 ns while the tco
time was 900 ns. The 1702A tACC performance of 1000 ns
was suitable for the 4004 series microprocessors, but
the 8080 processor required that the corresponding
numbers be reduced to tACC= 450 ns and tco= 120 ns.
This allowed a substantial improvement in performance
over the 4004 series of microprocessors, but placed a
substantial burden on the memory. The 2708 was
developed to be compatible with the 8080 both In ac·
cess time and power supply requirements. A portion of
each 8080 machine cycle time had to be devoted to the
architecture of the system decoding scheme used. This
devoted portion of the machine cycle included the time
required for the system controller (8224) to perform Its
function before the actual decode process could begin.
There are actually two problems with the scheme
described in the previous section. First, if one device In
a multiple memory system has a relatively long deselect
time, and a relatively fast decoder is used, it would be
possible to have another device selected at the same
time. If the two devices thus selected were reading opposite data; that is, device number one reading a HIGH
and device number two reading a LOW, the output tran·
sistors of the two memory devices would effectively pro·
duce a short circuit, as Figure 3 illustrates. In this case,
the current path is from VCC on device number one to
GND on device number two. This current is limited only
by the "on" impedance of the MOS output transistors
and can reach levels In excess of 200 mA per device. If
the MaS transistors have a lot of "extra" margin, the
current is usually not destructive; however, an instan·
taneous load of 400 mA can produce "glitches" on the
Vcc supply-glitches large enough to cause standard
TIL devices to drop bits or otherwise malfunction, thus
causing incorrect address decode or generation.
Let's pause here and examine the actual decode
scheme that was used so we can understand how the
control functions that a memory device requires are
related to system architecture.
The 2708 can be used to Illustrate the problem of having
a single control line. The 2708 has only one read control
A-64
The second problem with a single control line scheme is
more subtle. As previously mentioned, there is only one
control function available on the 2708 and any decoding
scheme must use it out of necessity. In addition, any inadvertent changes in the state of the high order address
lines that are inputs to the decoder will cause a change
in the device that is selected. The result Is the same as
before-bus contention, only from a different source.
The deselected device cannot get "off" the bus before
the selected one is "on" the bus as the addresses rapidly change state. One approach to solving this problem
would be to design (and specify as a maximum) devices
AP-67
with tOF time less than tco time, thereby assuring that if
one device Is selected while another Is simultaneously
being deselected, there would be some small (20 ns)
margin. Even with this solution, the user would not be
protected from devices which have very fast tco times
(tco Is specified as a maximum).
2708=-;------,
Vee
~
I
I
I
I
I
I
Vss
_______ .JI
r----"2iOa:i
I
OR
TIE
Vee
I
I
I
I
I
I
IL ______
Vss
_
DATA
BUS
RESULTS OF IMPROPER TIMING WHEN OR TYING MULTIPLE
MEMORIES.
generate the unique device selecting function, but a
separate and independent Output Enable (OE) control is
now used to gate data "on" and "off" the system data
bus. With this scheme, bus contention Is completely
eliminated as the processor determines the time during
which data must be present on the bus and then
releases the bus by way of the Output Enable line, thus
freeing the bus for use by other devices, either
memories or peripheral devices. This type of architecture can be easily accomplished If the memory devices
have two control functions, and the system Is implemented according to the block diagram shown in
Figure 5. It differs from the previous block diagram
(shown in Figure 1) In that the control bus, which Is connected to all memory Output Enable pins, provides
separate and Independent control over the data bus. In
this way, the microprocessor is always in control of the
system; while in the previous system, the microprocessor passed control to the particular memory device
and then waited for data to become available. Another
way to look at it Is, with a single control line the sytem Is
always asynchronous with respect to microprocessor/
memory communications. By using two control lines,
the memory is synchronized to the processor.
Figure 3. Results 01 Improper Timing when OR Tying Muillple
Memories
The only sure solution appears to be the use of an exter·
nal bus driver/transceiver that has an independent
enable function. Then that function, not the "device
selecting function," or addresses, could control the
flow of data "on" and "off" the bus, and any contention
problems would be confined to a particular card or area
of a large card. In fact, many systems are implemented
that way-the use of bus drivers is not at all uncommon
in large systems where the drive requirements of long,
highly capacitive interconnecting lines must be taken
into consideration-it also may be the reason why more
system deSigners were not aware of the bus contention
problem until they took a previously large (multicard)
system and, using an advanced micorprocessor and
higher density memory devices, combined them all on
one card, thereby eliminating the requirement for the
bus drivers, but experiencing the problem of bus contention as described above.
ADDRESS
--y
V--.1\_ _ _ _ _"
-
SELECTION
OUTPUT
ENABLE
D~~~ --------l(...__....J)I----Figure 4. Two Control Line Archltecture-
THE MICROPROCESSOR/MEMORY INTERFACE
From the foregoing discussion, It becomes clear that
some new concepts, both with regard to architecture
and performance are required. A new generation of two
control line devices Is called for with general require·
ments as listed below:
1. Capability to control the data "on" and "off" the
system bus, independent of the device selecting function Identified above.
2. Access time compatible with the high performance
microprocessors that are currently available ..
Now let's examine the system architecture that is reo
quired to implement the two line control and prevent
bus contention. This Is shown In the form of a timing
diagram (Figure 4). As before, addresses are used to
A65/A66
Figure 5. Two Control
Lln~
Architecture
inter
APPLICATION
NOTE
Ap·61
July 1979
© Intel Corporation, 1979
A-67
AP-61
Multitasking
For the 8086
Contents
INTRODUCTION
ANATOMY OF THE TASK MULTIPLEXER
DEFINITIONS
STATE DIAGRAM
LINKED LISTS
DELAY STRUCTURE
PROCEDURES
ACTIVA TE$TASK Procedure
ACTIVATE$DELAY Procedure
DECREMENT$DELAY Procedure
CASE$TASK Procedure
PREEMPT Procedure
DISPATCH Procedure
PL/M·86 PROCEDURES
Initialization and the Main Loop
Additional Ideas
Source Code
REFERENCES
A-68
AP-61
There are a number .of ways in which ta assign priarities.
Tasks are usually numbered and may be assigned
priarities accarding ta their ascending (.or descending)
numbers. They cauld instead be grauped inta a number
.of priarity levels, with tasks an the same level having
equal priarities. The latter appraach is taken in this
applicatian nate.
INTRODUCTION
Real-time saftware systems differ markedly fram batch
pracessing systems. An external signal indicating that
it is time far an haurly lag .or an interrupt caused by an
emergency canditian is an event usually nat encauntered in batch pracessing. Because real-time cantral
systems .of all types share a number .of characteristics,
it is passible ta develap flexible .operating systems
which will meet the needs .of a great majarity .of realtime applicatians. Intel Carparatian has develaped such
a system, the RMX/80™ system, far the iSBCTM line .of
8080/85 based single baard camputers. Thus, the user is
released fram the chare .of designing an .operating
system and is free ta cancentrate his effarts an the
applicatians saftware far the individual' tasks and
merely integrate them inta a pre-existing system.
But what if a user daes nat need all the capabilities .of an
RMX/80™ system or wants a different hardware canfiguratian than an iSBC™ camputer? This applicatian
nate cantains a set .of PLlM-86 procedures designed ta
be used in medium-camplexity 8086 real-time systems.
A narmal cantral system can be braken dawn inta a
number .of cancurrently executable tasks_ The CPU can
be running .only .one task at any instant .of time but the
speed .of the pracessar .often makes cancurrent tasks
appear ta be running simultaneausly. Breaking the saftware functians inta separate cancurrent tasks is the jab
.of the designer/pragrammer. Once this is dane there remains the prablem .of integrating these tasks with a
supervisary pragram which acts as a traffic cap in the
scheduling and executian .of the separate tasks. This
nate discusses a set .of PLlM-86 pracedures ta implement the supervisary pragram functian.
A minimum .operating system might (like its batch pracessing causin) have .only a queue far ready tasks (tasks
waiting ta be executed). Any task that becames ready is
put an the battam .of the queue and when a running task
is finished, the task an the tap .of the queue is started.
Any inferrupt causes the state .of the system ta be
saved, an interrupt rautine ta be executed, the state .of
the system ta be restared, and executian .of the interrupted pragram ta cantinue. The interrupt rautine might
(.or might nat) put a new task an the ready queue. This
appraach has warked well far many simple cantral
systems, especially in the single-chip camputer area.
But what features are lacking in this appraach that are
necessary (.or at least nice)?
Assume that a manthly repart is being printed and an
alarm .occurs in the external warld that, because .of its
impartance, must be attended ta immediately. The interrupt rautine,executed as a result .of the alarm input,
shauld nat autamatically return ta the interrupted lagging rautine but instead shauld call a preempt rautine
which'checks ta see if a higher priarity task is ready far
executian. The reasan far this is that the manthly repart
rautine, if returned ta, has na way .of "knawing" that a
higher priarity task is waiting ta be executed. The alarm
.output task has been readied by the interrupt rautine
and since it is knawn ta be higher priarity than the lagging task, it is executed first, thereby immediately
signaling the system aperatar that there has been an
alarm. It then returns ta the lagging task pravided that
there are na further high priarity tasks waiting ta be executed. The lagging printer may nat have even paused
during the alarm .output task. The camputer appears ta
human beings ta be executing cancurrent tasks
simultaneausly.
Of caurse, the alarm .output functian cauld be perlarmed
inside the interrupt pracedure. But saaner .or later, the
designer will encaunter a warst case situatian in which
there is nat enaugh time ta execute all required tasks
between interrupts, and the system will fall behind in
real-time. It is much Cleaner ta make the interrupt pracedures as shart as passible and stack up tasks ta be
executed than ta stack up interrupt pracedures.
'
2. Anather feature that might be necessary is a capability ta put a task ta sleep far a knawn peri ad .of real time.
Assume a relay .output must remain clased far .one secand. Mast real-time systems can nat talerate the dedicatian .of the CPU ta such a trivial task far that length .of
time sa a system .of pragrammable dynamic delays
cauld be implemented. This applicatian nate implements such a system.
1. A system .of priarities is .often needed. All waiting
ready tasks must be executed saaner .or later but same
tasks need immediate attentian while .others can be run
when there is nathing else ta da. If a midnight manthly
repart, due far campletian by 8 a.m. the next day, is in
the pracess .of printing at 1 a.m_ and a fire alarm .occurs,
it is reasanable ta assume that the fire alarm has higher
priarity since the fire cauld canceivably render the
manthly repart irrelevant.
Althaugh the PLlM-86 procedures here have been' debugged and tested, it is assumed that the user will want
ta change, add, .or delete features as needed. This applicatian nate is intended ta present ideas far a lagical
structure.of pracedures that, because they are written in
PLlM-86, can be easily madified ta user requirements.
Each pracedure will be discussed in detail, and integratian and aptianal features will be presented.
PLlM-86
PLM-86 is a black structured high level language that
allaws direct design .of saftware madules. Using
PLlM-86, designers can farget their assembly level
A-69
c'oding'problems and design direCtly,lIi a subset of the
English language. The 801i6' architect'ure was designed
to accommodatehigh'ly structured languages and the
PLM'86 compileriS quite effIC:ierit in the generation of
machine code.
',
'
PLM-86 STRUCTURE
PLlM-86 automatically keeps track of the level of the d,ifferentsoftware blocks, (See Chapter 10, "PLiM,86 Pro~
gramrningManual"). There are. methods' of writing
PLI,M·S6whic,h contribute to the understandability cif
I/Je source code without adding ,to the amountof,object
generated., For instance, the following three
IF/THEN/ELSEbiocks, generate identical object ,code
but are complied froln different source statements.
1'
l' ,
7
8
"
9
10
11
13
, ,,1,
2
2
1
14
15
16,' 2
17
2
,,18
1
IF
A= BTHEN PO;
O=D;
END;
ELSE DO;
E= F;
END;' ,
'Stateinent
II"A= 1;1 THEN C=D; ELSE E=F;G= H;
IF A=B THEN
C='D;'
ELSE
E=F;
G=H;
B
IF ,'A= THEN DO;
, ,C=D;
END;
.ELSE IF A = C TH EN PO;
D=E;
END;
".
ELSE IF A= D THEN DO;
E=F;
, END;
ELSE DO;
F=G;
END;
IF A= BTHEN DO;
C =' D;
.
END;
ELSE DO;
E= F;
END;
G=H;
'It is noi instantly apparent frond,~e,code on line3 or the
code starting at lirie 7 which' statements will be executed: However, adding the DO;!ln.d END; statements
(starting at line 11) remove any doubt. ' Either the
statements starting at line 11 or the statements starting
at 11Iie15 will be executed and the stahlment online 18
will Qe executed in either case. Why? Because all these
lines are at level 1 in the block structure. The other lines
are at level 2 because olthe OO;/END; combinations.
When 6,ne refers to the relatively complex structures of
thet~sk multiplexer procedures, the usefulness of such
an approach is obvioLis, as the procedures have been indented according to the level numbers generated by
PLlM·86. In particular, if the designer ,Is not careful,
nes\ed IFITHEN/ELSE statements' can generate impro'per resu,lts. Usinga proper number of DO;/Ei'JD; combinations avoids the possible ambiguity in nested
IF/TH'EN/ELSE statements as can be seen in the ACTIVATE$TASk procedure IIshid In the PLiM·86 source
code later hi this note. The DO;/END; construct naturalLy
must'be ~sed when multiple statements are required
within theIFliHEN/ELSE blocks. Foliowing are examples of the possible primary structures of PLlM-86:
DO; ,
A=B; ,
C=D; ,
END; ,
DO 1';',1,105;
A=I;
C=D+I;
END;
DO CASE A;
A=B;
A=C;
, ,A'=D;
END;
code
Lln~,' Level
3
t
DO WHILE A= B;
C=D;
E=F;
END;
'",:
.
A complete tutorial on structured programming Is
beyond the scope and intentof this application note and
the reader is referred to the appropriate referencesappearing in the bibliography.
ANATOMY OF THE TASK MULTIPLEXER
Once a deciSion is made on the 'details of thek'ind of
data' structure' that is needed to implement the task
multiplexer, the procedures that manipulate the structure are'relatively simple to write. ,The fallowing'characteristics are assumed for the task muJtiplexer appearing' in this applicaiiC)n note. '
,"
'
There"are .two levels of priority, high a~dJow.AIi high
priority tasks that are ready to run will be dispatched,
executed, and completed, on a FIFO basis, before any
.low priority task is dispatChed.
Any task can be Interrupted. No' task multiplexer procedure can be ,interrupted.
,"'",
If a high priority task is interruptEld, it ,,;iill bec'o'mplelEid
before any other task is dispatched.lla low,priorlty 'ask
is interrupted, all ready highpdority tasks wiil be~is
patched~ executed,and completed before program' control is returned to the low priority task.
'
A-70
AP-61
There are two ready queues, one for high priority tasks
and one for low priority tasks. Each queue has a head
(top) pointer and a tail (bottom) pointer and tasks on any
queue are link·listed from head to tail. Tasks are "dis·
patched" (taken off the queue) at the head and "activated" (put on the queue) at the tail on a FIFO basis.
HIGH$PRIORITY$HEAD = 5
HIGH$PRIORITY$TAIL = 3
LOW$PRIORITY$HEAD = 8
LOW$PRIORITY$TAIL = 10
DELAY$HEAD
=4
TASK NUMBER
Link-listed queues are chosen for simplicity. All dispatch and activate information is contained in the head
and tail pointers. Tasks located in the middle of these
link·lists .are of no concern for activating and dispatching. This means, of course, that tasks are executed in
the order that they appear on the queue, i.e., first-in,
first-out.
There is a painter byte associated with each task. If a
task is on either the low priority or high priority ready
queue, its associated pOinter byte will point to the next
task number on the list. These pOinter bytes enable the
task ready lists to be linked. Note that the pointer byte is
o for the last task on a list.
There is a status (flag) byte associated with each task. If
a task is on a ready list or a delay list, bit 7 will be a "1"
indicating that that particular task is busy. If a task is on
either high priority or low priority ready queues,.bit 6 will
be a "1" indicating that the task is on one of the ready
queues. If the task is listed on the delay list, (see next
item), bit 5 will be a "1" indicating that this particular
task has a delay in progress. If a task is unlisted, bits
5-7 will be "0." Bits 0-4 are not used by the task
multiplexer procedures and are available to the user, giving 5 user defined flags per task.
There is a delay byte associated with each task. This
feature allows tasks to be "put to sleep" for a variable
length of time, from 1 to 255 "ticks" of the interrupt
clock. If a task does not need an associated delay then
this byte is available to the user as a utility byte to be
used for any purpose. These delays will be discussed in
detail later in the application note.
The following diagram is a representation of the task
multiplexer data structure:
TASK NUMBER
POINTER BYTE
STATUS BYTE
DELAY BYTE
0
1
2
3
n
n+3
n+6
n+9
n+ 12
n+1
n+4
n+7
n+ 10
n+ 13
n+ 16
n+2
n+5
n+8
n+ 17
m-1
m
n+ 3m-6
n+3m- 2
n+3m-5
n+ 3m- 4
n+3m-l
n+3m
n+ 15
n+11
n+ 14
3m+3 TOTAL RAM BYTES
n = FIRST RAM ADDRESS OF ARRAY
Following is a chart of what a task multiplexer data
structure might look like at a given moment in time:
TASK(n).PNTR
7
1
o
2
10
o
10
TASK(n).STATUS
1100
1010
1100
1010
1100
0000
1010
1100
0000
1100
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
TASK(n).DELAY
o
o
o
·See text.
What information can one ascertain from observation of
the above chart? The ready-to·run high priority tasks, in
order, are 5,1,3. This can be seen by following the high
priority ready linked list from head to tail. The ready-torun low priority tasks, in order are 8, 10. The
TASK(n).PNTR byte 0 for the last listed task. Tasks 4,
7, 2 are listed, in order, on the delay list and have
associated delays of 4,10,13 ticks respectiVely. Tasks 6
and 9 are not I isted and therefore id Ie. The * for the
TASK (0) bytes indicate a special condition. There is no
TASKOO allowed and a zero condition is treated as an er·
ror condition. TASK(O).PNTR byte is used for the
DELAY$HEAD byte to minimize code in the ACTIVATE$DELA Y procedure. TASK(O).STATUS and
TASK(O).DELAY are unused bytes.
=
DEFINITIONS
NEW$TASK is the number of the task that will be installed on a ready list or the delay list when ACTIVATE$TASK or ACTIVATE$DELAY is called.
NEW$DELAY is the value of the delay that will be installed on the delay list when ACTIVATE$DELAY is
called.
A task is defined as RUNNING if it is in the act of execution or if an interrupt routine is executing which interrupted a RUNNING task.
A task is defined as PREEMPTED if it has been interrupted and a higher priority task is being executed.
A task is defined as READY if it is contained within one
of the ready queues.
A task is defined as IDLE if its BUSY$BIT (bit 7) is not
set, i.e., it is not listed anywhere else. Note that it is
possible to completely disable an IDLE task simply by
setting its BUSY$BIT. In that case, it is not and cannot
be listed anywhere else. This feature is useful during
system integration.
A-71
AP-61
STATE DIAGRAM
The state diagram indicates the relationships among
the possible task states and the procedures involved in
changing states.
The state diagram looks somewhat complicated and a
discussion of the possible change of states is in order.
Assuming a certain existing state, future possible
states will be discussed including the procedures which
can cause the change of state.
From the unlisted (idle) state, the ACTIVATE$TASK pro·
cedure will put the NEW$TASK on either the high priori·
ty ready queue or the low priority ready queue at the tail
end of the queue. The number of the task automatically
assigns the priority and therefore the proper queue. All
task numbers below FIRST$LOW$PRIORITY$TASK are
assumed to be high priority tasks. Also, from the
unlisted state the ACTIVATE$DELAY procedure will put
the NEW$TASK and NEW$DELAY at the proper position
on the delay list.
After a task has been put on either high priority ready
queue or low priority ready queue it eventually will go to
the RUNNING$TASK state. The DISPATCH procedure
accomplishes this action.
From the delay list a task can only go to one of the ready
queues. When a task's associated delay goes to zero the
DECREMENT$DELAY procedure calls the ACTI·
VATE$TASK procedure and installs the NEW$TASK on
the proper ready queue.
From the RUNNING$TASK state a task may use the
CASE$TASK procedure to put itself on the ready list tail
by setting NEW$TASK = RUNNING$TASK. It may
instead 'put itself on the delay list by setting
NEW$TASK= RUNNING$TASK and also setting
NEW$DELAY equal to something other than zero. Other·
wise, it will progress to the unlisted state upon comple·
tion.
The CASE$TASK procedure unlists tasks when they
have completed execution. A low priority RUN·
NING$TASK will go to the preempted state if a high
priority task is on the ready list following an interrupt
during execution of the low priority task if the PREEMPT
procedure is called.
And finally, a PREEMPTED$TASK will return to a RUN·
NING$TASK state when all high priority ready tasks
have completed execution. This is accomplished by the
DISPATCH procedure which then returns to the PRE·
EMPT procedure.
STATE DIAGRAM
A-72
AP-61
Some lockouts are necessary to avoid chaos in the task
multiplexer. These are as follows:
The unused bits in the STATUS byte are available to the
user.
The BUSY$BIT= 1 in the TASK(n).STATUS byte will
abort the ACTIVATE$TASK and the ACTIVATE$DELAY
procedures and return an indication of the aborting by
setting the STATUS byte equal zero. A task must be
unlisted to be able to be installed on a list.
The TASK(n).DELAY byte is a number which can put
TASK(n) to sleep for up to 255 system clock ticks. The
system clock tick is interrupt driven from the user's
timer and its period is chosen for the particular applica·
tion. A one millisecond timer is popular and assuming
such a time, delays of up to 255 ms are available in the
task multiplexer as it is written. If this delay range is not
wide enough, the user may want to define his
TASK(n).DELAY as a word instead of a byte in the
PLlM-86 declare statement, giving delays of up to 65
seconds from the basic one millisecond clock tick.
A RUNNING$TASK may put itself on a list after it has
executed but it is not allowed to re·list any listed tasks
(i.e., no task may ever be listed twice at the same time!).
A task that tries to activate another task that is already
busy can wait (via the delay feature) for the required task
to complete execution, become idle, and therefore be
available to be activated. A PREEMPTED$TASK may not
be listed. If the ACTIVATE$TASK or ACTIVATE$DELAY
procedure is called and NEW$TASK = PRE·
EMPTED$TASK, the procedure will be aborted and
return with STATUS = O. Otherwise, the STATUS byte is
returned with the new task status.
Only one task may be preempted as there are only two
levels of priority. The user may desire to implement
many levels of priority in which case a linked·list of
preempted tasks could be declared in a structure which
includes the number of the first task in each priority
level group of tasks. This obviously complicates the
PREEMPT and DISPATCH procedures.
The tasks themselves are made into reentrant proce·
dures because of the necessary forward references' of
the CASE$TASK procedure.
PLlM·86 allows structures and arrays of structures. The
structure needed for the task multiplexer is a link·list
pointer byte, a task status byte, and a task delay byte.
Each task has an associated painter byte, status byte,
and delay byte. These are combined into an array of up
to 255 tasks. For purposes of this discussion, the
number of tasks is chosen as an arbitrary 10, leading to
the following array declaration.
DECLARE TASK(10)STRUCTURE
(PNTR BYTE,STATUS BYTE,DELAY BYTE);
Thus the delay byte associated with task number 7 can
be accessed by using the variable TASK(7).DELAY and
the status of task number 5 can be examined through
the use of TASK(5).STATUS. The TASK(n).PNTR byte
contains the task number of the next listed task on the
same list as TASK(n), i.e., if TASK(n) is on the delay list,
then TASK(n).PNTR will contain the number of the next
task on the delay list or 0 indicating the end of the list.
TASK(n).STATUS is a byte with the following reserved
flags:
BIT
BIT
BIT
BIT
7 BUSY$BIT, "1" IF TASK IS BUSY
6 READY$BIT, "1" IF ON READY LIST
5 DELAY$BIT, "1" IF ON DELAY LIST
4 - BIT 0
UNUSED
LINKED LISTS
Linked lists are useful for a number of reasons.
However, a treatise on linked lists would defeat the pur·
pose of this application note and the reader is referred
to the references listed in the bibliography.
The linked lists used in this application, note have a
head byte associated with each list, i.e., the head byte
contains the number of the first task on the list. The first
task painter byte points to the second task on the list,
etc. The painter of the last task on the list is set at zero
to indicate that it is the last task. Two of the linked lists
are ready queues and require a tail byte as well as a head
byte. The tail byte paints to the last entry on the list.
Tasks are put on the bottom, or tail, of the ready lists
and are taken off the top, or head, of the ready lists. The
delay list has no tail but does have a head, called a
DELAY$HEAD. The delay list is not a queue, as delays
are installed on the list in order of delay magnitude for
reasons to be explained later.
There are two ready lists, one for high priority tasks and
one for low priority tasks. The head and tail pointers
associated with these two lists are: HIGH$PRIORITY$
HEAD, HIGH$PRIORITY$TAIL, LOW$PRIORITY$HEAD,
and LOW$PRIORITY$TAIL. Obviously, the structure can
be expanded to any number of priority levels by expand·
ing the head and tail pointers and the historical record
of the preempted tasks.
DELAY STRUCTURE
A task multiplexer can have a number of simultaneous
delays active and it would be efficient if there were a
way to keep from decrementing all delays on every clock
tick, which is most time consuming. One way to accom·
plish this feat is to move the problem from the
DECREMENT$DELAY routine to the ACTIVATE$DELAY
routine. The delays are arranged in a linked·list of
ascending sizes such that the value of each delay in·
cludes the sum of all previous delays. This allows the
decrementing of only one delay during each clock tick
interrupt routine. An example will further illuminate this
approach. Suppose the following conditions exisl:
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AP-61
Interrupts must be disabled whenever the link·lists are
being changed. If interrupts· are enabled when this
procedure is called, they should be re·enabled upon
returning.
Task 7 has a 5 millisecond delay
Task 3 has an 8 millisecond delay
Task 9 has a 14 millisecond delay
The delay structure is arranged so that:
The assignment of priority is a simple matter. A declare
statement, DECLARE FIRST$LOW$PRIORITY$TASK
LITERALLY 'N,' (where N is the actual number of the
first low priority task) indicates to the procedures that
tasks 1 to N are high priority tasks and tasks N or higher
are low priority tasks.
DELAY$HEAD = 07
TASK(7).PNTR = 03
TASK(3).PNTR = 09
TASK(9).PNTR = 00
TASK(7).DELAY=05 (FIRST DELAY=5)
TASK(3).DELAY = 03 (5 + 3 = 8)
TASK(9).DELAY =06(5 + 3 + 6 = 14)
This procedure checks the busy bit in the status byte to
see if this particular task is already busy and if so,
returns a STATUS of zero. Otherwise, it returns the new
STATUS of the task. It then checks the priority to see if
this particular task is a high or low priority. If it is high
priority, then the task pOinter pOinted to by the HIGH$
PRIORITY$TAIL pOinter is changed from zero to the
number of the NEW$TASK. The HIGH$PRIORITY$TAIL
pOinter is then changed to the number of the
NEW$TASK and the pOinter associated with NEW$
TASK is made equal to zero. This completes the ACTI·
VATE$TASK functions. If the new task is a low priority
task, then the same functions are performed using the
LOW$PRIORITY$TAIL pOinter.
The linked·list is arranged so that the delays are in
ascending order and each delay is equal to the sum of
all previous delays up through that point. Since this is
true, all delays are effectively decremented merely by
decrementing the first delay. Of course, something for
nothing is impossible and the speed gained by arrang·
ing the delays in the above manner is paid for by the
complexity of the ACTIVATE$DELAY routine. But since
the ACTIVATE$DELAY routine is executed less fre·
quently than the DECREMENT$DELAY routine, the sav·
ings in real time is worth the added complexity.
Suppose a new delay is to be activated in the· above
scheme. Task 5 with a delay of 10 milliseconds is to be
added. A before and after chart will indicate what the
ACTIVATE$DELAY procedure must accomplish.
ACTIVATE$DELAY Procedure
This procedure is initiated by a call with the byte NEW$
TASK containing the number of the task to be put on the
delay list and the byte NEW$DELAY containing the
value of the associated delay.
BEFORE
TASK NUMBER
POINTER
07
DELAY
07
03
09
03
09
00
05
03
06
AFTER ..
TASK NUMBER
POINTER
DELAY
07
07
03
05
09
03
05*
09@
00
05
03
02@
04*
FIRST POINTER IS THE DELAY$HEAD
CHANGES ARE MARKED WITH AN •
ADDITIONS ARE MARKED WITH AN @
Note that the pOinter before the added task has changed
and the delay after the added task has changed. The
function of the ACTIVATE$DELAY procedure is to ac·
complish these changes and additions.
PROCEDURES
The following procedure explanations reference the
PLlM·86 source code listing which follows the applica·
tion note text.
.
ACTIVATE$TASK Procedure
This procedure is initiated by a call instruction with the
byte NEW$TASK containing the number of the task to
be put on the proper ready queue.
Interrupts are disabled and the busy bit of this particular
task is checked. If the busy bit is set the STATUS byte is
set to zero and the procedure returns without activating
the delay. If the busy bit is not set the integer value DIF·
FERENCE is set equal to the NEW$DELAY value.
POINTER$O is set equal to the DELAY$HEAD. POINT·
ER$1 is set to zero. The DO WHILE loop executes until
POINTER$O equals zero or DIFFERENCE is less than
zero. Remember that the proper place to insert the new
delay is being searched for,and that wiH be eitherat the
end of the list (POINTER$O = 0) or when the sum of the
previous delays do not exceed the neW delay value. The
DO WHILE loop l;1as POINTER$O, POINTER$1, OLD$DIF·
FERENCE, and DIFFERENCE keeping track of where
the procedure is in the loop, while searching for the
proper place to insert the new delay. The existing delays
are sequentially subtracted from the remains of NEW$
DELAY according to the link·listed order until the end of
the list or a negative result is encountered indicating
that the proper delay insertion pOint has been reached.
At this point POINTER$O contains the task number to be
assigned to TASK(NEW$TASK).PNTR. POINTER$1 con·
tains the task number immediately preceding the
NEW$TASK such that TASK(POINTER$1). PNTR= NEW$
TASK and our. link list is fully updated, with the actual
delays yet to go. If POINTER$O = 0 it means that the new
delay is larger than any of the other delays and therefore
should go on the end of the list so TASK(NEW$
TASK).DELAY is set equal to the DIFFERENCE. If
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AP-61
POINTER$O is not equal to zero then if POINTER$O
equals POINTER$1 (indicating that there were not any
delays previously listed), then TASK(POINTER$1).PNTR
is set equal to zero. TASK(NEW$TASK).DELAY is
set equal to the OLD$DIFFERENCE and TASK
(POINTER$O).DELAY is set equal to the negative of DIF·
FERENCE which at this point is negative, thereby
resulting in a positive unsigned number. The reader is
encouraged to implement an example (see Delay Structure section) to prove that the above approach is valid.
Particular attention should be paid to the contents of
the two pOinters, as they are the key to the procedure.
The final function of this procedure is to set the
BUSY$BIT and DELAY$BIT in the TASK(NEW$
TASK).STATUSbyte. The byte named STATUS which is
returned by this procedure is set equal to the status of
the new task. If it is desired to have interrupts enabled,
they must be enabled after the procedure return instruction. The reason for such a complex method of activating a delay will become apparent in the following
section.
DECREMENT$DELAY Procedure
The first delay on the linked-list is decremented and, if it
is zero, the associated task is put on the appropriate
ready queue. The next delay (if any) is checked to see if
it is zero and if so, that task is put on the appropriate
ready ,queue, etc. A loop is performed until either no
delay or a non-zero delay is found. The procedure then
returns.
It is assumed that this procedure is part of an interrupt
routine and that the interrupts are disabled during its
execution. Interrupts cannot be enabled during changes
to any of the linked-lists or else recovery may not be
possible.,
This ,procedure begins by checking to see if there are
any active delays. If DELAY$HEAD = 0 thEm this procedure returns immediately. Otherwise it decrements
the first delay. If this delay goes to zE1ro then ,the
associated task number is passed to the ACTIVATE$
TASK procedure as the, OFF$DELAY byte. A new
DELAY$HEAD is chosen from the next link-listed delay
and that delay checked for a,value of zero which will
happen if the first two or more delays are equal. This
loop. is accomplished by the DO WHILE, DELAY$
HEAD <> 0 AND TASK(DELAY$HEAD).DELAY = 0; This
procedure is designed to require very little CPU time
unless a delay times out. The DO WHILE loop is bypassed if the resulting delay value is not zero. A certain
amount of care should be exercised to insure that many
delays do not all time out at the same time. One method
would be to modify the ACTIVATE$DELAY procedure to
insure that there are no zero entries in the delay bytes.
The basic procedure, however, assumes that the clock
"tick" timing will be chosen to minimize the above
potential problem.
CASE$TASK Procedure
This procedure performs the function of calling the task
indicated by the contents of the RUNNING$TASK byte.
All listed tasks are called in this manner. The
CASE$TASK procedure is called by the DISPATCH procedure. When a particular task has completed execution
it returns to the CASE$TASK procedure which then
resets the BUSY$BIT and the READY$BIT and re'turn,s to
the DISPATCH procedure after setting RUNNING$TASK
equal to zero. This procedure allows a task to relist itself
immediately upon returning from execution.
PREEMPT PROCEDURE
The PREEMPT procedure is called whenever it is possible that a high priority task has been put on the ready
queue while a low priority task was in the process of
execution. An example will il,lustrate:
Assume that the control system is being interrupted by
the 60 Hz line frequency and a register is being incremented each time this 16.67 ms edge occurs. When
the register gets to 60 (indicating that one second has
passed), the register is zeroed and the high priority timekeeping task is put on the ready queue. Assume also
that a low priority data logging task was running when
this interrupt occurred. The interrupt routine calls PREEMPT. If a high priority task is running, PREEMPT
simply returns. But in our example, a low priority task is
running so PREEMPT transfers RUNNING$TASK to
PREEMPTED$TASK and calls DISPATCH, which calls
CASE$TASK, which calls the time-keeping task. When
the time-keeping task ,has completed, it returns to
CASE$TASK which returns to DISPATCH which returns
to the PREEMPT procedure which returns to the interrupt routine which returns to the interrupted low priority
data logging task if no other high priority tasks are on
the ready queue. If the high priority ready queue is not
empty, any and all high priority tasks will be completed
before the interrupted routine is returned to. PREEMPT
refuses to return to the interrupt routine until HIGH$
PRIORITY$HEAD is equal to zero. It is important to note
that a low priority task will not be preempted unless the
PREEMPT procedure is called. As noted above,'it is normally called from the interrupt routine which interrupted
the low priority task, but there is nothing to prohibit
PREEMPT from being called from inside a low priority
task procedure.
DISPATCH PROCEDURE
This procedure calls a high priority task if HIGH$
PRIORITY$HEAD is not equal to zero, restores a preempted task if PREEMPTED$TASK is not equal to zero,
calls a low priority task if LOW$PRIORITY$HEAD is not
equal to zero, and simply returns if there is nothing to
do, all in order of priority. The DISPATCH procedure is
called from the main program loop which must enable
interrupts as DISPATCH disables interrupts as soon as
A-75
AP-61
it is called. It is also called by the PREEMPT procedure.
RUNNING$TASK must be 0 when this procedure is
called.
PLlM·a6 PROCEDURES
Because the block structure and levels are so important
to the understanding of the following procedures, they
have been indented according to level. This was a sim·
pie task accomplished by no indenting for level one,
indenting once for level two, etc. The resulting attrac·
tive, easy to follow format was worth the effort to
increase the initial level of understanding for readers of
this application note who are not intimately familiar
with PLiM.
Everything except the very simple main program loop
has been made into procedures. Interrupt routines and
tasks are also procedures. Keeping track of interrupts,
calis, and returns is easy for PLiMand a violation of the
block structure through such devices as GOTO targets
outside the procedure body is the best way the author
knows to crash and burn. Honor the power of the struc·
ture, accept the limitations involved, and checkout and
debugging will be a pleasure.
Since CASE$TASK references the individual tasks, the
task procedure structure was included in the PLlM·86
compilation. All the user has to do is insert the par·
ticular task code in place of the I'TASKnn CODE'I com·
ment, define the interrupt procedures and the system
should be ready to run. Obviously, the user will desire to
change the total number of tasks and the number of the
FIRST$LOW$PRIORITY$TASK.
INITIALIZATION AND THE MAIN LOOP
The last entry in the PLlM·86 program is the initialization
process which essentially zeros the task multiplexer
data and the main loop which loops until TRUE= FALSE,
i.e. forever, with interrupts enabled. The STATUS =
STATUS instruction simply insures that the loop can be
interrupted as the instruction following an ENABLE in·
struction is not interruptible.
These few instructions are included for information only
and will need to be expanded considerably for use in a
real·world system. The task multi'plexer procedures
were checked out on an iSBC 86112™ computer running
under random interrupt control and these instructions
were the minimum necessary to cause the system to
run. As was stated earlier, the following source code
does not include any interrupt procedures and these will
have to be generated following the format explained in
the PLlM·86 programming manual.
ADDITIONAL IDEAS
Resource allocation is a feature that could be added to
the task multiplexer. To keep it simple and yet avoid the
deadlock problem (two tasks each grab a resource that
the other needs), an extra array can be added to the
TASK(n).XXX structure in which each bit in the byte (or
word), represents a resource necessary for the execu·
tion of a task. A RESOURCES$STATUS byte can then
keep the dynamic busy status of the system resources
(printers, terminals, floating pOint math packages, etc.).
When the CASE$TASK procedure is called, the
resources required by the next RUNNING$
TASK can be compared to the RESOURCES$STATUS
byte to see if the required resources are available. I! they
are, the following PLlM·86 statement will update the
new status of the resources:
RESOURCES$STATUS= RESOURCES$STATUS OR
TASK(RUNNING$TASK).RESOURCES; .
However, if the resources are not available, the CASE$
TASK procedure can return the task to the ready ordelay
list and try again later. When the task has completed,
the following PLlM·86 statement will update the
resources status byte:
RESOURCES$STATUS,= RESOURCES$STATUS AND NOT
TASK(RUNNING$TASK).RESOURCES;
Message passing from task to task may also be
necessary. Assuming that a task will have only one
message at a time to deliver or receive, another byte
could be added to the task structure such that
TASK(RUNNING$TASK).MESSAGE could represent a
byte containing the number of the task wishing to
deliver a message to the RUNNING$TASK. Since a task
can call CASE$TASK which in turn will call another task,
message block parameters can be passed directly from
one task to another. The task that calls CASE$TASK
must handle the necessary housekeeping involved in
recoveri ng after the message has been passed. Of
course, the data structure would have to be expanded to
accommodate the message parameters and blocks. For
further ideas involving message handling refer to the
RMXI80™ user's guide.
Two additional relatively simple procedures could be
added to obtain the SUSPEND and RESUME features of
the RMXI80™ system. Remember that if the BUSY$BIT
is set in a TASK(n).STATUS byte and the task is unlisted,
then it cannot be listed. I! it is desired to dynamically
enable and disable a task, this bit could be set by a
SUSPEND procedure and reset by the RESUME pro·
cedure.
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AP-61
SOURCE CODE
Tl"186: DO;
OECLARE
OECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
TOTAL$TASKS LITERALLY' 10';
TRUE LITERALLY '0FFH';
FALSE LITERALLY '0';
BUSY$BIT LITERALLY' 10000000B';
READ~$BIT LITERALLY '01000000a';
DELAY$BIT LITERALLY '00100000B';
FIRST$LOW$PRIORIT~$TASK LITERALLY '6';
DECLARE
DECLARE
DECLARE
DECLARE
OECLARE
DECLARE
TASK(TOTAL$TASKS) STRUCTURE(PNTR B~TE, STATUS BYTE, DELAY BYTE);
HIGH$PRIORITY$HEAD BYTE, HIGH$PRIORITY$TAIL BYTE;
LOW$PRIORITY$HEAD BYTE, LOW$PRIORI'rY$'rAIL BYTE;
RUNNING$TASK BYTE, PREEMPTED$TASK BYTE;
STATUS BYTE, NEW$TASK BYTE, NEW$DELAY BYTE;
OELA~$HEAD BYTE AT (@TASK(0) .PNTR) ;
AC'rIVA'rE$TASK: PROCEDURE; /* ASSUMES NEW$TASK<>0 * /
DISABLE;
IF (TASK(NEW$TASK) .STATUS AND BUSY$BIT)<>0 THEN STATUS=0;
ELSE /* SINCE TASK IS NOT BUSY */ DO;
IF NEW$TASK < FIRST$LOW$PRIORITY$TASK THEN DO;
IF HIGH$PRIORITY$TAIL<>0 THEN DO;
TASK(HIGH$PRIORITY$TAIL) .PNTR=NEW$TASK;
END;
ELSE /* SINCE HIGH$PRIORITY$TAIL=0 THEN */ DO;
HIGH$PRIORIT~$HEAD=NEW$TASK;
END;
HIGH$PRIORIT~$TAIL=NEW$TASK;
END;
ELSE /* SINCE TASK IS LOW PRIORITY THEN */ DO;
I~ LOW$PRIORITY$TAIL<>0 THEN DO;
TASK(LOW$PRIORITY$TAIL) .PNTR=NEW$TASK;
END;
ELSE /* SINCE LOW$PRIORITY$TAIL=0 THEN */ DO;
LOW$PRIORITY$HEAD=NEW$TASK;
END;
LOW$PRIORITY$TAIL=NEW$TASK;
END;
TASK (NEW$TASK) .PNTR=0;
TASK (NEW$TASK) • STATUS=TASK(NEW$TASK) .STATUS OR
BUSY$BIT OR READY$BIT;
STATUS=TASK(NEW$TASK) .STATUS;
END;
NEW$TASK=0;
RE'rURN;
END ACTIVATE$TASK;
A-77
AP-61
ACTIVATE$DELAY: PROCEDURE;I*ASSUMES NEW$TASK, NEW$DELAY<>0*1
DECLARE POINTER$0 BYTE, POINTER$1 BYTE;
DECLARE OLD$DIFFERENCE INTEGER, DIFFERENCE INTEGER;
DISABLE;
IF (TASK(NEW$TASK) .STATUS AND BUSY$BIT)<>0 THEN STATUS=0;
ELSE 1* SINCE TASK IS NOT BUSY *1 DO;
DIFFERENCE=INT(NEW$DELAY) ;
POINTER$0=DELAY$HEAD;
POINTER$I=0;
DO wHILE POINTER$0<>0 AND DIFFERENCE>0;
OLD$DIFFERENCE=DIFFERENCE;
DIFFERENCE=DIFFERENCE-INT(TASK~POINTER$0) • DELAY) ;
IF DIFFERENCE>0 THEN DO;
POINTER$I=POINTER$0;
POINTER$0=TASK(POIN'rER$I) .PNTR; .
END;
END;
TASK(NEW$TASK) .PNTR=POINTER$0;
TASK(POINTER$I) .PNTR=NEW$TASK;
IF POIN'rER$0=0 THEN TASK (NEw$'rASK) • DELAY=LOW CUNSIGN (DIFFERENCE) );
ELSE 1* SINCE DIFFERENCE<0 THEN *1 DO;
IF POINTER$0=POINTER$1 THEN TASK(POINTER$I) .PNTR=0;
TASK(NEW$TASK) .DELAY=LOW(UNSIGN(OLD$DIFFERENCE));
TASK(POINTER$0) .DELAY=LOW(UNSIGN(-DIFFERENCE));
END;
.
TASK (NEw$TASK) .STATUS=TASK(NEw$TASK) .STATUS OR
BUSY$BIT OR DELAY$BIT;
STATUS=TASK(NEW$TASK) .STATUS;
END;
NEw$'rASK=0 ;
NEw$DELAY=0;
RE'rURN ;
END ACTIVATE$DELAY;
DECREMENT$DELAY: PROCEDURE;
lie ASSUMES INTERRUPTS DISABLED */
DECLARE OFF$DELAY BYTE;
IF DELAY$HEAD<>0 THEN DO;
TASK(DELAY$HEAD).DELAY=TASK(DELAY$HEAD) .DELAY-I;
DO wHILE DELAY$HEAD<>0 AND TASK(DELAY$HEAD).DELAY~0;
OFF$DELAY=DELAY$HEAD;
DELAY$HEAD=TASK(DELAY$HEAD) .PNTR;
TASK (OFF$DELAY) .STATUS=TASK(OF~$DELAY) ~STATUS
AND NOT (BUSY$BI'r OR DELAY$BIT);
NEW$TASK=OFF$DELAY;
CALL ACTIVATE$TASK;
END;
END;
RETURN;
END DECREMENT$DELAY;
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AP·61
CASE$TASK:
DO CASE
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
PROCEDURE
REENTRANT~
RUNNING$TASK~
'rASKfil0 ~
'rASK01 ~
'rASKfil2 ~
'rASK(B ~
TASK04~
'fASKfil5 ~
'fASKfil6 ~
TASKfil7~
'rASK08 ~
TASKfil9~
END~
"
TASK (RUNNING$TASK) • STA'rUS=TASK (RUNNING$TASK) • STATUS AND
NOT (BUSY$6I~ OR READY$BIT1~
TASK (RUN1UNG$'fASK) • PNTR=fil ~
IF RUNNING$TASK=NEw$TASK THEN DO~
IF NEw$DELAY<>fil THEN DO~
CALL ACTIVATE$DELAY~
END~
ELSE /* SINCE NEw$OELAY=fil */
CALL ACTIVATE$TASK~
DO~
END~
END~
RUNNING$'fASK=fil ~
RETURN ~
END CASE$'rASK~
PREEI>lPT:PROCEDURE REENTRANT~ /* ASSUMES INTERRUPTS DISABLED */
IF PREEMPTED$TASK=fil THEN DO~
IF (HIGH$PRIORITY$HEAD<>fil) AND (RUNNING$TASK>=
FIRST$LOW$PRIORITY$TASK) THEN DO~
PREEMPTED$TASK=RUNNING$TASK~
RUNNING$TASK=fil~
DO wHILE PREEMPTED$TASK<>fil~
CALL DISPATCH~
END~
END~
END~
RETURN ~
END PREEMPT~
A-79
AP~1
DISPATCH:PROCEDURE REENTRANT; 1* ASSUMES RUNNING$TASK=0 ~I
DISABLE;
IF HIGH$PRIORITY$HEAD<>0 THEN DO;
RUNNING$TASK=HIGH$PRIORITY$HEAD;
aIGH$PRIORITY$HEAD=TASK(RUNNING$TASK) .PNTR;
IF HIGH$PRIORITY$HEAD = 0 THEN HIGH$PRIORITY$TAIL
0;
CALL CASE$TASK;
END;
ELSE IF PREEMPTED$TASK<>0 THEN DO;
RUNNING$TASK=PREEMPTED$TASK;
PREEMPTED$TASK=0;
END;
ELSE IF LOW$PRIORITY$HEAD<>0 THEN DO;
RUNNING$TASK=LOW$PRIORITY$HEADj
LOW$PRIORITY$HEAD=TASK(RUNNING$TASK).PNTR;
IF LOW$PRIORITY$HEAD = 0 THEN LOW$PRIORITY$TAIL
0;
CALL CASE$TASK;
END;
ELSE RETURN;
RETURN;
END DISPATCH;
A~O
Ap·61
TASK00: PROCEDURE
REENTRAN'r~/*ERROR CODE*/RETURN~END
TASK01: PROCEDURE
REENTRANT~
ENABLE~
/*'rASK01 CODE* /
DISAi3LE~
RE'rURN~
END
TASK01~
TASK02: PROCEDURE
REENTRANT~
ENAi3LE~
/*'rASK02 CODE* /
DISAt3LE~
RETURN ~
END TASK02~
TASK01: PROCEDURE
REENTRANT~
ENABLE~
/*'rASK01 CODE*/
DISABLE~
RE'rURN ~
END 'l'ASK01 ~
'rASK04: PROCEDURE REENTRANT ~
ENABLE~
/*'rASK04 CODE */
DISABLE~
RETURN ~
END 'fASK0 4 ~
TASK05: PROCEDURE REENTRANT~
ENABLE ~
/*'rASK05 CODE* /
DISABLE~
RETURN ~
END TASK05~
TASK06: PROCEDURE
REENTRANT~
ENABLE~
/*TASK06 CODE*/
DISABLE~
RE'rURN ~
END TASK06~
TASK07: PROCEDURE REENTRANT~
ENABLE ~
/*'rASK07 CODE*/
DISABLE~
RETURN ~
END TASK07~
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TASK00~
AP-61
TASK0B: PROCEDURE REENTRANT;
ENABLE;
/*'rASK0 B CODE */
DISABLE;
RE'rURN ;
END TASK0B;
TASK09: PROCEDURE REENTRANT;
ENABLE;
/*'rASK09 CODE* /
DISABLE;
RETURN ;
END 'rASK09;
/* IN I'rIAL I ZE* /
DISABLE;
STATUS=0 'ro 9;
TASK(STATUS).PNTR=0;
TASK(STATUS) .STATUS=0;
TASK(STATUS).DELAY=0;
NEW$TASK,NEW$DELAY=0;
HIGH$PRIORITY$HEAD,HIGH$PRIORITY$TAIL=0;
LOW$PRIORITY$HEAO,LOW$PRIORITY$TAIL=0;
RUNNING$TASK,PREEMPTED$TASK=0;
END;
00
/* MAIN LOOP */
DO WHILE TRUE<>FALSE;
CALL DISPA'rCH;
ENABLE;
STATUS=STA'rus;
END;
END TMB6;
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AP-61
REFERENCES
1. Hansen, Brinch, Operating System Principles, Prentice·Hall, Englewood, N.J., 1973.
2. Knuth, D. E., The Art of Com'puter Programming, Addison-Wesley, Reading, Mass., 1969.
3. Wirth, Nicklaus, Algorithms + Data Structures
=Programs,
Prentice-Hall, Englewood, N.J., 1976.
4. "PLlM-86 Programming Manual," Intel Corporation, 1978, manual order number 9800466A.
5. "RMX/80 User's Guide," Intel Corporation, 1977, manual order number 9800522B.
A83/A84
inter
APPLICATION
NOTE
Ap·50
September 1979
© Intel Corporation, 1979
A-85
Ap·50
Debugging Stragegies
and Considerations for
8089 Systems
Contents
INTRODUCTION
STATIC (OR FUNCTIONAL) DEBUGGING
Hardware Testing
External Processor Interface
Software Testing
REAL·TIME TESTING
Logic Analyzer Techniques
A REVIEW OF lOP OPERATION
Task Execution
Going from Instruction Execution into DMA
DMA Termination
Priorities/Dual Channel Operation
SUMMARY
Appendix I. CHECKLIST OF
POSSIBLE PROBLEMS
Appendix II. BREAKPOINT ROUTINE
AND CONTROL PROGRAM
Our thanks to John Atwood and Dave Ferguson, the authors of this
note. Both John and Dave are members of Intel's 8089 design
engineering group. Please direct any questions you may have to
your local Intel FAE (field application engineer) or to MPO
Marketing at Intel, Santa Clara.
A-86
AP-50
An aid to debugging any system is a clean, well organized system design. The 6069 lends itself to structured,
modular software interfaces to the host CPU, via the
linked·list initialization structure, and parameter communication through the parameter block (PB) area.
Some of the aspects of structured programming that aid
debugging are:
INTRODUCTION
The Intel 6069 Is the first integrated 1/0 processor
available. This 1/0 processor (lOP) makes available the
power of 1/0 channels, as used in mainframes and minicomputers, In a microcomputer form. Designed as part
of the MCS·6S™ family, the lOP can be Interfaced with
the MCS·60™ and MCS·65™ families as well.
• Top Down Programming - The functions done by
low·level routines are well understood, and the
number of program fixes, which can cause more
errors, is minimized.
An 1/0 channel is basically a processor remote from the
main CPU, which independently runs 1/0 operations
upon command of the CPU. To relate the 6069 to exIsting LSI components, it is similar to a microprocessor
that is time·multiplexed with a DMA controller, but with
two channels available. However, since the 6069 proc·
essor is optimized for 1/0 and multiprocessor operations, and the DMA has been made much more flexible
than existing DMA controllers, a truly general purpose
and powerful 110 control system Is available on one chip.
• Program Modularity - Small, easy to manage subprograms can be debugged independently, increas·
ing the chance that the entire system will work the
first time.
• Modular Remoteness - By having all program
modules communicate only through a well-defined
interface, one module's knowledge of the "inner
workings" of another is minimized. System soft·
ware complexity is reduced. Updates to program
modules are more reliable, too.
Due to the uniqueness of the 6069, this application note
was written to review debugging strategies and point
out possible pitfalls when developing an lOP system.
Debugging an lOP system is very similar to debugging
m Icroprocessor/DMA controller systems, and many of
the techniques described here are standard microproc·
essor techniques. However, several factors are present
which can complicate the debugging process:
Two major areas of debugging will be outlined here static (or functional) debugging in which the hardware
and software are not tested in a real-time environment,
and real·time debugging. Applying a logic analyzer to
lOP debugging will also be explained, and a review of
lOP operation and potential problems will be done.
1. Multiprocessor Operation
Although usable by itself, the lOP is designed to be
used with other processors. All factors normally encountered with multiprocessor operation, including bus
arbitration, processor communication, critical code sec·
tions, etc., must be addressed in the design and debug
of an lOP system.
STATIC (OR FUNCTIONAL) DEBUGGING
The predominant errors in a system, when first tried out,
are, either errors in Implementation (I.e., wrong hookups
or coding errors), or an Incorrect implementation (a
wrong assumption somewhere). Most of these bugs can
be found through static debugging techniques that are
usually easier to work with than real-time testing.
2. DMA Tle·ln to lOP Program Execution
The relationship between lOP program execution and
DMA transfers and termination is different from earlier
DMA controllers and should be fully understood to properly run the system.
3. Dependency of Programs on Real·Tlme I/O
Operations
Requirements by 110 devices for maximum data rates
and minimum latency times farce the software program·
mer to be aware of hardware timing constraints and can
complicate program debugging.
Hardware Testing
Static hardware testing is done mainly to see if all indio
vidual parts of the system work, so the whole system
will "play" when run. The level of testing can run from
checking for continuity and shorts (which finds only
hookup errors) to trying to move data around and running 110 devices from a monitor or special test programs
(which can also find incorrect circuit design). In all but
the simplest systems, the lalter approach Is recom·
mended since it is a step towards software debugging.
Related to multiprocessor operation and real·time
dependencies, the two independent channels available
on the 6069 may have to be coordinated with each other
to make the whole system function. Dependence of one
channel on the other can also complicate debugging.
Several approaches to hardware testing will be covered.
Running diagnostic programs (such as a monitor) out of
the lOP's host system, in both the LOCAL and REMOTE
modes, will be covered. The case where the host system
cannot support diagnostic software and must have an
external processor to exercise the lOP and its periph·
erals will also be explained.
Due to the complexities of running in a real·time envi·
ronment, as many steps as possible should be taken to
facilitate debugging. A major help here is to make sure
as much of the hardware and software as possible is
working before running real-time tasks. This is a good
practice anyway, but it should be reemphasized that a
complex multichannel system can quickly get out of
hand if more than a few things are not right.
The case where the host system can run diagnostics or
test programs that have interactive user 110, such as a
CRT terminal or teletype, provides the most straightforward way to test the lOP. Naturally, before these pro·
grams can be run, the basic hardware must be correct
enough to run programs. When this point is reached, a
monitor program can be used to exercise memory and
110 controllers on the system bus.
4. Dual Channel Operation
A-87
AP-50
It should be mentioned that aids, other than just testing
with software, are helpful for hardware debugging.
While a necessity for real-time debugging, a logic
analyzer is also a definite help for static hardware
debugging. Its main use in hardware debugging is showing timing relationships between address or data paths
and other signals. It is especially useful for functional
software debugging, to be described shortly. The last
debugging section outlines the use of an analyzer with
the lOP. Of course, an oscilloscope, logic probes and
pulsers, etc., can be used to trace out specific logic or
timing problems.
REMOTE Mode
From a system design standpoint, running the lOP in
the REMOTE Mode is advantageous in that it removes
the 1/0 bus cycles from the system bus. Normally, the
remote 1/0 is not accessible to the host CPU. Until the
lOP is able to run its own test programs to transfer data
from the REMOTE bus to the system bus, 1/0 controllers
and memory on the REMOTE bus will be invisible to the
host. To get around this problem during prototyping,
either an external processor interface can be used (see
next section), or a temporary bypass can be made to access the REMOTE bus from the system bus.
LOCAL Mode
Bypassing the normal REMOTEISYSTEM interface is a
handy technique for doing preliminary debugging on the
REMOTE bus. This can be done by memory-mapping the
lOP's 1/0 space into an, unused portion of the host
CPU's system memory space. When accessing this
space, the lOP access to its own 1/0 space is disabled,
and a separate set of address buffers, transceivers and
bus control signal buffers are enabled. Reads and writes
can then be do'ne to the formerly inaccessible REMOTE
bus by the host CPU.
When the lOP is running in the LOCAL Mode, all 1/0 controllers and memory are accessible by the host or controlling CPU. Thus a standard monitor, such as the one
supplied with the SDK-86 or available for the iSBC86112™ development kit, can exercise all hardware on
the bus.· The breakpoint routines, however, will not
work due to the different instruction set. The 8086 or
8086 is best suited for running the lOP in the LOCAL
mode due to identical status lines and bus timing, as
well as the RequestlGrant line, which eliminates bus arbitration hardware. Figure 1 shows the general LOCAL
mode configuration.
A simple system (Figure 2) implements this bypassing
scheme. It was designed fpr just forCing or examining
devices on the REMOTE bus and may not read or write
correctly if the lOP is simultaneously trying to do bus
cycles. A more sophisticated arbitration system would
permit reliable run-time checking also.
"The SDK·B6 serial monitor is a good basis for a general BOB6 moniior.
The lOP cannot be used directly with the SDK·B6, since the BOB6 is run·
ning in the minimum mode. The SDK·B6 can be converted to run in the
maximum mode, if desired.
SYSTEM BUS
~
~
8284
CLOCK GENERATOR
ADo-AD15
A16- A19
READY RESET CLK
8086
CPU
CLK
So-52
RESET
A
'J
LOCALBUS~
3 x 8282
LATCH
~ ;l-
r--v
y-
~
rv-
\nI
PROM
f---P-
READY
LA
,---y
Ra/GRT
~
2 x 8286
TRANS.
RQ/GRT
READY
RAM
AOo-AD15 IA
CLK
RESET
;Ll\
A16- A19
8089
lOP
so-s,
I\[
so-s,
~
I MWTC
I AMWC
0
:0
c
8288
BUS
IIORDC
CONTROLLER
I 10WC
I-
x
w
CLK
IJI---1\
1\nI
SERIAL
1/0
(8251)
t--
IAIOWC
~
1/0
PERIPHERAL
1 1
CONSOLE 1/0
TO RUN TEST
PROGRAMS
Figure 1. Generalized LOCAL Conflguratlon-SOB6 in Max Mode
A-88
AP-50
SYSTEM (
ADDR~~~)}--______________~--------------~----------~------------~--------------~
SYSTEM ,DATABus)}--______________~--------------~--------~---------------~--------~----~
SYSTEM r-------------~----------------~--------~------------~----------~----~
CONTROL\L________________~------------~--------~--------------~--~----~----~
BUS'
r-------
lOP DISABLE
I
I
-l
I
~~~T5::, TO
1/:g~ESS
I
I
LOGIC
L ___________ :.JI
t================~==~=======;=====l ~~DRESS
I
BUS
I------------------------------------j 110 DATA
1--------------------~------------7BUS
110
" - - - - - - - - - - - - - - - - - - - - - ' - - - - - - ' - - - - - - - - - - - - - - - - - - - - - - - - - ' - - - - - - - - - - - - - CONTROL
BUS
Figure 2. Remote Mode Bypass for Debugging
Running the lOP in the REMOTE mode, particularly if
the MULTIBUS™ protocol is adhered to, has the advantage that the lOP can be exercised with any MULTIBUScompatible processor. If the main processor is not
amenable to being used as a debugging tool, another
processor could be used to debug the hardware interface. If the microprocessor is of the same type as the
intended host processor, software debugging can be
done as well. A generalized REMOTE mode configuration using the MULTIBUS is shown in Figure 3.
External Processor Interface
A technique that can be used if the host processor cannot run any debugging or monitor routines is to have an
external processor tie into the host processor's bus.
This is useful if the main system CPU cannot run an interactive monitor or other debugging programs. If a
MULTIBUS Interface is being used, an 8289 bus arbiter
and a set of address/data/control buffers can be used. A
somewhat simpler system, similar to the remote bus access system mentioned above, could be used for static
debugging of non-MULTIBUS systems. Again, if true bus
arbitration is added (which brings us nearly to a MULTIBUS interface), it could also be used for run-time
testing. Intel processors that have the MULTIBUS
interface include the iSBC-80/20™, iSBC-86/12™, iSBC-
80/10™, iSBC-80/05™, the Intellec'" development
systems, among others.
In the previously described systems, the external processor would disable the host CPU's access to the bus,
either by some form of bus request or by a "brute force"
disabling of the CPU's buffers. In the latter case, the external processor could only control the bus during a
time that the CPU is halted, without destroying the program flow. Mapping the processor's memory space into
the external processor memory space is the simplest
method, but can impact programs being run on the
external processor. If the processor under test utilizes
the MULTIBUS interface (with bus arbitration), then a
processor like the iSBC-80/30™ or iSBC-86/12™ could
be used as the debug vehicle with no special hardware.
A more flexible interface that would have less Impact on
the system memory space would have the addresses for
the system under test generated from latches loaded by
the I/O instructions from the external processor. This
case must have software routines to interface to the I/O
ports and handle the desired debugging routines (see
Figure 4).
Software Testing
It is desirable to check as much of the lOP program as
possible statically, since various tools and techniques
are available which may not be usable during real-time
A-89
AP-50
Figure 3. Generalized Remote Bus Using MULTI BUS Interlace
HIGH ORDER
ADDRESS LINES
ADDRESS DATA
CNTL
BUS
BUS SIGNALS
LOW ORDER
ADDRESS
16-20 BITS
rL~IN~E=S~__~__________-,~__________~ ~
THESE BUFFERS ENABLED WHEN SYSTEM
UNDER TESrS BUFFERS DISABLED ~
DATA
------++,..oH
CNTL - - - - -......~~I
r-~M~U~L~TI~B~U~S~C~O~N~TR~O~L~L~I~N=ES~_t~------_._+~~
EX)"ERNAL PROCESSOR
SYSTEM UNDER TEST'S MEMORY IS MAPPED
INTO EXTERNAL PROcESSOR'S MEMORY.
UPPER ADDRESS' BITS CAN BE SUPPLIED
FROM 1/0 LATCH.
SYSTEM UNDER JEST
Figure 4.- External Processor Interlace
AP-SO
testing. This "static" software testing is not applicable
to heavily 1/0·dependent or DMA·dependent routines,
but Is best su Ited to longer computational or data han·
dling routines. The idea is to test the correctness of
algorithms, rather than seeing if the whole system runs.
There are two main approaches to functional software
testing. One is to essentially run the program in real
time and monitor program flow on a logic analyzer. The
difference between this and real·time testing is that pro·
gram subsections can be tested separately by using different TP (Task Pointer) starting addresses. If it is
necessary to set up certain registers or parameters in
memory, a small "setup" program can be run afterini·
tialization, which can load up registers or memory, then
jump to the program· section desired.
.
since the lOP doesn't have arithmetic or logical condition codes, the PSW is not as importanl1 as in other
machines.
The most straightforward way to pass data from the lOP
to the host processor Is through the PB (Parameter
Block) area since the PP will normally remain relatively
fixed throughout the lOP program. In order not to in·
fringe on the PB areas used by the programs, an area 18
bytes long should be allocated at the end of the PB
block to hold the register contents. Using other areas to
store the register data requires saving and reloading a
pOinter register as part of the breakpOint escape
sequence.
The data returned from the breakpoint save routine will
appear to the host processor as a sequential block of
data in the PB area. Sixteen·bit data can easily be extracted, but 20-bit pointer data will have to be
reconstructed from the move pointer (MOVP) format:
Another technique is to run the programs with break·
point routines so that one can step through code
segments and follow program execution. Software
breakpOints are usually implemented by inserting a
jump or restart to a monitor routine at the breakpOint
location. This jump or restart is machine language
dependent so, unfortunately, the existing breakpoint
routines within monitors for the 8080 or 8086 are not
applicable.
New routines tailored to the 8089 can be used, and, if
done properly, can even be used to examine programs
running on a REMOTE bus. Using breakpOints is some·
what complicated on the 8089 because the minimum instruction length Is two bytes. There is no absolute CALL
Instruction, only a relative one (which would have to
have its displacement recalculated each time it was
used). But, with a several·byte absolute jump inserted at
each place a breakpoint is desired, full breakpOint
capabilities can be obtained.
There are many ways the breakpOints can be implemented. When a breakpOint is reached, the 8089 Itself
could output the machine state to a console through its
own routines. Better suited to debugging, though,is a
system that has the 8069 place its machine state in
memory, alert the host processor, and then halt. The
host then picks up the 8069's state and can treat it in the
same way it runs its own breakpoint routines. Since the
host processor is more likely to be running a monitor or
some other kind of debugging routine (and most likely
has at least temporary console 1/0), it is the logical system to initiate and examine 8089 breakpOints. If the lOP
is running in the REMOTE mode, and the host processor
has access to the 1/0 bus via the scheme mentioned in
the hardware debugging section, then lOP programs
running on the REMOTE bus can be examined.
The breakpoint itself can consist of an escape sequence
that is used to save the TP value and jump to the save
routine, or just a jump to the save routine. This routine
saves all register contents for the channel the break·
point is in, signals the host processor, and stops the
lOP. All user programmable registers (GA, GB, GC, IX,
MC, BC, TP), as well as the pOinter tags, are accessible.
The PP (Parameter POinter) and PSW are not normally
accessible, but if the generation of the CA is such that
the lOP can send itself a CA, then by sending a CA
HALT, the PSW will appear at PP+3. Remember that
I
07
07
I I
HIGHEST
ADDRESS D1S ... D16100~
015... 08
07... 00
I
LOWEST
ADDRESS
TAG BIT
O=SYSTEM
1=1/0
Several means are available to signal the host processor
that a breakpoint has been reached. A bit could be set in
memory or an interrupt sent to the CPU. The best way,
though, is to use the BUSY flag (at CP + 1 or CP + 9).
After starting the lOP, the BUSY flag is set to FF. When
a breakpoint is reached, the lOP performs its save
routine and does either a software or CA HALT. These
result In clearing the BUSY flag, which then signals the
CPU to obtain valid breakpoint data. The CPU can then
restart the lOP by either a CA START or CA CONTINUE.
The breakpoint routine outlined above will work for a
"one·shot" test. However, to be more useful as a
general purpose debugging tool, some refinements
must be added. To keep from destroying the program
whenever a breakpoint is placed, the supervisory pro·
gram running from the host processor must save the
lOP code that Is occupied by the escape sequence.
When the breakpOint is completed and lOP execution is
to resume, the host program restores the lOP code, sets
the TP in the CB area back to where the breakpoint was
placed, and sends a CA START. Since the length of each
instruction can be easily found from bits 1-4 of the opcode, a Single stepping function can also be done.' By
the time this is implemented, the host program is
becoming a full·fledged debugging routine. Appendix 3
describes a debugging program that makes use of tlie
ideas presented here.
Breakpoint routines can be quite useful, but some
restrictions and limitations should be mentioned. The
processor examining the breakpOints must have access
to the lOP program memory, either directly, or through
lOP programs that Simulate direct access. The program
memory must be in RAM. The breakpvint must be
·The formula for length of Instructions Is: length (In bytes)
1,0=01)+ 1 (If bits 3,2=01) +2 (If bit 3= 1)+2 (If LPOI).
A-91
=2 + 1 (If bits
AP-50
placed on an Instruction boundary, and multiple breakpoints must not be placed so that they overlap. There
may be some impact on the PB area. CA generation may
have to·be different than usual. But, despite these
IImltatlons,the breakpoints offer a useful and more conventional software debugging tool than analyzers.
REAL-TIME TESTING
Running an lOP program in its final environment with
real 110 devices is the true test of dynamic operation.
The program is no longer In a static, isolated environment. The demands of DMA and multiprocessing may
reveal unplanned timing dependencies or critical section problems. There may also be. sections of hardware
or software, which couldn't be tested statically, that
may have bugs. The whole purpose of static or functional testll1g Is to dig these problems out while convenient debugging tools can be used. Since there are no
simple techniques for real-time debugging, the use of a
logic state analyzer and techniques to fully understand
the lOP's real-time operation will be emphaSized.
Multiprocessing operations and real-time asynchronous
110 requests can cause the timing complexity of the
system as a whole to rise beyond the point of complete
comprehension by an individual. It is then essential that
techniques to ensure correctness are used. These include good design methods, especially a clean, wellstructured design, as well as good testing. A thorough
test requires the attitude that the system should be
tested for failures, rather than tested for correctness. In
other words, one should try to make the system fall,
tests should be chosen that will put the worst stress on
critical timing areas.
The best way to do this Is to write a diagnostic program
that puts the CPU, lOP, and 110 devices through the
worst conceivable timing and program combinations.
Ideally, the program should be self-checking so that It
can be run without supervision, printing any data or program errors that occur, much like a memory test.
The two main real-time problem areas are insufficient
data rates or latency, and critical section problems. To
,
:
test for data rate problems, run the system clock at Its
lowest expected frequency and use memory and 110
with maximum expected wait states. Identify the
tightest program timings and try to have these sections
coincide with worst case DMA or other heavy bus utilization (see dual channel operation later). Critical section
problems can occur when two Independent processors
communicate with each other with Improper "handshaking." This can result In one processor miSSing another's
message, or even having both processors hang up,
waiting for each other to go ahead. The 8089 provides
aids to these problems, Including the TSLlnstructlon (to
implement semaphores) and .the BUSY flag. However,
any interprocessor communication (Including one channel of the lOP to the other) should be checked. Beware
of cases when one processor is running considerably
slower than the other (due to DMA overhead or chained
instruction sequences).
The techniques for real;time debugging evolve from
functional testing using a logic analyzer. For all but the
simplest systems, an analyzer Is essential, since It can
graphically show program execution and timing relationships during real-time execution. Another aid Is a
delayed oscilloscope. Triggering the scope from the
logic analyzer, the delay can be adjusted so that any
signal in the system can be monitored.
i
To facilitate the use of the logic analyzer, especially if
its memory is not very deep or when using it to trigger
a·n oscilloscope, a repetitive system can be used to continually update the display. Using a repetitive reset
helps to debug the software-hardware Interface, since
oscilloscope or logic analyzer probes can be readily
moved around the circuit to observe new signals
without manually retriggering the display. At its
Simplest, thereset to the host processor can be strobed, say every 10 ms. The processor will then provide the
two channel attentions (CAs) that are needed to Initialize the lOP. Where this isn't feasible, the CAs can be
externally forced by either a string of one-shots or a simple proc·essor with timing loops (such as a SDK-85 or
SDK-86). See Figure 5 for Initialization timing.
:-250MS_
-.;lo4CK-r-->1CK
:--IFFiRS"-RESET
I
'RESET AFTER:
. __ -:.. e,C!.Y!,E!l:lJf .l
,
,,
I
CA
:
START CH2
SEL
,
: POWER
,ON
,-
-LONGER IF WAIT STATES
Figure 5. Inillalizalion Inpul Sequence
A-92
AP-50
BUS
CYCLE
Memory protection of the lOP and system programs Is
helpful when debugging DMA operation. It Is quite easy
for runaway DMA to wipe out memory. Another precau·
tlon to avoid this problem Is to set an upper limit on the
number of bytes transferred by always specifying a byte
count termination.
X
111
IDLE STATUS
T1
F0 10
101
20·BIT ADDRESS = FF010.
T2
E [ F F FlO 1
LOWER STATUS = MEMORY DATA READ
T3
E
A A 50
111
1f1.BIT DATA RETURNED = AASO
t
F 0 10
111
ADDRESS REMAINS IN CHIP OUTPUT
LATCH AFTER END OF BUS CYCLE
T4
E
DATA NOT READY YET
UPPER STATUS INDICATES: NON·DMA. CH1
In the absence of other powerful debugging systems,
the logic analyzer has shown to be an extremely useful
tool. Because of its importance in debugging an lOP
system, some basic techniques and observations that
relate to monitoring lOP operation will be reviewed here.
The particular brand or type of analyzer used Is not too
Important, but would be desirable to have the following
features:
As mentioned earlier, on a 16·bit bus, most instructions
starting on odd addresses won't. show the first fetch,
since the internal queue is in use. It is a good idea in
that case to use only even instruction boundaries' as
trigger words. When following dual channel operation,
one should keep an eye on the upper status bits (53-56),
since 53 indicates which channel Is runnlng.(0=CH1,
1 = CH2), and 54 indicates DMA/non·DMA transfer
(0 = DMA, 1 = non·DMA) .
At least a 24·bit data width
Flexible triggering and qualification control
Display after triggering on a sequence of states
Capability for hexadecimal data display
A REVIEW OF lOP OPERATION
(With things to look out for)
When trying to get an unfamiliar system gOing for the
first time, it is too easy to stumble on apparent prob·
lems that are really just unexpected operation modes or
peculiarities of the machine. For this reason the basic
principles of lOP operation will be reviewed here with
special emphasis on possible problem areas or pitfalls
that a user might encounter when debugging a 8089 system. The topics are covered generally in the order encountered when bringing up a system. For complete
details of operation and some design examples, see the
8086 Family User's. Manual.
It is best to hook up to the address/data lines at the lOP,
as opposed to looking at the separate address and data
lines, since 39 lines would be required just to look at ad·
dress, data and status lines. The three lower status lines
should be monitored to show the type of bus cycle be·
ing run. Other lines can be connected where needed, at
places like the DRO lines, the EXT lines or other lines
related to the system.
For general purpose debugging, triggering the analyzer
on the rising edge of the lOP clock shows the most
useful data concerning bus cycles. Of course, using the
falling edge may be necessary to check certain signals,
particularly ones that are active only while the clock is
low. The following discussion is based on sampling
data on the clock's rising edge.
RESET
RESET must be active (HIGH) for at least four clocks in
order to fully initialize all Internal circuitry. On power up,
RESET should be held high for at least 50 microseconds. The chip is only ready to accept a Channel Attention (CA) one clock after RESET goes inactive.
One should be careful when setting up the triggering
for the analyzer that the desired event is what is dis·
played and not a later event with the same trigger word.
This can happen when the logic analyzer is in the repet·
itive trigger mode. It may retrigger before the system ac·
tually resets. A sequence restart feature is helpful.
The basis of following program execution and DMA on a
logic analyzer is to follow an 8089 bus cycle, which is
Identical to a 8086 and 8088 bus cycle. The following
diagram shows a typical 8089 bus cycle.
For general purpose debugging, displaying every clock
Is useful, but for quickly finding one's way around a pro·
gram, the analyzer can be qualified so that only instruc·
tion letches (status = 100 or 000), with ALE active, are
trapped. A much more compact display of execution
flow results.
ADO-1S ~ PREVIOUS ADDRESS. UPPER STATUS
XXXX
Logic Analyzer Techniques
•
•
•
•
A16-19
Note that the SEL pin is sampled on the falling edge of
the first CA after RESET to tell the 8089 whether it is a
master (0) or a slave (1) for its request/grant Circuitry. If a
master, it will assume it has the bus from the beginning.
If a slave, it will strobe the RO/GT Line to request the
bus back and will not start any bus transfers until ithas
been granted the bus. If the RO/GT line is not being
used, make sure the lOP comes up in the master mode.
Initialization
Upon the first CA after reset, a sequence of Instructions
is executed from an internal ROM. These instructions
pick up parameters and load data from the linked list
sequence (Figure 6). The instruction sequence is essentially:
MOVB SYSBUS from FFFF6
LPD System Configuration Block (SCB) from FFFF8
MOVB SOC from (SCB)
LPD Control POinter (CP) from (SCB) + 2
MOVBI "00" to CP + 1 (clears BUSY flag)
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Remember that four bytes must be fetched during an
LPD. If on a 16-blt bus, with even addressed boundaries,
only two fetches are needed. Otherwise (8-bit bus or odd
boundaries), four fetches are needed.
Even though no bus cycles are run to fetch these instructions, the CH1 Task Pointer (TP) appears on the address latches during .the short internal fetch periods.
On power up, this value Is meaningless, but If a repetitive RESET is used, the TP remains unchanged from the
end of the last program run. See Figure 6 for the start of
a typical initialization sequence as viewed on a logic
analyzer.
Bit 0 in the SYSBUS field sets the actual (or physical)
system bus width that the lOP expects. In the 8-bit
mode, only byte accesses are made, and all 8-bit data
should appear on the lower eight data lines. In the 16-bit
mode, word accesses can be made (if the address is
even), all data on even addresses appears on the lower
eight data lines, and all data at odd addresses appears
on the upper eight.
Bit 0 in the SOC field sets the physical width for the 1/0
bus. The same rules for the system bus apply here. Note
that these bits should reflect the actual hardware implementation and are not to be confused with the OMA logical widths set by the WID instruction.
The R bit (bit 1) in the SOC field is used to change the
mode of the RQ/GT circuitry. When the lOP is on the
same bus as an 8086, it is required to have the R bit be 0,
with the 8086 as the master and the 8089 as the slave.
CA
A1S-AO
FF F F
FF F F
FF F F
FF F F
EOO 0
EOO 0
FFC6
F
F
F
F
0
0
D
S3-S0
T
111
111
111
111
111
111
111
COMMENTS
Trigger ClK
I
111
101
101
111
111
111
111
111
14 {
CK
FFC6 D
FF F F 8
EF F F F
EF F F 0
EF F F F
EF F F 8
EF F F 8
EF F F 8
EF F F 8
FF F FA
EF F F F
EF F FA
111
101
101
111
111
111
111
111
111
101
101
111
When two lOPs are being used on the same bus, the
RQ/GT circuity can be put into an equal priority mode
by setting the R bit to one. A slave can only be granted
the bus if the master is doing unchained instructions or
running idle cycles. The master can request the bus
back from the slave at any time. The slave grants it if doIng unchained instructions or if it is idling. The master
and slave are put on essentially the same priority.
At the end of initialization, the "BUSY" flag of CH1 is
cleared. For systems where the 8086 is waiting for the
initialization sequence to end before giving another CA,
it can set the BUSY flag high prior to initialization. The
BUSY flag going low is a sign that the lOP is ready for
another CA. It is important to remember that the lOP will
not respond to, nor latch, a CA during an initialization
sequence.
Channel Attentions
The main system processor initiates communications
with the lOP through the Channel Attention (CA) line. As
mentioned earlier, the first CA after system RESET initializes the lOP. All subsequent CAs cause the lOP to
do a two-step process. It first fetches the Channel Control Word (CCW) from the appropriate channel at (PP) for
channel 1 or (PP + 8) for channel 2. (SEL at the time of
CA falling determines the channel for all following actions.) The lower three bits of the CCW Command Field
(CF) are examined and then cause the lOP to execute
the desired function.
Bus un-tristated
Command Field (CF)
TP to latch
FFC6 D
FF F F 6
EF F F F
EF F 01
EF F F F
EF F F 6
EF F F 6
FFC6 D
The master (8086 or 8088) can never take the.IJus away
from the slave (8089); only the slave can give back the
bus. In other words, during OMA transfers, the 8089
would not have the bus taken away. This is the only
mode compatible with the 8086 or 8088.
T1
T2
T3
T4
Address loaded to latch
Data not ready yet (nothing on bus)
SYSBUS loaded into chip (01)
Nothing on bus
After bus cycle, address remains in
latch
TP is loaded to latch. even though
fetches are from internal ROM
T1
Address to latch
T2
T3
T4
1st 2 bytes of lPD data fetched (FFFO)
Control of task block programs is accomplished
through the command field. The various CF functions
are:
CF
000 - Examine other field only and set BUSY flag
001 - Start task program in I/O space
011 - Start task program in system memory
The start command causes the following instructions
to be executed out of the internal ROM:
LOP CP from (CP)+ 2 (CH1) or + 10 (CH2)
LOP TP from (PP) (for TP in system) or
MOVB TBP from (PP) (for TBP in I/O)
MOVBI "FF" to (CP) + 1 or + 9 (set BUSY flag)
111 - HALT channel. BUSY flag cleared to "00"
110 - HALT channel. Save state of machine and
clear BUSY flag by executing:
MOVP TP to (PP)
MOVB PSW to (PP) + 3
MOVBI "00" to (PP) + 1 or + 9
2nd 2 bytes of lPD data fetched (FFFA)
6
CK
EFF FA
FFC6 D
111
111
Figure 6. Start of Initialization Sequence On a 16·Bit Bus
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The channel will HALT and the machine will continue execution on the other channel or go'to idle if
the other channel is idle.
WAITING TO GET THE BUS BY RQ/GT - If the lOP has
given the bus away via RQicrr, it won't Initiate any bus
transfers until it has the bus back. The machine will run
up to just before T1 of a bus clock cycle and will threestate its address/data and status pins until It has been
granted the bus.
101 - Continue channel. The channel Is revived
after a HALT by executing:
MOVP TP from (PP)
MOVB PSW from (PP)+3
MOVBI "FF" to (CP) + 1 or + 9
(set BUSY flag)
WAITING FOR READY - When running bus transfers,
'READY Is sampled at T3 of a busy cycle. If Inactive, the
whole chip will walt until READY goes active.
Do not do a CONTINUE after Initialization without doing
a CA START first since the (PP) register In CH1 Is used
as a temporary register (to hold SCB) and Is only correctly loaded by a CA START.
The last two cases of waiting (or"walt" states) stop the
whole chip and do not permit the other channel to run.
However, with READY Inactive or with the bus not acquired, there Is not much that can be done on the other
channel anyway. These two cases only stop the chip
when running bus cycles. Any Internal operations can
proceed without having the bus or with the system not
READY.
.
The upper 5 bits in the CCW will have affect If CF = 000
or upon a CA START. Some things to note about these
upper fields are:
• Priority Bit - If both channels are doing tasks of
the same overall priority, the tasks with the higher
priority bit will run_ If the priority bits are the same,
execution will alternate between the two channels.
• BLL Bit (Bus Load Limit) - Keeps nonchalned Instructions from occurring more often than once
every 128 clocks. However, channel attention or termination cycles, even on the other channel, may
disrupt the exact time Interval to the next
instruction.
Note the difference between when the chip Is HALTed
when using RQ/GT and an external arbiter (8289) for
bus arbitration. Not having the bus due to RQ/GT will
inhibit the bus cycle from even starting. Since the 8289
stops the chip by forcing AEN inactive, which goes
through the 8284 clock generator to force READY inactive to the lOP (or 8086/8088), a bus cycle has already
been started, with ALE asserted, and the address on the
address/data lines. When the bus Is obtained, operation
proceeds at T3 of the bus cycle.
It should be noted that the setting or clearing of the
BUSY flag occurs after the loading ,or storing of
registers, so that In a system where the main CPU uses
the BUSY flag as a form of semaphore to tell when the
lOP Is truly finished, there is no danger that the SCB,
CP, PP or TP could be changed before the lOP loads
them.
As 'will be mentioned later, many invalid opcodes will
cause the machine to hang up. In these cases the
address/data lines will point to where the bad opcode
was fetched.
Also since DMA termination cycles and chained instruction execution have a higher priority than CA, it Is possible for CA to be "shut-out" by these higher priorities
runn'lng on· the other channel. However,. since CA is
always latched (except during initialization), it won't be
forgotten.
Although optimized for fast and flexible DMA operation,
the lOP Is also a full-fledged microprocessor. The 8086
Family User's Manual deals with programming
strategies and other details. Some of the things to be
noted during debugging will be mentioned here.
Task Execullon
Instruction Fetching
Unlike the 8085 (but like the 8086), the 8089 labels all
fetches from the instruction stream, whether OPCODE,
offset, displacement, or literal data, as an instruction
fetch on the status lines. In some cases, such as MOV
R,I and ADD R,I, the instruction fetch time greatly exceeds execution time because literals are treated as Instruction fetches. When following programs on a logic
analyzer, triggering on status = 100 or 000 (Instruction
fetch) and a known program address is the'handiest way
to trace the flow of the program.
How Can a Channel be Halted?
Sometimes a channel may stop its operation 'unexpectedly. To see what could cause this, and to show the
impact of halting a channel, the various ways of stopping a channel are explained:
HALTED CHANNEL - If the channel has never started
after Initialization, If It has received a CA HALT command or a software HALT, channel operation Is suspended. If the other channel can run, it will, otherwise
idle cycles will run. Only a CA START or CONTINUE can
resume operation.
'
,
WAITING FOR A DMA REQUEST - If the channel Is in a
source or destination synchronized DMA transfer mode,
it will wait until DRQ is active before running its synchronized transfer. To minimize the impact on .the
overall throughput of the chip, the other channel can run
during these DRQ wait periods.
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When running programs on a 16-blt bus, a 1-byte queue
register comes into play, saving the upper byte fetched
from the last Instruction fetch, If not used by the
previous instruction. This reduces fetch time and bus
utilization since the odd byte doesn't need to be fetched
again. An internal four-clock cycle fetches data from the
queue. Like the Internal ROM fetches,. the task pOinter is
put out on the address/data lines, but no bus cycle is run.
AP-50
The queue can have some possible unexpected affects
that have to be taken into account during debugging.
These apply only to 16·bit systems and are:
• GG - The only thing that affects instructions in the
CC register is the chaining bit. If chaining doesn't
matter (if only one channel is being used without
channel attentions, for example), then. the CC register can be general purpose. However, for portability of programs, it is strongly suggested not to use
the CC register except for altering DMA parameters
and chaining.
1. Instructions that start on odd boundaries will not
likely have bus cycles run to fetch the odd byte
unless jumped to, unless preceded by LPDI (which
clears the queue), or an instruction that modifies the
task pOinter is executed. The latter causes the queue
to be cleared so that part of..an old instruction won't
become part of the new one.
• MG - Is a general purpose 16-bit register, but is
also used to do a masked comparison either for
DMA search/match termination or for the JMCE and
JMCNE instructio'ns.
2. There is a queue register for each channel so loading
or.clearing the queue on one channel has no affect on
the other channel's queue.
• BG, IX, - Both general purpose 16-bit registers. In
instructions that reference memory using the AA
field, if AA 11, the IX register is incremented by
the number of bytes fetched or stored.
3. The second word of immediate data fetched by a
LPDI is done during a pseudo-Instruction fetch cycle
that cannot make use of the queue or already fetched
data. Thus, if on an odd boundary; fetching an LPDI
will be byte, word, byte, byte, byte, and the queue will
not be loaded.
=
• Pointer Registers (GA, GB, GG and TP) - Are,20-bit
registers, but can also be used as 16-bit registers.
Adds will carry into the upper 4 bits, but other
operations (CaMP, OR, AND) are done only on the
lower 16 bits. Note that when used as pOinters to
system memory, it is possible to add a large 16-blt
number to the pOinter and to put the pOinter Into
another 64K block of memory.
When Can the Other Channel Interrupt Inst.ructlon
Execution?
This will be explained more In the "dual channel" operation section" but a few pOints will be mentioned here. All
instructions are made up of internal cycles, with each
cycle composed of two to eight clocks. Each bus cycle
is one internal cycle, but there can be internal cycles
with no comunications to outside the chip. Internal
cycles Will be extended by the number of wait states in
each bus cycle. Between any of these cycles, DMA from
the other channel can intervene if the priorities permit it.
Instruction fetching and execution can only interrupt instructions on the other channel when the instruction
has been completed, not between internal cycles.
Sign Extension
Registers
All the registers have some special purpose use in the
.Instruction Execution or DMA, but all except the CC
register can be used as general purpose registers during
instruction sequences. A few are loaded specially:
Is only loaded during an initialization sequence. There is one CP register that handles both
channels. (All others are duplicated, one set for
each channel.)
All program data brought into the chip, either literals or
displacements in opcodes, or program data fetched
from memory, is sign·extended. Offsets used for
calculating addresses are not sign extended. Any 8-blt
data brought in has bit 7 sign-extended up to bit 19.
Sixteen-bit data is sign-extended from bit 15 to bit 19.1t
is important to note this, because it can affect logical
operations. For example, if one wanted to, OR 0084H
with 1234H, in register GC, you couldn't do ORBI GC,
84H, because bit 7 would sign-extend into the upper
byte. Instead, you should code ORI, 0084H to do this
properly (note that this has a word for the immediate
data). The non-ADD operations will cause the upper four
bits of the pOinter registers to be invalid since the upper
four bits of the ALU come only from the adder.
Tags
• GP -
• PP - Is only properly loaded during a CA START
command. It holds the SCB value after the initialization sequence.
• TP - This is included as part of the registers in the
RRR field, but cannot be operated on unless you
plan on having your program execution jump
around. Every time this is operated on, the queue is
cleared. The TP is loaded from two words (address
and displacement) on a CA START, LPD, or LPDI,
and loaded from 3-byte MOVP format (see illustration on page 5) on Ii CA CONTINUE, and can be op. erated on using any register oriented instructions.
The following registers are loaded during program execution, but can have special effects:
It should be noted that the way the lOP knows which
bus to access (system or 110) is via the Tag bit associ.ated with the pOinter register used. The TAG can only be
set in these ways: loading as a 16-bit register (MOV R,M,
MOV R,I) sets TAG to 110 space, loading as a pointer
(LPD, LPDI) sets TAG to a system space), or bringing the
TAG in from memory by a MOVP instruction .
Effects of Invalid Opcodes
The upper 6 bits of the, 2-btye opcode actually determine
which opcode will be executed. If these bits are a valid
opcode, but lower bits are invalid, the chances are good
that the bad bits will be ignored. But if the upper six bits
are invalid, there is a very good chance that the chip will
hang up and stop execution in that channel. The only
way to get out of this mode is to reset the chip. If this
hang-up occurs, it can usually be traced because the
last address of the instruction fetch will still be on the
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AP-50
address/data lines, showing where the program went
astray.
Going from Instruction Execution Into DMA
The XFER instruction places the current channel into
the OMA mode after the next Instruction. This permits
one last Instruction to star! up an I/O device (start CRT
display on an 8275, for example). However, in order for
the lOP to get setup for OMA, the GA, GB, and CC
registers should not be altered during this last Instruction. Failure to observe this will probably result In an
Improper first OMA fetch. The WID Instruction can be
placed after XFER.
DMA Transfers
Incrementing/Non-Incrementing pointers
A memory or I/O pointer can be made to Increment for
each byte transferred during OMA or It can remain fixed.
Incrementing Is used primarily for memory block
transfers, and non-Incrementing Is used to access I/O
ports.
B/W Mode
Each OMA transfer is composed of separate fetch and
store cycles so that 8/16-bit data can be assembled and
disassembled, and translation and termination may also
be easily handled. There are four possible trimsfers or
B/W modes. They are:
B - B-1 byte fetched, 1 byte stored
B/B - W - 2 bytes fetched, 1 word stored
W - B/B - 1 word fetched, 2 bytes stored
W - W ...:... 1 word fetched, 1 word stored
The BIW mode used depends on the logical bus width
(selected by the WID Instruction), address boundary,
and incrementing mode.
All systems with 8-blt physical buses will run in the B/B
mode. On 16-bit physical buses the other modes are
possible, depending on the logical widths selected.
Note that the logical bus width can be different than the
physical bus width since there are cases where an 8-blt
peripheral may be used on a 16-blt bus. The selection of
the logical width, and not the physical width, is what
determines the BIW mode. Thus it is the responsibility
of the programmer not to program an invalid combination (I.e., don't specify a 16-bit logical width on an 8-blt
physical bus).
Any transfer on an odd boundary will be B/B but if the
pOinter is Incrementing and on a 16-bit logical bus, after
the first transfer, the pOinter will be on an even boundary. The lOP will then try to maintain word transfers in
order to transfer data aseffeciently as possible. See the
user's manual for detalls~ The change in B/W mode occurs only after the first transfer or, as explained In the
termination section, upon certain byte count terminations.
Synchronlzafion .
In the unsynchronzied mode, transfers occur as fast as
priorities will allow. This is the lOP's "block-move"
mode. Most I/O peripherals only want a OMA transfer on
demand; the ORa .lines, along with synchronization
specified, will handle this need. Source synchronization
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Is used for I/O reads and destination synchronization Is
used for I/O writes.
If the lOP Is waiting for a OMA request, It will run programs or OMA on the other channel, or execute Idle
cycles If nothing Is pending. If running Idle cycles when
the ORa comes, the transfer starts five clocks after
ORa Is recognized. If running OMA or Instructions. on
the other channel, the ORa cannot be serviced until the
current Internal cycle Is done, and may require a maxImum of 12 clocks (without bus arbitration or walt
states).
Consecutive ORa-synchronized OMA transfers on the
same channel are separated by four Idle clocks (assuming no other delays) by an internal sampling mechanism.
This happens between the 2-byte fetches on sourcesynchronized B/B-W cycles, and between the two stores
on destination-synchronized W-B/B cycles. This delay
between consecutive OMA cycles allows adequate time
for proper acknowledgement of the current OMA request before the next request is processed. On
destination-synchronized OMA, this isn't a problem, but
on source-synchronized OMA, there will be four extra
clocks per transfer. Unless one is running right at the
speed limit, this won't be a problem. Near the maximum
data rate, unsynchronized transfers can be used, with
synchronization done by manipulating the READY line.
Translafe Mode
When the translate bit Is set, the data fetched during
OMA will be added to the GC register. This new pointer
will in turn be used to fetch, via a seven clock extra fetch
cycle, new data, which will then be stored. Translate Is
only defined for byte transfers. The bytes are added to
GC as a positive offset, so a lookup table for translating
data can be a maximum of 256 bytes long. Even If the
data to be translated falls within a smaller range (such
as ASCII code), a full 256-byte lookup table Is recommended so that erroneous data can be flagged and controlled.
Translate can be run on any of the B/B transfer modes,
so Jt Is useful for doing block translation within program
execution as well as translation directly to or from an I/O
port.
DMA Termination
One of the powerful features of the lOP Is Its varied
OMA termination conditions and their close tie-In with
resuming histruction Block programs. However, because of the multitude of OMA modes, care must be
taken in predicting the exact termination parameters.
Various things to be careful about will be outlined here.
Byte Count (BC) Termination
The BC register Is decremented for every byte transferred whether or not BC termination Is set. If Be termination Is set, the last transfer done Is the one that
results In BC being zero. To avoid the problem of missIng Be = 0 on word transfers, If Be Is odd between every
transfer, the lOP detects when Be Is 1, and forces the
last transfer to be In the B/B mode. Since both the fetch
and store cycles are complete, the source and destination pOinters point exactly to the next byte or word that
would have been fetched.
Ap·50
Masked Compare (MC) Termination
An MC termination occurs when a pattern matches (or
doesn't match, depending on mode selected) the lower
half of the MC register (the match pattern) with only the
bits that are enabled by the upper half of MC (the mask
pattern) contributing to a match. Thus the masked bits
can be "don't cares" in both the data byte and the match
byte.
In orderto preventan invalid signal level from becoming
trapped from the asynchronous EXT term lines, two
clocks of delay and signal conditioning are done on
these lines. In addition, a termination cycle can only be
started at certain times during OMA (or TB on the other
channel - see dual channel operation section). The EXT
terminate lines should be valid eight clocks before the
.
start of the OMA cycle to be stopped.
The masked comparison is only done onstore (deposit)
cycles. Any bytes transferred (in BIB or W-B/B mode) will
be compared. But, since the MC comparison is done on
only one byte, any words stored (W-W or B-B/W) have
only their lower byte compared. This may be fine, but if
not, make the destination logical width 8 bits.
EXT is sampled even when the lOP is running something
on the other channel. Remember though, that despite
the high priority of termination, the current instruction
on the other channel has to finish before the termination
cycle is run. Simultaneous EXTs on both channels result
in CH1 termination being done first.
Just like BC termination, the pointers will point to the
next data to be transferred. The BC will also be decremented correctly, except if the termination occurs on
the first byte of a W-B/B transfer. In this case the BC will
be decremented as if the entire transfer (both bytes) had
taken place.
In order to have enough time to process a byte count termination, the BC register is always decremented during
OMA fetch cycles. Because of this, external or MC terminations that occur during W-B/B cycles will result in
the byte count always being decremented by two, even
if only one byte is stored. This also occurs in the blockto-block or block-to-port B/B-W modes: To find the exact
number of bytes transferred, the source pointer address
can be checked in the block-to-port and block-to-block
modes during B/B-W cycles and in the block-to-port
W-B/B mode. The destination pointer address can be
used to find the number of bytes transferred in the portto-block and block-to-block modes during W-B/B cycles.
The store cycle that causes an. MC termination will be
lengthened by two extra clocks (or. by one extra clock if
there are, wait states), to allow time to set up the termlnationcycle.
Termination Cycles and Multiple Terminations
MASK PATTERN - - - - - '
MATCH
Figure 7. Masked Compare Logic for l·BIt
External (EXT) Termination
External termination allows the 1/0 device or controller
to use its own conditions to generate a termination.
Basically, the lOP will halt OMA as soon as it recognizes
an EXT terminate, even if a transfer is only partially complete. There might be concern that multi byte cycles
(W-B/B or B/B-W) might have data lost if an EXTterminate stopped the store cycle. In unsynchronized OMA
this would happen, but this mode is typically not used
with 1/0 controllers that could generate. external terminations. In synchronized OMA modes, it is assumed
that the I/O controller will only do a ORO for valid data
transferred, and that it won't give an EXT terminate with
its ORO active. In destination synchronization, the
possible problem occurs In the W-B/Bmode, where EXT
terminate comes after the first store but before the second. This is fine, since even though data was overfetched,the proper amount was actually transferred. in
source synchronization, the B/B-W mode raises problems since if an EXT terminate came after the first byte
fetched and before the second byte fetched, normally
no store cycles wouldbe done at all, thus losing the first
byte fetched. In this case (i.e., source synced, ORO inactive, and 1 byte already fetched), a single byte store
cycle is run before the termination'cycle, ensuring data
integrity.
Upon termination, the user can run different task block
programs, depending on which type of termination has
occurred, by specifying an appropriate termination offset. That is, instruction fetching will begin after a
termination cycle starting at either the TP value before
the OMA started, TP + 4 or TP + 8. These offsets permit
long or short jumps to termination routines.
The termination cycle is an add immediate instruction
that runs from the internal ROM and adds the proper offsetto the TP. It is 15 clocks long for TP + 4 and TP + 8
termination and 12 clocks long for TP+ 0 termination.
As mentioned earlier, EXT terminate must come a certain time before the end of a .transfer to ensure that the
next transfer. doesn't start. If it comes in time and MC
termination. also occurs on the current transfer, then the
termination cycle with the largest offset. is run. A
simultaneous BC terminate cycle will have priority over
Me and will result in the running the BC termination
program.
Priorities/Dual Channel Operation
The lOP can share its internal and external hardware
between two separate channels. The user sees two
identical lOP channels with all registers, machine flags,
etc., independent of the other channel. The only register
in common is the CP register, loaded by the initialization sequence. The mechanism for achieving dual channel operation is time multiplexing between the two
channels.
Since interleaving two channels afiects their response
time to external events and since interfacing to these
events is the prime purpose ofthelOP, sev.eral means of
adjusting the priorities of the channels are provided.
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Before gOing into the priority algorithms in detail the
four types of cycles that are affected by the priorities
will be outlined:
channel goes idle. Chaining will also lock out normal Instructions on the other channel. Chaining should thus
be used with care.
1. DMA Cycles - Any type of DMA transfer cycle,
including Single transfers and translate cycl.es. DMA
can be interrupted after any bus transfer by the other
. channel.
In order to reduce the possibility of shutting out channel
attentions, an exception is made to the above priority
scheme. After every DMA transfer, whether synchronized or unsynchronlzed, the lOP will service any pending CA. However, chained task block execution will still
shut out CAs on the other channel.
2. Instruction Cycles - Any instructions that have
been fetched out of I/O or system memory. Instruction cycles are made up of internal cycles, each two
to eight clocks long (assuming no wait states). Some
cycles may not run bus transfers. Instructions can be
interrupted by DMA after anyone of the internal
cycles, but can only be interrupted by instructions on
the other channel (normal ones or ones from internal
ROM) after the current instruction is completed.
3. Termination Cycle - Performed when DMA transfers
end and instructions resume (except on single
transfers).
4. Channel Attention Cycles - Performed when channel attention is given, performs actions specified in
the CCW field. Both termination and CA cycles can
be interrupted by DMA after any internal cycle, but
can only be interrupted by instruction cycles after
the complete sequence of internal cycles is done.
Termination and channel attention cycles as well as the
initialization cycle (which never runs concurrently with
other operations) are sequences of instructions fetched
from an internal ROM.
Recognizing the higher importance in doing DMA, termination and (to a lesser extent) CA cycles, the following priority scheme is built into the lOP. Any channel
that has a higher-priority operation will run continuously
until done. If both channels are running the same priority, execution will alternate between them_
Highest Priority
1.
2.
3.
4.
DMA transfers, termination, chained instructions
Channel attention cycles
Instruction cycles
Idle cycles
Lowes t Priority
Two ways exist to alter the priority scheme. One way is
to utilize the priority bits for each channel. If one is
greater than the other; that channel will run at the expense of the other if both channels are otherwise running at the same priority. Thus the P bit only has effect
on channels running at the same priority level.
If one wants to run instructions along with or in place of
DMA on the other channel, the other technique is to set
the chaining bit (in the CC register) which brings the
instruction priority up to the level of DMA. Care should
be taken with this since now CAs are at a lower priority
than instructions and will not be serviced unless that
What is the importance of priorities? Well, as an
example, let's say that we are running long periods of
non-time-critical block moves (via DMA) on one channel
and running short bursts of DMA that must be serviced
promptly on the other channel. With the default
priorities, the short DMA channel bursts would be interleaved with the longer DMA, reducing the maximum
transfer rate for both channels. If, however, the priority
bit was one on the burst mode DMA and zero on the
other, the bursts would be serviced continuously at the
fastest possible data rate.
An even more critical case would be the same low priority, long DMA transfers on one channel with DMA on the
other channel that must terminate, run a short Instruction sequence, and resume DMA again within a short,
fixed time. (This might be the case in running a CRT display with linked list processing between lines.) Normally, the low priority, long DMA could indefinitely block
the short TB sequence. By setting the high-priority channel's priority bit to one and putting it into the chained
instruction mode, the low priority channel would stop
its DMA entirely so that the terminationlinstructlon sequeneJe could run.
When establishing the priorities to be run, care should
be taken that both channels will run successfully under
a worst case combination. This can be tricky when the
channels are running asynchronously with fast data
rates andlor short latencies, but must be taken into account. Of course, running only one channel on the lOP is
an easy solution, but if more than one lOP is being used
in the system, the priorities and delays of the bus arbitration used (either RQ/GT or an 8289 bus arbiter) must
be taken into account. It may be found that the on-chip
arbitration between the two channels is faster and more
powerful than external arbitration.
SUMMARY
It is hoped that the material presented here will aid
those who are putting together and debugging an 8089
lOP system, and help them in understanding the operation of the lOP. Many of the debugging techniques
should be familiar to those who have worked with microand minicomputer systems before. Other debugging
techniques not mentioned here, which work well with
microprocessor systems, could be just as applicable to
the 8089. The unique nature of the lOP among LSI
devices warrants special consideration for its 110 functions and multiprocessor capabilities.
A-99
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The breakpoint routine uses a simple jump to a save
routine. The PUM-86 supervisory or control program
handles the placement of the jump within the users program. Since it can not normally access the remote bus,
all lOP programs to be tested must run out of system
memory.
Appendix'i
CHECKLIST OF POSSIBLE PROBLEMS
HARDWARE PROBLEMS
• Is RESET at least four clocks long?
• Are both Vss lines connected to ground?
• Does the first CA falling edge come at least two clocks
after RESET goes away?
• Does the second CA come at least 150 clocks (16-bit
system, no wait states) after the first CA?
• Is, READY correctly synchronized and gated by
local/system bus lines?
• Is SEL correct for first CA so that lOP comes up correctly as master or slave?
• If two lOPs are local t6 each other, is a 2.7K pull-up resistor used on RQ/GT?
SOFTWARE PROBLEMS
• Are the initialization parameters in the initialization
linked-list correct?
• Is BUSY flag being properly tested by host CPU software before modifying PB or providing a new command?
• Has the chaining, translate, or lock bit in the CC
register been erroneously set?
• Have DMA termination conditions been met? The lOP
could be trying to do endless DMA.
When the control program starts, It assumes the 10P,has
just been reset. It then prompts the user for the CP
and PP values. After this, it sends the first (initialization)
channel attention. It then asks the user for the channel
to be run, and the starting and stopping addresses. After
the stopping address has been entered, a Channel Attention Start is given. If the breakpoint is reached, a
HALT is executed, and the control program prints the
register contents. If the breakpoint hasn't been reached,
the user can type any character, and a Channel Attention Halt will be sent to the lOP. If the lOP responds
within 50 ms, the TP where it was halted is printed.
Otherwise, the control program issues ,an error
message. If, at any time, the user wants to get out of the
program, typing an ESC will pass control back to the
SDK·86 monitor. Figure 9 shows the flow of the control
program.
Note that, unlike a single CPU debugging routine, having the 8086 supervise the 8089 enables a clean exit
from crashed lOP programs. The program code where
jumps had been placed are always restored. The control
program is a good example of how the power of dual
processors can be put to good advantage.
Comments within the control program indicate
parameters that need to be changed to run on different
systems. It should be noted that channel attentions are
invoked by the recommended method of using an I/O
write to a port to generate CA and using AO for SEL.
Source and object files of. this program are available
through Intel's INSITE™ User's Program Library as program 8089 Break. 89 (number AD6).
Appendix II
BREAKPOINT ROUTINE
AND
CONTROL PROGRAM
MASTER DATA STORAGE LOCATIONS:
The debugging program described here is an example of
the kind of software development tool that can be
developed for the 8089 lOP. It was written to tryout
various breakpoint schemes, and has been used to
debug an engineering application test system. The program is not meant to be the ultimate debugging tool, but
is an example of what can be put together to utilize the
breakpoint routine described earlier in the application
note.
The debugging program was tested on ,a B086·based
system that emulates the SDK-86 I/O structure, and uses
the SDK-86 serial monitor. This enables it to use the
SDK-86 Serial Downloader to interface to an
Intellec@ development system on which: the software
was created. The 8086 system is interfaced via a
MULTIBUS™ Interface to an lOP running in the REMOTE
mode. The remote bus access technique, mentioned
earlier In this note, Is implemented on this system, but
was not used in the software debugging program.
TP
GA
=l
-
PP+239
r"
GA
GB
PP + 242
GB
GC
GC
BC
IX
CC
MC
INCREASING
ADDRESS
PP
TP
-
~ PP + 245
PP+ 248
i - PP + 250
t=
PP+252
PP+254
Figura 8. Breakpoint Routine to Run 8089 Program out of System
Memory
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NO
LOAD PP
WITH STARTING
POINT,
BUSY FLAG
WITH OFFH
Figure 9. Breakpoint Routine to Run 8089 Program out of System Memory
A-lOl
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PL/M-86 COMPILER
8089 BREAKPOINT ROUTINE
PAGE
ISIS-I I PLlM··86 Xl03 COMPILATION OF MODULE BREAKPOINT
OBJECT MODULE PLACED IN BREAK.OBJ
COMPILER INVOKED BY,
,F1; PLM86 BREAK. SRC PAGEWIDTH (100)
$TITLE ('8089 BREAKPOINT ROUTINE')
8089 BREAK POINT PROCEDURE
WRITTEN BY DAVE FERGUSON 2/2/79
INTEL CORPORATION
REV 2
8/14179
....... *1
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8
9
10
11
BRE:AK$POINT,
DO,
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
I BYTE,
SAVECODE (4) WORD, I*BUFFER FOR STORAGE*I
ONEPP POINTER, 1* CHAN ONE PP *1
TWOPP POINTER, 1* CHAN TWO PP *1
STARTBYTES (4) BYTE, 1* BUFFER FOR START ADDRESS *1
DECLARE
DECLARE
DECLARE
DECLARE
STARTPOINTER POINTER, 1* POINTER FOR START ADDR. *1
ENDPOINTER POINTER, 1* POINTER FOR END ADDR. *1
PRESENT POINTER AT (@INPNTR), 1* POINTER BUFFER *1
TRUE LITERALLY 'OFFH', FALSE LITERALLY '~O~H',
1* YOU MUST CONFIGURE YOUR 1/0 STRUCTURE AND
SYSTEM TO MATCH THE PROGRAM OR VISA VERSA *1
DECLARE CRT STATUS LITERALLY '0F,FF2H', 1* 8251 STATUS PORT *1
CRTDATA LITERALLY 'OFFFOH', 1* 8251 DATA PORTS *1
CHANATTEN LITERALLY 'OFAH', 1* CHANNEL ONE CHANNEL ATTENTION PORT *1
1* CHANNEL TWO CHANNEL ATTENTION PORT = CHANATTEN + 1 *1
CHANNELONE LITERALLY 'OOH',
CHANNEL TWO LITERALLY 'OIH',
1* ASC II IS A STR ING OF HEX CHARACHTERS IN ASCII FORM.; *1
ASCII (*) BYTE DATA ('0123456789ABCDEF'),
TITLE$STRING (*) BYTE DATA WAH,ODH, '8089 BREAKPOINT VER 1. 0',
OAH,ODH, 'TYPE ESCAPE TO RETURN TO MONITOR. "
OAH, bDH, 0),
CHANGIVEN (*) BYTE DATA ('CHANNEL ATTENTION GIVEN TYPE ANY KEY TO ABORT. '
,DAH, ODH, 0>,
IlKREACHED (*) BYTE DATA WAH,ODH, 'BREAKPOINT REACHED', OAH, ODH, 0),
GETCP (*) BYTE DATA (' INPUT CP IN HEX', OAH, ODH, 00),
GET$PP (*) BYTE DATA ('INPUT PP IN HEX FOR ',OOH),
GETSTART (*) BYTE DATA (OAH, ODH, 'INPUT STARTING ADDRESS IN HEX', OAH, ODH, OOH),
STOPADDR (*) IlYTE DATA ('INPUT END ADDRESS IN HEX',OAH,ODH,OOH),
CHANNUMIlER (*) BYTE DATA (OAH,ODH, 'CHANNEL ONE OR TWO? ',DOH),
ABORT (*) IlYTE DATA (' FATAL ERROR - lOP DOES NOT RESPOND TO CHANNEL',
, ATTENTION. RE-INITIALIZE SYSTEM ',0),
ABORTAT (*) BYTE DATA (' TP WAS ',0),
ONE (*) BYTE DATA (' CHANNEL ONE',OAH,ODH,OOH),
TWO (*) BYTE DATA (' CHANNEL TWO',OAH, ODH, OOH),
GASTRING (*) BYTE DATA ('GA = ',OOH),
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PAGE
8089 BREAKPOINT ROUTINE
GBSTRING (*) BYTE DATA ('GB = ',OOH),
GCSTRING (*) BYTE DATA ('GC = '.OH).
BCSTRING (*) BYTE DATA .(OAH,ODH. 'BC = ',OOH),
IXSTRING (*) BYTE DATA (OAH,ODH. 'IX
'.OOH).
CCSTRING (*) BYTE DATA (OAH.ODH. 'CC
'. OOH).
MCSTRING (*) BYTE DATA (OAH.ODH. 'MC, = '.OOH)
12
13
DECLARE CHAR BYTE,
DECLARE ONETWO BYTE,
1* SDKMON IS A PLM TECHNIQUE USED TO FORCE THE CPU INTO AN
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2
2
INTERUPT LEVEL 3.
IN ORDER TO USE THIS THE PROGRAM MUST
BE COMPIL.ED (LARGE), *1
SDKMON:
PROCEOURE.
DECLARE HERE (*) BYTE OATA (OCCH).
1* THIS IS AN INT.
3 *1
WHERE WORD DATA(.HERE),
CAL.L WHERE,
END,
1* CO SENDS A CHAR TO THE CONSOLE WHEN READY *1
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2
2
2
1* CI GETS A CHARACHTER FROM THE USER VIA THE SERIAL PORT *1
1.* CI AUTOMATICALLY ECHOS THE CHARACHTER TO THE USER CONSOLE *1
DECLARE ~SCAPE LITERALLY '1BH'.
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1* THIS ROUTINE IS WRI·TTEN TO RUN VIA THE SERIAL
PORT OF AN SDK86 *1
CO:
PROCEDURE (C),
DECLARE C BYTE,
DO WHILE (INPUT(CRTSTATUS) AND 01H)
0, END,
OUTPUT (CRTDATA) = C,
END.
1
2
2
2
2
2
2
CI: PROCEDURE BYTE,
DO WHILE (INPUT(CRTSSTATUS) AND 02H) = 0, END,
CHAR = INPUT (CRTDATA) AND 07FH.
CALL CO ( CHAR) •
IF CHAR = ESCAPE THEN CALL SDKMON, 1* GO TO SDK MONITOR *1
RETURN CHAR,
END.
1* VALIDHEX CHECKS THE VALIDITY OF A BYTE AS A HEX CHARACHTER*I
1* THE PROCEDURE RETURNS TRUE IF VALID FALSE IF NOT *1
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3
2
2
VALIDHEX:
PROCEDURE (H) BYTE,
DECLARE H BYTE,
DO 1=0 TO LAST(ASCII),
IF H=ASCII(I) THEN RETURN TRUE.
END,
RETURN FALSE,
END,
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PL/M-86 COMPILER
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2
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2
8089 BREAKPOINT ROUTINE
PAGE
1* HEXCONV CONVERTS A HEX CHARACTER TO BINARY FOR MACHINE USE.
IF THE CHARACTER IS NOT A VALID HEX CHAR. THE PROCEDURE RETURNS
THE VALUE OFFH *1
HEXCONV:
PROCEDURE (OAT) BYTE;
DECLARE OAT BYTE;
IF VALIDHEX(DAT) <> OFFH THEN RETURN TRUE;
DO 1=0 TO LAST(ASCII);
IF OAT = ASCII(I) THEN RETURN I;
END;
END;
1* HEXOUT'WILL CONVERT A VALUE OF TYPE BYTE TO AN ASCII STRING
AND SEND IT TO THE CONSOLE *1
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2
2
HEXOUT:
PROCEDURE (C);
DECLARE C BYTE;
CALL CO(ASCII(SHR(C.4) AND OFH»;
CALL CO(ASCII (C AND OFH»;
END;
2
2
2
2
1* WORDOUT CONVERTS A VALUE OF TYPE WORD TO AN ASCII STRING
AND SENDS IT TO THE CONSOLE *1
WORDOUT:
PROCEDURE (W);
DECLARE W WORD;
CALL HEXOUT(HIGH(W»;
CALL HEXUUT(LOW(W»;
END;
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1* GET ADDRESS 15 A PROCEDURE TO GET AN ADDRESS FROM THE CONSOLE.
THIS PROCEDURE WILL ONLY CONSIDER THE LAST 5 CHARACHTERS ENTERED
*1
DECLARE INPNTR (4) BYTE;
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2
2
2
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2
GETSADDRESS:
PROCEDURE POINTER;
DECLAR" BUFF BYTE;
I*CLEAR ALL VALUES TO ZERO *1
INPNTR (0)
0;
INPNTR ( 1 )
0;
INPNTR
(2)
0;
INPNTR(3)
0;
BUFF ~ 0;
DO WHILE BUFF () TRUE;
1* THIS SEQUENCE OF SHIFTS ALLOW THE USER TO TYPE IN FIVE
DR MORE CHARACHTERS TO BECOME THE ACTUAL POINTER FOR 8089
DR 8086. THIS PROCEDURE RETURNS THE LAST FIVE IN PROPER
SEQUENCE STORED IN INPNTR(0-3).
THE STORAGE
IS AS FOLLOWS:
1. THE LAST CHARACTER INPUT GOES INTO
THE LOW FOUR BITS OF INPNTR(O).
2. THE NEXT TO LAST CHARACTER GOES INTO
THE LOW FOUR BITS OF INPNTR(2).
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8089 BREAKPOINT ROUTINE
PL/M-86 COMPILER
3. THE THIRD CHARACTER INPUT GOES INTO
THE HIGH FOUR BITS OF INPNTR(2)
4. THE SECOND CHARACHTER INPUT GOES INTO
THE LOW FOUR BITS OF INPNTR(3)
5. THE FIRST CHARACTER INPUT GOES INTO
THE UPPER FOUR BITS OF INPNTR(3).
THE 86 SHIFTS INPNTR (2,AND3) LEFT FOUR BITS AND ADDS THIS TO
INPNTR(O) RESULTING IN THE ADDRESS THE USER TYPED IN. *1
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3
3
3
3
3
2
2
2
2
INPNTR(3) ~ '(SHL(INPNTR(3),4) OR (SHR( INPNTR(2),4) AND OFH»,
INPNTR(2) ~ (SHL(INPNTR(2),4) OR (INPNTR(O) AND OFH»,
INPNTR(O) ~ BUFF,
BUFF ~ CI,
BUFF ~ HEXCONV(BUFF),
END,
CALL CO(OAH), I*LINE FEED TO CRT*I
CALL CO(ODH), I*CARRIAGE RET TO CRT*I
RETURN PRESENT, 1* PRESENT IS A POINTER TO THE ARRAY INPNTR. *1
END,
1* STRINGOUT IS A PROCEDURE TO SEND THE CONSOLE AN ASCII STRING
ENDING IN THE VALUE 00. STRINGOUT NEEDS A VALUE OF TYPE POINTER
*1
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2
STR I NG$OUT:
PROCEDURE (PTR ),
DECLARE PTR POINTER,STR BASED PTR (1) BYTE,
I
0,
~
DO WHILE STR(I) <> 0,
CALL CO(STR(I»,
I
~
I + 1,
END,
END,
88
DECLARE TAGIS (*) BYTE DATA (' OPERATING IN ',0),
TAGISONE (*) BYTE DATA ('10 SPACE',OAH,ODH, 0),
TAGISZERO (*) BYTE DATA ('SYSTEM SPACE',OAH,ODH,O),
1* TAGTEST TESTS THE TAG BIT AND SENDS A MESSAGE TO THE CONSOLE
THE TAG IS LOCATED IN BIT THREE. A TAG BIT OF ONE MEANS THE
POINTER IS TO lID SPACE, AND A TAG BIT OF ZERO MEANS THE
POINTER IS TO SYSTEM SPACE *1
1* THE CALLER MUST DECIDE WHICH BYTE HAS THE TAG AND PASS IT TO TAGTEST *1
89
TAGTEST:
PROCEDURE (TEST),
DECLARE TEST BYTE,
CALL STRINGOUT(@TAGIS),
IF (TEST AND 01000B) <> 0
THEN
DO,
CALL STRINGOUT(@TAGISONE),
END,
ELSE
DO,
CALL STRINGOUT(@TAGISZERO),
END,
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qq
;;;
100
8089 BREAKPOINT ROUTINE
PAGE
END;
DECLARE 5AVESADDR LITERALLY '2000H',
SAVESSEG LITERALLY 'OOCOH';
DECLARE BREAK89 (4) WORD DATA (9B8IH,089IH,SAVESADDR,SAVESSEG),
1* BREAKB9 IS AN 4 WORD ESCAPE SEGUENCE TO ADDRESS 2000H
CONSIST,ING OF AN LPDI TP, SAVESADDR WITH SEGMENT·
LOCATED AT OCOOH,
*1
101
1* BRKRTN IS 33 BYTES OF CODE THAT STORES ALL REGISTERS
AS FOl LOWS:
GA STORED
GB STORED
GC STORED
BC STORED
IX STORED
CC STORED
MC STORED
AT
AT
AT
AT
AT
AT
AT
PP
PP
PP
PP
PP
PP
PP
+
+
+
+
+
+
+
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242
245
248
250
252
254
*1
DECLARE BRKRTN (33) BYTE AT (02COOH)
i* 02COOH 15 ACTUALL.Y (SAVESADDR + (SHL(SAVESSEG), 4», AND SHOULD
MATCH ADDRESS AND SEGMENT WHERE BREAK ROUTINE IS WANTED
*1
INITIAL
,03H,Q9BH,QEFH,023H,09BH,OF2H,043H,09BH,OF5H,063H,087H,OF8H,OA3H,087H,
OFAH,QC3H,Q87H,OFCH, OE3H,OB7H, OFEH,020H,048H)
DECLARE PP POINTER;
DECLARE PPP BASED PP (I) BYTE;
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1 :)5
lr,6
2
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;;;
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IG9
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",
;;;
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STARTSPROM
PROCEDURE(ONESTWO,PPP);
DECLARE ,ONEHWO BYTE, PPP POINTER,
WHERE BASED PPP (I) BYTE;
WHERECO) = STARTSBYTES(O),
WHERE( 1) = p;
WHERE(2) ~ STARTSBYTES(2),
WHERE(3) ~ STARTSBYTES(3);
CPDAT(CONESTWO) * 8) = 3,
1* IF ONETWO = 1 THEN OUTPUT TO PORT OFBH,
15 0 THEN OUTPUT TO PORT OFAH *1
OUTPUT CCHANATTEN + (ONETWO » = 0;
CALL STRINGOUT(@CHANGIVEN);
END;
1* THIS PART OF THE PROGRAM ALLOWS THE USER TO DEFINE THE
CP,PP OF EACH CHANNEL *1
DECl.ARE BREAKOUT BASED ENDPOINTER (I) WORD;
117
DECLARE CP POINTER;
DECLARE CPDAT BASED CP (I) BYTE,
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DECLARE ONEPPDAT BASED ONEPP (I) BYTE,
DECLARE TWOPPDAT BASED TWOPP (I) BYTE;
120
CALL STR INGOUT Ci!T ITLESTR ING),
lib
IF ONETWO
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8089 BREAKPOINT ROUTINE
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CALL STRINGOUTCIGETCP),
CP = GETADDRESS,
CALL STRINGOUTCIGETPP),
CALL STRINGOUTCIONE) ,
ONEPP = GETADDRESS,
CALL STRINGOUTCIGETPP),
CALL STRINGOUTC@TWO),
TWOPP = GETADDRESS,
OUTPUT CCHANATTEN) = 0, 1* INITIALIZATION CA *1
130
MAIN:
CALL STRINGOUTC@CHANNUMBER),
CHAR = CI, 1* GET CHANNEL NUMBER *1
IF (CHAR AND 01H) (> 0 1* CHECK BIT ZERO TO DEFINE
CHANNEL NUMBER *1
THEN DO,
CALL STRINGOUTC@ONE),
ONETWO = CHANNELSONE,
END,
ELSE
DO,
CALL STRINGOUTC@TWO),
ONETWO = CHANNELSTWO,
END,
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2
2
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1
2
2
2
CALL STRINGOUTC@GETSSTART), 1* GET STARTING ADDRESS
FROM USER *1
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1
2
2
1
STARTPOINTER = GET ADDRESS,
DO I = 0 TO 3, 1* MOVE STARTING ADDRESS INTO CP AREA *1
STARTBYTESCI) = INPNTRCI),
END,
CALL STRINGOUTC@STOPADDR), 1* GET STOP ADDRESS
FROM USER *1
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1
1
2
2
1
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1
ENDPOINTER : GETADDRESS,
DO I = 0 TO 3, 1* MOVE CODE TO SAFE AREA *1
SAVECODECI) = BREAKOUTCI),
END,
DO I = 0 TO 3,
BREAKOUT(I) = BREAK89CI), 1* MOVE ESCAPE SEClUENCE INTO PLACE *1
END,
CPDAT(I) ~ OFFH, 1* SET CHANNEL ONE BUSY FLAG *1
CPDAT(9) = OFFH, 1* SET CHANNEL TWO BUSY FLAG *1
DO CASE ONETWO,
PP = ONEPP,
PP = TWOPP,
END,
CALL STARTSPRGM(ONESTWO,PP),
1* WAIT FOR ONE OF THE FOLLOWING
I.CPDAT(I) = 0 CHI NOT BUSY
2.CPDAT(9) = 0 CH2 NOT BUSY
3. THE 8251 REC. BUFFER IS FULL BECAUSE USER HAS DEPRESSED A KEY
*1
DO WHILE C CCPDAT(I) AND CPDAT(9» AND CNOT CINPUTCCRTSSTATUS) AND 02H»)
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OFFH,
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8089 BREAKPOINT ROUTINE
END,
IF CINPUTCCRT.STATUS) AND 02H) (> 0
THEN
DO,
CHAR = CI,
DO I = 0 TO 3,
BREAKOUTCI) = SAVECODECI),
END,
1* IF ONE TWO = 0 THEN PUT CHA HLT IN CPDATCO)
IF ONETWO = 1 THEN PUT CHA HLT IN CPDAT(8)
*1
CPDATCONESTWO *8) = 06H,
= 0 THEN OUTPUT TO PORT OFAH.
IS 1 THEN OUTPUT TO PORT OFBH.
1* IF ONE TWO
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2
3
3
*1
OUTPUTCCHANATTEN + ONE TWO I
DO I e. 0 TO 5,
CALL TIMEClOO),
END,
IF ONETWO
= 0,
1* IF BUSY FLAG HAS BEEN CLEARED. THEN A CA HALT&SAVE
WAS EXECUTED.
IF SO. PRINT SAVED TP, IF NOT. ABORT
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3
CALL HEXOUTCPPPCI», 1* MIDDLE BYTE OF ADDR
STORED BY HALT *1
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3
CALL HEXOUTCPPPCO»; 1* LEAST SIG BYTE OF ADDR
STORED BY HALT *1
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1
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2
CALL STRINGOUTC@BKREACHED);
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CALL
CALL
CALL
CALL
CALL
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CALL STRINGOUTC@9BSTRING);
CALL COCASCIICSHRCPPP(244).4»);
CALL HEXOUTCPPP(243»,
*1
IF CPDATCSHLCONETWO.3) + I) () 0
1* CHECK BUSY FLAG *1
THEN
DO,
CALL STRINGOUTC@ABORT),
END,
ELSE
DO,
CALL STRINGOUTC@ABORTAT),
CALL COCASC!lCSHRCPPP(2).4»), 1* UPPER NIBBLE OF AD DR
STORED BY HALT *1
END,
CPDATCONETWO * 8)
GO TO MAIN,
= 3H;
1* CA START IN CPDATCO) OR CPDAT(8) *1
END;
DO;
STRINGOUTC@GASTRING);
COCASCIICSHRCPPP(241).4»);
HEXOUTCPPP(240»,
HEXOUTCPPP(239»;
TAGTESTCPPPC241»,
A-lOS
7
AP-50
PL/M-86 COMPILER
197
198
2
2
CALL HEXOUT(PPP(242ll,
CALL TAGTE5T(PPP(244ll,
CALL
CALL
CALL
CALL
CALL
1<;9
2
200
201
2
202
203
2
2
2
STRINGOUT(@GC5TRINGl,
CO(A5CII(SHR(PPP(247l,4lll,
HEXOUT(PPP(246ll,
HEXOUT(PPP(245ll,
TAGTE5T(PPP(247l),
204
2
205
206
.,2
CALL 5TRINGOUT(@BCSTRINGl,
CALL HEXOUT(PPP(249)l,
CALL HEXOUT(PPP(248)l,
207
208
209
2
2
2
CALL STRINGOUT(@IX5TRINGl,
CALL HEXOUT(PPP(251)l,
CALL HEXOUT(PPP(250ll,
210
211
212
2
2
2
CALL STRINGOUT(@CC5TRINGl,
CALL HEX OUT (PPP (253 1 l'
CALL HEXOUT(PPP(252l),
2
CALL STRINGOUT(@MCSTRINGl,
CALL HEXOUT(PPP(255l),
CALL HEXOUTIPPP(254)l,
213
214
215
END,
f* RESTORE CODE TO ORIGINAL LOCATION
DO I ~ 0 TO 3,
BREAKOUT(Il
SAVECODE(Il,
END,
~16
217
218
219
PAGE
8089 BREAKPOINT ROUTINE
2
GO TO MA IN,
220
END,
221
MODULE INFORMATION
CODE AREA SIZE,
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STAC~ SIZE
0619H
01EFH
0020H
0014H
15610
495D
320
200
427 LINES READ
o
PROGRAM ERROR(S)
END OF PLfM-86 COMPILATION
A-109
*1
8
AP-50
8089 ASSEMBLER
ISIS-II 8089 ASSEMBLER X004 ASSEMBLY OF MODULE AP50_BREAKPOINT_ROUTINE
OBJECT MODULE PLACED IN :FO:BRKASM.OBJ
ASSEMBLER INVOKED BY ASM89.4 BRKASM. SRC
AP50_BREAKPOINT_ROUTINE
1 NAME
2 BRKPNT SEGMENT
3 i**************************************
BASIC 8089 BREAKPOINT ROUTINE
4
BY JOHN ATWOOD
REV 3 8/13/79
5
6
INTEL CORPORATION
0000
7
8
9
2000
0000
9108 00200000
0000
OOEF
00F2
00F5
00F8
OOFA
OOFC
OOFE
0100
2000
2003
2006
2009
200C
200F
2012
039B
239B
439B
6387
A387
C387
E387
2015
2048
2017
EF
F2
F5
F8
FA
FC
FE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
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36
37
38
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45
46
47
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49
50
51
52
53
i**************************************
THE FOLLOWING CODE IS CONTAINED IN THE PL/M-86
CONTROL PROGRAM(BREAK.89) AND IS ASSEMBLED HERE
TO ILLUSTRATE HOW THE ESCAPE SEGUENCE AND SAVE
ROUTINE CODE WAS GENERATED.
TO USE THE 8089 BREAKPOINT PROGRAM, THIS ASM89 PROGRAM WOULD NOT BE
NEEDED.
SAVE ADDR IS THE SAME AS SAVE$ADDR IN THE
BREAK. 89 PROGRAM.
EGU
2000H
LPDI TP,SAVE_ADDR
,SAVE ROUTINE ADDRESS
,JUMP TO SAVE ROUTINE
i***************************************
REGISTER SAVE LOCATIONS WITHIN PB:
REGS
PBLOCK:
GASAV:
GBSAV:
GCSAV:
BCSAV:
IXSAV:
CCSAV:
MCSAV:
REGS
STRUC
OS
OS
OS
OS
OS
OS
OS
OS
ENDS
239
3
3
3
2
2
2
2
, PARAMETER BLOCK
,GA AREA
,GB AREA
, GC AREA
,BC AREA
, IX AREA
,CC AREA
, MC AREA
REGISTER SAVE ROUTINE:
MOVP [PPJ.GASAV,GA
MOVP [PPl.GBSAV,GB
MOVP [PPJ.GCSAV,GC
MOV [PPJ.BCSAV,BC
MOV [PPl. IXSAV, IX
MOV [PPl.CCSAV,CC
MOV [PPJ.MCSAV,MC
I
SAVE
,SAVE
,SAVE
,SAVE
,SAVE
,SAVE
,SAVE
GA
GB
GC
BC
IX
CC
MC
HLT
,STOP THIS CHANNEL,
,CLEAR BUSY FLAG.
;****************************************
BRKPNT
ENDS
END
A-lIO
APPLICATION
NOTE
Ap·51
March 1979
A-llI
AP-51
Designing 8086, 8088,
8089 Multiprocessor
Systems with the
8289 Bus Arbiter
Contents
INTRODUCTION
BUS ARBITER OPERATING CHARACTERISTICS
MULTI·MASTER SYSTEM BUS SURRENDER
AND REQUEST
8289 BUS ARBITER INTERFACING TO THE
8288 BUS CONTROLLER
8289 BUS ARBITER INTERNAL ARCHITECTURE
8086 FAMILY PROCESSOR TYPES AND
SYSTEM CONFIGURATIONS
8289 SINGLE BUS INTERFACE
lOB INTERFACE
RESBINTERFACE
INTERFACE TO TWO MULTI·MASTER BUSES
WHEN TO USE THE DIFFERENT MODES
Single Bus Multl·master Interface
lOB Made
Resident Bus Made
CONCLUSION
Our thanks ta Jim Nadir, the authar 61 this application nate. Jim is a
design engineer in the micrapracessars and peripherals .operatian
divisian. Please direct any technical questians yau may have t6
yaur lacal Intel FAE (Field Applicatian Engineer).
A-112
AP-51
INTRODUCTION
Over the past several years, microprocessors have been
increasing in popularity. The performance improve·
ments and cost reductions afforded by LSI technology
have spurred on the design motivation of using multiple
processors to meet system real·time performance
requirements. The desire for improved system real·time
response, system reliability and modularity has made
multiprocessing techniques an increasingly attractive
alternative to the system design engineer; techniques
that are characterized as having more than one micro·
processor share common resources, such as memory
and 1/0, over a common multiple processor bus.
This type of design concept allows the system designer
to partition overall system functions into tasks that
each of several processors can handle individually to
increase system performance and throughput. But, how
should a designer proceed to implement a multiprocessing system? Should he design his own? If so, how
are the microprocessors synchronized to avoid contention problems? The designer could put them all in phase
using one clock for all the microprocessors. This may
work, until the physical dimensions of the system
become large. When this occurs, the designer is faced
with many problems, like clock skew (resulting in bus
spec Violations) and duty cycle variations.
A better approach to implementing a multiprocessor
system is not to have a common processor clock, but
allow each processor to work asynchronously with
respect to each other. The microprocessor requests to
use the multiple processor bus could then be synchro·
nized to a high frequency extemal clock which will per·
mit duty cycle and phase shift variations. This type of
approach has the benefit of allowing modularity of hard·
ware. When new system functions are desired, more
processing power can be added without impacting
existing processor task partitioning.
One approach to implement this asynchronous process·
ing structure would be to have all the bus requests enter
a priority encoder which samples its inputs as a func·
tion of the higher frequency "bus clock". The inputs
would arrive asynchronously to the priority encoder and
would be resolved by the priority encoder structure as to
which microprocessor would be granted the bus. An·
other approach, that used by Intel, is rather than allow·
ing the requests to arrive asynchronously with respect
to one another at the priority encoder, the bus requests
are synchronized first to an external high frequency bus
clock and then sent to the priority encoder to be reo
solved. In this way, the resolving circuitry common to all
microprocessors is kept at a minimum. Overall system
reliability is improved in the sense that should a circuit
which serves to synchronize the processor's request
(which is now located on the same card as the micro·
processor itself) fail, it is only necessary to remove that
card from the system and the rest of the system will
continue to function. Whereas in the other approach,
should the synchronizing mechanism fail, the whole
system goes down, as the synchronizing mechanism is
located at the shared resource. In addition to the im·
proved system reliability, moving the synchronization
mechanism to the processor permits processor control
over that mechanism, thereby permitting system flexi·
bility (as will be shown) which could not be reasonably
obtained by any other approach.
This synchronizing or arbitrating function was inte·
grated into the 8289, a custom arbitration unit for the
8086, 8088, and 8089 processors. This note basically
describes the 8289 arbitration unit, illustrates its dif·
ferent modes of operation and hardware connect in a
multiprocessor system. Related and useful documents
are: 8086 user's manual, 8289 data sheet, Article Reprint
-55: Design Motivations for Multiple Processor
Microcomputer Systems (which discusses implementing a semaphore with the MULTIBUS™) and Application
Note 28A, Intel MULTIBUS™ interfacing.
BUS ARBITER OPERATING CHARACTERISTICS
The 8289 Bus Arbiter operates in conjunction with the
8288 Bus Controller to interface an 8086, 8088, or 8089
processor to a multi·master system bus (the 8289 is
used as a general bus arbitration unit). The processor is
unaware of the arbiter's existence and issues com·
mands as though it has exclusive use of the system bus.
If the processor does not have the use of the multi·
master system bus, the bus arbiter prevents the bus
controller, the data transceivers and the address latches
from accessing the system bus (i.e., all bus driver outputs are forced into the high impedance state). Since
the command was not issued, a transfer acknowledge
(XACK) will not be returned and the processor will enter
into wait states. Transfer acknowledges are signals
returned from the addressed resource to indicate to the
processor that the transfer is complete. This signal is
typically used to control the ready inputs of the clock
generator. The processor will remain in wait until the
bus arbiter acquires the use of the multi·master system
bus, whereupon the bus arbiter will allow the bus con·
troller, the data transceivers and the address latches to
access the system bus. Once the command has been
issued and a data transfer has taken place, a transfer
acknowledge (XACK) is returned to the processor. The
processor then completes its transfer cycle. Thus, the
arbiter serves to multiplex a processor (or bus master)
onto a multi·master system bus and avoid contention
problems between bus masters.
Since there can be many bus masters on a multi·master
system bus, some means of resolving priority between
bus masters simultaneously requesting the bus must be
provided. The 8289 Bus Arbiter provides for several
resolving techniques. All the techniques are based on a
priority concept that at a given time one bus master will
have priority above all the rest. These techniques in·
clude the parallel priority resolving techniques, serial
priority resolving and rotating priority techniques.
A-I 13
AP-51
A parallel priority resolving technique has a separate
bus request (BREQ) line for each arbiter on the multimaster bus (see Figure 1). Each BREQ line enters into a
priority encoder which generates the binary address of
the highest priority BREQ line which is active at the
inputs. The output binary address is decoded by a
decoder to select the corresponding BPRN (bus priority
in) line to be returned to the highest priority requesting
arbiter. The arbiter receiving priority (BPFilil active low)
then allows its associated bus master onto the rnulti·
master system bus as soon as it becomes available (Le.,
it is no longer busy). When one bus arbiter gains priority
over another arbiter, it cannot immediately seize the
bus, it must wait until the. present bus occupant com-
pletes its transfer cycle. Upon completing its transfer
cycle, the present bus occupant recognizes that it no
longer has priority and surrenders the bus, releasing
BUSY. BUSY is an active low OR-ti.ed signal iine which
goes to every bus arbiter on the system bus. When
BUSY goes high, the arbiter which presently has bus
priority (BPRN active low) ttien seizes the bus and pulls
BUSY low to· keep other arbiters off the bus. (See
waveform timing diagram, Figure 2.) Note that all multimaster system bus transactions are synchronized to the
bus clock (BCLK). This allows for the parallel priority
resolving circuitry or, any .other priority resolving
scheme employed, time to ·settle and make a correct
decision.
74138
3
D:CTgD~R 4
Figure 1. Parallel Priorlly Resolving Technique
0)
@
@
@)
HIGHER PRIORITY BUS ARBITER REQUESTS THE MULTI·MASTER SYSTEM BUS.
ATTAINS PRIORITY.
LOWER PRIORITY BUS ARBITER RELEASES BUSY.
HIGHER PRIORITY BUS ARBITER THEN ACQUIRES THE BUS AND PULLS BUSY DOWN.
Figure 2. Higher Priority Arbiter Obtaining The Bus From A Lower Priority Arbiter
A-114
AP-51
A serial priority resolving technique eliminates the need
for the priority encoder-decoder arrangement by daisychaining the bus arbiters together. This is accomplished
by connecting the higher priority bus arbiter's BPRO
(bus priority out) output to the BPRN of the next lower
priority (see Figure 3). The highest priority bus arbiter
would have its BPRN line grounded, signifying to the arbiter that it always has highest priority when requesting
the bus.
HIGHEST PRIORITY
/
CBRQ:
.
: BUSY
THE NUMBER OF ARBITERS THAT MAY BE DAISY·CHAINED
TOGETHER IN THE SERIAL PRIORITY RESOLVING TECH·
NIQUE IS A FUNCTION OF BCLK AND THE PROPAGATION
DELAY FROM ARBITER TO ARBITER. NORMALLY. AT 10 MHz
ONLY 3 ARBITERS MAY BE DAISY·CHAINED. SEE TEXT.
Figure 3. Serial Priority Resolving
A rotating priority resolving technique arrangement is
similar to that of the parallel priority resolving technique
except that priority is dynamically reassigned. The priority encoder is replaced by a more complex circuit
which rotates priority between requesting arbiters, thus
guaranteeing each arbiter equal time on the multimaster system bus.
There are advantages and disadvantages for each of the
techniques described above. The rotating priority resolving technique requires an extensive amount of logic
to Implement, while the serial technique can accommodate only a limited number of bus arbiters before the
daisy-chain propagation delay exceeds the multi-master
system bus clock (BCLK). The parallel priority resolving
technique is, in general, the best compromise. It allows
for many arbiters to be present on the bus while not
requiring much logic to implement.
Whatever resolving technique is chosen, it is the
highest priority bus arbiter requesting use of the multimaster system bus which obtains the bus. Exceptions
do exist with the 8289 Bus Arbiter where a lower priority
arbiter may take away the bus from a higher priority arbiter without the need for any additional external logic.
This Is accomplished through the use of the CBRQ pin,
discussed in a later section.
MULTI-MASTER SYSTEM BUS SURRENDER AND
REQUEST
The 8289 Bus Arbiter provides an intelligent interface to
allow a processor or bus master of the 8086 family to access a multi-master system bus. The arbiter directs the
processor onto the bus and allows both higher and
lower priority bus masters to acquire the bus. Higher
priority masters obtain the bus when the present bus
master utilizing the bus completes its transfer cycle (including hold time). Lower priority bus masters obtain
the bus when a higher priority bus master is not
accessing the system bus and a lower priority arbiter
has pulled CBRQ low. This signifies to the arbiter
presently holding the multi-processor bus that a lower
priority arbiter would like to acquire the bus when it is
not being used. A strapping option (ANYRQSn allows
the multi-master system bus to be surrendered to any
bus master requesting the bus, regardless of its priority.
If there are no other bus masters requesting .the bus, the.
arbiter maintains the bus. as long as its associated bus
master has not entered the HALT state. The 8289 Bus
Arbiter will not voluntarily surrender the system bus and
has to be forced off by another bus master. An exception to this can be obtained.by strapping CBRQ low and
ANYRQST high. In this configuration the 8289 will
release the bus after each transfer cycle.
How the 8289 Bus Arbiter is configured determines the
manner in which the arbiter requests and surrenders the
system bus. If the arbiter is configured to operate with a
processor which has access to both a multi-master
system bus and a resident bus, the arbiter requests the
use of the multi-master system bus only for system bus
accesses (i.e., it is a function of the SYSB/RESB input
pin). While the processor is accessing the resident bus,
the arbiter permits a lower priority bus master to seize
the system bus via CBRQ, since It is not being used. A
processor configuration with both an 110 peripheral bus
and a system bus behaves similarly. If the processor Is
accessing the peripheral bus, the arbiter permits the
surrendering of the multi-master system bus to a lower
priority bus master. To request the use of the multimaster system bus, the processor must perform a
system memory access (as opposed to an 110 access).
The arbiter decodes the processor status lines to determine what type of access is being performed and behaves correspondingly. For simpler system configurations, such as a processor which accesses only a
multi-master system bus, the arbiter requests the use of
the system bus when it detects the status lines initiating a transfer cycle. The decoding of these status
lines can be referenced in the 8086, 8088 (non-liD processor) data sheets or the 8089 (110 processor) data
sheet.
There is one condition common to all system configurations where the multi-master system bus is surrendered
to a lower priority bus master requesting the bus by pulling CBRa low. This is the idle or Inactive state (TI) which
is unique to the 8086 and 8088 processor family. This TI
state come·s about due to the processor's ability to
fetch Instructions in advance and store them internally
for quick access. The size of the internal queue was optimized so that the processor would make the most ef-
A-II5
AP-51
fective use of its resources and be slightly execution
bound. Since the processor can fetch code faster than it
can execute it, it will fill to capacity its internal storage
queue. When this occurs, the processor will enter into
idle or inactive states (TI) until the processor has ex·
ecuted some of the code in the storage queue. Once this
occurs, the processor will exit the TI state and again
start code fetching. Between entering into .and exiting
from the TI state an indeterminate number of TI states
can occur during which the bus arbiter permits the surrendering of the multi-master system bus to a lower
priority bus master. As noted earlier and worth
repeating here, once the 8289 Bus Arbiter acquires the
use of the mlJlti-master system it will not voluntarily surrender the bus and has to be forced off by another bus
master. This will be discussed in more detail later.
Two other signals, LOCK and CRQLCK (Figure 4), lend
to the flexibility of the 8289 Bus Arbiter within system
configurations. LOCK is a signal generated by the processor to prevent the bus arbiter from surrendering the
multi-master system bus to any other bus master, either
higher or lower priority. CRQLCK (common request lock)
serves to prevent the bus arbiter from surrendering the
bus to a lower priority bus master when conditions warrant. it. LOCK is used for implementing software
semaphores for critical code sections and real time
critical events (such as refreshing
transfers).
8289 BUS ARBITER INTERFACING TO THE 8288
BUS CONTROLLER
Once the 8289 Bus Arbiter determines to either allow its
associated processor onto the multi-master system bus
or to surrender the bus, it must guarantee that command setup and hold times are not violated. This is a
two part problem. One, guaranteeing hold time and two,
guaranteeing setup time. The 8288 Bus Controller performs the actual task of establishing setup time, while
the 8289 Bus Arbiter establishes hold time (see Figure
5).
The 8289 Bus Arbiter communicates with the 8288 Bus
Controller via the AEN line. When the arbiter allows its
associated processor access to the multi·master system bus, it activates AEN. AEN immediately enables the
address latches and data transceivers. The bus controller responds to AEN by bringing its command output
buffers out of high impedance state but keeping all
commands disqualified until command setup time is
established. Once established, the appropriate command is then issued. AEN is brought to the false state
after the command hold time has been established by
the arbiter when su rrenderi ng the bus.
LOCK TIMING
THE ONLY CRITICAL LOCK TIMING IS THAT SHOWN ABOVE. LOCK MUST BE
ACTIVATED NO SOONER THAN 20 ns INTO ,.,1 AND NO LATER THAN 40 ns
PRIOR TO THE END OF ".,2. LOCK INACTIVE HAS NO CRITICAL TIMING AND
CAN BE ASYNCHRONOUS.
CROlCK HAS NO CRITICAL TIMING AND IS CONSIDERED AS AN
ASYNCHRONOUS INPUT SIGNAL.
Figure 4. Lock Timing
AEN
(8289)
~SETUP~I
COMMAND
FLOAT
ACTIVE -..:.::::::.:.-t~
(8288)
*ADDRESS
CONT~sg~~E~2~~
AEN FRoM 8289
or hard disk
---...;c-
r-----------' '-_____
-J
·ADDRESSES ARE ACTIVATED IMMEDIATELY WHILE COMMAND IS DELAY
TO ESTABLISH SETUP TIME REQUIREMENTS.
uTHE 8289 ARBITER INTERNALLY TRACKS THE PROCESSOR CYCLE TO
ESTABLISH THE PROPER AMOUNT OF HOLD TIME AFTER THE COMMAND
HAS GONE INACTIVE.
Figure 5. Single Bus Interface Timing
A-116
'-------'1
AP-51
8289 BUS ARBITER INTERNAL ARCHITECTURE
bus is requested later in order to allow time for the
SYSB/RESB input to become valid. Forsystems which
access a peripheral bus, the arbiter issues a request for
the system bus only for memory transfer cycles which it
decodes from the status lines (and time must be allowed for the status lines to become valid and then de:
coded). In a system which accesses only a multi-master
system bus, a request is made as soon as the·arbiter
detects an active-going transition on the processor's
status lines. Thus, when the processor initiates a
transfer cycle, the FETG is triggered into operation and,
depending upon what mode the arbiter is configured in,
the STATUS & MODE DECODE circuitry initiates a request for the system bus at the appropriate time. The request enters the BREQ .SET circuitry where it is then
synchronized to the multi-master system bus clock
(BCLK) by the PROCESSOR SYNCHRONIZATION circuitry.· Once synchronized, the multi-master system
bus interface circuitry issues a BREQ. When the priority
resolving circuitry returns a BPRN (bus priority in), the
PROCESSOR SYNCHRONIZATION circuitry seizes the
b~s the next time it becomes available (i.e., BUSY goes
high) by pullin.llJ!..USY low one BCLK after it goes high
and enables AEN. (See waveform timing diagram in
Figure 2). Once the arbiter acquires the use of the
system bus and a data exchange has taken place (a
transfer acknowledge, XACK, was returned to the processor), the processor status Iines go passive and the
A block diagram of the internal architecture of the 8289
Bus Arbiter is shown in Figure 6.. lt is useful to understand this block diagram when discussing the different
modes of the 8289 and their impact on processor bus
operations; however, you may want to skip this section
to "8086 family processor types and system configurations" and return to it afterwards, as this section addresses the very involved reader. The front end state
generator (FETG) and the back end state generator
(BETG) allow the arbiter to track the processor cycle. An
examination of an 8086 family processor state tim,ings
show that all command and control signals are issued in
states T1 and T2 while being terminated in states T3 and
T4, with an indeterminate number of wait states (Tw) occurring in between. Note further, that an indeterminate
number of idle or inactive states can occur immediately
proceeding and following a given transfer cycle. Since
an indeterminate number of wait states can occur two
state generators are required; one to generate cdntrol
signals (the FETG) and one to terminate control Signals
(the BETG). The FETG is triggered into operation when
the processor activates the status lines. The FETG is
reset and the BETG is triggered into operation by the
status lines going to the passive condition. The BETG is
reset when the status lines again go active.
It is necessary for the 8289 Bus Arbiter to track the processor in order that it is properly able to determine where
and when to request or surrender the use of the multimaster system bus. In system configurations which access a resident bus, the use of the multi-master system
• Due to the asynchronous ~ature of processor trasnsfer request to the
multi-master system bus clo~k, it is necessary to synchr.onize the processor:s transfer request to BelK.
BCLK
PROCESSOR
SYNCHRONIZATION
CIRCUITRY
11l_ _....I'
:~~~
,,--,1 BPRO
IiUSV
CBRQ
MMS- BUS
SYNCHRONIZATION
CIRCUITRY
PRO~~~~~~ ~_ _...J'"
& CLOCK
STATUS & MOVE
DECODE
BREQ
RESET
WINDOW
~--------------~AEN
'MMS= MULTI·MASTERSYSTEM
Figure 6. 8289 Bus Arbiter Block Diagram
A-1l7
AP-51
lowed by the 1/0 bus Configuration and the Resident
Bus Configuration. Finally, brief mention is made of a
configuration that allows the processor to interface to
two multi·master system buses. This particular con·
figuration is briefly mentioned because, as will be seen,
it is simply an extension of the resident bus configura·
tion. When discussing the Single Bus Configuration,
processorlarbiter, arbiterlsystem bus and Internal ar·
biter, considerations are made resulting in a table that il·
Iustrates overhead in requesting the system bus. As this
applies tothe other 8289 configurations, only additional
considerations will be given. A summary of when to use
the different configurations is given at the end.
BETG is triggered into operation. The BETG provides
the timing for the bus surrender circuitries in the event
that conditions warrant the surrender of the multi·
master bus, i.e~, the bus arbiter lost priorityto a higher
bus master or the processor has entered into TI states
and CBRQ is pulled low, etc. If such is the case, the
BREQ RESET DECODER initiates a bus surrender reo
quest. The bus surrender request is synchronized by the
MMS BUS SYNCHRONIZATION CIRCUITRY to the proc·
essor clock. The MMS BUS SYNCHRONIZATION CIR·
CUITRY instructs the bus controller interface circuitry
to make AEN· go false and resets the BREQ. SET cir·
cuitry. Resetting the BREQ SET circuitry will cause its
output to go false and be synchronized by the processor
synchronization, eventually instructing the MULTI·
MASTER SYSTEM BUS INTERFACE circuitry to reset
BREQ. In the event that a lower priority arbiter has
caused the arbiter to surrender the bus, it is necessary
that BREQ be reset. Resetting BREQ allows the priority
resolving circuitry to generate BPRN to the next highest
priority bus master requesting the bus. The BREQ
RESET WINDOW circuitry provides a 'window' wherein
the arbiter allows the multi·master system bus to be sur·
rendered and serves as part of the M MS bus·processor
synchronization circuitry.
8289 SINGLE BUS INTERFACE
Figure 7 shows a block diagram of a bus master which
has to interface only to a system bus - preferably the
MUlTIBUS - where there exists more than one bus
master. In later configurations, it will be shown how the
processor can be made to interface with more than one
bus. Since the processor has only to interface with one
bus, this configuration is called "Single".
8086 FAMilY PROCESSOR TYPES AND
SYSTEM CONFIGURATIONS
There are two types of processors in the 8086 family an 1/0 processor (the 8089 lOP) and a non·I/O processor
(the 8086 and 8088 CPUs). Consequently, there are two
basic operating modes in the 8289 Bus Arbiter. One, the
lOB (1/0 peripheral bus) mode, permits the processor ac·
cess to both an 1/0 peripheral bus and a multi·master
system bus. The second, the RESB (residen\ bus) mode,
permits the processor to communicate over both a resi·
dent bus and a multi·master system bus. Even though it
is intended for the arbiter to be configured in the lOB
mode when interfacing to an 1/0 processor and for it to
be in the RESB mode when interfacing to a non·I/O proc·
essor, it is quite possible for the reverse to be true. That
is, it is possible for a non·I/O processor to have access
to an 1/0 peripheral bus or for an 1/0 processor to have
access to a resident bus as well as access to a multi·
master system bus. The lOB strapping option con·
figures the 8289 Bus Arbiter into the lOB mode and
RESB strapping option configures it into the resident
bus mode. If both strappi ng options are strapped false,
a third mode of operation is created, the single bus
mode, in which the arbiter interfaces the processor to a
multi·master system bus only. With bottvoptions strap·
ped true, the arbiter interfaces the processor to a multi·
master system bus, a resident bus and an 1/0 bus.
To better understand the 8289 Bus Arbiter, each of the
operating modes, along with their respective timings,
are examined by means of examples. The simplest con·
figuration, the Single Bus Configuration, (both lOB and
RESB strapped inactive) will be considered first, fol·
Connecting the 8289 Bus Arbiter to the processor is as
simple as it was to connect the 8288 Bus Controller.
Namely, the three status lines, SO, S1, and S2 are
directly connected from the processor to the arbiter.
The clock line from the 8284 Clock Generator is brought
down and connected. (Note that both the 8288 Bus Con·
troller and the 8289· Bus Arbiter are connected to the
same clock, ClK and not the peripheral clock, PClK as
the 8086 processor.) From the arbiter, AEN is con·
nected to the bus controller and to the clock generator.
The lOB pin on the arbiter is strapped high and on the
controller the lOB pin is strapped low. In addition, the
RESB pin on the arbiter is strapped low, finishing the
processor interface.
Some flexibility exists with the MUlTIBUS or multi·
master system bus interface. The system designer must
first decide upon the type of priority resolving scheme
to be employed, whether it is to be the serial, parallel, or
rotating priority scheme. A rotating priority scheme
would be employed where the system designer would
want to guarantee that every bus master on the bus
would be given time on the bus. In the serial and parallel
schemes, the possibility exists that the lowest assigned
priority bus master may not acquire the bus for long
periods of time. This occurs because priority is perma·
nently assigned and if bus demand is high by the higher
assigned priorities, then the lower priorities must wait.
In most cases, this situation is acceptable because the
highest priority is assigned to the bus master that can·
not wait. Highest priority is usually assigned to DMA
type devices where service requirements occur in real
time. CPUs are assigned the lower priorities. For the
purpose of this discussion, the parallel priority scheme
will be used with brief reference to the serial priority
scheme.
A-llS
AP-51
r----- ------------------------------.~l..
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Figure 7. Single
Multima~ter
Figure 8 shows how a typical multi·processing system
might be configured with the 8289 in the Single Bus
mode. In the system there are three bus masters, each
having the assigned priority as indicated-priority 1
being the highest and priority 3 being the lowest. Prior·
ity is established using the parallel priority scheme
(ignore the dotted signal interconnect for the moment).
Each bus arbiter monitors its associated processor and
issues a bus request (BREO) whenever its processor
wants the bus. A common clocking signal (BCLK) runs
to each of the arbiters in the system. It is from the failing edge of this clock that all bus requests are issued.
Since all bus requests are made on the same clock
edge, a valid priority can be established by the priority
resolving circuitry by the next falling BCLK edge. Note
that all mUlti-master system bus (MULTIBUS) input signals are considered to be valid at the falling edge of
BCLK. And that all multi-master system bus output
signals are issued from the falling edge of BCLK. With
the parallel resolving module, arbiters 2 and 3 would
Issue their respective BREOs (Figure 9) on the falling
!dge of BCLK 1, as shown. The outputs (BPRN 1, BPRN
2, and BPRN 3) of the priority encoder·decoder arrangement change to reflect their new input conditions and
need to be valid early enough in front of BCD<2 to
guarantee the arbiter's setup time requirements. Since
arbiter 2 at the time is the highest priority arbiter reguesting the bus, bus priority is given to arbiter 2 (BPRN
2 goes low), and since the bus was not busy (BUSY is
high) at the time priority was granted to arbiter 2 arbiter
2 pulls BUSY inactive on BCLK 2, thereby sei;ing the
bus and excluding all other arbiters access to the bus.
Once the bus is seized, arbiter 2 activates its AEN. AEN
going low directly enables the 8283 address latches and
Bus Interface
wakes up the 8288 Bus Controller. The bus controller
enables the 8287 transceivers, waits until the address to
command setup time has been established, and then
enables Its command drivers onto the bus.
If the serial priority resolving mode was used instead,
much of the events that happened for the parallel priority resolving mode would be the same except, of course,
there would be no parallel priority resolving module. Instead, the system would be connected as indicated in
Figure 8 by the dotted signal lines connecting the BPRO
of one arbiter to BPRN of the next lower priority arbiter.
The BREO lines would be disconnected and the priority
encoder-decoder arrangement removed. This arrangement is simpler than the parallel priority arrangement
except that the daisy-chain propagation delay of the
highest priority bus arbiter's BPRO to the lowest priority
bus arbiter's BPRN, including setup time requirement
(BPRN to BLCK), cannot exceed the BCLK period. In
short, this means there are only so many arbiters that
can be daisy·chained for a given BCLK frequency. Of
course, the lower the BCLK frequency, the more arbiters
can be daisy-chained. The maximum BCLK frequency Is
specified at 10 MHz, which would allow for three 8289
arbiters to be daisy-chained. In general, the number of
arbiters that can be connected in the serial daisy-chain
configuration can be determined from the following
equation:
BCLK period
~
TBLPOH
+ TPNPO (N -1) + TPNBL
where N = # of arbiters in system
A-1l9
AP-51
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AP-51
BREQ
ARBITER Hl
BREQ
ARBITER H2
BREQ
ARBITER H3
SPRN
ARBITER Hl
V
V
INVALID
INVALID'
\
BPRN
ARBITER H2
BPRN
ARBITER H3
I',
V
V
INVALID'
ARBITER
ARBITER #2
~\-"
INVALID
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'il
INVALID
ARBITER #3
..If
---\',\-I_ _ _ _
_ _ _ _ _ _--\1\-',_ _ _ _ _-\','\-,_ _ _ _
'DECODING GLITCHES ARE PERMITTED
Figure 9. Example Timing For Figure 8
Returning to Figure 9, it can be seen that K BClKs later,
arbiter 1 has decided to request the bus and its BREQ,
BREQ 1, has gone low. Since arbiter 1 is of higher priori·
ty than arbiter 2, which presently has the bus, bus priority is reassigned by the priority module (or the daisychain approach in the serial priority) to arbiter 1. BPRN 1
goes low and BPRN 2 now goes high (BPRN 3 remains
high, even though decoding can cause it to glitch
momentarily). The loss of priority instructs arbiter 2 that
a higher priority arbiter wants the bus and that it is to
release the bus as soon as its present transfer cycle is
done. Since arbiter 2 cannot immediately release the
bus, arbiter 1 must wait. In the particular case illustrated
in Figure 9, arbiter 2 releases the bus (allows BUSY to go
high) on clock edge M, and on clock edge M + 1, arbiter 1
now seizes the bus, pulling BUSY low. Arbiter 1 is the
highest priority arbiter in the system and it now has the
bus. Arbiters 2 and 3 still want the bus (their BREQs are
both low).
How quickly arbiter 1 can acquire the bus is dependent
upon the configuration and strapping options of the arbiter it is trying to acquire it from. For example, if the
lOCK input to arbiter 2 was active (low) at the time, then
arbiter 1, even though it was of higher priority, would not
have acquired the bus until after lOCK was released
(goes high). Effectively, lOCK locks the arbiter onto the
bus once the bus has been acquired. lOCK will not
force another arbiter to release the bus any sooner, it
just prevents the bus from being given away no matter
what the priority of the other arbiter. Another factor to
be considered is where in the transfer cycle is the processor when the arbiter is instructed to give up the bus.
Obviously, if the cycle had just started, it will take
longer for the bus to be released than if the cycle was
just ending. Another factor to be included in this consideration is the phase relationship of the processor's
clock (ClK) to the bus clock (BClK). This relationship is
examined in more detail later on. Table 1 lists the time
A-121
AP-51
requirements for various arbiter actions such as bus acquisition and bus release (under lOCK 2 ofTI and BREQI occurs I BClK(min)
to 2 BClKs (max) thereafter. Depending upon where status occurs
with respect to clock determines how lon9'a time exists between
status and .,2 of TI, and is anywhere from V, ClK (min) to I ClK
(max) ..
tRequest originates off of T2·.,1 and BREQI occurs I BClK (min) to
2 BClKs (max) thereafter. The same reasoning as used in the lOB
mode is valid here
Delay
(Max)
Delay
(Min)
Bus Rele.se (BREQt)
Mode
Higher Priority (BPRN I)
All
2 CLKs+
2BCCKs
I ClK+
I BClK
lower Priority (CBRQI)
All
2 ClKs+
2 BClKs'
I ClK+
I BClK
Surrender occurs once the proper surrender conditions exist.
Table 1. Surrender and Request Time Delays
One signal which has been basically ignored to. this
point is CBRO. CBRO, like BUSY, is an open-collector
Signal from the arbiter which is tied to the CBRO signals
of the other arbiters and to a pull-up resistor (see Figure
8). CBRO is both an input and an output. As an output,
CBRO serves to instruct the arbiter presently on the bus
that another arbiter wishes to acquire the bus. As an input, CBRO serves to instruct the arbiter presently on the
bus that another arbiter wants the bus. CBRO is an input
or output, dependent on whether the arbiter is on the
bus or not (respectively), and is issued as a fu nction of
BREO. Thus, a lower priority arbiter requesting the bus
already controlled by a higher priority arbiter will pull
CBRO low, as well as BREO. Even a higher priority arbiter will pull CBRO low until it acquires the bus. Note,
however, that the higher priority arbiter will acquire the
blls,through the reassignment of priorities - it being
given priority and the other arbiter presently on the bus
losing it. In effect, CBRO serves to notify the arbiter that
ali arbiterof'lower priority wants the bus.
If the arbiter presently on the bus is configured to react
toCBRO and the proper surrender conditions exist, the
bus is released. When releasing the bus, the arbiter also
tums off its BREO (BREO goes high) in order to allow
priority to be established to the next lower arbiter requesting the bus. Such is the case shown in Figure 9.
Whereas it was assumed that the proper surrender conditions did not exist for arbiter 2 when it had the bus, it
Is assumed that the proper conditions do exist during
the time that arbiter 1 has the bus. Arbiter 2 had to give
up the bus because an arbiter of higher priority was re-
questing it. Arbiter 1 surrenders the bus because the
proper surrender conditions exist and a lower priority arbiter requested the bus by pulling CBRO low. This is an
assumed condition which is not otherwise shown in
Figure 9. This is not an unrealistic condition. Normally,
a higher priority arbiter will acquire the bus through the
reassignment of priorities, while lower priority arbiters
acquire the bus through CBRO.
Digressing for a moment, the 8289 Bus Arbiter will not
voluntarily surrender the bus (except when the processor halts execution). As a result, it has to be forced off
the bus. The 8289 Bus Arbiter does not generate a BREO
for each cycle. It generates a BREO once and then
'hangs onto the bus. To do otherwise would require that
BREO be dropped (go high) after each transfer cycle so
that if it did ne.ed to do another transfer cycle,another
arbiter would automatically be assigned priority. This
approach, however, entails certain overhead. Command
to address setup and hold time must be prefixed and appended to each transfer cycle. Each transfer cycle
would be characterized by first acquiring the bus, then
establishing the setup time requirements, finally performing the transfer cycle, establishing the hold time requirements, and then releasing the bus (see Figure 10).
If another transfer cycle was to immediately follow and
if the arbiter still had priority, then the whole above procedure would be repeated. The end result would be
wasted time as hold times following setup times (see
Figure 10A). The approach taken by the 8289 Bus Arbiter
of having to be forced off the bus, even when it is not
using the bus (i.e., forced off by a lower priority arbiter),
provides for greater bus efficiency. A lower priority arbiter having to force ciff another arbiter that is not using
the bus but just hanging on to it, may not seem very efficient. In actuality it is a good trade-off: In many multimaster systems some bus masters occasionally demand the bus, while others demand the bus constantly.
The bus master which constantly demands the bus may
momentarily need not to access the bus. Why should
that arbiter surrender the bus when chances are that the
other bus masters which occasionally access the bus
don't want it at the time? If it doesn't give up the bus,
then it can momentarily cease access to the bus and
then continue, without any performance penalty of having to reestablish control of the bus. The greater bus efficiency that it affords is well worth the added complexity (Figure 10B).
'
Returning to Figure 9, the combination of the proper surrender conditions existing and CBRO being low,..forced
the higher priority arbiter, arbiter 1, ott the bus. Arbiter
2, being of next higher priority and wanting the. bus, acquired the bus. on clock edge N + 1. If arbiter ldecides
to:e-access the bus, it would reacquire the bus through
the reassignment of. priorities .. This is not the case
shown in Figure 9. Arbiter 1 has decided that it does not
need the bus and does not renew its BREO. Arbiter 2,
having acquired the bus .through CBRO; is now the
highest priority arbiter ,requesting the bus. As can be
seen it is not the only arbiter requesting the bus. Arbiter
3 is still patiently waiting for the bus andCBROremalns
low. The same conditions that forced,arbiter 1 off the
A-122
AP-51
bus for arbiter 2 now forces arbiter 2 off the bus for arbiter 3. When the proper surrender conditions exist, arbiter 2 releases its BREQ and surrenders the bus to arbiter 3. Arbiter 3 acquires the bus on clock edge P + 1
and releases its CBRQ. Since no other arbiter wants the
bus (i.e., there is no other arbiter holding CBRQ low),
CBRQ goes high (inactive). This would have also been
true when arbiter 2 acquired the bus and released its
CBRQ if arbiter 3 didn't want the bus.
the bus, the processor activates its status lines which in
turn enables the request input. Depending upon the
phase relationship between the occurrence of status (request active) and BClK, BREQ appears one to two
BClKs later. As shown in Figure 12, the phase relationship between request and BClK is such that the BRQ1
flip-flop mayor may not catch request on the first
BClK."
If BRQ1 flip-flop doe~ catch the request, then one BCD<
later, BREQ goes low and one BClK after that, BUSY
goes low (it is assumed that priority is immediately
granted and that the bus is avaiiable). If BRQ1 flip-flop
does not catch the request, then request is caught on
the next BClK and BREQ goes low one BClK later, followed by BUSY which also goes low one BClK later.
Note that BREQ and BUSY track, as BREQ is an input
term for BUSY. During bus acquisition, the surrender
flip-flop is false (SURNDR Q = low), and AEN follows
BUSY.
In the Single interface, the arbiter monitors the processor's status lines, which are activated whenever the
processor performs a transfer cycle. The arbiter, on
detecting the status lines going active, will issue a
BREQ if the status is not the HALT status. If the processor issues the HALT status, the arbiter will not request the bus, and if it has the bus, will release it.
This effectively concludes how arbiters interact to one
another on the bus. Having examined the processor-toarbiter interface, and arbiter-to-MUlTIBUS (arbiter-toarbiter) interaction, one interface is left, the internal
interface of processor-related signals to that of
MULTI BUS-related signals.
Once the bus is acquired, the surrender circuitry is
enabled so that when a valid surrender condition exists,
the bus can be surrendered. The surrender circuitry synchronizes the surrender request to the processor's
clock and drives SURNDR low. Like the acquisition circuitry, it takes from one to two processor clocks to generate SURNDR and depends upon the phase relationship between the surrender request and the processor's
clock.
'
An important point to remember is that the processor
has its own clock (ClK) and the multi-master system
bus has its own (BClK). These two clocks are usually
out of phase and of different frequencies. Thus, the arbiter must synchronize events occurring on one interface to events occurring on another interface. As a
result of this back and forth synchronization, ambiguity
can arise as to when events actually do take place.
'The two bus request flip-flops, BROt and BR02, are edge·triggered.
high resolution flip·flops and serve to reduce the probability of walkout
down to an acceptable level. Walkout occurs because BCLK Is asyn-"
chronous with respect to request. If walkout does occur on BROt flip·
flop, the probability Is high that the BROt fIIp·flop will resolve itself
prior to BR02 flip·flop being triggered. Even if BROt flip·flop did not
quite resoive itself, the probability of BR02 flip·flop walking out to an
u'nacceptable point in time is itself low.
'
Very simply, the 8289 arbiter operation can be represented as two events, requesting and surrendering.
Figure 11 is a representation of the timing relationships
involved. The request input is a function of the processor's clock and the surrender input is a function of
either the bus clock or the processor's clock. To request
"J
,bJ
a) BUS UTILIZATION AS A RESULT, OF HAVING TO REQUEST AND RELEASE THE BUS
FOR EACH TRANSFER CYCLE. THIS PERMITS LOWER PRIORITY ARBITERS EASY
ACCESS TO THE BUS SHOULD THE HIGHER PRIORITY ARBITER NO LONGER NEED
THE BUS. HOWEVER, BUS EFFICIENCY IS POOR DUE TO THE ARBITER THAASING ON
AND OFF OF THE BUS FOR EACH TRANSFER CYCLE.
b) 8289 BUS UTILIZATION IS MORE EFFICIENT IN THAT THE ARBITER HAS ONLY TO
ACQUIRE THE BUS ONCE. THE 8289 HANGS ONTO THE BUS UNTIL FORCED OFF.
THIS APPROACH ADDS A LlTILE MORE COMPLEXITY TO THE SYSTEM INASMUCH AS
SOME MEANS MUST BE PROVIDED FOR LOWER PRIORITY ARBITERS TO FORCE THE
HIGHER PRIORITY ARBITER OFF OF THE BUS WHEN IT IS NOT USING IT. THE ADDED
COMPLEXITY IS WELL WORTH THE BUS EFFICIENCY AND SYSTEM FLEXIBILITY IT
AFFORDS. THE 8289 ARBITER CAN BE CONFIGURED TO HAVE THE'TRANSFER TIMING·
AS SHOWN IN (a) (IMITATING THE METHOD 8218 AND 8219 USES, BUS ARBITERS FOR
8080 AND 8085 RESPECTIVELY) BY STRAPPING ANYRCST HIGH AND CBR~Q ,L~W.
Figure 10. Two Techniques For Doing
A-123
Multlbu~ Tr.~sler
Cycles
AP-51
./
j
-
BRQ. FF
REQUEST
-
D
~
...
BRQ2 FF
r--
I
'(eLK)
Q
S
~l
r-Q
Q
~
>1
....
BUSY FF
..---
~S
R
-
.Q
.~
BUSY
I
.
R
ACQU ISITION
CIRCUITRY
--
SURRENDER
CIRC UITRY
----------------- ----
-
'r-Q
D'
Q
l<~
SUiiNiiii
D
SURRENDER
REQUEST
I
'(BelK. elK)
1< -
-----Q
'-SAMPLE
RESOLVE
ClK
~
THIS CONCEPTUAL DIAGRAM IS PROVIDED FOR AIDING IN UNDERSTANDING
CLOCK AND BUS CLOCK RELATED EVENTS. IT DOES NOT REPRESENTJHE
ACTUAL SCHEMATIC OF THE 8289 DEVICE, AND IS FOR CONCEPTUAL
PURPOSES ONLY.
Figure 11. Symbolic Represenlallon of Inlernal 8289 Timing
ClK
IiElWm
'(elK)
Il
/
\
Iilffi(
®I
AER
I@
®I
I@
®I
I@
*WHEN THE IIElroEST OCCURS SIMULTANEOUSLY WITH BClK, BClK MAY OR
MAY NOT CATCH THE REQUEST. IF IT DOES, THE WAVEFORMS FOLLOW
THOSE SHOWN DESIGNATED BY
IF NOT, THE REQUEST IS PICKED UP
ON THE NEXT EDGE OF lillI:K AND THE WAVEFORMS FOllOW THOSE
SHOWN DESIGNATED BY @ .
®.
'Figure 12. Resulls Of An Asynchronous Evenl
A-124
AP-51
Having synchronized the surrender request to the processor's clock to generate SURNDR, SURNDR is then
synchronized to BClK to reset the BUSY and BRQ flipflops_ When BUSY-Q goes low, the surrender circuitry is
reset which in turn re-enables the request input The timing in Figure 13 shows the surrender request input
going high on the falling edge of the clock. If the Sample
flip-flop was able to catch the surrender request on the
edge of clock 1, then SURNDR would be generated (go
low) on clock edge 2. If not, SURNDR would be generated on clock edge 3. SURNDR going Iowan clock edge
2 will be, for ease of discussion, referred to as SURNDR
a and SURNDR going Iowan clock edge 3 will be referred to as SURNDR b. As can be seen from Figure 13,
SURNDR a just happens to go Iowan BClK edge 2.
Since SURNDR is used to reset the BRQ flip-flops,
which are clocked by the falling edge of BClK, the
BRQ1 flip-flop mayor may not catch SURNDR a on
BClK edge 2. If it does, then BRQ and BUSY go high on
BClK edge 3 which, for convenience, will be called
BREQ a or BUSY a. If not, theh BREQ and BUSY will go
high on BClK edge 4, which will be referred to as BREQ
b or BUSY b, respectively. SURNDR b occurs early
enough to assure that BUSY and BREQ are reset on
BClK edge 5, which will be referred to as BUSY b1 and
BREQ b1. Depending upon when BUSY goes high, determines when the surrender circuitry is reset and how
soon the next BREQ can be generated. BUSY a1 causes
SURNDR c to occur where shown and SURNDR c in turn
would allow the earliest bus request to occur at BREQ
c1. At the other extreme, BUSY b1 allows the earliest
bus request to occur at BREQ e1.
Table 1 summarizes the maximum and minimum delays
for bus request, once the proper request and surrender
conditions exist Table 2 lists the proper surrender conditions.
~~----- ----~--:---::-:--~-~
Mode
Single
Surrender Conditions
----cH-:-A-:-L-=T-s-la-te-"loss of BP-R-N-,-T-I.-C-B-'-R-EO--'---
lOB
HALT state, loss of BPRN, TI·CBREO,
110 Command.CBRO
RESB
HALT state, loss of BPRN, TI.CBREO,
ISYSBIRESB = O),CBRO
10B-RESB
HALT state,loss of BPRN, TI·CBREO,
ISYSBIRESB = O),CBREO,
110 Command.CBRO
Table 2. Surrender Conditions
ClK
SURRENDER
REaUEST
~
..J.,z b/
\
\ c1
\ d1
\ 91
\' - - _ ......
\ _ _ _ _ _ _ _\,1,....._
BREal
(EARLIEST THAT BREa COULD GO ACTIVE AFTER BUS RELEASE)
Figure 13. Asynchronous Bus Release
A-125
AP-51
lOB INTERFACE
Now that the processor-arbiter, arbiter-system bus and
internal .arbiter timings have been discussed, it is appropriate to consider the other interfaces that the 8289
Bus Arbiter provides.
In the lOB mode, the processor communicates and controls a host of peripherals over the peripheral bus. When
the 1/0 processor heeds to communicate with system
memory, it is done so over the system memory bus. Figure 14 shows a possible 1/0 processor system configuration, utilizing the 8089 1/0 processor in its
REMOTE mode. Resident memory exists on the peripheral bus in order that canned 1/0 routines and buffer
storage can be provided. Resident memory is treated as
an 110 peripheral. When a peripheral device needs servicing, the 1/0 processor accesses resident memory for
the proper 1/0 driver routine and services the device,
transmitting or storing peripheral data in buffer storage
area of resident memory. The resident memory's buffer
storage area could then be emptied or replenished from
system memory via the system bus. Using the lOB interface allows an 1/0 processor the capability of executing
from local memory (on the peripheral bus) concurrently
with the host processor.
Timing in this mode is no different from timing in the
SINGLE BUS mode. The only difference lies in the request and surrender conditions. The arbiter extends the
single bus mode conditions to qualify when the system
bus is requested and adds on additional surrender conditions. The system bus is only requested during system bus commands (the arbiter decodes the processor's
status lines) and, in addition to the other surrender
terms, the arbiter permits surrender to occur during I/O
bus (or local bus) commands, when the 1/0 processor is
using its own local bus.
Like the arbiter, the bus controller must also be informed of the mode it is operating in. In the lOB mode,
the 8288 bus controller issues 1/0 bus commands independently of the state of AEN from the arbiter. It is
assumed that all 1/0 bus commands are intended for the
1/0 bus and hence there is a separate 1/0 command bus
from the controller. All 1/0 bus commands are sent
directly to the 1/0 bus and are not influenced by AEN.
System bus commands are assumed as going to the
system bus. Since system bus commands are directed
to the system bus, they must still be influenced by AEiii
and the arbitration mechanism provided by the 8289.
As an example, suppose the processor issues an 1/0 bus
command. The 8288 Bus Controller generates the
necessary control signal to latch the 1/0 address and
configure the transceivers In the correct direction. In the
lOB mode, the multiplexed MCE/PDEN pin of the 8288
becomes PDEN (peripheral data enable) and serves to
enable the 1/0 bus's data transceivers during 1/0 bus
commands. DEN similarily serves to enable the system
bus's data transceivers during memory commands.
PDEN and DEN are mutually exclusive, so it is not possible for both sets of transceivers to be on, thereby
avoiding contention between the two sets. Since the 1/0
bus commands are generated independently of AEN In
the lOB mode, the 1/0 bus has no delay effects due to
the arbiter. During this time in which the processor is
accessing memory the arbiter, if it already has the bus,
will permit it to be surrendered to either a higher or
lower priority independently of where the processor is in
8284
CLOCK
XACK(IIO B U S ) ) - - - - - - j R D Y l
R D Y 2 1 - - - - - - - - - - - - - - - { X A C K MUlTI,MASTERSYSTEM BUS
8289
READY
Cl'
'"'
ARBITER
~=====:)MULnMASTER
CONTROL
'"'
COMMAND
'0
'"'
¢===::::;;;;;;;;;d
SYSTEM
~=====:)MULTI'MASTER
COMMAND
,US
MULTI·MASTER
SYSTEM BUS
'0
ADDRESS
'"'
~==~~~======JMULTI'MASTER
SYSTEM
ADDRESS
r+-----< ~fSVA~LE
'0
DATA
'"'
BUS
MULTI·MASTER
V':===========~SYSTEM
I\f
DATA
,US
Figure 14. 8289 Configured In 110 Bus Mode With 8089 1/0 Processor
A-126
AP-51
Its transfer cycle (i.e., independent of the machine
state). * If the arbiter does not already have the bus, it
will make no effort to acquire the bus.
If the processor issues a memory command instead, the
same set of events take place, except that 1) the system
bus's data transceivers are enabled instead of the
peripherals bus's data transceivers, and 2) when the
command is issued depends upon the state of the ar·
biter. In both cases of I/O bus commands and system
bus commands, the address generated for that com·
mand is latched into both sets of address latches, the
system bus's address latches, and the peripherals bus's
address latches. For each command (regardless of com·
mand type), an address is put out on the I/O bus and on
the system bus if the arbiter has the bus at that particu·
lar time. However, the bus controller only issues a com·
mand to one of the buses and hence, no ill effects are
suffered by addressing both buses.
If the arbiter already has the system bus when a system
bus command is issued, no delays due to the arbiter will
be noticed by the processor. If the arbiter doesn't have
the bus and must acquire it, then the processor will be
delayed (via the system bus command being delayed by
the bus controller through AEN from the arbiter) until
the arbiter has acquired the bus. The arbiter .will then
permit the bus controller to issue the command and the
transfer cycle continues.
RESBINTERFACE
The non·I/O processors in the 8086 family can communi·
cate with both a resident bus and a multi·master system
bus. Two bus controllers would be needed in such a con·
figuration as shown in Figure 15. In such a system con·
figuration the processor wou Id have to access to
memory and peripherals of both buses. Address map·
ping techniques can be applied to select which bus is to
be accessed. The SYSB/RESB (system bus/resident bus)
input on the arbiter serves to instruct the arbiter as to
whether or not the system bus is to be accessed. It also
enables or disables commands from one of the bus con·
trollers.
In such a system configuration, it is possible to issue
both memory and I/O commands to either bus and as a
result, two bus controllers are needed, one for each bus.
Since the controllers have to issue both memory and I/O
commands to their respective buses, the lOB options on
the controllers are strapped off (lOB is low). The ar·
biter, too, has to be informed of the system configuration in order to respond appropriately to system inputs
and has its RESB option strapped on (RESB is high). The
arbiter's lOB option is strapped inactive (lOB is high).
Strapping the arbiter into the resident bus mode
enables the arbiter to respond to the state of the
SYSB/RESB input. Depending upon the state of this input, the arbiter either requests and acquires the system
bus or permits the surrendering of that bus.
*Under other Circumstances, bus surrendering would only be permitted
during the period from where address to command hold time has been
established just prior to where the next command would be issued.
In the system shown in Figure 15, memory mapping
techniques are applied on the resident bus side of the
system rather than on the multiprocessor or system
bus side. As mentioned earlier in the lOB interface, both
sets of address latches (the resident bus's address
latches and the system bus's address latches) are
latched with the same address; in this case, by their
respective bus controllers. * The system bus's address
latches, however, mayor may not be enabled depending
upon the state of the arbiter. The resident bus's address
latches are always enabled, hence the address mapping
technique is applied to the resident bus.
Address mapping techniques can range in complexity
from a single bit of the address bus (usually the most
significant bit of the address), to a decoder, to a PROM.
The more elaborate mapping technique, such as PROM,
provides segment mapping, system flexibility, and easy
mapping modifications (Simply make a new PROM).
In actual operation, both bus controllers respond to the
processor's status lines and both will simultaneously
issue an address latch strobe (ALE) to their respective
address latches. Both bus controllers will issue command and control signals unless inhibited. The purpose
of the address mapping circuitry is to inhibit one of the
bus controllers before contention or erroneous commands can occur. The transceivers are enabled off the
same clock edge the commands are issued, namely <1>1
of T2 (Figure 16). The address is strobed into the ad. dress latches by ALE. ALE is activated as soon as the
processor issues status, and is terminated on <1>2 of of
T1. From when ALE is issued, plus the propagation
delay of the address latches, determines where the address is valid. The time from which the address is valid
to where control and commands are issued determines
how much settling time is available for the address mapping circuitry. The mapping circuitry must inhibit (via
CEN) one of the bus controllers prior to where controls
and commands are issued. Part of the settling time
(see Figure 16) is consumed as a setup time requirement
to the bus controllers. As it turns out, CEN (command
enable) can be disqualified as late as on the falling edge
of clock (the leading edge of <1>1 of T2) without fear of the
bus controller issuing any commands or transceiver
control signals. In systems (8 MHz) where less time is
available for the address mapping circuitry, the address
latches can be bypassed, hooking the mapping circuitry
straight onto the processor's multiplexed address/data
bus (the local bus) and using ALE to strobe the mapping
circuitry. This would avoid the propagation delay time of
the transceiv.ers. Besides needing to inhibit one of the
bus controllers, the arbiter needs to be informed of the
address mapping circuitry's decision. Depending upon
that decision, the arbiter acquires or permits the release
of the system bus.
• A simpler system with an 8086 or 8088 can exist, If it Is desirable to
only have PROM, ROM, or a read only peripheral interface on the resi·
dent bus. The 8086 and 8088 additionally generate a read signal in conJunction with the 8288 control Signals. By using this read signal and
memory mapping, the 8086 or 8088 could operate from local program
store without having the contention of using the system bus.
A-127
AP-51
o
8284
CLOCK
I - - - - - - - - - t - - - - - - - - XACK MULTI·MASTER SYSTEM 8US
MULTJ.MASTER SYSTEM
BUS CONTROL
Vee
SYSBIRESB
RESIDENT COMMAND
B,US
1:===::====1
MUlTI·MASTER SYSTEM
COMMAND BUS
\
MUl TI·MASTER
SYSTEM BUS
RESIOENT BUS
PROM
OR
DECODER
RESIDENT ADDRESS ('===~---'::===1
BUS
\;
MULnMASTER SYSTEM
ADDRESS BUS
rOT/A
RESIDENT DATA ;1---_ _ _ _~-_J\JTR:2~:;~~~ER
BUS
(2)
MULTI·MASTER SYSTEM
DATA BUS
1\c---------,;1
'BY ADDING ANOTHER 8289 ARBITER ANO CONNECTING ITS AEN TO THE 8288
WHOSE AEN IS PRESENTLY GROUNDED. THE PROCESSOR COULD HAVE ACCESS
TO TWO MULTI-MASTER BUSES
Figure 15. 8289 Configured In Resident Bus Mode
Tl
T4
T2
elK
PROCESSOR
STATUS
ALE (8288)
ADDRESS (8282,3)
COMMAND, CONTROL (8288)
TCY . {TeLAY
+
DELAY TIME THROUGH LATCHES]
+
5 "" TSETTLING
\
AVAILABLE
ADDRESS MAPPING
SETTLING TIME
Figure 16. Time Available For Address Mapping Prom
A-128
AP-51
The arbiter is informed of this decision via its
SYSB/RESB input. If the memory mapping circuitry
selects the resident bus, then SYSB/RESB input to the
arbiter and CEN input of the system bus controller are
brought low; and the CEN Input of the resident bus con·
troller is brought high. The commands and control
Signals of the resident bus are now enabled and those of
the system bus are disabled. In addition, with the arbiter
being informed that the transfer cycle is occurring on
the resident bus, the system bus is permitted to be sur·
rendered. Glitching is permitted on the SYSB/RESB in·
put of the arbiter up until <1>1 of T2. Thereafter, only clean
transitions can occur on the input. * So, if mapping cir·
cuitry can settle prior to <1>1 of T2, there is no need to be
concerned over glitching. If the mapping circuitry is
unable to settle prior to this time, then the designer
must guarantee a clean transition on the SYSB/RESB in·
put.
INTERFACE TO TWO MULTI·MASTER BUSES
The interface of an 8086 family processor to two multi·
system buses is simply an extension of the resident bus
interface. The only difference is that now two arbiters
are needed, one for each multi·master bus, and the ad·
dress mapping circuitry must acquire its input straight
off the processor's multiplexed address/data bus (the
local bus), using ALE as an address strobe input. Figure
17 depicts how such a system might be configured.
Figure 17 illustrates the use of the 8289 in a system en·
vironment in three of its four modes. The host 8086 CPU
(priority 3) is using the 8289 in its single bus multi·
master mode, while an 8089 I/O processor is using the
8289 in its lOB mode. A work station based on an 8088
processor uses the 8289 in it system/resident bus mode.
This diagram represents a hypothetical system wherein
there can exist more than one work station (only one
shown). Each work station shares system resources and
I/O. The lowest priority processor (8086) would provide
supervisory functions and system control, i.e., allow
operator intervention into the system resources. A work
station would call in assemblers and compilers or ap·
plication programs as needed. When compiled or
assembled, the results are transferred to the I/O station
for output, thus freeing up a work station for another
user.
'In certain memory mapping techniques, the CENs of the bus control·
lers are controlled differently from the SYSBIRESB input of the arbller.
In short, CEN is brought low automatically to both bus controllers,
thereby disabling their command and control outputs. This permits a
longer settling time for the memory mapping Circuitry, since both con·
trollers are disabled. When the mapping circuitry settles, sometime
after 4>1 of T2, one of the bus controllers and its associated bus arbiter
(If one exists) Is enabled. After 4>1 of T2, the arbiter can -only permit
clean transitions on the SYSBIRESB Input line.
If one work station is used, the serial priority resolving
technique could be used between the 8289 Bus Arbiters
(shown in dotted lines). If more than one work station Is
desired, it would be necessary to either slow down the
system bus clock to accommodate the additional ar·
biters, or resort to the parallel resolving technique (as
shown).
WHEN TO USE THE DIFFERENT MODES
Single Bus Multi·Master Interface
This mode is the simplest and is sufficient for systems
where a multiprocessing environment exists and the
system bus bandwidth is sufficient to handle the peak
concurrent requirements of a multi·master environment.
This solution can provide an inexpensive solution for
multi·masters to access an expensive I/O device. If,
however, the system bus bandwidth is exceeded, the
lOB or system/resident modes should be considered.
lOB Mode
The lOB mode is ideal when the bus can be separated In·
to an I/O bus and memory or system bus. This mode Is
commonly used with the 8089 I/O processor In its
REMOTE configuration to separate the I/O space from
memory space. With the 8089, all instructions operate
on either system or I/O address space. 64K bytes of I/O
space can be accessed by the processors in the 8086
family.
The remaining processors in the 8086 family are con·
strained to using only I/O instructions when referencing
I/O space. If this is a limitation, and it is desirable to
remove some of the processor functions to its private
resources, the resident bus mode should be considered.
Resident Bus Mode
The resident bus mode allows for maximum flexibility
for a CPU device, giving it both access to Its own local
resources with full instruction set capability, and the
system resources. The CPU can work from its own local
resources without contention on· the system bus. By
using a PROM for memory mapping, memory space can
be easily altered in this mode. This mode requires the
use of a second 8288 bus controller chip.
CONCLUSION
The 8289 brings a new dimension to microcomputer ar·
chitecture by allowing the advanced 8/16·bit microproc·
essors to play easily in a multi·master, multiprocessing
environment. With the fiexlble modes of the 8289, a user
can define one of several bus architectures to meet his
cost/performance needs. Modularity, improved system
reliability and Increased performance are just a few of
the benefits that designing a multiprocessing system
provides.
A-129
AP-51
80881
8086
CPU
READY
8284
CLOCK
ClK
ADDR/DATA
RDYAEN AENRDY
So-52
1
r-
,
ClK
8289
ARBITER
MUlTIBUS
CONTROL
(
1
So-52
2
XACK2
ClK
V!-
STATUS
I>..
SYSBI
RESB
8289
ARBITER
2
MULTI BUS
CONTROL
SO-52
y
~
AEN
2
If L:
XACK1
Ii
1
,-- I--
~
V
SYSBI
RESB
AEN
CEN
AEN
Ul
::>
.g
CD
~
u
AEN
Ii
MUlTiBUS
COMMANDS
CEN
ClK
8288
CONTROLLER
1
SO-52
'I
r--
---
I: I
lATC<
t
Ii
~
8288
CONTROllER
2
SO-52
,-
OT/R
DEN
ALE
Ii
\i
STB
OE
A
AODRIDATA
8283
lATCH
(2 OR 3)
~
y
.'1
ADDRESS
)
u
6
OE
'I
DATA
lI.
y
~7
Ii
-
~
OE
8283
lATCH
(2 OR 3)
ADDRESS
~y
ALE
6
STB
MUlTiBUS
COMMANDS
y
'I
OT/A' -
DEN
' - - ClK
*
8287
TRANSCEIVER
(lOR 2)
6
*
DTiR
DT/R
Ii
~
V
~
MEMORY MAPPING DECODING IS SHOWN TAKING PLACE DIRECTLY OFF OF
THE PROCESSOR'S LOCAL MULTIPLEXED ADDRESSIDATA BUS.
Figure 17. Using 82895 To Interface To Two Multimaster System Buses.
A-l30
OE
8287
TRANSCEIVER
(lOR 2)
DATA
lI.
)
y
THIS PAGE LEFT INTENTIONALLY BLANK
A-131
AP-51
r--------------------
~~
111
REAOy'-------------REAOY
8086
ClK~ClK
82!~.Q""N;!
..
I.
RDY2
DENDT/it
rr~ J.
~===::~
L...--OTIR
'----
"
~ 7L __________________
_
r-------------------
L __________________ _
Figure 18. 8289 Used In Each 01 3 Modes, Single Bus, 110 Bus, and Resident Bus Modes Implementing A Hypothetical Multlmaster Bus System
A-132
AP-51
,OMHa
CLOCK
r------------,
I
I
I
I
-====!t~w$ErBl~:,
",."''
!I
_
I,ENCODEA
DECODER
I
l2'
II
I
I
I
PRIOAIlYRESOLVING
L __ ~~E'::'FI~~___
_..J
I~
=hl~l::::II:;::I~I~
(
1111
=
I
I(
= IIII
:::!:
IA LJII
,
=
I I(
II I I I I ~
SYSUM
".
SYSTEM
MEMORY
o
...
...r-
=
l1 .. ... 1~ .J
"" INTO,,,'~~:frESS
"'''
MEMORY
c~:_
"'u
cONtReLlE!!
$ERVICEII[QUEIf
"
"""11"""'°1""""'1°1>"<'1
ii
....'
lowe
I
...! "'"
"" "."'''
AIOW"C
.. ~
L-.-
f--+--=".--:":I.. ~
=---'
1r r 1
If
h:::=::===~ F*
f----!----
DlIA
OEr---
un
-
PR'ORI(Y'
~
!
DTIIli
~OE
rr
1217
I
-----------------~
Figure 18o 8289 Used In Each Of 3 Modes, Single Bus, I/O Bus, and Resident Bus Modes Implementing A Hypothetical Mullimaster Bus System
A-133/ A-134
APPLICATION
NOTE
Ap·59
September 1979
121500-001
© Intel Corporation, 1979
A-135
AP-59
Using the 8259A
Programmable
Interrupt Controller
Contents
INTRODUCTION
CONCEPTS
MCS8DTM-8259A Overview
MCS85TM·8259A Overview
MCS86/88TM·8259A Overview
FUNCTIONAL BLOCK DIAGRAM
Interrupt Registers and Control Logic
Other Functional Blocks
Pin Functions
OPERATION OF THE 8259A
Interrupt Vectoring
MCS8D/85 Mode
MCS86/88 Mode.
Interrupt Priorities
Fully Nested Mode
End of Interrupt
Automatic Rotation
Specific Rotation
Interrupt Masking
Interrupt Triggering
Level Triggered Mode
Edge Triggered Mode
Interrupt Status
Reading Interrupt Registers
Poll Command
interrupt Cascading
Cascade Mode
Special Fully Nested Mode
Buffered Mode
PROGRAMMING THE 8259A
Initialization Command Words (ICWs)
Operational Command Words (OCWs)
APPLICATION EXAMPLES
Power Fail/Auto Start with Battery Back·Up RAM
78 Level Interrupt Structure
Timer Controlled Interrupts
CONCLUSIONS
APPENDIX A
APPENDIX B
A-136
AP-59
INTRODUCTION
The Intel 8259A is a Programmable Interrupt Controller
(PIC) designed for use in real· time interrupt driven
microcomputer systems. The 8259A manages eight
levels of interrupts and has built·in features for expan·
sion up to 64 levels with additional 8259A's. Its versatile
design allows it to be used within MCS·80, MCS·85,
MCS·86, and MCS·88 microcomputer systems. Being
fully programmable, the 8259A provides a wide variety of
modes and commands to tailor 8259A interrupt process·
ing for the specific needs of the user. These modes and
commands control a number of interrupt oriented func·
tions such as interrupt priority selection and masking of
interrupts. The 8259A programming may be dynamically
changed by the software at any time, thus allowing com·
plete interrupt control throughout program execution.
The 8259A is an enhanced, fully compatible revision of
its predecessor, the 8259. This means the 8259A can use
all hardware and software originally designed for the
8259 without any changes. Furthermore, it provides ad·
ditional modes that increase its flexibility in MCS·80
and MCS-85 systems and allow it to work in MCS·86 and
MCS·88 systems. These modes are:
'
•
•
•
•
•
MCS·86/88 Mode
Automatic End of Interrupt Mode
Level Triggered Mode
Special Fully Nested Mode
Buffered Mode
Each of these are covered in depth further in this appli·
cation note.
This application note was written to explain completely
how to use the 8259A within MCS·80, MCS·85, MCS·86,
and MCS·88 microcomputer systems. It is divided into
five sections. The first section, "Concepts", explains
the concepts of interrupts and presents an overview of
how the 8259A works with each microcomputer system
mentioned above. The second section, "Functional
Block Diagram", describes the internal functions of t,he
8259A in block diagram form and provides a detailed
functional description of each device pin. "Operation of
the 8259A", the, third section, explains in depth the
operation and use of each of the 8259A modes and commands. For clarity of explanation, this section doesn't
make reference to the actual programming of the 8259A.
Instead, all programming is covered in the fourth sec·
tion, "Programming the 8259A". This section explains
how to program the 8259A with the modes and com·
mands mentioned in the previous section. These two
sections are refer.enced in Appendix A. The fifth and
final section "Application Examples", shows the 8259A
in three typical applications. These applications are
fully explained with reference to both hardware and software.
The reader should note that some of the terminology
used throughout this application note may differ
slightly from existing data sheets. This is done to better
clarify and explain the operation and programming of
the 8259A.
1. CONCEPTS
In microcomputer systems there is usually a need for
the processor to communicate with various Input/Out·
put (1/0) devices such as keyboards, displays, sensors,
and other peripherals. From the system Viewpoint, the
processor should spend as little time as possible servicing the peripherals since the time required for these 110
chores directly affects the amount of time available for
other tasks. In other words, the system should be
designed so that 1/0 servicing has little or no effect on
the total system throughput. There are two basic
methods of handling the 1/0 chores in a system: status
polling and interrupt servicing.
The status poll method of 1/0 serviCing essentially in·
volves having the processor "ask" each peripheral if it
needs servicing by testing the peripheral's status line. If
the peripheral requires service, the processor branches
to the appropriate service routine; if not, the processor
continues with the main program. Clearly, there are
several problems in implementing such an approach.
First, how often a peripheral is polled is an important
constraint. Some idea of the "frequency-of-service"
required by each peripheral must be known and any software written for the system must accommodate this
time dependence by "scheduling" when a device is
polled. Second, there will obviously be times when a
device is polled that is not ready for service, wasting the
processor time that it took to do the poll. And other
times, a ready device would have to wait until the proc·
essor "makes its rounds" before it could be serviced,
slowing down the peripheral.
Other problems arise when certain peripherals are more
important than others. The only way to implement the
"priority" of devices is to poll the high priority devices
more frequently than lower priority ones. It may even be
necessary to poll the high priority devices while in a low
priority device service routine. It is easy to see that the
polled approach can be inefficient both time-wise and
software-wise. Overall, the polled method of 1/0 servicing can have a detrimental effect on system throughput,
thus limiting the tasks that can be performed by the
processor.
A more desirable approach in most systems would allow
the processor to be executing its main program and only
stop to service the 1/0 when told to do so by the 1/0
itself. This is called the interrupt service method. In
effect, the device would asynchronously signal the processor when it required service. The processor would
finish its current instruction and then vector to, the
service routine for the device requesting service. Once
the service routine is complete, the processor would
resume exactly where it left off. USing the interrupt service method, no processor time is spent testing devices,
scheduling is not needed, and priority schemes are
readily implemented. It is easy to see that, using the interrupt service approach, system throughput would increase, allowing more tasks to be handled by the
processor.
However, to implement the interrupt service method
between processor and peripherals, additional hardware
is usually required. This is because, after interrupting
the processor, the device must supply information for
vectoring program execution. Depending on the processor used, this can be accomplished by the device taking control of the data bus and "jamming" an instruction(s) onto it. The instruction(s) then vectors the pro-
A-137
AP·59
gram to the proper service routine. This of course requires additional control logic for' each interrupt requesting device. Yet the implementation so far is only in
the most basic forr:n. What if certain peripherals.are to
be of higher priority than others? What if certain interrupts must be disabled while others' are to be enabled?
The possible variations go on,b,uttheyall adduptq one
theme; to provide greater flexibility using the interrupt
service method, hardware requirements increase:
So, we're caught in the middl.e. The. status poll method
is' a less desirable way of servicing I/O in terms of
throughput, but its hardware requirements are minimal.
On the other hand, the interrupt service method is most
desirable in terms of flexlbilitY'and throughput, but
.
.
additional hardware IS required.
The perfect situation would be to have the flexibility and
throughput of the interrupt method in an implementation wi.th mini,mal hardware requirements.' The. 8259A
Programmable interrupt Controller (PIC) makes this all
possible;
.,.
.
The 8259A Programmable Interrupt Controller (PIC) was
designed to function as an overall manager of an interrupt driven system. No additional hardware is required_
The 8259A alone can handle eight prioritized interrupt
levels, controlling the complete interface between per.ipherals and processor.. Additional 8259A's can be
"cascaded" to increase the number of interrupt levels
processed. A wide variety of modes and commands for
programming the 8259A give it enough flexibility for
almost any interrupt controlled structure. Thus, the
8259A is the' feasible answer to handling I/O servicing in
microcomputer systems.
Now, before explaining exactly how to use the 8259A,
let's go over interrupt structures of the MCS-80, MCS-85,
MCS,86, and MCS,88 systems,. and how they Interact
with the 8259A.Figure 1 shows a block diagram of the
8259A interfacing with a standard system bus; This may
prove useful as reference throughout the rest of the
"Concepts" section.
I
INTERRUPT
R!QUESTS
r
Figure 1: 8259Alnterface to. Standard System Bus
I
."
1.1 MCS-80™_8259A OVERVIEW
In an MCS-80-8259A interrupt configuration, as in
Figure 2, a device may cause an interrupt by'pulling one;
of the 8259A's interrupt request pins (IRO-IR7) high. If
the 8259A accepts the interrupt request (this depends
On its programmed condition), the 8259A's INT (interrupt) pin will go high, driving the 8080A's INT pin high.
The 8080A can receive an. interrupt request anY.time,
since Its INT input is asynchronous. The 8080A, however, doesn't always have to acknowledge an interrupt
request immediately. It can accept or disregard requests under software control using the EI (Enable Interrupt) or 01 (Disable Interrupt) instructions. These instructions either set or reset an internal Interrupt enable
flip-flop. The output of this flip-flop controls the state of
the INTE (Interrupt Enabled) pin. Upon reset, the 8080A
interrupts aredisabled,making INTE low.
Ai
the end of each instruction cycle, the 8080A exam~
ines the state of its INT pin. If an interrupt request Is
present and Interrupts are enabled, the 8080A enters an
interrupt machine cycle. During the interrupt machine
cycle the 8080A resets the internal interrupt enable flipflop, disabling further interrupts until an EI instruction
is executed. Unlike normal machine cycles, the interrupt
machine cycle doesn't increment the program counter.
This ensures that the8080A can return to the preinterrupt program location after the: interrupt is completed.The 8080A then issues an INTA (Interrupt
Acknowledge) pulse via the 8228 System Controller Bus
Driver. ThislN'fA pulse signals the 8259A that the 8080A
is honoring the request and is ready to process the interru~
,
' .
The 8259A can now vector program execution to the corresponding service routine. This is done during a sequence of the three INTA pulses from the 8080A via the
8228. Upon receiving the first INTA pulse the 8259A
places the opcode for a CALL' instruction on the data
bus. This causes the contents of the program counter to
be pushed onto 'the stack. In addition, the CALL instruction causes two more INTA pulses to be issued, allow;
ing the 8259A to place onto the data bus the starting
address of the corresponding service routine. This
address is called the interrupt-vector address. The lower
8 bits (LSB) of the interrupt-vector address are released
during the second INTA pulse and the upper 8 bits
(MSB) during the third INTA pulse. Once this sequence
is completed, program execution then vectors to the
service routine at the interrupt-vector address.
If the same registers are used by both the main program
and the interrupt service routine, their contents should
be saved when entering the service routine. This includes the Program Status Word (PSW) which consists
of the accumulator and flags, The best way to do this is
to "PUSH" each register used onto the stac~. The service routine can then "POP" each register off the ,stack
in the reverse order when it is completed. This prevents
any ambiguous operation when returning to the main
program.
Once the service routine Is completed, . the main
program maybe re-entered by usinga·normal RET
(Return) instruction. Thi.s
"POP" the original con-
will
A-13B
AP-59
uration. When an interrupt occurs, a sequence of three
INTA pulses causes the 8259A to release onto the data
bus a CALL instruction and an interrupt-vector address
for the corresponding service routine. Other events that
occur during the 8080A interrupt machine cycle, such as
disabling interrupts and not incrementing the program
counter, also occur in the 8085A interrupt acknowledge
machine cycle. Additionally, the instructions for saving
registers, enabling or disabling of interrupts, and returning from service routines are literally the same.
tents of the program counter back off the stack to
re,sume program execution where it left off. Note, that
because interrupts are disabled during the interrupt
acknowledge sequence, the EI instruction must be
executed either during the service routine or the main
program before further interrupts can be processed.
For additional information on the 8080A interrupt structureand operation, refer to the MCS-80 User's Manual.
1.2 MCS·85™_8259A OVERVIEW
The 8085A, however, has a different interrupt hardware
scheme as shown in Figure 3. For one, the 8085A supplies its own INTA output pin rather than using an addi-
An MCS-85-8259A configuration processes interrupts
in much the same format as an MCS-80-8259A config-
I------------'===;'T----------,/
TO MEMORY AND 1/0
IRO_
IRl
IA2IA3 _
INTERRUPT
REQUEST
INPUTS
IR'
IRS_
L -_ _ _, / TO SLAVE 8259A5
L -_ _ _ _ _ _ _ _- , / TO MEMORY AND 1/0
Figure 2. MCS-80 8259A Basic Configuration Example
TO MULTIPLEXED
Mesas FAMILY
------
.-
rD~ t J
Xl
X2 RESET elK
RESET IN
OUT
A8·15
111'11
ADDRESS BUS
,Ill I
HOLD
~ISTB
ROY
TRAP
I
AO_7
HLDA
ALE
8085A
0°0_7
8282
OE
010_7
RS17.5
-=-
INTR
INTA
We
AOo_7
loiM'
E2 El A2 Al
AD
8205
00 0, 02 03 04 05
as
I
To STANDARD MEMORY
ANO OTHER 1/0
07
I I IJ III
R516.5
RS15.5
E3
V
AD
1/0 SELECT
"A-
To STANDARD MEMORY
ANO OTHER I/O
MULTIPLEXED ADDRESSIDATA BUS
I
I
+5-
Ro
lK
TO I/O & MEMORY
QUALIFIED BY loiM
8259A SELECT
IT
SP/EN
AD
Os
00_7
8259A
RD
WR
INTA
INT CASO_2
I
™8259A BaBic Configuration Example
Figure 3. MCS-85
A-139
IRD
IRl
IR2
IR3
IR'
IRS
IRS
IR7
--
II-
I-
r--
--
INTERRUPT
REQUEST
INPUTS
To SLAVE 8259A
AP-59
tional chip, as the 8080A uses the 8228 System Con:
troller Bus Driver. Another hardware difference is the
8085Ahas five hardware interrupt pins: INTR, RST 7."5,
RST6.5, RST 5.5, and TRAP. The INTR (Interrupt Request)
pin is the equivalent to the 8080A's INT pin. The RST
(Restart) pins and TRAP pin are all restart" interrupts
which vector program execution to an individual dedicated address when asserted: The' important factor
aSSOCiating these interrupts is their relative priority, as
shown below:
.
TRAP
RST 7.5
RST 6.5'
RST 5.5
INTR
Highest Priority
Lowest Priority
The INTR pin has lowest priority among the other 8085A
hardware interrupts. Thus, precautions to prevent interrupting 8259A service routines may be necessary. This,
of course, depends on how the 8085A interrupts are
being used in a particular application. Such precautions
can be implemented, however,by masking the RST pins
using the SIM instruction. The TRAP pinon the other
hand is non-maskable; all interrupt pins but TRAP can
be controlled by the EI.(Enable Interrupt) and 01 (Disable
Interrupt) instructions.:
For a complete description of the 808~A inter.rupt structure, refer to the' MCS~85 User's Manual.
1.3 MCS-S6ISS™--S259A OVERVIEW
Operation of an MCS-86/88-8259A configuration has
basic similarities of the MCS-80/85-8259A configura-
tions. That is, a device can cause an interrupt by pulling
one oftM8259A's interrupt request pins (lRO-IR7) high.
If the 8259A honors the request, its INT pin will go high,
driving the8086/8088's INTR pin high. Like the 8080A
and 8085A, the INTR pin of the 8086/8088 is 'asynchronous, thus it can receive an interrupt any time. The
8086/8088 can also accept or disregard requests on
INTR under software control using the STI (Set Interrupt)
or CLI (Clear Interrupt) instructions. These instructions
set or clear the interrupt-enabled flag IF. Upon
8086/8088 reset the IF flag is cleared, disabling external
interrupts on INTR. Beside the INTR pin, the 8086/8088
provides an NMI (Non-Maskable Interrupt) pin. The NMI
functions similar to the 8085A's TRAP; it can't be disabled or masked. NMI has higher priority than INTR.
Figure 4 shows an MCS·86 MAX Mode system interfacing with an 8259A on the Idcal bus. This MCS-86-8259A
configuration is also representative of an MCS-888259A configuration except for the data bus which is 16
bits for 8086 and 8 bits for 8088. In the MCS·86 system
the 8259A must be on the lower 8 bits of the data bus.
Note that the 8259A could also be interfaced on the
system bus.
Although there are some basic similarities, the actual
processing of interrupts with an 8086/8088 is different
than an 8080A or 8085A. When an interrupt request is
present and interrupts are enabled, the 8086/8088 enters
its Interrupt acknowledge machine cycle. The interrupt
acknowledge machine cycle pushes the flag registers
onto the stack (as in a PUSH F instruction). It then clears
the IF flag which disables interrupts. The contents of
I-:S"'VS=T"'EM'"'A""D"'DR=ES=S"'O"'US'"'&'"'ii!fE'"d, l~:~~ORY
A1
ADO.1SI----'M"'U"'LT!!!'P"'L"'EX"'ED"'A""D""DR,;;E"'SSJi"D"'A"'TA",,0"'US:!-,
I/L--'-S:::V=ST=E~M""DA=T""A=ou=s--"". TO MEMORY
,,-.~=~~~_,/ AND I/O
LOCK
8259A SELECT
-NMI
INTR
---,/
TO SLAVE 8259A
™S259AB••lc Configuration Example (8088 In Max. Mode)
Figura 4. MSC-88
A-140
AP-59
both the code segment and the instruction pOinter are
then also pushed onto the stack. Thus, the stack retains
the pre·interrupt flag status and pre·interrupt program
location which are used to return from the. service
routine. The 8086/8088 then issues the first of two INTA
pulses which signal the 8259A that the 8086/8088 has
honored ·its interrupt request. If the 8086/8088 is used in
its "MIN Mode" the INTA signal is available from the
8086/8088 on its INTA pin. If the 8086/8088 is used in the
"MAX Mode" the INTA signal is available via the 8288
Bus Controller INTA pin. Additionally, in the "MAX
Mode" the 8086/8088 LOCK pin goes low during the in·
terrupt acknowledge sequence. The LOCK signal can be
used to indicate to other system bus masters not to gain
control of the system bus during the interrupt acknowl·
edge sequence. A "HOLD" request won't be honored
while LOCK is low.
The 8259A is now ready to vector program execution to
the corresponding service routine. This is done during
the sequence of the two INTA pulses issued by the 80861
8088. Unlike operation with the 8080A or 8085A, the
8259A doesn't place a CALL instruction and the starting
address of the service routine on the data bus. Instead,
the first INTA pulse is used only to signal the 8259A of
the honored reql!est. The second INTA pulse·causes the
8259A to place a single interrupt·vector byte onto the
data bus. Not used ·as a direct address, this interrupt·
vector byte pertains to one of 256 interrupt "types" sup·
ported by the 8086/8088 memory. Program execution is'
vectored to the corresponding service routine by the
contents of a specified interrupt type.
All 256 interrupt types are located in absolute memory
locations 0 through 3FFH which make up the 80861
8088's interrupt-vector table. Each type in the interruptvector table requires 4 bytes of memory and stores a
code segment address and an instruction pOinter address. Figure 5 shows a block diagram of the interruptvector table. Locations 0 through 3FFH should be
reserved for the interrupt-vector table alone. Furthermore, memory locations 00 through 7FH (types 0-31) are
reserved for use by Intel Corporation for Intel hardware
and software products. To maintain compatibility with
present and future Intel products, these locations
should not be used.
-
3FFH
INTERRUPT TYPE 255
3FCH
3FBH
INTERRUPT TYPE 254
·•
•
3F8H
BH
INTERRUPT TYPE 2
8H
7H
INTERRUPTTYPE 1
4H
INTERRUPT TYPE 0
3H
OH
Figure 5. 8086/8088 Interrupt Vector Table
When the 8086/8088 receives an interrupt-vector byte
from the 8259A, it multiplies its value by four to acquire
the address of the interrupt type. For example, if the
interrupt-vector byte specifies type 128 (80H), the vectored address in 8086/8088 memory is 4 x 80H, which
equals 200H. Program execution is then vectored to the
service routine whose address is specified by the code
segment and instruction pOinter values within type 128
located at 200H. To show how this is done, let's assume
interrupt type 128 is to vector data to 8086/8088 memory
location 2FF5FH. Figure 6 shows two possible ways to
set values of the code segment and instruction poi nter
for vectoring to location 2FF5FH. Address generation
by the code segment and instruction pOinter is accomplished by an offset (they overlap). Of the total
20-bii address capability, the code segment can designate the upper 16 bits, the instruction pointer can
deSignate the lower 16 bits.
CS(MSB)
2FH
1FFH
CS(LSB)
FOH
1FEH
IP(MSB)
IP(LSB)
DOH
5FH
1FDH
1FCH
-
20H
CS(MSB)
CS(LSB)
DOH
IP(MSB)
IP(LSB)
FFH
5FH
1FFH
1FEH
~F,DH'
I
TYPE 128
1FCH
Figure 6. Two Examples 01 8086/8088 Interrupt Type 128 Vectoring
to Location 2FF5FH
When entering an interrupt service routine, those registers that are mutually used between the main program
and service routine should be saved. The best way to do
this is to "PUSH" each register used onto the stack immediately. The service routine can then "POP" each
register off the stack in the same order when it is completed.
Once the service routine is completed the main program
may be re-entered by using a IRET (Interrupt Return) instruction. The IRET instruction will pop the pre-interrupt
instruction pointer, code segment and flags off the
stack. Thus the main program will resume where it was
interrupted with the same flag status regardless of
changes in the service routine. Note especially that this
includes the state of the IF flag, thus interrupts are reenabled automatically when returning from the service
routine.
Beside external interrupt generation from the INTR pin,
the 8086/8088 is also able to invoke interrupts by software. Three interrupt instructions are provided: INT, INT
(Type 3), and INTO. INT is a two byte instruction, the second byte selects the interrupt type. INT (Type 3) is a one
byte instruction which select!! interrupt Type 3. INTO is
a conditional one byte Interrupt instruction which
selects interrupt Type 4 if the OF flag (trap on overflow)
is set. All the software interrupts vector program execution as the hardware interrupts do.
A-141
AP-59
sents oneof eight "daisy-chained" priority cells, one for
each IR input.
For further information on 8086/8088 interrupt operation
and internal interrupt structure refer to the MCS-86
User's Manual and the 8086.System Design application
note.
2_ 8259A FUNCTIONAL BLOCK DIAGRAM
A block diagram of the 8259A is' shown in Figure 7. As
can be seeri from this figure, the 8259A consists of eight
major blocks: the Interrupt Request Regl~ter (IRR), the
In-Service Register (ISR), the Interrupt Mask Register
(lMR), the Priority Resolver (PR), the cascade buffer/
comparator, the data bus buffer, and logic blocks for
control and read/write. We'll first go over the blocks
directly related to interrupt handling, the IRR, ISR, IMR,
PR, and the control logic. The remaining functional
blocks are'theri discussed.
2.1 INTERRUPT REGISTERS AND CONTROL LOGIC
Basically, interrupt requests are handled by three "cascaded" registers: the Interrupt Request Register (IRR) is
use to store all the interrupt levels requesting service;
the In-Service Register (lSR) stores all the levels which
are being serviced; and the Interrupt Mask Register
(IMR) stores the bits of the interrupt lines to be masked.
The Priority Resolver (PR) looks at the IRR, ISR and IMR,
and determines whether an INT should be Issued by the
the control logic to the processor.
Figure 8 shows conceptually how the Interrupt Request
(IR) Input handles an interrupt request and how the
various interrupt registers interact. The figure repre-
The best way to explain the operation of the priority cell
is to go through the sequence of internal events that
happen when an interrupt request occurs. However,
first, notice that the input circuitry of the priority cell
allows for both level sensitive and edge sensitive IR inputs. Deciding which method to use is dependent on the
particular application and will be discussed in more
detail later.
When the IR input is in an Inactive state (LOW), the edge
sense latch Is set. If edge sensitive triggering is
selected, the "Q" output of the edge sense latch will
arm the input gate.to the request latch. This input gate
will be disarmed after the IR input goes active (HIGH)
and the interrupt request has been acknowledged. This
disables the input from generating any further Interrupts untWit has returned low to re-arm the edge sense
latch. If level sensitive triggering is selected, the "a"
output of the edge sense latch is rendered useless. This
means the level of the IR input is in complete control of
interrupt generation; the Input won't be disarmed once
acknOWledged.
When an interrupt occurs on the IR input, it propagates
through the request latch and to the PR (assuming the
input Isn't masked). The PR looks althe incoming requests and the currently in-service interrupts to ascertain whether an interrupt should be issued to the processor. Let's assume ihat the request is the only one incoming and no requests are presently in service. The PR
then causes the control logic to pull the INT line to the
processor high.
PIN CONFIGURATION
cs
WR
vcc
.."
iii5
INTA
0,
IR7
D.
IR6
Os
IRS
D.
IR4
03
IR3
D.
IR2
·0,
IR1
Do
IRO
CASO
INT
CAS 1
SP/EN
GND
CAS 2
BLOCK DIAGRAM
DATA
BUS
CONTROL LOG Ie
BUFFER
PIN NAMES
°7- DO
DATA BUS (BI·DlRECTIONALI
RD
READ INPUT
WR
WRiTE INPUT
Ao
COMMAND SELECT ADDRESS
cs
CHIP SELECT
CAS1
CAS1-CASO
SP/EN
CASCADE LINES
SLAVE PROGRAM/ENABLE BUFFER
CAS'
INT
INTERRUPT OUTPUT
INTA
INTERRUPT ACKNOWLEDG.E INPUT
IRO-IR7
INTERRUPT REOUEST INPUTS
CASO
SP/EIiI _ _ _-'
Figure
i
~INTERNAL
.8259A Block Diagram and Pin Configuration
A-142
BUS
AP-59
LTIM BIT
TO OTHER PRIORITY CELLS
Oa EDGE
1 LEVEL
CLR ISA
=
ISR BIT
EDOE
SENse
~LA~T~CH~f--------t---+--+---<'ltjH-;;;:S~~1 SETISR
PRIORITV
RESOLVER
CONTROL
LOGIC
IR
NON·
MASKED
-I-[)o---+--------l>"K
POATD4
5
'"
LATCH
'"
4
+5 BATT
""_____+ ____
"15
14
'''-12 All
8205
RAMCS
T1
".
DECODER
I
J.
COlD-1
STAAT
0,",
I"
"------------------------1
Al
MC14049
A2
MC14013
f-_ _ _ _ _-'-""-j0 P~~T
A3 MC14528
Figure 26. Power Down Circuit - SBC 80/20 Interface
The fully nested mode for the 8259A is used in its initial
state to ensure the IRO always has the highest priority.
The remaining IR inputs can be used for any other purpose in the system. The only constraint is that the service routines must enable interrupts as early as possible. Obviously, this is to ensure that the power-down interrupt does not have to wait for service. If a rotating
priority scheme is desired, another 8259A could be
added as a slave and be programmed to operate in a
rotating mode. The master would remain in the initial
state of the fully nested mode so that the IRO still remains the highest priority input.
The software to support the power-down circuitry is
shown in Figure 27. The flow for each label will be
discussed.
After any system reset, the processor starts execution
at location OOOOH (START). The PFS status is read and
execution is transferred to CSTART if PFS indicates a
cold start (Le., someone is depressing the cold start
switch) or WSTART if a warm start is indicated (PFS
LOW). CSTART is the start of the user's program. The
Stack Pointers (SP) and device initialization were included just to remind the reader that these must occur.
The first EI instruction must appear after the 8259A has
received its initialization sequence. The 8259A (and
other devices) are initialized in the INIT subroutine.
When a power failure occurs, execution is vectored by
the 8259A to REGSAV by way of the jump table at
JSTART. The pre-power-down program counter is placed
on the stack. REGSAV saves the processor registers
and flags in the usual manner by pushing them onto the
stack. Other items, such as output port status, program-
mabie peripheral states, etc., are pushed onto the stack
at this time. The Stack Pointer (SP) could be pushed onto the stack by way of the register pair HL but the top of
the stack can exist anywhere in memory and there is no
way then of knowing where that is when in the power-up
routine. Thus, the SP is saved at a dedicated location in
RAM. It isn't really necessary to send an EOI command
to the 8259A in REGSAV since power will be removed
from the 8259A, but one is included for completeness.
The final instruction before actually losing power is a
HALT. This minimizes somewhat spurious transitions
on the various busses and lets the processor die
gracefully.
On reset, when a warm start is detected, execution is
transferred to WSTART. WSTART activates PFSR by
way of the 8255 (all outputs go low then the 8255 is initialized). In the power-down circuitry, PFSR clears the
PFS latch and removes the MPRO signal which then
allows access to the RAM. WSTART also clears the PFI
latch which arms the 8259A IRO input. Then the 8259A is
re-initialized along with any other devices. The SP is
retrieved from RAM and the processor registers and
flags are restored by popping them off the stack. Interrupts are then enabled. Now the power-down program
counter is on top of the stack, so executing a RETurn instruction transfers the processor to exactly where it left
off before the power failure.
Aside from illustrating the usefulness of the 8259A (and
the SBC-80120) in implementing a power failure protected microcomputer system, this application should
also point out a way of preserving the processor status
when using interrupts.
A-159
AP-59
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lflLL
lNlf
.;tmIl1Ll~l
105
IIJt.
1j1.iT
f1N:t
''lSc.liFI
LlI~tL!.
EI
luE
I'nW,I.'fT:.
le~
.1J:ErpPOGWT$Tflf:ISHE;;c.
11:10
1"
!HI
Figure 27. Power Down and Restart Software
5.2 78 LEVEL INTERRUPT SYSTEM
CAS BUS
The second application illustrates an interrupt structure
with greater than 64 levels for an 8080A or 8085A sys·
tem, In the cascade mode, the 8259A supports up to 64
levels with direct vectoring to the service routine, Ex·
tending the structure to greater than 64 levels requires
polling, using the poll command. A 78 level interrupt
structure is used as an illustration; however, the prin·
ciples apply' to systems with up to 512 levels,
To implement the 78 level structure, 3 tiers of 8259A's
are used, Nine 8259A's are cascaded in the master·slave
scheme, giving 64 levels at tier 2, Two additional
8259A's are connected, by way of the INT outputs, to
two of the 64 inputs, The 16 inputs at tier 3, combined
with the 62 remaining tier 2 inputs, give 78 total leyels,
The fully nested structure is preserved over all levels,
although direct vectoring is supplied for only the tier 2
inputs, Software is required to vector any tier 3 reo
quests, Figure 28 shows the tiered structure used in this
example, Notice that the tier 3 8259A's are connected to
the bottom level slave (SA7). The master·slaves are inter·
connected as shown in "Interrupt Cascading", while the
tier 3 8259A's are connected as "masters"; that is, the
SPIEN pins are pulled high and the CAS pins are left un·
connected, Since these 8259A~s are only going to be
used with the poll command, no INTA is required, there·
fore the INTA pins are pulled high,
A-160
~lt
SAOO
SAO
"'ITA
MO
IRO
'
SP07
INT
SA10
INTA
SP
INTA
SBOO
SAl
INTA
SSO
MASTER
M,
IR,
INT
SA17
INT
SA70
SP
SB07
INTA
SB10
SA7
INT
SS,
INTA
M7
'"7
INT
SA76
SA77
INT
Figure 28. 78 Level Interrupt Structure
SB17
AP-59
The concept used to implement the 78 levels is to
directly vector to all tier 2 input service routines. If a tier
2 input contains a tier 3 8259A, the service routine for
that input will poll the tier 3 8259A and branch to the tier
3 input service routine based on the poll word read after
the poll command. Figure 29 shows how the jump table
is organized assuming a starting location of 1000H and
contiguous tables for all the tier 2 8259A's. Note that
"SA35" denotes the IR5 input of the slave connected to
the master IR3 input. Also note that for the normal tier 2
inputs, the jump table vectors the processor directly to
the service routine for that input, while for the tier 2 in·
puts with 8259A's connected to their IR inputs, the proc·
essor is vectored to a service routine (i.e., S80) which
will poll to determine the actual tier 3 input requesting
service. The polling routine utilizes the jump table start·
ing at 1200H to vector the processor to the correct tier 3
service routine.
Each 8259A must receive an Initialization sequence
regardless of the mode. Since the tier 1 and 2 8259A's
are in cascade and the special fully nested mode is used
(covered shortly), all ICWs are required. The tier 3
8259A's don't require ICW3 or ICW4 since only polling
will be used on them and they are connected as masters
not in the cascade mode. The initialization sequence for
each tier is shown in Figure 30. Notice that the master is
initialized with a "dummy" jump table starting at OOH
since all vectoring is done by the slaves. The tier 3
devices also receive "dummy" tables since only polling
is used on tier 3.
As explained in "Interrupt Cascading", to preserve a
truly fully nested mode within a slave, the master 8259A
should be programmed in the special fully nested mode.
This allows the master to acknowledge all interrupts at
and above the level in service disregarding only those of
lower priority. The special fully nested mode is pro·
grammed in the master only, so it only affects the im·
mediate slaves (tier 2 not tier 3). To implement a fully
nested structure among tier 3 slaves some special
housekeeping software is required in all the tier·2·with·
tier·3·slave routines. The software should simply save
the state of the tier 2 IMR, mask all the lower tier 2 inter·
rupts, then issue a specific EOI, resetting the ISR of the
tier 2 interrupt level. On completion of the routine the
IMR is restored.
LOCATION
8259
CODE
1000 H
SAO
JMP
; SADa SERVICE ROUTINE
JMP
SA07
; SA07 SERVICE ROUTINE
JMP
SA10
; SAl a SERVICE ROUTINE
JMP
SAl7
; SA17 SERVICE ROUTINE
JMP
SA70
; SA70 SERVICE ROUTINE
JMP
JMP
sao
sal
; seo
sao
JMP
5800
; S800 SERVICE ROUTINE
JMP
sa07
; S807 SERVICE ROUTINE
sal
JMP
58'0
; 5810 SERVICE ROUTINE
JMP
SB17
; SB17 SERVICE ROUTINE
10le H
SAl
1020 H
COMMENTS
SADa
I03e H
; SA20-SAS7 SERVICE ROUTINES
10EO H
SA7
10F8 H
10FC H
1200 H
121CH
1220 H
123C H
POLL ROUTINE
; SBI POLL ROUTINE
Figure 29. Jump Table Organlzallon
INITIALIZATION SEQUENCE FOR 78 LEVEL INTERRUPT STRUCTURE
INITIALIZE MASTER
MINT:
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
A,15H
; ICWI,LTM=O,ADI=1,S=O,IC4=1
MPTA
;
;
;
;
;
;
;
A,OOH
MPTB
A.OFFH
MPT8
A,IOH
MPTB
MASTER PORT AO=O
ICW2, DUMMY ADDRESS
MASTER PORT AD = 1
ICW3, S7-SO = 1
MASTER PORT AD 1
ICW4, SFNM = 1
MASTER PORT AD = 1
=
; INITIALIZE SA SLAVES - X DENOTES SLAVE ID (SEE KEY)
SAXINT:
A,II
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
SAXPTA
A,10H
SAXPTB
AOXH
SAXPTB
A10H
SAXPTB
;
;
:
;
SEE KEY FOR ICW1, LTM=O. ADI=1, S=O,IC4=1
SA"X" PORT AO = 0
ICW2, ADDRESS MSB
SA"X" PORT AD= 1
; ICW3.SA 10
; SA"X" PORT AO= 1
: ICW4, SFNM=1
; SA"X" PORT AO= f
REPEAT ABOVE FOR EACH SA SLAVE
INITIALIZE
SBXINT
Figure 31 shows an example flow and program for any
tier 2 service routine without a tier 3 8259A. Figure 32
shows an example flow and program for any tier 2 ser·
vice routine with a tier 3 8259A. Notice the reading of the
ISR In both examples; this is done to determine whether
or not to issue an EOI command to the master (refer to
the section on "Special Fully Nested Mode" for further
details).
A-161
sa SLAVES -
X DENOTES 0 or 1 (DO
A,ISH
MVI
OUT
MVI
OUT
SBXPTA
A,OOH
SBXPTB
;
;
;
;
sao, REPEAT FOR SB1)
ICW1, LTM=O, ADI=1, S=1,IC4=0
sa"x" PORT AO=O
ICW2, DUMMY ADDRESS
SB"X" PORT AO=1
SA INITIALIZATION KEY
SA"X"
Q'(ICW1)
0
1
2
3
4
5
5
7
15
35
55
75
95
85
05
F5
JUMP TABLE START (H)
1000
1020
1040
1060
1080
10AO
1DCO
10EO
Figure 30; Initialization Sequence for 78 Lavel Interrupt Structure
AP-59
; SA"X" ROUTINE - GENERAL INTERRUPT SERVICE ROUTINE
; FOR TIER 2 INTERRUPTS WITHOUT TIER 3 8259A
SAX:
PUSH 0
; SAVE DE
PUSH B
PUSH H
PUSH PSW
;
;
;
;
EI
SAVE Be
SAVE HL
SAVE A, FLAGS
ENABLE INTERRUPTS
; SERVICE ROUTINE GOES HERE
01
.VI
OUT
.UI
OUT
IN
ANI
JZN
.VI
OUT
SAXRSR: POP
POP
POP
POP
EI
RET
; DISABLE INTERRUPTS
'"
; OCW2, NON·SPECIFIC EOI
: SA"X" PORT AD = 0
: OCW3, READ REGISTER, ISR
; SA"X" PORT AD '" 0
SAXPTA
A,OBH
SAXPTA
SAXPTA
; SA"X" PORT AO=O, SA"X"'SR
OFFH
A,DSH
: TEST FOR ZERO
; IF NOT ZERO, RESTORE STATUS
: OCW2. NON·SPECIFIC EOI
MA5PTA
; MASTER PORT AD '" 0
PSW
: RESTORE A, FLAGS
SAXRSR
H
; RESTORE HL
B
: RESTORE Be
o
: RESTORE DE
; ENABLE INTERRUPTS
: RETURN
Figure 31. Example Service Rouline for Tier 2 Interrupt (SA"X") without Tier 3 82S9A (SB"X")
: SB"X" ROUTINE - SERVICE ROUTINE FOR TIER 2
; INTERRUPTS WITH TIER 3 8259AS
sax:
PUSH 0
SAVE DE
PUSH B
SAVE BC
PUSH H
SAVE HL
PUSH PSW
SAVE A, flAGS
IN
SAXPTB
READ SA"X" IMR
MOV
D,A
SAVE
A,XXH
MASK SA"X" LOWER IR
MVI
OUT
SAXPTB
SA"X" PORT AD = 1
MVI
A,6X H
OCW2 SPECIFIC EOI SA"X"
OUT
SAXPT A
SA"X" PORT AD '" 1
LXI
H,1200H
: JUMP TABLE START
MVI
B,OOH
: CLEAR B
MVI
A,DCH
; OCW3, POLL COMMAND
; SB"X" PORT AO""O
OUT
SBXPTA
IN
SBXPTA; GET POLL WORD
ANI
D7H
: LIMIT TO 3 BITS
ADD
A
: GET TABLE OFFSET
ADD
A
MOV
C,A
; OFFSET TO C
DAD
B
; HL HAS TABLE ADDRESS
EI
: ENABLE INTERRUPTS
SB"X"RET ROUTINE - FOR EOI AND MASK RESTORE
AFTER SB"X" ROUTINE
SBXRET
01
MVI
OUT
.VI
OUT,
IN
ANI
JNZ
.VI
OUT
SBXRSR: MOV
OUT
POP
POP
POP
POP
EI
RET
A,20H
SBXPTA
A,OBH
SAXPTA
SBXPTA
OFFH
SBXRSR
A,2DH
MASPTA
A.O
SAXPTB
PSW
H
B
0
; DISABLE INTERRUPTS
: OCW2, NON SPECIFIC EOI
; SA"X" PORT AO=O
; ~f,~~' :~:~ :oE2~STER
Figure 32. Example Service Routine lor Tier 2 Interrupt (SA"X") with Tier 3 82S9A (SB"X")
A-162
ISR
SA"X" PORT AD", 0, ISR
TEST FOR ZERO
IF*O RESTORE IMR
OCW2, NON·SPECIFIC EOI
MASTER PORT AD '" 0
RESTORE SA"X" IMR
SA"X" PORT AO=1
RESTORE A, flAGS
RESTORE HL
RESTORE BC
RESTORE BC
; RESTORE DE
; RETURN
AP-59
5.3 TIMER CONTROLLED INTERRUPTS
In a large nurnber of controller type rnicroprocessor
designs, certain tirning requirernents rnust be irnple·
rnented throughout prograrn execution. Such tirne
dependent applications include control of keyboards,
displays, CRTs, printers, and various facets of industrial
control. These exarnples, however, are just a few of
rnany designs which require device servicing at specific
rates or generation of tirne delays. Trying to rnaintain
these tirning requirernents by processor control alone
can be costly in throughput and software cornplexity.
So, what can be done to alleviate this problern? The
answer, use the 8259A Prograrnrnable Interrupt Con·
troller and external tirning to interrupt the processor for
tirne dependent device servicing.
This application exarnple uses the 8259A for tirner con·
trolled interrupts in an 8086 systern. External tirning is
done by two 8253 Prograrnrnable Interval Tirners. Figure
33 shows a block diagrarn of the tirner controlled interrupt circuitry which was built on the breadboard area of
an SDK-86 (systern design kit). Besides the 8259A and
the 8253's, the necessary 1/0 decoding is also shown.
The tirner controlled interrupt circuitry interfaces with
the SDK-86 which serves as the vehicle of operation for
this design.
A short overview of how this application operates is as
follows. The 8253's are prograrnrned to generate interrupt requests at specific rates to a nurnber of the 8259A
IR inputs. The 8259A processes these requests by interrupting the 8086 and vectoring prograrn execution to the
appropriate service routine. In this exarnple, the
routines use the· SDK·86 display panel to display the
nurnber of the interrupt level being serviced. These
routines are rnerely for dernonstration purposes to show
the necessary procedures to establish the user's own
routines in a tirner controlled interrupt scherne;
Let's go over the operation starting with the actual interrupt tirning generation which is done by two 8253 Prograrnrnable Interval Tirners (8253 #1 and 8253 #2). Each
8253 provides three individual 16-bit counters (counters
0-2) which are software prograrnrnable by the processor. Each counter has a clock input (ClK), gate input
(GATE), and an output (OUT). The output signal is based
on divisions of the clock input signal. Just how or when
the output occurs is deterrnined by one of the 8253's six
prograrnrnable rnodes, a prograrnrnable 16-bit count,
and the state of the gate input.
Figure 34 shows the 8253 tirning configuration used for
generating interrupts to the 8259A. The SDK·86's PCLK
(peripheral clock) Signal provides a 400 ns period clock
to ClKO of 8253 #1. Counter 0 is used in rnode 3 (square
wave rate generator), and acts as a prescaler"to provide
the clock inputs of the other counters with II 10 rns
period square wave. This 10 rns clock period rnade it
easy to calculate exact tirnings for the other counters.
Counter 2 of the 8253 #1 is used in rnode 2 (rllte generator), it is prograrnrned to output a 10 rns pulse for every
200 pulses it receives (every 2 sec). The output of
counter 2 causes an interrupt on IR1 of the 8259A. All
the 8253 #2 counters are used in rnode 5 (hardware triggered strobe) in which the gate input initiates counter
operations. In this case the output of 8253 #1 counter 2
controls the gate of each 8253 #2 counter. When one of
the 8253 #2 counters receive the 8253 #1 counter 2 output pulse on its gate, it will output a pulse (10 rns in
duration) after a certain preprograrnrned nurnber of
clock pulses have occurred. The prograrnrned nurnber of
clock pulses for the 8253 #2 counters is as follows: 50
pulses (0.5 sec) for counter 0, 100 pulses (1 sec) for
counter 1, and 150 pulses (1.5 sec) for counter 2. The
outputs of these counters cause interrupt requests on
IR2 through IR4 of the 8259A. Counter 1 of 8253 #1 is..
used in rnode 0 (interrupt on terrninal count). Unlike the
other rnodes used which initialize operation autornatically or by gate triggering, rnode 0 allows software
controlled counter initialization. When counter 1 of 8253
#1 .is set during prograrn execution, it. will count 25
clocks (250 rns) and then pull its output high, causing an
interrupt request on IRO of the .8259A. Figure 35 shows
the tirning generated by the 8253's which cause interrupt request on the 8259A IRinputs.
EACH DEVICEVcc'" +5V,GND - ~
Flg.ure 33. Timer Controlled Interrupt Circuit on SDK 86 Breadboard Area
A-163
AP-59
GATE1 y+5V
elKl
GATEO
I
y+sv
MODE3
I
lOUT
CLK2
a
J
1
MODEO
GATE27+ SV
8253"
COUNTERO
I c~~~~~~ Ioun
I
I
IOUT2
8253111
I C~UONDTi~ I
2
(10 ms)
I
GATEa
CLKo.1
I
1
C~~~~~~ 0
MOOES
I
aUTO
I
GATE1
I c~~~~~~ loun
I
I
elK1
1
MOO.S
GATE2
elK.:!.1 cJ~~;~~ 2
I
OUT2
T
IR4
MODE 5
Figure 34. 8253 Timing Configuration lor Timer Controfled Interrupts
82531t1
\
IRa
COUNTER 1
82531t2
COUNTERO
u
u
Ir---u
u
'
II
U
------,U,--------,Ur- ------...,U
------"U,.-------...,U
c~~~~:~ 1 I\-I
C~~~~~~.2
\'\-,
I
I
!
I
I
I
I
1
I
!
I
'01
r
IR,
IR3
llR4
I
250 ms PER DIVISION
(EACH SMALL PULSE IS 10 ms IN DURATION)
Figure 35. 8259A IR Input Signal From 8253S
There are basically two methods of timing generation
that can be used in a timer controlled interrupt struc·
tu're: dependent timing and independent timing. Depen·
dent timing uses a single timing occurrence as a reference to base other timing occurrences on. On the other
hand, independent timing has no mutual reference be·
tween occurrences. 'Industrial controller type applica·
tions are more apt to use dependent timing, whereas in·
dependent timing is prone to individual device control.
Although this application uses primarily dependent tim·
ing, independent timing is also incorporated as an
example. The use of dependent timing can be seen back
in Figure 34, where timing for IR2 through IR4 uses the
IR1 pulse 3
rot.
; JUMP IF DISPLAY IS UNAVAILABLE
B4
JB
WAIT79
' ; DIGlT 8
AL, 87H
B5
MOV
,'.,
DX,AL
136
OUT
[lX,8FFE8H
' ; 8279 DATA WORD
137
MOV
MOV
,; CHARACTER "1'
AL,06H
138
[lX,AL
139
OUT
.. ; 8279 COI'II'IANI) WORD
DX,8FFEAH
149
HOY
MOV
AL,86H
; DIGIT 7
141
DX,AL
142
OUT
[lX, !lFFE8H
' ; 82i'9 DATA WORD
143
MOV
AL,59H
; CHARfl:TER "R"
MOV
144
DX,AL
145
OUT
; ENABLE UlTERRUPTS
STI
146
147 ;'
148
DUMMY PROGRAI'I
149
159
" :i51 DUI'IMY: JMP
; WAIT FOR INTtRRUPT
DUItIY
152
'153
AXTEI'IP,AX '
; SAVE AX
154 SAVE: MOV
' '; POP CfLL RETURN ADDRESS
AX
155
POP
STACK1,AX
; SAVE CALL RETURN AOOI<~S
156
MOV
fIX, AXIDIP
;RESTORE AX
I'tOV
157
' ; SAYE PROCESS~ STATUS
AX
158
PUSH
159
PUSH
BX
"',(',
009F
99A2
OOA4
OOA5
eaRS
000R
110AB
9I!AD
90AE
8080
BA09FF
8013
EE
BA9lFF
8048
EE
B003
EE
80E0
EE
0081 BAEAFF
0084 8900
eeu EE
0087 EC
eOO8 D0C8
98BA 72FB
OOBC 80S7
90BE EE
00BF BAEBFF
99C2BOO6
OOC4 EE
00C5 BAEAFF
OOC8 B086
99CA EE
90CB BAEBFF
OOCE B950
OOD8 EE
0001 FB
9002 EBFE
0004
0007
98D8
99DB
000E
OODF
A30200
58
A3!l91!9
A19200
59
53
"
'
. ".
",'
A-170
AP-59
11CS-86
ASSEMBLE~:
LOC OBJ
OOEO
OOEl
130E2
130E3
a0E4
90E5
OOE6
0eE7
!leEA
00EB
~1
52
55
56
57
1E
06
A1000(J
50
n
OOEC 53
BeED A3000B
00FB 07
e0F11F
OOF2 SF
B0n 5E
e0F4 50
0BF5 5A
00F6 59
e0F7 5B
a0F8 58
00F9 A30200
00FC A10000
9!1FF 50
0100 A1B20B
f.ll~3 (;3
0104
(j107
81(jA
810D
01eE
0111
91B
0114
8117
ESCDFF
BAEAFF
Aewe0
EE
BAEBFF
B080
EE
E8D5FF
CF
TCI59A
LINE
SOURCE
160
161
162
163
164
165
166
167
168
169
170
171 RI,STOR:
172
173
174
175
176
1f'('
178
179
180
181
132
133
134
185
186
187
183
189 .,
190
191 INTR72:
192
193
194
195
196
197
198
199
280
201
202
PUSH
PIJSH
PUSH,
PUSH
PIJSH
PUSH
PUSH
~10V
c:~
DX
BP
51
DI
OS
E5
AX, STACK1
PUSH
RET
AX
,; RESTORE CALL RETUf-<~-
Figure 6. Non Bus Vectored Interrupt Implementation
A-ISS
en,
W
Z
::l
AP;'28A
8US MASTER
BUS SLAVE
INTERRUPT
STROBE
MASTER CPU
(lORCI
INTRI
DATA
BU~
lowe I)
-
,; R
765432101
INT
PROGRAMMABLE INTERRUPT
CONTROLLER, .
CONTROLLER
L-...i..-
INTERRUPT
REQUEST
FLlPFLOP
~
PROGRAMMABLE INTERRUPT
1
0-7
DATO/·Tt
•
OR
FROM
MASTER
-
-1-- -
INTERRUPT ACKNOWLEDGE (lNTA/)
.,
tNT
DATO/-7.!
-
INTERRUPT REOUEST (INTx!)
INTERRUPT CODe (ADRS/- ACRAl)
INTERRUPTVECTQR ADDRESS (DATA BUS)
MUlTlDUS :rIMING
INTRI
~_,
____~--------------~r-
INTA/,
~1L..-_----I1
ADR8/A
______~~______~______-J){~__~__
DATO/·J
'N_T_R_X_AO_O_R_ES_S____
________________________________~----'x,
__J)(~________________________
nESTAnTO
){~____________________....._
XACKI
BUS LOCKI
*------\
'
,
/
* NON MUL TIBUS SIGNAL
''-----'-'----------'
Figure 7. B!"s Vectored Interrupt Logic ,(With 2 INTAI Timing Diagram)
When an interrupt.request from the MULTIBUS
interrupt lines INTOI . INT7 I occurs, the interrupt
control logic on the bus master interrupts its
processor. The processor on the bus master
generates an INTAI command which freezes the
state of the interrupt logic on the MULTIBUS
slaves for priority resolutiop. The bus master also
locks (retains the bus between bus cycles) -the
MULTIBUS ,control lines to guarantee itself
consecutive bus cycles. After the first INTAI
command, the bus master's interrupt control logic
puts an in,terrupt code on to the MULTIBUS
address lines ADR81 - ADRA/. The interrupt code
is the address of the highest priority active interrupt request line. At this point in the Bus Vectored
Interrupt procedure, two different sequences could
take place. The difference occurs, because the
MULTI BUS specification can support masters
which generate one additional INTAI (8086
masters) or two additional INTA/s (8080A and
8085masters).
,If the bus master generates one additional INTA/,
this second INTAI causes the bus slave interrupt
control logic to transmit an interrupt vector 8-bit
pointer on the MULTIBUS data lines. The vector
pointer is used by the bus master to determine the
memory address of the interrupt service r~lUtine.
If the bus ,master generates two additional
INT AI s, these two INTAI commands allow the
A-I 86
Ap·28A
highest priority master is then connected to the
priority input (BPRN/) of' the next lower priority
master, and so on. Any master generating a bus
request will set its BPROI signal high to the next
lower priority master, Any master seeing a high
signal on its BPRN/line will sets its BPRO/line
high, thus passing down priority information to
lower priority masters. In this implementation,
the bus request line (BREQ/) is not used outside of
the individual masters. A limited number of
masters can be accommodated by this technique,
due to gate delays through the daisy chain. Using
the current Intel MULTIBUS controller chip on
the master boards up to 3 masters may be accommodated if a BCLKI period of 100 ns is used. If
more bus masters are required, either BCLKI must
be slowed or a parallel priority technique used.
bus slave to puta two byte interrupt vector address
on to the MULTIBUS data lines (one byte for each
INTA/). The interrupt vector address is used by
the bus master to service the interrupt.
The MULTIBUS specification provides for only
one type of Bus Vectored Interrupt operation in a
given system. Slave boards which have an 8259
interrupt controller are only capable of 3 INTAI
operation (2 additional INTA/s after the first
INTA/). Slave boards with the 8259A interrupt
controller are capable of either 2 INTAI or 3
INTAI operation. All slave boards in a given
system must operate in the same way (2 INT AI s or
3 INTA/s) if Bus Vectored Interrupts are to be
used. However, the MULTIBUS specification
does provide forBus Vectored Interrupts and Non
Bus Vectored Interrupts in the same system.
Parallel Priority Technique
In the parallel priority technique, the priority is
resolved in a priority resolution circuit in which
the highest priority BREQI input is encoded with
a priority encoder chip (74148). This coded value is
then decoded with a priority decoder chip (74S138)
to activate the appropriate BPRNI line. The
BPROI lines are not used in the. parallel priority
scheme. However, since the MULTIBUS backplane contains a trace from the BPRNI signal of'
one card slot to the BPROI signal of the adjacent
lower card slot, the BPROI must be disconnected
from the bus on the board or the backplane trace
must be cut. A practical limit of sixteen masters
can be accommodated. using the parallel priority
technique due to physical bus length limitations.
Figure 9 contains the schematic for a typic;ll
parallel resolution network. Note that the parallel
priority resolution network must be externally
supplied.
MULTIBUS Multi-Master Operation - The
MULTIBUS system bus can accommodate several
bus masters on the same system, each one taking
control of the bus as it needs to affect data trans·
fers. The bus masters request bus control through
a bus exchange sequence.
Two bus exchange priority resolution techniques
are discussed, a serial technique and a parallel
technique. .Figures 8 and 9 illustrate these two
techniques. The bus exchange operation discussed later is the same for both techniques.
Serial Priority Technique
_Serial priority resolution is accomplished with a
daisy chain technique (see Figure 8). The priority
input (BPRN/) of the highest priority master is
tied to ground. The pri~rity output (BPRO/) ofthe
LOWEST
PRIORITY
MASTER
HIGHEST
PRIORITY
MASTER
BPRNI
BPROI
Figure 8. Serial Priority Technique
A-IS7
AP-28A
NO. ,
NO ,
PRIORITY
PRIORITY
r-<
BPRN,
,------
SPANI
,J
.us
f --<
~
SPRNI
BREDI
PRIORITy
RESOLVER
OTHER
NO 8
PRIORITY
(LOWEST>
NO 1
PRIORITY
IHIGHEST!
:
R
,4;;138
, P-l
4 ~
P-- J
,p,
J
OTHER
MASTER
OUTPUTS
0
Figure 9. Parallel Priority Technique
MULTIBUS Exchange Operation - A timing
diagram for the MULTIBUS exchange operation
is shown in Figure 10. This implementation
example uses a parallel resolution scheme, however, the timing would be basically the same for
the serial resolution scheme.
for master A are disabled. Master B must take
control of the bus with the next trailing edge of
BCLKI to complete the bus exchange. Master B
takes control by activating BUSY I and enabling
its .drivers.
It is possible for master A to retain control of the
bus and prevent maste'r B from getting control.
Master A activates the Bus Override (or Bus Lock)
signal which keeps BUSY I active allowing control of the bus to stay with master A. This
guarantees a master consecutive bus cycles for
software or hardware functions which require
exclusive, continuous access to the bus.
In this example, master A has been assigned a
lower priority than master B. The bus exchange
occurs because master B generates a bus request
during a time when master A has control of the
bus.
The exchange process begins when master B
requires the bus to access some resource such as an
I/O or memory module while master A controls the
bus. This internal request is synchronized with
the trailing edge (high to low) of BCLKI to
generate a bus request (BREQ/). The bus priority
resolution circuit changes the BPRNI signal from
active (low) to inactive (high) for master A and
from inactive to active for master B. Master A
must first complete the current bus command if
one is in operation. After master A completes the
command, it sets BUSY I inactive on the next
trailing edge of BCLK/. This allows the actual bus
exchange to occur, because master A has relinquished control of the bus, and master B has been
granted its BPRN/. During this time, the drivers
A-188
Note that in systems with only a single master it is
necessary to ground the BPRN I pin of the master,
if slave boards are to be accessed. In single board
systems which use a CPU board capable of Bus
Vectored Interrupt operation, the BPRNI pin must
also be grounded.
In a single master system bus transfer efficiency
may be gained if the BUS OVERRIDE signal is
kept active continuously. This permits the master
to maintain control of the bus at all times, therefore saving the overhead of the master reacquiring
the bus each time it is needed.
The CBRQI line may be used by a master in
control of the bus to determine if another master
AP-28A
_I
'SCY
1-
-·I'swl-
BClKf
TRANSFER
REQUEST I
(LOWI
BREDI
(LOWI
MAS TEA A
SPANI
PRIORITY
RESOLUTION
SHOWN
HERE
TRANSFER
REOUEST I
MASTER B
BREDI
I
SPAN/
MASTER B
ON BUS
• NOTE: BUS PRIORITY MUST BE RESOLVED
WITHIN ONE BCLKI PERIOD.
BUSY I
HIGH IMPEDENCE
STATE
ADDRESS/
ACTIVE STATE
COMMAND/
ACTIVE
HIGH IMPEDENCE
MASTER A
DRIVER
EXCHANGE
OF BUS
SHOWN
ENABLE!
HERE
HIGH IMPEDENCE
ADDRESSI
HIGH IMPEOENCE
MASTER B
COMMAND!
DRIVER
ENABLE I
Figure 10. Bus Control Exchange Operation
Note that except for the BUS OVERRIDE state, no
single master may keep exclusive control' of the
bus. This is true because iUs impossible for the
CPU on a inaster to require continuous access to
the bus. Other lower priority masters will always
be able to gain access to the bus betweenaccesses
of a higher priority master.
requires the bus. If a master cunently in control of
the bus sees the CBRQI line inaCtive, it will
maintain control of the bus between adjacent bus
accesses. Therefore, when a bus access is required,
the master saves the overhead of reacquiring the
bus. If a current bus master sees the CBRQI line
active, it will then relinquish control of the bus
after the current bus access and will contend for
the bus with the other master(s) requiring the bus.
The relative priorities of the masters will determine which master receives the bus.
Power Fail Considerations - The MULTIBUS
P2 connector signals provide a means of handling
power failures. The circuits required for power
A-189
AP-28A
AC LINE
115VAC
AClO
+ SV Vee
PFINt
PFSNI
MPROI
IeI
o ns MIN
.-100 ns M1N---.j
\\\\\\\\\\\\\\\1
INITI
j..-- 5 ms MIN------'I
POWER DOWN
POWER UP
Figure 11. Power Fall Timing Sequence
failure detection and handling are optional and
must be supplied by the user. Figure 11 shows
the timing of a power fail sequence.
a power up routine which resets the latch (PFSR/),
restores the environment, and resumes execution.
Note that INITI is activated only after DC power
has risen to the regulated voltage levels and must
stay low for five milliseconds minimum before the
system is allowed to restart. Alternatively,INITI
may be held low through an open collector device
by MPROI.
The power supply monitors the AC power level.
When power drops below an acceptable value, the
power supply raises ACLO which tells the power
fail logic that a minimum of three milliseconds will
elapse before DC power will fall below regulated
voltage levels. The power fail logic sets a sense
latch (PFSN I) and generates an interrupt (PFIN I)
to the processor so the processor can store its
environment. After a 2.5 millisecond timeout, the
memory protect signal (MPRO/) is asserted by the
power fail logic preventing any memory activity.
As power falls, the memory goes on standby
power. Note that the power fail logic must be
powered from the standby source.
How the power failure equipment is configured is
left to the system designer. The backup power
source may be batteries located on the memory
boards or more elaborate facilities located off·
board. The location of the power- fail logic
determines which MULTIBUS powerfaillines are
used. Pins on the P2 connector have been specified
for the power failure functions for use as needed.
As the AC line revives, the logic voltage level is
monitored by the power supply. After power has
been at its operating level for one millisecond
minimum, the power supply sets the signal ACLO
low, beginning the restart sequence. First, the
memory protect line (MPRO/) then the initialize
line (INIT/) become inactive. The bus master now
starts running. The bus master checks the power
fail latch (PFSN/) and, ifitfinds it set, branches to
To further clarify the location and use of the power
fail circuitry, an example of a typical power fail
system block diagram is shown in Figure 12. A
single board computer and a slave memory board
are contained in the system. It is desired to power
the memory circuit elemen ts of the memory board
from auxiliary power. The single board computer
will remain on the main power supply. To ac·
complish this, user supplied power fail logic and
A-190
AP-28A
DC Requirements - The drive and load charac·
teristics of the bus signals are listed in Appendix
C. The physical locations of the drivers and loads,
as well as the terminating resistor value for each
bus line, are also specified. Appendix D contains
the MULTIBUS power specifications.
MUL TIBUS™ Slave Interface
Circuit Elements
* USER
SUPPLIED
Figure 12. Typical Power Fail System Block Diagram
an auxiliary power supply have been included in
the system.
The single board computer is powered from the PI
power lines and accesses the P2 signal lines
PFIN/, PFSNI and PFSRI (only the P2 signal
lines used by a particular functional block are
shown on the block diagram). The PFSRI line is
driven from two sources: a front panel switch and
the single board computer. The front panel switch
is used during normal power·up to reset the power
fail sense latch. The single board computer uses
the PFSRI line to reset the latch during a power·up
sequence after a power failure. Current single
board computers must access the PFSNI and
PFSRI signals either directly with dedicated
circuitry and a P2 pin connection or through the
parallel I/O lines with a cable connection from the
parallel 110 connector to the P2 connector.
The slave memory board uses both the PI and P2
power lines, the P2 power lines are used (at all
times) to power the memory circuit elements and
other support circuits, the PI power lines power all
other circuitry. In addition, the MPROI line is
input and used to sense when memory contents
should be protected.
The power fail logic contains the power fail sense
latch, and uses the PFSRI and ACLO lines for
inputs and the PFINI PFSN/, and MPROI lines
for outputs. The power fail logic must be powered
by the P2 power lines.
A-191
There are three basic elements of a slave bus
interface: address decoders, bus drivers, and
control signal logic. This section discusses each of
these elements in general terms. A description of a
detailed implementation of a slave interface is
presented in a later section ofthis application note.
Address Decoding - This logic decodes. the
appropriate MULTIBUS address bits into,RAM
requests, ROM requests, or 110 selects. Care must
be taken in the design of the address decode logic
to ensure flexibility in the selection of base address
assignments. Without this flexibility, restrictions
may be placed upon various system configura·
tions. Ideally, switches and jumper connections
should be associated with the decode logic to
permit field modification of base address assign·
ments.
The initial step in designing the address decode
portion of a MULTIBUS interface is to determine
the required number of unique address locations.
This decision is influenced by the fact that
address decoding is usually done in two stages.
The first stage decodes the base address, pro·
ducing an enable for the second stage which
generates the actual device selects for the user
logic. A convenient implementation of this two
stage decoding scheme utilizes a pair of decoders
driven by the high order bits of the address for the
first stage and a second decoder for the low order
bits of the address bus. This technique forces the
number of unique address locations to be a power
of two, based at the address decoded by the first
stage. Consider the scheme illustrated in Figure
13.
As shown in Figure 13, the address bits A4 . ABare
used to produce switch selected outputs ofthe first
stage of decoding. The lout of 8 binary decoders
AP-28A
have been used. The top decoder decodes address
lines A4 - A 7, and the bottom decoder decodes
address lines A8' A B. If only address Jines AO -A 7
are being used for device selection, as in the case of
I/O port selection in 8-bitsystems, the bottom
decoder may be disabled by setting switch 82 to the
ground position. Address lines A7 and A B drive
enable inputs E2 or E3 of the decoders. The
address lines AO - A3 enter the second stage
address decoder to produce 8 user device selects.
The second stage decoder must first be enabled by
an address that corresponds to the switch-selected
base address.
devices are simultaneously selected, and because
the addressing within such a system is restricted
by the extent of the address space occupied by such
a scheme.
Address decoding must be completed before the
arrival of a command. Since the command may
become active within 50 ns after stable address,
the decode logic should be kept simple with a
minimal number of layers of logic. Furthermore,
the timing is extremely critical in systems which
make use of the inhibit lines.
In systems where the user designed logic must
place data onto the MULTIBUS data lines, threestate drivers are required. These drivers should be
enabled only when a memory read command
(MRDC/) or an I/O read command (lORC/) is
present and the module has been addressed.
A linear or unary select scheme in which no binary
encoding of device address (e.g., address bit AO
selects deviCe 0, address bit A 1 selects device 1,
etc.) is performed is not recommended because the
scheme offers no protection in case multiple
oSo
OS,
os,
-
E1
05 3
OS4
oss
OS6
os,
Data Bus Drivers - For user designed logic
which simply receives data from the MULTIBU8
data lines, this portion of the bus interface logic
may only consist of buffers. Buffers are required
to ensure that maximum allowable bus loading is
not exceeded by the user logic.
When both the read and write functio'ns are required, parallel bidirectional bus drivers (e.g., Intel
8226,8287, etc.) are used. A note of caution must be
included for the designer who uses this type of
device. A problem may arise if data hold time
requirements must be satisfied for user logic
following write operations. When bus commands
are used to directly produce both the chip select for
the bidirectional bus driver and a strobe toa latch
in the user logic, removal of that signal may not
provide the user's latch with adequate data hold
time. Depending on the specifics of the user logic,
this problem may be solved by permanently
enabling the data buffer's receiver circuits and
controlling only the direction of the buffers.
SECOND 5T AGE USER
DEVICE SELECTS
SWITCH
Sl
8205
DECODER
E1
A8===========~AO
Ag
AA
AB
A1
A2
E2,E3
8205
;'ECOOER
Control Signal Logic - The.control signal logic
consists of the circuits that forward the I/() and
memory read/write commands to their respective
destinations, provide the bus with a transfer
acknowledge response, and drive the system
interrupUines.
Bus Command Lines
r
SWITCH
S,
FIRST STAGE BASE
ADDRESS DECODER
Figure 13~ Two Stage Decoding Scheme
The MULTIBU8 information transfer protocol
lines (MRDC/, MWTC/, lORD/_ and lOWC/)
should be buffered by devices with very high speed
switching. Because the bus DC requirements
specify that each board may load these lines with
2.0 mA, Schottky devices are recommended. LS
devices are not recommended due to their poor
noise immunity. The commands should be gated
A-192
AP-28A
with a signal indicating the base address has been
decoded to generate read and write strobes for the
user logic.
is an 110 interface which will permit a 16-bit
master to perform 8 or 16 bit data transfers. 8-bit
masters may also use the 8/16-bit version of the
design example to perform 8-bit data transfers.
Transfer Acknowledge Generation
The 8-bit version of the design example may be
used by both 8 or 16-bit masters, but will only
perform 8-bit data transfers. It does not contain
the circuitry required to perform 16-bit data
transfers.
The user interface transfer acknowledge generation logic provides a transfer acknowledge response, XACK/, to notify the bus master that write
data provided by the bus master has been accepted
or that read data it has requested is available on
the MULTIBUS data lines. XACKI allows the bus
master to conclude its current instruction.
Both the 8/16-bit version and the 8-bit version of
the design example were implemented on an iSBC
905 prototype board. The schematics for each of
the examples are given in Appendices F and G.
Since XACKI timing requirements depend on both
the CPU of the bus master and characteristics of
the user logic, a circuit is needed which will provide
a range of easily modified acknowledge responses.
Functional/Programming Characteristics
The transfer acknowledge signals must be driven
by three-state drivers which are enabled when the
bus interface is addressed and a command is
present.
This section describes the organization of the
slave interface from two points of view, the
functional point of view and the programming
characteristics. First, the principal functions
performed by the hardware are identified and the
general data flow is illustrated. This point of view
is intended as an introduction to the detailed
description provided in the next section; Theory of
Operation. In the second point of view, the
information needed by a programmer to access the
slave is summarized.
Interrupt Signal Lines
The asynchronous interrupt lines must be driven
by open collector devices with a minimum drive of
16 mA.
In a typical Non Bus Vectored Inter"upt system,
logic must be provided to assert and latch-up an
interrupt signal. In addition to driving the
MULTIBUS interrupt lines, the latched interrupt
signal would be read by an 110 operation such as
reading the module's status. The interrupt signal
would be cleared by writing to the status register.
Functional Description - The function of this
110 slave is to provide the bus interface logic for
general purpose 110 functions and for two Intel
8255A Parallel Peripheral Interface (PPI) devices.
Eight device selects (port addresses) are available
for general purpose 110 functions. One of these
device select lines is used to read and reset the state
of an interrupt status flip-flop, the other seven
device selects are unused in this design. An
additional eight 110 device port addresses are
used by the two 8255A devices; four 110 port
addresses per 8255A (three 110 port address for
the three parallel ports A, B, and C and the fourth
110 port address for the device control register).
III. MULTIBUSTM SLAVE DESIGN
EXAMPLE
A MULTIBUS slave design example has been
included in this application note to reinforce the
theory previously discussed. The design example
is of general purpose 110 slave interface. This
design example could easily be modified to be used
as a slave memory interface by buffering the
address signals and using the appropriate
MULTIBUS memory commands. In addition, to
help the reader better understand an application
for an 110 slave interface, two Intel 8255A Parallel
Peripheral Interface (PPI) devices are shown connected to the slave interface.
Figure 14 contains a functional block diagram of
the slave design example. This block diagram
shows the fundamental circuit elements of a bus
slave: bidirectional data bus driverslreceivers,
address decoding logic and bus control logic. Also
shown is the address decoding logic for the low
order four bits, the interrupt logic which is selected
by this decoding logic, and the two 8255A devices.
The design example is shown in both 8/16-bit
version and an 8-bit version. The 8/16-bit version
A-193
AP-28A
8
:~i~ -<---ILITC----~---'4
DO ,
ADA4/-----fL~'
ADRBI _ _
+----.-'
BASE ADDA SELECT
IORDI
IDWATI
'XACKI
- - - I CDNTADLh-,--.
----,--1
LOGIC
port addresses XXI. - XX7 are not used in this
example. Port addresses XXB - XXF are used for
accessing the PPIs. If port addresses XXB - XXF
are selected, then ADROI is used to specify which
of two PPIs are selected. If the address is even
(XXB, XXA, XXC, or XXE) then one PPI is selected;
If the address is odd (XX9, XXB, XXD, or XXF'),
then the other PPI is selected. ADRll and ADR21
are connected directly to the PPIs. Table L
summarizes the 110 port addresses of the slave
design example. Note that if a 16-bit master is
used, it is possible to access the slave in a byte or
word mode. If word access is used with port
address XXB, XXA, XXC, or XXE, then 16 bit
transfers wilf occur' between the PPIs and the'
master. These 16 bit transfers occur because an
even address has bel,ln specified and the MULTI·
BUS BHEN/sig'nal indicates that a 16-bit
transfer is'requested.
ADI
Theory' of Operation
t----WRTI
1---_
SO ENABLE!
In the preceding section, each of the slave design
example functional blocks was identified and
briefly explained. This section explains how these
functions are implemented. For detailed circuit
information, refer to the schematics in Appendices
F and G. The schematic in Appendix F is on a
foldout page so that the following text may easily
be related, to the schematic.,
16
DATOl - ~'--'-''-I
OATF!
·ON-BOARD DATA BUS 00 - OF
Figure 14.' MULTIBUS'· Slave Design Example,
Functional Block Diagr!lm
The discussion of the theory of operation is divided
into five segments, each of which, discusses' a
different funCtion performed by the MULTIBUS
slave design example. The five segments are:
Programming Characteristics ,..... The slave
design example provides, 16 110 port addresses
which may be accessed by user, software. The
base address of the 16 contiguous port addresses
is selected by wire wrap connections on the prototype board. The wire wrap ,connections specify
address ,bits ADR41 - ADRBI, They allow, the
selection of a base address on any 16 byte
boundary. Twelve address bits (ADRO/- ADRB/)
are used since 16-bit (BOB6 based) masters use 12
bits to specity I/O port addresses. If an B bit (BOBO
or BOB5 based) master is used with this slave board,
the high order address bits (AD RBI -ADRB/)must
not be used by the decoding circuits; a wire wrap
jumper position (ground position) is provided for
this_
'
1. ' Bus address decoding
2. Data buffers
3. Control signals
4. Interrupt logic
, 5. PPI operation
Each of these topics are discussed with rega~d to
the 8/16-bit version' ,of the design example;
followed by a discussion of the circuit elements
which are required by the B-bit version of the
interfa~e.
"
,
The 16 110 port addresses are divided into two
groups'ofB port addresses by decoding address line
ADR3/. Port addressesXXO- XX7 are used for
general 1/0 functions (XX indicates any hexidecimal digit combination). Port address XXO is
used for accessing the interrupt status flip:flop and
Bus Address Decoding - Bus address decoding
is performed by two B205 1 out ofB binary d~coders.
One decoder (A3) decodes address bits ADRBi' :
ADRB/, and the second decoder (A2) decodes
address bits ADR41 - ADR7 I. The base address
A-194
AP-28A
Table 1
SLAVE DESIGN EXAMPLE PORT ADDRESSES
1/0 PORT ADDRESS
READ
WRITE
BYTE ACCESS
a = Interrupt Status
XXO
Bit
XX1 - XX?
Unused
Unused
XX8
Parallel Port A, Even PPi
Parallel Port A, Even PPI
XX9
Parallel Port A, Odd PPI
Parallel Port A, Odd PPI
XXA
Parallel Port B, Even PPI
Parallel Port B, Even PPI
Reset I nterrupt Status
XXB
Parallel Port B, Odd PPI
Parallel Port B, Odd PPI
XXC
Parallel Port C, Even PPI
Parallel Port C, Even PPI
XXD
Parallel Port C, Odd PPI
Parallel Port C, Odd PPI
XXE
Illegal Condition
Control, Even PPI
XXF
Illegal Condition
Control, Odd PPI
WORD ACCESS
a = Interrupt Status
XXO
Bit
XX2 - XX6
Unused
Unused
Parallel Port A, Even and Odd PPts
Reset Interrupt Status
XX8
Parallel Port A, Even and Odd PPls
XXA
Parallel Port B, Even and Odd PPls
Parallel Port B, Even and Odd PPls
XXC
Parallel Port C, Even and Odd PPls
Parallel Port C, Even and Odd PPls
XXE
Illegal Condition
Control, Even and Odd PPls
XX = Any hex digits, assigned by jumpers; XX defines the base address.
current). S-Series or standard series logic will not
meet this specification.
selected is determined by the position of wire wrap
jumpers. The outputs of the two decoders are
ANDed together to form the BASE ADR SELECTI
signal. This signal specifies the base address
for a group of 16 I/O ports. Using the wire wrap
jumper positions shown in the schematic, a base
address of EJ has been selected. Therefore, this
- MULTIBUS slave board will respond to I/O port
addresses in the EJO - EJF range.
Address decoder A4 is used to decode addresses
EJO - EJ7. The CSOI output of this decoder is used
to select the interrupt logic, thus I/O port address
EJO is used to read and reset the interrupt latch.
The remaining outputs from decoder A4 (CSl/ .
CS7/) are not used in this example. They would
normally be used to select other functions in a
slave board with more capability. Note that in the
schematic shown in Appendix G for the 8-bit
version of this slave design example, the high
order (ADR81 - ADRB/) address decoder is not
included and the BHEN I signal is not used.
If this slave board is to be used with 8-bit MUL1'1BUS masters, the high order address bits must not
be decoded. Therefore, the wire wrap jumper
which selects the output of decoder A3 must be
placed in the top (ground) position (pin 10 of gate
A9 to ground).
Data Buffers
directional .bus
BUS data lines
version of the
are used.
The low order 4 address lines (ADROI - AD RJ/) are
buffered and inverted using 74LS04 inverters.
These address lines are input to an 8205 for
decoding a chip select for the interrupt logic; the
address lines are also used directly by the PPIs.
LS-Series logic is required for buffering to meet the
MULTIBUS specification for IlL (low level inpu t
- Intel 8287 8-bit parallel bidrivers are used for the MULTIDATOI - DATF/. In the 81l6-bit
slave board, three 8287 drivers
When an 8-bit data transfer is requested, either
driver A5, which is connected to on-board. data
A-195
AP-28A
lines DO - D7, or driver A6, which is connected to
on-board data lines D8 - DF, is used. If a byte
transfer is requested from an even address, driver
A5 will be selected. If a byte transfer from an odd
address is requested, driver A6 will be selected. All
byte transfers take place on MULTIBUS data
lines DATOI - DAT7I. When a word (16-bit)
transfer is requested from an even address, drivers
A5 and A 7 will be used. Note that if a user program
requests a word transfer from an odd address,
16-bit masters in the iSBC product line will
actually perform two byte transfer requests.
when the MULTIBUS IOWCI signal is removed
(WRTI could have been used to steer the 8287
instead of RD); and if the capacitance of the onboard data bus lines is sufficient to hold the data
values on the bus after the 8287 OE signal and the
8255A PPI WRT I signal go inactive. The on-board
data bus may easily be designed such that the
capacitance of the lines is sufficient to meet the 30
ns data hold time requirement. In addition, the
current leakage of all devices connected to the onboard bus must be kept small to meet the 30 ns data
hold time requirement.
The logic which determines the chip selection
(8287 input signal OE, output enable) signals for
the bus drivers uses the low order address bit
(ADRO/) and the buffered Byte High Enable
signal (BHENBL/). Note that the MULTIBUS
signal BHENI has been buffered with an 74LS04
inverter. This is done to meet the bus address line
loading specification. The SWAP BYTEI signal
which is generated is qualified by the BD ENBLI
signal and used to select the bus drivers.
The 8-bit version of this design example uses only
one 8287 instead of the three required by the 8/16bit version. The logic required to control the swap
byte buffer is also not necessary. The chip select
signal used for the 8287 is the BD ENBLI signal.
Control Signals - The MULTIBUS control
signals used by this slave design example are
IORCI, IOWCI, and XACKI. IORCI and IOWCI
are qualified by the BASE ADR SELECT I signal
to form the signals RD and WRT. RD and WRT
are used to drive the interrupt logic, the PPI logic
and the XACKI (transfer acknowledge) logic.
The steering pin for the 8287 drivers is labelled T
(transmit) and is driven by the signal RD. When
an input (read) request is active or when neither a
read or· write command is being serviced, the
direction of data transfer ofthe 8287 will be set for
B to A.
For the XACKI logic RD and WRT are ORed to
form the BD ENBLI signal which is inverted and
used to drive the CLEAR pin of a shift register.
When the slave board is not being accessed, the
CLEAR pin of the shift register will be low (BD
ENBLI is high). This causes the shift register to
remain cleared and all outputs ofthe shift register
will be low. When the slave board is accessed, the
CLEAR pin will be high, and the A and B inputs
(which are high) will be clocked to the output pins
by CCLKI. To select a delay for the XACKI signal,
a jumper must be installed from one of the shift
register output pins to the 8089 tri-state driver.
Each of the shift register output pins select an
integer multiple of CCLKI periods for the signal
delay. Since the CCLKI signal is asynchronous,
the actual delay selected may only be specified
with a tolerance of one CCLKI period. In this
example a delay of 3 - 4 CCLKI periods was
selected; with a CCLKI period of 100 ns, the
XACKI delay would occur somewhere within the
range of 300 - 400 ns from the time when the
CLEAR signal goes high.
The 8287 drivers are set to point IN (directionB to
A) when no MULTIBUS I/O transfer command is
being serviced for two reasons. First, ifthe driver
were pointed OUT (direction A to B) and a write
command occured, it would be necessary to turn
the buffers IN and set the OE (output enable)
signal active before the data could be transferred
to the on-board bus. A possibility of a "bufferfight" could. occur in some designs ifthe OE signal
permitted an 8287 to drive the MULTIBUS data
lines momentarily before the steering signal could
switch the direction of the 8287. In this case, both
the MULTIBUS master and the slave would be
driving the data lines; this is not recommended.
(In this particular design, the steering signal will
always stabilize before the OE signal becomes
active.)
The second reason the driver is pointing IN when
no command is present is due to the "data valid
after WRITE" requirements of the 8255As. The
8255A requires that data remain on its data lines
for 30 ns after the WRITE command (WR at the
8255A) is removed. This requirement will be met if
the direction of the 8287 drivers is not switched
The control signal logic used in the 8-bit version of
the slave design example is identical to the logic
used in the 8/16-bit version.
A-196
AP·28A
E3D, and E3F. The even or odd liD port selection
is controlled by using the ADRO address line in
the chip select term of the PPIs: In addition, the
odd PPI (All) is selected when the BHENBL
'term is high. This occurs when the MULTIBUS
signal BHENI is low indicating that a word
(16-bit) 110 instruction is being executed. When
a word liD instruction is executed, both PPIs will
perform the liD operation specified,
Interrupt Logic - The interrupt logic uses a
74S74 flip-flop to latch an asynchronous interrupt
request from some external iogic. The Q output
of the INTERRUPT REQUEST LATCH is output
through an open collector gate to one of the
MULTIBUS interrupt lines. The state of the
INTERRUPT REQUEST LATCH is transferred
to the INTERRUPT STATUS LATCH when a
read command is performed on liD port BASE
ADDRESS+O (E30 for the jumper configuration
shown). The Qoutput ofINTERRUPT STATUS
LATCH is used to drive data line DO of the 01).board data bus by using an 8089 tri-state driver.
If a user program performs an INPUT from liD
port E30, data bit 0 will be set to 1 if the INTERRUPT REQUEST LATCH is.set.
The purpose of INTERRUPT STATUS LATCH is
to minimize the possibility of the asynchronous
interrupt occuring while the interrupt status is
being read by a bus master. If the latch was not
included in the design and an asynchronous interrupt did occur while a: bus master i's reading
MULTIBUS data line DATOI, a data buffer on the
master could go into a meta-ste.blestate. By
adding the extra latch, which is clocked by the
IORDI command for liD port E30, the possibility
of data line DATOI changing during a bus master
read operation is eliminated.
The specifications of the 8255A device state ,that
the addre!?s lines AO and, Al and the chip select
lines must be stable before the RD or WR lines are
activated. The MULTIBUS specification address
set:up time of 50 ns and the short gate propagation
, delays in this design assure that the address lines
are stable before RD or WR are active.'
, The data hold requirements. of the 8255A were
discussed in a previous section. The 8255A specification states that data will be 'stable on the data
bus lines a maximum .of 250 ns after a READ
command. This specification was used to select
the delay for the XACKI signal.
The INTERRUPT REQUEST LATCH is cleared
when a user program performs an OUTPUT to liD
port E30.
This interrupt structure assumes that several
interrupt sources may exist on the same MULTIBUS interrupt line (for example, INT3/). When the
MULTIBUS master gets interrupted, it must poll
the possible sources of the interrupt received and
after determining the source of the interrupt, it
must clear the INTERRUPT REQUEST LATCH
for that particular interrupt source.
The PPI operation for the 8-bit version of the
design example is slightly different than that used
for the 81 I6-bit version. The chip select signal for
the bottom PPI does not use the BHENBL term
since I6-bit data transfers are not possible with an
8-bit liD slave board. Also, the chip select and
address signals have been swapped so the top PPI
occupies liD address range X8 - XB, and the
bottom PPI occupies 110 address range XC -XF (X
is the base address of the8·bit version). This
swapping of the address lines was not necessary;
howJver, it was thought to be more convenient to
access the PPIs in two groups of4 contiguous liD
port addresses.
IV. SUMMARY,
The interrupt logic for the 8.-bit version of the
design example is identical to the interrupt logic of
the 8/16-bit version of the design example.
PPI Operation - Two 8255A Parallel Peripheral
Interface (PPI) devices are shown interfaced to
the slave design example logic. One PPI is connected to the on-board data bus lines DO - D7 and
is addressed with the even liD port addresses
E38, E3A, E3C, and E3E. The second PPI is
connected to data bus lines D8 - DF and is addressed with the odd liD port addresses E39, E3B,
A-197
This application note has shown the structure of
the Intel MULTIBUS system bus. The structure
supports a wide range of system modules from the
Intel OEM Microcomputer Systems product line
that can be extended with the addition of user
designed modules. Because the user designed
modules are no doubt unique to particular applications, a goal of this application note has been to
describe in detail the singular common element the bus interface. Materiai has also been
presented to assist the systems designer to understanding the bus functions so that successful
sY,stems integration can be achieved.
AP-28A
APPENDIX A
PIN ASSIGNMENT OF BUS SIGNALS ON MUL TIBUS BOARD P1 CONNECTOR
.
(COMPONENT SIDE)
PIN
1
3
MNEMONIC
(CIRCUIT SIDE)
DESCRIPTION
PIN
7
9
11
GND
+5V
+5V
+12V
-5V
GND
Signal GND
+5Vdc
+5Vdc
+ 12Vdc
-5Vdc
Signal GND
2
4
6
8
10.
12
GND
+5V
+5V
+12V
-5V
GND
BUS
CONTROLS
13
15
17
19
21
23
BCLK!
BPRN!
BUSY!
MRDC!
10RC!
XACK!
Bus Clock
Bus Pri. In
Bus Busy
Mem Read Cnid
I/O Read Cmd
XFER Acknowledge
14
16
18
20
22
24
INIT/
BPRO!
BREO!
MWTC!
.IOWC!
INH1!
BUS
CONTROLS
AND
ADDRESS
25
27
29
31
33
BHEN!
CBRO!
CCLK!
INTA!
Reserved
Byte High Enable
Common Bus Request
Constant Clk
Intr Acknowledge
26
28
30
32
34
INH2!
AD10!
AD11!
AD12!
AD13!
INTERRUPTS
35
37
39
41
INT6!
INT4!
INT2!
INTO!
Parallel
Interrupt
Requests
36
38
40
42
INT7!
INT5!
INT3!
INT1!
ADDRESS
43
45
47
49 .
51
53
55
57
ADRE!
ADRC!
ADRAI
ADR8!
ADR6!
ADR4!
ADR2!
ADRO!
44
46
48
50
52
54
56
58
ADRF!
ADRD!
ADRB/
ADR9!
ADR7!
ADR5!
ADR3!
ADR1!
DATA
59
61
63
65
67
69
71
73
DATE!
DATC!
DATA!
DAT8!
DAT6!
DAT4!
DAT2!
DATO!
60
62
64
66
68
70
DATF!
DATD!
DATB!
DAT9!
DAT7!
OATS!
DAT3!
DAT1!'
75
77
79
81
83
85
GND
POWER
SUPPLIES
POWER
SUPPLIES
5
-12V
+5V
+5V
GND
Address
Bus
Data
Bus
72
74
Signal GND
Reserved
-12Vdc
+5Vdc
+5Vdc
SignalGND
76
78
80
82
84
86
All Mnemonics © Intel Corporation 1978
A-198
DESCRIPTION
MNEMONIC
GND
-12V
+5V
+5V
GND
Signal GND
+5Vdc
+5Vdc
+12Vdc
-5Vdc
SignalGND
Initialize
Bus Pri. Out
Bus Request
Mem Write Cmd
I/O Write Cmd
Inhibit 1 disable RAM
Inhibit 2 disable PROM or ROM
Address
Bus
Parallel
Interrupt
Requests
Address
Bus
Data
Bus
Signal GND
Reserved
-12Vdc
+5Vdc
+5Vdc
SignalGND
AP-28A
APPENDIX A (Continued)
P2 CONNECTOR PIN ASSIGNMENT OF OPTIONAL BUS SIGNALS
(COMPONENT SIDE)
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
40
43
45
47
49
51
53
55
57
59
MNEMONIC
GND
5 VB
-5 VB
12 VB
PFSRI
-12 VB
PFSNI
PFINI
GND
+15V
-15V
PARll
PAR21
\
> Reserved
(CIRCUIT SIDE)
DESCRIPTION
PIN
Signal GND
+ 5V Battery
Reserved
-5V Battery
Reserved
+12V Battery
Power Fail Sense Resel
-12V Battery
Power Fail Sense
Power Fail Interrupt
Signal GND
+15V
-15V
Parity 1
Parity 2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
MNEMONIC
GND
5 VB
vccpp
-5 VB
Reserved
12 VB
Reserved
-12 VB
ACLO
MPROI
GND
+15V
-15V
HALTI
WAITI
ALE
Reserved
Reserved
AUX RESETI
Reserved
Notes:
1. PFIN, on slave modules, iI possible, should have the option of connecting to INTOI on PI.
2. All undefined pins are reserved for future use.
All Mnemonics © Intel Corporation 1978
A-199
DESCRIPTION
Signal GND
+5V Battery
+ 5V Pulsed Power
-5V Battery
+12V Battery
-12V Battery
ACLow
Memory Protect
Signal GND
+15V
-15V
Bus Master HALT
Bus Master WAIT STATE
Bus Master ALE
Reset switch
AP-28A
APPENDIX B
BUS TIMING SPECIFICATIONS SUMMARY
Parameter
Description
Minimum
Maximum
tBCY
Bus Clock Period
100
D.C.
tBW
Bus Clock Width
0.35 tBCY
0.65 tBCY
Units
ns
tSKEW
BCLKlskew
3
tPD
Standard Bus
Propagation Delay
3
tAS
Address Set-Up Time
(at Slave Board)
50
ns
tDS
Write Data Set·
Up Time
50
ns
tAH
Address Hold Time
50
ns
tDHW
Write Data Hold Time
50
ns
tDXL
Read Data Set
Up Time To XACK
0
ns
tDHR
Read Data Hold Time
0
65
ns
Acknowledge Hold
0
65
ns
tXAH
Time
ns
tXACK
Acknowledge Time
0
tTOUT
ns
tCMD
Command Pulse
Width
100
tTOUT
ns
tiD
Inhibit Delay
0
100
(Recommend
< 100 ns)
ns
tXACKA
Acknowledge Time of
of an Inhibited Slave
t IAD + 50 ns
tTOUT
tXACKB
Acknowledge Time of
an Inhibiting Slave
1.5
tTOUT
~s
tlAD
Acknowledge Disable
from Inhibit (An
internal parameter on
an inhibited slave;
used to determine
tXACKA Min.)
0
100
(arbitrary)
ns
tAIZ
Address to Inhibits
High delay
100
ns
tlNTA
INTAI Width
250
ns
tCSEP
Command Separation
100
ns
A-200
Ap·28A
APPENDIX B (Continued)
BUS TIMING SPECIFICATIONS SUMMARY
Parameter
Description
Maximum
Minimum
Units
tBREOL
IBCLKI 10 BREOI
Low Delay
0
35
ns
IBREOH
IBCLKI 10 BREOI
High Delay
0
35
ns
IBPRNS
BPRNI 10 IBCLKI
Selup Time
22
IBUSY
BUSY I delay
from IBCLKI
0
IBUSYS
BUSY 110 IBCLKI
Setup Time
25
IBPRO
IBCLK/to BPROI
(CLK 10 Priority Out)
0
40
ns
tBPRNO
BPRN 110 BPROI
IPriority In to Out)
0
30
ns
tCBRO
IBCLKllo CBROI
(CLKto Common
Bus Request)
0
60
ns
tCBROS
CBRO/to IBCLKI
Setup Time
35
tCPM
Central Priority
Module Resolution
Delay (Parallel
Priority)
0
tBCy-tBREO
-2tPD
-tBPRNS
-tSKEW
tCCY
C-clock Period
100
110
ns
tcw
C-clock Width
0.35tcCY
0.65tccY
ns
tlNIT
INIT/Width
5
ms
100
ns
tlNITS
.INIT 110 MPROI
Setup Time
tPBD
Power Backup
Logic Delay
0
tpFINW
PFINI Width
2.5
tMPRO
MPROI Delay
2.0
tACLOW
ACLOI Width
3.0
ns
70
ns
ns
ns
200
ns
ms
2.5
ms
ms
tPFSRW
PFsRI Width
100
tTOUT
Timeout Delay
5
tDCH
D.C. Power Supply
Hold from ALCOI
3.0
ms
tDCS
D.C. Power Supply
Setup to ACLOI
5
ms
ns
00
A-201
ms
AP';28A
APPENDIX.C
BUS DRIVERS, RECEIVERS,AND:rERMINATIONS
Drlvarl,3
Bus Slgnlls
Location
Typa
- ..
Racelvar2,3
Locltlon
IOL
IOH
Co
Mlnml Mln~. MlXpt
Tarmlnatlon
IlL
IIH
CI
MI'ml MI'~I M.'pl
Locltlon
Typa
R Units
OATO/-OATFI
(16 lines)
Masters
and Slaves
TAl
lil
-2000
300
Maslers
and Slaves
-0.8
125
. 18
.1 place
Pullup
2.2
Kg·
AOAO/-AOAB/,
Masters
TAl
16
-2000
300
Slaves
-0.8
125
18
.1 place
Pullup
2.2 .Kg
MAOC/,MWTC/' Masters
TAl
32
-2000
300
Slaves
(Memory;
-2
125
18
1 place
Pull up
1
Kg
-2
125
18
1 place
Pullup
1
Kg
-2
125
18
1 place
Pullup
510
g
1
Kg
220
330
g
g
1
Kg
BHEN/ ..
(21 lines)
memory~
mapped 110)
10ACI,IOWCI
Masters
TAl
32
-2000
300
Slaves
(1/0)
XACKI
Slaves
TAl
32
-2000
300
Masters
Inhibiting
Slaves
OC
16
-
1 place
(Master us)
TTL
48
-3000
300
Master
-2
BAEQI
Each
Master
TTL
5
-400
60
Central
Priority
Module
2
50
18
BPAOI
Each
Master
TTL
5
-400
60
Next Master
in Serial
Priority
Chainal
its BPANI
-1.6
50
18
Parallel:
Central
Priorily
Module
Serial:Prev
Masters
BPAOI
TTL
5
-400
300
Master
-2
50
INH1/,INH21
, 300
,
BCLKi ."
BPANI
,
Inhibited
Slaves
(AAM,PAOM,
AOM, MemoryMapped 1/0)
. -2
50
18
1 place
Pull~p
125
'18
MolM'erboard
To +5V
ToGNO
Central
Pullup
Priority
Module
(riotreq):
i
(not req)
'.":
(not req)
.
."
300
All Masters
-2
50
18'
I pllice
Pullup
1
Kg
300
All
-2
50
18
1 place
PulJup
2.2
Kg
-3000
300
Any
-2
125
,18,
. Motherboar~ .
32
-2000
300
Slaves
(Inlerrupling
1/0)
-2
125
18
1 place
PuliuP
1
Kg
O.C.
16
-
300
Masters
-1.6
40
18
1 place
Pullup
1
Kg
User's Fron
Panel?
TTL
16
-400
300
Slaves,
Maslers
-1.6
40
18
1 tiiace
. F'ullup
1
Kg
PFSN!
Power Back·
Up Unit
TTL
16
-400
300
Maslers
-1.6
40
16
I place
Pullup
1
Kg
ACLO
Power
Supply
O.C.
16
-400
300
Slaves,
Masters
-1.6
40
18
1 place
Pullup
1
Kg
PFIN!
Power BackUpUnil
D.C.
16
-400
300
Masters
-1.6
40
18
1 place
Pullup
1
Kg
MPAO!
Power BackUp Unil
TTL
16
-400
300
Slaves
Masters
-1.6
40
18
1 place
Pullup
1
Kg
BUSY/, CBRa
All Masters
D.C.
32
INIT/ .... ,
Master
O.C.
32
CCLKh,
1 place
TTL
48
INTA/ ..
Maslers
TAl
INTO/-INT7!
(8 lines)
Slaves
PFSA!
,,"
-
A-202
To +5V 220
ToGNO 330
g
g
AP-28A
APPENDIX C (Continued)
BUS DRIVERS, RECEIVERS, AND TERMINATIONS
Driver 1,3
Bus Signals
Aux Aesetl
LocaUon
User's
Front
Panel?
Type
Receiver 2,3
IOL
IOH
Co
Mlnma Mln~a Maxpf
Switch
toGND
-
-
-
LocaUon
Masters
Termination
Location
IlL
CI
IIH
MUms Max/J8 Maxpf
-2
50
t6
Type
R Units
None
Notes:
t. Driver Requirements
'0H
IOL
Co
TAl
O.C.
TTL
= High Output Current Drive
= Low Output Current Drive
= Capacitance Drive Capability
= 3-State Drive
= Open Collector Driver
= Totem-pole Driver
2. Receiver Requirements
IIH
IlL
C,
= High Input Current Load
= Low Input Current Load
= Capacitive Load
3. TTL low state must be 2 -0.5v but,;. 0.8v at the receivers
TTL high state must be2 2.0v but ~ 5.5v at the receivers
4. For the iSBC 80/10 and the iSBC 80/10A use only a 1K pull-up resistor to +5v for BClKI and CCLKI termination.
A-203
AP-28A
APPENDIX D
BUS POWER SPECIFICATIONS
Optional (P2)
Standard (P1)
Ballery Power Backup
Analog Power
Ground
+5
+12
-12
GND
+5V
6us Pins
Pl + 1,2,
11,12,
75,76
85,86
P1 + 3,4, P1 + 7,8
5,6,81,
82,83,
84
P1 + 79, P2+23,
80
24
+ 12V
-12V
+ 15
Mnemonic
+ 15V
-15
+5
+12
-12
-5
-126
-56
P2+25, P2+3,4, P2+ 11,
12
26
5,6
P2+ 15,
16
P2- 7,8
-15V
+56
+126
Nominal Output Ref.
+5.0V
+ 12.0V
-1'2.0V + 15.0V
-15.0V +5.0V
+ 12.0V
-12.0V
-5.0V
Tolerance from
Nominal'
Ref.
±5%
±5%
±5%
±3%
±3%
±5%
±5%
±5%
±5%
Ripple
(Pk-Pk)'
Ref.
50 mV
50 mV
50 mV
10 mV
10 mV
50 mV
50 mV
50 mV
50 mV
500/Ls
500/Ls
500/Ls
100/Ls
100/Ls
500/Ls
500/Ls
500/Ls
500/Ls
±10%
±10%
±10%
±10%
±10%
± 10%
± 10%
±10%
±10%
Transient
Response
Time'
Transient
Deviation'
NOTES:
1. Tolerance is worst case, including initial voltage setting line and load effects of power source, temperature drift, and any additional steady
state influences.
2. As measured over any bandwidth not to exceed 0 to 500 kHz.
3. As measured from the start of a load change to the time an output recovers within ±0.1% of final voltage.
4. Measured as the peak deviation from the initial voltage.
A-204
AP-28A
APPENDIX E
MECHANICAL SPECIFICATIONS
12.00 !O,OOS
0.25 X 45°
2 PLACES
8.109 0
11.500
~
IA/
I--
0.25
~
o i.-.9:~
~I
3HOL ES
COMPONENT SIDE
5.950
D>
to.DOS
6.20
5 REF
[»
0.06R -----
D>
~-----------:=a.
-----Rr
TV p
0
I-
L- ,---1" t-:--
0.55
I.
6.767 to,OOS
I
3.080
4.570
f
'-0. 30
0.390
'\.
CHAMFER ALL
CONNECTOR EDGES
0.040 x 45°
0.015 :!: 0.005 x 45°
2 PLACES
NOTES:
D>
B>
BOARD THICKNESS: 0,062
MUL llOUS CONNECTOR: 86-PIN, 0.156 SPACING
CDC VFBOl E43DOOA 1
VIKING 2VH4311ANE5
AUXILIARY CONNECTOR: BO·PIN, O. laO SPACING
CDC VPB01B30DOOAl
TI H311130
AMP PE5·14559
[9
EJECTOR TYPE: SCANBE #$203
5.
BUS DRIVERS AND RECEIVERS SHOULD BE LOCATED AS CLOSE AS POSSIBLE TO
s.
BOARD SPACING: 0.6
7.
COMPONENT HEIGHT: 0.4
s.
CLEARANCE ON CONDUCTOR NEAR EDGES: 0.050
THEIR RESPECTIVE MUL Tleus PIN CONNECTIONS
A-205
MUlT1BU~
tooNE.c.TOR
PI
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Appendix B
Device Specifications
B
iAPX 86/10
16-BIT HMOS MICROPROCESSOR
8086/8086-2/8086-1
• Bit, Byte, Word, and Block Operations
• 8 and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
• Direct Addressing Capability to 1
MByte of Memory
• Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages.
• 14 Word, by 16-Bit Register Set with
Symmetrical Operations
• Range of Clock Rates:
5 MHz for 8086,
8 MHz for 8086-2,
10 MHz for 8086-1
• 24 Operand Addressing Modes
• MULTIBUS™ System Compatible
Interface
The Intel iAPX 86/10 high performance 16-bit CPU is available in three ciock rates: 5, 8 and 10 MHz. The CPU is
implemented in N-Channel, depletion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package.
The iAPX 86/10 operates in both single processor and multiple processor configurations.to achieve high performance
levels.
EXECUTION UNIT
BUS INTERFACE UNIT
I
REGISTER FILE
RELOCATlO-;;-l
REGISTER FilE
DATA.
POINTER. AND
INDEX REGS
18 WORDSI
,-'""'""--""1.._ ii'H!IS,
Au/5 6
6·8VTE
INSTRUCTION
QUEUE
TEST--_r------~~------,
CONTROL & TIMING
2
HOlD--HLDA---"'-r__....-__.,.-__.,...-.....,..",-'
eLK
RESET
READY
Vee
AD15
AD13
A16/S3
AD12
A17IS4
AD11
AlB/55
AD10
A191$6
AD9
BHE/57
AD8
MN/MX
AD7
Rli
AD6
RO/GTO (HOLD)
ADS
RO/GT1 (HlDA)
AD4
lOCK
(WR)
AD3
S2
(M/iO)
AD2
51
So
(DT/A)
AD1
ADO
aso
(ALE)
NMI
aS1
(lNTA)
INTR
IN'--_
NMI---
AO/GTO.l
GND
A014
(DEN)
TEST
ClK
READY
GND
RESET
40 LEAD
GNO
V"
Figure 2. iAPX 86/10 Pin Configuration
Figure 1. iAPX 86/10 CPU Block Diagram
8-1
intJ
iAPX 86/10
Table 1. Pin Description
The following pin function descriptions are for iAPX 86 systems in either minimum or maximum mode. The "Local
Bus" in these descriptions Is the direct multiplexed bus interface connection to the 8086 (without regard to additional
bus buffers).
Symbol
Pin No.
AD,5·ADo 2·16.39
A,glSe.
A,afS5.
A17/S 4.
A,sfS3
35-38
Type
Name and Function
1/0
Address Data Bus: These lines constitute the time multiplexed memoryllO address (T,)
and data (T 2. T3. Tw. T4) bus. Ao is analogous to BHE for the lower byte of the data bus.
pins D7·Do. It is lOW during T, when a byte is to be transferred on the lower portion of
the bus in memory or 1/0 operations. Eight-bit oriented devices tied to the lower half
would normally use Ao to condition chip select functions. (See BHE.) These lines are
active HIGH and float to 3-state OFF during interrupt acknowledge and local bus "hold
acknowledge."
0
Address/Status: During T, these are the four most significant address lines for memory operations. During 1/0
operations these lines are lOW. During memory and 110
operations. status information is available on these
lines during T2. T3. Tw. and T4. The status of the interrupt
enable FLAG bit (S5) is updated at the beginning of each
ClK cycle. A17/S4 and A,sfS3 are encoded as shown.
This information indicates which relocation register is
presently being used for data accessing.
A17/S4
Als1S 3
Characteristics
o (LOW)
0
1
0
1
Alternate Data
Stack
Code or None
0
1 (HIGH)
1
$6 is 0
Oata
(LOW)
These lines float to 3·state OFF during local bus "hold
acknowledge."
BHE/S7
34
0
Bus High Enable/Status: During T, the bus high enable
signal (BHE) should be used to enable data onto the
most significant half of the data bus. pins D,5-D8' Eightbit oriented devices tied to the upper half of the bus
would normally use BHE to condition chip select functions. BHE is lOW during T, for read. write. and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status informalion is available during T2. T3. and T 4. The Signal is active
lOW. and floats to 3-state OFF in "hold." It is lOW during T, for the first interrupt acknowledge cycle.
BHE
AO
0
0
Whole word
0
1
Upper byte from!
to odd address
1
0
Lower byte froml
to even address
1
1
None
Characteristics
Read: Read strobe indicates that the processor is performing a memory of 1/0 read cycle. depending on the state of the S2 pin. This signal is used to read devices which
reside on the 8086 local bus. RD is active lOW during T2. T3 and Tw of any read cycle.
and is guaranteed to remain HIGH in T2 until the 8086 local bus has floated.
RD
32
0
READY
22
I
READY: is the acknowledgement from the addressed memory or 1/0 device that it will
complete the data transfer. The READY signal from memory/IO is synchronized by the
8284A Clock Generator to form READY. This signal is active HIGH. The 8086 READY input is not synch.ronized. Correct operation is not guaranteed if the setup and hold
times are not met.
INTR
18
I
Interrupt Request: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt
acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table
located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.
TEST
23
I
TEST: input is examined by the "Wait" instruction. If the TEST input is lOW execution
continues. otherwise the processor waits in an "Idle" state. This input is synchronized
internally during each clock cycle on the leading edge of ClK.
This signal floats to 3-state OFF in "hold acknowledge."
B-2
AFN-01497B
inter
iAPX 86/10
Table 1. Pin Description (Continued)
Pin No.
Type
NMI
17
I
Non·maskable interrupt: an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system
memory. NMI is not maskable internally by software. A transition from a lOW to HIGH
initiates the interrupt at the end of the current instruction. This input is internally syn·
chronized.
RESET
21
I
Reset: causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles. It restarts execution, as described in
the Instruction Set description, when RESET returns lOW. RESET is internally syn·
chronized.
ClK
19
I
Clock: provides the basic timing for the processor and bus controller. It is asymmetric
with a 33% duty cycle to provide optimized internal timing.
Symbol
Vcc
40
GND
1,20
MN/MX
33
Name and Function
Vcc:
+ 5V power supply pin.
Ground
I
Minimum/Maximum: indicates what mode the processor is to operate in. The two
modes are discussed in the following sections.
The following pin function descriptions are for the 808618288 system in maximum mode (i.e., MNIMX = Vssl. Only the
pin functions which are unique to maximum mode are described; all other pin functions are as described above.
S2, S1, So
26·28
a
Status: active during T4, T1, and T2 and is returned to the
. passive state (1,1,1) during T3 or during Tw when READY
is HIGH. This status is used by the 8288 Bus Controller
to generate all memory and I/O access control signals.
Any change by 8;,5" or So during T4 is ,used to indicate
the beginning of a bus cycle, and.the return to the pas·
sive state in T3 or Tw is used to indicate the end of a bus
cycle.
These signals float to 3·state OFF in "hold acknowl·
edge." These status lines are encoded as shown.
RQ/GT o,
RQ/GT1
30,31
I/O
52
51 So
OllOW)
0
0
0
0
0
0
1
1
1
0
1IHIGH)
1
1
1
0
0
0
1
1
0
1
1
1
Characteristics
Interrupt
Acknowledge
Read 110 Port
Write 1/0 Port
Hall
Code Access
Read Memory
Write Memory
Passive
Request/Grant: pins are used by other local bus masters to force the processor to
release the local bus at the end 01 the processor's current bus cycle. Each pin is
bidirectional with RQ/GT o having higher priority than RQ/GT 1 •. RQ/GT has an internal
pull-up resistor so may be left unconnected. The request/grant sequence is as follows
(see Figure 9):
1. A pulse of 1 ClK wide from another local bus master indicates a local bus request
("hold") to the 8086 (pulse 1);
2. During a T4 orT J clock cycle, a pulse 1 ClK wide from the 8086to the requesting master
(pulse 2), indicates that the 8086 has allowed the local bus to float and that it will enter
the "hold acknowledge" state at the next ClK. The CPU's bus interface unit is disconnected logically from the local bus during "hold acknowledge."
3. A pulse 1 ClK wide from the requesting master indicates to the 8086 (pulse 3) that
the "hold" request is about to end and that the 8086 can reclaim the local bus at the
next ClK.
Each master-master exchange of the local bus is a sequence of 3 pulses. There must
be one dead ClK cycle after each bus exchange. Pulses are active lOW.
If the request is made while the CPU is performing a memory cycle, itwill release the local
bus during T4 of the cycle when all the following conditions are met:
1.
2.
3.
4.
Request occurs on or before T2 .
Current cycle is not the low byte of a word (on an odd address),
Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
A locked instruction is not currently executing.
8-3
AFN-01497B
iAPX 86/10
Table 1. Pin Description (Continued)
Symbol
Pin No.
Type
Name and Function
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active
memory cycle apply with condition number 1 already satisfied.
LOCK
as" aso
29
a
LOCK: output indicates that other system bus masters are not to gain control of the
system bus while LOCK is active LOW. The LOCK signal is activated by the "LOCK"
prefix instruction and remains active until the completion of the next instruction. This
signal is active LOW, and floats to 3·state OFF in "hold acknowledge."
24,25
a
Queue Status: The queue status is valid during the CLK
cycle after which the queue operation is performed.
QS, and QSo provide status to allow external tracking of
the internal 8086 instruction queue.
The fol/owing pin function descriptions are for the 8086 in minimum mode (i.e., MN/MX = Vee). Only the pin functions which
are unique to minimum mode are described; al/ other pin functions are as described above.
MilO
28
a
Status line: logically equivalent to S2 in the maximum mode. It is used to distinguish a
memory access from an I/O access. MIlO becomes valid in the T4 preceding a bus cycle
and remains valid until the final T4 of the cycle (M = HIGH, 10 = LOW). MIlO floats to
3·state OFF in local bus "hold acknowledge."
WR"
29
a
Write: indicates that the proces~r is performing a write memory or write I/O cycle,
depending on the state of the MilO signal. WR is active for T2, T 3 and Tw of any write cy·
cle. It is active LOW, and floats to 3-state OFF in local bus "hold acknowledge."
INTA
24
a
INTA is used as a read strobe for interrupt acknowledge cycles. It is active LOW during
T2, T3 and Tw of each interrupt acknowledge cycle.
ALE
25
a
Address Latch Enable: provided by the processor to latch the address into the 82821
8283 address latch. It is a HIGH pulse active during T, of any bus cycle. Note that ALE
is never floated.
DT/R
27
a
Data Transmit/Receive: needed in minimum system that desires to use an 8286/8287
data bus transceiver. It is used to control the direction of data flow through the
transceiver. LogicallyDT/R is equivalent to 51 in the maximum mode, and its timing is
the same as for MIlO. (T = HIGH, R = LOW.) This signal floats to 3-state OFF in local bus
"hold acknowledge."
DEN
26
a
Data Enable: provided as an output enable for the 8286/8287 in a minimum system
which uses the transceiver. DEN is active LOW during each memory and I/O access and
for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of T2 until the middle of
T4. DEN floats to 3-state OFF in local bus "hold acknowledge."
31,30
I/O
HOLD: indicates that another master is requesting a local bus "hold." To be acknowledged, HOLD must be active HIGH. The processor receiving the "hold" request will
issue HLDA (HIGH) as an acknowledgement in the middle of a T4 orT, clock cycle. Simultaneous with the issuance of HLDAthe processor will float the local bus and control
lines. After HOLD is detected as being LOW, the processor will LOWer HLDA, and when
the processor needs to run another cycle, it will again drive the local bus and control
lines.
HOLD,
HLDA
The same rules as for RQIGT apply regarding when the local bus will be released.
HOLD is not an asynchronous input. External synchronization should be provided if the
system cannot otherwise guarantee the setup time.
8-4
AFN-Q1497B
iAPX86/10
MEMORY ORGANIZATION
FUNCTIONAL DESCRIPTION
The processor provides a 20-bit address to memory which
locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed
as OOOOO(H) to FFFFF(H). The memory is logically divided
into code, data, extra data, and stack segments of up to
64K bytes each, with each segment falling on 16-byte
boundaries. (See Figure 3a.)
GENERAL OPERATION
The internal functions of the iAPX 86/10 processor are
partitioned logically into two processing units. The first is
the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of
Figure 1.
All memory references are made relative to base
addresses contained in high speed segment registers. The
segment types were chosen based on the addressing
needs of programs. The segment register to be selected is
automatically chosen according to the rules of the following table. All information in one segment type share the
same logical attributes (e.g. code or data). By structuring
memory into relocatable areas of similar characteristics
and by automatically selecting segment registers, programs are shorter, faster, and more structured.
These units can interact directly but for the most part
perform as separate asynchronous operational processors. The bus interface unit provides the functions related
to instruction fetching and queuing, operand fetch and
store, and address relocation. This unit also provides the
basic bus control. The overlap of instruction pre-fetching
provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to
6 bytes of the instruction stream can be queued while
waiting for decoding and execution.
Word (16-bit) operands can be located on even or odd
address boundaries and are thus not constrained to
even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued
address location and the most significant byte in the
next higher address location. The BIU automatically performs the proper number of memory accesses, one if
the word operand is on an even byte boundary and two if
it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the
software. This performance penalty does not occur for
instruction fetches, only word operands.
The instruction stream queuing mechanism allows the
BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the
BIU will attempt a word fetch memory cycle. This greatly
reduces "dead time" on the memory bus. The queue
acts as a First-In-First-Out (FIFO) buffer, from which the
EU extracts instruction bytes as required. If the queue is
empty (following a branch instruction, for example), the
first byte into the queue immediately becomes available
to the EU.
Physically, the memory is organized as a high bank
(DIs-Del and a low bank (0 7-0 0) of 512K 8-bit bytes
addressed in parallel by the processor's address lines
The execution unit receives pre-fetched instructions
from the BIU queue and provides un-relocated operand
addresses to the BIU. Memory operands are passed
through the BIU for processing by the EU, which passes
results to the BIU for storage. See the Instruction Set
description for further register set and architectural
descriptions.
Memory
Reference Need
A19 - AI. Byte data with even addresses is transferred on
the 07-00 bus lines while odd addressed byte data (Ao
HIGH) is transferred on the DIS-Os bus lines. The processor provides two enable signals, BHE and Ao, to selectively
allow reading from or writing into either an odd byte
location, even byte location, or both. The instruction
stream is fetched from memory as words and is addressed
internally by the processor to the byte level as necessary.
Segment Register
Used
Segment
Selection Rule
Instructions
CODE (CS)
Automatic with all instruction prefetch.
Stack
STACK (SS)
All stack pushes and pops. Memory references relative to BP
base register except data references.
Local Data
DATA (OS)
Data references when: relative to stack, destinatibn of string
operation, or explicitly overridden.
External (Global) Data
EXTRA (ES)
Destination of string operations: Explicitly selected using a
segment override.
8-5
AFN-014978
iAPX 86/10
D}
consisting of a 16·bit segment address and a 16·bit off·
set address. The pointer elements are assumed to have
been stored at the respective places in reserved memory
prior to occurrence of interrupts .
...r---J.. FFFFFH
.4tB
.------'--~
CODE SEGMENT
XXXXOH
}STACK SEGMENT
tl}
RESET BOOTSTRAP
PROGRAM JUMP
.--'--4----l
SEGMENT
ERE~G~'SliiER~F~ILE3==~~~ :
FFFFFH
FFFFOH
3FFH
INTERRUPT POINTER
DATA SEGMENT
FOR TYPE 255
3FCH
}EXTRA DATA SEGMENT
7H
INTERRUPT POINTER
FOR TYPE 1
L--4---l
INTERRUPT POINTER
FOR TYPE 0
~OOOOOH
4H
3H
OH
Figure 3a. Memory Organization
Figure 3b. Reserved Memory Locations
In referencing word data the BIU requires one or two
memory cycles depending on whether or not the start·
ing byte of the word is on an even or odd address,
respectively. Consequently, in referencing word oper·
ands performance can be optimized by locating data on
even address boundaries. This is an especially useful
technique for using the stack, since odd address refer·
ences to the stack may adversely affect the context
switching time for interrupt processing or task multi·
plexing.
MINIMUM AND MAXIMUM MODES
The requirements for supporting minimum and maximLim
iAPX 86/10 systems .are sufficiently different that they
cannot be done efficiently with 40 uniquely defined
pins. Consequently, the 8086 is equipped with a strap
pin (MN/MX) which defines the system configuration.
The definition of a certain subset of the pins changes
dependent on the condition of the strap pin. When
MN/MX pin is strapped to GND, the 8086 treats pins.24
through 31 in maximum mode. An 8288_bl!,s s,ontroller
interprets status information coded into SO,S1,S2 to gen·
erate bus timing and control signals compatible with
the MULTIBUS™ architecture. When the MN/MX pin is
strapped to Vee. the 8086 generates bus control signals
itself on pins 24 through 31. as shown in parentheses in
Figure 2. Examples of minimum mode and maximum
mode systems are shown in Figure 4.
Certain locations in memory are reserved for specific
CPU operations (see Figure 3b.) Locations from address
FFFFOH through FFFFFH are'reserved for operations
including a jump to the initial program loading routine.
Following RESET, the CPU will always begin execution
at location FFFFOH where the jump must be, Locations
OOOOOH through 003FFH are reserved for interrupt
operations. Each of the 256 possible interrupt types has
its service routine pOinted to by a 4·byte pointer element
6-6
AFN·01497B
iAPX 86/10
lUi
Vee
..... m
I
CLK
M/i-- ~
D_A_T_A_O_U_T_'D_",..-_DD_'_ _
READY'
READY
READY
WAIT
WAIT
oTiii'
~
MEMORY ACC!8S TIM!---+
\\.-_-----11
Figure 5. Basic System Timing
8-9
AFN-01497B
inter
iAPX 86/10
EXTERNAL INTERFACE
sequence, which is used to "vector" through the appropriate element to the new interrupt service program
location.
PROCESSOR RESET AND INITIALIZATION
NON·MASKABLE INTERRUPT (NMI)
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8086 RESET is
required to be HIGH for greater than 4 elK cycles. The
8086 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is
HIGH. The low-going transition of RESET triggers an
internal reset sequence for approximately 10 elK cycles.
After this interval the 8086 operates normally beginning
with the instruction in absolute location FFFFOH (see
Figure 38). The details of this operation are specified in the
Instruction Set description of the MeS-86 Family User's
Manual. The RESET input is internally synchronized to the
processor clock. At initialization the HIGH-to-lOW transition of RESET must occur no sooner than 50 ,..s after
power-up, to allow complete initialization of the 8086.
The processor provides a single non-maskable interrupt
pin (NMI) which has higher priority than the maskable in·
terrupt request pin (INTR). A typical use would be to activate a power failure routine. The NMI is edge-triggered
on a lOW-to-HIGH transition. The activation of this pin
causes a type 2 interrupt. (See Instruction Set description.)
NMI is required to have a duration in the HIGH state of
greater than two elK cycles, but is not required to be
synchronized to the clock. Any high-going transition of
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves of a
block-type instruction. Worst case response to NMI
would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the
low-going edge; it may occur before, during, or after the
servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure. The Signal must be free of logical spikes in
general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.
NMI may not be asserted prior to the 2nd elK cycle following the end of RESET.
INTERRUPT OPERATIONS
Interrupt operations fall into two classes; software or
hardware initiated. The. software initiated interrupts and
software aspects of hardware interrupts are specified in
the Instruction Set description. Hardware interrupts can
be classified as non·maskable or maskable.
MASKABLE INTERRUPT (INTR)
The 86/10 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable FLAG status bit. The
interrupt request signal is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of elK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
block-type instruction. During the interrupt response
sequence further interrupts are disabled. The enable bit
is reset as part of the response to any interrupt (INTR,
NMI, software interrupt or single-step), although the
Interrupts result in a transfer of control to a new program location. A 256-element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see
Figure 3b), which are reserved for this purpose. Each
element in the table is 4 bytes in size and corresponds
to an interrupt "type". An interrupting device supplies
an 8-bit type number, during the interrupt acknowledge
I
T,
T2
T3
T41TII
T,
T,
ALE~~_-----Iln~
\
\
=
(NfA
AOo-AD1~
~FLOAT
} I
! (
rt'
) (I
j
_ _
/
~
\
\ >TYPE VECTOR
Figure 6. Interrupt Acknowledge Sequence
8-10
AFN-01497B
iAPX 86/10
FLAGS register which Is automatically pushed onto the
stack reflects the state of the processor prior to the
interrupt. Until the old FLAGS register is restored the
enable bit will be zero unless specifically set. by an
instruction.
to become active. It must remain active for at least 5
CLK cycles. The WAIT instruction is re·executed
repeatedly until that time. This activity does not consume bus cycles. The processor remains in an idle state
while waiting. All 8086 drivers go to 3-state OFF if bus
"Hold"ls entered. If interrupts are enabled, they may
occur while the processor is waiting. When this occurs
the processor fetches the WAIT instruction one extra
time, processes the interrupt, and then re-fetches and
re·executes the WAIT Instruction upon returning from
the interrupt.
During the response sequence (figure 6) the processor
executes two successive (back-to-back) interrupt
acknowledge cycles. The 8086 emits the LOCK signal
from T2 of the first bus cycle until T2 of the second. A
local bus "hold" request will not be honored until the
end of the second bus cycle. In the second bus cycle a
byte is fetched from the external interrupt system (e.g.,
8259A PIC) which identifies the source (type) of the
interrupt. This byte is multiplied by four and used as a
pOinter into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within
the limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable
bit when it restores the FLAGS.
BASIC SYSTEM TIMING
Typical system configurations for the processor
operating in minimum mode and in maximum mode are
shown in Figures 4a and 4b, respectively. In minimum
mode, the MN/MX pin is strapped to Vee and the processor emits bus control signals in a manner similar to
the 8085. In maximum mode, the MN/MX pin is strapped
to Vss and the processor emits coded status information which the 8288 bus controller uses to generate
MULTIBUS compatible bus control signals. Figure 5 illustrates the signal timing relationships.
HALT
When a software "HALT" instruction is executed the
processor indicates that it is entering the· "HALT" state
in one of two ways depending upon which mode is
strapped. In minimum mode, the processor issues one
ALE with no·qualifying bus control signals. In Maximum
Mode, the processor issues appropriate HALT status on
525,50 and tlie 8288 bus controller issues one ALE. The
8086 will not leave the "HALT" state when a local bus
"hold'.' is entered while in "HALT". In this case, the
processor reissues the HALT indicator. An interrupt
request or RESET will force the 8086 out of the "HALT"
state.
AX
AH
AL
ACCUMULATOR
BX
BH
BL
BASE
CX
CH
CL
COUNT
OX
DH
DL
DATA
~m
READ/MODIFY/WRITE (SEMAPHORE)
OPERATIONS VIA LOCK
I
The LOCK status information is provided by the proc·
essor when directly consecutive bus cycles are required
during the execution of an instruction. This provides the
processor with the capability of performing readlmodifyl
write operations on memory (via the Exchange Register
With Memory instruction, for example) without the
possibility of another system bus master receiving
intervening memory cycles. This is useful in multi·
processor system configurations to accomplish "test
and set lock" operations. The LOCK signal is activated
(forced LOW) in the clock cycle following the one in
which the software "LOCK" prefix instruction is
decoded by the EU. It is deactivated at the end of the
last bus cycle of the instruction following the "LOCK"
prefix instruction. While LOCK is active a request on a
RQ/GT pin will be recorded and then honored at the end
of the LOCK.
-
BASE POINTER
SI
SOURCE INDEX
01
DESTINATION INDEX
IP
FLAGSH
STACK POINTER
BP
I
FLAGS l '
I
INSTRUCTION POINTER
STATUS FLAGS
CS
CODE SEGMENT
OS
DATA SEGMENT
55
STACK SEGMENT
ES
EXTRA SEGMENT
Figure 7. iAPX 86/10 Register Model
SYSTEM TIMING -
MINIMUM SYSTEM
The read cycle begins in T, with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low·
going) edge of this signal is used to latch the address
information, which is valid on the local bus at this time,
into the 8282/8283 latch. The BHE and Ao signals
address the low, high, or both bytes. From T, to T4 the
MilO signal indicates a memory or 1/0 operation. At T2
the address is removed from the local bus and the bus
goes to a high impedance state. The read control signal
is also asserted at T2. The read (RD) signal causes the
addressed device to enable its data bus drivers to the
local bus. Some time later valid data will be available on
the bus and the addressed device will drive the READY
line HIGH. When the processor returns the read signal
EXTERNAL SYNCHRONIZATION VIA TEST
As an alternative to the interrupts and general 110
capabilities, the 8086 provides a single softwaretestable input known as the TEST signal. At any time the
program may execute a WAIT Instruction. If at that time
the TEST signal is inactive (HIGH), program execution
becomes suspended while the processor waits for TEST
8-11
AFN·D1497B
iAPX 86/10
to a HIGH level, the addressed device will again 3-state
its bus drivers. If a transceiver (8286/8287) is required to
buffer the 8086 local bus, signals DT/R and DEN are provided by the 8086.
A write cycle also begins with the assertion of ALE and
the emission of the address. The M/iO signal is again
asserted to indicate a memory or 1/0 write operation. In
the T2 immediately following the address emission the
processor emits the data to be written into the
addressed location. This data remains valid until the
middle of T4 . During T2, T3, and Tw the processor asserts
the write control signal. The write (WR) signal becomes
active at the beginning of T2 as opposed to the read
which is delayed somewhat into T2 to provide time for
the bus to float.
read (AD) signal and the address bus is floated. (See
Figure 6.) In the second of two successive INTA cycles,
a byte of information is read from bus lines D7-DO as
supplied by the interrupt system logic (i.e., 8259A Priority Interrupt Controller). This byte identifies the source
(type) of the interrupt. It is multiplied by four and used
as a pOinter into an interrupt vector lookup table, as
described earlier.
BUS TIMING-MEDIUM SIZE SYSTEMS
For medium size systems the MN/MX pin is connected to
Vss and the 8288 Bus Controller is added to the system as
well as an 828218283 latch for latching the system address,
and a 8286/8287 transceiver to allow for bus loading
greater than the 8086 is capable of handling. Signals ALE,
DEN, and DT/R are generated by the 828B instead of the
processor in this configuration although their timing remains relatively the same. The B086 status outputs (82, 8"
and So) provide type-of-cycle information and become
B2BB inputs. This bus cycle information specifies read
(code, data, or I/O), write (data or I/O), interrupt acknowledge, or software halt. The B2BB thus issues control
signals specifying memory read or write, 1/0 read or write,
or interrupt'acknowledge. The B2B8 provides two types of
write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the
leading edge of write. The advanced write strobes have
the same timing as read strobes, and hence data isn'tvalid
at the leading edge of write. The B2B6/B2B7 transceiver
receives the usual T and OE inputs from the B2BB's DT/R
and DEN.
The BHE and Ao signals are used to select the proper
byte(s) of the memoryllO word to be read or written
according to the following table:
BHE
AO
0
0
0
1
0
1
1
1
CHARACTERISTICS
Whole word
Upper byte from!
to odd address
Lower byte from!
to even address
None
The pOinter into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8259A Priority Interrupt Controller is
positioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiverwhen reading from the
master 8259A during the interrupt acknowledge
sequence and software "poll".
1/0 ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the
D7-DO bus lines and odd addressed bytes on D'5-D8'
The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt
acknowledge signal (INTA) is asserted in place of the
8-12
AFN-01497B
iAPX 86/10
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground .................. - 1.0 to + 7V
Power Dissipation ........................ 2.5 Watt
D.C. CHARACTERISTICS
Symbol
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
(8086: TA = O°C to 70°C, Vcc = 5V ± 10%)
(8086-1: TA = O°C to 70°C, Vee = 5V ± 5%)
(8086-2: TA = O°C to 70°C, Vee = 5V ± 5%)
Parameter
Min.
Max.
Units
TeBI Conditions
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
+0.8
V
Vee+ 0.5
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
V
IOL=2.5 mA
V
Icc
Power Supply Current: 8086
8086-1
8086-2
340
360
350
10H= -400/AA
mA
III
Input Leakage Current
± 10
"A
OV.;; VIN .;; Vee
ILO
Output Leakage Current
± 10
/AA
0.45V
+0.6
V
2.4
T A=25·C
~
VOUT ~ Vee
VeL
Clock Input Low Voltage
-0.5
VeH
Clock Input High Voltage
3.9
Vee+ 1.O
V
C IN
Capacitance of Input Buffer
(All input except
AD o-AD 15 • RQ/GT)
15
pF
fe= 1 MHz
CIO
Capacitance of I/O Buffer
(AD o-AD 15• RQ/GT)
15
pF
le= 1 MHz
8-13
AFN-01497B
inter
iAPX 86/10
A.C. CHARACTERISTICS
iooe,
(8086:TA = ooe to
VCC = 5V ± 10%)
(8086-1: TA = ooe to 70oe, Vcc = 5V ± 5%)
(8086-2: TA = ooe to 70oe, Vcc ;= 5V ± 5%)
MINIMUM COMPLEXITY SYSTEM
TIMING REQUIREMENTS
Symbol
Parameter
8086,1 (Preliminary)
8086
8086-2
Units
Min.
Max.
Min.
Max.
Min.
Max.
200
500
100
500
125
500
Test
Conditions
TCLCl
ClK Cycle Period
TClCH
ClKLowTime
(%TCLCl)-15
(% TClCL)-14
(%TCLCl)-15
TCHCl
ClK High Time
(1J.!TClCL)+2
(1J.!TCLCl)+6
(1J.!1'ClCl)+2
TCH1CH2
ClK Rise Time
10
10
10
ns
From 1.0Vto
3.5V
TCL2CL1
CLKFaliTime
10
10
10
ns
Fl'()m 3.5Vto
1.0V
TDVCl
Data in Setup Time
30
5
20
TClDX
Data in Hold Time
10
10
10
ns
TR1VCL
ROY Setup Time
into 8284A (See
Notes 1, 2)
35
35
35
ns
TCLRIX
ROY Hold Time
into 8284A (See
Notes 1,2)
0
0
0
ns
TRYHCH
READY Setup
Time into 8086
(%TClCL)-15
53
(% TClCl)-15
ns
TCHRYX
READY Hold Time
int08086
30
20
20
ns
TRYlCL
READY Inactive to.
CLK (See Note 3)
-8
-10
-8
ns
THVCH
HOLD Setup Time.
35
20
20
. ns
TINVCH
INTR. NMI, TEST
Setup Time (See
Note 2)
30
15
15
ns
TlLIH
Input Rise Time'
(Except ClK)
20
20
20
ns
'From 0.8" to
2.0V
TlHIL
Input Fall Time
(Except ClK)
12
12
12
ns
From 2.0Vto
0.8V
8·14.
n.
ns
ns
ns
AFN.()1497B
iAPX 86/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Parameter
8086
8086-1 (Preliminary)
Units
8086-2
Min.
Max.
Min.
Max.
Min.
Max.
TCLAV
Address Valid Delay
10
_110
10
50
10
60
TCLAX
Address Hold Time
10
TCLAZ
Address Float
Delay
TCLAX
10
80
10
10
40
TCLAX
ns
ns
50
ns
TLHLL
ALE Width
TCLLH
ALE Active Delay
80
40
50
ns
TCHLL
ALE Inactive Delay
85
45
55
ns
TLLAX
Address Hold Time
to ALE Inactive
TCLDV
Data Valid Delay
10
TCHDX
Data Hold Time
10
10
10
ns
TWHDX
Data Hold Time
AflerWR
TCLCH-30
TCLCH-25
TCLCH-30
ns
TCVCTV
Control Active
Delay 1
10
110
10
50
10
70
ns
TCHCTV
Control Active
Delay 2
10
110
10
45
10
60
ns
TCVCTX
Control Inactive
Delay
10
110
10
50
10
70
ns
TAZRL
Address Float to
READ Active
0
TCLCH-20
TCLCH-l0
TCHCL-l0
TCLCH-l0
TCHCL-l0
110
10
ns
TCHCL-l0
50
10
0
ns
60
0
ns
TCLRL
RD Active Delay
10
165
10
70
10
100
ns
RD Inactive Delay
10
150
10
60
10
80
ns
TRHAV
RD Inactive to Next
Address Active
TCLHAV
HLDA Valid Delay
TRLRH
RDWidth
2TCLCL-75
2TCLCL-40
2TCLCL-50
ns
TCLCL-35
10
160
10
ns
TCLCL-40
60
10
·CL = 20-100 pF
for all 8086 Outputs (In addition to 8086 selfload)
ns
TCLRH
TCLCL-45
Test
Conditions
100
ns
TWLWH
WRWidth
2TCLCL-60
2TCLCL-35
2TCLCL-40
ns
TAVAL
Address Valid to
ALE Low
TCLCH-60
TCLCH-35
TCLCH-40
ns
TOLOH
Output Rise Time
20
20
20
ns
From 0.8Vto
2.0V
TOHOL
Output Fall Time
12
12
12
ns
From 2.0Vto
0.8V
NOTES:
1. Signal at B2B4A shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state. (B ns into T3).
8-15
AFN-01497B
iAPX 86/10
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
DEVICE
UNDER
TEST
ICL~IOOPF
_.
AC. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND O.4SV FOR
A LOGIC "0.'" TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A
LOGIC "'1" AND "0."
CL INCLUDES JIG CAPACITANCE
WAVEFORMS
MINIMUM MODE
T,
·
CHr--\
ClK (8284A Output)
~
T2
TCHCTV
~
r'~
~~"'-=]J=--=lC'
I
~
-
I-
TClAV-
TClDV
TClAXBHE, A19-A18
TCllHALE
f-
TlHll-=:
TJAl
TCHLL-I
TCHDX57-53
:=
r--
0c- l'\\t\
-TRIVCL
VIL ---.:.
TRYlCl-
- h
I
-
-
-
TAVAl
TllAX_
r--
-I
-TClAZ
_TClAX
TDVCl-- -TCLDXDATA IN
A15-ADo
TAZRL-
RD
-= ----z-
READ CYCLE
(NOTE I)
(WR. INTA = VOH)
DTJR
TCHCTV
TClRl
-TCHRYX
-
TRYHCH-
-
,
\\\\\
I-TclRIX
TClAV-
tI~ __ -
V,H ' "
1
rL-
_,
-
_TlLAX
RDY (6264A Input)
SEE NOTE 4
f
-
r-- TClCH_
;------ TCHCl
MIlO
T,
Tw
~
-
READY (8086 Input)
13
::{
f
TCVCTV-
8-16
TClRH-
1-1
FlO:~'-
t-TRHAV
~
TRlRH
-TCHCTV
1
TCVCTX-
I
AFN-01497B
inter
iAPX 86/10
WAVEFORMS (Continued)
MINIMUM MODE (Continued)
Tw
VCH
CLK (8284A Oulpull
M/iO
ALE
WRITE CYCLE
(/IOTE 1)
DEN
(liD. iN'fA.
DTIII=voHI
INTA CYCLE
(NOTES I" 31
DT/R
RD. WRI:IVOH
I!RE=VOU
SOFTWARE HALTRD. WR. INTA = VOH
DT/R = INDETERMINATE
INVALID ADDRESS
SOFTWARE HALT
TCLAV
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. ROY is sampled near the end of T2• T3. Tw to determine if Tw machines states are to be inserted.
3. Two INTA cycles run back-to-back. The 8086 LOCAL AOORIOATA BUS is floating during both INTA cycles. Control signals shown
for second INTA cycle.
.
4. Signals at 8284A are shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
8-17
AFN·OI497B
iAPX 86/10
A.C. CHARACTERISTICS
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
Symbol
Parameter
8086
8086·1 (Preliminary)
8086-2 (Preliminary)
Min.
Max.
Min.
Max.
Min.
Max.
200
500
100
500
125
500
Units
Test
Conditions
TCLCL
CLK Cycle Period
TCLCH
CLK Low Time
(% TCLCL)-15
(% TCLCL)-14
(% TCLCL)-15
ns
TCHCL
CLK High Time
(1I:J TCLCL)+2
(Y, TCLCL)+6
(V, TCLCL)+2
TCH1CH2
CLK Rise Time
10
10
10
ns
From 1.0Vto
3.5V
TCL2CLI
CLK Fall Time
10
10
10
ns
From 3.5Vto
1.0V
ns
ns
TDVCL
Data in Setup Time
30
5
20
TCLDX
Data In Hold Time
10
10
10
ns
ns
TRtVCL
ROY Setup Time
into 8284A (See
Notes 1, 2)
35
35
35
ns
TCLR1X
ROY Hold Time
into 8284A (See
Notes 1, 2)
0
0
0
ns
TRYHCH
READY Setup Time
into 8086
(% TCLCL)-15
53
(% TCLCL)-15
ns
TCHRYX
READY Hold Time
into 8086
30
20
20
ns
TRYLCL
READY Inactive to
CLK (See Note 4)
-8
-10
-8
ns
TINVCH
Setup Time for
Recognition (INTR,
NMI, TEST) (See
Note 2)
30
15
15
ns
TGVCH
RQ/GT Setup Time
30
12
15
ns
TCHGX
RQ Hold Time into
8086
40
20
30
ns
TILIH
Input Rise Time
(Except CLK)
20
20
20
ns
From 0.8Vto
2.0V
TIHIL
Input Fall Time
(Except CLK)
12
12
12
ns
From 2.0Vto
0.8V
NOTES:
1.
2.
3.
4.
Signal at 8284A or 8288 shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next elK.
Applies only to T3 and wait states.
Applies only to T2 state (8 ns into T3).
8-18
AFN·01497B
iAPX 86/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
TCLML
Parameter
Command Active
8086-1 (Preliminary)
8086
8086·2 (Preliminary)
Units
Min.
Max.
Min.
Max.
Min.
Max.
10
35
10
35
10
35
ns
10
35
10
35
10
35
ns
65
ns
Test
Conditions
Delay (See Note 1)
TCLMH
Command Inactive
Delay (See Note 1)
TRYHSH
READY Active to
Status Passive (See
Note 3)
110
45.
TCHSV
Status Active Delay
10
110
10
45
10
60
ns
TCLSH
Status Inactive
10
130
10
55
10
70
ns
TCLAV
Address Valid
Delay
10
110
10
50
10
60
ns
TCLAX
Address Hold Time
10
TCLAZ
Address Float Delay
TCLAX
40
TCLAX
TSVLH
Status Valid to ALE
High (See Note 1)
15
TSVMCH
Status Valid to
MCE High (See
Note 1)
TCLLH
Delay
10
ns
ns
15
15
ns
15
15
15
ns
CLK Low to ALE
Valid (See Note 1)
15
15
15
ns
TCLMCH
CLK Low to MCE
High (See Note 1)
15
15
15
ns
TCHLL
ALE Inactive Delay
(See Note 1)
15
15
15
ns
TCLMCL
MCE Inactive Delay
(See Note 1)
15
15
15
ns
60
ns
110
10
10
50
60
10
50
10
TCLDV
Data Valid Delay
10
TCHDX
Data Hold Time
10
TCVNV
Control Active
Delay (See Note 1)
5
45
5
45
5
45
ns
TCVNX
Control Inactive
Delay (See Note 1)
10
45
10
45
10
45
ns
TAZRL
Address Float to
Read Active
0
10
10
ns
0
0
ns
TCLRL
RD Active Delay
10
165
10
70
10
100
ns
TCLRH
RD Inactive Delay
10
150
10
60
10
60
ns
TRHAV
RD Inactive to
Next Address Active
TCHDTL
TCLCL-45
Direction Control
TCLCL-35
Cl = 20-100 pF
for all 6066 Outputs (In addition to 6066 selfload)
TCLCL-40
ns
50
50
50
ns
30
30
30
ns
ns
Active Delay (See
Notel)
TCHDTH
Direction Control
Inactive Delay (See
Notel)
TCLGL
GT Active Delay
0
65
0
45
0
50
TCLGH
GT Inactive Delay
0
65
0
45
0
50
TRLRH
RDWidth
TOLOH
Output Rise Time
20
20
20
ns
From 0.6V to
2.0V
TOHOL
Output Fall Time
12
12
12
ns
From 2.0Vto
0.6V
2TCLCL-40
2TCLCL-75
8-19
2TCLCL-50
ns
ns
AFN·014978
iAPX 86/10
WAVEFORMS
MAXIMUM MODE
CLK
VCL
----~r---_r---r----+_--+_~TI7~7ir_--_+
§2,S1,So (EXCEPT HALT)
__ -----\
\.._----
TCHDX
I
ALE (8288 OUTPUn
SEE NOTE 5
1
r--
RDY (8284A INPUT)
-TCHRYX
READ CYCLE
TCLAV-j
TCLDXDATA IN
TCLRH+--t--t
RD
TRLRH
TCHDTl-
DTIR
TCLMH-+-
8288 OUTPUTS
SEE NOTES 5,6
MRDCORIORC
DEN
TCVNX-
8-20
AFN-01497B
inter
iAPX 86/10
WAVEFORMS (Continued)
MAXIMUM MODE (Continued)
T,
T,
T,
T.
Tw
ClK
VCl
\
~,'S1,So (EXCEPT HALT)
WRITE CYCLE
,~----
TCHDXDATA
TCVNXDEN
TCLMH8288 OlJtPUTS
SEE NOTES 5,6
AMWC OR AIOWC
MWTCOR lowe
INTACYCLE
AD1S- ADO
(SEE NOTES 3 & 4)
FLOAT
TCLDX
POINTER
FLOAT
TSVMCH-
I
,--
MCE!
POrn
TCHDTH
DT/A:
8288 OUTPUTS
SEe NOTES 5'6]INTA
DEN
SOFTWARE HALT(DEN VOLiR'D,MR1iC,IORC,MWTC,AMWC,IDWC,AIOWC,INTA,:::: VOH)
=
NOTES:
1. All signals switch between VO H and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, Tw to determine if Tw machines states are to be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The 8086 LOCAL ADDR/DATA BUS is floating during both INTA cycles. Control for pointer
address is shown for second INTA cycle.
5. Signals at 8284A or 8288 are shown for reference only.
6. The issuance of the 828'~ command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the
active high 8288 CEN. " \,
7. All timing measurement~ are made at 1.5V unless otherwise noted.
8. Status inactive in state
prior to T4.
iust
I,
8-21
AFN-01497B
inter
iAPX 86/10
WAVEFORMS (Continued)
ASYNCHRONOUS SIGNAL RECOGNITION
NM'
INTR
TEST
NOTE: 1. seTUP REQUIREMENTS FOR, ASYNCHRONOUS SIGNALS ONLY TO GUARANTEE RECOGNITION
AT NEXT elK
BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)
Any elK
cycle--J
I
An, elK Cycle __
ClIl.
REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTES;
1. THE COPROCESSOR MAY NOT DRIVE THE BUSES OUTSIDE THE REGION
SHOWN WITHOUT RISKING CONTENTION.
HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
TCLHAV
COPRO~ESSOR
ADIS-ADQ.
AlIfS.-Ala1S3.
L7Mlm
Dr/Fi, WR, Ii'N
8-22
AFNo01497B
intJ
iAPX 86/10
Table 2. Instruction Set Summary
DATA TRANSFER
IOV ~ 1m:
RegrsttrlmemO'ylallromregtsler
Immed,ale10 reglsle,'memOIY
Immeclllie10 reglsler
Memory 10 accumuialor
Accumulator 10 memory
Reglsle,'memo,yloseQmenl,eglsler
Segment uglste, 10 flg,ster/memory
71543210
7 B5 .. 3 2 I
I
110001011 w mod
111000'1 w
1101 I W Itg
I
I
I' 0 1 000 1 w I
11010 0 DOw
a
715 43 Z I 0
711543 Z I 0
dala
dala,l..,. 1
dala
I
I
adel,·low
acldr.hIQh"]
adel,·low
adel,·hlgh
II 0 001110 ImodOreg
II 0 0 a I I 00 I mod 0 r'g
DEC
dala,'w 1
I
I
"m
"m
POP="p:
R.glsl.rlmemClly
Regisler
Segmentreg,sIel
1000 11\ I madOOO ,1m
01011
1000legl111
'"
XCH8= heung.:
RegislerlmemolY wrth register
Regisler with actumulalar
I' 000011 W Imod '"
1'0010 reg I
Ilil-inpullrom:
Fiudporl
Valiablepoll
11110010 W I
"m
I' 0 0111 11
100 II 11 0
10011100
100111 0 I
I
pOll
'"
re~
'"
000 I DOd IN m.'
"m
100000 s w modO 1 0 "m
dala
100010 lOw
'"
'"
I
dala
dalallw 1
1000005 w modi II "m
0011 I lOw
dala
dala
dala Iisw 01
dalarlw 1
~
~
I'I II 0 I I WImod 100
1III011w
11010100
1 I 11 0 11 W
1111011w
11 0 1 0 101
10011 000
10011 001
"m
mod 10 I "m
00001010
mod 11 0 "m
mod 111 rim
00001010
1I0Tln'wl
1111011 w modO
SNL/SAL ShIIllo~lcal/a"'hme"c lell I' 0 1 00 v w mod I
SJlRShlllloQ,eallighl
111 0 I 0 0 v w Imodl
SAR Sh,lIaldhmetlclight
1'10100 v w Imod'
ROLRolalelelt
110100 v w modO
RORRolatelight
1111111 0 v w modO
RCLRolalelhloughcailyliagleft
110 I 0 0 v w modO
RCRRolalelhroughcarryrrghl
11 0 1 0 0 v w modO
1 0 "m
0 0 "m
0 1 "m
11 "m
0 0 ,1m
AND And:
Reg Imemory and reglsler 10 ellher
Jmmetbale10 leglsler/nlemary
Immed,aleto accumulalor
..,
0 I um
1 0 "m
11 "m
001000 d w mod
"m
1000000 w mod' 00 11m
00' 0 010 w
dala
data
dala,'w 1
daladw 1
TEST AndlunclionIDIIIDI,nor •• ult:
Regrsler/memolyand reglsler
I' 000010 w jmod
"m
Immedlaleda'aandleglslel/memory 1111011w modO 0 0 11m
Immedlatedala and Iccumulatar
'010100 w
dala
dlla
dala,lw'
dati It. I
O. Dr:
Reg Imemoryandleglslerlaellher
Immedlalela reglsler/memory
Immed,ale10 accumulalOI
OOOOIDdw mod
"m
1000000 w modO 01 "m
000011 0 w
data
dala
datalfw"
dala
datarlw·l
dalarlw'
IDR'Elclullv•• r:
Reg./memolyandreglslerlaerlher
Immedrllelolegrslellmemory
fmmedrale10 accumulalol
,1m
0011 0 Od w mod
1000000 w modI' 0 "m
00 II 0 lOw
dlla
dala
dalall. I
dalallw 1
datarlsw 01
dala II
.,
111111,. modO 0 0 ,1m
01000
00110111
00100111
..,
00101 Od w mod
"m
100000 s '" modi 0 1 "m
001011 0 w
dala
data
dalailw-'
da'a,I sw·Ot
..,
000110 It w m,'
"m
100000. w modO 11 "m
000111 0 w
dala
daliil
datlilw'l
'"
5111'01
IIC-IKruIIIIl:
111-SUlllrlClwltlllllrnw
Reg./memorr.nd register laeilh.r
Immtdi.lllrom reglstlr/m,mary
Immtdi.lllromlccLimul.tor
"m
001110 d w
Immediate with leg.ster/memory
ImmedlalewllhaccumulalOI
'"
ADC -MII.HllaIlY:
Rea·/mtmoryw"hreai$ler'oerlt1er
Immtdial.,olIgisler/memory
Immldi.1I10 accumula'or
Rq./mimoryanclrigilierlolilher
..,
mod
Reglslrrlmemory and reglsler
LOGIC
1110011w
1110lllw
11 0 1 0 I 11
10001101 mod
11 0 0 0 101 mod
11 100 III 0 0 Imod
000000 d w mod
<1m
1000005 w modO 0 0 ,1m
0000010 w
dala
Immedial.'rom If'.IIistellmemory
Immedlal,llomaccumUlalo,
"m
tampuI:
115 .. 3 2 I 0
porI
Rtt!./m.morywlthregisllrloei'hli
Immldi.'.,oregisl.r/memory
Immedlale10 ItCl/mutator
lUI -IIIMnct
~
11111011 w tmodO 11
7150210
I
I 111 0 110 wi
ARITHMEnC
ADD-Add,
Re;isllrlmemory
Rl;islll
UAaASCl1 adjUlI for add
IUr-Dlcimll.djustlorldd
765 .. 3Z I 0
I
OUT-OulputIO:
Fixed porI
Vallabl.parl
ILAT-Translal.by'eloAl
W-LoadEAloreg'sler
LDI·La.dpoinlelloDS
W·loadpoinllrtoES
LAIIF'LoadAHwilhllags
.AIIF,S!oreAHmlalllgs
'","F·Pushliags
PO"~Pop lIaas
a
IEB-ChangeSlgn
AlSASCllad,uSllorsubtracl
DAS Oetlmalad,uSllcrsublracl
IIIUl MulhplylunSlgnedl
IIUL Iniegermuiliply ISlgnedl
AlM ASCII adlUSI lor mul!lply
DIVD,v,(!elunslgnedl
IDI¥lnlegp.rdlvlde!srgnedl
AlOASCliadJuSlloldrvrde
caw Canvertbylt10 WDrd
cwo Canvert word to double wOld
111 I 1 II 1 mod 11 0 ,1m
01010 reg
000legll0
115 .. 321
11111111 w ImoclO 01 "m
Register
eMP
rUIH= 1'a.1I:
Regislerlmeml:lly
Reglsler
Segmenlregisler
Dlullalnl:
Reglslrr/memory
"m
"m
'"
I mod 000
dl!lII sw·Ol
'"
STRINO MANIPULATIDN
REP=Repeal
MOVS'MoYII bylefward
CMPS=CDmplllbyle{word
SCAS=SClnbyle/word
LDDS*LoadbvlelwdloALfAX
STOS=StorbylelwdlromALfA
1" 11001 Z I
'0 10010 w
10 I 0 0 11 w
10 1011 I w
101011 0 w
ItO I 0 I 0 1 w
I
Mnemonics ©Intel, 1978
8-23
AF~'497B
iAPX 86/10
Table 2, Instruction Set Summary (Continued)
CONTROL TRANSFER
CAll
0
CIII,
16543210
11
11
11
Direct within segment
Indirecl within segmerlt
Direct mlersegment
11
Indirect intersegment
JMP
=
16543210
16543210
76543210
I !lIsp-low
1 1 1 1 1 1 1 Imod 0 1 0 rIm
00 110 10 I
offset-low
I
seg-Iow
I
I
I
I
1 1 l I t 1 1 fmo!! 01 1 rIm
I
1 1 0 1 000
drsp:hlgh
I
JNB/JAEoJump on not below/above
or equal
JNBE/JAoJump on not below or
equal/above
JNP/JPO=Jump on nol par /par odd
olfset-high
JNOt-short
Indirecl within segment
Direct intersegment
1 10 100 1
\
seg-Iow
dlsp-hlgh
I
Olfset-hlghWO]
111100010]
11 1 1 0 0 0 0 1 I
=
Relurn from CALl:
Within seg. addmg Immed 10 SP
dlsp
disp
disp
]
I
I
I
I
I
dlsp
I
I
dlsp
dlsp
l1IDO'101~
l'
on overflow
IRET-Interruptreturn
Fll~l;,,;O~O;;O~O~',;:'f--,-,--.,.---,--;c:c-::-c:--,
Within segment
I 1·00000 I
II 1 1 000 1 1 I
11
disp
Interrupt
INTO~lnterrupt
RET
I
10 1 1. 1 tOOl
LOOP Loop CX times
LOOPZlLOOPE· Loop while zero/equal
LOOPNZlLOOPNE loop .... hlle not
zero/equal
JCll-Jump on CX zero
TypespCClfled
Type 3
111111111 ImOd 1 0 1 rim
Indrrecl mlersegment
765432 I 0
dlsp
I
disp
1011100011
JNS·Jump on nol Sign
tNT
Seg-high]
!0 , 1 '·0 nIl I
[0 1 1 1 0 1 1 1 I
10 1 1 1 1 0 1 1 I
I
00 1 1 0 0
1
1" 00111 0 I
1110 01111 I
data-low
data-hlgO
Fll~l,=O~O,=O;;O~'o~_--=="----'--"
11
i 001011
lntersegment. adding Immediate to SP FllC"C'O~O'='=l0'='=,~Of-----,;==--,---:;:::-;:::;:--,
data-low
data·hlgh I
PROCESSOR CONTROL
JE/Jl=Jump on equal/zero
JL/JNGE~~Ue~~a)n leSS/ni)l greater
101 1 1 0 1 00
~IO'='~'~'~''=,o~oF=~";;;;~-=\
disp
CLC Clear carry
CMC Complement carry
JLE/JNGg~~~~ron less or equal/not
JB/JN,U~~Ue~ea~n below/not above
Ip:O,,;l,,;l,,;l,,;l~l~l,,;O+~~~=4
dlsp
dlsp
(p:0,,;1,,;1,,;1,,;0;,;0~1,,;0+~~~=4
111 '11000
11 I 1·1 0 1 0 I
STC Sel carry
CtD Clear direction
11111 .. '.001 I
111111100
JBE/JNA~~~~~o~~ below or equal!
dlsp
1F.0,,;1,,;1=:1;,,;0~1C",=0+~~:"'==4
dlsp
1~0=1",.1=1=1",0='C'0*======4
dlsp
Ip:O;";l,,,l;,,;l,,;O;,;O,,;O;,,;O~IF=~::;;"'===i
STO Set direction
111111.101
CLI Clear Interrupt
111111010
STI Set Interrupt
10 1 1 1 1 000 I
liLT Halt
lii.i.iili:iJ
'1 1 , 1 0 1 00 I
11 a a , 1 0 1 1 I
Intersegment
JP/JPE·Jump on parity/parity even
JO~Jump on over/low
JS~Jump on sign
dlsp
dlsp
disp
JNE/Jlll=Jump on nol equal/nolzero p:0;,,;1,,;1,,;1;,;0~1;,;0~1*=~~=4
JNL/JGE;~ue~ea)n not less/greater
01111101
dlsp
WAIT Walt
ESC Escape
JNLE/JGg~~~~/n not less or equal! IP:O;";'~';";'~'~';';'~'*I=~~~=i
dlsp
(to e~ternal
deVice)
LDCK Bus lock prefix
I
I
I
I
i
~~xFo~imJ
[i"!!2!YTOJ
Footnot..:
Al '" 8-bit accumulator
AX '" 16-bit accumulator
ex '" Count register
OS Data segment
ES Extra segment
Above/below refers to unsigned value.
Greater", more positive;
less'" less positive (more negative) signed values
·\f d =1 then "to" reg; if d '" 0 then "from" reg
if w:: 1 then word instruction; if w '" a then byte instruction
0
0
if
if
if
if
mod 11 then
mod = 00 then
mod = 01 then
mod = 10 then
0
rim is treated as a REG field
OISP 0', disp-Iow and disp-high are absent
OISP = disp-Iow sign-extended to 16-bits, disp-high is absent
OISP = disp-high: disp-Iow
EA = (BX) , (SI) , OISP
EA (BX) , (01) , OISP
EA (BP) , (SI) , OISP
EA (BP) , (01) , OISP
EA = (SI) , OISP
EA (01) , OISP
EA (BP) ,0ISP'
EA = (BX) , OISP
byte of instruction (before data if required)
'except if mod
00 and rim
=
SEGMENT OVERRIDE PREFIX
10 0 1 reg 1 1 01
REG is assigned according to the following table:
0
if rim 000 then
if rim = 001 then
if rim = 010 then
if rim = 011 then
if rim = 100 then
if.r 1m = 101 then
if rim = 110 then
if rim = 111 then
OISP follows 2nd
0
if s:w=01then 16 bits of immediate data form the operand.
if s:w = 11 then an immediate data byte is sign extended to
form Ihe 16-bit operand.
if v = 0 then "count" = 1: if v = 1 then "count" in (Cl)
x = don't care
z is used for string primitives for comparison with Z.F FLAG.
f6-BIt (w tl
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 SI
111 01
0
0
0
0
8-BIt Iw' 0)
000 Al
001 Cl
010 Ol
011 Bl
100 AH
101 CH
110 OH
111 BH
Segment
00 ES
01 CS
10
S5
11 OS
0
0
0
110 then EA
0
disp-high: disp-Iow.
Instructions which reference the flag register file as a 160bit object use
the symbol FLAGS to represent the file:
FLAGS
0
X:X:X:X:(OF): (OF) :(IF):(TF) :(SF):(ZF) :X: (AF):X: (PF): X:(CF)
Mnemonics© Intel, 1978
AFN-D14978
MILITARY iAPX 86/10
16-81T HMOS MICROPROCESSOR
(M8086)
MILITARY
Direct Addressing Capability to 1
• MByte
of Memory
Assembly Language Compatible with
• 8080/8085
14 Word, By 16·Bit Register Set with
• Symmetrical
Operations
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Operations
16·Bit Signed and Unsigned
• 8·and
Arithmetic in Binary or Decimal
Including Multiply and Divide
• 5 MHz Clock Rate
MULTIBUS™ System Compatible
• Interface
Temperature Range:
• Military
-55°C to +125°C
The Intel® Military iAPX 86/10 is a new generation, high performance 16-bit microprocessor implemented in N-channel,
depletion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of
both 8- and 16-bit microprocessors. It addresses memory as a sequence of8-bit bytes, but has a 16-bit wide physical path to
memory for high performance.
EXE.CUTION UNIT
REGISTER FILE
BUS INTEAFACE UNIT
I
RELOCATION
REGISTER FILE
I
DATA.
POINTER. AND
INDEX REGS
18 WORDS)
,-....0..."--'-_ iiiirl51
A,glS 6
GND
Vee
AD14
A01S
ADI3'
A16/S3
AD12
A 17/S4
AD11
A18/S5
AD10
A19/S6
AD9
BHE/S7
A,6tSl
6·8VTE
INSTRUCTION
QUEUE
AD8
MN/MX
AD7
Ali
AD6
RO/GTO (HOLD)
AD5
RO/GT1 (HLDA)
AD4
LOCK
(WA)
AD3
(M/iO)
AD2
52
51
ADI
so
(DEN)
ADO
aso
(ALE)
NMI
aSl
«NTA)
INTR
TEsT--_r------~~------,
IN'--_
NMI---
CONTROl & TIMING
(DTii'i)
TEST
CLK
READY
GND
RESET
HOLO--HLDA--...-r__- , -__. - -__-.---c~
eLK
RESET
READY
GND
V"
Figure 1. Functional Block Diagram
Figure 2. Pin Configuration
Intel Corporation Assumes No Responaibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenaes 8,e Implied.
@INTELCORPORATION. 19BO
8-25 .
AFN-Q1237B
18086
16·81T HMOS MICROPROCESSOR
INDUSTRIAL
Grade Temperature
• Industrial
Range: -40°C to +85°C
• 24 Operand 'Addressing Modes
• Bit, Byte, Word, and Block Operations
and 16·Bit Signed and Unsigned
• 8·Arithmetic
in Binary or Decimal
Direct Addressing Capability to 1
• MByte
of Memory
Including Multiply and Divide
Language Compatible with
• Assembly
MCS·80,85®
• 5 MHz Clock Rate
MULTIBUS™ System Compatible
• Interface
14 Word, By 16·Bit General Register
• Set
The 'Intell!> Industrial iAPX 86/10 is a new generation, high performance microprocessor implemented in N-channel,
depletion load, silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributE/lIof both 8- and 16-bit microprocessors. It addresses memory as a sequence of 8-bit bytes, but has a 16-bit wide
physical paih to memory for high performance.
EXECUTION UNIT
BUS INTERFACE UNIT
REGISTER FILE
I A~~~~f:~I~~E I
DATA.
POINTER. AND
INDEX REGS
laWORDS)
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(SWORDS)
GND
VCC
AD14
AD15
AD13
Al61S3
AD12
A17/54
r-"":::"c.,..,-_ IIItEIS,
AD11
A1B/S5
AlrSa
AD10
A19/S6
A,IIS3
AD9
BHelS7
FLAGS
3
OTlR.DEN.ALE
AD8
MN/MX
AD7
Rii
AD6
RQ/iffij (HOLD)
AD5
RQ/GT1 (HlDA)
AD4
lOCK
(WA)
AD3
52
51
SO
(M/iO)
ADO
OSO
(ALE)
NMI
OSl
(MA)
A.D2
6·BYTE
INSTRUCTION
·QUEUE .
ADl
INTR
fEs'f-.. . - - - ' - - " ' " " ' - - - - - ,
'NT-_
.,,'-ROtolo.1
(DT/ii)
(DEN)
TEST
ClK
READY
GND
RESET
CONTROL & riMING
2
HOLD--
3
HLD.-"'"'L-r_.---,;----,;--~:-'
elK
I
RESET READY MN/MX
Sa,51,So
40 LEAD
aND
Vee
Figure 2_ 18086 Pin Diagram
Figure 1_ 18086 CPU Functional Block Diagram
8-26
iAPX 88/10
(8088)
8-BIT HMOS MICROPROCESSOR
• 8·Bit Data Bus Interface
• 24 Operand Addressing Modes
• 16·Bit Internal Architecture
• Byte, Word, and Block Operations
• Direct Addressing Capability to 1 Mbyte
of Memory
• 8-Bit and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal,
Including Multiply and Divide
• Direct Software Compatibility with
iAPX 86/10 (8086 CPU)
• Compatible with 8155·2, 8755A·2 and
8185·2 Multiplexed Peripherals
• 14-Word by 16-Bit Register Set with
Symmetrical Operations
The Intel® iAPX 88/10 is a new generation, high performance microprocessor implemented in N-channel, depletion load,
silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of both 8- and
16-bit microprocessors. It is directly compatible with iAPX 86/10 software and 8080/8085 hardware and peripherals.
MEMORY INTERFACE
C·BUS
MIN
MODE
INSTRUCTiON
STREAM BYTE
OUEUE
GND
Vee
A1'
A1S
A13
A16/S3
A12
A17IS4
All
A18/S5
A10
CS
BUS
INTERFACE
UNIT
SS
A19JS6
A9
SSO
AS
MN/MX
(HIGH)
OS
AD7
IP
AD6
HOLD
(RQ/GTD)
ADS
HlDA
(RO/Gfi)
AD.
m
(lOCK)
AD3
101M
(52)
AD2
DTill
(Si)
AD1
!lEN
(so)
ADO
ALE
(OSO)
NMI
INTA
(OS1)
INTR
TEST
A·BUS
EXECUTION
UNIT
1
[MAX
MODE
AH
BH
CH
Al
Bl
Cl
DH
Dl
SP
!iii
BP
ClK
READY
SI
GND
RESET
01
FLAGS
Figure 1. iAPX 88/10 CPU Functional Block Diagram
8-27
Figure 2. iAPX 88/10 Pin Configuration
iAPX 88/10
Table 1. Pin Description
The following pin function descriptions are for 8088 systems in either minimum or maximum mode. The "local bus" in
these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to additional bus
buffers).
.
Symbol
AD7-ADO
Pin No•.. "TYpe
Name and Function
9-16
I/O
Address Data Bus: These lines constitute the time multiplexed memory/IO
address (T1) and data (T2, T3, Tw, and T4) bus. These lines are active HIGH and
float to 3-state OFF during interrupt acknowledge and local bus "hold acknowl. edge".
A15-A8
2-8,39
0
Address Bus: These lines provide address bits 8 through 15 for the entire bus
cycle (T1-T4). These lines do not have to be latched by ALEto remain valid.
A15-A8 are active HIGH and float to 3-state OFF during interrupt acknowledge
and local bus "hold acknowledge".
A19/56, A18/55, .
A17/54, A16/53
34-38
0
Address/Status: During T1, these are the four
most significant address lines for memory operations. During I/O operations, these lines are
LOW. During memory and I/O operations, status
information is .available on these lines during
. T2, T3, Tw, and T4. 56 is always low. Thestatuscif
the interrupt enable flag bit (55) is updated at
the beginning of each clock cycle. 54 and 53 are
encoded as shown.
..
.3
,
,
CHARACTERISTICS
OllOW)
0
0
AI'ernaleData
1 (HIGH)
0
Stack
Code or None
Data
,
S6isO(LOW}
This information indicates which segment register is presently being used for data accessing.
These lines float to 3-state OFF during local bus
"hold acknowledge".
RD
32
0
Read: Read strobe indicates that the processor is performing a memory or I/O
read cycle, depending on the state of the 10/fiil pin or 52. This signal is used to
read devices which reside on the 8088 local bus. RD is active LOW during T2, T3
and Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the 8088
local bus has floated.
This signal floats to 3-state OFF in "hold acknowledge".
READY
22
I
READY: is the acknoWledgementfrom the addressed memory or I/O device that
it will complete the data transfer. The RDY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. This Signal is active
HIGH. The 8088 READY input is not synchronized. Correct operation is not
guaranteed if the set up and hold times are not met.
INTR
18
I
Interrupt Request: is a level triggered input which is sampled during the last
clock cycle of each instruction to determine if the processor should enter into an
interrupt acknowledge operation. A subroutine is vectoreq to via an interrupt
vector lookup table located in system memory. It can be internally masked by
software resetting the interrupt enable bit.INTR is internally synchronized. This
signal is active HIGH.
TE5T
23
I
TEST: input is examined by the "wait for test" instruction. If the TE5T input is
LOW, execution continues, otherwise the processorwaits in an "idle" state. This
input is synchronized internally durin!;! each clock cyde on the leading edge of
CLK.
NMI
17
I
Non-Maskable Interrupt: is an edge triggered input which causes a type 2
interrupt. A subroutine is vectored to via an interruPtv~ctor lookup table located
in system memory. NMI is not maskable internally by software. A transition from
a LOW to HIGH initiates the interrupt at the end of the current instruction. This
input is internally synchronized.
d
AFN.()()826B
iAPX 88/10
Table 1. Pin Description (Continued)
Pin No.
Type
Name and Function
RESET
Symbol
21
I
RESET: causes the processor to immediately terminate its present activity. The
signal must be active HIGH for at least four clock cycles. It restarts execution,as
described in the instruction set description, when RESET returns Law. RESET
is internally synchronized.
eLK
19
I
Clock: provides the basic timing for the processor and bus controller. It is
asymmetric with a 33% duty cycle to provide optimized internal timing.
Vee
40
GND
1,20
MN/MX
33
Vee: is the. +5V ±10% power supply pin.
GND: are the ground pins.
I
Minimum/Maximum: indicates what mode the processor is to operate in. The
two modes are discussed in the following sections.
The following pin function descriptions are for the 8088 minimum mode (i.e., MN/MX = VecJ. Only the pin functions which
are unique to minimum mode are described; all other pin functions are as described above.
IO/M
28
a
Status Line: is an inverted maximum mode S2. It is used to distinguish a
memory access from an I/O access. 10/M becomes valid in the T4 preceding a
bus cycle and remains valid until the final T4 of the cycle (I/O=HIGH, M= LOW).
10/M floats to 3-state OFF in local bus "hold acknowledge".
WR
29
a
Write: strobe indicates that the processor is performing a write memory or write
I/O cycle, depending on the state of the 10/M signal. WR is active for T2, T3, and
Tw of any write cycle. It is active LOW, and floats to 3-state OFF in local bus "hold
acknowledge" .
INTA
24
a
INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW
during T2, T3, and Tw of each interrupt acknowledge cycle.
ALE
25
a
Address Latch Enable: is provided by the processor to latch the address into
the 8282/8283 address latch. It is a HIGH pulse active during clock low of T1 of
any bus cycle. Note that ALE is never floated.
DT/R
27
a
Data Transmit/Receive: is needed in a minimum system that desires to use an
8286/8287 data bus transceiver. It is used to control the direction of data flow
through the transceiver. Logically, DT/R is equivalent to 51 in the maximum
mode, and its timing is the same as for 10/M (T=HIGH, R=LOW). This signal
floats to 3-state OFF in local "hold acknowledge".
DEN
26
a
Data Enable: is provided as an output enable for the 8286/8287 in a minimum
system which uses the transceiver. DEN is active LOW during each memory and
I/O access, and for INTA cycles. For a read or INTA cycle, it is active from the
middle of T2 until the middle of T4, while for a write cycle, it is active from the
beginning ofT2 until the middle ofT4. DEN floats to 3-state OFF during local bus
"hold acknowledge".
30,31
1,0
HOLD: indicates that another master is requesting a local bus "hold". To be
acknowledged, HOLD must be active HIGH. The processor receiving the "hold"
request will issue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or
TI clock cycle. Simultaneous with the issuance of HLDA the processor will float
the local bus and control lines. After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it
will again drive the local bus and control lines.
HOLD,HLDA
Hold is not an asynchronous input. External synchronization should be
provided if the system cannot otherwise guarantee the set up time.
SSO
34
a
Status line: is logically equivalent to SO in t~
maximum mode. The combination of SSO, 10/M
and DT/R allows the system to completely decode the current bus cycle status.
8-29
''0
,, ,,
,
: ,
101M
DTJR
~ (HIGHI
0
0
0
0
~~::eIIO port
0
0
0
Code access
Read memory
0
~:~~~v;emOfY
,,
o (LOW)
0
0
0
CHARACTERISTICS
Interrupt Ac~nowledge
Read 1/0 pori
AFN·008268
iAPX 88/10
Table 1. Pin Description (Continued)
The fol/owing pin function descriptions are for the 8088, 8228 system in maximum mode (i.e., MN/MX=GND.) Only the pin
functions which are unique to maximum mode are described; aI/ other pin functions are as described above.
Symbol
S2, S1, SO
Pin No.
26-28
Type
o
Name and Function
Status: is active during clock high of T4, T1,
and T2, and is returned to the passive state
(1,1,1) during T3 or during Tw when READY is
HIGH. This status is used by the 8288 bus controller to generate all memory and I/O access
control signals. Any change by S2, 51, or SO
during T4 is used to indicate the beginning of a
bus cycle, and the return to the passive state in
T3 or Tw is used to indicate the end of a bus
cycle.
,
,,
1 (HIGH)
These signals float to 3-state OFF during "hold
acknowledge". During the first clock cycle after
RESET becomes active, these signals are active
HIGH. After this first clock, they float to 3'state
OFF.
.
RQ/GTO,
RQ/GT1
30,31
I/O
Request/Grant: pins are used by other local bus masters to force the processor
to release the local bus at the end of the processor's current bus cycle. Each pin
is bidirectional with RQ/GTO Having higher priority than RQ/GT1. RQ/GT has an'
internal pull-up resistor, so may be left unconnected. The request/grant sequence is as follows (See Figure 8):
1. A pulse of one ClK wide from another local bus master indicates a local bus
request ("hold") to the 8088 (pulse 1).
2. During a T4 or TI clock cycle, a pulse one clock wide from the 8088 to the
requesting master (pulse 2), indicates that the 8088 has allowed the local bus
to float and that it will enter the "hold acknowledge" state at the next ClK.
The CPU's bus interface unit is disconnected logically from the local bus
during "hold acknowledge':. The same rules as for HOLD/HOLDA apply as for
when the bus is released.
3. Apulse one ClK wide from the requesting master indicates to the 8088 (pulse
3) that the "hold" request is about to end and that the 8088 can reclaim the
local bus at the next ClK. The CPU then enters T4.
Each master-master exchange of the local bus is a sequence of three pulses.
There must be one i'dle ClK cycle after each bus exchange. Pulses are active
lOW.
If the request is made while the CPU is performing a memory cycle, it will release
the local bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit ofa word.
3. Current cycle is not the .first acknowledge of an interrupt acknowledge
sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will
follow:
1. local bus will be released duririg the next clock.
2. A memory cycle will start within 3 clocKs. Now the four rules for a currently
active memory cycle apply:with condition number 1 already satisfied.
8-30
AFN.()()826B
iAPX 88/10
Table 1. Pin Description (Continued)
Symbol
lOCK
aS1, aso
Name and Function
Pin No.
"TYpe
29
a
lOCK: indicates that other system bus masters are not to gain control of the
system bus while lOCK is active (lOW). The iJ5CR signal is activated by the
"lOCK" prefix instruction and remains active until the completion of the next
instruction. This signal is active lOW, and floats to 3-state off in "hold acknowledge".
24,25
a
Queue Status: provide status to allow external
tracking of the internal 8088 instruction queue.
a51
aso
OlLOW~
0
0
The queue status is valid during the ClK cycle
after which the queue operation is performed.
-
34
a
,
I(HIGH)
,
,
0
CHARACTERISTICS
No operation
First tlyta of ope ode from queue
Empty the queue
Subsequ~nl byte from queue
Pin 34 is always high in the maximum mode.
8-31
AFN-00626B
inter
iAPX 88/10
the next higher address location. The BIU will automatically execute two fetch or write cycles for 16-bit
operands.
FUNCTIONAL DESCRIPTION
Memory Organization
The processor provides a 20-bit address to memory which
locates the byte being referenced. The memory is. organized as a linear array of up to 1 million bytes, addressed
as OOOOO(H) to FFFFF(H). The memory is logically divided
into code, data, extra data, and stack segments of up to
64K bytes each, with each segment falling on 16-byte
boundaries. (See Figure 3.)
All memory references are made relative to base
addresses coritained in high speed segment registers. The
segment types were chosen based on the addressing
needs of programs. The segment register to be selected is
automatically chosen according to the rules of the following table. All information in one segment type share the
same logical attributes (e.g. code or data). By structuring
memory into relocatable areas of similar characteristics
and by automatically selecting segment registers, programs are shorter, faster, and more structured.
Word 06-bit) operands can be located on even or odd address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower
valued address location and the most significant byte in
D}
~FFFFFH
..IKe
-~
CODE SEGMENT
RESET BOOTSTRAP
PROGRAM JUMP
~L..--I-_~
ORO
I
Minimum and Maximum Modes
The requirements for supporting minimum and maximum 8088 systems are sufficiently different that they
cannot be done efficiently with 40 uniquely defined
pins. Consequently, the 8088 is equipped with a strap
pin (MN/MX) which defines the system configuration.
The definition of a certain subset of the pins changes,
dependent on the condition of the strap pin. When the
MN/MX pin is strapped to GND, the 8088 defines pins 24
through 31 and 34 in maximum mode. When the MN/MX
pin Is strapped to Vee, the 8088 generates bus control
signals itself on pins 24 through 31 and 34.
XXXXOH
} STACK SEGMENT
SEGMENT
REGISTER FilE
Certain locations in memory are reserved for specific
CPU operations. (See Figure 4,) Locations from addresses FFFFOH through FFFFFH are reserved for
operations including a jump to the initial system initializationroutine. Following RESET, the CPU will always
begin execution at location FFFFOH where the jump
must be located. Locations OOOOOH through 003FFH are
reserved for interrupt operations. Four-byte pOinters
consisting of a 16-bit segment address and a 16-bitoffset address direct program flow to one of the 256 possible interrupt service routines. The pOinter elements are
assumed to have been stored at their respective places
in reserved memory prior to the occurrence of interrupts.
•
FFFFFH
lFFFFOH
\
MSB
E~3~~E~~==~Wl--;\~':-:::=E1 J
INTERRUPT POINTER
FOR TYPE 25S
3FFH
3FOH
DATA SEGMENT
OS
ES
•
7H
INTERRUPT POINTER
FOR TYPE 1
}EXTRA DATA SEGMENT
L-+_-!
INTERRUPT POINTER
FOR TYPE 0
~OOOOOH
Figure 3. Memory Organization
Memory
Reference Need
Instructions
4H
3H
OH
Figure 4. Reserved Memory Locations
Segment Register
Used
Segment
Selection Rule
CODE (CS)
STACK (SS)
Automatic with all instruction prefetch.
Stack
Local Data
DATA (DS)
Data references when: relative to stack, destination of string
operation, or explicitly overridden.
External (Global) Data
EXTRA (ES)
Destination of string operations: Explicitly selected using a
segment override.
All stack pushes and pops. Memory references relative to BP
base register except data references.
8-32
AFN.()()826B
iAPX88/10
The minimum mode 8088 can be used with either a
multiplexed or demultlplexed bus. The multiplexed bus
configuration Is compatible with the MCS·85™ multi·
plexed bus peripherals (8155, 8156, 8355, 8755A, and
8185). This configuration (See Figure 5) provides the user·
with a minimum. chip count system. This architecture
provides the 8088 processing power in a highly integrated
.
form.
The demultiplexed mode requires one latch (for 64K ad·
dressability) or two latches (for a full megabyte of ad·
dressing). A third latch can be used for buffering if the
address bus loading requires it. An 8286 or 8287 trans·
ceiver can also be used if data bus buffering is required.
(See Figure 6,) The 8088 provides i5EFl and DTiR to con·
trol the transceiver, and ALE to latch the addresses.
This configuration of the minimum mode provides the
standard demultiplexed bus structure with heavy bus
buffering and relaxed bus timing requirements.
The maximum mode employs the 8288 bus controller.
(See B9ure 7,) The 8288 decodes status lines SO, 51,
and 52, and provides the system with all bus control
signals. Moving the bus control to the 8288 provides
better source and sink current capability to the control
lines, and frees the 8088 pins for extended large system
features. Hardware lock, queue status, and two requestl
grant interfaces are provided by the 8088 in maximum
mode. These features allow co·processors in local bus
and remote bus configurations.
8-33
AFN.QOII26B
iAPX 88/10
TPOR~~
I
Vee
H-
eE
PORT~
WR
RD
.
ALE
DATAl
C
ADo- ADT
elK
AODR/DATA
'l
AODR
IN_
101M
TIMER
OUT
~
ALE
I-~
,...
r-
8088
Vee
rD1
X,
r-
READY
t--
I
RESET
I--
PORT
A
W
A S10
8355 ' 87S5A
DATAl
ADOR
I--vcc
l-
I-
101M
RD
I--
I-- t-
RESET
WR
I--
101M
I-
RES
8284A
RESET
CE
ALE
X2
elK
-V
READY
MNIMX
I---
RO
L..-
.---
•
(6)
lOW
ADOR
V
.----
'
PORT~
RESET
Aa- A19
B
8155
I-
GND
PORT
B
iOR
~
~c
IIIt
Vss Vee VOD PROG
WR
AD
eEl 8185
ALE
\-1-II-I-
CS, CE 2
As ,A 9
AD07
t I
v"
Vee
"V"J
Figure 5. Multiplexed Bus Configuration
8-34
AFN-00826B
iAPX 88/10
lUi
r
8284A
CLOCK
QENERATOR
CLK
UN/iii l..-VCC
READY
1m!
1
....
GND
"
101M
RESET
ROY
""
WJO
CPU INTA
OTII!
!fER
ALE
q~
r---:l
I
srs
GN~_+r-----: OE
:
8282
LATCH
(1,20R 3)
r--v
ADf)-AO,
ADORIDATA
As-A" ~
ADDRESS
~
INTR
D=
T
Of
8286
DATA
TRANSCEIVER
F
1\
1111 111r 11
Jll
8259A
INTERRUPT
CONTROL
W'ODII
2142 RAM (2)
1-
INT
2716·2 PROM
0'11 B ~WR I
Mes·so
PERIPHERAL
I
~IRO-T
~
Figure 6. Demultlplexed Bus Configuration
r
lUi
8284A
CLOCK
GENERATOR
1m!
1
ROY
~
MNIMj'
elK
GND
elK
READY
So
So
S;
S;
RESET
S,
0;
r-
-
B088
CPU
GND
MADe
MWTC
8268
BUS
=lORe i-
NC
_
DEN CTRlR lowe
Alowe r-N
OTiR
C
IHTA
ALE
r---:l
I
I
STB
Of
GND
ADo-AD,
As-A" rOORIOA~
LATCH
(1,20Rl)
INT
0=
1
8282
ADDRESS
J
I
T
Of
II
I
8286
TRANSCEIVER
DATA
ill
-----'\
F
1
WEODII
IN::~~~PT 1 CONTROL
I I
1l 111r 111
2142 RAM (2)
V
II
27162 PROM
o'IIB
II
•
~WRI
Mes·so
PERIPHERAL
I
~IRO-T
'---
Figure 7. Fully Buffered System Using Bus Controller
8-35
AFN-00826B
iAPX 88/10
Bus Operation
tion, the bus can be demultiplexed at the processor with
a single address latch if a standard, non-multiplexed
bus is desired for the system.
The 8088 address/data bus is broken into three parts the lower eight address/data bits (ADO-AD?), the middle
eight address bits (A8-A15), and the upper four address
bits (A16-A19). The address/data bits and the highest
four address bits are time multiplexed. This technique
provides the most efficient use of pins on the processor, permitting the use of a standard 40 lead package.
The middle eight address bits are not multiplexed, i.e.
they remain valid throughout each bus cycle. In addi-
Each processor bus cycle consists of at least four eLK
cycles. These are referred to as T1, T2, T3, and T4. (See
Figure 8), The address Is emitted from the processor
during T1 and data transfer occurs on the bus during T3
and T4. T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" Indication Is given by the addressed device,
! - - - - - - - { 4 + N W A I T ) " " T C y - - - - - _ j_ _ _ _ _ _ (4+NWAIT)_TCy _ _ _ _ _- j
T,
T,
T3
TWAIT
I
14
T,
12
13
I
TWAIT
14
elK
GOES INACTIVE IN THE STATE
~~'- - -_- - LJ. /~UJ. /.L LJ/um/ ~ ~'
\-----
ADDRfSTATUS
ADDR
ADDRIDATA
-----8______
----)---QC
0_AT_A_O_"T_IO_,._O,_1
READY
DT/R
\'---_---1/
Figure 8. Basic System Timing
8-36
AFN-008268
iAPX 88/10
EXTERNAL INTERFACE
"wait" states (Tw) are inserted between T3 and T4. Each
inserted "wait" state is of the same duration as a ClK
cycle. Periods can occur between 8088 driven bus
cycles. These are referred to as "idle" states (Ti), or inac·
tive ClK cycles. The processor uses these cycles for internal housekeeping.
Processor Reset and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8088 RESET is
required to be HIGH for greater than four clock cycles.
The 8088 will terminate operations on the high-going
edge of RESET and will remain dormant as long as
RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 7
clock cycles. After this interval the 8088 operates normally, beginning with the instruction in absolute location FFFFOH. (See Figure4J The RESET input is internally synchronized to the processor clock. At initialization, the HIGH to lOW transition of RESET must occur
no sooner than 50 p's after power up, to allow complete
initialization of the 8088.
During T1 of any bus cycle, the ALE (address latch
enable) signal is emitted (by either the processor or the
8288 bus controller, depending on the MN/m strap). At
the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched.
Status bits SO, 81, and S2 are used by the bus controller,
in maximum mode, to identify the type of bus transaction according to the following table:
S2
o (low)
0
0
0
1 (High)
1
1
1
S1
SO
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CHARACTERISTICS
If INTR is asserted sooner than nine clock cycles after
the end of RESET, the processor may execute one instruction before responding to the interrupt.
Interrupt Acknowledge
Read I/O
Write I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
Passive (no bus cycle)
All 3-state outputs float to 3-state OFF during RESET.
Status is active in the idle state for the first clock after
RESET becomes active and then floats to 3-state OFF.
Interrupt Operations
Status bits S3 through S6 are multiplexed with high
order address bits and are therefore valid during T2
through T4, S3 and S4 indicate which segment register
was used for this bus cycle in forming the address according to the following table:
S4
o (low)
0
1 (High)
1
S3
0
1
0
1
CHARACTERISTICS
Alternate data (Extra Segment)
Stack
Code or none
Data
S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to O.
I/O Addressing
In the 8088, I/O operations can address up to a maximum.of 64K I/O registers. The I/O address appears in the
same format as the memory address on bus lines
A15-AO. The address lines A19-A16 are zero in I/O
operations. The variable I/O instructions, which use
register DX as a pointer, have full address capability,
while the direct I/O instructions directly address one or
two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory locations.
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an
8-bit address on both halves of the 16-bit address bus.
The 8088 uses a full 16-bit address on its lower 16 address lines.
B-37
Interrupt operations fall into two classes; software or
hardware initiated. The software Initiated Intorrupts and
software aspects of hardware interrupts are specified In
the instruction set description in the B086 Family User's
Manual. Hardware interrupts can be classified as nonmaskable or maskable.
Interrupts result in a transfer of control to a new program location. A 256 element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see Figure 4), which are reserved for this purpose. Each element in the table is 4 bytes in size and corresponds to
an interrupt "type". An interrupting device supplies an
8·bit type number, during the interrupt acknowledge sequence, which is used to vector through the appropriate
element to the new interrupt service program location.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable interrupt request (INTR) pin. A typical use would be to activate a power failure routine. The NMI is edge-triggered
on a lOW to HIGH transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. Any higher going transition
of NMI is latched on-chip and will be serviced at the end
of the current instruction or between whole moves (2
bytes in the case of word moves) of a block type instruction. Worst case response to NMI would be for multiply,
divide, and variable shift instructions. There is no
specification on the occurrence of the low-going edge; it
may occur before, during, or after the servicing of NMI.
Another high-going edge triggers another response if it
AFN-Q0826B
iAPX 88/10
occurs after the start of the NMI procedure. The signal
must be free of logical spikes in general and be free of
bounces on the low·going edge to avoid triggering ex·
traneous responses.
HALT
When a software HALT instruction is executed, the
processor indicates that it is entering the HALT state in
one of two ways, depending upon which mode is
strapped, In minimum mode, the processor issues ALE,
delayed by one clock cycle, to allow the system to latch
the halt status, Halt status is available on 10/M, DT/R,
and SSO. In maximum mode, the processor issues appropriate HALT status on S2, S1, and SO, and the 8288
bus controller issues one ALE. The 8088 will not leave
the HALT state when a local bus hold is entered while in
HALT. In this case, the processor reissues the HALT indicator at the end of the local bus hold. An interrupt reo
quest or RESET will force the 8088 out of the HALT
state.
Maskable Interrupt (INTR)
The 8088 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The in·
terrupt request signal is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of CLK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the en(j of a whole move for a
block type instruction. During interrupt response sequence, further interrupts are disabled. The enable bit is
reset as part of the response to any interrupt (INTR,
NMI, software interrupt, or single step), although the
FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the interrupt. Until the old FLAGS register is restored, the
enable bit will be zero unless specifically set by an instruction.
Read/Modify/Write (Semaphore) Operations
via LOCK
The LOCK status Information is provided by the processor when consecutive bus cycles are required during
the execution of an instruction. This allows the processor to perform read/modify/write operations on
memory (via the "exchange register with memory"
instruction), without another system bus master receiving Intervening memory cycles. This is useful in multiprocessor system configurations to accomplish "test
and set lock" operations. The meR signal is activated
(LOW) in the clock cycle following decoding of the
LOCK prefix instruction. It is deactivated at the end of
the last bus cycle of the instruction following the LOCK
prefix. While LOCK is active, a request on a RQ/GT pin will
be recorded, and then honored at the end of the LOCK.
During the response sequence (See Figure 9), the processor executes two successive (back to back) interrupt
acknowledge cycles. The 8088' emits the LOCK signal
(maximum mode only) from T2 of the first bus cycle until
T2 of the second. A local bus "hold" request will not be
honored until the end of the second bus cycle. In the
second bus cycle, a byte is fetched from the external interrupt system (e.g., 8259A PIC) which identifies the
source (type) of the interrupt. This byte is multiplied by
four and used as a pOinter into the interrupt vector
lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit
and sample period, The interrupt return instruction includes a flags pop which returns the status of the
original interrupt enable bit when it restores the flags.
T,
I
T2
Ta
External Synchronization via TEST
As an alternative to interrupts, the 8088 provides a
single software-testable input pin (TEST). This Input is
utilized by executing a WAIT instruction. The single
T4
A L E J \_ _
T1
I
T2
~n,--
__
\~,_ _----'I
FLOAT
Figure g, Interrupt Acknowledge Sequence
8-38
AFN-00826B
intJ
iAPX 88/10
WAIT Instruction Is repeatedly executed until the TEST
Input goes active (LOW). The execution of WAIT does
not consume bus cycles once the queue is full.
If a local bus request occurs during WAIT execution, the
8088 3-states all output drivers. If interrupts are enabled,
the 8088 will recognize interrupts and process them.
The WAIT Instruction Is then refetched, and reexecuted.
Basic System Timing
In minimum mode, the MN/MX pin is strapped to Vee
and the processor emits bus control signals compatible
with the 8085 bus structure. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status information which the 8288 bus controller
uses to generate MULTIBUS compatible bus control
signals.
System Timing -
Minimum System
(See Figure 8.1
The read cycle begins In T1 with the assertion of the address latch enable (ALE) signal. The trailing (low going)
edge of this signal is used to latch the address Informa·
tion, which is valid on the addressldata bus (ADO-AD7)
at this time, into the 8282/8283 latch. Address lines A8
through A15 do not need to be latched because they remain valid throughout the bus cycle. From T1 to T4 the
101M signal indicates a memory or 110 operation. At T2
the address is removed from the addressldata bus and
the bus goes to a high impedance state. The read control signal is also asserted at T2. The read (RD) signal
causes the addressed device to enable its data bus
drivers to the local bus. Some time later, valid data will
be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns
the read signal to a HIGH level, the addressed device
will again 3·state its bus drivers. If a transceiver
(8286/8287) is required to buffer the 8088 local bus,
signals DT/A and DEN are provided by the 8088.
A write cycle also begins with the assertion of ALE and
the emission of the address. The 101M signal is again
asserted to indicate a memory or 110 write operation. In
T2, immediately following the address emission, the
processor emits the data to be written into the addressed location. This data remains valid until at least
the middle of T4. During T2, T3, and Tw, the processor
asserts the write control signal. The write (WR) signal
becomes active at the beginning of T2, as opposed to
the read, which is delayed somewhat into T2 to provide
time for the bus to float.
The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt
acknowledge (INTA) signal is asserted in place of the
read (RD) signal and the address bus is floated. (See
Figure 9.1 In the second of two successive INTA cycles,
a byte of information is read from the data bus, as sup·
plied by the interrupt system logic (i.e. 8259A priority interrupt controller). This byte identifies the source (type)
of the interrupt. It is multiplied by four and used as a
pOinter into the interrupt vector lookup table, as described earlier.
8-39
Bus Timing -
Medium Complexity Systems
(See Figure 10.1
For medium complexity systems, the MN/MXpin Is connected to GND and the 8288 bus controller is added to
the system, as well as an 828218283 latch for latching
the system address, and an 8286/8287 transceiver to
allow for bus loading greater than the 8088 Is capable of
handling. Signals ALE, iJErii, and DTiA are generated by
the 8288 instead of the processor in this configuration,
although their timing remains relatively the same. The
8088 status outputs (82, 51, and SO) provide type of
cycle information and become 8288 inputs. This bus
cycle information specifies read (code, data, or 110),
write (data or 110), interrupt acknowledge, or software
halt. The 8288 thus issues control signals specifying
memory read or write; 110 read or write, or interrupt
acknowledge. 'The 8288. provides two types of write
strobes, normal and advanced, to be applied as required.
The normal write strobes have data valid at the leading
edge of write. The advanced write strobes have the
same timing as read strotJes, and hence, data is not
valid at the leading edge of write. The 8286/8287 transceiver receives the usual T and DE inputs from the
8288's DTiR" ~nd DEN outputs.
The pointer into the interrupt vector table, which Is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8289A priority interrupt controller is
pOSitioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge sequence and software "poll".
The 8088 Compared to the 8086
The 8088 CPU is an 8-blt processor designed around the
8086 Internal structure. Most internal functions of the
8088 are identical to the equivalent 8086 functions. The
8088 handles the external bus the same way the 8086
does with the distinction of handling only 8 bits at a
time. Sixteen-bit operands are fetched or written in two
consecutive bus cycles. Both processors will appear
identical to the software engineer, with the exception of
execution time. The internal register structure is identical and all instructions have the same end resiJlt. The
differences between the 8088 and 8086 are outlined
below. The engineer who is unfamiliar with the 8086 is
referred to the 8086 Family User's Manual, Chapters 2
and 4, for function description and instruction set
Information.
Internally, there are three differences between the 8088
and the 8086. All changes are related to the 8-bit bus interface.
• The queue length is 4 bytes in the 8088, whereas the
8086 queue contains 6 bytes, or three words. The
queue was shortened to prevent overuse of the bus by
the BIU when prefetching instructions. This was required because of the additional time necessary to
fetch instructions 8 bits at a time.
AFN.()Q826B
intJ
iAPX 88/10
~Tofurtheroptimize
the queue, the prefetching algo'
rlthm was changed. The 8088 BIU will fetch a new Instruction to load into the queue eac': time there is a 1
!:lyte hole, (space available) in the queue. The 8086
, , waits until a, 2-byte ~pace is available.
~
The internal execution time of the instruction set is
affected by the 8-bit ,interface. All 16-bit fetches and
writes, fromlto memory take an additional four clock
cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs
when a series of. simple operations occur. When the
more ~ophisticated instructions ,of the 8088 are being
used, the queue has time to fill and the execution proceeds as fast as the execution unit.will allow.
The hardware intE1rface of the 8088 contains the major
differences between, the, two CPUs. The pin, assign·
ments are nearly identical, however, with the following
functional changes:
,A8-A15 - These pins are only address outputs on the
8088. These address lines are latched internally and
, remain valid throughout a bus cycle In a manner
similar to the 8085 upper address lines.
0,
o
BHE has no meaning on the 8088 and has,been elimi'
nated.
o
SSOprovides the SO status information in the minimum mode. This output occurs on pin 34 in minimum
mode only. DT/R, 101M, andSSO provide the cOmplete
bus status in minimum mode. '
o
10iM has been inverted to be compatible with the
MCS-85 bus structure.
'
o
ALE is delayed by one cloc:k cycle in the minimum
mode when entering HALT, to allow the status to be
latched with ALE.
8-40·
AFN-00826B
The 8088 and 8086 are completely ,software compatible
by virture of their identical execution units. Software
that is system dependent may not becomphiltely transferable, but software that ,is not system dependent will
operate equailyas well on an 8088 or an 8086.
iAPX 88/10
T,
ClK
---..r-
T,
T2
I'
I
T.
II-
X
OSl,OSO
8088
11111
52,51,SO
A19/S6-Al6JS3
A19-A16
ALE
'\
ROY
8284
READY
8088
8288
AD7-ADO
8088
'~~====
S6-53'
,--
~
A7
AD
'"
DATA IN
A15-A8
A15-A8
x=.
RD
DT/R
8288
MRDC
DEN
Figure 10. Medium Complexity System Timing
8-41
AFN-00826B
inter
iAPX 88/10
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... 0 °C to 70°C
Storage Temperature ............. - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .................. - 1.0 to + 7V
Power Dissipation ........................ 2.5 Watt
D.C. CHARACTERISTICS
(TA = O°C to 70°C, Vee = 5V ±10%)
Parameter
Min.
Max.
Units
Input low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vcc+ 0.5
V
VOL
VOH
Output low Voltage
0.45
V
Icc
Power Supply Current
340
III
Input leakage Current
I lO
Output leakage Current
vCl
Clock Input low Voltage
-0.5
VCH
Clock Input High Voltage
3.9
CIN
Capacitance of Input Buffer
(All input except
ADO-AD? RO/GT)
C IO
Capacitance of I/O Buffer
(ADo-AD? RO/GT)
Symbol
Vil
Output High Voltage
A.C. CHARACTERISTICS
Test Conditions
10l = 2.0 mA
V
2.4
10H = 400 flA
mA
TA = 25°C
±10
flA
OV.,. VIN'" Vee
±10
flA
0.45V" Vour " Vcc
+0.6
V
Vcc+1.0
V
15
pF
fc = 1 MHz
15
pF
fc = 1 MHz
(TA = O°C to 70°C, Vee = 5V ±10%)
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS
Symbol
TClCl
Parameter
Min.
200
(2;3 TClCl)-15
ClK Cycle Period
Max.
500
Units
ns
Test Conditions
ns
TClCH
ClK low Time
TCHCl
TCH1CH2
ClK High Time
ClK Rise Time
TCl2CL1
ClK Fall Time
TDVCl
TClDX
Data In Setup Time
Data In Hold Time
30
ns
10
TR1VCl
RDY Setup Time into 8284 (See Notes 1.2)
35
ns
ns
TClR1X
RDY Hold Time into 8284 (See Notes 1. 2)
READY Setup Time into 8088
0
ns
TRYHCH
(2;3 TClCl)-15
ns
TCHRYX
TRYlCl
READY Hold Time into 8088
READY Inactive to ClK(See Note 3)
30
-8
ns
ns
THVCH
HOLD Setup Time
TINVCH
INTR. NMI. TEST Setup Time (See Note 2)
35
30
ns
TILIH
Input Rise Time (Except ClK)
20
ns
From 0.8V to 2.0V
TIHll
Input Fall Time (Except ClK)
12
ns
From 2.0V to 0.8V
(V3 TClCl)+2
8-42
10
ns
ns
From 1.0V to 3.5V
10
ns
From 3.5V to 1.0V
ns
AFN.()()826B
inter
iAPX 88/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Parameter
Min.
Max.
Units
10
110
ns
TCLAV
Address Valid Delay
TCLAX
Address Hold Time
10
TCLAZ
Address Float Delay
TCLAX
TLHLL
ALE Width
ns
80
TCLCH-20
ns
ns
TCLLH
ALE Active Delay
80
ns
TCHLL
ALE Inactive Delay
85
ns
TLLAX
Address Hold Time to ALE Inactive
TCLDV
Data Valid Delay
10
TCHDX
Data Hold Time
10
TCHCL-10
ns
110
Data Hold Time After WR
TCVCTV
Control Active Delay 1
10
110
TCHCTV
Control Active Delay 2
10
110
ns
TCVCTX
Control Inactive Delay
10
110
ns
TAZRL
Address Float to READ Active
0
TCLRL
RD Active Delay
10
165
n5
TCLRH
RDlnactive Delay
10
150
TRHAV
RD Inactive to Next Address Active
TCLCH~30
ns
HLDA Valid Delay
RD Width
2TCLCL-75
10
ns
ns
TCLCL-45
TCLHAV
CL; 20-100 pFfor
all 8088 Outputs
in addition to
internal loads
ns
ns
TWHDX
TRLRH
Test Conditions
ns
ns
160
ns
ns
TWLWH
WR Width
2TCLCL-60
ns
TAVAL
Address Valid to ALE Low
TCLCH-60
ns
TOLOH
Output Rise Time
20
ns
From 0.8V to 2.0V
TOHOL
Output Fall Time
12
ns
From 2.0V to 0.8V
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
"J- .-~"" .o'"~
-
-~
DEVICE
UNDER
TEST
0.45
'1CC0100PF
-=-
A C TESTING INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC ,',. AND O,4SV FOR
A LOGIC' 0," THE CLOCK IS DRIVEN AT 4.3V AND Q.2SV TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A LOGIC ,. AND -0
C L INCLUDES JIG CAPACITANCE
8-43
AFN'()0826B
iAPX 88/10
WAVEFORMS
BUS TIMING-MINIMUM MODE SYSTEM
T,
T,
Tw
_TCLCL_TCH'CH21~'~,
vic
~~
elK (8284 Output)
--'" TCHCTV
101M,
T,
VCHV"'""""""\
T,
'--------Ir\._TCLCH_
TCHCL
SSO
TCLAV--
TCLLHALE
r
t--TCLDV
TCHDX --
-i
TCLAX+
A19- A16
s,-J,
1\
-
I---- TlLAX
TLHLL--=:
r-I
r-
TCHLL-I
!-- TAVAL-
ROY (8284 Input)
A15 - As (Float during INTA)
- -
SEENOTE5
----
:r~~-_~~\
~\\\\\\~
f
!--TCLR1X
'c:R -
READY (8088 Input)
1
I.
TRYHCH
-
I-TC~AZ
AD7-ADo
TAZRL-
j
-
-TCHRYX
-
TDVCL-,-- !--TCLDX-
-:(
DATA IN
TCLRH-
-=Y-TCHCTV
TCLRL
I
(WIi, INfA=VOH)
DTfR
TCVCTV- {
8-44
FLOA:-J'-f---TRHAV
~
READ CYCLE
(NOTE 1)
H
TRLRH
I
TCVCTX-
TCHCTV
L
AFN-ooe26B
inter
iAPX 88/10
WAVEFORMS (Continued)
BUS TIMING-MINIMUM MODE SYSTEM (Continued)
ClK 18284 Oulpul)
ACT-ADO
WRITE CYCLE
NOTE 1
ACT-ADO
DT/ii
INTA CYCLE
NOTES 1,3
IRD, WR=VOHI
SOFTWARE HALTDEiii,iiD,WR,lNTA
=VOH
DTIii" INDETERMINATE
INVALID ADDRESS
SOFTWARE HALT
TCLAV
NOTES:
1. ALL SIGNALS SWITCH BETWEEN VOH AND VOL UNLESS OTHERWISE
SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF T2, T3, Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. TWO INTA CYCLES RUN BACK·TO·BACK. THE 8088 lOCAL ADDRIDATA
BUS IS FLOATING DURING BOTH INTA CYCLES. CONTROL SIGNALS
ARE SHOWN FOR THE SECOND INTA CYCLE.
4. SIONALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
HOTED.
8-45
AFN.Q0826B
iAPX 88/10
A.C. CHARACTERISTICS (Continued)
MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
200
500
ns
Test Condltlons--
TCLCl
ClK Cycle Period
TClCH
ClK low Time
(% TClCl)-15
ns
TCHCl
ClK High Time
(V3 TClCl)+2
ns
TCH1CH2
ClK Rise Time
10
ns
From 1.0V to 3.5V
TCl2Cl1
ClK Fall Time
10
ns
From 3.5V to 1.0V
TDVCl
Data In Setup Time
30
ns
TCLDX
Data In Hold Time
10
ns
TR1VCl
RDY Setup Time into 8284 (See Notes 1. 2)
35
ns
TClR1X
RDY Hold Time into 8284 (See Notes 1, 2)
0
ns
TRYHCH
READY Setup Time into 8088
(% TClCl)-15
ns
TCHRYX
READY Hold Time into 8088
30
ns
-8
ns
TRYlCl
. READY Inactive to ClK (See Note 4)
TINVCH
Setup Time for Recognition (INTR, NMI, TEST)
(See Note 2)
30
ns
TGVCH
RQ/GT Setup Time
30
ns
TCHGX
RQ Hold Time into 8086
40
TILIH
Input Rise Time (Except ClK)
20
ns
From 0.8V to 2.0V
TIHll
Input Fall Time (Except ClK)
12
ns
From 2.0V to 0.8V
8-46
ns
AFN.()()826B
intel'
iAPX 88/10
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Min,
Max.
Units
Command Active Delay (See Note 1)
10
35
ns
TClMH .
Command Inactive Delay (See Note 1)
10
TRYHSH
READY Active to Status Passive (See Note 3)
TCHSV
Status Active Delay
TClSH
Symbol
TClMl
Parameter
35
ns
110
ns
10
110
ns
Status Inactive Delay
10
130
ns
TClAV
Address Valid Delay
10
110
TClAX
Address Hold Time
10
TClAZ
Address Float Delay
TClAX
80
ns
TSVlH
Status Valid to ALE High (See Note 1)
15
ns
TSVMCH
Status Valid to MCE High (See Note 1)
15
ns
TCllH
ClK low to ALE Valid (See Note 1)
15
ns
TClMCH
ClK low to MCE High (See Note 1)
15
ns
TCHll
ALE Inactive Delay (See Note 1)
15
ns
TClMCl
MCE Inactive Delay (See Note 1)
15
ns
TClDV
Data Valid Delay
10
110
ns
ns
ns
TCHDX
Data Hold Time
10
TCVNV
Control Active Delay (See Note 1)
5
45
ns
TCVNX
Control Inactive Delay (See Note 1)
10
45
ns
TAZRl
Address Float to Read Active
0
TClRl
RD Active Delay
10
165
ns
TClRH
RD Inactive Delay
10
150
ns
50
ns
TRHAV
RD Inactive to Next Address Active
TCHDTl
Direction Control Active Delay (See Note 1)
Test Conditions
ns
CL = 20-100 pF for
all 8088 Outputs
in addition to
internal loads
ns
TClCl-45
ns
TCHDTH
Direction Control Inactive Delay (See Note 1)
30
ns
TClGl
GT Active Delay
110
ns
TClGH
GT Inactive Delay
TRlRH
RD Width
TOlOH
Output Rise Time
20
ns
From 0.8V to 2.0V
TOHOl
Output Fall Time
12
ns
From 2.0V to 0.8V
85
2TClCl-75
ns
ns
NOTES:
1. Signal at 8284 or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next elK.
3. Applies only to T2 state (8 ns into T3 state).
4. Applies only to T2 state (8 ns into T3 state).
8-47
AFN-ooB26B
inter
iAPX 88/10
WAVEFORMS (Continued)
BUS TIMING-MAXIMUM MODE
SYSTEM (USING 8288)
CLK
r-\
VCH"
VCL
T,
T,
- T C L C L - TCH1CH2--l'H
J
TCLAV-
I~~
fL----J0-
~
'-----"
I--TCLCH-
TCHCL
.A\
-
I- TCL2CL1 r~
-
TCHSV
i-TCLSH
W;0
s"s"So (EXCEPT HALn
------
W(SEE NOTE 8)
\
\._---.;.,
A1S-Aa
-
I---T%~~X_
A19·A16
TSVLH
TCLLH+
j
ALE (8288 OUTPUn
SEE NOTE 5
- {
TCHDX-
=f
CLDV
-
5
57. 3
TCHLL
I
~
RDY (8284 INPUT)
r--
----
I-- Tr1VCL
~ -~~~~ ~~
TRYLCL
-;
TYHSH~I
..... TeLAX _
READ CYCLE
TCLAVAD7-ADO
E ~-
V
RD
1
MRDC OR IIDiC
-
FDVCL-I--TCLDX-
J
DATA IN
FL:~
TRHAV
TCLRH
\\
TCLRL
\
TRLRH
-
TCLMl-8288 OUTPUTS
SEE NOTES 5,8
I
r-
TAZRL-
DTIIi
TRYHCH-f
-TCLAZ -
TCHDTL-
r
-TCHRYX
-
TCHDTH
TCLMH-
'\
TCVNV-
DEN
Ii-
i{
TCVNX-
8-48
-
AFN-.
1"_feLAZ
COPROCESSOR
8-50
AFN-00826B
iAPX 88/10
iAPX 86/10, 88/10
INSTRUCTION SET SUMMARY_
DATA TRANSFER
IOW,IIVI:
71543 2 I [I
115432 I [I
I
Regrster1mem()!y tOlhom register
~O d w mOd fe~
Immedl~te 10 register/memory
11
Immediate loreo,sler
1,011 w reg
Memorv 10 accumulator
11
11
Accumulator 10 memOIV
Regl$terlmemol'IIO segmenllto'sier
Segment reo,ster to ,eg'sttlimemo'V
PUSIt
I 0 [I 0 I 1 w jll'lOll 0 G 0 tim
0 t 0 [I 0 0 w
0 I II 0 0 1 w
Li::.!!:ITi
I
I
I
715432 I
I
I
I
dala
addr·low
I
~ddl low!
1 10 Imod 0 leg rim I
11 000 \ 100 Imod-O~
11543 Z 1 II
[I
DEC
~ala II w I
1D5·t3210
1&543210
11543210
II I 1 I I 1 1 w ImOdO 0 I
I
I'I I '01 I w imOdO' 1
addrh~
andr h'~h
CMP
I
CampuI:
ReQ'SlerimemOlyana,egrsl!r
re~
00 1 1 10 d w mod
100000 S w mod 111 rim
Immed,ate With .ccumulator
001" lOw
AASASClladluStl0r~ub"~~t
~
01010 reg
US Owmal ad,uSllor subtra~t
MUl Muiliply lunSl~nedl
~'"".,.'''''.,.'"",'"",''=t----,-,-:-;:---,
OOOrtgllO
IMUl Inleger multiply ISIgnedl
I 1 I I 0 I 1 w mod I 0 I r,m
UM ASCllad,ustlor muiliply
11010100
Puth:
mod ItO rim
Segmentreglsltr
O.trlmln!
Reglsler/memory
~r~
Immedrate wrlh reglslerlmemory
Register/memory
PO'
rim
Pap:
Reg,sler/memOly
10001 I I t
Register
01011
modO 0 0 11m
reg
OOOreglll
(100001 1 w !mOd reg
ReOlster wltnaccumulato'
[T?Tt~
rim
00001010
II 1 I 101 I w ImOd I I a ,rm
i
IOI~
111 , 101 I w imod I I I "m
I
Integfr d,v'de ISIlinedl
~Iv,de
caw Conve't byleto word
cwo Convert word to double word
Reglslerlmemorywlth regiSler
1 I 1 1 0 1 1 w mod I 0 0 rim
UIVO,v,delunSlgnedl
Uti ASCII ad,ustlor
lCIIGohcll.ngl:
dala 01 SW 01
1'10'0 101 10000 l f i i J
100" 0 0 0
100 I 100 I
I
IN'lnpu\hom
I
Flxcdpol1
(I I 100 lOw
VarlOibleport
I HI 0 11 Ow I
POri
lOGIC
OUT·OUlpUIID
Fllcdpoll
Var,ablepol1
n,U·T,.nslate byte to Al
1I0T IMen
'1100 I I w I
1. I I 101 I 1 w .
port
SKR ShlHlog,eal "Qht
~~
SAR
UA'lo'dEAloreg'$ler
I I 0001 101 Imod
LDS,lo'd pOlnler laOS
111000101 ImOd
1,1000100 Imod reg
lfl·loadpOlnlerloES
SHllSAl Sh,H logical 3"tnmellC lelt
lAlIF·lGad AH with Hags
10011111
IAIIF'SloreAHrnlollags
I'Ulllf'Pushllags
1001 1 " 0
1 00 I 11 00
I'DrF·Papliags
100 11 10 I
S~llt
a!llhmellc "Qhl
ROlRolateletl
11m
RORRotate"ght
I
RClRotalethroughtarry!taglelt
RCA ROlale through carr v IIQht
AND
~Oooodwimod 'e~~
lioooOswmooooo r'm~~aIJ I~-:;'I;o1-~~-i.iJ
10 a 0 0 0 lOw
I
I
dala rl
wi!
Immedlale dala and reg,ster /memory
Immediate data and accumulalor
OR
Add willi urrv:
Reg Imemory wllh rtOlster to tither
O~'~'~'~':t'~'t·~1m~Ot'~"~o~q=~~=+::::::;~~G
f'\
r=T 0 0 0 0 0 0 w mOd 1 00 rim
0 0 tOOl 0 w
data
dala II w 1
1000loOdwlmod,eQ~
F.ll""'~'~'~'~'~,w~1m~o,;':;,~,'.:',""~'m~---:';;;":;-,-,----":;,,,;-;,'.-:.:c,"1
F.li:.'::iii:'~,:=;,=;;,~,"'""'"."+1=';,~,,::-,~F~~:7"l~-~
Or:
Reg/memory andreg,ster to e"her
ADC
11 0 I 0 0 v w modO 01 "m
110 I 0 0 v w modO 1 0 "m
0 I 00. w modO 1 I
II
r.\
Add:
Immedlaleto accumuialor
110 tOO. w modO 0 0 ,m
TEST And lunc!lan 10 1I11l1.na ruull:
Reg,sterlmemory and leg,stel
1-"-"-'-'-'-'-:-,::-,.'--'-:1m""o':-::,,:-.--:,C:,m-
ARITHMETIC
ADD
1 10100 v w mod 100 !Jm
And:
Reg Imemory and reg,ster to e,lher
tmmed,ate to reg,ster ImemOry
tmmed,ate 10 accumulalor
Reg Imemory w,th reg'slerto either
Immed,ate 10 re91~terrmemory
~lwmOdOIOrm
1'10 100 v w Imod 10 I rim
11 0 1 0 0 v w mod I I I om
loooolodwl!!,od reg~
ImmedialeloreQISler/memory
L:i:iOOOOOW ImOdOO!
Immedlaleto accumulator
lI::§OO£o 110 w
rim
!
I
data
I
lIata 01 w ,
data Llw I
I
Immedlilteto reglster/memory
XOII
Immediate 10 accumulator
hclullvlar:
ReQ Imemory and regls\tr 10 either
IIC,lncrlln,nl:
Regrsterlmemory
11111 I 1 1 w ImodO 0 0 11m
10 0 1 I 0 0 d w I mod reg
ii!ii:J
Immediate to reg,ster/memory
1 0 0 0 0 0 0 w modI I 0 rim
ImmedIate to accumulalor
0011 0 lOw
data
data IIw 1
01000 reg
W·ASClI ad,ust lor add
W·OeClmal adlust tor add
0011 0 I 1 I
~
IUI-SUlllrlCl:
ReglmemolYiillldreglsWloellher
~dwlmOd'egr,m
Immediate Irom reglsterlmemory
100000 s w mod 10 I rim
tmmedlatetrom accumulator
00 101 lOw
STRING MANIPULATION
REP-Reput
MO\lS·Movebytelword
CMPS'Comparebytel",o,d
••• • SUMract wllft 111m.
RIg Imemory and reglsUI 10 either
dala
000110 d w
reo
rim
SCAS'Scanbyte/word
111 1 1001
1
i
!10 10010 w !
1,0 10011 wi
101011 I w
lODS·loidbvtelwdto Al/AX
10 I 0 11 0 w
STOI'';tOI bvlel",d hom ALIA
l' 0 I 0 I 0 I w I
MnemontCS ©Intel. 1978
8-51
AFN-00826B
iAPX 88/10
INSTRUCTION SET SUMMARY (Continued)
CONTROL TRANSFER
CALL ~ CIII:
Direct within segment
Indirect wlthm segment
71543210
11
I 1 0 1 0 0 0
11543210
I
dlsp·!ow
11 1 1 1 1 1 1 1 ImOd 010
rIm
Direct mlersegment
10011010ollseHow
Indlred intersegment
1"
seQ-low
18S43110
I
I
dlsp-tllgh
71543210
I
J"./JAE·Jump on nol below/abo ... ,
or eQual
J ••E/JA·Jump on nol below or
equal/above
JMP/JPO'Jump on nol parlpar odd
JIO,Jump on not overllow
olfset.hlgh
seQ-high
mod 011 rim
11 111
JMP :, UnCllndltlanl1 Jump:
Direct within segment
Direct w.thln segment-short
Indirect wlthm segment
11 1 1 0 , 00 1 t
11 , 0 10 11
d.sp-Iow
d.sp
I
I
lIlt 0 1 0 1 0
Indirectlntersegmenl
1111 I 1 1 1 1 Imod 101 rim
RET : Return from CALL:
Within segment
W.thln seo_ adding immed to SP
]110000101
Inlersegment
1110010111
Inlersegmenl. adding Immediate to $P 11 1 0 0 1 0 1 0 [
JE/JZ=Jump on equal/zero
o 1 1 lOt 0 0
Jl/J18E·Jump on less/not grealer
o 1 1 1 1 I 00
or equal
JlE/JII=Jump on less orequallnol
1011
1 1 11 0
grealer
JI/JIAE=Jump on belowlnot above 10 I t 100101
or equal
J.E/JIA~~~~Coov~ below or eQuall
01110110
JP/JP(·Jump on panty/panly even
01111010
I
data·low
dala.hlg£]
data· low
data·hlgh
1 1 000 1 0 ]
dlsp
I
11
1 1 0000 1
dlsp
I
i
1 1 1 00000
dlso
1 1 I 000 1 1
dlSp
1 1 00 1 1 0 1
type
1 10011 00
111001110[
I' 1001 1 11 I
11 1 1 1 1 000
l' 11
10101
\, 11 1 1001
STC Set carry
dlsp
dlsp
dlsp
J
11
ClC Clear carry
CMC Complement carry
dlsp
dlsp
dlsp
LOOPl/LODPE loop while zero/equal
lOOPNl/LDOPIE loop .. hi Ie not
PROCESSOR CONTROL
1
dlsp
I
I
dlsp
, .. ,
INT Intmupt
Typespecilled
TypeJ
INTO-Interrupt on overllow
IRH Interrupt return
seg·low
I
dlsp
1011110011
Jell Jump on ex zero
olfset·low
I
dlsp
JIIS Jump on nol Sign
lOOP loop ex limes
zerofeQu,\'
1 1 1 1 1 1 1 1 mod 1 00 rim
O.rect mtersegment
18543210
10 1 1 1 00 II!
10 1 I 1 0 1 I 1 I
10 1 , 1 1 0 I 1 I
10 , 1 I ODD 1 I
I
I
I
11 1 1 1 , 0 0
CUI Clear directIOn
STD Set dtreClton
Cli Clear Interrupt
STI Set Interrupt
1 1 1 11 10 1
I" 1 1 ! 0 '0 I
liiiiiiiiJ
I" 1 10100 1
JO'Jumpon overllow
101 11 00001
dlsp
JS'Jump on sign
[011110001
dlsp
dlsp
HLT Hall
WAIT Walt
dlsp
dlsp
ESC Escape Ito external device I
1'1011 J(xxlmo~/~
LOCK Sus lock prellJ(
~oJJ
JIE/JIZ·Jump on not equallnotzero o 1 1 1 0 1 0 1
JILlJIE=Jump on nol less/grealer
01111101
or equal
JILEIJ8=Jump on not less or equal!
1011111111
grealer
1'0011011
1
Foot....:
AL ~ 8-bit accumulator
AX " 16-bit accumulator
CX " Count register
OS ~ Data segment
ES • Extra segment
Above/below refers to unsigned value.
Greater" more positive;
less" less positive (more negative) signed values
if d" 1 then "to" reg; if d " 0 then "from" reg
if w" 1 then word instruction; if w ," 0 then byte instruction
if
if
if
if
mod"
mod·
mod·
mod·
11 then
00 then
01 then
10 then
if rim ~ 000 then
if rim· 001 then
if rim· 010 then
if rim· 01 t then
if rim· 100 then
if rim· 101 then
if rim· 110 then
if rim ~ 111 then
OISP follows 2nd
r 1m is treated as a REG field
OIsP • 0", disp-Iow and disp-high are absent
OISP ~ disp-Iow sign-extended to 16-bits, disp-high is absent
OISP • disp-high: disp-Iow
EA • (BX) • (51) .0ISP
EA • (BX) • (01) .01SP
EA • (BP) • (SI) • OISP
EA • (BP) • (01) • OISP
EA ~ (SI) • OISP
EA ~ (01) • OlsP
EA • (BP). OISP"
EA • (BX) .00SP
byte of instruction (before data if required)
"except if mod ·00 and rim· 110 then EA
~
disp-high: disp-Iow,
if s:w = 01 then 16 bits 01 immediate data form the operand
iI s:w = 11 then an immediate data byte is sign extended to
. form the 16-bit operand,
il v 0 then "count" = 1; if v 1 then "count" in (CL)
x = don't care
I is used for string primitives lor comparison with l.F FLAG.
=
=
SEGMENT OVERRIDE PREFIX
10 0 1 reg 1 1 01
REG is
ass~gned
according to the following table:
1I1-Bit (w
~
000
OOt
010
011
100
tOl
110
111
AX
CX
DX
BX
SP
BP
SI
01
f)
B-Bit (w ~ 0)
000 AL
001
010
011
100
lOt
110
tl1
CL
OL
BL
AH
CH
OH
BH
Segment
00 ES
01 CS
10 S5
It OS
Instructions which reference the flag register file as a 16-biI object use the symbol FLAGS to
represent the tile:
FLAGS • X:X:X :X:(OF):(OF): (IF):(TF):(SF):(ZF):X: IAF):X:(PF):X:(CFI
Mnemonics© Intel, 1978
8-52
AFN-ooa26B
8089
8 & 16-BIT HMOS I/O PROCESSOR
• High Speed DMA Capabilities Including
I/O to Memory, Memory to I/O, Memory
to Memory, and I/O to I/O
• 1 Mbyte Addressability
• Memory Based Communication with
CPU
• Supports LOCAL or REMOTE I/O
Processing
• iAPX 86, 88 Compatible: Removes I/O
Overhead from CPU in iAPX 86/11 or
88/11 Configuration
• Flexible, Intelligent DMA Functions
Including Translation, Search, Word
Assembly/Disassembly
• MULTIBUS™ Compatible System
Interface
• Allows Mixed Interface of 8- & 16-Bit
Peripherals, to 8- & 16-Bit Processor
Busses
The Intel® 8089 is a revolutionary concept in microprocessor input/output processing. Packaged in a 40-pin DIP package,
the 8089 is a high performance processor implemented in N-channel, depletion load silicon gate technology (HMOS). The
8089's instruction set and capabilities are optimized for high speed, flexible and efficient I/O handling. It allows easy
interface of Intel's 16-bit iAPX 86 and 8-bit iAPX 8B microprocessors with 8- and 16-bit peripherals. In the REMOTE
configuration, the 80B9 bus is user definable allowing it to be compatible with any B/16-bit Intel microprocessor, interfacing
easily to the Intel multiprocessor system bus standard MULTIBUSTM.
The 8089 performs the function of an intelligent DMA controller for the Intel iAPX 86, BB family and with its processing
power, can remove I/O overhead from the iAPX 86 or iAPX B8. It may operate completely in parallel with a CPU, giving
dramatically improved performance in I/O intensive applications. The 8089 provides two I/O channels, each supporting a
transfer rate up to 1.25 mbyte/sec at the standard clock frequency of 5 MHz. Memory based communication between the,
lOP and CPU enhances system flexibility and encourages software modularity, yielding more reliable, easier to develop
systems.
CPU
I/O CHANNEL 1
r=--i
I
I
I
I
DMA REal
OMA
TERMINATEl
v"
I
I
A151D15
A12JD12
STATUS
I~I
A111D11
A1OJD10
A9/D9
I~I
L_
v"
A14/D14
=.J
1/0 CHANNEL 2
ADDRESS/
ABlD8
DATA
A7/07
A5ID5
A4ID4
DMA REQ2
OMA
TERMINATE2
ASSEMBlYI
DISASSEMBLY
SINTR·1
SINTR·2
<-_ _I""
INSTRUCTION
FETCH UNIT
Figure 1. 8089 1/0 Processor Block Diagram
8-53
RESET
Figure 2.
8089 Pin Configuration
8089
Table 1~ Pin
r----.--.-------------~----~~
Symbol Type
Name and Function
AD-A15/
DO-D15
I/O
Multiplexed Address and Data Bus: The
function of these lines are defined by the
state of SO, 51 and S2 lines. The pins are
floated after reset and when the bus is not
acquired. A8-A15 are stable on transfers to a
physical 8'blt data bus (same bus as 8088),
and are multiplexed'with data on transfers to
a 16-bit physical bus.
A16-A19/
83-S6
o
Address and Status: Multiplexed most
significant address lines and status information. The address lines are active only
when addressing memory. Otherwise, the
status lines are active and are encoded as
shown below. The pins are floated after reset
and when the bus is not acquired.
S6S5S4S3
1 1 0 0 DMA cycle on CH1
1 10 1 DMA cycle on CH'2
1 1 1 0 Non-DMA cycle on CH1
,1 1 1 1 Non-DMAeycleon CH2
BHE
9
•
.'
SO, S1, S2
0
Description
Bus High Enable: The, Bus High Enable 'is
used to enable data operations on the most
significant half of the data bus (D8-D15). The
signal is active low when a byte is to be
transferred on the upper half of the data bus.
The pin is floated after reset ilnd when the
bus is not acquired. BHE does not liave tei be
'latched.
Symbol
Type
lOCK
0
RESET
I
Reset: The receipt of a reset signal causes
the lOP to susfJEmd all its activities and enter
an idle state until a channel attention is
received. The signal must be active for at
least four clock cycles.
ClK
I
Clock: Clock provides all timing needed for
internal lOP operation.
CA
I
Channel Attention: Gets the attention of the
lOP. Upon the falling edge of this signal, the
SEl Input pin is examined to determine
Master/Slave or CH1/CH2 information. This
Input is active high.
SEl
I
Select: The first CA received after 'system
reset informs the lOP via the SEl line,whether it is a Master or Slave (0/1 for Master/Slave respectively) and starts the in~
itialization sequence. During any other CA
the SEl line signifies ihe selection, of
CH1/CH2. (0/1 respectively.) ,
DRQ1-2
I
Data Request: DMA request Inputs which
signal the lOP that a peripheral is ready to
transfer/receive data using channels 1 or 2
respectively. The signals must be held active
high until the appropriate fetch/stroke is
initiated.
RQ/GT
I/O
Request Grant: Request Grant implements
the communication dialogue required to arbitrate the use of.the system bus (between
lOP and CPU, lOCAL mode) or I/O bus when
two lOPs share.:!tle same bus (REMOTE
mode). The RQ/GT signal..!! a~ive low. An
internal pull-up permits RQ/GT to be left
floating if not used.
SINTR1-2
0
Signal Interrupt: Signal Interrupt outputs
from channels 1 and 2 respectively. The
interrupts may be sent directly to the CPU or
through the 8295A interrupt controller. They
are used to indicate to the system the
occurrence of user defined events.
EXT1-2
I
External Terminate: External terminate
inputs for channels 1 and 2 respectively. The
EXT signals will cause the termination of the
current DMA transfer operation if the channel is so programmed by the channel control
register. The signal must be held active high
until termination is complete.
Status: These are the status pins that define
the lOP activity during any given cycle. They
are encoded as shown below:
s2§iSii
o
o
o
o
0 0 Instruction fetch; i/o space
0 1 Data fetch; I/O space
1 0 Data store; I/O space
1 1 Not used
1 0 0 Instruction fetch; System Memory
1 0 1 Data fetch; System Memory
l' 1 0 Data store; System Memroy
1 1 1 Passive
The status lines are utilized, by the bus
controller and bus arbiter, to generate all
memory and I/O control signals. The signals
c,hange during T4 if a new cycle is to be
entered while the return to passive state in T3
or Tw Indicates the end of a cycle. The pins
are floated after system reset and when the
bus is not acquired.
READY
I
Ready: The ready Signal received from the
addressed device indicates that the device is
ready for data transfer. The signal is active
high and is synchronized by the 8284 clock
generator.
Vee
Vss
8-54
Name and Function
lock: The lock output signal indicates to the
bus controller that the bus is needed for more
than one contiguous cycle. It is set via the
channel control register, and during the TSl
instruction. The pin floats after reset and
when the bus is not acquired. This output is
active low.
Voltage: +5 volt power Input.
Ground.
AFN·00840C
inter
8089
control. CRT control, such as cursor control and auto
scrolling, is simplified with the 8089. Keyboard control,
communication control and general 1/0 are just a few of
the typical applications for the 8089.
FUNCTIONAL DESCRIPTION
The 8089 lOP has been designed to remove I/O processing, control and high speed transfers from the central
processing unit. Its major capabilities include that of in'JtIalizing and maintaining peripheral components and
supporting versatile DMA. This DMA function boasts
flexible termination conditions (such as external terminate, mask compare, single transfer and byte count expired). The DMA function of the 8089 lOP uses a two cycle approach where the information actually flows
through the 8089 lOP. This approach to DMA vastly simplifies the bus timings and enhances compatibility with
memory arid peripherals, in addition to allo"ling operations to be performed on the data as it is transferred.
Operations can include such constructs as translate,
where the 8089 automatically vectors through a lookup
table and mask compare, both on the "fly".
Remote and Local Modes
The 8089 is functionally compatible with Intel's iAPX 86, 88
family. It supports any combination of 8/16-bit busses. In
the REMOTE mode it can be used to complement other
Intel processor families. Hardware and communication
architecture are designed to provide simple mechanisms
for system upgrade.
The only direct communication between the lOP and
CPU is handled by the Channel Attention and Interrupt
lines. Status information, parameters and task programs are passed via blocks of shared memory, simplifying hardware interface and encouraging structured
programming.
The 8089 can be used in applications such as file and
buffer management in hard disk or floppy disk control. It
can also provide for soft error recovery routines and scan
so r
MNIMX
.....
....
ep"
....
l@
I-
sn
OND OE
CLOCK
GENERATOR
....
so
51 Ie
OOP
I
CA
SEl
DECODE
......
~ ~
T'i' i i
AOOR
lti
BHE
r-------,I
>-~
~DRI~
II
8282
LATCH
....
I
DATA
TRANSCEIVER
(10RZ)
-<~::f' I
II
".OTI/O ADDR :
I=-
-------,
Ii
n,20R3)
~
HD
iHE
INTA
~-----..,
~
a
AOIOT
Alowe I-H.C.
ALE
-'---
RESET
READY
• Up to two 8286 devices bidirectionally buffer the
system data bus.
IOAC
DEN TROLLER fc5WC
,""iff
L-. elK
• Up to three 8282 buffer/latches to latch the address to
the system bus.
AMWf I-H.e.
BUS
CON·
S.
A typical REMOTE configuration is shown in Figure 4. In
this mode, the lOP's bus is physically separated from
the system bus by means of system buffers/latches. The
lOP maintains its own local bus and can operate out of
local or system memory. The system bus interface contains the following components:
iIIIliC
!iWfC
8281
'"= DTili
~ESET
T
elK
so
51
iiiE
~~DY
-
OND
50
s;;
Shown in Figure 3 is the 8089 in a LOCAL configuration.
The iAPX86 (oriAPX88) is used in its maximum mode. The
8089 and iAPX 86 reside on the same local bus, sharing the
same set of system buffers. Peripherals located on the
system bus can be addressed by either the iAPX 86 or the
8089. The 8089 requests the use of the LOCAL bus by
means of the RQ/GT line. This performs a similar function
to that of HOLD and HLDA on the Intel B085A, 8080A and
iAPX 86 minimum mode, but is implemented on one
physical line. When the iAPX 86 relinquishes thE' system
bus, the 8089 uses the same bus control, latches and
transceiver components to generate the system address,
control and data lines. This mode allows a more
economical system configuration at the expense of
reduced CPU thruput due to lOP bus utilization.
I
I
~
IsrJ
I I
. I~I1
~
§
I~I~" ffJ[
(~
A.
I~
I~~
AAM
Il>WC
1K.I
:
tKIII
I~
I~
1i1;
III
II!;
II
2718-2
MC&IO
Me. . .
EPADM (.
PEAOr::-AL
PERIP HERAl
DUO
OM.
2K.8 2Kx8
DMAe
ONT
OMAC
I
NOTE: ONLY ONE LATCH IS NEEDED IF CONFIGURED WITH I0Il AND ONLY 14K
ADDRESSINO IS USED. ONLY ONE TRANSCEIVER IS NEEDED IF USINO A
PHYSICAL 8-BIT DATA BUS (8088).
Figure 3. Typical iAPX 86/11,88/11 Configuration with 8089 in LOCAL Mode, 8088, 8086 In MAX Mode
8-55
AFN-0084OC
inter
8089
• An 8288 bus controller supplies the control signals
necessary for buffer operation as well as MRDC
(Memory Read) and MWTC (Memory Write) signals.
the lOP which channel is being addressed. Communication from the lOP to the processor can be performed in a
similar manner via a system interrupt (SINTR 1,2), if the
CPU has enabled interrupts for this purpose. Additionally, the 8089 can store messages in memory regarding
its status and the status of any peripherals. Tllis communication mechanism is supported by a hierarchial
data structure to provide a maximum amount of flexibility of memory use with the added capability of handling multiple lOP's.
'
• An 8289 bus arbiter performs all the functions
necessary to arbitrate the use of the system bus. This
is used in place of the RQ/GT logic in the LOCAL
mode. This arbiter decodes type of cycle information
from the 8089 statqs lines to determine if the lOP
desires to perform a transfer over the "common" or
system bus.
The peripheral devices PER1 and PER2 are supported on
their own data and address bus. the 8089 communicates
with the peripherals without affecting system bus operation. Optional buffers may be used on the local bus when
capacitive loading conditions so dictate. I/O programs and
RAM buffers may also reside on the local bus to further
reduce system bus utilization.
Illustrated in Figure 5 is an overview of the communication data structure hierarchy that exists for the 8089 1/0
processor. Upon the first CA from RESET, if the lOP is
initialized as the BUS MASTER, 5 bytes of information are
read into the 8089 starting at location FFFFS (FFFFS,
FFFF8-FFFFB) where the type of system bus OS-bit or 8bit) and pointers to the system configuration block are
obtained. This is the only fixed location the 8089 accesses.
The remaining addresses are obtained via the data structure hierarchy. The 8089 determines addresses in the
same manner as does the iAPX 8S; i.e., a 1S-bit relocation
pointer is offset left 4 bits and added to the 1S-bit address
offset, obtaining a 20-bit address. Once these 20-bit addresses are formed, they are stored as such, as all the 8089
address registers are 20 bits long. After the system configuration pointer address is formed, the 8089 lOP accesses the system configuration block.
COMMUNICATION MECHANISM
Fundamentally, 'communication between the CPU and
lOP is performed through messages prepared in shared
memory. The CPU can cause the 8089 to execute a program by placing it in the 8089's memory space andlor
directing the 8089's attention to it by asserting a hardware Channel Attention (CA) signal to the lOP, activatingthe proper 1/0 channel. The SEL Pin indicates to
...--LOCAL
1 MEMORY
I
S2
eLK
, - - - - - j - - - - - - i S1 ~'i::
ROM/RAM
H'-J-+--}
ARBITRATION
/"::-"
MULTIBUS
ARBITRATION
SIONALS
Ir---I----~-E~~-lIHIi-so nR
(OPTIONAL-IF
NEEDED
TO REDUCE
LOADING ON 8089)
r--l
r~:J.,c-::'l'
~~~N "'"
IJ!--'-J'------"J: 8:::TI_R·~~i
~:=l-11~~~~~~~~~~i'" j~L t----"
~MEMAD
1
r-
,'"1.
: _______ '
Ie
ALE
If-----<~I: V'-----'"J.L.-..l..--L--'----'---L
L
~ .......-----.
'-----'\,--l----~
~I
J------'\j~
r52
5,
DAa,
~t-
1-----jexT 1
'I
VL.L...J-----'\I\,I
PER2
I\,.,.,-----,IIA
U
I
ADDRESS/DATA
elKREADYRclI RESET -
EXT2 aT
:
•
I
T
1M"
~~~":l
-y
UJ
---------1
-t- OE
f------L>I
V
8089
MEMWR
~~::~::~~~:k'·-AO.BH~
~ LATCH
So
PERl
i-----jORQ:z
elK
I
CPU
SYSTEM
BUS
07·00
D~DO
11'----'\
~AEN
~AEADY
TO ANOTHER
lOP
8284
rAESET
'-101-'
Figure 4_ Typical REMOTE Configuration
8-56
AFN-00840C
inter
8089
the 10P,allowing the lOP to operate concurrently with
the CPU, or reside in system memory.
The advantage of this type of communication between
the processor, lOP and peripheral, is that it allows for a
very clean method for the operating system to handle
1/0 routines. Canned programs or "Task Blocks" allow
for execution of general purpose 1/0 routines with the
status and peripheral command information being
passed via the Parameter Block ("data" memory). Task
Blocks (or "program" memory) can be terminated or
restarted by the CPU, if need be. Clearly, the flexibility
of this communication lends itself to modularity andap:
plicabllity to a large number of peripheral devices and
upward compatibility to future end user systems and
.
.
microprocessor families.
LOCATION
FFFF6
J
SYSTEM
CONFIOURATION
BLOCK
CB RELOCATION
CONTROL
BUSY
BLOCK
I
)
CCW
PB ADDRESS
CHANNEL
PB RELOCATION
1
BUSY
CCW
PB ADDRESS
CHANNEL
2
PB RELOCATION
TASK BLOCK
J
Register Set
1 ----':'::'=":'----'1
T
T T
r-,
T
The 8089 maintains separate registers for its two ilo
channels as well as some common registers (see Figure
6). There are sufficient registers for each channel to sustain its own DMA transfers, and process its own instruc'
tion stream. The basic DMA pOinter re.gisters (GA, GB 20 bits each), can pOint to either the system bus or local
bus, DMA source or destination, and can be autoincre·.
mented. A third register set (GC) can be used to allow
translation during the DMA process through a lookup
table it points to. Additionally, registers are provided for a
masked compare during the data transfer and can be set
up to act as one of the termination conditions. Other
registers are also provided. Many of these registers can be
used as general purpose registers during program execu·
tion, when the lOP is not performing DMA cycles.
lOP TASK
PROGRAM
Figure 5. Communication Data Structure Hierarchy
The System Configuration Block (SCB), used only during startup, pOints to the Control Block (CB) and provides
lOP system configuration data via the SOC byte. The
SOC byte initializes lOP 1/0 bus width to 8/16, and
defines one of two lOP RQ/GT ope'rating modes. For
RQ/GT mode 0, the lOP is typically initialized as SLAVE
and has its RQ/GT line tied to a MASTER CPU (typical
LOCAL configuration). In this mode, the CPU normally
has control of the bus, grants control to the lOP as needed, and has the bus restored to it upon lOP task comple·
tion (lOP request-CPU grant-lOP done). For RQ/GT
mode 1, useful only in remote mode between two lOPs,
MASTERISLAVE designation is used only to initialize
bus control: from then on, each lOP requests and grants
as the bus is needed (IOP1 request-IOP2 grant-IOP2
request-IOP1 grant). Thus, each lOP retains bus con·
trol until the other requests it. The completion of in·
itialization is signalled by the lOP clearing the BUSY
flag in the CB. This type of startup allows the user to
have the startup pOinters in ROM with the SCB in RAM.
Allowing the SCB to be in RAM gives the user the flex·
. ibility of being able to initialize multiple lOPs.
USER PROGRAMMABLE
0
TAG 19
G.P. ADDRESS A (GA)
G.P. ADDRESS B (G8)
G,P. ADDRESS C (GC)
TASK POINTER tTP)
'--- 1·81T POINTER TO EITHER 110 OR SYSTEM MEMORY SPACE
15
0
INDEX (IX)
BYTe COUNT (BC)
MASK
COMPARE (Me)
CHANNEL CONTROL (CC)
NON USER PROGRAMMABLE
(ALWAYS POINTS TO SYSTEM MEMORy)
The Control Block furnishes bus control Initialization for
the lOP operation (CCW or Channel Control Word) and
provides pOinters to the Parameter Block or "data"
memory for both channels 1 and 2. The CCW is retrieved
and analyzed upon all CA's other than the first after a
reset. The CCW byte is decoded to determine channel
operation.
191
I
I
PARAMETER POINTER (PP)
CHANNEL CONTROL POINTER (CP)
P
I
Figure 6. Register Model
The Parameter Block contains the address of the Task
Block and acts as a messge center between the lOP and
CPU. Parameters or variable information is passed from
the CPU to its lOP in this block to customize the software interface to the peripheral device. It is also used
for transferring data and status information between the
lOP and CPU.
The Task Block contains the instructions for the respective channel. This block can reside on the local bus of
8-57
Bus Operation
The 8089 utilizes the same bus structure as the
iAPX 86, 88 in their maximum mode configurations (see
Figure 7). The address is time multiplexed with the data
on the first 16/8 lines. A16 through A19 are time multi·
plexed with four status lines 83·S6. For 8089 cycles, S4
and S3 determine what type of cycle (DMA versus non·
DMA) is being performed on channels 1 or 2. S5 and S6
AFN·00640C
inter
8089
are a unique code assigned to the 8089 lOP, enabling
the user to detect which processor is performing a bus
cycle In a multiprocessing environment.
16·bits wide with either an 8·bit peripheral (under byte
column) or 16·bit peripheral (word column) being shown.
The latency refers to the worst case response time bv
the lOP to a DMA request, without the bus arbitration
times. Notice that the word transfer allows 50% more
bandwidth. This occurs since three bus cycles are reo
quired to map 8·bit data into a 16·bit location, versus two
for a 16·bit to 16·bit transfer. Note that it is possible to
fully saturate the system bus in the LOCAL mode
whereas in the REMOTE mode this is reduced to a max·
imum of 50%.
The first three status lines, 80·82, are used with an 8288
bus controller to determine if an Instruction fetch or
data transfer is being performed in 1/0. or system
memory space.
DMA transfers require at least two bus cycles with each
bus cycle requiring a minimum of four clock cycles. Ad·
ditional clock cycles are added If wait states are reo
qulred. This two cycle approach simplifies considerably
the bus timings in burst DMA. The 8089 optimizes the
transfer between two different bus widths by using
three bus cycles versus four to transfer 1 word. More
than one read (write) is performed when mapping an
8·bit bus onto a 16·bit bus (vice versa). For example, a
data transfer from an 8·bit peripheral to a 16·bit physical
location in memory is performed by first doing two
reads, with word assembly within the lOP assembly
register file and then one write.
Table 2. Achievable 5 MHz 8089 Operations
Local
Bandwidth
As can be expected, the data bandwidth of the lOP is a
function of the phYSical bus width of the system and 1/0
busses. Table 2 gives the bandwidth, latency and bus
utilization of the 8089. The system bus is assumed to be
i - - - - - ! 4 + N W A I T ) ..
T,
T2
I
T~
Remote
Byte
Word
Byte
Word
830 KB/S
1250 KB/S
830 KB/S
1250 KBiS
Latency
1.0/2.4 ~sec· 1.0/2.4 ~sec· 1.0/2.4 ~sec· 1.0/2.4 ~sec·
System Bus
Utilization
2.4 ~sec
PER
TRANSFER
1.6 ~sec
PER
TRANSFER
0.8 ~sec
PER
TRANSFER
0.8 ~sec
PER
TRANSFER
*2.4 psec if interleaving with other channel and no wait states. 1,usec if
channel 15 waiting for request.
T C V - - - - - I - - - - - 14+N wAlr) .. T o v - - ' - - - - - i
TWA'T
I
T~
T,
T3
TWAIT
I
T.
\1.-SEE NOTE 1
-----~'-__,_.,_.O_UT_"_,,_-,._)_~~-~
ADDR/DATA
(1G.eIT
PHYSICAL 8US)
DTIA
DeN
\'----~/
NOTE 1; IRE IS STABLE II.•.• NON MULTIPLEXED) THROUGHOut EACH TRANSFER
CYCLE. .....
IIUS.
,1,,' ARE ALSO STABLE ON TRANSFERS TO A PHYSICAL '·BIT
Figure 7. 8089 Bus Operation
8-58
AFN-00840C
8089
ABSOLUTE MAXIMUM RATINGS·
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Ambient Temperature Under Bias ......... O'C to 70'C
Storage Temperature ...•..•...... -65'C to + 150'C
Voltage on Any Pin with
Respect to Ground ................. - 1.0 to
7V
Power Dissipation .....•................•.. 2.5 Watt
+
D.C. CHARACTERISTICS
Symbol
(TA = O'C to 70'e, Vee = 5V ±10%)
Parameter
Min.
Max.
Units
-0.5
+0.8
V
Test Conditions
Vcc+1.0
V
0.45
V
IOL=2.0 mA
V
10H = -400",A
VIL
Input Low Voltage
V IH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Icc
Power Supply Current
350
mA
TA=25'C
III
Input Leakage Current(1)
±10
OV
I lO
Output Leakage Current
± 10
".A
".A
VCl
Clock Input Low Voltage
+0.6
V
V CH
Clock Input High Voltage
V cc + 1.0
V
C IN
Capacitance of Input Buffer
(All input except
ADo- AD 15 , RQ/GT)
15
pF
fc = 1 MHz
C IO
Capacitance of I/O Buffer
(ADo- AD 15, RQ/GT)
15
pF
fc = 1 MHz
A.C. CHARACTERISTICS
2.0
2.4
-0.5
3.9
<
VIN
0.45V .;;
<
Vee
Your .;;
Vee
(TA = O'C to 70'C, Vee = 5V ±10%)
8089/8086 MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
200
500
ns
Tast Conditions
TClCl
ClK Cycle Period
TClCH
ClK low Time
('hTClCl)-15
TCHCl
ClK High Time
(V,TClCl) + 2
TCH1CH2
ClK Rise Time
10
ns
.From 1.0V to 3.5V
TCl2Cl1
ClK Fall Time
10
ns
From 3.5V to 1.0V
TDVCl
Data In Setup Time
30
ns
TClDX
Data In Hold Time
TR1VCl
ROY Setup Time into 8284 (See Notes 1. 2)
10
35
ns
ns
ns
ns
TClR1X
ROY Hold Time into 8284 (See Notes 1. 2)
TRYHCH
READY Setup Time into 8089
TCHRYX
READY Hold Time into 8089
TRYlCl
READY Inactive to ClK (See Note 4)
TINVCH
Setup Time Recognition (ORO 1.2 RESET. Ext 1.2) (See Note 2)
30
ns
TGVCH
RO/GT Setup Time
30
ns
0
('h TClCl) -
ns
15
ns
30
ns
-8
ns
TCAHCAl
CA Width
95
ns
TSlVCAl
SEl Setup Time
75
ns
TCAlSlX
SEl Hold Time
0
ns
TCHGX
GT Hold Time into 8089
TILIH
Input Rise Time (Except ClK)
20
ns
From 0.8V to 2.0V
TIHll
Input Fall Time (Except ClK)
12
ns
From 2.0V to O.8V
40
8-59
ns
AFN·00840C
8089
A.C~
CHARACTERISTICS (Continued)
TIMING RESPONSES
Min.
Max.
Units
TClML
Command Active Delay (See Note 1)
10
35
ns
TClMH
Command Inactive Delay (See Note 1)
10
TRYHSH
READY Active to Status Passive (See Note 3)
Symbol
Parameter
35
ns
110
ns
ns
TCHSV
Status Active Delay
10
110
TClSH
Status Inactive Delay
10
130
ns
rClAV
Address Valid Delay
10
110
ns
TClAX
Address Hold Time
10
TClAZ
Address Float Delay
TCLAX
TSVlH
Status Valid to ALE High (See Note" 1)
TCllH
TCHLl
TClDV
Data Valid Delay
10
TCHDX
Data" Hold Time
10
TCVNV
Control Active Delay (See Note 1)
f---
Test Conditions
Cl=BO pF
ns
BO
ns
15
ns
ClK low to ALE Valid (See Note 1)
15
ns
ALE Inactive Delay (See Note 1)
15
ns
110
ns
5
45
ns
10
45
ns
CL= 150 pF
ns
TCV"!X
ContrOl Inactive Delay (See Note 1)
TCHDTl
Direction ContrOl Active Delay (See Note 1)
50
ns
TCHDTH
Direction Control Inactive Delay (See Note 1)
30
ns
TClGl
RQ Active Delay
B5
ns
CL= 100 pF"
TClGH
RQ Inactive Delay
B5
ns
Note 5: CL = 30 pF
TClSRV
SINTR Valid Delay
150
ns
Cl=100 pF
TDLDH
Output Rise Time
20
ns
From O.BV to 2.0V
TDHOL
Output Fall Time
12
ns
From 2.0V to O.BV
0
NOTES: 1. Signal at 8284 or 8288 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next elK.
3. Aplies only to T3 and TW states.
.
.
4. Applies only to T2 state.
5. Applies only if RQ/GT Mode 1 CL=SOpf, 2.7 Kn pull up to Vee.
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
DEVICE
UNDER
TEST
~C'_'00PF
A.G. TESTING: INPUTS ARE DRIVEN AT2.4V FDA A LOGIC "1" ANDO.45V FDA
A LOGIC "0," THE CLOCK IS DRIVEN AT 4.3V AND 0.25\1. TIMING MEASUREMENTS ARE MADE AT 1.SV FOR BOTH A LOGIC "1" AND "0,"
CL
::::
l00pF
C, INCLUDES JIG CAPACITANCE
8-60
AFN.Q084OC
8089
WAVEFORMS
8089 BUS TIMING USING 8288
CLK
VCH
1
r-'-
,
Tw
I,r""-\
r'\
,r-\
1'----1
VCL--'
TCLAV-
see NOTE 7
2
CH1CH2-- --_I_TCL2CL1
Aa-A,s ON TRANSFERS
~
I\-----l
~
1 - TCHCL
L
1__
--TeLCL-_
f\---..-J
-TCHDX
-ro~=
~'-____---1-------+--~------1-----t-----__r-~
( TO AN 8·BIT PHYSICAL BUS
AND SHE
- - _ TCHSV
S2,S"So (EXCEPT HAL 1)
1------+1->"11
TCLAXA
A
19
----T::SV::L::H--t+-:'
_
a
\
2:~----
TCHDX-
~l~
56-53
~+--+--f--+----t-------f--~
16
{
-
~
ClOV
relAV
FLOAT
(SEE NOTE 3)
- TCLSH
FLOAT
(SEE NOTe 3)
TCHLL
r--
TCLlH
~----~~~-r--t---+-----r---yJ~---
ALE (8288 OUTPUT)
SEe NOTE 4
~~Ii~~
\
ROY (8264 INPUT)
TAYlCl_
f-TCHRYX
READY (80891NPUn
T
LAYHSH-l-
READ - (MWTC,AMWC.IOWC,AIDWC
=VOH)
see NOTE 1 (
AND ABOVE
AD'S,ADo
(lffiE)
-1
rCLAX ~ TRYHCH-
__T_C_LA_V_-+-+.JI.-r---f____-+T_C_LA,Z
Il
-
AwAo
____-+-+'I~+_--+-J
!-TDVCL-l-TCLDX--!
FLOAT
I
DATA IN
FLOA
,.II-
--
______-II-T.,C_H_D_TL_--+__
tTCHDTH
\~-4___~----t----rr
TCLML--
TCLMH-
8288 OUTPUTS
see NOTES 4,
5
TCVNV-
---++---f----f--+-'-'
WRITE - (RD,MRDC,IORC,DT/R
SEE NOTE 7 (
AND ABOVE
L
=YOH)
TCLAV-
AD,S·ADo
~ 1___
TCVNX-
-TCLAXr-
-
TCLD
I-
~FLOAT
TCHDX - -
(SEE
~'-_1--_-1_-' 1,---+--+------+----1-,1
, - - + - - - - - f - - - - - - - - + - - - - - - + - ' NOTE
A1S·AO
DATA OUT
-----+---1'
(BHE)
TCVNV-
DEN
r-__+
-----+~--+_--tJl
______-I-I____-+____--+_."I·~TCLML
3)
+-__________-I__T_C_v_NX_---+__~\1
____
~--TCLMH-
-
8288 OUJPUTS
see NOTES 4,5
TCLML
MWTC OR lowe
_
-
TCLMH
I
I. ALL SIQNAU; SWITCH BETWEEN YOH AND Ym UNLESS OTHERWise SPECIFIED
2. AOY IS SAMPLEO NEAR tHE END OF 1,.1",1.,. TO DETERMINE IF Tw "'''CHINE STAlES ARE TO BE INSERTED
3. ~~~t~~i~~ t:=~T:t7SV~L;L~'fl~~E:v. .;~: ::a~~~~:~~:oa~~~;~:~~uR~~~:s;Oi~; :6~NMO;;~:~:~~~~~ TO RUN "NOTl~ Ell BU5
~,SIGN"LS"T82&'OR82MAAESHDWNfOAREFEAENCEONLV.
______ _
5. THE ISSUANCE OF THE 6288 COMMolNO AND CONTROL SIGN"LS IMADe, MWlC. "",we, 10RC. lowe. "'lowe. INT .... AND DENllAGS THE
"CnVfHIGH8288CEN
8. ALL TIMING MEASUREMENTS ARE "''''DE AT 1.5Y UNLESS OTHEFlWIS~ NOTED
a 81T PHYSICAL DUA BUS,. A._A"
DON'T FLOAT ON II. AUD FROM AN 8 BIT PHYSICAL eus OR MULTIPLEX WITH
OATA ON A WAITE TO AN 8 BIT PHYSICAL BUS 1HE IS STABLE ,NON
MULllPlEXEOIFORAll TRANSFERS
T, A.oA" AAESTABlEON1AANSFERSTO AN
8-61
AFN-D0840C
intJ
WAVEFORMS (Continued)
ASYNCHRONOUS SIGNAL RECOGNITION
, C,LK
NOTES:',
,
1. SETUP REQUIREMENTS FOR ASYNCHRONOUS SIGNALS ONLY TO OUARANTEE
z.
NEGAllVE EDOiE TRIGGERED.
RECOQNInON AT NEXT elK.
ALL INPUTS EXCEPT CA ARE LATCHED ON A elK EDGE. THE CA INPUT IS
n.
3. DRQ BECOMINQ ACTIVE GREATER THAN 30
AFTER THE RISING EDGE OF elK
WILL GUARANTEE NON·RECOGNITION UNTIL THE NEXT RISING CLOCK EDGE.
BUS LOCK SIGNAL TIMING AND SI"TR
Any elK
cYCle-I
elK
elK
'-----_Tel.RYj,---..
SlNTR 1,2: _
"-----."
REQUEST/GRANT SEQUENCE
8019 AS SLAYE (MODe D)
~tT
rJ
"" I I
8019 aT INPUT
(FROM MASTER)
8089;m OUTPUT
'
.
"-
8089 AS MASTER
(TOMAs1'EA)
8089 REQIUESTB BUS
8089 WAITS
(MODE~)
F~A BUS
8089 FLOATS STATUS BUS
TCHGX
lOYeH
TeL.l
-I
TeLa"
8089 FLOATS
AID BUS
L-.!.
.._._,."'Q:-'-NP'"'U"T....J'
(FROM CURRENT SLAYE)
-.~"'-~ .
TCHOX
raveH
---+-
8089 aT OUTPUT
(OLD MASTER BeCOMes NEW SLAVE)
r.oaJ
- --
t
808. RQ INPUT
(FAOM CURRENT SLAYE)
i-- TeLal
-=
-!
FLOATS AID BUS
_TeLa"
1- t
TCHOX
1
F-~~~J:
8011 CiT OUTPUT
(OLD MASTER BECOMES NEW SLAVE)
8-62
1011 iiEmft INPUT
(TO MASTER)
AFN·00840C
8089
WAVEFORMS (Continued)
EXTERNAL TERMINATE SETUP
elK
EXT 1,2
SEL SETUP AND TIMING
TCAHCAl_
CA
SEL
. •'SLVCAL_I--'CALSLX.
8-63
AFN-00840C
8089
8089 INSTRUCTION SET SUMMARY
Data Transfers
OPCODE
POINTER INSTRUCTIONS
7
LPD P,M
LPDI P,I
MOVPM,P
MOVPP,M
Load Pointer PPP from Addressed Location
Load Pointer PPP Immediate 4 Bytes
Store Contents of Pointer PPP in Addressed Location
Restore Pointer
P
P
P
P
P
P
P
P
oA
0
1
0
0
A
000
A A
A A
o
o
M,M
MOV
MOV
MOVI
MOVI
R,M
M,R
R
M
1 1 0 0 0
1
0 0 0
1 100 1
1 1 000
o
1
1
1
1
OMM
000
OMM
1 MM
OPCODE
MOVE DATA
MOV
0
0 7
P
P
P
P
o
o
0 0 0 OAAW
SourceO. 0 0 OAAW
Destination- .
RR R 0
A .AW
Load Register RRR from Addressed Location
Store Contents of Register RRR in Addressed Location R R R 0 OAAW
R R R wb OOW
Load Register RRR Immediate (Byte) Sign Extend
000 wb AAW
Move Immediate to Addressed Location
Move from Source to Destination
o
o
1
0 1
1 1 00
1 000
1 000
0 1 1
1 0 0
o
o
OOMM
11M M
OOMM
1 MM
0 0 0
11M M
o
o
Control Transfer
OPCODE
07
CALLS
7
"CALL
Call Unconditional
11
o0
1 1 MM 1
OPCODE
JUMP
JMP
JZ
M
R
JZ
JNZ M
JNZ R
JBT
JNBT
JMCE
JMCNE
0
dd A AW 11 0 0 1
1 0 0
000
R R R
000
R RR
B B B
B. B B
000
000
Unconditional
Jump on Zero Memory
Jump on Zero Register
Jump on Non-Zero Memory
Jump on Non-Zero Register
Test Bit and Jump if True
Test Bit and Jump if Not True
Mask/Compare and Jump on Equal
Mask/Compare and Jump on Non-Equal
o0
OOW
AAW1
o0 0 0
AAW1
000 o
A AD 1
A AD 1
A AD 1
A AD 1
dd
dd
dd
dd
dd
dd
dd
dd
dd
1
1
1
1
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
1
o
0 0 0
01MM
o10 0
OOMM
o0 0 0
11M M
10M M
OOMM
o 1MM
Arithmetic and Logic Instructions
OPCODE
INCREMENT, DECREMENT
"ADDI
'ADDI
tADD
tADD
M,I
R,I
M,R
R,M
ADD
ADD
ADD
ADD
o 000
Immediate to Memory
Immediate to Register
Register to Memory
Memory to Register
R RR 0
0 0 0
R RR 0
o
8-64
0
07
7
OAAW 1 1 1 0
0 0 0 o 0 1 1
OAAW 1 1 1 0
o0 0 0 0 1 1
o
o
1
1
1
1
OMM
000
1MM
100
AFN-00840C
inter
8089
Arithmetic and Logic Instructions
OPCODE
ADD
o
7
ADDI
ADDI
ADD
ADD
M,l
R,l
M,R
R,M
ADD
ADD
ADD
ADD
000
R R R
R R R
R R R
M,l
R,l
M,R
R,M
AND
AND
AND
AND
000 wb AAW 1 1 0 0
R R R wb OOW a a 1 0
R R R a a A AW 1 1 a 1
R R R a OAAW 101 a
1 OMM
1 a a a
1 OMM
1 OMM
OPCODE
Memory with Immediate
Register with Immediate
Memory with Register
Register with Memory
OPCODE
OR
ORl
ORl
OR
OR
M,l
R,l
M,R
R,M
OR
OR
OR
OR
a a a wb AAW 1 1 a a
R R R wb AAW a a 1 a
R R R a OAAW1 1 a 1
R R R a OAAW 101 0
Memory with Immediate
Register with Immediate
Memory with Register
Register with Memory
R
M
R,M
a 1MM
a 100
a 1MM
a 1MM
OPCODE
NOT
NOT
NOT
NOT
0
0 OMM
0 000
0 OMM
OOMM
AND
ANDl
ANDI
AND
AND
7
wb AAW 1 1 0
wb OOW o 0 1
0 OAAW1 1 0
0 OAAW 101
0
0
1
0
Immediate to Memory
Immediate to Register
Register to Memory
Memory to Register
R R a a a a a a a 1 a
a a a a OAAW 1 1 0 1
R R R a OAAW 1 a 1 a
IR
Complement Register
Complement Memory
Complement Memory, Place in Register
1 1 a a
1 1 MM
1 1 MM
Bit Manipulation and Test Instructions
OPCODE
BIT MANIPULATION
7
SET
CLR
a
a
oAAol111 1
OAA O l111 1
0 1 MM I
1 OM MJ
OPCODE
TEST
TSL
0
07
IB B B
IB B B
Set the Selected Bit
Clear the Selected Bit
Test and Set Lock
10
aa
1
1 A A
a 11 a
0 1
a
1 MM
I
Control
OPCODE
Control
7
HLT
SINTR
NOP
XFER
WID
Halt Channel Execution
Set Interrupt Service Flip Flop
No Operation
Enter DMA Transfer
Set Source, Destination Bus Width; S,D 0=8, 1 = 16
8-65
aa1a
a1aa
aaaa
a11a
1 S 0 a
07
aaaa
aaaa
aaaa
aaaa
aaaa
0
a10a 1aaa
aa0a aaaa
aa0a aaaa
aa0a aaaa
aa0a aaaa
AFN-00840C
intJ
8089
'II field in call instruction can be 00, 01, 10 only.
NOTES:
"OPCODE is second byte fetched.
All Instructions consist of at least 2 bytes, while some
Instructions may use up to 3 additional bytes to specify
literals and displacement data. The definition of the
various fields within each instruction is given below:
BBB Bit Select Field
The bit select field replaces the RRR field in bit manipulation instructions and is used to select a bit to be operated on by those instructions. Bit 0 is the least significant bit.
wb
o
01
10
dd
01
10
7
PPP BBB
1 byte literal
2 byte (word) literal
1 byte displacement
2 byte (word) displacement.
AA Field
00 The selected pOinter contains the operand address.
01 The operand address is formed by adding an B-bit,
unsigned, offset contained in the instruction to the
selected pOinter. The contents of the pointer are unchanged.
10 The operand address is formed by adding the contents of the Index register to the selected pointer.
Both registers remain unchanged.
11 Same as 10 except the Index register is post autoincremented (by 1 for B-bit transfer, by 2 for 16-bit
transfer).
M M Base Pointer Select
00 GA
01 GB
10 GC
11 PP
RRR Register Field
The RRR field specifies a 1S-bit register to be used in
the instruction. If GA, GB, GC or TP, are referenced by
the RRR field, the upper 4 bits of the registers are loaded with the sign bit (Bit 15). PPP registers are used as
20-bit address pOinters.
W Width Field
o
The selected operand is 1 byte long.
1 The selected operand is 2 bytes long.
RRR
000
001
010
011
100
101
110
111
rO
r1
r2
r3
r4
r5
rS
r7
GA
GB
GC
BC
TP
IX
CC
MC
Additional Bytes
; byte count
; task block
; index register
; channel control (mode)
; mask/compare
OFFSET: B-blt unsigned offset.
SDISP : B/1S-bit signed displacement.
LITERAL: B/1S-bit literal. (32 bits for LOP!).
The order in which the above optional bytes appear in lOP
instructions is given below:
ppp
000
001
010
100
OFFSET
pO
p1
p2
p4
GA
GB
GC
TP
I
Offsets are treated as unsigned numbers. Literals and
displacements are sign extended (2's complement).
; task block pOinter
8-66
AFN-00840C
8259A/8259A-2/8259A-8
PROGRAMMABLE INTERRUPT CONTROLLER
• iAPX 86, iAPX 88 Compatible
• Programmable Interrupt Modes
• MCS-80®, MCS-85® Compatible
• Individual Request Mask Capability
• Eight-Level Priority Controller
• Single
• Expandable to 64 Levels
• 28-Pin Dual-In-Line Package
+ 5V Supply (No Clocks)
The Intel'" 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28·pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel'" 8259. Software originally written for the 8259 will operate the
8259A in all 8259 equivalent modes (MCS·80/a5, Non-Suffered, Edge Triggered).
°7-°0
DATA
BUS
CONTROL LOGIC
BUFFER
IRO
IR'
IR2
RD
ViR
IT
CASD
CASCADE
CAS 1
Cs
WR
AD
"0
0,
IR1
D.
IR6
0,
IR5
D.
IR4
0,
IR3
0,
IR2
0,
IR'
iNfA
Do
IRO
CASO
INT
CAS'
SP/EN
GND
CAS2
BUFFERI
COMPARATOR
CAS 2
SP/EN
~INTERNAl
BUS
Figure 1. Block Diagram
Figure 2. Pin Configuration
8-67
8259A/8259A-2/8259A-8
Table 1. Pin Description
Pin No.
Type
Vee
Symbol
26
I
Supply: +5V Supply.
GND
14
I
Ground.
1
I
Chip Select: A lowon this pin enables RD and WR communication between the CPU and the 6259A.
INTA functions are independent of CS.
WR
2
0
Write: A low on this pin when CS is low enables the 6259A to accept command words from the CPU.
RD
3
I
Read: A Iowan this pin when CS is low enables the 8259A to release status onto the data bus forthe
CPU.
CS
Name and Function
4-11
I/O
Bidirectional Data Bus: Control, status and interrupt-vector information is transferred via this bus.
12,13,15
I/O
Cascade Lines: The CAS lines form a private 6259A bus to control a multiple 6259A structure. These
pins are outputs for a master 6259A and inputs for a slave 6259A.
SP/EN
16
I/O
Slave Program/Enable Buller: This is a dual function pin. When in the Buffered Mode it can be used
as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input
to designate a master (SP = 1) or slave (SP = 0).
INT
17
0
Interrupt: This pin goes high whenever a valid interrupt request is asserted. It is used to interruptthe
CPU, thus it is connected to the CPU's interrupt pin.
16-25
I
Interrupt Requests: Asynchronous inputs. An interrupt request is executed by raising an IR input
(low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high
level on an IR input (Level Triggered Mode).
INTA
26
I
Interrupt Acknowledge: This pin is used to enable 6259A interrupt-vector data onto the data bus by
a sequence of interrupt acknowledge pulses issued by the CPU.
Ao
27
I
AO Address Line: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 6259A
to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically
connected to the CPU AO address line (AI for iAPX 66, 68).
D7-DO
CASO-CAS2
IRo-IR7
AFN.(){)221C
inter
8259A/8259A-2/8259A-8
FUNCTIONAL DESCRIPTION
Interrupts in Microcomputer Systems
Microcomputer system design requires that 1/0 devices
such as keyboards, displays, sensors and other com·
ponents receive servicing In an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on through·
put.
match his system requirements. The priority modes can
be changed or reconfigured dynamically at any time duro
ing the main program. This means that the complete
interrupt structure can be defined as required, based on
the total system environment.
The most common method of servicing such devices II'
the Polled approach. This Is where the processor mus,
test each device in sequence aild In effect "ask" each
one if It needs servicing. It is easy to see that a large por·
tion of the main program is looping through this con·
tinuous polling cycle and that such a method would
have a serious, detrimental effect on system through·
put, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness
of using such devices.
A more desirable method would be one that would allow
the microprocessor to be executing its main program
and only stop to service peripheral devices when it Is
told to do so by the device itself. In effect, the method
would provide an external asynchronous input that
would inform the processor that It should complete
whatever instruction that is currently being executed
and fetch a new routine that will service the requesting
device. Once this servicing is complete, however, the
processor would resume exactly where it left off.
cpu· DRIVEN
MULTIPLEXOR
CPU
RAM
The 8259A
The 8259A Is a device specifically designed for use in
real time, interrupt driven microcomputer systems. It
manages eight levels or requests and has bullt·ln fea·
tures for expandabllity to other 8259A's (up to 64 levels).
It is programmed by the system's software as an I/O
peripheral. A selection of priority modes Is available io
the programmer so that the manner In which the reo
quests are processed by the 8259A can be configured to
8-69
<:==:>
~
ROM
1/0111
I--
1/0121
r--
r---,
I
I
~
110 INI
t---~
IL ___ ..JI
v
This me\hod is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
The Programmable Interrupt Controller (PIC) functions
as an overall manager In an Interrupt·Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the Incoming requests
is of the highest importance (priority), ascertains
whether the incoming request has a higher priority value
than the level currently being serviced, and issues an
interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or "routine" that is associated with its specific
functional or operational requirements; this is referred
to as a "service routine". The PIC, after issuing an Inter·
rupt to the CPU, must somehow Input Information into
the CPU that can "point" the Program Counter to the
service routine associated with the requesting device.
This "pointer" is an address In a vectoring table and will
often be referred to, In this document, as vectoring data.
:~~
----
Figure 3a. Polled Method
CPU
INT
I--
t-lt-
RAM
~
['r-V
ROM
r---v ~
110111
t-
~
1/0121
-
Kr--
PIC
~
,-----,
I
I
~
IIOINI
r--
1_____ J1
7
Figure 3b. Interrupt Method
AFN·00221C
intJ
8259A!8259A-2/8259A-8
INTERRUPT REQUEST REGISTER (IRR) AND
IN·SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register
(IRR) and the In·Service Register (ISR). The IRR is used
to store all the interrupt levels which are requesting ser·
vice; and the ISR is used to store all the interrupt levels
which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorities of the bits set
in the IRR. The highest priority is selected and strobed
into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt lines
to be masked. The IMR operates on the IRR. Masking of
a higher priority input will not affect the interrupt
request lines of lower priority.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible
with the 8080A, 8085A and 8086 input levels.
Figure 4a. 8259A Block Diagram
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring
information onto the data bus. The format of this data
depends on the system mode ("PM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control words
and status information are transferred through the Data
Bus Buffer.
READIWRITE CONTROL LOGIC
The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command
Word (OCW) registers which store the various control
formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the
Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading or
writing of the chip will occur unless the device is
selected.
Figure 4b. 8259A Block Diagram
WR (WRITE)
A LOW on this input enables the CPU to write control
words (ICWs and OCWs) to the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In Service
Register (ISR), the. Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.
8-70
Ao
This input signal is used in conjunction with WR and RD
signals to write. commands into the various command
registers, as well as reading the various status registers
of the chip. This line can be tied directly to one of the address lines.
AFN-00221C
8259A18259A-2/8259A-8
If no interrupt request is present at step 4 of either
sequence (I.e., the request was too short in duration) the
8259A will issue an Interrupt level 7. Both the vectoring
bytes and the CAS lines will look like an Interrupt level 7
was requested.
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all
8259A's used in the system. The associated three 1/0
pins (CASO-2) are outputs when the 8259A Is used as a
master and are Inputs when the 8259A is used as a
slave. As a master, the 8259A sends the ID of the Inter·
rupting slave device onto the CASO-2 lines. The slave
thus selected will send Its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses. (See section "Cascading the
8259A".)
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or Indirect
jumping to the specific interrupt routine requested
without any polling of the interrupting devices. The nor·
mal sequence of events during an interrupt depends on
the type of CPU being used.
..
iW
'"
OR'
The events occur as follows in an MCS·80/85 system:
_IRI
1. One or more of the INTERRUPT REQUEST lines
(IR7-0) are raised high, setting the corresponding IRR
bit(s).
2. The 8259A evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an
INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259A will also release a CALL in·
struction code (11001101) onto the 8·bIt Data Bus
through its D7 -0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus. The lower 8·bit address is released at the first
INTA pulse and and the higher 8·bit address is reo
leased at the second INTA pulse.
7. This completes the 3·byte CALL instruction released
by the 8259A. In the AEOI mode the ISR bit is reset at
the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is
issued at the end of the interrupt sequence.
"
OR'
Figure 4c. 8259A Block Diagram
\
ADDRESS BUS UB}
\
CONTROL BUS
l
l
IfOR
\
The events occurring in an iAPX 86 system are the same
until step 4.
LINES
INTA
\
CAH
D
WI<
INT
INTA
825eA
CAS'
CAS 2
SPlm
liD
°7.0 0
"0
IRQ IRO IRQ IRQ IRO IRQ IRO IRQ
3
7
5
4
2
0
•
PROGL~ I I I
5. The iAPX 86/10 will initiate a second INTA pulse.
During this pulse, the 8259A releases an 8·bit pointer
onto the Data Bus where it is read by the CPU.
INT
DATA BUS (81
"-{=
--
4. Upon receiving an INTA from the CPU group, the high·
est priority ISR bit is set and the corresponding IRR
bit is reset. The 8259A does not drive the Data Bus
during this cycle.
iTOii
SLAVE
I
ENABLE BUFFER
•
I
III
11
INTERRUPT
REQUESTS
6. This completes the interrupt cycle. In the AEOI mode
the ISR bit is reset at the end of the second INTA
pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the
interrupt subroutine.
8-71
Figure 5. 8259A Interface to Standard
System Bus
AFN-0022.C
8259A/8259A-2/8259A-8
not issue any data to the processor and leaves its data bus
buffers disabled. On the second interrupt acknowledge
cycle in iAPX 86 modethe master (or slave if so programmed) will send a byte of data to the processor with
the acknowledged interrupt code composed as follows
(note the state of the ADI mode control is ignored and
As-A11 are unusediniAPX 86 mode):
INTERRUPT SEQUENCE OUTPUTS
MCS-aO®,MCS-85®
This sequence is, timed by three INTA pulses. During the
first INTA pulse the CALL opcode is enabled onto the
data bus.
Content of First Interrupt
Vector Byte
07
I
CALL CODE
06
1
05
04
0
0
03
02
01
DO
0
1
Content of Interrupt Vector Byte
for IAPX 86 System Mode
I
DO
07
06
05
04
03
02
01
During the second INTA pulse the lower address of the
appropriate service routine is enabled onto the data bus.
When Interval 4 bits As-A7 are programmed, while AoA4 are automatically inserted by the 8259A. When Inter, val =8 only As and A7 are programmed, while Ao-As are
automatically inserted.
IA7
T7
TS
T5
T4
T3
1
1
1
lAS
T7
TS
T5
T4
T3
1
1
0
IA5
T7
TS
T5
T4
T3-
1
0
1
IA4
T7
TS
T5
T4
T3
1
0
0
IA3
T7
TS
T5
T4
T3
0
1
1
IA2
T7
T6
T5
T4
T3
0
1
0
Content of Second Interrupt
Vector Byte
IAI
T7
T6
T5
T4
T3
0
0
1
lAO
T7
T6
T5
T4
T3
0
0
'0
=
Inlerval~4
IR
07
06
05
04
03
02
01
DO
7
A7
AS
A5
1
1
1
0
0
S
A7
A6
AS
1
1
0
0
0
5
A7
AS
AS
1
0
1
0
0
4
A7
A6
AS
1
0
0
0
0
3
A7
AS
AS
0
._.-
1
1
0
0
2
A7
AS
AS
0
A7
AS
AS
0
0
1
1
0
1
0
0
0
0
0
A7
A6
AS
0
0
0
0
0
07
06: '
05
04
03
02
01
DO
7
A7
AS
1
1
1
S
A7
AS
1
1
0
0
0
0
0
A7
AS
1
0
1
0
A7
AS
1
0
0
0
0
1
IR
S
-
4
PROGRAMMING THE 8259A
The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (JCWs): Before normal
operation can begin, each 8259A in the system must
be brought to a starting point - by a sequence of 2 to
4 bytes timed by WR pulses.
.
2. Operation Command Words (OCWs): These are the
command words which command the 8259A to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
Inlerval=8
--
-
0
-~
0
0
0
0
The OCWs can be written into the 8259A anytime after
Initialization.
0
--A7
2
AS
0
1
0
0
0
0
------------1
A7
A6 0
0
1
0
0
0
-------------------------------~
AS
0
000
0
0
0
- - - - - , . _ - - _.. _----3
--
A7
AS
1
0
0
INITIALIZATION COMMAND WORDS
(ICWS)
GENERAL
During the third INTA pulse the higher address of the
appropriate service routine, which was programmed as
byte 2 of the initialization sequence (As - A 1s), is
enabled onto the bus.
Whenever a command is issued with AO =0 and 04 = 1,
this is interpreted as Initialization Command Word 1
(ICW1). ICW1 starts the initialization sequence during
which the following automatically occur.
Content of Third Interrupt
Vector Byte
a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input
must make a low-to-high transition to generate an
interrupt.
b. The Interrupt Mask Register is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set to
IRR.
f. If IC4=O, then all functions selected in ICW4 are set to
zero. (Non-Buffered mode", no Auto-EOI, MCS-80, 85
system).
07
AIS
I-
06
03
02
01
DO
A14
All
Al0
A9
AS
iAPX 86, iAPX 88
iAPX 86 mode is similar to MCS-80 mode except that only
two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor. The
first interrupt acknowledge cycle is similar to that of
MCS-80, 85 systems in that the 8259A uses it to internally
freeze the state of the interrupts for priority resolution and
as a master it issues the interrupt code on the cascade
lines at the end of the INTA pulse_ On this first cycle it does
8-72
"Nole: Masler/Slave In ICW4 is only used in the buffered mode.
AFN-00221C
inter
8259A/8259A·2/8259A·8
INITIALIZATION COMMAND WORD 3 (lCW3)
INITIALIZATION COMMAND WORDS 1 AND 2
(ICW1,ICW2)
A5-A 15: Page starting address of service routines. In an
MCS 80/85 system, the 8 request levels will generate
CALLs to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (A o-A 15). When the
routine interval is 4, Ao-A4 are automatically inserted by
the 8259A, while A5-A 15 are programmed externally.
When the routine Interval Is 8, Ao-A5 are automatically
inserted by the 8259A, while As-A15 are programmed
externally.
The 8·byte interval will maintain compatibility with cur·
rent software, while the 4·byte Interval is best for II com·
pact jump table.
In an iAPX 86 system A15-A11 are inserted in the five most
significant bits of the vectoring byte and the 8259A sets
the three least significant bits according to the interrupt
level. A10-A5 are ignored and ADI (Address interval) has
no effe9t.
LTIM:
If LTIM=1, then the 8259A will operate In the
level Interrupt mode. Edge detect logic on the
Interrupt Inputs will be disabled.
ADI:
CALL address Interval. ADI = 1 then Interval = 4;
ADI = 0 then Interval = 8.
.
SNGL: Single. Means that this Is the only 8259A In the
system. If SNGL= 1 no ICW3 will be Issued.
IC4:
If this bit Is set - ICW4 has to be read. If ICW4
Is not needed, set IC4 = O.
This word is read only when there is more than one
8259A In the system and cascading is used, in which
case SNGL= O. It will load the 8·bit slave register. The
functions of this register are:
a. In the master mode (either when SP = 1, or in buffered
mode when M/S= 1 in ICW4) a "1" is set for each
slave in the system. The master then will release byte
1 of the call sequence (for MCS-80/85 system) and
will enable the corresponding slave to release bytes.2
and 3 (for iAPX 86 only byte 2) through the cascade
lines.
b.ln the slave mode (either when SP=O, or If BUF= 1
and MIS = 0 in ICW4) bits 2-0 identify the slave. The
slave compares its cascade Input with these bits and,
If they are equal, bytes 2 and 3 of the call sequence (or
just byte 2 for iAPX 86 are released by it on the Data
Bus.
INITIALIZATION COMMAND WORD 4 (lCW4)
SFNM: If SFNM = 1 the special fully nested mode Is
programmed.
BUF: If BUF = 1 the buffered mode Is programmed. In
buffered mode SP/EN becomes an enable outplA
and the mastfilrlslave determination Is by MIS.
MIS: If buffered mode Is selected: MIS = 1 means the
8259A Is programmed to be a master, MIS = 0
means the 8259A Is programmed to be a slave. If
BUF = 0, MIS has no function.
AEOI: If AEOI =·1 the automatic end of Interrupt mode
Is programmed.
"PM: Microprocessor mode: p,PM = 0 sets the 8259A for
MCS-80, 85 system operation, p,PM = 1 sets the
8259A for iAPX 86 system operation.
NO ISINGL '" 1)
NO (1C4 = 0)
Figure 6_ Initialization Sequence
8-73
AFN'()0221C
8259A!8259A-2/8259A-8
lew,
1 lewe NEEDED
0: NO ICW" NEEDED
1 = SINGLE
o ;;
CASCADE MODE
CAll AL'ORESS INTERVAL
1" INTERVAL OF ..
O· INTERVAL OF 8
1, = LEvEL TRIGGERED MODE
EDGE TRIGGEAED MODE
o=
A7-AS 01 INTERRUPT
VECTOR ADDRESS
(MeS-BO/BS MODE ONLY)
A,
lew,
0,
D.
A'5-Aa OF INTERRUPT
VECTOR ADDRESS
(MCSaD/55 MODE)
T7-T3 OF INTERRUPT
VECTOR ADDRESS
tatllMASTER DEVICE)
(808618088 MODE)
1 = IR INPUT HAS A SLAVE
0" IR INPUT OOES NOT HAVE
A SLAVE
..
ICW31SLAVE DEVICE)
0,
D.
0
0
0,
0,
0,
'
"
I ' I I I I I 1'0, lID, 11D,j
D.
0
0
U,
0
SLAVE 10111
o ,
o ,
o 0
o 0
,
3
•
•
•
7
0
,
0
,
0
,
,
,
0
0
0
o , ,
,,
,,
1 = B08618088 MODE
0= Mes-aOl55 MODE
1
AUTO EOI
0= NORMAl. EOI
,-0
- BUFFERED MODEfSlAVE
~
1
1
- BUFFERED MODE/MASTER
x
.
NON BUFFERED MODE
1 = SPECIAL FUllY NESTED
L-_ _ _ _ _ _ _ _+j 0 ;;
NOTE 1: SLAVE 10 IS EQUAL TO THE CORRESPONDING
MASTER IR INPUT.
~g~~PECIAL
FULLY
NESTED MODE
Figure 7. Initialization Command Word
8-74
Forma~
AFN.()()221C
8259A!8259A-2/8259A-8
OPERATION COMMAND WORDS (OCWs)
OPERATION CONTROL WORD 1 (OCW1)
After the Initialization Command Words (ICWs) are programmed Into the 8259A, the chip Is ready to accept
Interrupt requests at Its Input lines. However, during the
8259A operation, a selection of algorithms can command the 8259A to operate In various modes through
the Operation Command Words (OCWs).
OCW1 sets and clears the mask bits in the interrupt
Mask Register (lMR). M7 - Mo represent the eight mask
bits. M = 1 indicates the channel is masked
(inhibited), M = 0 indicates the channel is enabled.
OPERATION CONTROL WORD 2 (OCW2)
R, SL, EOI - These three bits control the Rotate and
End of Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Operation Command Word Format.
OPERATION CONTROL WORDS (OCWs)
OCWl
AO
[i]
07
I M7
06
05
04
03
02
01
DO
M6
M5
M4
M3
M2
Ml
MO
I
L2 , L1 , Lo-These bits determine the interrupt level acted
upon when the SL bit is active.
OPERATION CONTROL WORD 3 (OCW3)
OCW2
0
I
A
SL
EOI
0
0
L2
Ll
LO
I
ESMM - Enable Special Mask Mode. When this bit is
set to 1 it enables the SMM bit to set or reset the Special
Mask Mode. When ESMM = 0 the SMM bit becomes a
"don't care".
=
OCW3
0
0
ESMM SMM
0
P
AA
AIS
I
8-75
SMM - Special Mask Mode. If ESMM 1 and SMM = 1
the 8259A will enter Special Mask Mode. If ESMM = 1
and SMM = 0 the 8259A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.
AFN-D0221C
8259A18259A-2/8259A-8
ocw,
OCW2
AO
Ol
D,
Os
04
~
D3
Do
D,
I • "I ILI'O'I· I· I L,I L·I Lol
I
IRLEVELTOBE
ACTED UPON
• ,, •, 4 5, • ,7
• • • •
• • , , •, •, ,, ,,
••••
2
l r
rt.fff-i"
•.f
,fci"f-i"
• rut-;
.1i'1-1r
,I-TI-T
~~~
~:...!..!.2.
NON-SPECIFIC EOICOllMAND
SPECIFIC EOI eoMMANO
AOTATI! ON NON-SPECIFIC EOI COMMAND
ROTATE IN AU1"OMATIC EOI MODE (SETl
AOTArI! IN AUTOMATIC ,EOI MODE (CLEAR)
"ROTATE ON SPECIFIC EOI COMMAND
"SET PRIORITY COMMAND
NOO~ON
l
}
l
END OF INTERRUPT
. AIITOIlATlCROTATlON
SPEClFJC ROTATION
"LO-L2 AfIE USED
OOW.
At.
I· I
0 7Da'?s
0
D.Dl
IESMMI SMM I • I ' I
D,
D2
p
I
RR
Do
I "IS
I
I Lf.
READ REGISTER COMMAND
• I ,
• I •
NO ACTION
•
,
READ
IR REG
~N£:,(T
,
,
READ
ISREG
ON NEXT
RDPULSE RDPULSE
, .. POLL COMMAND
a-NO POLL COMMAND
SPECIAL MASK MODE
• I ,
• I •
•,
NO ACTION
SPECIAL
RESET
MASk
,
,
SET
SPECIAL
MASK
Figure 8. Operation Command Word Format
8-76
AFN.()()221C
8259A/8259A-2/8259A-8
FULLY NESTED MODE
AUTOMATIC ROTATION
This mode is entered after initialization unless another
mode is programmed. The interrupt requests are
ordered in priority form 0 through 7 (0 highest). When an
interrupt Is acknowledged the highest priority request is
determined and Its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all further interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be
acknowledged only If the microprocessor internal Interrupt enable flip·flop has been re-enabled through software).
(Equal Priority Devices)
In some applications there are a number of Interrupting
devices of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
requesting an Interrupt will have to walt, In the worst
case until each of 7 other devices are serviced at most
once. For example, If the priority and "In service" status
Is:
Before Rotate (IR4 the highest priority requiring service)
"IS" Status
ISO
0
Low••t Priority
Priority Status
After the Initialization sequence, IRO has the hlgnesl
priority and IR7 the lowest. Priorities can be changed, as
will be explained, In the rotating priority mode.
157 lSI 1&5 164 153 152 151
101 , 101,010101
1
Hlgh"~rlOrlt'
I 716 I 5 I 4 I 3 I 2 I 1]'0 I
After Rotate (lR4 was serviced, all other priorities
rotated correspondingly)
END OF INTERRUPT (EOI)
The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when ~EOI bit in ICW1 is set) or by a command
word that must be Issued to the 8259A before returning
from a service routine (EOI command). An EOI command
must be issued twice if in the Cascade mode, once forthe
master and once for the corresponding slave.
There are two forms of EOI commalld: Specific and Non·
Specific. When the 8259A is operated in modes which
preserve the fully nested structure, it can determine
which IS bit to reset on EOI. When a Non·Speclflc EOI
command is issued the 8259A will automatically reset
the highest IS bit of those that are set, Since in the
fully nested mode the highest IS level was necessarily the
last level acknowledged and serviced. A non-specific EOI
can be issued with OCW2 (EOI = 1, SL = 0, R = 0).
IS7 lSI IS5 164 153 IS2 151
ISO
"IS" Status
1 0 1 , 1010101010101
Priority Status
I I 110 I 7f'a-rD I 1
Hlgh••t Prtorlt,
2
Low ••t Prlortt,
4
3
There are two ways to accomplish Automatic Rotation
using OCW2, the Rotation on Non-Specific EOI Command
(R = 1, SL = 0, EOI = 1) and the Rotate in Automatic EOI
Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared
by (R = 0, SL = 0, EOI = 0).
SPECIFIC ROTATION
(Specific Priority)
When a mode is used which may disturb the fully nested
structure, the 8259A may no longer be able to determine
the last levei acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the
command the IS level to be reset. A specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R = 0, and LO-L2 is the
binary level of the IS bit to be reset).
The programmer can change priorities by programming
the bottom priority and thus fixing all other priorities;
i.e., if IR5 is programmed as the bottom priority device,
then IR6 will have the highest one.
It should be noted that an IS bit that is masked by an
IMR bit will not be cleared by a non·specific EOI if the
8259A is In the Special Mask Mode.
Observe thaUn this mode internai status is updated by
software control during OCW2. However, it is independent
of the End of Interrupt (EOI) command (also executed by
OCW2). Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI command
in OCW2 (R = 1, SL = 1, EOI = 1 and LO-L2 = IR level to
receive bottom priority).
AUTOMATIC END OF INTERRUPT (AEOI) MODE
If AEOI = 1 In ICW4, thenthe 8259A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode. the 8259A will automatically perform a nonspecific EOI operation at the trailing edge of the last
interrupt acknowledge pulse (third pulse in MCS·80/85,
second in iAPX 86). Note that from a system standpoint,
this mode should be used only when a nested multilevel
interrupt structure is not required within a single 8259A.
The AEOI mode can only be used in a master 8259A and
not a slave.
8-77
The Set Priority command is issued in OCW2 where:
R = 1, SL = 1; LO-L2 isthe binary priority level codeofthe
bottom priority device.
INTERRUPT MASKS
Each Interrupt Request Input can be masked Individually by the Interrupt Mask Register (lMR) programmed
through OCW1. Each bit In the IMR masks one Interrupt
channel If It Is set (1). Bit 0 masks IRO, Bit 1 masks IR1
and so forth. Masking an IR channel does not affect the
other channels operation.
AF~1C
8259A18259A-2/8259A-8
SPECIAL MASK MODE
POLL COMMAND
Some applications may require an interrupt service
routine to dynamically alter the system priority struc·
ture during its execution under software control. For
example, the routine may wish to Inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion.
.
In this mode the INT output is not used or the microprocessor internal Interrupt Enable flip-flop is reset, disabling
its interrupt input. Service to devices is achieved by
software using a Poll command.
The Poll command is Issued by setting P = "1" in OCW3.
The 8259A treats the next RD pulse to the 8259A (i.e.,
RD = 0, OS 0) as an interrupt acknowledge, sets the
appropriate IS bit if there is a reque~ and~ads the
priority level. Interrupt is frozen from WR to RD.
=
The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine),
the 8259A would have Inhibited all lower priority
requests with no easy way for the routine to enable
them
The word enabled onto the data bus during
07
That is where the Special Mask Mode comes In. In the
special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables inter·
rupts from a/l other levels (lower as well as higher) that
are not masked.
I
04
05
03
I
Rl5 is:
02
01
DO
W2
W1
wol
WO-W2: Binary code of the highest priority level
requesting service.
I: Equal to a "1" if there is an interrupt.
Thus, any interrupts may be selectively enabled by
loading the mask register.
This mode is useful if there is a routine command com·
mon to several levels so that the INiA sequence is not
needed (saves ROM space). Another application is to
use the poll mode to expand the number of priority
levels to more than 64.
The special Mask Mode is set by OCW3 where:
SSMM=1, SMM=1, and cleared where SSMM=1,
SMM=O.
lTtM 81T
0", EDGE
08
TO OTHER ,."'OATY CElL.S
CLIII I,ft
1 :.lEVEl
eLA Q
EDGE
ISAIIT
SET
-l-___+_-1-__..(~r-ttt----::=!:::::::-t1 SET ISA
SENSE
~LA~T:=;CH~+-_ _
!'AIORIn
AESOL~ER
CONHIOL
lOGIC
MC8-80,85
MOOE
1f
NON
/linLJ.
"
--+-11>~+----~
MASKED
.EO
f'lIlU[
IAPX 86
MOOE {
'-+--~
-+++--4~
__-+_ _ _ _
INTERNAL
o.r
.... BUS
I~
INTAn
FREEZE,
___
r----NOTES
1. MA'TER CLEAR .... CTlVE ONLY DURING ICW'
fRIEZE/IS .... CTIVE DURING INTiI AND POLL SEQUENCES ONl Y
TRUTH rML£ FOR D·lATCH
c1
•
I
OPE .....TION
0
FOLLOW
Oi
X
HOLD
Figure 9. Priority Cell-Simplified Logic Diagram
8-78
AFN'()()221C
intel'
8259A/8259A-2/8259A-8
READING THE 8259A STATUS
EDGE AND LEVEL TRIGGERED MODES
The input status of several internal registers can be read to
update the user information on the system. The following
registers can be read via OCW3 (IRR and ISR or OCW1
[IMRl).
This mode is programmed using bit 3 in ICW1.
If LTIM = '0', an interrupt request will be recognized by a
low to high transition on an IR input. The IR input can remain high without generating another interrupt.
Interrupt Request Register (IRR): 8-bit register which contains the levels requesting an interrupt to be acknowledged. The highest request level is reset from the IRR
when an interrupt is acknowledged. (Not affected by IMR.)
If LTIM = '1', an interrupt request will be recognized bya
'high' level on IR Input, and there is no need for an edge
detection. The interrupt request must be removed before
the EOI command is issued orthe CPU interrupt is enabled
to prevent a second interrupt from occurring.
In-Service Register(lSR): 8-bit register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command is issued.
The priority cell diagram shows a conceptual circuit of the
level sensitive and edge sensitive input circuitry of the
8259A. Be sure to note that the request latch is a transparent D type latch.
Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.
The IRR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 0.)
In both the edge and level triggered modes the IR inputs
must remain high until after the falling edge of the first
INTA. If the IR input goes low before this time a DEFAULT
IR7 will occur when the CPU acknowledges the interrupt.
This can be a useful safeguard for detecting interrupts
caused by spurious noise glitches on the IR inputs. To implement this feature the IR7 routine is used for "clean up"
simply executing a return instruction, thus ignoring the
interrupt. If IR7 is needed for other purposes a default IR7
can still be detected by reading the ISR. A normal IR7
interrupt will set the corresponding ISR bit, a default IR7
won't. If a default IR7 routine occurs during a normallR7
routine, however, the ISR will remain set. In this case it is
necessary to keep track of whether or not the IR7 routine
was previously entered. If another IR7 occurs it is a
default.
The ISR can be read when, prior to the RD pulse, a Read
Register Command is issued with OCW3 (RR = 1, RIS = 1).
There is no need to write an OCW3 before every status
read operation, as long as the status read corresponds
with the previous one; i.e., the 8259A "remembers"
whether the IRR or ISR has been previously selected by
the OCW3. This is not true when poll is used.
After initialization the 8259A is set to IRR.
For reading the IMR, no OCW3 is needed. The output data
bus will contain the IMR whenever RD is active and AO =1
(OCW1).
Polling overrides status read when P = 1, RR = 1 in OCW3.
IR
8086/8088
INT
8080/8085
------l-..J
8086/8088
INTA
-----+------"""'
8080/8085
LATCH'
ARMED
EARliEST IR
CAN BE REMOVED
'EDGE TRIGGERED MODE ONLY
LATCH'
ARMED
Figure 10. IR Triggering Timing Requirements
8-79
AFN.Q()221C
8259A18259A-2/8259A-8
THE SPECIAL FULLY NESTED MODE
mode, whenever the 8259A's .data bus outputs are enabled, the SP/EN output becomes active.
This mode will be used In the case of a big system
where cascading is used, and the priority has to be con·
served within each slave. In this case the fully nested
mode will be programmed to the master (using ICW4).
This mode is similar to the normal nested mode with the
following exceptions:
This modification forces the use of software programming to determine whether the 8259A is. a master or a
slave. Bit 3 in ICW4 programs the buffered mode, and bit
2 In ICW4 determine.s whether it is a master or a slave.
CASCADE MODE
a. When an interrupt request from a certain slave is in
service this s'lave is not locked out from the master's
priority logic and further interrupt requests from
higher prloriiy IR's within the slave will be recognized
by the master and will initiate interrupts to the processor. (In the normal nested mode a slave is masked
out when Its request is in service and no higher
requests from the same slave can be serviced.)
The 8259A can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.
The master controls the slaves through the 31ine cascade
bus . The cascade bus acts like chip selects to the slaves
during the INTA sequence.
In a cascade configuration, the slave interrupt outputs are
connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave to
release the device routine address during bytes 2 and 3 of
INTA. (Byte 2 only for 8086/8088).
b. When exiting the. Interrupt Service routine the software has to check whether the interrupt serviced was
the only onefr()m that slave. This is done by sending
a non-specific End of Interrupt (EOI) command to the
slave and then. reading its In-Servic'e register and
checking 'or zero. If it is empty, a non-specific' EOI
can be sent to the master too. If not, no EOI should be
.sent.
The cascade bus lines are normally. low and will contain
the slave address code from the trailing edge of the first
INTA pulse to the. trailing edge of the .third pulse. Each
8259A in the system mustfollow a separate initialization
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for
the master and once for the corresponding slave. An
address decoder is required to activate the Chip Select
(CS) input of each 8259A. .
..
BUFFERED MODE
When the 8259A .15 used In a large system where bus
driving buffers are required on the data bus and the cascading mode Is used, there exists the problem of enablIng buffers.
The cascade lines of the Master 8259A are activated only
for slave inputs, non slave inputs leave the cascade line
inactive (low).
The buffered mode will structure the 8259A to send an
enable signal on SP/EN to enable the buffers. In this
\
ADDRESS BUS 06J
\
CONTROL BUS
\
INT REO
\
\
DATA BuS !81
-- - - - -- --I-
-
--
-
00-7
G!O
I
-
CAS 1
6
5
• 3
2
6
5
3
2
,....
"0
~
IN'
INTA
SLAVE B
SP/EN7
GIo
cs
CASO
CASO
CAS 1
CAS 1
CAS2
CAS 2
6
5
4
3
2
1
0
6
5
4
3
2
,
0
I 1 1 1 Ill!
1
7
I
00·7
8259A
r-
III
-
I
cs
CASO
I I 1 I• I I
7
- - -
--
!NT
tNTA
8259A
SLAVE A
SPIEN7
---- - -- -
r---'
...
cs
-
r
"0
00-7
INT
INTA
6259A
MASTER
SPIENM7 M6 M5 M4 M3 M2 Ml MO
L1, t1• 1• 31 1 1
1
0
I
INTERRUPT REOUESTS
Figure 11_ Cascading the 8259A
8-80
AFN'()0221C
8259A/8259A·2/8259A·8
ABSOLUTE MAXIMUM RATINGS*
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Ambient Temperature Under Bias ...... -40·Ct085·C
Storage Temperature ......•...•... -65·Cto +150·C
Voltage on Any Pin
with Respect to Ground ............. -0.5V to + 7V
Power Dissipation .........•................ 1 Watt
D.C. CHARACTERISTICS
Symbol
[TA =
o·c to 70·C, Vee
Parameter
= 5V ±10% (8259-A), Vee = 5V ±10% (B259A)]
Min.
-0.5
Max.
Units
Input Low Voltage
0.8
VIH
Input High Voltage
2.0
VOL
V
IOL = 2.2mA
VOH
Output High Voltage
Output High Voltage
Vee+ 0.5V
0.45
V
V
2.4
V
IOH - -400/LA
VOH(lNT)
Interrupt Output High
Voltage
3.5
V
IOH = -100/LA
2.4
V
. IOH - -400/LA
OV,,;;VIN ,,;;Vee
VIL
III
Input Load Current
ILOL
Output Leakage Current
lee
Vee Supply Current
ILiR
IR Input Load Current
CAPACITANCE
10
-10
Test Con\iitions
/LA
/LA
rnA
85
-300
10
0.45V ,,;;VOUT ,,;;Vee
/LA
VIN = 0
/LA
VIN = Vee
(TA = 25·C; vee = GND = OV)
Typ.
Symbol
Parameter
Max.
Unit
C'N
Input Capacitance
10
pF
fc=lMHz
ClIO
110 Capacitance
20
pF
Unmeasured pins returned to Vss
AC. CHARACTERISTICS
Min.
Test Conditions
[TA = O·Cto 70·C, Vee = 5V ±5% (8259A-8), vee = 5V ±10% (8259A)]
. TIMING REQUIREMENTS
Symbol
Parameter
8259A·8
Min.
Max.
8259A
Min.
Max.
8259A·2
Min.
Units
Test Conditions
Max.
TAHRL
AO/CS Setup to RD/INTAI
50
0
0
ns
TRHAX
AO/CS Hold after RDIINTAr
5
0
0
ns
TRLRH
RD Pulse Width
420
235
160
ns
TAHWL
AO/CS Setup to WRI
50
0
0
ns
TWHAX
AO/CS Hold after WRr
20
0
0
ns
TWLWH
WR Pulse Width
400
290
190
ns
TDVWH
Data Setup to WRr
300
240
160
ns
TWHDX
Data Hold after WRr
40
0
0
ns
TJLJH
Interrupt Request Width (Low)
100
100
100
ns
TCVIAL
Cascade Setup to Second or Third
INTAI (Slave Only)
55
55
40
ns
TRHRL
End of RD to Next Command
160
160
160
ns
TWHRL
cnd of WR to Next Command
190
190
190
ns
I
See Note 1
Note: Th,s ,s the low t,me reqUired to clear the ,nput latch ,n the edge triggered Mode.
8-81
AFN·00221C
inter
8259A/8259A-2/8259A-8
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
8259A-8
Parameter
Min.
TRLDV
Dala Valid from RD/INTAj
8259A-2
8259A
Max.
Min.
300
Max.
Min.
Units
Test Conditions
Max.
200
120
ns
C 01 Dala Bus =
100pF
C of Dala Bus
Max text C = 100 pF
Min. test C = 15 pF
TRHDZ
Dala Floal after RD/INTAT
200
100
85
ns
TJHIH
Interrupt Output Delay
400
350
300
ns
TIALCV
Cascade Valid from FirstlNTAj
(Master Only)
565
565
360
ns
C'NT = 100 pF
CCASCADE = 100 pF
10
TRLEL
Enable Active from RD j or INTAj
160
125
100
ns
TRHEH
Enable Inactive from RDT or INTAT
325
150
150
ns
TAHDV
Data Valid from Stable Address
350
200
200
ns
TCVDV
Cascade Valid to Valid Data
300
300
200
ns
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
. >
"=X
2.0
TEST POINTS
0.8
0.45
< )C
2.0
DEVICE
UNDER
TEST
lcL~100PF
-=
0.8
A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC .",. AND 0.45V FDA
A LOGIC "0," TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC r
AND C.SV FOR A LOGIC "0 "
CL= 100pF
CL INCLUDES JIG CAPACITANCE
WAVEFORMS
WRITE
TWLWH
cs
ADDRESS IUS
-
\
TAHWL
-
-
TWHAX
-
J~
)
-TDVWH-
)
DATA IUS
8-82
-TWHDX
(
AFN-00221C
8259A/8259A-2/8259A-8
WAVEFORMS (Continued)
READ/INTA
iiiMNTA - - - - - - - - "
t - - - - - T R L R H - - - - - - t ••_ - - - - - - - - -
TIILEL
TRHAX
a-----""""'\
ADDIIESS BUS
Ao--------'
N"_-- -------
. . ________..J} ------
----~~~l
OTHER TIMING
IIDIJRn-----'"
1----TWHAl---_1
INTA SEQUENCE
IA
INT-------'
INTA------------~
-- -0--
D8----------- __
_TCVIAL
TCYDY
CO.2-_ _ _ _ _ _ _ _ _~---~----L--~~-------~--
TlALCV--.--
NOTES: Interrupt output must remain HIGH at least until leading edge of first INTA.
1. Cycle 1 in iAPX 86, iAPX 88 systems, the Data Bus is not active.
8-83
AFIHlO221C
8282/8283
OCTAL LATCH
•
Address Latch for iAPX 86, 88,
MCS·80®, MCS·85®, MCS·48® Families
•
High Output Drive Capability for
Driving System Data Bus
•
Fully Parallel 8·Bit Data Register and
Buffer
•
Transparent during Active Strobe
•
3·State Outputs
.20·Pin Package with 0.3" Center
•
No Output Low Noise when Entering
or Leaving High Impedance State
The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers_ They can be used to Implement latches, buffers
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of the principal perl ph
eral and input/output functions of a microcomputer system can be implemented with these devices.
-------;
~.
OI5-~
~F
E}~
l_______
DO,
~
010
,
01,
2
01 2
3
01 3
4
DI4
5
015
6
01 6
7
01 7
8
OE
9
D03
Figure 2. Pin Configurations
Figure 1. Logic Diagrams
8-84
inter
8282/8283
Table 1. Pin Description
Pin
FUNCTIONAL DESCRIPTION
Description
STB
STROBE (Input). STB Is an input control
pulse used to strobe data at the data input
pins (Ao-A7) into the data latches. This
signal is active HIGH to admit input data.
The data Is latched at the HlGH to LOW
transition of STB.
OE
OUTPUT ENABLE (Input). OE Is an input
control signal which when active LOW
enables the contents of the data latches
onto the data output pin (Bo-B7)' OE being
Inactive HIGH forces the output buffers to
their high impedance state.
01 0-01 7
DATA INPUT PINS (Input). Data presented
at these pins satisfying setup time requirements when STB is strobed and
latched into the data input latches.
000-00 7
(8282)
00 0'-00 7
(8283)
DATA OUTPUT PINS (Output). When OE is
true, the data In the data latches is presented as Inverted (8283) or non-Inverted
(8282) data onto the data output pins.
The 8282 and 8283 octal latches are 8·bit latches with
3-state output buffers. Data havi ng satisfied the setup
time requirements is latched into the data latches by
strobing the STS line HIGH to LOW. Holding the STe
line in its active HIGH state makes the latches appear
transparent. Data Is presented to the data output pins by
activating the OE input line. When OE is Inactive HIGH
the output buffers are In their high impedance state.
Enabling or disabling the output buffers will not cause
negative-going transients to appear on the data output
bus.
AFN-Q0727C
8282/8283
ABSOLUTE MAXIMUM RATINGS·
-NOTICE: Stresses above those lIsted under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ................. 0 DC to 70 DC
Storage Temperature ............. -65 DC to + 150 DC
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages ................ , . - 1.0V to + 5.5V
Power Dissipation .......................... 1 Watt
D_C. CHARACTERISTICS
Symbol
(Vee = 5V ±10%, TA = O°C to 70°C)
Parameter
Max.
Units
Vc
Input Clamp Voltage
-1
V
Icc
Power Supply Current
160
mA
IF
Forward Input Current
-0.2
mA
VF = 0.45V
IR
Reverse Input Current
50
,..A
V R = 5.25V
VOL
Output Low Voltage
.45
V
IOL = 32 mA
VOH
Output High Voltage
IOFF
Output Off Current
VIL
Input Low Voltage
V IH
Input High Voltage
C IN
Min.
2.4
V
± 50
,..A
O.B
V
2.0
IOH = -5 mA
V OFF = 0.45 to 5.25V
V
Input Capacitance
12
Test Conditions
Ie = -5mA
Vee= 5.0V
See Note t
Vee= 5.0V
See Note 1
F= 1 MHz
V SIAS =2.5V, Vee=5V
TA=25°C
pF
NOTE:
1. Output Loading IOL=32mA, 10H= -5mA, eL=300pF.
A.C. CHARACTERISTICS
Symbol
TIVOV
TSHOV
(Vee = 5V ±10%, TA = O°C to 70°C
Loading: Outputs -IOL = 32 mA, IOH = -5 mA, CL = 300 pF)
Min.
Max.
Units
Input to Output Delay
-Inverting
-Non-Inverting
Parameter
5
5
22
30
ns
ns
STB to Output Delay
-Inverting
-Non-Inverting
10
10
40
45
ns
ns
Test Conditions
(See Note 1)
TEHOZ
Output Disable Time
5
18
ns
TELOV
Output Enable Time
10
30
ns
TIVSL
Input to STB Setup Time
0
ns
TSLIX
Input to STB Hold Time
25
ns
TSHSL
STB High Time
15
ns
TILlH, TOLOH
Input, Output Rise Time
20
ns
From O.BV tq 2.0V
TIHIL, TOHOL
Input, Output Fall Time
12
ns
From 2.0V to O.BV
NOTE:
1. See waveforms and test load circuit on following page.
8-86
AFN.Q()727C
8282/8283
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUTIOUTPUT
A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC ..,.. AND 0.45V FOR
A LOGIC ··0:· TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A
LOGIC .,',. AND "0:'
OUTPUT TEST LOAD CIRCUITS
1.5V
1.SV
3312
OUT 0-----
I300PF
3-STATE TO VOL
2.14V
18012
OUT 0-----
I
OUT 0 - -
300PF
3-STATE TO VOH
B-87
52.712
SWITCHING
AFN.(J()727C
inter
8282/8283
WAVEFORMS
\11
/1\
INPUTS
\11
)1\
! - - - T l V S L -I*TSLIX.
STB
,I
\
TSHSL~I\
-.l
II
...
-
E
f\
-'~~I-VOH-.1V
I*TlVOV-
\V
OUTPUTS
\
/
. ..
m~-
1>-------
~f\
. .
.
VOL +.1V
SEE NOTE 1
-TSHOV-
NOTE: 1.8283 ONLY -
OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED.
50
50
8282
8283
40
&l--+----1-1 D
Q
D
Q
EFI
(TO OTHER 8284As)
Figure 3. CSYNC Synchronization
8-92
AFN.Q1472B
8284A
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute- maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O·C to 70·C
Storage Temperature .............. -65·C to +150·C
All Output and Supply Voltages ......... -0.5V to + 7V
All Input Voltages ................... -1.0V to +5.5V
Power Dissipation .......................... 1 Watt
DC CHARACTERISTICS (TA-O·C
to 70'C , Vcc-5V±
10%)
Max.
Units
Test Conditions
IF
Forward Input Current (ASYNC)
Other Inputs
-1.3
-0.5
rnA
rnA
VF =0.45V
VF =0.45V
IR
Reverse Input Current (ASYNC)
Other Inputs
50
50
p.A
p.A
VR= Vcc
VR=5.25V
Vc
Input Forward Clamp Voltage
-1.0
V
Ic= -5mA
Icc
Power Supply Current
162
rnA
V,L
Input lOW Voltage
0.8
V
V,H
Input HIGH Voltage
2.0
V
V'HR
Reset Input HIGH Voltage
2.6
V
VOL
Output lOW Voltage
V
5mA
VOH
Output HIGH Voltage ClK
Other Outputs
4
2.4
V
V
-1mA
RES Input Hysteresis
0.25
V
Symbol
V'HR- V'LR
Parameter
Min.
0.45
~1mA
A.C. CHARACTERISTICS (TA=O·C to 70·C, Vcc=5V± 10%)
TIMING REQUIREMENTS
Symbol
Parameter
tEHEL
External Frequency HIGH Time
tELEH
External Frequency lOW Time
tELEL
EFI Period
Min.
Max.
Units
Test Conditions
13
ns
13
ns
10%-10% V,N
tEHEL + tELEH + d
ns
(Note 1)
XTAl Frequency
12
30
90%-90% V,N
MHz
t R1VCL
RDY1, RDY2 Active Setup to ClK
35
ns
ASYNC= HIGH
tR1VCH
RDY1, RDY2 Active Setup to ClK
35
ns
ASYNC=lOW
t R1VCL
RDY1, RDY2 Inactive Setup to ClK
35
ns
tCLR1X
RDY1, RDY2 Hold to ClK
0
ns
tAYVCL
ASYNC Setup to ClK
50
ns
tCLAYX
ASYNC Hold to ClK
0
ns
tA1VR1V
AEN1, AEN2 Setup to RDY1, RDY2
15
ns
tCLA1X
AEN1, AEN2 Hold to ClK
0
ns
t YHEH
CSYNC Setup to EFI
20
ns
tEHYL
CSYNC Hold to EFI
20
ns
tYHYL
CSYNC Width
2' tELEL
ns
t'1HCL
RES Setup to ClK
65
ns
(Note 2)
tCLl1H
RES Hold to ClK
20
ns
(Note 2)
t'LiH
Input Rise Time
20
tlLlL
Input Fall Time
12
8-93
ns
From 0.8V to 2.0V
ns
From 2.0V to O.BV
AFN·01472B
8284A
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Parameter
t CLCL
ClK Cycle Period
tCHCL
Min.
Max.
Units
Test Conditions
100
ns
ClK HIGH Time
(Y3 t cLc Ll+2 for ClK Freq ... B MHz
(V:! tCLcLl+6 for ClK Freq.=10 MHz
ns
Fig. 7 & Fig. B
tCLCH
ClK lOW Time
(% tCLcLl-15 for ClK Freq ...B MHz
(% tCLcL)-14 for ClK Freq.=10 MHz
ns
Fig. 7 & Fig. B
tCH1CH2
tCL2CLl
ClK Rise or Fall Time
ns
1.0V to 3.5V
tpHPL
PClK HIGH Time
tCLCL-20
ns
tpLPH
PClK lOW Time
tCLCL -20
ns
tRYLCL
Ready Inactive to ClK (See Note 4)
-B
ns
Fig. 9 & Fig. 10
tRYHCH
Ready Active to ClK (See Note 3)
(% tCLcLl-15 for ClK Freq ... B MHz
(% tCLcLl-14 for ClK Freq.=10 MHz
ns
Fig. 9 & Fig. 10
tCLlL
ClK to Reset Delay
40
ns
t CLPH
ClK to PClK HIGH DELAY
22
ns
10
22
ns
22
ns
tCLPL
ClK to PClK lOW Delay
tOLC";
OSC to ClK HIGH Delay
-5
t OLCL
OSC to ClK lOW Delay
2
35
ns
tOLOH
Output Rise Time (except ClK)
20
ns
From O.BV to 2.0V
tOHOL
Output Fall Time (except ClK)
12
ns
From 2.0V to O.BV
NOTES:
1. 0= EFI rise (5ns max) + EFI fall (5ns max).
2. Setup and hold necessary only to guarantee recognition at next clock.
3. Applies only to T3 and TW states.
4. Applies only to T2 states.
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD ClflCUIT
INPUT/OUTPUT
. . . Vl =2.0BV
~L
DEVICE
UNDER
TEST
'" 325n
i-----
I-=
A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND O,4SV FOR
CL
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 1.SV FOR BOTH A
LOGIC ''1'' AND "0."
CL = l00pF FOR ClK
CL= 30pF FOR READY
8-94
AFN·014728
8284A
WAVEFORMS
CLOCKS AND RESET SIGNALS
NAME
EFI
OSC
ClK
0
PClK
0
CSYNC
I
RESET
0
____~/~--------~~t
NOTE: All TIMING MEASUREMENTS ARE MADE AT 1.5 VOLTS, UNLESS OTHERWISE NOTED.
READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
ClK
tR1VCL
RDY1,2
READY
tRYHCH
8-95
AFN-01472B
8284A
WAVEFORMS (Continued)
READY SIGNALS (FOR SYNCHRONOUS DEVICES)
elK
tR1VCL
RDY1,2
tCLR1X
READY
IRYHCH
X1
tRYLCL
I
I
ClK
24MHZ$
lOAD
(SEE NOTE 1)
I
X2
R2
-
F/C
1
CSYNC
j.
-
R1 = R2 = 5100.
Clock High and Low Time (Using X1, X2)
..
I
PULSE
GENERATOR
I
I
EFI
L
ClK
I
I
lOAD
(SEE NOTE 1)
I
V
.r-
F/C
CSYNC
Clock High and Low Time (Using EFI)
8-96
AFN-01472B
intJ
8284A
Vcc
AEm
ClK 1-----1
,-------------,------t X1
READY 1----1
24MHz CJ
r---;=======~~--1X2
1------1 RDY2
OSC
Fie
AEN2
CSYNC
R, - R2 - 510fl.
Ready to Clock (Using X1, X2)
ClK 1----1
t--1~--tEFI
Fie
PULSE
GENERATOR
AEN1
1 - - - - t RDY2
AEN2
CSYNC READY'I----I
NOTES:
Ready to Clock (Using EFI)
',CL=l00pF
2. CL-30pF
8-97
AFN-01472B
M8284
CLOCK GENERATOR AND DRIVER
FOR MILITARY iAPX 86
MILITARY
• Military Temperature Range:
- 55°C to + 125°C
• 18·Pin Package
• Generates System Reset Output
from Schmitt Trigger Input
• Generates the System Clock for the
M8D8S
• Provides Local Ready and
MULTIBUS™ Ready Synchronization
• Uses a Crystal or TTL Signal for
Frequency Source
• Capable of Clock Synchronization
with other M8284's
• Single +5V Power Supply
The M8284 is a bipolar clock generator/driver designed to provide clock signals for the Military iAPX 86 and peripherals. It
also contains READY logic for operation with two MULTIBUS™ systems and provides the processors required READY
synchronization and timing. Reset logic with hysteresis and synchronization is also provided.
CSYNC
VCC
X1
x,
ose
PClK
X1
AEN1
X2
RDY1
N.C.
READY
EFI
RDY2
Fie
AEN2
OSC
ClK
RES
GND
RESET
eLK
Fie
EFI
PCLK
CSYNC
eK
RDY1
AEN1
READY
AEN2
RDY2
Figure 1. Block Diagram
X11
X21
Fie
EFI
CSYNC
ROY' 1
RDY2 I
AEN11
AEN21
Figure 2. Pin Configuration
CONNECTIONS FOR CRYSTAL
CLOCK SOURCE SELECT
EXTERNAL CLOCK INPUT
CLOCK SYNCHRONIZATION INPUT
REAOY SIGNAL FROM TWO MUlTIBUS™ SYSTEMS
ADDRESS ENABLED QUALIFIERS FOR RDY1.2
RES
RESET
OSC
CLK
PCLK
READY
VCC
GND
M8284 Pin Names
8-98
RESET INPUT
SYNCHRONIZED RESET OUTPUT
OSCILLATOR OUTPUT
MOS CLOCK 108086
TTL CLOCK FOR PERIPHERALS
SYNCHRONIZED READY OUTPUT
+ 5 VOLTS
o VOLTS
inter
18284
CLOCK GENERATOR AND DRIVER
FOR iAPX 86, 88 PROCESSORS
INDUSTRIAL
Temperature Range:
• Industrial
-40°C to +85°C
the System Clock for the
• Generates
Industrial iAPX
Uses a Crystal or a TTL Signal for
• Frequency
Source
• Single +5V Power Supply
• 18·Pin Package
System Reset Output from
• Generates
Schmitt Trigger Input
Provides Local Ready and MULTIBUS™
• Ready
Synchronization
Capable of Clock Synchronization with
• other
8284's
86/10
The 18284 is a bipolar clock generator/driver designed to provide clock signals for the iAPX 86, 88 and peripherals. It
also contains READY logic for operation with two MULTIBUS™ systems and provides the processors required READY
synchronization and timing. Reset logic with hysteresis and synchronization is also provided.
CSYNC
VCC
X1
x,
osc
PClK
X1
ClK
AEN1
X2
RDY1
N.C.
READY
EFI
RDY2
FIe
AEN2
ClK
asc
RES
Fie
EFI
PCLK
CSYNC
ROY1
AEN1
AeN2
RDY2
~
CK
READY
[>"==0
GND
Figure 1. Block Diagram
X'I
X21
Fie
EFI
CSYNC
ROY' I
RDY2 I
AEN1 I
AEN21
RESET
Figure 2. Pin Configuration
RES
CONNECTIONS FOR CRYSTAL
VCC
RESET INPUT
SYNCHRONIZED RESET OUTPUT
OSCILLATOR OUTPUT
MOS CLOCK 108086
TTL CLOCK FOR PERIPHERALS
SYNCHRONIZED READY OUTPUT
+5 VOLTS
GND
o VOLTS
REser
CLOCK SOURCE SELECT
EXTERNAL CLOCK INPUT
CLOCK SYNCHRONIZATION INPUT
READY SIGNAL FROM TWO MULTIBUS™ SYSTEMS
ADDRESS ENABLED QUALIFIERS FOR RDY1.2
18284 Pin Names
8-99
OSC
CLK
PCLK
READY
18286/8287
OCTAL BUS TRANSCEIVER
INDUSTRIAL
•
Data Bus Buffer Driver for iAPX 86,88,
MCS-80®, MCS-85®, and MCS-48®
Families
•
High Output Drive Capability for
Driving System Data Bus
•
Fully Parallel 8-Bit Transceivers
•
3-State Outputs
•
20-Pin Package with 0_3" Center
•
No Output Low Noise when Entering
or Leaving High Impedance State
•
Industrial Temperature Range:
-40°C to +85°C
The 18286 and 18287 are 8·bit bipolar transceivers with 3·state outputs. The 18287 Inverts the input data at its outputs
while the 18286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.
18286
18287
r-------l
r-------l
I
I
I
I
I
I
I
I
Figure 2. Pin Configuration
Figure 1. Logic Diagrams
8-100
8288
BUS CONTROLLER
FOR iAPX 86, 88 PROCESSORS
•
Bipolar Drive Capability
•
3-State Command Output Drivers
•
Provides Advanced Commands
•
Configurable for Use with an 110 Bus
•
Provides Wide Flexibility in System
Configurations
•
Facilitates Interface to One or Two
Multi-Master Busses
The Intellll> 8288 Bus Controller is a 20-pin bipolar component for use with medium-to-Iarge iAPX 86, BB processing
systems. rhe bus controller provides command and control timing generation as well as bipolar bus drive capability while
optimizing system performance.
.
.
A strapping option on the bus controller configures it for use with a multi-master system bus and separate I/O bus.
MRDC
8086
STATUS
ISo~-
_
STATUS
DECODER
S2 - - - :
lOB
- . MWTC
COM·
MAND
SIGNAL
GENER·
ATOR
AMWC
10RC
10WC
MULTIBUS™
COMMAND
SIGNALS
AIOWC
iNTA
CONTROL
INPUT
r
LK
liEN- NCE
CONTROL
LOGIC
CONTROL
SIGNAL
GENER·
ATOR
10B-
+5V
LATCH, DATA
DTIR
}ADDRESS
'
DEN
TRANSCEIVER, AND
MCEiPDEN INTERRUPT CONTROL
SIGNALS
ALE
.
51
VCC
So
52
MCElPDEN
ALE
DEN
AEN
CEN
MRDC
INTA
AMWC
10RC
MWTC
GND
AIOWC
10WC
GND
Figure 1. Block Diagram
8-101
Figure 2.
Pin Configuration
~1504B
8288
Table 1. Pin Description
Symbol
Type
GND
5 0 ,5,,52
Status Input Pins: These pi ns are the
status input pins from the 8086, 8088 or
8089 processors. The 8288 decodes these
inputs to generate command and control
signals at the appropriate time. When
these pins are not in use (passive) they are
all HIGH. (See chart under Command and
Control Logic.)
Clock: This is a clock signal from the
8284 clock g!lnerator and serves to establish when command and control signals
are generated.
ALE
0
Address Latch Enable: This signal
serves to strobe an address into the
address latches. This signal is active HIGH
and latching occurs on the falling (HIGH
to LOW) transition. ALE is intended for
use with transparent D type latches.
DEN
0
Data Enable: This signal serves to enable data transceivers onto either the
local or system data bus. This signal is
active HIGH.
DT/R
0
Data Transmit/Receive: This signal establishes the direction of data flow
through the transceivers. A HIGH on this
line indicates Transmit (write to I/O or
memory) and a LOW indicates Receive
(Read).
AEN
Type
I
Address Enable: AEN enables command
outputs of the 8288 Bus Controller at least
115 ns after it becomes active (LOW). AEN
going inactive immediately 3-states the
command output drivers. AEN does not
affect the I/O command lines if the 8288 is
in the I/O Bus mode (lOB tied HIGH).
CEN
I
Command Enable: When this signal is
LOW all 8288 command outputs and the
DEN and PDEN control outputs are forced
to their inactive state. When this signal is
HIGH, these same outputs are enabled.
lOB
I
Input/Output Bus Mode: When the lOB is
strapped HIGH the 8288 functions in the
I/O Bus mode. When it is strapped LOW,
the 8288 functions in the System Bus
mode. (See sections on I/O Bus·and System Bus modes).
8-102
Name and Function
AIOWC
0
Advanced I/O Write Command: The
AIOWC issues an I/O Write Command
earlier in the machine cycle to give I/O
devices an early indication of a write instruction. Its timing is the same as a read
command signal. AIOWC is active LOW.
10WC
0
I/O Write Command: This command line
instructs an I/O device to read the data on
the data bus. This signal is active LOW.
10RC
0
I/O Read Command: This command line
instructs an I/O device to drive its data
onto the data bus. This Signal is active
LOW.
AMWC
0
Advanced Memory Write Command: The AMWC issues a memory write
command earlier in the machine cycle to
give memory devices an early indication
of a write instruction. Its timing is the
same as a read command signal. AMWC is
active LOW.
MWTC
0
Memory Write Command: This command line instructs the memory to record
the data present on the data bus. This
signal is active LOW.
MRDC
0
Memory Read Command: This command line instructs the memory to drive
its data onto the data bus. This signal is
active LOW.
INTA
0
Interrupt Acknowledge: This command
line tells an interrupting device that its
interrupt has been acknowledged and
that it should drive vectoring information
onto the data bus. This signal is active
LOW.
MCE/PDEN
0
This is a dual function pin.
MCE (lOB Is tied LOW): Master Cascade
Enable occurs during an interrupt sequence and serves to read a Cascade
Address from a master PIC (Priority Interrupt Controller) onto the data bus. The
MCE signal is active HIGH.
PDEN (lOB Is tied HIGH): Peripheral
Data Enable enables the data bus transceiver for the I/O bus that DEN performs
for the system bus. PDEN is active LOW.
..
Ground.
I
I·
CLK
Symbol
Name and Function
Power: +5V supply.
Vcc
AFN-ol504B
intel'
8288
FUNCTIONAL DESCRIPTION
Command and Control Logic
The command logic decodes the three 8086, 8088 or 8089
CPU status lines (So, S1, S2l to determine what command
is to be issued,
This chart shows the meaning of each status "word".
s;
~
SO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 Interrupt Acknowledge
1 Read 110 Port
0 Write 110 Port
1 Halt
0 Code Access
1 Read Memory
0 Write Memory
1 Passive
Processor State
8288Command
INTA
10RC
10WC,AIOWC
None
MRDC
MRDC
MWTC,AMWC
None
The command is issued in one of two ways dependent
on the mode of the 8288 Bus Controller.
110 Bus Mode - The 8288 is in the 110 Bus mode if the
lOB pin is strapped HIGH. In the 110 Bus mode all 110
command lines (IORC, 10WC, AIOWC, INTA) are always
enabled (i.e., not dependent on AEN). When an 110 com·
mand is initiated by the processor, the 8288 immediately
activates the command lines using PDEN and DT/R to
control the I/O bus transceiver. The 110 command lines
should not be used to control the system bus in this
configuration because no arbitration is present. This
mode allows one 8288 Bus Controller to handle two ex·
ternal busses. No waiting is involved when the CPU
wants to gain access to the I/O bus. Normal memory ac·
cess requires a "Bus Ready" signal (AEN LOW) before it
will proceed. It is advantageous to use the lOB mode if
I/O or peripherals dedicated to one processor exist in a
multi·processor system.
System Bus Mode - The 8288 is in the System Bus mode
if the lOB pin is strapped LOW. In this mode no command
is issued until 115 ns after the AEN Line is activated
(LOW). This mode assumes bus arbitration logic will in·
form the bus controller (on the AEN line) when the bus is
free for use. Both memory and I/O commands wait for bus
arbitration. This mode is used when only one bus exists.
Here, both I/O and memory are shared by more than one
processor.
COMMAND OUTPUTS
The advanced write commands are made available to in·
itiate write procedures early in the machine cycle. This
signal can be used to prevent the processor from enter·
ing an unnecessary wait state.
The command outputs are:
MRDC
MWTC
10RC
10WC
AMWC
AIOWC
INTA
-
Memory Read Command
Memory Write Command
I/O Read Command
I/O Write Command
Advanced Memory Write Command
Advanced I/O Write Command
Interrupt Acknowledge
INTA (Interrupt Acknowledge) acts as an I/O read during
an interrupt cycle. Its purpose is to inform an inter·
rupting device that its interrupt is being acknowledged
and that it should place vectoring information onto the
data bus.
CONTROL OUTPUTS
The control outputs of the 8288 are Data Enable (DEN),
Data Transmit/Receive (DT/R) and Master Cascade
Enable/Peripheral Data Enable (MCE/PDEN). The DEN
signal determines when the external bus should be
enabled onto the local bus and the DT/R determines the
direction of data transfer. These two signals usually go
to the chip select and direction pins of a transceiver.
The MCE/PDEN pin changes function with the two
modes of the 8288. When the 8288 is in the lOB mode
(lOB HIGH) the PDEN Signal serves as a dedicated data
enable signal for the I/O or Peripheral System bus.
INTERRUPT ACKNOWLEDGE AND MCE
The MCE signal is used during an interrupt acknowl·
edge cycle if the 8288 is in the System Bus mode (lOB
LOW). During any interrupt sequence there are two inter·
rupt acknowledge cycles that occur back to back. Our·
ing the first interrupt cycle no data or address transfers
take place. Logic should be provided to mask off MCE
during this cycle. Just before the second cycle begins
the MCE signal gates a master Priority Interrupt Con·
troller's (PIC) cascade address onto the processor's
local bus where ALE (Address Latch Enable) strobes it
into the address latches. On the leading edge of the
second interrupt cycle the addressed slave PIC gates an
interrupt vector onto the system data bus where it is
read by the processor.
If the system contains only one PIC, the MCE signal is
not used. In this case the second Interrupt Acknowledge
signal gates the interrupt vector onto the processor bus.
ADDRESS LATCH ENABLE AND HALT
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
~d~ss latches. ALE also serves to strobe the status (SQ,
SI, S2l into a latch for halt state decoding.
COMMAND ENABLE
The Command Enable (CEN) input acts as a command
qualifier for the 8288. If the CEN pin is high the 8288
functions normally. If the CEN pin is pulled LOW, all
command lines are held in their inactive state (not
3·state). This feature can be used to implement memory
partitioning and to eliminate address conflicts between
system bus devices and resident bus devices,
8-103
AFN'()l504B
intel"
8288
ABSOLUTE MAXIMUM RATINGS*
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias .................. O'C to 70'C
Storage Temperature ............... -6S'C to +1S0'C
All Output and Supply Voltages ......... -O.SV to + 7V
All Input Veltages .................... -1.0V te +S.SV
Power Dissipatien ........................... 1.S Watt
D.C. CHARACTERISTICS (Vee =
Symbol
SV ± 10%, TA = O'C te 70°C)
Parameter
Min.
Max.
Unit
Ve
Input Clamp Veltage
-1
V
lee
IF
Pewer Supply Current
230
mA
Ferward Input Current
-0.7
mA
VF = O.4SV
IR
Reverse Input Current.
SO
/LA
VR = Vee
VeL
Output lew Veltage
Cemmand Outputs
Centrel Outputs
O.S
O.S
V
V
leL
leL
= 32 mA
= 16 mA
V
V
. leH
leH
= -S mA
= -1 mA
VeH
Output High Veltage
Cemmand Outputs
Centrel Outputs
V1L
V1H
Input lew Veltage
leFF
Output Off Current
2.4
2.4
Input High Veltage
A.C. CHARACTERISTICS
(Vec=
0.8
V
100
/LA
2.0
sv ±
Test Conditions
Ie
= -S mA
V
. VeFF
= 0.4 te S.2SV
10%, TA = O'C te 70'C)
TIMING REQUIREMENTS
Symbol
Parameter
TClCl
ClK Cycle Peried
TClCH
TCHCl
Min.
Max.
Unit
Test Conditions
100
ns
ClK lew Time
SO
ns
ClK High Time
30
ns
TSVCH
Status Active Setup Time
3S
ns
TCHSV
Status Active Held Time
10
ns
TSHCl
Status Inactive Setup Time
3S
ns
TClSH
Status Inactive Held Time
10
TILIH
Input, Rise Time
20
ns
Frem 0.8V to 2.0V
TIHll
Input, Fall Time
12
ns
Frem 2.0V te 0.8V
8-104
ns
AFN·01504B
8288
A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Min.
Parameter
TCVNV
Control Active Delay
Max.
Unit
5
45
n5
10
Test Conditions
TCVNX
Control Inactive Delay
45
ns
TCLLH,
TCLMCH
ALE MCE Active Delay (from CLK)
20
ns
ALE MCE Active Delay (from
Status)
20
ns
4
15
ns
MRDC
IORC
TSVLH,
. TSVMCH
ALE Inactive Delay
TCHLL
,
TCLML
Command Active Delay
10
35
ns
TCLMH
Command Inactive Delay
10
35
ns
MWTC
TCHDTL
Direction Control Active Delay
50
ns
IOWC
IOH
TCHDTH
Direction Control Inactive Delay
30
ns
INTA
CL
= -5 mA
= 300 pF
TAELCH
Command Enable Time
40
ns
AMWC
TAEHCZ
Command Disable Time
40
ns
AiOWC
10L
= 16 mA
TAELCV
Enable Delay Time
IOL == 32 mA
'I
200
ns
AENto DEN
20
CEN to DEN, PDEN
25
ns
ns
TCELRH
TOLOH
CEN to Command
Output, Rise Time
TCLML
20
ns
. ns
From 0.8V to 2.0V
TOHOL
Output, Fall Time
ns
From 2.0V to O.8V
TAEVNV
. TCEVNV
115
12
Oth"
10H = -1 mA
CL = 80 pF
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT
A.C. TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC "1" AND OASV FOR
A LOGIC "0," THE CLOCK IS DRIVEN AT 4.3V AND 0.25v' TIMING MEASURE-
MENTS ARE MADE AT 1.SV FOR BOTH A LOGIC ·'1" AND "0:·
TEST LOAD CIRCUITS-3·STATE COMMAND OUTPUT TEST LOAD
1.SV
1.SV
oo'~'·'
I
oo,~~
300 pF
1300 PF
3·STATE TO HIGH
3·STATE TO LOW
2.28V
2.14V
.
·lS2.72
OUT~
.~
r300PF
COMMAND OUTPUT
TEST LOAD
B-1 05
oo'~"·
.
r~PF
CONTROL OUTPUT
TEST LOAD
AFN.()1504B
inter
8288
WAVEFORMS
STATE
CLK
_TO- _T,
n
/
-TCLCH-
1\
I-
TCHSV-
T,
I----'- TCLCLR
-
I
L-.I
-
TSVCH
- T3
\
- ~y
I
n
\
X
rl
ADDRESS/DATA
ADDR
VALID
WRITE
rr.
TCLLH_
DATA VALID
CD
I -TCHLL
TSVLH
ALE
-
r-TCLMH
\
\
--.
I
--.
-TCLML
I
1\
-
~
~TCVNV
V
)
)
v
i--TCLML
\
\
j
\
-
TCVNX-
\
)
)
1\
I
1--.
TCVNV-
V
DEN (WRITE)
\
J
r\
--.
V
\
--_.-
TCHDTH-
MCE
~TCVNX
\
PDEN (WRITE)
DTIR(READ)
(INTA)
~
TSHCL
TCLS~
\
1\
LF
--
h
TCHCL-
TO-
----
.t::
IJ
-
If l@
TCLMCH-
1--
I
1
LTSVMCH"
TCHOTL
\
TCHDTHr-TCVNX
l
..,.,.
1. ADDAES8IDATA BUS IS SHOWN ONLY FOR REFERENCE PURPOSES.
2. LEADING EDGE ~ ALE AND MeE IS DETERMINED BY THE FAWNG EDGE OF CLK OR STATUS GOINO ACTIVE, WHICHEVER OCCURS LAST.
3. ALL nY.NO MEASUREMENTS NlE MADE AT 1.5V UNLESS SPECIFIED OTHERWISE.
B~106
AFN-QI504B
inter
8288
WAVEFORMS (Continued)
DEN, PDEN QUALIFICATION TIMING
\V
CEN
/1\
V
J\
AEN
-TAEVNV-
\V
DEN
\I
/\
jl~
-TCEVNV_
\I
/\
PDEN
ADDRESS ENABLE (AEN) TIMING (3-STATE ENABLE/DISABLE)
\-'.5-V -TAELCV~
1.5V
\~------1---------~
TAELCHt
OUTPUT _ _ _ _ _ _ _ _ _ _ _ _
IITAEHCZ
~I
o·i v
~
VOH
VOH
---'J,r-~'--.-t-\----""T"1V....---.,,"\:,'---...::--- t - - - - - - -
ro~~
/~
/
-TCELRH
V
CEN---------------;T:;:;CE::;-l;;;RH~_1
\
,\
NOTE: CEN must be low or valid prior to T2 to prevent the command from being generated.
8-107
AfN-Ol504B
18288
BUS CONTROLLER
FOR iAPX 86, 88 PROCESSORS
INDUSTRIAL
•
•
•
•
•
Bipolar Drive Capability
•
3·State Command Output Drivers
Provides Advanced Commands
Provides Wide Flexibility in System
Configurations
•
Configurable for Use with an 1/0 Bus
Facilitates Interface to One or Two
Multi·Master Busses
Industrial Temperature Range:
- 40°C to 85°C
The Intel® 18288 Bus Controller is a 20-pin bipolar component for use with medium-to-Iarge iAPX 86 processing
systems. The bus controller provides command and control timing generation as well as bipolar bus drive capability
while optimizing system performance.
A strapping option on the bus controller configures it for use with a multi-master system bus and separate 1/0 bus.
lOB
VCC
ClK
so
51
52
DT/R
/50-
8086
STATUS \
-
~--
STATUS
DECODEA
52--·...
MRDC
--- .. MWTC
COM·
MAND
SIGNAL
GENER·
AIDR
AM we
10RC
rowe
1
MUlTIBUSTM
J COMMAND
SIGNALS
MCE/PDEN
ALE
DEN
AEN
CEN
iiRilC
INTA
AMWC
IORC
MWTC
AIOWC
GND
10WC
AIOWC
Figure 2. Pin Configuration
INTA
I
l
ClK
CONTROL
INPUT
--
AEN--
CONTROL
CEN--
lOGIC
108--
+ 5V
CONTROL
SIGNAL
GENER·
AlDR
eliA
DEN
MCEIPDEN
ALE
l
GND
VCC
ADDRESS LATCH, DATA
TRANSCEIVER, AND
I INTERRUPT CONTROL
SIGNALS
COMMAND
BUS
MWTC
GND
MRDC
Figure 1. Block Diagram
li1288
10RC
INTA
DT/R
ALE
MCElPDEN
: } CONTROL
_
OUTPUT
DEN
Figure 3. Functional Pin·Out
8289
BUS ARBITER
• Provides Multi-Master System Bus
Protocol
• Four Operating Modes for Flexible
System Configuration
• Synchronizes iAPX 86, 88 Processors
with Multi-Master Bus
• Compatible with Intel Bus Standard
MULTIBUS™
• Provides Simple Interface with 8288
Bus Controller
• Provides System Bus Arbitration for
8089 lOP in Remote Mode
The Intel 8289 Bus Arbiter is a 20-pin, 5-volt-only bipolar component for use with medium to large iAPX 86, 88 multimaster/multiprocessing systems. The 8289 provides system bus arbitration for systems with multiple bus masters, such as
an 8086 CPU with 8089 lOP in its REMOTE mode, while providing bipolar buffering and drive capability.
~
I
80881808818088 {
STATUS
PROCESSOR
CONTROL
BCLK
BREa
BPRN
iNiT
BPRO
SO
BUSY
CBRa
CR~~~~
RESB
ANYRaST
lOB
I
MULTIBUSTM
COMMANO
SIGNALS
.
}
AEN
-L~::::::!~~=~~~~~J- SYSB/RHIi
.
SYSTEM
SIGNALS
+5V
Figure 1. Block Diagram
VCC
GND
VCC
51
So
-INIT
RESB
CLK
-iiCLK
iiCLK
iliff
[ljCi(
BREa
ilJIMCK
ANYRaST
CONTROU
STRAPPING
OPTIONS
Am'
CiRQ"
GND
BUSY
Figure 2. Pin Diagram
-
--
LOCK
8288
CLK
CRQLCKi
RESB
!
ANYRast
~
iiPiiN
Bl'RO
IlmV
MULTIBUS
INTERFACE
SYSB/l!ED } SYSTEM
AEIiI
SIGNALS
Figure 3. Functional Pinout
8-109
inter
8289
Table 1. Pin Description
Symbol
Power: +5V supply ±10%.
GND
Type
Name end Function
AEN
0
Address Enable: The output of the 8289
Arbiter to the processor's address latc~es,
to the 8288 Bus Controller and 8284A
Clock Generator. AEJij serves to instruct the
Bus Controller and address latches when
to tri-stat.e their output drivers.'
SYSBI
RESB
I
System Busl.Resldent Bus: An Input
signal when the arbiter is configured in the
S.R. Mode (RESB is strapped high) which
determines when the mUlti-master system
bus is requested and mUlti-master system
bus surrendering is permitted. The Signal
Is Intended. to originate from a ·form of
address-mapping circuitry, as a decoder or
PROM attached to the resident address
bus. Signal transitions and glitches are
permitted on this pin from.p1 of T4 to.p 1 of
T2 of the processor cycle. During the
periodfrom.p1 ofT2to.p1 ofT4,onlyciean
transitions are permitted on this pin (no
glitches). If a glitch occurs, the arbiter may
capture or miss it, and the mUlti-master
system bus may be requested or surrendered, depending upon the state of the
glitch. The arbiter requests the multimaster system bus in the S.A. Mode when
the state of the SYSB~ pin is high and
permits the bus to be surrendered when
this pin is low.
CBRO
1/0
Common Bus Request: An input signal
which instructs the arbiter if there are any
other arbiters of lower priority requesting
the use of the mUlti-master system bus.
Ground.
SO,S1,S2
I
Status Input Pins: The status input pins
from an 8086, 8088 or 8089 processor. The
8289 decodes these. pins to Initiete bus request and surrender actions. (See Table 2.)
ClK
I
Clock: From the 8284 clock chip and
serves to establish when bus arbiter actions are Initiated.
lOCK
I
Lock: A processor generated signal which
when activated (low) prevents the arbiter
from surrendering the multi-master system
bus to. any other bus artiter, regardless of
its priority.
CROlCK
I
Common Request Lock: An active low
signal which prevents the arbiter from surrenderingthemulti-master system bus to
any other bus arbiter requesting the bus
through the CBRO input pin.
RESB
I
Resident Bus: A strapping option to configure the arbiter to operate in systems'having both a multi-master system bus and a
Resident Bus. Strapped high, the multimaster system bus is requested or s~
dered as a function of the SYSB/RESB
input pin. Strapped low, the SYSB/RESB
input is ignored.
ANYROST
I
Any Request: A strapping option which
permits the multi-master system bus to be
surrendered to a lower priority arbiter as if
it were an arbiter of higher priority (i.e.,
when a la,wer priority arbiter requests the
use of the mulii-master system bus, the bus
is surrendered as soon as it is possible).
When ANYROST Is strapped low, the bus is
surrendered according to Table 2. If ANYROST is strapped high and CBRO is activated, the bus is surrendered althe end of
the present bus cycle. Strapping CBRO low
and ANYROST high forces the 8289 arbiter
to surrender the mUlti-master system bus
after each transfer cycle. Note that when
surrender occurs BREO is driven false
(high).
lOB
Symbol
Name end Function
lYpe
Vcc
I
The CBRO pins (open-collector output) of
:all the 8289 Bus Arbiters which surrender
to the multi-master system bus upon request are connected together.
The Bus Arbiter running the current transfer cycle will not itself pull the CBRO line
low. Any other arbiter connected to the
CBRO line can request the mUlti-master
system bus. The arbiter presently running
the current transfer cycle drops its BREO
signal and surrenders the bus whenever
the proper surrender conditions exist.
Strapping CBRO low and ANYROST high
allows. the multi-master. system bus to be
surrendered after each transfer cycle. See
the pin definition of ANYROST.
10 Bus: A strapping option which configures the 8289·Arbiter to operate in systems having both an 10 Bus (Peripheral
Bus) and a mUlti-master system bus. The
arbiter requests and surrenders the use of
the mUlti-master system bus as a function
of the status line, 82. The multi-master system bus is permitted to be surrendered
while the processor is performing 10 commands and is requested whenever the processor 'performs a memory' command.
Interrupt cycles are assumed as coming
from. the peripheral bus and are treated as
an 10 command.
INIT
8-110
I
Initialize: An active low multi-master systerT] bus input Signal used to reset all the
bus arbiters on the mUlti-master system
bus. After initialization, no arbiters have
the use of the multi~master system bus.
AFNoOO839C
8289
Table 1. Pin Descriptions (Continued)
Symbol
~pe
Name and Function
BClK
I
Bus Clock: The multi-master system bus
clock to which all multi-master system bus
interface signals are synchronized.
BREQ
0
Bus Request: An active low output signal
in the parallel Priority Resolving Scheme
which the arbiter activates to request the
use of the multi-master system bus.
BPRN
I
Symbol
Bus Priority In: The active low signal returned tothe arbiter to instruct ilthat it may
acquire the mUlti-master system bus on the
next failing edge of BClK. BPRN indicates
to the arbiter that It Is the highest priority
requesting arbiter presently on the bus.
The loss of BPRN instructs the arbiter that
it has lost priority to a higher priority
arbiter.
FUNCTIONAL DESCRIPTION
The 8289 Bus Arbiter operates in conjunction with the
8288 Bus Controller to interface iAPX 86, 88 processors to
a multi-master system bus (both the iAPX 86 and iAPX 88
are configured in their rnax mode). The processor is unaware of the arbiter's existenqe and issues commands as
though it has exclusive use of the system bus. If the processor does not have the use of the multi-master system
bus, the arbiter prevents the Bus Controller (8288), the
data transceivers and the address latches from accessing
the system bus (e.g. all bus driver outputs are forced into
the high impedance state). Since the command sequence
was not issued by the 8288, the system bus will appear as
"Not Ready" and the processor will enter wait states. The
processor will remain in Wait until the Bus Arbiter acquires the use of the multi-master system bus whereupon
the arbiter will allow the bus controller, the data transceivers, and the address latches to access the system. Typically, once the command has been issued and a data
transfer has taken place, a transfer acknowledge (XACK)
is returned to the processor to indicate "READY" from the
accessed slave device. The processor then completes its
transfer cycle. Thus the arbiter serves to multiplex a processor (or bus master) onto a multi-master system bus and
avoid contention problems between bus masters.
Arbitration Between Bus Masters
In general, higher priority masters obtain the bus when a
lower priority master completes Its present transfer
cycle. Lower priority bus masters obtain the bus when a
higher priority master is not accessing the system bus.
A strapping option (ANYRQST) is provided to allow the
arbiter to surrender the bus to a lower priority master as
though it were a master of higher priority. If there are no
other bus masters requesting the bus, the arbiter maintains the bus so long as Its processor has. not entered
~pe
BPRO
0
BUSY
I/O
Name and Function
Bus Priority Out: An active low output
signal used in the serial priority resolving
scheme where BPRO Is daisy-chained to
BPRN of the next lower priority arbiter.
Busy: An active low open collector
mUlti-master system bus interface signal
used to Instruct all the arbiters on the bus
when the multi-master system bus is available. When the multi-master system bus is
available the highest requesting arbiter
(determined by BPRN) seizes the bus and
pulls BUSY low to keep other arbiters off of
the bus. When the arbiter is done with the
bus, it releases the BUSYsignal, permitting
it to go high and thereby allowing another
arbiter to acquire the mUlti-master system
bus.
the HALT State. The arbiter will not voluntarily surrender
the system bus and has to be forced off by another
master's bus request, the HALT State being the only exception. Additional strapping options permit other
modes of operation wherein the multl·master system
bus Is surrendered or requested under different sets of
conditions.
Priority Resolving Techniques
Since there can be many bus masters on a multi·master
system bus, some means of resolving priority between
bus masters simultaneously requesting the bus must be
provided .. The 8289 Bus Arbiter provides several resolv·
Ing techniques. All the techniques are based on a priority concept that at a given time one bus master will have
priority above all the rest. There are provisions for using
parallel priority resolving techniques, serial priority
resolving techniques, and rotating priority techniques.
PARALLEL PRIORITY RESOLVING
The parallel priority resolving technique uses a separate
bus request line (~ for each arbiter on the multi·
master system bus, see Figure 4. Each BREQ line enters
Into a priority encoder which generates the binary ad·
dress of the highest priority BREQ line which Is active.
The binary address Is decoded by a decoder to select
the corresponding BPRN (Bus Priority In) line to be
returned to the highest priority requesting arbiter. The
arbiter receiving priority (BPRN true) then allows its
associated bus master onto the multi·master system
bus as soon as it becomes available (I.e., the bus Is no
longer busy). When one bus arbiter gains priority over
another arbiter It cannot immediately seize the bus, It
must wait until the present bus transaction Is complete.
8-111
AFN·00839C
8289
Upon completing its transaction the present bus occupant recognizes that it no longer has priority and surrenders the bus by releasing BUSY. BUSY is an active
'low "OR" tieel signal line which goes to every bus arbiter
on the system bus. When BUSY goes inactive (high), the
arbiter which presently has bus priority (BPRN true) then
seizes the bus and pulls BUSY low to keep other arbiters
off of the bu~. See waveform timing diagram, Figure 5.
Note that all mUlti-master system bus transactions, are
synchronized to the bus clock (BClK). This allows the
parallel priority resolving circuitry or any other priority
resolving scheme employed to settle.
74148
r---~I :~~OOR~~~
74138
H08
DECODER
Figure 4_ Parallel Priority Resolving Technique
~
HIGHER PRIORITY BUS ARBITER REQUESTS THE MULTI·MASTER SYSTEM BUS.
2
3
ATTAINS PRIORITY.
LOWER PRIORITY BUS ARBITER RELEASES BUSY.
4
HIGHER PRIORITY BUS ARBITER THEN ACQUIRES THE BUS AND PULLS BUSY DOWN.
Figure 5_ Higher Priority Arbiter obtaining the Bus from a Lower Priority Arbiter
8-112
AFN-00839C
8289
SERIAL PRIORITY RESOLVING
The serial priority resolving technique eliminates the
need for the priority encoder-decoder arrangement by
daisy-chaining the bus arbiters together, connecting the
higher priority bus arbiter's BPRO (Bus Priority Out) output to the BPRN of the next lower priority. See Figure 6.
8289 MODES OF OPERATION
There are two types of processors in the iAPX 86 family. An
Input/Output processor (the 8089 lOP) and the iAPX 86/10,
88/10 CPUs. Consequently, there are two basic operating
modes in the 8289 bus arbiter. One, the lOB (I/O Peripheral
Bus) mode, permits the processor access to both an I/O
Peripheral Bus and mUlti-master system bus. The second, the RESB (Resident Bus mode), permits the processor to communicate over both a Resident Bus and a
multi-master system bus. An I/O Peripheral Bus is a bus
where all devices on that bus, including memory, are
treated as I/O devices and are addressed by I/O commands. All memory commands are directed to another
bus, the multi-master system bus. A Resident Bus can
issue both memory and I/O commands, but it is a distinct
and separate bus from the multi-master system bus. The
distinction is that the Resident Bus has only one master,
providing full availability and being dedicated to that one
master.
a
THE NUMBER OF ARBITERS THAT MAY BE DAISY·CHAINED TOGETHER IN THE
SERIAL PRIORITY RESOLVING SCHEME IS A FUNCTION OF 8CLK AND THE PROPA·
GATION DELAY FROM ARBITER TO ARBITER. NORMALLY, AT 10 MHz ONLY 3 ARBI·
TER MAY BE
DAIS~.CHAINED.
Figure 6•. Serial Priority Resolving
ROTATING PRIORITY RESOLVING
The rotating priority resolving technique Is similar to
that of the parallel priority resolving technique except
that priority Is dynamically re-asslgned. The priority encoder Is replaced by a more complex circuit which rotates priority between requesting arbiters thus allowing
each arbiter an equal chance to use the multi-master
system bus, over time.
Which Priority Resolving Technique To
Use
There are advantages and disadvantages for each of the
techniques described above. The rotating priority
resolving technique requires substantial external logic
to Implement while the serial technique uses no externallogic but can accommodate only a limited number of
bus arbiters before the daisy-chain propagation delay
exceeds the multi-master's system bus clock (BCLK).
The parallel priority resolving technique Is in general a
good compromise between the other two techniques. It
allows for many arbiters to be present on the bus while
not requiring too much logic to implement.
The lOB strapping option configures the 8289 Bus Arbiter into the lOB mode and the strapping option RESB
configures it into the RESB mode. It might be noted at
this point that if both strapping options are strapped
false, the arbiter interfaces th.e processor to a multimaster system bus only (see Figure 7). With both options strapped true, the arbiter interfaces the processor
to a multi-master system bus, a Resident Bus, and an 1/0
Bus.
In the lOB mode, the proce~sor communicates and controls a host of peripherals over the Peripheral Bus. When
the 1/0 Processor needs to communicate with system
memory, it does so over the system memory bus. Figure
8 shows a possible 1/0 Processor system configuration.
The iAPX 86 and iAPX 88 processors can communicate
with a Resident Bus and a multi-master system bus. Two
bus controllers and only cine Bus Arbiterwould be needed
in such a configuration as shown in Figure 9. In such a
system configuration the processor would have access to
memory and peripherals of both busses. Memory mapping techniques are applied to select which bus is to be
accessed. The SYSB/RESB input on the arbiter serves to
instruct the arbiter as to whether or not the system bus is
to be accessed. The Signal connected to SYSB/RESB also
enables or disables commands from one of the bus
controllers.
A summary of the modes that the 8289 has, along with
its response to its status lines inputs, is summarized in
Table 2.
·In some system configurations it is possible for a non-I/O Processor to
have access to more than one Multi·Master System Bus, see 8289
Application Note.
8-113
AFN-OOB39C
8289
Table 2, Summary of 8289 Modes, Requesting and Relinquishing the Multi·Master System Bus
Single
~
Status Lines From
8086 or 8088 or 8089
1/0
COMMANDS
lOB Mode
Only
52
51
So
0
0
0
0
0
1
0
1
0
·x
x
x
x
HALT
0
1
1
MEM
COMMANDS
1
1
1
0
0
1
0
1
0
IDLE
1
1
1
RESB (Mode) Only
lOB = High RESB = High
lOB Mode RESB Mode
tOB = Low RESB = High
lOB", Low SYSB/RESB = High SYSB/RESB = Low
x
SYSB/RESB = High SYSB/RESB = Low
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
lOB = High
RESB = Low
x
x
x
x
NOTES:
1. X=.Multi·Master System Bus is allowed to be Surrendered.
2. V' = Multi·Master System Bus is Requested.
Multi·Master System Bus
Pin
Strapping
Requested"
Single Bus
Multi·Master Mode
10B= High
RESB= Low
Whenever the processor's
status lines go active
HLT + TI • CBRQ + HPBRQ t
RESB Mode Only
10B= High
RESB= High
SYSB/RESB = High·
ACTIVE STATUS
(SYSB/RESB = Low + TI) •
CBRQ + HLT + HPBRO
lOB Mode Only
10B=Low
RESB= Low
Memory Commands
(110 Status + TI) • CBRO +
HLT+HPBRO
lOB Mode· RESB Mode
10B=Low
RESB= High
(Memory Command) •
(SYSB/RESB = High)
«110 Status Commands)+
SYSB/RESB = LOW)) • CBRO
+ HPBRQt + HLT
Mode
Surrendered"
NOTES:
• LOCK prevents surrender of Bus to any other arbiter, CRQ[CR prevents surrender of Bus to any lower priority arbiter.
·'Except for HALT and Passive or IDLE Status.
t HPBRQ, Higher priority Bus request or BPRN = 1.
1. lOB Active Low.
2. RESB Active High.
3. + is read as "OR" and· as "AND."
4. TI= Processor Idle Status 52, 51,SO= 111
5. HLT= Processor Halt Status 52,81, SO=011
8·114
AFN·00839C
inter·
8289
rlD~
j
.....
RDY2bJ
CLOCK
AEN2
READY
RDYl
CLK
AEN1
"::'
(
"',
,US
ARBITER
- - - - ' I elK AN~QSTh
READY
....
CLK
i--
SO·!}AEN RES''1
ffi~
STATUS 50,51,52
I
I
1
r-
CS
PRO CESSOR
LOC AL BUS
VCC
I
CPU
A~':'~~: :-
XACK MULTI-MASTER SYSTEM BUS
MULTI-MASTER
CONTROL BUS
STB
~
AEN
8288
BUS
CONTROLLER
CLK
108
DTIA
_
MULrl·MASTER
SYSTEM
ADDRESS
.,.~
8282
(20A3)
!
C,
rd
I
I
MULTI-MASTER
SYSTEM BUS
BUS
11
I -
ALE
DEN
I
ADDRESS
LArCH
MULTI·MASTER
SYSTEM
COMMAND
BUS
XCVR
DiSAiitE
DTIA
MULTI-MASTER
SYSTEM
TRANSCEIVER
828&18287
DATA
BUS
,~
Figure 7. Typical Medium Complexity CPU System
_
XACK (110 8 U 5 ) > - - - - - - - _ .
UICA
RDY~LOC~DY2I__--------------_ COMMAND
~=====;;;:;;;;;;;:;j
-----
MULTI-MASTER
SYSTEM
BUS
MULTI·MASTER
UOBUS
SYSTEM BUS
'0
ADDRESS
BUS
'0
DATA
BUS
~===~=::~=======)MULTI'MASTER
SYSTEM
ADDRESS
BUS
k:=============:> MULTloMASTER
SYSTEM
DATA
BUS
Figure 8. Typical Medium Complexity lOB System
8-115
AFN-00839C
8289
o
AEN2
AEN1't--------,
1284A
CLOCK
ROY1i--------+-------- XACK MULTI·MASTER SYSTEM BUS
~~;~ENT B U S - - - - - - - - - ! R D Y 2
Vee
AEN
RESIDENT COMMAND
,US
1'------'----1
8288
MUl fl.MASTER SYSTEM
COMMAND BUS
MUlTI·MASTER
RESIDENT BUS
SYSTEM BUS
PROM
OR
DECODER
:~~IDENT
ADDR
LATCH
ADDRESS <:;::==~~===1
828218283
fZOR3)
MULTI·MASTER SYSTEM
AODRESS BUS
RESIDENT DATA~======~
BUS
\,
'BY ADDING ANOTHER 8289 ARBITER AND CONNECTING ITS AEN TO THE 8288
WHOSE A'ER IS PRESENTLY GROUNDED, THE PROCESSOR COULD HAVE ACCESS
TO TWO MUL TI·MASTER BUSES.
Figure 9. 8289 Bus Arbiter Shown in System·Resident Bus Configuration
8·116
AFN-00839C
inter
8289
·NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................. O·C to 70·C
Storage Temperature ............. -65·C to + 150·C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipation ..••..•..••.••........... 1.5 Watt
D.C. CHARACTERISTICS
(TA =
o·c to 70·C, Vee =
+5V ±10%)
Max.
Units
Ve
Input Clamp Voltage
-1.0
V
IF
Input Forward Current
-0.5
mA
Vee = 5.50V, VF = 0.45V
IR
Reverse Input leakage Current
60
,..A
Vcc =5.50, VR=5.50
VOL
Output Low Voltage
BUSY, CBRa
AEN
BPRO,BREa
0.45
0.45
0.45
V
V
V
IOL=20 mA
IOL= 16 mA
IOL= 10 mA
V
IOH = 400 ,..A
Symbol
Min.
Parameter
Output High Voltage
BUSY,CBRa
VOH
Open Collector
All Other Outputs
2.4
165
mA
.8
V
Icc
Power Supply Current
VIL
Input Low Voltage
V1H
Input High Voltage
Cin Status
Input Capacitance
25
pF
Cln (Others)
Input Capacitance
12
pF
A.C. CHARACTERISTICS (Vee =
Test Condition
Vee=4.50V, le= -5 mA
2.0
+5V ±10%, TA =
V
o·c to 70·C)
TIMING REQUIREMENTS
Symbol
Parameter
TClCl
ClK Cycle Period
TClCH
TCHCl
Min.
Max.
Unit
125
ns
ClK low Time
65
ns
ClK High Time
35
TSVCH
Status Active Setup
65
TClCl-l0
ns
TSHCl
Status Inactive Setup
50
TClCl-l0
ns
THVCH
Status Active Hold
10
ns
THVCl
Status Inactive Hold
10
ns
TBYSBl
BUSYi ~Setup to
BClK~
20
ns
TCBSBl
CBRQt~Setup
BClK~
20
ns
TBlBl
BClK Cycle Time
100
TBHCl
BClK High Time
30
TCllll
lOCK Inactive Hold
10
ns
TCllL2
lOCK Active Setup
40
ns
TPNBl
BPRN~ito
15
ns
TClSRl
SYSB/RESB Setup
0
ns
TClSR2
SYSB/RESB Hold
20
ns
TIVIH
Initialization Pulse Width
3TBlBl+
3 TClCl
ns
to
BClK Setup Time
\
Test Condition
ns
ns
.65[TBlBlJ
ns
TILIH
Input Rise Time
20
ns
From 0.8 to 2.0V
TIHll
Input Fall Time
12
ns
From 2.0V to 0.8V
8-117
AFN·00839C
8289
A.C.CHARACTERISTICS (Continued)
TIMING RESPONSES
Symbol
Parameter
TBLBRL
BCLK to BREO Delay.l i
Min.
Max.
Unit
35
ns
TBLPOH
BCLK to BPRO.l i (See Note 1)
40
ns
TPNPO
BPRN.I ito BPRO.l iDelay
(See Note 1)
25
ns
Test Condition
TBLBYL
BCLK to BUSY Low
60
ns
TBLBYH
BCLK to BUSY Float (See Note 2)
35
ns
TCLAEH
CLK to AEN High
65
ns
TBLAEL
BCLK to AEN Low
40
ns
TBLCBL
BCLK to CBRO Low
60
ns
TRLCRH
BCLK to CBRO Float (See Note 2)
35
ns
TOLOH
Output Rise Time
20
ns
From O.BV to 2.0V
TOHOL
Output Fall Time
12
ns
From 2.0V to O.BV
.Ii Denotes that spec applies to both transitions of the signal.
NOTES:
1. BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRON.
2. Measured at .5V above GND.
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
INPUT/OUTPUT
DEVICE
UNDER
TEST
i}CC-'OOPF
-=-
A.C. TESTING: INPUTSAAE DRIVEN AT 2.4V FOR A LOGIC "1" AND O.4SV FOR
A LOGIC "0." THE CLOCK IS DRIVEN AT 4.3V AND O.2SV. TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A LOGIC "1" AND "0."
C L = 100pF
CL INCLUDES JIG CAPACITANCE
8-118
AFN.Q0839C
8289
WAVEFORMS
eLK
I:mlK
(SEE NOTE 1)
SYSBIJrESij
ill
(SEE NOTE 3)
PROCESSOR elK RE~TED
BUS eLK RELATED
......
(!ISlR)fl1)
lIPRll ..
(mill #3)
....
NOTES:
1. iJ5CK ACTIVE CAN OCCUR DURING ANY STATE, AS LONG AS THE
RELATIONSHIPS SHOWN ABOVE WITH RESPECT TO THE CLK ARE MAINTAINED.
i1iCii INACTIVE HAS NO CRITICAL TIME AND CAN BE ASYNCHRONOUS.
-CRQLCK HAS NO CRITICAL TIMING AND IS CONSIDERED AN ASYNCHRONOUS
INPUT SIGNAL
'
2. GUTCHING OF SYSBIRESa PIN IS PERMITTED DURING THIS TIME. AFTER 2 OF
Tl, AND BEFORE 1 OF T4, SYSBIRESB SHOULD BE STABLE.
3. AEN LEADING EDGE IS RELATED TO BCLK, TRAIUNG EDGE TO CLK. THE
TRAILING EDGE OF AEN OCCURS AFTER BUS PRIORITY IS LOST.
ADDITIONAL NOTES:
The signals related to ClK are typical processor signals, and do not relate to the depicted sequence of events of the
signals referenced to BCCK. The signals shown related to the BClK represent a hypothetical sequence of events for
illustration. Assume 3 bus arbiters of priorities t, 2 and 3 configured in serial priority resolving scheme as shown in
Figure 6. Assume arbiter 1 has the bus and is holding busy low. Arbiter #2 detect~rocessor wants the 'bus and
pulls low BREQ#2. If BPRN#2 is high (as shown), arbiter #2 will pull low CBRO line. CBRO signals to the higher priority
arbiter #1 that a lower priority arbiter wants the bus. [A higher priority arbiter would be granted BPRN when it makes
the bus request rather than having to wait for another arbiter to release the bus through 'CBIrol." Arbiter #1 will relinquish the multi-master system bus when it enters a state not requiring it (see Table 1), by lowering its BPRO#l (tied to
BPRN#2) and releasing BUSY. Arbiter #2 now sees that it has priority from BPRN#2 being low and releases CBRQ. As
soon as BUSY signifies the bus is available (high), arbiter #2 pulls BUSY low on next falling edge of BClK. Note that if
arbiter #2 didn't want the bus at the time it received priority, it would pass priority to the next lower priority arbiter by
lowering its EiPROii2 [TPNPOj.
··Note that even a higher priority arbiter which is acquiring the bus through
8-119
'B'PAN will
momentarily drop
C"B"RQ until
It has acquired the bus.
AFN-OOB39C
MODEL 230
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM
Complete microcomputer development
center for Intel MCS-86, MCS-80, MCS-85
and MCS-48 microprocessor families
LSI electronics board with CPU, RAM,
ROM, 110, and interrupt circuitry
Powerful ISIS-II Diskette Operating
System software with relocating
macroassembler, linker, and locater
1 million bytes (expandable to 2_5M
bytes) of diskette storage
64K bytes RAM memory
Self-test diagnostic capability
Eight-level nested, maskable priority
interrupt system
Supports PUM and FORTRAN high level
languages
Standard MULTIBUS with multiprocessor
and DMA capability
Built-in interfaces for high speed paper
tape reader/punch, printer, and universal
PROM programmer
Compatible with standard Inteliec/iSBC
expansion modules
Integral CRT with detachable upper/
lower case typewriter-style full ASCII
keyboard
Software compatible with previous
Intellec systems
The Model 230 Intellec Series II Microcomputer Development System Is a complete center for the development of
microcomputer-based products. It Includes a CPU, 64K bytes of RAM, 4K bytes of ROM memory, a 2000-character CRT,
a detachable full ASCII keyboard, and dual double density diskette drives providing over 1 million bytes of on-line data
storage. Powerful ISIS-II Diskette Operating System software allows the Model 230 to be used quickly and efficiently
for assembling and/or compiling and debugging programs for Intel's MCS-S6, MCS-SO, MCS-S5, or MCS-4S microprocessor families without the need for handling paper tape. ISIS-II performs all file handling operations, leaving the user
free to concentrate on the details of his own application. When used .In conjunction with an optional in-circuit
emulator (ICE) module, the Model 230 provides ali the hardware and software development tools necessary for the
rapid development of a microcomputer-based product.
8-120
MODEL230
FUNCTIONAL DESCRIPTION
card communicates with the IPB over an 8-bit bidirectional data bus.
Hardware Components
Memory and Control Cards - In addition, 32K bytes of
RAM (bringing the total to 64K bytes) is located on a
separate card in the main cardcage. Fabricated from
Intel's 16K RAMs, the board also contains all necessary
address decoding and refresh logic. Two additional
boards in the cardcage are used to control the two
double-density floppy disk drives.
The Intellec Series II Model 230 is a packaged, highly
integrated microcomputer development system consistIng of a CRT chassis with a 6-slot card cage, power supply, fans, cables, and five printed circuit cards. A
separate, full ASCII keyboard is connected with a cable.
A second chassis contains two floppy disk drives capable of double-density operation along with a separate
power supply, fans, and cables for connection to the
main chassis. A block diagram of the Model 230 is
shown in Figure 1.
CPU Cards - The master CPU card contains its own
microprocessor, memory, 110, interrupt and bus interface circuitry fashioned from Intel's high technology LSI
components. Known as the Integrated processor board
(IPB), it occupies the first slot in the cardcage. A second
slave CPU card is responsible for all remaining 110 control including the CRT and keyboard Interface. This card,
mounted on the rear panel, also contains Its own microprocessor, RAM and ROM memory, and 110 interface
logic, thus, in effect, creating a dual processor environment. Known as the 110 controller (lOC), the slave CPU
Expansion - Two remaining slots. in the card cage are
available for system expansion. Additional expansion of
4 slots can be achieved through the addition of an Intellec Series II expansion chassis.
System Components
The heart of the IPB Is an Intel NMOS 8:bit microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with sys- .
tem bootstrap ~'seH-test" diagnostics and the Intellec
Series II System Monitor. The eight-level vectored priorIty interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259A interrupt controller, the interrupt system may be user programmed to
respond to Individual needs.
Figure 1. Intellec Series II Model 230 Microcomputer Development System Block Diagram
8-121
MODEL230
Input/Output
IPB Serial Channels - The I/O subsystem in the Model
230 consists of two parts: the 10C card and two serial
channels on the IPB itself. Each serial channel is RS232
compatible and is capable of running asynchronously
from 110 to 9600 baud or synchronously from 150 to 56K
baud. Both may be connected to a user defined data set
or terminal. One channel contains current loop
.adapters. Both channels are implemented using Intel's
8251A USART. They can be programmatically selected
to perform a variety of I/O functions. Baud rate selection
Is accomplished programmatically through an Intel 8253
Interval timer. The 8253 also serves as a real·tlme clock
for the entire system. I/O activity through both serial
channels is signaled to the system through a second
8259 interrupt controller, operating in a polied mode
nested to the primary 8259.
IOC Interface - The remainder of system I/O activity
takes place in the IOC. The 10C provides interface for
the CRT, keyboard, and standard Intellec peripherals
including printer, high speed paper tape reader/punch,
and universal PROM programmer. The 10C contains its
own independent microprocessor, also an 8080A-2. The
CPU controls all I/O operations as well as supervising
communications with the IPB. 8K bytes of ROM contain
all I/O control firmware. 8K bytes of RAM are used for
CRT screen refresh storage. These do not occupy space
in Intellec Series II main memory since the 10C is a
totally independent microcomputer subsystem.
Integral CRT
Display - The CRT is a 12-lnch raster scan type monitor
with a 50/60 Hz vertical scan rate and 15.5 kHz horizontal
scan rate. Controls are provided for brightness and contrast adjustments. The interface to the CRT is provided
through an Intel 8275 single chip programmable CRT
controller. The master processor on the IPB transfers a
character for display to the 10C, where it is stored in
RAM. The CRT controller reads a line at a time into its
line buffer through an Intel 8257 DMA controller and
then feeds one character at a time to the character gen·
erator to produce the video signal. Timing for the CRT
control is provided by an Intel 8253 interval timer. The
screen display is formatted as 25 rows of 80 characters.
The full set of ASCII characters are displayed, including
lower case alphas.
Keyboard - The keyboard interfaces directly to the 10C
processor via an 8·bit data bus. The keyboard contains
an Intel UPI-41 Universal Peripheral Interface, which
scans the keyboard, encodes the characters, and buffers the characters to provide N-key rollover. The keyboard itself is a high quality typewriter style keyboard
containing the full ASCII character set. An upperllower
case switch allows the system to be used for document
preparation. Cursor control keys are also provided.
Peripheral Interface
A UPI·41 Universal Peripheral Interface on the 10C board
performs similar functions to the UPI-41 on the PIO
board in the Model 210. It provides interface for other
standard Intellec peripherals including a printer, high
speed paper tape reader, high speed paper tape punch,
and universal PROM programmer. Communication
between the IPB and 10C Is maintained over a separate
8-bit bidirectional data bus. Connectors for the four
devices named above, as well as the two serial channels, are mounted directiy on the 10C itself.
Control
User control is maintained through a front panel, con·
sisting of a power switch and indicator, reset/boot
switch, run/halt light, and eight interrupt switches and
indicators. The front panel circuit board is attached
directly to the IPB, allowing the eight interrupt switches
to connect to the primary 8259A, as well as to the Intellec
Series II bus.
Diskette System
The Intellec Series II double density diskette system
provides direct access bulk storage, intelligent controller, and two diskette drives. Each drive provides V2 million bytes of storage with a data transfer rate of 500,000
bits/second. The controller is implemented with Intel's
powerful Series 3000 Bipolar Microcomputer Set. The
controller provides an interface to the Intellec Series II
system bus, as well as supporting up to four diskette
drives. The diskette system records all data in soft sector format. The diskette system is capable of performing
seven different operations: recalibrate, seek, format
track, write data, write deleted data, read data, and verify
CRC.
Diskette Controller Boards - The diskette controller
conSists of two boards, the channel board and the inter·
face board. These two PC boards reside iri the Intellec
Series II system chassis and constitute the diskette
controller. The channel board receives, decodes and
responds to channel commands from the 8080A-2 CPU
in the Model 230. The interface board provides the
diskette controller with a means of communication with
the diskette drives and with the Intellec system bus. The
interface board validates data during reads using a
cyclic redundancy check (CRC) polynomial and generates CRC data during write operations. When the diskette controller requires access to Intellec system memory, the interface board requests and maintains DMA
master control of the system bus, and generates the
appropriate memory command. The interface board also
acknowledges I/O commands as required by the Intellec
bus. In addition to supporting a second set of double
density drives, the diskette controller may co·reside
with the Intel single density controller to allow up to 2.5
million bytes of on·line storage.
MULTIBUS Capability
All Intellec Series II models implement the industry
standard MULTIBUS. MULTIBUS enables several bus
masters, such as CPU and DMA devices, to share the
bus and memory by operating at different priority levels.
Resolution of bus exchanges is synchronized by a bus
clock signal derived independently from processor
clocks. Read/write transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microcomputer family.
8-122
MODEL 230
SPECIFICATIONS
AC·Requlrements - 50/60 Hz, 115/230V AC
Host Processor (IPB)
RAM - 64K (system monitor occupies 62K through 64K)
ROM - 4K (2K in monitor, 2K In boot/diagnostic)
Environmental Characteristics
Diskette System Capacity (Basic Two Drives)
Operating Temperature - O· to 35·C (95·F)
Unformatted
Per Disk: 6.2 megabits
Per Track: 82.0 kiloblts
Formatted
Per Disk: 4.1 megabits
Per Track: 53.2 kilobits
Equipment Supplied
Model 230 chassis
Integrated processor board (lPB)
I/O controller board (IOC)
32K RAM board
CRT and keyboard
Double density floppy disk controller (2 boards)
Qual drive floppy disk chassis and cables
2 floppy disk drives (512K byte capacity each)
ROM-resident system monitor
Diskette Performance
Diskette System Transfer Rate - 500 klloblts/sec
Diskette System Access Time
Track-to-Track: 10 ms
Head Settling Time: 10 ms
Average Random Positioning Time - 260 ms.
Rotational Speed - 360 rpm
Average Rotational Latency - 83 ms
Recording Mode - M2FM
ISIS-II system diskette with MCS-80/MCS-85
macroassembler
Physical Characteristics
Width - 17.37 In. (44.12 cm)
Height - 15.81 in. (40.16 cm)
Depth - 19.13 in. (48.59 cm)
Weight - 73 Ib (33 kg)
Reference Manuals
9800558 - A Guide to Microcomputer Development
Systems (SUPPLIED)
9800550 - Intellec Series II Installation and Service
Guide (SUPPLIED)
Keyboard
Width - 17.37 in. (44.12 cm)
Height - 3.0 in. (7.62 cm)
Depth - 9.0 in. (22.86 cm)
Weight - 6 Ib (3 kg)
9800306 -
9800556 - Intellec Series II Hardware Reference Manual (SUPPLIED)
Dual Drive Chassis
Width - 16.88 in. (42.88 cm)
Height - 12.08 in. (30.68 cm)
Depth - 19.0 in. (48.26 cm)
Weight - 64 Ib (29 kg)
9800301 - 8080/8085 Assembly Language Programming Manual (SUPPLIED)
9800292 - ISIS-II 8080/8085 Assembler Operator's Manual (SUPPLIED)
Electrical Characteristics
9800605 - Intellec Series II Systems Monitor Source
Listing (SUPPLIED)
DC Power Supply
Volts
Supplied
..
+ 5:1:5%
+12:1:5%
-12±S%
-10:1:5%
+15:1:5%
+24:1:5%
ISIS-II System User's Guide (SUPPLIED)
Amps
Supplied
Typical
System Requirements
30
2.5
0.3
1.5
1.5
1.7
1.4.25
0.2
0.05
15
1.3
9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
Reference manuals are shipped with each product only
if designated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 BOwers
Avenue, Santa Clara, California 95051.
·Not available on bus.
ORDERING INFORMATION
Part Number Description
MDS-230
Intellec Series II Model 230
microcornputer development system
(110V/60 Hz)
MDS-231
Intellec Series II Model 230
microcomputer development system
(220V/50 Hz)
8-123
MODEL 286
INTELLEC® SERIES III
MICROCOMPUTER DEVELOPMENT SYSTEM
• Supports Intellec 432/100 Evaluation
and Educational System
II
• Compatible with iSBC-090 Series 90
Memory System Upgrade: 512K Byte
t01MByte
96K Bytes of User Program RAM
Memory Available for iAPX 86,88
Programs
• Series 11/80 and Series 11/85
Upgradeable to 8085/iAPX 86 Series III
Functionality
• Complete 16-bit High Performance,
Microcomputer Development Solution
for Intel iAPX 86,88 Applications. Also
Supports MCS-85™ , MCS-80 and
MCS-48 Families
II
Intellec Model 800 Upgradeable to
8080/iAPX 86 Series III Functionality
.. Compatible with Intellec Distributed
Development Systems
• Supports Full Range of iAPX 86,88Resident, High-Level Languages:PLlM
86/88, PASCAL 86/88, and FORTRAN
86/88
• 2 Host CPUs-iAPX 86 and 8085A-for
Enhanced System Performance and
Two Native Execution Environments
II
Compatible with Previous Intellec
Systems
• Software Applications Debugger for
User iAPX 86,88 Programs
• Upgradeable to a Complete Ethernet*
Communications Development System
Environment, Using the Model 677
Upgrade
The Intellec Series-III Microcomputer Development System is a high-performance system solution designed
specifically for iAPX 86,88 microprocessor development. It contains two host CPUs, an iAPX 86 and an 8085,
that provide two native execution environments for optimum performance and compatibility with the Intellec
software packages for both CPUs. The basic system includes 96K bytes of iAPX 86,88 user RAM memory and a
250K byte floppy disk drive. The powerful Disk Operating System maximizes system processing by utilizing the
power of both host processors. Standard software includes a full range of iAPX 86,88 resident software. The
high-level languages PLIM 86/88, PASCAL 86/88, and FORTRAN 86/88 are also available. A ROM resident
software debugger not only provides self-test diagnostic capability, but also gives the user a powerful iAPX
86,88 applications debugger.
"Ethernet is a trademark of Xerox Corporation.
The following are trademarks of Intel Corporation and jts affiliates and may be used only to identify Intel products: i, tntel, INTEL, INTELLEC, MeS, 1m, iCS, ICE, UPI. exp, iSBC, iSBX,
Insite. iRMX, System 2000, CREDIT, iRMXJBO, MULTI BUS, PROMPT. Promware, Megachassis: library Manager, MAIN MULTIMODULE, and the combination of MeS, ICE, iSBC, iAMX or
iCS and a numerical suffix.
© INTEL CORPORATION, 1981.
8-124
AFN-01588B
121670-002
intel'
MODEL 286
FUNCTIONAL DESCRIPTION
Hardware Components
The Intellec Series III is contained in a single package consisting of a CRT chassis with a 6-slot card
cage, power supply, fans, cables, single floppy disk
drive, detachable upper/lower case full ASCII keyboard, and four printed circuit cards. A block diagram of the system is shown in Figure 1.
System Components
Two CPU cards reside on the Intellec MULTIBUS
bus, each containing its own microprocessor,
memory, I/O, interrupt and bus interface circuitry
implemented with Intel's high technology LSI components. The integrated processor card (IPC-85),
occupies the first slot in the cardcage. A second
CPU card, the resident processor board (RPB-86)
contains Intel's 16-bit HMOS microprocessor. These
CPUs provide the dual processor environment.
A third CPU card performs all remaining I/O including interface to the CRT, integral floppy disk, and
keyboard. This card, mounted on the rear panel,
contains its own microprocessors, RAM and ROM
memory, and I/O interface logic. Known as the I/O
controller (IOC), this slave CPU card communicates
with the IPC-85 over an 8-bit bidirectional data bus.A
64K byte RAM expansion memory board is also
included.
Expansion
Two additional slots in the system cardcage are
available for system expansion. The Intellec expansion chassis Model 201 is available to provide 4 additional expansion slots for either memory or I/O expansion.
THE INTELLEC DEVELOPMENT SYSTEM FOR
ETHERNET (DS/E)
The Intellec Series III can be expanded to provide the
user with the tools necessary to develop and test
Figure 1, INTELLEC Series III Block Diagram
B-125
AFN·01588B
MODEL 286
communications software and applications that will
use Ethernet as a communications subsystem. The
power of the Intellec Series III combined with Model
677 allows the user to develop either 8e or 16-bit
Ethernet-based applications.
THE INTELLEC 432/100 EVALUATION'AND
EDUCATIONAL SYSTEM
The Intellec Series III provides a complete. system
environment necessary for evaluation of the Intel
iAPX 432 32-bit micromainframe. The iSBC 432/100
board plugs into a Multibus slot in the Intellec Series III, sharing system. memory and resources. A
comprehensive set of documentation,system
software and hardware provides the evaluation and
educational environment for the powerful iAPX 432.
iAPX 286 Evaluation System
The Intellec Series III provides a complete system
environment for evaluation of the iAPX 286 microprocessor's architecture and. its instruction set, segmentation timing, memory mapping and protection
features. A user can begin the development of complex iAPX 286 programs, systems and operating system nuclei with the Intellec Series III and iAPX 286
. evaluation package.
CPU Cards
IPC-8S
The heart of the IPC"85 is an Intel NMOS 8-bit microprocessor, the 8085A-2, running at 4.0 MHz. 64K
bytes of RAM niemory are provided on the board
using 16K dynamic RAMs. 4K of ROM is provided,
preprogrammed with system bootstrap "self-test"
diagnostics and the Intellec System Monitor. The
, eight-level vectored priority interrupt system allows
interrupts to be! individually masked. Using Intel's
versatile 8259A,interrupt controller; the interrupt
system may be user programmed to respond to indi.vidual needs. .
RPB-86
The heart of the RPB-86 is an Intel HMOS 16-bit
microprocessor, the iAPX 86 (8086), running at 5.0
MHz. 64K bytes of RAM memory are provided on the
board. 16K of ROM is provided on board, prepro c
grammed with an iAPX 88/86 applications debugger
which provides .features necessary to debug and
execute application software for the iAPX 88/86
microprocessors ..
The 8085A-2 and. iAPX 86 access two independent
memory spaces. This allows the two processors to
:execute concurrently when an iAPX 88/86 program
is run. In this mode, the IPC-85 becomes an intellegent I/O processor board to the RPB-86.
Input/Output ..
IPC-8S SERIAL CHANNELS
The I/O subsystem in the Series III consists of two
parts: the 10C card and two serial channels on the
IPC-85 itself. Each serial channel is independently
configurable. Both are RS232-compatible and is capable of running asynchronously from 110 to 9600
baud or synchronously from 150 to 56K baud. Both
may be connected to a user defined data set or terminal. One channel contains current loop adapters.
Both channels are implemented using Intel's 8251A
USART. They can be programmed to perform a variety of I/O functions. Baud rate selection is accomplished through an Intel 8253 interval timer. The
8253 also serves as a real-time clock for the entire
system. I/O activity through each serial channel is
independently signaled to the system through a
second 8259A (slave) interrupt controller, operating
.in a polled mode nested to the master 8259A.
IOC INTERFACE
The remainder of the system I/O activity is handled
by the 10C. The 10C provides the interface and control for the keyboard, CRT, integral floppy disk drive,
and standard Intellec-compatable peripherals including printer, high speed paper tape reader/
punch, and universal PROM programmer. The 10C
contains its own independent microprocessor, an
8080A-2. This CPU issues commands,receives
status, and controls. all I/O operations as well as
supervising communications with the IPC-85. The
10C contains interval timers, its own 10C bus system
controller, and 8K bytes of ROM for all I/O control
firmware. The 8K bytes of RAM are used for CRT
screen refresh storage. Neither the ROM'nor the
RAM occupy space in the Intellec Series III main
memory address range because the 10C is a totally
independent microcomputer subsystem.
Integral CRT
DISPLAY
The CRT is a 12-inch raster scan type monitor with a
50/60 Hz vertical scan rate and 15.5 kHz horizontal
scan rate. Controls are provided for brightness and
contrast adjustments. The interface to the CRT is
provided through an Intel 8275 single chip programmable CRT controller. The master processor
on the IPC-85 transfers a character for display to the
10C, where it is stored in RAM. The CRT controller
reads a line at a time into its line buffer through an
Intel 8257 DMA Controller. It then feeds one character at a time to the character generator to produce
the video signal. Timing for the CRT control is
provided by an Intel 8253 programmable interval
B-126
AFN-Ol588B
MODEL 286
timer. The screen display is formatted as 25 rows of
80 characters. The full set of ASCII characters are
displayed, including lower case alphas.
KEYBOARD
The keyboard interfaces directly to the IOC processor via an 8-bit data bus. The keyboard contains
an Intel U PI-41 A Universal Peri pheral Interface,
which scans the keyboard and encodes the characters to provide N-key roll over. The keyboard itself is
a typewriter style keyboard containing the full ASCII
character set. An upper/lower case switch allows the
system to be used for dor-l!ment preparation. Cursor
control keys are also provided.
Dual Drive Floppy Disk System (Option)
The Intellec Series III Double Density Diskette System provides direct access bulk storage, intelligent
controller and two diskette drives. Each drive
provides 1/2 million bytes of storage with a data
transfer of 500,000 bits/second. The controller is
implemented with Intel's powerful Series 3000 Bipolar Microcomputer Set and supports up to four diskette drives to allow more than 2 million bytes of
on-I i ne storage.
The diskette controller consists of two boards, the
channel board and the interface board. These two
PC boards reside in the Intellec Series III system
chassis. The channel board receives, decodes and
responds to channel commands from the 8085A-2
CPU on the IPC-85. The interface board provides the
diskette controller with a means of communication
with the disk drives and with the Intellec system bus.
The interface board also validates data during disk
transactions.
Peripheral Interface
A UPI-41A Universal Peripheral Interface on the IOC
board provides built-in interface for standard
Intellec-compatable peripherals including a printer,
high speed paper tape reader, high speed paper
tape punch, and universal PROM programmer.
Communication between the IPC-85 and IOC is
maintained over a separate 8-bit bidirectional data
bus. Connectors for the four devices named above,
as well as the two serial channels, are mounted directly on the IOC itself.
An additional cable and connectors are also
supplied to optionally convert the integral floppy
disk from single density to double density.
Control
User control is maintained through a front panel,
consisting of a power switch and indicator, reset/
boot switch, run/halt light and eight interrupt
switches and LED indicators. The front panel circuit
board is attached directly to the IPC-85, allowing the
eight interrupt switches to connect the master
8259A, as well as to the Intellec Series III bus.
User program control in the iAPX 88/86 environment
of the Intellec Series III is also directed through keyboard control sequences to transfer control to the
iAPX 88/86 applications debugger, abort a user program or translator and returning control to the
IPC-85.
DISK SYSTEM
Integral Floppy Disk Drive
The integral floppy disk is controlled by an Intel 8271
single chip, programmable floppy disk controller.
The disk provides capacity of 250K bytes. It transfers
data via an Intel 8257 DMA Controller between an
IOC RAM buffer and the diskette. The 8271 handles
reading and writing of data, formatting diskettes,
and reading status, all upon appropriate commands
from the IOC microprocessor.
B-127
Hard Disk System (Option)
The Intellec Series III Hard Disk System provides
direct access bulk storage, intelligent controller and
a disk drive containing one fixed platter and one
removable cartridge. Each provides approximately
3.65 million bytes of storage with a data transfer rate
of 2.5 Mbits/second. The controller is implemented
with Intel's Series 3000 Bipolar Microcomputer Set.
The controller provides an interface to the Intellec
Series III system bus, as well as supporting up to 2
disk drives. The disk system records all data in Double Frequency (FM) on 2 surfaces per platter. Each
platter can be write protected by a front panel
switch.
HARD DISK CONTROLLER BOARDS
The disk controller consists of two boards which
reside in the Intellec Series III system chassis. The
disk system is capable of performing six operations:
recalibrate, seek, format track, write data, read data,
and verify CRC. In addition to supporting a second
drive, the disk controller may co-exist with the
double-density diskette controller to allow up to 17
million bytes of on-line storage.
AFN-01588B
inter
MODEL 286
8"bit translations and applications are handled by
the 8-bit CPU, and 16-bit translations and applications are handled by the 8086. This feature provides
complete compatibility for current systems and
means that software running on current Intellec Development Systems will run on the new system.
MULTI BUS Interface Capability
All models of the Intellec Series III implement the
industry standard MULTIBUS protocol. The MULTIBUS architecture allows several bus masters, such
as CPU and DMA devices, to share the bus and
memory by operating at different priority levels.
Resolution of bus exchanges is synchronized by a
bus clock signal derived independently from processor clocks. Read/write transfers may take place
at rates up to 5 MHz. The bus structure is suitable for
use with any Intel microcomputer family.
High-Level Languages for iAPX 86,88-The Model
286 allows the current Intellec system user to take
advantage of a breadth of new resident iAPX 86,88
high-level languages: PUM 86/88, PASCAL 86/88,
and FORTRAN 86/88. The iAPX8.6,88 Resident
Macro Assembler and these high-level language
compilers execute on the 8086 h.ost CPU, thereby
increasing system performance.
System Software Features
The Mod.el 286 offers many key advantages for iAPX
86,88 applications and Intellec Development Systems: enhanced system performance through a dual
host CPU environment, a full spectrum of iAPX
86,88-resident high-level languages, expanded user
program space for iAPX 86,88programs, and a powerful high-level software applications debugger for
iAPX 86,88 microprocessor software.
Expanded Program Memory-By adding a Model
286 to an existing Intellec Development System, 96K
bytes of user program RAM memory are made available .for iAPX 86,88 programs. System memory is
expandable by adding additional RAM memory
modules. This, combined with the two host CPU
system architecture, dramatically increases the processing power of the system.
Dual Host CPU-The addition of a 16-bit 8086 to the
existing 8-bit host CPU increases iAPX 86,88 compilation speeds and provides fOr iAPX 86,88 code
execution. When the 8086 is executing a program,
the 8-bit CPU off-loads all I/O activity and operates
as an intelligent I/O controller to double buffer data
to and from the 8086. The 8086 also provides an
execution vehicle for 8086 and 8088 object code. An
added benefit of two host microprocessors is that
Software Applications Debugger-The RPB-86
contains the applications debugger which allows
iAPX 86,88 programs to be developed, tested, and
debugged within the Intellec system. The debugger
provides a subset of In-Circuit Emulator commands
such as symbolic debugging, control structures and
compound commands specifically oriented toward
software debug needs.
SPECIFICATIONS
Integral Floppy Disk
Host.P.rocessor Boards
Capacity-250K bytes (formatted)
Transfer Rate-160K bits/sec
Access TimeTrack to Track: 10 ms max.
Average Random Positioning: 260 ns
Rotational Speed: 360 rpm
Average Rotational Latency: 83 ms
Recording Mode: FM
INTEGRATED PROCESSOR CARD
-(IPC-85) 8085A-2 based, operating at 4 MHz
-64K RAM, 4K ROM (2K in monitor and 2K in boot/
diagnostic)
RESIDENT PROCESSOR BOARD
-(RPB-86) 8086 based, operating at 5 MHz, 64K
RAM, 16K ROM (applications debugger)
BUS
-MULTIBUS bus, maximum transfer rate of 5 MHz
DIRECT MEMORY ACCESS
-(DMA) Standard capability on the MULTIBUS bus;
implemented for user seJected DMA devices
through optional DMA module
-Maximum transfer rate of 2 MHz
Dual Floppy Disk Option
Capacity- .
Per Disk: 4.1 megabits (formatted)
Per Track: 53.2 kilobits (formatted)
Transfer Rate.....:.500·kilobits/sec
Access Ti me- .
Track.to Track: 10 ms
Head Setting Time: 10 ms
Average Random Positioning.Time-260ms
B-128
AFN·015BBB
intel·
MODEL 286
Rotational Speed-360 rpm
Average Rotational Latency: 83 ms
Recording Mode: M2 FM
ELECTRICAL CHARACTERISTICS
DC Power Supply
Hard Disk Drive Option
Type-5440 top loading cartridge and one fixed
platter
Tracks per Inch-200
Mechanical Sectors per Track-12
Recording Technique-double frequency (FM)
Tracks per Surface-400
Density-2,200 bits/inch
Bits per Track-62,500
Recording Surfaces per Platter-2
CapacityPer Surface-15M bits
Per Platter-29M bits
Per Drive-59M bits
Per Drive-7.3M bytes (formatted)
Transfer Rate-2.5M bits/sec
Access TimeTrack to Track: 13 ms max
Full Stroke: 100 ms
Rotational Speed: 2,400 rpm
Typical
System
Requirements
Volts
Supplied
Amps
Supplied
+ 5 ± 5%
30.0
+1"2 ± 5%
2.5
1.1
-12 ± 5%
0.3
0.1
-10 ± 5%
1.0
0.08
+15 ± 5%'
1.5
1.5
+24 ± 5%'
1.7
1.7
17.0
'Not available on bus
AC Requirements for Mainframe
110V, 60 Hz-5.9 Amp
220V, 50 HZ-3.0 Amp
ENVIRONMENAL CHARACTERISTICS
System Operating Temperature-0° to 35°C
(32°F to 95°F)
Physical Characteristics
Humidity-20% to 80%
Width-17.37 in. (44.12 cm)
Height-15.81 in. (40.16 cm)
Depth-19.13 in. (48.59 cm)
Weight-81 lb. (37 kg)
DOCUMENTATION SUPPLIED
Intellec Series 1/1 Microcomputer Development System Product Overview, 121575
KEYBOARD
Width-17.37 in. (44.12 cm)
Height-3.0 in. (7.6 cm)
Depth-9.0 in. (22.86 cm)
Weight-6 lb. (3 kg)
A Guide to Intellec Series III Microcomputer Development Systems, 121632-001
Intellec Series /II Microcomputer Development System Console Operating Instructions, 121609
Intellec Series /II Microcomputer Development System Pocket Reference, 121610
DUAL FLOPPY DRIVE SYSTEM (OPTION)
Width-16.88 in. (42.88 cm)
Height-12.08 in. (30.68 cm)
Depth-1.0 in. (48.26 cm)
Weight-64 lb. (29 kg)
Intellec Series /II Microcomputer Development System Programmer's Reference, 121618
iAPX 88/86 Family Utilities User's Guide for 8086Based Development Systems, 121616
8086/8087/8088 Macro Assembly Language Reference Manual for 8086-Based Development Systems,
121627
HARD DISK DRIVE SYSTEM (OPTION)
Width-18.5 in. (47.0 cm)
Height-34.0 in. (86.4 cm)
Depth-29.75 in. (75.6 cm)
Weight-202 lb. (92 kg)
8086/8087/8088 Macro Assembly Language Pocket
Reference, 9800749
B-129
AFN·015888
MODEL 286
8086/8087/8088 Macro Assembler Operating Instructions for 8086-Based Development Systems,
121628
Intellec Series III Microcomputer Development System Installation and Checkout Manual, 121612
ISIS-II CREDIT (CRT-Based Text Editor) Pocket Reference, 9800903
The 8086 Family User's Manual, 9800722
The 8086 Family User's Manual, Numeric Supplement, 121S86
Intellec Series III Microcomputer Development System Schematic Drawings, 121642
For Series III Plus Hard Disk Systems Only:
ISIS-II CREDIT (CRT-Based Text Editor) User's
Guide, 9800902
Model 740 Hard Disk Subsystem Operation and
Checkout, 9800943
ORDERING INFORMATION
DS287FD KIT
Part Number Description
DS286 KIT
Intellec Series III Model 286 Microcomputer Development System
(110V/60Hz)
DS287 KIT
Intellec Series III Model 287 Microcomputer Development System
(220V/SOHz)
DS286FD KIT
Intellec Series III Model 286 Microcomputer Development System with
Dual Double Density Flexible Disk
System (110V/60Hz)
Intellec Series III Model 287 Microcomputer Development System with
Dual Double Density Flexible Disk
System (220V/SOHz)
DS286HD KIT Intellec Series III Model 286 Microcomputer Development System with
Pedestal Mou nted Hard Disk.
(110V/60Hz)
DS287HD KIT Intellec Series III Model 287 Microcomputer Development System with
Pedestal Mounted Hard Disk.
(220V/SOHz)
Requires Software License
8-130
AFN·01588B
PL/M 86/88 SOFTWARE PACKAGE
•
Executes on Series III iAPX 86
Processor for Fastest Compilations
•
Language Is Upward Compatible from
PL/M 80, Assuring MCS-80/85 Design
Portability
•
•
Supports 16-Bit Signed Integer and
32-Bit Floating Point Arithmetic in
Accordance with IEEE Proposed
Standard
Easy-To-Learn Block-Structured
Language Encourages Program
Modularity
m
Improved Compiler Performance Now
Supports More User Symbols and
Faster Compilation Speeds
II
Produces Relocatable Object Code
Which Is Linkable to All Other 8086
Object Modules
1:1
Code Optimization Assures Efficient
Code Generation and Minimum
Application Memory Utilization
[]
Built-In Syntax Checker Doubles
Performance for Compiling Programs
Containing Errors
Like its counterpart for MCS-80/85 program development, PL/M 86/88 is an advanced, structured high-level
programming language. The PL/M 86/88 compiler was created specifically for performing software development for the Intel 8086and 8088 Microprocessors.
PL/M is a powerful, structured, high-level system implementation language in which program statements can
naturally express the program algorithm. This frees the programmer to concentrate on the logic of the program without concern for burdensome details of machine or assembly language programming (such as register allocation, meanings oiassembler mnemonics, etc.).
The PL/M 86/88 compiler efficiently converts free-form PL/M language statements into equivalent 8088/8086
machine instructions. Substantially fewer PL/M statements are necessary for a given application than if it were
programmed at the assembly language or machine code level.
The use of PL/M high-level language for system programming, instead of assembly languag'e, results in a high
degree of engineering productivity during project development. Tflis translates into significant reductions in
initial software development and follow-on maintenance costs for the user.
NOTE: The Inteliee']; Microcomputer Development System pictur,ed her~ is not included with the PUM 86/88 Software Package but merely depicts a language in its operating
environment.
The following are trademarks of Inlel Corporation and may be used only to identify Intel products: i, Intel, INTEL, INTELLEC, MeS. im , les, ICE, UPI, BXP.-iSBC, iSBX, iNSITE, iRMX,
CREDIT. RMXl60. p,Scope. Multibus, PROMPT, Promware, Megachassis, Library Manager, MAIN MULTI MODULE, and the combination of MeS,ICE, SBC, RMX or ieS and a numerical
suffix; e.g., iSBC-BO.
© Intel Corporation 1980
8-131
September 1980
inter
PL/M 86/88 SOFTWARE PACKAGE
FEATURES
Major features of the Intel PUM 86/88 compiler and
programming language include:
Another powerful facility allows the use of BASED
variables that map more than one variable to the
same memory location. This is especially useful for
passing parameters, relative and absolute addressing, and memory allocation.
Block Structure
Two· Data Structuring Facilities
PUM source code is developed in a series of modules, procedures, and blocks. Encouraging program
modularity in this manner makes programs more
readable, arid easier to maintain and debug. The
language becomes more flexible, by clearly defining
the scope of user variables (local to a private procedure, global to a public procedure, for example).
In addition to the five data types and based variables,
PUM supports two data structuring facilities. These
add flexibility to the referencing of data stQred in
large groups.
The use of procedures to break down a large problem is paramount to productive software development. The PUM 86/88 implementation of a block
structure allows the use of REENTRANT (recursive)
procedures, which are especially useful in system
design.
.
Language CompatibiUty
PUM 86/88 object modules are compatible with object modules generated by all other 86/88 translators. This means that PL/M programs may be
linked to programs written in any other 86/88
language.
Object modules are compatible with ICE-88 and
ICE-86 units; DEBUG compiler control provides the
In-Circuit Emulators with symbolic debugging
capabilities.
PL/M 86/88 Language is upward-compatible with
PUM 80, so thatapplication programs may be easily
ported to run on the iAPX 86 or 88.
- Array: Indexed list of same type data elements
- Structure: Named collection of same.or different
type data elements
- Combinations of Each: Arrays of structures or
structures of arrays
8087 Numerics Support
PL/M programs that use 32-bit REAL data may be
executed using the Numeric Data Processor for improved performance. All floating"point operations
supported by PUM may be executed.onthe iAPX
86/20 or 88/20 NDP, or the 8087 Emulator (a software
module) provided with the package. Determination
of use of the chip or Emulator takes place at linktir:ne, allowing compilations to be run-time
independent.
Built-In String Handling FaciUties
The PUM 86/88 language contains built-in functions
for string manipulation. These byte and word functions perform the following operations on character
strings: MOVE, COMPARE, TRANSLATE, SEARCH,
SKIP, and SET.
Interrupt Handling
Supports Five Data Types
PUM makes use of five data types for various applications. These data types range from one to four
bytes, and facilitate various arithmetic, logic, and
addressing functions:
- Byte: 8-bit unsigned number
- Word: 16-bit unsigned number
-Integer: 16-bit signed number
- Real: 32-bit floating point number
- Pointer: 16-bit or 32-bit memory address
indicator
PUM has the facility for generating interrupts to the
iAPX 86 or 88 via software. A procedure may be
defined with the INTERRUPT attribute, and the
compiler will automatically initialize an interrupt
vector at the appropriate memory location. The
compiler will also generate code to same and restore the processor status, for execution of the
user-defined interrupt handler routine. The procedure SET$INTERRUPT, the function retuning
an INTERRUPT$PTR, and the PL/M statement
CAUSE$INTERRUPT all add flexibility to user
programs involving interrupt and handling.
B-132
AFN-01661A
inter
PL/M 86/88 SOFTWARE PACKAGE
-
Compiler Controls
Including several that have been mentioned, the
PL/M 86/88 compiler offers more than 25 controls
that facilitate such features as:
-
Conditional compilation
Including additional PL/M source files from disk
Intra- and Inter-module cross reference
Corresponding assembly language code in the
listing file
Setting overflow conditions for run-time handling
Segmentation Control
The PLiM 86/88 compiler takes full advantage of
program addressing with the SMALL, COMPACT,
MEDIUM, and LARGE segmentation controls. Programs with less than 64KB total code space can
exploit the most efficient memory addressing
schemes, which lowers total memory requirements.
Larger programs can exploit the flexibility of extended one-megabyte addressing.
Code Optimization
The PL/M 86/88 compiler offers four levels of optimization for significantly reducing overall program
size.
-
Combination or "folding" of constant expressions; and short-circuit evaluation of Boolean expressions.
"Strength reductions" (such as a shift left rather
than multiply by 2); and elimination of common
sub-expressions within the same block.
- Machine code optimizations; elimination of
superfluous branches; re-use of duplicate code;
removal of unreadable code.
- Byte comparisons (rather than 20-bit address
calculations) for pointer variables; optimization
of based-variable operations.
Error Checking
The PL/M 86/88 compiler has a very powerful feature
to speed up compilations. If a syntax or program
error is detected, the compiler will skip the code
generation and optimization passes. This usually
yields a 2X performance increase for compilation of
programs with errors.
A fully detailed set of programming and compilation
errors is provided by the compiler.
Compiler Performance
Performance benchmarks may provide valuable information in estimating compile times for various
programs. It is extremely important to understand,
however, the effect of varying conditions on compiler performance. Storage media, coding style,
program length, and the use of INCLUDE files significantly change the compiler's overall performance.
We tested typical PL/M programs of varying lengths.
The resu Its are listed in Table 1.
Table 1. PL/M Program Compile Times
Program Size
SMALL (71)
Compile Time(Sec)
Lines/Minute
20
213
MEDIUM (610)
54
678
LARGE (1710)
128
802
LARGE (1403)
129
653
(with very dense code,
plus include file)
NOTE: These programs were run on a Series III with ISIS 4.1 and a hard disk. The lines per minute figures reflect fifteen percent blank lines
and comments.
The compiler allows approximately 1000 ten-character user symbols.
B-133
AFN·01661A
inter
M:DO:
PL/M 86/88 SOFTWARE PACKAGE
. Beginning of module'
~
SORTPROC: PROCEDURE (PTR, COUNT, RECSIZE, KEYINDEX)~;
DECLARE·PTA POINTER, (COUNT, RECSIZE, KEYINDEX) INTEGER,
• Parameters:
PTR is pointer to first record.
COUNT is number of records to be sorted.
RECSIZE is.number of bytes in each record-max is 128.
KEYINDEX is byte position within each record of a BYTE scalar
to be used as sort key ..
DECLARE RECORD BASED PTR (1) BYTE,
CURRENT (128) BYTE,
(I, J) INTEGER:
SORT
FIND:
I
PUBLIC and EXTERNAL attributes promote
program modularity,
"Bas,ed"" Variables allow manipulation of external data by
passing the base of the data structure (a pointer). This
minimizes ,the STACK space used for parameter passing, and
the execution time to perform many STACK operations.
DO J 1 TO COUNT-1:
CALL MOVB(@RECORD(J·RECSIZE),,,-,,,-=-=-,-,,-=---<.:.,RECSIZE):
10 J:
DO WHILE 10
AND RECORD((I 1)'RECSIZE - KEYINDEX)
·CURRENT(KEYINDEX):
CALL MOVB(@RECORD((I 1j'RECSIZE),
@RECORDWRECSIZE),
RECSIZE):
I~I
1:
END FIND:
The "AT" operator returns the address o1'a
variable, instead of its contents. This is very useful
in passing pOinters for based variables.
(@CURRENT, @RECORD(I'RECSIZE), RECSIZE):
END SORTPROC:
END M:
One of several PLIM built-in procedures for string
manipulation.
"End of module';'
Figure 1, Sample PL/M 86/88 Program
BENEFITS
PUM 86/88 is designed to be an efficient, costeffective solution to the special requirements of
iAPX 86 or 88 Microsystem Software Development,
as illustrated by the following benefits of PUM use:
Low Learning Effort
PL/M 86/88 is easy to learn and to use, even for the
novice programmer,
Earlier Project Completion
Critical projects are completed much earlier than
otherwise possible because PUM 86/88, a structured high-level language, increases programmer
productivity,
Lower Development Cost
Increases in programmer productivity translate immediately into lower software development costs
because less programming resources are required
for a given programmed function,
Increased Reliability
PUM 86/88 is designed to aid in the development of
reliable software (PUM 86/88 programs are simple
statements of the program algorithm). This sUbstantially reduces the risk of costly correction of errors in
systems that have already reached full production
status, as the more simply stated the program is, the
more likely it is to perform its intended function.
Easier Enhancements
and Maintenance
Programs written in PL/M tend to be self-documenting, thus easier to read and understand, This means
it is easier to enhance and maintain PUM programs
as the system capabilities expand and future products are developed.
8-134
AFN-01661A
PL/M 86/88 SOFTWARE PACKAGE
SPECIFICATIONS
Operating Environment
REQUIRED HARDWARE:
Intellec® Microcomputer Development System
- Series III or equivalent
Dual Diskette Drives
- Single- or Double-Density
System Console
- CRT or Hardcopy Interactive Device
REQUIRED SOFTWARE:
ISIS-II Diskette Operating System, V4.1 or later
Series III Operating System
Documentation Package
PL/M-86 User's Guide for 8086-based Development
Systems (121636)
OPTIONAL HARDWARE:
Universal PROM Programmer
Line Printer
ICE-86rM
ORDERING INFORMATION
Part Number
Description
MDS-313'
PLiM 86/88 Software Package
Requires Software License
'MOS is an ordering code only and is not used as a product name or trademark. MOS'" is a registered trademark of Mohawk Data Sciences
Corporation.
.
8-135
AFN·01661A
FORTRAN 86/88
SOFTWARE PACKAGE
• Features high-level language support
for floating-point calculations,
transcendentals, interrupt procedures,
and run-time exception handling
• Offers powerful extensions tailored to
microprocessor applications
• Offers upward compatibility with
FORTRAN 80
• Meets ANS FORTRAN 77 Subset
Language Specifications
• Provides FORTRAN run-time support for
iAPX 86,88-based design
• Supports iAPX 86/20, 88/20 Numeric
Data Processor for fast and efficient
execution of numeric instructions
• Provides users ability to do formatted
and unformatted I/O with sequential or
direct access methods
• Uses REALMATH Floating-Point
Standard for consistent and reliable
results
FORTRAN 86/88 meets the ANS FORTRAN 77 Language Subset Specification and includes many features of
the full standard. Therefore, the user is assured of portability of most existing ANS FORTRAN programs and of
full portability from other computer systems with an ANS FORTRAN 77 Compiler.
.
.
FORTRAN 86/88 programs developed and debugged on the iAPX 86 Resident Intellec Series III Microcomputer
Development System may be: tested with the prototype using ICE symbolic debugging, and executed on an
RMX-86 operating system, or on a user's iAPX 86,88-based operating system.
FORTRAN 86/88 is one of a complete family of compatible programming languages foriAPX 86,88 development: PUM, Pascal, FORTRAN, and Assembler. Therefore, users may choose the language best suited fora
specific problem solution.
©
Intel Corporation, 1981.
8-136
APRIL 1981
AFN-(l1653A
FORTRAN 86/88 SOFTWARE PACKAGE
FEATURES
Intel® Microprocessor Support
Extensive High-Level Language
Numeric Processing Support
FORTRAN 86/88 language features support of iAPX
86/20, 88/20 Numeric Data Processor
Single (32-bit), double (64-bit), and double extended
precision (80-bit) floating-point data types
Compiler generates in-line iAPX 86/20, 88/20 Numeric Data Processor object code for floating-point
arithmetic (See Figu re 1)
REALMATH Proposed IEEE Floating-Point Standard) for consistent and reliable results
Full support for all other data types: integer, logical,
character
Ability to use hardware (iAPX 86/20, 88/20 Numeric
Data Processor) or software (simulator) floatingpoint support chosen at link time
Intrinsics allow user to control iAPX 86/20, 88/20
Numeric Data Processor
iAPX 86,88 architectural advantages used for indexing and character-string handling
Symbolic debugging of application using ICE-86
and ICE-88 emulators
ANS FORTRAN 77 Standard
FLOATING-POINT-STATMENT
TEMPER = (PRESS - VOlUM I ~UEK) - 3.45 I (PRESS - VOlUM I QUEK)
- (PRESS - VDlUM I QUEK) * (PRESS - VDlUM I QUEK)
&
OBJECT CODE GENERATED
Intel FORTRAN-86 Compiler
IAPX 86/20, 88/20
MACHINE CODE
0013
0018
0010
0022
0025
002B
002E
0031
0034
0037
003A
0030
0040
0045
9B09060COO
9608360000
9B082E0800
9BOO01
962E083EOOOO
9B09C9
960002
9BOEE9
9B09C1
9608C8
9BOOC2
960EE1
9B091E0400
98
ASSEMBLER MNEMONICS
FlJ
FDIV
FSUB:<
FST
FOIV~
FXCrlG
;:ST
FSUBRP
FLO
FMUl
FFREE
FSUBP
FSTP
WAIT
I.,
STATEMENT # 2
VDlUM
::lUEK
PRESS
T::JS+1H
CS:@CONST
TOS+1H
TOS+2H
T:JS+1H
TOS
TOS+2H
TEMPER
Figure 1. Object Code Generated by FORTRAN 86/88 for a Floating-Point Calculation Using iAPX 86/20,
88/20 Numeric Processor
8-137
AFN-01653A
FORTRAN 86/88 SOFTWARE PACKAGE
Microprocessor Application Support
Early Project Completion
-Direct byte- or word-oriented port I/O
FORTRAN is an industry-standard, high-level
numerics processing language. FORTRAN programmers can use FORTRAN 86/88 on microprocessor projects with little retraining. Existing FORTRAN software can be compiled with. FORTRAN
86/88 and programs developed in FORTRAN 86/88
can run on other computers with ANS FORTRAN 77
with little or no change. Libraries of mathematical
programs using ANS 77 standards may be compiled
with FORTRAN 86/88.
-Reentrant procedures
-Interrupt procedures
Flexible Run-Time Support
Application object code may be executed in iAPX 86,
88-based environment of user's choice:
-a Series III Intellec Development System with Series III Operating System
-an iAPX 86,88-basedsystem with iRMX-86 Operating System
-an iAPX 86,88-based system with user-designed
Operating System
Run-time exception handling for fixed-point numerics, floating-point numerics, and I/O errors
Relocatable object libraries for complete run-time
support of I/O and arithmetic functions. In-line code
execution is generated for iAPX 86/20, 88/20 Numeric Data Processor
Application Object Code
Portability for a Processor Family
FORTRAN 86/88 modules "talk" to the resident Intellec development operating system using Intel's
standard interface for all development-system
software. This allows an application developed on
the Series III operating system to execute on iRMX/
86, or a user-supplied operating system by linking in
the iRMX/86 or other appropriate interface library. A
standard logical-record interface enables communication with non-standard I/O devices.
BENEFITS
Comprehensive, Reliable
and Efficient Numeric Processing
FORTRAN 86/88 provides a means of developing
application software for the Intel iAPX 86,88 products lines in a familiar, widely accepted, and
industry-standard programming language. FORTRAN 86/88 will greatly enhance the user's ability to
provide cost-effective software development for
Intel microprocessors as illustrated by the
following:
The unique combination of FORTRAN 86/88, iAPX
86/20, 88/20 Numeric Data Processor, and
REALMATH (Proposed IEEE Floating-Point Standard) provide universal consistency in results of
numeric computations and efficient object code
generation.
SPECIFICATIONS
REQUIRED SOFTWARE
ISIS-II Diskette Operating System V4.1 or later
Operating Environment
REQUIRED HARDWARE
Intellec® Series III Microcomputer Development
System
Documentation Package
FORTRAN 86/88 User's Guide (121539-001)
-System Console
-Doubi~-Density Dual-Diskette Drive. A Hard Disk
is recommended
Shipping Media
-Hard Disk'
Flexible Diskettes
'Recommended.
-Single- and Double-Density
8-138
AFN·01653A
PASCAL 86/88
SOFTWARE PACKAGE
Resident on iAPX 86 Based Intellec®
• Series
III Microcomputer Development
•
Supports iAPX86/20, 88/20 Numeric
Data Processors
Strict Implementation of ISO Standard
Pascal
System for Optimal Performance
II
Object Compatible and Linkable with
PL/M 86/88, ASM 86/88 and FORTRAN
86/88
III
Useful Extensions Essential for
Microcomputer Applications
!Ill
Separate Compilation with TypeChecking Enforced Between Pascal
Modules
I!l
Compiler Option to Support Full RunTime Range-Checking
ICE™ Symbolic Debugging Fully
• Supported
III
III
Implements REALMATH for Consistent
and Reliable Results
PASCAL 86/88 conforms to and implements the ISO Draft Proposed Pascal standard. The language is
enhanced to support microcomputer applications with special features, such as separate compilation, interrupt handling and direct port I/O. To assist the development of portable software, the compiler can be directed
to flag all non-standard featu res.
The PASCAL 86/88 compiler runs on the iAPX 86 Resident Intellec® Series III Microcomputer Development
System. A well-defined I/O interface is provided for run-time support. This allows a user-written operating system to support application programs as an alternate to the development system environment. Program modules compiled under PASCAL 86/88 are compatible and linkable with modules written in PUM 86/88, ASM
86/88 or FORTRAN 86/88. With a complete family of compatible programming languages for the iAPX 86, 88
one can implement each module in the language most appropriate to the task at hand.
PASCAL 86/88 object modules contain symbol and type information for program debugging using ICE-86™
emulator. For final production version, the compiler can remove this extra information and code.
Note: The Intellec~ microcomputer developme,nt system pictured here is not included with the Pascal 66/66 Software Package but merely depicts the language in its operating
environment.
The following are trademarks of Intel Corporation and may be used only to identity Intel products: BXP, CREDIT,lntellec, Multibus, i. iSSe, Multimodule, ICE, iSBX. PROMPT, iRMX,
leS, Library Manager, Promware. Insite, MeS, RMX, Intel, Megachassis, UPI, lntelevision, Micromap, ,..,Scope and the combination of iCE, leS, iSBC, iSBX, MeS, or RMX and a numerical suffix.
© Intel Corporation 1980
8-139
121660-001 Rev. A
PASCAL 86/88
FEATURES
Includes all the language features of Jensen & Wirth
Pascal as defined in the ISO Draft Proposed Pascal
Standard.
Supports required extensions for microcomputer
applications.
-Interrupt handling
Supports numerous compiler options to control the
compilation process, to INCLUDE files, flag nonstandard Pascal statements and others to control
program listings and object modules.
Utilizes the IE.EE standard for Floating-Point Arithmetic (the Intel REALMATH standard) for arithmetic
operations.
-Direct port I/O
Separate compilation extensions allow:
-Modular decomposition of large programs
Well-defined and documented run-time operating
system interfaces allow the user to execute the applications under user-designed operating systems.
-Linkage with other Pascal modules as well as
PUM 86/88, ASM 86/88 and FORTRAN 86/88.
-Enforcement of type-checking at LINK-time
BENEFITS
Provides a standard Pascal for iAPX 86, 88 based
applications.
-Pascal has gained wide acceptance as the portable application language for microcomputer
applications
-It is being taught in many colleges and universities
around the world
-It is easy to learn, originally intended as a vehicle
for teaching computer programming
-Improves maintainability: Type mechanism is
both strictly enforced and user extendable
Provides run-time support for co-processors. All
real-type arithmetic is performed on the 86/20 numeric data processor unit or software emulator.
Run-time library routines, common between Pascal
and other Intel languages (such as FORTRAN), permit efficient and consistently accurate results.
Extended relocation and linkage support allows the
user to link Pascal program modules with routines
written in other languages for certain parts of the
program. For example, real-time or hardware dependent routines written in ASM 86/88 or PUM 86/88
can be linked to Pascal routines, further extending
the user's ability to write structured and modular
programs.
-Few machine specific language constructs
Strict implementation of the proposed ISO standard
for Pascal aids portability of application programs. A
compile time option checks conformance to the
standard making it easy to write conforming
programs.
PASCAL 86/88 extensions via predefined procedures for interrupt handling and direct port I/O make
it possible to code an entire application in Pascal
without compromising portability.
Standard Intel REALMATH is easy to use and provides reliable results, consistent with other Intel
languages and other implementations of the IEEE
proposed Floating-Point standard.
PASCAL 86/88 programs "talk" to the resident
operating system using Intel's standard interface for
translated programs. This allows users to replace
the development operating system by their own
operating systems in the final application.
PASCAL 86/88 takes full advantage of iAPX 86, 88
high level language architecture to generate
efficient machine code without using timeconsuming optimization algorithms.
Compiler options can be used to control the program listings and object modules. While debugging,
the user may generate additional information such
as the symbol record information required and
useful for debugging using ICE emulation. After debugging, the production version may be streamlined
by removing this additional information.
8-140
AFN·01652A
PASCAL 86/88
SPECIFICATIONS
Operating Environment
REQUIRED HARDWARE
Intellec® Series III Microcomputer Development
System
-System Console
-Double Density Dual Diskette Drive OR Hard Disk
REQUIRED SOFTWARE
ISIS-II Diskette Operating System V4.1 or later
Documentation Package
PASCAL 86 User's Guide (121539-001)
Shipping Media
Flexible Diskettes
-Single and Double Density
ORDERING INFORMATION
Part Number
Description
MDS*-314
PASCAL 86/88 Software Package
Requires software license .
• MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Science.
8-141
AFN·01652A
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
PL/M-86 high level programming language
ASM86 macro assembler for 8086/8088
assembly language programming
CONV86 converter for conversion of
8080/8085 assembly language source
code to 8086/8088 assembly languagesource code
OH86 object-to-hexadecimal converter
LlNK86 and LOC86 linkage and
relocation utilities
LI B86 ,library manager
The 8086/8088 software development package provides a set of software development tools for the 8086 and the 8088
microprocessors and iSSC 86/12 single board computer. The package operates under the ISIS·II operating system on
Intellec Microcomputer Development Systems-Model 800 or Series II-thus minimizing requirements for additional
hardware or training for Intel Microcomputer Development System users.
The package permits 8080/8085 users to efficiently convert existing programs into 8086/8088 object code from either
8080/8085 assembly language source code or PLlM·80 source code.
For the new Intel Microcomputer Development System user, the package operating on an Intellec Model 230 Micro·
computer Development System provides total 8086/8088 software development capability.
8-142
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
PL/M·86 HIGH LEVEL PROGRAMMING LANGUAGE
Sophisticated new complier design
allows user to achieve maximum benefits
of 8086/8088 capabilities
Language Is upward compatible from
PL/M·80, assuring MCS·80/8S design
portability
Supports 16·bit signed integer and 32·bit
floating point arithmetic
Produces relocatable and linkable object
code
Supports full extended addressing
features of the 8086 and the 8088
microprocessors
Code optimization assures efficient code
generation and minimum application
memory utilization
Like its counterpart for MCS·80/85 program development, PLiM·86 is an advanced structured high level programming
language. PLlM·86 is a new compiler created specifically for performing software development for the Intel 8086 and
8088 Microprocessors.
PLlM·86 has significant new capabilities over PLlM·80 that take advantage of the new facilities provided by the 8086
and the 8088 microprocessors, yet the PLlM·86 language remains upward compatible from PLlM·80.
With the exception of interrupts, hardware flags, and tlme·critical code sequences, PLlM·80 programs may be recom·
piled under PLM·86 with little or no conversion required. PLlM·86, like PLlM·80, is easy to learn, facilitates rapid pro·
gram development, and reduces program maintenance costs.
PLiM is a powerful, structured high level algorithmic language in which program statements can naturally express the
program algorithm. This frees the programmer to concentrate on the system implementation without concern for bur·
densome details of assembly language programming (such as register allocation, meanings of assembler mnemonics,
etc.).
The PLlM·86 compiler efficiently converts free·form PLiM language statements into equivalent 8086/8088 machine in·
structions. Substantially fewer PLiM statements are necessary for a given application than if it were programmed at
the assembly language or machine code level.
Since PLiM programs are implementation problem oriented and more compact, use of PLiM results in a high degree of
engineering productivity during project development This translates into significant reductions in Initial software
development and follow·on maintenance costs for the user.
FEATURES
• Relocatable and Linkable Object Code
Major features of the Intel PLlM·86 compiler and pro·
gramming language include:
• Supports Five Data Types
-
Byte: 8·bit unsigned number
Word: 16·bit unsigned number
Integer: 16·blt signed number
Real: 32·bit floating point number
Pointer: 16·bit or 32·bit memory address indicator
• Block Structured Language
-
• Bullt·ln String Handling Facilities
-
-
• Two Data Structuring Facilities
-
Operates on byte strings or word strings
Six Functions: MOVE, COMPARE, TRANSLATE,
SEARCH, SKIP, and SET
• Automatic Support for 8086 Extended Addressing
Permits use of structured programming tech·
niques
Array: I ndexed list of same type data elements
Structure: Named collection of same or different
type data elements
Combinations of Each: Arrays of structures or
structures of arrays
Permits PLlM·86 programs to be developed and
debugged in small modules. These modules can
be easily linked with other PLlM·86 or ASM86 ob·
ject modules andlor library routines to form a com·
plete application system.
-
Three compiler options offer a separate model of
computation for programs up to 1·Megabyte In
size
Language transparency for extended addressing
• Support for ICE·86 Emulator and Symbolic Debugging
-
8-143
Debug option for Inclusion of symbol table In ob·
ject modules for In·Clrcult Emulation with sym·
bolic debugging
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
for the development of 8086 and 8088 designs.
PLlM-86 and other elements of ',SIS-i1 and the 80861
8088 Software Development Package are all that is
needed for development of software for the 8086 and
the 8088 microcomputers and iSBC 86/12 single board
computer_ This further reduces development time and
costs because expensive (and remote) time sharing of
large computers is not required. Present users of Intel
Intellec Development Systems can begin to develop
8086 and 8088 designs without expensive hardware
reinvestment or costly,retraining.
o Numerous Complier Options
-
A host of 26 compiler options including:
o
o
o
o
o
Conditional compilation
Included file or copy facility
'Two'leveis of optimization
Intra-module and inter-module cross reference'
Arbitrary placement of compiler and user files
on any available combination of disk drives
o Reentrant and Interrupt Procedures
-
May be specified as user options
SAMPLE PROGRAM
BENEFITS
STATISTICS: DO;
PLlM-86 is designed to be an efficient, cost-effective
solution to the special requirements of 8086/8088
Microcomputer Software Development, as illustrated by
the following benefits of PLlM-86 use:
o
Reduced Learnlrig Effort - PLlM-86is easy to learn
and to use, even for the novice programmer.
o
Critical projects are
completed much earlier than otherwise possible
because PLlM-86, a structured high-level language, increases programmer productivity.
I*The procedure in this mOdule computes the mean and
variance of an array of data, X, of length N + 1, according
to the method of Kahan and Parlett (University of California, Berkeley, Memo no. UCB/ERL M77/21.*1
STAT: PROCEDURE(X$PTR,N,MEAN$PTR,
VARIANCE$PTR) PUBLIC;
Earlier Project Completion -
Increases in programmer
productivity translate immediately into lower soft- ,
ware development costs because less programming
resources are required for a given programmed function.
o Lower Development Cost -
o
Increased Reliability - PLlM.-86 is designed to aid in
the development of reliable software (PLlM-86 programs are simple statements of the program
algorithm). This substantially reduces the risk of costly co'rrection of errors, in systems that have already
reached full production status, as the more simply
stated the program is, the more likely it is to perform
its intended function.
DECLARE
(X$PTR,MEAN$PTR.VARIANCE$PTR)
POINTER,X BASED X$PTR (1) REAL,
N INTEGER,
MEAN BASED MEAN$PTR REAL,
VARIANCE BASED VARIANCE$PTR REAL,
(M,Q,DIFF) REAL,
I INTEGER;
M=X(O);
M=O.O;
DO 1= 1 TO N;
DIFF=X(I)- M;
M = M + DIFF/FLOAT(I + 1);
Q= Q+ DIFF*DIFF*FLOAT(I)/FLOAT(I + 1);
Programs
written in PLiM tend to be self-documenting, thus
easier to read and understand. This means it is easier
to enhance and maintain PLiM programs as the
system capabilities expand and future products are
developed.
o Easier Enhancements and Maintenance -
o
END;
MEAN=M;
VARIANCE = Q/FLOAT(N);
END STAT;
Thelntellec Development Systems offer a cost-effective hardware base
Simpler Project Development -
END STATISTICS;
8-144
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
ASM86 MACRO ASSEMBLER
Powerful and flexible text macro facility
with three macro listing options to aid
debugging
High-level data structuring facilities
such as "STRUCTUREs" and
"RECORDs"
Highly mnemonic and compact
language, most mnemonics represent
several distinct machine instructions
Over 120 detailed and fully documented
error messages
"Strongly typed" assembler helps detect
errors at assembly time
Produces relocatable and linkable object
code
ASM86 is the "high-level" macro assembler for the 8086/8088 assembly language. ASM86 translates symbolic
8086/8088 assembly language mnemonics into 8086/8088 machine code.
ASM86 should be used where maximum code efficiency and hardware control is needed. The 8086/8088 assembly
language includes approximately 100 instruction mnemonics. From these few mnemonics the assembler can generate
over 3,800 distinct machine instructions. Therefore, the software development task is simplified, as the programmer
need know only 100 mnemonics to generate all possible 8086/8088 machine instructions. ASM86 will generate the
shortest machine instruction possible given no forward referencing or given explicit information as to the
characteristics of forward referenced symbols.
ASM86 offers many features normally found only in high-level languages. The 8086/8088 assembly language is strongly typed. The assembler performs extensive checks on the usage of variables and labels. The assembler uses the attributes which are derived explicitly when a variable or label is first defined, then makes sure that each use of the symbolln later instructions conforms to the usage defined for that symbol. This means that many programming errors will
be detected when the program is assembled, long before it is being debugged on hardware.
FEATURES
Major features of the Intel 8086/8088 assembler and
assembly language include:
• Powerful and Flexible Text Macro Facility
Macro calls may appear anywhere
Allows user to define the syntax of each macro
Built-in functions
• conditional assembly (IF-THEN-ELSE, WHILE)
• repetition (REPEAT)
• string processing functions (MATCH)
• support of assembly time I/O to console (IN,
OUT)
Three Macro Listing Options include a GEN mode
which provides a complete trace of all macro calls
and expansions
• Fully Supports 8086/8088 Addressing Modes
Provides for complex address expressions involving base and indexing registers and (structure)
field offsets.
Powerful EQU facility allows complicated expressions to be named and the name can be used as a
synonym for the expression throughout the
module.
• Powerful STRING MANIPULATION INSTRUCTIONS
Permit direct transfers to or from memory or the
accumulator.
Can be prefixed with a repeat operator for
repetitive execution with a count-down and a condition test.
• High-Level Data Structuring Capability
STRUCTURES: Defined to be a template and then
used to allocate storage. The familiar dot notation
may be used to form instruction addresses with
structure fields.
ARRAYS: Indexed list of same type data elements.
RECORDS: Allows bit-templates to be defined and
used as instruction operands andlor to allocate
storage.
• Over 120 Detailed Error Messages
Appear both in regular list file and error print file.
User documentation fully explains the occurrence
of each error and suggests a method to correct it.
8-145
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
• Generates Relocatable and Linkable Object CodeFully Compatible with LlNK86, LOC86 and LIB86
-
Permits ASM86 programs to be developed and
debugged in small modules. These mOdules can
be easily linked with other ASM86 or PLlM-86 object modules and/or library routines to form a complete application system.
• Support for ICE-86 Emulation and Symbolic Oebugglng
-
Debug options for inclusion of symbol table in
object modules for In-Circuit Emulation with symbolic debugging.
BENEFITS
The 8086/8088 macro assembler allows the extensive
capabilities of the 8086/8088 to be fully exploited. In any
application, time and space critical routines can be
effectively written in ASM86. The 8086/8088 assembler
outputs relocatable and linkable object modules. These
object modules may be easily combined with object
modules written in PLlM-86-lntel's structured, highlevel programming language. ASM86 compliments
PLM-86 as the programmer may choose to write each
module in the language most appropriate to the task
and then combine the modules into the complete applications program using the 8086/8088 relocation and
linkage utilities.
CONV86
MCS-BO/aS to MCS-B6 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
Translates 8080/8085 Assembly
Language Source Code to 8086/8088
Assembly Language Source Code
Automatically generates proper ASM·86
directives to set up a "virtual 8080"
environment that is compatible with
PLM·86
Provides a fast and accurate means to
convert 8080/8085 programs to the 8086
and the 8088, faCilitating program
portability
In support of Intel's commitment to software portability, CONV86 is offered as a tool to move 8080/8085 programs to
the 8086 and the 8088. A comprehensive manual, "MCS-86 Assembly Language Converter Operating Instructions for
ISIS-II Users" (9800642), covers the entire conversion process. Detailed methodology of the conversion process is fully
described therein.
CONV86 will accept as input an error-free 8080/8085 assembly-language source file and optional controls, and produce
as output, optional PRINT and OUTPUT files.
The PRINT file is a formatted copy of the 8080/8085 source and the 8086/8088 source fiie with embedded caution
messages.
The OUTPUT file is an 8086/8088 source file.
CONV86 issues a caution message when it detects a potential problem in the converted 8086/8088 code.
A transliteration of the 8080/8085 programs occurs, with each 8080/8085 construct mapped to its exact 8086/8088
counterpart:
-Registers
-Condition flags
-I nstructions
-Operands
-Assembler directives
-Assembler control lines
-Macros
8-146
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
Because CONV86 Is a transliteration process, there Is the possibility of as much as a 15%-20% code expansion over
the 8080/8085 code. For compactness and efficiency It is recommended that critical portions of programs be re-coded
In 8086/8088 assembly language.
Also, as a consequence of the transliteration, some manual editing may be required for converting instruction sequences dependent on:
·instruction length, timing, or encoding
-Interrupt processing
l mechanical editing procedures
-PLIM parameter passing conventions ~ for these are suggested in the converter manual.
The accompanying diagram illustrates the flow of the conversion process. Initially, the abstract program may be repre·
sented in 8080/8085 or 8086/8088 assembly language to execute on that respective target machine. The conversion
process is porting a source destined for the 8080/8085 to the 8086 or the 8088 via CONV86.
SOURCE CODE
IN 8080/80BS
ASSEMBLY LANG
EXECUTE
ON
SOURCE CODE
------
IN 808618088
ASSEMBLY LANG
ALGORITHM
ASSEMBLE
FOR
BOBOl8085
B08016085
ABSTRACT PROGRAM
II
f-------f--------
CONva6
EQUIVALENT
FUNCTION
II
f-------f--------
PORTING 80BO/8085 SOURCE CODe TO THE 808618088
8-147
.
ASSEMBLE
FOR
808616088
EXECUTe
ON
6086/8088
SOS6/S08SS0FTWARE DEVELOPMENT PACKAGE
LINK86
Automatic combination .of separately
complied or assembled 8086/8088
programs into a relocatable module
Automatic.selectlon ()f required modules
from specified libraries to satisfy
.
symbolic references
Exten·sive debug symbol manipulation,
allowing line numbets,local symbols,
and public symbols to be purged and
listed selectively
Automatic generation of a summary map
giving results of the LINK86 process
.
Abbreviated control syntax
Relocatable modules .may be merged
Into a single module suitable for
inclusion in a library
Supports "incremental" linking
Supports type checking of public and
external symbols
LINK86 combines object modules specified in the LINK86 input list into a single output module. LlNK86 combines
segments from the input modules according to the order in which the modules are listed.
Support for incremental linking is provided since an output module produced by LlNK86 can be an input to another
link. At each stage in the. Incremental linking process,unnEleded public symbols may be purged.
LlNK86 supports type checking of public and external symbols reporting an error If their types are not consistent.
LlNK86 will link any valid set of input modules without any controls. However, controls are available to control the output of diagnostic information in the LlNK86 process and to control the content of the output module.
LlNK86 allows the user to create a large program as the combination of several smaller, separately compiled modules.
After development and debugging of these component modules the user can link them together, locate them using
LOC86, and enter final testing with much of the work accomplished.
LOC86
Automatic and independent relocation
of segments. Segments may be
relocated to best match users memory
configuration
Extensive debug symbol manipulation,
allowing line numbers, local symbols,
and public symbols to be purged and.
listed selectively
Automatic generation of a summary map
giving starting address, segment
addresses and lengths,. and debug
symbols and their addresses
Extensive capability to .manipulate the
order and placement of segments in
8086/8088 memory
Abbreviated control syntax
Relocatability allows the· programmer to code programs or sections of programs without having to know the final arrangement of the object code in m e m o r y . ·
.
.
LOC86 converts relative addresses In an input module to absolute addresses. LOC86 orders the segments in the input
module and assigns absolute addresses to the segments. The sequence In which the segments in the input module
are assigned absolute addresses is determined by their order In the Input module and the controls supplied with the
command.
LOC86 will relocate any valid input module without any controls. However, controls are available to control the output
of diagnostic Information in the LOC86 process, to control the content of the output module, or both.
The program you are developing will almost certainly use some mix of random access memory (RAM), read-only
memory (ROM), and/or programmable read-only memory (PROM). Therefore, the location of your program affects both
cost and performance In your application. The relocation feature allows you to develop your program on the Intellec
development system and then simply relocate the object code to suit your application.
8-148
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
OH86
Converts an 8086/8088 absolute object
module to symbolic hexadecimal format
Converts an absolute module to a more
readable format that can be displayed
on a CRT or printed for debugging
Facilitates preparing a file for later
loading by a symbolic hexadecimal
loader, such as the iSBC Monitor or
Universal PROM Mapper
The OH86 command converts an 8086/8088 absolute object module to the hexadecimal format. This conversion may
be necessary to format a module for later loading by a hexadecimal loader such as the ISBC 86/12 monitor or Universal
Prom Mapper. The conversion may also be made to put the module in a more readable format that can be displayed or
printed.
The module to be converted must be in absolute format; the output from LOC86 is in absolute format.
UB86
LlB86 is a library manager program
which allows you to:
Create specially formatted files to
contain libraries of object modules
Maintain these libraries by adding or
deleting modules
Libraries can be used as input to LINK86
which will automatically link modules
from the library that satisfy external
references in the modules being linked
Abbreviated control syntax
Print a listing of the modules and
public symbols in a library file
Libraries aid in the Job of building programs. The library manager program, LlB86, creates and maintains files containing object modules. The operation of LlB86 is controlled by commands to Indicate which operation LlB86 is to perform. The commands are:
CREATE - creates an empty library file
ADD - adds object modules to a library file
DELETE - deletes modules from a library file
LIST - lists the module directory of library files
EXIT - terminates the LlB86 program and returns control to ISIS-II
8-149
.8086/8088 SOFTWARE DEVELOPMENT PACKAGE
I$IS·II
TEXT EDITOR
PLlM·86
SOURCE
RELOCAT ABLE
OBJECT MODULE
USER
SYSTEM
SDK·B6
lINK86
AND
LOCSS
ISIS·II
TEXT EDITOR
ASM86
SOURCE
RELOCATABLE
OBJECT MODULE
ASM80/85
SOURCE
87150
iSBC 86112
ICE·86
UPM
8086/8088 SOFTWARE DEVELOPMENT PACKAGE
SPECIFICATIONS
Operating Environment
Required Hardware
Documentation Package
Intellec Microcomputer Development System
PLlM-86 Programming Manual (9800466)
ISIS-II PL/M-B6 Complier Operator's Manual (9B0047B)
MCS-B6 User's Manual (9800722)
MCS-86 Software Development Utilities Operating
Instructions for ISIS-II Users (9800639)
MCS-86 Macro Assembly Language Reference Manual
(9800640)
MCS-B6 Macro Assembler Operating Instructions for
ISIS-II Users (9B00641)
MCS-86 Assembly Language Converter Operating
Instructions for ISIS-II Users (9B00642)
Universal PROM Programmer User's Manual
(9800B19A)
- MDS-BOO, MDS-B88
- Series II MDS-220 or MDS-230
64K Bytes of RAM Memory
Dual Diskette Drives
-
Single or Double' Density
System Console
-
CRT or Hardcopy Interactive Device
Optional Hardware
Universal PROM Programmer
Line Printer'
ICE-86lM '
Raqulred Software
Flexible Diskettes
ISIS-II Diskette Operating System
-
-
Single or Double' Density
• Recommended
ORDERING INFORMATION
Part Number Description
MDS-311
BOB6/B088 Software Development
Package
Also available In the following development support
packages:
Part Number Description
SP86A-KIT
SPB6A Support Package (for Intellec
Model BOO)
Includes ICE-B6 In-Circuit Emulator
(MDS-86-ICE) and BOB6/BOBB Software
Development Package (MDS-311)
SPB6B-KIT
SPBBB Support Package (for Series II)
Includes ICE-B6 In-Circuit Emulator
(MDS-86-ICE), BOB6/BOBB Software
Development Package (MDS-31l),
and Series II Expansion Chassis
(MDS-201)
8-151
Single and Double' Density
8087
SOFTWARE SUPPORT PACKAGE'
• ProgriJm Generation for the 8087 .
Numeric Data Processor on the.
Intellec® Microcomputer Development
System
• 8087 Emulator Duplicates Each 8087..
Floating-Point Instruction in Software,
for Evaluation of Prototyping, or for
Use in an End Product
• Consists of: 8086/8087/8088 Macro
Assembler, 8087 Software Emulator
• Macro Assembierand 8087 Emulator
are Fully Compatible with Other
8086/8088 Development Software
• Macro Assembler Generates Code for
8087 Processor or Emulator, While
Also Supporting the 8086/8088
Instruction Set
• Implementation of the IEEE Proposed
Floating-Point Standard (the Intel®
Realmath Standard)
The 8087 Software Support Package is an optional extention of Intel's 8086/8088 Software Development
Package that runs under ISIS"" on an Intellec or Series II Microcomputer Development System.
The 8087 Software Support Package consists of the 8086/8087/8088 Macro Assembler, and the Full 8087
Emulator. The assembler is functional superset of the 8086/8088 Macro Assembler, and includes instructions for over sixty new floating-point operations, plus new data types supported.by the 8087..
a
The 8087 Emulator is an 8086/8088 object module that simulates the environment of the 8087, and executes
each floating-point operation using software algorithms. This emulator functionally duplicates the operation
of the 8087 Numeric Data Processor.
. . . .
Also included in this package are interface libraries to link with 8086/8087/8088 object modules, which are
used for specifying whether the 8087 Processor or the 8087 Emulator is to be used. This enables the run-time
environment to be invisible to the programmer at assembly time.
The following are trademarks of Intel Corporation and may,be used only to identify Intel products: BXP, CREDIT,lntellec, Multibus, i, iSeC, Multimodule, ICE, iSeX, PROMP:r, iRMX,
ICS, Library Manager. Prom ware, Insite, MeS. RMX, Intel. Megachassis, UPI. Intelevision, Micromap, "Scope and the combination of iCE, ICS, ISeC, iSeX, MeS, or AMX and a
~~~~:C~~~~~f:=tion 1980
8-152
121653-001 Rev. A
8087 SOFTWARE SUPPORT PACKAGE
FUNCTIONAL DESCRIPTION
8086/8087/8088 Macro Assembler
The 8086/8087/8088 Macro Assembler translates
symbolic macro assembly language instructions
into appropriate machine instructions. It is an extended version of the 8086/8088 Macro Assembler,
and therefore supports all of the same features and
functions, such as limited type checking, conditional assembly, data structures, macros, etc. The
extensions are the new instructions and data types
to support floating-point operations. Realmath
floating-point instructions (see Table 1) generate
code capable of being converted to either 8087 instructions or interrupts for the 8087 Emulator. The
Processor/Emulator selection is made via interface
libraries at LINK-time. In addition to the new
floating-point instructions, the macro assembler
also introduces two new 8087 data types: aWORD
(8 bytes) and TBYTE (ten bytes). These support the
highest precision of data processed by the 8087.
Full 8087 Emulator
The Full 8087 Emulator is a 16-kilobyte object module that is linked to the application program for
floating-point operations. Its functionality is identical to the 8087 chip, and is ideal for prototyping and
debugging floating-point applications. The
Emulator is an alternative to the use of the 8087 chip,
although the latter executes floating-point applications up to 100 times faster than an 8086 with the
8087 Emulator. Furthermore, since the 8087 is a
"co-processor," use of the chip will allow many. operations to be performed in parallel with the 8086.
Table 1. 8087 Instructions
Arith metic Instructions
Processor Control Instructions
Addition
FADD
FADDP
FIADD
FINIT/FNINIT
Add real
Add real and pop
Integer add
Subtraction
FSUB
FSUBP
FISUB
FSUBR
FSUBRP
FISUBR
Subtract real
Subtract real and pop
Integer subtract
Subtract real reversed
Subtract real reversed and
pop
Integer subtract reversed
Multiplication
FMUL
FMULP
FIMUL
Multiply real
Multiply real and pop
Integer multiply
Division
rDIV
FDIVP
FIDIV
FDIVR
FDIVRP
FIDIVR
Divide real
Divide real and pop
Integer divide
Divide real reversed
Divide real reversed .and
pop
Integer divide reversed
FABS
FCHS
Disable interrupts
FENI/FNENI
Enable interrupts
FLDCW
Load control word
FSTCW/FNSTCW
Store control word
FSTSW/FNSTSW
Store status word
FCLEX/FNCLEX
Clear exceptions
FSTENV/FNSTENV
Store environment
FLDENV
Load environment
FSAVE/FNSAVE
Save state
FRSTOR
Restore state
FINCSTP
Increment stack pointer
FDECSTP
Decre,ment stack pointer
FFREE
Free reg ister
FNOP
No operation
FWAIT
CPU wait
Comparison Instructions
FCOM
Other Operations
FSQRT
FSCALE
FPREM
FRNDINT
FXTRACT
Initialize processor
FDISI/FNDISI
Square root
Scale
Partial remainder
Round to integer
Extract exponent and
significand
Absolute value
Change sign
B-153
Compare real
FCOMP
Compare real and pop
FCOMPP
Compare real and pop
twi.ce
FICOM
Integer com pare
FicOMP
Integer compare and pop
FTST
Test
FXAM
Examine
AFN-01574A
8087 SOFTWARE SUPPORT PACKAGE
Table 1, ,8087 Instructions (cont'd)
Transcendental Instructions
Data..Transfer Instructions
FPTAN
Partial tangent
FPATAN
Partial arctangent
F2XM1
2'-1
FYL2X
y. 10g,X
y. 10g,(X+ 1)
FYL2XP1
Real Transfers
FLD
FST
FSTP
FXCH
Load real
Store real
Store real and pop
Exchange registers
Inleger Transfers
Integer load
Integer store
Integer store and pop
FILD
FIST
FISTP
Constant Instructions
FLDZ
Load +0,0
FLD1
Load +1,0
FLDPI
Load
FLDL2T
Load log,10
FLDL2E
Load log,e
Packed Decimal Transfers
FBLD
11'
FLDLG2
Load log 102
FLDLN2
Load log,2
FBSTP
Packed decimal (BCD)
load
Packed decimal (BCD)
store and pop
SPECIFICATIONS
REQUIRED SOFTWARE
Operating Environment
ISIS-II Diskette Operating System
-Single or Double Density
REQUIRED HARDWARE
Intellec® Microcomputer Development System
-Model 800
-Series, II (Models 220, 225 or equivalent)
64K Bytes of RAM Memory
Minimum One Diskette Drive
-Single or Double' Density
System Console
-CRT or Hardcopy Interactive Device
OPTIONAL HARDWARE
Universal PROM Programmer'
Line Printer'
'Recommended
8086/8088 Software Development Package
Documentation Package
8086/8087/8088 Macro Assembly Language Reference Manual for 8080/808S-Based Development
Systems (121623-001)
8086/8087/8088 Macro Assembler Operating Instructions for 8080/808S-Based Development Systems (121624-001)
The 8086 Family Users Manual Supplement for the
8087 Numeric Data Processor (121586-001)
Shipping Media
1 Single and 1 Double Density Diskette
ORDERING INFORMATION
Part Number
Description
MDS'-38?
808? Software Support Package
Requires Software License
*MDS is an ordering code only and is not used as a product name or trademark, MDS" is a registered trademark of Mohawk Data Sciences
Corporation,
B-154
AFN-01574A
8089 ASSEMBLER SUPPORT PACKAGE
8089 I/O processor program generation
on the Intellec Microcomputer
Development System.
Relocatable object module compatible
with the 8086 and 8088 Microprocessors.
Includes software development utilities
to facilitate 8089 design.
-LIN K86: Combines 8086 or 8088 object
modules with 8089 object
modules and resolves
external references.
-LOC86: Assigns absolute memory
addresses to 8089 object
modules.
-OH86:
Supports 8089·based addressing modes
with a structure facility that enables easy
access to based data.
Fully detailed set of error messages.
Converts 8086/8088/8089
object code to symbolic
hexadecimal format.
-UPM86: . A PROM programming aid
which has been updated to
support PROM programming
for 8086, 8088 and 8089
applications.
The 8089 Assembler Support Package extends Intellec microcomputer development system support to the 8089 i/O
Processor. The assembler translates 8089 assembly language source instructions into appropriate machine operation codes. The 8089 Assembler Support Package allows the programmer to fully utilize the capabilities of the 80891/0
Processor.
8-155
8089 ASSEMBLER SUPPORT PACKAGE
A sample assembly listing is shown in table 1.
FUNCTIONAL DESCRIPTION
The 8089 Assembler Support Package contains the 8089
assembler (ASM89) as well as LlNK86 and LOC86relocation and linkage utilities, OH86-8086/8088/8089
object code to hexadecimal converter, and UPM86PROM programming software updated to program object
code in the 8086 formats. ASM89 translates symbolic
8089 assembly language instructions into the appropriate machine operation codes. The ability to refer to .
program addresses with symbolic names eliminates the
errors of hand translation and makes it easier to modify
programs when adding or deleting instructions.
ASM89 provides relocatable object module compatibility with the 8086 and 8088 microprocessors. This
object module compatibility, along with the 8086/8088
relocation and.linkage utilities, facilitates the designing
of the 8089 into an 8086 or 8088 system.
t i l l - I I " " ASUIIILU
v,
I
~SS£".t.Y
OF "DDUlE CINSaL
DUEtr NODULE PUCEa IN :F"tONSOL au
IIISSE,,'UI IHYDK£O IY IISrI" tINSeL SIC
.,
I CONSOLE
l ,
SECMENT
INITIUIZE U1S tRT AND 8H9 UUOUD tQNnOLLUS
'CONTROL
,
18U5'OIl'S
P/IIRA',:
NUUI,:
as
os
l
I
j
PUAIIETU PORT
•
1112
,
STAns'
os
I
,
~fIo'UVCa'!I'AND
IIIl
"
i
ST"tUS/C'O"".NDPOItT
~
1 . .1
'11'
II
U
:::~
: 8Z7tPORTS
NULLU'
as
stAHI'D5
IJ
:: CDNTIIO~
. . I.
11l1.IU
...... ue 12 II
.... lue.1 4F
. . Ie
POtT
(NOS
"
IIOY'
17
lIoYII tCAI STAT7S..
::
U4C I ' Dl
3
I
U.4I18H
,$£T PORT IIASE MDDIIESS
:
INITIALIZE 82'5
:~::: :~:: ;:::~~:::~II
1111
1114
IUt .. u
IA4CIIU
21
~~
IIOY81 rCAIPAR!l75.611"
MOYB! I till I ~Mh'5, LiN
1111
IIIC
U4t" II
U4C" 31
23
24
IIDY81 tCAI
Il(t'o'li ICAI
SUT~i,'
~UT",UII
: IIiITlAlIZ£ B2H
"
"
.
26CIlIISOl[EHDS
DHN YAlIlt n"
---------- ----
,
,
"·
·
ASM89 fully supports the based addressing modes of
the 8089. A structure facility in the assembler provides
easy access to based data. The structure facility allows
the user to define a template that enables accessing of
based data symbolically.
"
1111
1111
1111
1113
1111
lin
I . .,
""
.":~:
m
'"
'"
~::~:~~
HlllUI
NIILLI2
PARA?S
STAPS
STAn,
Table 1. Sample 8089 Assembly listing
Required Software
SPECIFICATIONS
ISIS-II Diskette Operating System
Operating Environment
-Single or Double· Density
Required Hardware
Intellec Microcomputer Development System
-MDS-800, MDS-888
Documentation Package
-Series II Models 220 or 230
8089 Assembler User's Guide (9800938)
64K Bytes of RAM Memory
8089 Assembler Pocket Reference (9800936)
Minimum One Diskette Drive
MCS-86 Software Development Utilities
Operating Instructions for ISIS-II User's (9800639)
-Single or Double" Density
MCS-86 Absolute Object File Formats (9800821)
System Console
Universal PROM Programmer User's Manual (9800819)
-CRT or Hardcopy Interactive Device
Optional Hardware
Flexible Diskettes
Universal PROM Programmer·
Line Printer·
-Single and Double· Density
ORDERING INFORMATION:
Part Number
Description
MDS-312
8089 Assembler Support Package
8-156
6Recommended
ICE-86ATM
iAPX 86 IN-CIRCUIT EMULATOR
• Real-Time In-Circuit Emulation of iAPX
86 Microsystems
• Emulate Both Minimum and Maximum
Modes of 8086 CPU
• Full Symbolic Debugging
• Breakpoints to Halt Emulation on a
Wide Variety of Conditions
• Comprehensive Trace of Program
Execution
.
• Disassembly of Trace or Program
Memory from Object Code into
Assembler Mnemonics
.. Software Debugging With or Without
User System
.. Handles Full 1 Megabyte
Addressability of iAPX 86
• Enhance Existing ICE-86™ Emulators
to ICE-86A™ Capabilities with
.
ICE-86L1™ Upgrade Package
The Intel® ICE-86A In-Circuit Emulator provides sophisticated hardware and software debugging capabilities
for iAPX 86 microsystems and iAPX 86 Single-Board Computers. These capabilities include In-Circuit Emulation for the 8086 Central Processing Unit plus extensions to debug systems including the 80891/0 Processor
and 8087 Numeric Processor Ex~ension. The emulator includes three circuit boards which reside in any
Intellec® Microcomputer Development System. A cable and buffer box connect the Intellecsystem to the user.
system by replacing the user's 8086, thus extending powerful Intellec system debugging functions into the
user system. Using the ICE-86A module, the designer can execute prototype 8086 or 8089 software in
continuous or single~step modes and can substitute blocks of Intellec system memory for user equival~nts.
Breakpoints allow the user to stop emulation on user-specified conditions of the iAPX 86 system, and the trace
capability gives a detailed history of the program execution prior to the break. All user access to the prototype
system software may be done symbolically by referring to the source program variables and labels.
The ICE-86Uln-Circuit Emulator upgrade package converts any existing ICE-86 module (non"A version) tothe
capabilities of an ICE-86A module.
ICE-86A™ IN-CIRCUIT EMULATOR
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
3. When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-86A module is then used for real-time
emulation of the 8086 to debug the system as a
completed unit.
The ICE-86A emulator allows hardware and software
development to proceed interactively. This is more
effective than the traditional method of independent
hardware and software development followed by
system integration. With the ICE-86A module, prototype hardware can be added to the system as it is
designed. Software and hardware testing occurs
while the product is being developed.
Thus the ICE-86A module provides the user with the
ability to debug a prototype or production system at
any stage in its development without introducing
extraneous hardware or software test tools.
Conceptually, the ICE-86A emulator assists three
stages of development:
SYMBOLIC DEBUGGING
1. It can be operated without being connected to
the user's system, so the ICE-86A module's
debugging capabilities can be used to facilitate
program development before any of the user's
hardware is available.
Symbols and PUM statement numbers may be substituted for numeric values in any of the ICE-86A
emulator commands. This allows the user to make
symbolic references to I/O ports, memory addresses, and data in the user program. Thus the user
need not remember the addresses of variables or
program subroutines.
2. Integration of software and hardware can begin
when any functional element of the user system
hardware is connected to the 8086 socket.
Through ICE-86A emulator mapping capabilities,
Intellec memory, ICE module memory, or diskette
memory can be substituted for missing prototype
memory. Time-critical program modules are
debugged before hardware implementation by
using the 2K-bytes of high-speed ICE-resident
memory. As each section of the user's hardware is
completed, it is added to the prototype. Thus
each section of the hardware and software is
"system" tested as it becomes available.
Symbols can be used to reference variables, procedures, program labels, and source statements. A
variable can be displayed or changed by referring to
it by name rather than by its absolute location in
memory. Using symbols for statement labels, program labels, and procedure names simplifies both
tracing and breakpoint setting. Disassembly of a
section of code from either trace or program
memory into its assembly mnemonics is readily
accomplished.
PLUG INTO
USER
8086 SOCKET
BUFFER BOX
, -_ _ _Y~.C~AB~L~E
~X~.C~A~BL~E______________________- - ,
r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --,
I .... ____ -,
I
I
I
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II
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L ____ - I
T·CABLE
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IN~~~TEC
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AUXILLIARY CONNECTOR
L ____________________________
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Figure 1. ICE-86A™ Eniulator Block Diagram
8-158
AFN-Q1950A
ICE-86A™ IN-CIRCUIT EMULATOR
A typical iAPX 86 development configuration. It is based on Intellec® Series III Development System, which
hosts the ICE-86ATM emulator. The ICE-86ATM module is shown connected to a user prototype system, In this
case, an SDK-86.
Furthermore, each symbol may have associated
with it one of the data types BYTE, WORD, INTEGER,
SINTEGER (for short, 8-bit integer), POINTER,
REAL, OREAL, or TREAL. Thus the user need not
remember the type of a source program variable
when examining or modifying it. For example, the
command "!VAR" displays the value in memory of
variable VAR in a format appropriate to its type, whiie
the command "!VAR = !VAR + 1" increments the
value of the variable.
The user symbol table generated along with the object file during a PUM-86, PASCAL-86 or FORTRAN86 compiiation or an ASM-86 assembly is loaded into
memory along with the user program which is to be
emulated. The user can utilize the avaiiable symbol
table space more efficiently bl using the SELECT
option to choose which program modules-will have
symbols loaded in the symbol table. The user may
also add to this symbol table any additional symbolic
values for memory add resses, constants, or
variables that are found useful during system
debugging.
The ICE-86A module provides access through symbolic definition to all of the 8086 registers and flags.
The READY, NMI, TEST, HOLD, RESET, INTR,
MN/MX, and RQ/GT pins of the 8086 can also be
read. Symbolic references to key ICE-86A emulation
information are also provided.
8-159
MACROS AND COMPOUND COMMANDS
The ICE-86A module provides a programmable diagnostic facility which allows the user to tailor its operation using macro commands and compound
commands.
A macro is a set of ICE-86A commands which is given
a single name. Thus, a sequence of commands
which is executed frequently may be invoked simply
by typing in a single command. The user first defines
the macro by entering the entire sequence of commands which he wants to execute. He then names
the macro and stores it for future use. He executes
the macro by typing its name and passing up to ten
parameters to the commands in the macro. Macros
may be saved on a disk file for use in subsequent
debugging sessions.
Compound commands provide conditional execution of commands (IF). and execution of commands
until a condition is met or until they have been executed a specified number of times (COUNT,
REPEAT).
Compound commands and macros may be nested
any number of times.
AFN-01950A
ICE-86A ™ IN-CIRCUIT EMULATOR
MEMORY MAPPING
Memory for the user system can be resident in the
user system or "borrowed" from the Intellec System
through the ICE-86A emulator's mapping capability.
The speed of run emulation by the ICE-86A module
depends on which mapping options are being used.
The ICE-86A emulator allows the memory which is
addressed by the 8086 to be mapped in 1K-byte
blocks to:
emulation and provide a detailed trace of execution
in any part of the user's program. A summary of the
emulation commands is shown in Table 1.
Table 1. Summary of ICE-86ATM Emulation
Commands
Command
GO
1. Physical memory in the user's system, which provides 100 percent real-time emulation at the usersystem clock rate (up to 5 MHz) with no wait
states.
2. Either of two 1K-byte blocks of ICE-86A module
high-speed memory, which allow nearly fullspeed emulation (with two additional wait states
per 8086-controlled bus cycle).
3. Intellec System memory, which provides emulation at approxi mately 0.02 percent of real-ti me with a
5 MHz clock.
4. A random-access diskette file, with emulation
speed comparable to Intellec System memory, except the emulation must wait when a new page is
accessed on the diskette.
The user can also designate a block of memory as
non-existent. The ICE-86A module issues an error
message when any such "guarded" memory is addressed by the user program.
As the user prototype. progresses to include
memory, emulation becomes real time.
OPERATION MODES
Description
Initializes emulation and allows the user to
specify the starting point and breakpoints.
Example:
GO FROM .STARTTILL .DELAY EXECUTED
where START and DELAY are statement
labels.
STEP
Allows the user to single-step through the
program.
Breakpoints: The ICE-86A module has two breakpoint registers that allow the user to halt emulation
when a specified condition is met. The breakpoint
registers may be set up for execution or nonexecution breaking. An execution breakpoint consists of a single address which causes a break
whenever the 8086 executes from its queue an .instruction byte which was obtained from the address.
A non-execution breakpoint causes an emulation
break when a specified condition other than an instruction execution occurs. A non-execution breakpoint condition, using one or both breakpoint
registers, may be specified by anyone of or a combination of:
1. A set of address values. Break on a set of address
values has three valuable features:
a. Break on a single address.
The ICE-86A software is a RAM-based program that
provides the user with easy-to-use commands for
initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system parameters. ICE-86A commands are
configured with a broad range of modifiers which
provide the user with maximum flexibility in describing the operation to be performed,
Emulation
Emulation commands to the ICE-86A emulator control the process of setting up, running and halting an
emulation of the user's iAPX 86 System. Breakpoints
and tracepoints enable the ICE-86A module to halt
B-160
b. The ability to set any number of breakpoints
within a limited range (1024 bytes maximum)
of memory.
c. The ability to break in an unlimited range. Execution is halted on any memory access to an
address greater than (or less than) any 20-bit
breakpoint address.
2. A particular status of the 8086 bus (one or more
of: memory or I/O read or write, instruction fetch,
halt, or interrupt acknowledge).
3. A set of data values (features comparable to
break on a set of address values, explained in
point one).
4. A segment register (break occurs when the register is used in an effective address calculation).
AFN-01950A
inter
ICE-86A™ IN-CIRCUIT EMULATOR
Emulation break can also be set to occur on an
external signal condition. An external breakpoint
match output and emulation status lines are provided on the buffer box. These allow synchronization
of other test equipment when a break occurs or
when emulation is begun.
Tracepoints: The ICE-86A module has two
tracepoint registers which establish match conditions to conditionally start and stop trace collection.
The trace information is gathered at least twice per
bus cycle, first when the address signals are valid
and second when the data signals are valid. If the
8086 execution queue is otherwise active, additional
frames of trace are collected.
Each trace frame contains the 20 address/data lines
and detailed information on the status of the 8086.
The trace memory can store 1,023 frames, or an
average of about 300 bus cycles, providing ample
data for detemining how the 8086 was reacting prior
to emulation break. The trace memory contains the
last 1,023 frames of trace data collected, even if this
spans several separate emulations. The user has the
option of displaying each frame of the trace data or
displaying by instruction in actual ASM-86 Assembler mnemonics. Unless the user chooses to disable
trace, the trace information is always available after
an emulation.
Interrogation and Utility
Interrogation and utility commands give th'euser
convenient access to detailed information about the
user program and the state of the 8086 that is useful
in debugging hardware and software. Changes can
be made in both memory and the 8086 registers,
flags, input pins, and I/O ports. Commands are also
provided for various utility operations such as loading and saving program files, defining symbols and
macros, displaying trace data, setting up the
memory map, and returning control to ISIS-II.A summary of the basic interrogation and utility Commands is shown in Table 2.
Table 2. Selected ICE-BSA™ Module Interrogation and Utility Commands
Memory/Register Commands
Display or change the contents of:
• Memory
• BOB6 Registers
• 8086 Status flags
• 8086 Input pins
• 80B6 I/O ports
• ICE-86A Pseudo-Registers (e.g. emulation timer)
RQ/GT
Set or display the status of the Request/Grant facility which'
enables the ICE-8SA module to share the system bus with
coprocessors.
Memory Mapping Commands
Display, declare, set, or reset the ICE-86A memory mapping.
CAUSE
Display the cause of the most recent emu lation break.
BUS
Display which device in the user's iAPX 86 system is currently master of the system bus.
Symbol Manipulation Commands
Display any or all symbols, program modules, and program
line numbers and their associated values (locations in
memory).
Set the domain (choose the particular program module) for
the line numbers.
Define new symbols as they are needed in debugging.
Remove any or all symbols, modules, and program
statements.
Change the value of any symbol.
Select program modules whose' symbols will be used in
debugging.
PRINT
Display the specified portion of the trace memory.
LOAD
Fetch user symbol table and object code from the inputfile.
EVALUATE
Display the value of an expression in binary, octal, decimal,
hexadecimal, and ASCII.
CLOCK
Select the internal (ICE-86A module provided, for standalone mode only) or an external (user-provided)· system
clock.
TYPE
Assign or change the type of any symbol in the symbol table.
RWTIMEOUT
Allows the user to time out READ/WRITE command signals
based on the time taken by the 8086 to access lritellec
memory or diskette memory.
DASM
Disassemble user program memory intoASM-86Assembler
mnemonics.
ENABLE/DISABLE RDY
Enable or disable logical AND of ICE-BSA emulator Ready
with the user Ready signal for accessing Intellec memory,
ICE memory, or diskette memory.
8-161
AFN-D1950A
ICE-86A ™ IN-CIRCUIT EMULATOR
both the 8086 and 8089 microprocessors), or remote
RAM (accessible by the 8089 lOP only). The user may
request execution to begin at any location and continue until normal termination, a specified breakpoint is reached, or the program is otherwise
aborted. If a program is modified during a debugging session, RBF-89 can save the latest version by
copying it from application system memory to a diskette fi.le.
iAPX 86/20 DEBUGGING
The ICE-86A module has the extended capabilities to
debug iAPX 86/20 microsystems which contain both
the 8086 microprocessor and the 8087 Numeric
Processor Extension (NPX). An iAPX 86/20 system is
configured in the 8086's "maximum" mode and
communication between the processors is accomplished through the RQ/GT signals. Debugging can
be done either using the 8087 chip itself (in which
case the 8086 ESCAPE instruction is interpreted as a
floating point instruction) or using the 8087
software emulator E8087 (where the 8086 INTERRUPT instruction is interpreted as a floating point
instruction). Three ne\l\l data types are defined to use
the NPX:
Breakpoints
REAL (4 byte Short Real)
OREAL (8 byte Long Real)
TREAL (10 byte Temporary Real)
RBF-89 supports setting up to twelve breakpoints
(six per 8089 channel) in the user program. RBF-89
implements each breakpoint by inserting a HALT
instruction at the breakpoint location, while saving
the overwritten instruction in temporary storage.
When a breakpoint is reached during program execution the program halts. At this point the user can
examine 8089 registers, flags, and memory, and optionally resume program execution. The invoked
breakpoint address is recorded in one of two breakpoint registers-one register for each 8089 channel.
Through simple RBF-89 commands the user can
display or change the contents of these registers.
While the 8087 NPX is not a programmable part, it
does interact closely with the 8086 and can execute
instructions in parallel with it. The ICE-86A module
provides information abo.ut the relative timing of
instruction execution in each processor so that the
complete system can be debugged. Other debugging capabilities available through the ICE-86A
module are: symbolically disassemble NPX call instructions from memory or trace history; display or
change the control, status and flag values of the
NPX; display the NPX stack either in hexadecimal or
disassembled form; and display the last instruction
address, last operand, and last operand address.
As in the ICE-86A emulator, the RBF-89 extension
accepts symbolic references for variables and
labels, including symbols in the symbol table
generated by the ASM-89 assembler.
iAPX 86/11 DEBUGGING
Through RBF-89, the user can display and change
the contents of :
The 8089 Real-Time Breakpoint Facility (RBF-89) is
an extension of the ICE-86A emulator that aids in
testing and trouble-shooting iAPX 86/11 systems designed around a combination of the 8086 CPU and
the 8089 Input/Output Processor'(IOP). RBF-89 interrogates 8089 registers, sets breakpoints in 8089
programs, and performs its other functions by preparing special control blocks in application system
memory. It then issues input/output channelattention commands to the 8089 in the user's system
to perform these functions. While using the RBF-89
extension, the user can also enter and execute the
other standard ICE-86A emulator commands.
RBF~89 allows the user to load his application
(channel) program from diskette into 8089 lOP
memory and execute it in real time. The program can
reside in either local (system) RAM (accessible by
Symbolic Debugging
-
memory, which can be displayed as either
numeric data or disassembled (8089 assemblylanguage mnemonic) code.
-
all 8089 registers except the channel control
pointer (CCP) and status flags.
Multiprocessor Operation
The ICE-86A emulator and RBF-89 support 8089
configurations in both local and remote modes. The
ICE-86A emulator may be operating either in minimum or maximum mode. In maximum mode, the
8086 RQ/GT lines are employed. This is required for
the 8089 local mode configuration to provide local
bus arbitration between the two processors. Using
RBF-89, the user can:
B-162
AFN.()1950A
ICE-86A™ IN-CIRCUIT EMULATOR
Set RQ/GT to operate for a local or remote
configuration.
Display status to determine which processor controls the system bus.
Start and halt 8089 channel programs.
RBF-89 permits the 8089 and emulated 8086 to run
simultaneously as well as sequentially. The user can
specify breakpoints and begin program execution in
three operating sequences:
Set breakpoints, start the 8089, and return control
to the console until a breakpoint is reached or the
program runs to completion or is aborted. Use this
sequence when the 8086 and 8089 programs do
not need to be executed simultaneously.
Set breakpoints, start the 8089, return control to
the console, and start the 8086. This sequence lets
both microprocessors run simultaneously.
Set breakpoints, start the 8086, and allow that
program to drive the 8089 program in a master/slave relationship. This sequence would be
used, for instance, to verify the 8086 communication driver program.
program, running on the 8089, reads and writes
data to and from 8089 memory and registers, and
sets and removes breakpoints in the user's task
program.
The 200 bytes of RAM required by the utility program must be accessible to both the ICE-86A
emulator and the 8089.
DC CHARACTERISTICS OF THE
ICE-86A™ MODULE USER CABLE
1. Output Low Voltages [VodMax)=O.4V]
IOL (Min)
ADO-AD15
A16/S3-A19/S7, BHE/S7, RD,
lOCK, QSO, QS1, SO, S1, S2,
WR, M/iQ, DT/R, DEN, ALE,
INTA
HlDA
RBF-89 is furnished as a superset of the ICE-86A
emulator software. Its main components are:
A HOST PROGRAM that resides in Intellec development system RAM, where it serves as an extension of the ICE-86A emulator's software driver.
This program, executed by the development system, translates the user's keyboard input into lowlevel directives that can be processed by the
RBF-89 control program (described below), and
converts information supplied by the control program into easily understood display output.
A CONTROL PROGRAM that resides in 'ICE-86A
emulator memory. Running on the emulator's 8086
microprocessor, the control program monitors
such operations as preparing program control
blocks for communication with the 8089 microprocessor; issuing commands to the 8089 to start,
terminate, and continue the 8089 task program;
and directing the 8089 to start execution of the
RBF-89 utility program (described below).
A UTILITY PROGRAM that resides in the 8089 RAM
in the user's prototype application system. This
8-163
7 mA
16 mA
2. Output High Voltages [VOH (Min)=2.4V]
IOH (Min)
ADO-AD15
RBF-89 System Components
12 mA
(24 mA @ 0.5V)
8 mA
(16 mA @ 0.5V)
A16/S3-A19/S7, BHE/S7, RD,
lOCK, QSO, QS1, SO, S1, S2,
WR, M/IO, DT/R, DEN, ALE,
INTA, HlDA
RQ/GT
-3 mA
-2.6 mA
250 mA
3. Input Low Voltages [VIL (Max)=O.8V]
IlL (Max)
ADO-AD15
NMI, ClK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1 J.Lf to GND)
-0.2
-0.4
-0.8
-1.4
-3.3
mA
mA
mA
mA
mA
4. Input High Voltages [VIH (Min)=2.0V]
IIH (Max)
ADO-AD15
NMI, ClK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1 J.LF to GND)
80J.LA
20 J.LA
40J.LA
-0.4 mA
-1.1 mA
5. No current is taken from the user circuit at
Vee pin.
AFN·01950A
ICE-86A™ IN-CIRCUIT EMULATOR
SPECI FICATIONS
Physical Characteristics
ICE-86A Operating Environment
PRINTED CIRCUIT BOARDS
Width: 12.00 in (30.48 cm)
Height: 6.75 in (17.15 cm)
Depth: 0.50 in (1.27 cm)
Packaged Weight: 9.00 Ib (4.10 kg)
REQUIRED HARDWARE
Intellec microcomputer development system with:
1. Three adjacent slots for the ICE-86A module.
2. 64K bytes of Intellec memory. If user prototype
program memory is desired, additional memory
above the basic 64K is required.
System console
Intellec diskette operating system
ICE-86A module
.
Electrical Characteristics
DC POWER
Vcc = +5V +5%-1%
Icc = 17A maximum; 11A typical
VDD = +12V ±5%
100 = 120 mA maximum; 80 mA typical
Vee = -10V ±5% or -12V ±5% (optional)
ise = 25 mA maximum; 12mA typical
REQUIRED SOFTWARE
System Monitor
ISIS-II, version 3.4 or subsequent
ICE-86A software
Equipment Supplied
Printed circuit boards (3)
Interface cable and emulation buffer module
Operator's manual
ICE-86A software, diskette-based
Environmental Characteristics
OPERATING TEMPERATURE
0° to 400C
Emulation Clock
User system clock up to 5 MHz or 2 MHz ICE-86A
internal clock in stand-alone mode
OPERATING HUMIDITY
Up to 95% relative humidity without condensation.
ORDERING INFORMATION
Part Number
Description
MDS*-86A-ICE
iAPX 86 microsystem in-circuit emulator, cable assembly, and interactive software
MDS*-86U-ICE
Upgrade kit to convert ICE-86 emulators to ICE-86A emulator capabilities.
*MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data
Sciences Corporation.
B-164
ICE 86A™, ICE 88A™
iAPX 86, 88 IN-CIRCUIT EMULATOR
• iAPX 86, 88 in-circuit emulation
• Upgradable from ICE-86/88
Full symbolic debugging support for all
• languages
of trace or memory from
• Disassembly
object code into assembler mnemonics
• 2K bytes of high-speed memory
debugging with or without user
• Software
system
iAPX 86/21, 88/21
• Supports
configurations
full 1 megabyte address ability
• ofHandles
iAPX 86, 88
• Breakpoints to halt emulation
trace of program
• Comprehensive
execution, both conditional and
unconditional
The ICE-86A(88A) module provides in-circuit emulation for the 8086(88) microprocessor and the iSBC 86/ 12A single
board computer. It includes three circuit boards which reside in Intellec Series II or Series III Microcomputer Development
System. A cable and buffer box connect the Intellec system to the user system by replacing the user's 8086(88). Powerful
Intellec debug functions are thus extended into the user system. Using the ICE-86A(88)A module, the designer can execute
prototype software in continuous or single-step mode and can substitute blocks of Intellec system memory for user equivalents. Breakpoints allow the user to stop emulation on user-specified conditions, and the trace capability gives a detailed
history of the program execution prior to the break. All user access to the prototype system software may be done
symbolically by referring to the source program variables and labels for all languages.
PLUG INTO
USER
8086 SOCKET
(8088)
r - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --,
I
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Figure 1. ICE-86AI88A™ Block Diagram
B-165
....!N~L~CJ
inter
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The ICE-86A(88A) emulator allows hardware and software development to proceed interactively. This is more
effective than the traditional method of independent hardware and software development followed by system integration. With the ICE-86A(88A) module, prototype
hardware can be added to the system as it is designed.
Software and hardware testing occurs while the product is
being developed.
Conceptually, the ICE-86A(88A) emulator assists three
stages of development:
1. It can be operated without being connected to the user's system, so ICE-86A(88A) debugging capabilities can
be used to facilitate program development before any of
the user's hardware is available.
2. Integration of software and hardware can begin when
any functional element of the user system hardware is con-
nected to the 8086(88) socket. Through ICE-86A(88A)
mapping capabilities,lntellec memory, ICE memory, or diskette memory can be substituted for missing prototype
memory. Time-critical program modules are debugged before hardware implementation by using the 2K-bytes of
high-speed ICE-resident memory. As each section of the
user's hardware is completed, it is added to the prototype.
Thus each section of the hardware and software is "system" tested as it becomes available.
3. When the user's prototype is complete, it is tested with
the final version of the user system software. The ICE86A(88A) module is then used for real-time emulation of
the 8086(88) to debug the system as a completed unit.
Thus the ICE-86A(88A) module provides the user with the
ability to debug a prototype or production system at any
stage in its development without introducing extraneous
hardware or software test tools.
8-166
iAPX 86/20, 88/20
Numerics Supplement
Table of Contents
TITLE
PAGE
Processor Overview... . . . . . . . . . . . . . . . . . . . . . . . .. Sol
Evolution ................................. Sol
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-3
Usability ........................... :-...... S-3
Applications. . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. S-4
Programming Interface. . . . . . . . . . . . . . . . . . . . .. S-5
Hardware Interface ........................... S7
Processor Architecture . . . . . . . . . . . . . . . . . . . . . . .. S-7
Control Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-8
Numeric Execution Unit. . . . . . . . . . . . . . . . . . . .. S-9
Register Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-9
Status Word ............ " ................ SolO
Control Word ............................. SolO
Tag Word ................................. S-lO
Exception Pointers ...... '........ ; . . . . . . . .. S-ll
Computation Fundamentals. . . . . . . . . . . . . . . . . .. S-ll
Number System ........................ ; .. S"12
Data Types and Formats .................... S-13
Binary Integers .......................... S-14
Decimal Integers. . . . . . . . . . . . . . . . . . . . . ... S-14
Real Numbers ............... '............ S-15
Special Values ........................... S-16
Rounding Control. . . . . . . . . . . . . . . . . . . . . . . .. S-17
Precision Control. . . . . . . . . . . . . . . . . . . . . . . . .. S-17
Infinity Control. . . . . . . . . . . . . . . . . . . . . . . . . .. S-18
Exceptions ...... '.' . . . . . . . . . . . . . . . . . . . . .... S-18
Memory ................................... S-21
Data Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-21
Storage Access ......... '. . . . . . . . . . . . . . . . . .. S-22
Dynamic Relocation ................ : . . . . .. S-22
Dedicated and Reserved Memory Locations ... S-22
Multiprocessing Features . . . . . . . . . . . . . . . . . . . .. S-22
Instruction Synchronization ............ '... '. .S-23
Local Bus Arbitration .......... '. . . . . . . .. . .. S-24
System Bus Arbitration ..................... S-25
Controlled Variable Access ................. S-25
Processor Control and Monitoring. . . . . . . . . . . .. S-26
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-26
CPU Identification. . . . . . . . . . . . . . . . . . . . . . .. S-26
Interrupt Requests. . . . . . . . . . . . . . . . . . . . . . . .. S-27
Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . .. S-27
Endless Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-28
Status Lines .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-29
TITLE
PAGE
Instruction Set ............................ ~.
Data Transfer Instructions. . . . . . . . . . . . . . . . ..
Arithmetic Instructions ..... : . . . . . . . . . . . . . ..
Comparison Instructions . . . .. . . . . . . . . . . . . . ..
Transcendental Instructions .......... ; . . . . . ..
Constant Instructions ...... ; . . . . . .. . . . . . . ..
Processor Control Instructions ........ .. • . . . ..
Instruction Set Reference Information. • . . .. ..
Execution Time .................... ~ . . ..
Bus Transfers ... ':'.... : . . . . . . . . . . . . . . . . ..
Instruction Length .................... : ..
Programming Facilities .......................
PL/M-86 .......................... : . . . . ..
ASM-86 .......................' ... ; . . . . . ..
Defining Data. . . . . . . . . . . . . . . . . .. .. . . . . ..
Records and Structures .........'. . . • . . . ....
Addressing Modes .... , ..................
8087 Emulators . . . . . . . . . . . . . . . . . . . . . . . . ...
Programming Example .. : ..... , ...... , .. ...
Special Topics ......•.........,...............
Nonnormal Real Numbers. . . . . .. . . . . . . . . . ..
Denormals ................... :. . . . . . . ..
Unnormals ...................... ~.,: .. : '..
Zeros· and Pseudo-zeros .............. ; ~ . '. ..
Inifinities ................. '. . . . . . . . . . . ... ..
NANs ...... , ............................
Data Type Encodings. . . . . . . . . . . . . . . . . . . . ..
Exception Handling Details. . . . . . . . . • . . . . . ..
,Programming Examples ......................
Conditional Branching ......... , .... '. . . . . ..
S-29
S-30
S-31
S-35
S-36
S-38
S-39
S-42
S-44
S-44
S-44
5-58
S-58
S-59
S-60
S-60
S-61
S-61
S-63
S'~66
8-67
S-67
'S-69
S-70
S-72
S-73
S-74
S-75
S-82
S-82
Tables
Illustrations
PAGE
TITLE
S-1
S-2
S-3
S-4
S-5
S-6
S-7
S-8
S-9
S-10
S-l1
S-12
S-13
S-14
S-15
S-16
S-17
S-18
S-19
S-20
S-21
S-22
S-23
S-24
S-25
S-26
S-27
S-28
S-29
S-30
S-31
S-32
S-33
A-I.
A-2.
8087/Emulator Speed Comparison ........ S-3
Data Types ........... , ................. S-6
Principal Instructions ................... S-6
Real Number Notation ................. S-15
Rounding Modes ...................... S-17
Exception and Response Summary ....... S-20
Processor State Following
Initialization .......................... S-26
Bus Cycle Status Signals ................ S-28
Data Transfer Instructions .............. S-30
Arithmetic Instructions ................. S-32
Basic Arithmetic Instructions
and Operands ......................... S-33
Comparison Instructions ............... S-36
FXAM Condition Code Settings ......... S-37
Transcendental Instructions ............. S-37
Constant Instructions .................. S-38
Processor Control Instructions .......... S-39
Key to Operand Types .................. S-42
Execution Penalties .................... S-43
Instruction Set Reference Data ......... ; S-44
PLlM-86 Built-in Procedures ........... S-59
Storage Allocation Directives ............ S-60
Addressing Mode Examples ....... " .... S-62
Denormalization Process ............... S-68
Exceptions Due to Denormal
Operands ............................ S-69
Unnormal Operandsand Results ......... S-70
Zero Operands and Results .............. S-71
Infinity Operands and Results ........... S-72
Binary Integer Encodings ............... S-75
Packed Decimal Encodings
S-76
Real and Long Real Encodings
S-76
Temporary Real Encodings ............. S-77
Exception Conditions and Masked
Responses ............................ S-79
Masked Overflow Response for
Directed Rounding .................... S-81
Instruction Encoding ................... A-I
Machine Instruction Decoding
Guide ................................ A-2
.0
••••
0
••••
•••
0
••
0
0.
••
0
PAGE
TITLE
S-1
S-2
S-3
S-4
S-5
S-6
S-7
S-8
S-9
S-IO
S-11
S-12
S-13
S-14
S-i5
S-16
S-17
S-18
S-19
S-20
S-21
S-22
S-23
S-24
S-25
S-26
S-27
S-28
S-29
S-30
8087 Numeric Data Processor Pin
Diagram .............................. S-2
8087 Evolution and Relative
Performance ........................... S-2
NDP Interconnect ...................... S-7
8087 Block Diagram .................... S-8
Register Structure ...................... S-9
Status Word Format ................... S-IO
Control Word Format. ................. S-l1
Tag Word Format ..................... S-12
Exception Pointers Format. ............. S-12
8087 Number System ................... S-13
Data Formats ......................... S-14
Projective Versus Affine Closure ......... S-18
Storage of Integer Data Types ........... S-21
Storage of Real Data Types ............. S-21
Synchronizing Execution With
WAIT ............................... S-24
Interrupt Request Logic ................ S-27
Interrupt Request Path ................. S-29
FSA VE/FRSTOR Memory Layout. ...... S-41
FSTENV IFLDENV Memory Layout ..... S-41
Sample 8087 Constants ................. S-43
Status Word RECORD Definition
S-62
Structure Definition ................... S-62
Sample PLlM-86 Program .............. S-64
Sample ASM-86 Program ............... S-65
Instructions and Register Stack .......... S-68
Conditional Branching for Compares ..... S-82
Conditional Branching for FXAM ....... S-83
Full State Exception Handler. " ......... S-86
Latency Exception Handler ............. S-87
Reentrant Exception Handler ............ S-87
.0
••••
0
THE 8087 NUMERIC DATA PROCESSOR
register and instruction sets of the host CPU and
adds several new data types as well. The programmer generally does not perceive the 8087 as a
separate device; instead, the computational
capabilities of the CPU appear greatly expanded.
This supplement describes the8087 Numeric Data
Processor (NDP). Its organization is similar to
chapters 2 and 3 of The 8086 Family User's
Manual:
1.
Processor Overview
2.
Processor Architecture
3.
Computation Fundamentals
4.
Memory
5.
Multiprocessing Features
6.
Processor Control and Monitoring
7.
Instruction Set
8.
Programming Facilities
9.
Special Features
The 8087 is the only chip required to add extensive high-speed numeric processing capabilities to
an 8086- or 8088-based system. It is specifically
designed to deliver stable, correct results when
used in a straightforward fashion by programmers who are not expert in numerical analysis. Its
applicability to accounting and financial
environments, in addition to scientific and
engineering settings, further distinguishes the
8087 from the "floating point accelerators"
employed in many computer systems, including
minicomputers and mainframes. The NDP is
housed in a standard 40-pin dual in-line package
(figure S-I) and requires a single +5V power
source.
10. Programming Examples
Section 1 covers both hardware and software
topics at a general level. Sections 2 and 4 through
6 are largely hardware-oriented, while sections 3
and 7 through 10 are of greatest interest to programmers. Section 9 describes features of the
NDP that will be of interest to specialized groups
of users; it is not necessary to understand this section to successfully use the 8087 in most applications. Hardware coverage in this supplement is
limited to discussing processor facilities in functional terms. Timing, electrical characteristics,
and other physical interface data may be found in
Appendix B, as well as in Chapter 4 of The 8086
The description of the 8087 in this section
deliberately omits some operating details in order
to provide a coherent overall view of the
processor's capabilities. Subsequent sections of
the supplement describe these capabilities, and
others, in more detail.
Evolution
Family User's Manual.
The performance of first- and second-generation
microprocessor-based systems was limited in
three principal areas: storage capacity,
input/output speed, and numeric computation.
The 8086 and 8088 CPUs broke the 64k memory
barrier, allowing larger and more time-critical
applications to be undertaken. The 8089
Input/Output Processor eliminated many of the
I/O bottlenecks and permitted microprocessors
to be employed effectively in I/O-intensive
designs. The 8087 Numeric Data Processor clears
the third roadblock by enabling applications with
significant computational requirements to be
implemented with microprocessor technology.
Note that throughout this supplement the term
"CPU" refers to either an 8086 or 8088 configured in maximum mode. To make best use of
the material in this publication, readers should
have a good understanding of the operation of the
8086/8088 CPUs.
5.1 Processor Overview
The 8087 Numeric Data Processor is a
coprocessor that performs arithmetic and comparison operations on a variety of numeric data
types; it also executes numerous built-in
transcendental functions (e.g., tangent and log
functions). As a coprocessor to a maximum mode
8086 or 8088, the NDP effectively extends the
Figure S-2 illustrates the progression of Intel
numeric products and events that have led to the
development of the 8087. In the mid-1970's, Intel
S-1
8087 NUMERIC DATA PROCESSOR
Vss
A14/D14
100
A13/D13
A12/D12
All/Dll
Al0/01D
w
A19/S6
U
A9/D9
SHE/57
..:
A8/DB
RO/GT1
z
::;:
a:
o
A7I07
LL
a:
A6/06
W
c..
W
AS/OS
>
~
A4/D4
..J
W
A3/D3
10
a:
A2/D2
A1/D1
AD/DO
NC
NC
ClK
1977
VSS
1978
1979
1980
YEAR INTRODUCED
NC = NO CONNECT
Figure 8-1. 8087 Numeric Data Processor Pin
Diagram
Figure 8-2. 8087 Evolution and Relative.
Performance
made the commitment to expand the computational capabilities of microprocessors from
addition and subtraction of integers to an array of
widely useful operations on real numbers. (Real
numbers encompass integers, fractions, and
irrational numbers such as nand V2.) In 1977,
the corporation adopted a standard for representing real numbers in a "floating point"
format. Intel's Floating Point Arithmetic Library
(FPAL) was the first product to utilize this standard format. FP AL is a set of subroutines for the
8080/8085 microprocessors. These routines perform arithmetic and limited standard functions
on single precision (32-bit) real numbers; an
FP AL multiply executes in about 1.5 ms (1.6
MHz 8080A CPU). The next product, the iSBC
31O™ High Speed Math Unit, essentially
implements FPAL in a single iSBC™ card,
reducing a single-precision multiply to about 100
/AS. The Intel® 8232 is a single-chip arithmetic processor for the 8080/8085 family. The 8232 accepts
double precision (64-bit) operands as well as
single precision numbers. It performs a single
precision multiply in about 100 /AS and mUltiplies
double precision numbers in about 875 /As (2 MHz
version).
In 1979, a working committee of the Institute for
Electrical and Electronic Engineers (IEEE) proposed an industry standard for minicomputer and
microcomputer floating point arithmetic*. The
intent of the standard is to promote portability of
numeric programs between computers and to provide a uniform programming environment that
encourages the development of accurate, reliable
software. The proposed standard specifies
requirements and options for number formats as
well as the results of computations on these
numbers. The floating point number formats are
identical to those previously adopted by Intel and
used in the products described in this section.
The 8087 Numeric Data Processor is the most
advanced development in Intel's continuing effort
to provide improved tools for numericallyoriented microprocessor applications. It is a
single-chip hardware implementation of the
proposed IEEE standard, including all its options
for single and double precision numbers. As such,
it is compatible with previous Intel numerics
products; programs written for .the 8087 will be
transportable to future products that conform to
* J. Coonen, W. Kahan, LPalmer, T. Pittman, D. Stevenson, "A Proposed Standard for Binary Floating
Point Arithmetic," A eM SIGNUM Newsletter, October 1979.
S-2
8087 NUMERIC DATA PROCESSOR
the proposed IEEE standard. The NDP also provides many additional functions that are
extensions to the proposed standard.
The 8087's unique coprocessor interface to the
CPU can yield an additional performance increment beyond that of simple instruction speed. No
overhead is incurred in setting up the device for a
computation; the 8087 decodes its own instructions automatically in parallel with the CPU.
Moreover, built-in coordination facilities allow
the CPU to proceed with other instructions while
the 8087 is simultaneously executing its numeric
instruction. Programs can exploit this processor
parallelism to increase total system throughput.
Performance
As figure S-2 indicates, the 8087 provides about
10 times the instruction speed of the 8232 and a
100-fold improvement over FP AL. The 8087
multiplies 32-bit and 64-bit real numbers in about
19 lAs and 27 lAs, respectively. Of course, the actual
performance of the NDP in a given system
depends on numerous application-specific
factors.
Usability
Viewed strictly from the standpoint of raw speed,
the 8087 enables serious computation-intensive
tasks to be performed by microprocessors for the
first time. The 8087 offers more than just high
performance, however. By synthesizing advances
made by numerical analysts in the past several
years, the NDP provides a level of usability that
surpasses existing minicomputer and mainframe
arithmetic units. In fact, the charter of the 8087
design team was first to achieve exceptional functionality and then to obtain high performance.
Table S-l compares the execution times of several
8087 instructions with the equivalent operations
executed in software on a 5 MHz 8086. The software equivalents are highly optimized assembly
language procedures from the 8087 emulator, an
NDP development tool discussed later in this
section.
The performance figures quoted in this section
are for operations on real (floating point)
numbers. The 8087 also has instructions that
enable it to utilize fixed point binary and decimal
integers of up to 64 bits and 18 digits; respectively. Using an 8087, rather than multiple precision software algorithms for integer operations,
can provide speed improvements of 10-100 times.
The 8087 is explicitly designed to deliver stable,
accurate results when programmed using
straightforward "pencil and paper" algorithms.
While this statement may seem trivial, experienced users of "floating point processors" will
Table S-I. 8087 Emulator Speed Comparison
Approximate Execution Time (JAs)
(5 MHz Clock)
Instruction
8087
8086
Emulation
Multiply (single precision)
19
1,600
Multiply (double precision)
27
2,100
Add
17
1,600
Divide (single preciSion)
39
3,200
Compare
9
1,300
Load (single precision)
9
1,700
Store (single precision)
18
1,200
Square root
36
19,600
Tangent
90
13,000
100
17,100
Exponentiation
S-3
8087 NUMERIC DATA PROCESSOR
that exhibit any of the following characteristics
can benefit by implementing numeric processing
on the 8087:
•
Numeric data vary over a wide range of
values, or include non-integral values;
recognize its fundamental importance. For
example, most computers can overflow when two
single precision floating point numbers are
multiplied together and then divided by a third,
even if the final result is a perfectly valid 32-bit
number. The 8087 delivers the correctly rounded
result. Other typical examples of undesirable
machine behavior in straightforward calculations
occur when solving for the roots of a quadratic
equation:
•
•
-b+vb 2 -4ac
•
Performance requirements exceed the
capacity of traditional microprocessors;
•
Consistently safe, reliable results must be
delivered using a programming staff that is
not expert in numerical techniques.
2a
or computing financial rate of return, which
involves the expression: (1 +i:)n. Straightforward
algorithms will not deliver consistently correct
results (and will not indicate when they are incorrect) on most machines. To obtain correct results
on traditional machines under all conditions
usually requires sophisticated numerical techniques that are foreign to most programmers.
General application programmers using straightforward algorithms will produce much more
reliable programs on the 8087. This simple fact
greatly reduces the software investment required
to develop safe, accurate computation-based
products.
Algorithms produce very large or very small
intermediate results;
Computations must be very precise, i.e., a
large number of significant digits must be
maintained;
Note also that the 8087 can reduce software
development costs and improve the performance
of systems that do not utilize real numbers but
operate on multi-precision binary or decimal
integer values.
A few examples, which show how the 8087 might
be utilized in specific numerics applications, are
described below. In many cases, these types of
systems have been implemented in the past with
minicomputers. The advent of the 8087 brings the
size and cost savings of microprocessor
technology to these applications for the first time.
Beyond traditional numerics support for "scientific" applications, the 8087 has built-in facilities
for "commerical" computing. It can process
decimal numbers of up to 18 digits without roundoff errors, and it performs exact arithmetic on
integers as large as 264 • Exact arithmetic is vital in
accounting applications where rounding errors
may introduce money losses that cannot be
reconciled.
•
Business data processing-The NDP's ability
to accept decimal operands and produce
exact decimal results of up to 18 digits greatly
simplifies accounting programming. Financial calculations which use power functions
can take advantage of the 8087's
exponentiation and logarithmic instructions.
•
Process control-The 8087 solves dynamic
range problems automatically and its
extended precision allows control functions
to be fine-tuned for more accurate and efficient performance. C.ontrol algorithms
implemented with the NDP also contribute
to improved reliability and safety, while the
8087's speed can be exploited in real-time
operations.
Numerical control-The 8087 can move and
position machine tool heads with extreme
accuracy. Axis positioning also benefits from
the hardware trigonometric support provided
by the 8087.
The NDP contains a number of facilities that can
optionally be invoked by sophisticated users.
Examples of these advanced features include two
models of infinity, directed rounding, gradual
underflow, and traps to user-written exception
handling software.
Applications
•
The NDP's versatility and performance make it
appropriate to a broad array of numericallyoriented applications. In general, applications
S-4
8087 NUMERIC DATA PROCESSOR
•
Robotics-Coupling small size and modest
power requirements with powerful computational abilities, the NDP is ideal for on-board
six-axis positioning.
•
Navigation-Very small, light weight, and
accurate inertial guidance systems can be
implemented with the 8087. Its built-in
trigonometric functions can speed and
simplify the calculation of position from
bearing data.
•
Graphics terminals-The 8087 can be used in
graphics terminals to locally perform many
functions which normally demand the attention of a main computer; these include rotation, scaling, and interpolation. By also
including an 8089 Input/Output Processor to
perform high speed data transfers, very
powerful and highly self-sufficient terminals
can be built from a relatively small number
of 8086 family parts.
•
Table 8-2 lists the seven 8087 data types. Internally, the 8087 holds all numbers in the temporary
real format; the extended range and precision of
this format are key contributors to the NDP's
ability to consistently deliver stable, expected
results. The 8087's load and store instructions
convert operands between the other formats and
temporary real. The fact that these conversions
are made, and that calculations may be performed on converted numbers, is transparent to
the programmer. Integer operands, whether
binary or decimal, yield correct integer results,
just as real operands yield correct real results.
Moreover, a rounding error does not occur when
a number in an external format is converted to
temporary real.
Computations in the 8087 center on the processor's register stack. These eight 80-bit registers
provide the equivalent capacity of 40 of the 16-bit
registers found in typical CPUs. This generous
register space allows more constants and
intermediate results to be held in registers during
calculations, reducing memory access and consequently improving execution speed as well as bus
availability. The 8087 register set is unique in that
it can be accessed both as a stack, with instructions operating implicitly on the top one or two
stack elemeIlts, and as a fixed register set, with
instructions operating on explicitly designated
registers.
Data acquisition-The 8087 can be used to
scan, scale, and reduce large quantities of
data as it is collected, thereby lowering
storage requirements as well as the time
required to proce:;s the data for analysis.
The preceding examples are oriented toward
"traditional" numerics applications. There are,
in addition, many other types of systems that do
not appear to the end user as "computational,"
but can employ the 8087 to advantage. Indeed,
the 8087 presents the imaginative system designer
with an opportunity similar to that created by the
introduction of the microprocessor itself. Many
applications can be viewed as numerically-based
if sufficient computational power is available to
support this view. This is analogous to the
thousands of successful products that have been
built around "buried" microprocessors, even
though the products themselves bear little
resemblance to computers.
Table 8-3 lists the 8087's major instructions by
class. Assembly language programs are written in
A8M-86, the 8086/8088/8087 common assembly
language. A8M-86 provides directives for defining all 8087 data types and mnemonics for all
instructions. The fact that some instructions in a
program are executed by the 8087 and others by
the CPU is usually of no concern to the programmer. All 8086/8088 addressing modes may
be used to access memory-based 8087 operands,
enabling convenient processing of numeric
arrays, structures, based variables, etc.
NDP routines may also be written in PL/M-86,
Intel's high-level language for the 8086 and 8088
CPUs. PLlM-86 provides the programmer with
access to many 8087 facilities while reducing
the programmer's need to understand the
architecture of the chip.
Programming Interface
The combination of an 8086 or 8088 CPU and an
8087 generally appears to the programmer as a
single machine. The 8087, in effect, adds new
data types, registers, and instructions to the CPU.
The programming languages and the coprocessor
architecture take care of most interprocessor
coordination automatically.
Two features of the 8087 hardware further
simplify numeric application programming. First,
the 8087 is invoked directly by the programmer's
instructions. There is no need to. write instructions
8-5
8087 NUMERIC DATA PROCESSOR
Table S-2. Data Types
Data Type.
Bits
Significant
Digits (Decimal)
Approximate Range (Decimal)
Word integer
16
4
-32,768 ~ X ~ + 32,767
Short integer
32
9
-2x10 9 ~ X ~ +2x10 9
Long integer
64
18
Packed decimal
80
18
-99 ... 99 ~ X ~ + 9~ ... 99 (18 digits)
8.43x10-37 ~ Ixi ~ 3.37x10 38
4.19x10-307 ~ Ixl ~ 1.67x10308
32
6-7
Long real'
64
15-16
Temporary real
80
19
Short real'
-9x10 18 ~ X ~ +9x1018
3.4x10-4932.~
Ixl ~ 1.2x104932
"The short and long real data types correspond to the single and double precision data types
.
defined in other Intel numerics products.
Table S-3. Principal Instructions
Class
.
Instructions
Data Transfer
Load (all data types), Store (all data types), Exchange
Arithmetic
Add, Subtract, Multiply, Divide, Subtract Reversed,
Divide Reversed, Square Root, Scale, 'Remainder,
Integer Part, Change Sign, AbsoluteValue, Extract
Comparison
Transcendental
Compare, Examine, Test
Tangent, Arctangent, 2X -1, yeLog2(X + 1), YeLog 2(X)
Constants
0,1,n, Log 10 2, Log e2,Log 210, Log 2e
Processor Control
Load Control Word, Store Control Word, Store Status
Word, Load Environment, Store Environment, Save,
Restore, Enable Interrupts, Disable Interrupts, Clear
Exceptions, Initialize
executes entirely on an 8086 or 8088 CPU. The
emulator allows 8087 routines to be developed
and checked out on an 8086/8088 execution
vehicle before prototype 8087 hardware is operational. At the source code level, there is no
difference between a routine that will ultimately
run on an 8087 or on a CPU emulation of an
8087. At link time, the decision is made whether
to use the NDP or the software emulator; no recompilation or re-assembly is necessary. Source
programs are independent of the numeric execution vehicle: except for timing, the operation of
the emulated NDP is the same as for "real hardware". The emulator also makes it simple fora
product to offer the NDP as a "plug-in"
performance option without the necessity of
maintaining two sets of source code.
that "address" the NDP as an "I/O device", or
to incur the overhead of setting up a DMA operation to perform data transfers. Second, the NDP
automatically detects exception conditions that
can potentially damage a calculation at run-time.
On-chip exception handlers are automatically
invoked by default to field these exceptions so
that a reasonable result is produced and execution
may proceed without program intervention.
Alternatively, the 8087 can interrupt the CPU and
thus trap to a user procedure when an exception is
detected.
Besides the assembler and compiler, Intel
provides a software emulator for the 8087. The
8087 emulator (E8087) is a software package that
provides the functional equivalent of an 8087; it
S-6
8087 NUMERIC DATA PROCESSOR
when the 8087 is not in control of the local bus.
When it is in control of the bus, the 8087 relinquishes the bus (at the end of the current bus
cycle) upon a request from the connected lOP,
giving the lOP higher priority than itself. In this
way, two local 8089's can be configured in a
module that also includes a CPU and an 8087.
Hardware Interface
As a coprocessor to an 8086 or 8088, the 8087 is
wired directly to the CPU as shown in figure S-3.
The CPU's queue status lines (QSO and QSl)
enable the NDP to obtain arid decode instructions
in synchronization with the CPU. The NDP's
BUSY signal informs the CPU that the NDP is
executing; the CPU WAIT instruction tests this
signal to ensure that the NDP is ready to execute a
subsequent instruction. The NDP can interrupt
the CPU when it detects an exception. The NDP's
interrupt request line is typically routed to the
CPU through an 82S9A Programmable Interrupt
Controller.
All processors utilize the same clock generator
and system bus interface components (bus controller, latches, transceivers, ·and bus arbiter).
Thus, no additional hardware beyond the 8087
is required to add powerful computational
capabilities to an 8086- or 8088-based system.
8.2 Processor Architecture
The NDP uses one of its host CPU's
request/grant lines to obtain control of the local
bus for data transfers (loads and stores). The
other CPU request/ grant line is available for
general system use, for example, by a local 8089
Input/Output Processor. A local 8089 may also
be connected to the 8087's RQ/GTl line. In this
configuration, the 8087 passes the request/grant
handshake signals between the CPU and the lOP
.. - -
I
I
L
..,
INT
8259A
PIC
I
INTR
I
ClK 808g~t088
r---
....lR"_ J
~ Ra/GT1
aso aS1
-
8284
CLOCK
GENERATOR
ClK
As shown in figure S-4, the NDP is internally
divided into two processing elements, the control
unit (CU) and the numeric execution unit (NEU).
In essence, the NEU executes all numeric instructions, while the CU fetches instructions, reads
and writes memory operands, and executes the
processor control class of instructions. The two
t
TEST
aso aS1
...
BUSY
"jj
8087
NDP
...
Ra/GT1
I
A
-
"jj
+ +
INT
L-
~
~
RQ/GTO
ClK
T
"jj
...
~ClK
~
".Ig~
I ~
8089
lOP
...
Figure 8-3. NDP Interconnect
S-7
8086
FAMilY
BUS
INTERFACE
~
COMPONENTS
~
H
MUlTIMASTER
SYSTEM
BUS
8087 NUMERIC DATA PROCESSOR
elements are able to operate independently of
one another, allowing the CU to maintain
synchronization with the CPU while the NEU
executes numeric instructions.
The two processors execute the instruction stream
differently, however. The first five bits of all 8087
machine instructions are identical; these bits
designate the coprocessor escape (ESC) class of
instructions. The control unit ignores all instructions that do not match these bits, since these
instructions are directed to the CPU only. When
the CU decodes an instruction containing the
escape code, it either executes the instruction
itself, or passes it to the NEU, depending on the
type of instruction.
Control Unit
The CU keeps the 8087 operating in synchronization with its host CPU. 8087 instructions are
intermixed with CPU instructions in a single
instruction stream fetched by the CPU. By
monitoring the status signals emitted by the CPU,
the NDP control unit can determine when an
instruction is being fetched. When the instruction
byte or word becomes available on the local bus,
the CU taps the bus in parallel with the CPU and
obtains that portion of the instruction.
The CPU distinguishes between ESC instructions
that reference memory and those that do not. If
the instruction refers to a memory operand, the
CPU calculates the operand's address and then
performs a "dummy read" of the word at that
location. This is a normal read cycle, except that
the CPU ignores the data it receives. If the ESC
instruction does not contain a memory reference,
the CPU simply proceeds to the next instruction.
The CU maintains· an instruction queue that is
identical to the queue in the host CPU. By
monitoring the CPU's queue status lines, the CU
is able to obtain and decode instructions from the
queue in synchronization with the CPU. In effect,
both processors fetch and decode the instruction
stream in parallel.
A given 8087 instruction (an ESC to the CPU) will
either require loading an operand from memory
into the 8087, or will require storing an operand
from the 8087 into memory, or will not reference
DATA"-~~
I
I
I
I
I
I
(61
STATUS
ADDRESS
T
A
G
I
I
I
L
(51
(41
REGISTER STACK
W
(31
0
R
D
-
-
--
(21
.-
80 BITS
Figure S-4. 8087 Block Diagram
S-8
I
(11
-.
(01
-
-- ~
8087 NUMERIC DATA PROCESSOR
79
memory at all. In the first two cases, the CU
makes use of the "dummy read" cycle initiated
by the CPU. The CU captures and saves the
operand address that the CPU places on the bus
early in the "dummy read". If the instruction is
an 8087 load, the CU additionally captures the
first (and possibly only) word of the operand
when it becomes available on the bus. If the
operand to be loaded is longer than one word, the
CU immediately obtains the bus from the CPU
and reads the rest of the operand in consecutive
bus cycles. In a store operation, the CU captures
and saves the operand address as in a load, and
ignores the data word that follows in the "dummy
read" cycle. When the 8087 is ready to perform
-the store, the CU obtains the bus from the CPU
·and writes the operand at the saved address using
as many consecutive bus cycles as are necessary to
store the operand.
o
64 63
SIGNIFICAND
Figure 8-5. Register Structure
For example, the ASM-86 instruction FSQRT
replaces the number at the top of the stack with its
square root; this instruction takes no operands
because the top-of-stack register is implied as the
operand. Other instructions allow the programmer to explicitly specify the register that is to be
used. Explicit register addressing is "toprelative" where the ASM-86 expression ST
denotes the current stack top and ST(i) refers
to the ith register from ST in the stack (O~ i ~7).
For example, if ST contains OllB (register 3 is the
top of the stack), the following instruction would
add registers 3 and 5:
Numeric Execution Unit
FADD ST, ST(2)
The NEU executes all instructions that involve
the register stack; these include arithmetic,
comparison, transcendental, constant, and data
transfer instructions. The data path in the NEU is
68 bits wide and allows internal operand transfers
to be performed at very high speeds.
In typical use, the programmer may conceptually
"divide" the registers into a fixed group and an
adjustable group. The fixed registers are used like
the conventional registers in a CPU, to hold constants, accumulations, etc. The adjustable group
is used like a stack, with operands pushed on and
results popped off. After loading, the registers in
the fixed group are addressed explicitly, while
those in the adjustable group are addressed
implicitly. Of course, all registers may be
addressed using either mode, and the "definition" of the fixed versus the adjustable areas may
be altered at any time. Section S.8 contains a programming example that illustrates typical register
stack use.
Register Stack
Each of the eight registers in the 8087's register
stack is 80 bits wide, and each is divided into the
"fields" shown in figure S-5. This format
corresponds to the NDP's temporary real data
type that is used for all calculations. Section S.3
describes in detail how numbers are represented in
the temporary real format.
The stack organization and top-relative addressing of the registers simplify subroutine
programming. Passing subroutine parameters on
the register stack eliminates the need for the
subroutine to "know" which registers actually
contain the parameters and allows different
routines to call the same subroutine without
having to observe a convention for passing
parameters in dedicated registers. So long as the
stack is not full, each routine simply loads the
parameters on the stack and calls the subroutine.
The subroutine addresses the parameters as ST,
ST(l), etc., even though ST may, for example,
refer to register 3 in one invocation and register 5
in another.
At a given point in time, the ST field in the status
word (described shortly) identifies the current
top-of-stack register. A load ("push") operation
decrements ST by 1 and loads a value into the new
top register. A store-and-pop operation stores the
value from the current top register and then
increments ST by 1. Thus, like 8086/8088 stacks
in memory, the 8087 register stack grows "down"
toward lower-addressed registers.
Instructions may address registers either implicitlyor explicitly. Many instructions operate on the
register at the top of the stack. These instructions
implicitly address the register pointed to by ST.
S-9
8087 NUMERIC DATA PROCESSOR
Status Word
Bit 7 is the interrupt request field. TheNDP sets
this field to record a pending interrupt to the
CPU.
The status word reflects the overall condition of
the 8087; it may be examined by storing it into
memory with an NDP instruction and then
inspecting it with CPU code. The status word is
divided into the fields shown in figure S-6. The
busy field (bit 15) indicates whether the NDP is
executing an instruction (B=I) or is idle (B=O).
Bits 5-0 are set to indicate that the NEU has
detected an exception while executing an instruction. Section S.3 explains these exceptions.
Control Word
Several 8087 instructions (for example, the comparison instructions) post their results. to the
condition code (bits 14 and 10-8 of the status
word). The principal use of the condition code is
for conditional· branching. This may be
accomplished by executing an instruction that sets
the condition code, storing the status word in
memory and then examining the condition code
with CPU instructions.
To satisfy a broad range of application
requirements, the NDP provides several processing options which are selected by loading a word
from memory into the control word. Figure S-7
shows the format and encoding of the fields in the
control word; it is provided here for reference.
Section S.3 explains the use of each .of these 8087
facilities except the interrupt-enable control field,
which is covered in section S.6.
Bits 13-11 of the status word point to the 8087
register that is the current stack top (ST). Note
that if ST=OOOB, a "push" operation, which
decrements ST, produces ST=l11B; similarly,
popping the stack with ST=IIIB yields ST=OOOB.
15
Tag Word
The tag word marks the content of each register
as shown in figure S-8. The principal fUnction
7
I
ST
I
I
c21 C1 I CO I'R I
0
I PE I UE I OE I ZE I DEl,E
I
@
EXCEPTION FLAGS (1 = EXCEPTION HAS OCCURRED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERODIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT REQUEST
CONDITION CODE(l)
STACK TOP PO)NTER(2)
BUSY
See descriptions of compare, test, examine and remainder instructions in section S.7 for
condition code interpretation.
(2) ST values:
000 = register 0 is stack top
0~1 = register 1 is stack top
(1).
.
111 = register 7 is stack top
Figure S-6. Status Word Format
S-lO
8087 NUMERIC DATA PROCESSOR
15
o
7
I
I
IIC I
RC
I
-r--
I
-r--
~
EXCEPTION MASKS (1
= EXCEPTION IS MASKED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERODIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT-ENABLE MASK(l)
PRECISION CONTROLl2)
ROUNDING CONTROLl3)
INFINITY CONTROLl4)
(RESERVED)
(1) Interrupt-Enable Mask:
o = Interrupts Enabled
1 = Interrupts Disabled (Masked)
Precision Control:
00 = 24 bits
01 = (reserved)
10 = 53 bits
11 = 64 bits
(3) Rounding Control:
00 = Round to Nearest or Even
01 = Round Down (toward -00)
10 = Round Up (toward +00)
11 = Chop (Truncate Toward Zero)
(4) Infinity Control:
o = Projective
1 = Affme
(2)
Figure S-7. Control Word Format
of the tag word is to optimize the NDP's
performance under certain circumstances and
programmers ordinarily need not be concerned
with it.
5.3 Computation
Fundamentals
Exception Pointers
This section covers 8087 programming concepts
that are common to all applications. It describes
the 8087's internal number system and the various
types of numbers that can be employed in NDP
programs. The most commonly used options for
rounding, precision and infinity (selected by fields
in the control word) are described, with
exhaustive coverage of less frequently used
facilities deferred to section S.9. Exception conditions which may arise during execution of NDP
instructions are also described along with the
options that are available for responding to these
exceptions.
The exception pointers (see figure S-9) are provided for user-written exception handlers;
Whenever the 8087 executes an instruction, the
CU saves the instruction address and the instruction opcode in the exception pointers. In
addition, if the instruction references a memory
operand, the address of the operand is retained
also. An exception handler can store these
pointers in memory and thus obtain information
concerning the' instruction that caused the
exception.
S-ll
8087 NUMERIC DATA PROCESSOR
Tag values:
00 Valid (Normal Dr Unnormal)
01
Zero (True)
10 Special (Not·A·Number, 00, Dr Denormal)
11
Empty
_
=
=
=
=
Figure S-8. Tag Word Format
I
OPERAND ADDRESS(1)
I
INSTRUCTION ADDRESS(1)
I
INSTRUCTION OPCODE(2)
o
-10
(1) 20.blt physical address
(2) 11 least significant bits of opcode; 5 most significant bits are aiwaysSOS7 hook (110118)
Figure S-9. Exception Pointers Format
Figure S-IO superimposes the basic 8087 real
number system on a real number line (decimal
numbers are shown for clarity, although the 8087
actually represents numbers in binary). The dots
indicate the subset of real numbers the 8087 can
represent as data and final results of calculations.
The 8087's range is approximately ±4.19xlO-307
to ±1.67x10308 . Applications that are required to
deal With data and final results outside this range
are rare. By comparison, the range of the IBM
370 is about ±0.54xlO-78 to ±O. 72xI076.
Number System
The system of real numbers that people use for
pencil and paper calculations is conceptually
infinite and continuous. There is no upper or
lower limit to the magnitude of the numbers one
ellD employ in a calculation, or to the precision
(number of significant digits) that the numbers
can represent. When considering any real
number, there are always an infinity of numbers
both larger and smaller. There is also an infinity
of numbers between (Le., with more significant
digits than) any two real numbers. For example,
between 2.5 and 2.6 are 2.51,2.5897,2.500001,
etc.
The finite spacing in figure S-IO illustrates that
the NDP can represent a great many, but not all,
of the real numbers in its range. There is always a
"gap" between two "adjacent" 8087 numbers;
and it is possible for the result of a calculation to
fall in this space. When this occurs, the NDP
rounds the true result to a number that it can
represent. Thus, a real number that requires more
digits than the 8087 can accommodate (e.g., a 20
digit number) is represented with some loss of
accuracy. Notice also that the 8087's representable numbers are not distributed evenly along the
real number line. There are, in fact, an equal
number of representable numbers between successivepowers of 2 (i.e., there are as many
representable numbers between 2 and 4 as
between 65,536 and 1-31,072). Therefore, the
"gaps" between representable numbers are
While ideally it would be desirable for a computer
to be able to operate on the entire real number
system, in practice this is not possible. Computers, no matter how large, ultimately have
fixed-size registers and memories that limit the
system of numbers that can be accommodated.
These limitations proscribe both the range and the
precision of numbers. The result is a set of
numbers that is finite and discrete, rather than
infinite and continuous. This sequence is a subset
of the real numbers which is designed to form a
useful approximation of the real number system.
S-12
8087 NUMERIC DATA PROCESSOR
....
I
[
NEGATIVE RANGE
(NORMALIZED)
-5
•
-1.67x10 308
-4
...
••
-3
-2
-1
I
• .c_-... t ..................., . ]
.,
POSITIVE RANGE
(NORMALIZED)
I
I
4
o
I
~~~~~~~~.-~-.--.-----.--~~
1.67x10308
-4.19x10-307
2.00000000000000000
(NOT REPRESENTABLE)
......- - - - 1.99999999999999999
PRECISION:
1+-18 DIGITS--I
Figure S-10. 8087 Number System
"larger" as the numbers increase in magnitude.
All integers in the range ±264 , however, are
exactly representable.
Conversely, and equally important, the 8087 does
perform exact arithmetic on its integer subset of
the reals. That is, an operation on two integers
returns an exact integral result, provided that the
true result is an integer and is in range. For example, 4+2 yields an exact integer, 1+3 does not, and
240 x 230 + 1 does not, because the result requires
greater than 64 bits of precision.
In its internal operations, the 8087 actually
employs a number system that is a substantial
superset of that shown in figure S-1O. The internal
format (called temporary real) extends the 8087's
range to about ±3.4x1O-4932 to ±1.2x104932 , and
its precision to about 19 (equivalent decimal)
digits. This format is designed to provide extra
range and precision for constants and
intermediate results, and is not normally intended
for data or final results.
Data Types and Formats
The 8087 recognizes seven numeric data types,
divided into three classes: binary integers, packed
decimal integers, and binary reals. Section S.4
describes how these formats are stored in memory
(the sign is always located in the highest- address~
ed byte). Figure S-l1 summarizes the format of
each data type. In the figure, the most significant
digits of all numbers (and fields within numbers)
are the leftmost digits. Table S-2 provides the
range and number of significant (decimal) digits
that each format can accommodate.
From a practical standpoint, the 8087's set of real
numbers is sufficiently "large" and "dense" so
as not to limit the vast majority of microprocessor
applications. Compared to most computers,
including mainframes, the NDP provides a very
good approximation of the real number system. It
is important to remember, however, that it is not
an exact representation,. and that arithmetic on
real numbers is inherently approximate.
S-13
8087 NUMERIC DATA PROCESSOR
_ _ INCREASING SIGNIFICANCE
WORD INTEGER
lsi
MAGNITUDE
Ig~~~tEMENT)
o
15
I
I~I
SHORT INTEGER I.
MAGNITUDE
(TWO'S
. ...,~_ _ _ _ _ _ _ _ _ _... COMPLEMENT)
31
LONG INTEGER
0
I
II
(TWO'S
COMPLEMENT)
S
MAGNITUDE
~6~3------------------------------------~0
PACKED DECIMAL
d17 d 16 d 1S d 14 d13 d12 d11
79
MAGNITUDE
d10 dg ds d 7
d6
ds
d4
d3
d2
d1
do
o
72
SHORT REAL
o
LONG REAL
BIASED
EXPONENT
S
SIGNIFICAND
o
63
I'
I~___E_:_J_~_~E_t_N_T___.bj_I~_ _ _ _ _ _ _S_IG_N_I_F_IC_A_N_D_____________...
TEMPORARY REAL IS
.....
79
6463 1
0
NOTES:
S = Sign bit (0 = positive, 1 = negative)
dn = Decimal digit (two per byte)
X = Bits have no significance; 8087 ignores when loading, zeros when storing.
, = Position of impliCit binary point
I = Integer bit of significand; stored in temporary real, implicit in short and long real
Exponent Bias (normalized values):
Short Real: 127 (7FH)
Long Real: 1023 (3FFH)
Temporary Real: 16383 (3FFFH)
Figure S-ll. Data Formats
Binary Integers
are 0). The 8087 word integer format is identical
to the 16-bit signed integer data type of the 8086
and 8088.
The three binary integer formats are identical
except for length, which governs the range that
can be accommodated in each format. The leftmost bit is interpreted as the number's
sign: O=positive and 1=negative. Negative
numbers are represented in standard two's complement notation (the binary integers are the only
8087 format to use two's complement). The quantity zero is represented with a positive sign (all bits
Decimal Integers
Decimal integers are stored in packed decimal
notation, with two decimal digits "packed"into
each byte, except the leftmost byte, which carries
the sign bit (0 = positive, 1 = negative). Negative
S-14
8087 NUMERIC DATA PROCESSOR
expressed exactly in decimal). When a translator
encounters such a value, it produces a rounded
binary approximation of the decimal value.
numbers are not stored in two's complement form
and are distinguished from positive numbers only
by the sign bit. The most signifiCant digit of the
number is the leftmost digit. All digits must be in
the range OH-9H.
The NDP usually carries the digits of the significand in normalized form. This means that, except
for the value zero, the significand is. an integer
and airaction as follows:
Real Numbers
ItJff...ff
The 8087 stores real numbers in a three-field
binary format that resembles scientific, or
exponential, notation. The number's significant
digits are held in the significand field,· the
exponent field locates the binary point within the
significant digits (and therefore determines the
number's magnitude), and the sign field indicates
whether the number is positive or negative. (The
exponent and significand are analogous to the
terms "characteristic" and "mantissa" used to
describe floating point numbers on some computers.) Negative numbers differ from positive
numbers only in their sign bits.
where A indicates an assumed binary point. The
number of fraction bits varies according to the
real format: 23 for short, 52 for long and 63 for
temporary real. By normalizing real numbers so
that their. integer bit is always a 1, the .8087
eliminates leading zeros in small values (lxl < 1).
This technique maximizes the number of significant digits that can be accommodated in a
significand of a given width. Note that in the
short and long real formats the integer bit is
implicit and is not actually stored; the integer bit
is physiCally present in the temporary real format
only ..
Table S-4 shows how the real number 178.125
(decimal) is stored in the 8087 short real format.
The table lists a progression of equivalent notations that express the same value to show how a
number can be converted from one form to
another: The ASM-86 and PLlM-86 language
translators perform a similar process when they
encounter programmer-defined real number constants. Note that not every decimal fraction has
an exact binary equivalent. The decimal number
1110, for example, cannot be expressed exactly
in binary (just as the number 113 cannot be
If one were to examine only the signifiCand with
its assumed binary point, all normalized real
numbers would have values between l.and 2. The
exponent field locates the actual binary point in
the significant digits. Just as in decimal scientific
notation, a positive exponent has the effect of
moving the binary point to the right and a
negative exponent effectively moves the binary
point to the left, inserting leading zeros as
necessary. An unbiased exponent of zero
Table 8-4. Real Number Notation
Notation
Value
Ordinary Decimal
178.125
Scientific Decimal
1f:,.78125E2
Scientific Binary
1f:,.011 001 0001 E111
Scientific Binary
(Biased Exponent)
1f:,. 0110010001 E10000110
8087 Short Real
(Normalized)
Sign
Biased
Exponent
0
10000110
S-15
Significand
01100100010000000000000
1f:,. (implicit)
L
8087 NUMERIC DATA PROCESSOR
Special Values
indicates that the position of the assumed binary
point is also the position of the actual binary
point. The exponent field, then, determines a real
number's magnitude.
Besides, being able to represent positive and
negative numbers, the 8087 data formats may be
used to describe other entities. These special
values provide extra flexibility but most users do
not need to understand them in detail to use the
8087 successfully. Accordingly, they are discussed
here only briefly; expanded coverage, including
the bit encoding of each value, is provided in
section S.9.
In order to simplify comparing real numbers
(e.g., for sorting), the 8087 stores exponents ina
biased form. This means that a constant is'added
to the true exponent described above. The value
of this bias is different for each real format (see
figure S-l1). Ithas been chosen so as to force the
biased exponent to be a positive value. This
allows two real numbers (of the same format and
sign) to be compared as if they are unsigned
binary integers. That is, when comparing them
bitwis..e from left to right (beginning with the leftmost exponent bit), the first bit position that
differs orders the numbers; there is no need to
proceed further with the comparison. A number's
true exponent can be determined simply by subtracting the. bias value of its format.
The value zero may be signed positive or negative
in the real and decimal integer formats; the sign
of a binary integer zero is always positive. The
fact that zero rnay be 'signed, however, is
transparent to the programmer.
The real number formats allow for the representation of the special values +00 and -00. The 8087
may generate these values as its built-in response
to exceptions such as division by zero, or the
attempt to store a result, that exceeds the upper
range limit of the destination format. Infinities
may participate in arithmetic and comparison
operations, and in fact the processor provides two
different conceptual models for handling these
special values.
The short and long real formats exist in memory
only. If a number in one of these formats is
loaded into a register, it is automatically
converted to temporary real, the format used for
all internal operations. Likewise,data in reg~sters
can be converted to short or long reaJ'for storage
in memory. The temporary real format may be
used in memory also, typically to store
intermediate results that cannot be held in
registers.
If a programmer attempts an operation for which
the 8087 cannot deliver a reasonable result, it will,
at the programmer's discretion, either request an
interrupt, or return the special value indefinite.
Taking the square root of a negative number is an
example of this type of invalid, operation. The
recommended action in this situation is to stop
the computation by trapping to a user-written
exception handler. If, however, the programIl}.er
elects to continue the computation, the specially
coded indefinite value will propagate through the
calculation and thus flag the erroneous computation when it is eventually delivered as the result.
Each format has an encoding that represents the
special value indefinite.
Most applications should use the long real form
to store real number data and results; it provides
sufficient range and precision to return correct
results with a minimum of programmer attention.
The short real format is appropriate for applications that are constrained by memory, but it
should be recognized that this format provides a
smaller margin of safety. It is also useful for
debugging algorithms because roundoff problems
will manifest themselves more quickly in this format. The temporary real format should normally
be reserved for holding intermediate results, loop
accumulations, and constants. Its extra length is
designed to shield final results from the effects
of rounding and overflow/underflow in intermediate calculations. When the temporary real
format is used to hold data or to deliver final
results, the safety features built into the 8087 are
compromised. Furthermore, the range and precision of the long real form are adequate for most
microcomputer applications.
In the real formats,a: whole range of special
values, both positive and negative, is designated
to represent a class of values called NAN (Not-ANumber). The special value indefinite is a
reserved NAN encoding, but all other encodings
are made available to be defined in any way by
application software. Using a NAN as an operand
raises the invalid operation exception, and can
trap to a user-written routine to process the NAN.
Alternatively, the 8087's built-in exception
S-J6
8087 NUMERIC DATA PROCESSOR
Table S-5. Rounding Modes
RC Field
Rounding Mode
00
Round to nearest
Rounding Action
Closertob ota are; it
equally close, select even
number (the one whose
least significant bit is zero).
01
Round down (toward -00)
10
Round up (toward
11
Chop (toward 0)
a
+ 00)
e
Smaller in magnitude of
a are
Note: a
< b < e; a and e are representable, b is not.
handler will simply return the NAN itself as the
result of the operation; in this way NANs,
including indefinite, may be propagated through
a calculation and delivered as a final, specialvalued, result. One use for NANs is to detect
uninitialized variables.
destination cannot exactly represent the infinitely
precise true result. For example, a real number
may be rounded if it is stored in a shorter real format, or in an integer format. Or, the infinitely
precise true result may be rounded when it is
returned to a register.
As mentioned earlier, the 8087 stores non-zero
real numbers in "normalized floating point"
form. It also provides for storing and operating
on reals that are not normalized, i.e., whose
significands contain one or more leading zeros.
Nonnormals arise when the result of a calculation
yields a value that is too small to be represented in
normal form. The leading zeros of nonnormals
permit smaller numbers to be represented, at the
cost of some lost precision (the number of significant digits is reduced by the leading zeros). In
typical algorithms, extremely small values are
most likely to be generated as intermediate, rather
than final results. By using the NDP's temporary
real format for holding intermediates, values as
small as ±3.4xlO-4932 can be represented; this
makes the occurrence of nonnormal numbers a
rare phenomenon in 8087 applications. Nevertheless, the NDP can load, store and operate on
nonnormalized real numbers.
The NDP has four rounding modes, selectable by
the RC field in the control word (see figure S-7).
Given a true result b that cannot be represented
by the target data type, the 8087 determines the
two representable numbers a and c that most
closely bracket b in value (a < b < c). The processor then rounds (changes) b to a or to c
according to the mode selected by the RC field as
shown in table S-5. Rounding introduces an error
in a result that is less than one unit in the last
place to which the result is rounded. "Round to
nearest" is the default mode and is suitable for
most applications; it provides the most accurate
and statistically unbiased estimate of the true
result. The "chop" mode is provided for integer
arithmetic applications.
"Round up" and "round down" are termed
directed rounding and can be used to implement
interval arithmetic. Interval arithmetic generates
a certifiable result independent of the occurrence
of rounding and other errors. The upper and
lower bounds of an interval may be computed by
executing an algorithm twice, rounding up in one
pass and down in the other.
Rounding Control
Internally, the 8087 employs three extra bits
(guard, round and sticky bits) which enable it to
represent the infinitely precise true result of a
computation; these bits are not accessible to
programmers. Whenever the destination can
represent the infinitely precise true result, the
8087 delivers it. Rounding occurs in arithmetic
and store operations when the format of the
Precision Control
The 8087 allows results to be calculated with 64,
53, or 24 bits of precision as selected by the PC
field of the control word. The default. setting, and
S-17
8087 NUMERIC DATA PROCESSOR
with affine mode reserved for local computations
where the programmer can take advantage of the
sign and knows for certain that the nature of the
computation will not produce a misleading result.
the one that is best-suited for most applications, is
the full 64 bits. The other settings are required by
the proposed IEEE standard, and are provided to
obtain compatibility with the specifications of
certain existing programming languages. Specifying less precision nullifies the advantages of the
temporary real format's extended fraction length,
and does not improve execution speed. When
reduced precision is specified, the rounding of the
fraction zeros the unused bits on the right.
Exceptions
During the execution of most instructions,
the 8087 checks for six classes of exception
conditions.
Infinity Control
The 8087 reports invalid operation if any of the
following occurs:
The 8087's system of real numbers may be closed
by either of two models of infinity. These two
means of closing the number system, projective
and affine closure, are illustrated schematically in
figure S-12. The setting of the IC field in the control word selects one model or the other. The
default means of closure is. projective, and this is
recommended for most computations. When pro~
jective closure is selected, the NDP treats the
special values +00 and -00 as a single unsigned
infinity (similar to its treatment of signed zeros).
In the affine mode the NDP respects the signs of
+00 and -00.
•
An attempt to load a register that is not
empty, (e.g., stack overflow),
•
An attempt to pop an operand from an
empty register (e.g., stack underflow),
•
•
An operand is a NAN,
The operands cause the operation to be
indeterminate (0/0, square root of a negative
number, etc.).
An invalid operation generally indicates a program error.
While affine mode may provide more information than projective, there are occasions when the
sign may in fact represent mi~information. For
example, consider an algorithm that yields an
intermediate result x of +0 and -0 (the same
numeric value) in different executions. If IIx
were then computed in affine mode, two entirely
different values (+00 and -00) would result from
numerically identical values of x. Projective
mode, on the other hand, provides less information but never returns misinformation. In general,
then, projective mode should be used globally,
If the exponent of the true result is too large for
the destination real format, the 8087 signals
overflow. Conversely, a true exponent that is too
small to be represented results in the underflow
exception. If either of these occur, the result of
the operation is outside the range of the destination real format.
Typical algorithms are most likely to produce
extremely large and small numbers in the calculation of intermediate, rather than final, results.
Because of the great range of the temporary real
format (recommended as the destination format
for intermediates); overflow and underflow are
relatively rare events in most 8087 applications;
If division of a finite non-zero operand by zero is
attempted, the 8087 reports the zerodivide
exception.
If an instruction attempts to operate on a denor·
mal, the NDP reports the denormalized
exception. This exception is provided for users
who wish to implement, in software, an option of
the proposed IEEE standard which specifies that
operands must be prenormalized before they are
used.
o
PROJECTIVE CLOSURE
.
+'"
.~.~-----r------..
o
AFFINE CLOSURE
Figure S-12. Projective Versus Affine Closure
S-18
8087 NUMERIC DATA PROCESSOR
If the result of an operation is not exactly
representable in the destination format, the 8087
rounds the number and reports the precision
exception. This exception occurs frequently and
indicates that some (generally acceptable)
accuracy has been lost; it is provided for applications that need to perform exact arithmetic only.
(assuming the interrupt path is clear). These
responses are summarized in table S-6. Section
S.9 contains a complete description of all exception conditions and the NDP's masked responses.
Note that when ,exceptions are masked, the NDP
may detect multiple exceptions in a single instruction, since it continues executing the instruction
after performing its masked response. For
example, the 8087 could detect a denormalized
operand, perform its masked response to this
exception, and then detect an underflow.
Invalid operation, zerodivide, and denormalized
exceptions are detected before an operation
begins, while overflow, underflow, and precision
exceptions are not raised until a true result has
been computed. When a "before" exception is
detected, the register stack and memory have not
yet been updated, and appear as if the offending
instruction has not been executed. When an
"after" exception is detected, the register stack
and memory appear as if the instruction has run
to completion, i.e., they may be updated.
(However, in a store or store and pop operation,
unmasked over/underflow is handled like a
"before" exception; memory is not updated and
the stack is not popped.) In cases where multiple
exceptions arise simultaneously,one exception is
signalled according to the 'following precedence
sequence:
By writing different values into the exception
masks of the control word, the user can accept
responsibility for handling exceptions, or delegate
this to the NDP. Exception handling software is
often difficult to write, and the 8087's masked'
responses have been tailored to deliver the most
"reasonable" result for each condition. The
majority of applications will find that masking all
exceptions other than invalid operation will yield
satisfactory results with the least programming
investment. An invalid operation exception
normally indicates a fatal error in a program that
must be corrected; this exception should not
normally be masked.
• Denormalized (if unmasked),
•
Invalid operation,
• Zerodivide,
• Denormalized (if masked),
• Over/underflow,
• Precision.
(The terms "masked" and "unmasked" are
explained shortly.) This means, for example, that
zero divided by zero will result in an invalid
operation and not a zerodivide exception. '
The exception flags are "sticky" and can be
cleared only by executing the FCLEX (clear
exceptions) instruction, by reinitializing the processor, or by overwriting the flags with an
FRSTOR or FLDENV instruction. This means
that the flags can provide a cumulative record of
the exceptions encountered in a long calculation.
A program can therefore mask all exceptions (except, typically, invalid operation), run the
calculation and then inspect the status word to see
if any exceptions were detected at any point in the
calculation. Note that the 8087 has another set of
internal exception flags that it clears before each
instruction. It is these flags and not those in the
status word that actually trigger the 8087's exception response. The flags in the status word provide a cumulative record of exceptions for the
programmer only.
The 8087 reports an exception by setting the corresponding flag in the status word to 1. It then
checks the corresponding exception mask in the
control word to determine if it should "field" the
exception (mask=I), or if it should issue an interrupt request to invoke a user-written exception
handler (mask=O). In the first case, the exception
is said to be masked (from user software) and the
NDP executes its on-chip masked response for
that exception. In the second case, the exception
is unmasked, and the processor performs its
unmasked response. The masked response always
produces a standard result and then proceeds with
the instruction. The unmasked response always
traps to user software by interrupting the CPU
If the NDP executes an unmasked response to an
exception, it is assumed that a user exception
handler will be invoked via an interrupt from the
8087. The 8087 sets the IR (interrupt request) bit
in the status word, but this, in itself,. does not
guarantee an immedjate CPU interrupt. The
interrupt request may be blocked by the !EM
(interrupt-enable mask) in the 8087 ,control word,
S-19
8087 NUMERIC DATA PROCESSOR
Table S~6. Exception and Response Summary
Exception
Unmasked Response
Masked Response
Invalid
Operation
If one operand is NAN, return it; if
both are NANs; return NAN with
larger absolute value; if neither is
NAN, return indefinite.
Request interrupt.
Zerodivide
Return co signed with "exclusive
or" of operand,~igns.
Request interrupt.
Denormalized
Memory operand: proceed as
usual. Register operand: convert
to valid unnormal, then re-evaluate
for exceptions.
Request interrupt.
'Overflow'
Return properly signed 00.
Register destination: adjust
exponent', store result, request.
interrupt., Memory destination:
request interrupt.
Underfl()w
Denormalize result.
Register destination: adjust
exponent', store result, request
interrupt. Memory destination:,
request interrupt.
Precision
Return rounded result.
Return rounded result, request
interrupt.
~On overflow, 24,576 decimal is subtracted from the true result's exponent; this forces tlie exponent back
into range arid permits a user exception handler to ascertain the true result from the adjusted result that
is returned. On underflow, the same constant is added to the true result's exponent.
by the 8259A Programmable Interrupt Controller,or by the CPU itself. If any exception flag
is unmasked, it is imperative that the interrupt
path to the CPU is eventually cleared so that the
user's software can field the exception and the
offending task can resume execution. Interrupts
are covered iIi detail in section S.6.
A user-written exception handler takes the form
of an 8086/8088', inte~rupt procedure. Although
exception handlers will vary widely from one
application to the next, most will include these
basic steps:
• Store the 8087 environment (control, status
and tag -words, operand and instruction
pointers) as it existed at the time of the
exception;
• Clear the exception bits in the status word;
• Enable interrupts on the CPU;
• Identify the exception by exammmg the
status and control words in the saved
environment;
•
•
Take application-dependent action;
Return to the point of interruption, resuming
normal execution.
Possible "application-dependent actions"
include:
•
Incrementing a'n exception counter for later
display or printing;
• Printing or displaying diagnostic
information (e.g., the 8087 environment and
registers) ;
• Aborting further execution of the calculation
causing the exception;
• Aborting all furthe~ execution;
• Using the. exception pointers to build an
instruction that will run without exception
and executing it.
• Storing a diagnostic value (a NAN) in the
result and continuing with the computation.
8087 NUMERIC DATA PROCESSOR
Notice that an exception mayor may not constitute an error depending on the application. For
example, an invalid operation caused by a stack
overflow could signal an ambitious exception
handler to extend the register stack to memory
and continue running.
on the CPU to generate the addresses of memory
operands, the NDP can take advantage of the
CPU's memory addressing modes and its ability
to relocate code and data during execution.
5.4 Memory
Figures S-13 and S-14 show how the 8087 data
types are stored in memory. The sign bit is always
located in the highest-addressed byte. The least
significant binary or decimal digits in a number
Data Storage
The 8087 can access any location in its host
CPU's megabyte memory space. Because it relies
+3
!M!
sl~l
+2
+3
+1
+0
l~
jB
+0
WORD INTEGER
sl~1
IE
LM
+2 5151
EF
+1
SHORT INTEGER
IL
IS
+0
+9 51
.1
+8
+7
1
S:~:
-jiij
+7
II)
III
II)
II)
+6
III
a:
c
c
<0:
a:
+5
+6
+5
III
:J:
":;:
+4
+3
+4
+3
.If
(X)
MSD
+9
7
:
SHORT REAL
i
I
+7
I
I
I
+6
L
Is
E
+8
SI~I
E
IMI
+7 1151
I
I~I~I
F
+6
IEIF
!
:~I
5 EI
+5
+5
II)
III
I
II)
II)
+4
I
:
III
a:
+4
c
c
<0:
+3
a:
+3
III
:J:
+2
+2
I
":;:
+2
I
+1
:~
+0
16
I
+1
I
+0
I
I
+1
+1
L
Is
F
+0
LSD
+2
I~
+0
F
o
LONG INTEGER
PACKED DECIMAL
LONG REAL
S: Sign bit
MSB/LSB: Most/least significant bit
MSD/LSD: Most/least significant decinial digit
(X): Bits have no significance
TEMPORARY REAL
5: Sign bit
MSE/LSE: Mostlleast significant exponent bit
MSF /LSF: Mostlleast significant fraction bit
I: Integer bit of slgnificand
Figure S-14. Storage of Real Data Types
Figure S-13. Storage of Integer Data Types
S-21
8087 NUMERIC DATA PROCESSOR
(or in a field in the case of reals) are those with the
lowest addresses. The word integer format is
stored exactly like an 8086/8088 16-bit signed
integer, and is directly usable by instructions
executed on either the CPU or the NDP.
As described in section S.6, the 8087 automatically determines the identity of its host CPU.
When the NDP is wired to an 8088, it transfers
one byte per bus cycle in the same manner as the
CPU. When used with an 8086, the NDP again
operates like the CPU, accessing odd-addressed
words in two bus cycles and even-addressed words
in one bus cycle. If the 8087 is reading or writing
more than one word of an odd-addressed operand
in 8086 memory, it optimizes the transfer by
accessing a byte on the first transfer, forcing the
address to even, and then transferring words up
to the last byte of the operand.
A few special instructions access memory to load
or store formatted processor control and state
data. The formats of these memory operands are
provided with the discussions of the instructions
in section S. 7.
Storage Access
To minimize operand transfer time and 8087 use
Qf the system bus, it is advantageous to align 8087
memory operands on even addresses when the
CPU is an 8086. Following the same practice for
8088-based systems will ensure top performance
without reprogramming if the application is
transferred to an 8086. The ASM-86 EVEN directive can be used to force word alignment.
The host CPU always generates the address of the
first (lowest-addressed) byte of a. memory
operand. The CPU interprets an 8087 instruction
that references memory as an ESC (escape), and
generates the operand's effective and physical
addresses normally as discussed in section 2.3.
Any 8086/8088 memory addressing modedirect, register indirect, based, indexed or based
indexed-can be used to access an 8087 operand
in memory. This makes the NDP easy to use with
data structures sU'ch as arrays, structures, and
lists.
Dynamic Relocation
Since the host CPU takes care of both instruction
fetching and memory operand addressing, the
NDP may be utilized in systems that alter program addresses during execution. The only
restriction on the CPU is that it should not change
the address of an 8087 operand while the 8087 is
executing an instruction which stores a result to
that address. If this is done, the 8087 will store to
the operand's old address (the one it picked up
during the "dummy read").
When the CPU emits the 20-bit physical address
of the memory operand, the 8087 captures the
address and saves it. If the instruction loads
information into the NDP, the 8087 captures the
lowest-addressed word when it becomes available
on the bus as a result of the CPU's "dummy
read." (The "dummy read" .may require either
one or two bus cycles depending on the CPU type
and the alignment of the operand.) If the operand
is longer than one word (all 8087 operands are an
integral number of words), the 8087 immediately
requests use of the local bus by activating its CPU
request! grant (RQ/GTO) line, as described in
section S.6. When the NDP obtains the bus! it
runs consecutive bus cycles incrementing the
saved address until the rest of the operand has
been .obtained, returns the local bus to the CPU,
and then executes the instruction.
Dedicated and Reserved
Memory Locations
The 8087 does not require any addresses in
memory to be set aside for special purposes. Care
should be taken, however, to respect the
dedicated and reserved areas associated with the
CPU and the lOP (see sections 2.3 and 3.3).
Using any of these areas may inhibit compatibility
with current or future Intel hardware and software products.
If an operation stores data from ~he NDP to
memory, the NDP and the CPU both ignore the
data placed on the bus by the CPU's "dummy
read." The NDP does not request the bus from
the CPU until it is ready to write the result of the
instruction to memory. When it obtains the bus,
the NDP writes the operand in successive bus
cycles, incrementing the saved address as in a
load.
S.5 Multiprocessing Features
As a coprocessor to an 8086 or 8088 CPU, the
NDP is by definition always used in a
multiprocessing environment. This section
S-22
8087 NUMERIC DATA PROCESSOR
describes the facilities built into the 8087 that
simplify the coordinaton of mUltiple processor
systems. Included are descriptions of instruction
synchronization, local and system bus arbitration, and shared resource access control.
instruction following the WAIT. If TEST is
active, the CPU examines the pin again. Thus, the
effective execution time of aWAIT can stretch
from 3 clocks (3 clocks are required for decoding
and setup) to infinity, as long as TEST remains
active. The WAIT instruction, then, prevents the
CPU from decoding the next instruction until the
8087 is not busy. The instruction following a
WAIT is decoded simultaneously by both
processors.
Instruction Synchronization
In the execution of a typical NDP instruction, the
CPU will complete the ESC long before the 8087
finishes its interpretation of the same machine
instruction. For example, the NDP performs a
square root in about 180 clocks, while the CPU
will execute its interpretation of this same instruction in 2 clocks. Upon completion of the ESC, the
CPU will decode and execute the next instruction,
and the NDP's CU, tracking the CPU, will do the
same. (The NDP "executes" a CPU instruction
by ignoring it). If the CPU has work to do that
does not affect the NDP, it can proceed with a
series of instructions while the NDP is executing
in parallel; the NDP's CU will ignore these CPUonly instructions as they do not contain the 8087
escape code. This asynchronous execution of the
processors can substantially improve the
performance of systems that can be designed to
exploit it.
To satisfy the first case mentioned above, every
8087 instruction that affects the NEU should be
preceded by aWAIT to ensure that the NEU is
ready. All instructions except the processor
control class affect the NEU. To simplify programming, the 8086 family language translators
provide the WAIT automatically. When an
assembly language programmer codes:
FMUL
FDlV
the assembler produces four machine
instructions, as if the programmer had written:
WAIT
FMUL
WAIT
FDIV
There are two cases, however, when it is necessary
to synchronize the execution of the CPU to the
NDP:
1.
An NDP instruction that is executed by the
NEU must not be started if the NEU is still
busy executing a previous instruction.
2.
The CPU should not execute an instruction
that accesses a memory operand being
referenced by the NDP until the NDP has
actually accessed the location.
;(multiply)
;(divide)
This ensures that the multiply runs to completion
before the CPU and the 8087 CU decode the
divide.
To satisfy the second case, the programmer
should explicitly code the FW AIT instruction
immediately before a CPU instruction that
accesses a memory operand read or written by a
previous 8087 instruction. This will ensure that
the 8087 has read or written the memory operand
before the CPU attempts to use it. (The FW AIT
mnemonic causes the assembler to create a CPU
WAIT instruction that can be eliminated at link
time if the program is to run on an 8087 emulator.
See section S.8 for details.)
The 8086/8088 WAIT instruction allows software
to synchronize the CPU to the NDP so that the
CPU will not execute the following instruction
until the NDP is finished with its current (if any)
instruction.
Figure S-15 is a hypothetical sequence of
instructions that illustrates the effect of the
WAIT instruction and parallel execution of the
NDP with a CPU.
Whenever the 8087 is executing an instruction, it
activates its BUSY line. This signal is wired to the
CPU's TEST input as shown in figure S-3. The
NDP ignores the WAIT instruction, and the CPU
executes it. The CPU interprets the WAIT
instruction as "wait while TEST is active." The
CPU examines the TEST pin every 5 clocks; if
TEST is inactive, execution proceeds with the
The first two instructions in the sequence (FMUL
and FSQRT) are 8087 instructions that illustrate
the ASM-86 assembler's automatic generation of
S-23
8087 NUMERIC DATA PROCESSOR
;ASSUME
,
,
,
8087 REGISTER STACK IS LOADED WITH OPERANDS,
NEU IS NOT BUSY,
.
AND THAT 'ALPHA' AND 'BETA' ARE WORD
INTEGERS.
FMUL
FSQRT
CMP
JG
ALPHA,100
CONTINUE
ALPHA,100
BETA
MOV
AX,BETA
MOV
CONTINUE: FIST
FWA IT
FMUL
NDP:
BUSV ..TEST:
;MULTIPLY TOP STACK
;ELEMENTS
;SQUARE ROOT OF PRODUCT
;ALPHA> 100?
;YES, LEAVE UNALTERED
;NO, SET TO 100
;STORE ROOT AS INTEGER WORD
;WAIT FOR 8087 TO COMPLETE
;STORE OF BETA
;PROCEED TO PROCESS BETA
I I..-I_ _ _ _ _FS_Q_R_T_ _ _ _.....II
V
_---'I
FIST
I
V"'--~'---
NOTES:
. [W~~ = Assembler·generated instruction .
• Instruction execution times are not drawn to scale.
Figure S-15. Synchronizing Execution With WAIT
a preceding WAIT, and the effect of the WAIT
when the NDP is, and is not, busy. Since the NDP
is not busy when the first WAIT is encountered,
the CPU executes it and immediately proceeds to
. the next instruction; the NDP ignores the WAIT.
The next instruction is decoded simultaneously by
both processors. The NDP starts the multiplication and raises its BUSY line. The CPU executes
the ESC and then the second WAIT. Since TEST
is active (it is tied to BUSY), the CPU effectively
stretches execution of this WAIT until the NDP
signals completion of the multiply by lowering
BUSY. The next instruction is interpreted as a
square root by the NDP and another escape by
the CPU. The CPU finishes the ESC well before
the NDP completes the FSQRT. This time, instead of waiting, the CPU executes three instructions (compare, jump if greater, and move) while
the 8087 is working on the FSQRT. The 8087
ignores these CPU-only instructions. The CPU
then encounters the third WAIT, generated by the
assembler immediately preceding the FIST (store
stack top into integer word). When the NDP
finishes the FSQRT, both processors proceed to
the next instruction, FIST to the NDP and ESC to
the CPU. The CPU completes the escape quickly
and then executes an explicit programmer-coded
FWAIT to ensure that the 8087 has updated
BETA before it moves BETA's new value to
register AX.
Mnemonics © Inle11978, 1980
The 8087 CU can execute most processor control
instructions by itself regardless of what the NEU
is doing: thus the 8087 can, in these cases, potentially execute two instructions at once. The
ASM-86 assembler provides separate "wait" and
"no wait" mnemonics for these instructions. For
example, the instruction that sets the 8087 interrupt enable mask, and thus disables interrupts,
can be coded as FDISI or FNDISI. The assembler
does not generate a preceding WAIT if the second
form is coded, so that interrupts can be disabled
while the NEU is busy executing a previous
instruction. The no~wait forms are principally
used in exception handlers and operating systems.
Local Bus Arbitration
Whenever an NDP instruction writes data to
memory, or reads more than one word from
memory, the NDP forces the CPU to relinquish
the local bus. It does this by means of the
request/grant facility built into all 8086 family
processors. For memory reads, the NDP requests
the bus immediately upon the CPU's completion
of its "dummy read" cycle; it follows from this
that the CPU may "immediately" update a
variable read by the NDP in the previous instruction with the assurance that the NDP will have
obtained the old value before the CPU has altered
it. For memory writes, the NDP performs as
S-24
8087 NUMERIC DATA PROCESSOR
much processing as possible before requesting the
bus. In all cases, the 8087 transfers the data in
back-to-back bus cycles and then immediately
releases the bus.
System Bus Arbitration
A single 8288 Bus Controller (plus latches and
tranceivers as required) links both the host CPU
and the NDP to the system bus. The 8087 performs system bus transfers exactly the same as its
CPU; status, address, and data signals and timing
are identical.
The 8087's RQ/GTO line is wired to one of the
CPQLrequest/grant lines. Connecting it to
RQ/GTI on th~PU (see figure S-3) leaves the
higher priority RQ/GTO open for possible attachment of a local 8089 to the CPU. Note that an
8089 on RQ/GTO will obtain the bus if it requests
it simultaneously with an 8087 attached to
RQ/GTl; it cannot, however, preempt the 8087 if
the 8087 has the bus. The NDP requests the local
bus by pulsing its RQ/GTO line. If the CPU has
the bus, it will grant it to the NDP by pulsing the
same request/grant line. The CPU grants the bus
immediately unless it is running a bus cycle, in
which case the grant is delayed until the bus cycle
is completed. The NDP releases the bus back to
the CPU by sending a final pulse on RQ/GTO
when it has completed the transfer.
In systems that allow multiple processing modules
on separate local buses common access to a public
system bus, the 8087 also shares its host CPU's
8289 Bus Arbiter. The 8289 operates identically
regardless of whether the system bus request is
initiated by the CPU or the NDP. Since only one
of the processors in the module will have control
of the local bus at the time of a request to access
the system bus, the transfer will be between the
controlling processor and the system bus. If the
8289 does not obtain the system bus immediately,
it causes the bus to appear "not ready" (as if a
slow memory were being accessed), and the 8087
will stretch the bus cycle by adding the wait states.
The 8087 provides a second request/grarit line,
RQ/GTl, that may be used to service local bus
requests from an 8089 Input/Output Processor
(see figure S-3). By using this line, a CPU, two
lOPs (one is attached directly to the CPU) and an
NDP can all reside on the same local bus, sharing
a single set of system bus interface components.
Because it presents the same system bus interface
as a maximum mode 8086 family CPU, the NDP
is also electrically compatible with lntel's
Multibus™ shared system bus architecture. This
means that the 8087 can be utilized in systems that
are based on the broad line of iSBCTM single
board computers, controllers, and memories.
When the 8087 detects a bus request pulse on
RQ/GTl, its response depends on whether it is
idle, executing, or running a bus cycle. If it is idle
or executing, the 8087 passes the bus request
through to the CPU via RQ/GTO. The subsequent grant and release pulses are also passed
between the CPU and the requesting device. If the
8087 is running a bus cycle (or a series of bus
cycles), it has already obtained the bus from the
CPU so it grants the bus directly at the end of the
current bus cycle rather than passing the request
on to the CPU. When the 8089 releases the bus,
the 8087 resumes the series of bus cycles it was
running before it granted the bus to the 8089.
Thus, to an 8089 attached to the 8087's RQ/GTI
line, the NDP appears to be a CPU. An lOP
attached to an NDP also effectively has higher
local bus priority than the NDP, since it can force
the NDP to relinquish the bus even in the midst of
a multi-cycle transfer. This satisfies the typical
system requirement for 1/0 transfers to be serviced as soon as possible.
Controlled Variable Access
If an 8087 and a processor other than its host
CPU can both update a variable, access to that
variable should be· controlled so that one
processor at a time has exclusive rights to it. This
may be implemented by a semaphore convention
as described in section 2.5. However, since the
8087 has no facility for locking the system bus
during an instruction, the host CPU should
obtain exclusive rights to the variable before the
8087 accesses it. This can be done using an XCHG
instruction prefixed by LOCK as discussed in
section 2.5. When the NDP no longer needs the
controlled variable the CPU should clear the
semaphore to signal other processors that the
variable is again available for use.
S-25
8087 NUMERIC DATA PROCESSOR
5.6 Processor Control and
Monitoring
The FINIT (intialize) and FSAVE (save state)
instructions also initialize the processor. Unlike a
RESET pulse, software initialization does not
affect the 8087's tracking of the CPU.
Initialization
CPU Identification
The NDP may be initialized by hardware or software. Hardware initialization occurs in response
to a pulse on the 8087's RESET line. When the
processor detects RESET going active, it suspends
all activities. When RESET subsequently goes
inactive, the NDP initializes itself. The state of
the NDP following initialization is shown in table
S-7. Hardware initialization also causes the 8087
to identify its host CPU and begin to track its
instruction fetches and execution. Initialization
does not affect the content of the registers or of
the exception pointers (these have indeterminate
values immediately following power up).
However, since the stack is effectively emptied by
initialization (ST = 0, all registers tagged empty),
the contents of the registers should normally be
considered "destroyed" by initialization.
The 8087's bidirectional BHE (bus high enable)
line is tied to pin 34 of the CPU (BHE on the
8086, SSO on the 8088). The 8088 always holds
SSO = 1 . The 8086 emits a 0 on BHE whenever it
is accessing an even-addressed word or an oddaddressed byte.
Following RESET, the CPU always performs a
word fetch of its first instruction from the
dedicated memory location: FFFFOH. The 8087
identifies its host CPU by monitoring BHE
during the CPU's first fetch following RESET. If
BHE =1, the CPU is an 8088; if BHE =0, the
CPU is an 8086 (because the first fetch is an evenaddressed word). Note that to ensure proper
operation, the same pulse must reset both the
8087 and its host CPU.
Table S-7. Processor State Following Initialization
Field
Control Word
Infinity Control
Rounding Control
Precision Control
Interrupt-enable Mask
Exception Masks
Value
Interpretation
0
00
11
1
111111
Projective
Round to nearest
64 bits
Interrupts disabled
All exceptions masked
0
000
0
000000
Not busy
(indeterminate)
Empty stack
No interrupt
No exceptions
Tag Word
Tags
11
Empty
Registers
N.C.
Notchanged
Exception Pointers
Instruction Code
Instruction Address
Operand Address
N.C.
N.C.
N.C.
Notchanged
Not changed
Not chan\jed
Status Word
Busy
Condition Code
Stack Top
Interrupt Request
Exception Flags
????
S-26
8087 NUMERIC DATA PROCESSOR
clear the interrupt request bit before returning to
normal execution on the 8087. If it does not, the
interrupt will immediately be generated again and
the program will enter an endless loop.
Interrupt Requests
The 8087 can request an interrupt of its host CPU
via the 8087 INT (interrupt request) pin. This
signal is normally routed to the CPU's INTR
input via an 8259A Programmable Interrupt
Controller (PIC). The 8087 should not be tied to
the CPU's NMI (non-maskable interrupt) line.
Interrupt Priority
Most systems can be viewed as consisting of two
distinct classes of software: interrupt handlers
and application tasks. Interrupt handlers execute
in response to external events; in the 8086 family
they are implemented as interrupt service
procedures. (Of course, the CPU interrupt
instructions allow interrupt handlers to respond
to internal "events" also.) A hardware interrupt
controller, such as the 8259A, usually monitors
the external events and invokes the appropriate
interrupt handler by activatiog the CPU INTR
line, and passing a code to the CPU that identifies
the interrupt handler that is to service the event.
Since the 8259A typically monitors several events,
a priority-resolving technique is used to select one
All 8087 interrupt requests originate in the detection of an exception. The interrupt request logic is
illustrated in figure S-16. The interrupt request
is made if the exception is unmasked and 8087
interrupts are enabled, i.e . , both the relevant
exception mask and the interrupt-enable mask are
clear (0). If the exception is masked, the processor
executes its masked response and does not set the
interrupt request bit.
If the exception is unmasked but interrupts are
disabled (IBM = 1), the 8087's action depends on
whether the CPU is waiting (the 8087 "knows" if
the CPU is waiting because it decodes the WAIT
instruction in parallel with the CPU). If the CPU
is not waiting, the 8087 assumes that the CPU
does not want to be interrupted at present and
that it will enable interrupts on the 8087 when it
does. The 8087 sets the interrupt request bit and
holds its BUSY line active. The 8087 CU continues to track the CPU, and if an 8087
instruction (without a preceding WAIT) comes
along, it will be executed. Normally in this situation the instruction would be FNENI (enable
interrupts without waiting). This will clear the
interrupt-enable mask and the 8087 will then
activate INT. However, any instruction will be
executed, and it is therefore conceivably possible
to abort the interrupt request before it is ever
handled. Aborting an interrupt request in this
manner, however, would normally be considered
a program error.
If the CPU is waiting, then the processors are in
danger of entering an endless wait condition
(discussed shortly). To prevent this condition, the
8087 ignores the fact that interrupts are disabled
and activates INT even though the interruptenable mask is set.
The interrupt request bit remains set until it is
explicitly cleared (if INT is not disabled by IBM,
it will remain active also). This can be done by the
FNCLEX, FNSA VE, or FNINT instructions. The
interrupt procedure that fields the 8087's interrupt request, i.e., the exception handler, must
Figure S-16. Interrupt Request Logic
S-27
8087 NUMERIC DATA PROCESSOR
event when several Occur simultaneously. Many
systems allow higher-priority interrupts to
preempt lower-priority interrupt handlers. The
8259A supports several priority-resolving techniques; a system will normally select one of these by
programming the 8259A at initialization time.
should be done by executing the FNSTCW and
FNDISI instructions before enabling CPU interrupts. Before returning, the interrupt handler
should restore the original control word in the
8087 by executing FLDCW.
Users should consult "Using the 8259A Programmable Interrupt ControlJer", Intel Application
Note No. AP-59, for a description of the 8259A's
various modes of operation.
Application tasks execute only when no external
event needs service, i.e., when no interrupt
handler is running. Application tasks are invoked
by software, rather "than hardware; typically a
scheduling or dispatching algorithm is used to
select one task for execution. In effect, any interrupt handler has higher priority than any application task, since the recognition of an interrupt will
invoke the interrupt handler, preempting the
application task that was running.
Endless Wait
The 8087 and its host CPU can enter an endless
wait condition when the CPU is executing a
WAIT instruction and a pending interrupt request
from the 8087 is prevented from being recognized
by the CPU. Thus, the CPU will wait for the 8087
to lower its BUSY line, while the NDP will wait
for the CPU to invoke the exception handler
interrupt procedure, and the task which has
generated the exception will be blocked from
further execution.
There are two important questions to consider
when assigning a priority to the 8087's interrupt
request:
•
•
Who can cause 8087 exceptions-only
application tasks, or interrupt handlers as
well?
Figure S-17 shows the typical path of an interrupt
request from the· 8087 to the interrupt procedure
which is design&ted to field NDP exceptions. The
interrupt request can be potentially blocked at
three points. along the path, creating an endless
wait if the CPU is executing a WAIT instruction.
The first block can occur at the 8087's interruptenable mask (lEM). If this mask is set, the interrupt request is blocked except that the 8087 will
override the mask if the CPU is waiting (the 8087
decodes the WAIJ' instruction simultaneously
with the CPU). Thus, the 8087 detects apd
prevents one of the endless wait conditions.
Who should be preempted by NDP
exceptions-only applications tasks, or interrupt handlers as well?
Given these considerations, the 8087 should
normally be assigned the lowest priority of any
interrupting device in the system. This allows the
interrupt handler (Le., the NDP exception
handler) to preempt any application task that
generates an 8087 exception, and at the same time
prevents the exception NDP handler from
interfering with other interrupt handlers.
A given interrupt request, IRn, can be masked on
the 8259A by setting the corresponding bit in the
PIC's interrupt mask register (IMR). This will
prevent a request from the 8087 from being
passed to the CPU. (The 8259A's normal priorityresolving activity can also block an interrupt
request.) Finally, the CPU can exclude all
interrupts tied to INTR by clearing its interruptenable flag (IF). In these two cases, the CPU can
"escape" the endless wait only if another interrupt is recognized (if IF is cleared, the interrupt
must arrive on NMI, the CPU's non-maskable
interrupt line). Following execution of the interrupt procedure and resumption of the WAIT; the
endless wait will be entered again, unless, as part
of its response to the interrupt it recognizes, the
CPU clears the interrupt path from the 8087,
If an interrupt handler uses the 8087 and requires
the service of the exception handler, it can effectively "raise" the priority of the exception
handler by disabling all interrupts lower than
itself and higher than the 8087. Then,any unmasked exception caused by the interrupt handler
will be fielded without interference from lowerpriority interrupts.
If, for some reason, the 8087 must be given higher
priority than another interrupt source, the interrupt handler that services the lower-priority
device may want to prevent interrupts from the
8087 (which may originate in a long instruction
still running on the 8087 when the interrupt
handler is invoked) from preempting it. This
S-28
8087 NUMERIC DATA PROCESSOR
A user-written exception handler can itself cause
an unending .wait. When the exception handler
starts to run, the 8087 is suspended with its BUSY
line active, waiting for the exception to be
cleared, and interrupts on the CPU are disabled.
If, in this condition, the exception handler issues
any 8087 instruction, other than a no-wait form,
the result will be an unending wait. To prevent
this, the exception handler should clear the exception on the 8087 and enable interrupts on the
CPU before executing any instruction that is
preceded by aWAIT.
speed, bus transfers, and exceptions, as well
as a coding example for each combination of
operands accepted by the instruction. This
information is concentrated in a table, organized
alphabetically by instruction mnemonic, for easy
reference.
Throughout this section, the instruction set is
described as it appears to the ASM-86 programmer who is coding a program. Appendix A covers
the actual machine instruction encodings, which
are principally of use to those reading unformatted memory dumps, monitoring instruction
fetches on the bus, or writing exception handlers.
More generally, an instruction that is preceded by
aWAIT (or an FW AIT instruction) should never
be executed when CPU interrupts are disabled
and there is any possibility that the 8087's BUSY
line is active.
The instruction descriptions in this section concentrate on describing the normal function of
each operation. Table S-19 lists the exceptions
that can occur for each instruction and table S-32
details the causes of exceptions as well· as the
8087's masked responses.
Status Lines
When the 8087 has control of the local bus, it
emits signals on status lines S2-S0 to identify
the type of bus cycle it is running. The 8087
generates the restricted (compared to a CPU) set
of encodings shown in table S-8. These lines
correspond exactly to the signals output by the
8086 and 8088 CPU's, and are normally decoded
by an 8288 Bus Controller.
The typical NDP instruction accepts one or tW(
operands as "inputs", operates on these, anc
produces a result as an "output". Operands are
Table S-8. Bus Cycle Status Signals
S2
Sl
-
So
1
Type of Bus Cycle
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive; no bus cycle
8087
1
Status line S7 is currently identical to BHE of the
same bus cycle, while S4 and S3 are both currently
1; however, these signals are reserved by Intel for
possible future use. Status line S6 emits 1 and S5
emits 0 . · ·
.
r
8259A
1
S.7 Instruction Set
1
CPU
This section describes the operation of each of the
8087's 69 instructions. The first part of the
section describes the function of each instruction
in detail. For this discussion, the instructions are
divided into six functional groups: data transfer,
arithmetic, comparison, transcendental, constant, and processor controL The second part
provides instruction attributes such as execution
1
_ -{l EXCEPTION
, HANDLER
Figure S-17. Interrupt Request Path
S-29
8087 NUMERIC DATA PROCESSOR
Data Transfer Instructions
most ,often (the contents of) register or memory
locations. The, operands of some instructions are
predefined; for example, FSQRT always taiST(1) then FPREM must be
executed again; if ST=ST(1) then the remainder is
0; if ST source
ST < source
ST= source
ST? source
FTST
FTST (test) tests the top stack element by comparing it to zero. The result is posted to the condition
codes as follows:
C3
CO
Result
0
0
0
1
1
1
0
1
ST is positive and
nonzero
ST is negative and
nonzero
STiszero(+ or-)
ST is not comparable (i.e., it is a
NAN or projective
NANs and 00 (projective) cannot be compared
and return C3=CO= 1 as shown above.
Table S-12. Comparison Instructions
FCOM
FCOMP
FCOMPP
FICOM
FICOMP
FTST
FXAM
Compare real
Compare real and pop
Compare real and pop twice
Integer compare
Integer compare and pop
Test
Examine
00)
FXAM
FXAM (examine) reports the content of the top
stack element as positive/negative and NAN/
unnormalldenormallnormallzero, or empty.
Table S-13 lists and interprets all the condition
code values that FXAM generates. Although four
different encodings may be returned for an empty
register, bits C3 and CO of the condition code are
both 1 in all encodings. Bits C2 and Cl should be
ignored when examining for empty.
FCOMP / /source
FCOMP (compare real and pop) operates like
FCOM, and in addition pops the stack.
FCOMPP
Transcendental Instructions
FCOMPP (compare real and pop twice) operates
like FCOM and additionally pops the stack twice,
discarding both operands. The comparison is of
the stack top to ST(I); no operands may be
explicitly coded.
The instructions in this group (table S-14) perform the time-consuming core calculations for all
common trigonometric, inverse trigonometric,
hyperbolic, inverse hyperbolic, logarithmic and
exponential functions. Prologue and epilogue
software may be used to reduce arguments to the
range accepted by the instructions and to adjust
the result to correspond to the original arguments
if necessary. The transcendentals operate on the
top one or two stack elements and they return
their results to the stack also.
FICOM source
FICOM (integer compare) converts the source
operand, which may Jeference a word or short
binary integer variable, to temporary real and
compares the stack top to it.
Mnemonics © Intel 1980
S-36
8087 NUMERIC DATA PROCESSOR
ensure that operands are valid and in-range
before executing a transcendental. For periodic
functions, FPREM may be used to bring a valid
operand into range.
Table S-13. FXAM Condition Code Settings
Condition Code
CO
Interpretation
C3
C2
C1
0
0
0
0
+ Unnormal
0
0
0
1
+ NAN
0
0
1
0
- Unnormal
0
0
1
1
-NAN
0
1
0
0
0
1
0
1
+ Normal
+00
0
1
1
0
- Normal
0
1
1
1
- 00
1
0
0
0
+0
1
0
0
1
Empty
1
0
1
0
-0
1
0
1
1
Empty
FPTAN
FPT AN (partial tangent) computes the function
YIX = TAN (0). 0 is taken from the top stack
element; it must lie in the range 0 < 0 < 11/4. The
result of the operation is a ratio; Y replaces 0 in
the stack and X is pushed, becoming the new
stack top.
The ratio result of FPT AN and the ratio argument of FP AT AN are designed to optimize the
calculation of the other trigonometric functions,
including SIN, COS, ARCSIN and ARCCOS.
These can be derived from TAN and ARCTAN
via standard trigonometric identities.
1
1
0
0
+ Denormal
1
1
0
1
Empty
1
1
1
0
- Denormal
FPATAN
1
1
1
1
Empty
FP AT AN (partial arctangent) computes the function 0 = ARCTAN (Y IX). X is taken from the
top stack element and Y from ST(l). Y and X
must observe the inequality 0 < Y < X < 00. The
instruction pops the stack and returns 0 to the
(new) stack top, overwriting the Y operand.
Table S-14. Transcendental Instructions
FPTAN
Partial tangent
FPATAN
Partial arctangent
F2XM1
2X-1
FYL2X
Y -IOQ2X
FYL2XP1
Y - IOQ2(X + 1)
F2XM1
F2XM1 (2 to the X minus 1) calculates the function Y = 2x -1. X is taken from the stack top and
must be in the range 0 ~ X ~ 0.5. The result Y
replaces X at the stack top.
The transcendental instructions assume that their
operands are valid and in-range. The instruction
descriptions in this section provide the range of
each operation. To be considered valid, an
operand to a transcendental must be normalized;
denormals, unnormals, infinities and NANs are
considered invalid. (Zero operands are accepted
by some functions and are considered out-ofrange by others.) If a transcendental operand is
invalid or out-of-range, the instruction will
produce an undefined result without signalling an
exception. It is the programmer's responsibility to
This instruction is designed to produce a very
accurate result even when X is close to zero. To
obtain Y=2x , add 1 to the result delivered by
F2XMl.
The following formulas show how values other
than 2 may be raised to a power of X:
10X = 2xoLOG210
S-37
eX =
2xoLOG2e
yX =
2xoLOG2Y
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table 8-15. Constant Instructions
As shown in the next section,the 8087 has built-in
instructions for loading the constants LOG 21O
and LOG 2e, and the FYL2X instruction may be
used to calculate XeLOG 2Y.
FYL2X
FYL2X (Y log base 2 of X) calculates the function
Z ~ YeLOGz'{. Xis taken from the stack top and
Y from ST(1). The operands must be in the ranges
0< X < 00 and - 00 < Y < + 00. The instruction
pops the stack and returns Z at the (new) stack
top, replacing the Y operand.
This function optimizes the calculation of log to
any base other than two since a multiplication is
always required:
FLDZ
Load +0.0
FLD1
Load +1.0
FLDPI
Loadrr
FLDL2T
Load IOQ21O
FLDL2E
Load IOQ2e
FLDLG2
Load IOQ102
FLDLN2
Load IOQ e2
FLDZ
FLDZ (load zero) loads (pushes) +0.0 onto the
stack.
FLD1
FYL2XP1
FLDl (load one) loads (pushes)
stack.
FYL2XPI (Y log base 2 of (X + I)) calculates
the function Z = YeLOG 2 (X+I). X is taken
from the. stack top and must be in the range
0< IXI< (l -('\[ii2)). Y is taken from ST(l) and
must be in the range - 00 < Y < 00. FYL2XPI
pops the stack and returns Z at the (new) stack
top, replacing Y.
+ 1.0 onto the
FLOPI
FLDPI (load rr) loads (pushes) rr onto the stack.
FLDL2T
This instruction provides improved accuracy over
FYL2X when computing the log of a number very
close to I, for example I + E where E < < 1.
Providing E rather than I + E as the input to the
function allows more significant digits to be
retained.
FLDL2T (load log base 2 of 10) loads (pushes) the
value LOG 2 1O onto the stack.
FLOL2E
FLDL2E (load log base 2 of e) loads (pushes) the
value LOG 2e onto the stack.
Constant Instructions
FLDLG2
Each of these instructions (table S-15) loads
(pushes) a commonly-used constant onto the
stack. The values have full temporary real precision (64 bits) and are accurate to approximately
19 decimal digits. Since a temporary real constant
occupies 10 memory bytes, the constant instructions, which are only two bytes long, save storage
and improve execution speed, in addition to
simplifying programming.
Mnemonics © Intel 1980
FLDLG2 (load log base 10 of 2) loads (pushes)
the value LOG 102 onto the stack.
FLDLN2
FLDLN2 (load log base e of 2) loads (pushes) the
value LOGe2 onto the stack.
S-38
8087 NUMERIC DATA PROCESSOR
Processor Control Instructions
FDISI/FNDISI
Most of these instructions (table S-16) are not
used in computations; they are provided principally for system-level activities. These include
initialization, exception handling and task
switching.
FDlSIIFNDlSI (disable interrupts) sets the interrupt enable mask in the control word and
prevents the NDP from issuing an interrupt
request.
Table S-16. Processor Control Instructions
As shown in table S-16, an alternate mnemonic is
available for many of the processor control
instructions. This mnemonic, distinguished by a
second character of "N", instructs the assembler
to not prefix the instruction with a CPU WAIT
instruction (instead, a CPU NOP precedes the
instruction). This "no-wait" form is intended for
use in critical code regions where a WAIT instruction might precipitate an endless wait. Thus,
when CPU interrupts are disabled, and the NDP
can potentially generate an interrupt, the no-wait
form should be used. When CPU interrupts are
enabled, as will normally be the case when an
application task is running, the "wait" forms of
these instructions should be used.
FINIT I FNINIT
Initialize processor
FDISII FNDISI
Disable interrupts
FENI/FNENI
Enable interrupts
FLDCW
Load control word
FSTCW I FNSTCW
Store control word
FSTSW I FNSTSW
Store status word
FCLEX/FNCLEX
Clear exceptions
FSTENV I FNSTENV
Store environment
FLDENV
Load environment
FSAVE/FNSAVE
Save state
FRSTOR
Restore state
FINCSTP
Increment stack pointer
FDECSTP
Decrement stack pointer
FFREE
Free register
FNOP
No operation
FWAIT
CPU wait
Except for FNSTENV and FNSAVE, all instructions which provide a no-wait mnemonic are selfsynchronizing and can be executed back-to-back
in any combination without intervening FWAITs.
These instructions can be executed by the 8087
CU while the NEU is busy with a previously
decoded instruction. To insure'that the processor
control instruction executes after completion of
any operation in progress in the NEU, the \'wait"
form of that instruction should be used.
FENI/FNENI
FINIT IFNINIT
FENIIFNENI (enable interrupts) clears the interrupt enable mask in the control word, allowing
the 8087 to generate interrupt requests.
FLDCW source
FINIT IFNINIT (initialize processor) performs
the functional equivalent of a hardware RESET
(see section S.6), except that it does not affect the
instruction fetch synchronization of the 8087 and
its CPU.
FLDCW (load control word) replaces the current
processor control word with the word defined by
the source operand. This instruction is typically
used to establish, or change, the 8087's mode of
operation. Note that if an exception bit in the
status word is set, loading a new control word
that unmasks that exception and clears the interrupt enable mask will generate an immediate
interrupt request before the next instruction is
executed. When changing modes, the recommended procedure is to first clear any exceptions
and then load the new control word.
For compatibility with the 8087 emulator, a
system should call the INIT87 procedure in lieu of
executing FINIT IFNINIT when the processor is
first initialized (see section S.8 for details). Note
that if FNINIT is executed while a previous 8087
memory referencing instruction is running, 8087
bus cycles in progress will be aborted.
S-39
MnemoniCS © Intel 1980
8087 NUMERIC DATA PROCESSOR
FSA VE/FNSA VE is useful whenever a program
wants to save the current state of the NDP and
initialize it for a new routine. Three examples are:
FSTCW IFNSTCW destination
FSTCW IFNSTCW (store control word) writes
the current processor control word to the memory
10catiQn defined by the destination.
FSTSW IFNSTSW destination
FSTSW IFNSTCW (store status word) writes the
current value of the 8087 status word to the
destination operand in memory. The instruction
has many uses:
•
to implement conditional branching
following a comparison or FPREM instruction (FSTSW);
•
to poll the 8087 to determine if it is busy
(FNSTSW);
•
to invoke exception handlers in environments
that do not use interrupts (FSTSW).
•
an operating system needs to perform a
context switch (suspend the task that had
been running and give control to a new task);
•
•
an interrupt handler needs to use the 8087;
an application task wants to pass a "clean"
8087 to a subroutine.
FNSAVE must be "protected" by executing it in
a critical region, i.e., with CPU interrupts disabled. This prevents an interrupt handler from
executing a second FNSA VE (or other "no-wait"
processor control instruction that references
memory) which could destroy the first FNSA VE
if it is queued in the 8087. An FW AIT should be
executed before CPU interrupts are enabled or
any subsequent 8087 instruction is executed.
(Because the FNSA VE initializes the NDP, there
is no danger of the FW AIT causing an endless
wait.) Other CPU instructions may be executed
between the FNSA VE and the FW AIT; this
parallel execution will reduce interrupt latency if
the FNSA VE is queued in the 8087.
FCLEX/FNCLEX
FCLEX/FNCLEX (clear exceptions) clears all
exception flags, the interrupt request flag and the
busy flag in the status word. As a consequence,
the 8087's INT and BUSY lines go inactive. An
exception handler must issue this instruction
before returning to the interrupted computation,
or another interrupt request will be generated
immediately, and an endless loop may result.
FRSTOR source
FRS TOR (restore state) reloads the 8087 from the
94-byte memory area defined by the source
operand. This information should have been written by a previous FSA VE/FNSA VE instruction
and not altered by any other instruction. CPU
instructions (that do not reference the save image)
may immediately follow FRSTOR, but no NDP
instruction should be without an intervening
FW AIT or an assembler-generated WAIT.
FSAVE/FNSAVE destination
FSA VE/FNSA VE (save state) writes the full 8087
state-environment plus register stack-to the
memory location defined by the destination
operand. Figure S-18 shows the layout of the 94byte save area; typically the instruction will be
coded to save this image on the CPU stack. If an
instruction is executing in the 8087 NEU when
FNSAVE is decoded, the CPU queues the
FNSA VE and delays its execution until the running instruction completes normally or
encounters an .unmasked exception. Thus, the
save image reflects the state of the NDP following
the completion of any running instruction. After
writing the .state image to memory,
FSAVE/FNSA VE initializes the 8087 as if
FINIT IFNINIT had been executed.
Note that the 8087 "reacts" to its new state at the
conclusion of the FRSTOR; it will for example,
generate an immediate interrupt request if the
exception and mask bits in the memory image so
indicate.
FSTENV IFNSTENV destination
FSTENV IFNSTENV (store environment) writes
the 8087's basic status-control, status and tag
words, and exception pointers-to the memory
location defined by the destination operand.
Typically the environment is saved on the CPU
stack. FSTENV IFNSTENV is often used by
Mnemonics © Intel 1980
S-40
8087 NUMERIC DATA PROCESSOR
exception handlers because it provides access to
the exception pointers which identify the offending instruction and operand. After saving the
environment, FSTENV IFNSTENV sets all exception masks in the processor; it does not affect the
interrupt-enable mask. Figure S-19 shows the format of the environment data in memory. If
FNSTENV is decoded while another instruction is
executing concurrently in the NEU, the 8087
queues the FNSTENV and does not store the
environment until the other instruction has completed. Thus, the data saved by the instruction
reflects the 8087 after any previously decoded
instruction has been executed.
FSTENV IFNSTENV must be allowed to complete before any other 8087 instruction is
decoded. When FSTENV is coded, an explicit
FW AIT, or assembler-generated WAIT, should
precede any subsequent 8087 instruction. An
FNSTENV must be executed in a critical region
that is protected from interruption, in the same
manner as FNSA VE. (There is no risk of the
following FW AIT causing an endless wait,
because FNSTENV masks all exceptions, thereby
preventing an interrupt request from the 8087.)
INCREASING ADDRESSES
:=iJ
H::!
15
CONTROL WORD
INCREASING ADDRESSES
STATUS WORD
15
INSTRUCTION {
POINTER
CONTROL WORD
+0
STATUS WORD
+2
TAG WORD
+4
IP1S-0
+6
IP19-16 101
OPCODE
OP15-0
OPERAND {
POINTER
OP19-16 1
TOP STACK {
ELEMENT:ST
sl
NEXT STACK
ELEMENT:ST(1)
{
OPERAND {
POINTER
+8
0
+14
SIGNIFICAND 31-16
+16
sl
SIGNIFICAND 47-32
+18
SIGNIFICAND 63-48
+20
OP19-16I
+8
+10
0
+12
FLDENV (load environment) reloads the 8087
environment from the memory area defined by
the source operand. This data should have been
written by a previous FSTENV IFNSTENV
instruction. CPU instructions (that do not
reference the environment image) may
immediately follow FLDENV, but no subsequent
NDP instruction should be executed without an
intervening FW AIT or assembler-generated
WAIT.
+22
SIGNIFICAND 15-0
+24
SIGNIFICAND 31-16
+26
SIGNIFICAND 47-32
+28
+30
EXPONENT 14-0
+32
SIGNIFICAND 15-0
+84
SIGNIFICAND 31-16
+86
SIGNIFICAND 47-32
+88
SIGNIFICAND 63-48
+90
EXPONENT 14-0
OP1S-0
FLDENV source
~
LASTSTACK {
ELEMENT:ST(7)
+6
OPCODE
+12
SIGNIFICAND 15-0
EXPONENT 14-0
IP19-16I 01
+4
IP1S-0
Figure S-19. FSTENV IFLDENV Memory
Layout
+10
SIGNIFICAND 63-48
sl
INSTRUCTION {
POINTER
TAG WORD
Note that loading an environment image that contains an unmasked exception will cause an
immediate interrupt request from the 8087
(assuming IEM=O in the environment image).
FINCSTP
+92
FINCSTP (increment stack pointer) adds 1 to the
stack top pointer (ST) in the status word. It does
not alter tags or register contents, nor does it
transfer data. It is not equivalent to popping the
stack since it does not set the tag of the previous
stack top to empty. Incrementing the stack
pointer when ST=7 produces ST=O.
NOTES:
S; Sign
Bit 0 of each field is rightmost, least significant bit of corresponding
register field.
Bit 63 of significand is integer bit (assumed binary point is immediately
to the right)_
Figure S-18. FSAVE/FRSTOR Memory
Layout
S-41
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
FDECSTP
tion until the 8087 instruction has completed. The
following coding shows how FW AIT can be used
to force the CPU instruction to wait for the 8087:
FDECSTP (decrement stack pointer) subtracts 1
from ST, the stack top pointer in the status word.
No tags or registers are altered, nor is any data
transferred. Executing FDECSTP when ST=O
produces ST=7.
FNSTSW
FWAIT
MOV
STATUS
;Wait for FNSTSW
AX,STATUS
Programmers should not code WAIT to
synchronize the CPU and the NDP. The routines
that alter an object program for 8087 emulation
eliminate FW AITs (and assembler-generated
WAITs) but do not change any explicitly coded
WAITs. The program will wait forever if aWAIT
is encountered in emulated execution, since there
is no 8087 to drive the CPU's TEST pin active.
FFREE destination
FFREE (free register) changes the destination
register's tag to empty; the content of the register
is unaffected.
FNOP
Instruction Set Reference Information
FNOP (no operation) stores the stack top to the
stack top (FST ST ,ST(O» and thus effectively
performs no operation.
Table S-19 lists the operating characteristics of all
the 8087 instructions. There is one table entry for
each instruction mnemonic; the entries are in
alphabetical order for quick lookup. Each entry
provides the general operand forms accepted by
the instruction as well as a list of all exceptions
that may be detected during the operation.
FWAIT (CPU instruction)
FW AIT is not actually an 8087 instruction, but an
alternate mnemonic for the CPU WAIT instruction described in section 2.8. The FWAIT
mnemonic should be coded whenever the programmer wants to synchronize the CPU to the
NDP, that is, to suspend further instruction
decoding until the NDP has completed the current
instruction. A CPU instruction should not
attempt to access a memory operand that has
been read. or written by a previous 8087 instruc-
There is one entry for each combination of
operand types that can be coded with the
mnemonic. Table S-17 explains the operand identifiers allowed in table S-19. Following this entry
are columns that provide execution time in clocks,
the number of bus transfers run during the operation, the length of the instruction in bytes, and an
ASM-86 coding sample.
Table S-17. Key to Operand Types
Explanation
Identifier
ST
Stack top; the register currently at the top of the stack.
ST(i)
A register in the stack i (0..;i..;7) stack elements from the
top. ST(1) is the next-on-stack register, ST(2) is below
ST(1), etc.
Short-real
A short real (32 bits) number in memory.
Long-real
A long real (64 bits) number in memory.
Temp-real
A temporary real (80 bits) number in memory.
Packed-decimal
A packed decimal integer (18 digits, 10 bytes) in memory.
Word-integer
A word binary integer (16 bits) in memory.
Short-integer
A short binary integer (32 bits) in memory.
Long-integer
A long binary integer (64 bits) in memory.
nn-bytes
A memory area nn bytes long.
Mnemonics © Intel 1980
S-42
8087 NUMERIC DATA PROCESSOR
decrease execution time from the typical figure,
but it will still fall within the quoted range. The
precision exception has no effect on execution
time. Unmasked overflow and underflow, and
masked denormalized exceptions, impose the
penalties shown in table S-18. Absolute worstcase execution time is therefore the high range
figure plus the largest penalty that may be
encountered.
Execution Time
The execution of an 8087 instruction involves
three principal activities, each of which may contribute to the total duration (execution time) of
the operation:
•
Instruction fetch
•
Instruction execution
•
Operand transfer
For instructions that transfer operands to or from
memory, the execution times in table S-19 show
that the time required for the CPU to calculate
the operand's effective address (EA) should be
added. Effective address calculation time varies
according to addressing mode; table 2-20 supplies
the figures.
The CPU and NDP simultaneously prefetch and
queue their common instruction stream from
memory. This activity is performed during spare
bus cycles and proceeds in parallel with the execution of instructions from the queue. Because of
their complexity, 8087 instructions typically take
much longer to execute than to fetch. This means
that in a typical sequence of 8087 instructions the
processors have a relatively large amount of time
available to maintain full instruction queues.
Instruction fetching is therefore fully overlapped
with execution and does not contribute to the
overall duration of a series of instructions. Fetch
time does become apparent when a CPU jump or
call instruction alters the normal sequential
execution. This empties the queues and delays
execution of the target instruction until it is
fetched from memory. The time required to fetch
the instruction depends on its length, the type of
CPU, and, if the CPU is an 8086, whether the
instruction is located at an even or odd address.
(Slow memories, which force the insertion of wait
states in bus cycles, and the bus activities of other
processors in the system, may also lengthen fetch
time.) Section 2.7 covers this topic in more detail.
Table S-18. Execution Penalties
Exception
Additional Clocks
Overflow (unmasked)
14
Underflow (unmasked)
16
Denormalized (masked)
33
Bus Transfers
Instructions that reference memory execute bus
cycles to transfer operands. Each transfer
requires one bus cycle. The number of transfers
depends on the length of the operand, the type of
CPU, and the alignment of the operand if the
CPU is an 8086. The figures in table S-19 include
the "dummy read" transfer(s) performed by the
CPU in its execution of the escape instruction that
corresponds to the 8087 instruction. The first
8086 figure is for even-addressed operands, and
the second is for odd-addressed operands.
Table S-19 quotes a typical execution time and a
range for each instruction. Dividing the figures in
the table by5 (assuming a 5 MHz clock) produces
execution time in microseconds. The typical case
is an estimate for operand values that normally
characterize most applications. The range
encompasses best- and worst-case operand values
that may be found in extreme circumstances.
Where applicable, the figures include all overhead
incurred by the CPU'.5 execution of the ESC
instruction, local bus arbitration (request! grant
time), and the average overhead imposed by a
preceding WAIT instruction (half of the 5-clock
cycle that it uses to examine the TEST pin).
A bus cycle (transfer) consumes four clocks if the
bus is immediately available and if the memory is
running at processor speed, without wait states.
Additional time is required if slow memories are
employed, because these insert wait states into the
bus cycle. In multiprocessor environments, the
bus may not be available immediately if a higher
priority processor is using it; this also can increase
effective transfer time.
The execution times assume that no exceptions
are detected. Invalid operation, denormalized
(unmasked), and zero divide exceptions usually
S-43
8087 NUMERIC DATA PROCESSOR
Note that the lengths quoted in table 8-19 do not
include the one byte CPU WAIT instruction that
the assembler automatically inserts in front of all
NDP instructions (except those coded with a "nowait" mnemonic).
Instruction Length
Instructions that do not reference memory are
two bytes long. Memory reference instructions
vary between two and four bytes. The third and
fourth bytes are used for 8- or 16-bit displacement
values; the assembler generates the short displacement whenever possible. No displacements are
required in memory references that use only CPU
register contents to calculate an operand's effective address.
Table 8-19. Instruction 8et Reference Data
FABS
FABS (no operands)
Absolute value
Exceptions: I
Transfers
Execution Clocks
Operands
(no operands)
FADD
Typical
Range
8086
14
10-17
0
8088
o.
FADD //source/destination,source.
Add real
I1ST,ST(i)/ST(i),ST
short-real
long-real
FADDP
...
Typical
Range
8086
8088
85
105+EA
110+EA
70-100
90-120+EA
95-125+EA
0
2/4
4/6
0
4
8
FADDP destination,source
Add real and pop
Execution Clocks
Operands
ST(i),ST
FBLD
packed-decimal
Mnemonics © Intel 1980
Range
8086
8088
90
75-105
0
0
Bytes
2
2-4
2-4
Coding Example
FADD ST,ST(4)
FADD AIR_TEMP [SI]
FADD [BX].MEAN
Bytes
2
Coding Example
FADDP ST(2),St
Exceptions: I
Transfers"
Typical
Range
8086
8088
300+EA
290-310+EA
5/7
10
8-44
Exceptions: I, D, 0, U, P
Transfers
Typical
Execution"Clocks
FABS
Exceptions: I,D, 0, U, P
FBLD source
Packed decimal (BCD) load
Operands
2
Coding Example
Transfers
Execution Clocks
Operands
Bytes
Byte~
2-4
Coding Example
FBLD YTD_SALES
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FBSTP
FBSTP destination
Packed decimal (BCD) store and pop
Execution Clocks
Operands
packed-decimal
FCHS
Range
8086
8088
530+EA
520-540+EA
6/8
12
(no operands)
FCLEX/FNCLEX
(no operands)
FCOM
Range
8086
8088
15
10-17
0
0
FCLEX (no operands)
Clear exceptions
'FCOMP
Range
8086
8088
5
2-8
0
0
2
FCHS
Bytes
2
Coding Example
FNCLEX
Exceptions: I, D
Transfers
Typical.
Range
8086
8088
45
65+EA·
70+EA
40-50
60-70+EA
65-75+EA
0
2/4
4/6
0
4
8
FCOMP Iisource
Compare real and pop
Execution Clocks
Operands
Coding Example
Bytes
Transfers
Typical
Execution Clocks
IIST(i)
short-real
long-real
FBSTP [BX).FORECAST
Exceptions: None
FCOM IIsource
Compare real
Operands
2-4
Transfers
Typical
Execution Clocks
Operands'
Coding Example
Bytes
Exceptions: I
Execution Clocks
IIST(i)
short-real
long-real
Transfers
Typical
FCHS (no operands)
Change sign
Operands
Exceptions: I
2
2-4
2-4
FCOM ST(1)
FCOM [BP).UPPEFL-LIMIT
FCOM WAVELENGTH
Exceptions: I, D
Transfers
Typical
Range
8086
8088
47
68+EA
72+EA
42-52
63-73+EA
67-77+EA
0
2/4
4/6
0
4
8
S-45
Coding Example
Bytes
Bytes
2
2-4
2-4
Coding Example
FCOMP ST(2)
FCOMP [BP+2).N_READINGS
FCOMP DENSITY
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FCOMPP
FCOMPP (no operands)
Compare real and pop twice
Execution Clocks
Operands
(no operands)
FDECSTP
(no operands)
FDISI/FNDISI
Range
8086
8088
50
45-55
0
0
FDECSTP (no operands)
Decrement stack pointer
(no operands)
FDIV
8086
8088
9
6-12
0
0
FDISI (no operands)
Disable interrupts
FDIVP
Range
8086
8088
5
2-8
0
0
Mnemonics © Intel 1980
2
Coding Example
FDECSTP
2
Coding Example
FDISI
Transfers
Range
8086
8088
198
220+EA
225+EA
193-203
215-225+EA
220-230+EA
0
2!4
4!6
0
4
8
Bytes
2
2-4
2-4
Coding Example
FDIV
FDIV DISTANCE
FDIV ARC [DIJ
Exceptions: I, D, Z, 0, U, P
Transfers
Typical
Range
8086
8088
202
197-207
0
0
S-46
Bytes
Exceptions: I, D, Z, 0, U, P
Typical
Execution Clocks
ST(i),ST
Bytes
Transfers
Typical
FDIVP destination,source
Divide real and pop
Operands
FCOMPP
Exceptions: None
Execution Clocks
!!ST(i),ST
short-real
long-real
2
Coding Example
Transfers
Range
FDIV !!source!destination,source
Divide real
Operands
Bytes
Exceptions: None
Typical
Execution Clocks
Operands
Transfers
Typical
Execution Clocks
Operands
Exceptions: I, D
Bytes
2
Coding Example
FDIVP ST(4),ST
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FDIVR
FDIVR Iisource/destination,source
Divide real reversed
Execut,ion Clocks
Operands
IIST,ST(i)/ST(i),ST
short-real
10flg-real
FDIVRP
ST(I),ST
FENI/FNENI
Transfers
Typical
Range
8086
8088
199
221+EA
226+EA
194-204
216-226+EA
221-23,1 +EA
0
2/4
4/6
0
6
8
Bytes
,2
2-4
2-4
FDIVRP destlnation,source
Divide real reversed and pop
Execution Clocks
Operands
Exceptions: I, D, Z, 0, U, P
Transfers
Typical
Range
8086
8088
203
198-208
0
0
Bytes
2
FENI (no operands)
FFREE
Typical
Range
5
2-8
' 0
8088
0
FFREE destination
,ST(i)
11
FIADD
8086
8088
9-16
0
0
FNENI
Bytes
2
Coding Example
FFREE ST(1)
Exceptions: I, D, 0, P
Execution Clocks
word-integer
short-integer
2
Transfers "
'Range
FI,II.DD source
Integer add
Operands"
Coding Example
Bytes
. Exceptions: None
Execution Clock,s
Typical.
FDIVRP ST(1 ),ST
Transfers
,8086
Free register
Operands
Coding Example
Exceptions: None
Execution Clocks
(no operands)
FDIVR ST(2),ST
FDIVR [BX].PULSLRATE
FDIVR RECOROER.FREQUENCY
Exceptions: I, D, Z, 0, U, P
Enable interrupts
Operands
Coding Example
Transfers
Typical
Range
8086
8088
120+EA
125+EA
102-137+EA
108-143+EA
112
2.
.4
8-47
2/4
Bytes
2-4
2-4
Coding Example,
FIADD DISTANCE_TRAVELLED
FIADD PULSE_COUNT [SI]
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FICOM
FICOM source
Integer compare
Execution Clocks
Operands
word-integer
short-integer
FICOMP
Exceptions: I, 0
"
Transfers
Typical
Range
8086
8088
80+EA
85+EA
72-8S+EA
78-91+EA
1/2
2
4
2/4
FICOMP source
Integer compare and pop
Bytes
2-4
2-4
Coding,Example
FICOM TOOL.N_PASSES
FICOM [BP+4].PARM_COUNT
Exceptions: I,D
"
Execution Clocks'
Operands
word-integer
short-integer
FIDIV
, Transfers
Typical
Range
8086
8088
82+EA
B7+EA
74-8B+EA
BO-93+EA
1/2
2/4
2
4
FIDIV source
Integer divide
word-integer
short-integer
FIDIVR
word-integer
short-integer
FILD
Range
80B6
808B'
230+EA
23S+EA
224-23B+EA
230-243+EA
1/2
2/4
2
4
FIDIVR source
Integer divide reversed
Mnemonics © Intel 1980
2-4
2-4
Coding Example
FIOIV SURVEY.OBSERVATIONS
FIOIV RELATIVE_ANGLE [01]
Transfers
Typical
Range
BOB6
80BB
230+EA
237+.EA
225-239+EA
231-245+EA
1/2
2/4
2
,4
Bytes
2-4
2"4
Coding Example ..
FIOIVR [BP].X_COORO
FIOIVR FREQUENCY
Exception: I
Execution Clocks
word-i nteger
short-integer
long-integer
Bytes
Exceptions: I, 0, Z, 0, U, P
FILD source
Integer load
Opera!1ds
FICOMP [BP].LlMIT [SI]
FICOMP N_SAMPLES
Transfers
Typical
Execution' Clocks
Operands
2-4
2-4
Coding Example
Exceptions: I,D, Z, 0, U, P
Execution Clocks
Operands
Bytes
Transfers
Typical'
Range
80B6
BOBB
50+EA
56+EA
S4+EA
4S-54+EA
52-60+EA
SO-S8+EA
1/2,
2/4
4/S
2
4
8
S-48
Bytes
2-4
2-4
2-4
Coding Example
FILO [BX].SEQUENCE
FILD STANDOFF [01]
FILO RESPONSE.COUNT
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FIMUL
FIMUL source
Integer multiply
Exceptions: I, D, 0, P
Execution Clocks
Operands
word-integer
short-integer
FINCSTP
Typical
Range
8086
8088
130+EA
136+EA
124-138+EA
130-144+EA
1/2
2/4
2
4
FINCSTP (no operands)
Increment stack pointer
Execution Clocks
Operands
(no operands)
FINIT IFNINIT
(no operands)
FIST
8086
8088
9
6-12
0
0
FINIT (no operands)
Initialize processor
FISTP
Range
8086
8088
5
2-8
0
0
2
Coding Example
FINCSTP
Bytes
2
Coding Example
FINIT
Exceptions: I, P
Transfers
Typical
Range
8086
8088
86+EA
88+EA
80-90+EA
82-92+EA
2/4
3/5
4
6
Execution Clocks
word-integer
short-integer
long-integer
Bytes
Transfers
FISTP destination
Integer store and pop
Operands
FIMUL BEARING
FIMUL POSITION.LAXIS
Exceptions: None
Typical
Execution Clocks
word-integer
short-integer
2-4
2-4
Transfers
Range
FIST destination
Integer store
Operands
Coding Example
Bytes
Exceptions: None
Typical
Execution Clocks
Operands
Transfers
Bytes
2-4
2-4
Coding Example
FIST OBS.COUNT [SI]
FIST [BP].FACTORED_PULSES
Exceptions: I, P
Transfers
Typical
Range
8086
8088
88+EA
90+EA
100+EA
82-92+EA
84-94+EA
94-105+EA
2/4
3/5
5/7
4
6
10
Bytes
2-4
2-4
2-4
Coding Example
FISTP [BX].ALPHA_COUNT [SI]
FISTP CORRECTED_TIME
FISTP PANEL.N_READINGS
-- --
S-49
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd;)
FISUB
FISUB source
Integer subtract
Exceptions: I, D, 0, P
Execution Clocks
Operands
word-integer
short-integer
FISUBR
Typical
Range
8086
8088
120+EA
125+EA
102-137+EA
108-143+EA
1/2
2/4
2
4
FISUBR source
Integer subtract reversed
Execution Clocks
Operands
word-integer
short-integer
FLO
Transfers··
FLOCW
Range
8086
8088
120+EA
125+EA
103-139+EA
109-144+EA
1/2
2/4
2
4
2-bytes
FLOENV
14-bytes
Mhemonics © Intel 1980
Coding.Example
2-4 . FISUBR FLOOR [BX) [SI)
2-4
FISUBR BALANCE
Transfers
Typical
Range
8086
8088
20
43+EA
46+EA
5HEA
17-22
38-5S+EA
40-S0+EA
53-S5+EA
0
2/4
4/6
5/7
0
4
8
10
FLDCW source
Load control word
Bytes
2
2-4
2-4
2-4
Coding Example
FlO
FLD
FLD
FLD
ST(O)
READING [SI).PRESSURE
[BP).TEMPERATURE
SAVEREADING
Exceptions: None
Transfers
Typical
Range
8086
8088
10+EA
7-14+EA
1/2
2
FLDENV source
Load environment
Bytes
2-4
Coding Example
FLDCW CONTROLWORD
t:xceptions: None
Execution Clocks
Operands
Bytes
Exceptions: I, D
Execution Clocks
Operands
FISUB BASE_FREQUENCY
FI5UB TRAIN_SIZE [01)
Transfers
Typical·
EXecution Clocks
5T(i)
short-real
long-real
temp-real
2-4
2-4
Coding Example
Exceptions: I, D, 0, P
FLD source
Load real
Operands
Bytes
Transfers
Typical
Range
8086
8088
40+EA
35-45+EA
7/9
14
S-50
Bytes
2-4
Coding Example
FLDENV [BP+S)
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FLOLG2
FLDLG2 (no operands)
Load log10 2
Exceptions: 1
Execution Clocks
Operands
(no operands)
FLOLN2
Transfers
Typical
Range
8086
8088
21
18-24
0
0
FLDLN2 (no operands)
Load loge 2
(no operands)
FLOL2E
(no operands)
FLOL2T
Range
8086
8088
20
17-23
0
0
FLDL2E (no operands)
Load 1092 e
(no operands)
FLOPI
Range
8086
8088
18
15-21
0
0
FLDL2T (no operands)
Load log21O
FLOLN2
Bytes
2
Coding Example
FLOL2E
Exceptions: 1
Transfers
Typical
Range
8086
8088
19
16-22
0
0
Bytes
2
Coding Example
FLOL2T
Exceptions: 1
Execution Clocks
(no operands)
2
Coding Example
Transfers
Typical
FLDPI (no operands)
Load n
Operands
Bytes
Exceptions: 1
Execution Clocks
Operands
FLOLG2
Transfers
Typical
Execution Clocks
Operands
2
Coding Example
Exceptions: 1
Execution Clocks
Operands
Bytes
Transfers
Typical
Range
8086
8088
19
16-22
0
0
S-51
Coding Example
Bytes
2
FLOPI
Mnemonics © Inlel1980
8087 NUMERIC DATA PROCESSOR
. Table S-19. Instruction Set Reference Data (Cont'd.)
FLDZ
FLDZ (no operands)
Load +0.0
Exceptions: I
Execution Clocks
Operands
(no operands)
FLD1
Transfers
Typical
Range
8086
8081!
14
11-17
0
0
FLD1 (no operands)
Load +1.0
(no operands)
FMUL
Typical
Range
8086
8088
18
15-21
0
0
Bytes
2
Codin!! Example
FLD1
Exceptions: I, D, 0, U, P
Transfers
Execution Clocks
IIST(i),ST/ST,ST(i)'
IIST(i),ST/ST,ST(i)
short-real
long-real'
long-real
FLDZ
Transfers
FMUL Iisource/destination,source
Multiply real
Operands,
2
Coding Example
Exceptions: I
Execution Clocks
Operands
Bytes
Typical
Range
8086
8088
97
138
118+EA
120+EA
161+EA
90-105
130-145
110-125+EA
112-126+EA
154-168+EA
0
0
0
0
4
8
8
2/4
4/6
4/6
Bytes
2
2
2-4
2-4
2-4
Coding Example
FMUL
FMUL
FMUL
FMUL
FMUL
ST,ST(3)
ST,ST(3)
SPEED_FACTOR
[BPj.HEIGHT
[BPj.HEIGHT
,
occurs when one or both operands is "short"-it has 40 trailing zeros in its fraction. (e.g., it was loaded from a short-real
memory operand).
FMULP
FMULP destination,source
Multiply real and pop
Execution Clocks
Operands
ST(i),ST'
ST(i),ST
Exceptions: I, D, 0, U, P
Transfers
Typical
Range
8086
8088
100
142
94-108
134-148
0
0
0
0
,
Bytes
2
2
Coding Example
FMULP ST(1),ST
FMULP ST(1),ST
occurs when one or both operands is "short"-it has 40 trailing zeros in its fraction (e.g., it was loaded from a short-real
memory operand).
Mnemonics © Intel 1980
S-52
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FNOP
FNOP (no operands)
No operation
Exceptions: None
Execution Clocks
Operands
(no operands)
FPATAN
Transfers
Typical
Range
8086
8088
13
10-16
0
0
FPATAN (no operands)
Partial arctangent
(no operands)
FPREM
(no operands)
FPTAN
Range
8086
8088
650
250-800
0
0
FPREM (no operands)
Partial remainder
(no operands)
FRNDINT
(no operands)
2
Coding Example
FPATAN
Transfers
Typical
Range
8086
8088
125
15-190
0
0
FPTAN (no operands)
Partial tangent
Bytes
2
Coding Example
FPREM
Exceptions: I, P (operands not checked)
Transfers
Typical
Range
8086
8088
450
30-540
0
0
FRNDINT (no operands)
Round to integer
Bytes
2
Coding Example
FPTAN
Exceptions: I, P
Execution Clocks
Operands
Bytes
Exceptions: I, D, U
Execution Clocks
Operands
FNOP
Transfers
Typical
Execution Clocks
Operands
2
Coding Example
Exceptions: U, P (operands not checked)
Execution Clocks
Operands
Bytes
Transfers
Typical
Range
8086
8088
45
16-50
0
0
S-53
Bytes
2
Coding Example
FRNDINT
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FRSTOR
FRSTOR source
Restore saved state
Exceptions: None
Execution Clocks
Operands
94-bytes
Typical
210+EA
FSAVE/FNSAVE
Transfers
Range
8086
205-215+EA 47/49
94-bytes
Typical
210+EA
FSCALE
(no operands)
FSQRT
(no operands)
FST
8086
205-215+EA 48/50'
Bytes
8088
2-4
94
FSCALE (no operands)
Scale
Mnemonics © Intel 1980
FSAVE [SP]
Transfers
Typical
Range
8086
8088
35
32-38
0
0
Bytes
2
FSQRT (no operands)
Square root
Coding Example
FSCALE
Exceptions: I, 0, P
Transfers
Typical
Range
8086
8088
183
180-186
0
0
Coding Example
Bytes
2
FSQRT
Exceptions: 1,0, U, P
Transfers
Execution Clocks
ST(i)
short-real
long-real
Coding Example
Exceptions: 1,0, U
FST destination
Store real
Operands
FRSTOR [SP]
Transfers
Range
Execution Clocks
·Operands
Coding Example
Exceptions: None
Execution Clocks
Operands·
2-4
96
FSAVE destination
Save state
Execution Clocks
Operands
Bytes
8088
Typical
Range
8086
8088
18
87+EA
100+EA
15-22
84-90+EA
96-104+EA
0
3/5
5/7
0
6
10
S-S4
Bytes
2
2-4
2-4
Coding Example
FST ST(3)
FST CORRELATION [01]
FST MEAN_READING
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FSTCW IFNSTCW
FSTCW destination
Store control word
Exceptions: None
Execution Clocks
Operands
2-bytes
FSTENV/FNSTENV
Range
8086
8088
15+EA
12-18+EA
2/4
4
FSTENV destination
Store environment
Execution Clocks
Operands
14-bytes
FSTP
Transfers
Typical
Range
8086
8088
45+EA
40-50+EA
8/10
16
20
89+EA
102+EA·
55+EA
FSTSW IFNSTSW
2-bytes
FSUB
8086
8088
17-24
86-92+EA
98-106+EA
52-58+EA
0
3/5
5/7
6/8
0
6
10
12
FSTSW destination
Store status word
Bytes
2
2-4
2-4
2-4
Coding Example
FSTP
FSTP
FSTP
FSTP
ST(2)
[BX].ADJUSTED_RPM
TOTAL_DOSAGE
REG_SAVE [SI]
Transfers
Typical
Range
8086
8088
15+EA
12-1B+EA
2/4
4
Execution Clocks
IIST,ST(i)/ST(i),ST
short-real
long-real
FSTENV [BP]
Exceptions: None
FSUB Iisource/destination,source
Subtract real
Operands
2-4
Coding Example
Transfers
Range
Execution Clocks
Operands
Bytes
Exceptions: 1,0, U, P
Execution Clocks
ST(i)
short-real
long-real
temp-real
FSTCW SAVE_CONTROL
Transfers
Typical
Typical
2-4
Coding Example
Exceptions: None
FSTP destination
Store real and pop
Operands
Bytes
2-4
Coding Example
FSTSW SAVE_STATUS
Exceptions: I,D,O,U,P
Transfers
Typical
Range
8086
8088
85
105+EA
110+EA
70-100
90-120+EA
0
2/4
95~125+EA
4/6
0
4
8
S-55
Bytes
Bytes
2
2-4
2-4
Coding Example
FSUB ST,ST(2)
FSUB BASE_VALUE
FSUB COORDINATE.X
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table 8-19; Instruction 8et Reference Data (Cont'd.)
FSUBP
FSUBP destination,source
Su btract real and pop
Execution Clocks
Operands
ST(i),ST
FSUBR
Exceptions: I,D,O,U,P
Transfers
Typical
Range
8086
8088
90
75-105
0
0
FSUBR //source/destination,source
Subtract real reversed
Execution Clocks
Operands
//ST,ST(i)/ST(i),ST
short-real
long-real
FSUBRP
ST(i),ST
FTST
Range
8086
8088
87
105+EA
110+EA
70-100
90-120+EA
95-125+EA
0
2/4
4/6
0
4
8
FSUBRP destination,source
Subtract real reversed and pop
FWAIT
Range
8086
8088
90
75-105
0
0
(no operands)
Coding Example
Bytes
2
2-4
2-4
FSUBR ST,ST(1)
FSUBR VECTOR[Sll
FSUBR [BX1.INDEX
8086
8088
42
38-48
0
0
FWAIT (no operands)
(CPU) Wait while 8087 is busy
FSUBRP ST(1),ST
Coding Example
Bytes
2
FTST
Exceptions: None (CPU instruction)
Transfers
Typical
Range
8086
8088
3+5n'
3+5n'
0
0
'n = numberof times CPU examines TEST line before 8087 lowers BUSY.
8-56
2
Coding Example
Transfers
Range
Mnemonics © Intel 1980
Bytes
Exceptions: I, D
Typical
Execution Clocks
Operands
Exceptions: I,D,O,U,P
Transfers
Typical
Execution Clocks
(no operands)
FSUBP ST(2),ST
Exceptions: I,D,O,U,P
FTST (no operands)
Test stack top against lO.O
Operands
2
Transfers
Typical
Executon Clocks
Operands
Coding Example
Bytes
Coding Example
Bytes
..
1
FWAIT
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
FXAM
FXAM (no operands)
Examine stack top
Execution Clocks
Operands
(no operands)
FXCH
Exceptions: None
Transfers
Typical
Range
8086
8088
17
12-23
0
0
FXCH Ildestination
Exchange registers
IIST(i)
FXTRACT
Range
8086
8088
12
10-15
0
0
FXTRACT (no operands)
Extract exponent and significand
(no operands)
FYL2X
Typical
50
Range
27-55
Execution Clocks
(no operands)
FYL2XP1
(no operands)
8086
8088
0
0
FXCH ST(2)
Bytes
2
Coding Example
FXTRACT
Exceptions: P (operands not checked)
Transfers
Range
8086
8088
950
900-1100
0
0
FYL2XP1 (no operands)
Y oI092(X+1)
Bytes
2
Coding Example
FYL2X
Exceptions: P (operands not checked)
Transfers
Typical
Range
8086
8088
850
700-1000
0
0
S-57
2
Coding Example
Transfers
Typical
Execution Clocks
Operands
Bytes
Exceptions: I
FYL2X (no operands)
yo Log 2 X
Operands
FXAM
Transfers
Typical
Execution Clocks
Operands
2
Coding Example
Exceptions: I
Execution Clocks
Operands
Bytes
Bytes
2
Coding Example
FYL2XP1
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Table S-19. Instruction Set Reference Data (Cont'd.)
F2XM1
F2XM1 (no operands)
2 x_1
Execution Clocks
Operands
(no operands)
Exceptions: U, P (operands not checked)
Transfers
Typical
Range
8086
8088
500
310-630
0
0
Bytes
2
Coding Example
F2XM1
Mnemonics © Intel, 1980
The utility of the REAL data type is extended by
the PLlM-86 compiler's practice of holding
intermediate results in the 8087's temporary real
format. This means that the full range and precision of the processor may be utilized for
intermediate results. Underflow, overflow, and
rounding errors are most likely to occur during
intermediate computations rather than during
calculation of an expression's final result.
Holding intermediate results in temporary real
format greatly reduces the likelihood of overflow
and underflow and eliminates roundoff as a
serious source of error until the final assignment
of the result is performed.
S.8 Programming Facilities
Writing programs for the 8087 is a natural extension of the process described in section 2.9, just as
the NDP itself is an extension to the CPU. This
section describes how PLlM-86 and ASM-86 programmers work with the 8087 in these languages.
It also covers the 8087 software emulators
provided for both translators.
The level of detail in this section is intended to
give programmers a basic understanding of the
software tools that can be used with the 8087, but
this information is not sufficient to document the
full capabilities of these facilities. The definitive
description of ASM-86 and the full 8087 emulator
is provided in MCS-86 Assembly Language
Reference Manual, Order No. 9800640, and
MCS-86 Assembler Operating Instructions for
ISIS-II Users, Order No. 9800641. PLlM-86 and
the partial emulator are documented in PL/M-86
Programming Manual, Order No. 9800466 and
ISIS-II PL/M-86 Compiler Operator's Manual,
Order No. 9800478. These publications may be
ordered from Intel's Literature Department.
The compiler generates 8087 code to evaluate
expressions. that contain REAL data types,
whether variables or constants or both. This
means that addition, subtraction, multiplication,
division, comparison, and assignment of REALs
will be performed by the NDP. INTEGER expressions, on the other hand,are evaluated on the
CPU.
Five built-in procedures (table S-20) give the
PLlM-86 programmer access to 8087 functions
manipulated by the processor control instructions. Prior to any arithmetic operations, a
typical PLlM-86 program will setup the NDP
after power up using the INIT$REAL$MATH
$UNIT procedure and then issue
SET$REAL$MODE to configure the NDP.
SET$REAL$MODE loads the 8087 control word,
and its 16-bit parameter has the· format shown in
figure S-7. The recommended value of this
parameter is 033EH (projective closure, round to
nearest, 64-bit precision, interrupts enabled, all
exceptions masked except invalid operation).
Other settings may be used at the programmer's
discretion.
Readers should be familiar with section 2.9 of the
8086 Family User's Manual in order to benefit
from the material in this section.
PL/M-86
High level language programmers can access a
useful subset of the 8087's (real or emulated)
capabilities. The PLlM-86 REAL data type
corresponds to the NDP's short real (32-bit) format. This data type provides a range of about
8.43*10-37 ". Ixl ". 3.38*10 38 , with about seven
significant decimal digits. This representation is
adequate for the data manipulated by many
microcomputer applications.
Mnemonics © Intel 1980
S-58
8087 NUMERIC DATA PROCESSOR
Table S-20. PLlM-86 Built-In Procedures
Procedure
8087 Instruction
Description
INIT$REAL$MATH$UNIT(1)
FINIT
Initialize processor.
SET$REAL$MODE
FLDCW
Set exception masks, rounding
precision, and infinity controls.
GET$REAL$ERROR(2)
FNSTSW & FNCLEX
Store, then clear, exception
flags.
SAVE$REAL$ST ATUS
FNSAVE
Save processor state.
RESTORE$REAL$STATUS
FRSTOR
Restore processor state.
(1)Also initializes interrupt pOinters for emulation.
(2)Returns low-order byte of status word.
If any exceptions are unmasked, an exception
handler must be provided in the form of an interrupt procedure that is designated to be invoked by
CPU interrupt pointer (vector) number 16. The
exception handler·· can use the GET$REAL
$ERROR procedure to obtain the low-order byte
of the 8087 status word and to then clear the
exception flags. The byte returned by
GET$REAL$ERROR contains the exception
flags; these can be examined to determine the
source of the exception.
NDP can request an interrupt and that interrupt is
blocked (this may result in the endless wait
condition described in section S.6.)
ASM-86
The ASM-86 assembly language provides a single
uniform set of facilities for all combinations of
the 8086/8088/8087 processors. Assembly
language programs can be written to be completely independent of the processor set on which
they are destined to execute. This means that a
program written originally for an 8088 alone will
execute on an 8086/8087 combination without
re-assembling. The programmer's view of the
hardware is a single machine with these resources:
The SAVE$REAL$ST ATUS and RESTORE
$REAL$ST A TUS procedures are provided for
multi-tasking environments where a running task
that uses the 8087 may be preempted by another
task that also uses the 8087. It is the responsibility
o f t h e pre e mp tin g t ask t 0 iss u e
SAVE$REAL$ST ATUS before it executes any
statements that affect the 8087; these include the
INIT$REAL$MATH$UNIT and SET$REAL
$MODE procedures as well as arithmetic expressions. SAVE$REAL$STATUS saves the 8087
state (registers, status, and control words, etc.) on
the CPU's stack. RESTORE$REAL$STATUS
reloads the state information; the preempting task
must invoke this procedure before terminating in
order to restore the 8087 to its state at the time the
running task was preempted. This enables the
preempted task to resume execution from the
point of its preemption.
•
•
•
8 general registers
•
4 segment registers
•
8 floating-point registers, organized as a
stack
160 instructions
12 data types
The combination of the assembly language and
the 8087 emulator decouple the source code from
the execution vehicle. For example, the assembler
automatically inserts CPU WAIT instructions in
front of those 8087 instructions that require them.
If the program actually runs with the emulator
rather than the 8087, the WAITs are automatically removed at link time (since there is no
NDP for which to wait).
Note that the PL/M-86 compiler prefixes every
8087 instruction with a CPU WAIT. Therefore,
programmers should not code PL/M-86
statements that generate 8087 instructions if the
S-59
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Defining Data
decimal integers, although the assembler will
accept and convert other representations of
integers. Real values may be written as ordinary
decimal real numbers (decimal point re·quired), as
decimal numbers in scientific notation,or as hexadecimal strings. Using hexadecimal strings is
primarily intended for defining special values
such as infinities, NANs, and nonnormalized
numbers. Most programmers will find that
ordinary decimal and scientific decimal provide
the simplest way to initialize 8087 constants.
Figure S-20 compares several ways of setting the
various 8087 data types to the same initial value.
The ASM-86 directives shown in table S-21
allocate storage for 8087 variables and constants.
As with other storage allocation directives, the
assembler associates a type with any variable
defined with these directives. The type value is
equal to the length of the storage unit in bytes (10
for DT, 8 for DQ, etc.). The assembler checks the
type of any variable coded in an instruction to be
certain that it is compatible with the instruction.
For example, the coding FIADD ALPHA will be
flagged as an error if ALPHA's type is not 20r 4,
because integer addition is only available for
word and short integer data types. The operand's
type also tells the assembler which machine
instruction to produce; although to the programmer there is only an FIADD instruction, a
different machine instruction is required for each
operand type.
Note that preceding 8087 variables and constants
with the ASM-86 EVEN directive ensures that the
operands will be word-aligned in memory. This
will produce the best performance in 8086-based
systems, and is good practice even for 8088 soft~
ware, in the event that the programs are trans~
ferred to an 8086. All 8087 data types occupy
integral numbers of words so that no storage is
"wasted" if blocks of variables are defined
together and preceded by asiI1gle EVEN
declarative.
On occasion it is desirable to use an instruction
with an operand thal has no declared type. For
example, if register BX points to a short integer
variable, a programmer may want to code
FIADD [BX]. This can be done by informing the
assembler of the operand's type in theinstruction,
coding FIADD DWORD· PTR· [BX]. The
corresponding. overrides for the other storage
allocations are WORD PTR, QWORD PTR, and
TBYTEPTR.
Records and Structures
The ASM-86 RECORD and STRUC(structure)
declaratives can be very useful in NDP programming. The record facility can be used to define the
bit fields of the control, status, and tag words.
Figure S-21· shows one definition of the status
word and how it might be used in a routine that
polls the 8087· until it has completed an instruc~
tion.
The assembler does not, however, check the types
of operands .used in processor control instructions. Coding FRSTOR [BP] implies that the pro"
grammer has set up register BP to point to the
stack location where the processor's 94-byte state
record has been previously saved.
Because structures allow different but related
data types to be grouped together, they often provide a natural way to represent "real world" data
organizations. The fact that the structure
template may be "moved" about in memory adds
to its flexibility. Figure S-22 shows a simple struc-
The initial values for 8087 constants may be
coded in several different ways. Binary integer
constants may be specified asbit strings, decimal
integers, octal integers, or hexadecimal strings.
Packed decimal values are normally written as
Table S-21. 8087 Storage P.llocation Directives
Directive
8087 Data Types
Interpretation
DW
Define Word
Word integer
DD
Define Doubleword
Short integer, short real
DO
Define Ouadword
Long integer, long real
DT
Define Tenbyte
Packed decimal, temporary real
S-60
8087 NUMERIC DATA PROCESSOR
THE FOLLOWING ALL ALLOCATE THE CONSTANT: -126
NOTE TWO'S COMPLEMENT STORAGE OF NEGATIVE BINARY INTEGERS.
; EVEN
FORCE WORD ALIGNMENT
WORD INTEGER
OW 111111111000010B
BIT STRING
SHORT INTEGER DO OFFFFFF82H
HEX STRING MUST START WITH DIGIT
LONG INTEGER
DQ -126
ORDINARY DECIMAL
SHORT REAL
DO -126.0
NOTE PRESENCE OF ' ,
LONG REAL
DO -1.26E2
"SCIENTIFIC"
PACKED_DECIMAL DT -126
; ORDINARY DECIMAL INTEGER
IN THE FOLLOWING, SIGN AND EXPONENT IS 'COOS',
SIGNIFICAND IS '7E00 ... 00', 'R' INFORMS ASSEMBLER THAT
THE STRING REPRESENTS A REAL DATA TYPE.
TEMP REAL
DT
OCOOS7EOOOOOOOOOOOOOOR
; HEX STRING
Figure S-20. Sample 8087 Constants
; RESERVE SPACE FOR STATUS WORD
STATUS_WORD
OW ?
; LAY OUT STATUS WORD FIELDS
STATUS RECORD
&
BUSY:
1,
&
COND COOE3:
1,
&
STACK TOP:
3,
&
COND COOE2:
1,
&
COND-CODE1:
1,
&
COND-CODEO:
1,
&
INTREQ:
1,
&
RESERVED:
1,
&
P FLAG:
1,
&
U-FLAG:
1,
&
O-FLAG:
1,
&
Z-FLAG:
1,
&
D-FLAG:
1,
&
I-FLAG:
1
; POLL-STATUS WORD UNTIL 8087 IS NOT BUSY
POLL:
FNSTSW STATUS WORD
TEST
STATUS=WORD, MASK BUSY
JNZ
POLL
data aggregates ranging from simple to complex
according to the needs of the application. The
addressing modes, and the ASM-86 notation used
to specify them in instructions, make the accessing of structures, arrays, arrays of structures, and
other organizations direct and straightforward.
Table S-22 gives several examples of 8087 instructions coded with operands that illustrate different
addressing modes.
8087 Emulators
Intel offers two software products that provide
the functional equivalent of· an 8087,
implemented in 8086/8088 software. The full
emulator (E8087) emulates all 8087 instructions.
The partial emulator (PE8087) is a smaller version
that implerrients only the instructions needed to
support PL/M-86 programs. The full emulator
adds about 16k bytes to a program, while the
partial e!llulator executes in about 8k. Any
emulated program will deliver the same results
(except for timing) if it is executed on 8087
hardware.
Figure S-21, Status Word RECORD Definition
SAMPLE
STRUC
N OBS
DO
;SHORT INTEGER
MEAN
DQ
;LONG REAL
MODE
OW
;WORD INTEGER
STD DEV
DQ
;LONG REAL
;ARRAY OF OBSERVATIONS
WORD INTEGER
TEST SCORES
OW
1000 DUP (1)
SAMPLE ENOS
The emulators may be viewed as consisting of
emulated hardware and emulated instructions.
The emulators establish in CPU memory the
equivalent of the 8087 register stack, control, and
status words and all other programmer-accessible
elements of the NDP architecture. The emulator
instructions utilize the. same algorithms as their
hardware counterparts. Emulator instructions are
actually implemented as CPU interrupt procedures. During relocation and linkage the 8087
machine instructions generated by the ASM-86
and PLlM-86 translators are changed to software
interrupt (lNT) instructions which invoke these
procedures as the CPU processes its instruction
stream.
Figure S-22. Structure Definition
ture that might be used to represent data consisting of a series of test score samples. A structure could also be used to define the organization
of the information stored and loaded by the
FSTENV and FLDENV instructions.
Addressing Modes
8087 memory data can be accessed with any of the
CPU's five memory addressing modes. This
means that 8087 data types can be incorporated in
S-61
Mnemonics © Intel 1978, 1980
8087 NUMERIC DATA PROCESSOR
Table S-22. Addressing Mode Examples
Coding
Interpretation
FIAOO
ALPHA
ALPHA is a simple scalar (mode is
direct).
FOIVR
ALPHA.BETA
BETA is a field in a structure that is
"overlaid" on ALPHA (mode is
direct).
FMUL
aWORO PTA [BX]
BX contains the address of a long real
variable (mode is register indirect).
FSUB
ALPHA [SI]
ALPHA is an array and SI contains the
offset of an array element from the
start of the array (mode is indexed).
FILO
[BP].BETA
BP contains the address of a
structure on the CPU stack and BETA
is a field in the structure (mode is
based).
FBLO
TBYTE PTR [BX] [01]
BX contains the address of a packed
decimal array and 01 contains the offset of an array element (mode is
based indexed).
Since the decision to produce real or emulated
8087 instructions is made at link time, a program
may be switched from one mode to the other
without retranslating the source code. When the
PLlM-86 compiler or ASM-86 assembler places
an 8087 machine instruction into an object
module, it also inserts a special external reference.
This reference is satisfied by linking the object
module to one of two Intel-supplied libraries: the
real library, or the emulator library. If the real
library is specified, LlNK-86 simply deletes the
external references, leaving the original 8087
machine instructions.
the FW AIT mnemonic should always be used
when the external processor that the CPU is to
wait for is an 8087.
In order to be compatible with E8087, ASM-86
programs should observe the following
conventions:
•
Their stack segment and class should be
named STACK.
Interrupt pointer (vector) 16 should be
•
designated for the user's exception handler
interrupt procedure.
•
The external procedure INIT87 should be
called in the program's initialization (powerup) sequence. If the emulator is being used,
this procedure will initialize CPU interrupt
pointers 20-31 to the addresses of emulator
procedures and will execute an (emulated)
FINIT instruction. If the program is not
being emulated, INIT87 simply executes the
FINIT instruction.
To run on an emulated 8087, the object program
is linked to the emulator library and to a file containing the code of either the full or the partial
emulator. LlNK-86 then adds the emulator code
to the program and changes the 8087 machine
instructions (and their preceding WAITs) to CPU
software interrupt instructions. Any FW AIT
instructions are also changed to CPU NOPs.
Note that an explicitly-coded CPU WAIT instruction will not be changed; if it is executed under
emulation, the CPU will wait forever. This is why
Mnemonics © Intel 1980
PL/M-86 automatically observes corresponding
conventions.
S-62
8087 NUMERIC DATA PROCESSOR
is assumed that an exception handler has been
written to field the invalid operation, if it occurs,
and that it is invoked by interrupt pointer 16.
Either version of the program will run on an
actual or an emulated 8087 without altering the
code shown.
Programming Example
Figures S-23 and S-24 show the PLlM-86 and
ASM-86 code for a simple 8087 program, called
ARRSUM. The program references an array
(X$ARRA Y), which contains 0-100 short real
values; the integer variable N$OF$X indicates the
number of array elements the program is to
consider. ARRSUM steps through X$ARRA Y
accumulating three sums:
•
SUM$X, the sum of the array values;
•
SUM$INDEXES, the sum of each array
value times its index, where the index of the
first element is 1, the second is 2, etc.;
•
SUM$SQUARES, the sum of each array
element squared.
The PLlM-86 version of ARRSUM (figure S-23)
is very straightforward and illustrates how easily
the 8087 can be used in this language. After
declaring variables the program calls built-in
procedures to initialize the processor (or its
emulator) and to load the control word. The program clears the sum variables and then steps
through X$ARRAY with a DO-loop. The loop
control takes into account PL/M-86's practice of
considering the index of the first element of an
array to be O. In the computation of
SUM$INDEXES, the built-in procedure FLOAT
converts 1+1 from integer to real because the
language does not support "mixed mode"
arithmetic. One of the strengths of the NDP, of
(A true program, of course, would go beyond
these steps to store and use the results of these
calculations.) The control word is set with the
recommended values: projective closure, round to
nearest, 64-bit precision, interrupts enabled, and
all exceptions masked except invalid operation. It
PLfM-86 COMPILER
ARRAYSUM
ISIS-II PLfl~-86 DE.BUG V2.1 COMPILATION OF I~ODULE ARRAYSUM
OBJECT MODULE PLACED IN :F4:ARRSUM.OBJ
COMPILER INVOKED BY: : FO: PLM86 : F4: ARRSUM. P86 XREF
1****" ** 11-******** ***** II- It .. * ** * .... *** •• ****
*
*
A R RAY SUM • MOD
... ** Mo*.******** .... ***************** ***** .. /
ARRAY$SUM:
2
3
4
DECLARE
DECLARE
DECLARE
DECLARE
5
DO;
(SUM$X,SUM$INDEXES,SUM$SQUARES) REAL;
X$ARRAY (100)
REAL;
(N$OF$X,I) INTEGER;
CONTROL$87 LITERALLY '033EH';
f* ASSUME X$ARRAY AND N$OF$X ARE INITIAJ,IZED *f
7
f* PREPARE THE 8087, OR ITS EMULATOR
CALL INIT$REAL$MATd$UNIT;
CALL SET$REAL$MODE(CONTROL$87);
8
f* CLEAR SUMS *f
SUM$X, SUM$INDEXES, SUM$SQUARES
6
*f
= 0.0;
f*
9
1
11
2
12
13
2
10
2
2
LOOP THROUGH X$ARRAY, ACCUMULATING SUMS *f
DO I = 0 TO N.tOF$X - 1;
SUM$X = SUM$X + X$ARRAY(I);
SUM$INDEXES = SUM$INDEXES +
(X$ARRAY(I) * FLOAT(I + 1));
SUM$SQUARES = SUMtSQUARES + (X$ARRAY(I) * X$ARRAY(I));
END;
f*
14
END
ETC •• •*f
ARRAY$SU~;
Figure S-23. Sample PL/M-86 Program
S-63
3087 NUMERIC DATA PROCESSOR
PL/M-86 COMPILER
ARRAYSUM
CROSS-REFERENCE LISTING
DEFN
4
2
2
2
3
ADDR
SIZE
0002H
151
019EH
2
019CH
2
0004H
OOOBH
OOOOH
OOOCR
4
4
4
400
!lAME, ATTRIBUTES, AND REFERENCES
ARRAYSUM •
CONTROLB?
FLOAT.
r.
INITREALMATRUNIT
NOFX •
SETREALMODE.
SUtUNDEXES
SUt~SQUARES
SUt1X •
XARRAY •
PROCEDURE STACK=0002H
LITERALLY
7
11
BUILTIN
10
INTEGER
9
6
BUILTIN
INTEGER
9
BUILTIN
7
REAL
B
11
REAL
8
12
10
REAL
B
REAL ARRAY( 100)
10
11
12
11
12
MODULE INFORMATION:
CODE AREA SIZE
0099H
CONSTANT AREA SIZE = 0004H
VARIABLE AR.EA SIZ8 = 01 AOH
MAXIMUM STACK SIZE = 0002H
33 LINES READ
o PROGRAM ERROR(S)
153D
4D
416D
2D
END Or' PL/M-86 COMPILATION
Figure S-23. Sample PLlM-86 Program (Cont'd.)
course, is that it does support arithmetic on mixed
data types, and assembly language programmers
can take advantage of this facility.
ment registers and stack pointer, the program
calls INIT87 and loads the control word. The
computation begins with the next three instructions, which clear three registers by loading
(pushing) zeros onto the stack. As shown in figure
S-25, these registers remain at the bottom of the
stack throughout the computation while temporary values are pushed on and popped off the
stack above them.
The ASM-86 version (figure S-24) defines the
external procedure INIT87, which makes the different initialization requirements of the processor
and its emulator transparent to the source code.
After defining the data, and setting up the seg-
8086/8087/8088 MACRO ASSEI1BLER
ARRSUM
ISIS-II 8086/8087/B088 MACRO ASSEMBLER V3.0 ASSEMBLY OF HODUI,E ARRSUM
OBJECT MODULE PLACED IN :Fl :ARRSUM.OBJ
:FO:AS1186 :Fl :ARRSUH.A86 XREF
ASSEMBLER INVOKED BY:
LOC
OBJ
LINE
;DEFINE INITIALIZATION ROUTINE
EXTRN
INITB7:FAR
4
;ALLOCATE SPACE FOR DATA
DATA
SEGMENT PUBLIC' DATA'
CONTROL 87
DW
033EH
N OF X DW
?
X=ARRAY
DD
100 DUP (?)
5
0000 3E03
0002 ????
0004
ii66
????????
SOURCE
1
2
3
6
7
8
j""""" "
0194 ????????
0198 ????????
019C ????????
9
10
11
12
SUM X
SUM-INDEXES
SUM-SQUARES
DATA
DD
DD
DD
ENDS
Figure S-24. Sample ASM-86 Program
Mnemonics © Intel 1978, 1980
S-64
8087 NUMERIC DATA PROCESSOR
8086/8087/8088 MACRO ASSEMBLgR
LOC
OBJ
LINE
13
14
15
16
0000 (200
ARRSUM
SOURCE
;ALLOCATE CPU STACK SPACE
STACK
SEGMENT STACK 'STACK'
200 DUP (?)
DW
1???
)
0190
0000
0000
0003
0005
0008
OOOA
B8---8ED8
B8---SEDO
BC9001
OOOD 9AOOOO---0012 9BD92EOOOO
R
R
R
E
R
0017 9BD9EE
001 A 9BD9EE
001D 9BD9EE
0020
0024
0026
0029
002B
002D
002D
0030
0035
0038
003B
003E
8BOE0200
E329
B80400
F7E9
8BFO
83EE04
9BD9840400
9BDCC3
9BD9CO
9BDCC8
9BDEC2
R
R
0041 9BDEOE0200
0046 9BDEC2
R
0049 FFOE0200
004D E2DE
R
004F
004F 9BD91 E9COI
0054 9BD91 E9801
0059 9BD91 E9401
R
R
R
0000
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
;LABEL
72
73
74
75
76
77
78
79
80
SEGI~ENT PUBLIC 'CODE'
CS:CODE,DS:DATA,SS:STACK,ES:NOTHING
MOV
MOV
110V
110V
MOV
AX,DATA
DS,AX
AX,STACK
SS,AX
SP,OFFSET STACK_TOP
; ASSUME X ARRAY & N OF X ARE INITIALIZED.
;
NOTE: PROGRAM ZEROS N OF X
; PREPARE THE 8087 OR ITS EMULATOR.
CALL
FLDCII
INIT87
CONTROL_87
;CLEAR 3 REGISTERS TO HOLD RUNNING SUMS.
FLDZ
FLDZ
FLDZ
;SETUP CX AS LOOP COUNTBR & SI AS INDEX TO X_ARRAY.
MOV
JCXZ
MOV
IMUL
MOV
48
49
50
·51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
WORD
CODE
ASSUME
START:
36
37
38
39
40
41
42
43
44
45
46
47
INITIAL TOP OF STACK
STACK TOP
LABEL
STACKENDS
CX,N_OF_X
POP RESULTS
; EXIT EARLY IF X_ARRAY EMPTY
AX,'I'YPE X_ARRAY
CX
SI,AX
;SI NOli CO~TAINS INDEX OF LAST ELEMENT + 1.
;LOOP THRU X_ARRAY ACCUMULATING SUMS.
SUM_NEXT:
BACKUP ONE ELEMENT
SUB
SI, TYPE X ARRAY
FLD
X ARRAY[ sY]
PUSH IT ONTO STACK
FADD
s'I'(3) ,ST
ADD INTO SUM OF X
FLD
ST
DUPLICATE X ON TOP
FMUL
SQUARE IT
FADDP
ADD INTO SUM OF SQUARES
~i(n,ST
AND DISCARD
GET X TIMES ITS INDEX
FIMUL
N OF X
FADDP
ADD INTO SUM OF (INDEX * X)
s'I'( 2T, ST
AND DISCARD
REDUCE INDEX FOR NEXT ITERATION
DEC
N OF X
SUM_NEXT
CO~TINUE
LOOP
;POP RU:lNING SUMS INTO ~IEI~ORY
POP_RESULTS:
FSTP
SUM SQUARES
SUM-INDEXES
FSTP
FSTP
SUM:::X
;ETC .••
CODE
ENDS
BND
START
Figure S-24. Sample ASM-86 Program (Cont'd.)
Sc65
Mnemonics © Intel 197B, 19BO
8087 NUMERIC DATA PROCESSOR
8086/8087/8088 MACRO ASSEMBLER
ARRSUM
XREF SYMBOL TABLE LISTING
NAME
TYPE
??SEG
CODE.
CONTROL 87.
DATA. INIT87.
N OF X• • •
pllp l!ESULTS
STAUK •
STACK TOP •
START-.
SUM INDEXES
SUJoINEXT ••
SUM-SQUARES
SUJoIX •••
X_Al!RAY •
SEGMENT
SEGMENT
V WORr;SEGMENT
L FAR
V WORD
L NEAR
SEGMENT
V WORD
L NEAR
V DWORD
L NEAR
V DWORD
V DiiORD
V DWORD
VALUE
OOOOH
00001!
0002H
004FH
0190H
OOOOH
0198H
002DH
019CH
0194H
0004H
ATTRIBUTES, XREFS
SIZE=OOOOH PARA PUBLIC
SIZE=005EH PARA PUBLIC 'CODE'
DATA 6# 37
SIZE=Ol AOH PARA PUBLIC 'DATI.'
EXTRN 2# 36
DATA 7# 47 63 66
CODE 48 70#
SIZE=0190H PARA STACK 'STACK',
STACK 19# 30
CODE 25# 80
DATA 10# 72
CODE 55# 67
DATA 11# 71
DATA 9# 73
DATA 8# 49 56 57
22# 23 78
3# 12 23 26
ASSEMBLY COMPLETE, NO ERRORS FOUND
Figure S-24. Sample ASM-86 Program (Cont'd.)
The program uses the epu LOOP instruction to
control its iteration through X_ARRAY; register
ex, which LOOP automatically decrements, is
loaded with N_OF_X, the number of array
elements to be summed. Register 81 is used to
select (index) the array elements. The program
steps through X_ARRAY from "back to
front", so 81 is initialized to point at the element
just beyond the first element to be processed. The
A8M-86 TYPE operator is used to determine the
number of bytes in each array element. This permits changing X_ARRAY to a long real array by
simply changing its definition (DD to DQ) and
re-assembling.
S.9 Special Topics
This section describes features of the 8087 which
will be of interest to groups of users who have
special requirements. Most users will not need to
understand this material in detail in order to
utilize the NDP successfully. Most readers, then,
can either browse this section, or skip it altogether
in favor of the programming examples in section
8.10.
The first four topics in this section cover the
8087's generation and handling of nonnormalized
real values, zeros, infinities and NANs. In the
great majority of applications, these special
values will either not appear at all, or in the case
of zeros, will function according to the normal
niles of arithmetic. Next the bit encodings of each
data type are summarized in table form, including
special values. This information may be of use to
programmers who are sorting these data types or
are decoding unformatted memory dumps or data
monitored from the bus. At the end of the section
is a table that lists all 8087 exception conditions
by class, and the processor's masked response to
each exception. This information will principally
be of use to writers of exception handlers and to
anyone else interested in ascertaining the exact
conditions under which the NDP signals a given
type of exception.
Figure 8-25 shows the effect of the instructions in
the program loop on the NDP register stack. The
figure assumes that the program is in its
first iteration, that N_OF_X is 20, and that
X_ARRAY(l9) (the 20th element) contains the
value 2.5. When the loop terminates, the three
sums are left as the top stack elements so that the
program ends by simply popping them into
memory variables.
Mnemonics © Intel 1978, 1980
8-66
8087 NUMERIC DATA PROCESSOR
FLO X ARRAY[5Il
FLDZ,FLDZ,FLDZ
-
ST(O)
0.0
SUM_SQUARES
ST(O)
ST(1)
0.0
SUM_INDEXES
ST(1)
ST(2)
0.0
S
SUM_SQUARES
ST(2)
----ST(3)
FADD 5T(3)
, 5T
X._ARRAY (19)
2.5
0.0
SUM_INDEXES
0.0
SUM_X
FLO 5 T
ST(O)
2.5
X_A RRAY (19)
ST (0)
2.5
X_ARRAY (19)
ST(1)
0.0
SUM _.SQUARES
ST (1)
2.5
X_ARRAY (19)
ST(2)
0.0
SUM _INDEXES
ST (2)
0.0
SUM_SQUARES
ST(3)
2.5
SUM
ST (3)
0.0
X
----
ST(4)
FMUL 5T 5T
ST(O)
-
ST(2)
FADDP
5H2)
, 5T
X_ARRAY(19)2
ST(O)
2.5
X_ARRAY(19)
2.5
X_ARRAY(19)
ST(1)
6.25
SUM_SQUARES
0.0
SUM_SQUARES
ST(2)
0.0
SUM_INDEXES
ST(3)
2.5
SUM_X
6.25
.......- - - - 1
ST(1)
2.5
.......- - - - - 1
ST(3)
0.0
SUM_INDEXES
.......- - - - - 1
ST(4)
2.5
~---~
SUM_X
.........
FIMUL N OF X
.....
ST(O)
50.0
X_A RRAY(19)'20
-ffiFAD
5H2)
D,5T
P
ST(O)
6.25
SUM_SQUARES
ST(1)
6.25
SUM _SQUARES
ST(1)
50.0
SUM_INDEXES
ST(2)
0.0
SUM _INDEXES
ST(2)
2.5
SUM_X
ST(3)
2.5
SUM
X
Figure S-25. Instructions and Register Stack
Nonnormal Real Numbers
Denormals
As discussed in section S.3, the 8087 generally
stores nonzero real numbers in normalized
floating point form; that is, the integer (leading)
bit of the significand is always a 1. This bit is
explicitly stored in the temporary real format, and
is implicit in the short and long real forms. Normalized storage allows the maximum number of
significant digits to be held in a significand of a
given width, because leading zeros are eliminated.
A denormal is the result of the NDP's masked
response to an underflow exception. Underflow
occurs when the exponent of a true result is too
small to be represented in the destination format.
For example, a true exponent of -130 will cause
underflow if the destination is short real, because
-126 is the smallest exponent this format can
accommodate. (No underflow would occur if the
destination were long or temporary real since
these can handle exponents down to -1023 and
-16,383, respectively.)
S-67
8087 NUMERIC DATA PROCESSOR
exception is masked. Gradual underflow is
accomplished by denormalizing the result until it
is just within the exponent range of the destination. Denormalizing means incrementing the true
result's exponent and inserting a corresponding
leading zero in the significand, shifting the rest of
the significand one place to the right. Table S-23
illustrates how a result might be denormalized to
fit a short real destination.
The NDP's unmasked response to underflow is to
stop and request an interrupt if the destination is
a memory operand. If the destination is a register,
the processor adds the constant 24,576 (decimal)
to the true result's exponent, returns the result,
and then requests an interrupt. The constant
forces the exponent into the range of the temporary real format, and an exception handler can
subtract out the constant to ascertain the true
exponent. Thus, execution always stops when
there is an unmasked underflow.
Denormalization produces a denormal or a zero.
Denormals are readily identified by their
exponents, which are always the minimum for
their formats; in biased form, this is always the
bit string: 00 ... 00. This same exponent value is
also assigned to the zeros, but a denormal has a
nonzero significand. A denormal in a register is
tagged special.
The intent of the masked response to underflow is
to allow computation to continue without program intervention, while introducing an error that
carries about the same risk of contaminating the
final result as roundoff error. Roundoff (precision) errors occur frequently in real number
calculations; sometimes they spoil the result of
computation, but often they do not. Recognizing
that roundoff errors are often non-fatal, computation usually proceeds and the programmer
inspects the final result to see if these errors have
had a significant effect. The 8087's masked
underflow response allows programmers to treat
underflows in a similar manner; the computation
continues and the programmer can examine the
final result to determine if an underflow has had
important consequences. (If the underflow has
had a significant effect, an invalid operation will
probably be signalled later in the computation.)
The denormalization process may cause the loss
of low-order significand bits as they are shifted
off the right. In a severe case, all the significand
bits of the true result are shifted out and replaced
by the leading zeros. In this case, the result of
denormalization is a true zero, and if the value is
in a register, it is tagged as such. However, thi$ is
a comparatively rare occurrence, and in any case
is no worse than "abrupt" underflow.
Denormals are rarely encountered in most
applications. Typical debugged algorithms
generate extremely small results during the
evaluation of intermediate subexpressions; the
final result is usually of an appropriate magnitude
for its short or long real destination. If
intermediate results are held in temporary real, as
is recommended, the great range of this format
Most computers underflow "abruptly"; they
simply return a zero result, which is likely to produce an unacceptable final result if computation
continues. The 8087, on the other hand,
underflows "gradually" when the underflow
Table S-23. Denormalization Process
Sign
Exponent(l)
True Result
0
-129
1/\01011100 ... 00
Denormalize
0
-128
0/\101011100 ... 00
Denormalize
0
-127
0/\0101011100 ... 00
Denormalize
0
-126
0/\00101011100 ... 00
Denormal Result(2)
0
-126
0/\00101011100 ... 00
Operation
Significand
Notes:
(1)expressed as unbiased,decimal number
(2)Before storing, significand is rounded to 24 bits, integer bit is dropped, and exponent is
biased by adding 126.
S-68
8087 NUMERIC DATA PROCESSOR
makes underflow very unlikely. Denormals are
likely to arise only when an application generates
a great many intermediates, so many that they
cannot be held on the register stack or in
temporary real memory variables. If storage
limitations force the use of short or long reals for
intermediates, and small values are produced,
underflow may occur, and if masked, may
generate denormals.
Unnormals
An unnormal is the "descendent" of a denormal
and therefore of a masked underflow response.
An unnormal may exist only in the temporary real
format; it may have any exponent that a normal
may have, but it is distinguished from a normal
by the integer bit of its significand, which is
always O. An unnormal in a register is tagged
valid.
Accessing a denormal may produce an exception
as shown in table S-24. (The denormalized exception signals that a denormal has been fetched.)
Denormals may have reduced significance due to
lost low-order bits, and an option of the proposed
IEEE standard precludes operations on nonnormalized operands. This option may be
implemented in the form of an exception handler
that responds to unmasked denormalized exceptions. Most users will mask this exception so that
computation may proceed; any loss of accuracy
will be analyzed by the user when the final result
is delivered.
Unnormals allow arithmetic to continue following an underflow while still retaining their identity
as numbers which may have reduced significance.
That is, unnormal operands generate unnormal
results, so long as their unnormality has a significant effect on the result. Unnormals are thus
prevented from "masquerading" as normals,
numbers which have full significance. On the
other hand, if an unnormal has an insignificant
effect on a calculation with a normal, the result
will be normal. For example, adding a small
unnormal to a large normal yields a normal
result. The converse situation yields an unnormal.
As table S-24 shows, the division and remainder
operations do not accept denormal divisors and
raise the invalid operation exception. Recall, also,
that the transcendental instructions require
normalized operands and do not check for exceptions. In all other cases, the NDP converts denormals to unnormals, and the unnormal arithmetic
rules then apply.
Table S-25 shows how the instruction set deals
with unnormal operands. Note that the unnormal
may be the original operand or a temporary
created by the 8087 from a denormal.
Table S-24. Exceptions Due to Denormal Operands
Operation
Exception
Masked Response
FLD (short/long real)
D
Load as equivalent un normal
arithmetic (except following)
D
Convert (in a work area) denormal to equivalent
un normal and proceed
Compare and test
D
Convert (in a work area) denormal to equivalent
unnormal and proceed
Division or FPREM with
denormal divisor
I
Return real indefinite
S-69
Mnemonics © Intel 19BO
8087 NUMERIC DATAPROCESSOR
Table S-25. Unnormal Operands and Results
Result
Operation
Addition I subtraction
Normalization of operand with larger absolute
value determines normalization of result.
Multiplication
If either operand
unnormal.
Division (unnormal dividend only)
Result is unnormal.
is
unnormal,
result is
FPREM (un normal dividend only)
Result is normalized.
Division IFPREM (unnormal
divisor)
Signal invalid operation.
Compare I FTST
Normalize as much as possible before making
comparison.
FRNDINT
Normalize
rounding.
FSQRT
Signal .invalid operation.
FST, FSTP (short/long real
destination)
If value is above destination's underflow
boundary, then signal invalid operation; else
signal underflow.
as
much
FSTP (temporary real destination)
Store as usual.
FIST, FISTP, FBSTP
Signal invalid operation.
as
possible
before
FLD
Load as usual.
FXCH
Exchange as usual.
Transcendental instructions
Undefined; operands must be normal and are
not checked.
operands and also shows how a true zero may be
created from nonzero operands. (Nonzero
operands are denoted "X" or "Y" in the table.)
Zeros and Pseudo-Zeros
As discussed in section S.3, the real and packed
decimal data types support signed zeros, while the
binary integers represent a single zero, signed
positive. The signed zeros behave, however, as
though they are a single unsigned quantity. If
necessary, the FXAM instruction may be used to
determine a zero's sign.
Only the temporary real format may contain a
special class of values called pseudo-zeros. A
pseudo-zero is an unnormal whose significand is
all zeros, but whose (biased) exponent is nonzero
(true zeros have a zero exponent). Neither is a
pseudo-zero's exponent all ones, since this
encoding is reserved for infinities and NANs. A
pseudo-zero result will be produced if two
unnormals, containing a total of more than 64
leading zero bits in their significands, are
multiplied together. This is a remote possibility in
most applications, but it can happen.
The zeros discussed above are called true zeros; if
one of them is loaded or generated in a register,
the register is tagged zero. Table S-26 lists the
results of instructions executed with zero
Mnemonics © Intel 19BO
S-70
8087 NUMERIC DATA PROCESSOR
Table S-26. Zero Operands and Results
FLD, FBLD (1)
+0
-0
FILD (2)
+0
FST,FSTP
+0
-0
+X (3)
-X (3)
FBSTP
+0
-0
FIST, FISTP
+0
-0
+X (4)
-X (4)
Addition
+0 plus +0
-0 plus-O
+0 plus -0, -0 plus +0
-X plus +X, +X plus-X
±O plus ±X, ±X plus ±O
+0
-0
+0
+0
-0
+0
-0
+0
-0
+0
+0
+0
+0
+0
-0
'0 (5)
'0 (5)
tx (6)
Subtraction
+0 minus-O
-0 minus+O
+0 minus +0, -0 minus -0
+X minus +X, -X minus-X
±O minus ±X, ±X minus ±O
+0
-0
'0 (5)
'0 (5)
Multiplication
+0· +0, -0·-0
+0· -0, -0· +0
+0· +X, +X· +0
+0. -X, -X. +0
-0· +X, +X·-O
-0· -X, -X·-O
+X·+Y,-X·-Y
+X· -Y, -X. +Y
+0
-0
+0
-0
-0
+0
+0, underflow (7)
-0, underflow (7)
Result
Operation/Operands
Result
Operation/Operands
Division
±O-;- ±O
±X-;-±O
+0 -;- +X, -O-;--X
+O-;--X,-O-;-+X
-X -;- -Y, +X -;- +Y
-X -;- +Y, +X -;--Y
Invalid operation
Zerodivide
+0
-0
+0, underflow (8)
-0, underflow (8)
FPREM
±O rem ±O
±X rem ±O
+0 rem +X, +0 rem -X
-0 rem +X, -0 rem-X
+X rem +Y, +X rem-Y
-X rem -Y, -X rem +Y
Invalid operation
Invalid operation
+0
-0
+0 (9)
":'0 (9)
FSQRT
-0
+0
-0
+0
Compare
±O:+X
±O:±O
±O:-X
AB
FTST
±O
FCHS
+0
-0
FABS
±O
F2XM1
+0
-0
FRNDINT
+0
-0
FXTRACT
+0
-0
tx (6)
Zero
-0
+0
+0
+0
-0
+0
-0
Both +0
Both -0
Notes:
Arithmetic and compare operations with real memory operands interpret the memory operand signs in
the same way.
(2) Arithmetic and compare operations with binary integers interpret the integer sign in the same manner.
(3) Severe underflows in storing to short or long real may generate zeros.
(1)
(4)
(5)
(6)
Small values (IXI < 1) stored into integers may round to zero.
Sign is determined by rounding mode:
• = + for nearest, up or chop
• = - for down
t = sign of X.
S-71
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR.
(7)
Very small values of X and Y may yield zeros, after rounding of true result. NDP signals underflow to
warn that zero has been yielded by nonzero operands.
(8)
Very small X and very large Y may yield zero, after rounding of true result. NDP signals underflow to
warn that zero has been yielded from nonzero operands.
When Y divides into X exactly.
(9)
Pseudo-zero operands behave like unnormals,
except in the following cases where they produce
the same results as true zeros:
•
•
•
'ADD ..• DD; if the infinity is in a register, it is
tagged special. The significand distinguishes
infinities from NANs, induding realindefinite.
compare and test instructions
FRNDINT (round to integer)
division, where the dividend is either a true
zero or a pseudo-zero (the divisor is a
pseudo-zero) .
A programmer may code an infinity, or-it may be
created by the NDP as its masked response to an
overflow or a zerodivide exception. Note that
when rounding is up or down,_ the masked
response may create the largest valid value
representable in the destination rather than infinity. See table S-33 for details. As operands,
infinities behave somewhat differently depending
on how the infinity control field in the control
word is set (see table S-27). When the projective
model of infinity is selected, the infinities behave
as a single unsigned representation; because of
this; infinity cannot be compared with any value
except infinity. In affine mode, the signs of the
infinities are observed, and comparisons are
possible.
In addition and subtraction of a pseudo-zero and
a true zero or another pseudo-zero, the pseudozero(s) behave like unnormals, except for the
determination of the result's sign. The sign is
determined as shown in table S-26 for two true
zero operands.
. Infinities
The real formats support signed representations·
.of infinities. These values are encoded with a
biased exponent of all ones and a significand of
Table S-27. Infinity Operands and Results
Operation
Addition
+00 plus +00
-00 plus-oo
+00 plus-oo
-00 plus +00
±oo plus ±X
±X plus ±oo
Subtraction
+00 minus -00
-00 minus +00
. +00 minus +00
-00 mirius -00
±oo minus±X
±X minus±oo
Multiplication
±OO. ±oo
±oo. ±Y
±O. ±oo, ±oo' ±O
Projective Result
Affine Result
Invalid operation
Invalid operation
Invalid operation
Invalid operation
'00
'00
+00
-00
Invalid operation
Invalid operation
'00
'00
Invalid operation
Invalid operation
Invalid operation
Invalid operation
'00
too
+00
-00
Invalid operation
Invalid operation
'00
too
E900
E900
Invalid operation
E900
E900
Invalid operation
S-72
8087 NUMERIC DATA PROCESSOR
Table S·27. Infinity Operands and Results (Cont'd.)
Operation
Projective Result
Affine Result
Division
±oo -;- ±oo
±oo';- ±X
±X.;- ±oo
Invalid operation
(1)00
(1)0
Invalid operation
(1)00
(1)0
FSQRT
-00
+00
Invalid operation
Invalid operaton
Invalid operation
+00
FPREM
±oo rem ±oo
±oorem ±X
±Y rem ±oo
±O rem ±oo
Invalid operation
Invalid operation
·Y
·0
Invalid operation·
Invalid operation
·Y
·0
FRNDINT
±oo
·00
·00
FSCALE
±oo scaled by ±oo
±oo scaled by ±X
±O scaled by ±oo
±Y scaled by ±oo
Invalid operation
·00
*0
Invalid operation
Invalid operation
*00
*0
Invalid operation
FXTRACT
±oo
Invalid operation
Invalid operation
A=B
A ? B (and) invalid
operation
A ? B (and) invalid
operation
-00 < +00
Compare
±oo: ±oo
±oo: ±Y
±oo: ±O
FTST
±oo
A? B (and) invalid
operation
-00 < Y <+00
-00 < 0 < +00
·00
Notes: X = zero or nonzero operand
Y = nonzero operand
• = sign of original operand
t = sign is complement of original operand's sign
(1)= sign is "exclusive or" original operand signs (+ if operands had same sign,
- if operands had different signs)
NANs
negative; its significand is encoded 1A100 ... 00.
All other NANs represent programmer-created
values.
A NAN (Not-A-Number) is a member of a class
of special values that exist in the real formats
only. A NAN has an exponent of ll...llB, may
have either sign, and may have any significand
except lAOO ... OOB, which is assigned to the
infinities. A NAN in a register is tagged special.
Whenever the NDP uses an operand that is a
NAN, it signals invalid operation. Its masked
response to this exception is to return the NAN as
the operation's result. If both operands of an
instruction are NANs, the result is the NAN with
the larger absolute value. In this way, a NAN that
enters a computation propagates through the
computation and will eventually be delivered as
The 8087 will generate the special NAN, real
indefinite, as its masked response to an invalid
operation exception. This NAN is signed
S-73
Mnemonics © Intel 19BO
8087 NUMERIC DATA PROCESSOR
the final result. Note, however, that the transcendental instructions do not check their
operands, and a NAN will produce an undefined
result.
creating a different NAN for each error. When
the program ended, the NAN results could be
used to access the diagnostic data saved at the
time the errors occurred. Many errors could thus
be diagnosed and corrected in one test run.
By unmasking the invalid operation exception,
the programmer· can use NANs to trap to the
exception handler. The generality of this
approach and the large number of NAN values
that are available, provide the sophisticated programmer with a tool that can be applied to a
variety of special situations.
Data Type Encodings
Tables 8-28 through 8-31 summarize how various
types of values are encoded in the seven NDP data
types. In all tables, the less significant bits are to
the right and are stored in the lowest memory
addresses. The sign bit is always the left-most bit
of the highest-addressed byte.
For example, a compiler could use NANs to
references to uninitialized (real) array elements.
The compiler could pre-initialize each array element with a NAN whose significand contained
the index (relative position) of the element. If an
application program attempted to access an element that it had not initialized, it would use the
NAN placed there by the compiler. If the invalid
operation exception were unmasked, an interrupt
would occur, and the exception handler would be
invoked. The exception handler could determine
which element had been accessed, since the
operand address field of the exception· pointers
would point to the NAN, and the NAN would
contain the index number of the array element.
Notice that in every format one encoding is interpreted as representing the special value indefinite.
The 8087 produces this encoding as its response to
a masked invalid operation exception. In the case
of the reals, indefinite can be loaded and stored
like any NAN and it always retains its special
identity; programmers are advised not to use this
encoding for any other purpose. Packed decimal
indefinite may be stored by the NDP in a FBSTP
instruction; attempting to use this encoding in
a FBLD instruction, however, will have an
undefined result. In the binary integers, the same
encoding may represent either indefinite or the
la,rgest negative number supported by the format
(-2 15 , -2 31 or -2 63 ). The 8087 will store this
encoding as its masked response to an invalid
operation, or when the value in a source register
represents, or rounds to, the largest negative
integer representable by the destination. In situations where its origin may be ambiguous, the
invalid operation exception flag can be examined
to see if the value was produced by an exception
response. When this encoding is loaded, or used
by an integer arithmetic or compare operation, it
is always interpreted as a negative number; thus
indefinite cannot be loaded from a packed
decimal or binary integer.
NANs could also be used to speed up debugging.
In its early testing phase a program often contains
multiple errors. An exception handler could be
written to save diagnostic information in memory
whenever it was invoked. After storing the
diagnsotic data, it could supply a NAN as the
result of the erroneous instruction, and that NAN
could point to its associated diagnostic area in
memory. The program would then continue,
8-74
8087 NUMERIC DATA PROCESSOR
Table 8-28. Binary Integer Encodings
Sign
Magnitude
(Largest)
0
11 ... 11
(Small~st)
0
0
1
00 ... 01
00 ... 00
11...11
Class
1/1
CD
>
;:
'iii
0
Q.
Zero
(Smallest)
1/1
-.
CD
.:=
1\1
CI
CD
z
(Largest/Indefinite· )
•
•
•
•
•
•
1
Exception Handling Details
Table 8-32 lists every exception condition that the
NDP detects and describes the processor's
response when the relevant exception mask is set.
The unmasked responses are described in table
S-6. Note that if an unmasked overflow or
underflow occurs in an FST or FSTP instruction,
no result if stored, and the stack and memory are
left as they existed before the instruction was
executed. This gives an exception handler the
opportunity to examine the offending operand on
the stack top.
•
•
•
•
•
•
When rounding is directed (the RC field of the
control word is set to "up" or "down"), the 8087
handles a masked overflow differently than it
does for the "nearest" or "chop" rounding
modes. Table S-33 shows the NDP's masked
response when the true result is too large to be
represented in it's destination real format. For a
normalized result, the essence of this response is
to deliver 00 or the largest valid number representable in the destination format, as dictated by the
rounding mode and the sign of the true result.
Thus, when RC=down, a positive overflow is
rounded down to the largest positive number.
Conversely, when RC=up, a negative overflow is
rounded up to the largest negative number. A
properly signed 00 is returned for a positive
overflow with RC=up, or a negative overflow
with RC=down. For an unnormalized result, the
action is similar except that the the unnormal
character of the result is preserved if the sign and
rounding mode do not indicate that 00 should be
delivered.
00 ... 00
Word: 1.--15 bits-.l
Short: ~31 bits ....1
Long: ~ 63 bits----t
* If this encoding is used as a source operand
(as in an integer load or integer arithmetic
instruction), the 8087 interprets it as the
largest negative number representable in the
format: _215 , _231 , or _263. The 8087 will deliver
this encoding to an integer destination in two
cases:
1)
if the result is the largest negative
number,
2)
as the response to a masked invalid
operation exception, in which case it
represents the special value integer
In all masked overflow re~ponses for directed
rounding, the overflow flag is not set, but the
precision exception is raised to signal that the
exact true result has not been returned.
indefinite.
S~7S
8087 NUMERIC .DATA PROCESSOR
Table S-29. Packed Decimal EncodiIigs
Class
UI
(Largest)
0
.
CD
•
~
·iii
•
o
11.
~ r_------~-----r------r_----------~------------------------------~
>
:0::
«I
I:Il
CD
Z
• The packed decimal indefinite encoding is stored by FBSTP in response to a masked invalid
operation exception. Attempting to load this value via FBLD produces an undefined result.
Note: "UUUU" means bit values are undefined and may contain any value.
Table S~30. Real and Long Real Encodings
. Class '
NANs
co
UI
CD
>
:0::
Normals
·iii
0
11.
III
iii
CD
a::
Denormals
Zero
Sign
Biased
Exponent
Significand*
Aff ... ff
0
11 ... 11
11 ... 11
0
0
0
11 ... 11
11 ... 11
11...10
00 ... 01
00 ... 00
11...11
0
0
00 ... 01
00 ... 00
00 ... 00
11 ... 11
0
0
00 ... 00
00 ... 00
00 ... 01
00 ... 00
•
•
•
•
•
•
•
•
•
S-76
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8037 NUMERIC DATA PROCESSOR
Table S-30. Real and Long Real Encodings (Cont'd.)
Class
Zero
Denormals
If)
'iii
(]l
a:
Normals
en
(]l
.::
n;
Cl
(]l
z
00
If)
~
z
I Indefinite
Sign
Biased
Exponent
Significand*
lIff...ff
1
00 ... 00
00 ... 00
1
00 ... 00
00 ... 01
0
0
0
0
0
0
0
0
0
1
00 ... 00
11...11
1
00 ... 01
00 ... 00
0
0
0
0
0
0
0
0
0
1
11...10
11...11
1
11...11
00 ... 00
1
11...11
00 ... 01
0
0
0
0
0
0
0
0
0
1
11...11
10 ... 00
0
0
0
0
0
0
0
0
0
1
11...11
11...11
Short: 1<- 8 bits -l>1l
Long: 1<-11 bits-l>I~52 bits--l>j
* Integer bit is implied and not stored.
Table S-31. Temporary Real Encodings
Class
Ul
(]l
~
NANs
'iii
0
Q.
00
Sign
Biased
Exponent
Significand
11Iff .. ff
0
11...11
111...11
0
0
0
0
0
0
0
0
0
0
11...11
100 ... 01
0
11...11
100 ... 00
S-77
8087 NUMERIC DATA PROCESSOR
Table S-31. Temporary Real Encodings (Cont'd.)
Class
Sign
Biased
Exponent
Significand
0
11 ... 10
Normals
•
•
•
•
•
•
•
•
•
•
•
•
•
•
111 ... 11
•
•
•
•
•
•
•
•
UI
CD
~
•
•
'iii
0
D..
•
•
0
00 ... 01
11Iff ..• ff
•
•
•
•
100 ... 00
Un normals
011 ... 11
•
•
•
000 ... 00
Denormals
0
00 ... 00
011 ... 11
0
0
1
00 ... 00
00 ... 00
00 ... 00
1
00 ... 00
000 ... 01
000 ... 00
000 ... 00
Denormals
000 ... 01
•
•
•
I--
Reals
I Zero
l Zero
•
•
•
UI
CD
>
:;:
III
Cl
CD
Z
00
•
•
•
•
•
•
•
•
•
1
1
00 ... 00
00 ... 01
011 ... 11
Unnormals
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
000 ... 00
1
1
8-78
•
•
•
•
•
•
•
11 ... 10
11 ... 11
0
•
•
•
011 ... 11
Normals
100 ... 00
•
•
•
111 ... 11
100 ... 00
8087 NUMERIC DATA PROCESSOR
Table 8-31. Temporary Real Encodings (Cont'd.)
Class
Sign
Biased
Exponent
Significand
IAff ... ff
1
11 ... 11
100 ... 00
•
•
•
•
•
1
11 ... 11
110 ... 00
•
•
•
•
•
•
•
•
•
•
UI
CII
~
m
I
NANs Indefinite
CI
CII
Z
1
•
•
•
11 ... 11
-15 bits
111 ... 11
~.
6<1 bits~
Table 8-32. Exception Conditions and Masked Responses
Masked Response
Condition
Invalid Operation
Source register is tagged empty (usually
due to stack underflow).
Return real indefinite.
Destination register is not tagged empty
(usually due to stack overflow).
Return real indefinite (overwrite
destination value).
One or both operands is a NAN.
Return NAN with larger absolute value
(ignore signs).
(Compare and test operations only):
one or both operands is a NAN.
Set condition codes "not comparable".
(Addition operations only): closure is
affine and operands are opposite-signed
infinities; or closure is projective and both
operands are 00 (signs immaterial).
Return real indefinite
(Subtraction operations only): closure is .
affine and operands are like-signed
infinities; or closure is projective and both'
operands are 00 (signs immaterial).
Return real indefinite.
(Multiplication operations only):
O' 00.
00'
Return real indefinite.
0; or
(Division operations only): 00 .;. 00; or 0.;. 0;
or 0 .;. pseudo-zero; or divisor is denormal
or unnormal.
Return real indefinite.
Return real indefinite, set condition code
"complete remainder" .
(FPREM instruction only): modulus
(divisor) is unnormal or denormal;
or dividend is 00.
=
Return real indefinite.
(FSQRT instruction only): operand is
nonzero and negative; or operand is
denormal or unnormal; or closure is affine
and operand is -00; or closure is projective
and operand is 00.
8-79
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
Exception Conditions and Masked Responses (Cont'd.)
Invalid Operation
(Compare operations only): closure is
projective and 00 is being compared with 0
or a normal, or 00.
Set condition code = "not comparable"
(FTST instruction only): closure is
projective and operand is 00.
Set condition code = "not comparable".
(FIST, FISTP instructions only): source
register is empty, or a NAN, or denormal,
or unnormal, or 00, or exceeds representable range of destination.
Store integer indefinite.
(FBSTP instruction only): source register
is empty, or a NAN, or denormal, or
unnormal, or 00, or exceeds 18 decimal
digits.
Store packed decimal indefinite.
(FST, FSTP instructions only): destination
is short or long real and source register is
an unnormal with exponent in range.
Store real indefinite.
(FXCH instruction only): one or both
registers is tagged empty.
Change empty register(s) to real indefinite
and then perform exchange:
Denormalized Operand
(FLO instruction only): source operand is
denormal.
No special action; load as usual.
(Arithmetic operations only): one or both
operands is denormal.
Convert (in a work area) the operand to the
equivalent unnormal and proceed.
(Compare and test operations only): one
or both operands is denormal or un normal
(other than pseudo-zero).
Convert (in a work area) any denormal to
the equivalent unnormal; normalize as
much as possible, and proceed with
operation.
Zerodivide
__ _
..
......
.......
Return 00 signed with "exclusive or" of
operand signs.
(Division operations only): divisor = O.
Overflow
(Arithmetic operations only): rounding is
nearest or chop, and exponent of true
result> 16,383.
Return properly signed ooand signal
precision exception.
(FST, FSTP instructions only): rounding is
nearest or chop, and exponent of true
result> +127 (short real destination)
or> +1023 (long real destination).
Return properly signed·oo and signal
precision exception.
Mnemonics © Intel 1980
S-80
8087 NUMERIC DATA PROCESSOR
Exception Conditions and Masked Responses (Cont'd.)
Underflow
(Arithmetic operations only): exponent of
true result <-16,382 (true).
Denormalize until exponent rises to
-16,382 (true), round significand to 64 bits.
If denormalized rounded significand = 0,
then return true 0; else, return denormal
(tag = special, biased exponent =0).
(FST, FSTP instructions only): destination
is short real and exponent of true result
<-126 (true).
Denormalize until exponent rises to -126
(true), round significand to 24 bits, store
true 0 if denormalized rounded significand
= 0; else, store denormal (biased exponent = 0).
(FST, FSTP instructions only): destination
is long real and exponent of true result
< -1022 (true).
Denormalize until exponent rises to -1022
(true), round significand to 53 bits, store
true 0 if rounded denormalized significand
= 0; else, store denormal (biased exponent = 0).
Precision
True rounding error occurs.
No special action.
Masked response to overflow exception
earlier in instruction.
No special action.
Table S-33. Masked Overflow Response for Directed Rounding
True Result
Normalization
Sign
Result Delivered
+00
Normal
+
Up
Normal
Down
Normal
+
-
Normal
-
Down
-00
Un normal
+
-
Up
+00
Unnormal
Unnormal
Unnormal
(1)
Rounding
Mode
+
-
Largest finite positive number(l)
Up
Largest finite negative number(1)
Down
Largest exponent, result's significand(2)
Up
Largest exponent, result's significand(2)
-00
Down
The largest valid representable reals are encoded:
exponent: 11 ... 108
significand: (1)lI11 ... 108
(2) The significand retains its identity as an unnormal; the true result is rounded as usual
(effectively chopped toward 0 in this case). The exponent is encoded 11 ... 108.
S-Sl
Mnemonics © Intel 1980
8087 NUMERIC DATA PROCESSOR
pond to the CPU's zero and carry flags (ZF and
CF), if the byte is written into the flags (see
figures 2-32 and S-6). The code fragment, then,
sets ZF and CF to the values of C3 and CO and
then uses the CPU conditional jumps to test the
flags. Table 2-15 shows how each conditional
jump instruction tests the CPU flags.
5.10 Programming Examples
Conditional Branching
As discussed in section S. 7, the comparison
instructions post their results to the condition
code bits of the 8087 status word. Although there
are many ways to implement conditional branching following a comparison, the basic approach is
as follows:
•
•
•
•
The FXAM instruction updates all four condition
code bits. Figure S-27 shows how a jump table
can be used to determine the characteristics of the
value .examined. The jump table (FXAM_TBL)
is initialiied to contain the 16-bit displacement of
16 labels, one for each possible condition code
setting. Note that four of the table entries contain
the same value, since there are four condition
code settings that correspond to "empty."
execute the comparison,
store the status word,
inspect the condition code bits,
jump on the result.
Figure S-26 isa code fragment that illustrates how
two memory-resident long real numbers might be
compared (similar code could be used with the
FTST instruction). The numbers are called A and
B, and the comparison is A toB. The comparison
itself simply requires loading A onto the top of
the 8087 register stack and then comparing it to B
and popping the stack in the same instruction.
The status word is written to memory and the
code waits for completion of the store before
attempting to use the result.
There are four possible orderings of A and B, and
bits C3 and CO of the condition code indicate
which ordering holds. These bits are positioned in
the upper byte of the status word so as to corres-
A
B
The program fragment performs the FXAM and
stores the status word. It then manipulates the
condition code bits to finally produce a number in
register BX that equals the condition code times
2. This involves zeroing the unused bits in the byte
that contains the code, shifting C3 to the right so
that it is adjacent to C2, and then shifting the
code to mUltiply it by. 2. The resulting value is
used as an index which selects one of the
displacements from FXAM_ TBL (the
multiplication of the condition code is required
because of the 2-byte length of each value in
FXAM_TBL). The unconditional JMP instruction effectively vectors through the jump table to
the labelled routine that contains code (not shown
in the example) to process each possible result of
• the FXAM instruction.
OQ?
OQ?
STAT 87 o.W
?
;LDAO A ONTO TOP OF 87 STACK
FLO
A
;COMPARE A:B, POP A
FCOMP B
FSTSW STAT 87 ;STORE RESULT
;WAIT FOR STORE
FWA IT
Figure S-26. Conditional Branching for Compares
Mnemonics © Intel 1978, 1980
S-82
8087 NUMERIC DATA PROCESSOR
,
iLOAD CPU REGISTER AH WITH BYTE OF
STATUS WORD CONTAINING CONDITION CODE
MOV
AH, BYTE PTR STAT_87+1
,
iLOAD CONDITION CODES INTO CPU FLAGS
SAHF
,
iUSE CONDITIONAL JUMPS TO DETERMINE
ORDERING OF A AND B
JB
A_LESS_OR_UNORDERED
iCF (CO) = 0
JNE
A_GREATER
A_EQUAL:
iCF (CO) = 0, ZF (C3) =
A_GREATER:
iCF (CO) = 0, ZF (C3) = 0
A_LESS_OR_UNORDERED:
iCF (CO) = 1, TEST ZF (C3)
JNE
A_LESS
A_B_UNORDERED:
iCF (CO) = 1, ZF (C3) = 1
A_LESS:
iCF
(CO) = 1, ZF (C3) = 0
Figure S-26. Conditional Branching for Compares (Cont'd.)
FXAM_TBL
&
&
&
&
STAT_87
DW POS_UNNORM, POS_NAN, NEG_UNNORM,
NEG_NAN, POS_NORM, POS_INFINITY,
NEG_NORM, NEG_INFINITY, POS_ZERO,
EMPTY, NEG_ZERO, EMPTY, POS_DENORM,
EMPTY, NEG_DENORM, EMPTY
DW ?
.Figure S-27. Conditional Branching for FXAM
.Mnemonics © Inle11978, 1980
8087 NUMERIC DATA PROCESSOR
;EXAMINE ST, STORE RESULT, WAIT FOR COMPLETION
FXAM
FSTSW
STAT_8?
FWA IT
;CLEAR UPPER HALF OF BX, LOAD CONDITION CODE
IN LOWER HALF
MOV
BH,O
MOV
BL, BYTE PTR STAT_8?+1
;COPY ORIGINAL IMAGE
MOV
AL,BL
;CLEAR ALL BITS EXCEPT C2-CO
AND
BL,00000111B
;CLEAR ALL BITS EXCEPT C3
AND
AL,01000000B
;SHIFT C3 TWO PLACES RIGHT
SHR
AL,1
SHR
AL,1
;SHIFT C2-CO" ONE PLACE LEFT (MULTIPLY BY 2)
SAL
BX,1
;DROP C3 BACK IN ADJACENT TO C2 (OOOXXXXO)
OR
BL,AL
;JUMP TO THE ROUTINE' 'ADDRESSED" BY CONDITION CODE
JMP
FXAM_TBL[BX]
iHERE ARE THE JUMP TARGETS, ONE TO HANDLE
EACH POSSIBLE RESULT OF FXAM
POS UNNORM:
Figure S-27. Conditional Branching for FXAM (Cont'd.)
Mnemonics © Inlel"1978, 1980
S-84
8087 NUMERIC DATA PROCESSOR
POS ZERO:
EMPTY:
NEG ZERO:
POS DENORM:
NEG DENORM:
Figure S-27. Conditional Branching for FXAM (Cont'd.)
must not load an unmasked exception flag into
the SOS7 or another interrupt will be requested
immediately (assuming SOS7 interrupts are also
loaded as unmasked).
Exception Handlers
There are many approaches to writing exception
handlers. One useful technique is to consider the
exception handler interrupt procedure as consisting of "prologue," "body" and "epilogue"
sections of code. (For compatibility with the SOS7
emulators, this procedure should be invoked by
interrupt pointer (vector) number 16.)
Figures S-2S through S-30 show the ASM-S6
coding of three skeleton exception handlers. They
show how prologues and epilogues can be written
for various situations, but only provide comments
indicating where the application-dependent
exception handling body should be placed.
At the beginning of the prologue, CPU interrupts
have been disabled by the CPU's normal interrupt
response mechanism. The prologue performs all
functions that must be protected from possible
interruption by higher-priority sources. Typically
this will involve saving CPU registers and
transferring diagnostic information from the SOS7
to memory. When the critical processing has been
completed, the prologue may enable CPU interrupts to allow higher-priority interrupt handlers
to preempt the exception handler.
Figures S-2S and S-29 are very similar; their only
substantial difference is their choice of instructions to save and restore the SOS7. The tradeoff
here is between the increased diagnostic information provided by FNSA VE and the faster
execution of FNSTENV. For applications that are
sensitive to interrupt latency, or do not need to
examine register contents, FNSTENV reduces the
duration of the "critical region," during which
the CPU will not recognize another interrupt
request (unless it is a non-maskable interrupt).
The exception handler body examines the
diagnostic information and makes a response that
is necessarily application-dependent. This
response may range from halting execution, to
displaying a message, to attempting to repair the
problem and proceed with normal execution.
After the exception handler body, the epilogues
prepare the CPU and the NDP to resume execution from the point of interruption (i.e., the
instruction following the one that generated the
unmasked exception). Notice that the exception
flags in the memory image that is loaded into the
SOS7 are cleared to zero prior to reloading (in
fact, in these examples, the entire status word
The epilogue essentially reverses the actions of the
prologue, restoring the CPU and the NDP so that
normal execution can be resumed. The epilogue
S-S5
Mnemonics © Intel 1978, 1980
8087 NUMERIC DATA PROCESSOR
image is cleared). The prologue also provides for
indicating to the interrupt controller hardware
(e.g., 8259A) that the interrupt has been processed. The actual processing done here is
application-dependent, but might typically
involve writing an "end of interrupt" command
to the interrupt controller.
the general approach shown in figure S-30 can be
employed. The basic technique is to save the full
8087 state and then to load a new control word in
the prologue. Note that considerable care should
be taken when designing an exception handler of
this type to prevent the handler from being
reentered endlessly.
The examples in figures S-28 and S-29 assume
that the exception handler itself will not cause an
unmasked exception. Where this is a possibility,
SAVE ALL
PROC
,
;SAVE CPU REGISTERS, ALLOCATE STACK SPACE
;FOR 8087 STATE IMAGE
PUSH
BP
MOV
BP,SP
SUB
SP,94
;SAVE FULL 8087. STATE, WAIT FOR COMPLETION,
;ENABLE CPU INTERRUPTS
FNSAVE
[BP-941
FWAIT
STI
,
;APPLICATION-DEPENDENT EXCEPTION HANDLING
;CODE GOES HERE
;CLEAR EXC£PTION FLAGS IN STATUS WORD
;RESTORE MODIFIED STATE
;IMAGE
MOV
BYTE PTR [BP-921, OH
FRSTOR
[BP-941
;WAIT FOR RESTORE TO FINISH BEFORE RELEASING MEMORY
FWAIT
;DE-ALLOCATE STACK SPACE, RESTORE CPU REGISTERS
MOV
SP,BP
,
POP
.BP
;CODE TO SEND' 'END OF INTERRUPT"
; 8259A GOES ,HERE
COMMAND TO
,
;RETURN TO INTERRUPTED CALCULATION
IRET
SAVE_ALL
ENDP
Figure S-28. Full State Exception Handler
Mnemonics
, © Intel 1978, 1980
S-86
8087 NUMERIC DATA PROCESSOR
SAVE_ENVIRONMENT PROC
,
iSAVE CPU REGISTERS, ALLOCATE STACK SPACE
iFOR 8087 ENVIRONMENT
PUSH
BP
MOV
BP,SP
SUB
SP,14
iSAVE ENVIRONMENT, WAIT FOR COMPLETION,
iENABLE CPU INTERRUPTS
FNSTENV [BP-141
FWAIT
,
.STI
i APP LI CAT I ON EX CEPT I ON-HAN 0 LI NG COD EGO ESHE RE
iCLEAR EXCEPTION FLAGS IN STATUS WORD
iRESTORE MODIFIED
iENVIRONMENT IMAGE
MOV
BYTE PTR [BP-121, OH
FLDENV
[BP-141
iWAIT FOR LOAD TO FINISH BEFORE ·RELEASING MEMORY
FWA IT
iDE-ALLOCATE STACK SPACE, RESTORE CPU REGISTERS
MOV
SP,BP
,
POP
iCODE
BP
TO SEND' 'END OF INTERRUPT"
COMMAND TO
i8259A GOES HERE
,
iRETURN TO INTERRUPTED CALCULATION
IRET
SAVE_ENVIRONMENT ENDP
Figure 8-29. Reduced Latency Exception Handler
Mnemonics © Intel 1978, 1980
8087 NUMERIC DATA PROCESSOR
LOCAL_CONTROL
REENTRANT
,
DW
?
;ASSUME INITIALIZED
PROC
;SAVE CPU REGISTERS, ALLOCATE STACK SPACE FOR
;8087 STATE IMAGE
PUSH
BP
MOV
BP,SP
SUB
SP,94
;SAVE STATE, LOAD NEW CONTROL WORD, WAIT
;FOR COMPLETION, ENABLE CPU INTERRUPTS
FNSAVE
[BP-94]
FLDCW
LOCAL_CONTROL
FWA IT
STI
;CODE TO SEND' 'END OF INTERRUPT" COMMAND TO
;8259A GOES HERE
;APPLICATION EXCEPTION HANDLING CODE GOES HERE.
;AN UNMASKED EXCEPTION GENERATED HERE WILL
;CA~SE THE EXCEPTION HANDLER TO BE REENTERED.
;IF LOCAL STORAGE IS NEEDED, IT MUST BE
;ALLOCATED ON THE CPU STACK.
;CLEAR EXCEPTION FLAGS IN STATUS WORD
iRESTORE MODIFIED STATE IMAGE
MOV
BYTE PTR [BP-92], OH
FRSTOR
[BP-94]
;WAIT FOR RESTORE TO FINISH BEFORE RELEASING MEMORY
FWA IT
;DE-ALLOCATE STACK SPACE, RESTORE CPU REGISTERS
MOV
SP,BP
POP
BP
;RETURN TO POINT OF INTERRUPTION
I RET
REENTRANT
ENDP
Figure S-30. Reentrant Exception Handler
Mnemonics © Inle11978, 1980
S-88
inter
iAPX 86/20
iAPX 88/20
NUMERIC DATA PROCESSOR
• High Performance 2-Chip Numeric
Data Processor
• Standard iAPX 86/10,88/10 Instruction
Set Plus Arithmetic, Trigonometric,
Exponential, and Logarithmic
Instructions For All Data Types
• Support 8 Data Types: 8-, 16-, 32-, 64Bit Integers, 32-, 64-, 80-Bit Floating
Point, and 18-Digit BCD Operands
• 8x80-Bit Individually Addressable
Register Stack plus 14 General
Purpose Registers
• All 24 iAPX 86/10,88/10 Addressing
Modes Available
• 7 Built-in Exception Handling
Functions
• Conforms To Proposed IEEE Floating
Point Standard
• MULTI BUS System Compatible
Interface
The Intel iAPX 86/20 and iAPX 88/20 are two-chip numeric data processors (NDP's). They provide the instructions and data types needed for high-performance numeric applications. The NDP provides 100 times the
performance of an iAPX 86/10, 88/10 CPU alone for numeric processing. The iAPX 86/20 cQnsists of an iAPX
86/10 (16-bit 8086 CPU) and a numeric processor extension (NPX), the 8087. The iAPX 88/20 consists of the
NPX in conjunction with the iAPX 88/10 (8-bit 8088 CPU). The NDP conforms to the proposed IEEE Floating
Point Standard.
Both components of the iAPX 86/20 and iAPX 88/20 are implemented in N-channel, depletion load, silicon gate
technology (HMOS), housed in two 40-pin packages. The iAPX .86/20, 88/20 adds 68 numeric processing
instructions to the iAPX 86/10, 88/10 instruction set and eight 80-bit registers to the register set.
MAX
MODE
B086
GND
r::--------,
8088
"
8088
REQUESTI QUEUE
GRANT
STATUS
I
I
I
I
I
REQUEST/ QUEUE
GRANT
STATUS
~
NPX
L
_ _ _ _ _ _ --1'86120,88120
(A14) AD14
(A13) AD13
(A12)AD12
(A11) AD11
(A10) AD10
(A9)AD9
(AS)ADB
GND
Vee
AD15
(A14) AD14
A16/S3
A17/S4
(A13)AD13
3
(A12) AD12
4
A1BiS5
(A11)AD11
5
A19iS6
(A10)AD10
BHEiS7
RQIGT1
AD7
AD6
INT
ADS
AD4
Ne
Ne
AD3
AD2
52
AD1
ADO
{~~E}
RQ,mo
(AB) AD9
(AS) ADS
AD7
AD6
A16/S3
A17/S4
,
7
,
9
"
34
" BHE/S7 (HIGH)
MN/MX
Rii
RQ/GTO
RQIGTi
so
LoCK
52
51
So
51
QSO
QSO
Ne
QS1
Ne
BUSY
QS1
TEST
READY
RESET
READY
RESET
eLK
GND
Figure 2. iAPX 86l20, 88/20 Pin Configuration
Figure 1. iAPX 86/20, 88/20 Block Diagram
Intel Corporation Assumes No Responsibilly for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
@INTELCORPORATION, 1981.
S-89
A:~.~~8~~~
iAPX 86/20, 88/20
Table 1. 8087 Pin Description
lYpe
Name and Function
AD15-ADO
I/O
Address Data: These Ii nes constitute the time mu Iti plexed memory add ress (T1) and data (T2.
T3. TW. T4) bus. AO is analogous to BHE for the lower byte of the data bus. pins D7-DO. It is
LOW during T1' when a byte is to be transf.erred on the lower portion of the bus in memory
operations. Eight·bit oriented devices tied to the lower half of the bus would normally use AD
to condition chip select functions. These lines are active HIGH~ They are input/output lines for
8087 driven bus cycles and are inputs which the 8087 monitors when the 8086/8088 is in
control of the bus. A15·A8:do not require an address latch in an iAPX 88/20. The 8087 will
supply an address for the T1·T4 period:
A19/56.
A18/55.
A17/54.
A16/53
I/O
Address Memory: During T1 these are the four most significant address lines
for memory operations. During memory operations. status information is available on
these lines during T2. T3. Tw. and T4. For 8087 controlled bus cycles. 56. 54. and 53
are reserved and currently one (HIGH). while 55 is always LOW. These lines are inputs which
the 8087 monitors when the 8086/8088 is in control of the bus.
BHE/57
I/O
Bus High Enable: DuringT1 the bus high enable signal (BHE) should be used to enable data
onto the most significant half of the data bus. ~ D15-D8. Eight·bit oriented devices tied to
the upper half of the bus would normally use BHE to condition chip select functions. BHE is
LOW during T1 for read and write cycles when a byte isto be transferred on the high portion of
the bus. The 57 status information is available during T2. T3. Tw. and T4. The signal is active
LOW. 57 is an input which the 8087 monitors during 8086/8088 controlled bus cycles.
Symbol
52. 51.
SO
I/O' Status: For 8087 driven bus cycles. these status lines are encoded as follows:
S1
SO
X
X
Unused
-1 (HIGH)
Unused
0
0
1
Read Memory
0
1
Write Memory
1
1
0
1
1
Passive
1
5tatus is driven active during T4. remains valid during T1 and T2. and is returned to the
passive state (1.1.1) during T3 orduring Tw when READY is HIGH. This status is used by the
8288 Bus Controller to generate all memory access control signals. Any change in 52. 51. or
50 during T4 is used to indicate the beginning of a bus cycle. and the return to the passive
state in T3 orTw is used to indicatetheend of a bus cycle. These signals are monitored by the
8087 when the 8086/8088 is in control of the bus.
S2
o (LOW)
RQ/GTO
I/O
Request/Grant:This request/grant pin is used by the NPX to gain control of the local bus from
the CPU for operand transfers or on behalf of another bus master. It must be. connected to one
of the two processor request/grant pins. The request grant sequence on 'this pin is as follows:
1. A pulse one clock wide is passed to the CPU to indicate a local bus request by either the,
'
, 8087 or the master connected to the 8087 RQ/GT1 pin.
2. The 8087 waits for the grant pulse and when it is received will either initiate bus transfer
activity in the clock cycle following the grant or pass the grant out on the RQ/GT1 pin in this
clock if the initial request was for another bus master.
3. The 8087 will generate a release pulse to the CPU one clock cycle after the completion of
the last 8087 bus cycle or on rec:eipt of the release pulse from the bus master on RQ/GT1.
AFN-01S20C
iAPX 86/20, 88/20
Table 1. 8087 Pin Description (Continued)
Symbol
'TYpe
Name and Function
RQ/GT1
110
RequestlGrant:This request/grant pin is used by another local bus master to force the 8087 to
request the local bus. If the 8087 is not in control of the bus when the request is made the
request/grant sequence is passed through the 8087 on the RQ/GTO pin one cycle later.
Subsequent grant and release pulses are also passed through the 8087 with a two and one
.clock delay, respectively, for resynchronization. RQ/GT1 has has an internal pullup resistor,
·andso may be left unconnected. If the 8087 has control of the bus the request/grant sequence
is as follows:
1. A pulse 1 ClK wide from another local bus master indicates a local bus request to the 8087
(pulse 1).
-- 2. During the 8087's next T4 or T1 a pulse 1 ClK wide from the 8087 to the requestin_g master
(pulse-2) indicates that the 8087 has allowed the local bus to-float and that it will entedhe
"RQ/GT acknowledge" state at the next ClK. The 8087's control unit is disconnected
logically from the local bus during "RQ/GTacknowledge."
3. A pulse 1 ClK wide from the requesting master indicates to the 8087 (pulse 3) that the
"RQ/GT" request is about tq end and that the 8087 can reclaim the local bus at the next
ClK,
Each master·master exchange of the local bus is a sequence of 3 pulses. There must be one
dead ClK cycle after each bus exchange. Pulses are active lOW.
I
OSl, OSO: Q-S1 and QSO provide the 8087 with status to allow tracking of the CPU
instruction queue.
----------OSl
OSO
o (lOW)
0 No Operation
0
1 First Byte of Op Code from Queue
0 Empty the Queue
1 (HIGH)
1
1 Subsequent Byte from Queue
QS1,
QSO
INT
0
Interrupt: This line is used to indicate that an unmasked exception has occurred during
numeric instruction execution when 8087 interrupts are enabled. This Signal is typically
routed to an 8259A. INT is active HIGH.
BUSY
0
Busy: This signal indicates that the 8087 NEU is executing a numeric instruction. It is connected to the CPU's TEST pin to provide synchronization. In the case of an unmasked
exception BUSY remains active until the exception is cleared. BUSY is active HIGH.
READY
I
Ready: READY is the acknowledgment from the addressed memory device that it will
complete the data transfer. The ROY Signal from memory is synchronized by the 8284A Clock
Generator to form READY. This Signal is active HIGH.
RESET
I
Reset: RESET causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles. RESET is internally synchronized.
ClK
I
Clock: The clock provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing.
Vcc
Power: VCC is the +5V power supply pin.
GND
Ground: GND are the ground pins.
NOTE:
For the pin descriptions of the 8086 and 8088 CPU's reference those respective data sheets (iAPX 86/10, iAPX 88/10).
S-91
AFN-0182OC
inter
iAPX 86/20, 88/20
APPLICATION AREAS
FUNCTIONAL DESCRIPTION
.The iAPX 86/20 and iAPX 88/20 provide functions
meant specifically for high performance numeric
processing requir~ments. Trigonometric, logarith~
mic, and exponential functions are built into the
. processor hardware. These functions are essential
in scientific, engineering, navigational, or military
applications.
The iAPX 86/20, 88/20 Numeric DataProcessor's architecture is designed for high performance
numeric computing in· conjunction with general
purpose proce~sing .
The·8087 is a numeric processor extension that
provides arithmetic and logical instruction support
for a variety of numeric data types in iAPX 86/20,
88/20 systems. It also executes numerous built-in
transcendental functions (e.g., tangent and log
functions). The 8087 executes instructions as a
coprocessor to a maximum mode 8086 or 8088. It
effectively extends the· register and instruction set of
an iAPX 86/10 or 88/10 b·ased system and adds
.several new data types as well. Figure 3 presents the
registers of the iAPX 86/20. Table 2 shows the range
of. data types supported by the NDP. The 8087 is
treated as an extension to the iAPX 86/10 or 88/10,
providing register; data types, control, and instruction capabilities at the hardware level. At the programmers level the iAPX 86/20, 88/20 is viewed as a
single unified processor.
The NDP also has capabilities meant for business or
commercial computing. An iAPX 86/20, 88/20 can
process Binary Coded Decimal (BCD) numbers up
to 18 digits without roundofferroi"s. It can also perform arithmetic on integers as large as ·64 bits
(±1018).
PROGRAMMING LANGUAGE SUPPORT
Programs for the iAPX 86/20 and iAPX 88/20 can be
written in A8M-86, the iAPX 86,88 assembly language, PUM-86, FORTRAN-86, and PA8CAL~86, Intel's high-level languages for iAPX 86, 88 systems.
Details
iAPX 86/20, 88/20 System Configuration
The remainder of the data sheet will concentrate on
the numeric processor extension (refered to as NPX
or 8087); For iAPX 86/10 or iAPX 88/10 CPU details
refer to those respective data sheets.
As a coprocessor to an 8086 or 8088, the 8087 is
wired in parallel with the CPU as shown in Figure4.
The CPU's status (80-82) and queue status lines
(080-081) enable the 8087 to monitor and de.code
8087.
DATA FIELD
IAPX 86110, 68110
AX
1~6 II
FILE:···
ax .
0
R1
R2
S:N
78 EXPONENT 84 83
TAG FIELD
SIGNIFICAND
0
!-=::::.:..I--'==::...-t-,----==:.::::::.::...---I
I--t----t-,---------I
I
R3
ox
.:
R4
SI
01
I
I
I
R5
R6
I--t----t-,---------I
RI
R7
1.-_'--_ _ _.1.--_ _ _ _ _ _ _.....
CX
SP
ap
.
.
.
. ..
0
..
t===t=======t================l
L __ ,
"'--""'I""P--'"
FLAGS
~1
15
I
I
IL.. _ _ _ _ -.,
I
I
~~ 1-1------1 I
CONTROL REGISTER
STATUS REGISTER
iNSTRUCTION POINTER
DATA POINTER
I
1
Figure 3. iAPX 86/20 Architecture
S-92
..
iAPX 86/20, 88/20
Table 2. iAPX 86/20, 88/20 Data Types
Data
Formats
Range
Most Significant Byte
Precision
7
017
10J Two's Complement
Byte Integer
102
8 Bits
17
Word Integer
104
16 Bits
115
Short Integer
10 9
32 Bits
131
Long Integer
10 18
64 Bits
163
Packed BCD
1018
18 Digits
Short Real
10±38
24 Bits
SI E7
Long Real
10±308
53 Bits
S I E10
10±4932
64 Bits
S E14
Temporary Real
017
017
017
017
017
017
01
101 Two's Complement
>1
Two's
10 Complement
10 1 Dol
SI- 0 17 0 16 1
F231 FO Implicit
EoIF1
E~1
I
F521 FO Implicit
EolFo
F63J
Real: (-1 )8(2E-BIA8)(Fo'F1' .. )
Packed BCD: (-1 )8(017 ... 00)
-
017
10J Two's Complement
Integer: I
r -
017
Bias=127 for Short Real
1023 for Long Real
16383 for Temp Real
-a
INT t - - - - - . I N T R
82S9A
PIC
IAPX86
BUS
INTERFACE
COMPONENTS
MUlTIMASTER
SYSTEM
BUS
8284A
CLOCK
GENERATOR
ClK
1-t-------1......- - . C l K
'----+---IINT
~OJ~
I
Ra~GT1
:
I
r
I
'- -'ClK
'iG'i-"
I
I
I:
8089
lOP
~-~
Figure 4. NDP System Configuration
S-93
AFN-G1820C
iAPX 86/20, 88/20
instructions in synchrohization with. the CPU and
without any CPU overhead. Once started the 8087
can process in parallel with and independent of the
host CPU. For resynchronization, the NPX's BUSY
signal informs the CPU that the NPX isexecuting an
instruction and the CPU WAIT instruction tests this
signal to insure that the NPX is ready to execute
subsequent instructions. The NPX can interrupt the
CPU when it detects an error or exception. The
8087's interrupt request .line is typically routed to
the CPU through an 8259A Programmable Interrupt Controller. (See Figure 2 for 8087 pinout
information.)
cycle being run:
The 8087 uses one of the request/grant lines of the
iAPX 86, 88 architectu re (typically RQ/GTi) to obtain
control of the local bus for data transfers. The other
request/grant line is available for general system use
(for instance by an I/O processor in LOCAL mode). A
bus master can also be connected to the 8087's
RQ/GT1 line. In this configuration the 8087 will pass
the request/grant handshake signals between the
CPU and the attached master when the 8087 is not in
control of the bus and will relinquish the bus to the
master directly when the 80~7 is in control. In this
way two additional masters can be configured in an
iAPX 86/20, 88/20 system; one will share the 8086
bus with the 8087 on a first come first served basis,
and the second will be guaranteed to be higher in
priority than the 8087.
The NDP includes the standard iAPX86/10, 88/10
instruction set for general data manipulation and
program control. It also includes 68 numeric
instructions for extended precision integer, floating
point,trigonometric, logarithmic, and exponential
functions. Sample execution times for several NDP
functions are shown in Figure 4. Overall iAPX86/20
system performance is 100 times that of an iAPX
86/10 class processor for numeric instructions.
S2
o
1
1
1
1
S1
so
X
X
o
o
1
1
o
1
o
1
Unused
Unused
Memory Data Read
Memory Data Write
Passive (no bus
cycle)
.
Programming Interface
Any instruction executed by the NDP is the
combined result of the CPU and NPX activity. The
CPU and the NPX have specialized functions and
registers providing fast concurrent operation. The
CPU controls overall program execution while the
NPX uses the coprocessor interface to recognize
and perform numeric operations.
As Figure 4 shows, all processors utilize the same
clock generator and system bus interface components (bus controller, latches, transceivers and bus
arbiter).
Bus Operation
The 8087 bus' structure, operation and timing are
identical to all other processors in the iAPX 86, 88
series (maximum mode configuration). The address
is time multiplexed with the data on the first 16/8
lines of the address/data bus. Ai6 through A19 are
time multiplexed with four status lines 53-56. 53, 54
and 56 are always one (high) for 8087 driven bus
cycles while 55 is always zero (low). When the 8087
is monitoring CPU bus cycles (passive mode) 56 is
also monitored by the 8087 to differentiate
8086/8088 activity from that of a local I/O processor
or any other local bus master. (The 8086/8088 must
be the only processor on the local bus to drive 56
low.) 57 is multiplexed with and has the same value
as BHE for all 8087 bus cycles.
The first threestatus lines, SO-52, are used with an
8288 bus controller to determine the type of bus
S-94
Table 2 lists the eight data types the iAPX 86/20,
88/20 supports and presents the format for each
type. Internally, the NPX holds all numbers in the
. temporary real format. Load and store instructions
automatically convert operands represented in
memory as 16-, 32-, or 64-bit integers, 32- or 64-bit
floating point numbers or i8-digit packed BCD
numbers into temporary real format and vice versa.
The NDP also provides the capability to control
round off, underflow, and. overflow errors in· each
calculation.
Computationsin the NPX use the processor's register stack. These eight 80-bit registers provide the
equivalent capacity of 20 32-bit registers. The NPX
register set can be accessed as a stack, with instructions operating on the top one or two stack elements, or as a fixed register set, with instructions
operating on explicitly designated registers.
Table 5 lists the 8087's instructions by class. All appear as ESCAPE instructions to the host. Assembly
language programs are written in A5M-86, the iAPX
86, 88 assembly language. Table 3 gives the execution times of some typical numeric instructions.
AFN-01820C
iAPX 86/20,88/20
NUMERIC PROCESSOR
EXTENSION ARCHITECTURE
Table 3. Execution Times for Selected iAPX 86/20
Numeric Instructions and Corresponding
iAPX 86/10 Emulation
As shown in Figure 5, the 8087 is internally divided
into two processing elements, the control unit (CU)
and the numeric execution unit (NEU). The NEU
executes all numeric instructions, while the CU
receives and decodes instructions, reads and writes
memory operands and executes NPX control instructions. The two elements are able to operate
independently of one another, allowing theCU to
maintain synchronization with the CPU while the
NEU is busy processing a numeric instruction.
Approximate Execution
Time (p,s)
Floating Point
Instruction
iAPX 86/20 iAPX 86/10
(5 MHz
Clock)
Emulation
Add/Subtract
Multiply (single'
precision)
Multiply (extended
precision)
Divide
Compare
Load (double precision)
Store (double precision)
Square Root
Tangent
Exponentiation
17
1,600
19
1,600
27
39
9
10
21
36
90
100
2,100
3,200
1,300
1,700
1,200
19,600
13,000
17,100
Control Unit
The CU keeps the 8087 operating in synchronization
with its host CPU. 8087 instructions are intermixed
with CPU instructions in a single instruction stream.
The CPU fetches all instructions from memory; by
monitoring the status signals (80-82, 86) emitted by
the CPU, the NPX control unit determines when an
DATA
16
STATUS
EXCEPTION
POINTERS
ADDRESS
-
-
-
,I
I
I
I
I
L
I
I
I
I
I
I
(6)
T
A
G
(5)
REGISTER STACK
W
0
R
D
-
-
-
-
(4)
(3)
(2)
I
(1)
,-
ao BITS
-,-
(0)
-
-
-- ~
Figure 5. 8087 Block Diagram
S-95
AFN-0182DC
iAPX 86/20, 88/20
8086 instruction is being fetched. The CU monitors
the Data bus in parallel with the CPU to obtain instructions that pertain to the 8087.
The CU maintains an instruction queue that is identical to the queue in the host CPU. The CU automatically determines if the CPU is an 8086 or an 8088
immediately after reset (by monitoring the BHE/ S7
line) and matches its queue length accordingly. By
monitoring the CPU's queue status lines (OSO, OS1),
the CU obtains and decodes instructions from the
queue in synchronization with the CPU.
A numeric instruction appears as an ESCAPE instruction to the 8086 or 8088 CPU. Both the CPU and
NPX decode and execute the ESCAPE instruction
together. The 8087 only recognizes the numeric instructions shown in Table 5. The start of a numeric
operation is accomplished when the CPU executes
the ESCAPE instruction. The instruction mayor may
not identify a memory operand.
The CPU does, however, distinguish between ESC
instructions that reference memory and those that
do not. If the instruction refers to a memory operand,
the CPU ca,lculates the operand's address using any
one of its available addressing modes, and then performs a "dummy read" of the word at that location.
(Any location within the 1M byte address space is
allowed.) This is a normal read cycle except that the
CPU ignores the data it receives. If the ESC instruction does not contain a memory reference (e.g. an
8087 stack operation), the CPU simply proceeds to
the next instruction.
An 8087 Instruction can have one of three memory
reference options; (1) not reference memory; (2)
load an operand word from memory into the 8087; or
(3) store an operand word from the 8087 into
memory. If no memory reference is required, the
8087 simply executes its instruction. If a memory
reference is required, the CU uses a "dummy read"
cycle initiated by the CPU to capture and save the
address that the CPU places on the bus. If the instruction is a load, the CU additionally captures the
data word when it becomes available on the local
data bus. If data required is longer than one word,
the CU immediately obtains the bus from the CPU
using the requesVgrant protocol and reads the rest
of the information in consecutive bus cycles. In a
store operation, the CU captures and saves the store
address as in a load, and ignores the data word that
follows in the "dummy read" cycle. When the 8087 is
ready to perform the store, the CU obtains the bus
from the CPU and writes the operand starting at the
specified address.
Numeric Execution Unit
The NEU executes all instructions that involve the
register stack; these include arithmetic, logical,
transcendental, constant and data transfer instructions. The data path in the NEU is 84 bits wide (68
fraction bits, 15 exponent bits and a sign bit) which
allows internal operand transfers to be performed at
very high speeds.
When the NEU begins executing an instruction, it
activates the 8087 BUSY signal. This signal can be
used in conjunction with the CPU WAIT instruction
to resynchronize both processors when the NEU has
completed its current instruction.
Register Set
The iAPX 86/20 register set is shown in Figure 3.
Each of the eight data registers in the 8087's register
stack is 80 bits wide and is divided into "fields"
corresponding to the NDP's temporary real data
type.
At a given point in time the TOP field in the control
word identifies the current top-of-stack register. A
"push" operation decrements TOP by 1 and loads a
value into the new top register. A "pop" operation
stores the value from the current top register and
then increments TOP by 1. Like iAPX 86/10, 88/10
stacks in memory, the 8087 register stack grows
"down" toward lower-addressed registers.
Instructions may address the data registers either
implicitly or explicitly. Many instructions operate on
the register at the top of the stack. These instructions implicitly address the register pointed to by the
TOP. Other instructions allow the programmer to
explicitly specify the register which is to be used.
Explicit register addressing is "top-relative."
Status Word
The status word shown in Figure 6 reflects the over~
all state of the 8087; it may be stored in memory and
then inspected by CPU code. The status word is a
16-bit register divided into fields as shown in Figure
6. The busy bit (bit 15) indicates whether the NEU is
either executing an instruction or has an interrupt
request pending (B = 1), or is idle (B = 0). Several
instructions which store and manipulate the status
word are executed exclusively by the CU, and these
do not set the busy bit themselves.
S-96
AFN.()1B20C
iAPX 86/20, 88/20
15
I
B I
c,
ITO piC, I
c,
I C, IIR I X I PE I UE I OE I ZE I DE liE
I
I
EXCEPTION FLAGS (1 = EXCEPTION HAS OCCURRED)
INVALID OPERATION
DENQRMALIZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT REQUEST(l)
CONDITION CODE(2)
TOP OF STACK POINTER(3)
NEU BUSY
l'liR is set if any unmasked exception bit Is set, cleared otherwise.
(2lSee Table 3 for condition code interpretation.
(3)Top Values:
000 - Register 0 is Top of Stack.
001 Register ~ is Top of Stack.
;0
111 = Register 7 is Top of Stack.
Figure 6. 8087 Status Word
The four numeric condition code bits (C O-C3 ) are
similar to the flags in a CPU: various instructions
update these bits to reflect the outcome of NDP
operations. The effect of these instructions on the
condition code bits is summarized in Table 4.
Tag Word
The tag word marks the content of each register as
shown in Figure 7. The principal function of the tag
word is to optimize the NDP's performance. The tag
word can be used, however, to interpret the contents
of 8087 registers.
Bits 14-12 of the status word point to the 8087 register that is the current top-of-stack (TOP) as
described above.
Instruction and Data Pointers
Bit 7 is the interrupt request bit. This bit is set if any
unmasked exception bit is set and cleared otherwise.
The instruction and data pointers (see Figure 8) are
provided for user-written error handlers. Whenever
the 8087 executes an NEU instruction, the CU saves
the instruction address, the operand address (if
present) and the instruction opcode. 8087 instructions can store this data into memory.
Bits 5-0 are set to indicate that the NEU has
detected an exception while executing an instruction.
S-97
AFN·01B20C
iAPX 86/20, 88/20
Table 4. Condition Code Interpretation
Instruction
Interpretation
C3
C2
Cl
Co
Compare, Test
0
0
1
1
X
X
X
X
X
X
X
X
0
1
0
1
A>8
A<8
A=8
A? 8 (not comparable)
Remainder
0,
0,
0
1
00
00
02
02
Complete reduction
Incomplete reduction
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Examine
Valid, positive, unnormalized
Invalid, positive, exponent"" 0
Valid, negative, unnormalized
Invalid, negative, exponent"" 0
. Valid, positive, normalized
Infinity, positive
Valid, negative, normalized
Infinity, negative
Zero, positive
Empty
Zero, negative
Empty
Invalid, positive, exponent=O
Empty
Invalid, negative, exponent = 0
Empty
x = value is not affected by instruction.
o = Co, ~, C,
hold 3 LSBs of the quotient generated during a remainder operation.
15
15.
INSTRUCTION POINTER (15-0)
INSTRUCTION POINTER
TAG VALUES:
00 = VALID
(19-16)
01 = ZERO
10 = SPECIAL
11 = EMPTY
II
0
INSTRUCTION OPCODE "(10.0)
DATA POINTER (15-0)
DATA POINTER (19-16)
Figure 7. 8087 Tag Word
I
0
Figure 8. 8087 Instruction and Data Pointers
s-98 I
AFN.Q'820C
iAPX 86/20, 88/20
Control Word
Exception Handling
The 8087 provides several processing options which
are selected by loading a word from memory into the
control word. Figure 9 shows the format and encoding of the fields in the control word.
The 8087 detects six different exception conditions
that can occur during instruction execution. Any or
all exceptions will cause an interrupt if unmasked
and interrupts are enabled.
The low order byte of this control word configures
8087 interrupts and exception masking. Bits 5-0 of
the control word contain individual masks for each
of the six exceptions that the 8087 recognizes and
bit 7 contains a general mask bit for all 8087 interrupts. The high order byte of the control word
configures the 8087 operating mode including
precision, rounding, and infinity controls. The precision control bits (bits 9-8) can be used to set the
8087 internal operating precision at less than the
default of temporary real precision. This can be useful in providing compatibility with earlier generation
arithmetic processors of smaller precision than the
8087. The rounding control bits (bits 11-10) provide
for directed rounding and true chop as well as the
unbiased round to nearest mode specified in the
proposed IEEE standard. Control over closure of the
number space at infinity is also provided (either
affine closure, ±oo, or projective closure, 00, is treated
as unsigned, may be specified).
If interrupts are disabled the 8087 will simply continue execution regardless of whether the host
clears the exception. If a specific exception class is
masked and that exception occurs, however, the
8087 will post the exception in the status register
and perform an on-chip default exception handling
procedure, thereby allowing processing to continue.
The exceptions that the 8087 detects are the
following:
1. INVALID OPERATION: Stack overflow, stack underflow, indeterminate form (0/0, 00- 00, etc.) or
the use of a Non-Number (NAN) as an operand.
An exponent value is reserved and any bit pattern
with this value in the exponent field is termed a
Non-Number and causes this exception. If this
exception is masked, the 8087's default response
is to generate a specific NAN called INDEFINITE,
or to propagate already existing NANs as the calculation result.
15
I
x x
X
II C I
R C
I
P C
I M
I
x
I PM I UM I OM I ZM I DM 11M
I
EXCEPTION MASKS (1
I
= EXCEPTION
IS MASKED)
INVALID OPERATION
DENORMALIZED OPERAND
ZERO DIVIDE
OVERFLOW
UNDERFLOW
PRECISION
(RESERVED)
INTERRUPT MASK (1
0
INTERRUPTS ARE MASKED)
PRECISION CONTROL(1)
ROUNDING CONTROL(2)
INFINITY CONTROL (0
0
PROJECTIVE, 1
0
AFFINE)
(RESERVED)
(1)Precision Control
00 = 24 bits
= Reserved
10 = 53 bits
11 = 64 bits
01
{2 l Rounding
Control
00.:: Round to Nearest or Even
01 = Round Down (toward _ 10)
10:: Round Up (toward + ac)
11 = Chop {truncate toward zero)
Figure 9. 8087 Control Word
S-99
AFN-Q1820C
iAPX 86/20, 88/20
2. OVERFLOW: The result is too large in magnitude
to fit the specified format. The 8087 will generate
an encoding for infinity if this exception is
masked.
3. ZERO DIVISOR: The divisor is zero while the dividend is a non-infinite, non-zero number. Again,
the 8087 will generate an encoding for infinity if
this exception is masked.
4. UNDERFLOW: The result is non-zerO but too
small in magnitude to fit in the specified format. If
this exception is masked the 8087 will
denormalize (shift right) the fraction until the exponent is in range. This process is called gradual
.
underflow.
5. DENORMALIZED OPERAND: At. least one of the
operands or the result is denormalized; it has the
smallest exponent but a non-zero significand.
Normal processing continues if this exception is
masked off.
6. INEXACT RESULT: If the true result is not exactly
representable in the specified format, the result
is rounded according to the rounding mode, and
this flag is set. If this exception is masked, processing will simply continue.
S-100
AFN-01B20C
iAPX 86/20, 88/20
-NOTICE: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ........... O°C to 70°C
Storage Temperature ................. -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .................... -1.0V to +7V
Power Dissipation ............................3.0 Watt
D.C. CHARACTERISTICS
Symbol
(TA = O°C to 70°C, VCC =+5V ±10%)
Parameter
Min.
Max.
Units
Test Conditions
Vil
Input low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
0.45
V
IOl = 2.0 mA
V
IOH = -400 !LA
VOL
Output low Voltage
VOH
Output High Voltage
Icc
Power Supply Current
475
mA
TA = 25°C
III
Input leakage Current
±10
!LA
OV.;;; VIN';;; Vee
ILO
Output leakage Current
±10
!LA
0.45V .;;; VOUT .;;; Vee
Vel
Clock Input low Voltage
-0.5
+0.6
V
VCH
Clock Input High Voltage
3.9
Vce + 1.0
V
CIN
Capacitance of Inputs
10
pF
fc = 1 MHz
CIO
Capacitance of I/O Buffer
(ADO-15, A16-A19, BHE, S2-S0,
RQ/GT) and ClK
15
pF
fc = 1 MHz
10
pF
fc = 1 MHz
COUT
2.4
Capacitance of Outputs
BUSY,INT
A.C. CHARACTERISTICS
(TA = O°C to 70°C, Vee = +5V ±10%)
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
200
500
ns
TClCl
ClK Cycle Period
TClCH
ClK low Time
(21.3 TClCl) - 15
TCHCl
ClK High Time
(V3 TClCl) + 2
Test Conditions
ns
ns
TCH1CH2 ClK Rise Time
10
ns
From 1.0V to 3.5V
TCl2Cl1
ClK Fall Time
10
ns
From 3.5V to 1.0V
TDVCl
Data In Setup Time
TClDX
Data In Hold Time
TRYHCH
READY Setup Time
TCHRYX
READY Hold Time
30
ns
10
ns
(2h TClCl) - 15
ns
ns
TRYlCl
READY Inactive to ClK (See Note 3)
30
-8
TGVCH
RQ/GT Setup Time
30
ns
TCHGX
RQ/GT Hold Time
40
ns
TQVCl
QSO-1 Setup Time
30
ns
TClQX
QSO-1 Hold Time
10
ns
TSACH
Status Active Setup Time
30
ns
TSNCl
Status Inactive Setup Time
30
TILIH
Input Rise Time (Except ClK)
20
ns
TIHll
Input Fall Time (Except ClK)
12
ns
S-101
ns
ns
From 0.8V to 2.0V
From 2.0V to 0.8V
AFN.()l82OC
iAPX 86/20, 88/20
A.C; CHARACTERISTICS (Continued)
TIMING RESPONSES
Min.
Max.
Units
TClMl
Symbol
Command Active Delay (See Note 1)
Parameter
10
35
ns
TClMH
Command Inactive Delay (See Note 1)
10
TRYHSH
Ready Active to Status Passive (See Note 2)
35
110
ns
Test Conditions
ns
TCHSV
Status Active Delay
10
110
ns
TClSH
Status Inactive Delay
10
130
ns
110
ns
80
ns
TClAV
Address Valid Delay
10
TClAX
Address Hold Time
10
TClAZ
Address Float Delay
TClAX
TSVlH
TCllH
Status Valid to ALE High (See Note 1)
15
ClK low to ALE Valid (See Note 1)
15
ns
ns
TCHll
ALE inactive Delay (See Note 1)
TClDV
Data Valid Delay
10
ns
15
ns
CL= 20-100 pF for all
110
ns
8087 Outputs (in addition
ns
to 8087 self-load)
TCHDX
Data Hold Time
10
TCVNV
Control Active Delay (See Note 1)
45
ns
TCVNX
Control Inactive Delay (See Note 1)
5
10
45
ns
TCHBV
BUSYand INT Valid Delay
10
150
ns
TCHDTl
Direction Control Active Delay (See Note 1)
50
ns
TCHDTH
Direction Control Inactive Delay (See Note 1)
30
ns
TClGl
RQ/GT Active Delay
0
85
ns
TClGH
RQ/GT Inactive Delay
0
85
ns
CL = 40 pF (in
addition to 8087 self-load)
TOlOH
Output Rise Time
20
ns
From 0.8V to 2.0V
TOHOl
Output Fall Time
12
ns
From 2.0V to 0.8V
NOTES:
1. Signal at 8284A or 8288 shown for reference only.
2. Applies only to T3 and wait states.
3. Applies only to T2 state (8 ns into T3)'
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUTfOUTPUT
DEVICE
UNDER
TEST
~CL~100PF
-=
A,C. TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC "1" AND O.45V FDA
A LOGIC "0." THE CLOCK IS DRIVEN AT 4.3V AND Q,25V. TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A LOGIC ''1'' AND "0."
.
C L INCLUDES JIG CAPACITANCE
S-102
AFN·0182OC
iAPX 86/20, 88/20
WAVEFORMS
MASTER MODE
T,
CLK
::c
VCl
T,
,
-+- TClCl ~H1CH2 __ ~-I i--TCl2Cl1
~~~CHCl
Tw
V~~~
W;;,
H
If""'
'
\
V/(SEE NOTE 5)
TClAV
~
TCLAX ....
BHE, Au -A'5
TSVlH ....
TCllH'"
ALE (8288 OUTPUT)
(SEE NOTES 4, 6)
I
c=-
rt
READY (8087 INPUT) {
(SEE NOTE 2)
--- .~
~OV
A
-- ---
TCHOX
\I
57-53
./' FLOAT
(SEE NOTE 3)
CHll
I
TRYl~t l-
I:
-- rr
of-
:+-....
,,..-----
TCHRYX
ijl
TClAV-
READ CYCLE
,t:.
A
AD15-ADo
AZ
III
A'5- AO
TCHOTL_
TRYHCH __
I~TOVCl
.r-
.11
TCLOX
OATAIN
TCHOTH'"
\
{M:::
8288 OUTPUTS
(SEE NOTES 6, 7)
.r--
TClML ___
TCLMH-+
II-
TCVNV-
II
DEN
TCVNX~
WRITE CYCLE
TCLAV
:::-I
TClOV
)K
::I
A,,-A.
)K
OATAOUT
TCVNV_
TCLMH
1\
AM:::
{
F 1\
"
-+ l l - T CHOX
rc
~
FLOAT
TCVNX
TClML_
8288 OUTPUTS
(SEE NOTES 6, 7)
\y
FLOAT
FL7
TClML
MWTC
~
TCLMH
3)
11
NOTES:
1. ALL SIGNALS SWITCH BETWEEN VOL ANa VOH UNLESS OTHERWISE SPECIFIED.
2. READY IS SAMPLED NEAR THE END OFT2, T3 ANDTw TO DETERMINE IFTW MACHINE STATE8ARETO BE INSERTED.
3. THE LOCAL BUS FLOATS ONLY IFTHE 8OB7 IS RETURNING CONTROL TO THE B068/B066.
4. ALE RISES AT LATER OF (TSVLH, TCLLH).
5. STATUS INACTIVE IN STATE JUST PRIOR TO T 4.
6. SIGNALS AT B2B4A OR B2BB ARE SHOWN FOR REFERENCE ONLY.
7. THE ISSUANCE OF B2BB COMMAND AND CONTROL SIGNALS (MRDc,
MWi'C, AMWC AND DEN)
LAGS THE ACTIVE HIGH B2BB CEN.
B. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED.
S-103
AFN.()lB20C
inter
iAPX 86/20, 88/20
WAVEFORMS (Continued)
PASSIVE MODE
T,
T,
ClK
\
'-----
FLOAT
I++---;~o-----;o-i
TClDX
FLOAT'
AD,s-AD o
READY (
IN~&~
RESET TIMING
~o------> 50 ~sec-:-----t
1"1
1_---- ~20 ClK CYClES-----I
VCC
ClK
RESET
8087 TRACKS
CPU ACTIVITY
:;:::4 elK CYCLES
8087 READY TO
EXECUTE INSTRUCTIONS
REQUEST/GRANTo TIMING
-0_t-'b~g:~
ClK
TClGl
ROtGTO
~
AO,s-AD o
A'9/Se-A16/S3
82 ,$1'50
CPU
SHE/S7
NOTE: THE CPU PROVIDES ACTIVE PUllUP OF RQ/GTO. SEE TClGH SPEC.
S-104
AFN-01820C
iAPX 86/20, 88/20
WAVEFORMS (Continued)
REQUEST/GRANT 1 TIMING
ClK
AD,s-AD o
A,·iS,-A,s/S3
52 ,5,,50
(SEE NOTE)
BHE/S7
NOTE: ALTERNATE MASTER MAY NOT DRIVE THE BUSES OUTSIDE OF THE REGION
SHOWN WITHOUT RISKING BUS CONTENTION.
BUSY AND INTERRUPT TIMING
ClK
\'------~£f
BUSY,INT
-----TCHBV
S-105
------
AFN-01820C
iAPX 86/20, 88/20
Mnemonics © Intel 1980
S-106
AFN-Q1820C
iAP)( 86/20, 88/20
Table 5. 8087 Extensions to the 8086/8088 Instruction Set (Continued)
7 6 5
Arithmetic
4
3
2 1
0 7
6 5
4
3
2 1
0
7 6 5
4 3
2
1
0 7
6 5 4
3
2
1
0
FADD = Addition
Integer/Aeal Memory with ST(O)
ESCAPE
ST(i) and ST(O)
ESCAPE
MF
d
IMOD
P
0
11
0
0
RIM
0
0
STII)
0
R
RIM
R
RIM
IDISP-LO)
IDISP-HI)
IDISP-LO)
IDISP-HI)
IDISP-LO)
IDISP-HI)
IDISP-LO)
IDISP-HI)
FSUB " Subtraction
IntegerlReal Memory with ST(O)
ESCAPE
ST(i) and ST(O)
ESCAPE
MF
d
IMOD
P
11
1
FMUL " Multiplication
Integer/Real Memory with ST(O)
ESCAPE
ST(i) and ST(O)
ESCAPE
o
MF
d
P
1 MOD
0
1
RIM
11
0
1
RIM
FDIV = Division
MF
Integer/Aeal Memory with ST(O)
ESCAPE
ST(i) and ST(O}
ESCAPE
FSQRT = Square Root of ST(O)
ESCAPE
1 11
FSCALE'" Scale SI(O) by ST(l)
ESCAPE
11
d
P
R
RIM
1
R
RIM
1
1
0
1
1
1
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
0 1
0
1
1
01 MOD
o
11
1
0
1
1
FPREM " Partial Remainder of
ESCAPE
0
0
1 11
FRNDINT = Round ST(O}
to Integer
ST(OI
ESCAPE
0
0
1 11
FXTRACT = Extract Components
of ST(O)
ESCAPE
1
0
FABS " Absolute Value of ST(O)
ESCAPE
0
0
1 11
1
0
0
FCHS
ESCAPE
111
1
0
~
ST(l)
1
Change Sign of ST(O)
=:
1
11
1
1
Transcendental
FPTAN
Partial Tangent of ST(O)
=:
ESCAPE
0
0
1
111
0
FPATAN = Partial Arctangent of
ESCAPE
0
0
111
F2XM1 = 2 8T(0)_1
ST(O)
ESCAPE
0
0
111
FYL2X
ESCAPE
=
~
ST(l)
ST(l)' L092 [ST(O)]
FYL2XP1 = ST(1)' L092 [ST(O) + 1J
ESCAPE
1
0
1 11
0
1
I
1
1
11
0
1
0
1 1
0
I
0
1
1
o1
oI
1
1
Constants
FLOZ = LOAD + 0.0 into ST(O)
ESCAPE
FLD1 = LOAD + 1.0 into ST(O)
ESCAPE
FLOPI
= LOAD
FLOL2T
11"
into ST(O)
= LOAD 1092
10 into ST(O)
FLOL2E = LOAD 1092 e into ST(O)
FLDLG2
= LOAD
FLOLN2
= LOAD 10ge 2
10910 2 into ST(O)
into ST(O)
0
ESCAPE
0
0
1
ESCAPE
0
0
1
0
1
ESCAPE
ESCAPE
1
1
1
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
ESCAPE
I
I
0
0
1
1
Mnemonics © Intel 1980
S-107
AFN-01820C
intJ
iAPX 86/20, 88/20
.Table 5•. 8087 Extensions to the 8086/8088 Instruction Set (Continued)
7 ·6 5
4 3 2 1
0
7
6
5 4 3
2 1 ·0
7
6
5
4 3
2 1
0
7
6
5
4 3
2
1 0
Processor Control
=Initialize NDP
=Enable Interrupts
ESCAPE
1 1 11
1 1 11
0 1 1 11
FLDCW = Load Control Word
ESCAPE
0
0
1
I MOD
(DISP-LO)
(DISP-HI)
FSTew = Store Control Word
ESCAPE
·0
0
1
MOD
1 1 1
.,R/M
(DISP-LO)
(DISP-HI)
FSTSW = Store Status Word
ESCAPE
1 0
1
MOD
1 1 1 ··H/M
(DISP-LO)
(DISP-HI)
FCLEX = Clear Exceptions
ESCAPE
0
FSTENY ::: Store Environment
ESCAPE
(DISP-HI)
FLDENV = Load Environment
ESCAPE
0
FSAYE = Save State
ESCAPE·
FASTOR = Restore State
FINeSTP = Increment Stack Pointer
FINIT
FENI
FDISI '" Disable
FDECSTP
Interr~pts
=Decrement Stack Pointer I
FFREE =" Free ST(i)
ESCAPE
0
1 0
0
0
1 1
ESCAPE
0
1 0
0
0
0
0
1 0
0
0
0
1
1 0
1
RIM
1 1
1 0
0
0
1 0
0
1
MOD
1 1 0
RIM
(DISP-LO)
0
1
MOD
1 0
0
RIM
(DISP-LO)
(DISP-HI)
1 .0
1
MOD
1 1 0
RIM
(DISP-LO)
(DISP-HI)
ESCAPE
1 0
1
MOD
1
RIM
(DISP-LO)
(DISP-HI)
ESCAPE
0
1
1 1 0
1 1 1
1
1 1 0
1 1 0
0
ESCAPE
0
ESCAPE
1 0
FNOP = No Operation
I
ESCAPE
FWAIT = CPU Wait for NDP
11
0
0
1 1
0
1 11
1 11
1 1
o.0
0
0
I
I
I
I
·ST(i)
0
1 0 0
O·
0
I
FOOTNOTES:
If mod = 00 then DISP = 0', disp-Iow and disp-high are absent
If mod = 01 then DISP = disp-Iow sign-extended to 16-bits,
dlsp-high Is absent'
If mod = 10 then DISP= disp-hlgh; disp-Iow
if mod = 11 then rIm is treated as an ST(I) field
If rIm = 000 then
if rIm = 001 then
if rIm = 010 then
if rIm = 011 then
if rIm 100 then
if rIm = 101 then
if rIm 110 then
if rIm 111 then
=
=
=
'except if mod
MF =
EA = (BX)
EA = (BX)
EA = (BP)
EA = (BP)
EA (51)
EA = (01)
EA (BPl
EA (BX)
=
=
=
+ (51) + DISP
+ (01) + DISP
+ (51) + DISP
+ (01) + DISP
+ DISP
+ DISP
+ DISP'
+ DISP
ST(O) =
ST(i) =
Current stack top
Ith register beloY\' stack top
d=
Destination
o -Destination is ST(O)
1 - Destination is ST(i)
P=
Pop
0 - No pop
1 - Pop ST(O)
R=
Reverse: When d = 1 reverse the sense of R
o1-
=000 and rIm =110 then EA =dlsp-high: disp-Iow.
Memory Format
00 - 32-bit Real
01 - 32-bit Integer
10 - 64-bit Real
11 - 16-bit Integer
For
For
For
For
Destination (op) Source
Source (op) Destination
FSQRT:
FSCALE:
F2XM1:
FYL2X:
-0:5 8T(0) :5 +'"
_2 15 $ ST(ll < +2'5 and ST(ll integer
For FYL2XP1:
0:5 8T(0) :5 2- 1
0.< 8T(0) < '"
-"'< 8T(1) < + '"
"'18T(O)l < (2 -' ..;2)/2
For FPTAN:
For FPATAN:
Os ST(O)
o
-co < ST(1) < co
o '" ST(O) < nl4
< ST(1) < +co
Mnemonics ©·lnteI1980
S-108
AFN'{)182OC
8087 Instructions,
Encoding and Decoding
APPENDIX A
MACHINE INSTRUCTION ENCODING
AND DECODING
.
encoding scheme in more detail, and in particular,
shows how each memory addressing mode is
encoded.
8087 machine instructions assume one of five
different forms as shown in table A-I. In all
cases, the instructions are at least two bytes long
and begin with the bit pattern 110118, which
identifies the escape class of instructions. Instructions which reference memory operands are
encoded much like similar CPU instructions,
since the CPU must calculate the operands effective address from the information contained in
the instruction. Section 4.2 discusses this
Note that all instructions (except those coded with
a "no-wait" mnemonic) are preceded by an
assembler-generated CPU WAIT instruction
(encoding: 100110118). Segment override
prefixes may also precede 8087 instructions in the
instruction stream.
Table A-I. Instruction Encoding
.~-
~
O,1,o~ 2r bytes
Higher-addressed Byte
Lower-addressed Byte
(1)
RIM
DISPLA9 ~MENT
OP-S
RIM
DISPLAC EMENT
OP-S
REG
1
1
0
1
1
1
1
0
1
1 FORMAT OP-A MOD
1
1
0
1
1
R
P OP-A 1
1
1
1
0
1
1
0
0
1
1
1
1
OP
1
1
0
1
1
0
1
1
1
1
1
OP
7
6
5
4
3
2
OP-A
1
MOD
1
OP-S
(2)
J
(3)
(4)
(5)
J
J
0765432
o
(1)Memory transfers, including applicable processor control instructions; 0, 1, or 2 displacement bytes may
follow.
(2)Memory arithmetic and compilrison instructions; 0, 1, or 2 displacement bytes may follow.
(3)Stack arithmetic and comparison instructions.
(4)Constant, transcendental, some arithmetic instructions.
(5)Processor control instructions that do not reference memory.
OP, OP-A, OP-S: Instruction opcode, possibly split into two fields.
MOD: Same as CPU mode field; see table 4-8.
RIM: Sames as CPU registerlmemory field; see table 4-10.
S-110
MACHINE INSTRUCTION ENCODING AND DECODING
Table A-I. Instruction Encoding (Cont'd.)
FORMAT: Defines memory operand
00 = short real
01 = short integer
10 = long real
11 = word integer
R: 0 = return result to stack top
1 = return result to other register
P: 0 = do not pop stack
1 = pop stack after operation
REG: register stack element
000 = stack top
001 = next on stack
010 = third stack element, etc.
the data bus. Users writing exception handlers
may also find this information useful to identify
the offending instruction.
Table A-2 lists all 8087 machine instructions in
binary sequence. This table may be used to
"disassemble" instructions in unformatted
memory dumps or instructions monitored from
Table A-2. Machine Instruction Decoding Guide
1st Byte
Hex
08
08
08
08
08
08
08
08
08
08
08
08
08
08
08
08
09
09
09
Binary
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
Mnemonics © Intel 1980
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1001
1001
1001
2nd Byte
MOOOO
MOOOO
MOO01
MOO01
M0010
M0010
M0011
M0011
1100
1100
1101
1101
1110
1110
1111
.1111
MODOO
"·MOOOO
M.OO01
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OREG
1REG
OREG
1REG
OREG
1REG
OREG
1REG
OR/M
1R/M
OR/M
Bytes 3, 4
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hl)
(disp-Io),(dlsp-hi)
(disp-Io),(disp-hi)
(dlsp-Io),(dlsp-hl)
(disp-Io),(disp-hl)
(dlsp-Io),(dlsp-hl)
(disp-Io),(dlsp-hi)
(dlsp-Io),(dlsp-hi)
S-I11
ASM-86 Instruction
Format
FADO
short-real
short-real
FMUL
FCOM
short-real
short-real
FCOMP
F5UB
short-real
F5UBR
short-real
FOIV
short-real
FOIVR
short-real
FAOO
5T,5T(I)
5T,5T(i)
FMUL
FCOM
,5T(I)
5T(i)
FCOMP
F5UB
.5T,5T(i)
5T,5T(I)
F5UBR
FOIV
. 5T,5T(I)
FOIVR
5T,5T(I)
FLO
. short-real
reserved
short-real
F5T
MACHINE INSTRUCTION ENCODING AND DECODING
Table A-2. Machine Instruction Decoding Guide (Cont'd.)
1st Byte
Hex
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
09
OA
OA
DA
OA
OA
OA
Binary
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1010
1010
1010
1010
1010
1010
2nd Byte
MOO01
M0010
M0010
M0011
M0011
1100
1100
1101
1101
1101
1101
1101
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
MOOOO
MODOO
MOO01
MOO01
M0010
M0010
1R/M
OR/M
1R/M
OR/M
1R/M
OREG
1REG
0000
·0001
00101-1REG
0000
0001
0010100
0101
0111000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
111OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
Bytes 3,4
(disp-Io),(disp-hi)
(disp-Io),(disp-h i)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io):(disp-hi)
(disp-Io),(d isp-hi)
(disp-Io),(d isp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
S-112
ASM-86 Instruction
Format
FSTP
FLOENV
FLOCW
FSTENV
FSTCW
FLO
FXCH
FNOP
reserved
reserved
reserved
*(1 )
FCHS
FABS
reserved
FTST
FXAM
reserved
FL01
FLOL2T
FLOL2E
FLOPI
FLOLG2
FLOLN2
FLOZ
reserved
F2XM1
FYL2X
FPTAN
FPATAN
FXTRACT
reserved
FDECSTP
FINCSTP
FPREM
FYL2XP1
FSQRT
reserved
FRNOINT
FSCALE
reserved
FIAOO
FIMUL
FICOM
FICOMP
FISUB
FISUBR
short-real
14-bytes
2-bytes
14-bytes
2-bytes
ST(i)
ST(i)
short-integer
short-integer
short-integer
short-integer
short-integer
short-integer
Mnemonics © Intel 1980
MACHINE INSTRUCTION ENCODING AND DECODING
Table A-2. Machine Instruction Decoding Guide (Cont'd.)
, 1st Byte
Hex
DA
DA
DA
DB
DB.
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Binary
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
Mnemonics © Intel 1980
1010
1010
1010
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
2nd Byte
MOD11
MOD11
11-MODOO
MODOO
MOD01
MOD01
MOD10
MOD10
MOD11
MOD11
1101110
1110
1110
1110
1110
1110
1111
MODOO
MODOO
MOD01
MOD01
MOD10
MOD10
MOD11
MOD11
1100
1100
1101
1101
1110
1110
1111
1111
MODOO
MODOO
MOD01
MOD01
MOD10
MOD10
MOD11
MOD11
1100
1100
1101
1101
OR/M
1R/M
Bytes 3,4
(disp-Io),(disp-hi)
(d isp-Io),(disp-hi)
----
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
(disp-Io) ,(disp-hi)
(d isp-Io) ,(disp-hi)
(d isp-Io) ,(d isp-hi)
(d isp-Io),(d isp-hi)
(d isp-Io), (disp-hi)
(d isp-Io),(d isp-hi)
(d isp-Io),(disp-hi)
(d isp-Io), (disp-h i)
---0000
0001
0010
0011
01-1---
---OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OREG
1REG
OREG
1REG
OREG
1REG
OREG
1REG
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OREG
1REG
OREG
1REG
(disp-Io), (d isp-hi)
(d isp-Io) ,(disp-h i)
(disp-Io),(d isp-h i)
(d isp-Io), (d isp-h i)
(disp-Io),(disp-hi)
(disp-Io) ,(d isp-h i)
(disp-Io),(d isp-h i)
(disp-Io),(disp-hi)
(disp-Io), (disp-hi)
(disp-Io),(d isp-hi)
(disp-Io), (disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
S-l13
ASM-86 Instruction
Format
FIDIV
FIDIVR
reserved
FILD
reserved
FIST
FISTP
reserved
FLD
reserved
FSTP
reserved
FENI
FDISI
FCLEX
FINIT
reserved
reserved
reserved
FADD
FMUL
FCOM
FCOMP
FSUB
FSUBR
FDIV
FDIVR
FADD
FMUL
*(2)
*(3)
FSUB
FSUBR
FDIV
FDIVR
FLD
reserved
FST
FSTP
FRSTOR
reserved
FSAVE
FSTSW
FFREE
*(4)
FST
FSTP
short-integer
shorHnteger
short-integer
short-integer
short-integer
temp-real
temp-real
long-real
long-real
long-real
long-real
long-real
long-real
long-real
long-real
ST(i),ST
ST(i),ST
ST(i),ST
ST(i),ST
ST(i),ST
ST(i),ST
long-real
long-real
long-real
94-bytes
94-bytes
2-bytes
ST(i)
ST(i)
ST(i)
MACHINE INSTRUCTION ENCODING AND DECODING
Table A-2. Machine Instruction Decoding Guide (Cont'd.)
1st Byte
Hex
DD
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DF
DF
DF
DF
DF
DF
DF
DF
DF
DF
DF
DF
DF
Binary
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
2nd Byte
111MODOO
MODOO
MOD01
MOD01
MOD10
MOD10
MOD11
MOD11
1100
1100
1101
1101
1101
1101
1101
1110
1110
1111
1111
MODOO
MODOO
MOD01
MOD01
MOD10
MOD10
MOD11
MOD11
1100
1100
1101
1101
111-
Bytes 3,4
---OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OR/M
1R/M
OREG
1REG
0--1000
1001
10111-OREG
1REG
OREG
1REG
OR/M
1R/M
OR/M
1R/M
OR/M
1R1M
OR/M
1R/M
OREG
1REG
OREG
1REG
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
(disp-Io),(d isp-h i)
(disp-Io),(d isp-h i)
(disp-Io),(disp-hi)
(disp-Io ),(d isp-hi)
(disp-Io),(disp-hi)
(disp-Io), (d isp-h i)
(disp-Io),(disp-hi)
(disp-Io),(disp-hi)
----
ASM-86 Instruction
Format
reserved
FIADD
FIMUL
FICOM
FICOMP
FISUB
FISUBR
FIDIV
FIDIVR
FADDP
FMULP
*(5)
reserved
FCOMPP
reserved
reserved
FSUBP
FSUBRP
FDIVP
FDIVRP
FILD
reserved
FIST
FISTP
FBLD
FILD
FBSTP
FISTP
*(6)
*(7)
*(8)
*(9)
reserved
word-integer
word-integer
word-integer
word-integer
word-integer
word-integer
word-integer
word-integer
ST(i),ST
ST(i),ST
ST(i),ST
ST(i),ST
ST(i),ST
ST(i),ST
word-integer
word-integer
word-integer
packed-decimal
long-integer
packed-decimal
long-integer
* The marked enco~ings are not generated by the language translators. If, however, the 8087
encounters one one these encodings in the instruction stream, it will execute it as follows:
(1) FSTP
ST(i)
(2) FCOM
ST(i)
(3) FCOMP
(4) FXCH
(5) FCOMP
(6) FFREE
ST(i)
ST(i)
ST(i)
ST(i) and pop stack
(7) FXCH
ST(i)
(8) FSTP
ST(i)
(9) FSTP
ST(i)
S~114
Mnemonics ©lnte11980
inter
U.S. AND CANADIAN SALES OFFICES
3065 Bowors Avenue
Sanla Clara, California 95051
August 1981
Tel: (408) 987·8080
TWX: 910·338·0026
TelEX: 34·6372
ALABAMA
Intol Corp.
303 Williams Avenue. S.w.
Suite 1422
Huntsville 35801
Tal: (205) 533·9353
ARIZONA
Intol Corp.
10210 N. 25th Avenue, Suite 11
Phoenix 65021
Tel: (602) 669·4980
CALIFORNIA
Inial Corp.
7670 Opportunity Rd.
Suila 135
San Diego 92111
Tel: (714) 268·3563
Intel Corp.'
2000 East 4th Street
Suile 100
Santa Ana 92705
Tel: (714) 635·9642
TWX: 910·595·1114
Intel Corp,"
5530 Corbin Ava.
Suita 120
Tarzana 91356
Tel: (213) 708-0333
TWX: 910·495·2045
Intel Corp,"
3375 Scott Blvd.
Santa Clara 95051
Tel: (408) 987·808e
TWX: 910·339·9279
910-338-0255
Earle Associates, Inc.
4617 Ruffner Street
Suite 202
San Diego 92111
Tel: (714) 278·5441
Mac·1
2576 Shatluck Ave.
Suile 4B
Berkeley, CA 94704
Mac·1
558 Valley Way
Calaveras Business Park
Milpitas 95035
Tel: (408) 946·8885
Mac·1
P.O. Box 8763
Fountain Valley 92708
Tel: (714) 839·3341
Mac·1
25 Village Parkway
Santa Monica 90409
Tel: (213) 452·7611
Mac·1
20121 Ventura Blvd., Suile 240E
Woodland Hills 91364
Tel: (213) 347·5900
COLORADO
Intel Corp."
650 S. Cherry Street
SUite 720
Denver 60222
TeJ: (303) 321·8086
TWX: 910·931·2289
CONNECTICUT
Intel Corp.
36 Padanaram Road
Danbury 06810
Tel: (203) 792·8368
TWX: 710·456·1199
EMC Corp.
48 Purnell Place
Manchester 06040
Tel: (203) 846·8085
FLORIDA
Intel Corp.
1500 N.W. 62nd Street, Suite t04
FI. Lauderdale 33309
Tel: (305) 771·0600
TWX: 510·958·9407
Intel Corp.
600 N. Mailland, Suite 205
Maitland 32761
Tel: (305) 828·2393
TWX: 810·853·9219
GEORGIA
Intel Corp.
3300 Holcomb Bridge Rd.
Norcr08S 30092
Tel: (404) 449·0541
ILLINOIS
Intel Corp."
2550 Golf Road, Suite 815
Rolling Mesdows 60008
Tel: (312) 981·7200
TWX: 910·651·5881
INDIANA
Intel Corp.
9101 Wesleyan Road
Suite 204
Indianapolis 46268
Tel: (317) 875·0623
IOWA
Inlel Corp.
S!. Andrews Building
1930 SI. Andrews Drive N.E.
Cedar Rapids 52402
Tel: (319) 393·5510
KANSAS
Intel Corp.
9393 W. 110th St., Ste. 265
Overland Park 66210
Tel: (913) 642·8080
MARYLAND
Inlel Corp."
7257 Parkway Drive
Hanover 21076
Tel: (301) 796·7500
TWX: 710·862·1944
MASSACHUSETTS
Intel Corp.'
27 Industrial Ave.
Chelmsford 01824
Tel: (617) 256·1800
TWX: 710·343·6333
EMC Corp.
381 Elliot Street
Newton 02164
Tel: (617) 244·4740
TWX: 922531
MICHIGAN
Intel Corp.'
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313) 353·0920
TWX: 610·244·4915
MINNESOTA
Intel Corp.
7401 Metro Blvd.
Suite 355
Edina 55435
Tel: (612),835·6722
TWX: 910·576·2867
MISSOURI
Intel Corp.
502 Earth City Plaza
Suite 121
Earth City 63045
Tel: (314) 291-1990
NEW JERSEY
Intel Corp.'
Raritan Plaza
2nd Floor
Raritan Center
Edison 08837
Tel: (201) 225·3000
TWX: 710·480·6238
M. T.I.
383 Route 46 Weat
Fairfield, NJ 07006
NEW MEXICO
BFA Corporation
P.O. Box 1237
Las Cruces 88001
Tel: (505) 523·0601
TWX: 910·983·0543
BFA Corporation
3705 Westerfield, N.E.
Albuquerque 87111
Tel: (505) 292·1212
TWX: 910·989·1157
NEW YORK
Intel Corp.'
300 Molar Pkwy.
Hauppauge 11767
Tel: (516) 231·3300
TWX: 510·227·6236
Intel Corp.
80 Washington St.
Poughkeepsie 12601
Tel: (914) 473-2303
TWX: 510·248-0060
Intel Corp.'
2255 Lyell Avenue
Lower Floor East Suite
Rochesler 14606
Tel: (716) 254·6120
TWX: 510·253·7391
T·Squared
4054 Newcourt Avenue
Syracuse 13206
Tel: (315) 463-8592
TWX: 710·541·0554
T·Squared
7353 Pittsburgh
Victor Road
Victor 14564
Tel: (716) 924·9101
TWX: 510·254·8542
NORTH CAROLINA
Intel Corp.
2306 W. Meadowview Rd.
Suite 206
Greensboro 27407
Tel: (919) 294·1541
OHIO
Inlel Corp.'
6500 Poe Avenue
Dayton 45414
Tel: (513) 890-5350
TWX: 810'450-2526
Intel Corp.'
Chagrin' Brainard Bldg .• No. 300
26001 Chagrin Blvd.
Cleveland 44122
Tel: (216) 464-2736
TWX: 610·427·9298
OREGON
Intel Corp.
10700 S.W. Beaverton
Hillsdale Highway
Suite 324
Beaverton 97005
Tel: (503) 641·8066
TWX: 910-467-8741
PENNSYLVANIA
Inlel Corp.'
510 Pennsylvania Avenue
Fort Washington 19034
Tel: (215) 641-1000
TWX: 510-661,2077
Intel Corp.'
201 Penn Cenler Boulevard
Suite 301W
Pittsburgh 15235
Tel: (412) 823·4970
Q.E.D. Electronics
300 N. York Road
Hatboro 19040
Tel: (215) 674·9600
TEXAS
Intel Corp.'
2925 L.B.J. Freeway
Suite 175
Dallas 75234
Tel: (214) 241·9521
TWX: 910·860·5617
Intel Corp.'
6420 Richmond Ave.
Suite 280
Houston 77057
Tel: (713) 784·3400
TWX: 910·881·2490
Industrial Digital SyslemS Corp.
5925 Sovereign
Suite 101
Houston 77036
Tel: (713) 988-9421
Inlel Corp.
313 E. Anderson Lane
Suita 314
Austin 78752
Tel: (512) 454·3628
UTAH
Intal Corp. (temporary)
3519 Lexington Dr.
Bountiful, UT 84010
Tel: (801) 292·2164
VIRGINIA
Intel Corp.
1501 Santa Rosa Road
Suite C-7
Richmond, VA 23288
Tel: (804) 282-5668
WASHINGTON
Intel Corp.
Suite 114, Bldg. 3
1603 116th Ave. N.E.
Bellevue 98005
Tel: (206) 453·8066
TWX: 910·443·3002
WISCONSIN
Intel Corp.
150 S. Sunnyslope Rd.
Brookfield 53005
Tel: (414) 784·9060
CANADA
Inial Semiconductor Corp .•
Suite 233, Bell Mews
39 Highway 7, Belts Corners
Ottawa. Ontario K2H 8R2
Tel: (613) 829·9714
TELEX: 053·4115
Intel Semiconductor Corp.
50 Galaxy Blvd.
Unit 12
Aexdale, Ontario
M9W 4Y5
Tel: (416) 675-2105
TELEX: 06963574
Multllek, Inc."
15 Grenfell Crescent
Ottawa, Ontario K2G OG3
Tel: (613) 226·2365
TELEX: 053-4565
Multilak, Inc.'
Toronlo
Tel: 1·800·267-1070
Multilek.lnc.
Monlreal
Tal: 1·800·267·1070
'Field Application Location
U.S. AND CANADIAN DISTRIBUTORS
3065 Bowers Avenue
Santa Clara, Celifornia 95051
Tel: (408) 987·8080
TWX: 910·338·0026
TELEX: 34·6372
ALABAMA
Arrow Electronics
4717 University Dr.
Suite 102 1/2 D.
Huntsville 35405
Tel: (205) 830·1103
tHemiltonl Avnet Electronics
4812 Commercial Drive N.W.
Huntsville 35805
Tel: (205) 837·7210
TWX: 810·726·2162
tPioneer / Huntsville
1207 Putnam Drive N.W.
Huntsville 35805
.
Tel: (205) 837·9300
TWX: 810·726·2197
ARIZONA
tHemilton/ Avne! Electronics
505 S. Madison Drive
Tempe, AZ 85281
Tel: (602) 231·5140
TWX: 910·950·0077
tWyle Distribution Group
8155 N. 24th Streat
Phoenix 85021
Tel: (602) 995·9185
TWX: 910·951·4282
CALIFORNIA
Arrow Electronics, Inc.
521 Weddell Dr.
Sunnyvale 94086
Tel: (408) 745·6600
TWX: 910·339·9371
tAvne! Electronics
350 McCormick Avenue
Costa Mesa 92626
Tel: (714) 754·6051
TWX: 910·595·1928
Hamilton/ Avnet Electronics
1175 Bordeaux Dr.
Sunnyvale 94086
Tel: (408) 743·3300
TWX: 910·339·9332
tHemilton/ Avnet Electronica
4545 Viewridge Ave
San Diego 92123
Tel: (714) 563-1969
TWX: 910·335·1216
tHamillonl Avne! Electronics
10912 W. Washington Blvd.
Culver City 90230
Tel: (213) 558·2193
TWX: 910·340·6364 or 7073
tHemilton Electro Sales
3170 Pullman Street
Costa Mesa 92626
Tel: (714) 641·4109
TWX: 910·595·2638
tWyle Distribution Group
~~~~~~~~~n~o~~;et
Tel:,1(213) 322-8100
TWX: 910·348·7140 or 7111
~~l~ec~:~~~~~~~ g~~uP
San Diego 92123
Tel: (714) 565·9171
TWX: 910·335-1590
tWyle Distribution Group
3000 Bowers Avenue
Santa Clara 95052
Tel: (408) 727-2500
TWX: 910-338-0451 or 0296
Wyle Distribution Group
17872 Cowan Avenue
Irvine 92713
Tel: (714) 641-1600
TWX: 910·595·1572
COLORADO
tWyle Distribution Group
451 E 124th Avenue
Thornton, CO 80241
Tel: (303) 457·9953
TWX: 910-936-0770
tHamilion / Avnet Electronics
8765 E. Orchard Road
Suite 708
Englewood 80111
Tel: (303) 740-1017
TWX: 910-935·0787
August 1981
CONNECTICUT
tArrow Electonics
12 Beaumont Road
Wallingford 06512
Tel: (203) 265·7741
TWX: 710·476·0162
tHamiltonl Avnet Electronics
Commerce Industrial Park
Commerce Drive
Danbury 06810
Tel: (203) 797·2800
TWX: 710-456·9974
tHarvey Electronics
112 Main Street
Norwalk 06851
Tel: (203) 853·1515
TWX: 710·468·3373
FLORIDA
t Arrow Electronics
1001 N.W. 62nd Street
Suite 108
Ft. Lauderdale 33309
Tel: (305) 776·7790
TWX: 510·955·9456
t Arrow Electronics
115 Palm Bay Road, N.W.
Suite 10, Bldg. 200
Palm Bay 32905
Tel: (305) 725-1480
TWX: 510·959·6337
tHamilion / Avnet Electronics
6800 Northwest 20th Ave.
FI. Lauderdale 33309
Tel: (305) 971·2900
TWX: 510·956,3097
Hamilton I Avnet Electronics
3197 Tech. Drive North
St. Petersburg 33702
Tel: (813) 576·3930
TWX: 810·863·0374
tPioneerlOrlando
6220 S. Orange Blossom Trail
Suite 412
Orlando 32809
Tel: (305) 859·3600
TWX: 810·850·0177
GEORGIA
Arrow Electronics
2979 Pacific Drive
Norcross 30071
Tel: (404) 449·8252
TWX: 810·766·0439
tHamiltonl Avnet Electronics
5825 D. Peachtree Corners
Norcross 30092
Tel: (404) 447·7500
TWX: 810·766·0432
Pioneer I Georgia
5835 8 Peachtree Corners E
Norcross 30092
Tel: (404) 448·1711
TWX: 810·766·4515
ILLINOIS
Arrow Electronics
492 Lunt Avenue
P.O. Box 94248
Schaumburg 60172
Tel: (312) 893·9420
TWX: 910·291·3544
tHamiitonl Avnet Electronics
3901 No. 25th Avenue
Schiller Park 60176
Tel: (312) 678·6310
TWX: 910·227,0060
Pioneer/Chicago
1551 Carmen Drive
Elk Grove 60007
Tel: (312) 437·9680
TWX: 910·222'1834
INDIANA
Arrow Electronics
2718 Rand Road
Indianapolis 46241
(317) 243·9353
TWX: 810·341·3119
tHamilton/ Avnet Electronics
485 Gradle Drive
Carmel 46032
Tel: (317) 844·9333
TWX: 810·260·3966
INDIANA (Cont.)
Pioneer /Indiana
6408 Castleplace Drive
Indianapolis 46250
Tel: (317) 849·7300
TWX: 810·260·1794
NEW HAMPSHIRE
t Arrow Electronics
1 Perimeter Drive
Manchester 03103
Tel: (603) 668·6968
TWX: 710·220'1664
KANSAS
tHamillon I Avne! Electronics
9219 Quivera Road
Overland Park 66215
Tel: (913) 888·8900
TWX: 910-743·0005
tComponent Speclalllea, Inc.
8369 Nieman Road
lenexa 66214
Tel: (913) 492·3555
NEW JERSEY
tArrow Electronics
Pleesant Valley Avenue
Moorestown 08057
Tel: (215) 928·1800
TWX: 710·897·0829
tArrow Electronics
265 Midland AVenue
Saddle Brook 07662
Tel: (201) 797·5800
TWX: 710·998·2206
tHamilton/ Avnet Electronics
1 Keystone Ave.
Bldg. 38
Cherry Hill 08003
Tel: (609) 424·0100
TWX: 710·940·0262
Hamilton/ Avnet Electronics
10 Industrial Road
Fairfield 07006
Tel: (201) 575·3390
TWX: 710·734·4388
tHarvey Electronics
45 Route 46
Pinebrook 07058
Tel: (201) 227-1262
TWX: 710-734'4382
Measurement Technology Sales Corp'.,
383 Route 46 W
Fairfield, NJ 07006
Tel: (201) 227·5552
MARYLAND
tHamiJtonl Avnet Electronics
6822 Oak Hall Lane
Columbia, MD 21045
Tel: (301) 995·3500
TWX: 710·862-1861
Mesa
16021 Industrial Dr.
Gaithersburg 20760
Tel: (301) 948,4350
tPioneer /Washington
9100 Gaither Road
Gaithersburg 20760
Tel: (301) 948·0710
, TWX: 710·828,0545
MASSACHUSETTS
tHamiltonl Avnet Electronics·
50 Tower Office Park
Woburn 01801
Tel: (617) 935·9700
TWX: 710·393·0382
tArrow Electronics
Arrow Dr.
Woburn 01801
Tel: (617) 933·8130
TWX: 710·393·6770
Harvey / 80slon
44 Hartwell Ave.
Lexington 02173
Tel: (617) 863,1200
TWX: 710·326·6617
MICHIGAN
t Arrow Electronics
3810 Varsity Drive
Ann Arbor 48104
Tel: (313) 971·8220
TWX: 810·223·6020
tPioneer/Michigan
13485 Stamford
Livonia 48150
Tel: (313) 525-1800
TWX: 810-242·3271
tHamilton / Avnet Electronics
32487 SchOOlcraft Road
Livonia 48150
Tel: (313) 522-4700
TWX: 810-242'8775
MINNESOTA
tArrow Electronics
5230 W. 73rd Street
Edina 55435
Tel: (612) 830·1800
TWX: 910·576·3125
tlndustrial Components
5229 Edina Induatrial Blvd.
MinneapOlis 55435
Tel: (612) 831-2666
TWX: 910·576·3153
Hamiltonl Avnet Electronics
10300 Bren Ad. East
Minnetonka 55343
Tel: (612) 932·0666
TWX: (910) 576·2720
tHamiltonl Avnet Electronics
7449 Cahill Road
Edina 55435
Tel: (612) 941-3801
TWX: 910·576,2720
MISSOURI
tArrow Electronics
2380 Schuetz
St. Louis, MO 63141
Tel: (314) 567·6888
tHamilton/ Avnet Electronics
13743 Shorline Ct.
Earth City 63045
Tel: (314) 344·1200
TWX: 910·762·0684
NEW MEXICO
tAliiance Electronics Inc.
11030 Cochiti S.E.
Albuquerque 87123
Tel: (505) 292·3360
TWX: 910·989'1151
tHamilton/ Avnet Electronics
2524 Baylor Drive S.E.
Albuquerque 87119
Tel: (505) 765·1500
TWX: 910-989'0614
NEW YORK
tArrow Electronics
900 Broad Hollow Rd,
Farmingdale, NY 11735
Tet: (516) 694·6800
TWX: 510·224·6494
tArrow Electronics
3000 South Winton Road
Rochester 14623
Tel: (716) 275·0300
TWX: 510·253·4766
t Arrow Electronics
7705 Maltage Drive
Liverpool 13068
Tel: (315) 652·1000
TWX: 710·545,0230
Arrow Electronics
20 Oser Avenue
Hauppauge 11787
Tel: (516) 231·1000
TWX: 510·227·6623
tHamilton / Avnet Electronics
333 Metro Park
Rochester 14623
Tel: (716) 475·9130
TWX: 510·253·5470
tHamittonl Avnet Electronics
16 Corporate Circle
E. Syracuse 13057
Tel: (315) 437·2641
TWX: 710·541·1560
tHamilton I Avnet Electronics
5 Hub Drive
Melville, Long Island 11746
Tel: (516) 454·6000
TWX: 510·224·6166
Harvey Electronics
P.O. Box 1208
Binghampton 13902
Tel: (607) 748·8211
TWX: 510·252·0893
tMicrocomputer System Technical Demonstrator Centers
intJ
u.s. AND CANADIAN DISTRIBUTORS
3065 Bowers Avenue
Santa Clara, California 95051
August 1981
Tel: (408) 987·8080
TWX: 910·338·0026
TELEX: 34·6372
NEW YORK (Cont.)
OREGON
WASHINGTON
tHarvey Electronics
tAlmacfStroum Electronics
8022 S.W. Nimbus, Bldg. 7
Beaverton 97005
Tel: (503) 641-9070
TWX: 910-467-8743
tAlmacl Stroum Electronics
5811 Sixth Ave. South
Seallie 98108
Tel: (206) 763-2300
TWX: 910-444-2087
tHamilton! Avnet Electronics
14212 N.E. 21st Street
Bellevue 98005
Tel: (206) 453-5844
TWX: 910-443-2489
60 Crossways Park Wesl
Woodbury, Long Island 11797
Tel: (516) 921·8920
TWX: 510·221·2184
Harvey IRochester
840 Fairport Park
Fairport 14450
Tel: (716) 381·7070
TWX: 510·253-7001
Measurement Technology Salos Corp.
169 Northern Blvd
Grealneck 11021
Tel: (516) 482·3500
TWX: 510·223·0846
NORTH CAROLINA
Arrow Electronics
938 Burke Sireet
Winston' Salem 27102
Tel: (919) 725,8711
TWX: 510·931·3169
tHamillonl Avnel Electronics
2803 Industrial Drive
Raleigh 27609
Tel: (919) 829·8030
TWX: 510·928·1836
Pioneer /Carolina
106 Industrial Ave.
Greensboro 27406
Tel: (919) 273-4441
TWX: 510-925-1114
OHIO
Arrow Electronics
10 Knolkrest Dr.
Reading, OH 45237
Tel: (513) 761-5432
TWX: 810-461-2670
Arrow Electronics
7620 McEwen Road
Centerville 45459
Tel: (513) 435-5583
TWX: 810-459'1611
tHamillonl Avnet Electronics
6024 S.W. Jean Rd.
Bldg. C, Suite 10
Lake Oswego 97034
Tel: (503) 635-7848
TWX: 910-455-8179
PENNSYLVANIA
Arrow Electronics
650 Seco Rd.
Monroeville, PA 15146
Tel: (412) 856-7000
tArrow Electronics
650 Seco Rd.
Monroeville 15148
Tel: (412) 856-7000
Pioneer fPittsburgh
259 Kappa Drive
Pittsburgh 15238
Tel: (412) 782-2300
TWX: 710-795-3122
Pioneer/Delaware Valley
261 Gibralter Road
Horsham 19044
Tel: (215) 674-4000
TWX: 510·665-6778
TEXAS
Arrow Electronics
13715 Gsms Road
Dallas 75234
Tel: (214) 386-7500
TWX: 910-660-5377
Arrow Electronics
6238 Cochran Ad.
Solon 44139
Tel: (216) 248·3990
TWX: 810'427-9409
Arrow ElectroniCS, Inc.
10700 Corporate Drive, Suite 100
Stafford 77477
Tel: (713) 491-4100
TWX: 910·880-4439
Component SpeCialties, Inc.
8222 Jamestown Drive
Suite 115
Austin 78756
Tel: (512) 837-8922
TWX: 910-874-1320
tHamiltonf Avnet Electronics
954 Senate Drive
Dayton 45459
Tel: (513) 433-0610
TWX: 910-450-2531
tCcmponent Speciallies, Inc.
10907 Shady Trail, Suite 101
Dallas 75220
Tel: (214) 357-6511
TWX: 910-861-4999
tHamiltonf Avnet Electronics
4588 Emery Industrial Parkway
Warrensl/ille Heights 44128
Tel: (216) 831-3500
TWX: 810-427-9452
tPioneerfDayton
4433 Interpoint BII/d.
Daylon 45424
Tel: (513) 236-9900
TWX: 810'459-1622
tComponent Speciallies, Inc.
8181 Commerce Park Drive, Suite 700
Houston 77036
Tel: (713) 771-7237
TWX: 910-881-2422
Hamilton! Avnet Electronics
10508A Boyer Blvd.
Austin 78757
Tel: (512) 837-8911
TWX: 910-874-1319
tPioneer f Cleveland
4800 E. 131s1 Street
Cleveland 44105
Tel: (216) 587·3600
TWX: 810·422-2211
tHamillonl Avnet Electronics
2111 W. Walnut Hilt lane
Iving 75062
Tel: (214) 659-4100
TWX: 910-860-5929
tHamillonl Avnet Electronics
3939 Ann Arbor Drive
Houston 77063
Tel: (713) 780-1771
TWX: 910-881-5523
OKLAHOMA
tComponenls Specialties, Inc.
7920 E. 401h Street
Tulsa 74145
Tel: (918) 664·2820
TWX: 910-845-2215
ONTARIO
tHamiltonl Avnet Eleclronics
6845 Rexwood Roed, Units G & H
Missies8uga L4V lM5
Tel: (416) 671-4732
TWX: 610'492-8867
tHamiltonl Avnet Electronics
1735 Courtwood Cresent
Ottawa K2C 3J2
Tel: (613) 226-1700
TWX: 053-4971
tWyle Distribution Group
1750 132nd Avenue N.E.
Bellevue 96005
Tel: (208) 453-8300
TWX: 910-443-2526
tL.A. Varah, Ltd.
505 Kenora Avenue
Hamilton L8E 3P2
Tel: (416) 561-9311
TWX: 061-8349
WISCONSIN
tArrow Electronics
430 W. Rausson Avenue
Oakcreek 53154
Tel: (414) 764-6600
TWX: 910-262-1193
tZentronics
141 Catherine Street
Ottawa K2P lC3
Tel: (613) 238-6411
TWX: 053-3636
tHamilton! Avnet Electronics
2975 Moorland Road
New Berlin 53151
Tel: (414) 784-4510
TWX: 910-262-1182
CANADA
tZentronics
6 Kilbury CI.
Brampton, Ontario
Toronto, l6T 3T4
Tel: (416) 451-9600
Telex: 06-976-78
Zentronics
564 f 10 Weber St., N.
Walerloo, NAL 5C6
Tel: (519) 884-5700
ALBERTA
tL.A. Varah Ltd.
4742 14th Street N.E.
Calgary T20 617
Tel: (403) 230-1235
TWX: 038-258-97
QUEBEC
Zentronics
9224 27th Avenue
Edmonton T6N lB2
Tel: (403) 463·3014
Telex: 03742841
Zentronics
3651 21st N.E.
Calgary T2E 6T5
Tel: (403) 230- 1422
Zentronics
50tO Rue Pare Street
Monlreel H4P 1P3
Tel: (514) 735-5361
TWX: 05-827-535
tHamillonl Avnet Electronics
2670 Sabourin Streel
SI. laurent H4S 1M2
Tel: (514) 331·6643
TWX: 610-421·3731
BRITISH COLUMBIA
tL.A. Varah Ltd.
2077 Albarta Street
Vancouver V5Y lC4
Tel: (604) 873-3211
TWX: 610-929-1068
Zentronics
550 Cambie SI.
Vancouver V6B 2N7
Tel: (604) 688-2533
TWX: 04-5071-89
MANITOBA
L.A. Varah
1-1632 King Edward Street
Winnipeg R2R ONI
Tel: (204) 633·6190
TWX: 07-55-365
Zentronics
590 Berry 51.
Winnipeg R3H 051
Tel: (204) 775-8661
NOVA SCOTtA
Zentronics
30 Simmonds Dr., Unit B
Dartmouth, B3B lR3
UTAH
tHamillonf Avnet Electronics
1585 West 2100 South
Salt Lake City 84119
Tel: (801) 972-2800
TWX: 910-925·4018
tMicrocomputer System Technical Demonstrator Centere
inter
u.s. AND CANADIAN SERVICE OFFICES
3065 Bowers Avenue
Santa Clara, Calilornia 95051
Tel: (408) 987·8080
TWX: 910·338·0026
TELEX: 34·6372
CALIFORNIA
Intel Corp.
1601 Old Bayahora Hwy.
Suite 345
Burlingame 94010
Tel: (415) 692·4762
TWX: 910·375·3310
Inlel Corp.
2000 E. 4th Street
Suite 110
Santa Ana 92705
Tel: (714) 835·2870
TWX: 910-595'2475
Intel Corp.
7670 Opportunity Road
San Diego 92111
Tel: (71.) 268·3563
Inlel Corp.
5530 N. Corbin Ave.
Suite 120
Tarzana 91358
Tel: (213) 708·0333
COLORADO
Inlel Corp.
850 South Cherry
Suite 720
Denver 80222
Tel: (303) 321·8086
TWX: 910·931·2289
AU9ust 1981
MASSACHUSETTS
Intel Corp.
27 Industrial Avenue
Chelmsford 01824
Tel: (617) 256·1800
TWX: 710·343-6333
MICHIGAN
Intel Corp.
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313) 353-0920
TWX: 810-244-4915
MINNESOTA
Intel Corp.
7401 Metro Blvd.
SLlile 355
Edina 55435
Tel: (612) 835-6722
TWX: 910-576-2867
MISSOURI
Intel Corp.
502 Earth City Plaza
Suite 121
Earth City 63045
Tel: (314) 291-1990
NEW JERSEY
CONNECTICUT
Inlel Corp.
36 Padanaram Rd.
Danbury, CT 06810
Tel: (203) 792-8366
Intel Corp.
2460 Lemoine Avenue
1st Floor
Ft. Lee 07024
Tel: (201) 947·6287
TWX: 710·991-6593
FLORIDA
Inlel Corp.
1500 N. W. 62nd Street
Suite 104
Ft. Lauderdale 33309
Tel: (305) 771-0600
TWX: 510·956·9407
Intel Corp.
2255 Lyell Avenue
Rochester, NY 14606
Tel: (718) 254·6120
Inlel Corp.
500 N. Maitland Ave.
SLlile 205
Maitland, FL 32751
Tel: (305) 628·2393
TWX: 810·853·9219
Inlel Corp.
5151 Adanson SI.
Orlando 32804
Tel: (305) 628·2393
GEORGIA
Inlel Corp.
3300 Holcomb Bridge Rd. #225
Norcross, GA 30092
Tel: (404) 449,0541
ILLINOIS
Inlel Corp.
2550 Golf Road
Suile 815
Rolling Meadows 80008
Tel: (312) 981-7230
TWX: 910·253-1825
KANSAS
Inlel Corp.
9393 W. 110lh Street
Suile 265
Overland Park 66210
Tel: (9t3) 842-8080
MARYLAND
Inlel Corp.
7257 Parkway Drive
Hanover 21078
Tel: (301) 796·7500
TWX: 710-862'1944
NEW YORK
NORTH CAROLINA
Intel Corp.
2306 W. Meadowview Rd.
Suite 206
Greensboro, NC 27407
Tel: (919) 294-1541
OHIO
Intel Corp.
Chagrin·Brainard Bldg. Suite 300
28001 Chagrin Blvd.
Cleveland 44122
Tel: (216) 464·2736
TWX: 810-427·9298
Intel Corp.
6500 Poe Avenue
Dayton 45414
Tel: (513) 890-5350
TWX: 810·450-2528
OREGON
Intel Corp.
10700 S.W. Beaverton-Hillsdale Hwy.
SLlite 22
Beaverton 97005
Tel: (503) 641·8086
TWX: 910·467·8741
PENNSYLVANIA
Inlel Corp.
500 Pennsylvania Avenue
Fort Washington 19034
Tel: (215) 641-1000
TWX: 510·661,2077
Intel Corp.
201 Penn Center Blvd.
Suite 301 W.
PittsbLlrgh, PA 15235
Tel: (412) 823-4970
TEXAS
Intel Corp.
313 E. Anderson Lane
SLlite 314
Austin 78752
Tel: (512) 454·8477
TWX: 910·874·1347
Intel Corp.
2925 L.B.J. Freeway
Suite 175
. Dallas 75234
Tel: (214) 241-2820
TWX: 910·860-5817
Intel Corp.
6420 Richmond AvenLle
Suite 280
Houston 77057
Tel: (713) 784-1300
TWX: 910-881-2490
VIRGINIA
Intel Corp.
7700 Leesburg Pike
Suite 412
Falls Church 22043
Tel: (703) 734-9707
TWX: 710·931-0625
WASHINGTON
Intel Corp.
1603 116th Ave. N.E.
Suite 114
BellevLle 98005
Tel: (206) 232-7823
TWX: 910-443-3002
WISCONSIN
Inlel Corp.
150 S. SLlnnyslope Road
Suite 148
Brookfield 53005
Tel: (414) 784-9060
CANADA
Intel Corp.
50 Galaxy Blvd.
Unit 12
Raxdale. Ontario
M9W4Y5
Tel: (416) 675·2105
Telex: 069·89278
Intel Corp.
39 Bells Corners
Ottawa, Ontario
K2H 8R2
Tel: (613) 829·9714
Telex: 053·4115
inter
In'tel Corporation
30,65 Bowers Awnue
Sahta Clara, CA 95051
In,tel Corporation S.A.
Pare Seny
Rue du ~1oulin aPapier 51
B6ite 1
B~1160 Brussels
B~lgium
ln~el
Japan K.K.
5-6 Tokodai Toyosato-maehi
Tsukuba-gun, lbaraki-ken 300-26
Japan
Prtnted In U.SA/C-258n81 /45K/RRD
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