1982_AMD_Bipolar_MOS_Memories_Data_Book 1982 AMD Bipolar MOS Memories Data Book

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11
Advanced Micro Devices

Bipolar/MOS Memories
Data Book

The International Standard of Qt ]aJj!y
guarantees these electrical AQLs on all
parameters over the opern.t.in2 temperahtre ICll¥!e: 0.1% on MOS RAMS & ROMs;
0.2% on13i Iar
.c & Interface; 0.3%
on Linear,
gic&othermemortes.

© 1982 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products without
notice in order to improve design or performance characteristics. The company
assumes no responsibility for the use of any circuits described herein.
901 Thompson Place, P.O. Box 453, Sunnyvale, California 94086
(408) 732-2400 TWX: 910-339-9280 TELEX: 34-6306
Printed in U.S.A. 10/82 BPM-2100

II

Index Section
Numerical Device Index ...................................................................... 1-1
Functional Index and Selection Guide .......................................................... 1-5
Industry Cross Reference ..................................................................... 1-13
Application Note Testing High-Performance Bipolar Memory . ................................. 1-19

NUMERICAL DEVICE INDEX
Am100415
Am100415A
Am100470
Am100470A
Am100470SA
Am 100474
Am 100474A
Am 100474SA
Am10415
Am10415A
Am10415SA
Am10470
Am 10470A
Am 10470SA
Am 10474
Am10474A
Am 10474SA
Am1702A
Am2101
Am2111
Am2147
Am2148
Am2149
Am21l41
Am2708
Am27128
Am2716
Am2732
Am2732A
Am2764
Am27lS00
Am27lS00A
Am27lS00-1
Am27lS00-1 A
Am27lS01
Am27lS01A
Am27lS01-1
Am27lS01-1A
Am27lS02
Am27lS03
Am27lS06
Am27lS07
Am27lS18
Am27lS184
Am27lS185
Am27lS19
Am27PS181
Am27PS181A
Am27PS185
Am27PS191
Am27PS191A
Am27PS281

Eel 1024 x 1 IMOXTM II Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-69
Eel 1024 x 1 IMOX II Bipolar RAM ....................................... 3-691]
Eel 4096 x 1 IMOX Bipolar RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-83
Eel 4096 x 1 IMOX Bipolar RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-83
Eel 4096 x 1 IMOX Bipolar RAM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-83
Eel 1024 x 4 IMOX Bipolar RAM ......................................... 3-75
Eel 1024 x 4 IMOX Bipolar RAM ............ , ................... , ........ 3-75
Eel 1024 x 4 IMOX Bipolar RAM ......................................... 3-75
Eel 1024 x 1 IMOX Bipolar RAM ....................................... " 3-62
Eel 1024 x 1 IMOX Bipolar RAM. . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . .. 3-62
Eel 1024 x 1 IMOX Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-62
Eel 4096 x 1 IMOX Bipolar RAM ......................................... 3-76
Eel 4096 x 1 IMOX Bipolar RAM ......................................... 3-76
Eel 4096 x 1 IMOX Bipolar RAM ............ , ........................ " .. 3-76
Eel 1024 x 4 IMOX Bipolar RAM ......................................... 3-74
Eel 1024 x 4 IMOX Bipolar RAM ......................................... 3-74
Eel 1024 x 4 IMOX Bipolar RAM ......................................... 3-74
256-Word by 8-Bit Programmable Read Only Memory ........ , . . ..... . .. .. .. 6-1
256 x 4 Static R/W Random Access Memories ............................. 4-1
256 x 4 Static R/W Random Access Memories ............................. 4-7
4096 x 1 Static R/W Random Access Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-39
1024 x 4 Static R/W Random Access Memory .............................. 4-45
1024 x 4 Static R/W Random Access Memory .............................. 4-45
4096 x 1 Static R/W Random Access Memory .............................. 4-25
1024 x 8 Erasable Read Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
16,384 x 8-Bit UV Erasable PROM .................. , ..................... 6-27
2048 x 8-Bit UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-11
4096 x 8-Bit UV Erasable PROM.. . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 6-16
4096 x 8-Bit UV Erasable PROM ......................................... 6-21
8192 x 8-Bit UV Erasable PROM ......................................... 6-22
low-Power Schottky 256-Bit Bipolar RAM.. .. . . . . . .. . . . . . . . .. . . . . . . . . . . . .. 3-36
low-Power Schottky 256-Bit Bipolar RAM ................................. 3-36
low-Power Schottky (Noninverting) 256-Bit Bipolar RAM. . . . . .. . . . . . . . . . . . .. 3-42
low-Power Schottky (Noninverting) 256-Bit Bipolar RAM. . . . . .. . . . . . . . . . . . .. 3-42
low-Power Schottky 256-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-36
low-Power Schottky 256-Bit Bipolar RAM ................................. 3-36
low-Power Schottky (Noninverting) 256-Bit Bipolar RAM. . . . . .. . . . . . . . . . . . .. 3-42
low-Power Schottky (Noninverting) 256-Bit Bipolar RAM. . . . . .. . . . . . . .. . . . .. 3-42
low-Power Schottky 64-Bit Bipolar RAM .................................. 3-7
low-Power Schottky 64-Bit Bipolar RAM .................................. 3-7
low-Power, Noninverting 64-Bit Bipolar RAM. . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-32
low-Power, Noninverting 64-Bit Bipolar RAM .............................. 3-32
low-Power Schottky 256-Bit Generic Series Bipolar PROM. . . .. . . . . . . . . . . . . . 2-8
8192-Bit Generic Series Bipolar IMOX PROM .............................. 2-92
8192-Bit Generic Series Bipolar IMOX PROM .............................. 2-92
low-Power Schottky 256-Bit Generic Series Bipolar PROM. . . .. . . . . . . . . . . . . . 2-8
8,192-Bit Generic Series IMOX Bipolar PROM .............................. 2-80
8,192-Bit Generic Series IMOX Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-80
8192-Bit Generic Series Bipolar IMOX PROM .............................. 2-97
16,384-Bit Generic Series IMOX Bipolar PROM ............................. 2-109
16,384-Bit Generic Series IMOX Bipolar PROM ............................. 2-109
8,192-Bit Generic Series IMOX Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-80

IMOX is a trademark of Advanced Micro Devices.
1-1

NUMERICAL DEVICE INDEX (Cont.)
Am27PS281A
Am27PS291
Am27PS291A
Am27PS41
Am27S02
Am27S02A
Am27S03
Am27S03A
Am27S06
Am27S06A
Am27S07
Am27S07A
Am27S12
Am27S12A
Am27S13
Am27S13A
Am27S15
Am27S18
Am27S18A
Am27S180
Am27S180A
Am27S181
Am27S181A
Am27S184
Am27S184A
Am27S185
Am27S185A
Am27S19
Am27S19A
Am27S190
Am27S190A
Am27S191
Am27S191A
Am27S20
Am27S20A
Am27S21
Am27S21A
Am27S25
Am27S25A
Am27S27
Am27S28
Am27S28A
Am27S280
Am27S280A
Am27S281
Am27S281A
Am27S29
Am27S29A
Am27S290
Am27S290A
Am27S291
Am27S291A
Am27S30
Am27S30A

8,192-Bit Generic Series IMOX Bipolar PROM ..... " ..................... '" 2-80
16,384-Bit Generic Series IMOX Bipolar PROM .............................. 2-109
16,384-Bit Generic Series IMOX Bipolar PROM .............................. 2-109
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-131
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Noninverting Schottky 64-Bit Bipolar RAM .................................. 3-26
Noninverting Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 3-26
Noninverting Schottky 64-Bit Bipolar RAM.. .. . . .... . . . .. . . ..... .. . . . . . . . . .. 3-26
Noninverting Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. 3-26
2048-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
2048-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
2048-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
2048-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-29
256-Bit Generic Series Bipolar PROM. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
256-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
1024 x 8-Bit Generic Series Bipolar IMOX PROM. " ........................ 2-73
1024 x 8-Bit Generic Series Bipolar IMOX PROM ............................ 2-73
1024 x 8-Bit Generic Series Bipolar IMOX PROM ............................ 2-73
1024 x 8-Bit Generic Series Bipolar.IMOX PROM ............................ 2-73
8192-Bit Generic Series Bipolar IMOX PROM ...................... " ....... 2-87
8192-Bit Generic Series Bipolar IMOX PROM ............................... 2-87
8192-Bit Generic Series Bipolar IMOX PROM ...................... " ....... 2-87
8192-Bit Generic Series Bipolar IMOX PROM ............................... 2-87
256-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
256-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-102
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-15
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-15
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 2-15
1024-Bit Generic Series Bipolar PROM.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-15
4K-Bit (512 x 8) Generic Series Bipolar IMOX Registered PROM. . . . . . . . . . . . . .. 2-34
4K-Bit (512 x 8) Generic Series Bipolar IMOX Registered PROM. . . . . . . . . . . . . .. 2-34
4096-Bit Generic Series Bipolar Registered PROM. . . . . . . . . . . . . . . . . . . . . . . . . .. 2-41
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-47
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-47
1024 x 8-Bit Generic Series Bipolar IMOX PROM ............................ 2-73
1024 x 8-Bit Generic Series Bipolar IMOX PROM ............................ 2-73
1024 x 8-Bit Generic Series Bipolar IMOX PROM ............................ 2-73
1024 x 8-Bit Generic Series Bipolar IMOX PROM ............................ 2-73
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-47
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-47
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .................... " ........ 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .................... " ........ 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-102
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. 2-52
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
1-2

NUMERICAL DEVICE INDEX (Cont.)
Am27S31
Am27S31A
Am27S32
Am27S32A
Am27S33
Am27S33A
Am27S35
Am27S35A
Am27S37
Am27S37A
Am27S40
Am27S40A
Am27S41
Am27S41A
Am27S43
Am27S43A
Am27S45
Am27S45A
Am27S47
Am27S47A
Am27S65
Am27S75
Am27S85
Am29700
Am29701
Am29702
Am29703
Am29720
Am29721
Am29750A
Am29751A
Am29760A
Am29761A
Am29770
Am29771
Am29775
Am3101
Am3101A
Am3101-1
Am31L01
Am31L01A
Am5489
Am5489-1
Am54S189
Am54S289
Am7489
Am7489-1
Am74S189
Am74S289
8316E
Am9016

4096-Bit Generic Series Bipolar PROM ...................... , . . . . . . . . . . . . .. 2-52
4096-Bit Generic Series Bipolar PROM ..................................... 2-521]
4096-Bit Generic Series Bipolar PROM ...................... , . . . . . . . . . . . . .. 2-57
4096-Bit Generic Series Bipolar PROM ...................... , . . . . . . . . . . . . .. 2-57
4096-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-57
4096-Bit Generic Series Bipolar PROM .................... " .. . . . . . . . . . . . . .. 2-57
8K-Bit (1024 x 8) Generic Series Bipolar IMOX Registered PROM. . . . . . . . . . . . .. 2-64
8K-Bit (1024 x 8) Generic Series Bipolar IMOX Registered PROM. . . . . . . . . . . . .. 2-64
8K-Bit (1024 x 8) Generic Series Bipolar IMOX Registered PROM. . . . . . . . . . . . .. 2-64
8K·Bit (1024 x 8) Generic Series Bipolar IMOX Registered PROM. . . . . . . . . . . . .. 2-64
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-125
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-125
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-125
16,384-Bit Generic Series Bipolar IMOX PROM .............................. 2-125
32,768-Bit Generic Series Bipolar IMOX PROM .............................. 2-137
32,768-Bit Generic Series Bipolar IMOX PROM .............................. 2-137
16K-Bit (2048 x 8) Generic Series Bipolar IMOX Registered PROM ............. 2-116
16K-Bit (2048 x 8) Generic Series Bipolar IMOX Registered PROM ............. 2-116
16K-Bit (2048 x 8) Generic Series Bipolar IMOX Registered PROM ............. 2-116
16K-Bit (2048 x 8) Generic Series Bipolar IMOX Registered PROM ............. 2-116
Generic Series 4-Wide Bipolar IMOX Registered PROMs with
SSR Diagnostics Capability .,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-62
Generic Series 4-Wide Bipolar IMOX Registered PROMs with
SSR Diagnostics Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-62
Generic Series 4-Wide Bipolar IMOX Registered PROMs with
SSR Diagnostics Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-62
Noninverting Schottky 64-Bit RAM. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-31
Noninverting Schottky 64-Bit RAM. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-31
Schottky 64-Bit RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 3-6
Schottky 64-Bit RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 3-6
Low- Power Schottky 256- Bit Random Access Memories. . . . . . . . . . . . . . . . . . . . .. 3-41
Low-Power Schottky 256-Bit Random Access Memories. . . . . . . .. . . . . . . . . . . . .. 3-41
256-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . 2-7
256- Bit Generic Series Bipolar PROM ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 2-21
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . .. 2-21
2048-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . .. 2-28
2048-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 2-28
4096-Bit Generic Series Bipolar PROM with Register. .. . . . . .. . .. . . . . . . . . . . . .. 2-46
Schottky 64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
Schottky 64-Bit Bipolar RAM ............... " " ....... " . . . . . . . . . . . . . . . . . . . .. 3-16
Schottky 64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-21
64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-21
Schottky 64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
Schottky 64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
Schottky 64-Bit Bipolar RAM. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-16
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-16
Schottky 64-Bit Write Transparent Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
Schottky 64-Bit Write Transparent Bipolar RAM. . . . . . .. . . . . .. . .. . . . . . . . . . . . .. 3-11
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-16
Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 3-16
2048 x 8 Read Only Memory .............................................. 5-1
16,384 x 1 Dynamic R/W Random Access Memory Advanced MaS/LSI ......... 4-59
1-3

NUMERICAL DEVICE INDEX (Cant.)
Am9044
Am9101
Am9111
Am9112
Am9114
Am9122
Am9124
Am9128
Am9167
Am9168
Am9169
Am91L01
Am91L11
Am91L12
Am91L22
Am92128
Am9218
Am92256
Am9232
Am9233
Am9244
Am9264
Am9265
Am93412
Am93412A
Am93415
Am93415A
Am93422
Am93422A
Am93425
Am93425A
Am93L412
Am93L412A
Am93L422
Am93L422A
Am9708
Am9716

4096 x 1 Static R/W Random Access Memory .............................. . 4-31
256 x 4 Static R/W Random Access Memories .............................. . 4-1
256 x 4 Static R/W Random Access Memories .............................. . 4-7
256 x 4 Static R/W Random Access Memories .............................. . 4-13
1024 x 4 Static R/W Random Access Memory .............................. . 4-35
256 x 4 Static R/W RAMs ................................................ . 4-19
1024 x 4 Static R/W Random Access Memory .............................. . 4-35
2048 x 8 Static R/W Random Access Memory .............................. . 4-51
16,384 x 1 Static R/W Random Access Memory ............................. . 4-57
4096 x 4 Static R/W Random Access Memory .............................. . 4-58
4096 x 4 Static R/W Random Access Memory .............................. . 4-58
256 x 4 Static R/W Random Access Memories .............................. . 4-1
256 x 4 Static R/W Random Access Memories .............................. . 4-7
256 x 4 Static R/W Random Access Memories .............................. . 4-13
256 x 4 Static R/W RAMs ................................................ . 4-19
128K (16,384 x 8) Read Only Memory ...................................... . 5-15
2048 x 8 Read Only Memory ................ ; ............................ . 5-1
256K (32,768 x 8) Read Only Memory ................... , .............. " .. 5-18
4096 x 8 Read Only Memory ............................................. . 5-4
4096 x 8 Read Only Memory ............................................. . 5-4
4096 x 1 Static R/W Random Access Memory .............................. . 4-31
64K (8192 x 8) Read Only Memory ........................................ . 5-8
64K (8192 x 8) Read Only Memory ......................... " ............. . 5-12
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-47
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-47
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-57
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-57
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-47
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-47
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-57
TIL 1024-Bit Bipolar IMOX RAM ......................................... . 3-57
Low-Power TIL 1024-Bit Bipolar IMOX RAM ............................... . 3-52
Low-Power TIL 1024-Bit Bipolar IMOX RAM ............................... . 3-52
Low-Power TTL 1024-Bit Bipolar IMOX RAM ............................... . 3-52
Low-Power TIL 1024-Bit Bipolar IMOX RAM ............................... . 3-52
1024 x 8 Erasable Read Only Memory .......... '" ........ '" ............. . 6-7
2048 x 8-Bit UV Erasable PROM ........................... " ............. . 6-11
Testing High-Performance Bipolar Memory .............. " . . . . . . . . . . . . .. 1-19
Technical Report ...........................................' ............ 2-142
Guide to the Analysis of Programming Problems ........ '" .............. 2-151
PROM Programming Equipment Guide .................................. 2-154

1-4

Bipolar PROM
Functional Index and Selection Guide
Access Time
Icc
COM'L/MIL COM'L/MIL
Organization
Max
Max
Output

Part
Number
Am27L818 1

32 x 8

50/65

1

32 x 8

Am27L819

Number
of Pins Packages

Comments

Page
No.

80/80

OC

16

D, P, F, L

50/65

80/80

38

16

D, P, F, L

2-8

D, P, F, L

2-1

Low power

2-8

Am27818

32 x 8

40/50

115/115

OC

16

Am27818A

32 x 8

25/35

115/115

OC

16

D, P, F, L

2-1

Am27819

32 x 8

40/50

115/115

38

16

D, P, F, L

2-1

Am27819A

32 x 8

25/35

115/115

38

16

D, P, F, L

2-1

Am27820

256 x 4

45/60

130/130

OC

16

D, P, F, L

2-15

D, P, F, L

2-15

Am27820A

256 x 4

30/40

130/130

OC

16

Am27821

256 x 4

45/60

130/130

38

16

D, P, F, L

2-15

Am27821A

256 x 4

30/40

130/130

38

16

D, P, F, L

2-15

Am27812

512 x 4

50/60

130/130

OC

16

D, P, F, L

2-22

Am27812A

512 x 4

30/40

130/130

OC

16

D, P, F, L

2-22

Am27813

512 x 4

50/60

130/130

38

16

D, P, F, L

2-22

Am27813A

512 x 4

30/40

130/130

38

16

D, P, F, L

2-22

Am27815

512 x 8

60/90

175/185

38

24

D, P, F,L

2-29

Am27825

512 x 8

N.A.2/N.A.2

185/185

38

24

D, P, F, L

Output registers,
THINDIP Pkg 3

2-34

Am27825A

512 x 8

N.A. 4/N.A. 4

185/185

38

24

D, P, F, L

Output registers,
THINDIP Pkg 3

2-34

Am27827

512 x 8

N.A.2/N.A.2

185/185

38

22

D, P, L

Output registers

2-41

Am27828

512 x 8

55/70

160/160

OC

20

D, P, L

2-47

Am27828A

512 x 8

35/45

160/160

OC

20

D, P, L

2-47

Am27829

512 x 8

55/70

160/160

38

20

D, P, L

2-47

Am27829A

512 x 8

35/45

160/160

38

20

D, P, L

2-47

Am27830

512 x 8

55/70

175/175

OC

24

D, P, F, L

2-52

Am27830A

512 x 8

35/45

175/175

OC

24

D, P, F, L

2-52

Am27831

512 x 8

55/70

175/175

38

24

D, P, F, L

2-52

Am27831A

512 x 8

35/45

175/175

38

24

D, P, F, L

2-52

D, P, F, L

2-57

Am27832

1024 x 4

55/70

140/145

OC

18

Am27832A

1024 x 4

35/45

140/145

OC

18

D, P, F, L Ultra fast

2-57

Am27833

1024 x 4

55/70

140/145

38

18

D, P, F, L

2-57

Am27833A

1024 x 4

35/45

140/145

38

18

D, P, F, L Ultra fast

2-57
2-64

Am27835

1024 x 8

N.A.2/N.A.2

185

38

24

Output registers,
D, P, F, L asynchronous initialize,
THINDIP Pkg 3

Am27835A

1024 x 8

N.A.4/N.A.4

185

38

24

Ultra fast, output
D, P, F, L registers, asynchronous
initialize, THINDIP Pkg 3

2-64

Am27837

1024 x 8

N.A.2/N.A.2

185

38

24

Output registers,
D, P, F, L synchronous initialize,
THINDIP Pkg 3

2-64

1-5

II

BIPOLAR PROM (Cont.)
Part
Number

Access Time
COM'LjMIL
Organization
Max

ICC

COM'LjMIL
Max

Output

Number
of Pins Packages

N.A.4/N.A.4

185

38

24

Ultra fast, output
D, P, F, L registers, synchronous
initialize, THINDIP Pkg 3

2-64

Page
No.

Comments

Am27837A

1024 x 8

Am278180

1024 x 8

60/80

185/185

D, P, F, L

2-73

1024 x 8

35/50

185/185

OC
DC

24

Am278180A

24

D, P, F, L Ultra fast

2-73

Am278181

1024 x 8

60/80

185/185

38

24

D, P, F, L

2-73

Am278181A

1024 x 8

35/50

185/185

38

24

D, P, F, L Ultra fast

2-73

Am27P8181

1024 x 8

38

24

D, P, F, L Power switched

2-80

Am27P8181A

1024 x 8

2-80

Am278280

1024 x 8

38

24

D, P, F, L Power switched

24

D, P, F, L THINDIP Pkg 3

24

D, P, F, L Ultra fast, THINDIP Pkg

24

D, P, F, L THIN DIP Pkg 3

Am278280A

1024 x 8

35/50

185/185

DC
DC

Am278281

1024 x 8

60/80

185/185

38

Am278281A

1024 x 8

60/80

35/50

185/185

185/185

38

24

D, P, F, L Ultra fast, THINDIP Pkg

2-73
3

2-73
2-73

3

2-73

Am27P8281

1024 x 8

38

24

Power switched,
D, P, F, L
THINDIP Pkg 3

Am27P8281A

1024 x 8

38

24

D, P, F, L

Am278184

2048 x 4

50/55

150/150

18

D, P, F, L

2-87

Am278184A

2048 x 4

35/45

150/150

DC
DC

18

D, P, F, L Ultra fast

2-87

Am278185

2048 x 4

50/55

150/150

38

18

D, P, F, L

2-87

Am278185A

2048 x 4

35/45

150/150

38

18

D, P, F, L Ultra fast

2-87
2-92

Ultra fast, power switched,
THINDIP Pkg 3

2-80
2-80

Am27L8184

2048 x 4

60/65

120/125

DC

18

D, P, F, L Low power

Am27L8185

2048

x4

60/65

120/125

38

18

D, P, F, L Low power

2-92

Am27P8185

2048 x 4

60/65

150/755

38

18

D, P, F, L Power switched

2-97

Am278190

2048 x 8

50/65

185/185

D, P, F, L

2-102

2048 x 8

35/50

185/185

DC
DC

24

Am278190A

24

D, P, F, L Ultra fast

2-102

Am278191

2048 x 8

50/65

185/185

38

24

D, P, F, L

2-102
2-102

Am278191A

2048 x 8

35/50

185/185

38

24

D, P, F, L Ultra fast

Am27P8191

2048 x 8

65/75

185/80 5

38

24

D, P, F, L Power switched

2-109

Am27P8191A

2048 x 8

50/65

185/80 5

38

24

D, P, F, L Ultra fast, power switched

2-109

Am278290

2048 x 8

50/65

185/185

24

D, P, F, L THINDIP Pkg 3

2-102

Am278290A

2048 x 8

35/50

185/185

DC
DC

24

D, P, F, L Ultra fast, THIN DIP Pkg 3

2-102

3

Am278291

2048 x 8

50/65

185/185

38

24

D, P, F,L THINDIP Pkg

Am278291A

2048 x 8

35/50

185/185

38

24

D, P, F, L Ultra fast, THINDIP Pkg 3

2-102
2-109

2-102

Am27P8291

2048 x 8

65/75

185/805

38

24

Power switched,
D, P, F, L
THINDIP Pkg 3

Am27P8291A

2048 x 8

50/65

185/805

38

24

D, P, F, L

Am27840

4096 x 4

50/65

165/170

20

D, P, L

Am27840A

4096 x 4

35/50

165/170

DC
DC

20

D, P, L

Am27841

4096 x 4

50/65

165/170

38

20

D, P, L

Am27841A

4096 x 4

35/50

165/170

38

20

D, P, L

Ultra fast

2-125

50/65

170/85 5

38

20

D, P, L

Power switched

2-131

Am27P841

4096 x 4

1-6

Ultra fast, power switched,
THINDIP Pkg 3

2-109
2-125

Ultra fast

2-125
2-125

BIPOLAR PROM (Cont.)
Part
Number

Access Time
COM'L/MIL
Organization
Max

ICC

COM'L/MIL
Max

Output

Number
of Pins Packages

Comments

Page
No.

Am27843

4096

x8

N.A.

185

38

24

D, P, F, L

2-137

Am27843A

4096

x8

N.A.

185

38

24

D, P, F, L Ultra fast

2-137

Am27P843

4096

x8

N.A.

N.A.

38

24

D, P, F, L Power switched

Am27845

2048

x8

N.A.2

185/185

38

24

D, P, L

Output registers,
asynchronous initialize,
THINDIP Pkg 3

2-116

Am27845A

2048

x8

N.A.4

185/185

38

24

D, P,L

Ultra fast, output registers,
asynchronous initialize,
THINDIP Pkg 3

2-116

Am27847

2048

x8

N.A.2

185/185

38

24

D, P, L

Output registers,
synchronous initialize,
THINDIP Pkg 3

2-116

Am27847A

2048

x8

N.A.4

185/185

38

24

D, P, L

Ultra fast, output registers,
synchronous initialize,
THIN DIP Pkg 3

2-116

Notes: 1.
2.
3.
4.
5.

Replaces Am27LS08/09
Contains built-in pipeline registers: nominal address to clock setup time
300-millateral pin spacing.
Contains built-in pipeline registers: nominal address to clock setup time
IcC are power up and power down current limits respectively.

1-7

= 35ns (typ), clock to output = 20ns (typ).

= 25ns (typ), clock to output =

15ns (typ).

-

II

Bipolar Memory RAM
Functional Index and Selection Guide
BIPOLAR Eel RAM
Part
Number

Access Time
COML/MIL
Organization
Max

lEE
COML/MIL
Max

ECL
Series

Number
of Pins

Packages

Comments

Page No.

Am10415SA

1024 x 1

15/20

-150/-165

10K

16

D, P, F, L

3-62

Am10415A

1024 x 1

20/25

-150/-165

10K

16

D, P, F, L

3-62

I\m10415

1024

x1

35/40

-150/-165

10K

16

D, P, F, L

3-62

Am100415A

1024 x 1

15/-

-150/-

100K

16

D, P, F, L

3-69

Am100415

1024 x 1

20/-

-150/-

100K

16

D, P, F, L

3-69

Am10470SA

4096 x 1

15/20

-230/-255

10K

18

D, Fl, L

3-76

Am10470A

4096 x 1

25/30

-200/-220

10K

18

D, Fl, L

3-76

Am10470

4096 x 1

35/40

-200/-220

10K

18

D, Fl, L

3-76

Am100470SA

4096 x 1

15/-

-230/-

100K

18

D, Fl, L

3-83

Am100470A

4096 x 1

25/-

-195/-

100K

18

D, Fl, L

3-83

Am100470

4096 x 1

35/-

-195/-

100K

18

D, Fl, L

3-83

Am10474A

1024 x 4

15/20

-230/-255

10K

24

D, F, L

3-74

Am10474

1024 x 4

25/30

-230/-220

10K

24

D, F, L

3-74

Am100474A

1024 x 4

15/-

-230/-

100K

24

D, F, L

3-75

Am100474

1024 x 4

25/-

-200/-

100K

24

D, F, L

3-75

COML/MIL
Max

Number
of Pins

Packages

Output

Note: 1. For flat package consult factory.

BIPOLAR TTL RAM
Part
Number

Access Time
COML/MIL
Organization
Max

ICC
(Note 1)

Am27S02A

16 x 4

25/30

100/105

OC

16

D, P, F, L

Am27S03A

16 x 4

25/30

100/105

3S

16

D, P, F, L

Comments
Ultra Fast

Page No.
3-1
3-1

Am27S02

16 x 4

35/50

105/105

OC

16

D, P, F, L

3-1

Am27S03

16 x 4

35/50

125/125

3S

16

D, P, F, L

3-1

Am27LS02

16 x 4

55/65

35/38

OC

16

D, P, F, L

Am27LS03

16 x 4

55/65

35/38

3S

16

D, P, F, L

3-7

Am74/54S289

16 x 4

35/50

105/105

OC

16

D, P, F, L

3-16

Am74/54S189

16 x 4

35/50

125/125

3S

16

D, P, F, L

3-16

Am27S06A

16 x 4

25/30

100/105

OC

16

D, P, F, L

Am27S07A

16 x 4

25/30

100/105

3S

16

D, P, F, L

Am27S06

16 x 4

35/50

100/105

OC

16

D, P, F, L

Am27S07

16 x 4

35/50

100/105

3S

16

D, P, F, L

Am27LS06

16 x 4

55/65

35/38

OC

16

D, P, F, L

Am27LS07

16 x 4

55/65

35/38

3S

16

D, P, F, L

Am3101A

16 x 4

35/50

100/105

OC

16

D, P, F, L

Am3101-1

16 x 4

35/50

100/105

OC

16

D, P, F, L

Am3101

16 x 4

50/60

100/105

OC

16

D, P, F, L

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

1-8

Low Power

3-7

3-26
Noninverting
Outputs

3-26
3-26
3-26

Noninverting
Outputs,
Low Power

3-32
3-32
3-16

Write
Transparent 2

3-11
3-11

BIPOLAR TTL RAM (Cont.)
Part
Number

Access Time
COM'LjMIL
Organization
Max

ICC
COM'LjMIL
Max

Number
of Pins

Packages

Output

(Note 1)

Am31L01A

16 x 4

55/65

35/38

OC

16

D, P, F, L

Am31L01

16 x 4

80/90

35/38

OC

16

D,P, F, L

Am74/5489-1

16 x 4

35/50

100/105

OC

16

D, P, F, L

Am74/5489

16 x 4

50/60

100/105

OC

16

D, P, F, L

Am27LSOOA

256 x 1

35/45

115/115

3S

16

D,P, F, L

Am27LS01A

256 x 1

35/45

115/115

OC

16

D, P, F, L

Am27LSOO

256 x 1

45/55

70/70

3S

16

D,P, F, L

Am27LS01

256 x 1

45/55

70/70

OC

16

D, P, F, L

Am27LSOO-1A

256 x 1

35/45

115/115

3S

16

D, P, F, L

Am27LS01-1A

256 x 1

35/45

115/115

OC

16

D,P,F,L

Am27LSOO-1

256 x 1

45/55

70/70

3S

16

D, P, F, L

Comments
Low Power,
Write Transparent2
Write Transparent2
Ultra Fast
Fast, Low Power

Page No.
3-21
3-21
3-11
3-11
3-36
3-36
3-36
3-36
3-42

Noninverting Outputs

3-42
3-42

Am27LS01-1

256 x 1

45/55

70/70

OC

16

D, P, F, L

3-42

Am93415A

1024 x 1

30/40

155/170

OC

16

D, P, F, L

3-57

Am93425A

1024 x 1

30/40

155/170

3S

16

D, P, F, L

Am93415

1024 x 1

45/65

155/170

OC

16

D, P, F, L

3-57

Am93425

1024 x 1

45/65

155/170

3S

16

D, P, F, L

3-57

Am93412A

256 x 4

35/45

155/170

OC

223

D, P,F,L

Am93422A

256 x 4

35/45

155/170

3S

223

D, P, F, L

Am93412

256 x 4

45/60

155/170

OC

22 3

D, P, F, L

3-47

Am93422

256 x 4

45/60

155/170

3S

223

D, P, F, L

3-47

Am93L412A

256 x 4

45/55

80/90

OC

223

D, P, F, L

3-52

Am93L422A

256 x 4

45/55

80/90

3S

223

D, P, F, L

Am93L412

256 x 4

60/75

80/90

OC

223

D, P, F, L

Am93L422

256 x 4

60/75

80/90

3S

22 3

D, P, F, L

Notes: 1. D = Hermetic DIP, P = Molded DIP, F = Cerpak, L = Chip-PakTM.
2. Complement of data in is available on the outputs in the write mode when both CS and WE are low.
3. Cerpak (F) is 24 pin.

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

1-9

Ultra Fast

Ultra Fast

Low Power

3-57

3-47
3-47

3-52
3-52
3-52

II

MOS Memory
1K STATIC RAMs
Part
Number

Am9101A
Am91 L01A
Am9101B
Am91L01B
Am9101e
Am91L01C
Am9101D
Am9111A
Am91L11A
Am9111B
Am91L11B
Am9111e
Am91L11e
Am9111D
Am9112A
Am91L 12A
Am9112B
Am91L12B
Am9112e
Am91L12e
Am9112D
Am9122-25
Am9122-35
Am91L22-35
Am91L22-45
Am91L22-60

Organization

256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4
256x4

Functional Index and Selection Guide
Access
Time (ns)

Power Dissipation (mW)
Standby

Active

Pins

500
500
400
400
300

47
38
47
38
47

22
22
22
22
22

300

38

250
500
500
400
400
300
300
250
500
500
400
400
300
300
250
25
35
35
45
60

47
47
38
47
38
47
38
47
47
38
47
38
47
38
47

290
173
290
173
315
189
315
290
173
290
173
315
189
315
290
173
290
173
315
189
315
660
660
440
440
248

120
150
200
250
450
450
300
300
250
250
200
200
450
450
300
300
250
250
200
200
450
450
300
300
200
200
450
450
300
300

25
25
25
25

200
200
200
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250
350
250

18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18

-

22
22
18
18
18
18
18
18
18
16
16
16
16
16
16
16
22
22
22
22
22

Supply
Voltage (V)

Temp
Range

Package

Page
No.

5
5
5
5
5
5
5
5

e,M
e,M
e,M
e,M
e,M
e , ivi
e
e,M
e,M
e,M
e,M
e,M
e,M
e
e,M
e,M
e,M
e,M
e,M
e,M
e
e
e,M
e
e,M
e

D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P

4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-7
4-7
4-7
4-7
4-7
4-7
4-7
4-13
4-13
4-13
4-13
4-13
4-13
4-13
4-19
4-19
4-19
4-19
4-19

e
e
e
e
e,M
e,M
e,M
e,M
e,M
e,M
e
e
e,M
e,M
e,M
e,M
e,M
e,M
e
e
e,M
e,M
e,M
e,M
e,M
e
e,M
e,M
e,M
e,M

D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P
D,P,F
D,P,F
D,P,F
D,P,F
D,P
D,P
D,P,F
D,P,F
D,P,F
D,P,F

4-25
4-25
4-25
4-25
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-31
4-35
4-35
4-35
4-35
4-35
4-35
4-35
4-35
4-35
4-35

5
5
5
5
5
5
5

5
5
5
5
5
5
5
5
5
5
5

4K STATIC RAMs
Am21L41-12
Am21L41-15
Am21L41-20
Am21L41-25
Am9044B
Am90L44B
Am9044e
Am90L44e
Am9044D
Am90L44D
Am9044E
Am90L44E
Am9244B
Am92L44B
Am9244e
Am92L44e
Am9244D
Am92L44D
Am9244E
Am92L44E
Am9114B
Am91L14B
Am9114e
Am91L14e
Am9114E
Am91L14E
Am9124B
Am91L24B
Am9124e
Am91L24e

4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
4096 x 1
1024 x 4
1024 x 4
1024 x4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x 4
1024 x4
1024 x 4

150
100
150
100
150
100
150
100

150
100
150
100

1-10

5
5
5
5
5
5
5
5
5
5

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

4K STATIC RAMs (Cont.)
Part
Number

Organization

Am2147-35
Am2147-45
Am2147-55
Am2147-70
Am21l47-45
Am21l47-55
Am2148-55
Am2148-70
Am2149-55
Am2149-70

4096x 1
4096 x 1
4096 x 1
4096x 1
4096 x 1
4096 x 1
1024 x4
1024x4
1024 x4
1024 x4

Access
Time (ns)

35
45
55
70
45
55
55
70
55
70

Power Dissipation (mW)
Standby

Active

Pins

Supply
Voltage (V)

Temp.
Range

165
165
165
110
83
83
165
165

990
990
990
880
688
688
990
990
990
990

18
18
18
18
18
18
18
18
18
18

5
5
5
5
5
5
5
5
5
5

e
M
e,M
e,M
e
e
e,M
e,M
e,M
e,M

-

Package

Page
No.

O,l
O,l
O,l
O,l

4-39
4-39
4-39
4-39
4-39
4-39
4-45
4-45
4-45
4-45

Package

Page
No.

°

O;l
O,l
O,l

°°

16K STATIC RAMs
Part
Number

Organization

Access
Time (ns)

2048 x8
2048 x 8
2048 x8
2048x8
16384 x 1
16384 x 1
4096x4
4096x4

100
150
200
70
45
55
45
55

Am9128-10
Am9128-15
Am9128-20
Am9128-70*
Am9167-45*
Am9167-55*
Am9168-45*
Am9168-55*

Power Dissipation (mW)
Standby

Active

Pins

Supply
Voltage (V)

Temp·
Range

83
83
165
165
165
165
165
165

660
550
660
770
660
660
660
660

24
24
24
24
20
20
20
20

5
5
5
5
5
5
5
5

e
e,M
e,M
e
e
e,M
e
e,M

*Available in 1983.

O,P
O,P
O,P
O,P

°°
°°

4-51
4-51
4-51
4-51
4-57
4-57
4-58
4-58

DYNAMIC RAMs
Part
Number

Am9016e
Am9016D
Am9016E
Am9016F

Organization

Access
Time (ns)

16384 x 1
16384 x 1
16384 x 1
16384 x 1

300
250
200
150

Power Dissipation (mW)
Standby

Active

Pins

20
20
20
20

420
420
420
420

16
16
16
16

1-11

Supply
Voltage (V)

+12
+12
+12
+12

±5
±5
±5
±5

Temp
Range

Package

Page
No.

e,l
e,l
e,l
e

P,D,l
P,D,l
P,D,l
P,D,l

4-59
4-59
4-59
4-59

II

ROMs
Part
Number

Organization

Access Time
(ns)

8316E
Am9218B
Am9218C
Am9232B
Am9232C
Am9232D
Am9233B
Am9233C
Am9233D
Am9264B
Am9264C
Am9264D
Am9265B
Am9265C
Am9265D
Am92128B
Am92128C
Am92128D
Am92256B
Am92256C
Am92256D

2048 x8
2048x8
2048x8
4096x8
4096x8
4096x8
4096x8
4096x8
4096x8
8192 x8
8192 x8
8192 x 8
8192x 8
8192 x8
8192 x 8
16384 x 8
16384 x 8
16384 x 8
32768 x8
32768x8
32768x8

450
450
350
450
300
250
450
300
250
450
300
250
450
300
250
450
300
250
450
300
250

Temp
Range

Supply
Voltage

Pins

Operating Power
Max(mW)

Outputs

Page
No.

+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5

24
24
24
24
24
24
24
24
24
24
24
24
28
28
28
28
28
28
28
28
28

499
368
368
420
420
420
420
420
420
440
440
440
440,1101
440,110 1
440,110 1
440,137 1
440,137 1
440,137 1
660,165 1
660,165 1
660,165 1

3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State

5-1
5-1
5-1
5-4
5-4
5-4
5-4
5-4
5-4
5-8
5-8
5-8
5-12
5-12
5-12
5-15
5-15
5-15
5-18
5-18
5-18

C,M
C,M
C
C,M
C
C
C,M
C
C
C,M
C
C
C,M
C
C
C,M
C
C
C
C
C

Note: 1. Standby

u.v. ERASABLE PROMs
Part
Number

Organization

Access
Time (ns)

Am1702A
Am1702AL
Am1702A-1
Am1702AL-1
Am1702A-2
Am1702AL-2
Am2708/9708
Am2708-1
Am2716
Am9716
Am2716-1
Am2716-2
Am2732
Am2732-1
Am2732-2
Am2732N
Am2764-2
Am2764
Am2764-3
Am2764-4
Am27128·

256x8
256x8
256x8
256x8
256x8
256x8
1024x8
1024x8
2048 x8
2048x8
2048 x8
2048 x8
4096x8
4096x8
4096x8
4096x8
B192 x 8
8192 x B
8192xB
8192x8
16384 x 8

1000
1000
550
550
650
650
450/480
350
450
300
350
390
450
350
390
250
200
250
300
450
250

·Available first quarter 1983

Temp
Range

Operating PowerAct/Stby Max (mW)

Supply
Voltages

Outputs

Number
of Pins

Page
No.

676

-9, +5
-9, +5
-9,+5
-9, +5
-9, +5
-9, +5
+5, +12,-5
+5, +12,-5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5
+5

3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State
3-State

24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
28
28
28
28
28

6·1
6-1
6-1
6·1
6-1
6-1
6·7
6-7
6-11
6-11
6-11
6-11
6-16
6-16
6-16
6-21
6-22
6-22
6-22
6-22
6-27

C,L
C,L
C,L
C,L
C,L
C,L
C,M
C
C,I,L,M
C
C,I,L
C
C,I,L,M
C
C
C
C,I
C,I,M
C,I
C,I,M
C

676

676

800
800
525/132
525/132
525/132
525/132
787/157
787/157
787/157
7B7/1B4
525/105
525/105
525/105
525/105
525/210

Temperature Ranges

Package Types

C = Commercial 0 to 70°C
M = Military -55 to +125°C
L = Extended -55 to +85°C or + 100°C
I = Industrial -40 to +B5°C

o = Cerdip
P = Plastic
F = Flat Pack
L = Leadless Chip Carrier

1-12

Bipolar PROM
Cross Reference Guide

II
Am27lS18 1

256

32 x 8

OC

16

50165

53/63lS080

NlS82S23

Am27lS19 1

256

32 x 8

3S

16

50165

53163lS081

NlS82S123

TBP18S030

Am27S18

256

32 x 8

OC

16

40/50

DM75/8577
DM54/74S188

NlS82S23

TBP18SA030

Am27S18A

256

32x8

OC

16

25135

Am27S19

256

32 x 8

3S

16

40/50

DM7518578
DM54/74S288

N/S82S123

TBP18S030

Am27S19A

256

32 x 8

3S

16

25135

Am27S20

1024

256x 4

OC

16

45160

Am27S20A

1024

256x4

OC

16

30/40

Am27S21

1024

256 x 4

3S

16

45160

Am27S21A

1024

256 x 4

3S

16

30/40

Am27S12

2048

512 x 4

OC

16

50160

Am27S12A

2048

512 x 4

OC

16

30/40

Am27S13

2048

512 x 4

3S

16

50/60

Am27S13A

2048

512 x 4

3S

16

30/40

Am27S15

4096

512 x 8

3S

24

60/90

Am27S25

4096

512 x 8

3S

24

N.A.2

Am27S25A

4096

512 x 8

3S

24

N.A.4

Am27S27

4096

512 x 8

3S

22

N.A. 2

Am27S28

4096

512 x 8

OC

20

55170

Am27S28A

4096

512 x 8

OC

20

35/45

Am27S29

4096

512 x 8

3S

20

55170

Am27S29A

4096

512 x 8

3S

20

35145

Am27S30

4096

512 x 8

OC

24

55170

Am27S30A

4096

512 x 8

OC

24

35/45

Am27S31

4096

512 x 8

3S

24

55170

Am27S31A

4096

512 x 8

3S

24

35145

Am27S32

4096

1024 x 4

OC

18

55170

Am27S32A

4096

1024 x 4

OC

18

35145

Am27S33

4096

1024 x 4

3S

18

55/70

Am27S33A

4096

1024 x 4

3S

18

35/45

N.A.2

Am27S35

8192

1024 x 8

3S

24

Am27S35A

8192

1024 x 8

3S

24

N.A.4

Am27S37

8192

1024 x 8

3S

24

N.A.2

Am27S37A

8192

1024 x 8

3S

24

N.A.4

Am27S180

8192

1024 x 8

OC

24

60/80

Am27S180A

8192

1024 x 8

OC

24

35/50

Am27S181

8192

1024 x 8

3S

24

60/80

Am27S181A

8192

1024 x 8

3S

24

35/50

Am27PS181

8192

1024 x 8

3S

24

Am27PS181A

8192

1024 x 8

3S

24

Am27S280 3

8192

1024 x 8

OC

24

60/80

Am27S280A3

8192

1024 x 8

OC

24

35150

Am27S281 3

8192

1024 x 8

3S

24

60/80

Am27S281A3

8192

1024 x 8

3S

24

35150

HM7602

5316330-1

TBP18SA030

53/6330-1

HM7603

53/6331-1
53/6331-1

93417

HM7610A

M3601

53/6300-1

DM54/74S387

29660

NlS82S126

TBP24SA10

DM54/74S287

29661

NlS82S129

TBP24S10

53/6305-1

DM54/74S570

29610

NlS82S130

5316306-1

DM54/74S571

29611

N/S82S131

53/6300-1

93427

HM7611A

M3621

53/6301-1
53/6301-1

HM7620A

93436

M3602
3602

93446

HM7621A

M3622

HM7647R

N/S82S115

MB7123

HM7648

53/6348

DM54/74S473

29620

NlS82S146

TBP28SA42

MB7124

HM7649

53/6349

DM54/74S472

29621

NlS82S147

TBP28S42

93438

HM7640A

M3604

53/6340

DM77/87S475

29624

N/S82S140

TBP28SA46

93448

HM7641A

M3624

53/6341

DM77/87S474

29625

N/S82S141

TBP28S46

HM7642A

M3605

53/6352

DM54/74S572

29640

N/S82S136

TBP24SA41

HM7643A

M3625

53/6353

DM54/74S573

29641

NlS82S137

TBP24S41

93452

MB7121E
MB7121H

93453

MB7122E
MB7122H

53/63S441A

DM87SR81

93450

MB7131

HM7680

93451

MB7132

HM7681

M3628

53/6380

DM77/87S180

29630

N/S82S180

TBP28SA86

53/6381

DM77/87S181

29631

N/S82S181

TBP28S86

29633

53/6380JS

53/6381JS

1-13

BIPOLAR PROM CROSS REFERENCE GUIDE
o·

~

§'

~

;;-

if
~

;'$

q,1Ii

~
~

~

Am27PS281

8192

!!

!I
~
~
0
1024 x 8

!;

~

~

~

N

#0

~~
q,1Ii ",.:~8~

3S

24

c¥

~
~

~
~

~

~

«:~

~

.~

If
~

?f o·
I:
.f~
~

~

§

;'$

:R

!
tt

l

"

;'$

~

ilJO}

~

35150

Am27PS281A3

8192

1024 x 8

3S

24

Am27S184

8192

2048 x 4

OC

18

50155

MB7127

Am27S184A

8192

2048 x 4

OC

18

35145

MB7127H

Am27S185

8192

2048 x 4

3S

18

50155

MB7128

Am27S185A

8192

2048 x 4

3S

18

35145

MB7128H

Am27LS184

8192

2048 x 4

OC

18

60165

Am27LS185

8192

2048 x 4

3S

18

60165

Am27PS185

8192

2048 x 4

3S

18

60165

Am27S190

16384

2048 x 8

OC

24

50165

Am27S190A

16384

2048 x 8

OC

24

35150

Am27S191

16384

2048 x 8

3S

24

50165

Am27S191A

16384

2048 x 8

3S

24

35150

Am27PS191

16384

2048 x 8

3S

24

65175

Am27PS191A

16384

2048 x 8

3S

24

50165

Am27S2g03

16384

2048 x 8

OC

24

50/65

Am27S290A3

16384

2048 x 8

OC

24

35150

Am27S291 3

16384

2048 x 8

3S

24

50165

Am27S291A3

16384

2048 x 8

3S

24

35150

Am27PS291 3

16384

2046 x 6

3S

24

65175

Am27PS291A3

16384

2048 x 8

3S

24

50/65

Am27S40

16384

4096 x 4

OC

20

50165

Am27S40A

16384

4096 x 4

OC

20

35150

Am27S41

16384

4096 x 4

3S

20

50/65

Am27S41A

16384

4096 x 4

3S

20

35150

Am27PS41

16384

4096 x 4

3S

20

50165

Am27S43

32768

4096 x 8

3S

24

N.A.

Am27S43A

32768

4096 x 8

3S

24

N.A.

Am27PS43

32768

4096 x 8

3S

24

N.A.

Am27S45

16384

2048 x 8

3S

24

N.A.2

Am27S45A

16384

2048 x 8

3S

24

N.A.4

Am27S47

16384

2048 x 8

3S

24

N.A.2

Am27S47A

16384

2048 x 8

3S

24

N.A.4

Notes: 1.
2.
3.
4.

#11

§~

~

!:

HM7684

HM7685

53/63100

DMnt87S184

29650

NlS82S184

TBP24SA81

53/63101

DMnt87S185

29651

NlS82S185

TBP24S81

DMnt87S190

29680

NlS82S190

DMnt87S191

29681

NlS82S191

53/63S841A

29653
93510

MB7137

HM76160

93511

MB7138

HM76161

M3636B
M3636B-1

29683

29681S

29683S

HM76164

MB7134

53/63S1641

HM76165

29641

NlS82S195

53/63S1641A
29643
MB7142

3632

Replaces Am27LS08/LS09.
Contains built-in pipeline registers: nominal address to clock setup time
300-millateral pin spacing.
Contains built-in pipeline registers: nominal address to clock setup time

1-14

= 35ns (typ). clock to output = 20ns (typ).
= 25ns (typ). clock to output = 15ns (typ).

NlS82S321

TBP28S166

Bipolar Memory RAM
TTL and ECL Cross Reference Guide

II

BIPOLAR ECl RAM CROSS REFERENCE GUIDE

1024 xl

Aml0415SA

16

15/20

10K

-150/-165

HM2110-2
HM2110-1

Aml0415A

1024 x 1

16

10K

20/25

-150/-165

F10415A

MBM10415AN

HM2110-2
HM2110-1

Aml0415

1024 xl

16

10K

35/40

-150/-165

F10415

MBM10415A

HM2110

Aml00415A

1024 xl

16

lOOK

15/-

-150/-

Am100415

1024 x 1

16

lOOK

20/-

-150/-

Aml0470SA

4096 xl

18

10K

15/20

-230/-255

Aml0470A

4096 xl

18

10K

25/30

-200/-220

F10470A

Aml0470

4096 xl

18

10K

35/40

-200/-220

F10470

Am 100470SA

4096 xl

18

lOOK

15/-

-230/-

Am 100470A

4096 xl

18

lOOK

25/-

-195/-

Aml00470

4096 xl

18

lOOK

35/-

-195/-

Am 10474A

1024 xl

24

10K

15/-

-230/-

Aml0474

1024 xl

24

10K

25/-

-230/-

Aml00474A

1024 x 1

24

lOOK

15/-

-230/-

Aml00474

1024 xl

24

lOOK

25/-

-230/-

10415A

MCM10146

DM10415

10415

GXB10415

DM10415A
l00415A

Fl00415A

100415
MBM10470A

HM10470-1
HM10470

MCM10470A

10470A

MBM10470
MBM100470A

DM10470
HM100470-1
HM100470

Fl00470

MBM100470

F10474

MBM10474

100470A

HM10474-1
HM10474
HM100474-1
HM100474

F100474

GXB100474

BIPOLAR TTL RAM CROSS REFERENCE GUIDE
o·

·s~

~
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q,lfi

~

~

~
0

....

~

$

f;;t ~~~

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16

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25/30

100/105

6560A

DM74/54S289A

6561

DM74/54S189A

Am27S03A

16x4

16

3S

25/30

100/105

Am27S02

16 x 4

16

OC

35/50

1051105

Am74/54S289

16 x 4

16

OC

35150

1051105

Am3101A

16 x 4

16

OC

35150

105/105

DM74/54S289
93403
74S289

3101A

5501

6515560

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4064

q;

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~o;

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N/S82S25
N/S74/54S289

SN74/54S289

N3101A

Am27S03

16 x 4

16

35

35150

1251125

Am74/54S189

16x4

16

3S

35150

1251125

Am27LS02

16 x 4

16

OC

55/65

35138

L6515560

DM74/54LS289

Am27LS03

16x4

16

3S

55/65

35138

L6515561

DM74/54LS189

93405
74S189

DM74/54S189

6515561

N/S74/54S189

SN74/54S189

DM8517599

Am27S06A(1)

16 x 4

16

OC

25130

100/105

Proprietary

Am27S07A(1)

16x4

16

3S

25130

100/105

Proprietary

Am27S06(1)

16 x 4

16

OC

35150

100/105

Proprietary

Am27S07(1)

16 x 4

16

3S

35150

100/105

Proprietary

Am27LS06(1)

16 x 4

16

OC

55165

35138

Proprietary

Am27LS07(1)

16x4

16

3S

55165

35138

Proprietary

Am31 01-1 (2)

16 x 4

16

OC

35150

1001105

Am74/5489-1 (2)

16 x 4

16

OC

35150

100/105

Am3101(2)

16 x 4

16

OC

50/60

1001105

7489

3101

DM74/5489

SN74/5489

Am74/5489(2)

16x4

16

OC

50/60

100/105

Am31 LOl A(2)

16 x 4

16

OC

55165

35138

Proprietary

Am31L01(2)

16x4

16

OC

80/90

35138

Proprietary

Am27LSOOA

256 x 1

16

3S

35145

1151115

Proprietary

Am27LS01A

256 xl

16

OC

35145

1151115

Proprietary

Am27LSOO

256 x 1

16

3S

45155

70/70

93L420
93421
93L421

3106

6515531

1-15

4256

DM74/54S200

N/582S116

N/582S16

SN74/54S201
SN74/54S200
SN74/54LS200

BIPOLAR TTL RAM CROSS REFERENCE GUIDE (Cont.)
o·

.~~

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;:

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q,tri

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tf

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N/582S117
N/582S17

I::
SN74/S4S301
SN74/S4S300
SN74/S4LS300

OC

45155

16

3S

35145

115/115

Proprietary

16

OC

35/45

115/115

Proprietary

256 xl

16

3S

45/55

70/70

Proprietary

Am27LSOH(1)

256 xl

16

OC

45/55

70/70

Am93415A

1024 xl

16

OC

30/40

1551170

93415A

2115

Am93425A

1024 xl

16

3S

30/40

155/170

93425A

2125

Am93415

1024 xl

16

OC

45/60

155/170

93415

2115

MCM93415

NlS82S10

SN74/S4S314

Am93425

1024 x 1

16

3S

45/60

155/170

93425

2125

MCM93425

N/582S11

SN74/S4S214

Am93412A

256 x 4

22 3

OC

35/45

155170

93412A

Am93422A

256 x 4

22 3

3S

35/45

155170

93422A

Am93412

256 x 4

22 3

OC

45160

1551170

93412

MCM93412

Am93422

256 x 4

22 3

3S

45160

155/170

93422

MCM93422

Am93L412A

256 x 4

22 3

OC

45155

80/90

93L412A

Am93L422A

256 x 4

22 3

3S

45155

80/90

93L422A

Am93L412

256 x 4

22 3

OC

60/75

80/90

93L412

Am93L422

256 x 4

22 3

3S

60/75

80/90

93L422

Am27LS01

256 xl

16

Am27LSOO-1A(1 )

256 xl

Am27LSOHA(1)

256 xl

Am27LSOO-l (1)

70/70

3107

65/5530

DM74/S4S206

Proprietary
N/582S110
N/S82S111

Notes: 1_ Noninverting outputs.
2. Write transparent; complement of data-in is available on the outputs in the Write Mode when both CS and WE are low_
3. Cerpak is 24 pin.

1-16

Competitive MOS Memory Cross Reference
AMI

AMD

INTEL (Cont.)

AMD

NATIONAL (Cont.)

AMD

S2333
S2364
S4216B
S4264
S68A364
S6831B
S68332

Am9233
Am9265
Am9218
Am9264
Am9264 2
Am9218
Am9232

1506
1507
1702A
1702AL
2114A
2114AL
2117
2128
2141
2147
2148
2149
2316/8316E
2332
2364
2401
2405
2708
2716
2732
2732A
2764
27128

Am1506
Am1507
Am1702A
Am1702AL
Am9114
Am91l14
Am9016
Am9128
Am21L41
Am2147
Am9148
Am9149
Am9218
Am9233
Am9265
Am2401
Am2405
Am2708
Am2716
Am2732
Am2732
Am2764
Am27128

MOSTEK

AMD

MM2147
MM2708
MM2716
MM4006
MM4007
MM4025
MM4026
MM4027
MM4055
MM4056
MM4057
MM5025
MM5026
MM5027
MM5055
MM5057
MM5058
MM5202AQ
MM52116
MM52132
MM52164
MM5235
MM5257
MM5258
MM5290

Am2147
Am2708
Am2716
Am1406
Am1407
Am2825
Am2826
Am2827
Am2855
Am2856
Am2857
Am2855
Am2826
Am2827
Am2855
Am2857
Am2833
Am1702A
Am9218
Am9232
Am9264
Am9265
Am9044
Am9218
Am9016

MK1002P
MK1007
MK2147
MK2716
MK2764
MK32000
MK34000
MK36000
MK37000
MK3702
MK3708
MK38000
MK4104
MK41 04
MK4116
MK4802

Am2810
Am2847
Am2147
Am2716
Am2764
Am9232
Am9218
Am9264
Am9265
Am1702A
Am2708
Am92256 3
Am92442
Am21L41
Am9016
Am9128

EA

AMD

EA-2316E18316E
EA-2364
EA-23128
EA-8332
EA-8333

Am9218
Am9264
Am92128
Am9232
Am9233

FAIRCHILD

AMD

F16K
F2114
F2114L
F2533
F2708
F3341
F3341 A
F3347
F3357-2
F4116
F93422
F93L422

Am9016
Am9114
Am9114
Am2833
Am2708
Am2841
Am2841A
Am2847
Am2847
Am9016
Am9122
Am91l22

FUJITSU

AMD

MBM2147
MBM2148
MBM2149
MBM2716
MBM2732
MBM2764
MBM4044
MBM8114
MB8116
MB8128
MB8216
MB8414 (CMOS)
MB8416 (CMOS)

Am2147
Am9148
Am9149
Am2716
Am2732
Am2764
Am9044
Am9114
Am9016
Am9128
Am9016
Am91L142
Am9128 2

G.I.

AMD

R03-9322

Am9232

HITACHI

AMD

HM4334 (CMOS)
HN462532
HN462716
HN462732
HM4716A
HM472114
HM4847
HM6116 (CMOS)
HM6147 (CMOS)
HM6148 (CMOS)

Am91L142
Am2732 3
Am2716
Am2732
Am9016
Am9114
Am2147
Am9128 2
Am21472
Am9148 2

INTEL

AMD

1402A
1403A
1404A
1405A
1406
1407

Am2802
Am2803
Am2804
Am2805
Am1406
Am1407

MOTOROLA

AMD

MCM2114
MCM2147
MCM2708
MCM2716
MCM2532
MCM4016
MCM4116
MCM58366
MCM68A364
MCM68B364
MCM68308
MCM68332
MCM68365
MCM8316E

Am9114
Am2147
Am2708
Am2716
Am2732 3
Am9128
Am9016
Am9264
Am9264 2
Am9264 2
Am9208
Am9232
Am9264 2
Am9218

NATIONAL

AMD

MM1402A
MM1403A
MM1404A
MM1702A
MM2114
MM2114L
MM2116

Am2802
Am2803
Am2804
Am1702A
Am9114
Am9114
Am9128

1-17

NEC

AMD

JLP02114L
JLP02147
JLP02149
JLP02316E
JLP02332
JLP023128
JLP02364
JLP02708
JLP02716
JLP 041 04
JLP04104
JLP0416
JLP0444 (CMOS)
JLP0446 (CMOS)
JLP06514 (CMOS)
JLP02732

Am9114
Am2147
Am9149
Am9218
Am9232
Am92128 2
Am9264
Am2708
Am2716
Am92L442
Am21L412
Am9016
Am91l142
Am9128 2
Am91l142
Am2732

SIGNETICS

AMD

1702A
2332
2364
23128
2502
2503
2504
2505
2506
2507
2512
2521
2524
2525
2532
2533
2616
2632
2664

Am1702A
Am9233
Am9265 2
Am92128 2
Am2802
Am2803
Am2804
Am2805
Am1406/1506
Am1407/1507
Am2806
Am2809
Am2807
Am2808
Am2847
Am2833
Am9218
Am9232
Am9264

II

COMPETITIVE
MOS MEMORY CROSS REFERENCE (Cent.)

SYNERTEK

AMD

T.I.

AMD

TOSHIBA

AMD

SY1402
SY1403
SY1404
SY2101
SY2111
SY2112
SY2114
SY2114L
SY2128
SY2316E
SY2332
SY2333
SY2364
SY2365
SY23128
SY2405
SY2802
SY2803
SY2804
SY2825
SY2826
SY2827
SY2833

Am2802
Am2803
Am2804
Am9101
Am9111
Am9112
Am9114
Am9114
Am9128
Am9218
Am9232
Am9233
Am9264
Am9265
Am92128
Am2405
Am2802
Am2803
Am2804
Am2825
Am2826
Am2827
Am2833

TMS2147
TMS2149
TMS2708
TMS2516
TMS2532
TMS3114
TMS3120
TMS3128
TMS3133
TMS3406
TMS3407
TMS2412
TMS3413
TMS3414
TMS4016
TMS40L44
TMS4044
TMS40L45
TMS4045
TMS4116
TMS4244
TMS4245
TMS4732
TMS4764

Am2147
Am9149
Am2708
Am2716
Am2732 3
Am2814
Am2847
Am2809
Am2833
Am1406
Am1407
Am2802
Am2803
Am2804
Am9128
Am90L44
Am9044
Am91L14
Am9114
Am9016
Am9244
Am9124
Am9232
Am9264

TC5516 (CMOS)
TMM2016
TMM2732D
TMM323D
TMM416

Am9128 2
Am9128
Am2732-1
Am2716
Am9016

1-18

Notes: 1. 110mW Standby Power Dissipation.
2. Pin-for-pin functional equivalent.
3. Different pinout.

Testing High-Performance
Bipolar Memory

By Bob Lutz
Advanced Micro Devices

1-19

II

Testing High-Performance Bipolar Memory
INTRODUCTION

cess. This combination of advanced design and fabrication
technologies assures the military user of receiving components
which are intended for his application while providing the commercial user with the extra margins, performance advantages
and procurement benefits mentioned above.

During the last several years, the state-of-the-art of TTL compatible bipolar memory integrated circuits has advanced very
rapidly. Device complexity has increased dramatically not only in
terms of the memory storage capacity but also by the addition of
new on-chip functions such as the inclusion of output data registers. Simultaneously, advances in bipolar LSI design and
manufacturing technology have generated significant improvements in the performance levels of bipolar memory. Similarly,
the complexity and performance levels of systems which employ
these devices have grown. The concomitant growth of system
complexity has placed additional demands on both the device
manufacturer and the user's incoming inspection area to assure
the performance capabilities of each component before it is
assembled into the system.

THE SYSTEM ENVIRONMENT
To understand the problems of high-performance memory testing, it is helpful to understand the electrical environment in which
the memory devices will actually operate, i.e., the typical system
environment. The system designer must address and resolve
several critically important questions if the system is to consistently perform to its design specifications. These questions
include:
1. What noise voltages can the system's logic and memory devices tolerate?
2. What are the sources of system noise?
3. What can be done to control and minimize this noise?

Several test equipment manufacturers now supply sophisticated, computer controlled testers for these inspection tasks.
Most of this equipment is inherently capable of the millivolt and
nanosecond accuracies which are required; most memory testers can generate the complex waveforms and test patterns
needed. However, the details of applying this equipment to a
specific test problem, including the problem of interfacing the
tester to the device-under-test, are usually left to the user. The
purpose of this application note is to discuss several problems
which are frequently encountered when testing high performance bipolar memory devices, and to aquaint the user with
how such problems may be identified, measured and corrected.

The first question is answered relatively easily. The magnitude
of noise which can be tolerated relates directly to the worst case
noise immunity specified for the logic family. Noise immunity is
simply the difference between the worst case output levels (VOH
and VOL) of the driving circuit and the worst case input voltage
requirements (VIH and VIL, respectively) of the receiving circuit.
For TTL devices the worst case noise immunity is typically
400mV for both the high and low logic levels.
If "system noise" is defined as the sum of things which subtract
from this noise immunity, several sources can be identified. A
few of the most important sources found in a digital, TTL system
are listed below:

WHAT MAKES A MEMORY GOOD?
Before discussing the specifics of bipolar memory testing problems, it is important to understand the basic characteristics
which these devices should exhibit. Clearly each device must
meet all product specification parameters but, first and foremost,
a bipolar memory should be fast! Address access time (delay
from address input to data output), enable access time, and enable recovery time should be as small as possible. High performance is often the primary reason for using bipolar memory.
Similarly, the performance of the ideal bipolar memory should
remain relatively constant with changes in supply voltage, ambient temperature and output load capacitance. Fast devices,
offering stable performance over a broad range of conditions,
permit the user to qualify a smaller number of part types; one
fast device can accommodate many standard as well as high
performance applications. Such devices provide added safety
margin for the system design, permit simplification of system
test and debug, and assure trouble-free system performance in
the field. Hence the "best" memory is a fast, stable device which
not only meets a given user specification, but also offers the
extra performance needed for a broad range of applications.

• Cross-Talk: The desire to pack system components as
tightly as possible inevitably causes signal wires or PC board
traces to be placed in close proximity. The lead-to-Iead
capacitance and mutual inductance thus created (see Figure
1) causes "noise" voltages to appear when adjacent signal
paths switch.
• Transmission Line Reflections: Like it or not, every signal
path in the system has transmission line characteristics. TTL
signal paths are usually not designed as transmission lines,
with predictable and uniform characteristic impedances. This
is partly because of the higher costs implied for multilayer PC
boards with internal ground planes, termination resistors, etc.
It is aiso the result of TTL logic's limited ability to drive the low
impedance lines provided by current PC board technologies.
Hence, TTL signal paths do exhibit the ringing and reflection
problems associated with improperly terminated transmission
lines. These reflections subtract from the available noise immunityas shown in Figure 2.

Advanced Micro Devices offers a family of bipolar Random
Access Memories (RAMs) and Programmable Read Only
Memories (PROMs) which are designed to meet this idealized
definition as closely as possible. First, each AMD device is designed to meet a "military design goaL" This means AMD bipolar
memories are designed to provide the extra margins and higher
output drive capabilities needed to assure proper performance
over the extended military supply voltage and operating temperature ranges. This often necessitates the use of more advanced
design techniques such as on-chip regulators, temperature and
voltages compensation networks, and feedback circuits. Second, AMD has conceived and developed an advanced, oxide
separated, ion implanted manufacturing process called IMOX™.
Developed specifically for the production of high density bipolar
memories, this technology provides both high density and excellent performance in a truly reliable and manufacturable pro-

• Ground Network Noise: Most high-performance systems
employ large numbers of high-performance ICs. These devices typically draw large ICC currents from the power supply.
Cumulatively, these currents can reach several amperes per
board. Such currents, flowing in the ground network, cause
non-negligible DC voltage drops to occur; not all device
ground pins are at zero volts. Since the output levels and the
input thresholds of each TTL device reference the local
ground (Figure 3a), these drops also subtract from the available noise immunity. Additional noise margin losses occur
each time the device outputs switch. This occurs because
large currents must flow to rapidly charge and discharge the
interconnect and input capacitances which load each output.
These charging currents flow in a loop (Figure 3b) through the
ground network which is normally a simple interconnection of

IMOX is a trademark of Advanced Micro Devices, Inc.
1-20

Testing High-Performance Bipolar Memory

---00

VI

•

\
C

---0(] I .
~CI
V2

/

/

'1
p

II

II

1:
C1 I

VI

VOH
V1H
VIL

Cp

VOL

\

'2

00---

00---

•

VOL

VOH
VIH

As V1 switches, 11 flows to charge the input capacitance Ci- 12
flows as a result of mutual inductance_ The V1 voltage change is
also coupled directly to V2 through the parasitic line-to-line
capacitances, C p_

V1L
VOL

Figure 1. An Example of Cross-Talk

VI

VOH

tD-lIV'

VIH
V'L
VOL

--~--

I

JC

u

I

V2

VOH

The unit length capacitance and inductance (C u and Lu) give
each system connection transmission line characteristics_ Without a matched termination, switching at V1 causes reflection
voltages to appear at V2, reducing noise immunity_

V'H
V'L
VOL

Figure 2. Line Reflections

Vi = Va - (n -Icc) RGND

When Vi goes HIGH, Va goes LOW discharging CL- The discharge current Id flows through the ground inductance LGND,
creating a transient voltage Vt- The input voltage seen by gate B
is actually Vi - Vtb) Transient Ground Noise

a) DC Ground "Noise"
Figure 3.

1-21

II

Testing High-Performance Bipolar Memory
wires, each with some value of resistance and inductance per
unit length. Some additional resistive drops occur. But, the
rapid changes in these currents (large dildt) , occurring as
charging starts and stops, mean a transient ground noise
voltage is also generated. This voltage obeys the law of v =
L(di/dt) where L is the ground circuit inductance and di/dt is
the rate of change of the charging currents. Notice that adding
local bypass capacitors can only reduce this voltage by
paralleling the ground inductance with the VCC network inductance. Bypassing cannot eliminate this problem because
these capacitors shunt the devices and not the ground and
Vcc network inductances where the noise is generated.

Since noise margin violations result in system malfunctions, the
system designer must define a set of rules governing the physical construction techniques to be used within the system. These
rules address a host of considerations including power distribution, AC grounding, lead placement, line termination requirements, logic loading (fan in and fan out), and interconnect
delays. Specifying these rules is a complex process of making
appropriate cost-performance tradeoffs.
For a medium to high performance system, these rules might
specify arranging devices in an array with VCC power traces
running vertically up the columns while ground metal running
horizontally between the rows. Inserting bypass capacitors at
each grid intersection forms an AC ground mesh (Figure 4),
limiting the amount of ground inductance at each array site. If
limits are also placed on the total capacitance each device may
drive (cumulative interconnect and input capacitance on all outputs), the total charging currents may be controlled thus limiting

Controlling and minimizing noise in a digital system becomes
more challenging as the system performance requirements increase. These requirements demand devices capable of short
propagation delays, e.g., ultra-fast memories with excellent
diive characteristics to minimize fully loaded access times.

GND

GND

GND

GND

Note: Transient ground currents flow in four directions from each device ground: right and left on the ground bus; up and
down the Vee bus after passing through the local bypass capacitor, C. Equivalent ground inductance is very low.

Figure 4. Example of an AC Ground Mesh

1-22

Testing High-Performance Bipolar Memory
the noise immunity eroded by ground circuit noise. Similarly, the
distance between adjacent traces and the maximum length of
unterminated lines may be specified to control noise immunity
losses caused by cross-talk and termination mismatches.
Ultra-high performance systems may require additional measures; e.g., multilayer boards with true ground planes or increased usage of line drivers and receivers. Though the preceding descriptions have been simplified, it should be clear that
distances between driving and receiving devices, the quantity
and distribution of load capacitance, as well as the AC ground
network integrity are all essential elements of the system design.

The OUT must be tested inside this equipment, requiring still
more wiring between the test head and the actual test site.
Ideally, all test hardware would be located immediately adjacent
to the test site to minimize cross-talk, reflections and ground
noise. However, this objective must be compromised to address
the other objectives and constraints outlined above. Techniques
commonly employed in making this compromise are illustrated
in Figure 5. Notice that OUT drivers are remote from the test site,
driving signal to the OUT through "series terminated" transmission lines. Similarly the receivers are some distance from the
test site, receiving signals from the OUT through a series of connectors and wires which can degrade the signal. Most annoying
of all, the test site ground connection has been compromised.
This single path must carry heavy transient and OC currents
during test and should provide a very solid, low impedance reference against which all AC and DC tests are made. Accumulating resistance and inductance in this path jeopardizes
the integrity of all test results.

THE MEMORY TEST ENVIRONMENT
Ideally the test system hardware and fixtures would be designed
to even more stringent rules than those used for the system.
This is reasonable as the tester is the standard employed for accepting or rejecting components used in the system. Because a
collection of additional objectives constrain the test environment, designing test hardware to equally or more stringent rules
is usually impractical.

Hence, the electrical environment provided at the test site is
generally inferior to the actual system environment where the
memory component will be used.

Memory testers must test many types of components under a
variety of conditions. Tests performed include OC parametric
tests, functional and AC tests with complex test patterns, and
margin tests to assure device operation at the extremes of
applied conditions and supply voltage. To accomplish this, connections to sets of programmable input drivers and output receivers (comparators), multiple device bias and power supplies,
relays to permit connection of the OC parametric test unit, and
special load circuits must all converge at the test site.

TEST RELATED PROBLEMS AND SOLUTIONS
Accurately measuring or verifying memory performance in the
test system environment requires a recognition of its inherent
limitations. Outlined below are five problem areas commonly
encountered when testing high-performance bipolar memories.
Methods of identifying and alleviating these problems are
indicated.
o Contending with Ground Noise: Ground noise is one of the
most common and troublesome test problems. As defined
above, ground noise is caused by switching currents flowing
through the ground network impedance. Whereas the system
environment (Figure 4) may provide multiple low inductance
ground paths into a ground mesh or plane, the tester provides
one long, higher inductance path back to the test system
ground (Figure 5). This path includes handler contacts, connectors and the OUT load board, all of which increase ground

To provide flexibility and facilitate repair, test hardware must be
modular. This requirement dictates placing the hardware (drivers, receivers, etc.) on many small PC boards which then must
talk to the OUT (device under test) through additional wiring and
connectors.
Frequently the quantity of parts tested necessitates mating an
automatic device handler to the tester. Handlers also provide
capabilities for testing at temperature extremes when needed.

HANDLER CONTACTS
OR TEST SOCKET

TEST
SITE

DUTGROUND

CBYPASS

Vee

DUTLOAD
BOARD

INPUT
SIGNALS

OUTPUT
SIGNALS

~.---------------------,~-----COMPARATORS

DRIVERS

PARASITIC
GROUND
INDUCTANCE

/SERIES
LMATCHING
RESISTOR

CeOMPARATOR

SYSTEM GROUND

Figure 5. The Test System Environment

1-23

TEST HEAD
AND SYSTEM

II

Testing High-Performance Bipolar Memory
inductance and resistance. Transient currents which result
when the OUT switches can be enormous. Consider the case
of a byte wide (8 output) memory functional test. At some
point in the test sequence, all memory outputs will switch from
high to low (VOH to VOL) at the same instant, discharging
all eight load capacitances simultaneously. If the input capacitance of the receiver is 40pF and the interconnect
capacitance of the test fixture is lOpF, the total load capacitance driven by all device outputs would be 400pF. A fast
memory device could discharge this load at a 1V/ns rate. The
relationship i = C(dv/dt) implies peak charging currents of
400mA must flow through ground. As Figure 6 illustrates, this
charging current does not build to its full value instantaneously. For a fast device the time required to go from zero to
full charging current would approximate 2ns A resultant
ground current di/dt of 200mA/ns is implied. If the ground inductance is 1 nanohenry (approximate inductance of 1 inch of
straight, small guage wire), then v = L(di/dt) predicts AC

ground noise of 200mV. As you have probably guessed, the
typical test site ground inductance exceeds 1nh. The path is
longer and it is usually not a straight line connection. Actual
tester ground noise of up to 800mV is common when testing
high-performance byte wide memories. This noise can be
measured easily with a high bandwidth oscilloscope by attaching the scope ground to the actual test system ground
and monitoring the OUT ground pin with one channel.

Excessive ground noise creates several problems. First, this
noise is capacitively coupled to the input drive signals through
the OUT input capacitances; if large enough, DC coupling
through the OUT input clamp diodes can occur (Figure 7). The
OUT output levels are, of course, referenced to the OUT
ground potential whereas the receiver board is referenced to
test system ground, introducing inaccuracy in access time
measurements, etc.

BYTE WIDE
MEMORY

Vo

8 OUTPUTS

V,

Figure 6. Byte Wide Memory Ground Transients

MEMORY

INPUT
CIRCUIT

IOC
FROM

INPUT

DRIVER

L_-----I;j--Q------,.---,--t---;:,.

For small magnitudes of noise, Vt, noise is AC coupled to the inputs through the input capacitance, Ci. If Vi is low, large positive
values of Vt may momentarily forward bias the input clamp
diode, creating a DC coupling.
Figure 7. Ground Noise Coupling to the Inputs

1-24

Testing High-Performance Bipolar Memory
Worst of all severe ground noise can make functional testing
at or near the guaranteed input levels (VIH and VIL) impossible. To demonstrate, assume the device ground noise
reaches a positive O.8V with respect to test system ground
during output switching. Assume the input driver high level is
programmed to 2.0V, minimum VIH for most TTL devices.
The actual voltage between a "high" OUT input and its ground
is only 1.2V. The typical room temperature threshold voltage
of a TTL device is 1.5V, and the device interprets 1.2V as a
logic "low." This causes the memory to access a new memory
location momentarily. The resultant momentary change in
output data interferes with access time measurements. In severe cases, this momentary switching of output data creates
additional ground noise which also feeds back to the inputs
resulting in sustained oscillations. This noise interaction can
also be viewed with a dual trace oscilloscope as shown in
Figure 8. Channel A of the scope is connected to the address
input while channel B monitors the OUT ground pin. The input
voltage, as seen by the OUT, can be viewed directly by putting the scope in "A - B," algebraic subtract mode. Note the
scope ground is connected to test system ground as before.
Attaching scope ground to the OUT pin ground should be
avoided as this creates a "ground loop." If connected this
way, large noise currents flow in the alternate ground path
provided by the scope back to earth ground; this interferes
with the scope's ability to measure high-speed events and
modifies the condition which is to be observed.

-

- If the system uses a Kelvin (force - sense) ground system, terminate the system by shorting force to sense on
the OUT load board. Kelvin systems provide DC accuracy,
but their response times are much too slow to aid in the
suppression of ground noise at the test site. Terminating
Kelvin early sacrifices a little DC accuracy, but the ability to
use the previous sense line as second, low impedance
ground path usually improves the overall test accuracy.
Provide multiple high frequency bypass capacitors as
close as possible to the OUT, and again on the DUT load
board. This allows the Vee wiring to serve as an extra AC
ground path for high frequency ground noise.
Reduce the DUT load capacitance (receiver and interconnect capacitance) as much as possible; avoid using low
values of load resistors. Both techniques reduce the
transient currents, thus improving test accuracy. When
necessary, DUT output drive capability can usually be verified with DC tests.
-

Several techniques can be employed to reduce ground noise
problems:
-

Minimize the number of series connections in the DUT
ground path; provide as many parallel ground connections
as possible through each remaining connector.

If VIL and VIH tests are necessary, measure the maximum
amount of ground noise that the specific device type to be
tested generates in the actual test site. Set the input drive
levels no tighter than "VIH plus the maximum noise" and
"VIL minus the maximum noise." Using tighter limits over
tests the device!
Alternatively, use DC bench tests on a sample basis to
verify that input margins are acceptable. This is a sound
practice as the input thresholds of bipolar devices are ex-

Keep the ground path as short as possible; use large
diameter wire and "straight line" wiring techniques.

LVCC
r---------~

~----------~----~

CBYPASS

DC LOAD

OUT

l

LlL,
VB

I

u

II

EJ

::~,

GND

Figure 8. Monitoring Ground Noise

1-25

A

B

II

Testing High-Performance Bipolar Memory
tremely insensitive to fabrication process variations. Virtually any process variation or defect which would result in
a threshold failure would also result in the catastrophic
failure of other tests.

Corrective action for this problem includes:
Use short, low inductance connections from the OUT output to the receiver; minimize comparator and interconnect
capacitance. Both techniques raise the resonant frequency of the tank circuit which limits the time measurement error and reduces the OUT's ability to stimulate
ringing in the tank.

DC verification of VIL and VIH can also be performed on
the test system, but care must be exercised to insure that
input voltages NEVER cross through the 0.8 to 2.0V window; voltages residing in this window can cause the OUT
to switch, triggering sustained oscillations.

Use twisted pair wiring techniques to connect OUT outputs
to the receivers. Though this raises the capacitance
slightly, it reduces the purely inductive character of the
interconnect, usually tending to reduce ringing .

• The Output "Tank Circuit": A second common problem encountered is resonance in the circuitry which connects the
OUT outputs to the output comparators or receivers. This resonance occurs because the wire connecting the OUT outputs
to the receivers is actually an inductor connected in series
with the comparator input capacitance, forming a series resonanttank circuit (Figure 9). This load circuit is quite different
from the typical loading situation found in a system environment. Notice that the capacitance in the tester tends to be a
single large value of capacitance, lumped at the end of the
OUT output drive line. The load capacitance in the system is
generally smaller and it is distributed along the drive line; this
configuration looks much more like a transmission line, with
per unit length values of inductance and capacitance, than it
does a resonant tank. The resonant frequencies found at the
test site vary with wire length and capacitive load, but tend to
be in the 100 - 500MHz range. The input voltage sensed by
the receiver is actually the voltage at the center connection
within the tank circuit, which can ring violently when the outputs switch; measurement errors of 5ns or more can occur. A
good evaluation technique for this problem is to compare the
waveforms observed at the output of the device with a
"shmoo plot" of the output. Assuming a simple pattern is
used, differences in these results may indicate a resonance
problem.

• Minimizing Cross-Talk: Cross-talk between the input and
output lines of the OUT is also a common problem. Obviously,
the greater the number of paths which must be packed into a
given area, the greater the problem. The signal coupling that
occurs adds noise to both the input lines, making VIH and VIL
testing difficult, and output lines, reducing the accuracy of
timing measurements. Techniques which tend to reduce
cross-talk include the following:
-

Keep wires as short as possible and avoid laying wires on
top of each other.
Reduce output loading to minimize the magnitude of current transients which could be coupled into adjacent lines.
Use twisted pair or coaxial cable wherever possible; take
care to tie all grounds from these transmission lines
together at both ends.
Use ground plane or ground mesh techniques in the load
board and the handler interface if possible. A true ground
plane permits the use "strip" transmission lines which not
only minimize cross-talk, but also reduce ground noise.

Though expensive, ground plane techniques offer the test
engineer a consistent reference voltage which can be used to
identify and segregate the various components and sources
of noise.

ACTUAL ACCESS TIME

OUT

m

t--t;b~~=-

CO.PAMTO.
VOLTAGE

f\.e=;- t

LL, the interconnect inductance and CCOMPARATOR form a series resonant tank circuit which can cause time measurement errors.

Figure 9. Resonance at the Outputs

1-26

Testing High-Performance Bipolar Memory
environment may also selectively reject the best performing devices; i.e., those with the fastest access times and best drive
characteristics. This occurs because high-performance devices
magnify the problems found in the tester environment. The information presented here should aid the component engineer in
recognizing and resolving these special test environment problems. Attention to these details will reward the bipolar memory
user by assuring acceptance of the best and broadest range of
bipolar memories currently available.

CONCLUSION

Advanced Micro Devices has invested significantly in the development of advanced, high-performance bipolar memory
technologies and products. As the preceding discussion demonstrates, the memory tester presents a very different environment to the memory device than does the system. The
additional constraints placed on the tester virtually guarantee
that devices which function in this "worst case" environment will
perform satisfactorily in the system. However, this worst case

1-27

II

7

Bipolar Programmable
Read Only Memory (PROM) Index
Am27S18A/19A Series
Am29750A/Am29751A
Am27LS18/19
Am27S20A/21A Series
Am29760A/Am29761A
Am27S12A/13A Series
Am29770/Am29771
Am27S15
Am27S25A/25
Am27S27
Am29775
Am27S28A/29A Series
Am27S30A/31A Series
Am27S32A/33A Series
Am27S65
Am27S35A/37A Series
Am27S180A/181A Series
Am27S280A/281A Series
Am27PS181A/281A Series
Am27S184A/185A Series
Am27LS 184/185
Am27PS185
Am27S75
Am27S190A/191A Series
Am27S290A/291A Series
Am27PS191A/291A Series
Am27S45A/47 A Series
Am27S40A/41A Series
Am27PS41
Am27S85
Am27S43A/43

256-Bit Generic Series Bipolar PROM...... .... .. ........ ....... 2-1
256-Bit Generic Series Bipolar PROM.......... .. ........ ....... 2-7
Low-Power Schottky 256-Bit Generic Series Bipolar PROM ....... 2-8
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . .. 2-15
1024-Bit Generic Series Bipolar PROM. . . . . . . . . . . . . . . . . . . . . . . . .. 2-21
2048-Bit Generic Series Bipolar PROM ......................... 2-22
2048-Bit Generic Series Bipolar PROM ......................... 2-28
4096-Bit Generic Series Bipolar PROM ......................... 2-29
4K-Bit (512 x 8) Generic Series Bipolar IMOX Registered PROM. . . .. 2-34
4096-Bit Generic Series Bipolar Registered PROM .......... '. . . .. 2-41
4096-Bit Generic Series Bipolar PROM with Register. . . . . . . . . . . .. 2-46
4096-Bit Generic Series Bipolar PROM ......................... 2-47
4096-Bit Generic Series Bipolar PROM ......................... '2-52
4096-Bit Generic Series Bipolar PROM ......................... 2-57
Generic Series 4-Wide Bipolar IMOX Registered PROMs ......... 2-62
8K-Bit (1024 x 8) Generic Series Bipolar IMOX Registered PROM. ... 2-64
1024 x 8-Bit Generic Series Bipolar IMOX PROM ................ 2-73
1024 x 8-Bit Generic Series Bipolar IMOX PROM ................ 2-73
8192-Bit Generic Series IMOX Bipolar PROM .................... 2-80
8192-Bit Generic Series Bipolar IMOX PROM .................... 2-87
8192-Bit Generic Series Bipolar IMOX PROM .................... 2-92
8192-Bit Generic Series Bipolar IMOX PROM .................... 2-97
Generic Series 4-Wide Bipolar IMOX Registered PROMs ......... 2-62
16,384-Bit Generic Series Bipolar IMOX PROM .................. 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .................. 2-102
16,384-Bit Generic Series Bipolar IMOX PROM .................. 2-109
16K-Bit (2048 x 8) Generic Series Bipolar IMOX Registered PROM ... 2-116
16,384-Bit Generic Series Bipolar IMOX PROM .................. 2-125
16,384-Bit Generic Series Bipolar IMOX PROM .... , ............. 2-131
Generic Series 4-Wide Bipolar IMOX Registered PROMs ......... 2-62
32,768-Bit Generic Series Bipolar IMOX PROM .................. 2-137
Technical Report ............................................ 2-142
Guide to the Analysis of Programming Problems .............. 2-151
PROM Programming Equipment Guide ........................ 2-154

Am27S18A • Am27S19A
Am27S18 • Am27S19
25~BnGenericSeriesB~o~rPROM

(32 x 8 bits with ultra fast access time)
"A" VERSION ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 25ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures
• 100% MIL-STO-883C assurance testing
• Guaranteed to INT-STO-123

The Am27S18A/18 and Am27S19A/19 are high speed electrically programmable Schottky read only memories.
Organized in the industry standard 32 x 8 configuration,
they are available in both open collector Am27S18A/18 and
three-state Am27S19A/19 output versions. After programming, stored information is read on outputs 00-07 by
applying unique binary addresses to Ao-A4 and holding
the chip select input, CS, at a logic LOW. If the chip select
input goes to a logic HIGH, 00-07 go to the off or high
impedance state.

BLOCK DIAGRAM

GENERIC SERIES CHARACTERISTICS
This Am27S18A/18 and Am27S19A/19 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.
All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words
are pre-programmed during manufacturing to insure
extremely high field programming yields, and produce
excellent parametric correlation.

32.8

FUSE ARRAY

'~"

5

~---------Tf-ST-W-O-RO-O--------~'"

~--------~TE~ST~W~OR~D~'--------~~

BPM·018

CONNECTION DIAGRAMS
Top Views

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
non-conductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

Chip-Pak™
L-20-1

DIP

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.

Vee

cs

O.

A4

0;,

A3
A2

O.

A,

O.
AO

07

BPM-020

BPM-276

Note: Pin 1 is marked for orientation.
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Chip-Pak is a trademar~ of Advanced Micro Devices, Inc.
2-1

Am27S18A/S19A/S18/S19
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +VCcmax

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE
Temperature

Vee

LOGIC SYMBOL

4.75 to 5.25V
4.5 to 5.5V

Te = -55 to +125°C
10
11
12
13
14

Ao
Al
A2
A3
A4

32 X8 PROM

15

12345679

Vee = Pin 16
GND = Pin 8

BPM·019

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ

Test Conditions

Parameters

Description

VOH (Note 2)

Output HIGH Voltage

Vee = MIN,IOH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN,IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Vee = MAX, VIN = 2.7V

Ise(Note2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

lee

Power Supply Current

All inputs = GND, Vee = MAX

VI
leEX

Input Clamp Voltage

Vee = MIN,IIN = -18mA

Output Leakage Current

Vee = MAX
VC§ = 2.4V

Min

(Note 1)

Max

2.4

Volts
0.45

2.0

-40
90

0.8

Volts

-0.250

rnA

25

/LA

-90

rnA

115

rnA

-1.2

Volts

40

Vo =4.5V
Note 2

Vo = 2.4V

40

Vo = O.4V

-40

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 5)

4

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 5)

8

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters ar,e not 100% tested, but are periodically sampled.

2-2

Volts
Volts

-0.010

-20

Units

/LA

pF

Am27S18A/S19A/S18/S19
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
"A" VERSION ADVANCED INFORMATION
Typ
Test Conditions

Description

Parameter
tM

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

A

ACTest Load
(8ee Notes 1-3)

Max

5V25°
STD

A

COM'L
STD

A

MIL
STD

Units

18

25

25

40

35

50

13

15

20

25

25

30

ns

13

15

20

25

25

30

ns

ns

Notes: 1. tM is tested with switch 81 closed and CL = 30pF.
2. For open collector outputs, tEA and t ER are tested with 81 closed to the 1.5V output level. CL = 30pF.
3. For three state outputs, tEA is tested with CL = 30pF to the 1.5V level; 81 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with 81 open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with S1 closed to tho VOL + 0.5V level.

SWITCHING WAVEFORMS

,,0·3
ES

3.0V
1.5V
OV

I

f

I

f--IAA -------i

°0-°7

~IER:J

»»>=::~::;:'

X>--kNv-4
•

I

i
Vcsp

BPM·023

n
BPM·277

2-4

Am27S18A/S19A/S18/S19
APPLYING THE Am27S18A/18 AND Am27S19AI19
The Am27S18A/18 and Am27S19A/19 PROMs may be used as
code converters. Examples include conversion of hexadecimal,
octal of BCD to seven segment display drive format. In many
code conversion applications an extra PROM address input is
available and may be used as a polarity control, blanking control

or code selector input. The use of a single Am27S18A118 or
Am27S19A119 to convert the outputs of a binary counter to
either excess three or gray code format is illustrated below. In
this case both codes are generated in true and complemented
form simultaneously.

TRUTH TABLE

Am25LS2569
4·BIT COUNTER

Y3·Yo
4 ~

CODE SELECT
INPUT

A3· A O

A4l

Csr
;

Am27S18A/18
OR
Am27S19A/19

~l

·t

CODE

CODE

0,-0,

BPM-278

ADDRESS

COMPLEMENT

TRUE

A4 A3 A2 A1 Ao

0 7 0 6 Os 0 4

03 02 0 1 00

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1

1

1

1

0
0

1
1

1
1

1
1

1
1

0
1
0

2-5

1
1
1
1
1
1
1
1
1
1
1
1
1
1

1

1
1
1
1
1
0
0
0
0
0

X
X
X
X
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

1

0

0

0
0
0
0

1
1

1

1
1
1
1
0

X
X
X
X
X
X
1
1
1
1
0
0
0
0
0
0
0
0

0

1

0
0

0

1
1

0

0
0

0

1
X
X
X
X
X
X
1
1
0
0
0
0

1
1
1
1

1
1
1
X
X
X
X
X
X
1
0
0

1
1
0
0

1
1
0
0

0
0
0
0
0

0

1

1

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
X
X
X
X
X
X

0
0
0
0

0
0

0

1
1

0

1
X
X
X
X
X
X

0

0

X
X
X
X
X

X
X
X
X
X
X

0
0
0
0
0
0
0
0

1
1
1
1
1

1

0
0
0
0

0

1

1
1

1 ·0
1 1

1
1

1

1
1

0
0
0
0

1
1
1
1
1
1
1
1
0
0
0
0

X
0
0

1

><

m

en
en

1

-I
::I:

:::c

1

0

m
m
(')

0

C

m

-

1
1

1
1
1
1

0
0

0
0
0
0

0
0

1
1
1
1

0
0

0
0

m
(')

1

1
1

1
1

1
1
0

C)

:::c

>
<

(')

0

C

m

Am27S18A/S19A/S18/S19
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Scottsdale, AZ 85260
Redwood City,
CA94063

Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

Programmer
Model(s)

ModelS, 7, and 9
Systems 17, 19,29 and 100

M9oo, M900B, M910, IM1010
M920, and M980

MPP-80S

UPP-801

UPP-803 PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev W
919-1286-1 Rev H*

PM 9058

IMAMDGEN1

MOD 14

PM 102

FAM-12

PM 2000
Code 90

Am27S18A/18
Am27S19A/19

715-1407-1

PA 16-6and
32x8L

IM32x8-16AMD

SA3-1

DIS-156AM

DA22

AM 11D-2

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

• Rev shown Is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

ORDERING INFORMATION
Order Code

Three-State

Package
Type
(Note 1)

Screening
Flow Code
(Note 2)

Operating
Range
(Note 3)

AM27S19APC
AM27S19APCB
AM27S19ADC
AM27S19ADCB
AM27S19ALC
AM27S19ALCB

P-16-1
P-16-1
D-16-1
D-16-1
L-20-1
L-20-1

C-l
B-1
C-l
B-1
C-l
B-1

COM'L

35ns

AM27S18ADM
AM27S18ADMB
AM27S18AFM
AM27S18AFMB
AM27S18ALM
AM27S18ALMB

AM27S19ADM
AM27S19ADMB
AM27S19AFM
AM27S19AFMB
AM27S19ALM
AM27S19ALMB

D-16-1
D-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
B-3
C-3
B-3
C-3
B-3

MIL

40ns

AM27S18PC
AM27S18PCB
AM27S18DC
AM27S18DCB
AM27S18LC
AM27S18LCB

AM27S19PC
AM27S19PCB
AM27S19DC
AM27S19DCB
AM27S19LC
AM27S19LCB

P-16-1
P-16-1
D-16-1
D-16-1
L-20-1
L-20-1

C-l
B-1
C-l
B-1
C-l
B-1

COM'L

50ns

AM27S18DM
AM27S18DMB
AM27S18FM
AM27S18FMB
AM27S18LM
AM27S18LMB

AM27S19DM
AM27S19DMB
AM27S19FM
AM27S19FMB
AM27S19LM
AM27S19LMB

D-16-1
D-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
B-3
C-3
B-3
C-3
B-3

MIL

Speed
Selection

Open
Collector

25ns

AM27S18APC
AM27S18APCB
AM27S18ADC
AM27S18ADCB
AM27S18ALC
AM27S18ALCB

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-l and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

.......

2-6

Am29750A· Am29751A
256·Bil Generic Series Bipolar PROM

Refer to

Am27S18 • Am27S19
Bipolar Memory PROM Product Specification

The Am29750A is replaced by the Am27S18
(open collector).
The Am29751A is replaced by the Am27S19
(three-state).

2-7

Am27LS18· Am2,7LS19

Low-Power Schottky 256-Bit Generic Series Bipolar PROM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 55ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures.
• 100% MIL-STD-883C assurance testing
• Guaranteed to INT-STD-123

The Am27LS18 and Am27LS19 are high speed electrically
programmable Schottky read only memories. Organized in
the industry standard 32 x 8 configuration, they are available in both open collector Am27LS18 and three-state
Am27LS19 output versions. After programming, stored
information is read on outputs 00-07 by applying unique
binary addresses to Ao-~ and holding chip select input,
CS, at a logic LOW. If either chip select input goes to a logic
HIGH, 00-07 go to the OFF or high impedance state.

BLOCK DIAGRAM

GENERIC SERIES CHARACTERISTICS
The Am27LS18 and Am27LS19 are members of an Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.

AO
32 x 8
FUSE ARRAY

A,
A2

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test words are
pre-programmed during manufacturing to insure extremely
high field programming yields and produce excellent parametric correlation.

A3

TEST WORD 0

A4

TEST WORD 1

Cs

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

BPM-018

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths produCing the
fastest speeds possible from Schottky processed PROMs.

CONNECTION DIAGRAMS
Top Views
DIP

Chip-Pak™

L-20-1
°0

Vee

0,

Cs

°2

A4

OJ

AJ

°4

A2

Os

A,

0

cf

'"

0,

°6

AO

GND

°7

o.

"

0,

"
=::::"~: ««<

XXX*

ov
VO H
1.SV
VOL

Note: Level on output while CS is HIGH is determined extemally.
BPM·021

KEY TO TIMING DIAGRAM
WAVEFORM

-:

JJJJJJ

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

-WAVEFORM

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

l1HK

L

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE.
"OFF" STATE

AC TEST LOAD

vcc~o--S1
R1
300n
OUTPUT

ect

R2
600n

-:..::BPM-022

2-10

Am27LS18/LS19
PROGRAMMING

The Am27LS18 and Am27LS19 are manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the device, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS input is at a logic HIGH. Current
is gated through the addressed fuse by raising the CS input
from a logic HIGH to 15 volts. After 50 p'sec, the 20 volt supply is removed, the chip enabled, and the output level sensed
to determine if the link has opened. Most links will open within
50 p.sec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5 msec. If a link has not
opened after a total elapsed programming time of 400 msec,
further programming of the device should not be attempted.
Successive links are programmed in the same manner until all
desired bit locations have been programmed to the HIGH
level.
Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which

the current drops to approximately 40mA. Current into the CS
pin when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to
the large currents being passed. Programming cycles should
not be applied to one device more than 5 seconds to avoid
heat damage. If this programming time is exceeded, all power
to the chip including Vcc should be removed for a period of 5
seconds after which programming may be resumed.
When all programming has been completed, the data content
of the memory should be verified by sequentially reading all
words. Occasionally this verification will show that an extra
undesired link has been fused. Should this occur, immediately
check the programming equipment to make sure that all device pins are firmly contacting the programming socket, that
the input signal levels exhibit sufficient noise margins, and
that the programming voltages are within the specified limits.
All of these conditions must be maintained during programming. AMD PROMs are thoroughly tested to minimize unwanted fusing; fusing extra bits is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Parameter

Min

Max

Units

Vccp

Vcc During Programming

5.0

5.5

Volts

V 1HP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

Vcsp

CS Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

0

Vccp+0.3

Volts

10NP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

d(Vcs)/dt

Description

tp

20

mA

20

250

V//-Lsec

Rate of CS Voltage Change

100

1000

V//-Lsec

Programming Period - First Attempt

50

100

/-Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
2. Delays t1, t2, t3 and t4 must be greater than 100 ns; maximum delays of 1 /-Lsec are recommended to minimize heating during
programming.
3. During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses
are required.
4. Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM
Vecp

:x.

A~~~~~~"I

ENAB~
PROGRAMMED
OUTPUT

'C VILP
1 '

SELECTED ADDRESS STABLE

-

%(VCSI-=--y1h

-1h' ~ "
--I

I

I

VIHP

~~

r

1\

_13

~~~
PROGRAMMING CYCLE

~o-

I ''''

~4
Iv

=: :

\lU::~
-

I -

Am27LS18
OR
Am27LS19

VIHP

I

I

I

i

~

v

VCSP

OL

BPM·023

SL

SL

VOP

BPM·024

2-11

Am27LS18/LS19
PROGRAMMING EQUIPMENT
Generic programming boards and device adapters are available from the sources listed below. In each case, the programming boards are used in these manufacturer's automatic
SOURCE AND LOCATION

programmers to program all AMD generic series bipolar
PROMs; individual adapters are required for each basic part
type in the series.

Data 1/0 Corp.
P.O. Box 308
Issaquah, Wash. 98027

Pro-Log Corp.
2411 Garden Road
Monterey, Ca. 93940

PROGRAMMER MODEL(S)

Model 5, 7 and 9

M900 and M920

AMD GENERIC BIPOLAR
PROM PERSONALITY BOARD

909-1286-1

PM9058

Am27LS18· Am27LS19
ADAPTERS AND
CONFIGURATORS

715-1407-1

PA16-6 and 32 x 8 (L)

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can
be delivered with your order or may be transmitted over a
TWX machine or time-sharing terminal. ASCII 8PNF is our
preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a. truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

ASCII BPNF
An example of an ASCII tape in the 8PNF format is shown
below. They can be punched on any Teletypeil!l or on a TWX
or Telex machine. The format chosen provides relatively good
error detection. Paper tapes must consist of:

3. A trailer of at least 25 rubouts.

1. A leader of at least 25 rubouts.
2. The data patterns for all 32 words, starting with word 0, in the
following format:
a. Any characters, including carriage return and line feed,
except "8".
b. The letter "8", indicating the beginning of the data
word.
c. A sequence of eight Ps or Ns, starting with output 0 7 ,
d. The letter "F", indicating the finish of the data word.
e. Any text, including carriage return and line feed, except
the letter "8".

A convenient pattern to use for the data words is to prefix the
word (or every few words with the word number, then type the
data word, then a comment, then carriage return and line feed
as shown below. There must be no characters between the 8
and the F except for the eight Ps and Ns. If an error is made
in a word, the entire word must be cancelled with rubouts
back to the letter 8, then the word re-typed beginning with the
8.

A P is a HIGH logic I.evel = 2.4 volts.
An N is a LOW logic level = 0.4 volts.

When TWXing your tape, be sure the tape is in even parity.
Parity is not necessary if the tape is mailed.

TYPICAL PAPER TAPE FORMAT
¢¢¢
¢¢2
¢¢4

BPNPPNNNPF
BPPPPPPNNF
BNNNPPPPNF
BNNNNNNNNF
BPNNNNNNPF
BNPPNPPNNF

¢~6

~~::~

¢31

BNNNNPPPNF

WORD ZERO®

RESULTING DEVICE TRUTH TABLE (CS

©

~iINTiIELD~@

TEX'I R

L

CAN R L
GO R

L
~E R @

EN°D ® @

@a CARRIAGE RETURN

(0= LINE FEED

= LOW)

A4

A3

A2

A,

Ao

07

Os

Os

04

03

02

0,

00

L

L
L
L
L
H
H
H

L

L
H

H

H

H
H

L
L
L
H
L

H

L
H

L
L
L
H

L
L
H
H

L
H
H
L
L
H
H

H

H

L
H
H

L

L
L
L
L
L
L

L
L
L
L
L
L
L

L
L
L
L

L
L
L
H
L
L

H

H

H

L

L

H

H

H

L

L
L
H

L
H
L
H
L

L
L
H
H

L
H
L
L
L
H
L

H

H

L

L

L
H
H

H

L

ASCII PAPER TAPE
rASClI'B'

f
.......... ~::::;~ ~ ~ ~ ..... ~ ::::;;;;~ ~ :..................... /
LEADER

/

ASCIl
'F'

[B'

,,.. WORD '0'

00000

o

00000

~

TRAILER

WORD'"

0000000

0

L

00000

8P'sORN's

LLF

OPTIONAL COMMENTS MAY BE INSERTED HERE

2-12

BPM·025

Am27LS18/LS19
APPLYING THE Am27LS18 AND Am27LS19
The Am27LS18 and Am27LS19 PROMs may be used as code
converters. Examples include conversion of hexadecimal,
octal or BCD to seven segment display drive format. In many
code conversion applications an extra PROM address input is
available and may be used as a polarity control, blanking con-

trol or code selector input. The use of a single Am27LS18 or
Am27LS19 to convert the outputs of a binary counter to either
excess three or gray code format is illustrated below. In this
case both codes are generated in true and complemented
form simultaneously.

TRUTH TABLE

Am25LS2569
4-BIT COUNTER

Y3' YO

4

CODE SELECT
INPUT

A3· A O

A41

csr

Am27LS18!
Am27LS19

O,<>l
CODE

,t

0,-0,

CODE

BPM·026

ADDRESS

COMPLEMENT

TRUE

A4 A3 A2 A1 Ao

0 7 Os Os 0 4

03 02 01 00

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

2-13

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1

1

0

0

0
0
0
0

1
1

1

0 1
0 1
0 1
0 1
0 0
X X
X X
X X
X X
X X
X X
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1

0
0

0
1

o·

1
1

1

0

0
0

0

1

1

1

X X
X X
X X
X X
X X
X X
1
1

0
0
0
0
1
1
1
1

0
0
0
0
1
1

1

0
0
1
1

0
0
1
1

0
0
1
1

0
0
1

0
0
0
0
0

0

1

1

1
1
1
1

0
0

0

1
1

0

1
1
1
1
1

0
0
0
0

0
0

0

1
1

0

1

X
X
X
X
X
X
0
0
0
0
0
0
0
0

X
X
X
X
X
X
0
0
0
0

0
X
X
X
X
X
X
0
0

0
m
X
0
0
X
C
m
X
X
X
X
I--0

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0

1
1
1
1

0
0
0
0
1
1
1
1

0
0

1
1
1
1

m

><
0

m

en
en

-t

:J:
::0

m

1
1

0
0
1
1

0
0
1
1

0
0
1
1

0

C)

::0

»

-<
0

0

C

m

Am27S18A/S19A/S18/S19
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
7335 E. Acoma Dr.
630 Price Avenue
Redwood City,
Scottsdale, AZ 85260
CA94063

Source and
Location

DataI/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

Programmer
Model(s)

M900, M900B, M910, IM1010
Model 5, 7, and 9
Systems 17, 19,29 and 100 M920, and M9S0

MPP-SO

UPP-S01

UPP-S03 PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-12S6-1 Rev HO
919-12S6-1 Rev HO
Unipak Rev HO
(Code 1602)

PM 9058

IMAMDGEN1

MOD 14

PM102

FAM-12

PM 2000
Code 90

Am27LS1S/19

715-1407-1

PA 16-6and
32xS(L)

IM32xS-16-AMD

SA3-1 B32x8/16

DIS-156AM

DA-22

AM110

"Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM27LS19PC
AM27LS19PCB
AM27LS19DC
AM27LS19DCB
AM27LS19LC
AM27LS19LCB

P-16-1
P-16-1
D-16-1
D-16-1
L-20-1
L-20-1

C-1
B-1
C-1
B-1
C-1
8-1

COM'L

D-16-1
D-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

55ns

AM27LS18PC
AM27LS18PCB
AM27LS18DC
AM27LS18DCB
AM27LS18LC
AM27LS18LCB

75ns

AM27LS18DM
AM27LS18DM8
AM27LS18FM
AM27LS18FM8
AM27LS18LM
AM27LS18LM8

AM27LS19DM
AM27LS19DM8
AM27LS19FM
AM27LS19FM8
AM27LS19LM
AM27LS19LM8

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-14

Am27S20A • Am27S21A
Am27S20 • Am27S21
1024·Bit Generic Series Bipolar PROM
(256 x 4 bits with ultra fast access time)
"A" VERSION ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 30ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures
• 100% MIL-STO-883C assurance testing
• Guaranteed to INT-STO-123

The Am27S20A/20 and Am27S21A/21 are high speed
electrically programmable Schottky read only memories.
Organized in the industry standard 256 x 4 configuration,
they are available in both open collector Am27S20A/20 and
three-state Am27S21A/21 output versions. After programming, stored information is read on outputs 00-03 by applying unique binary addresses to Ao-A7 and holding chip
select inputs, CS1 and CS2, at a logic LOW. If either chip
select input goes to a logic HIGH, 00-03 go to the OFF or
high impedance state.
BLOCK DIAGRAM
COLUMN TEST RAIL

A7

GENERIC SERIES CHARACTERISTICS

32 x 32
FUSE ARRAY

As
As

The Am27S20N20 and Am27S21N21 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.

A4
A3
TESTWORDO
TEST WORD 1

All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test words are
pre-programmed during manufacturing to insure extremely
high field programming yields, and produce excellent parametric correlation.

BPM·027

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

CONNECTION DIAGRAMS - Top Views
Chip-Pak™
L-20-1

DIP

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.

Vee

A,

A4

cs,

-'3

CS,

...

°0
0,

°2

A,
A,

°3

BPM-029

cf

cf
BPM-273

Note: Pin 1 is marked for orientation.
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-15

Am27S20A/S21A/S20/S21
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30to +5mA

LOGIC SYMBOL

OPERATING RANGE
Temperature
AO
Al
A2
A3
A4
A5
Ae
A7

Te = -55to +125°C

15

256.4
PROM

14
13

Vee = Pin 16
GND = PinS

12

11

10

BPM·028

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH (Note 2)

Output HIGH Voltage

Vee = MIN, IOH
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

IIH

Input HIGH Current

Ise(Note2)

Output Short Circuit Current

lee

Power Supply Current

VI

Input Clamp Voltage

Min

= -2.0mA

(Note 1)

204
0045
2.0

= MAX, VIN = OA5V
= MAX, VIN = 2.7V
Vee = MAX, VOUT = O.OV (Note 4)
All inputs = GND
Vee = MAX
Vee = MIN, liN = -1SmA

Output Leakage Current

Vee = MAX
Vcs, = 2AV

= 2.0V @ f = 1MHz (Note 5)
= 1MHz (Note 5)

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT = 2.0V @f

Vo

Volts

-0.250

mA
/LA

-40

-90

mA

100

130

mA

-1.2

Volts

40
40

Vo= 2AV
(Note 2)

O.S

25

Vee

-20

Volts
Volts

-0.010

Vee

Units
Volts

V07" 4.5V
leEX

Max

= OAV

/LA

-40
4
pF
S

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to
test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but are periodically sampled.

2-16

Am27S20A/S21A/S20/S21
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
"A" VERSION ADVANCED INFORMATION
Typ

Max

5V 25°C

Parameter
tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(See Notes 1-3)

COM'L
STD

A

MIL
STD

A

STD

A

20

25

30

45

40

60

ns

15

15

20

20

25

30

ns

15

15

20

20

25

30

ns

Test Conditions

Description

Units

Notes: 1. tAA is tested with switch Sl closed and CL = 30pF.
2. For open collector outputs, tEA and t ER are tested with Sl closed to the 1.5V output level. CL = 30pF.
3. For three state outputs, tEA is tested with CL = 30pF to the 1.5V level; Sl is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with Sl open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with Sl closed to the VOL + 0.5V level.

SWITCHING WAVEFORMS

Note: Level on output while either CS is HIGH is determined externally.

BPM-030

KEY TO TIMING DIAGRAM
WAVEFORM

-a
JJJIff

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

-WAVEFORM

11HR

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

WILL BE
CHANGING
FROM L TO H

ACTESTLOAD

R1

300n

OUTPUT 0 - - -......- - - . . .

eLI

R2

600n

BPM-031

2-17

Am27S20A/S21A/S20/S21
PROGRAMMING

the current drops to approximately 40mA. Current into the CS1
pin when it is raised to 15 volts is typically 1.5mA.

The Am27S20A/20 and Am27S21A/21 are manufactured with a
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. To program the
device, the fusible links are selectively opened.

The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS1 input is a logic HIGH. Current is
gated through the addressed fuse by raising the CS1 input from
a logic HIGH to 15 volts. After 50/-Lsec, the 20 volt supply is removed, the chip is enabled, and the output level is sensed to
determine if the link has opened. Most links will open within
50/-Lsec. Occassionlly a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit locations have been programmed to the HIGH level.

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be
approximately 140mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Description

Parameters

Min

Max

Units

Vccp

Vcc During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

Vcsp

CS1 Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

VONP

Voltage on Outputs Not to be Programmed

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

tp

Vccp

Volts

+ 0.3

Volts

20

rnA

20

250

V/f-Lsec

Vlf-Lsec

100

1000

Programming Period - First Attempt

50

100

f-Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

Rate of CS1 Voltage Change

d(Vcs)/dt

Notes: 1.
2.
3.
4.

0

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of 1f-Lsec are recommended to minimize heating during programming.
During t y , a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM

Vccp

I
CSt

h
t

PROGRAMMED
OUTPUT

'2

Ip

_'J

~4
IV

csr
_

' - - - ..'!.dl (Vop)

-,

I

"

OUTPUT::

Vop

CS t

~()-<
Am27S20/20A
OR

Am27S21/21A

-

!

~o-

~o-

~

V
OH

\"y'E.!!!!'lu_ VOL
PROGRAMMING CYCLE

Joon

~

AO-A7Q
ENABLE

YONP

R·

I

Ycsp

BPM-032

11

11

-=-

-=-

Vop

BPM-274

2-18

Am27520A/S21A/S20/S21
APPLYING THE Am27S20A/20 AND Am27S21A/21

Typical application of the Am27S20A/20 and Am27S21A/21 is
shown below. The Am27S20A/20 and the Am27S21A/21 are
employed as mapping ROMs in a microprogram computer control unit. The eight-bit macroinstruction from main memory is
brought into the AO-A? inputs of the mapping ROM array. The
instruction is mapped into a 12-bit address space with each
PROM output supplying 4 bits. The 12 bits of address are then
supplied to the "0" inputs of the Am2910 as a possible next

address source for microprogram memory. The MAP output of
the Am2910 is connected to the CS1 input of the Am27S20A/
20/21A/21 such that when the CS1 input is HIGH, the outputs of
the PROMs are either HIGH in the case of the Am27S20A/20 or
in the three-state mode in the case of the Am27S21A/21. In both
cases the CS2 input is grounded; thus data from other sources
are free to drive the 0 inputs of the Am2910 when MAP is HIGH;

OTHER DATA INPUTS

'/
, "-

,

,

'I' 'I"

'I' ' / ,

Ao

/

Al
A2
MACRO
INSTRUCTION
OF CODE

A3

<

00

A4 Am27~~OA/20 01
AS Am27S21A/21 O2
AS

03

A7

-f

Csl
Cs2

-DO

~Ao

- 01

- I - - - Al

O2
03

A2
00

04

A4 Am27S20A/20 01

Os

Am27~~lA/21 02

Os

03

07

A3

AS
AS

Am2910
MICROPROGRAM

Y O- ll

~ MEMORY
AOORESS

08

A7

Cs1

-

~Cs2

-

09
0 10
0 11

MAP
_AO
' - - - Al
A2
00
A4 Am27g~OA/20 0 1

A3

AS Am27S21A/21 O2
AS

03

A7

.r

Csl

Cs2

MICROPROGRAMMING INSTRUCTION MAPPING

2-19

BPM-275

Am27S20A/S21A/S20/S21
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

DataI/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29 and 100

M900, M900B, M910, IM1010
M920, and M9S0

MPP-80

UPP-801

UPP-803

PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev H·
919-1286-1 Rev H·

PM 9058

1M AMDGEN1

MOD14

PM 102

FAM-12

PM 2000
Code 90

Am27S20A/21A
Am27S20/21

715-1408-1

PA 16-5 and
256x4(L)

IM256x4-16AMD

SA4-2

DIS-133 AM

DA 21

AM130-2

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City,
Scottsdale, AZ 85260
CA94063

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

·Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched .paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM27S21APC
AM27S21 APCB
AM27S21AOC
AM27S21 AOCB
AM27S21ALC
AM27S21 ALCB

P-16-1
P-16-1
0-16-1
0-16-1
L-20-1
L-20-1

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

AM27S21 ADM
AM27S21 AOM8
AM27S21AFM
AM27S21 AFMB
AM27S21ALM
AM27S21ALMB

0-16-1
0-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
8-3
C-3
8-3
C-3
8-3

MIL

45ns

AM27S20PC
AM27S20PC8
AM27S200C
AM27S200CB
AM27S20LC
AM27S20LC8

AM27S21PC
AM27S21 PCB
AM27S21DC
AM27S210C8
AM27S21LC
AM27S21LC8

P-16-1
P-16-1
0-16-1
0-16-1
L-20-1
L-20-1

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

60ns

AM27S200M
AM27S200MB
AM27S20FM
AM27S20FM8
AM27S20LM
AM27S20LM8

AM27S21OM
AM27S210M8
AM27S21FM
AM27S21FM8
AM27S21LM
AM27S21LM8

0-16-1
0-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

30ns

AM27S20APC
AM27S20APCB
AM27S20AOC
AM27S20AOCB
AM27S20ALC
AM27S20ALCB

40ns

AM27S20AOM
AM27S20AOMB
AM27S20AFM
AM27S20AFMB
AM27S20ALM
AM27S20ALMB

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STO-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STO-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commerCial and military specifications. Pad layout and bonding
diagram available upon request.

2-20

Am29760A • Am29761A
1024·Bit Generic Series Bipolar PROM

Refer to

Am27S20 • Am27S21
Bipolar Memory PROM Product Specification

The Am29760A is replaced by the Am27S20
(open collector).
The Am29761A is replaced by the Am27S21·
(three-state).

2-21

Am27S 12A • Am27S 13A
Am27S12 • Am27S 13
2048·Bit Generic Series Bipolar PROM
(512 x 4 bits with ultra fast access timeJ
"A" VERSION ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 30ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures
• 100% MIL-STD-883C assurance testing
• Guaranteed toINT-STD-123

The Am27S12A/12 and Am27S13A/13 are high speed
electrically programmable Schottky read only memories.
Organized in the industry standard 512 x 4 configuration,
they are available in both open collector Am27S12A/12 and
three-state Am27S13A113 output versions. After programming, stored information is read on outputs 00-03 by applying unique binary addresses to Ao-As and holding the
chip select input, CS, at a logic LOW. If the chip select input
goes to a logic HIGH, 00-03 go to the off or high impedance state.

BLOCK DIAGRAM
COLUMN TEST RAIL

A8
A,

GENERIC SERIES CHARACTERISTICS

64x32
FUSE ARRAY

As

The Am27S12A/12 and Am27S13A/13 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.

A5
A,
TEST WORD 0

A3
TEST WORO 1

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test words are
pre-programmed during manufacturing to insure extremely
high field programming yields, and produce excellent parametric correlation.

BPM-001

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

CONNECTION DIAGRAMS - Top Views
Chip-Pak TIl
L-20-1

DIP
~

Vee

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.

~

Jl ...-

A7
A.

A,

A3

cs

Ao

00

A8

cs
00

A,

0,
0,

A,

02
03

B

0'

Note: Pin 1 is marked for orientation.
BPM-003

BPM-263

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-22

Am27S12A/S13A/S12/S13
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8) Coritinuous

-0.5to +7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5V to + VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +S.SV

DC Input Current

-30 to +SmA

OPERATING RANGE

Vee

LOGIC SYMBOL

Temperature

4.75 to 5.25V
4.5t05.5V

Te = -55to

+ 125°C

15
14
13

AO
A1
A2
A3
A4
As
As
A7
As
CS

512x4
PROM

00

01

°2

03

I I I I

12

11

10

Vee = Pin 16
GND= PinS
BPM·002

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Min

Test Conditions

VOH (Note 2)

Output HIGH Voltage

Vee = MIN, IOH
VIN = VIH or VIL

= -2.0mA

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee = MAX, VIN = OA5V

IIH

Input HIGH Current

Vee = MAX, VIN = 2.7V

Ise (Note 2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

Icc

Power Supply Current

All inputs = GND
Vee = MAX

VI

Input Clamp Voltage

Vee = MIN, liN

(Note 1)

2.4
0045

2.0

Output Leakage Current

Vee = MAX
V6S = 2A\t

O.S

Volts

-0.250

rnA

25

J,LA

-40

-90

rnA

100

130

rnA

-1.2

Volts

= -1SmA

(Note 2)

Volts
Volts

-0.010

-20

Units
Volts

40

Vo = 4.5V
leEX

Max

Vo = 2AV

40

Vo = OAV

-40

CIN

Input Capacitance

VIN = 2.0V @f = 1MHz (Note 5)

4

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 5)

S

J,LA

pF

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to
test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but are periodically sampled.

2-23

Am27S12A/S13A/S12/S13
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
"A" VERSION ADVANCED INFORMATION
Typ
Parameter

Description

tAA

Address Access Time

tEA

Enable Access Time

tEA

Enable Recovery Time

Test Conditions
AC Test Load
(See Notes 1-3)

Max

5V25°C
STD
A

A

COM'L
STD

20

30

30

50

40

60

15

15

20

25

25

30

ns

15

15

20

25

25

30

ns

A

MIL
STD

Units
ns

Notes: 1. tAA is tested with switch S1 closed and CL = 30pF.
2. For open collector outputs, tEA and tEA are tested with S1 closed to the 1.5Voutput level. CL = 30pF.
3. For three state outputs, tEA is tested with CL = 30pF to the 1.5V level; S1 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tEA is tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with S1 closed to the VOL + O.5V level.

SWITCHING WAVEFORMS

A.A,

cs

3~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-=

I-----

~'--=-_=__=__=__=__=_~ :~v

---;1-----------/
_~-..--tAA~---1~--__r_f--T""I""'rtER:J

0
00- 3

:ov:

~tEA-i

=---'-XXX*~===-l...l_L..l.JH+ffir+--*-::~:-o~~:v+f-f-1@(H-:::
Note: Level on output while CS is HIGH is determined externally.
BPM·004

KEY TO TIMING DIAGRAM
WAVEFORM

--

JJJJJJ

INPUTS

OUTPUTS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

.JJl//1

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

}J}-+g

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

vcc~o-81

R1

300!!

----.. .
cl 1

OUTPUT 0 - - -

I

R2
600!!

BPM·005

2-24

Am27S12A/S13A/S12/S13
PROGRAMMING

The Am27S12A/12 and Am27S13A/13 are manufactured with a
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. To program the
device, the fusible links are selectively opened.

the current drops to approximately 40mA. Current into the CS
pin when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to the
memory output after the CS input is a logic HIGH .. Current is
gated through the addressed fuse by raising the CS input from a
logic HIGH to 15 volts. After 50lLsec, the 20 volt supply is
removed, the chip is enabled and the output level is sensed to
determine if the link has opened. Most links will open within
50lLsec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be
approximately 140mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Min

Max

Units

Vccp

Vcc During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCSP

CS Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

0

Vccp + 0.3

Volts

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

d(Vcs)/dt

Rate of CS Voltage Change

Description

Parameters

tp
Notes: 1.
2.
3.
4.

20

mA

20

250

V/p..sec

100

1000

V/p..sec

Programming Period - First Attempt .

50

100

p..sec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1, t2, lJ and t4 must be greater than 100ns; maximum delays of 1p..sec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

SIMPLIFIED PROGRAMMING DIAGRAM

PROGRAMMING WAVEFORMS

ADDRESS
INPUTS

=x

x=

ADDRESS
STABLE
_ _ _ _ SELECTED
___
___
_____

V,HP
V,LP

cs
ENABLE

PROGRAMMED
OUTPUT
"

OUTPUT"

\.:!..E~l.JJ_

-----1·1

VOL

BPM-006

2-25

BPM-264

Am27S12AjS13AjS12jS13
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data 1/0
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

Programmer
Model(s)

Model 5, 7. and 9
Systems 17, 19.29 and 100

AMDGeneric
Bipolar PROM
Personality
Module
Am27S 12A/13A
Am27S12/13

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ 85260

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

M900, M900B, M910, IM10l0
M920, and M980

MPP-80

UPP-801

UPP-803

PPX

909-1286-1 Rev W
919-1286-1 Rev H*

PM 9058

IMAMDGENl

MOD 14

PM 102

FAM-12

PM 2000
Code 90

715-1408-2

PA 16-5and
512x4(L)

IM512x4-16-AMD

SA4-1

DIS-134AM

DA-21

AM130-3

*Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

APPLYING THE Am27S12A/12 AND Am27S13A/13
The Am27S12A/12 and Am27S13A/13 can be used with a high
speed counter to form a pico-controller for microprogrammed
systems. A typical application is illustrated below wherein a multiplexer, under control of one of the PROMs, is continuously
sensing the CONDITIONAL TEST INPUTS. When the selected
condition occurs, a HIGH signal will result at the multiplexer

output causing a predetermined branch address to be loaded
into the parallel inputs of the counters on the next clock
pulse. The counter then accesses the preprogrammed data or
control information sequence from the Am27S 12A/12 or
Am27S13A/13 PROMs.

CONDITIONAL TEST INPUTS
01234567

SEL

.--------------7''-------1

'HIGH'

Am74S151
MULTIPLEXER

w
BRANCH

CLOCK

OUTPUT BITS FOR DATA OR CONTROL

BPM·009

2-26

Am27S12A/S13A/S12/S13
ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM27S13APC
AM27S13APC8
AM27S13ADC
AM27S13ADC8
AM27S13ALC
AM27S13ALC8

P-16-1
P-16-1
D-16-1
D-16-1
L-20-1
L-20-1

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

AM27S13ADM
AM27S13ADM8
AM27S13AFM
AM27S13AFM8
AM27S13ALM
AM27S13ALM8

D-16-1
D-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
8-3
C-3
8-3
C-3
8-3

MIL

50ns

AM27S12PC
AM27S12PC8
AM27S12DC
AM27S12DC8
AM27S12LC
AM27S12LC8

AM27S13PC
AM27S13PC8
AM27S13DC
AM27S13DC8
AM27S13LC
AM27S13LC8

P-16-1
P-16-1
D-16-1
D-16-1
L-20-1
L-20-1

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

60ns

AM27S12DM
AM27S12DM8
AM27S12FM
AM27S12FM8
AM27S12LM
AM27S12LM8

AM27S13DM
AM27S13DM8
AM27S13FM
AM27S13FM8
AM27S13LM
AM27S13LM8

D-16-1
D-16-1
F-16-1
F-16-1
L-20-1
L-20-1

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

30ns

AM27S12APC
AM27S12APC8
AM27S12ADC
AM27S12ADC8
AM27S12ALC
AM27S12ALC8

40ns

AM27S12ADM
AM27S12ADM8
AM27S12AFM
AM27S12AFM8
AM27S12ALM
AM27S12ALM8

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-27

Am29770 • Am29771
2048· Bit Generic Series Bipolar PROM

Refer to

Am27S12 • Am27S13
Bipolar Memory PROM Product Specification

The Am29770 is replaced by the Am27S12
(open collector).
The Am29771 is replaced by the Am27S13
(three-state).

2-28

Am27S15

4096·Bit Generic Series Bipolar PROM
(512 x 8 Bits with Output Data Latches)

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• On-chip data latches
• Latched true and complemented output enables for
easy word expansion
• Predetermined OFF outputs on power-up
• Plug-in replacement for the 82S115
• Fast access time - 60ns commercial and 90ns
military maximum
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ > 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing
extremely flat AC performance over military range
• Member of generic PROM series utilizing standard
programming algorithm
• 100% MIL-STD-883C assurance testing
• Guaranteed to INT-STD-123

The Am27S15 is an electrically programmable Schottky
read only memory incorporating on-Chip data and enable
latches. The device is organized as 512 words of 8 bits and
features three-state outputs with full 16mA drive capability.
When in the transparent mode, with the strobe (ST) input
HIGH, reading stored data is accomplished by enabling the
chip (E1 LOW and E2 HIGH) and applying the binary word
address to the address inputs, AD-As. In this mode,
changes of the address inputs cause the outputs, 00-07,
to read a different stored word; changes of either enable
input level disable the outputs, causing them to go to the
high impedance state.
Dropping the strobe input to the LOW level places the device in the latched mode of operation. The output condition
present (reading a word of stored data or disabled) when
the strobe goes LOW remains at the outputs, regardless
of further address or enable transitions, until a positive
(LOW to HIGH) strobe transition occurs. With the strobe
HIGH, 00-07 again respond to the address and enable
input conditions.

If the strobe is LOW (latched mode) when VCC power is first
applied, the outputs will be in the disabled state, eliminating
the need for special "power-up" design prec~lUtions.
BLOCK DIAGRAM

GENERIC SERIES CHARACTERISTICS
This 4K PROM is a member of an Advanced PROM series
incorporating common electrical characteristi,cs and programing procedures. All parts in this series are produced
with a fusible link at each memory location storing a logic
LOW and can be selectively programmed to a logic HIGH
by applying appropriate voltages to the circuit.

COLUMN TEST RAIL

AO
A,
A,

64.64
PROGRAMMABLE
ARRAY

A3

A.

TEST WORD 0

A5

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test words are
pre-programmed during manufacturing to insure extremely
high field programming yields, and produce excellent
parametric correlation.
Platinum-Silicide was selected as the fuse link matj3rial to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long-term reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

A.
A,

A.

BPM-012

CONNECTION DIAGRAM - Top View

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.
BPM-011

Note: Pin 1 is marked for orientation. NC"" No connection.

2-29

Am27S15
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5to +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE

Vee

LOGIC SYMBOL

Temperature

4.75 to 5.25V
4.5 to 5.5V

21 22 23

1

2

3

4

5

6

Te = -55to +125°C
20

E,

19

E2

18

ST

7

BPM·OIO

8

9 10 14 15 16 17

Vee = Pin 24
GND = Pin 12
(Pins 11 and 13 open)

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions
Vee = MIN, IOH = -2.0mA
VIN = VIH or VIL

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

IIH

Input HIGH Current

MIL

204

Max

2.0
COM'L

0.85

MIL

0.80

Volts
COM'L

-0.100

MIL

-0.150

rnA
25

Vee = MAX, VOUT = O.OV
(Note 2)

-70

MIL

-15

-65

All Inputs = GND
Vee = MAX

COM'L

125

175

MIL

125

185

VI

Input Clamp Voltage

Vee = MIN, liN = -18mA

leEX

Output Leakage Current

Vee = MAX,
VE1 = 204V
VE 2 = Oo4V

CIN

Input Capacitance

Volts
Volts

-20

Power Supply Current

Units
Volts

COM'L

IcC

Notes: 1.
2.
3.
4.

2.7

Vee = MAX, VIN = 2.7V

Output Short Circuit Current

Output Capacitance

COM'L

(Note 1)

0.5

Vee = MAX, VIN = Oo45V

Ise

COUT

Min

p.,A
rnA

rnA
1.2
Vo= 4.5V

40

Vo = Oo4V

-40

VIN = 2.0V @ f = 1MHz (Note 3)

5

VOUT = 2.0V @f = 1MHz (Note 3)

12

p.,A

pF

Typical limits are at Vee = 5.0Vand TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

2-30

Volts

Am27S15
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COM'L

Typ.
Parameter
tpHdA)
tpLH(A)

Test Conditions

Description
Transparent Mode Address to
Output Access Time

tw(S)

Strobe Pulse Width (HIGH)
Address to Strobe (LOW) Set-up Time

tH(A)

Address to Strobe (LOW) Hold Time

ts(E 1)
ts(E 2)

Enable to Strobe (LOW) Set-up Time

tH(E 1)
tH(E 2)

Enable to Strobe (LOW) Hold Time

tPZH@'1. E 2)
tpzdE 1.E2)

Transparent Mode Enable to
Output Enabled (HIGH or LOW) Time

C L = 30pF
S1 Closed for tpZL.
& Open for tpZH

tpHZ(S)
tpLZ(S)

Strobe Delatch (HIGH) to Output
Disabled (OFF or HIGH impedance) Time

CL = 5pF (Note 2)

CL = 30pF
S1 Closed
(See AC Test
Load Below)

Min.

Max.

Units

90

ns

60

10

30

40

35

60

90

ns

-10

0

5

ns

40

50

ns

10

10

ns

0

Transparent Mode Enable to Output
Disabled (OFF or high impedance) Time

MIL

Max.

35

ts(A)

tI?HZ(§1. E2)
tpLZ(E 1.E2)

Min.

(Note 1)

20

S1 closed for tpLZ
& Open for tpHZ

20

ns

40

50

ns

35

45

ns

40

50

ns

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. tpHZ and tpLZ are measured to the VOH - 0.5V and VOL + 0.5V output levels respectively. All other switching parameters are tested
from and to the 1.5V threshold levels.
3. Tests are performed with input rise and fall times (10% to 90%) of 5ns or less.

SWITCHING WAVEFORMS
TRANSPARENT READ

LATCHED READ
3V
1.SV

ov
3V
1.SV
OV

?j
r=,,"A'

T

1.SV
OV

,"lA' =1

=r\
f
E"""--1-,"1-",=:J-""~!"I
:H
\1=. . ,,,.
!--.",IA';;j
ts(E2)

3V

X

tH(E2)

tplZ(El)

tplH(A)

tPlZ(E2)

VO H

.5V

I

1.SV
VOL

.5V
I=tPHZ(S)
tplZ(S)

t:tW(S)=i
3V
1.SV

ST -

OV

~\

AC TEST LOAD

BPM·013

KEY TO TIMING DIAGRAM
WAVEFORM

Rl

30011
OUTPUT

l:

f

0----.---..
R2

600n

-JJIJJJ

BPM·014

2-31

INPUTS

OUTPUTS

MUST BE
STEADY

Will BE
STEADY

MAY CHANGE
FROM H TO l

Will BE
CHANGING
FROM H TO l

MAY CHANGE
FROM l TO H

WilL BE
CHANGING
FROM l TO H

-WAVEFORM

H

INPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

DOES NOT
APPLY

OUTPUTS

CHANGING;
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

Am27S15
PROGRAMMING
The Am27S15 is manufactured with a conductive PlatinumSilicide link at each bit location. The output of the memory with
the link in place is LOW. To program the device, the fusible links
are selectively opened.

the current drops to approximately 40mA. Current into the
pin when it is raised to 15 volts is typically 1.5mA.

E1

The memories may become hot during programming due to
the large currents being passed. Programming cycles should
not be continuously applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip including V cc should be removed for a period of 5 seconds after which programming
may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to the memory output after the E1 input is at a logic HIGH. Current is gated
through the addressed fuse by raising the E1 input from a logic
HIGH to 15 volts. After 50,usec, the 20 volt supply is removed,
the chip is enabled and the output level sensed to determine
if the link has opened. Most links will open within 50,usec. Occasionally a link will be stronger and require additional
programming cycles. The recommended duration of additional
programming periods is 5msec. If a link has not opened after
a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming eqUipment problems.

Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Parameter

Min.

Max.

Units

Vccp

V cc During Programming

Description

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VENP

E1 Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

0.0

Vccp+0.3

Volts

IONP

Current into Outputs Not to be Programmed

20

mA

d(Vop)/dt

Rate of Output Voltage Change

20

250

V/,usec

d(VEN)/dt

Rate of E1 Voltage Change

100

1000

V/,usec

Programming Period - First Attempt

50

100

,usec

Programming Period - Subsequent Attempts

5.0

15

msec

tp

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; Le., not to the midpoints.
2. Delays t1 through t4 must be greater than 100ns; maximum delays of 1,usec are recommended to minimize heating during programming.
3. During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses
are required.
4. Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM
Vccp

ADDRESS
INPUTS

--V
---h._____S_EL_ECT_ED_A_D_D_RE_S_SS_T_AB_L_E_ _ _ _V-A.-

VIHP
VILP

El
ENABLE

PROGRAMMED
OUTPUT
,

OUTPUT

II

\..!.E.!!!.'!..U_

-----11

VOL

BPM-015

2-32

BPM-016

Am27S15
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

DataI/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ 85260

Programmer
Model(s)

ModelS, 7, and 9
Systems 17, 19,29 and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev G*
919-1286-1 Rev G*

PM 9058

IMAMDGEN1

MOD14

PM 102

FAM-12

Am27S15

715-1411-1

PA24-14 and
512x8(L)

1M 512 x 8-2427S15-AMD

SA 17-3B512x8/24

DIS-165AMD

DA33

r-_OR_e_v_s_h_ow
__
n_is_m_i_ni_m_u_m_a_p_p_ro_v_ed__
re_v_is_io_n_.____________________________________________________________________

OBTAJNING PROGRAMMED UNITS
Prograrnmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the distributor or factory resulting in longer lead times, greater possibility of error, and higher cost.

ORDERING INFORMATION

Speed
Selection

Order Code

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

60ns

AM27S15PC
AM27S15PCB
AM27S15DC
AM27S15DCB

P-24-1
P-24-1
0-24-1
D-24-1

C-1
B-1
C-1
B-1

COM'L

90ns

AM27S15DM
AM27S150MB
AM27S15FM
AM27S15FMB

0-24-1
0-24-1
F-24-1
F-24-1

C-3
B-3
C-3
B-3

MIL

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, F = Cerpak. Numberfollowing letter is
number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STO-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications.
Pad layout and bonding diagram available upon request.

2-33

~~

Am27S25A • Am27S25
4K·Bit (512 x 8J Generic Series IMOX™
Bipolar High Performance Registered PROM
with PRESET and CLEAR INPUTS
"A" VERSION ADVANCED INFORMATION

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Member of AM D's Generic Family of 8-bit wide
registered PROMs
• On-chip edge-triggered registers - ideal for pipelined
microprogrammed systems
• Versatile synchronous and asynchronous enables for
simplified word expansion
• Buffered common PRESET and CLEAR inputs
• Slim, 24-pin, 300-millateral center package occupies
approximately 1/3 the board space required by standard
discrete PROM and register
• Consumes approximately 1/2 the power of separate
PROM/register combination for improved system
reliability
• Standard version - 50ns max setup and 27ns max
clock-to-output allows system speed improvements
• "A" version offers improved AC performance in critical
paths (30ns max setup and 20ns max clock-to-output)
• Platinum-Silicide fuses guarantee high reliability, fast
programming, and exceptionally high programming
yields (typ>98%)
• AC performance is factory tested utilizing programmed
test words and columns
• 100% MIL-STD-883C processing
• Guaranteed to INT-STD-123

The Am27S25N25 are Schottky TTL programmable read
only memories (PROMs) incorporating true D-type,
master-slave data registers on chip. These devices feature
the versatile 512-word by 8-bit organization and are available with three-state outputs. Designed to optimize system
performance, these devices also substantially reduce the
cost and size of pipelined microprogrammed systems and
other designs where accessed PROM data is temporarily
stored in a register. The Am27S25N25 also offer maximum
flexibility for memory expansion and data bus control
by providing both synchronous and asynchronous
output enables.

BLOCK DIAGRAM

AS
A7
As
As

1 OF 64
ROW
DECODER

64 X 64
PROGRAMMABLE
ARRAY

A4
A3

A2
A1
Ao

When Vee power is first applied, the synchronous enable
(E"s) flip-flop will be in the set condition causing the outputs
(00-07) to be in the OFF or high-impedance state. Reading
data is accomplished by first applying the binary word address to the address inputs (AD-As) and a logic LOW to the
synchronous enable (E"S). During the address setup time,
stored data is accessed and loaded into the master flipflops of the data register. Since the synchronous enable
setup time is less than the address setup requirement,
additional decoding delays may occur in the enable path
without reducing memory performance. Upon the next
LOW-to-HIGH transition of the clock (CP), data is transferred to the slave flip-flops which drive the output buffers.
Providing the asynchronous enable (E") is also LOW, stored
data will appear on the outputs (00-07). IfEs is HIGH when
the positive clock edge occurs, outputs go to the OFF or"
high impedance state regardless of the state of E. The outputs may be disabled at any time by switching E to a HIGH
level. Following the positive clock edge the address and
synchronous enable inputs are free to change; changes will
not affect the outputs until another positive clock edge occurs. This unique feature allows the PROM decoders and
sense amplifiers to access the next location while previously addressed data remains stable on the outputs. For
less complex applications either enable may be effectively
eli mated by tying it to ground.
The on-chip edge-triggered register simplifies system
timing since the PROM clock may be derived directly from
system clock without introducing dangerous race
conditions. Other register timing requirements are similar to
those of standard Schottky registers and are easily
implemented.

10FB
COLUMN
DECODER

B·BIT EDGE-TRIGGERED REGISTER

The Am27S25 has buffered asynchronous PRESET and
CLEAR inputs. These functions are common to all registers
and are useful during power up timeout sequences. With
outputs enabled the PS input asserted LOW will cause all
outputs to be set to a logic 1 (HIGH) state. When the CLR
input is LOW, the internal flip-flops of the data register are
reset and, a logic 0 (LOW) will appear on all outputs. These
functions will control the state of the data register, independent of all other inputs but exclusive of each other.

BPM-330

IMOX is a trademark of Advanced Micro Devices, Inc.
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
2-34

Am27S25A/S25
GENERIC SERIES CHARACTERISTICS
The Am27S25N25 are members of an Advanced PROM series
incorporating common electrical characteristics and programming procedures. All parts in this series are produced with a
fusible link at each memory location storing a logic LOW and can
be selectively programmed to a logic HIGH by applying appro-

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
nonconductive gaps that ensure long-term reliability. Extensive
operating testing has shown that this low-field, large-gap
technology offers the best reliability for fusible link PROMs.

priate voltages to the circuit.
All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming equipment) these products can be rapidly programmed to any customized pattern. Extra test words are pre-programmed during
manufacturing to insure extremely high field programming yields

Common design features include active loading of all critical AC
paths regulated by a built-in temperature and voltagecompensated bias network to provide excellent parametric performance over the full military power supply and temperature
ranges. Selective feedback techniques have been employed to
minimize delays through all critical paths producing the fastest
speeds possible from Schottky processed PROMs.

CONNECTION DIAGRAMS
Top Views

LOGIC SYMBOL

~_a_n_d_p_ro_d_u_c_e_e_x_c_e_lIe_n_t_p_a_ra_m__e_tr_ic_c_o_rr_e_la_t_io_n_.______________~----------------------------------------------~~

DIP

Kii:I

Chip-Pak™
L-32-2
~

.c

76

~

~

32123

Vee

A7

Ps

A.

21

As

As

As

~

A.

E

A3

NC

A,
A3

CLR

A2

CLR

Es

A,

g

A2

A.

CP

A,

CP

Ao

07

00

06

0,

Os

O2

0,

GND

03

19
18
22
20

9

NC

0.

°7

0,

0,

rS

a

r1

10

11

13

14

15

16

17

BPM-333

c;
BPM-332

Vee = Pin 24
GND = Pin 12

BPM-331

Note: Pin 1 is marked for orientation.

AMD's GENERIC FAMILY OF a-WIDE REGISTERED PROMs

1

•

A7

Vce

A7

Vee

A7

24

VCC

A6

As

A6

As

A6

23

As

As

Ps

As

A9

As

22

A9

~

E

A4

21

AlO

A3

INIT/1N1TS

A3

20

INIT/1N1TS

~

CLR

A3

E/ES

A2

ES

A2

ES

A2

Al

CP

Al

CP

Al

Am27S45 19
Am27S47
IS

Ao

07

Ao

07

Ao

17

07

00

Os

00

AS

00

IS

aS

CP

01

Os

01

Os

01

10

IS

aS

02

04

02

04

02

11

14

04

GND

03

GND

03

GND

12

13

03

512x8

BPM-336

BPM-335

BPM-334

1024 X a
Note: Pin 1 is marked for orientation.

;hip-Pak is a trademark of Advanced Micro Devices, Inc.

2-35

2048 X 8

Am27S25A/S25
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +Vccmax

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE
Temperature

Te= -55to+125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Min

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
VIN == VIH or VIL

VOL

Output lOW Voltage

Vee == MIN, IOL == 16mA
VIN == VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 2)

VIL

Input lOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 2)

Input LOW Current

Vee = MAX, VIN = OA5V
Vee == MAX, VIN == Vee

Ise

Output Short Circuit Current

Vee = MAX, VOUT == O.OV (Note 3)

Power Supply Current

All inputs = GND, Vee = MAX

Input Clamp Voltage

Vee == MIN, liN == -18mA

'eEX

Output Leakage Current

Vee == MAX
\IE == 2AV

0.50

2.0

Input HIGH Current

-40
120

IVo == Vee
IVo = OAV

0.8

Volts

-0.250

mA

40

p.A

-90

mA

185

mA

-1.2

Volts

40
p.A
-40

CIN

Input Capacitance

VIN == 2.0V @ f == 1MHz (Note 4)

5

COUT

Output Capacitance

VOUT = 2.0V@f= 1MHz(Note4)

12

pF

Notes: 1. Typical values are at Vee == 5.0V and TA = 25°C.
2. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment (see Notes on Testing).
3. Only one output should be shorted at a time. Duration of the short circuit should not be more than one second.
4. These parameters are not 100% tested, but are periodically sampled.

2-36

Volts

Volts

-0.020

-20

Units
Volts

0.38

IlL

lee

Max

2.4

IIH

VI

(Note 1)

Am27S25A/S25
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (See Notes on Testing)
'A' VERSION ADVANCE INFORMATION
Am27S25A
Typ
Parameters

Description

(Note 1)

Am27S25

COM'L
Max
Min

MIL
Min
Max

COM'L
Min
Max

MIL
Min
Max

Units

ts(A)

Address to CP (HIGH) Setup Time

35

30

35

50

55

ns

tH(A)

Address to CP (HIGH) Hold Time

-10

0

0

0

0

ns

tpHdCP)

Delay from CP (HIGH) to
Output (HIGH or LOW)

tpLH(CP)
tWH(CP)

All Outputs
Simultaneous

15

20

25

27

30

Single Output
(Note 3)

13

15

20

23

26

ns

CP Width (HIGH or LOW)

20

20

20

20

ns

15

10

15

ns

5

5

ns

twdCP)
Es to CP (HIGH) Setup Time

5

10

tH(Es)

Es to CP (HIGH) Hold Time

-2

5

tpHdCLR)

Delay from PRESET or CLEAR (LOW)
to Outputs (LOW or HIGH)

16

PRESET or CLEAR Recovery
(Inactive) to CP (HIGH)

10

20

25

20

25

ns

PRESET or CLEAR Pulse Width

10

20

25

30

25

ns

Delay from CP (HIGH) to Active Output
(HIGH or LOW)

18

25

30

35

45

ns

Delay from E (LOW) to Active Output
(HIGH or LOW)

15

25

30

35

45

ns

Delay from CP (HIGH) to Inactive Output
(OFF or High Impedance) (Note 4)

21

25

30

35

45

ns

Delay from E1 (HIGH) to Inactive Output
(OFF or High Impedance) (Note 4)

15

25

30

35

45

ns

ts(Es)

tpLH(PS)
tR(PS)
tR(CLR)
twdPS)

5
20

25

25

30

ns

twdCLR)
tpzdCP)
tpZH(CP)
tpzdE)
tpZH(E)
tpLZ(CP)
tpHZ(CP)
tpLz(E)
tpHZ(E)
Notes: 1.
2.
3.
4.

Typical values are at Vee = 5.0V and TA = 25°C.
Tests are performed with input 10 to 90% rise and fall times of 5ns or less.
Single register performance numbers provided for comparison with discrete register test data.
tpHZ and tpLZ are measured to the VOH -0.5V and VOL +0.5V output levels respectively. All other switching parameters are tested from and
to the 1.5V threshold levels.

2-37

Am27S25A/S25
SWITCHING WAVEFORMS
(See Notes on Testing)

~_tH_(A_)_mr"")~'""

Ao-AS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

r-r+r-----""'"T~

-tSIEs)-i-tHIES)-

-tsIEs)

l l__

_ _....- - - - - - - - - - - -

---------

tHIES)--lr-r-r-'rJ-r""T"'lr-T-r-------------

:~V
3V
1.SV

I~~-----~~~~------~~~~~~~--------------- ov

I,---Th~~~~~---------------

3V
- - - - - - - - - - 1.SV

CP

~~--Jr~~--I~~~L--~'r_~-_11~~Li~~-------------- ov
_-

r-r+r--------T""lt"..... Ir---:---""'"T~ - o.sv

tPLH(PS)

tPH~CLR)

tpzHIE)VOH

1

H - - i - - - - - - -......- f - < -

H
I

\-.l.+L_ _ _ _ _ _ _L..Jr.J \..-...;..----L..I....Ji

-O.SV

1.SV
VOL

Ir-------~ - - - - - - - 3 V

- - - - - - - 1.SV

~

PS OR CLR

twdPS)
tWL(CLR)

I--

~------ov

tRIPS),tR(CLR)

. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3V
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1.SV

--------------------------------------------OV
BPM·337

NOTES ON TESTING

Incoming test procedures on these devices should be carefully
planned, taking into account the high performance and output
drive capabilities of the parts. The following notes may be useful.

2. Do not leave any inputs disconnected (floating) during
any test.
3. Do not attempt to perform threshold tests under AC conditions. Large amplitude, fast ground current transients
normally occur as the device outputs discharge the load
capacitances. These transients flowing through the parasitic
inductance between the device ground pin and the test system ground can create significant reductions in observable
input noise immunity.

1. Ensure that adequate decoupling capacitance is employed
across the device VCC and ground terminals. Multiple
capacitors are recommended, including a O.1p,Farad or
larger capacitor and a 0.01 p,Farad or smaller capacitor placed
as close to the device terminals as possible. Inadequate
decoupling may result in large variations of power supply
voltage, creating erroneous function or transient performance
failures.

ACTESTLOAD

KEY TO TIMING DIAGRAM

WAVEFORM

OUTPUT

--

O----.----i

JJJJJJ

BPM-338

Notes: 1.
2.
3.
4.

CL == 50pF for all switching characteristics except tpLZ and tpHZ.
CL == 5pF for tpLZ and tPHZ.
S1 is closed for all tests except for tpZH and tpHZ'
All device test loads should be located within 2" of device outputs.

2-38

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

-WAVEFORM

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

Am27S25AjS25
PROGRAMMING
The Am27S25A125 are manufactured with a conductive
Platinum-Silicide link at each bit location. The output of the
memory with the link in place is LOW. The fusible links are
opened one at a time by passing current through them from a 20
volt supply which is applied to the memory output after the E
input is at a logic HIGH. Current is gated through the addressed
fuse by raising the E input from a logic HIGH to 15 volts. After
50J-tsec, the 20 volt supply is removed, the chip enabled, and the
CP input is clocked. Each data verification attempt must be preceded by a positive going (LOW-to-HIGH) clock edge to load the
array data into the on-chip register. The output level is then
sensed to determine if the link has opened. Most links will open
within 50J-tsec. Occasionally a link will be stronger and require
additional programming cycles. The recommended duration of
additional programming periods is 5msec. If a link has not
opened after a total elapsed programming time of 400msec,
further programming of the device should not be attempted.
Successive links are programmed in the same manner until all
desired bit locations have been programmed to the HIGH level.

current drops to approximately 40mA. Current into the
when it is raised to 15 volts is typically 1.5mA.

E pin

The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
continuously applied to one device more than 5 seconds to
avoid heat damage. If this programming time is exceeded, all
power to the chip including VCC should be removed for a period
of 5 seconds after which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by clocking and reading all
words. Occasionally this verification will show that an extra undesired link has been fused. Should this occur, immediately
check the programming equipment to make sure that all device
pins are firmly contacting the programming socket, that the input
Signal levels exhibit sufficient noise margins, and that the prog~amming voltages are within the specified limits. All of these
conditions must be maintained during programming. AMD
PROMs are thoroughly tested to minimize unwanted fusing;
fusing extra bits is generally related to programming equipment
problems.

Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which the

PROGRAMMING PARAMETERS
Min

Max

Units

Veep

Vee During Programming

5.0

5.5

Volts

V1HP

Input HIGH Level During Programming

2.4

5.5

Volts

V1LP

Input LOW Level During Programming

0.0

0.45

Volts
Volts

Parameters

Description

VENP

E Voltage During Programming

14.5

15.5

Vop

Output Voltage During Programming

19.5

20.5

VONP

Voltage on Outputs Not to be Programmed

0

Veep

+ 0.3

Volts
Volts

IONP

Current into Outputs Not to be Programmed

20

rnA

d(Vop)/dt

Rate of Output Voltage Change

20

250

V/p.sec

d(V§\j)/dt

Rate of E Voltage Change

50

1000

V/p.sec

Programming Period - First Attempt

50

100

p'sec

Programming Period - Subsequent Attempts

5.0

15

msec

tp
Notes: 1.
2.
3.
4.

All delays between edges are specified from completion of the first edge to beginning of the second edge; Le., not to the midpoints.
Delays t1 through t7 must be greater than 100ns; maximum delays of 1p'sec are recommended to minimize heating during programming.
During tv. a user defined period. the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM

v-

vccp

SELECTED ADDRESS STABLE
______________
........A-

VIHP
VILP

, - - - - -.....- - - - - - 1 -

VENP

VONP

E
ENABLE

PROGRAMMED
OUTPUT

'------:-.,..-==-rr
I \ OUTPUT"

f--

CP
CLOCK

VO H

\.LER1Fl.u.

~:~Hlp
-t.~-=--=--=--=--=--=--=--=--P-RO-G-R-AM-M-IN-G-CY-C-LE-----=---~-fl

VILP

BPM-340

BPM-339

2-39

Am27S25A/S25
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
735 E. Acoma Dr.
Redwood City,
Scottsdale, AZ 85260
CA94063

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

Programmer
Model(s)

ModelS, 7, and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 RevG·
919-1286-1 RevG·
Unipak Rev H 003
(Code6265)

PM 9058

IMAMDGEN1

MOD 14

PM102

FAM-12

PM 2000
Code 90

715-1617

PA 24-16 and
512 x 8(L)

IM512x8-27S25
AMD

SA31-2B
512 x 8/24

DIS-213AM

DA31-5

AM 190-2

Socket Adapters
Am27S25

• Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, however, much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

ORDERING INFORMATION
Package
Type

Screening
Flow Code

Operating
Range

Order Code

(Note 1)

(Note 2)

(Note 3)

30ns

AM27S25APC
AM27S25APC8
AM27S25ADC
AM27S25ADC8
AM27S25ALC
AM27S25ALC8

P-24-1AA (Note 4)
P-24-1AA(Note4)
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

35ns

AM27S25ADM
AM27S25ADM8
AM27S25AFM
AM27S25AFM8
AM27S25ALM
AM27S25ALM8

D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3

MIL

50ns

AM27S25PC
AM27S25PC8
AM27S25DC
AM27S25DC8
AM27S25LC
AM27S25LC8

P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

55ns

AM27S25DM
AM27S25DM8
AM27S25FM
AM27S25FM8
AM27S25LM
AM27S25LM8

D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection
(Setup Time)

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
4. This package will be available soon. Consult Factory.
This device is also available in die form selected to commercial and military speCifications. Pad layout and bonding diagram
available upon request.

2-40

Am27S27

4096·Bil Generic Series Bipolar Registered PROM
(512 x8 Bits with D-Type Output Data Register)

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• On-chip edge triggered registers - Ideal for pipelined
microprogrammed systems
• Versatile synchronous and asynchronous enables for
simplified word expansion
• Predetermined OFF outputs on power-up
• Fast 55ns address setup and 27ns clock to output times
• Excellent performance over the military range
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ > 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing
extremely flat AC performance over military range
• Member of generic PROM series utilizing standard
programming algorithm
• 100% MIL-STD-883C assurance testing
• Guaranteed to INT-STD-123

The Am27S27 is a 512 word x 8-bit PROM which incorporates an on-chip D-type, master-slave data register with
three-state outputs. Designed to optimize system performance, these devices also substantially reduce the cost of
pipelined microprogrammed system and other designs
wherein accessed PROM data is temporarily stored in a
register. The Am27S27 also offers maximal flexibility for
memory expansion and data bus control by providing both
synchronous and asynchronous output enables.
When Vee power is first applied, the synchronous enable
(Es) flip-flop will be in the set condition causing the outputs,
00-07, to be in the OFF or high impedance state, eliminating the need for a register clear input. Reading data is accomplished by first applying the binary word address to the
address inputs, Ao-As, and a logic LOW to the synchronous
output enable, Es. During the address setup time, stored
data is accessed and loaded into the master flip-flops of the
data register. Since the synchronous enable setup time is
less than the address setup requirement, additional decoding delays may occur in the enable path without reducing
memory performance. Upon the next LOW-to-HIGH transition of the clock, CP, data is transferred to the slave
flip-flops which drive the output buffers. Providing the
asynchronous enable, E, is also LOW, stored data will appear on the outputs, 00-07. IfEs is HIGH when the positive
clock edge occurs, outputs go to the OFF or high impedance state. The outputs may be disabled at any time by
switching E to a HIGH level. Following the positive clock
edge, the address and synchronous enable inputs are free
to change; changes do not affect the outputs until another
positive clock edge occurs. This unique feature allows the
PROM decoders and sense amplifiers to access the next
location while previously addressed data remains stable on
the outputs. For less complex applications either enable
may be effectively eliminated by tying it to ground.

BLOCK DIAGRAM
COLUMN TEST RAIL

64 x 64
PROGRAMMABLE
ARRAY

TEST WORD 0

CP

0--------.,

The on-chip, edge triggered register simplifies system
timing since the PROM clock may be derived directly
from system clock without introducing dangerous race
conditions. Other register timing requirements are
similar to those of standard Schottky registers and are
easily implemented.

Es 0 - - - - - - ,

E 0-----01

BPM-036

CONNECTION DIAGRAM
Top View

LOGIC SYMBOL
19 20 21

1

2

3

4

5

6

18

17

Es

16

CP

7

BPM·037

8

9

10 12 13 14 15

Vee = Pin 22
GND= Pin 11
BPM-038

2-41

Note: Pin 1 is marked for orientation.

Am27S27
GENERIC SERIES CHARACTERISTICS
The Am27S27 is a member of an Advanced PROM series incorporating common electrical characteristics and programming
procedures. All parts in this series are produced with a fusible
link at each memory location storing a logic LOW and can be
selectively programmed to a logic HIGH by applying appropriate
voltages to the circuit.

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field, largegap technology offers the best reliability for fusible link PROMs.

All parts are fabricated with AMD's fast programming highly reliable Platinum-Silicide Fuse technology. Utilizing easily implemented programming (and common programming personality
card sets) these products can be rapidly programmed to any
customized pattern. Extra test words are pre-programmed during
manufacturing to insure extremely high field programming yields,
and produce excellent parametric correlation.

Common design features include active loading of all critical AC
paths regulated by a built-in temperature and voltage compensated bias network to provide excellent parametric performance
over MIL supply and temperature ranges. Selective feedback
techniques have been employed to minimize delays through all
critical paths producing the fastest speeds possible from
Schottky processed PROMs.

MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias
Supply Voltage to Ground Potential (Pin 22 to Pin 11) Continuous

-O.5V to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-O.5V to +Vee max.
21V

DC Voltage Applied to Outputs During Programming
Output Current into Outputs During Programming (Max. Duration of 1 sec.)

250mA

DC Input Voltage

-O.5V to +5.5V

DC Input Current

-30mA to +5mA

OPERATING RANGE
Temperature

Vee
4.75 to 5.25V
4.5t05.5V

Te = -55to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless otherwise noted)
Typ.
Parameters

Description

Min.

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN., IOH
VIN == VIH or VIL

VOL

Output LOW Voltage

Vee = MIN., IOL = 16mA
VIN == VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

Vee == MAX., VIN == 0.45V

IIH

Input HIGH Current

Vee = MAX., VIN

II

Input HIGH Current

Vee = MAX., VIN

Ise

Output Short Circuit Current

Vee == MAX., VOUT = o.OV
(Note 2)

Icc

Power Supply Current

All inputs == GND
Vee = MAX.

VI

Input Clamp Voltage

Vee

leEX

Output Leakage Current

0.38

Vee == MAX.
VE = 2.4V

I

VIN

COUT

VOUT = 2.0V @ f

0.8

Volts

-0.250

rnA

25

/LA

1.0

rnA

-40

-90

rnA

130

185

rnA

-1.2

Volts

Vo== 4.5V

40

Vo == O.4V

-40

= 1MHz (Note 3)

/LA

5
pF
12

Typical limits are at Vee = 5.0V and TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

2-42

Volts
Volts

-0.010

= 2.0V @ f = 1MHz (Note 3)

Input CapaCitance
Output Capacitance

0.50

2.0

-20

Units
Volts

= 2.7V
= 5.5V

I

Max.

2A

= MIN., liN = -18rnA

CIN

Notes: 1.
2.
3.
4.

= -2.0rnA

(Note 1)

Am27S27
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Typ
5V
Parameter

Description

Test Conditions

ts(A)

Address to CP (HIGH) Setup Time

tH(A)

Address to CP (HIGH) Hold Time

tpHdCP)
tpLH(CP)

Delay from CP (HIGH) to Output
(HIGH or LOW)

tWH(CP)
twdCP)

CP Width (HIGH or LOW)

ts(Es)

Es to CP (HIGH) Setup Time

tH(Es)

Es to CP (HIGH) Hold Time

tpzdCP)
tpZH(CP)

Delay from CP (HIGH) to Active
Output (HIGH or LOW)

tpzdE)
tPZH(E)

Delay from E (LOW) to Active
Output (HIGH or LOW)

tpLZ(CP)
tpHZ(CP)

Delay from CP (HIGH) to Inactive Output
(OFF or High Impedance)

tpLZ(E)
tpHZ(E)

Delay from E (HIGH) to Inactive Output
(OFF or High Impedance)

CL = 30pF
Sl closed.
(See AC Test
Load below)

C L = 30pF
Sl closed for tpZL
and open for tpZH

CL = 5pF (Note 1)
Sl closed for tpLZ
and open for tpHZ

COM'L
Min
Max

25°C

MIL
Min

Max

Units

40

55

65

ns

-15

0

0

ns

15

27

ns

30

10

30

40

ns

10

25

30

ns

-10

0

0

ns

15

35

45

ns

15

40

45

ns

15

35

45

ns

10

30

40

ns

Notes: 1. tpHZ and tpLZ are measured to the VOH - 0.5V and VOL + 0.5V output levels respectively. All other switching parameters are tested from and
to the 1.5V threshold levels.
2. Tests are perfomed with input 10% to 90% rise and fall times of 5ns or less.

SWITCHING WAVEFORMS

~~--------------------3V

- - - - - - - - 1.SV

------------------------ov
rT~~~~_r~------------------------3V

- - - - - - - - - 1.SV
~'~~----------~~~~------------~~~~~~~-------------------------OV
1r-----~~~_r~-----------------------------3V
~-------."
1.SV

CP

~~---JI~~--~L~-----'I~~~1~~~~----Jr~~_1~~~~~----------------------------ov

1r---------------,I--------3V
- - - - - - - 1.SV
1'--------------OV
BPM·039

KEY TO TIMING DIAGRAM

ACTESTLOAD

WAVEFORM

VCC~
51
R1

300n
OUTPUT 0 - - - -........- - - - - - .
R2

600n

-

JJJJI!

BPM-040

2-43

INPUTS

OUTPUTS

MUST BE
STEADY

Will BE
STEADY

MAY CHANGE
FROM H TO l

Will BE
CHANGING
FROM H TO l

MAY CHANGE
FROM l TO H

Will BE
CHANGING
FROM l TO H

-

WAVEFORM

"

INPUTS

DON'TCARE;
ANY CHANGE
PERMITTED

DOES NOT
APPLY

OUTPUTS

CHANGING;
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

Am27S27
PROGRAMMING

current drops to approximately 40mA. Current into the Epin when
it is raised to 15 volts is typically 1.5mA.

The Am27S27 is manufactured with a conductive PlatinumSilicide link at each bit location. The output of the memory with
the link in place is LOW. The fusible links are opened one at a
time by passing current through them from a 20 volt supply
which is applied to the memory output after the E input is at a
logic HIGH. Current is gated through the addressed fuse by
raising the E input from a logic HIGH to 15 volts. After 50 p,sec,
the 20 volt supply is removed, the chip is enabled and the CP
input is clocked. Each data verification attempt must be preceded by a positive going (LOW-to-HIGH) clock edge to load
the array data into the on-chip register. The output level is then
sensed to determine if the link has opened. Most links will open
within 50 p,sec. Occasionally a link will be stronger and require
additional programming cycles. The recommended duration of
additional programming periods is 5 msec. If a link has not
opened after a total elapsed programming time of 400 msec,
further programming of the device should not be attempted.
Successive links are programmed in the same manner until all
desired bit locations have been programmed to the HIGH level.

The memorie.s may become hot during programming due to the
large currents being passed. Programming cycles should not be
continuously applied to one device more than 5 seconds to avoid
heat damage. If this programming time is exceeded, all power to
the chip including V ce should be removed for a period of 5
seconds after which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by clocking and reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which the

PROGRAMMING PARAMETERS
Min.

Max.

Units

Vecp

Vee During Programming

5.0

5.5

V

V 1HP

Input HIGH Level During Programming

2.4

5.5

V

. V 1LP

Input LOW Level During Programming

0.0

0.45

V

VENP

E Voltage

14.5

15.5

V

Vop

Output Voltage During Programming

19.5

20.5

V

Vo NP

Voltage on Outputs Not to be Programmed

0

Veep+0.3

V

20

mA

Parameter

Description

During Programming

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Aate of Output Voltage Change

20

250

V//Lsec

d(VEN)/dt

Aate of E Voltage Change

50

1000

V//Lsec

Programming Period - First Attempt

50

100

/Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

tp

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
2. Delays t1 through ts must be greater than 100 ns; maximum delays of 1/Lsec are recommended'to minimize heating during programming.
3. During tv, a user defined period, the output being programmed is switched to the load A and read to determine if additional pulses are
required.
4. Outputs not being programmed are connected to VONP through resistor A which provides output current limiting.

SIMPLIFIED PROGRAMMING DIAGRAM

PROGRAMMING WAVEFORMS

--v

V--

A~~~~~ --A~____
SE_LE_CTE_D_AD_D_RE_S_S_ST_AB_L_E_ _ _ _A--

V1HP
VItP

E
ENABLE

------------=--=-----1

CLOg~ -':'1-.->------PROGRAMMING CYCLE
\-0.

BPM·042

BPM·041

2-44

Am27S27
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

DataI/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ 85260

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29 and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev G*
919-1286-1 Rev G*

PM 9058

IMAMDGENl

MOD14

PM102

FAM-12

Am27S27

715-1412-2

PA22-4and
512 x 8(L)

1M 512 x 8-2227S27-AMD

SA 18 B 512 x 8/22

DIS-l68AMD

DA28

~._R_e_v_sh_o_w_n_i_s_m_in_i_m_u_m_a_p_p_ro_v_e_d_re_v_is_io_n_.

________________________________________________________________________

OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred
paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the distributor
or factory resulting in longer lead times, greater possibility of
error, and higher cost.

ORDERING INFORMATION

(ts(A»

Order Code

Package
Type
(Note 1)

55ns

AM27S27PC
AM27S27PC8
AM27S27DC
AM27S27DC8

P-22-1
P-22-1
D-22-1
D-22-.1

C-1
8-1
C-1
8-1

COM'L

65ns

AM27S27DM
AM27S27DM8

D-22-1
D-22-1

C-3
8-3

MIL

Speed
Selection

Screening

Flow Code
(Note 2)

Operating
Range
(Note 3)

Notes: 1. P = Molded DIP, D = Hermetic DIP. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad
layout and bonding diagram available upon request.

2-45

~~

Am29775

4096·8it Generic Series Bipolar PROM with Register

Refer to

Am27S27
Bipolar Memory PROM Product Specification

The Am29775 is replaced by the Am27S27
(three-state).

2-46

Am27S28A • Am27S29A
Am27S28 • Am27S29
4096·Bit Generic Series Bipolar PROM
(512 x 8 bits with ultra fast access time)
"A" VERSION - ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 35ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures.
• 100% MIL-STO-883C assurance testing
• Guaranteed to INT-STO-123

The Am27S28A/28 and Am27S29A/29 are high speed
electrically programmable Schottky read only memories.
Organized in the industry standard 512 x 8 configuration,
they are available in both open collector Am27S28A/28 and
three-state Am27S29A/29 output versions. After programming, stored information is read on outputs 00-07 by
applying unique binary addresses to Ao-Aa and holding the
chip select input, CS, at a logic LOW. If the chip select input
goes to a logic HIGH, 00-07 go to the off or high
impedance state.

BLOCK DIAGRAM
COLUMN TEST RAIL

64x 64
PROGRAMMABLE
ARRAY

GENERIC SERIES CHARACTERISTICS
The Am27S28A/28 and Am27S29A/29 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.
All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test rows are
pre-programmed during manufacturing to insure extremely
high field programming yields, and produce excellent
parametric correlation.

As

TEST ROW 0

00

0,

02

03

05

O.

BPM-083

07

06

CONNECTION DIAGRAMS - Top Views

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

DIP

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.

Chip-Pak™
L-20-1

Ao

Vee

A,

As

A2

A7

AJ

A6

A4

As

00

CS

0,

07

O2

06

OJ

05

GND

04

.r

~

~

,;>

.t

"
"

."

0,

"

0,

os

0,

'"
~

S

or

Cf

Note: Pin 1 is marked for orientation.
BPM-085

BPM-286

Chip-Pak is a trademark of Advanced Micro Devices, Inc.
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

2-47

Am27528A/529A/528/S29
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 20 to Pin 10) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5V to + VCC max

DC Voltage Applied to Outputs During Programming

21V
250mA

Output Current into Outputs During Programming (Max Duration of 1 sec)
DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE
LOGIC SYMBOL

Temperature

1

2

3

4

5 16 17 18 19

Te = -55to +125°C
AO A, A2 A3 A4 As As A7 As

15

cs
512 X 8 PROM

6

7

8

9

11 12 13 14

Vee = Pin20
GND = Pin 10

BPM-084

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Min

Test Conditions

VOH (Note 2)

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Vee = MAX, VIN = 2.7V

Ise (Note 2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

lee

Power Supply Current

All inputs = GND
Vee = MAX

VI

Input Clamp Voltage

Vee = MIN, liN = -18mA

(Note 1)

2.4
0.50
2.0

Output Leakage Current

Vee = MAX
Vcs = 2.4V

(Note 2)

Volts
Volts

-0.010

-20

Units
Volts

0.8

Volts

-0.250

mA

25

p.A

-40

-90

mA

105

160

mA

-1.2

Volts

40

Vo= 4.5V
leEX

Max

Vo = 2.4V

40

Vo = O.4V

-40

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 5)

4

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 5)

8

p.A

pF

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but are periodically sampled.

2-48

Am27S28A/S29A/S28/S29
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
"A" VERSION ADVANCED INFORMATION
Typ
Parameter

Description

Test Conditions

tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(See Notes 1-3)

Max

5V25°C
A
STD

COM'L
STD
A

A

MIL
STD

30

35

35

55

45

70

12

15

20

25

25

30

ns

12

15

20

25

25

30

ns

Units
ns

Notes: 1. tAA is tested with switch S1 closed and CL = 30pF.
2. For open collector outputs, tEA and t ER are tested with 51 closed to the 1.5V output level. CL = 30pF.
3. For three-state outputs, tEA is tested with CL = 30pF to the 1.5V level; 51 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with 51 open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with 51 closed to the VOL + 0.5V level.

SWITCHING WAVEFORMS

,·,·3
cs

3.0V
1.SV

ov

I

f--t AA -1

00.0 7

~

-l-

I

~tER:i

~tEA-i

»»>=:::::::

XXX*

1.SV

~

Note: Level on output while CS is HIGH is determined externally.

ov
VO H
1.SV
VOL

BPM·086

KEY TO TIMING DIAGRAM

WAVEFORM

---

--

---

JJ!JJJ

INPUTS

--

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

WAVEFORM

"

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

AC TEST LOAD

VCC~O--S1
Rl
300n
OUTPUT

oct

R2
SOOll

~
BPM·087

2-49

Am27S28AjS29AjS28jS29
PROGRAMMING

The Am27S28A/28 and Am27S29A/29 are manufactured with a
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. To program the
device, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to the
memory output after the CS input is at a logic HIGH. Current is
gated through the addressed fuse by raising the CS input from a
logic HIGH to 15 volts. After 50p-sec, the 20 volt supply is
removed, the chip enabled, and the output level sensed to
determine if the link has opened. Most links will open within
50p-sec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit locations have been programmed to the HIGH level.
Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which the

current drops to approximately 40mA. Current into the CS pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
continuously applied to one device more than 5 seconds to
avoid heat damage. If this programming time is exceeded, all
power to the chip including VCC should be removed for a period
of 5 seconds after which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Parameter

Min

Max

Units

Vecp

Vec During Programming

5.0

5.5

Volts

V 1HP

Input HIGH Level During Programming

2.4

5.5

Volts

V 1LP

Input LOW Level During Programming

0.0

0.45

Volts

Vesp

CS Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

0.0

Vccp+0.3

Volts

10NP

Current into Outputs Not to be Programmed

d(VOp)/dt

Rate of Output Voltage Change

Description

d(VEN)/dt
tp

20

mA

20

250

V//Lsec
vl/Lsec

Rate of CS Voltage Change

100

1000

Programming Period - First Attempt

50

100

/Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
2. Delays t1 through t4 must be greater than 100ns; maximum delays of 1/Lsec are recommended to minimize heating during programming.
3. During tv. a user defined period. the output being programmed is switched to the load R and read to determine if additional pulses
are required.
4. Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM
VONP

VCCP

J

~

SELECTED ADDRESS STABLE

Ao-Aac=)

cs
ENABLE

R '" 300n

~o-

-..lh ~~"
.. I .~
"

Am27S28A/28 •
Am27S29A/29

~I ~:::
_ 1 3 _14 _IV _

CSr-07

VvOP

r--:o......

PROGRAMMED
OUTPUT
-,

I

dl

OP

,

OUTPUT:,

~E!3J!l.U_
PROGRAMMING CYCLE

•

I

I

I
I

OH
VOL

Vcsp

n
-::-

BPM-OSS

2-50

-=1

i

0-

n
-::-

VOP

BPM-2S7

Am27528A/529A/528/529
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

Programmer
Model(s)

ModelS, 7, and 9
Systems 17,19,29 and 100

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 RevH·
919-1286-1 RevH·

Am27S28A/29A

715-1413

Am27S28/29

International
Microsystems,lnc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City,
Scottsdale, AZ 85260
CA94063

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

M900,M900B,M910, IM1010
M920, and M980

MPP-80

UPP-801

UPP-803

PPX

PM 9058

IMAMDGEN1

MOD 14

PM 102

FAM-12

PM2000
Code 90

PA20-4 and

1M 512 x 8-20-AMD

SA 6

DIS-l58 AM

DA-34

AM120-3

512x8 (Ll

"Rev shown is minimum approved revision.
f - - - - - - - - - - - - t

OBTAINING PROGRAMMED UNITS
Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

40ns

AM27S28APC
AM27S28APCB
AM27S28AOC
AM27S28AOCB
AM27S28ALC
AM27S28ALCB

AM27S29APC
AM27S29APCB
AM27S29AOC
AM27S29AOCB
AM27S29ALC
AM27S29ALCB

P-20-1
P-20-1
0-20-1
0-20-1
L-20-1
L-20-1

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

50ns

AM27S28AOM
AM27S28AOMB
AM27S28ALM
AM27S28ALMB

AM27S29AOM
AM27S29AOMB
AM27S29ALM
AM27S29ALMB

0-20-1
0-20-1
L-20-1
L-20-1

C-3
B-3
C-3
B-3

MIL

55ns

AM27S28PC
AM27S28PCB
AM27S280C
AM27S280CB
AM27S28LC
AM27S28LCB

AM27S29PC
AM27S29PCB
AM27S290C
AM27S290CB
AM27S29LC
AM27S29LCB

P-20-1
P-20-1
0-20-1
0-20-1
L-20-1
L-20-1

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

70ns

AM27S280M
AM27S280MB
AM27S28LM
AM27S28LMB

AM27S290M
AM27S290MB
AM27S29LM
AM27S29LMB

0-20-1
0-20-1
L-20-1
L-20-1

C-3
B-3
C-3
B-3

MIL

Speed
Selection

Open
Collector

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip-Pak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STO-883, Class C.
Levels B-1 and B-3 conform to MIL-STO-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-51

fJ

Am27S30A • Am27S31 A
Am27S30 • Am27S31
4096·Bit Generic Series Bipolar PROM
(512 x 8 bits with ultra fast access time)
"A" VERSION ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 35ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements forindustry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures
• 100% MIL-STO-883C assurance testing
• Guaranteed to INT-STO-123

The Am27S30A/30 and Am27S31A/31 are high speed
electrically programmable Schottky read only memories.
Organized in the industry standard 512 x 8 configuration,
they are available in both open collector Am27S30N30 and
three-state Am27S31A/31 output versions. After programming, stored information is read on outputs 00-07 by applying unique binary addresses to Ao-As and holding CS1
and CS2 LOW and CS3 and CS4 HIGH. All other valid input
conditions on CS1, CS2, CS3 and CS4 place 00-07 into the
OFF or high impedance state.

BLOCK DIAGRAM
COLUMN TEST RAIL

.
64 x 64
PROGRAMMABLE
ARRAY

GENERIC SERIES CHARACTERISTICS
The Am27S30N30 and Am27S31N31 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.
All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test rows are
preprogrammed during manufacturing to insure extremely
high field programming yields, and produce excellent parametric correlation.
Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.
Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.

As

TEST ROW 0

CS,
CS2--~~"'"

C S J - - -....."
CS4

BPM·114

CONNECTION DIAGRAMS - Top Views
DIP

Chip-Pak™

L-32-2
~
A,

Vee

A.

A.

A,

NC

~

~

c·

A,
A.

CS1

A.

CS,

AJ

CS2

A,

CSJ

A.

CS2

A,

CS,

A,

CS,

A.

CS.

A,

Ao

0,

00

0,

0,

0,

0,

0,

O.

07

OJ

0,

O.

BPM·116

GND/NC

Note: Pin 1 is marked for orientation.

GIID/HC

BPM·261

This document contains information on a product under development at AdvancedMicro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.
2-52

Am27S30A/S31A/S30/S31
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to + 125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

-0.5to +7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +Vccmax

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 ~ec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

Vee

LOGIC SYMBOL

Temperature

4.75 to 5.25V

TA = Oto +75°C

4.5t05.5V

Te= -55to+125°C

8

7

6

5

4

3

2

1 23

21

20

19--~-'1

cs

512 X 8 PROM

18

9

Vee = Pin24
GND = Pin 12
(Pin 22 Open)

10 11 13

14

15 16

17

BPM-115

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ

Parameters

Test Conditions

Description

VOH (Note 2)

Output HIGH Voltage

Vee = MIN,IOH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN,IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee

IIH

Input HIGH Current

Vee

Ise (Note 2)

Output Short Circuit Current

Vee == MAX, VOUT = O.OV (Note 4)

lee

Power Supply Current

All inputs = GND
Vee == MAX

VI

Input Clamp Voltage

Vee

Min

2.0

Output Leakage Current

Vee = MAX
VCS1 = 204V

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 5)

COUT

Output Capacitance

VOUT = 2.0V @f

= 1MHz (Note 5)

0.8

Volts

-0.250

mA

25

p.A

-40

-90

mA

115

175

mA

-1.2

Volts

-18mA

(Note 2)

Volts
Volts

-0.010

-20

Units
Volts

0.50

Vo
leEX

Max

204

= MAX, VIN == Oo45V
= MAX, VIN = 2.7V

= MIN,IIN =

(Note 1)

= 4.5V

40

Vo = 204V

40

Vo = Oo4V

-40

p.A

4
pF
8

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to ground pin and include all bvershoots due to system and/or tester noise. Do not attempt to test these
values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but periodically sampled.

2-53

Am27S30A/S31A/S30/S31
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
.. A" VERSION ADVANCED INFORMATION
Typ
Parameter

Test Conditions

Description

tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(5ee Notes 1-3)

Max

5V25°C
A
STD

A

COM'L
STD

30

35

35

55

45

70

ns

12

15

20

25

25

30

ns

12

15

20

25

25

30

ns

A

MIL
STD

Units

Notes: 1. tAA is tested with switch 51 closed and CL = 30pF.
2. For open collector outputs, tEA and tER are tested with 51 closed to the 1.5V output level. CL = 30pF.
3. For three state outputs, tEA is tested with CL = 30pF to the 1.5V level; 51 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with 51 open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with 51 closed to the VOL + 0.5V level.

SWITCHING WAVEFORMS

A"A·3
CS3' cS4

CS1' CS2

3.0V
1.5V

OV

I

* **«

I

~tER':l

~tAA-1

@=::::,::

XXXI

00-0 7

f-tEA-i

Note: Level on output while chip is disabled is determined externally.

3.0V
1.5V

ov
VOH
1.5V

VOL

BPM·l17

KEY TO TIMING DIAGRAM

WAVEFORM

---

-

---

JJJJI!

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

WAVEFORM

---

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

VCC~O--51
Rl
300n

OUTPUT

ect

R2
600n

~
BPM·118

2-54

Am27S30AjS31 AjS30jS31
PROGRAMMING
The Am27S30A/30 and Am27S31A/31 are manufactured with a
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. The fusible links are
opened one at a time by passing current through them from a 20
volt supply which is applied to one memory output after the CS1
input is a logic HIGH. Current is gated through the addressed
fuse by raising the CS1 input from a logic HIGH to 15 volts. After
50 JLsec, the 20 volt supply is removed, the chip is enabled and
the output level sensed to determine if the link has opened. Most
be
links will open within 50 JLsec. Occasionally a link
stronger and require additional programming cycles. The recommended duration of additional programming periods is
5msec. If a link has not opened after a total elapsed programming time of 400msec, further programming of the device
should not be attempted. Successive links are programmed in
the same manner until all desired bit locations have been programmed to the HIGH level.

the current drops to approximately 40mA. Current into the CS1
pin when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
continuously applied to one device more than 5 seconds to
avoid heat damage. If this programming time is exceeded, all
power to the chip including VCC should be removed for a period
of 5 seconds after which programming may be resumed.

wil

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be
approximately 140mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Min

Max

Units

Vccp

Vcc During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCSP

CS, Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

VONP

Voltage on Outputs Not to be Programmed

0.0

Description

Parameters

Vccp

+ 0.3

Volts
Volts

IONP

Current into Outputs Not to be Programmed

20

mA

d(VOp)/dt

Rate of Output Voltage Change

20

250

V//Lsec

d(VEN)/dt

Rate of CSl Voltage Change

100

1000

V//Lsec

Programming Period - First Attempt

50

100

/Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

tp
Notes: 1.
2.
3.
4.

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t, through t4 must be greater than 100ns; maximum delays of 1/Lsec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

SIMPLIFIED PROGRAMMING DIAGRAM

PROGRAMMING WAVEFORMS

ADDRESS
INPUTS

Vccp

=x

C

SELECTED ADDRESS STABLE
'--______________

VIHP
VILP

CS,
ENABLE

VIHPD----~
VILPD----t
PROGRAMMED
OUTPUT
\

OUTPUT

II

L:!-Efjff!..JJ_

------11

VOL
VCSP

BPM-119

2-55

BPM·262

Am27S30A/S31 A/S30/S31
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ 85260

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29 and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev H"
919-1286-1 Rev H'

PM 9058

IMAMDGEN1

MOD 14

PM 102

FAM-12

Am27S30A/31 A
Am27S30/31

715-1545

PA24-13 and
512x8(L)

1M 512 x 8-24-AMD

SA 22-6

DIS-135AM

DA29

·Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

40ns

AM27S30APC
AM27S30APCB
AM27S30ADC
AM27S30ADCB
AM27S30ALC
AM27S30ALCB

AM27S31APC
AM27S31 APCB
AM27S31ADC
AM27S31 ADCB
AM27S31ALC
AM27S31ALCB

P-24-1AC
P-24-1AC
D-24-1AC
D-24-1AC
L-32-2
L-32-2

C-1
8-1
C-1
B-1
C-1
8-1

COM'L

50ns

AM27S30ADM
AM27S30ADMB
AM27S30AFM
AM27S30AFMB
AM27S30ALM
AM27S30ALMB

AM27S31 ADM
AM27S31ADMB
AM27S31AFM
AM27S31 AFMB .
AM27S31ALM
AM27S31ALMB

D-24-1AC
D-24-1AC
F-24-1
F-24-1
L-32-2
L-32-2

C-3
B-3
C-3
8-3
C-3
8-3

MIL

55ns

AM27S30PC
AM27S30PC8
AM27S30DC
AM27S30DC8
AM27S30LC
AM27S30LCB

AM27S31PC
AM27S31PC8
AM27S31DC
AM27S31DCB
AM27S31LC
AM27S31LC8

P-24-1AC
P-24-1AC
D-24-1AC
D-24-1AC
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

70ns

AM27S30DM
AM27S30DMB
AM27S30FM
AM27S30FM8
AM27S30LM
AM27S30LMB

AM27S31OM
AM27S31DMB
AM27S31FM
AM27S31FM8
AM27S31LM
AM27S31LMB

D-24-1AC
D-24-1AC
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip-Pak. F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-56

Am27S32A • Am27S33A
Am27S32 • Am27S33
4096·Bit Generic Series Bipolar PROM
(1024 x 4 bits with ultra fast access time)

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High Speed - 35ns max commercial range access time
• Excellent performance over full MIL and
commercial ranges
• Highly reliable, ultra-fast programming PlatinumSilicide fuses
• High programming yield
• Low current PNP inputs
• High current open collector and three-state outputs
• Fast chip select
• Access time tested with N2 patterns
• Pin for pin replacements for industry standard products
• Common Generic PROM series electrical characteristics
and simple programming procedures.
• 100% MIL-STO-883C assurance testing
• Guaranteed to INT -STO-123

The Am27S32A132 and Am27S33A133 are high speed
electrically programmable Schottky read only memories.
Organized in the industry standard 1024 x 4 configuration,
they are available in both open collector Am27S32A132 and
three-state Am27S33A133 output versions. After programming, stored information is read on outputs 00-03 by
applying unique binary addresses to AO-Ag and holding the
chip select input, CS1, and CS2 LOW. If either chip select
input goes to a logic HIGH, 00-03 go to the off or high impedance state.

BLOCK DIAGRAM
COLUMN TEST RAil

A9

GENERIC SERIES CHARACTERISTICS

AS

The Am27S32A/32 and Am27S33A/33 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages
to the circuit.

A7
A6

1 OF 66
ROW
DECODER

AS
A4

A3

All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly programmed to any customized pattern. Extra test words are
pre-programmed during manufacturing to insure extremely
high field programming yields, and produce excellent parametric correlation.

A2
A1
AO

CS1
CS2

BPM-090

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

CONNECTION DIAGRAMS
Top Views
Chip-Pak™
L-20-1

DIP

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths producing the
fastest speeds possible from Schottky processed PROMs.

AS

vee

AS

A7

A4

AS

A3

A9

AD

00

Al

01

'".,

A2

02

·2

eSl

03

GND

eS2

~

:t

~

~

...,

A,
A,
0,

0,

Irl"

1l1"

rS

8

Note: Pin 1 is marked for orientation.
BPM-092

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-57

BPM-290

Am27S32A/S33A/S32/S33
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 18 to Pin 9) Continuous

-0.5V to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5V to

+ VCC max.

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max. Duration of 1 sec.)

250mA

DC Input Voltage

-0.5V to +5.5V

DC tnput Current

-30 to +5mA

OPERATING RANGE

Vee

LOGIC SYMBOL

Temperature

T e = - 55 to

+ 125°C

1
17
16
15

AO
A1
A2
A3
A4
AS
A6
A7
AS
A9

CS1
1024

x4

PROM

CS2

00

01

02

03

14

13

12

11

Vee = Pin 18
GND = Ping

10

BPM-091

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ

Parameters

Description

Test Conditions

Min

VOH
(Note 2)

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

(Note 1)

2.4

2.0

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

Input HIGH Current

Vee = MAX, VIN = 2.7V

Ise
(Note 2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

lee

Power Supply Current

All inputs = GND,
Vee = MAX

VI

Input Clamp Voltage

-40

(Note 2)

Volts

-0.250

mA

25

ILA

-90

mA

COM'L

105

140

105

145
-1.2

Vee = MIN, liN = -18mA
Vee = MAX
Ves 1 = 2.4V

0.8

MIL

Vo = 2.4V

40

Vo =·O.4V

-40

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 5)

5

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 5)

12

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time_ Duration of the short circuit should not be more than one secQnd.
5. These parameters are not 100% tested, but are periodically sampled.

2-58

mA
Volts

40

VO=4.5V
Output Leakage Current

Volts
Volts

-0.020

-20

Units
Volts

0.45

IIH

leEX

Max

ILA

pF

Am27S32A/S33A/S32/S33
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Typ
Parameter

Description

Test Conditions

tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(See Notes 1-3)

Max

5V25°C
A
STD

COM'L
A
STD

A

MIL
STD

25

38

35

55

45

70

ns

18

20

25

25

30

30

ns

18

20

25

25

30

30

ns

Units

Notes: 1. tAA is tested with switch S1 closed and CL = 30pF.
2. For open collector outputs, tEA and tER are tested with S1 closed to the 1.5Voutput level. CL = 30pF.
3. For three state outputs, tEA is tested with CL = 30pF to the 1.5V level; S1 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with S1 closed to the VOL + 0.5V level.

SWITCHING CHARACTERISTICS

'O-A·3
CS1-CS2

3.0V
1.SV

ov

1~
'Elf= ::~: ,';~ @«

I
I

~tERJ

/-tAA-------j

XXXI

00-03

.

~tEA-l

Note: Level on output while either CS is HIGH is determined externally.

I.SV

ov
VOH
I.SV
VOL

BPM-093

KEY TO TIMING DIAGRAM

WAVEFORM

---

--

---

JJJJJJ

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

--

WAVEFORM

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF"' STATE

AC TEST LOAD

vcc~o-SI

Rl
300n
OUTPUT

cc±

R2
600n

~
BPM-094

2-59

Am27S32A/S33A/S32/S33 .
PROGRAMMING
the current drops to approximately 40mA. Current into the
CS 1 pin when it is raised to 1S volts is typically 1.SmA.

The Am27S32N32 and Am27S33N33 are manufactured with
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. To program the
device, the fusible links are selectively opened.

The memories may become hot during programming due to
the large currents being passed. Programming cycles should
not be applied to one device more than S seconds to avoid
heat damage. If this programming time is exceeded, all power
to the chip including VCC should be removed for a period of S
seconds after which programming may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS 1 input is at a logic HIGH. Current
is gated through the addressed fuse by raising the CS 1 input
from a logic HIGH to 1S volts. After SOjLsec, the 20 volt supply
is removed, the chip enabled, and the output level sensed to
determine if the link has opened. Most links will open within
SOjLsec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is Smsec. If a link has not opened
after a total elapsed programming time of 400msec, further programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.

When all programming has been completed, the data content
of the memory should be verified by sequentially reading all
words. Occasionally this verification will show that an extra
undesired link has been fused. Should this occur, immediately
check the programming equipment to make sure that all device pins are firmly contacting the programming socket, that
the input signal levels exhibit sufficient noise margins and
that the programming voltages are within the specified limits.
All of these conditions must be maintained during programming. AMD PROMs are thoroughly tested to minimize unwanted fusing; fusing extra bits is generally related to programming equipment problems.

Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Min

Max

VCCP

VCC During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

Parameter

Description

Units

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCSP

CS 1 Voltage During Programming

14.5

15.5

Volts

VOP

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs. Not to be Programmed

0

VCCP+0.3

Volts

IONP

Current into Outputs. Not to be Programmed

20

mA

d(VOP)/dt

Rate of Output Voltage Change

20

250

V/p,sec

d(VCS)/dt

Rate of CS 1 Voltage Change

100

1000

V/jLsec

Programming Period - First Attempt

50

100

p,sec

Programming Period - Subsequent Attempts

5

15

msec

tP

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; Le. not to the midpoints.
2. Delays t1, t2. t3 and t4 must be greater than 100 ns; maximum delays of 1 p,sec are recommended to minimize heating during
programming.
3. During tv, a user defined period. the output being programmed is switched to the load R and read to determine if additional pulses
are required.
4. Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM
veep

I

VONP
R " 300n

~

AD-Ag¢

~oAm27S32A/32
OR
Am27S33A/33
eSlr-eS2

-f"
vesp

BPM-095

2-60

~o~o-

~

11

Jl

-::-

-::-

VOP

BPM-291

I

Am27S32A/S33A/S32/S33
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

Programmer
Model(s)

Model 5, 7, and 9
Systems 17,19,29 and 100

M900, M900B, M910, IM1010
M920, and M980

MPP-80

UPP-801

UPP-803 PPX

AMD Generic
Bipolar PROM
Personality
Module

909-1286-1 Rev H*
919-1286-1 RevW

PM 9058

IMAMDGEN1

MOD14

PM 102

FAM-12

PM 2000
Code 90

Am27S32A/33A
Am27S32/33

715-1414

PA 18-6and
1024 x 4(L)

1M 1024x4-18-AMD

SA24

DIS 136 AM

DA 38

AM170-2

International
Microsystems,lnc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City,
Scottsdale, AZ 85260
CA94063

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

r-_.R_e_v_s_h_o_w_n_is_m_i_ni_m_u_m_a_p_p_ro_v_ed__
re_v_is_io_n_.____________________________________________________________________

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

ORDERING INFORMATION
Order Code

Three-State

Package
Type
(Note 1)

Screening
Flow Code
(Note 2)

Operating
Range
(Note 3)

AM27S33APC
AM27S33APCB
AM27S33ADC
AM27S33ADCB
AM27S33ALC
AM27S33ALCB

P-18-1
P-18-1
D-18-1
D-18-1
L-20-1
L-20-1

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

AM27S32ADM
AM27S32ADMB
AM27S32ALM
AM27S32ALMB

AM27S33ADM
AM27S33ADMB
AM27S33ALM
AM27S33ALMB

D-18-1
D-18-1
L-20-1
L-20-1

C-3
B-3
C-3
B-3

MIL

55ns

AM27S32PC
AM27S32PCB
AM27S32DC
AM27S32DCB
AM27S32LC
AM27S32LCB

AM27S33PC
AM27S33PCB
AM27S33DC
AM27S33DCB
AM27S33LC
AM27S33LCB

P-18-1
P-18-1
D-18-1
D-18-1
L-20-1
L-20-1

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

70ns

AM27S32DM
AM27S32DMB
AM27S32LM
AM27S32LMB

AM27S33DM
AM27S33DMB
AM27S33LM
AM27S33LMB

D-18-1
D-18-1
L-20-1
L-20-1

C-3
B-3
C-3
B-3

MIL

Speed
Selection

Open
Collector

35ns

AM27S32APC
AM27S32APCB
AM27S32ADC
AM27S32ADCB
AM27S32ALC
AM27S32ALCB

45ns

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.
Flat packages are available upon special request. Consult factory.

2-61

~~

Am27S65 • Am27S75
• Am27S85
'MaX
Generic Series 4·Wide Sipolar
Til Registered PROMs
with SSR™ Diagnostics Capability
ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

SERIAL SHADOW REGISTER (SSR)
DIAGNOSTICS CAPABILITIES

• On-chip edge-triggered registers - ideal for pipelined
microprogrammed systems
• On-chip diagnostic shift register for serial observability
and controllability of the output register
• High speed - 25ns address setup and 15ns clock to
output delay
• Programmable synchronous and asynchronous enables
• Optional synchronous or asynchronous INITIALIZE
• Increased drive capability, 24mA IOL COM'L
• THINOIP, 24-pin, 300-millateral center package
increases overall board density
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ >98%)
• AC performance is factory tested utilizing programmed
test words and columns
• 100% MIL-STO-883C processing
• Guaranteed to INT-STO-123

• Serial access to output register to allow input of
diagnostic control information
• Serial access of output register allows observation of
register data
• Eliminates the need for diagnostics code internal to the
PROM, allowing increased applications code density
• Simplified diagnostics increases system reliability
• Separate diagnostiC register allows real time "snap shot"
of machine state

4-WIDE REGISTERED PROMs WITH SSR DIAGNOSTICS
CONNECTION DIAGRAMS

Am27S65
(1Kx4)

Am27S85
(4K x 4)

Am27S75
(2Kx4)

A7

24

Vee

A7

Vee

A7

Vee

A6

23

As

A6

As

A6

As

As

22

Ag

As

Ag

As

Ag

A4

21

e

A4

Ala

A4

Ala

A3

20

e/ES

A3

"E/ES

A3

All

A2

19

INIT/INITS

A2

INIT/INITS

A2

ElES/INIT/INITS

Al

18

00

Al

00

Al

00

Ao

17

01

Ao

°1

Ao

01

MODE

16

°2

MOOE

O2

MOOE

°2

DeLK

03

DCLK

03

03

10

15

SOl

11

14

SOO

SOl

GND

12

13

PCLK

GNO

DCLK

I-

300MIL-j

SOO
PCLK

1-300MIL-j

Note: Pin 1 is marked for orientation.

SOO

SOl

PCLK

GNO

I-

300MIL-j

BPM·341

IMOX and SSR are trademarks of Advanced Micro Devices, Inc.

2-62

Am27S65jS75jS85
BLOCK DIAGRAMS

Am27S75

Am27S65

64 x 128
PROGRAMMABLE
ARRAY

32x 128
PROGRAMMABLE
ARRAY

MODE---_-I

INIT/iNiTS

PCLK

00

0,

O2

00

03

0,

O2

03

BPM-343

BPM-342

Am27S85

AU
A,O
Ag
AS
A7

128 x 128
PROGRAMMABLE
ARRAY

A6
AS

BPM-344

2-63

Am27S35A • Am27S35
Am27S37A • Am27S37
8K·Bit (1024 x 8J Generic Series IMOX™
Bipolar High Performance Registered PROM with
Programmable INITIAI.IZE

DISTINCTIVE CHARACTERISTICS

GENERIC SERIES CHARACTERISTICS

• Member of AMO's Generic Family of 8-bit wide
registered PROMs
• On-chip edge-triggered registers - ideal for pipelined
microprogrammed systems
• Versatile synchronous and asynchronous enables for
simplified word expansion
• Versatile programmable register INITIALIZE either
asynchronous (Am27S35N35) or synchronous
(Am27S37 N37)
• Slim, 24-pin, 300-millateral center package occupies
approximately 1/3 the board space required by standard
discrete PROM and register
• Consumes approximately 1/2 the power of separate
PROM/register combination for improved system
reliability
• Fast standard version - 40ns max setup and 25ns max
clock-to-output allows system speed improvements
• "Au version offers improved AC performance in critical
paths (35ns max setup and 20ns max clock-to-output)
• Platinum-Silicide fuses guarantee high reliability, fast
programming, and exceptionally high programming
yields (typ>98%)
• AC performance is factory tested utilizing programmed
test words and columns
• 100% MIL-STO-883C processing
• Guaranteed to INT-STO-123

The Am27S35N35 and Am27S37 N37 are members of an
Advanced PROM series incorporating common electrical
characteristics and programming procedures. All parts in
this series are produced with a fusible link at each memory
location storing a logic LOW and can be selectively programmed to a logic HIGH by applying appropriate voltages to
the circuit.
All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
equipment) these products can be rapidly programmed to
any customized pattern. Extra test words are preprogrammed during manufacturing to insure extremely high
field programming yields and produce excellent parametric
correlation.
Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure long-term reliability. Extensive
operating testing has shown that this low-field, large-gap
technology offers the best reliability for fusible link PROMs.
Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltagecompensated bias network to provide excellent parametric
performance over the full military power supply and temperature ranges. Selective feedback techniques have been
employed to minimize delays through all critical paths producing the fastest speeds possible from Schottky processed
PROMs.

BLOCK DIAGRAMS
Am27S37

Am27S35

128 X64
PROGRAMMABLE
ARRAY

128 X 64
PROGRAMMABLE
ARRAY

iNifs - - - - < l I :>----t

cp-I>C~----I

CP

ES
E------I

BPM-309

BPM-310

IMOX is a trademark of Advanced Micro Devices, Inc.

2-64

Am27S35A/S35/S37A/S37
FUNCTIONAL DESCRIPTION
The Am27S35N35 and Am27S37 N37 are Schottky TTL programmable read only memories (PROMs) incorporating true
D-type, master-slave data registers on chip. These devices
feature the versatile 1024-word by 8-bit organization and are
available with three-state outputs. Designed to optimize system
performance, these devices also substantially reduce the cost
and size of pipelined microprogrammed systems and other
designs where accessed PROM data is temporarily stored in a
register. The Am27S35N35 and Am27S37 N37 also offer maximum flexibility for memory expansion and data bus control by
providing both synchronous and asynchronous output enables.
When Vee power is first applied, the synchronous enable (ES)
flip-flop will be in the set condition causing the outputs (00-07) to
be in the OFF or high impedance state. Reading data is accomplished by first applying the binary word address to the address inputs (Ao-Ag) and a logic LOW to the synchronous enable
(ES). During the address setup time, stored data is accessed and
loaded into the master flip-flops of the data register. Since the
synchronous enable setup time is less than the address setup
requirement, additional decoding delays may occur in the enable
path without reducing memory performance. Upon the next
LOW-to-HIGH transition of the clock (CP), data is transferred to
the slave flip-flops which drive the output buffers. Providing the
asynchronous enable (E) is also LOW, stored data will appear on
the outputs (00-07). If Es is HIGH when the positive clock edge
occurs, outputs go to the OFF or high impedance state regardless
of the value of E. The outputs may be disabled at any time by
switching Eto a HIGH level. Following the positive plock edge the
address and synchronous enable inputs are free to change;
changes will not affect the outputs until another positive clock
edge occurs. This unique feature allows the PROM decoders and
sense amplifiers to access the next location while previously
addressed data remains stable on the outputs. For less complex
applications either enable may be effectively eli mated by tying it
to ground.
The on-chip edge-triggered register simplifies system timing
since the PROM clock may be derived directly from system clock

2-65

without introdUCing dangerous race conditions. Other register
timing requirements are similar to those of standard Schottky
registers and are easily implemented.
These devices also contain a built-in initialize function. When
activated, the initialize control input (INIT) causes the contents of
an additional (1025th) 8-bit word to be loaded into the on-Chip
register.This extra word is user programmable. Since each bit is
individually programmable, the initialize function can be used to
load any desired combination of HIGHs and LOWs into the register. In the unprogrammed state, activating INIT will perform a
register CLEAR (all outputs LOW). If all bits of the initialize word
are programmed, activating INIT performs a register PRESET
(all outputs HIGH).
This ability to tailor the initialize outputs to the system requirements simplifies system design and enhances performance. The
initialize function is useful during power up and timeout sequences. This flexible feature can also facilitate implementation
of other sophisticated functions such as a built-in "jump-start"
address.
The Am27S35N35 has an asynchronous initialize input (INIT).
Applying a LOW to the INIT input causes an immediate load of the
programmed initialize word into the slave flip-flops of the register
independent of all other inputs(including CPl. The initialize data
will appear at the device outputs after the outputs are enabled by
bringing the asynchronous enable (E) LOW.
The Am27S37A/37 has a synchronous INITS input. Applying a
LOW to the INITS input causes an immediate load of the programmed initialize word into the master flip-flops of the register
only independent of all other inputs (including CPl. To bring this
data to the device outputs, the synchronous enable (ES) should
be held LOW until the next LOW-to-HIGH transition of the clock
(CP). Following this, the data will appear on the outputs after the
asynchronous enable (E) is brought LOW.

Am27S35A/S35/S37A/S37
CONNECTION DIAGRAMS
Top Views

LOGIC SYMBOL

Chlp-PackTil
L-32-2

DIP

A7

vee

A6

As

As

Ag

As

A,

e-

A,

A3

iNii'tiNii's

A2

ES

A,

CP

Ao

07

00

06

a,

as

02

a,

GND

03

:t

,ll li :t

C

23

22

AI

21

A,
A,

i'NiT,i'NiT.

.

Es

0,

0,

0,

0,

A,

19
18
20

,s

~ cr

li r1

10

11

13

14

15

16

17

BPM·313

rf

BPM·312

BPM·311

VCC=Pin24
GND=Pin 12

Note: Pin 1 is marked for orientation.

AMD's GENERIC FAMILY OF 8-WIDE REGISTERED PROMs

A7

Vee

A7

Vee

A7

Vee

A&

As

A&

As

A&

As

As

PS

As

Ag

As

Ag

A.t

E

A.t

E

A4

A'0

A3

CLR

A3

INIT/1N1TS

A3

INIT/1N1Ts

A2

ES

A2

ES

A2

E/ES

A,

CP

Al

CP

Al

CP

Ao

07

Ao

Or

Ao

07

00

0&

00

0&

00

Os

01

05

01

05

01

05

02

04

02

04

02

04

GND

03

GND

03

GND

Q3

BMP·314

512x8

BPM·315

1024x8

Note: Pin 1 is marked for orientation.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-66

BPM·316

2048x8

Am27S35AjS35jS37AjS37
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

- 65 to + 150°C

Temperature (Ambient) Under Bias

-55 to + 125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

Vee

Temperature

4.75 to 5.25V

4.5to 5.5V

Te = -55 to

+ 125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Min

Test Conditions

Description

VOH

Output HIGH Voltage

Vee = MIN, IOH = - 2.0mA
VIN = VIH or Vil

VOL

Output LOW Voltage

Vee = MIN, IOl = 16mA
VIN = VIH orVll

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 2)

Vil

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 2)

III

Input LOW Current

Vee = MAX, VIN = OA5V

IIH

Input HIGH Current

Vee = MAX, VIN = Vee

Ise

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 3)

ICC

Power Supply Current

All inputs = GND, Vee = MAX

VI

Input Clamp Voltage

Vee = MIN, liN = -18mA

leEX

Output Leakage Current

Vee = MAX
VE; = 2AV

(Note 1)

Max

204

Volts
0.38

0.50

2.0

Volts

Volts

-0.020

-20

Units

-40
130

IVo= Vee
IVo = OAV

0.8

Volts

-0.250

rnA

40

/LA

-90

mA

185

rnA

-1.2

Volts

40
-40

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 4)

5

COUT

Output Capacitance

VOUT = 2.0V@f= 1MHz (Note 4)

12

/LA

pF

Notes: 1. Typical values are at Vee = 5.0V and TA = 25°C.
2. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment (see Notes on Testing).
3. Only one output should be shorted at a time. Duration of the short circuit should not be more than one second.
4. These parameters are not 100% tested, but are periodically sampled.

2-67

Am27S35AjS35jS37AjS37
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (See Notes on Testing)
Am27S35A· Am27S37A
Typ
Parameters

Description

(Note 1)

COM'L
Min
Max

MIL
Min
Max

Am27S35· Am27S37
COM'L
Min
Max

Min

MIL
Max

Units

ts(A)

Address to CP (HIGH) Setup Time

25

35

40

40

45

ns

tH(A)

Address to CP (HIGH) Hold Time

-4

0

0

0

0

ns

tpHdCP)

Delay from CP (HIGH) to
Output (HIGH or LOW)

tpLH(CP)
tWH(CP)

All Outputs
Simultaneous

13

20

25

25

30

Single Output
(Note 3)

11

18

21

20

23

ns

CP Width (HIGH or LOW)

20

20

20

20

ns

twdCP)
tS(Es)

Es to CP (HIGH) Setup Time

5

15

15

15

15

ns

tH(Es)

ES to CP (HIGH) Hold Time

-2

5

5

5

5

ns

tpHdlNIT)

Delay from INIT (LOW) to
Outputs (LOW or HIGH)

20

tpLH(INIT)
tR(INIT)

INIT Recovery (Inactive) to
CP(HIGH)

twdlNIT)

INIT Pulse Width

ts(INITs)

INITS to CP (HIGH)
Setup Time

tH(INITS)
tpzdCP)
tpZH(CP)
tpzd E)
tpZH(E)
tpLZ(CP)
tpHZ(CP)
tpLZ(E)
tpHZ(E)

Am27S35 Only

30

35

40

35

ns

8

20

20

20

20

ns

10

25

30

25

30

ns

18

25

30

30

35

ns

INITS to CP (HIGH)
Hold Time

-5

0

0

0

0

ns

Delay from CP (HIGH) to Active Output
(HIGH or LOW)

15

25

30

30

35

ns

Delay from E (LOW) to Active Output
(HIGH or LOW)

15

25

30

30

35

ns

Delay from CP (H IGH) to Inactive Output
(OFF or High Impedance) (Note 4)

15

25

30

30

35

ns

Delay from E (HIGH) to Inactive Output
(OFF or High Impedance) (Note 4)

10

25

30

30

35

ns

Am27S37 Only

Notes: 1. Typical values are at Vee = 5.0V and TA = 25°C.
' 2 .. Tests are performed with input 10 to 90% rise and fall times of 5ns or less.
3. Single register performance numbers provided for comparison with discrete register test data.
4. tpHZ and tpLZ are measured to the VOH -0.5V and VOL +0.5V output levels respectively. All other switching parameters are tested from and
to the 1.5V threshold levels.

2-68

Am27S35A/S35/S37A/S37
SWITCHING WAVEFORMS
(See Notes on Testing)

3V
1.5V

ov
3Y
1.5V

ov
3V

CP

1.5V
OY

YOH

VOL

i
Am27S35 {INIT
ONLY

'S(iNif~sl
Am26~~ { INITs

'
.
"
'
"
g~.::::

~

3V
I.SV
DV

3V
I.SY

=======================================================================

'H(INITS)

\...I.II._ _ _--'I.L.I

OV

3V

_-_-_-_-_-_-_-_-~_-_-_-_-_-_-_-_-~_-_-_-~_-_-_-_-_-_-_-_-~_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-~_-_-_-_-_-_-_-_-_-_-_-_-~_-_-_-_-_-_-_-_-~_-_-_-_-_

1.5V
OV

BPM-317

NOTES ON TESTING

2. Do not leave any inputs disconnected (floating) during any
test.

Incoming test procedures on these devices should be carefully
planned, taking into account the high performance and output
drive capabilities of the parts. The following notes may be useful.

3. Do not attempt to perform threshold tests under AC conditions. Large amplitude, fast ground current transients
normally occur as the device outputs discharge the load
capacitances. These transients flowing through the parasitic
inductance between the device ground pin and the test system ground can create significant reductions in observable
input noise immunity.

1. Ensure that adequate decoupling capacitance is employed
across the device VCC and ground terminals. Multiple
capaCitors are recommended, including a 0.1 fLFarad or
larger capaCitor and a 0.01 fLFarad or smaller capacitor placed
as close to the device terminals as possible. Inadequate decoupling may result in large variations of power supply voltage, creating erroneous function or transient performance
failures.

KEY TO TIMING DIAGRAM

ACTESTLOAD

WAVEFORM

VCC~
51
R1

-.-

3ool!
OUTPUT
Cl

R2

I

600ll

BPM·040

Notes: 1.
2.
3.
4.

CL = 50pF for all switching characteristics except tpLZ and tpHZ'
CL = 5pF for tpLZ and tpHZ'
S1 is closed for all tests except for tpZH and tPHZ'
All device test loads should be located within 2" of device outputs.

2-69

INPUTS

OUTPUTS

MUST BE
STEADY

Will BE
STEADY

MAY CHANGE
FROM HTO l

WILL BE
CHANGING
FROM H TO l

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

WAVEFORM

---

H

INPUTS

DON'TCARE;
ANY CHANGE
PERMITTED

DOES NOT
APPLY

OUTPUTS

CHANGING;
STATE
UNKNOWN

CENTER
LINE ISHIGH
IMPEDANCE
"OFF" STATE

fa

Am27S35AjS35jS37AjS37
PROGRAMMING

The Am27S35N35 and Am27S37 N37 are manufactured with a
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. The fusible links are
opened one at a time by passing current through them from a 20
volt supply which is applied to the memory output after the E and
INIT/lNITs inputs are at a logic HIGH. Current is gated through
the addressed fuse by raising the Einputfrom a logic HIGH to 15
volts. After SOJLsec, the 20 volt supply is removed, the chip enabled, and the CP input is clocked. Each data verification attempt
must be preceded by a positive going (LOW-to-HIGH) clock
edge to load the array data into the on-chip register. The output
level is then sensed to determine if the link has opened. Most
links will open within 50JLsec. Occasionally a link will be stronger
and require additional programming cycles. The recommended
duration of additional programming periods is Smsec. If a link
has not opened after a total elapsed programming time of
400msec, further programming of the device should not be attempted. Successive links are programmed in the same manner
until all desired bit locations have been programmed to the
HIGHleve/.
The initialize word is programmed by setting the INIT/INITS input
to a logic LOW and programming the desired initialize word,
output by output, in the same manner as any other address location. This is easily implemented by inverting the A10 address
input from a PROM programmer and applying this signal to the
INIT/lNITs input. Using this method the initialize word would be
programmed as address 1024.

When INIT/INITS is asserted LOW the internal programming circuitry for all other addresses is deselected.
Typical current into an output during programming will be approximately 140mA until the fuse link is opened, after which the
current drops to approximately 40mA. Current into the E pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
continuously applied to one device more than S seconds to
avoid heat damage. If this programming time is exceeded, all
power to the chip including Vee should be removed for a period
of S seconds after which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by clocking and reading all
words. Occasionally this verification will show that an extra undesired link has been fused. Should this occur, immediatelY
check the programming equipment to make sure that all device
pins are firmly contacting the programming socket, that the input
Signal levels exhibit sufficient noise margins, and that the programming voltages are within the specified limits. All of these
conditions must be maintained during programming. AMD
PROMs are thoroughly tested to minimize unwanted fusing;
fusing extra bits is generally related to programming equipment
problems.

2-70

Am27S35A/S35/S37A/S37
PROGRAMMING PARAMETERS
Min

Max

Veep

Vee During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VENP

E Voltage During Programming

14.5

15.5

Volts

VOP

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

Parameters

d(Va::.i)/dt
tp

Description

0

Veep

+ 0.3

Units

Volts

20

mA

20

250

V/f.Lsec
Vlf.Lsec

Rate of E Voltage Change

50

1000

Programming Period - First Attempt

50

100

f.Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., notto the midpoints.
2. Delays t1 through ta must be greater than 100ns; maximum delays of 1f.Lsec are recommended to minimize heating during programming.
3. During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
4. Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

SIMPLIFIED PROGRAMMING DIAGRAM

PROGRAMMING WAVEFORMS

v-......_______________
L..
SELECTED ADDRESS STABLE

VIHP
V1LP

,----.....,.·------1--

VENP

VONP

El
ENABLE

PROGRAMMED
OUTPUT

~---~-r~~~~VOH
~\ OUTPUT"

~E~r- ~~HLp

CP
CLOCK

i------PROGRAMMING C y C L E - - - - - I 1

VILP

BPM·318
BPM·319

2-71

Am27S35A/S35/S37A/S37
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data 1/0
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City,
Scottsdale, AZ 85260
CA94063

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

Programmer
Model(s)

ModelS, 7, and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev G*
919-1286-1 Rev G*
Unipak Rev H 003
(Code 6266)

PM 9058

IMAMDGEN1

MOD 14

PM 102

FAM-12

PM 2000
Code 90

715-1723

PA24-18 and
1025x8(L)

1M 1024 x 8-275351
37-AMD

5A31-1 B
1024 x 8124

D15-218AM

DA65

AM 190-3

Socket Adapters
Am27S35
Am27S37

• Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, however, much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

ORDERING INFORMATION
Order Code
Asynchronous
INITIALIZE

Synchronous
INITIALIZE

Package
Type
(Note 1)

Screening
Flow Code
(Note 2)

Operating
Range
(Note 3)

35ns

AM27S35APC
AM27S35APCB
AM27S35ADC
AM27S35ADCB
AM27S35ALC
AM27S35ALCB

AM27S37APC
AM27S37APCB
AM27S37ADC
AM27S37ADCB
AM27S37ALC
AM27S37ALCB

P-24-1AA(Note4)
P-24-1AA (Note 4)
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

40ns

AM27S35ADM
AM27S35ADMB
AM27S35AFM
AM27S35AFMB
AM27S35ALM
AM27S35ALMB

AM27S37ADM
AM27S37ADMB
AM27S37AFM
AM27S37AFMB
AM27S37ALM
AM27S37ALMB

D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
B-3
C-3
B-3
C-3
B-3

MIL

40ns

AM27S35PC
AM27S35PCB
AM27S35DC
AM27S35DCB
AM27S35LC
AM27S35LCB

AM27S37PC
AM27S37PCB
AM27S37DC
AM27S37DCB
AM27S37LC
AM27S37LCB

P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

45ns

AM27S35DM
AM27S35DMB
AM27S35FM
AM27S35FMB
AM27S35LM
AM27S35LMB

AM27S37DM
AM27S37DMB
AM27S37FM
AM27S37FMB
AM27S37LM
AM27S37LMB

D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
B-3
C-3
B-3
C-3
B-3

MIL

Speed
Selection
(Setup Time)

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
4. This package will be available soon. Consult Factory.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding diagram
available upon request.

2-72

Am27S180A· Am27S181A
Am27S280A • Am27S281A
Ultra Fast Access Time

Am27S180· Am27S181
Am27S280 • Am27S281.
Fast Access Time
1024 x 8 Bit Generic Series Bipolar IMOX™ PROM

DISTINCTIVE CHARACTERISTICS
Part Number

Package Width

Am27S180A
Am27S181A
Am27S180

Other Features
Ultra fast - 35ns max

24-Pin, Plug in Replacement for Industry Standard
600-mil Configuration No Board Changes Required
Fast - 60ns max

Am27S181
Am27S280A
Am27S281A
Am27S280

Ultra fast - 35ns max
New Space-Saving 24-Pin, THINDIP, 300-mil
Configuration Increases Overall Board Density

Am27S281

IMOX is a trademark of Advanced Micro Devices, Inc.

2-73

Fast - 60ns max

Am27S180A/S181A/S280A/S281A/S180/S181/S280/S281
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ > 98%)

These 8K PROMs are high speed electrically programmable
Schottky read only memories. Organized in the industry standard 1024 x 8 configuration, they are available in both open
collector (Am27S180A{180 and Am27S280A{280) and threestate (Am27S 181 A/181 and Am27S281{281) output versions.
After programming, stored information is read on outputs 00-07
by applying unique binary addresses to AO-Ag and holding CS1
and CS2 LOW and CS3 and CS4 HIGH. All other valid input
conditions on CS1, CS2, CS3 and CS4 place 00-07 into the
OFF or high impedance state.

• AC performance is factory tested utilizing programmed test
words and columns
• Voltage and temperature compensated providing extremely
flat AC performance over military range
• Members of Generic PROM series utilizing standard
programming algorithm
• 100% processed to MIL-STD-883C
• Guaranteed to INT-STD-123

BLOCK DIAGRAM
COLUMN TEST RAIL

GENERIC SERIES CHARACTERISTICS

These 8K PROMs are members of an Advanced PROM series
incorporating common electrical characteristics and programming procedures. All parts in this series are produced with a
fusible link at each memory location storing a logic LOW and
can be selectively programmed to a logic HIGH by applying
appropriate voltages to the circuit.

64 x 128
PROGRAMMABLE
ARRAY

TEST WORD 0

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming equipment) these products can be rapidly programmed to any customized pattern. Extra test words are pre-programmed during
manufacturing to insure extremely high field programming yields
and produce excellent parametric correlation.
Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long-term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

BPM·307

LOGIC DIAGRAM

Common design features include active loading of all critical AC
paths regulated by a built-in temperature and voltage compensated bias network to provide excellent parametric performance
over MIL supply and temperature ranges. Selective feedback
techniques have been employed to minimize delays through all
critical paths.

876543212322

Ao A1 A2 A3 A4 As A6 A7 As Ag

21

These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOX. This advanced
process combined with a merged fuse array permits an increase
in density and a decrease in internal capacitance resulting in
the fastest possible PROMs.

CS 1

20

CS2

19

CS 3

18

CS 4

9

10 11 .13 14 15 16 17

BPM-099

Vee = Pin 24
GND = Pin 12

CONNECTION DIAGRAMS - Top Views
DIP

Chip-Pak™

BPM-279

Note: Pin 1 is marked for orientation.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-74

Am27S180A/S181A/S280A/S281A/S180/S181/S280/S281
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

- 0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

- 0.5 to + 5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

Vee

Temperature

4.75 to 5.25V
4.5 to 5.5V

Te = -55 to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH (Note 2)

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
V,N = V,H or V,l

VOL

Output LOW Voltage

Vee = MIN, IOl = 16mA
V,N = V,H or V,l

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

Vll

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

III

Input LOW Current

Vee = MAX, V,N = 0,45V

I'H

Input HIGH Current

Vee = MAX, V,N = Vee

Ise(Note2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV
(Note 4)

lee

Power Supply Current

All inputs = GND, Vee = MAX

VI

Input Clamp Voltage

Vee = MIN, liN = -18mA

leEX

Output Leakage Current

Vee = MAX
VCS1 = 2,4V

Min

(Note 1)

Max

2,4

Volts
0.50

2.0
0.8

Volts

-0.250

rnA

40

J.tA

-20

-40

-90

-15

-40

-90

115

I Vo= Vee
I Vo = O,4V

rnA

185

rnA

-1.2

Volts

40
J.tA
-40

C'N

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 5)

4.0

COUT

Output Capacitance

VOUT = 2.0V @f = lMHz (Note 5)

8.0

Notes: 1. Typicallirnits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shQrted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but are periodically sampled.

2-75

Volts
Volts

-0.010

I COM'L
I MIL

Units

pF

Am27S180A/S181A/S280A/S281A/S180/S181/S280/S281
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Typ

Max

5V25°C
Description

Parameters

Test Conditions

tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(5ee Notes 1, 2, 3)

COM'L

MIL

A

STD

A

STD

A

STD

25

30

35

60

50

80

ns

10

10

25

40

30

50

ns

10

10

25

40

30

50

ns

Units

Notes: 1. tAA is tested with switch 51 closed and CL = 30pF.
2. For open collector outputs, tEA and tER are tested with 51 closed to the 1.5V output level. CL = 30pF.
3. For three-state outputs, tEA is tested with CL = 30pF to the 1.5V level; 51 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made to an output voltage to with 51 open to VOH
- 0.5V with 51 open; LOW to high impedance tests are made to the VOL + 0.5V level with 51 closed.

SWITCHING WAVEFORMS

3.0V

~A·3
cs 3 , cS4
Cs

Cs2

"

1.5V
OV

t,,,~

I
I
~tAA--1

»»>-::~ :,',~ @«

XXX*

00.0 7

t'~-1

1.5V

ov
VOH
I.SV
VOL

Note: Level on output while chip is disabled is determined externally.
BPM·101

KEY TO TIMING DIAGRAM

WAVEFORM

INPUTS

OUTPUTS

-----

MUST BE
STEADY

WILL BE
STEADY

--

l!JJJJ

--

WAVEFORM

WILL BE
MAY CHANGE CHANGING
FROM H TO L FROM H TO L

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

WILL BE
MAY CHANGE
CHANGING
FROM L TO H FROM
L TO H

ACTESTLOAD

:

vcc~o--S,
R,
300n

OUTPUT

cj

R2
600n

-=
BPM·208

2-76

Am27S180A/S181A/S280A/S281A/S180/S181/S280/S281
PROGRAMMING
the current drops to approximately 90mA. Current into the CS1
pin when it is raised to 15 volts is typically 1.5mA.

The entire Generic PROM Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the
devices, the fusible links are selectively opened.

The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to the
memory output after the CS1 input is at a logic HIGH. Current is
gated through the addressed fuse by raising the CS1 input from
a logic HIGH to 15 volts. After 50J,Lsec, the 20 volt supply is
removed, the chip is enabled tmd the output level is sensed to
determine if the link has opened. Most links will open within
50J,Lsec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be
approximately 180mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Parameters

Description

Min

Max

Units
Volts

Vccp

Vcc During Programming

5.0

5.5

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCS1P

CS1 Voltage During Programming

14.5

15.5

Volts

VOP

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

0

Vccp + 0.3

Volts

IONP

Current into Outputs Not to be Programmed

20

rnA

d(Vop)/dt

Aate of Output Voltage Change

20

250

V/J.Lsec
V/J.Lsec

d(VCS1)/dt

tp
Notes: 1.
2.
3.
4.

Aate of CS1 Voltage Change

100

1000

Programming Period - First Attempt

50

100

J.Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of 1J.Lsec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load A and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor A which provides output current limiting.

SIMPLIFIED PROGRAMMING DIAGRAM

PROGRAMMING WAVEFORMS

ADIDNRpEUSTSS

-vl-_-d-------------v.....A.

dt

V(CSll _____

ENABLE

~d
'

--1l"

PROGRAMMED
OUTPUT

h
•

"

'L- -,

I

(Vop)

1\
!

1'1::

I '

I

dt

\
PROGRAMMING CYCLE

VVIIHLPP

Vcs,p

\

C

VONP

1

~

SELECTED ADDRESS STABLE

CSt

Vccp

~~1:;~J ;1
\"';':-,-

lKx8
PROM

v
OH
VOL

BPM-209

BPM-308

2-77

fa

Am27S180A/S181A/S280A/S281A/S180/S181/S280/S281
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Sourceard
Location

Data 1/0
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City, CA 94063 Scottsdale, AZ 85260

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920 and M980

IM1010

MPP-80

UPP-801

UPP-803 PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev HO
919-1286-1 Rev HO
Unipak Rev KO
(Code 16 37)

PM 9058

IMAMDGEN1

MOD14

PM 102

FAM-12

PM 2000
Code 90

Am27S180A/181A
Am27S180/181

715-1545-2

PA24-13 and
1024x8(L)

1M 1024 x 8-24AMD

SA 22-7 B 1024 x 8/24

DIS-137AM

DA29

AM1oo-6

Am27S280A/281A
Am27S280/281

715-1545-3

PA24-28 and
1024 x 8(L)

27S280/281-AMD

SA 29 B 1024 x 8/24

DIS-214AM

DA60

AM190-6

1M 1024 x 8-24-

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

• Rev shown is minimum approved revision.
OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

2-78

Am27S180AjS181 AjS280AjS281 AjS180jS181jS280jS281
ORDERING INFORMATION
Order Code
Speed
Selection

Open
Collector

Three-State

Package
Type

Flow Code

Operating
Range

Screening

(Note 1)

(Note 2)

(Note 3)

35ns

AM27S180APC
AM27S180APCB
AM27S280APC
AM27S280APCB
AM27S180ADC
AM27S180ADCB
AM27S280ADC
AM27S280ADCB
AM27S180ALC
AM27S 180ALCB

AM27S181APC
AM27S181APCB
AM27S281APC
AM27S281APCB
AM27S181ADC
AM27S181ADCB
AM27S281ADC
AM27S281ADCB
AM27S181ALC
AM27S181ALCB

P-24-1AC
P-24-1AC
P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AC
D-24-1AC
D-2A-1AA
D-24-1AA
L-32-2
L-32-2

C-l
B-1
C-l
B-1
C-l
B-1
C-l
B-'
C-l
B-1

COM'L

SOns

AM27S180ADM
AM27S180ADMB
AM27S280ADM
AM27S280ADMB
AM27S180AFM
AM27S 180AFMB
AM27S 180AlM
AM27S180AlMB

AM27S181ADM
AM27S181ADMB
AM27S281ADM
AM27S281ADMB
AM27S181AFM
AM27S181AFMB
AM27S181ALM
AM27S181ALMB

D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
B-3
C-3
B-3
C-3
B-3
C-3
B-3

MIL

60ns

AM27S180PC
AM27S180PCB
AM27S280PC
AM27S280PCB
AM27S180DC
AM27S180DCB
AM27S280DC
AM27S280DCB
AM27S180LC
AM27S180LCB

AM27S181PC
AM27S181PCB
AM27S281PC
AM27S281PCB
AM27S181DC
AM27S181DCB
AM27S281DC
AM27S281DCB
AM27S181LC
AM27S181LCB

P-24-1AC
P-24-1AC
P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-l
B-1
C-l
B-1
C-l
B-1
C-'
B-1
C-l
8-1

COM'L

80ns

AM27S180DM
AM27S180DMB
AM27S280DM
AM27S280DM8
AM27S180FM
AM27S180FMB
AM27S180LM
AM27S180LMB

AM27S181DM
AM27S181DM8
AM27S281DM
AM27S281DMB
AM27S181FM
AM27S181FM8
AM27S181LM
AM27S181LMB

D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
F-24-1
F-24-1
l-32-2
L-32-2

C-3
8-3
C-3
B-3
C-3
8-3
C-3
8-3

Mil

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
AC = 600 mil center package. AA = 300 mil center package.
2. Levels C-l and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and 8-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
4. This package will be available soon. Consult factory.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding diagram
available upon request.

2-79

Am27PS181A • Am27PS281A
Am27PS181 • Am27PS281
Ultra Fast Access Time

Fast Access Time
8,192-8it Generic Series 'MOX"" Bipolar PROM
1 024 x 8 8its with Power-Down Via CS 1
PRELIMINARY DATA

DISTINCTIVE CHARACTERISTICS
Part Number

Package Width

Am27PS181A

24-Pin, Plug in Replacement for Industry Standard
600-mil Configuration No Board Changes Required

Am27PS181
Am27PS281A
Am27PS281

New Space-Saving 24-Pin, THINDIP, 300-mil
Configuration Increases Overall Board Density

IMOX is a trademark of Advanced Micro Devices, Inc.

2-80

Other Features
Ultra fast - 50ns max
Fast - 65ns max
Ultra fast - 50ns max
Fast - 65ns max

Am27PS181A/PS281A/PS181/PS281
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time allows high system speed
• 50% power savings on deselected parts - enhances
reliability through total system heat reduction
• Plug in replacement for industry standard product no board changes required
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ > 98%)
• AC performance is factory tested utilizing programmed test
words and columns
• Voltage and temperature compensated providing extremely
flat AC performance over military range
• Rapid recovery from power-down state provides
minimum delay
• Members of generic PROM series utilizing standard
programming algorithm
• 100% processed to MIL-STD-883C
• Guaranteed to INT-STD-123

These 8K PROMs are high speed electrically programmable
Schottky read only memories. Organized in the industry standard 1024 x 8 configuration, they are available in both the
standard 600-mil package (Am27PS181A1181) and the spacesaving THINDIP, 300-mil package (Am27PS281A/281)
versions. After programming, stored information is read on outputs 00 - 07 by applying unique binary addresses to Ao - Ag
and holding CS1 and CS2 LOW and CS3 and CS4 HIGH. All
other input combinations on CS1. CS2, CS3 and CS4 place
00 - 07 into the OFF or high impedance state and reduce ICC
by more than 50%.

BLOCK DIAGRAM

12BX64
PROGRAMMABLE
ARRAY

GENERIC SERIES CHARACTERISTICS
These 8K PROMs are members of an Advanced PROM series
incorporating common electrical characteristics and programming procedures. All parts in this series are produced with a
fusible link at each memory location storing a logic LOW and
can be selectively programmed to a logic HIGH by applying appropriate voltages to the circuit.
All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming personality card sets) these products can be rapidly programmed to
any customized pattern. Extra test words are pre-programmed
during manufacturing to insure extremely high field programming yields, and produce excellent parametric correlation.

BPM-303

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long-term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

CONNECTION DIAGRAMS - Top Views
DIP

Common design features include active loading of all critical AC
paths regulated by a built-in temperature and voltage compensated bias network to provide excellent parametric performance
over MIL supply and temperature ranges. Selective feedback
techniques have been employed to minimize delays through all
critical paths.
A7

These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOX. This advanced
process combined with a merged fuse array permits an increase
in density and a decrease in internal capacitance resulting in the
fastest possible PROMs.

As

As

A4

A3

A,

Ao

00

Chip-Pak™
L-32-2
:t .c !i
Jl

c·

A2

.

A,

CS1

"

LOGIC SYMBOL

02 GND

0,

A,

8

21
20

7

6

5

CSi
CS2

4

3

2

1

23 22

CS2

A,

cs,

Ao

cs,

D.

0,

0,

0,

8K
PROM
1024 x 8

19 CS3
18 CS4

Vee = Pin 24
GNDPin 12

A,

(j

9

10

11

13

14

15

16

17

c5'

,; &'

Note: Pin 1 is marked for orientation.

BPM-302

Chip-Pak is a trademark of Advanced Micro Devices, Inc.
2-81

BPM-304

Am27PS181AjPS281AjPS181jPS281
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65to +150°C

Temperature (Ambient) Under Bias

- 55 to + 125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

- 0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

- 0.5V to + VCC max

21V

DC Voltage Applied to Outputs During Programming
Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5to +5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

Vee

Temperature

4.75 to 5.25V
4.5to 5.5V

Te = -55to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN, IOH = -2.0rTiA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Ise

Output Short Circuit Current

lee

Power Supply Current

All inputs = GND

leeD

Power Down Supply Current

CS1 = 2.7V

VI

Input Clamp Voltage

Vee = MIN, liN = -1BmA

2.4

Volts
0.50

Output Leakage Current

Volts

-0.010

Volts

-0.250

mA

40

I COM'L
I MIL

-20

-40

-90

-15

-40

-90

115

1B5

50

BO

/LA
mA

mA

-1.2

Volts

40
/LA
-40

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 3)

4.0

COUT

Output Capacitance

VOUT = 2.0V@f = 1MHz (Note 3)

8.0

Notes: 1.
2.
3.
4.

O.B

I Vo= Vee
I Vo = O.4V

Ves 1 = 2.4V

Volts

2.0

I All other inputs = GND

Vee = MAX

Units

Max

(Note 1)

Vee = MAX, VIN = Vee
Vee = MAX, VOUT = O.OV
(Note 2)

leEX

Min

pF

Typical limits are at Vee = 5.0V and TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
PRELIMINARY

Typ

Max
MIL

Parameters
tAA1
tAA2

tEA

A

STD

Units

65

65

75

ns

65

BO

75

90

ns

65

BO

75

90

ns

25

35

30

45

ns

Description
Address Access Time

Enable Access Time
15

1;P:Y

~'!~9J5F:'

6. tEA is tested with CL = 3oP5.~gJHe
I
; 'S1 is open for high impedance to HIGH tests and closed for high impedance to LOW tests. tER is
tested with CL = 5pF. HIG~J? high Impedance tests are made with S1 open to an output voltage of VOH -0.5V with S1 open; LOW-to-high
impedance tests are made to the VOL +0.5V level with S1 closed.

2-82

Am27PS181A/PS281A/PS181/PS281
SWITCHING WAVEFORMS

Note: Level on output while chip is disabled
is determined externally.

Figure 1.

BPM·305

ACTESTLOAD

KEY TO SWITCHING WAVEFORMS
WAVEFORM

VCC~=T1

---

--

S,

---

R,

300!!

OUTPUT

LI

C

R,

60011
7

JJJJJJ

Figure 2.

BPM-145

NOTES ON POWER SWITCHING
The Am27PS181A/181 and Am27PS281A/281 are power
switched devices. When the chip is selected, important internal
currents increase from small idling or standby values to their
larger selected values. This transition occurs very rapidly,
meaning that access times from the powered-down state are
only slightly slower than from the powered-up state. Deselected,
lee is reduced to less than half its full operating amount. Due to
this unique feature, there are special considerations which
should be followed in order to optimize performance:

Typicallvee Current Surge without 0.1JLF
(Ivee is Current Supplied by Vee Power Supply)

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

--

WAVEFORM

INPUTS

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

WILL BE
CHANGING
FROM L TO H

Figure 3.

1. When the Am27PS181A/181 and Am27PS281A/281 are
selected, a current surge is placed on the Vee supply due to
the power-up feature. In order to minimize the effects of this
current transient, it is recommended that a 0.1JLf ceramic
capacitor be connected from pin 24 to pin 12 at each device.
(See Figure 4.)
2. Address access time (tM) can be optimized if a chip enable
setup time (tEAS) of greater than 25ns is observed. Negative
setup times on chip enable (tEAS < 0) should be avoided.
(For typical and worse case characteristics, see Figure 5.)

Typicallvee Current Surge with 0.1 JLF
(Ivee is Current Supplied by Vee Power Supply)

~1 3~~~__+--+__~~-4--~-+__1

~1 3 ~-J-~--~-+--

~~
~
0

I~ g 0 ~-+---4--~-+--+---t'--I---+--+-i

g

I

~

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

--

- - - - ----

c==

~~

t-"1----t---t--+--t--+,"__-+-+--I

120 1--+---t--+--+--+--+-~['\.-t---t--+---4
110 1---+----t--+--+--~-+f_\I,--~-+--1
100 f--90

110
100

1---+-4--~-+--+---t---if--+--+__1
~-+-~--+--+-4--+--t----t-/-:::l;.;_

1 :~701--+-~--~~~--+---t----J~/--t--+---4
-r-.. "
/

~~ ~~,---t--+--+--~-H-4--~-+__1

E

~ :~ t=~;=j~::~r-..=~~::.t=_=-jl-ff-_ -_~-_--1-+_-_--+-+_--I-l
.2

o

100

200

300

400

500

TIME -

600

700

BOO

I

601---+--4--~~
~~+---t-~f--+---+__1

.2

40L-.....J...---J_....L...---L._ _-'---'----JL-....L...---L.~

~ 501---+--4--~-+-~~=-~~--if---+---+

40 L-.....J...---J_....L...---L._-'---'-_L........I...---'---'

o

900 1000

100

200

300

400

ns-

500

600

700

BOO 900 1000

TIME - n s -

Figure 4. lee Current

BPM-146

BPM-147
30
201-+---+--+--+---+--+--1
10 ~+--t--~-+---+--+--I

~

0

A

;. -101------'--''---'-\--+---+---+--+_-I
tEA TYP

-20

I

-20

"-

-30 '---'---'-_J.....,;......- - l . _ - ' - - . . . J
20 30 40 50 60 70 80 90

-3~~0~3~0~40~5~0~6~0~70~~BO~90
IAA -

BPM-148

\

~~I= :i~v -"Id-",--I-+--+---t
lEA - ns ___

ns-

Figure SA. tAA versus tEAS

Figure 58. tEA versus tAES

2-83

BPM·149

Am27PS181AjPS281AjPS181jPS281
PROGRAMMING
The entire Generic PROM Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the
devices, the fusible links are selectively opened.

the current drops to approximately 90mA. Current into the CS1
pin when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to the
memory output after the CS1 input is a logic HIGH. Current is
gated through the addressed fuse by raising the CS1 input from
a logic HIGH to 15 volts. After 50JLsec, the 20 volt supply is
removed, the chip is enabled and the output level is sensed to
determine if the link has opened. Most links will open within
50JLsec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be
approximately 180mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Parameters

Description

Min

Max

Units
Volts

Veep

Vee During Programming

5.0

5.5

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCS1P

CS1 Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

0

Veep + 0.3

Volts

VONP

Voltage on Outputs Not to be Programmed

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

d(VCS1)/dt

Rate of CS 1 Voltage Change

tp
Notes: 1.
2.
3.
4.

20

rnA

20

250

V/JLsec
V/JLsec

100

1000

Programming Period - First Attempt

50

100

JLsec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints;
Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of 1JLsec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM
vccP

VONP

1
AO·Ag

R .. 2000

~

c:)

01

r.:
CS4

v 1HP

1Kx8
PROM

~

··
·
r-:o.......
07

CSl

-:1-

~

0--

I

I
I
0--

I

-411.
BPM-209

2-84

-:-

VCS1P

11.
-:-

vOP

BPM-306

Am27PS181A/PS281A/PS181jPS281
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond. WA 98052

Pro-log Corporation
2411 Garden Road
Monterey. CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn. CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City. CA 94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale. AZ 85260

Programmer
Model(s)

Model 5. 7. and 9
Systems 17. 19 and 29

M900. M900B. M910.
M920 and M980

IM1010

MPP·80

UPP-801

UPP-803 PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev HO
919-1286-1 Rev HO
Unipak Rev H·
(Code 16 37)

PM 9058

IMAMDGEN1

MOD14

PM 102

FAM-12

PM 2000
Code 90

Am27PS181N
181

715-1545-2

PA24-13 and
1024x8(L)

1M 1024 x 8-24AMD

SA 22-7 B 1024 x 8/24

DIS-137AM

DA61

AM100-6

DIS-214AM

DA60

Am27PS281N
281

1M 1024 x 8-2427S280/281-AMD

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale. CA 94086

• Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

2-85

Am27PS181A/PS281A/PS181/PS281
ORDERING INFORMATION
Speed
Selection

Order Code
Three-State

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

50ns

AM27PS181APC
AM27PS181APC8
AM27PS281APC
AM27PS281APC8
AM27PS181ADC
AM27PS181ADC8
AM27PS281ADC
AM27PS281ADC8
AM27PS181ALC
AM27PS181ALC8

P-24-1AC
P-24-1AC
P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1

COM'L

65ns

AM27PS181ADM
AM27PS181ADM8
AM27PS281ADM
AM27PS281ADM8
AM27PS181AFM
AM27PS181AFM8
AM27PS181ALM
AM27PS181ALM8

D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3
C-3
8-3

MIL

65ns

AM27PS181PC
AM27PS181PC8
AM27PS281PC
AM27PS281PC8
AM27PS181DC
AM27PS181DC8
AM27PS281DC
AM27PS281DC8
AM27PS181LC
AM27PS181LC8

P-24-1AC
P-24-1AC
P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1

COM'L

75ns

AM27PS181DM
AM27PS181DM8
AM27PS281DM
AM27PS281DM8
AM27PS181FM
AM27PS181FM8
AM27PS181LM
AM27PS181LM8

D-24-1AC
D-24-1AC
D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3
C-3
8-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is
number of leads. AC = 600 mil center package. AA = 300 mil center package.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
4. This package will be available soon. Consult factory.
This device is also available in die form selected to commercial and military specifications. Pad layout
and bonding diagram available upon request.

2-86

Am27S 184A • Am27S 185A
Am27S184· Am27S185
8192·Bit Generic Series Bipolar 'MOX™ PROM
(2048 x 4 bits with ultra fast access time)

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Ultra fast access time "A" version (35ns max) Fast access time Standard version (50ns max) allow tremendous system speed improvements

The Am27S184A and Am27S185A, Am27S184 and
Am27S185 are high speed electrically programmable
Schottky read only memories. Organized in 2048 x 4
configuration, they are available in both open collector
(Am27S184A and Am27S184) and three-state
(Am27S185A and Am27S185) output versions. After
programming, stored information is read on outputs 0 0-03
by applying unique binary addresses to Ao-A1O and holding
the chip select input, CS LOW. If the chip select input
goes to a logic HIGH, 0 0 -03 go to the OFF or high impedance state.

• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming yields
(typ> 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing
extremely flat AC performance over military range
• Member of generic PROM series utilizing standard
programming algorithm

BLOCK DIAGRAM

• 100% MIL-STD-883C assurance testing
COLUMN TEST RAIL

• Guaranteed to INT-STD-123
Ag
As

GENERIC SERIES CHARACTERISTICS

128 X 64
FUSE ARRAY

A7

These 8K PROMs are members of an Advanced PROM
series incorporating common electrical characteristics and
programming procedures. All parts in this series are produced with a fusible link at each memory location storing a
logic LOW and can be selectively programmed to a logic
HIGH by applying appropriate voltages to the circuit.

A6

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words
are pre-programmed during manufacturing to insure
extremely high field programming yields, and produce
excellent parametric correlation.

A,o

As
A.
AJ

TEST ROW 0
TEST ROW 1

A2
A,
Ao

cs

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
non-conductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

CONNECTION DIAGRAMS - Top Views
Chip-PakTM
L-28-2

DIP

,,~

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths.

A7

AS

As
Ag

00
0,

These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOXTM. This
advanced process permits an increase in density and a
decrease in internal capacitance resulting in the fastest
possible PROMs.

A,
A,

Ao
A,

O2
A,

03

cs

AlO

BPM-108

I~

Note: Pin 1 is marked for orientation.
IMOX is a trademark of Advanced Micro Devices, Inc.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

>

Vee

2-87

0'
BPM-257

Am27S184A/S185A/S184/S185
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 18 to Pin 9) Continuous

-0.5to

DC Voltage Applied to Outputs (Except During Programming)

+ 7.0V

- 0.5V to + VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

- 0.5 to + 5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

Vee

Temperature

LOGIC SYMBOL

4.75 to 5.25V
4.5t05.5V

AO

Te = -55to +125°C

Al
A2
A3
A4

cs

As

17

A6
A7

16
15

As
Ag

8

A 10

Vee = Pin 18
GND= Pin9

00

01

O2

03

14

13

12

11

10

BPM-107

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ

Parameters

Description

Test Conditions

Min

VOH (Note 2)

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
VIN = VIH orVIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Vee = MAX, VIN = Vee

Ise(Note2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

lee

Power Supply Current

All inputs = GND,
Vee = MAX

VI

Input Clamp Voltage

Vee = MIN, liN = -18mA

Output Leakage Current

Vee = MAX
Vcs = 2.4V

leEX

(Note 1)

Max

2.4

Volts
0.50

2.0
0.8

Volts

-0.250

mA

40

p.A

-45

-90

mA

105

150

mA

-1.2

Volts

I Vo = Vee

40
p.A

lVo = O.4V

-40

CIN

Input Capacitance

VIN = 2.0V @f = 1MHz (Note 5)

5.0

COUT

Output Capacitance

VOUT = 2.0V @ f = 1MHz (Note 5)

8.0

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but are periodically sampled.

2-88

Volts
Volts

-0.020

-20

Units

pF

Am27S184AjS185AjS184jS185
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE
Typ

Max

Parameters

Test Conditions

Description

tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(5ee Notes 1,'2, 3)

MIL

COM'L

5V25°C
A

STD

A

STD

A

STD

Units

28

30

35

50

45

55

ns

10

10

25

25

30

30

ns

10

10

25

25

30

30

ns

Notes: 1. tAA is tested with switch 51 closed and CL = 30pF.
2. For open collector outputs, tEA and tER are tested with 51 closed to the 1.5V output level. CL = 30pF.
3. For three-state outputs, tEA is tested with CL = 30pF to the 1.5V level; 51 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with 51 open to an output voltage of VOH - 0.5V;
LOW to high impedance tests are made with 51 closed to the VOL + 0.5V level.

, . . - - - - - - - - - - - ,

SWITCHING WAVEFORMS
~_
~

_ _- - 3 ' O V

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1.5V

I----i_

~I---_l_
~'AA---i

0

0 -0

3

~'---'EA--j-

l-'ER-1

OV

1 5V
.

OV

=-----m~====wt-+-~--::::-:'-t-++-o(W..H-~:
Note: Level on output while C5 is HIGH is determined externally.

BPM-109

KEY TO TIMING DIAGRAM

WAVEFORM

-JJ[JJJ

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM HTO L

WILL BE
CHANGING
FROM HTO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

--

WAVEFORM

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMmED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

R1

300n
OUTPUT

0 - - - + - - -.....
R2

"r
2-89

600n

BPM-199

fa

Am27S184AjS185AjS184jS185
PROGRAMMING
This entire Generic PROM Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the device, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS input is a logic HIGH. Current is
gated through the addressed fuse by raising the CS input from a
logic HIGH to 15 volts. After 50p-sec, the 20 volt supply is
removed, the chip is enabled, and the output level sensed to
determine if the link has opened. Most links will open within
50p-sec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.
Typical current into an output during programming will be approximately 180mA until the fuse link is opened, after which the

current drops to approximately 90mA. Current into the CS pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Description

Parameters

Min

Max

Units

Vccp

Vcc During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts
Volts

VCSP

CS Voltage During Programming

14.5

15.5

VOP

Output Voltage During Programming

19_5

20.5

VONP

Voltage on Outputs Not to be Programmed

0

Vccp

Volts

+ 0.3

Volts

IONP

Current into Outputs Not to be Programmed

20

mA

d(Vop)/dt

Rate of Output Voltage Change

20

250

V//Lsec

d(VCSp)/dt

Rate of CS Voltage Change

100

1000

VI/Lsec

Programming Period - First Attempt

50

100

/Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

tp
Notes: 1.
2.
3.
4.

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1. t2. t3 and t4 must be greater than 100ns; maximum delays of 1/Lsec are recommended to minimize heating during programming.
During tv. a user defined period. the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM

Vccp

A~~:~~~

-:J.I,1..-______________C
SELECTED ADDRESS STABLE

~ (Vcsp)

cs

'"OO~~~
ENABLE

-y

~l" I~ ~
L
-,

I

I

VIHP
VILP

~

I\

I

2Kx4
PROM

'.'

~ ~", r--I~= : :
\~~lj_

dl

PROGRAMMING CYCLE

I

IL

VOP

VOL

BPM-259

BPM-260

2-90

Am275184A/5185A/5184/5185
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data 1/0
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ 85260

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

Programmer
Model(s)

ModelS, 7, and 9
Systems 17, 19,29 & 100

M900, M9GOB, M910,
M920, and M980

IM10l0

MPP-80

UPP-801

UPP-803

PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 RevH*
919-1286-1 Rev H*
Unipak Rev H*
(Code 1606)

PM 9058

IMAMDGENl

MOD 14

PM 102

FAM-12

PM 2000
Code 90

PA 18-8 and
2048 x 4(L)

1M 2048 x 4-18-AMD

SA 4-4 B 2048 x 4/18

DIS-211 AM

DA23

AM 140-3

Am27S184N185A

Am27S184/185

715-1616

r-*_R_e_v_sh_o_w_n_i_s_m_in_im_u_m
__
a_pp_r_ov_e_d_re_v_is_io_n_.____________________________________________________________________

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

ORDERING INFORMATION
Order Code
Speed
Selection

Open
Collector

Three-State

Package
Type
(Note 1)

Screening
Flow Code
(Note 2)

Operating
Range
(Note 3)

P-18-1
P-18-1
D-18-1
D-18-1

COM'L

AM27S184APC
AM27S184APC8
AM27S184ADC
AM27S184ADC8
AM27S184ALC
AM27S184ALCB

AM27S 185APC
AM27S 185APC8
AM27S185ADC
AM27S185ADC8
AM27S185ALC
AM27S185ALC8

L-28-2

C-1
8-1
C-1
8-1
C-1
8-1

45ns

AM27S184ADM
AM27S184ADMB
AM27S184ALM
AM27S184ALM8
AM27S184AFM
AM27S184AFM8

AM27S185ADM
AM27S185ADM8
AM27S 185ALM
AM27S185ALMB
AM27S 185AFM
AM27S185AFMB

D-18-1
D-18-1
L-28-2
L-28-2
(Note 4)
(Note 4)

C-3
B-3
C-3
8-3
C-3
B-3

MIL

50ns

AM27S184PC
AM27S184PCB
AM27S184DC
AM27S184DCB
AM27S184LC
AM27S184LCB

AM27S185PC
AM27S185PCB
AM27S185DC
AM27S185DCB
AM27S185LC
AM27S 185LCB

P-18-1
P-18-1
D-18-1
D-18-1
L-28-2
L-28-2

C-1
8-1
C-1
B-1
C-1
B-1

COM'L

55ns

AM27S184DM
AM27S184DMB
AM27S184LM
AM27S184LMB
AM27S184FM
AM27S184FMB

AM27S185DM
AM27S185DMB
AM27S185LM
AM27S185LMB
AM27S185FM
AM27S 185FMB

D-18-1
D-18-1
L-28-2
L-28-2
(Note 4)
(Note 4)

C-3
B-3
C-3
B-3
C-3
8-3

MIL

35ns

L~28-2

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip- Pak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
4. Consult factory for flat package outline drawings.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-91

~~

Am27LS184 • Am27LS185
8192·8it Generic Series 8ipolar 'MOX™ PROM
(2048 x 4 bits with .ow power dissipation)

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Excellent performance over the full military and
commercial ranges
• Low power dissipation
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming yields
(typ >98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing
extremely flat AC performance over military range
• Member of generic PROM series utilizing standard
programming algorithm
• 100% MIL-STD-883C assurancetesting
• Guaranteed to INT-STD-123

The Am27LS184 and Am27LS185 are high speed electrically programmable Low-Power Schottky read only
memories. Organized in the industry standard 2048 x 4
configuration, they are available in both open collector
Am27LS184 and three-state Am27LS185 output versions.
After programming, stored information is read on outputs
0 0 -03 by applying unique binary addresses to Ao-A1O and
holding the chip select input CS LOW. If the chip select
input goes to a logic HIGH, 0 0 -03 go to the off or highimpedance state.

BLOCK DIAGRAM
COLUMN TEST RAIL

GENERIC SERIES CHARACTERISTICS

Ag

These 8K PROMs are members of an Advanced PROM
series incorporating common electrical characteristics and
programming procedures. All parts in this series are produced with a fusible link at each memory location storing a
logic LOW and can be selectively programmed to a logic
HIGH by applying appropriate voltages to the circuit.

As
A7
As
As

128 X 64
FUSE ARRAY

1 OF 128
ROW
DECODER

A4
TEST ROW 0

A3

TEST ROW 1

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words
are pre-programmed during manufacturing to insure
extremely high field programming yields, and produce
excellent parametric correlation.

AlO
A2
A,
Ao

Cs

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
non-conductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

CONNECTION DIAGRAMS - Top Views
Chip-PakTil
L-28-2

DIP

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths.

~

l;!

~

VCC
As

A7
As

These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOXTM. This
advanced process permits an increase in density and a
decrease in internal capacitance resulting in the fastest
possible PROMs.

Ag

00

A.
A,

Ao

01

AI

O2

A2

03

A,.

es
BPM-271

BPM-140

Note: Pin 1 is marked for orientation
IMOX is a trademark of Advanced Micro Devices, Inc.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-92

Am27LS184/LS185
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 18 to Pin 9) Continuous

-0.5 to + 7.0V

. DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE
LOGIC SYMBOL

Temperature

Vee

TA = Oto +75°C
AO

Te = -55to +125°C

A,
A2
A3
A4

cs

204Sx4PROM

As

10

As

17

A7

16
15
S

A,o

As
Ag

Vee = Pin 18
GND=Pin9

14

13

12

11

BPM-139

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions

Min

Parameters

Description

VOH(Note2)

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Vee = MAX, VIN = Vee

Ise(Note2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

lee

Power Supply Current

All inputs = GND, Vee = MAX

Typ
(Note 1)

0.50

-0.020

-45
80

Vee = MIN, liN = -18mA

leEX

Output Leakage Current

Vee = MAX
Ves = 2.4V

CIN

Input Capacitance

VIN = 2.0V @f = 1MHz (Note 5)

5

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 5)

8

IVo = Vee
IVo = O.4V

0.8

Volts

-0.250

mA

40

f.LA

-90

mA

125

mA

-1.2

Volts

40
-40

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. These parameters are not 100% tested, but are periodically sampled.

2-93

Volts

Volts

2.0

-20

Units
Volts

2.4

Input Clamp Voltage

VI

Max

f.LA

pF

Am27LS184/LS185
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Max

Typ
5V
Parameter
tAA

Test Conditions

Description

25°C

COM'L

MIL

Units

40

60

65

ns

10

25

30

ns

10

25

30

ns

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

AC Test Load
(5ee Notes 1-3)

Notes: 1. tAA is tested with switch 51 closed and C L = 30pF.
2. For open collector outputs, tEA and tER are tested with 51 closed to the 1.5V output level. CL = 30pF.
3. For three state outputs, tEA is tested with C L = 30pF to the 1.5V level; 51 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with 51 open to an output voltage of VO H - O.5V;
LOW to high impedance tests are made with 51 closed to the VOL + 0.5V level.

SWITCHING CHARACTERISTICS
~-----3.0V
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - - - _ 1.5V

I-----

OV

t_

------7-- - - /
1

~IAA---l

0
00- 3

f-IER~

1 5V
•

~'---IEA--l- OV

====xm""""""'-"""""""'' ' ' ' -------------rT"):l-t-z
'
.yt-+f}+---::,-"
....
: "-:~----f-1«!-+-~f-{~-- ::
Note: Level on output while C5 is HIGH is determined externally.

BPM-109

KEY TO TIMING DIAGRAM

WAVEFORM

-JJJJJJ

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

--

WAVEFORM

]HE

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

AC TEST LOAD

Rl
300n
OUTPUT

0---....---4

"t

>

R2
600n

BPM-110

2-94

Am27LS184/LS185
PROGRAMMING
The Am27LS184 and Am27LS185 are manufactured with a
conductive Platinum-Silicide link at each bit location. The output
of the memory with the link in place is LOW. To program the device, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS input is a logic HIGH. Current is
gated through the addressed fuse by raising the CS input from a
logic HIGH to 15 volts. After 50JLsec, the 20 volt supply is removed, the chip enabled, and the output level sensed to determine if the link has opened. Most links will open within 50JLsec.
Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened after a total
elapsed programming time of 400msec, further programming of
the device should not be attempted. Successive links are programmed in the same manner until all desired bit locations have
been programmed to the HIGH level.
Typical current into an output during programming will be approximately 180mA until the fuse link is opened, after which the

current drops to approximately 90mA. Current into the CS pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to
the large currents being passed. Programming cycles should
not be applied to one device more than 5 seconds to avoid
heat damage. If this programming time is exceeded, all power
to the chip including Vee should be removed for a period of 5
seconds after which programming may be resumed.
When all programming has been completed, the data content
of the memory should be verified by sequentially reading all
words. Occasionally this verification will show that an extra
undesired link has been fused. Should this occur, immediately
check the programming equipment to make sure that all device pins are firmly contacting the programming socket, that
the input signal levels exhibit sufficient noise margins, and
that the programming voltages are within the specified limits.
All of these conditions must be maintained during programming. AMD PROMs are thoroughly tested to minimize unwanted fusing; fusing extra bits is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Description

Parameters

Min

Max

Units
Volts

Veep

Vec During Programming

5.0

5.5

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

Vr'LP

Input LOW Level During Programming

0.0

0.45

Volts

VCSP

CS Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

d(VCSp)/dt
tp

0

Vccp

+ 0.3

Volts

20

rnA

20

250

V/p.sec

Rate of CS, Voltage Change

100

1000

V/p.sec

Programming Period - First Attempt

50

100

p'sec

Programming Period - Subsequent Attempts

5.0

15

msec

Notes: 1. All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
2. Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of 1p.sec are recommended to minimize heating during programming.
3. During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are
required.
4. Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

~:::;;

I "dt

Cs

Vccp

PROGRAMMED
OUTPUT

-,

VILP
Ao·A,o

(VCSP)~

L~(Vop)
dt

Vcsp

~

PROGRAMMING CYCLE

r=>

I~-""
\

OUTPUT /,

~E!!!f!.l"-

I

VONP

I

R;;,.30011

~
~o--<
Am27lS184
OR
Am27lS185

r- ''''

r---

II~~ "

I

CVIHP

SELECTED ADDRESS STABLE

ENABLE

-1

SIMPLIFIED PROGRAMMING DIAGRAM

Csr-

02

-..:0.....

()--<

~o--<

VOP

~

VOH
VOL

Vcsp

BPM·272

2-95

11-

11-

-=-

-=-

Vop

BPM·112

Am27LS184/LS185
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

DataI/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ 85260

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

Programmer
Model(s)

Model 5, 7 and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920, and MOO0

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev H"
919-1286-1 RevH*

PM 9058

IMAMDGEN1

MOD 14

PM 102

FAM-12

PM 2000
Code 90

Am27LS184
Am27LS185

715-1616

PA 18-8and
2048x4(L)

1M 2048 x 4-1 8-AMD

SA 4-4 B 2048 x 4/1 8

DIS-211 AM

DA23

AM 140-3

"Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error, and higher cost.

ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM27LS185PC
AM27LS185PCB
AM27LS185DC
AM27LS185DC8
AM27LS185LC
AM27LS 185LC8

P-18-1
P-18-1
D-18-1
D-18-1
L-28-2
L-28-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

D-18-1
D-18-1
L-28-2
L-28-2
(Note 4)
(Note 4)

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

60ns

AM27LS184PC
AM27LS184PCB
AM27LS184DC
AM27LS184DCB
AM27LS184LC
AM27LS184LCB

65ns

AM27LS184DM
AM27LS184DMB
AM27LS184LM
AM27LS 184LMB
AM27LS184FM
AM27LS184FMB

AM27LS185DM
AM27LS185DM8
AM27LS185LM
AM27LS185LMB
AM27LS185FM
AM27LS185FMB

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
4. Consult factory for flat package outline drawings.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-96

Am27PS185

8192-Bit Generic Series Bipolar IMOX™ PROM
(2048 x 4 bits with power-down via CSJ

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time (60ns max) allows system speed
improvements
• 50% power savings on deselected parts - enhances
reliability through total system heat reduction
• Plug in replacement for industry standard product - no
board changes required
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming yields
(typ> 98%)

The Am27PS185 is a high speed electrically programmable
Schottky read only memory. Organized in the industry
standard 2048 x 4 configuration, it is available in the threestate (Am27PS185) output version. After programming,
stored information is read on outputs 0 0.03 by applying
unique binary addresses to Ao-A1O and holding the chip
select input CS LOW. If the chip select input goes to a logic
HIGH, 0 0 -03 go to the OFF or high-impedance state, and
Icc is reduced by 50%.

• AC performance is factory tested utilizing programmed
test rows and columns

BLOCK DIAGRAM

• Voltage and temperature compensated providing
extremely flat AC performance over military range
COLUMN TEST RAIL

• Member of generic PROM series utilizing standard
programming algorithm

Ag

• 100% MIL-STD-883C assurance testing

As

• Guaranteed to INT-STD-123

A6

A7

As

128 X 64
FUSE ARRAY

1 OF 128
ROW
DECODER

A4

GENERIC SERIES CHARACTERISTICS

TEST ROW 0

A3

TEST ROW 1

The Am27PS185 is a member of an Advanced PROM
series incorporating common electrical characteristics and
programming procedures. All parts in this series are produced with a fusible link at each memory location storing a
logic LOW and can be selectively programmed to a logiC
HIGH by applying appropriate voltages to the circuit.

A,O
A2
A,
Ao

All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words
are pre-programmed during manufacturing to insure
extremely high field programming yields, and produce
excellent parametric correlation.

cs

CONNECTION DIAGRAMS - Top Views

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
non-conductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

DIP

Chip-Pak™
L-2B-2
~

A6

VCC

As

A7

~

lil

As

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths.

A7
A.

A4

As

A3

Ag

Ao

00

A,

0,

A2

O2

A.

A.

A3

NC

Ao

These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOXTM. This
advanced process permits an increase in density and a
decrease in internal capacitance resulting in the fastest
possible PROMs.

A,o

03

GND

cs

BPM-108

A,

NC

A,

00

A,O

0,

NC

0,

lil

I~

0BPM-257

Note: Pin 1 is marked for orientation.
IMOX is a trademark of Advanced Micro Devices, Inc.
Chip- Pak is a trademerk of Advanced Micro Devices, Inc.

2-97

Am27PS185
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 18 to Pin 9) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-O.SV to +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

LOGIC SYMBOL

Vee

Ao
A,

Temperature

A2
A3
A.
As

4.75 to 5.25V
4.5t05.5V

Te = - 55 to + 125°C

CS

0--10

A6
A7
A8
Ag

17
16

15
8

A,o

00

0,

O2

03

14

13

12

11

Vee= Pin 18
GND = Pin9

BPM-107

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN, IOH
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs

IlL

Input LOW Current

Vee

IIH

Input HIGH Current

Vee

Ise

Output Short Circuit Current

ICC

Power Supply Current

VI

Input Clamp Voltage

leEX

Output Leakage Current

Min

= -2.0mA

204

-0.020

All inputs = GND

Vee

0.8

Volts

-.250

mA

40

!LA

-40

-90

mA

105

150

50

75

mA

I All other inputs = GND

= MIN, liN = -18mA

-1.2

IVo= Vee

Vee = MAX
Vcs = 204V

Volts

Volts

2.0

-15

Units
Volts

0.50

= MAX, VIN = 0.45V
= MAX, VIN = Vee
Vee = MAX, VOUT = O.OV (Note 2)

CS = 2.7V

Max

(Note 1)

Volts

40

IVo = Oo4V

-40

CIN

Input Capacitance

VIN = 2.0V @f = 1MHz (Note 3)

5

COUT

Output Capacitance

VOUT = 2.0V @ f = 1MHz (Note 3)

8

!LA

pF

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
3. These parameters are not 100% tested, but are periodically sampled.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Parameter

Description

Test Conditions

tAA1

Address Access Time

tEAS ~ 25ns

tAA2

Power Switched Address Access Time

tEAS = Ons

tEA

Enable Access Time

tAES~ Ons

tER

Enable Recovery Time

AC
Test Load
Fig. 1-3, 5
(Notes 1, 4 and 5)

Typ

Max

SV 2S C

COM'L

MIL

Units

28

50

55

ns

41

60

65

ns

41

60

65

ns

10

25

30

ns

Q

Notes: 4. tAA is tested with switch S1 closed and CL = 30pF.
5. tEA is tested with CL = 30pF to the 1.5V level; 51 is open for high impedance to HIGH tests and closed for high impedance to LOW tests. tER is
tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage of VOH -0.5V with S1 open; LOW-to-HIGH
impedance tests are made to the VOL +O.5V level with S1 closed.

2-98

Am27PS185
SWITCHING WAVEFORMS

Ao·AI0

~"'

______________-J*"'-------- ::v

=======:::::_-~-,A\ -------------------'~I--....-_-_-_-_-_-_-_-:_-_-_-_-_-_-_

I

f- lEAS

CS4

f-----IAA--1

Figure 1.

BPM·144

KEY TO TIMING DIAGRAM
WAVEFORM

VCC~~

-----

51

CL

::v

f--IEA-l

»»}I-::: ~:: (flf;:

AC TEST LOAD

OUTPUT

~

~IER~

« < 98%)

These 16K PROMs are high speed electrically programmable
Schottky read only memories. Organized in the industry standard
2048 x 8 configuration, they are available in both open collector
(Am27S190A/190 and Am27S290A/290) and three-state
(Am27S191A/191 and Am27S291A/291) output versions. After
programming, stored information is read on outputs 00-07 by
applying unique binary addresses to AO-A1O and holding CS1
LOW and CS2 and CS3 HIGH. All other valid input conditions
on CS1, CS2, and CS3 place 00-07 into the OFF or HIGH
impedance state.

• AC performance is factory tested utilizing programmed test
words and columns
• Voltage and temperature compensated providing extremely
flat AC performance over military range
• Members of generic PROM series utilizing standard
programming algorithm
• 100% MIL-STD-883C assurance testing
• Guaranteed to INT-STD-123

BLOCK DIAGRAM

GENERIC SERIES CHARACTERISTICS
128 X 128
PROGRAMMABLE
ARRAY

These 16K PROMs are members of an Advanced PROM series
incorporating common electrical characteristics and programming procedures. All parts in this series are produced with a
fusible link at each memory location storing a logic LOW and can
be selectively programmed to a logic HIGH by applying appropriate voltages to the circuit.
All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming personality card sets) these products can be rapidly programmed to any
customized pattern. Extra test words are pre-programmed during
manufacturing to insure extremely high field programming yields,
and produce excellent parametric correlation.
Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long-term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible link
PROMs.
Common design features include active loading of all critical AC
paths regulated by a built-in temperature and voltage compensated bias network to provide excellent parametric performance
over MIL supply and temperature ranges. Selective feedback
techniques have been employed to minimize delays through all
critical paths.

BPM-203

LOGIC SYMBOL
8

20

These PROMs are manufactured using Advanced Micro Devices'
selective oxidation process, IMOX. This advanced process combined with a merged fuse array permits an increase in density
and a decrease in internal capacitance resulting in the fastest
possible PROMs.

7

6

5

CS1

4

3

2

1 23 22 21

16K
PROMs
2048 x 8

19 CS2
18 CS3

Vee = PIN 24
GND = PIN 12

9

10

11

13

14

15

16

17

BPM-204

DIP

CONNECTION DIAGRAMS - Top Views

Chip-Pak™

'5

"
"

"
"
'0
o.
0,

Note: Pin 1 is marked for orientation.

BPM-205

BPM-206

Chip-Pak is a trademark of Advanced Micro Devices, Inc.
2-103

Am27S190A/S191 A/S290A/S291 A/S190/S191/S290/S291
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

- 0.5 to

DC Voltage Applied to Outputs (Except During Programming)

+ 7.OV

- O.SV to + VCC max

DC Voltage Applied to Outputs During Programming

21V

Output, Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE

Vee

Temperature

4.75 to 5.25V
4.5 to 5.5V

Te = -55 to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters

Description

VOH
(TS Devices only)

Output HIGH Voltage

Vee = MIN, IOH
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

Vee

IIH

Input HIGH Current

Vee

Ise

Output Short Circuit Current

Min

Test Conditions

Vee

=

= 16mA

-2.0mA

2.0

Icc

Power Supply Current

All inputs = GND, Vee = MAX

Input Clamp Voltage

Vee

leEx

Output Leakage Current

= MIN,

Ve s 1
Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 3)

COUT

Output Capacitance

VOUT = 2.0V @ f

Notes: 1.
2.
3.
4.

=

1MHz (Note 3)

-0.250

mA

40

p.A

-90

-15

-40

-'-90

115

CIN

Volts

-40

I Va = Vee
IVa = O.4V

= 2.4V

0.8

-20

liN = -18mA

Vee = MAX

mA

185

mA

-1.2

Volts

40

p.A

-40
4.0
8.0

Typical limits are at Vee = 5.0V and TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

2-104

Volts
Volts

-0.010

I COM'L
I MIL

Units
Volts

0.50

= MAX, VIN = 0.45V
= MAX, VIN = Vee
= MAX, VOUT = O.OV

VI

Max

2.4

(Note 2)

(TS Devices only)

Typ
(Note 1)

pF

Am27S190A/S191A/S290A/S291A/S190/S191/S290/S291
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE
Typ

Max

5V 25°C
Parameters

Description

Test Conditions

tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

AC Test Load
(8ee Notes 1, 2, 3)

MIL

COM'L

A

STD

A

STD

A

STD

Units

25

30

35

50

50

65

ns

10

10

25

25

30

30

ns

10

10

25

25

30

30

ns

Notes: 1. tAA is tested with switch 81 closed and CL = 30pF.
2. For open collector outputs, tEA and tER are tested to the 1.5V output level with 81 closed; CL = 30pF.
3. For three-state outputs, tEA is tested with CL = 30pF to the 1.5V level; 81 is open for high impedance to HIGH tests and closed for high impedance
to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made to an output voltage to VOH - O.5Vwith 81 open; LOW to high
impedance tests are made to the VOL + 0.5V level with 81 closed.

SWITCHING WAVEFORMS

3.0V

~A"3
CS2. CS3

CS1

1.SV

ov

~'''~

I
I

f--t ---1
AA

»f =:::::::

XXX!

00.0 7

t,,,~

«@

Note: Level on output while chip is disabled is determined externally.

1.SV

ov
VOH
1.SV
VOL

BPM-207

KEY TO TIMING DIAGRAM

WAVEFORM

---

--

---

JJJJJJ

INPUTS

--

WAVEFORM

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

V"~
S1

R1
300n

OUTPUT

c
L

I
-=-

R2
600n

-:
BPM-20B

2-105

Am27S190A/S191A/S290A/S291AjS190/S191jS290/S291
PROGRAMMING
The entire Generic PROM Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the devices,
the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to the memory output after the CS1 input is at a logic HIGH. Current is gated
through the addressed fuse by raising the CS1 input from a logic
HIGH to 15 volts. After 50,usec, the 20 volt supply is removed, the
chip is enabled and the output level is sensed to determine if the
link has opened. Most links will open within 50,usec. Occasionally
a link will be stronger and require additional programming cycles.
The recommended duration of additional programming periods is
5msec. If a link has not opened after a total elapsed programming
time of 400msec, further programming of the device should not
be attempted. Successive links are programmed in the same
manner until all desired bit locations have been programmed to
the HIGH level.
Typical current into an output during programming will be approximately 180mA until the fuse link is opened, after which the

current drops to approximately 90mA. Current into the CS1 pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage.
If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Parameters

Min

Max

Units

Veep

Vee During Programming

Description

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCS1P

CS1 Voltage During Programming

14.5

15.5

Volts

VOP

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

0

Vccp + 0.3

Volts

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

d(Vcs,)dt
tp
Notes: 1.
2.
3.
4.

20

mA

20

250

V/,usec
V/,usec

Rate of CSt Voltage Change

50

1000

Programming Period - First Attempt

50

100

,usec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of 1,usec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

",~:::i

I

Vccp

~
dt

CS1

ENABLE
-1

SELECTED ADDRESS STABLE

~

V(ES,)'!

-,

I

'--

~(Vop)
dt

PROGRAMMING CYCLE

r:::-

I

2Kx8
PROM

VOH
VOL

11.
-=-

BPM·209

2-106

V CS1P

~

··
·

07

CSl

-vop

~E!!!.F~,-

01

CS3

V IHP

R '" 2000

~

AO.Al0e:)

~-""
\ OUTPUT ,o,

VONP

I

F:':::':

11~~ p-I--V
,

PROGRAMMED
OUTPUT

SIMPLIFIED PROGRAMMING DIAGRAM

0--<

0--<

~

*

I

I
I

11.
-=-

I

J
Vop

BPM·210

Am27S190A/S191A/S290A/S291A/S190/S191/S290/S291
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Pro-Log Corporation
Data I/O
10525 Willows Rd. N.E. 2411 Garden Road
Redmond, WA 98052
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City, CA 94063

Oigelec, Inc.
3 Tevuo! Haaretz Sf.
Tel-Aviv, Israel

Stag Systems, Inc.
1120 San Antonio Rd.
Palo Alto, CA 94303

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19 and 29

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMO Generic
Bipolar PROM
Personality
Module

909-1286-1 Rev H919-1286-1 Rev HUnipak Rev H(Code 16 68)

PM 9058

1M AMOGEN1

MOD 14

PM 102

FAM-12

PM 2000
Code 90

Am27S190A/191A
Am27S190/191

715-1688-1

PA 24-17 and
2048 x 8(L)

1M 2048 x 8-24AMO

SA 22-10 B 2048 x 8/24

01S-151 AM

DA 61

AM100-5

Am27S290N291A
Am27S290/291

715-1688-2

PA 24-28 and
2048 x 8(L)

1M 2048 x 8-2427S290/291-AMO

SA 29 B 2048 x 8/24

DIS-215 AM

DA 62

AM190-7

• Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor or
Advanced Micro Devices. The program data should be submitted
in the form of a punched paper tape and must be accompanied by
a written truth table. The punched tape can be delivered with your
order or may be transmitted over a TWX machine or a timesharing terminal. ASCII 8PNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the distributor
or factory resulting in longer lead times, greater possibility of
error, and higher cost.

ASCII BPNF

An example of an ASCII tape in the 8PNF format is shown below.
They can be punched on any Teletype@ or on a TWX or Telex
machine. The format chosen provides relatively good error
detection. Paper tapes must consist of:
1. A leader of at least 25 rubouts.
2. The data patterns for all 2048 words, starting with word 0, in
the following format:
a. Any characters, including carriage return and line feed,
except "8".
b. The letter "8", indicating the beginning of the data word.
c. A sequence of eight Ps or Ns, starting with output 07.
d. The letter "F", indicating the finish of the data word.
e. Any text, including carriage return and line feed, except the
letter "8".

3. A trailer of at least 25 rubouts.
A P is a HIGH logic level = 2.4 volts.
An N is a LOW logic level = 0.5 volts.
A convenient pattern to use for the data words is to prefix the word
(or every few words) with the word number, then type the data
word, then a comment, then carriage return and line feed as
shown below. There must be no characters between the 8 and
the F except for the eight Ps and Ns. If an error is made in a word,
the entire word must be cancelled with rubouts back to the letter
8, then the word re-typed beginning with the 8.
When TWXing your tape, be sure the tape is in even parity. Parity
is not necessary if the tape is mailed.

RESULTING DEVICE TRUTH TABLE
(CS1 LOW AND CS2 CS3 HIGH)

TYPICAL PAPER TAPE FORMAT

¢¢¢
¢¢2
¢¢4

¢e6
2047

BPNPPNNNPF
BPPPPPPNNF
BN!1l1PPPPNF
BNNNNNNNl'lF
BPNNNNNNPF
BNPPNPPNNF
BPNNPPPNNF

TEXT

BNNNNPPPNF

EN°D®®

..........
..........

WORD ZERO®

~

~'lELDR
R

L

Ato Ag As A7

As ~ A3 A2 A1

Ao

~ 06 05 0 4 0 3 O2 0 1 0 0

L
L
L
L
L

L
L
L
L
L

L
H
L

H
H
L
L
H

L
H
L
L
L

H
H
L
L
L

H
H
H
L
L

L
'H

H

H
L

L
H

L

H

H
H

L

L

L

L

L

L

L

L

H

H

H

L

L
L
L
L
L

L
L
L
L
L

L

L

L

L

H

L
L
L
L
L

L
L
L
L
L

L
L
L
L
L

L
L

L

L
L

L

L

L

L

L

H

H

H

H

H

H

@

CAN R L
GO R L
HEoRE R ®

®~ CARRIAGE RETURN
©~ LINE FEED

As

L
L
L
L
L

2-107

··

L
L
H
H
L

L
L

L
L
L
L
H
H

H

H

L
H
L

H

H

H

H

L

H

··

L
H
H
L
L
H

L
H
H
L
L

L,
L

H
L
L

H
L
L
L
H

Am27S190A/S191A/S290A/S291A/S190/S191/S290/S291
ASCII PAPER TAPE

LEADER
[

..........

/

rA~~1I

ASCII 'B'
WORD '0'

['B'

r'rF',

CR

WORD '1'

..---..

TRAILER

:::::;;~;:.....:::::;;;;:~ :..................... /
00000

a

00000

~

0000000

a

L

00000

S'P'sOR'N's

LLF

OPTIONAL COMMENTS MAY BE INSERTED HERE

BPM-211

ORDERING INFORMATION
Order Code
Speed
Selection

Open
Collector

Three-State

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

35ns

AM27S190APC
AM27S 190APCB
AM27S290APC
AM27S290APC8
AM27S190ADC
AM27S190ADC8
AM27S290ADC
AM27S290ADC8
AM27S190ALC
AM27S 190ALC8

AM27S191APC
AM27S191APCB
AM27S291APC
AM27S291APC8
AM27S191ADC
AM27S191ADC8
AM27S291ADC
AM27S291ADC8
AM27S191ALC
AM27S191ALCB

P-24-1AC
P-24-1AC
P-24-1M (Note 4)
P-24-1M (Note 4)
D-24-1AC
D-24-1AC
D-24-1M
D-24-1M
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1

COM'L

50ns

AM27S190ADM
AM27S190ADM8
AM27S290ADM
AM27S290ADM8
AM27S 190AFM
AM27S190AFM8
AM27S190ALM
AM27S190ALM8

AM27S191ADM
AM27S191ADM8
AM27S291ADM
AM27S291ADM8
AM27S191AFM
AM27S191AFM8
AM27S191ALM
AM27S191ALM8

D-24-1AC
D-24-1AC
D-24-1M
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3
C-3
8-3

MIL

50ns

AM27S190PC
AM27S190PC8
AM27S290PC
AM27S290PC8
AM27S190DC
AM27S190DC8
AM27S290DC
AM27S290DC8
AM27S190LC
AM27S190LC8

AM27S191PC
AM27S191PC8
AM27S291PC
AM27S291 PC8
AM27S191DC
AM27S191DC8
AM27S291DC
AM27S291DC8
AM27S191LC
AM27S191LC8

P-24-1AC
P-24-1AC
P-24-1M (Note 4)
P-24-1M (Note 4)
D-24-1AC
D-24-1AC
D-24-1M
D-24-1M
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1
C-1
8-1

COM'L

65ns

AM27S190DM
AM27S190DM8
AM27S290DM
AM27S290DM8
AM27S190FM
AM27S190FM8
AM27S190LM
AM27S190LM8

AM27S191DM
AM27S191DM8
AM27S291DM
AM27S291 DM8
AM27S191FM
AM27S191FM8
AM27S191LM
AM27S191LM8

D-24-1AC
D-24-1AC
D-24-1AA
D-24-1M
F-24-1
F-24-1
L-32-2
L-32-2

C-3
8-3
C-3
8-3
C-3
8-3
C-3
8-3

MIL

Notes: 1, P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak, Number following letter is number of leads,
AC = 600 mil center package, M = 300 mil center package,
2, Levels C-1 and C-3 conform to MIL-STD-883, Class C,
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8,
3, See Operating Range Table,
4, This package will be available soon, Consult factory,
This device is also available in die form selected to commercial and military specifications, Pad layout and bonding diagram
available upon request.

2-108

Am27PS191A· Am27PS291A
Ultra Fast Access Time

Am27PS191 • Am27PS291
Fast Access Time
16,384-Bit Generic Series IMOX™ Bipolar PROM
2048 x 8 Bits with Power-Down Via CS

DISTINCTIVE CHARACTERISTICS
Part Number

Package Width

Am27PS191A

24-Pin, Plug in Replacement for Industry Standard
600-mil Configuration No Board Changes Required

Am27PS191
Am27PS291A
Am27PS291

New Space-Saving 24-Pin, THINDIP, 300-mil
Configuration Increases Overall Board Density

IMOX is a trademark of Advanced Micro Devices, Inc.

2-109

Other Features
Ultra fast - 50ns max
Fast - 65ns max
Ultra fast - 50ns max
Fast - 65ns max

Am27PS191AjPS291AjPS191jPS291
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time allows high system speed
• 50% power savings on deselected parts - enhances
reliability through total system heat reduction
• Plug in replacement for industry standard product no board changes required
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ > 98%)
• AC performance is factory tested utilizing programmed test
words and columns
• Voltage and temperature compensated providing extremely
flat AC performance over military range
• Rapid recovery from power-down state provides
minimum delay
• Members of generic PROM series utilizing standard
programming algorithm
• 100% processed to MIL-STD-883C
• Guaranteed to INT-STD-123

These 16K PROMs are high speed electrically programmable
Schottky read only memories. Organized in the industry standard 2048 x 8 configuration, they are available in both the
standard 600-mil package (Am27PS191N191) and the spacesaving THINDIP, 300-mil package (Am27PS291A/291)
versions. After programming, stored information is read on outputs 00 - 07 by applying unique binary addresses to Ao - A10
and holding CS1 LOW and CS2 and CS3 HIGH. All other input
combinations on CS1, CS2, and CS3 place 00 - 07 into the OFF
or high impedance state and reduce ICC by more than 50%.

BLOCK DIAGRAM

128 X 128
PROGRAMMABLE
ARRAY

GENERIC SERIES CHARACTERISTICS

These 16K PROMs are members of an Advanced PROM series
incorporating common electrical characteristics and programming procedures. All parts in this series are produced with a
fusible link at each memory location storing a logic LOW and
can be selectively programmed to a logic HIGH by applying
appropriate voltages to the circuit.
All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming personality card sets) these products can be rapidly programmed to
any customized pattern. Extra test words are pre-programmed
during manufacturing to insure extremely high field programming yields, and produce excellent parametric correlation.
Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long-term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

CONNECTION DIAGRAMS - Top Views
DIP

Common deSign features include active loading of all critical AC
paths regulated by a built-in temperature and voltage compensated bias network to provide excellent parametric performance
over MIL supply and temperature ranges. Selective feedback
techniques have been employed to minimize delays through all
critical paths.
These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOX. This advanced
process combined with a merged fuse array permits an increase
in density and a decrease in internal capacitance resulting in the
fastest possible PROMs.

A7

20

7

6

5

4

3

Csi

9

10

11

13

14

A3

A,

A2

Ao

00

~

~

16

02 GNO

~

"
'"

"
CS 1

"
"
"

15

0,

..

"
"

1 23 22 21

PROM
2048 x8

18 CS3

A4

:r

16K

19 CS2

Vee = Pin24
GNDPin 12

2

As

Chip-Pak™
L-32-2

LOGIC SYMBOL
8

Aij

Note: Pin 1 is marked for orientation.

cs,
cs,

0,

0,

0,

0,

17

BPM-204

Chip-Pak is a trademark of Advanced Micro Devices, Inc.
2-110

c;

c;

or rr

BPM-205

Am27PS191 A/PS291 A/PS191/PS291
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

- 55 to + 125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

- 0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

- 0.5V to + VCC max

21V

DC Voltage Applied to Outputs During Programming
Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

- 0.5 to + 5.5V

DC Input Current

-30to +5mA

OPERATING RANGE
Vee

Temperature

4.75 to 5.25V
4.5t05.5V

Te = -55to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN,loH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Ise

Output Short Circuit Current

Icc

Power Supply Current

All inputs = GND

IceD

Power Down Supply Current

CS1 = 2.7V

VI

Input Clamp Voltage

Vee = MIN,IIN = -1SmA

Output Leakage Current

Vee = MAX

Units

2.4

Volts
0.50

Volts

2.0

Volts

-0.010

O.S

Volts

-0.250

rnA

40

I COM'L
I MIL

-20

-40

-90

-15

-40

-90

115

1S5

50

SO

I All other inputs = GND

Ves 1 = 2.4V

/LA
rnA

rnA

-1.2

I Vo= Vee
I Vo = O.4V

Volts

40
/LA
-40

CIN

Input Capacitance

VIN = 2.0V @ f = 1MHz (Note 3)

4.0

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 3)

S.O

Notes: 1.
2.
3.
4.

Max

(Note 1)

Vee = MAX, VIN = Vee
Vee = MAX, VOUT = O.OV
(Note 2)

leEX

Min

pF

Typical limits are at Vee = 5.0V and TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Max

Typ
COM'L

5V25°C
Parameters

Description

Test Conditions

tM1

Address Access Time

tEAS"" 25ns

tM2

Power Switched Address Access Time

tEAS = Ons

tEA

Enable Access Time

tAES> Ons

tEA

Enable Recovery Time

AC
Test Load
Fig. 1-3,5
(Notes 5 and 6)

MIL

STD

A

STD

A

STD

Units

30

50

65

65

75

ns

50

65

SO

75

90

ns

50

65

SO

75

90

ns

15

25

35

30

45

ns

Notes: 5. tM is tested with switch S1 closed and CL = 30pF.
6. tEA is tested with CL = 30pFtothe 1.5V level; S1 is open for high impedance to HIGH tests and closed for high impedance to LOW tests. tEA is
tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage of VOH -0.5Vwith S1 open; LOW-to-high
impedance tests are made to the VOL +0.5V level with S1 closed.

2-111

Am27PS191 A/PS291 A/PS191/PS291
SWITCHING WAVEFORMS

~,--_____________-,W'--------

AD·A'D

-

*

r-

c~,:: 3--

tEAS

=1

I
f-tAA------1

0~03

BPM·230

KEY TO SWITCHING WAVEFORMS

-----

--

R,
300n

0----.----+

c,±

.-

Figure 2.

NOTES ON POWER SWITCHING
The Am27PS191A/191 and Am27PS291A/291 are power
switched devices. When the chip is selected, important internal
currents increase from small idling or standby values to their
larger selected values. This transition occurs very rapidly,
meaning that access times from the powered-down state are
only slightly slower than from the powered-up state. Deselected,
lee is reduced to less than half its full operating amount. Due to
this unique feature, there are special considerations which
should be followed in order to optimize performance:

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

~13~~-+-r-4--+-*-~-+_+-~

I

""

Jfll!1

H

DOES NOT
APPLY

~1 3~~-+_r-4--+__*-~-+_+-~
a:~

-

ItO

I

80 ~-+'<:",-+--t--4----t-+/f--~-+--+---i

f--+--+--~+-+--+--t---t-+--j

100 - r - - .

r-....

90

~ ~~t=j==1~~t:jt=j==t==~/~~==1=~
I

~ 50~-+--+--~~~=__
~'--~-+--+---i

60~4--+--r-"~,,~--~~--t-+-~

~ ~L-~~_~~~_~~_~~~--'

40'--~~-~-L-J-~-L~_~~
o 100 200 300 400 500 600 700 800 900 1000

o

TIME _ n5.-

100

200

300

400

500

TIME -

600

700

,"-

30
20

I

j

0

1""-

-10

tAA;TYP
-20
-30
20

30

BPM·147

~AAIMAX-

."k

~

900 1000

\'J!\J

r\tAl TYP

10

800

ns---

Figure 4. lee Current

BPM-146

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

I~~ 0 ~~-+--~~-+--+'-~--+-+-~

~ :~~=j=~~~:t~=j==1==~I==~=j==1=j
~

OUTPUTS

CHANGING;
STATE
UNKNOWN

Figure 3.

120 f--+--+--~~-+-t-.f\-+--+--+--I
110 ~-t--+--+-4----t--++\
,~-+--+---i

l"-

IN?UTS
DON'T CARE;
ANY CHANGE
PERMITTEO

Typicallvee Current Surge with O.1~F
(Ivee is Current Supplied by Vee Power Supply)

~~

,

..", AVL:rCni...1

2. Address access time (tAA) can be optimized if a chip enable
set-up time (tEAS) of greater than 25ns is observed. Negative
set-up times on chip enable (tEAS < 0) should be avoided.
(For typical and worse case characteristics, see Figure 5.)

~~0~~-+--~~-+-~~-4-+-~

,

CUTrUT~

INr'UTZ

1. When the Am27PS191A/191 and Am27PS291A/291 are
selected, a current surge is placed on the Vee supply due to
the power-up feature. In order to minimize the effects of this
current transient, it is recommended that a 0.1~f ceramic
capacitor be connected from pin 24 to pin 12 at each device.
(See Figure 4.)

Typicallvee Current Surge without O.1~F
(Ivee is Current Supplied by Vee Power Supply)

90

f-tEA-j

Figure 1.

WAVEfcm.~

lGO I--

*,....~~~~~: :~v

»»;1- ::~ ~::: ({f(E :~:

ACTESTLOAD

BPM-145

~ tAES=-l

f-tER--j

« 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• 100% MIL-STD-883C processing
• Guaranteed to INT-STD-123

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
nonconductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.
Common design features include active loading of all critical
AC paths, which are regulated by a built-in temperature and
voltage compensated bias network to provide excellent
parametric performance over the full military power supply
and temperature ranges. Selective feedback techniques
have been employed to minimize delays through all critical
paths producing the fastest speeds possible from Schottky
processed PROMs.

BLOCK DIAGRAMS

Am27S45A/45

Am 27S47A/47

128x 128

128.128

PROGRAMMABLE
ARRAY

PROGRAMMABLE
ARRAY

.....

IN ITS ----ct~--

BPM·320

BPM-321

IMOX is a trademark of Advanced Micro Devices, Inc.
2-116

Am27545A/545/547 A/547
FUNCTIONAL DESCRIPTION

decoders and sense amplifiers to access the next location while
previously addressed data remains stable on the outputs.

The Am27S45N45 and Am27S47N47 are Schottky TTL programmable read only memories (PROMs) incorporating true
D-type, master-slave data registers on chip. These devices
feature the versatile 2048-word by 8-bit organization and are
available with three-state outputs. Designed to optimize system
performance, these devices also substantially reduce the cost
and size of pipelined microprogrammed systems and other
deSigns where accessed PROM data is temporarily stored in a
register. The Am27S45N45 and Am27S47N47 also offer maximum flexibility for system design by providing either synchronous
or asynchronous initialize, and sychronous or asynchronous
output enable.

The on-chip edge-triggered register simplifies system timing
since the PROM clock may be derived directly from the system
clock without introducing dangerous race conditions. Other register timing requirements are similar to those of standard
Schottky registers and are easily implemented.

When Vee power is first applied, the state of the ouputs will
depend on whether the enable has been programmed to be a
synchronous or asynchronous enable. If the synchronous enable
(Es) is being used, the register will be in the set condition causing
the outputs (0 0 to 0 7 ) to be in !be OFF or HIGH impedance state.
If the asynchronous enable (E) is being used, the outputs will
come up in the OFF or HIGH impedance state only if the enable
(E) input is at a logic HIGH level. Reading data is accomplished by
first applying the binary word address to the address inputs (Ao
through Aw) and a logic LOW to the enable input. During the
address setup time, the stored data is accessed and loaded into
the master flip-flops of the data register. Upon the next LOW-toHIGH transition of the clock input (CP), data is transferred to the
slave flip-flops which drive the output buffers, and the accessed
data will appe~r at the outputs (0 0 through 0 7 ), If the asynchronous enable (E) is being used, the outputs may be disabled at any
time by switching the enable to a logic HIGH, and may be returned
to the active state by switching the enable back to the logic LOW
state. For devices using the synchronous enable (Es), the outputs will go into the OFF or HIGH impedance state upon the next
positive clock edge after the synchron'ous enable input is
switched to a HIGH level. If the synchronous enable pin is
switched to a logic LOW, the next positive clock edge willi return
the output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change, since
no change in the output will occur until the next LOW-to-HIGH
transition of the clock. This unique feature allows the PROM

These devices also contain a built-in initialize function. When
activated, the initialize control input (INIT) causes the contents of
an additional (2049th) 8-bit word to be loaded into the on-chip
register. This extra word is user programmable. Since each bit is
individually programmable, the initialize function can be used to
load any desired combination of HIGHs and LOWs into the register. In the unprogrammed state, activating INIT will perform a
register CLEAR (all outputs LOW). If all bits of the initialize word
are programmed, activating INIT performs a register PRESET
(all outputs HIGH).
This ability to tailor the initialize outputs to the system requirements simplifies system design and enhances performance. The
initialize function is useful during power up and timeout sequences. This flexible feature can also facilitate implementation
of other sophisticated functions such as a built-in "jump-start"
address.
The Am27S45N45 has an asynchronous initialize input (lNIT).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register independent of all other inputs (including
CPl. The initialize data will appear at the device outputs after
the outputs are enabled by bringing the asynchronous enable
(E) LOW.
The Am27S47N47 has a synchronous INITS input. Applying a
LOW to the INITS input causes an immediate load of the programmed initialize word into the master flip-flops of the register
only independent of all other inputs (including CPl. To bring this
data to the outputs of a device with a synchronous enable, the
synchronous enable (Es) should be held LOW until the next
LOW-to-HIGH transition of the clock (CP). For a device with an
asynchronous enable, the data will appear at the device outputs
after the next LOW-to-HIGH clock transition if the enable (E) is
held LOW.

2-117

Am27S45AjS45jS47 AjS47
CONNECTION DIAGRAMS
Top Views

LOGIC SYMBOL

Chip-PakTil
L-32-2

DIP

~

0

c-

~

it

A7

VCC

As

A8

A,

At

As

Ag

A,

A,.

23

A4

A 10

A,

Ne

A3

INIT/iNiTs

A,

iNiT

A2

ElES

At

ElES

Al

CP

Ao

07

00

as

01

as

°2

a.

GND

03

A"

19

E/Es

18

CP

.,,'

CP

01

at

a.

21

16K (2048 x 8) REGISTERED PROM

_ IN!T/!N!TS
00

Ne

a,

22

10

11

13

14

15

16

17

BPM-324

a

a

0

BPM-322

0'
BPM-323

VcC=Pin24
GND=Pin 12

Note: Pin 1 is marked for orientation_

AM D's GENERIC FAMILY OF 8-WIDE REGISTERED PROMs

A7

Vee

A7

Vee

A7

24

Vee

As

A8

As

As

As

23

As

As

Ps

As

A9

As

22

Ag

~

E

A4

E

A4

21

Al0

A3

CLR

A3

INIT/INITs

A3

A2

ES

A2

ES

A2

S

Al

CP

Al

CP

Al

7

Ao

07

Ao

07

Ao

17

07

00

as

00

as

00

16

as

01

as

01

as

01

10

15

as

02

04

02

04

02

11

14

04

03

GND

03

GND

12

13

03

GND

BPM-325

512x8

20
Am27S45 19
Am27S47 lS

Note: Pin 1 is marked for orientation_
Chip-Pak is a trademark of Advanced Micro Devices, Inc_

2-118

CP

BPM-327

BPM-326

1024 x 8

INIT/INITS

E/ES

2048x8

Am27545AjS45jS47Aj547
PRELIMINARY
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 24 to Pin 12) Continuous

-0.5 to +7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5Vto +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE

Vee

Temperature

4.75 to 5.25V
4.5t05.5V

Te = -55to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
PRELIMINARY

Typ
Parameters

Test Conditions

Description

Min

VOH

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
V IN = VIH or VIL

VOL

Output LOW Voltage.

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 2)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 2)

IlL

Input LOW Current

Vee = MAX, VIN = 0,45V

IIH

Input HIGH Current

Vee = MAX, VIN = Vee

Ise

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 3)

lee

Power Supply Current

All inputs = GND, Vee = MAX

VI

Input Clamp Voltage

Vee = MIN, liN = -18mA

leEX

Output Leakage Current

Vee = MAX
VE = 2,4V

I

{Note 4)

(Note 1)

Max

2,4

Volts
0.38

0.50

-0.020

-40
130

IVo = Vee
IVo = O,4V

0.8

Volts

-0.250

mA

40

/LA

-90

mA

185

mA

-1.2

Volts

40
-40

CIN

Input Capacitance

VIN = 2.0V @f = 1MHz (Note 5)

5

COUT

Output Capacitance

VOUT = 2.0V @f = 1MHz (Note 5)

12

Notes: 1. Typical values are at Vee = 5.0V and TA = 25°C.
2. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment (see Notes on Testing).
3. Only one output should be shorted at a time. Duration of the short circuit should not be more than one second.
4. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
5. These parameters are not 100% tested, but are periodically sampled.

2-119

Volts

Volts

2.0

-20

Units

/LA

pF

Am27S45A/S45/S47 A/S47
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (See Notes on Testing)
PRELIMINARY
Am27S45A· Am27S47A
COM'L
Max
Min

Typ
Parameters

Description

(Note 1)

Am27S45· Am27S47

MIL
Max
Min

COM'L
Min
Max

Min

MIL
Max

Units

ts(A)

Address to CP (HIGH) Setup Time

25

40

45

45

50

ns

tH(A)

Address to CP (HIGH) Hold Time

-4

0

0

0

0

ns

tpHdCP)

Delay from CP (HIGH) to
Output (HIGH or LOW)

tpLH(CP)

All Outputs
Simlutaneous

13

20

25

25

Single Output
(Note 3)

11

18

21

20 "

ns

CP Width (HIGH or LOW)

10

20

20

ts(Es)

Es to CP (HIGH) Setup Time

5

15

15

tH(Es)

Es to CP (HIGH) Hold Time

-2

5

tpHL(INIT)

Delay from INIT (LOW) to Outputs
(LOW or HIGH) (Note 5)

-

tR(INIT)

INIT Recovery (Inactive) to CP (HIGH)
(Note 5)

,,,,""',

twdlNIT)

INIT Pulse Width (Note 5)

ts(INITs)

INITs to CP (HIGH) Setup Time (Note 6)

tH(lNITs)

INITs to CP (HIGH) Hold Time (Note 6)

tpzdCP)

,,'0'

Cp

Delay from
(HIGH) to Active Output
tpZH(CP) , (HIGH qr ~OW) (Note7)
tpLZ(CP)
tpHZ(CP)
tpzdE)
tpZH(E)
tpLZ(E)
tpHZ(E)
Notes: 1.
2.
3.
4.
5.
6.
7.
8.

'(
,,;

2oC
" ",

';:'8,,' "
'"

',:
I"

"

","

","'"
, 25

'

""<,">""'"

<15',

"",5;,

y;~;"

rJ ''

",'"

'

('"

I;;:

23

i:

Iii

20
"':,,

ns

15

ns

5

ns

"",

35

40

ns

""

,"',':'

\,::

""

"'" 5 "

,"'3D"

"""',>'"

.;,
j ; } .;<;

twdCP)

tpLH(lNID

i

"C'

,,,"/"'"

tWH(CP)

30

\,\

20

20

20

ns

30

25

30

ns

> ,,:o1S

25

30

30

35

ns

-5

0

0

0

0

ns

<'

3

15

25

30

30

35

ns

15

25

30

30

35

ns

Delay from E (LOW) to Active Output
(HIGH or LOW) (Note 8)

15

25

30

30

35

ns

Delay from E (HIGH) to Inactive Output
(OFF or High Impedance) (Notes 4 and 8)

10

25

30

30

35

ns

Delay from CP(H1GH) to Inactive Output
(OFF or High Impedance) (Notes 4 and 7)
-

Typical values at Vee = 5.0V and TA = 25°C.
Tests are performed with input 10 to 90% rise and fall times of 5ns or less.
Single register performance numbers provided for comparison with discrete register test data.
tpHZ and tpLZ are measured to the VOH -0.5V and VOL +0.5V output levels respectively. All other switching parameters are tested from and
to the 1.5V threshold levels.
Applies only to the Am27S45N45 (asynchronous INITIALIZE function).
Applies only to the Am27S47 N47 (synchronous INITIALIZE function).
Applies only when synchronous ENABLE function is used.
Applies only when asynchronous ENABLE function is used.

2-120

Am27S45A/S45/S47 A/S47
SWITCHING WAVEFORMS
(See Notes on Testing)

3V
t.5V
OV

3V
1.5V
OV

3V
1.5V

CP

OV

VOH

VOL

3V
1.5V

I ~_'R_(~_NI_n

Am27S45 {INIT

Only

H;

OV

__________________________________________________________________ 3V
1.5V

OV

WLlINIT)

IS(iNIT~)

IH(INITS)

Am2~~{ INITS

--r-r-------------------------------------

\..10.1.1._ _ _....LIJ-J

3V

_-~~~~~~~~~~~~~~_-~_-_-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~_-_ OV
BPM-327

NOTES ON TESTING
Incoming test procedures on these devices should be carefully
planned, taking into account the high performance and output
drive capabilities of the parts_ The following notes may be useful.
1. Ensure that adequate decoupling capacitance is employed
across the device Vcc and ground terminals. Multiple
capacitors are recommended, including a 0.1JLFarad or
larger capacitor and a 0.01 JLFarad or smaller capacitor
placed as close to the device terminals as possible. Inadequate decoupling may result in large variations of power
supply voltage, creating erroneous function or transient performance failures.

2. Do not leave any inputs disconnected (floating)
during any tests.
3. Do not attempt to perform threshold tests under AC conditions. Large amplitude, fast ground current transients
normally occur as the device outputs discharge the load
capacitances. These transients flowing through the parasitic
inductance between the device ground pin and the test system ground can create significant reductions in observable
input noise immunity.

ACTESTLOAD

KEY TO TIMING DIAGRAM

WAVEFORM

Rl
300n

---+

OUTPUT 0 - - -......

R2
600n

BPM-040

-

JJJJJJ

Notes: 1. CL = 50pF for all switching characteristics except tpLZ
and tpHZ.
2. CL = 5pF for tpLZ and tpHZ'
3. 51 is closed for all tests except for tpHZ and tPZH.
4. All device test loads should be located within 2" of
device outputs.

2-121

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

--

WAVEFORM

H

INPUTS

DON'T CARE;
ANY CHANGE
PE~MITTED

DOES NOT
APPLY

OUTPUTS

CHANGING;
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

fl

Am27S45A/S45/S47 A/547
PROGRAMMING
These 16K registered PROMs are manufactured with a conductive Platinum-Silicide link at each bit location. The output of the
memory with the link in place is LOW. Programming each bit location (i.e. opening the fusible links) is accomplished by first applying a logic HIGH to the E/Es and INIT/INITS inputs, followed
by a LOW-to-HIGH clock transition in order to disable the outputs (although devices with an asynchronous ENABLE input do
not require this clock pulse, it nevertheless may be included in
the programming algorithm without affecting the programmability of the devices. This feature allows the use of a common
generic programming algorithm for use on all registered
PROMs). The output is then raised to 20 volts, and current from
this 20 volt supply is then gated through the addressed fuse by
raising the 'E/Es input from a logic HIGH to 15 volts. After
50p.sec, the 20 volt supply is removed, the chip is enabled and
the CP input is clocked. Each data verification must be preceded
by a positive going (LOW-to-HIGH) clock edge to load the array
data into the on-chip register. The output level is then sensed to
determine if the link has opened. Most links will open within
50p.sec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5 msec. If a link has not opened
after total elapsed programming time of 400 msec, further programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.
The initialize word is programmed by setting the INIT/INITS input
to a logic LOW and programming the desired initialize word,
output by output, in the same manner as any other address location. The address inputs may assume either logic state, but
should not be left open, in order to avoid the possibility of oscillation. This is easily implemented by inverting the A11 address
input from a PROM programmer and applying this signal to the
INIT/INITS input. Using this method the initialize word would be
programmed as address 2048. When INIT/INITS is asserted
LOW the internal programming circuitry for all other addresses
is deselected. Address AO must be LOW.
The enable input for these devices is shipped from the factory
as an asynchronous enable (E) and may be programmed to a
synchronous enable (Es) by using the following programming
procedure. To program the enable function to a synchronous
enable the INIT/INITS input must be set to a logic LOW, with address Ao in a logic HIGH state. A standard programming pulse
should then be applied to output Q o. The remaining address inputs may assume either logic state, but should not be left open

in order to avoid possibility of oscillation. This is easily implemented by inverting the A11 address from a PROM programmer and applying this signal to the INIT/INITS input. Using
this method the synchronous enable word would be treated as
address 2049.
Typical current into an output during programming will be approximately 190mA until the fuse link is opened, after which the
current drops to approximately 11 OmA. Current into the E/Es pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
continuously applied to one device more than 5 seconds to
avoid heat damage. If this programming time is exceeded, all
power to the chip including Vee should be removed for a period
of 5 seconds after which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by clocking and reading all
words. Occasionally this verification will show that an undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.
It should be noted that when programming ]'s, the enable pin is
changing from an asynchronous enable (E) to a synchronous
enable (Es). This is a functional change rather than a data
change to the part. Therefore, verification that the programming
event has taken place must be performed in a different manner.
The Am27S45/47 contains on-chip circuitry which when enabled
will cause the E/Es fuse to appear as data on all outputs simultaneously; i.e. fuse intact = asynchronous enable = 00 16 and
fuse programmed = synchronous enable = FF 16 . This verification circuitry is enabled by taking the Ao input to a "zener high
level" (14V. to 15V.). This "zener high level" should be used for
read and verification cycles only (not programming) and preferably for the explicit address used for E/Es data only.
An alternative to using the on-chip verification circuitry would be
for the programming equipment to utilize decision making capability in conjuction with clock and enable to determine in which
functional mode the enable is operating.

2-122

Am27S45A/S45/S47A/S47
PROGRAMMING PARAMETERS
Description

Parameters

Min

Max

Units
Volts

Veep

Vee During Programming

5~0

5.5

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

V1LP

Input LOW Level During Programming

0.0

0.45

Volts

V"ENP

ElEs Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

VONP

Voltage on Outputs Not to be Programmed

IONP

Current into Outputs Not to be Programmed

20

mA

d(VOp)/dt

Rate of Output Voltage Change

20

250

V//-Lsec
V//-Lsec

d(V"EN)/dt
tp
Notes: 1.
2.
3.
4.

0

Veep

+ 0.3

Volts
Volts

Rate of ElEs, Voltage Change

50

1000

Programming Period - First Attempt

50

100

/-Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1 through t7 must be greater than 100ns; maximum delays of 1/-Lsec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM

VONP

--v
A~~~~ ....A_ _ _ _ _

\~VIHP

S_E_LE_CT_ED_A_DD_RE_S_SS_TA_BL_E_ _ _-\~

~

V
tLP

~ES
ENABLE

PROGRAMMED
OUTPUT

CP
CLOCK

BPM-328
BPM·329

2-123

Am27S45A/S45/S47 A/S47
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Oigelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City,
Scottsdale, AZ. 85260
CA94063

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803 PPX

AMO Generic
Bipolar PROM
Personality
Module

909-1286-1 Rev J*
919-1286-1 Rev J*

PM 9058

IMAMOGEN1

MOD 14

PM102

FAM-12

PA24 and
2049 x 8(L)

1M 2048 x 8-27S45/
47 AMD

SA 31 B
2048 x 8/24

01S-217 AM

DA 64

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94086

PM 2000
Code 90

Socket Adapters and Configurators
Am27S45
Am27S47

715-1660

* Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be

delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

ORDERING INFORMATION
Speed
Selection

Order Code

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

P-24-1AA (Note 4)
P-24-1 AA (Note 4)
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
B-3
C-3
B-3
C-3
B-3

MIL

AM27S47PC
AM27S47PCB
AM27S47DC
AM27S47DCB
AM27S47LC
AM27S47LCB

P-24-1AA (Note 4)
P-24-1AA (Note 4)
D-24-1AA
D-24-1AA
L-32-2
L-32-2

C-1
B-1
C-1
8-1
C-1
B-1

COM'L

AM27S47DM
AM27S47DMB
AM27S47FM
AM27S47FMB
AM27S47LM
AM27S47LMB

D-24-1AA
D-24-1AA
F-24-1
F-24-1
L-32-2
L-32-2

C-3
B-3
C-3
B-3
C-3
B-3

MIL

Asynchronous
INITIALIZE

Synchronous
INITIALIZE

40ns

AM27S45APC
AM27S45APCB
AM27S45ADC
AM27S45ADCB
AM27S45ALC
AM27S45ALCB

AM27S47APC
AM27S47APCB
AM27S47ADC
AM27S4 7ADCB
AM27S47ALC
AM27S47ALCB

45ns

AM27S45ADM
AM27S45ADMB
AM27S45AFM
AM27S45AFMB
AM27S45ALM
AM27S45ALMB

AM27S47ADM
AM27S47ADMB
AM27S47AFM
AM27S47AFMB
AM27S47ALM
AM27S47ALMB

45ns

AM27S45PC
AM27S45PCB
AM27S45DC
AM27S45DCB
AM27S45LC
AM27S45LCB

50ns

AM27S45DM
AM27S45DMB
AM27S45FM
AM27S45FMB
AM27S45LM
AM27S45LMB

(Setup Time)

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
4. This package will be available soon. Consult Factory.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding diagram
available upon request.

2-124

Am27S40A • Am27S41A
Am27S40 • Am27S41
16,384-Bit Generic Series Bipolar 'MOX™ PROM
(4096 x 4 bits with ultra fast access time)

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Ultra fast access time "A" version (35ns max) Fast access time Standard version (50ns max) allow tremendous system speed improvements

The Am27S40A, Am27S41 A, Am27S40, and Am27S41 are
high speed electrically programmable Schottky read only
memories. Organized in 4096 x 4 configuration, they are
available in both open collector (Am27S40A and Am27S40)
and three-state (Am27S41A and Am27S41) output versions. After programming, stored information is read on outputs 0 0 -03 by applying unique binary addresses to Ao-A11
and holding the chip select inputs, CS 1 and CS 2, LOW. If
either chip select input goes to a logic HIGH, 0 0 -03 go to the
OFF or HIGH impedance state.

• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming yields
(typ> 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing
extremely flat AC performance over military range

BLOCK DIAGRAM

• Member of generic PROM series utilizing standard
programming algorithm
• 100% MIL-STD-883C assurance testing
• Guaranteed to INT-STD-123

128 X 128
FUSE ARRAY

GENERIC SERIES CHARACTERISTICS

These 16K PROMs are members of an Advanced PROM
series incorporating common electrical characteristics and
programming procedures. All parts in this series are produced with a fusible link at each memory location storing a
logic LOW and can be selectively programmed to a logic
HIGH by applying appropriate voltages to the circuit.
All parts are fabricated with AMD's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words are
pre-programmed during manufacturing to insure extremely
high field programming yields, and produce excellent
parametric correlation.

A4
A3
A2
Al
AO

eS 1
eS 2

BPM-194

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large nonconductive gaps that ensure very stable long-term reliability.
Extensive operating testing has proven that this low-field,
large-gap technology offers the best reliability for fusible
link PROMs.

CONNECTION DIAGRAMS - Top Views

.

~

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths.
These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOX™. This
advanced process combined with a merged fuse array permits an increase in density and a decrease in internal
capacitance resulting in the fastest possible PROMs.

Chip-Pak™

DIP

A8

Vee

(j
(j

z

(j

z

u

>

.£'

A,o

A7

A9

A7

As

Ala

As

A"

As

All

As

CS2

A.

CS,

A3

Ne

A2

NC

A,

NC

A4

eS 2

A3

eS 1

A2

00

Al

°1

Ao

°2
03

GND

Ao

00

NC

0,

(j

z

BPM-195

c

z

"

(j

z

Note: Pin 1 is marked for orientation.

IMOX is a trademark of Advanced Micro Devices, Inc.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.
2-125
-

-

---

B

0
BPM-196

Am27S40A/S41A/S40/S41
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

- 55 to + 125°C

Supply Voltage to Ground Potential (Pin 20 to Pin 10) Continuous

- 0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5V to +VCC max

DC Voltage Applied to Outputs During Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

- 0.5 to + 5.5V

DC Input Current

-30 to +5mA

OPERATING RANGE

Vee

Temperature

LOGIC SYMBOL

4.75 to 5.25V
4.5 to 5.5V

Te

1

= -55 to +125°C

19

18

A4
A3
A2

Am27S40A/4l A
Am27S40/4l

Al

All

17

CS l

15

CS 2

16

AO

Vee = Pin 20
GND = Pin 10

14

13

12

11

BPM·197

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Type
Parameters
VOH
(TS Devices only)

Output HIGH Voltage

Vee = MIN, IOH = - 2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

Vee = MAX, VIN = 0.45V

IIH

Input HIGH Current

Vee

(Note 1)

Vee = MAX, VOUT
(Note 2)

Output Short Circuit Current

lee

Power Supply Current

VI

Input Clamp Voltage

Vee

leEX

Output Leakage Current

Vee = MAX
VCS 1 = 2.4V

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

COM'L

0.45

MIL

0.50

@f

0.8

Volts

-0.250

mA

40

/LA

COM'L

-20

-40

-90

MIL

-15

-40

-90

COM'L

110

165

MIL

110

170

= MIN, liN = -18mA

-1.2

IVo = Vee
Iva = O.4V
= 1MHz (Note 3)

= 2.0V @ f = 1MHz (Note 3)

mA

mA
Volts

40
-40
5.0
8.0

Typical limits are at Vee = 5.0V and TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

2-126

Volts

Volts

-0.020

= o.OV

Units
Volts

2.0

All inputs = GND,
Vee = MAX

= 2.0V

Max

2.4

= MAX, VIN = Vee

Ise
(TS Devices only)

Notes: 1.
2.
3.
4.

Min

Test Conditions

Description

/LA
pF

Am27S40A/S41A/S40/S41
SWITCHING CHARACTERISTICS
OVER OPERATING RANGE
Typ

Max

5V 25°C
Parameters

Test Conditions

Description

tM

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

AC Test Load
(See Notes 1, 2, 3)

COM'L

MIL

A

STD

A

STD

A

STD

Units

25

30

35

50

50

65

ns

10

10

25

25

30

30

ns

10

10

25

25

30

30

ns

Notes: 1. tM is tested with switch S1 closed and CL = 30pF.
2. For open collector outputs, tEA and tER are tested with Sl closed to the 1.5V output level. CL = 30pF,
3. For three-state outputs, tEA is tested with CL = 30pF to the 1.5V level; S1 is open for high impedance to HIGH tests and closed for high impedance
to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage of VOH - 0.5V; LOW to high
impedance tests are made with S1 closed to the VOL + 0.5V level.

SWITCHING CHARACTERISTICS

"·,,,3
CS 1.CS2

3.0V
1.SV
OV

I
f--1

AA

---J

r.-4'~

f-'''~

»»>-::~:.: «@

XXX*

00- 0 3

~

f

I

Note: Level on output while either CS is HIGH is determined externally.

1.SV
OV

VO H
1.SV
VOL

BPM-198

KEY TO TIMING DIAGRAM

WAVEFORM

---

---

-JJJ[ff

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM HTO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

--

WAVEFORM

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

VCC~O--S1
R1
3000
OUTPUT

"r
2-127

R2
6000

-==
BPM·199

Am27S40A/S41A/S40/S41
PROGRAMMING
This entire Generic PROM. Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the device,
the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS1 input is a logic HIGH. Current is
gated through the addressed fuse by raising the CSl input from a
logic HIGH to 15 volts. After 50ll-sec, the 20 volt supply is
removed, the chip is enabled, and the output level sensed to
determine if the link has opened. Most links will open within
50ll-sec. Occasionally a link will be stronger and require additional
programming cycles. The recommended duration of additional
programming periods is 5msec. If a link has not opened after a
total elapsed programming time of 400msec, further programming of the device should not be attempted.· Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.
Typical current into an output· during programming will be approximately 180mA until the fuse link is opened, after which the

current drops to approximately 90mA. Curreht into the CS1 pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage.
If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are Within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Description

Parameters

Min

Max

Units

Veep

Vee During Programming

S.O

5.S

Volts

VIHP

Input HIGH Level During Programming

2.4

5.S

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCS1P

CS1 Voltage During Programming

14.S

15.5

Volts

VOP

Output Voltage During Programming

19.5

20.S

Volts

VONP

Voltage on Outputs Not to be Programmed

0

Veep + 0.3

Volts

IONP

Current into Outputs Not to be Programmed

20

rnA

d(Vop)/dt

Rate of Output Voltage Change

20

250

V/p.sec

d(VCS1)/dt

Rate of CS1 Voltage Change

SO

1000

V/p.sec

Programming Period - First Attempt

SO

100

p.sec

Programming Period - Subsequent Attempts

S.O

15

msec

tp
Notes: 1.
2.
3.
4.

All delays between edges are specified from completion of the first edge to beginning of the second edge; Le., not to the midpoints.
Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of lp.sec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

A~~::i~

I

d
(it

cs,

ENABLE

Vccp
SELECTED ADDRESS STABLE

Y

_
(Vcs,P),

11~~
-,

...-J

PROGRAMMED
OUTPUT

~

C

1

V1HP
VILP
VCS,P

PROGRAMMING CYCLE

AO-A11G

r- ''''

cs, , - -

_IV _

cSiI

\ OUTPUT ,.,. VOH
~E.!!!f.lu_
'-:OL

Vcsl

I

n
-=-

BPM-200
2-128

VONP

R.. 2oon

~

~o4Kx4
PROM

~-"~
~ 1_14
VOP

'-!!.(VOPl
dl

I

SIMPLIFIED PROGRAMMING DIAGRAM

kO~o-

1"

n

VOP

-=BPM-201

Am27S40A/S41A/S40/S41
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

Data 110
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City,
CA 94063

Digelec, Inc.
3 Tevuot Haaretz St.
Tel-Aviv, Israel

Stag Systems, Inc.
1120 San Antonio Rd.
Palo Alto, CA 94303

Programmer
Model(s}

Model 5, 7, and 9
Systems 17 and 19

M900, M900B, M910,
M920, and M9BO

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMD Generic
Bipolar PROM
Personality
Module

909-1286-1 Rev H·
919-1286-1 Rev H*

PM 9058

1M AMDGEN1

MOD 14

PM 102

FAM-12

PM 2000
Code 90

PA 20-9 and
4096 x 4(L)

1M 4096 x 4-20-AMD SA 30 B 4096 x 4/20

DIS-216AM

DA63

AM 120-6

Am27S40A/41 A
Am27S40/41

715-12B2

K:'t

• Rev shown is minimum approved revision.

~-----------i~
OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred
paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth table
requires the generation of a punched paper tape at the distributor
or factory resulting in longer lead times, greater possibility of
error, and higher cost.

ASCII BPNF
An example of an ASCII tape in the SPNF format is shown below.
They can be punched on any Teletype@ or on a TWX or Telex
machine. The format chosen provides relatively good error
detection. Paper tapes must consist of:
1. A leader of at least 25 rubouts.
2. The data patterns for all 4096 words, starting with word 0, in
the following format:
a. Any characters, including carriage return and line feed,
except "S".
b. The letter "S", indicating the beginning of the data word.
c. A sequence of four Ps or Ns, starting with output 03.
d. The letter "F", indicating the finish of the data word.
e. Any text, including carriage return and line feed, except
the letter "S".

3. A trailer of at least 25 rubouts.
A P is a HIGH logic level = 2.4 volts.
An N is a LOW logic level = 0.5 volts.
A convenient pattern to use for the data words is to prefix the
word (or every few words) with the word number, then type the
data word, then a comment, then carriage return and line feed as
shown below. There must be no characters between the Sand
the F except for the four Ps and Ns. If an error is made in a word,
the entire word must be cancelled with rubouts back to the letter
S, then the word re-typed beginning with the S.
When TWXing your tape, be sure the tape is in even parity.
Parity is not necessary if the tape is mailed.

RESULTING DEVICE TRUTH TABLE
(CS 1 AND CS 2 = LOW)

TYPICAL PAPER TAPE FORMAT

WORD ZERO@ ~
COMMENT FIELD R @

¢¢¢
¢¢2
¢¢4
¢¢6

BNNNPF
BPPNNF
BPPPNF
BNNNNF
BNNNPF
BPPNNF
BPPNNF

TEX'I R

4095

BPPPNF

EN"D@@

I

......
.. ....

All Al0 Ag

ANY~'
~
L

CAlI

GO R L
HERE R @

2-129

As A7 As As A4 A3 A2 Al Ao

03 02 01

00

L
H
H
L
L
H
H

L
L
H
L
L
L
L

H
L
L
L
H
L
L

H

H

L

L
L
L
L
L
L
L

L
L
L
L
L
L
L

L
L
L
L
L
L
L

L L L L
L L L H
L L H L
L L H H
L H L L
L H L H
L H H L

L
H
H
L
L
H
H

H

H

H H H H H H H H H H

H

L
L
L
L
L
L
L

L L
L L
L L
L L
L L
L L
L L

L
L
L
L
L
L
L

L
L
L
L
L
L
L

Am27S40A/S41A/S40/S41
ASCII PAPER TAPE

I

LEADER
25 RUBOUTS

, __

..........

/

I

ASCII 'B'
WORD '0'

A~F~II

['B'

,

r

'F'

WORD '1'

TRAILER

rCR

25 RUBOUTS

::::;;;;: :::::;;;;:~ :
00000

o

00000

4 'P's OR 'N's

.....

L

0000000

0

.....................

00000

4 'P's OR 'N's

L

/

LF

OPTIONAL COMMENTS MAY BE INSERTED HERE

8f>M-202

ORDERING INFORMATION
Order Code
Speed
Selection

Open
Collector

Three-State

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

35ns

AM27S40APC
AM27S40APCB
AM27S40ADC
AM27S40ADCB
AM27S40ALC
AM27S40ALCB

AM27S41APC
AM27S41 APCB
AM27S41ADC
AM27S41ADCB
AM27S41ALC
AM27S41ALCB

P-20-1
P-20-1
D-20-1
D-20-1
L-28-2
L-28-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

50ns

AM27S40ADM
AM27S40ADMB
AM27S40ALM
AM27S40ALMB

AM27S41ADM
AM27S41ADMB
AM27S41ALM
AM27S41ALMB

D-20-1
D-20-1
L-28-2
L-28-2

C-3
B-3
C-3
B-3

MIL

50ns

AM27S40PC
AM27S40PCB
AM27S40DC
AM27S40DCB
AM27S40LC
AM27S40LCB

AM27S41PC
AM27S41 PCB
AM27S41DC
AM27S41DCB
AM27S41LC
AM27S41LCB

P-20-1
P-20-1
D-20-1
D-20-1
L-28-2
L-28-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

65ns

AM27S40DM
AM27S40DMB
AM27S40LM
AM27S40LMB

AM27S41DM
AM27S41DMB
AM27S41LM
AM27S41LMB

D-20-1
D-20-1
L-28-2
L-28-2

C-3
B-3
C-3
B-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

2-130

Am27PS41
16,384-Bit Generic Series Bipolar IMOX™ PROM
4096 x 4 Bits with Power-Down Via CS

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time Standard version (50ns max) allows tremendous system speed improvements

The Am27PS41 is a high speed electrically programmable
Schottky read only memory. Organized in 4096 x 4 configuration, it is available in the three-state (Am27PS41) output
version. After programming, stored information is read on
outputs 0 0-03 by applying unique binary addresses to
Ao-A11 and holding the chip select inputs, CS1 and CS2,
LOW. If either chip select input goes to a logic HIGH, 0 0 -03
go to the OFF or HIGH impedance state.

• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming yields
(typ> 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing
extremely flat AC performance over military range

BLOCK DIAGRAM

• Member of generic PROM series utilizing standard
programming algorithm
• 100% MIL-STD-883C assurance testing

A"

• Guaranteed to INT-STD-123

A'D
A9

1 OF 128
ROW
DECODER

A8

GENERIC SERIES CHARACTERISTICS

'28 X ,28
FUSE ARRAY

A7

This 16K PROM is a member of an Advanced PROM series
incorporating common electrical characteristics and programming procedures. All parts in this series are produced
with a fusible link at each memory location storing a logic
LOW and can be selectively programmed to a logic HIGH
by applying appropriate voltages to the circuit.

As
As

A4
A3
A2

All parts are fabricated with AM D's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words
are pre-programmed during manufacturing to insure
extremely high field programming yields, and produce
excellent parametric correlation.

A,
AD

CS,
CS 2

BPM-194

Platinum-Silicide was selected as the fuse link material to
achieve a well controlled melt rate resulting in large
non-conductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

CONNECTION DIAGRAMS - Top Views
Chip-Pak™
L-28-2

DIP
.;

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths.
These PROMs are manufactured using Advanced Micro
Devices' selective oxidation process, IMOX. This advanced
process combined with a merged fuse array permits an
increase in density and a decrease in internal capacitance
resulting in the fastest possible PROMs.

<)

z

<)

z

.r

A8

VCC

A7

Ag

A7

As

A'D

As

All

As

AI'

As

CS2

A.

CS,

A4

CS 2

A3

CS;

A2

00

A,

0,

AD

O2

03

GND

A'D

A3

NC

A2

NC

A,

NC

Ao

00

NC

0,

<)

z

BPM-195

0

z

"

<)

z

Note: Pin 1 is marked for orientation.
IMOX is a trademark of Advanced Micro Devices, Inc.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

0

,;>

2-131
. -

.. -

.-

,f

c;
BPM-196

Am27PS41
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to + 125°C

Supply Voltage to Ground Potential (Pin 20 to Pin 10) Continuous

-0.5to +7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5V to + VCC max

DC Voltage Applied to Outputs DurinOg Programming

21V

Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5 to +5.5V

DC Input Current

-30to +5mA

OPERATING RANGE
LOGIC SYMBOL

Temperature

1

TC = -55 to +125°C

19

18

17

15
16

Vee = Pin20
GND = Pin 10

14

13

12

11

BPM·219

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN,IOH
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN,IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 4)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 4)

IlL

Input LOW Current

Vee

IIH

Input HIGH Current

Vee

Ise

Output Short Circuit Current

Vee = MAX, VOUT
(Note 2)

lee

Power Supply Current

VI

Input Clamp Voltage

leEX

Output Leakage Current

= -2.0mA

(Note 1)

Max

2,4
0,45

I MIL

0.50

Volts

2.0

Volts

-0.020

I COM'L
I MIL

0.8

Volts

-0.250

mA

40

/-LA

-20

-40

-90

-15

-40

-90

All inputs

110

170

CSl

50

85

= O.OV

= GND
= 2.7V I All other inputs = GND
Vee = MIN,IIN = -18mA
Vee
VCS

= 2.0V @f = 1MHz (Note 3)
= 2.0V @ f = 1MHz (Note 3)

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

mA

mA
-1.2

IVa = Vee
IVa = O,4V

= MAX
= 2,4V

Volts

40
-40
5.0
8.0

Typical limits are at Vee = 5.0V and TA = 25°C.
Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
These parameters are not 100% tested, but are periodically sampled.
These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

2-132

Units
Volts

I COM'L

= MAX, VIN = 0,45V
= MAX, VIN = Vee

1

Notes: 1.
2.
3.
4.

Min

/-LA

pF

Am27PS41
SWITCHING CHARACTERISTICS ,OVER OPERATING RANGE
Typ
Description

Parameters
tAA1

Test Conditions

Address Access Time

COM'L

MIL

Units

30

50

65

ns

50

70

85

ns

50

70

85

ns

10

25

30

ns

tEAS;;" 25ns

tAA2

Power Switched Address Access Time

tEAS = Ons

tEA

Enable Access Time

tAES;;" Ons

tER

Enable Recovery Time

Max

5V25°C

AC
Test Load
(Notes 1 and 2)

Notes: 1. tAA is tested with switch S1 closed and CL = 30pF. tEAS is defined as chip enable setup time.
2. For the three-state output. tEA is tested with CL = 30pF to the 1.5V level; S1 is open for high impedance to HIGH tests and closed for
high impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage
of VOH - O.5V; LOW to high impedance tests are made with S1 closed to the VOL +0.5V level.

SWITCHING WAVEFORMS

A(r-A11

~'---_____________---J\V"'-------- :~

-_-_-_-:_-_-_-_-:_-_-_-_-_

:::::::~~~::_-_-:_--JA\_-----------------:IKI-.,-

r-

tEAS

cs=\

I

f

I

f-tAA--J

t

AES

--1

f-tER~

««XXX!

o~

~

3.0V

\-::
f-tEA-i

({{{E::

»»)I-::~:

Note: Level on output while either CS is HIGH is determined externally.

BPM-198

KEY TO SWITCHING WAVEFORMS

WAVEFORM

---

---

-l!!lIJ

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM HTO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

WAVEFORM

---

H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

Vcc~O--51
R1

300n
OUTPUT

oct

R2

600n

-=:
BPM·220

2-133

Am27PS41
POWER SWITCHING

1. When the Am27PS41 is selected by a low level on CS1, a
current surge is placed on the Vee supply due to the
power-up feature. In order to minimize the effects of this
current transient, it is recommended that a 0.1/LF ceramic
capacitor be connected from pin 20 to pin 10 at each device.
(See Figure 1.)

The Am27PS41 is a power switched device. When the chip is
selected, important internal currents increase from small idling
or standby values to their larger selected values. This transition
occurs very rapidly, meaning that access times from the
powered-down state are only slightly slower than from the
powered-up state. Deselected, ICC is reduced to half its full
operating amount. Due to this unique feature, there are special
considerations which should be followed in order to optimize
performance:

2. Address access time (tAA) can be optimized if a chip enable
set-up time (tEAS) of greater than 25ns is observed. Negative
set-up times on chip enable (tEAS < 0) should be avoided.
(For typical and worse case characteristics, see Figure 2.)

Typical lee Current Surge without O.1/LF
(Iec is Current Supplied by Vee Power Supply)

Typical lee Current Surge with O.1/LF
(lee is Current Supplied by Vee Power Supply)

~t3

I

I

~f!?

I~g 0
120

<

E
I
0

2

3

I~~

0

II
Il

2:f!?

_;..J

t

~t

110
100
90

f\
I
I ['-.....
I

r-1\

80
70
60
50

"

't--...

...."-

40
0

100

200

300

400

500

-

110

........ ~

t

<

II
II

600

E
I
0

.9
700

100
i--90
80
70
60
50
40

900 1000

800

r-...

./r~

""

0

100

200

L

L

~

300

./

........ t-- ./

400

600

500

700

900 1000

800

TIME - n s -

TIME - n s -

BPM-147

BPM-146

Figure 1. lee Current

30
20

t

10

til

c
I

0

, N K

,

':"\

~

tAA1- MAX

~

II)

~ -10

.'"

"

I"

I'"

60

70

t
c
,

K,

0

1/1

w

teATY~/

= 25°C
V~c = 5.0V

-20 f--- TA

"

90

\

20

30

40

~~

I~~<

~

-30

100

I'"

1\

...< -10

K

tAA - n s -

I'--t--

10

III

~~

80

I

teA-M~

20

I\.. tAA2-~AX

~l /

tAA2 TYP ""-20 I- TA 25"C
Vee s.OV
-30
40
20
30
50

=
=

30

50

60

70

80

I'"

90

100

teA - n s BPM-222

BPM-221

Figure 2A. tAA versus tEAS

Figure 28. tEA versus tAES

2-134

Am27PS41
PROGRAMMING
This entire Generic PROM Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the device, the fusible links are selectively opened.
The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS1 input is a logic HIGH. Current is
gated through the addressed fuse by raising the CS1 input from
a logic HIGH to 15 volts. After 50lLsec, the 20 volt supply is
removed, the chip is enabled, and the output level sensed to
determine if the link has opened. Most links will open within
50lLsec. Occasionally a link will be stronger· and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.
Typical current into an output during programming will be approximately 180mA until the fuse link is opened, after which the

current drops to approximately 90mA. Current into the CS1 pin
when it is raised to 15 volts is typically 1.5mA.
The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.
When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input signal
levels exhibit sufficient noise margins, and that the programming
voltages are- within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing; fusing extra bits
is generally related to programming equipment problems.

PROGRAMMING PARAMETERS
Min

Max

Units

Vccp

Vcc During Programming

Description

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

Parameters

VCS1P

CS1 Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

0

Vccp + 0.3

Volts

VONP

Voltage on Outputs Not to be Programmed

IONP

Current into Outputs Not to be Programmed

d(Vop)/dt

Rate of Output Voltage Change

d(VcS1)/dt
tp
Notes; 1.
2.
3.
4.

20

rnA

20

250

V/J.Lsec
V/J.Lsec

Rate of CS 1 Voltage Change

100

1000

Programming Period - First Attempt

50

100

J.Lsec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1. t2. t3 and t4 must be greater than 100ns; maximum delays of 1/-Lsec are recommended to minimize heating during programming.
During tv, a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

SIMPLIFIED PROGRAMMING DIAGRAM

VONP

VCCP

ADDRESS

~

SELECTED ADDRESS STABLE

~: I ~ ~'), I

PROGRAMMED
OUTPUT

~

C

I
V'HP
AO-At1

r- : '

It------PROGRAMMING CYCLE

ii

\ OUTPUT
~E.!!!,F.!.u_

-----11

PROM
CS1

r--

csif

v

OH

vcs,P

VOL

0--

-0......
4Kx4

\

"--- _ (Vop)
dt

~
01

~l" I~d ~ IC ~=::
-'-I

--I

c::)

R",2000

n
':"

~o-~o--

-=1-

n

VOP

':"

BPM-201

BPM-200

2-135

Am27PS41
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
Location

DataI/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc. Digelec, Inc.
630 Price Avenue
7335 E. Acoma Dr.
Redwood City,
Scottsdale, AZ S5260
CA94063

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920, and M9S0

IM1010

MPP-SO

UPP-801

UPP-S03 PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev H*
919-1286-1 Rev H*

PM 9058

IMAMDGEN1

MOD 14

PM 102

FAM-12

PM 2000
Code 90

Am27PS41

715-1282

PA20-9and
4096 x 4(L)

1M 4096 x 4-20-AMD

SA 30 B 4096 x 4/20

DIS-216AM

DA63

AM 120-6

Stag Systems, Inc.
52S-5 Weddell Dr.
Sunnyvale, CA 94086

* Rev shown is minimum approved revision.
OBTAINING PROGRAMMED UNITS
Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submissionof a truth table
requires the generation of a punched paper tape at the distributor or factory resulting in longer lead times, greater possibility of error, and higher cost.

ORDERING INFORMATION

Speed
Selection

tAA1 = 50ns
tAA2 = 70ns

tAA1 = 65ns
tAA2 = 85n5

Order Code

Package
Type

Screening
FlowCode·

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM27PS41PC
AM27PS41 PCB
AM27PS41DC
AM27PS41 DCB
AM27PS41LC
AM27PS41 LC8

P-20-1
P-20-1
D-20-1
D-20-1
L-28-2
L-28-2

C-1
B-1
C-1
B-1
C-1
8-1

COM'L

AM27PS41DM
AM27PS41 DM8
AM27PS41LM
AM27PS41 LM8

D-20-1
D-20-1
L-28-2
L-28-2

C-3
8-3
C-3
8-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak. Number following letter is
number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications.
Pad layout and bonding diagram available upon request.

2-136

Am27S43A • Am27S43
32,768·Bit Generic Series Bipolar 'MOX™ PROM
(4096 x 8 bits with ultra fast access timeJ
ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Ultra fast access time "A" version (40ns max) Fast access time Standard version (55ns max) allow tremendous system speed improvements
• Platinum-Silicide fuses guarantee high reliability, fast
programming and exceptionally high programming
yields (typ > 98%)
• AC performance is factory tested utilizing programmed
test words and columns
• Voltage and temperature compensated providing extremely flat AC performance over military range
• Member of generic PROM series utilizing standard programming algorithm
• 100% MIL-STO-883C assurance testing
• Guaranteed to INT-STO-123

The Am27S43A and Am27S43 are high speed electrically
programmable Schottky read only memories. Organized in
4096 x 8 configuration, they are available in three-state
(Am27S43A and Am27S43) output versions. After programming, stored information is read on outputs 00-07 by
applying unique binary addresses to Ao-A11 and holding the
chip select inputs, CS1, LOW and CS2, HIGH. If CS1 goes
to logic HIGH or CS2 goes to a logic LOW, 00-07 go to the
OFF or HIGH impedance state.

BLOCK DIAGRAM

All
A IO

GENERIC SERIES CHARACTERISTICS

128 x 256

Ag

PROGRAMMABLE
ARRAY

As

These 32K PROMs are members of an Advanced PROM
series incorporating common electrical characteristics and
programming procedures. All parts in this series are produced with a fusible link at each memory location storing a
logic LOW and can be selectively programmed to a logic
HIGH by applying appropriate voltages to the circuit.

A7
A6
As

A4
A3

All parts are fabricated with AMO's fast programming highly
reliable Platinum-Silicide Fuse technology. Utilizing easily
implemented programming (and common programming
personality card sets) these products can be rapidly
programmed to any customized pattern. Extra test words
are pre-programmed during manufacturing to insure
extremely high field programming yields, and produce
excellent parametric correlation.

A2
Al
Ao

CS I
cS2

Platinum-Silicide was selected as the fuse link material
to achieve a well controlled melt rate resulting in large
non-conductive gaps that ensure very stable long-term
reliability. Extensive operating testing has proven that this
low-field, large-gap technology offers the best reliability for
fusible link PROMs.

CONNECTION DIAGRAMS - Top Views
DIP

Common design features include active loading of all critical
AC paths regulated by a built-in temperature and voltage
compensated bias network to provide excellent parametric
performance over MIL supply and temperature ranges.
Selective feedback techniques have been employed to
minimize delays through all critical paths.

Chip-Pak™
L-32-2
~

or

l;l

~

0

z

~

Vee
Aa
A,
A10

As

As

"-

A,.

A,

These PROMs are manufactured using Advanced Micro
Oevices' selective oxidation process, IMOX™. This
advanced process combined with a merged fuse array
permits an increase in density and a decrease in internal
capacitance resulting in the fastest possible PROMs.

CS1
A"

CS,

0,

CS,

A2
A,

An

Au

cs,

NC

Ne

0,
Os
O.

0,

0.

0,

0,

o.

8

8

l;l

BPM-266

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

2-137

0'
BPM-267

Note: Pin 1 is marked for orientation_
IMOX is a trademark of Advanced Micro Devices, Inc.

0

Am27S43A/S43
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 20 to Pin 10) Continuous

- 0.5 to + 7.0V

DC Voltage Applied to Outputs (Except During Programming)

-0.5V to + VCC max

21V

DC Voltage Applied to Outputs During Programming
Output Current into Outputs During Programming (Max Duration of 1 sec)

250mA

DC Input Voltage

-0.5to +5.5V

DC Input Current

-30to +5mA

OPERATING RANGE

Vee

Temperature

LOGIC SYMBOL

4.75 to 5.25V
4.5 to 5.5V

Te = -55to +125°C
8

7

6

5

4

CS1

3

2

1 23 22 21 19

32K
PROM
4096 x 8

9

10

11

13

14

15

16

17

Vee = Pin 24
GND = Pin 12

BPM-268

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
ADVANCED INFORMATION
Typ
Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

Vee = MIN, IOH = -2.0mA
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN, 'IOL = 16mA
VIN = VIH or VIL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 2)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 2)

IlL

Input LOW Current

Vee = MAX, VIN = Oo45V

IIH

Input HIGH Current

Vee = MAX, VIN = Vee

Ise

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 3)

lee

Power Supply Current

All inputs = GND,
Vee = MAX

VI

Input Clamp Voltage

leEX

Output Leakage Current

CIN

Input Capacitance

COUT

Output Capacitance

Vee = MIN, liN
Vee = MAX
Vcs, = 204V
VIN = 2.0V @ f

Min

(Note 1)

Max

204

Volts
0.50

2.0

-40

0.8

Volts

-0.250

rnA

40

p.A

-100

rnA

I COM'L

135

185

I

135

185

MIL

= -18mA

I

-1.2

Vo= Vee

VOUT = 2.0V @ f = 1MHz (Note 4)

Volts
p.A

-40
5.0
8.0

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
3. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
4. These parameters are not 100% tested, but are periodically sampled.

2-138

rnA

40

I Vo = Oo4V
= 1MHz (Note 4)

Volts
Volts

-0.020

-15

Units

pF

Am27S43A/S43
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
ADVANCED INFORMATION
Typ

Max

5V25°C
Parameters
tAA

Address Access Time

tEA

Enable Access Time

tER

Enable Recovery Time

ACTestLoad
(See Notes 1 and 2)

COM'L

MIL

A

STD

A

STD

A

STD

Units

30

35

40

55

55

65

ns

20

20

30

35

35

40

ns

20

20

30

35

35

40

ns

Test Conditions

Description

Notes: 1. tAA is tested with switch S1 closed and CL = 30pF.
2. For three-state outputs, tEA is tested with CL = 30pF to the 1.5V level; S1 is open for high impedance to HIGH tests and closed for high
impedance to LOW tests. tER is tested with CL = 5pF. HIGH to high impedance tests are made with S1 open to an output voltage of VOH -0.5V;
LOW to high impedance tests are made with S1 closed to the VOL +0.5V level.

SWITCHING CHARACTERISTICS

"·,,,3
CS,• cS 2

3.0V
I.SV
OV

I

f-"j
f-'''-l
»[=::::: «@

f--tAA---j

XXX*

0 0-03

~

f

I

Note: Level on output while CS 1 is HIGH or CS2 is LOW is determined externally.

I.SV
OV

VO H
I.SV
VOL

BPM-269

KEY TO TIMING DIAGRAM

WAVEFORM

-----

-JJJJJ!

INPUTS
MUST BE
STEADY

--

OUTPUTS

WAVEFORM

WILL BE
STEADY

WILL BE
MAY CHANGE CHANGING
FRoM H TO L FROM H TO L

"

WILL BE
MAY CHANGE
CHANGING
FROM L TO H FROM
L TO H

INPUTS

OUTPUTS

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

ACTESTLOAD

VCC~~
51
RI
300n
OUTPUT

e't
2-139

R2
600n

--=

BPM-199

Am27S43A/S43
PROGRAMMING
the current drops to approximately 90mA. Current into the CS1
pin when it is raised to 15 volts is typically 1.5mA.

The entire Generic PROM Series is manufactured with a conductive Platinum-Silicide link at each bit location. The output of
the memory with the link in place is LOW. To program the
device, the fusible links are selectively opened.

The memories may become hot during programming due to the
large currents being passed. Programming cycles should not be
applied to one device more than 5 seconds to avoid heat damage. If this programming time is exceeded, all power to the chip
including VCC should be removed for a period of 5 seconds after
which programming may be resumed.

The fusible links are opened one at a time by passing current
through them from a 20 volt supply which is applied to one
memory output after the CS1 input is a logic HIGH. Current is
gated through the addressed fuse by raising the CS1 input from
a logic HIGH to 15 volts. After 50p.sec, the 20 volt supply is
removed, the chip is enabled, and the output level sensed to
determine if the link has opened. Most links will 9pen within
50p.sec. Occasionally a link will be stronger and require additional programming cycles. The recommended duration of additional programming periods is 5msec. If a link has not opened
after a total elapsed programming time of 400msec, further
programming of the device should not be attempted. Successive
links are programmed in the same manner until all desired bit
locations have been programmed to the HIGH level.

When all programming has been completed, the data content of
the memory should be verified by sequentially reading all words.
Occasionally this verification will show that an extra undesired
link has been fused. Should this occur, immediately check the
programming equipment to make sure that all device pins are
firmly contacting the programming socket, that the input Signal
levels exhibit sufficient noise margins, and that the programming
voltages are within the specified limits. All of these conditions
must be maintained during programming. AMD PROMs are
thoroughly tested to minimize unwanted fusing: fusing extra bits
is generally related to programming equipment problems.

Typical current into an output during programming will be
approximately 180mA until the fuse link is opened, after which

PROGRAMMING PARAMETERS
Min

Max

Units

Vccp

Vcc During Programming

5.0

5.5

Volts

VIHP

Input HIGH Level During Programming

2.4

5.5

Volts

VILP

Input LOW Level During Programming

0.0

0.45

Volts

VCS1P

CS1 Voltage During Programming

14.5

15.5

Volts

Vop

Output Voltage During Programming

19.5

20.5

Volts

VONP

Voltage on Outputs Not to be Programmed

'ONP

Current into Outputs Not to be Programmed

d(VOp)/dt

Rate of Output Voltage Change

d(VCS1)/dt

Parameters

Description

tp
Notes: 1.
2.
3.
4.

0

+ 0.3

Volts

20

mA

20

250

V/p.sec

Rate of CS1 Voltage Change

100

1000

V/p.sec

Programming Period - First Attempt

50

100

p'sec

Programming Period - Subsequent Attempts

5.0

15

msec

All delays between edges are specified from completion of the first edge to beginning of the second edge; i.e., not to the midpoints.
Delays t1, t2, t3 and t4 must be greater than 100ns; maximum delays of 1p.sec are recommended to minimize heating during programming.
During t y , a user defined period, the output being programmed is switched to the load R and read to determine if additional pulses are required.
Outputs not being programmed are connected to VONP through resistor R which provides output current limiting.

PROGRAMMING WAVEFORMS

ADDR

Vccp

ESS

--V
--Are

--1l"
I

OUTPUT _ _

I

V-~

SELECTED ADDRESS STABLE

~~: I ~ ~~"-y

PROGRAMMED

SIMPLIFIED PROGRAMMING DIAGRAM

~

VCCP

I

YIHP

AQ'Al1Q

cS2
VIHP~

r- : '

I~ ~ ~ ~=::
-1-1
PROGRAMMING CYCLE

CS1-

\!e~~

I -

·· ··
·
~.~· ·
-~vo,
•
•

I

I
I

I

YOH

-

~
~o-

4Kx8
PROM

'--

iii (Yop)

VONP

R .. 2000

YOL

VCS1P

n

-=1:

-=
BPM-270

BPM-200

2-140

Am27S43A/S43
PROM PROGRAMMING EQUIPMENT INFORMATION
The PROM Programming Equipment from the following manufacturers has been evaluated and approved by AMD:
Source and
location

Oatal/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 95603

Kontron Electronic, Inc.
630 Price Avenue
Redwood City, CA 94063

Oigelec, Inc.
7335 E. Acoma Or.
Scottsdale AZ 85260

Stag Systems, Inc.
528-5 Weddell Or.
Sunnyvale, CA 94086

Programmer
Model(s)

Model 5, 7, and 9
Systems 17, 19,29
and 100

M900, M900B, M910,
M920, and M980

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMOGeneric
Bipolar PROM
Personality
Module

909-1286-1 Rev W
919-1286-1 Rev H·

PM 9058

IMAMDGEN1

MOO 14

PM 102

FAM-12

PM 2000
Code 90

Am27S43A/43

715-1698-002

1M 4096 x 8-24-AMO

"Rev shown is minimum approved revision.

OBTAINING PROGRAMMED UNITS

Programmed devices may be purchased from your distributor
or Advanced Micro Devices. The program data should be
submitted in the form of a punched paper tape and must be
accompanied by a written truth table. The punched tape can be
delivered with your order or may be transmitted over a TWX
machine or a time-sharing terminal. ASCII BPNF is our preferred paper tape format.

Truth tables are also acceptable, but are much less desirable
especially for larger density PROMs. Submission of a truth
table requires the generation of a punched paper tape at the
distributor or factory resulting in longer lead times, greater
possibility of error and higher cost.

ORDERING INFORMATION
Speed
Selection

Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

40ns

AM27S43APC
AM27S43APC8
AM27S43ADC
AM27S43ADC8
AM27S43ALC
AM27S43ALC8

P-24-1AC
P-24-1AC
D-24-1AC
D-24-1AC
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

55ns

AM27S43ADM
AM27S43ADM8
AM27S43ALM
AM27S43ALM8

D-24-1AC
D-24-1AC
L-32-2
L-32-2

C-3
8-3
C-3
8-3

MIL

55ns

AM27S43PC
AM27S43PC8
AM27S43DC
AM27S43DC8
AM27S43LC
AM27S43LC8

P-24-1AC
P-24-1AC
D-24-1AC
D-24-1AC.
L-32-2
L-32-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

65ns

AM27S43DM
AM27S43DM8
AM27S43LM
AM27S43LM8

D-24-1AC
D-24-1AC
L-32-2
L-32-2

C-3
8-3
C-3
8-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak. Numberfol!owing letter is
number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications.
Pad layout and bonding diagram available upon request.
Flat packages are available upon special request. Consult factory.

2-141

Technical Report
Reliability Report
Bipolar Generic PROM Series
ABSTRACT
This report is a review of the manufacturing process, the circuit design techniques, the
testing, the fuse element, and the reliability of Advanced Micro Devices' Generic Bipolar
PROM Series. Results indicate that platinum silicide forms a fuse with excellent reliability
characteristics.

The purpose of this report is to present a description of
Advanced Micro Devices' Bipolar PROM circuits, their
manufacturing process and their reliability. Included is a discussion of the wafer fabrication in which an advanced, highly
reliable platinum silicide fuse is utilized, a description of the
circuits and their testing, an analysis of the fusing characteristics of platinum silicide and supportive reliability data.
The products evaluated in this report are members of a
generic family of field programmable-read-only memories
(PROMs) from 256 bits through 16384 bits. Advanced Micro
Devices utilizes two manufacturing processes. The first is the
platinum-silicide Schottky, washed emitter process described. in this report. The second is the IMOXTIol process.
IMOX is the trademark name for a selective oxide isolation
process which employs ion-implantation of various transistor
elements. This improved process incorporates many of the
technologies previously developed, such as platinum silicide
fuses, dual layer metal, and platinum-silicide Schottkies.
IMOX allows further reduction in chip size due to tighter device spacings and device dimensions. All new product developments for the PROM family use the IMOX process. This
high density process allows Advanced Micro Devices to con-

tinue to supply very high speed, high performance products
while increasing device complexity. The circuit design concepts are similar on each of the PROMs with the result that
the products can be programmed using the same hardware.
Only the socket adaptor required for the PROM configuration
and pin count is different. The same programming algorithm
is used for all devices with completely satisfactory results.
The PROMs utilize a platinum Schottky diode structure with
barrier metal. Dual-layer metallization is also employed to
maximize speed and minimize chip size. All Advanced Micro
Devices' circuits receive screening per MIL-STD-883,
Method 5004 class C or better. Part of the 883 flow involves
sample acceptance tests in which all temperature requirements are sampled to Lot Tolerance Percent Defective
(LTPD) plans. A 5% LTPD corresponds to about a 0.65%
Acceptance Quality Level (AQL). In early 1981 Advanced
Micro Devices announced a new program that guarantees
the highest quality levels for semiconductor devices in the industry. The new program is called INTERNATIONAL STANDARD 123. Under INT-STD-123 all Bipolar Memory PROMs
are sampled to a 0.3% AQL. This is a direct statement of
AMD's commitment to excellence.

Prepared by: Advanced Micro Devices Quality and Reliability Department in Conjunction
with Bipolar Memory Engineering.

Advanced Micro Devices cannot assume responsibility for use of any circuitry described other than circuitry entirely
embodied in an Advanced Micro Devices' product.
'MOX is a trademark of Advanced Micro Devices, Inc.

2-142

Technical Report

THE PROCESS TECHNOLOGY

eration allows platinum silicide to form. The residual platinum is
etched off the wafer leaving the silicide contacts, Schottkies,
and fuses. After this step, the semiconductor elements of the
circuit have been completely formed, and all that remains is the
interconnect metallization.

Advanced Micro Devices has chosen a platinum silicide
Schottky, washed emitter, dual-layer metal process for its
bipolar PROMs. Platinum silicide has been chosen as the
material to form the fuse for several reasons. First, it has been
demonstrated to be an extremely reliable fuse material. It does
not have the growback phenomenon common to nichrome
technologies; it is not moisture sensitive in freeze-out tests; it is
less fragile than nichrome, and it does not have mass transport
problems associated with moderate current densities. Second,
the manufacturing process is easily controlled with regard to
reliability factors and fusing currents. Third, the fuses are quite
easy to form during the manufacturing process without a substantial number of additional processing steps.

To form the interconnects, aluminum is used as the primary
conducting element. Aluminum has a very strong affinity for
silicon, including that in platinum silicide. To retain the advantages of the very stable platinum silicide Schottky devices, it is
necessary to sputter an inactive metal, tungsten, with a small
amount of titanium as a bonding agent over the surface of the
wafers to serve as a barrier to the diffusion or microalloying of
the aluminum. Aluminum is now evaporated over the surface of
the wafers and conventional masking and etching cycles are
used to define the aluminum interconnections. Figure 3 shows
the structure of this metal layer.

Figure 2 is a cross section of a transistor and a fuse. A heavily
doped buried layer diffusion is first performed to allow for the
fabrication of NPN transistors with low saturation resistances. A
thin epitaxial layer is grown followed by isolation and base diffusions. The isolation and base are effectively self-aligned
using a composite masking approach. A short series of steps
results in the definition of polycrystalline silicon in the shape of
the fuse.

To complete the dual-layer metallization structure, silicon
dioxide is chemically vapor deposited on the wafer and etched
with interlayer metal contact openings (vias). A second layer of
aluminum is then placed on top of the dielectric. This layer has
a thickness substantially greater than the first one and is especially suited for power busses and output lines.

A second composite mask now defines all the emitter, contact,
Schottky diode and ohmic contact areas.
Following the emitter diffusion and the contact mask, platinum
is sputtered over the entire wafer. Since all contacts,
Schottkies, and fuses are exposed at this pOint, an alloying op-

To complete the circuit, a passivation layer is deposited over
the top of the wafers and etched at the appropriate locations to
allow for bonding pad contact.
EMITTER
DIFFUSION

PLATINUM SILICIDE
FUSE

p+
ISOLATION
N·EPITAXIAL LAYER
N+ BURIED LAYER
SUBSTRATE

BPM·121

Figure 2. Transistor & Fuse Structures.

----

TOPSIDE PASSIVATION

---------------------------------

PLATINUM SILICIDE FUSE
SILICON WAFER

BPM·122

Figure 3. 2 Layer Metallization Structure.

2-143

fa

Technical Report

The sense amplifier is a proprietary fast level shifter-inverter
with temperature and voltage threshold sensitivities compensated for the driving circuitry. Each of the four sense amplifiers
in this circuit provides active drive to an output buffer.

PROGRAMMABLE READ-ONLY
MEMORY CIRCUITRY
Advanced Micro Devices' bipolar PROM designs have the
general configuration shown in Figure 4. Although the figure is
for that of the Am27S20, the circuit techniques are the same for
the entire generic family of PROMs.

Each output buffer also contains a disable input, which is
driven from the chip-enable buffer. The chip-enable buffer input
is a Schottky diode clamped PNP buffered design with an active pull up and pull down to drive the output buffer. Additionally, the chip-enable gate contains circuitry to provide fuse
control as described below.

Input, Memory & Output Circuitry
Two groups of input buffers and decoders called "X" and "Y" are
used to drive word lines and columns respectively. The X-decode
addresses (A3 -A7 ) have Schottky clamp diode protected, PNP
inputs for minimum loading. (Figure 5). The X-input buffers
(A3 -A7) p'rovide A and A outputs toa Schottky decode matrix
which selects one of 64 word drivers. The word line drivers are
very fast high current, high voltage, non-saturating buffers providing voltage pull down to the selected word line.

Fusing Circuitry
Platinum silicide fuses as implemented in Advanced Micro Devices' PROMs have extremely high fuse current to sense current ratios. Sensing normally requires that only a few hundred
microamps flow through the fuse, whereas absolute minimum
requirements for opening the fuse are approximately 100 times
that amount. This provides a significant safety margin for
transient protection and long-term reliability.

The Y-decode address buffers (Ao-A2) are also Schottky diode
clamped, PNP inputs driving a Schottky diode matrix. However,
this diode matrix selects one of eight columns on each of the
four output bits. The selected column line drives the sense
amplifier input to a high level in the case of a blown fuse, or
current is shunted through an unblown fuse through the selected word driver to ground resulting in a "low" input to the
sense amplifier.

High-yield fusing of platinum silicide fuses requires that a substantial current be delivered to each fuse. This current is
sourced from the output terminals through darlingtons which
can drive the column lines when enabled. These darlingtons
are driven directly from the output and are selected by the Ydecode column select circuitry. Current during fusing flows
from the output through the darlington directly to the fuse
OUTPUTS

DO

AO
A1

COLUMN
DECODE

SENSE
AMPLIFIER
& FUSE
CIRCUITRY

•

•

•

SENSE
AMPLIFIER
& FUSE
CIRCUITRY

A2

----------C/l

!;
II.

CE

:!:

A3
A4
As

ROW
DECODE

A6
A7

BPM-123

Figure 4. PROM Circuitry Block Diagram.

2-144

Technical Report

Vee

PNP FOR
LOW IlL

APP"E"~
SCHOTIKY CLAMP
FOR TRANSIENT CLAMPING

BPM-124

Figure 5. Input Buffer Schematic.

through the selected array Schottky and finally through the
word-driver output transistor to ground. This path is designed
for a very large fusing current safety margin.
The control circuitry works as follows: After Vee is applied, the
appropriate address is selected and the CE input is taken to a
logic high, the programmer applies 20 volts to the bit output to
be programmed_ The application of the 20 volts simultaneously
deselects the output buffer to prevent destructive current flow,
and powers down internal circuitry unneeded during fusing to
minimize chip heating_

It also enables the darlington base drive circuitry, makes power
available to the darlington from the output and enables the
fusing control circuitry. At this point, the PROM is ready for the
control line at the chip-select pin to release the selected word
driver to allow current flow through the fuse_ This technique is
particularly advantageous because the control signal does not

supply the large fusing currents. They are supplied through the
darlington from the output power supply. Some care must be
taken to avoid excessive line inductance on the output line.
Reasonable and normal amounts of care will reward the user
with high-programming yields.

Special Test Circuitry
All Advanced Micro Devices PROMs include high-threshold
voltage gates paralleling several address lines to allow the
selection of special test words and the deselection of the columns to allow for more complete testing of the devices. Additionally, special test pads accessible prior to assembly allow
for testing of some key attributes of the devices_ The function of
these special circuits will be described in more detail in the
section, "Testing", later in this report.

2-145

Technical Report
blow it, a near DC condition may be safely applied to it with no
danger of developing a reliability problem such as that which
occurs with nichrome fuses. This will be discussed in more
detail later. The algorithm can therefore be designed first to
minimize the time required to program the PROM, i.e. with a
fast first pulse, and second, to maximize the probability that
any circuit will program. Most PROMs do, of course, fuse
satisfactorily with all short pulses. However, it is impossible for
any manufacturer to guarantee absolutely that all fuses in all
circuits receive 100 percent of the rated fusing current during
programming.

THE PLATINUM SILICIDE FUSE
Fusing Technique
Advanced Micro Devices' PROM circuits have been designed
to use a programming algorithm which minimizes the requirements on the programmer yet allows the circuit to fuse the
platinum silicide links quickly and reliably. Specifically, the following sequence of events must take place:
1.
2.
3.
4.
5.

Vee power is applied to the chip;
The appropriate address is selected;
The chip is deselected;
The programming voltage is applied to one output;
The chip enable voltage is raised to enable high-threshold
voltage gate. This action gates the current flow through the
proper fuse resulting in an open fuse in a few microseconds;
6. The output voltage is lowered; the programming voltage is
removed.
7. The device is enabled and the bit is sensed to verify that the
fuse is blown. In the unusual event that the fuse does not
verify as blown, a sequence of much longer pulses is
applied to the fuse at a high duty cycle until the fuse opens;
and,
8. The sequence of 2 through 7 is repeated for each bit which
must be fused.

Circuit defects which may be resistant to pre-programming
testing prevent such a guarantee. It is, therefore, quite important to have a fuse material insensitive to marginal conditions.
Even the application of single, short pulses does not guarantee
that no fuse received marginal amounts of current during fusing. The silicide fuse provides this safety margin and allows the
programmer to maximize the possibility of fusing by applying
near DC condition to the fuses.

Fuse Characteristics

The second major advantage of this technique is that in the
event that the fuse does not open during the first attempt to

When a fast (less than 500ns rise time) current pulse is applied
to a fuse, the fuse voltage rises abruptly to a value approaching
the level anticipated from calculations of the room temperature
resistance. However, it quickly falls to a value of approximately
two volts. This value is nearly independent of the applied current. During this period of time, typically, the fuse is molten.
Very abruptly, the fuse current drops to zero indicating the
separation of the platinum silicide into two distinct sections.
Scanning Electron Microscope photographs of the resulting
fuses (see Figure 6) indicate that the typical case is a sharp,
clean separation in excess of a micron. This separation occurs
in the center of the fuse because the bow-tie structure (see
Figure 7) concentrates the energy density in the center away
from the aluminum lines. The energy density in the center of
the fuse is capable of creating temperatures substantially
greater than required to melt the silicide. The very abrupt, high

Unprogrammed Fuse

Programmed Fuse

There are several advantages to this technique. First, the two
high current power sources, Vee and the voltage applied to the
output do not have critical timing requirements. The low current
chip select pin gates the fusing current into the circuit. Since it
is generally desirable to gate the fusing current into the chip at
relatively fast rates, the use of the chip select for this purpose
avoids the speed trade-off which would exist using the output
voltage as the control. The output voltage must not be raised
too quickly to avoid breakdown and latchback conditions which
might occur with sUb-microsecond rise times on the. output.

Figure 6.

2-146

Technical Report
power applied to the fuse melts the fuse center and results in a
wicking of material on either side due to surface tension.

Reliability of Fuses Programmed Under
Non-optimal Conditions
The. marginally opened fuse has been studied in some detail
even though it rarely occurs in practice. Under conditions
where the fuse is purposely blown at much slower rates, it is
possible for the fuse to assume a high impedance state which
is sensed as an open fuse by the circuit. This occurs because
the fuse cools before separation is achieved. Electrical and
SEM studies of fuses blown with these characteristics indicate
that a small conductive path of silicon remains of sufficiently
high resistance to prevent appropriate power transfer required
for complete opening on subsequent applications of power.
Under these slow-blow conditions, the thermal conductivity of
the silicon nitride pedestal on which the fuse rests, the silicon
dioxode beneath that, and the silicon chip become factors because sufficient time exists for the heat flow to carry a significant amount of energy away from the fuse. This is extremely
unusual in practice since it requires a rather narrow set of conditions. However, a number of PROMs have been specially
programmed under these unusual conditions which can cause
this type of fuse to occur. These devices have been life tested
for over two thousand hours. No failures occurred in any of
these circuits. It is clear from this study that partially opened
platinum silicide fuses are stable. Although it is very rare to see
such a fuse in a circuit which has been programmed under
normal conditions, Advanced Micro Devices believes that such
fuses do not represent a reliability hazard based on this study
and the results of the other studies run on the programmable-

2-147

read-only memories. It should be noted that most manufacturers carefully specify the conditions under which their devices
must be programmed in order to avoid reliability problems. Reliability data available on these devices must be assumed to
have been generated using optimally programmed devices.
Advanced Micro Devices believes that the study described
here and four billion fuse hours of data from many production lots
of PROMs demonstrate the capability of the platinum slicide
fuse under a wide variety of conditions.

ALUMINUM

ALUMINUM

CONTACT
AREA

CONTACT
AREA

"

/

COOLER REGIONS HERE
RESULT IN CORRECT
SURFACE TENSION FORCES
FOR PULLBACK OF FUSE
MATERIAL FROM CENTER GAP

BPM·125

Figure 7. Bowtie Fuse Design.

Technical Report

FINAL TESTING OF ADVANCED
MICRO DEVICES' MEMORIES
Wafer Level Tests
In addition to all the standard DC tests, Advanced Micro Devices
performs a series of special tests to conform to the screening
criteria of MIL-STD-883, Method 5004 3.3 and the 0.3% AQL
INT-STO-123. Also, AMD performs special tests to increase the
confidence level of unique address selection and to demonstrate
fusing capability on all columns and word drivers. To accomplish
this, diodes are connected from the column lines and the word
lines to special test pads which are accessible only during wafer
probing. (See Figure 4). Using these diodes, Advanced Micro
Devices confirms that each word driver is capable of sinking
sufficient current to blow fuses, has appropriate saturation
characteristics for AC performance, and has sufficient voltage
breakdown to withstand fusing voltages. In addition, using special software, a sequence of tests dramatically increases the
confidence of unique address selection on the address decoding. All darlingtons are checked to confirm that sufficient current
drive is available to blow fuses from any column. Schottky diode
array leakage is also checked to affirm that it is sufficiently low
so as not to overload the pull down circuitry during the highvoltage application of fusing. Finally, high voltages are applied to
the inputs and outputs to remove potentially weak devices before the PROM's are assembled.

relatable measures of the access times that the user can expect from his devices after he has placed his own program in
the memory. These test words are not visible to the user unless
he applies special voltages to certain address pins. Figure 8 is
a diagram of this input circuit. One hundred percent of the
PROM devices shipped from Advanced Micro Devices have
had AC testing for access and enable times at high-and lowpower supply voltages to affirm their AC characteristics.
The result of this extensive testing at both the wafer and
finished device level is a product with very high-programming
yields and virtually guaranteed AC performance after the user
places his program in the parts. Additionally, the high voltage
tests provide an additional level of confidence that the oxide
and junction integrity is excellent in each circuit and that the
devices will be relatively insensitive to small transients common
to programming equipment.

TO DECODE

ARRAY

Test Fusing
Each PROM has two additional word drivers connected to special test fuses. These test words are valuable in demonstrating
beyond reasonable doubt that the device is capable of opening
fuses in all columns. They also increase the confidence level in
unique addressing. Furthermore, the test words serve as cor-

BPM·126

Figure 8. Special Input Circuit Used for Array
Oeselection and Test Word Check.

THE MANUFACTURING PROCESS
All products bearing the Advanced Micro Devices' logo will have
screening meeting the requirements of the MIL-STD-883
Method 5004, for Class C microcircuits and INT-STD-123 Quality Levels. A summary of the standard processing is shown
below. The presence of the Advanced Micro Devices' logo on

the package is confirmation that the screening has been completed. The only exceptions to this procedure are special products revised by contract for a customer's lesser requirements
and distinctly marked for that customer alone. Standard burn-in
option B is available on standard product which allows the
customer to upgrade to Class B microcircuits.

Assembly and Environmental Standard
Processing
1. Die Visual Inspection
2. Wire Bond

3.
4.
5.
6.
7.
8.
9.
10.

Internal Visual
Seal
High Temperature Storage
Temperature Cycle
Constant Acceleration
Visual Inspection
Fine Leak
Gross Leak

Electrical Test through Shipping Standard
Processing

Method 2010 Condition B
Method 2010 Condition B
rebonds less than 10 percent
Method 2010 Condition B

1. Initial Electrical Test
2.

Method 1008 Condition C
Method 1010 Condition C
Method 2001 Condition E
Method 5004
Method 1014 Condition A or B
Method 1014 Condition C
Step 2

3.

4.
5.

Method 5004 to device
specifications.
INT-STD-123
Group A Electrical
quality levels.
Mark
Per customer order or
Advanced Micro Devices
catalog identification.
External Visual
Method 2009
Sample Quality Inspection Physical or electrical
verification of product identity.

Note: Steps 7-10 not required for solid packages.

2-148

Technical Report

RELIABILITY TESTING

Advanced Micro Devices selects samples of its product stratified
by product type at periodic intervals for this testing. Figure 10 is
a tabulation of the results of the lots placed on test during this
period of time. The data demonstrates a highly reliable process.
The fuse has an immeasurably low contribution to the failure
rate at this point in the reliability testing.

Advanced Micro Devices .has an ongoing reliability program to
evaluate its bipolar memory products. Reliability testing conforms to MIL-STD-883 Method 1005 Conditions C or D. Examples of the test circuits used are shown in Figure 9. Data has.
now been accumulated on the process described here in excess of ten thousand hours on some devices. Over forty billion
fuse hours have been completed with no fuse oriented failures.
Vee

300n

1Kn

As

A7

A4

CS 2
CS 1

A3

A1
Ao

300n

300n

Vee

A6

A2

300n

14
13
12

AM27S20 0 0
11
01
10
O2

-=

03

GND

Condition C - Static

BPM-127

Vee

1Kn

IF'

100kHz

J

1
CP
00

CET
eEP

PE

6

01

r--

O2

r--

03

r--

AM9316

MR

5

r-7

4

AO
A1
A2
Vee

A3

TC

I

16
5

I
00

~

eEP

PE

01
AM9316
O2

MR

03

3

r-2

r-1

r--15
r---

A4

A3

As
A6

As

A7

L....-

eET
eEP

J

14
13

PE
MR

AM9316

00

r--

o

13

1

02

r--

01

300n

11

AM27S20
O2

A6

10

A7
03

CS2
CS 1

1
'----

300n

A4

Te

14

00

300n

12

A2

15

CP

300n

Vee

A1

CP
CET

Ao

GND

CS2
CS1

X

r--

03~
Condition 0 - Dynamic
BPM-126

FiIJure 9. Burn-In Circuits For Conditions C & 0-27520.

2-149

Technical Report

BIPOLAR MEMORY RELIABILITY SUMMARY

Product

Production
Lots

Units
Tested

Total
Unit Hours
(thousands)

Total
Fuse Hours
(billions)

Unit
Failures

Fuse
Related
Failures

Unit Failure
Rate@60%
Confidence
%/1000 hrs
at 125°C

Unit Failure
Rate"@60%
Confidence
%/1000hrs
at 70°C

0

0

0.10

0.0010

27518/19
(256 bit PROM)

5

491

982

.2518

27520/21
(1K bit PROM)

16

1321

2207

2.2608

2··

0

0.01

0.0001

27512/13
(2K bit PROM)

11

571

1840

3.7688

0

0

0.05

0.0005

27515
27527
27528/29
27532/33
(4K bit PROM)

24

1870

1408

5.7678

0

0

0.07

0.0007

275180/181
(8K bit PROM)

12

463

926

7.5868

0

0

0.11

0.0010

275184/185
IMOX
(8K bit PROM)

15

556

1112

9.1098

0

0

0.09

0.0008

275190/191
IMOX
(16K bit PROM)

2

69

795

13.0258

0

0

0.12

0.0011

Totals for
PROM products

85

5341

9270

41.7668

2··

0

0.02

0.0002

·Assuming on activation energy of 1.0 eV.
··Oxide failure.

Figure 10.

SUMMARY
The Advanced Micro Devices' bipolar memory process has
been described with particular emphasis on programmableread-only memories. An advanced form of the low-power
Schottky process is used in conjunction with a highly reliable

and stable platinum silicide fuse. Extensive testing and
screening have been used to assure that the products will meet
all specification after the user has placed his program into the
device and that the circuit reliability will be outstanding.

2-150

Guide to the Analysis
of Programming Problems
Advanced Micro Devices
Bi polar Memory
Product Engineering
INTRODUCTION
Advanced Micro Devices' Generic Series of Programmable
Read Only Memory (PROM) circuits have been designed to provide extremely high programming yields. Available programming
currents are over designed by a factor of four and special circuitry accessible only during testing is incorporated into each
product to eliminate ordinarily difficult to detect shorts and opens
in the array and decoders. As a result, unique decoding and very
large fusing currents are virtually assured to the user. AMD
PROMs have test fuses programmed prior to shipment as a
further guarantee. The results of such extensive testing and design considerations are programming yields consistently in the
98% to 99.5% range.

2-151

Key to the achievement of such yields is a programmer properly
calibrated to the AMD specification with good contactors,
"clean" electrical wave forms and properly functioning subcircuits. In the event that your programming yields fall below 98%,
you should investigate the characteristics of the failed devices to
find a prominent failure mode, then use the attached information
as a guide to resolving the problem. Simple problems can be
very costly if not detected and corrected.
Should you continue to have trouble optimizing your programming yield, contact your AMD representative or local programmer manufacturer representative.

Guide to the Analysis of Programming Problems

Primary Symptom

Secondary Symptom

I) Units fail to program
all desired bits

A) Binary blocks of
missing data

Possible Causes
1) Address driver output which remains continuously low or
continuously high.
2) Address driver with a "low" voltage greater than O.5V or a "high" voltage less
than 2.4V.
3) Poor, intermittent or no electrical contact to one or more address input pins.
Any of the above may result in over programming half the array and not programming
the other half.

B) Random bits of
missing data

1) Address driver with a "low" voltage greater than O.5V or a "high" voltage less
than2.4V.
2) Poor electrical contact to aooress, chip enable and output pins.
3) Excessive transient noise on Vee, output pin (> 20.5V), or ground pins. Check
with a high speed storage oscilloscope for peak values during programming.
Use transient suppression networks where appropriate.
4) Programmer does not comply with AMD Programming Specification.
(See Programming Parameters.)
Examples:
-

C) All data associated with
a single output missing
D) No data change

Output voltage during programming less than 19.5V
during programming less than 5.0V
CS voltage during programming less than 14.5V

~

1) Poor or no electrical contact to that output pin.
2) Defective current switch in programmer.
1) Wrong device or programming socket.
2) Programmer does not comply with AMD's Programming Specifications.
(See Programming Parameters.)
Examples: -

II) Over-Programmed
Devices

A) One output continuously
at a Logic "1"

Output voltage during programming less than 19.5V
~e during programming less than 5.0V

CS voltage during programming less than 14.5V

1) Programmer does not comply with AMD's Programming Specifications.
(See Programming Parameters.)
Examples: -

Output voltage during programming greater than 20.5V
Programmer timing incorrect

2) Open outputs can appear to be programmed to Logic "1" with the presence of a
pullup resistor even though the device has not actually been programmed.
3) Excessive voltage transients on output lines during programming. Be sure
appropriate transient suppression networks are placed on the outputs.
(See Figure 1.)
B) All outputs continuously
at a Logic "1"

1) No Vee applied to device.
2) No ground applied to device.
3) Incorrect device type.
4) Incorrect programming socket.
5) Excessive voltage transients on output lines. Use transient suppression network
shown in Figure 1.

2-152

Guide to the Analysis of Programming Problems

Over Programmed

DEFINITIONS

-

Fuse
-

Conductive Platinum-Silicide link used as a memory element
in Advanced Micro Devices' PROM circuits.

Address Driver
The voltage source which drives an individual address pin in
the PROM. This source is part of the programmer and drives
the address pin with "O"s (0 to .45V) and "1"s (2.4 to 5.5V)
depending on instructions from the programmer control
circuitry. There is a separate address driver for every PROM
address pin.

Unprogrammed Bit
-

A conductive fuse.

Programmed Bit
-

A nonconductive fuse, that is one which has been opened.

Output Low (Logic "0")
-

Programmer

An output condition created by an unprogrammed bit.

A system capable of providing the appropriate array of
signals to a PROM circuit to cause certain user controlled bits
to be programmed (Le., fuses opened) in the device. As a
minimum it consists of a memory containing the pattern to be
programmed, control circuitry to sequence the addressing
and fusing control pulses, power supplies, and address
drivers.

Output High (Logic "1")
-

A device failure in which a fuse which was not selected to
open nevertheless opened during the fusing operation.

An output condition created by a programmed bit.

Failure to Program
A device failure in which a fuse selected to be opened failed
to open during the fusing operation.

TRANSIENT SUPPRESSION NETWORK

l ...

(

TO OUTPUTS

....~,
'-

1N4148 OR EQUIVALENT

~

' ] r1N4746A OR EQUIVALENT

.01p.F//.1p.F

j

Notes: 1. Clamp diodes should be connected to each output as close as physically possible to the device pin.
2. Vee should be decoupled at the device pin using .01/LFII.1/LF capacitors.
3. AMD recommends that all address pins be decoupled using .001/LF capacitors.

Figure 1.

2-153

PROM Programming Equipment Guide
Source and
Location

Data I/O
10525 Willows Rd. N.E.
Redmond, WA 98052

Pro-Log Corporation
2411 Garden Road
Monterey, CA 93940

International
Microsystems, Inc.
11554 C. Avenue
Auburn, CA 93940

Kontron Electronic, Inc.
630 Price Avenue
Redwood City, CA
94063

Digelec, Inc.
7335 E. Acoma Dr.
Scottsdale, AZ
85260

Stag Systems, Inc.
528-5 Weddell Dr.
Sunnyvale, CA
94086

Programmer
Model(s)

Model 5, 7 and 9
Systems 17,19,29
and 100

M900, M900B, M910,
M920 and M980

IM1010

MPP-80

UPP-801

UPP-803

PPX

AMDGeneric
Bipolar PROM
Personality
Module

909-1286-1
919-1286-1
RevH

PM 9058

IMAMDGEN1

MOD 14

PM102

FAM-12

PM 2000
Code 90

16 02

PA 16-6 and 32 x 8(L)

1M 32 x 8-16-AMD

SA3-1 B32x8/16

DIS-156AM

DA22

AM 110-2

Unipak
Rev 003
(Family and
Pin Code)

Socket Adapters and Configurators
Am27S18/19
Am27LS18/19

715-1407-1

Am27S20/21

715-1408-1

1601

PA 16-5 and 256 x 4(L)

1M 256x4-16-AMD

SA4-2 B256x4/16

DIS-133AM

DA21

AM130-2

Am27S12113

715-1408-2

1603

PA 16-5 and 512 x 4(L)

1M 512 x 4-16-AMD

SA4-1 B512x4/16

DIS-134AM

DA21

AM 130-3

Am27S15

715-1411-1

PA 24-14 and
512x8(L)

1M 512 x 8-2427S15-AMD

SA 17-3 B 512 x 8/24

DIS-165AM

DA33

-

Am27S25

715-1617

PA24-16and
512x8(L)

1M 512 x 8-2427S25-AMD

SA31-2B512x8/24

DIS-213AM

DA31

AM 190-2

PA 22-4 and 512 x 8(L)

1M 512 x 8-2227S27-AMD

SA 18 B 512 x 8/22

DIS-168AM

DA28

AM 120-3

62 65

-

Am27S27

715-1412-2

Am27S28/29

715-1413

1609

PA 20-4 and 512 x 8(L)

1M 512 x 8-20-AMD

SA6B512x8/20

DIS-158AM

DA34

Am27S30/31

715-1545

16 36

PA 24-13 and 512 x 8(L)

1M 512 x 8-24-AMD

SA 22-6 B 512 x 8/24

DIS-135AM

DA29

-

Am27S32133

715-1414

1638

PA 18-6 and 1024 x 4(L)

1M 1024x4-18-AMD

SA24B1024x4/18

DIS-136AM

DA38

AM 170-2

Am27S35
Am27S37

715-1723

62 66

PA 24-18 and
1025x8(L)

1M 1024 x 8-27S35/
37-AMD

SA31-1 B
1024 x 8/24

DIS-218AM

DA65

AM 190-3

Am27S180/181
Am27PS181

715-1545-2

1637

PA 24-13 and
1024x8(L)

1M 1024 x 8-24-AMD

SA22-7B
1024 x 8/24

DIS-137 AM

DA29

AM 100-6

DIS-214AM

DA60

-

Am27S2801281
Am27PS281

1637

Am27S184/185
Am27LS184/185 715-1616
Am27PS185

1606

PA 18-8and
2048x4(L)

1M 2048 x 4-18-AMD

SA4-4B
2048x4/18

DIS-211 AM

DA23

AM 140-3

Am27S190/191
Am27PS191

715-1688-1

1668

PA 24-17 and
2048x8(L)

1M 2048 x 8-24-AMD

SA22-10B
2048 x 8/24

DIS-151 AM

DA61

AM 100-5

Am27S290/291
Am27PS291

715-1688-2

1668

PA24-28 and
2048 x 8(L)

1M 2048 x 8-2427S290/291-AMD

SA 29 B 2048 x 8/24

DIS-215AM

DA62

AM 190-7

PA20-9and
4096 x 4(L)

1M 4096 x 4-20-AMD

SA 30 B 4096 x 4/20

DIS-216AM

DA63

AM 120-6

SA31 B
2048 x 8/24

-

DA64

AM 170-3

-

-

-

-

1M 1024 x 8-2427S280/281-AMD

Am27S40/41
Am27PS41

715-1282

-

Am27S45
Am27S47

715-1660

-

-

1M 2048 x 8-2427S45147-AMD

715-1698-002

-

-

1M 4096 x 8-24-AMD

Am27S43

2-154

-

-

7

Bipolar Random Access
Memories (RAM) Index
TTL
Am27S02A/03A Series
Am29702/Am29703
Am27lS02/03
Am3101-1/54/7489-1 Series
Am3101A/54S/74S289 Series
Am31l01A/31l01
Am27S06A/07 A Series
Am29700/Am2970 1
Am27lS06/07
Am27lS00A/01A Series
Am29720/Am29721
Am27lS00-1A/01-1A Series
Am93412A/422A Series
Am93l412A/l422A Series
Am93415A/425A Series

Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
Schottky 64- Bit RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
low-Power Schottky 64-Bit Bipolar RAM. . . . . . . . . . . . . . . . . . . . . . . .. 3-7
Schottky 64-Bit Write Transparent Bipolar RAM ................... 3-11
Schottky 64- Bit Bipolar RAM .................................... 3-16
64-Bit Write Transparent Bipolar RAM ............................ 3-21
Noninverting Schottky 64-Bit Bipolar RAM ........................ 3-26
Noninverting Schottky 64-Bit RAM ............................... 3-31
low-Power, Noninverting 64-Bit Bipolar RAM ..................... 3-32
low-Power Schottky 256-Bit Bipolar RAM .... : ................... 3-36
low- Power Schottky 256- Bit Random Access Memories ........... 3-41
Low-Power Schottky (Noninverting) 256-Bit Bipolar RAM .......... 3-42
TTL 1024-Bit Bipolar IMaX RAM ............................... 3-47
low-Power TTL 1024-Bit Bipolar IMaX RAM ..................... 3-52
TTL 1024-Bit Bipolar IMaX RAM .... : ......... : ................. 3-57

Eel
Am10415SA Series
Am100415A/415
Am10474SA Series
Am100474SA Series
Am10470SA Series
Am100470SA Series

Eel
Eel
Eel
Eel
Eel
Eel

1024
1024
1024
1024
4096
4096

x 1 IMaX
x 1 IMaX
x 4 IMaX
x 4 IMaX
x 1 IMaX
x 1 IMaX

Bipolar RAM ................................ 3-62
" Bipolar RAM .............................. 3-69
Bipolar RAM ................................ 3-74
Bipolar RAM ................................ 3-75
Bipolar RAM ................................ 3-76
Bipolar RAM ............... , ... , ............ 3-83

Am27S02A • Am27S03A
Am27S02 • Am27S03
Schottky 64·Bit Bipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 16-word x 4-bit Low-power
Schottky RAMs

The Am27S02/02A and Am27S03/03A are 64-bit RAMs
built using Schottky diode clamped transistors in conjunction with internal ECL circuitry and are ideal for use in
scratch pad and high-speed buffer memory applications.
Each memory is organized as a fully decoded 16-word
memory of 4 bits per word. Easy memory expansion is
provided by an active LOW chip select (CS) input and open
collector OR tieable outputs (Am27S02/02A) or three-state
outputs (Am27S03/03A). Chip selection for large memory
systems can be controlled by active LOW output decoders
such as the Am74S138.

• Ultra-Fast "A" Version: Address access time 25ns
• Standard Version: Address access time 35ns
• Low Power: ICC typically 75mA
• Internal ECL circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate write
recovery glitch
• Available with open collector outputs (Am27S02/02A) or
with three-state outputs (Am27S03/03A)

An active LOW Write line (WE) controls the writing/reading
operation of the memory. When the chip select and write
lines are LOW the information on the four data inputs Do to
D3 is written into the addressed memory word and preconditions the output circuitry so that correct data is present at
the outputs when the write cycle is complete. This precon~
ditioning operation insures minimum write recovery times
by eliminating the "write recovery glitch".

• Pin compatible replacements for 3101 A, 74S289, 93403,
6560 (use Am27S02N02); for 74S189, 6561, DM8599
(use Am27S03N03)
• 100% reliability assurance testing in compliance
with MIL-STD-883
• Guaranteed to INT-STD-123

Reading is performed with the chip select line LOW and the
write line HIGH. The information stored in the addressed
word is read out on the four inverting outputs 0'0 to 03'
During the writing operation or when the chip select line is
HIGH the four outputs of the memory go to an inactive higl)
impedance state.

LOGIC SYMBOL

LOGIC BLOCK DIAGRAM

CS

AO
15

Al

14

A2

13

A3

DO

0,

10

12

O2

03

WE

64-BIT RAM
16W x4B
°0

°1

°2

°3

ffff
11

Vee = Pin 16
GND = PinS

BPM-239

BPM-238

3-1

Am27S02A/S03A/S02/S03
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8)

-0.5to +7V

DC Voltage Applied to Outputs for High Output State

-0.5VtoVcC max

DC Input Voltage

-0.5to +5.5V

Output Current, Into Outputs

20mA

DC Input Current

- 30 to + 5.0mA

OPERATING RANGE

FUNCTION TABLE
Input

Ambient Temperature

Vce

CS

4.75 to 5.25V
4.5to5.5V

-55to +125°C

WE

Function

Data ~tp,!! Status
00- 0 3

Low

Low

Write

Output Disabled

Low

High

Read

Selected Word (Inverted)

High

Don't
Care

Deselect

Output Disabled

DC CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters
VOH (Note 2)

Description
Output HIGH Voltage

Test Conditions
Vee = MIN,
V,N = V,H or V,l
Vee = MIN,
V,N = V,H or V,l

IOH = -5.2mA
IOH = -2.0mA

ICOM'L
IMIL

Min

(Note 1)

2.4

3.2

Max

Volts

IOl = 16mA

0.350

0.45

IOl = 20mA

0.380

0.5

VOL

Output LOW Voltage

V,H

Input HIGH Level

Guaranteed Input Logical HIGH
Voltage for All Inputs (Note 3)

V,l

Input LOW Level

Guaranteed Input Logical LOW
Voltage for All Input (Note 3)

I,l

Input LOW Current

Vee = MAX,
V,N = 0.40V

Volts

Volts

2.0
0.8

WE, Do-D3, Ao-A3

-0.015

-0.25

CS

-0.030

-0.25

I'H

Input HIGH Current

Vee = MAX, V,N = 2.4V

Ise (Note 2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV (Note 4)

Icc

Power Supply Current

All inputs = GND
Vee = MAX

Vel

Input Clamp Voltage

leEX

Output Leakage Current

Units

Volts

mA

0.0

10

/LA

-45

-90

mA

COM'L

75

100

MIL

75

105

-0.850

-1.2

Volts

0

40

/LA

-20

mA

Vee = MIN, liN = -18mA
Vcs = V,H or ViNE = V,l
VOUT =2AV

Am27S02N03A
Am27S02/03

Vc§ = V,H or VWE = V,l
VOUT = OAV, Vee = MAX

(Note 2)

-40

0

Note 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester nOise. Do not attempt
to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.

3-2

/LA

Am27S02A/S03A/S02/S03
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions: See Figures 3 and 4 and Notes 3,4, and 5
Am27S02A· Am27S03A
Typ
Description

Parameters
tpLH(A)

(Note 1)

Am27S02· Am27S03

COM'L
MIL
Min Max Min Max

Typ
(Note 1)

COM'L
MIL
Min Max Min Max

Units

Delay from Address to Output

See Fig. 2

15

25

30

22

35

50

ns

Delay from Chip Select (LOW) to
Active Output and Correct Data

See Fig. 2

10

15

20

14

17

25

ns

Delay from Write Enable (HIGH)
to Active Output and Correct Data
(Write Recovery - See Note 2)

See Fig. 1

12

20

25

19

35

40

ns

ts(A)

Setup Time Address
(Prior to Initiation of Write)

See Fig. 1

-6.0

0

0

-6.0

0

0

ns

th(A)

. Hold Time Address
(After Termination of Write)

See Fig. 1

-2.5

0

0

-2.5

0

0

ns

tpHdA)
tpZH(CS)
tpzdCS)
tpZH(WE)
tpzdWE)

ts(DI)

Setup Time Data Input
(Prior to Termination of Write)

See Fig. 1

9.0

20

25

18

25

25

ns

th(DI)

Hold Time Data Input
(After Termination of Write)

See Fig. 1

-4.0

0

0

-4.0

0

0

ns

tpw(WE)

MIN Write Enable Pulse Width
to Insure Write

See Fig. 1

10

20

25

18

25

25

ns

Delay from Chip Select (HIGH)
to Inactive Output (HI-Z)

See Fig. 2

10

15

20

13

17

25

ns

Delay from Write Enable (LOW)
to Inactive Output (HI-Z)

See Fig. 1

12

20

25

15

25

35

ns

tPHZ(CS)
tpLZ(CS)
tPLZ(WE)
tPHZ(WE)

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. Output is preconditioned to data in (inverted) during write to insure correct data is present on all outputs when write is terminated.
(No write recovery glitch.)
3. tpLH(A) and tpHdA) are tested with S1 closed and CL = 30pF with both input and output timing referenced to 1.5V.
4. For open collector, all delays from Write Enable (WE) or Chip Select (CS) inputs to the Data Output (DOUT), tpLz(WE), tpLZ(CS)
tpzdWE) and tpzdCS) are measured with S1 closed and CL = 30pF; and with both the input and output timing referenced to 1.5V.
5. For 3-state output, tpZH(WE) and tpZH(CS) are measured with 81 open, CL = 30pF and with both the input and output timing referenced to
1.5V. tpzdWE) and tpzdC8) are measured with 81 closed, CL = 30pF and with both the input and output timing referenced to 1.5V.
tpHZ(WE) and tpHZ(C8) are measured with 81 open and CL ,,:; 5pF and are measured between the 1.5V level on the input to the VOH - 500mV
level on the output. tpLZ(WE) and tpLZ(C8) are measured with 81 closed and CL ,,:; 5pF and are measured between the 1.5V level on the
input and the VOL + 500mV level on the output.

CONNECTION DIAGRAMS
Top Views

Chip-PakTM

DIP

AO

Vee

cs

A,

WE

A2

DO

A3

0

°

D3

D,

°
°

0,
GND

3

D2

2

Note: Pin 1 is marked for orientation.

BPM-240

Chip-Pak IS a trademark of Advanced Micro Devices, Inc.

3-3

Am27S02A/S03A/S02/S03
SWITCHING WAVEFORMS
WRITE MODE

KEY TO TIMING DIAGRAM

ADD=~~~ --------FI--------------l~H-IHH-!H-If-HHH-Jf-f-

-

Ipw lWEI _

I,IAI_

'\\\H\,
\\\\\\

1.5V

r-t,IDIl

_I

I

IhID!)

DON'T CARE

0 0- 3

1.5 V

r-----t:PLZI~1
IpHZIWEI

WAVEFORM

INPUTS

OUTPUTS

--

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM HTO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILLBE
CHANGING
FROM L·TO H

DON'TCARE;
ANY CHANGE
PERMITIED

CHANGING;
STATE
UNKNOWN

1.5V

IhlAl

lIlIfJ

-lpZH~11
IpZLIWEI

\\H\\,

1111111111

111111

H\\\\\\\

---

BPM-241

H

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

Write Cycle Timing. The cycle is initiated by an address change. After ts(A) min, the write enable may begin. The chip select must also be LOW for
writing. Fo"owing the write pulse. th(A) min must be allowed before the address may be changed again. The output will be inactive (floating for the
Am27S03N03) while the write enable is (WE) LOW.

Figure 1

READ MODE
ADDRESS

"0-3

__

ADDRESS;

ADDRESSk

1.5V

ADDRESS I

----------'

~ -----~-----------------------------------T--------~--------~--------------~~---------------

OUTPUT
DISABLE

READ A HIGH
IN ADDRESS;

READ A LOW IN
ADORESSk

DISABLE
OUT~UT

ENABLE
OUTPUT

READAHIGH
IN ADDRESS I

1.5V

DISABLE
OUTPUT

Switching delays from address and chip select inputs to the data output. For the Am27S03N03 disabled output is "OFF.... represented by a
single center line. For the Am27S02N02, a disabled output is HIGH.

Figure 2

BPM-242

AC TEST LOAD AND WAVEFORM
INPUT PULSES

ACTESTLOAD

VCC~
Sl
3.0Vp-p---------It----------1.

R1
300n

GND -----'::.OUTPUT O---~r------'

R2
600n
GND------~~~~----~

BPM-054

Figure 3

Figure 4

3·4

BPM-055

Am27S02A/S03A/S02/S03
ORDERING INFORMATION

Order Code
Speed
Selection

Open
Collector

3-State

Package Type

Screening
Flow Code

Operating Range

(Note 1)

(Note 2)

(Note 3)

25ns

AM27S02APC
AM27S02APC8
AM27S02ADC
AM27S02ADC8
AM27S02ALC
AM27S02ALC8

AM27S03APC
AM27S03APC8
AM27S03AOC
AM27S03AOC8
AM27S03ALC
AM27S03ALC8

P-16-1
P-16-1
D-16-1
0-16-1
Consult Factory
Consult Factory

C-l
8-1
C-l
8-1
C-l
8-1

COM'L

30ns

AM27S02AOM
AM27S02ADM8
AM27S02AFM
AM27S02AFM8
AM27S02ALM
AM27S02ALM8

AM27S03AOM
AM27S03AOM8
AM27S03AFM
AM27S03AFM8
AM27S03ALM
AM27S03ALM8

0-16-1
0-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
8-3
C-3
8-3
C-3
8-3

MIL

35ns

AM27S02PC
AM27S02PC8
AM27S020C
AM27S020C8
AM27S02LC
AM27S02LC8

AM27S03PC
AM27S03PC8
AM27S030C
AM27S030C8
AM27S03LC
AM27S03LC8

P-16-1
P-16-1
0-16-1
D-16-1
Consult Factory
Consult Factory

C-l
8-1
C-l
8-1
C-l
8-1

COM'L

50ns

AM27S020M
AM27S02DM8
AM27S02FM
AM27S02FM8
AM27S02LM
AM27S02LM8

AM27S030M
AM27S030M8
AM27S03FM
AM27S03FM8
AM27S03LM
AM27S03LM8

0-16-1
0-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-l and C-3 conform to MIL-STO-883, Class C. Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See operating range table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding diagram available upon request.

3-5

Am29702 • Am29703
Schottky 64·Sit RAM

Refer to

Am27S02 • Am27S03
Bipolar Memory RAM Product Specification
The Am29702 is replaced by the Am27S02
(open collector).
The Am29703 is replaced by the Am27S03
(three-state).

3-6

Am27LS02 • Am27LS03
Low-Power Schottky 64-Bil Bipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 16-word x 4-bit Low-power
Schottky RAMs
• Ultra-low power: ICC typically 30mA
• High speed: Address access time typically 40ns
• Internal ECL circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate the write
recovery glitch
• Available with three-state outputs (Am27LS03) or with
open collector outputs (Am27LS02)
• Pin compatible replacements for DM74L89A,
DM74LS289, L6560, 7489 (use Am27LS02), for
DM86L99, DM74LS189, (use Am27LS03).
• 100% MIL-STD-883C assurance testing
• Electrically tested and optically inspected die for the
assemblers of hybrid products
• Guaranteed to INT-STD-123

The Am27LS02 and Am27LS03 are 64-bit RAMs built using
Schottky diode clamped transistors in conjunction with
internal ECL circuitry and are ideal for use in scratch pad
and high-speed buffer memory applications where power is
at a premium. Each memory is organized as a fully decoded
16-word memory of 4 bits per word. Easy memory expansion is provided by an active LOW chip select (CS) input
and open collector OR tieable outputs (Am27LS02) or
three-state outputs (Am27LS03). Chip selection for large
memory systems can be controlled by active LOW output
decoders such as the Am7 4LS 138.
An active LOW write line (WE) controls the writing/reading
operation of the memory. When the chip select and write
lines are LOW, the information on the four data inputs Do to
03 is written into the addressed memory word and preconditions the output circuitry so that correct data is present at
the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times
by eliminating the "write recovery glitch".

LOGIC BLOCK DIAGRAM

Reading is performed with the chip select line LOW and the
write line HIGH. The information stored in the addressed
word is read out on the four inverting outputs 00 to 03.
During the writing operation or when the chip select line is
HIGH the four outputs of the memory go to an inactive high
impedance state.

LOGIC SYMBOL

AO
15

cs

DO

AI

14

A2

13

A3

0,

10

12

O2

03

WE

64·BIT RAM
16W x 4B
°0

°1

°2

°3

IIII
11

Vee = Pin 16
GND = PinS

BPM·345

DIP

CONNECTION DIAGRAMS - Top Views

Note: Pin 1 is marked for orientation.

BPM·346

Chip-Pak™

BPM·347

Chip-Pak is a trademark of Advanced Micro Devices, Inc.
3-7

Am27LS02/LS03
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8)

-0.5 to +7V

DC Voltage Applied to Outputs for High Output State

-0.5V to VCC max

DC Input Voltage

-0.5 to +5.5V
20mA

Output Current, Into Outputs
DC Input Current

-30to +5.0mA

OPERATING RANGE
Ambient
Temperature

-55 to +125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ

DC
Test Conditions

Description

Parameters

= -5.2mA

IOH

= -2.0mA

ICOM'L
IMIL

Min

(Note 1)

204

3.6

Max

VOH
(Am27LS03 Output HIGH Voltage
only)

Vee = MIN,
VIN = VIH orVll

IOH

Output LOW Voltage

Vee = MIN,
VIN = VIH or Vil

IOl = 8.0mA

0.280

0045

IOl = 10mA

0.310

0.5

VOL

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 2)

Vil

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 2)

IlL

Input LOW Current

Vee = MAX,
VIN = Oo4OV

Input HIGH Current

IIH

Ise
(Am27LS03 Output Short Circuit Current
only)
Power Supply Current

lee
Vel

leEX

Input Clamp Voltage

Output Leakage Current

Units
Volts

2.0

Volts

Volts
0.8

Volts

WE, Do-D3, Ao-A3

-0.015

-0.250

CS

-0.030

-0.250

0

10

p.A

-45

-90

rnA

l COM'L

30

35

, MIL

30

38

-0.850

-1.2

Volts

0

40

p.A

Vee = MAX, VIN = 204V
-20

Vee = MAX, VOUT = O.OV

All inputs = GND
Vee = MAX
Vee = MIN, liN = -18mA
Vcs = VIH or ViNE = Vil
VOUT= 2AV

Am27LS02/03

Vcs = VIH or VWE == Vil
VOUT = OAV, Vee == MAX

Am27LS03

-40

0

rnA

rnA

p.A

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. These are absolute voltages with respect to device ground pin and include all overshoots and undershoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.

FUNCTION TABLE
Input
CS

WE

Function

Data Output
Status 00-3

Low

Low

Write

Output Disabled

Low

High

Read

Selected Word (Inverted)

High

Don't
Care

Deselect

Output Disabled

3-8

Am27LS02/LS03
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters
tpLH(A)

AC
Test Conditions

Description

Typ
(Note 1)

COM'L
Min
Max

MIL
Min

Max

Units

Delay from Address to Output

See Fig. 2

40

55

65

ns

Delay from Chip Select to Active
Output and Correct Data

See Fig. 2

18

30

35

ns

Delay from Write Enable (HIGH)
to Active Output and Correct Data
(Write Recovery - See Note 2)

See Fig. 1

18

30

35

ns

Setup Time Address (Prior to
Initiation of Write)

See Fig. 1

th(A)

Hold Time Address (After
Termination of Write)

See Fig. 1

ts(DI)

Setup Time Data Input (Prior to
Termination of Write)

See Fig. 1

th(DI)

Hold Time Data Input (After
Termination of Write)

tpw(WE)

tpHd A)
tpZH(CS)
tpzdCS)
tpZH(WE)
tpzdWE)
ts(A)

tPHZ(CS)
tPlZ(CS)
tplZ(WE)
tpHZ(WE)

-17

0

0

ns

-6

0

0

ns

16

45

55

ns

See Fig. 1

-8

0

0

ns

Min Write Enable Pulse Width
to Insure Write

See Fig. 1

25

45

55

ns

Delay from Chip Select to
Inactive Output (HI-Z)

See Fig. 2

18

30

35

ns

Delay from Write Enable (LOW)
to Inactive Output (HI-Z)

See Fig. 1

18

30

35

ns

Figure 3 Test Load
and Figure 4 for
Input Waveform
Characteristics
See Notes 3 and 4

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. Output is preconditioned to data in (inverted) during write to insure correct data is present on all outputs when write is terminated.
(No write recovery glitch)
3. For open collector Am27LS02, all delays from Write Enable (WE) or Chip Select (CE) inputs to the Data Output (DOUT), tplZ(WE), tplZ(CS),
tpzdWE) and tpzdCS» are measured with S1 closed and CL = 30pF; and with both the input and output timing referenced to 1.5V.
4. For 3-state output Am27LS03, tPZH(W..§ and tpZH(CS) are measured with S1 open, CL = 30pF and with both the input and output timing
referenced to 1.5V. tPZL(WE) and tpzdCS) are measured with S1 closed, CL = 30pF and with both the input and output timing referenced
to 1.5V. tpHZ(WE) andtpHZ(CS) are measured with S1 open and CL ~5pF and are measured between the 1.5Vlevel on the input to the
VOH - 500mV level on the output. t PLZ(WE) and t PlZ(CS) are measured with S1 closed CL ~ 5pF and are measured between the 1.5V
level on the input and the VOL + 500mV level on the output.

SWITCHING WAVEFORMS
WRITE MODE

(CS

= LOW unless otherwise noted)
KEY TO TIMING DIAGRAM
WAVEFORM

INPUTS

OUTPUTS

-.-

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L,TO H

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

1.5V

i'Pw -

'hlA)

'WE1 -

tslAI_

1\\ \\ H

1,5V

,\\\\\\
t-'siDII

0 0 -3

'h lDll

DON'T CARE

1.5 V

r----t-~PLzIWE)

'PHzIWE)

0'0-3

~

I--'PZHI~)
'PZ IWE)

))))))

J!lf!1
Ft-fR

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

Write Cycle Timing. The cycle is initiated by an address change. After ts(A) min, the write enable may begin.
The chip select must also be LOW for writing. Following the write pulse, th(A) min must be allowed before the
address may be changed again. The output will be inactive (floating for the Am27LS03) while the write enable
is LOW or the chip select is HIGH.

Figure 1.

3-9

BPM-348

Am27LS02/LS03
SWITCHING WAVEFORMS (Cont.)
READ MODE
ADDRESS

ADDRESSj

1<0-3

ADDRESSk

ADDRESS I

------1.5V

~ ---+-------~------------_.r_----~----~~------_.~--------- 1.5V

OUTPUT
DISABLE

READA LOW IN
ADDRESS k

READ A HIGH
IN ADDRESSj

DISABLE
OUTPUT

ENABLE
OUTPUT

DISABLE
OUTPUT

READ A HIGH
IN ADDRESS I

Switching delays from address and chip select inputs to the data output. For the Am27LS03, disabled output is
"OFF", represented by a single center line. For the Am27LS02, a disabled output is HIGH.

Figure 2.

BPM-349

AC TEST LOAD AND WAVEFORM
INPUT PULSES

AC TEST LOAD

vcc~
Sl

3.0Vp·p------=Jr------~

R1

600n
OUTPUT

GND---=-

0---_---..
R2

1200n

GND------~--~--~

Figure 4.

Figure 3.
See Notes 2,3 and 4 of Switching Characteristics.

BPM-350

BPM-351

ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM27LS03PC
AM27LS03PCB
AM27LS030C
AM27LS030CB
AM27LS03LC
AM27LS03LCB

P-16-1
P-16-1
0-16-1
0-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

0-16-1
0-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
B-3
C-3
B-3
C-1
B-1

MIL

Speed
Selection

Open
Collector

55ns

AM27LS02PC
AM27LS02PCB
AM27LS020C
AM27LS020CB
AM27LS02LC
AM27LS02LCB

65ns

AM27LS020M
AM27LS020MB
AM27LS02FM
AM27LS02FMB
AM27LS02LM
AM27LS02LMB

AM27LS030M
AM27LS030MB
AM27LS03FM
AM27LS03FMB
AM27LS03LM
AM27LS03LMB

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STO-883, Class C.
Levels B-1 and B-3 conform to MIL-STO-883, Class B.
3. See Operating Range Table.

3-10

Am3101-1 • Am54/7489-1
Am3101 • Am54/7489
Schottky 64·Bit Write Transparent Bipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 16-word x 4-bit low-power write
transparent Schottky RAMs
• Fast "-1" Version: Address access time 35ns
• Standard Version: Address access time 50ns
• low Power: Icc typically 75mA
• Internal ECl circuitry for optimum speed/power
performance over voltage and temperature
• Available with open collector outputs
• Pin compatible replacements for 6560,93403
• 100% reliability assurance testing in compliance
with Mll-STD-883
• Guaranteed to INT-STD-123

The Am3101-1/3101 and Am54/7489-1/Am54/7489 are
64-bit RAMs built using Schottky diode clamped transistors
in conjunction with internal ECl circuitry and are ideal for
use in scratch pad and high-speed buffer memory applications. Each memory is organized as a fully decoded 16word memory of 4 bits per word. Easy memory expansion ts
provided by an active lOW chip select (CS) input and open
collector OR tieable outputs. Chip selection for large memory systems can be controlled by active lOW output decoders such as the Am74S138.
An active lOW Write line (WE) controls the writing/reading
operation of the memory. When the chip select and write
lines are lOW the information on the four data inputs Do to
03 is written into the addressed memory word. During the
write cycle, the outputs are active and invert the four data
inputs, Do to 03.
Reading is performed with the chip selectline lOW and the
write line HIGH. The information stored in the addressed
word is read out on the four inverting outputs Co to 03.
When the chip select line is HIGH, the four outputs of the
memory go to an inactive high impedance state.

LOGIC BLOCK DIAGRAM

LOGIC SYMBOL

6

10

12

D2
15

A,

14

A2

13

A3

64-BIT RAM
16W x 4B

°0

I

0,

°2

9

°3

I
11

Vee = Pin 16
GND = Pin8

BPM-244

BPM-243

3-11

Am3101-1j54/7489-1/31 01/54/7489
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8)

-0.5 to +7V

DC Voltage Applied to Outputs for High Output State

-0.5V to VCC max

DC Input Voltage

-0.5 to +5.5V

Output Current, Into Outputs

20mA

DC Input Current

-30 to +5.0mA

OPERATING RANGE

FUNCTION TABLE
Ambient
Temperature

Input

-55to +125°C

Data Output Status

00- 0 3

CS

WE

Function

Low

Low

Write

00-03 (Inverted)

Low

High

Read

Selected Word (Inverted)

High

Don't
Care

Deselect

Output and Write Disabled

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters
VOL

Description
Output LOW Voltage

Vee == MIN,
VIN == VIH or Vil

VIH

Input HIGH Level

Guaranteed Input Logical HIGH
Voltage for All Inputs (Note 2)

Vil

Input LOW Level

Guaranteed Input Logical LOW
Voltage for All Inputs (Note 2)

III

Input LOW Current

Vee == MAX,
VIN == 0.40V

IIH

Input HIGH Current

Vee == MAX, VIN == 2.4V

Power Supply Current

All inputs == GND
Vee == MAX

lee
Vel
leEX

Typ
(Note 1)

Max

IIOl == 16mA

0.350

0.45

IIOl== 20mA

0.380

0.5

Test Conditions

Min

2.0

Units
Volts

Volts
0.8

I WE, 0 0 -03, Ao- A3

-0.015

-0.25

ICS

-0.030

-0.25

0.0

10

ICOM'L

75

100

IMIL

75

105

Volts
mA
/LA

mA

Input Clamp Voltage

Vee == MIN, liN == -18mA

-0.850

-1.2

Volts

Output Leakage Current

Vcs== VIH
VOUT== 2.4V
Vcs == VIH or VWE == Vil

0

40

/LA

Notes: 1. Typical limits are at Vee == 5.0V and TA == 25°C.
2. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt
to test these values without suitable equipment.
'
3. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.

3-12

Am3101-1/54/7489-1/3101/54/7489
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions: See Figures 3 and 4 and Notes 3 and 4

Am3101-1 • Am54/7489-1
Typ
Parameters
tpLH(A)

Description

(Note 1)

COM'L
Min Max

Am3101 • Am54/7489

MIL
COM'L
Typ
Min Max (Note 1) Min Max

MIL
Min Max

Units

Delay from Address to Output

See Fig. 2

22

35

50

32

50

60

ns

tpzdCS)

Delay from Chip Select (LOW) to
Active Output and Correct Data

See Fig. 2

14

17

25

20

30

40

ns

tpzdWE)

Delay from Write Enable (HIGH)
to Active Output and Correct Data
(Write Recovery - See Note 2)

See Fig. 1

19

35

50

30

50

60

ns

ts(A)

Setup Time Address (Prior
to Initiation of Write)

See Fig. 1

-6.0

0

0

-6.0

0

0

ns

th(A)

Hold Time Address (After
Termination of Write)

See Fig. 1

-2.5

0

0

-2.5

0

0

ns

ts(DI)

Setup Time Data Input (Prior
to Termination of Write)

See Fig. 1

18

25

25

24

30

30

ns

th(DI)

Hold Time Data Input (After
Termination of Write)

See Fig. 1

-4.0

0

0

-4.0

0

0

ns

tpw(WE)

MIN Write Enable Pulse Width
to Insure Write

See Fig. 1

18

25

25

24

30

30

ns

tPl2(CS)

Delay from Chip Select (HIGH)
to Inactive Output (Hi-Z)

See Fig. 2

13

17

25

20

30

40

ns

Delay Data Input to Correct
Data Output (WE = CS = V,Ll

See Fig. 1

18

35

50

30

50

60

ns

tpHdA)

-

tpLH(DI)
tpHdDl)
Notes: 1.
2.
3.
4.

Typical limits are at Vee = 5.0V and TA = 25°C.
Output is conditioned to data in (inverted) during write to insure correct data is present on all outputs during write and after write is terminated.
tpLH(A) and tpHdA) are tested with Sl closed and CL = 30pF with both input and output timing referenced to 1.5V.
For open collector, all delays from Write Enable (WE) or Chip Select (CS) inputs to the Data Output (Dour), tpLZ(WE), tPLZ(CS), tpzdWE)
and tpzdCS) are measured with Sl closed and CL = 30pF; and with both the input and output timing referenced to 1.5V.

CONNECTION DIAGRAMS
Top Views

Chlp-Pak™

DIP

AO

Vee

Cs

Al

WE

A2

°0

A3

50

°3

°1

53

51

°2

GNO

°
2

BPM-245

Note: Pin 1 is marked for orientation.

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

3-13

Am3101-1/54/7489-1/3101/54/7489
SWITCHING WAVEFORMS
WRITE MODE

KEY TO TIMING DIAGRAM
WAVEFORM

INPUTS

OUTPUTS

---

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM HTO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L·TO H

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

JJJJJJ

xx

H

BPM-246

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"'OFF"'STATE

Write Cycle Timing. The cycle is initiated by an address change. After ts(A) min, the write enable may begin. The chip select must also be LOW for
writing. Following the write pulse, th(A) min must be allowed before the address may be changed again. The output will be inactive while the write
enable is (WE) LOW.

Figure 1

READ MODE
ADD~E~ _ _

ADDRESS j

ADDRESSk

1.5V

ADDRESS I

~ ----~r-----------------------------------~--------~--------~--------------~-----------------

OUTPUT
DISABLE

READ A HIGH
IN ADDRESSj

READ A LOW IN
ADDRESSk

DISABLE
OUTPUT

ENABLE
OUTPUT

READ A HIGH
IN ADDRESS I

1.5V

DISABLE
OUTPUT

BPM-247

Switching delays from address and chip select inputs to the data output. A disabled output is HIGH.

Figure 2

AC TEST LOAD AND WAVEFORM
ACTESTLOAD

INPUT PULSES

vcc~
S1

3.0Vp-p---------t.-----oooo/.
R1

300n

GND

OUTPUT O---~_--_4
R2

GND------~~~~--~-

600n

BPM-249

BPM-248

Figure 4

Figure 3

3-14

Am3101-1/54/7489-1j3101j54/7489
ORDERING INFORMATION
Order Code
Speed
Selection

Open
Collector

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

35ns

AM3101-1PC
AM7489-1N
AM3101-1PCB
AM7489-1NB
AM3101-1DC
AM7489-1J
AM3101-1DCB
AM7489-1JB
AM3101-1LC
AM7489-1LC
AM3101-1LCB
AM7489-1LCB

P-16-1
P-16-1
P-16-1
P-16-1
D-16-1
D-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory
Consult Factory
Consult Factory

C-l
C-1
B-1
B-1
C-1
C-l
B-1
B-1
C-1
C-l
B-1
B-1

COM'L

50ns

AM3101-1DM
AM5489-1J
AM3101-1DMB
AM5489-1JB
AM3101-1FM
AM5489-1W
AM3101-1FMB
AM5489-1WB
AM3101-1LM
AM5489-1LM
AM3101-1LMB
AM5489-1LMB

D-16-1
D-16-1
D-16-1
D-16-1
F-16-1
F-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory
Consult Factory
Consult Factory

C-3
C-3
B-3
B-3
C-3
C-3
B-3
B-3
C-3
C-3
B-3
B-3

MIL

50ns

AM3101PC
AM7489N
AM3101PCB
AM7489NB
AM3101DC
AM7489J
AM3101DCB
AM7489JB
AM3101LC
AM7489LC
AM3101LCB
AM7489LCB

P-16-1
P-16-1
P-16-1
P-16-1
D-16-1
D-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory
Consult Factory
Consult Factory

C-1
C-1
B-1
B-1
C-1
C-1
B-1
B-1
C-l
C-1
B-1
B-1

COM'L

60ns

AM3101DM
AM5489J
AM3101DMB
AM5489JB
AM3101FM
Am5489W
AM3101FMB
AM5489WB
AM3101LM
AM5489LM
AM3101LMB
AM5489LMB

D-16-1
D-16-1
D-16-1
D-16-1
F-16-1
F-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory
Consult Factory
Consult Factory

C-3
C-3
B-3
B-3
C-3
C-3
B-3
B-3
C-3
C-3
B-3
B-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following
letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications.
Pad layout and bonding diagram available upon request.

3-15

Am3101A· Am54S/74S2891
Am54S/74S 189
Schottky 64·Bit Bipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 16-word x 4-bit low power
Schottky RAMs
• Ultra-High speed: Address Access time 35ns
• low Power: Icc typically 7SmA
• Internal ECl circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate write
recovery glitch
• Available with open collector outputs
(Am54S/74S289/Am31 01 A) or with three-state outputs
(Am54S/74S189)
• Pin compatible replacements for Am27S02, 93403,
6560 (use Am54S/74S289/Am3101A); for Am27S03,
6561, DM8599 (use Am54S/74S189)
• 100% Mll-STD-883C assurance testing
• Guaranteed to INT-STD-123 quality levels

The Am3101A/Am54S/74S289 and Am54S/74S189 are
64-bit RAMs built using Schottky diode clamped transistors
in conjunction with internal ECl circuitry and are ideal for
use in scratch pad and high-speed buffer memory applications. Each memory is organized as a fully decoded 16word memory of 4 bits per word. Easy memory expansion is
provided by an active lOW chip select (CS) input and open
collector OR tieable outputs (Am3101A/Am54S/74S289) or
three-state outputs (Am54S/74S189). Chip selection for
large memory systems can be controlled by active lOW
output decoders such as the Am74S138.
An active lOW Write line (WE) controls the writing/reading
operation of the memory. When the chip select and write
lines are lOW the information on the four data inputs Do to
D3 is written into the addressed memory word and preconditions the output circuitry so that correct data is present at
the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times
by eliminating the "write recovery glitch".
Reading is performed with the chip select line lOW and
the write line HIGH. The information stored in the addressed word is read out on the four inverting outputs
00 to 03.
During the writing operation or when the chip select line is
HIGH the four outputs of the memory go to an inactive high
impedance state.

LOGIC BLOCK DIAGRAM

LOGIC SYMBOL

CS
AO
15

Al

14

A2

13

A3

°0

6

10

12

° 1

°2

°3

64-BIT RAM
16W x 4B

00

° 1

°2

°3

9

11

Vee:: Pin 16
GND:: Pin8

BPM-250

3-16

WE

BPM-251

Am3101A/54S/74S289/54S/74S189
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8)

-0.5to +7V

DC Voltage Applied to Outputs for High Output State

-0.5V to VCC max

DC Input Voltage

-0.5 to +5.5V

Output Current, Into Outputs

20mA

DC Input Current

-30 to +5.0mA

OPERATING RANGE

FUNCTION TABLE
Ambient
Temperature

Input

-55 to +125°C

Data Output Status

00- 0 3

CS

WE

Low

Low

Write

Output Disabled

Low

High

Read

Selected Word (Inverted)

High

Don't
Care

Deselect

Output Disabled

Function

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters

Description

VOH
(Note 2)

Output HIGH Voltage

VOL

Output LOW Voltage

Test Conditions
IOH= -5.2mA

IOl = 16mA

0.350

0.45

IOl= 20mA

0.380

0.5

Vil

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

III

Input LOW Current

Vee = MAX,
VIN = 0.40V

IIH

Input HIGH Current

Vee = MAX, VIN = 2.4V

Ise
(Note 2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV
(Note 4)

Icc

Power Supply Current

All inputs = GND
Vee = MAX

Output Leakage Current

3.2

Vee = MIN,
VIN = VIH or Vil
Guaranteed input logical HIGH
voltage for all inputs (Note 3)

ICEX

2.4

Max

IOH = -2.0mA

Input HIGH Level

Input Clamp Voltage

COM'L

Typ
(Note 1)

Vee = MIN,
VIN = VIH or Vil

VIH

Vel

1

Min

IMIL

Units
Volts

2.0

Volts

Volts
0.8

Volts

WE, 00-03, Ao-A3

-0.015

-0.250

CS

-0.030

-0.250

0.0

10

pA

-45

-90

mA

-20

mA

COM'L

75

100

MIL

75

105

Vee = MIN, liN = -18mA

-0.850

-1.2

Volts

VC'S = VIH or VWE = Vil
VOUT= 2.4V

0

40

/LA

Ves = VIH or VWE = Vil
VOUT = O.4V, Vce = MAX

(Note 2)

-40

0

mA

/LA

Notes: 1. Typical limits are at Vec = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt
to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.

3-17

Am3101Aj54Sj74S289j54Sj74S189
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions: See Figures 1 and 2 and Notes 3, 4, 5

Typ
Parameters
tpLH(A)

Description

(Note 1)

COM'L
Min
Max

MIL
Min

Max

Units

Delay from Address to Output

See Fig. 2

22

35

50

ns

Delay from Chip Select (LOW) to Active
Output and Correct Data

See Fig. 2

14

17

25

ns

Delay from Write Enable (HIGH) to Active
Output and Correct Data (Write Recovery See Note 2)

See Fig. 1

19

35

40

ns

t5(A)

Setup Time Address (Prior to
Initiation of Write)

See. Fig. 1

-6.0

0

0

ns

th(A)

Hold Time Address (After
Termination of Write)

See Fig. 1

-2.5

0

0

ns

t5(DI)

Setup Time Data Input (Prior to
Termination of Write)

See Fig. 1

18

25

25

ns

th(DI)

Hold Time Data Input (After
Termination of Write)

See Fig. 1

-4.0

0

0

ns

tpw(WE)

MIN Write Enable Pulse Width to
Insure Write

See Fig. 1

18

25

25

ns

Delay from Chip Select (HIGH) to
Inactive Output (HI-Z)

See Fig. 2

13

17

25

ns

Delay from Write Enable (LOW) to
Inactive Output (HI-Z)

See Fig. 1

15

25

35

ns

tpHdA)
tpZH(CS)
tpzdCS)
tpZH(WE)
tpzdWE)

tPHZ(CS)
tpLZ(CS)
tPLZ(WE)
tPHZ(WE)

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. Output is preconditioned to data in (inverted) during write to insure correct data is present on all outputs when write is terminated.
(No write recovery glitch.)
3. tpLH(A) and tpHdA) are tested with S1 closed and CL = 30pF with both input and output timing referenced to 1.5V.
4. For open collector, all delays from Write Enable (WE) or Chip Select (CS) inputs to the Data Output (DOUT' tpLZ(WE), tpLZ(CS), tpzdWE)
and tpzL..-

---+

OUTPUT ( ) - - -.....

R2

6000
GND------~~~----~~

BPM·24B

BPM·249

Figure 3.

Figure 4.
See Notes 3 and 4 of Switching Characteristics.

3-24

Am31 L01Aj31 L01
ORDERING INFORMATION
Order Code

Package
Type

Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

P-16-1
P-16-1
0-16-1
0-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

65ns

AM31L01AOM
AM31L01AOMB
AM31L01AFM
AM31L01AFMB
AM31 L01 ALM
AM31L01ALMB

0-16-1
0-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
B-3
C-3
B-3
C-3
B-3

MIL

80ns

AM31L01PC
AM31L01PCB
AM31 L01DC
AM31 L01DCB
AM31L01LC
AM31L01LCB

P-16-1
P-16-1
0-16-1
0-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

90ns

AM31L010M
AM31 L01DMB
AM31L01FM
AM31L01FMB
AM31L01LM
AM31L01LMB

0-16-1
0-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
B-3
C-3
B-3
C-3
B-3

MIL

Speed
Selection

Open
Collector

55ns

AM31L01APC
AM31L01APCB
AM31 L01AOC
AM31 L01AOCB
AM31L01ALC
AM31L01ALCB

Screening

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip- Pak, F = Cerpak.
Numberfollowing letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STO-883, Class C.
Levels B-1 and B-3 conform to MIL-STO-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad
layout and bonding diagram available uporl request.

3-25

Am27S06A • Am27S07A
Am27S06 • Am27S07
Noninverfing Schottky 64·8if 8ipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 16-word x 4-bit low-power, noninverting
Schottky RAMs
• Ultra-high speed "A" version:
Address access time typically 15ns
High speed standard version:
Address access time typically 22ns
• Low power: IcC typically 75mA
• Internal ECl circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate write
recovery glitch
• Available with three-state outputs (Am27S07A/07) or
with open collector inputs (Am27S06A/06)
• 100% reliability assurance testing in compliance with
Mll-STD-883
• Guaranteed to INT-STD-123 quality levels
• Electrically tested and optically inspected die are
available for the assemblers of hybrid products

The Am27S06A/06 and Am27S07A/07 are 64-bit RAMs
built using Schottky diode clamped transistors in conjunction with internal ECl circuitry and are ideal for use in
scratch pad and high-speed buffer memory applications.
Each memory is organized as a fully decoded 16-word
memory of 4 bits per word. Easy memory expansion is
provided by an active lOW chip select (CS) input and open
collector OR tieable outputs (Am27S06A/06) or three-state
outputs (Am27S07A/07). Chip selection for large memory
systems can be controlled by active lOW output decoders
such as the Am74S138.
An active lOW write line WE controls the writing/reading
operation of the memory. When the chip select and write
lines are lOW the information on the four data inputs Do to
D3 is written into the addressed memory word and preconditions the output circuitry so that correct data is present at
the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times
by eliminating the "write recovery glitch".
Reading is performed with the chip select line lOW and the
write line HIGH. The information stored in the addressed
word is read out on the four noninverting outputs 00 to 03.
During the writing operation or when the chip select line is
HIGH the four outputs of the memory go to an inactive high
impedance state.
LOGIC SYMBOL

lOGIC BLOCK DIAGRAM

°0
15

A1

14

A2

13

A3

°1

10

12

°2

°3

WE

54-BIT RAM
16W x4B

00

01

O2

°3

11

Vee = Pin 16
GND = PinS

BPM-353

CONNECTION DIAGRAMS - Top Views
DIP

BPM-352

Chip-Pak™

AO

Vee

Cs

A,

WE

A2

DO

A3

°0

D3

D,

°3

0,

D2

GND

°2

Note: Pin 1 is marked for orientation.

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

3-26

BPM-354

Am21S06A/07A/06/07
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8)

-0.5to +7V

DC Voltage Applied to Outputs for High Output State

-0.5V to VCC max

DC Input Voltage

-0.5 to +5.5V

Output Current, Into Outputs

20mA

DC Input Current

-30 to +5.0mA

OPERATING RANGE
Ambient
Temperature

-55 to +125°C

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

VOH
(Note 2)

Output HIGH Voltage

VOL

Output LOW Voltage

Test Conditions

IOH = -2.0mA

MIL

Vee = MIN,
VIN = VIH or Vil

IOl= 16mA

0.350

0.45

IOl = 20mA

0.380

0.5

Vil

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

III

Input LOW Current

Vee = MAX,
VIN = 0.40V

IIH

Input HIGH Current

Vee = MAX, VIN = 2.4V

Ise
(Note 2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV
(Note 4)

lee

Power Supply Current

All inputs = GND
Vee = MAX

Output Leakage Current

3.2

Vee = MIN,
VIN = VIH or Vil

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

leEX

2.4

Max

COM'L

Input HIGH Level

Input Clamp Voltage

(Note 1)

IOH = -5.2mA

VIH

Vel

Min

Units
Volts

2.0

Volts

Volts
0.8

Volts

WE, Do-D3, Ao-A3

-0.015

-0.250

CS

-0.030

-0.250

0.0

10

/LA

-45

-90

mA

mA

-20
COM'L

75

100

MIL

75

105

Vee = MIN, liN = -18mA

-0.850

-1.2

Volts

Vcs = VIH or VWE = Vil
VOUT= 2.4V

0

40

/LA

Vcs = VIH or VWE = Vil
VOUT = O.4V, Vee = MAX

(Note 2)

-40

0

mA

/LA

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt
to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.

FUNCTION TABLE
Input
CS

WE

Function

Data Output
Status 00-3

Low

Low

Write

Output Disabled

Low

High

Read

Selected Word

High

Don't
Care

Deselect

Output Disabled

3-27

Am27S06A/07A/06/07
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Test Conditions: See Figures 3 and 4 and Notes 3, 4, 5

(Unless Otherwise Noted)

Am27S0SA· Am27S07A
Typ

Parameters
tpLH(A)

COM'L
(Note 1) Min Max

Description

Am27S0S· Am27S07

MIL
Typ
COM'L
Min Max (Note 1) Min Max

MIL
Min Max

Units

Delay from Address to Output

See Fig. 2

15

25

30

22

35

50

ns

Delay from Chip Select (LOW) to
Active Output and Correct Data

See Fig. 2

10

15

20

14

17

25

ns

Delay from Write Enable (HIGH)
to Active Output and Correct Data
(Write Recovery - See Note 2)

See Fig. 1

12

20

25

19

35

40

ns

ts(A)

Setup Time Address (Prior
to Initiation of Write)

See Fig. 1

-6.0

0

0

-6.0

0

0

ns

th(A)

Hold Time Address (After
Termination of Write)

See Fig. 1

-2.5

0

0

-2.5

0

0

ns

ts(DI)

Setup Time Data Input (Prior
to Termination of Write)

See Fig. 1

9.0

20

25

18

25

25

ns

th(DI)

Hold Time Data Input (After
Termination of Write)

See Fig. 1

-4.0

0

0

-4.0

0

0

ns

tpw(WE)

Min Write Enable Pulse Width
to Insure Write

See Fig. 1

10

20

25

18

25

25

ns

Delay from Chip Select (HIGH)
to Inactive Output (Hi-Z)

See Fig. 2

10

15

20

13

17

25

ns

Delay from Write Enable (LOW)
to Inactive Output (Hi-Z)

See Fig. 1

12

20

25

15

25

35

ns

tpHdA )
tpZH(CS)
tpzdCS)
tpZH(WE)
tpzd WE )

tpHZ(CS)
tpLZ(CS)
tpLZ(WE)
tpHZ(WE)

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. Output is preconditioned to data in (noninverted) during write to insure correct data is present on all outputs when write is terminated.
(No write recovery glitch.)
3. tpLH(A) and tPHL(A) are tested with S1 closed and CL = 30pF with both input and output timing referenced to 1.5V.
4. For open collector, all delays from Write Enable (WE) or Chip Select (CS) inputs to the Data Output (DOUT), tpLZ(WE), tpLZ(CS), tpzdWE)
and tpzdCS) are measured with S1 closed and CL = 30pF and with both the input and output timing referenced to 1.5V.
5. For 3-state output, tPZH(WE) and tpZH(CS) are measured with S1 open, CL = 30pF and with both the input and output timing referenced
to 1.5V. tpZL(WE) and tpzdCS) are measured with S1 closed, CL = 30pF and with both the input and output timing referenced to 1.5V.
tpHZ(WE) and tpHZ(CS) are measured with S1 open and CL";; 5pF and are measured between the 1.5V level on the input to the
VOH - 500mV level on the output. tpLz(WE) and tpLZ(CS) are measured with S1 closed and CL ,,;; 5pF and are measured between
the 1.5V level on the input and the VOL + 500mV level on the output.

KEY TO TIMING DIAGRAM

SWITCHING WAVEFORMS
WRITE MODE

ADD~~~~

--1-[

(CS = LOW unless otherwise noted)

--H~H-HH-H-H-H-H-H-

Is(AI_

-

Ih(AI

rls(OII

Ih(OIi

1.5V

ilpw(WE'-

I\\\\\V
,\\\\\\

1.5V

I

DON'T CARE

1.5V

r------t-~PLz(~1

IpHZ(WEI

f---IpZH(.Y!..§.1
IpZL(WEI

WAVEFORM

INPUTS

OUTPUTS

-.-

MUST BE
STEADY

Will BE
STEADY

MAY CHANGE
FROM H TO l

Will BE
CHANGING
FROM H TO l

MAY CHANGE
FROM l TO H

Will BE
CHANGING
FROM l·TO H

DON'TeARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

--

]HE

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

Write Cycle Timing. The cycle is initiated by an address change. After ts(A) min, the write enable may begin.
The chip select must also be LOW for writing. Following the write pulse, th(A) min must be allowed before the
address may be changed again. The output will be inactive (floating for the Am27S07A/07) while the write
enable is LOW.

Figure 1.

3-28

BPM-355

Am27S06Aj07Aj06j07
SWITCHING WAVEFORMS (Cont.)
READ MODE

ADD~E~

__

ADDRESS j

ADDRESSk

ADDRESS I

1.5V

~ ----~r_~------------------------------_+--------~--------~--------------~---------------

OUTPUT
DISABLE

READAHIGH
IN ADDRESSj

READA LOW IN
ADDRESSk

DISABLE
OUTPUT

ENABLE
OUTPUT

READA HIGH
IN ADDRESS I

1.5V

DISABLE
OUTPUT

Switching delays from address and chip select inputs to the data output. For the Am27S07A/07 disabled
output is "OFF", represented by a single center line. For the Am27S06A/06 disabled output is HIGH.

Figure 2. .

BPM-356

ACTESTLOAD

Vcc~
51
R1

3000
OUTPUT O-----_~-----4
R2

600!l

See Notes 3, 4, and 5 of Switching Characteristics.

Figure 3.

BPM-357

INPUT PULSES

3.0Vp-p-------::.~----=!_

GND

GND------~~~----~~

Figure 4.

3-29

BPM-358

Am27S06A/07A/06/07
ORDERING INFORMATION
Order Code

Package
Type

Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

P-16-1
P-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

AM27S07ADM
AM27S07ADMB
AM27S07AFM
AM27S07AFMB
AM27S07ALM
AM27S07ALMB

D-16-1
D-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
B-3
C-3
8-3
C-3
B-3

MIL

35ns

AM27S06PC
AM27S06PCB
AM27S06DC
AM27S06DCB
AM27S06LC
AM27S06LCB

AM27S07PC
AM27S07PCB
AM27S07DC
AM27S07DCB
AM27S07LC
AM27S07LC8

P-16-1
P-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
8-1
C-1
B-1

COM'L

SOns

AM27S06DM
AM27S06DMB
AM27S06FM
AM27S06FMB
AM27S06LM
AM27S06LM8

AM27S07DM
AM27S07DMB
AM27S07FM
AM27S07FMB
AM27S07LM
AM27S07LMB

D-16-1
D-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
8-3
C-3
B-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

Three-State

25ns

AM27S06APC
AM27S06APCB
AM27S06ADC
AM27S06ADCB
AM27S06ALC
AM27S06ALCB

AM27S07APC
AM27S07APCB
AM27S07ADC
AM27S07ADCB
AM27S07ALC
AM27S07ALCB

30ns

AM27S06ADM
AM27S06ADMB
AM27S06AFM
AM27S06AFM8
AM27S06ALM
AM27S06ALMB

Screening

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

3-30

Am29700
• Am29701
Noninverting
64· Bit
Schottky

RAM

Refer to

Am27S06 • Am27S07
Bipolar Memory RAM Product Specification
The Am29700 is replaced by the Am27S06
(open collector).
The Am29701 is replaced by the Am27S07
(three-state).

3-31

Am27LS06 • Am27LS07
L.ow Power, Noninverting 64·Bit Bipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

•
•
•
•

The Am27LS06 and Am27LS07 are 64-bit RAMs built using
Schottky diode clamped transistors in conjunction with
internal ECL Circuitry and are ideal for use in scratch pad
and high-speed buffer memory applications. Each memory
is organized as a fully decoded 16-word memory of 4 bits
per word. Easy memory expansion is provided by an active
LOW chip select (CS) input and open collector OR tieable
outputs (Am27LS06) or three-state outputs (Am27LS07).
Chip selection for large memory systems can be controlled
by active LOW output decoders such as the Am74LS189.

•
•
•
•
•

Fully decoded 16-word x 4-bit low power Schottky RAMs
Ultra-low power: ICC typically 30mA
High-speed: Address access time typically 40ns
Internal ECL circuitry for optimum speed/power
performance over voltage and temperature
Output preconditioned during write to eliminate the write
recovery glitch
Available with three-state outputs (Am27LS07) or with
open collector outputs (Am27LS06)
100% MIL-STD-883 assurance testing
Electrically tested and optically inspected die for the
assemblers of hybrid products
Guaranteed to INT-STD-123

An active LOW Write line WE controls the writing/reading
operation of the memory. When the chip select and write
lines are LOW the information on the four data inputs Do to
D3 is written into the addressed memory word and preconditions the output circuitry so that correct data is present at
the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times
by eliminating the '''write recovery glitch".
Reading is performed with the chip select line LOW and the
write line HIGH. The information stored in the addressed
word is read out on the four noninverting outputs 00 to 03.
During the writing operation or when the chip select line is
HIGH the four outputs of the memory go to an inactive high
impedance state.

LOGIC BLOCK DIAGRAM

LOGIC SYMBOL

DO
15

Al

14

A2

13

A3

6

10

12

01

O2

03

RAM
16W x4B
°0

°1

°2

°3

9

11

Vee = Pin 16
GND = PinS

BPM-224

CONNECTION DIAGRAMS
Top Views
DIP
AO

Chip·Pak™
vee

cs

Al

WE

A2

DO

Aj

°0

03

01

°3

°1

O2

GNO

°2

BPM-225
BPM-223

Note: Pin 1 is marked for orientation.

Chip- Pak is a trademark of Advanced Micro Devices, Inc.

3-32

~~

o

A,

o~~~
Q(}

A,
01

~~~

WE
A7

As
As

BPM-359

Note: Pin 1 is marked for orientation.

LOGIC DIAGRAM

r---------,
'¢'~~"
I
I

AO
A1

~:;:

"-0

A2

20::

IL

16 X 16

I

_ _ _ _ _ _ _ _ -'

,----------,I
B

ARRAY OF
MEMORY CELLS

A

C

Am27LS01·1AiOl·l

DO

I

A3

01

BPM-360

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

3-42

Am27LSOO-1A/LS01-1A/LSOO-1/LS01-1
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous

-0.5to +7V

DC Voltage Applied to Outputs for High Output State

-0.5Vto +VCC max

DC Input Voltage

-0.5Vto +VCC
30mA

Output Current, Into Outputs

-30 to +5mA

DC Input Current

OPERATING RANGE

Ambient
Temperature
TA = Oto +75°C
TA = -55 to

+ 125°C

ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

VOH(Note2)

Output HIGH Voltage

Vee = MIN,
VIN = VIH or VIL

I COM'L
10H == -2.0mA I MIL

VOL

Output LOW Voltage

Vee == MIN,
VIN = VIH or VIL

10L = 16mA

VIH

Input HIGH Level

Guaranteed input logical HIGH
voltage for all inputs (Note 3)

VIL

Input LOW Level

Guaranteed input logical LOW
voltage for all inputs (Note 3)

IlL

Input LOW Current

Vee = MAX, VIN = 0.40V

IIH

Input HIGH Current

Vee = MAX, VIN = 2.7V

Ise(Note2)

Output Short Circuit Current

Vee = MAX, VOUT = O.OV

Icc

Power Supply Current

All inputs = GND
Vee = MAX

VeL

Input Clamp Voltage

Output Leakage Current

leEX

10H = - 5.2mA

Min

(Note 1)

2.4

3.2

0.310

Units
Volts

0.45

Volts

2.0

Volts
O.S

Volts

0.030

0.25

mA

<1

20

/l-A

-30

-60

mA

I "A" version

SO

115

I Standard

55

70

-0.S50

-1.2

Volts

0

30

/J- A

-20

mA

Vee = MIN, liN = -lSmA
VC'S = VIH or VWE = VIL
VOUT= 2.4V
VC'S = VIH or VWE = VIL
VOUT = O.4V, Vee = MAX

Max

I (Note2)

-30

/J- A

0

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies to three-state devices only.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt
to test these values without suitable equipment.

FUNCTION TABLE

CS

WE

01

Function

Data Output
Status
DO

High

Don't
Care

Don't
Care

No Selection

Output Disabled

Input

Low

Low

Low

Write "0"

Output Disabled

Low

Low

High

Write "1"

Output Disabled

High

Don't
Care

LOGIC SYMBOL
2 1 15 14 7 9 10 11

256W x 1-BIT

RAM

Low

Read

Selected Word

6

DO

1 2 - < > WE

Vee = Pin 16
GND= PinS
BPM-361

3-43

Am27LSOO-1A/LS01-1A/LSOO-1/LS01-1
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions: See Figures 3 and 4 and Notes 3,4 and 5
Am27LSOO-1A· Am27LS01-1A
Typ

Parameters
tpLH(A)

COM'L
(Note 1) Min Max

Description

Am27LSOO-1 • Am27LS01-1

MIL
Typ
COM'L
Min Max (Note 1) Min Max

MIL
Min Max

Units

Delay from Address to Output

See Fig. 4

25

35

45

35

45

55

ns

Delay from Chip Select (LOW) to
Active Output and Correct Data

See Fig. 4

15

25

25

15

25

30

ns

Delay from Write Enable (HIGH)
to Active Output and Correct Data

See Fig. 3

tpzdWE)
tred WE )

Delay from Write Enable (HIGH)
to Correct Output Data

See Fig. 3

25

35

45

35

45

55

ns

ts(A)

Setup Time Address (Prior
to Initiation of Write)

See Fig. 3

0

0

5

-5

0

5

ns

th(A)

Hold Time Address (After
Termination of Write)

See Fig.3

0

0

5

-5

0

5

ns

ts(DI)

Setup Time Data Input (Prior
to Termination of Write)

See Fig. 3

25

25

30

25

30

55

ns

th(DI)

Hold Time Data Input (After
Termination of Write)

See Fig. 3

0

5

5

-5

0

5

ns

Min Write Enable Pulse Width
to Insure Write

See Fig. 3

20

Delay from Chip Select (HIGH)
to Inactive Output (HI-Z)

See Fig. 4

15

25

25

15

25

30

ns

Delay from Write Enable (LOW)
to Inactive Output (HI-Z)

See Fig. 3

20

30

40

20

30

40

ns

tpHL(A)
tpZH(CS)
tpzdCS)
tpZH(WE)

-

tpw(WE)
tpHZ(CS)
tpLZ(CS)
tpLZ(WE)
tpHZ(WE)

5

5

25

5

5

30

20

30

ns

35

ns

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. Output is preconditioned to data in during write to insure correct data is present on all outputs when write is terminated.
(No write recovery glitch.)
3. tPLH(A) and tpHdA) are tested with S closed and CL = 50pF with both input and output timing referenced to 1.5V.
4. For open collector, all delays from Write Enable (WE) or Chip Select (CS) inputs to the Data Output (DOUT), tpLZ(WE), tpLZ(CS)
tpzdWE) and tpzdCS) are measured with S closed and CL = 50pF and with both the input and output timing referenced to 1.5V.
5. For3-state output, tPZH{WE) and tpZH(CS) are measured with S open, CL = 50pF and with both the input and output ti'ming referenced
to 1.5V. tpZL(WE) and tpzL(CS) are measured with S closed, CL = 50pF and with both the input and output timing referenced to 1.5V.
tpHz(WE) and tpHZ(CS) are measured with S open and CL';:; 5pF and are measured between the 1.5V level on the inputtothe
VOH - 500mV level on the output. tpLZ(WE) and tpLZ(CS) are measured with S closed and CL .;:; 5pF and are measured between
the 1.5V level on the input and the VOL + 500mV level on the output.

AC TEST LOAD AND WAVEFORM
AC TEST LOAD

INPUT PULSES

TEST POINT

0 - - - - Vee

3.0Vp-p

300n

GND

<10ns
FROM
OUTPUT

<10ns

3.0Vp-p
CL

I

600n

-=

GND
BPM-296

BPM-295

Figure 2.

Figure 1.
See Notes 3, 4 and 5 of Switching Characteristics.
3-44

Am27LSOO-1A/LS01-1A/LSOO .. 1/LS01 .. 1
SWITCHING WAVEFORMS
WRITE MODE

KEY TO TIMING DIAGRAM
ADDRE~ ----------------~--------------------------~~~~~~~~~
A~7

_______________1~

______________________

-4~~~~~~~~

WAVEFORM

-JJIfff

---

DO

(If~-LI

------------------------~~~

H

BPM·297

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
fROM H TO L

WILL BE
CHANGING
fROM H TO L

MAY CHANGE
fROM L TO H

WILL BE
CHANGING
fROM L TO H

DON'TCARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

OOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OfF" STATE

Write Cycle Timing. The cycle is initiated by an address change. After ts(A) max, the write enable may begin. The chip select must also
be LOW for writing. Following the write pulse, th(A) max must be allowed before the address may be changed again. The output will be
inactive (floating for the Am27LSOO-1NOO-1) while the write enable is LOW. Ordinarily, the chip select should be LOW during the entire
write pulse.

Figure 3.

8PM-362

READ MODE

ADDRESS
AO-7

- - ADDRESS j - - - I f - - - - - - - - - A D D R E S S k - - - - - - - - r - - A D D R E S S I - - - - - - - - - - - -

DO

OUTPUT
DISABLED

READ A HIGH
IN ADDRESS j

READ A LOW IN
ADDRESS k

DISABLE
OUTPUT

ENABLE
OUTPUT

READ A HIGH
IN ADDRESS I

BPM·29B

Switching delays from address and chip select inputs to the data output. For the Am27LSOO-1NOO-1 disabled output is "OFF,"
represented by a single center line. For the Am27LS01-1N01-1, a disabled output is HIGH.

Figure 4.

3-45

8PM·363

Am27LSOO-1A/LS01-1A/LSOO-1/LS01-1
ORDERING INFORMATION
Order Code
Speed
Selection

Open
Collector

Three-State

Package
Type
(Note 1)

Flow Code

Screening
(Note 2)

Operating
Range
(Note 3)

35ns

AM27LS01-1 APC
AM27LS01-1APCB
AM27LS01-1 ADC
AM27LS01-1 ADCB
AM27LS01-1 ALC
AM27LS01-1 ALCB

AM27LSOO-1 APC
AM27LSOO-1 APCB
AM27LSOO-1 ADC
AM27LSOO-1 ADCB
AM27LSOO-1 ALC
AM27LSOO-1 ALCB

P-16-1
P-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

45ns

AM27LS01-1 ADM
AM27LS01-1 ADMB
AM27LS01-1 AFM
AM27LS01-1AFMB
AM27LS01-1ALM
AM27LS01-1 ALMB

AM27LSOO-1 ADM
AM27LSOO-1 ADMB
AM27LSOO-1 AFM
AM27LSOO-1 AFMB
AM27LSOO-1 ALM
AM27LSOO-1 ALMB

D-16-1
D-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
B-3
C-3
B-3
C-3
B-3

MIL

45ns

AM27LS01-1 PC
AM27LS01-1 PCB
AM27LS01-1DC
AM27LS01-1 DCB
AM27LS01-1 LC
AM27LS01-1 LCB

AM27LSOO-1 PC
AM27LSOO-1 PCB
AM27LSOO-1 DC
AM27LSOO-1 DCB
AM27LSOO-1 LC
AM27LSOO-1 LCB

P-16-1
P-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

55ns

AM27LS01-1DM
AM27LS01-1 DMB
AM27LS01-1FM
AM27LS01-1 FMB
AM27LS01-1LM
AM27LS01-1 LMB

AM27LSOO-1 DM
AM27LSOO-1 DMB
AM27LSOO-1 FM
AM27LSOO-1 FMB
AM27LSOO-1 LM
AM27LSOO-1 LMB

D-16-1
D-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
B-3
C-3
B-3
C-3
B-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels B-1 and B-3 conform to MIL-STD-883, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

3-46

Am93412A • Am93422A
Am93412 • Am93422
TTL 1024·Bif Bipolar IMOX™ RAM

DISTINOTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 256-word x 4-bit RAMs

The Am93412A/412 and Am93422A/422 are 1024-bit
RAMs built using Schottky diode clamped transistors in
conjunction with internal ECl circuitry and are ideal for use
in high-spe~d control and buffer memory applications.
Each memory is organized as a fully decoded 256-word
memory of four bits per word. Easy memory expansion is
provided by an active lOW chip select one (CS1) and an
active HIGH chip select two (CS2) as well as open collector
OR tieable outputs (Am93412A/412) or 3-state outputs
(Am93422A/ 422).

• High-speed "A" version:
Address access time typically 25ns
High-Speed Standard version:
Address access time typically 30ns
• Internal ECl circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate write
recovery glitch

An active lOW write line (WE) controls the writing/reading
operation of the memory. When the chip select one (CS1)
and write line (WE) are lOW and chip select two (CS2) is
HIGH, the information on data inputs (Do through D3) is
written into the addressed memory word and preconditions
the output circuitry so that true data is present at the outputs
when the write cycle is complete. This preconditioning
operation insures minimum write recovery times by eliminating the "write recovery glitch."

• Available with 3-state outputs (Am93422A/422) or with
open collector outputs (Am93412A/412)
• 100% reliability assurance testing in compliance with
Mll-STD-883
• Electrically tested and optically inspected die for the
assemblers of hybrid products
• Plug-in replacement for Fairchild 93412/412A and
93422/422A

Reading is performed with the chip select one (CS1) lOW
and the chip select two (CS2) HIGH and the write line (WE)
HIGH and with the output enable (DE) lOW. The information stored in the addressed word is read out on the
noninverting outputs (00 through 03).

• Power dissipation decreases with increasing
temperature
• Guaranteed to INT-STD-123 quality levels

The outputs of the memory go to an inactive highimpedance state whenever chip select one (CS1) is HIGH,
chip select two (CS2) is lOW, output enable (0 E) is HIGH,
or during the writing operation when write enable (WE)
is law.

LOGIC BLOCK DIAGRAM

LOGIC SYMBOL

(4)

4

Ao

(3)

3

A,

(2)

2

A2

(1)

1

A3

(23) 21

A4

(9)
9

(11)
11

(15)
13

(17)
15

Do

D,

D2

D3

CS 2

17

(19)

CS,
WE
DE

19

(21)

18

00

10

(10)
(14)

20 (22)
(20)

(5)

5

As

0,

12

(6)

6

As

02

14

(16)

(7)

7

A7

03

16

(18)

Vee = Pin 22 (24)
GND = Pin 8 (8)
BPM-130

BPM-129

IMOX is a trademark of Advanced Micro Devices, Inc.
3-47

Note: Pin numbers in parentheses "(
for 24-pin flat package.

)" indicate pinout

Am93412A/422A/412/422
MAXIMUM RATINGS

(Above which the useful life may be impaired)

Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 22 to Pin 8)

-0.5 to + 7.0V

DC Voltage Applied to Outputs for High Output State

-O.5V to Vee max

DC Input Voltage

-0.5 to +5.5V

Output Current, Into Outputs (Low)

20mA

DC Input Current

-30 to +5.0mA

OPERATING RANGE

FUNCTION TABLE

Vee

Ambient
Temperature

4.75 to 5.25V
4.5t05.5V

-55 to +125°C

Inputs

Output

CS 2

CS 1

WE

OE

Dn

On

Mode

L

X

X

X

X

'HIGHZ

Not Select

X

H

X

X

X

'HIGHZ

Not Select

H

L

H

H

X

'HIGH Z

Output Disable

H

L

H

L

X

Selected Data

Read Data

H

L

L

X

L

'HIGHZ

Write "0"

H

L

L

X

H

'HIGH Z

Write "1"

H = High Voltage Level

L

= Low Voltage Level

X = Don't Care

'High Z implies outputs are disabled or off. This condition is defined as a high
impedance state for the Am93422N422 and as an output high level for the

Am93412N412.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Parameters

Description

Test Conditions

VOH
(Note 2)

Output HIGH Voltage

Vee = MIN,
VIN = VIH or VIL

VOL

Output LOW Voltage

Vee = MIN,
VIN = VIH or VIL

IOH == -5.2mA
IOL== 8.0mA

Min

Typ
(Note 1)

204

3.6

Units
Volts

0045

Volts

1.5

0.8

Volts

0.350
2.1

Max

VIH

Input HIGH Level (Note 3)

Guaranteed input logical HIGH voltage for all inputs

VIL

Input LOW Level (Note 3)

Guaranteed input logical LOW voltage for all inputs

IlL

Input LOW Current

Vee = MAX, VIN = OAOV

-100

-300

/-LA

IIH

Input HIGH Current

Vee = MAX, VIN = 4.5V

1

40

/-LA

Ise
(Note 2)

Output Short Circuit Current

Vee = MAX, VOUT ~ O.OV (Note 4)

-90

rnA

lee

Power Supply Current

All inputs = GND, Vee == MAX

100

TA;;' 75°C

VeL

Input Clamp Voltage

1.6

Volts

130

TA = O°C

155

TA = -55°C

170

Vee = MIN, liN = -10mA
VOUT= 2AV

Am93422A/422

-0.850

-1.5

0

50

rnA

Volts

leEX

Output Leakage Current

VOUT= 0.5V,
Vee = MAX

Am93422A/422

VOUT== 4.5V

Am93412A/412

CIN

Input Pin Capacitance

See Note 5

4

pF

COUT

Output Pin Capacitance

See Note 5

7

pF

-50

0
0

Notes: 1. Typical characteristics are at Vee == 5.0V and TA == 25°C.
2. Applies only to the Am93422A and Am93422 with 3-state outputs.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. Input and output capacitance measured on a sample basis @ f == 1.0MHz.

3-48

/-LA
100

Am93412A/422A/412/422
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions: See Figures 3 and 4 and Notes 3, 4 and 5 (below)

Am93412A· Am93422A
Typ
Parameters
tpLH(A) (Note 3)
tpHdA) (Note 3)
tpZH(CS1, CS2)
tpZdCS1, CS2)
tPZH(WE)
tpzdWE)
tpZH(OE)
tpzdOE)

Description

(Note 1)

COM'L
Min

Max

Am93412· Am93422

MIL
Min

Typ
Max (Note 1)

COM'L
Min

Max

MIL
Min

Max

Units

Delay from Address to Output
(Address Access Time) (See Fig. 2)

25

35

45

30

45

60

ns

Delay from Chip Select to Active
Output and Correct Data (See Fig. 2)

15

25

35

15

30

45

ns

Delay from Write Enable to
Active Output and Correct Data
(Write Recovery) (See Fig. 1)

15

25

40

15

40

50

ns

Delay from Output Enable to Active
Output and Correct Data (See Fig. 2)

10

25

35

10

30

45

ns

ts(A)

Setup Time Address (Prior to
Initiation of Write) (See Fig. 1)

-10

5

5

-10

10

10

ns

th(A)

Hold Time Address (After
Termination of Write) (See Fig. 1)

-10

5

5

-10

5

5

ns

ts(DI)

Setup Time Data Input (Prior to
Initiation of Write) (See Fig. 1)

-10

5

5

-10

5

5

ns

th(DI)

Hold Time Data Input (After
Termination of Write) (See Fig. 1)

-10

5

5

-10

5

5

ns

ts(CS1, CS2)

Setup Time Chip Select (Prior to
Initiation of Write) (See Fig. 1)

-10

5

5

-10

5

5

ns

th(CS1, CS2)

Hold Time Chip Select (After
Termination of Write) (See Fig. 1)

-10

5

5

-10

5

5

ns

tpw(WE)

Min Write Enable Pulse Width
to Insure Write (See Fig. 1)

15

20

35

15

30

40

ns

Delay from Chip Select to Inactive
Output (HIGH-Z) (See Fig. 2)

15

30

35

15

30

45

ns

Delay from Write Enable to Inactive
Output (HIGH-Z) (See Fig. 1)

15

30

40

15

35

45

ns

Delay from Output Enable to
Inactive Output (HIGH-Z) (See Fig. 2)

15

30

35

15

30

45

ns

tpHZ(CS1, CS2)
tpLZ(CS1, CS2)
tpHZ(WE)
tpLZ(WE)
tpHZ(OE)
tpLZ(OE)

Typical characteristics are at Vee = 5.0V and TA = 25°C.
Input and output capacitance measured on a sample basis @ f = 1.0MHz.
tpLH(A) and tpHdA) are tested with Sl closed and CL = 15pF with both input and output timing referenced to 1.5V.
For open collector Am93412A/412, all delays from Write Enable (WE) or selects (CS 1, CS2, OE) inputs to the Data Output
(00-03) (tpLz(WE), tpLZ(CS1, CS2). tpLZ(OE), tpzdWE), tpZdCS1, CS2) and tpzL (OE)) are measured with Sl closed and CL = 15pF; and
with both the input and output timing referenced to 1.5V.
5. For 3-state output Am93422A/422, tpZH(WE). tPZH (CS1, CS2) and tpZH(OE) are measured with Sl open, CL = 15pF and with both the input
and output timing referenced to 1.5V. tpZL(WE), tPZdCS1, CS2) and tpZL(OE) are measured with Sl closed. CL = 15pF and with both the input
and output timing referenced to 1.5V. tpHZ(WE). tpHZ(CS1. CS2) and tPHZ(OE) are measured with Sl open and CL ~ 5pF and are measured
between the 1.5V level on the input to the VOH - 500mV level on the output. tpLZ(WE). tpLZ(CS1. CS2) and tpLZ(OE) are measured with Sl
closed and CL ~ 5pF and are measured between the 1.5V level on the input and the VOL + 500mV level on the output.

Notes: 1.
2.
3.
4.

3-49

Am93412A/422A/412/422
SWITCHING WAVEFORMS
WRITE MODE (WITH OE
CHIP
SELECT

= LOW)

KEY TO TIMING DIAGRAM

ES,
WAVEFORM

---

Ao-A7
ADDRESS
INPUTS

Ox
DATA
INPUT

WE
WRITE
ENABLE

Ox
DATA
OUTPUT

JJIIJJ

------+---~~--------~

----+-H+<

H

IPZH<§l CS2)
I pzLlCS,CS2)

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM HTO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L·TO H

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF"STATE

BPM-231

Figure 1.

READ MODE
ADD=~~~

--ADDRESS i - - I - - - - - - - - A D D R E S S k - - - - - - - - - - I - - - - - - A D D R E S S 1 - - - - - 1 . 5 V

~OR~,---~~------~--------------~Ir-----~I'-----~-----------~~--------------~-----~-------------~---~---_1------~--------1.5V

Ox
DATA OUT _____...&.1......1.&01

----------~--~~~~~====~~~
READ A LOW

OUTPUT READ A HIGH
DISABLED IN ADDRESS i

READ A HIGH
IN ADDRESS I

IN ADDRESS k

DISABLE
OUTPUT

Switching delays from address input, output enable input and the chip select inputs to the data output.
For the Am93422N422 disabled output is "OFF", represented by a single center line, For the
Am93412N412, a disabled output is HIGH.
Figure 2.

BPM-232

AC TEST LOAD AND WAVEFORM
ACTESTLOAD

INPUT PULSES

vcc~
S1

3.0V
R1
600n
GND

OUTPUT

CL

I

R2
1200n
GND

-=-

Figure 3.
BPM·233

Figure 4.
See Notes 3, 4 and 5 of Switching Characteristics.

3-50

BPM·234

Am93412A/ 422A/ 412/422
CONNECTION DIAGRAMS
Top Views
Flat Package

DIP

AJ

Vee

A2

A4

e1

A3

Chip-Pak™
L-28-2

.r

24

u

z

u

z

u

.J>

.;

A2
A,
Ao

A,

WE

Ao

~,

A6

As

Of

GNO

A6

CS 2

As

A2

WE

A,

Cs,

A7
Ao

OE

AS

CS2

DO
00

A7

03

A6

GNO

03

03

DO

O2

A7

03

00

02

NC

02

0,
NC

12

13

BPM-236

0,

NC

O2

NC

a,

u

z

~

rf

~

Note: Pin 1 is marked for orientation_

BPM-235

Speed
Selection

Open
Collector

Three-State

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

35ns

AM93412APC
AM93412APC8
AM93412ADC
AM93412ADC8
AM93412ALC
AM93412ALC8

AM93422APC
AM93422APC8
AM93422ADC
AM93422ADC8
AM93422ALC
AM93422ALC8

P-22-1
P-22-1
D-22-1
D-22-1
L-28-2
L-28-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

45ns

AM93412ADM
AM93412ADM8
AM93412AFM
AM93412AFM8
AM93412ALM
AM93412ALM8

AM93422ADM
AM93422ADM8
AM93422AFM
AM93422AFM8
AM93422ALM
AM93422ALM8

D-22-1
D-22-1
F-24-1
F-24-1
L-28-2
L-28-2

C-3
8-3
C-3
8-3
C-3
8-3

MIL

45ns

AM93412PC
AM93412PC8
AM93412DC
AM93412DC8
AM93412LC
AM93412LC8

AM93422PC
AM93422PC8
AM93422DC
AM93422DC8
AM93422LC
AM93422LC8

P-22-1
P-22-1
D-22-1
D-22-1
L-28-2
L-28-2

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

60ns

AM93412DM
AM93412DM8
AM93412FM
AM93412FM8
AM93412LM
AM93412LM8

AM93422DM
AM93422DM8
AM93422FM
AM93422FM8
AM93422LM
AM93422LM8

D-22-1
D-22-1
F-24-1
F-24-1
L-28-2
L-28-2

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Notes: 1. P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is
number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications. Pad layout and bonding
diagram available upon request.

:hip-Pak is a trademark of Advanced Micro Devices, Inc.

3-51

c
BPM-237

ORDERI'NG INFORMATION
Order Code

8

m

Am93L412A· Am93L422A
Am93L412· Am93L422
Low Power TTL 1024·Sil Bipolar 'MOX™ RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 256-word x 4-bit RAMs

The Am93L412A/L412 and Am93L422A/L422 are 1024-bit
RAMs built using Schottky diode clamped transistors in
conjunction with internal ECL circuitry and are ideal for use
in high-speed control and buffer memory applications.
Each memory is organized as a fully decoded 256-word
memory of four bits per word. Easy memory expansion is
provided by an active LOW chip select one (CS1) and an
active HIGH chip select two (CS2) as well as open collector
OR tieable outputs (Am93L412A/L412) or 3-state outputs
(Am93L422A/L422).

• High speed "A" version:
Address access time typically 30ns
Fast Standard version:
Address access time typically 45ns
• Internal ECL circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate write
recovery glitch

An active LOW write line (WE) controls the writing/reading
operation of the memory. When the chip select one (CS1)
and write line (WE) are LOW and chip select two (CS2) is
HIGH, the information on data inputs (Do through D3) is
written into the addressed memory word and preconditions
the output circuitry so that true data is present at the outputs
when the write cycle is complete. This preconditioning
operation insures minimum write recovery times by eliminating the "write recovery glitch."

• Available with 3-state outputs (Am93L422A/L422) or
with open collector outputs (Am93L412A/L412)
• 100% reliability assurance testing in compliance with
MIL-STD-883
• Electrically tested and optically inspected die for the
assemblers of hybrid products
• Plug-in replacement for Fairchild 93L412A/L412 and
93L422A/L422

Reading is performed with the chip select one (CS1) LOW
and the chip select two (CS2) HIGH and the write line (WE)
HIGH and with the output enable (0 E) Law. The information stored in the addressed word is read out on the
noninverting outputs (00 through 03).

• Power dissipation decreases with increasing
temperature
• Guaranteed to INT-STD-123 quality levels

The outputs of the memory go to an inactive highimpedance state whenever chip select one (CS1) is HIGH,
chip select two (CS2) is LOW, output enable (0 E) is HIGH,
or during the writing operation when write enable (WE)
is Law.

LOGIC BLOCK DIAGRAM

LOGIC SYMBOL

(9)
9

(11)
11

01

(15)
13

(17)
15

03

CS 2

17

(19)

19

(21)

A2

CS1
WE

1

A3

OE

18

(23) 21

A,

(4)

4

Ao

(3)

3

A1

(2)

2

(1)

20 (22)
(20)

00

10

(10)

5

As

01

12

(14)

(6)

6

A6

O2

14

(16)

(7)

7

A7

03

16

(18)

(5)

Vee = Pin 22 (24)
GND = Pin 8 (8)
BPM-137

BPM-129

IMOX is a trademark of Advanced Micro Devices, Inc.
3-52

Note: Pin numbers in parentheses "(
for 24-pin flat package.

)" indicate pinout

Am93L412A/L422A/L412/L422
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 22 to Pin 8)

-0.5 to + l.OV

DC Voltage Applied to Outputs for High Output State

-0.5V to Vee max

DC Input Voltage

-0.5 to +5.5V

Output Current, Into Outputs (Low)

20mA

DC Input Current

- 30 to + 5.0mA

FUNCTION TABLE

OPERATING RANGE

Vee

Ambient
Temperature

4.75 to 5.25V
4.5 to 5.5V

-55to +125°C

Inputs

Output

CS 2

CS 1

WE

OE

On

On

Mode

L

X

X

X

X

"HIGH Z

Not Select

X

H

X

X

X

"HIGH Z

Not Select

H

L

H

H

X

"HIGH Z

Output Disable

H

L

H

L

X

Selected Data

Read Data

H

L

L

X

L

"HIGHZ

Write "0"

H

L

L

X

H

"HIGHZ

Write "1"

H = High Voltage Level

L = Low Voltage Level

X = Don't Care

"High Z implies outputs are disabled or off. This condition is defined as a high
impedance state for the Am93L422A/L422 and as an output high level for the
Am93L412NL412.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Description

Test Conditions

Output HIGH Voltage

Vee = MIN,
VIN = VIH or Vil

IOH = -5.2mA

VOL

Output LOW Voltage

Vee = MIN,
VIN = VIH or Vil

IOl = B.OmA

VIH

Input HIGH Level (Note 3)

Guaranteed input logical HIGH voltage for all inputs

Vil

Input LOW Level (Note 3)

Guaranteed input logical LOW voltage for all inputs

III

Input LOW Current

IIH

Input HIGH Current

Ise
(Note 2)

Output Short Circuit Current

Vee = MAX, Vour = O.OV (Note 4)

VOH
(Note 2)

Min

(Note 1)

2.4

3.6
0.350

Max

Units
Volts

0.45

Volts

1.5

0.8

Volts

Vee = MAX, VIN = 0.40V

-100

-300

Ji-A

Vee = MAX, VIN = 4.5V

1

40

Ji-A

-90

rnA

2.1

55

TA"" 75°C
lee

Power Supply Current

All inputs = GND, Vee = MAX

Vel

Input Clamp Voltage

Vee = MIN, liN = -10mA

1.6

TA = -55°C

Am93L422A/L422

Vour= 0.5V,
Vee = MAX

Am93L422A/L422

Vour= 4.5V

Am93L412A/L412

75
80

TA= O°C

Vour= 2.4V

Volts

rnA

90

-50

-0.850

-1.5

0

50

0

Volts

leEX

Output Leakage Current

CIN

Input Pin Capacitance

See Note 5

4

pF

Cour

Output Pin Capacitance

See Note 5

7

pF

0

Notes: 1. Typical characteristics are at Vee = 5.0V and TA = 25°C.
2. Applies only to the Am93L422A and Am93L422 with 3-state outputs.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
4. Not more than one output should be shorted at a time. Duration of the short circuit should not be more than one second.
5. Input and output capacitance measured on a sample basis @ f = 1.0MHz.

3-53

Ji-A
100

Am93L412A/L422A/L412/L422
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwlse Noted)
Test Conditions: See Figures 3 and 4 and Notes 3, 4 and 5 (below)

Am93L412A· Am93L422A
Typ
Parameters
tpLH(A) (Note 3)

Description

(Note 1)

Min

Max

Am93L412· Am93L422

MIL

COM'L
Min

Typ

Max (Note 1)

COM'L
Min

Max

MIL
Min

Max

Units

60

75

ns

20

35

45

ns

45

25

45

50

ns

40

20

35

45

ns

Delay from Address to Output
(Address Access Time) (See Fig. 2)

30

45

55

45

Delay from Chip Select to Active
Output and Correct Data (See Fig. 2)

15

30

40

Delay from Write Enable to
Active Output and Correct Data
(Write Recovery) (See Fig. 1)

25

40

Delay from Output Enable to Active
Output and Correct Data (See Fig. 2)

15

30

ts(A)

Setup Time Address (Prior to
Initiation of Write) (See Fig. 1)

-5

5

10

-5

10

10

ns

th(A)

Hold Time Address (After
Termination of Write) (See Fig. 1)

-5

5

5

-5

5

10

ns

ts(DI)

Setup Time Data Input (Prior to
Initiation of Write) (See Fig. 1)

-5

5

5

-5

5

5

ns

th(DI)

Hold Time Data Input (After
Termination of Write) (See Fig. 1)

-5

5

5

-5

5

5

ns

t s(CS 1, CS2)

Setup Time Chip Select (Prior to
Initiation of Write) (See Fig. 1)

-5

5

5

-5

5

5

ns

th(CS1, CS2)

Hold Time Chip Select (After
Termination of Write) (See Fig. 1)

-5

5

5

-5

5

10

ns

tpw(WE)

Min Write Enable Pulse Width
to Insure Write (See Fig. 1)

15

35

40

15

45

55

ns

Delay from Chip Select to Inactive
Output (HIGH-Z) (See Fig. 2)

20

30

40

20

35

45

ns

Delay from Write Enable to Inactive
Output (HIGH-Z) (See Fig. 1)

25

35

40

30

40

45

ns

Delay from Output Enable to
Inactive Output (HIGH-Z) (See Fig. 2)

20

30

40

20

35

45

ns

tpHdA) (Note 3)
tpZH(CS1, CS2)
tpzdCS 1, CS 2)
tpZH(WE)
tpzdWE)
tpZH(OE)
tpzdOE)

tpHZ(CS1, CS2)
tpLZ( CS 1, CS2)
tPHZ(WE)
tpLZ(WE)
tpHZ(OE)
tpLZ(OE)

Typical characteristics are at Vee = 5.0V and TA = 25°C.
Input and output capacitance measured on a sample basis @ f = 1.0MHz.
tpLH(A) and tpHdA) are tested with Sl closed and C L = 15pF with both input and output timing referenced to 1.5V.
For open collector Am93L412A/L412. all delays from Write Enable (WE) or selects (CS1. CS2. OE) inputs to the Data Output
(00-03) (tpLZ(WE), tpLZ(CS 1• CS2). tPLZ(OE). tpzdWE). tpZdCS1. CS 2) and tpZL (OE)) are measured with Sl closed and CL = 15pF; and
with both the input and output timing referenced to 1.5V.
5. For 3-state output Am93L422NL422. tpZH(WE), tpzH (CS1' CS 2) and tpZH(OE) are measured with Sl open. CL = 15pF and with both the input
and output timing referenced to 1.5V. tpzdWE). tpZdCS1. CS2) and tpzdOE) are measured with Sl closed, CL = 15pF and with both the input
and output timing referenced to 1.5V. tpHZ(WE), tpHZ(CS1, CS2) and tpHZ(OE) are measured with Sl open and CL .:; 5pF and are measured
between the 1.5V level on the input to the VOH - 500mV level on the output. tpLZ(WE), tpLZ(CS1, CS2) and tpLZ(OE) are measured with Sl
closed and CL .:; 5pF and are measured between the 1.5V level on the input and the VOL + 500mV level on the output.

Notes: 1.
2.
3.
4.

3-54

Am93L412A/L422A/L412/L422
SWITCHING WAVEFORMS
WRITE MODE (WITH OE = LOW)

KEY TO TIMING DIAGRAM

CS,

CHIP
SELECT

AO-A?
ADDRESS
INPUTS

----\-L..LJI.JI

Ox
DATA
INPUT

INPUTS

OUTPUTS

--

MUST BE
STEADY

Will BE
STEADY

MAY CHANGE
FROM H TO l

Will BE
CHANGING
FROM H TO l

l/JJJJ

WE
WRITE
ENABLE

Ox
DATA
OUTPUT

WAVEFORM

---+-H+<

tpZH(~,CS2)

tPHZ@'. CS 2)
IplZ(CS,. CS 2)

t pz LlCS,CS 2 )

H

MAY CHANGE
FROM l TO H

Will BE
CHANGING
FROM l·TO H

DON'T CARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
liNE IS HIGH
IMPEDANCE
"OFF" STATE

Figure 1.

BPM-231

READ MODE
ADD~~~~

--ADDRESS i - - I - - - - - - - - A D D R E S S k - - - - - - - + _ - - - - A D D R E S S

1 - - - - - 1.5V

OEORCS,----'Ir-----~---------~Ir---'Ir---_+---------~l~-----------~----~---------~---~---_+------+_------1.5V

CS2----~-----~---------~~----~---_+-------/~--------IpZH(CS,)
tpZH(~)
IpZH(OE)

Ox
DATA OUT _ _ _ _..u.LL~

--------------~~~~~====~~~
READ A LOW

OUTPUT READ A HIGH
DISABLED IN ADDRESS i

IN ADDRESS k

READ A HIGH
IN ADDRESS I

DISABLE
OUTPUT

Switching delays from address input, output enable input and the chip select inputs to the data output.
For the Am93L422NL422 disabled output is "OFF", represented by a single center line. For the
Am93L412NL412, a disabled output is HIGH.

Figure 2.

BPM-232

AC TEST LOAD AND WAVEFORM

BPM-233

See Notes 3, 4 and 5 of Switching Characteristics.

3-55

BPM-234

Am93L412A/L422A/L412/L422
CONNECTION DIAGRAMS
Top Views
DIP

Flat Package

Vee

A3

e1

A3

Chip-Pak™
L-28-2
A4

A,
AD

WE
CS,

As

OE

CS,

A6

CS 2

A7

03

As

OE

GNO

03

A6

CS 2

00

°2

00
0,

°2
0,

A2

A4

A,

WE

AD

A7

03

GNO

03

DO

O2

00

O2

0,

0,

12

NC

~

Vee

24

A2

13

NC

g

g

.;

A2

WE

AI

CS,

AD

DE

As

CS2

A6

03

A7

03

NC

°2

NC

O2

NC

0,

BPM-236

u

z

fil

~

CI

Note: Pin 1 is marked for orientation_

BPM-235

Order Code
Open
Collector

Three-State

Package
Type

Flow Code

Operating
Range

Screening

(Note 1)

(Note 2)

(Note 3)

45ns

AM93L412APC
AM93L412APCB
AM93L412ADC
AM93L412ADCB
AM93L412ALC
AM93L412ALCB

AM93L422APC
AM93L422APCB
AM93L422ADC
AM93L422ADCB
AM93L422ALC
AM93L422ALCB

P-22-1
P-22-1
D-22-1
D-22-1
L-28-2
L-28-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

55ns

AM93L412ADM
AM93L412ADMB
AM93L412AFM
AM93L412AFMB
AM93L412ALM
AM93L412ALMB

AM93L422ADM
AM93L422ADMB
AM93L422AFM
AM93L422AFMB
AM93L422ALM
AM93L422ALMB

D-22-1
D-22-1
F-24-1
F-24-1
L-28-2
L-28-2

C-3
B-3
C-3
B-3
C-3
B-3

MIL

60ns

AM93L412PC
AM93L412PCB
AM93L412DC
AM93L412DCB
AM93L412LC
AM93L412LCB

AM93L422PC
AM93L422PCB
AM93L422DC
AM93L422DCB
AM93L422LC
AM93L422LCB

P-22-1
P-22-1
D-22-1
D-22-1
L-28-2
L-28-2

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

75ns

AM93L412DM
AM93L412DMB
AM93L412FM
AM93L412FM8
AM93L412LM
AM93L412LM8

AM93L422DM
AM93L422DMB
AM93L422FM
AM93L422FMB
AM93L422LM
AM93L422LMB

D-22-1
D-22-1
F-24-1
F-24-1
L-28-2
L-28-2

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Notes: 1_ P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F = Cerpak. Number following letter is
number of leads_
2_ Levels C-1 and C-3 conform to MIL-STD-883, Class C_
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications_ Pad layout and bonding
diagram available upon request

Chip-Pak isa trademark of Advanced Micro Devices, Inc_

3-56

~

0

BPM-237

ORDERING INFORMATION

Speed
Selection

u

SJ

Am93415A • Am93425A
Am93415 • Am93425
TTL 1024·Bif Bipolar 'MOX™ RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fully decoded 1024-word x 1-bit RAMs
• Ultra-high speed "A" version:
Address Access time typically 22ns
High Speed Standard version:
Address Access time typically 30ns
• Internal ECL circuitry for optimum speed/power
performance over voltage and temperature
• Output preconditioned during write to eliminate write
recovery glitch
• Available with three-state outputs (Am93425A/425) or
with open collector outputs (Am93415A/415)
• 100% reliability assurance testing in compliance with
MIL-STD-883
• Electrically tested and optically inspected die for the
assemblers of hybrid products
• Plug in replacement for Fairchild 93415A/415 and
93425A/425
• Power dissipation decreases with increasing
temperature
• Guaranteed to INT-STD-123 quality levels

The Am93415A/415 and Am93425A/425 are 1024-bit
RAMs built using Schottky diode clamped transistors in
conjunction with internal ECL circuitry and are ideal for use
in high-speed control and buffer memory applications.
Each memory is organized as a fully decoded 1024-word
memory of 1 bit per word. Easy memory expansion is provided by an active LOW chip select (CS) input and open
collector OR tieable outputs (Am93415A/415) or three-state
outputs (Am93425A/425). Chip selection for large memory
systems can be controlled by active LOW output decoders
such as the Am74S138.
An active LOW write line (WE) controls the writing/reading
operation of the memory. When the chip select and write
lines are LOW the information on the data input (DIN) is
written into the addressed memory word and preconditions
the output circuitry so that true data is present at the outputs
when the write cycle is complete. This preconditioning
operation insures minimum write recovery times by eliminating the "write recovery glitch."
Reading is performed with the chip select line LOW and the
write line HIGH. The information stored in the addressed
word is read out on the noninverting output (DOUT).

LOGIC SYMBOL
15

Ao

During the writing operation or when the chip select line is
HIGH the output of the memory goes to an inactive high
impedance state.

14

cs

A1

LOGIC BLOCK DIAGRAM

A2
A3
A4
As

10

A6

11

A7

12

As

AO

13

A,
A,
A3

Ag

ADDRESS
DECODER

WORD
DRIVERS

A4

DOUT

Vee =

Pin 16
GND = Pin8
BPM-050

CONNECTION DIAGRAMS - Top Views
DIP

Chip-Pak™
Vee

!v~

DIN

o~~~

WE
Ag
As
A7
A6

~~~

~

~

As

BPM-051

BPM-049

Note: Pin 1 is marked for orientation

IMOX is a trademark of Advanced Micro Devices, Inc.
Chip-Pak is a trademark of Advanced Micro Devices, Inc.

3-57

Am93415A/425A/415/ 425
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65to +150°C

Temperature (Ambient) Under Bias

-55 to +125°C

Supply Voltage to Ground Potential (Pin 16 to Pin 8)

-0.5 to +7V

DC Voltage Applied to Outputs for High Output State

-0.5V to VCC max
-0.5 to +5.5V

DC Input Voltage
Output Current, Into Outputs (Low)

20mA

DC Input Current

-30to +5.0mA

FUNCTION TABLE

OPERATING RANGE
Ambient
Temperature

Output

Inputs

Mode

CS

WE

DIN

DOUT

H

x

X

*HIGH-Z

Not Selected

L

L

L

*HIGH-Z

Write "0"

L

L

H

*HIGH-Z

Write "1"

X

Selected
Data

Read

-55 to +125°C

L

H

H = High Voltage Level

L = Low Voltage Level

X = Don't Care

*HIGH-Z implies outputs are disabled or off. This condition is defined as a
high impedance state for the Am93425A/425 and as an output high level
for the Am93415A/415.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Typ
Parameters

Test Conditions

Description

VOH
(Note 2)

Output HIGH Voltage

VOL

Output LOW Voltage

IOH = -10.3mA

Vee = MIN,
VIN = VIH orVll

IOH

Vee = MIN,
VIN = VIH or Vil

= -5.2mA

ICOM'L
IMIL

Min

(Note 1)

2.4

3.6

0.350

IOl == 16mA

VIH

Input HIGH Level (Note 3)

Guaranteed input logical HIGH voltage for all inputs

Vil

Input LOW Level (Note 3)

Guaranteed input logical LOW voltage for all inputs

III

Input LOW Current

IIH

Input HIGH Current

= MAX, VIN = 0.40V
Vee = MAX, VIN = 4.5V

Ise
(Note 2)

Output Short Circuit Current

Vee

lee

Power Supply Current

All inputs = GND, Vee

2.1

Vee

TA ",,75°C

Vel

leEX

CIN
COUT

Volts
0.8

Volts

-180

-400

f.LA

1

40

f.LA

-100

rnA

95

110
125
145

= MIN, liN = -10mA

Vee

Output Leakage Current

Vcs = VIH or VWE = Vil
VOUT = 2.4V

Am93415A/425A
Am93415/425

Vc§ = VIH or VWE
VOUT = O.5V, Vee

Am93425A
Am93425

Volts

1.5

TA == -55°C
Input Clamp Voltage

= Vil
= MAX

0.45

= O°C

TA

Units
Volts

1.6

= MAX, VOUT = O.OV

= MAX

Max

-0.850

-1.5

0

100

rnA

Volts

f.LA
-50

0

Input Pin Capacitance

See Note 4

4

pF

Output Pin Capacitance

See Note 4

7

pF

Notes: 1. Typical limits are at Vee = 5.0V and TA = 25°C.
2. This applies only to the Am93425A/425 with three-state outputs.
3. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt
to test these values without suitable equipment.
4. Input and output capacitance measured on a sample basis using pulse technique.

3-58

Am93415A/ 425A/ 415/ 425
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
Test Conditions; See Figures 3 and 4 and Notes 2, 3, and 4 (below)
Am93415A· Am93425A

COM'L
(Note 1) Min Max
Typ

Parameters
tpLH(A)

Description

Am93415· Am93425

MIL
Typ
COM'L
Min Max (Note 1) Min Max

MIL
Min Max

Units

Delay from Address to Output
(Address Access Time)

See Fig. 2

22

30

40

30

45

60

ns

Delay from Chip Select to
Active Output and Correct Data

See Fig. 2

10

20

30

15

35

45

ns

Delay from Write Enable to
Active Output and Correct Data
(Write Recovery)

See Fig. 1

10

25

35

15

40

50

ns

ts(A)

Setup Time Address (Prior
to Initiation of Write)

See Fig. 1

0

5

5

0

10

15

ns

th(A)

Hold Time Address (After
Termination of Write)

See Fig. 1

0

5

5

0

5

5

ns

ts(DI)

Setup Time Data Input (Prior
to Initiation of Write)

See Fig. 1

0

5

5

0

5

5

ns

th(DI)

Hold Time Data Input (After
Termination of Write)

See Fig. 1

0

5

5

0

5

5

ns

ts(CS)

Setup Time Chip Select
(Prior to Initiation of Write)

See Fig. 1

0

5

5

0

5

5

ns

th(CS)

Hold Time Chip Select
(After Termination of Write)

See Fig. 1

0

5

5

0

5

5

ns

tpw(WE)

Min Write Enable Pulse Width
to Insure Write

See Fig. 1

12

20

30

15

30

40

ns

Delay from Chip Select
to Inactive Output (HIGH-Z)

See Fig. 2

10

20

30

15

35

50

ns

Delay from write Enable
to Inactive Output (HIGH-Z)

See Fig. 1

10

20

30

15

35

35

ns

tpHdA)
tpZH(CS)
tpzdCS)
tpZH(WE)
tpzdWE)

tpHZ(CS)
tpLZ(CS)
tpHZ(WE)
tpLZ(WE)

Notes: 1. Typical characteristics are at Vee = 5.0V and TA = 25°C.
2. tpLH(A) and tpHdA) are tested with S1 closed and CL = 30pF with both input and output timing referenced to 1.5V.
3. For open collector Am93415N415, all delays from Write Enable (WE) or Chip Select (CE) inputs to the Data Output (DOUT), tpLZ(WE),
tpLZ(CS), tpzdWE) and tpzdCS) are measured with S1 closed and CL = 30pF; and with both the input and output timing referenced to 1.5V.
4. For 3-state output Am93425N425, tpZH(WE) and tpZH(CS) are measured with S1 open, CL = 30pF and with both the input and output timing
referenced to 1.5V. tpzdWE) and tpzdCS) are measured with S1 closed, CL = 30pF and with both the input and output timing referenced to
1.5V. tpZH(WE) and tpHZ(CS) are measured with S1 open and CL '" 5pF and are measured between the 1.5V level on the input to the VOH
-500mV level on the output. tpLZ(WE) and tpLZ(CS) are measured with S1 closed and CL '" 5pF and are measured between the 1.5V level on
the input and the VOL + 500mV level on the output.

3-59

Am93415A/425A/ 415/ 425
SWITCHING WAVEFORMS
KEY TO TIMING DIAGRAM

WRITE MODE
Cs

WAVEFORM

CHIP
SELECT

--

AO-A9
ADDRESS
INPUTS

JJJJJJ

---

WE
WRITE
ENABLE

DOUT

H

DATA ----+-~~
OUTPUT

tpHZ(~)

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L·TO H

DON'TCARE;
ANY CHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

tpLZ(CS)

Figure 1.

BPM-052

READ MODE
AD~:~!~

_ _ ADDRESS j

- _ - 1 -_ _ _ _ _ _ _ _

ADDRESS k

--------+-----

ADDRESS I - - - - - - 1.5V

~---+-----~---------_+----~----_7-------~------- 1.5V

DATA OUT ---~..............

OUTPUT
DISABLED

READ A HIGH
IN ADDRESS j

READ A LOW IN
ADDRESS k

DISABLE
OUTPUT

ENABLE
OUTPUT

READA HIGH
IN ADDRESS I

DISABLE
OUTPUT

Switching delays from address and chip select inputs to the data output. For the Am93425A/425 disabled
output is "OFF", represented by a single center line. For the Am93415A/415 a disabled output is HIGH.

Figure 2.

BPM-053

AC TEST LOAD AND WAVEFORM
ACTESTLOAD

INPUT PULSES

VCC~
Sl

3.0Vp-p
R1
300n
GND

OUTPUT
3.0Vp-p
CL

BPM-054

R2

I

Goon
BPM-055

GND

Figure 3.

Figure 4.
See Notes 2, 3, and 4 of Switching Characteristics.

3-60

Am93415A/425A/415/425
ORDERING INFORMATION
Order Code

Package
Type

Screening
Flow Code

Operating
Range

Three-State

(Note 1)

(Note 2)

(Note 3)

AM93425APC
AM93425APC8
AM93425ADC
AM93425ADC8
AM93425ALC
AM93425ALCB

P-16-1
P-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory

C-1
8-1
C-1
8-1
C-1
B-1

COM'L

AM93425ADM
AM93425ADM8
AM93425AFM
AM93425AFM8
AM93425ALM
AM93425ALM8

D-16-1
D-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
8-3
C-3
8-3
C-3
8-3

MIL

45ns

AM93415PC
AM93415PC8
AM93415DC
AM93415DC8
AM93415LC
AM93415LC8

AM93425PC
AM93425PC8
AM93425DC
AM93425DC8
AM93425LC
AM93425LC8

P-16-1
P-16-1
D-16-1
D-16-1
Consult Factory
Consult Factory

C-1
8-1
C-1
8-1
C-1
8-1

COM'L

60ns

AM93415DM
AM93415DM8
AM93415FM
AM93415FM8
AM93415LM
AM93415LM8

AM93425DM
AM93425DM8
AM93425FM
AM93425FM8
AM93425LM
AM93425LM8

D-16-1
D-16-1
F-16-1
F-16-1
Consult Factory
Consult Factory

C-3
8-3
C-3
8-3
C-3
8-3

MIL

Speed
Selection

Open
Collector

30ns

AM93415APC
AM93415APC8
AM93415ADC
AM93415ADC8
AM93415ALC
AM93415ALC8

40ns

AM93415ADM
AM93415ADM8
AM93415AFM
AM93415AFM8
AM93415ALM
AM93415ALM8

Notes: 1, P = Molded DIP, D = Hermetic DIP, L = Chip-Pak, F == Cerpak, Numberfoliowing letter is number of leads.
2. Levels C-1 and C-3 conform to MIL-STD-883, Class C.
Levels 8-1 and 8-3 conform to MIL-STD-883, Class 8.
3. See Operating Range Table.
This device is also available in die form selected to commercial and military specifications.
Pad layout and bonding diagram available upon request.

3-61

Am10415SA •
Am10415A • Am10415
EeL 1024 x 1 IMOX™ Bipolar RAM

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time (10ns typ.) - improves system
cycle speeds
• Fully compatible with standard voltage compensated
10K series ECl - no board changes required
• Internally voltage compensated providing flat AC
performance
• Outputs preconditioned during write cycle eliminating
write recovery glitch
• 100% Mll-STD-883C screening and guaranteed to
INT-STO-123 insures the highest reliability
• Emitter follower outputs - easy wire-ORing
• Power dissipation decreases with increasing
temperature

The Am10415SA, Am10415A and Am10415 are fully decoded 1024-bit ECl RAMs organized 1024 words by one bit.
Bit selection is achieved by means of a 10-bit address, Ao
through Ag. Easy memory expansion is provided by an active
lOW chip select (CS) input and an unterminated OR tieable
emitter follower output.
An active lOW write line (WE) controls the write/read operation of the memory. When the chip select and write lines are
lOW, the data input (DIN) is written into the addressed
memory word simultaneously preconditioning the output so
true data is present when the write cycle is complete. This
preconditioning operation insures minimum write recovery
times by eliminating the "write recovery glitch".
Reading is performed with the chip select line lOW and the
write line HIGH. The information stored in the addressed
word is read out on the noninverting output (DOUT).
During the writing operation or when the chip select line is
HIGH the output of the memory goes to a lOW state.

BLOCK DIAGRAM
.-----------~--~~~--~

ROW
DECODER

BPM·212

CONNECTION DIAGRAMS - Top Views
DIP
Dour

Vee

AD

DIN

A1

cs

A2

WE

A3

Ag

A4

As

As

AT

VEE

LOGIC SYMBOL

Chip-Pak™

14

cs

~~
o.I/

\.1.lYYXY'

I IXXI-lE/.A7\NIJI\.

\.IIIX

xxxxx

[IIII

/.1u.MA\.

IXXIIIII 1/
IX
IIIIIIII"I\.

\.

IXIXIIII

/.

IX

II:';'\,

IWHO

Iwso
I-Iw-

WE
WRITE
ENABLE

\-

_1\

I-IWSA

I

J~

IWHA_

IwscS
DOUT
DATA
OUTPUT

IIXIJ

IWHCS

111/

\\\\,
'\'\'\1\

1111

f--IACS--

I-IWS--/

////

\\\\,

I-IWR-

_IRCS-!

'\'\'\1\

1111

Figure 2.

BPM-192

KEY TO TIMING DIAGRAM

WAVEFORM

-J!JIff

INPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

--

OUTPUTS

WAVEFORM

INPUTS

OUTPUTS

DON'T CARE;
ANYCHANGE
PERMITTED

CHANGING;
STATE
UNKNOWN

WILL BE
CHANGING
FROM L TO H

BPM-193

3-72

Am100415A/415
ORDERING INFORMATION

Speed
Selection

Order Code

Package
Type

Screening
Flow Code

Operating
Range

(Note 1)

(Note 2)

(Note 3)

15ns

AM100415APC
AM100415APCB
AM100415AOC
AM100415AOCB
AM 100415ALC
AM100415ALCB

P-16-1
P-16-1
0-16-1
0-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

20ns

AM100415PC
AM100415PCB
AM1004150C
AM1004150CB
AM100415LC
AM100415LCB

P-16-1
P-16-1
0-16-1
0-16-1
Consult Factory
Consult Factory

C-1
B-1
C-1
B-1
C-1
B-1

COM'L

Notes: 1. P = Molded DIP, 0 = Hermetic DIP, L = Chip-Pak. Number following letter is number
of leads.
2. Levels C-1 and C-3 conform to MIL-STO-123, Class C.
Levels B-1 and B-3 conform to MIL-STO-123, Class B.
3. See Operating Range Table.
This device is also available in die form selected to commercial specifications. Pad layout and
bonding diagram available upon request.

3-73

Am10474SA· Am10474A
Am10474
Eel. 1024 x 4 'MOX™ Bipolar RAM
ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time (12ns typ) - improves system
cycle speeds
• Fully compatible with standard voltage compensated
10K series ECl - no board changes required
• Internally voltage and temperature compensated
providing flat AC performance
• 100% Mll-STO-883C screening and guaranteed to
INT -STO-123 insures the highest reliability
• Emitter follower outputs - easy wire-ORing
• Power dissipation decreases with increasing
temperature

The Am10474SA, Am10474A and Am10474 are fully decoded 4096-bit ECl RAMs organized 1024 words by 4 bits.
Word selection is achieved by means of a 10-bit address,
Ao through Ag. Easy memory expansion is provided by an
active LOW chip select (CS) input and an unterminated OR
tieable emitter follower output.

LOGIC BLOCK DIAGRAM

An active lOW write line (WE) controls the write/read operation of the memory. When the chip select and write lines
are lOW, the data input (01-04) are written into the addressed memory words.
Reading is performed with the chip select line lOW and the
write line HIGH. The information stored in the addressed
word is read out on the noninverting outputs 01-04.
Ouring the writing operation or when the chip select line is
HIGH the output of the memory goes to a lOW state.
LOGIC SYMBOL

A4
Ao

A5

17

18

19

20

21

16

CS

01

02

03

04 WE

A1

A6

A2

A7

A3

As

A4

Ag

1024 x 4
ECLRAM

A5
11

A6

13

A7

14

As

15

Ag

22

23

2

3

BPM-368

DIP

CONNECTION DIAGRAMS - Top Views

Chip-Pak™

Note: Pin 1 is marked for orientation.
IMOX is a trademark of Advanced Micro Devices, Inc.

VCC2 = Pin 24
VEE = Pin 12

BPM-369

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

3-74

Am100474SA· Am100474A
Am100474
Eel. 1024 x 4 'MOX"''' Bipolar RAM
ADVANCED INFORMATION
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time (12ns typ) - improves system
cycle speeds
• Fully compatible with 100K series ECl logic - no board
changes required
• Enhanced output voltage level compensation providing
6X (improvement in) VOL and VOH stability over supply
and temperature ranges
• Internally voltage and temperature compensated
providing flat AC performance
• 100% MIL-STO-883C screening and guaranteed to
INT-STO-123 insures the highest reliability
• Emitter follower outputs - easy wire-ORing
• Power dissipation decreases with increasing
temperature

The Am100474SA, Am100474A and Am100474 are fully
decoded 4096-bit ECl RAMs organized 1024 words by 4
bits. Word selection is achieved by means of a lO-bit address, Ao through Ag. Easy memory expansion is provided
by an active LOW chip select (CS) input and unterminated
OR tieable emitter follower outputs.

Reading is performed with the chip select line LOW and the
write line HIGH. The information stored in the addressed
words is read out on the noninverting outputs 01-04.

LOGIC BLOCK DIAGRAM

During the writing operation or when the chip select line is
HIGH the output of the memory goes to a lOW state.

An active lOW write line (WE) controls the write/read operation of the memory. When the chip select and write lines
are lOW, the data inputs (01-04) are written into the addressed memory words.

LOGIC SYMBOL

A4
As
As
A7
As
Ag

AO

BPM-364

DIP

AI

A2

Ao

11

A,

12

A2

13

A3

14

A4

15

As

17

As

19

A7

20

As

21

Ag

0,

°3

cs

°4

WE

0,

Ag

°2

As

Vce

A7

As

°4

NC

Ao

As

AI

A4

Az

A3

1

2

3

CS

0,

02

03

04 WE

'02414
ECLRAM

0,

°2

03

°4

4

5

8

9

BPM-365

Chip-Pak™

~~

o~~~

~~~

VEE

°3

24

A3

CONNECTION DIAGRAMS - Top Views

°2

VCCA

10

Q~

Note: Pin 1 is marked for orientation.
IMOX is a trademark of Advanced Micro Devices, Inc.

22

23

BPM-366

Chip-Pak is a trademark of Advanced Micro Devices, Inc.

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to
evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

3-75

Am10470SA·
Am10470A·
Am10470
x
EeL 4096

1 IMOX™ Bipolar RAM

PRELIMINARY
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Fast access time (12ns typ) - improves system
cycle speeds
• Fully compatible with standard voltage compensated
10K series ECl - no board changes required
• Internally voltage compensated providing flat
AC performance
• Outputs preconditioned during write cycle eliminating
write recovery glitch
• 100% Mll-STD-883C screening and guaranteed to
INT-STD-123 insures the highest reliability
• Emitter follower outputs - easy wire-ORing
• Power dissipation decreases with increasing
temperature

The Am10470SA, Am10470A and Am10470 are fully decoded 4096-bit ECl. RAMs organized 4096 words by one
bit. Bit selection is achieved by means of a 12-bit address,
Ao through A11. Easy memory expansion is provided by an
active lOW chip select (CS) input and an unterminated OR
tieable emitter follower output.
An active lOW write line (WE) controls the write/read operation of the memory. When the chip select and write lines
are lOW, the data input (DIN) is written into the addressed
memory word simultaneously preconditioning the output so
true data is present when the write cycle is complete. This
preconditioning operation insures minimum write recovery
times by eliminating the 'write recovery glitch.'
Reading is performed with the chip select line lOW and the
write line HIGH. The information stored in the addressed
word is read out on the noninverting output (DOUT).
During the writing operation or when the chip select line is
HIGH the output of the memory goes to a lOW state.

BLOCK DIAGRAM
r---------~------ DOUT

ROW
DECODER

BPM-299

LOGIC SYMBOL

CONNECTION DIAGRAMS - Top Views
DIP

Chip-Pak™

DOUT

Vee

Ao

DIN

Al

~

A2

WE

A3

All

~

Al0

As

At

At

At

VEE

A7

~(§>

o

1.4

I

200

~
1.2

~

240

~

~

./

220

Y

c

I
~

./

200
180

150

V'

./

/

160
1.0
0

25

50

TA - AMBIENT TEMPERATURE _ °c

75

100

o

140
25

50

75

TA - AMBIENT TEMPERATURE - °c

o

100

200

300

400

500

600

CL -pF

MOS-349

4-6

Am9111/Am91
L11 IAm2111 Family
x
256

Part
Number

Access
Time

4 Static R/W Random Access Memories

Am2111

Am2111-2

Am9111A
Am91L11A
Am2111-1

Am9111B
Am91L 11B

1000ns

650ns

500ns

400ns

Am9111C
Am91L11C

Am9111D

250ns

300ns

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• 256 x 4 organization for small memory systems
• Low operating power dissipation
125mW typ; 290mW maximum - standard power
100mWtyp; 175mWmaximum -Iowpower
• DC standby mode reduces power up to 84%
• Logic voltage levels identical to TTL
• High output drive - two full TTL loads
• High noise immunity - full 400mV
• Single +5 volt power supply - tolerances ±5%
commercial, ±10% military
• Uniform switching characteristics - access times
insensitive to supply variations, addressing patterns
and data patterns
• Both military and commercial temperature ranges
available
• Bussed input and output data on common pins
• Output disable control
• Zero address setup and hold times for simplified timing
• 100% MIL-STD-883 reliability assurance testing

The Am9111/Am91L 11 series of devices are highperformance, low-power, 1024-bit, static, read/write random access memories. They offer a wide range of access
times including versions as fast as 200ns. Each memory is
implemented as 256 words by 4 bits per word. This organization permits efficient design of small memory systems
and allows finer resolution of incremental memory depth.
The input data and output data signals are bussed together
to share common I/O pins. This feature not only decreases
the package size, but also helps eliminate external logic in
bus-oriented memory systems.
These memories may be operated in a DC standby mode
for reductions of as much as 84% of the normal power dissipation. Data can be retained with a power supply as low
as 1.5 volts. The low power Am91 L 11 series offer reduced
power dissipation during normal operating conditions and
even lower dissipation in the standby mode.
The Chip Enable input control signals act as high order
address lines and they control the write amplifier and the
output buffers. The Output Disable signal provides independent control over the output state of enabled chips.
These devices are fully static and no refresh operations,
sense amplifiers or clocks are required. Input and output
signal levels are identical to TTL specifications, providing
simplified interfacing and high noise immunity. The outputs
will drive two full TTL loads for increased fan-out and better
bus interfacing capability.

CONNECTION DIAGRAM
Top View

Am9111 BLOCK DIAGRAM

r---

110-

_0

A1 -

§§

-

~~

A3 -

15~

A

2

A4_

32 X 8

32 X 8

32 X 8

32 X 8

STORAGE

STORAGE

STORAGE

STORAGE

ARRAY

ARRAY

ARRAY

ARRAY

ADDRESS3[
ADDRESS2[

a:~

~
1lB PV

17 PADDRESS4

ADDRESS 1 [

3

16 P

ADDRESS 0 [

4

15

ADDRESS 5 [

5

141J DATA 1/°4

'---

AS-------I
A6-------l
A7

COLUMN DECODER/INPUT CONTROL!
OUTPUT BUFFERS/SELECT LOGIC/
DISABLE LOGIC

-------1

L--.rt---r-t

-........--It

--r--

1/0 1

1/0 2

t

1/03

WRITE ENABLE

~ CHIP ENABLE

6[

6

131J DATA 1/03

ADDRESS 7 [

7

12

IGND) VSS [

8

11

OUTPUT DISABLE [

9

10

ADDRESS

I-WE
I-m
I-cn
I - OD

cc l+5V)

2

1

IJ
P

DATA 1/°2
DATA 1/° 1

P

CHIP ENA8LE 2

I/D4

MOS-351

MOS-350

4-7

Am9111/Am91L11/Am2111 Family

MAXIMUM RATINGS above which the useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
VCC With Respect to VSS, Continuous

-O.5V to +7.0V
-O.5V to +7.0V

DC Voltage Applied to Outputs
DC Input Voltage

-O.5V to +7.0V

Power Dissipation

1.0W

ELECTRICAL CHARACTERISTICS
Am9111PC
Am91 L 11 PC
Am2111

TA=O°Cto+70oC
V CC = +5.0V ±5%

Parameters

Description

Am9111/
Am91L11
Family
Min. Max.

Test Conditions
10H = -200.uA

VOH

Output HIGH Voltage

Vee= MIN.

VOL

Output LOW Voltage

Vee = MIN.

Am2111
Family
Min. Max.

2.4

10H = -150.uA

Volts

2.2

10L = 3.2mA

Units

0.4

Volts

10L = 2.0mA

0.45

VIH

Input HIGH VoTtage

2.0

Vee

2.2

Vec

Volts

VIL

Input LOW Voltage

-0.5

0.8

-0.5

0.65

Volts

III

Input Load Current

10

10

.uA

VOUT= VCC

5.0

15

VOUT = O.4V

-10

-50

Am9111A/B

50

ILO

I/O Leakage Current

VCC = MAX., OV

~

VIN

~

5.25V

VeE = VIH

T A = 25°C

ICCl

Power Supply Current

Data out open
VCC = Max.
VIN = VCC

ICC2

TA = O°C

Am9111 C/D/E

55

Am91 LllA/B

31

Am91L11C

34

Am9111A/B

55

Am9111 C/D/E

60

Am91 L11A/B

33

Am91L11C

36

ELECTRICAL CHARACTERISTICS
Am9111DM
Am91L11DM

Description

60

mA

70

Am9111/
Am91L 11
Family

TA = _55°C to +125°C
vcc = +5.0V ±10%

Parameters

.uA

Test Conditions

Min.
VCC = 4.75V

2.4

VCC = 4.5V

2.2

Max.

Units

VOH

Output HIGH Voltage

VOL

Output LOW Voitage

VIH

Input HIGH Voltage

2.0

VCC

Volts

VIL

Input LOW Voltage

-0.5

0.8

Volts

III

Input Load Current

10

.uA

ILO

Output Leakage Current

10H = -200j.LA
VCC = MIN., 10L = 3.2mA

0.4

VCC = MAX., OV.;; VIN .;; 5.5V
Vcr = VIH

TA = 25°C

ICCl

Power Supply Current

Data out open
VCC = Max.
VIN = VCC
TA = _55°C

ICC3

Volts

VOUT = VCC

10

VOUT = O.4V

-10

Am9111A!Am9111 B

50

Am9111C

55

Am91 LllA/Am91LllB

31

Am91 L11C

34

Am9111 A/ Am9111 B

60

Am9111C

65

Am91 L11A/Am91L11B

37

Am91L11C

40

Volts

.uA

mA

CAPACITANCE
Parameters
CIN

Description
Input Capacitance, VIN = OV

T A = 25°C, f = 1 mHz
COUT

Typ.

Max.

Am2111

4.0

8.0

Am9111/Am91 L11

3.0

6.0

Am2111

10

15

Am9111/Am91 L11

8.0

11

Test Conditions

Output Capacitance, VOUT = OV

4-8

Units
pF

pF

Am9111/Am91 L11/Am2111 Family
SWITCHING CHARACTERISTICS

over operating temperature and voltage range

Output Load = 1 TTL Gate + 100pF
TA = 0 to 70°C
Transition Times = 10ns
TA = -55 to +125°C
Input Levels, Output References = 0.8V and 2.0V

2111

Parameters

Description

Vee = +5V ±5%
Vee = +5V ±10%

2111-2

9111A
91L11A

2111-1

91118
91Ll18

9111C
91L11C

91110

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units

tAe

Read Cycle Time

tA

Access Time

1000

650

500

500

400

300

250

ns

teo

Chip Enable to Output
ON Delay (Note 1)

800

400

350

200

175

150

125

ns

too

Output Disable to Output
ON Delay

700

350

300

175

150

125

100

ns

toH

Previous Read Data Valid with
Respect to Address Change

0

tOFl

Output Disable to Output
OFF Delay

0

200

0

150

0

150

5.0

125

5.0

100

5.0

100

5.0

75

ns

tOF2

Chip Enable to Output
OFF Delay

0

200

0

150

0

150

10

150

10

125

10

125

10

100

ns

twe

Write Cycle Time

1000

650

500

500

400

300

250

ns

tAW

Address Set-up Time

150

150

100

0

0

0

0

ns

twp

Write Pulse Width

750

400

300

175

150

125

100

ns

tew

Chip Enable Set-up Time
(Note 1)

900

550

400

175

150

125

100

ns

tWA

Address Hold Time

50

50

50

0

0

0

0

ns

tow

Input Data Set-up Time

700

400

280

150

125

100

85

ns

tOH

Input Data Hold Time

100

100

100

0

0

0

0

ns

1000

650

500

0

400

500

40

0

300

40

250

40

ns

ns

30

Note: 1. Both CE1 and CE2 must be LOW to enable the chip.

SWITCHING WAVEFORMS

READ CYCLE

WRITE CYCLE

1-1·-------tRC--------t-I-------twc--------,,.........--i1
ADDRESS

~---------..,~r------------,C

I

CHJPENABLE
CHIP
ENABLE 21
(NOTE 11

I
WRITE ENABLE

I

f

~\

I

I

~tAW '1

~r-:---~I-.---------~I----I--"""\\

tco~
OUTPUT DISABLE

-tI

t

cw

I
;"""---J-

,

twp

I

tWR

fr------

tPF2~1

L'"---'' ---1-~~
I

---t-I--I '"

DATA 1/0

1-------tA--------l

MOS·352

4-9

Am9111/Am91L11/Am2111 Family
tco Access Time from Chip Enable. The minimum time during
which the chip enable must be LOW prior to reading data on
the output.
tOH Minimum time which will elapse between change of
address and any change of the data output.
tOF1 Time delay between output disable HIGH and output
data float.
tOF2 Time delay between chip enable OFF and output data
float.

DEFINITION OF TERMS
FUNCTIONAL TERMS
CE1, CE2 Chip Enable Signals. Read and Write cycles can be
executed only when both CEl and CE2 are LOW.
WE Active LOW Write Enable. Data is written into the memory
if WE is LOW and read from the memory if WE is HIGH.
Static RAM A random access memory in which data is stored
in bistable latch circuits. A. static memory will store data as
long as power is supplied to the chip without requiring any
special clocking or refreshing operations.

twe Write Cycle Time. The minimum time required between
successive address changes while writing.
tAW Address Set-up Time. The minimum time prior to the
falling edge of the write enable during which the addr~ss inputs
must be correct and stable.
twp The minimum duration of a LOW level on the write enable
guaranteed to write data.
tWR Address Hold Time. The minimum time after the rising
edge of the write enable during which the address must remain
steady.
tow Data Set-up Time. The minimum time that the data input
must be steady prior to the rising edge of the write enable.
tOH Data Hold Time. The minimum time that the data input
must remain steady after the rising edge of the write enable.
tew Chip Enable Time during Write. The minimum duration
of a LOW level on the Chip Select prior to the rising edge of
WE to guarantee writing.

N-Channel An insulated gate field effect transistor technology
in which the transistor source and drain are made of N-tvpe
material, and electrons serve as the carriers between the two
regions. N-Channel transistors exhibit lower thresholds and
faster switching speeds than P-Channel transistors.
SWITCHING TERMS
too Output enable time. Delay time from falling edge of 00
to output on.
tRC Read Cycle Time. The minimum time required between
successive address changes while reading.
tA Access Time. The time delay between application of an
address and stable data on the output when the chip is enabled.

4-10

Am9111/Am91L11/Am2111 Family
POWER DOWN STANDBY OPERATION
The Am9111/Am91 L11 Family is designed to maintain
storage in a standby mode. The standby mode is entered by
lowering VCC to around 1.5-2.0 volts (see table and graph
below). When the voltage to the device is reduced, the
storage cells are isolated from the data lines, so their
contents will not change. The standby mode may be used
by a battery operated backup pewer supply system, or, in a

large system, memory pages not being accessed can be
placed in standby to save power. A standby recovery time
must elapse following restoration of normal power before
the memory may be accessed.
To ensure that the output of the device is in a high impedance OFF state during standby, the chip select should
be held at VIH or VCES during the entire standby cycle.

STANDBY OPERATING CONDITIONS OVER TEMPERATURE RANGE
Parameters

Description

Min.

Typ.

Max.

Am91L11
Am9111
Am91L11

11
13
13

25
31
31

Am9111
Am91L11
Am9111
Am91L11
Am9111

17
11
13
13
17

41

Test Conditions

vee in Standby Mode

VPD

VPD = 1.5V

TA = o°c
All Inputs = VPD

VPD = 2.0V

ICC in Standby Mode

IpD

VPD = 1.5V
TA = -55°C
All Inputs = VPD
dv/dt
tR

VPD = 2.0V

Rate of Change of VCC
Standby Recovery Time
Chip Deselect Time
CE Bias in Standby

tcP
VCES

25

INPUTS = 5.0V
Am9111

E
I

1l
RECOVERY

15

ns
ns
Volts

24
22

18

VCC (+5VI

ADDRESS 2

17

ADDRESS 4

16

WRITE ENABLE

15

CHIP ENABLE 1

14
5

ADDRESS6

6

DATA 1/04

I
J:

_0
I

0

z

«

18
16

/\
/ \

14
12

I

I

10

0

Vee =,4.75V

~~ow

:;:

STATE

2

TA = 25'e

\

\

I

8

..J

,

HIGH

1\ STATE
\.
'\.

"k.

oo
Vee - VOLTS

VOUT- VOLTS

Access Time
Versus Vee Normalized
to Vce = +5.0 Volts

Typical Power Supply Current
Versus Ambient Temperature

-- ---

30
28

TA=1 70'e
1.0

J

/'
\/

4

1.05

~

«

\

20

o

3

4

«

E

f
I

10

Metallization and Pad Layout

ADDRESS 5

V/J.l.s

Typical Output Current
Versus Voltage

/
o

READ OR
WRITE
CYCLE

ADDRESS 3

f..---

~

-'

/l.-J"

20

«

ADDRESSO

mA

VPD

TA =25°e

ADDRESS 1

28
34
34
46
1.0

0

30

STANDBY MODE

mA

tRC

Typical Power Supply Current
Versus Voltage

DESELECT
CHIP

Units

1.5

0.95

26

I

~

24

~

22

I

20

.::>

18

u

Vee=MAX.-

......... r--

-.......... r-.

--

16
0.90

14
12

13

DATA 1/03

12

DATA 1/02

IGNDI VSS

' - -_ _ _ _ 11

DATA 1/01

OUTPUT
DISABLE

L-------10

0.85
4.0

10
4.5

5.0
Vee- VOLTS

5.5

6.0

o

75
50
25
TA - AMBIENT TEMPERATURE _ 'e

CHIP ENABLE 2

DIE SIZE: 0.132" X 0.131"
MOS-354

4-11

Am9111/Am91L11/Am2111 Family
Am9111 FAMILY -APPLICATION INFORMATION

directly to such a processor since the common I/O pins act as
a bidirectional data bus.

These memory products provide all of the advantages of
AMD's other static N-channel memory circuits: +5 only power
supply, all TTL interface, no clocks, no sensing, no refreshing,
military temperature range available, low power versions available, high speed, high output drive, etc. In addition, the
Am9111 series features a 256 x 4 organization with common
pins used for 'both Data In and Data Out signals.

The Output Disable control signal is provided to prevent signal
contention for the bus lines, and to simplify tri-state bus
control in the external circuitry. If the chip is enabled and the
output is enabled and the memory is in the Read state, then the
output buffers will be impressing data on the bus lines. At
that point, if the external system tries to drive the bus with
data, in preparation for a write operation, there will be conflict
for domination of the bus lines. The Output Disable signal
allows the user direct control over the output buffers, independent of the state of the memory. Although there are
alternative ways to resolve the conflict, normally Output
Disable will be held high during a write operation.

This bussed I/O approach cuts down the package pin count
allowing the design of higher density memory systems. It also
provides a direct interface to bus-oriented systems, eliminating
bussing logic that could otherwise be required. Most microprocessor systems, for example, transfer information on a
bidirectional data bus. The Am9111 memories can connect

Typical tA Versus
Ambient Temperature

Typical V1N Limits
Versus Ambient Temperature
1.8

300

1.6

250

Vee

z

->

r--- ~H=~ r---

=MIN.

240

~

c:

I

1.4t----

200

~

tv;'L =MAX:" t---1.2

Typical tA Versus CL
260

~

l--""'"

./

220
c

I

200

V

~

180

150

V
./

./

V

160
1.0
25

0

75

50

TA - AMBIENT TEMPERATURE _ °e

100

0

25

50

75

140

0

100

TA - AMBIENT TEMPERATURE - °e

200

300

400

500

600

eL - pF

MOS·355
I

ORDERING INFORMATION
Ambient
Temperature
Specification

Access Times
Package
Type
Molded DIP

Oto +70°C
Hermetic DIP

Power
Type

Hermetic DIP

650ns

500ns

400ns

300ns

P2111-1
AM9111APC

AM9111BPC

AM9111CPC

Low

AM91L11APC

AM91L11BPC

AM91L11CPC

Standard

C2111-1
AM9111ADC

AM9111BDC

AM9111CDC

AM91L11ADC

AM91L11BDC

AM91L11CDC

Standard

AM9111ADM

AM9111BDM

AM9111CDM

Low

AM91L11ADM

AM91L11BDM

AM91L11CDM

Standard

Low
-55to +125°C

1000ns
P2111

C2111

P2111-2

C2111-2

4-12

250ns
AM9111DPC

AM9111DDC

Am9112/Am91L12 Family
256 x 4 Static R/W Random Access Memories

Part
Number

Access
Time

Am2112

Am2112-2

Am9112A
Am91L12A

Am9112B
Am91L12B

Am9112C
Am91L12C

Am9112D

1000ns

650ns

500ns

400ns

300ns

250ns

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• 256 x 4 organization
• 16-pin standard DIP
• Low operating power dissipation
125mW typ; 290mW maximum - standard power
100mW typ; 175mW maximum - low power
• DC standby mode reduces power up to 84 %
20mW Typ; 47mW maximum
• Logic voltage levels identical to TTL
• High output drive - two full TTL loads guaranteed
• High noise immunity - full 400mV
• Uniform switching characteristics - access times
insensitive to supply variations, address patterns
and data patterns
• Single +5V power supply - tolerances ±5%
commercial, ±10% military
• Bus-oriented I/O data
• Zero address, setup and hold times guaranteed for
simpler timing
• Direct plug-in replacement for 2112 type devices
• 100% MIL-STD-883 reliability assurance testing

The Am9112/Am91L 12 series of products are high performance, low power, 1024-bit, static read/write random access memories. They offer a range of speeds and power
dissipations including versions as fast as 200ns and as low
as 100mWtypicai.
Each memory is implemented as 256 words by 4-bits per
word. This organization allow,s efficient design of small
memory systems and permits finer resolution of incremental memory word size relative to 1024 by 1 devices. The
output and input data signals are internally bussed together
and share 4 common I/O pins. This feature keeps the
package size small and provides a simplified interface to
bus-oriented systems.
The Am9112/Am91L 12 memories may be operated in a DC
standby mode for reductions of as much as 84 % of the
normal operating power dissipation. Though the memory
cannot be operated, data can be retained in the storage
cells with a power supply as low as 1.5 volts. The Am91 L12
versions offer reduced power during normal operating conditions as well as even lower dissipation in standby mode.
The eight Address inputs are decoded to select 1-of-256
locations within the memory. The Chip Enable input acts as
a high-order address in multiple chip systems. It also controls the write amplifier and the output buffers in conjunction
with the Write Enable input. When CE is low and WE is
high, the write amplifiers are disabled, the output buffers
are enabled and the memory will execute a read cycle.
When CE is low and WE is low, the write amplifiers are enabled, the output buffers are disabled and the memory will
execute a write cycle. When CE is high both the write
amplifiers and the output buffers are disabled.

Am9112 BLOCK DIAGRAM

32XS
STORAGE
ARRAY

32XS
STORAGE
ARRAY

32XS
STORAGE
ARRAY

32XS
STORAGE
ARRAY

These memories are fully static and require no refresh operations or sense amplifiers or clocks. All input and output
voltage levels are identical to standard TTL specifications,
including the power supply.

CONNECTION DIAGRAM
Top View

AS-------l
A6

--------1

COLUMN DECODERIINPUT CONTROLI
OUTPUT SUFFERS/SELECT LOGICI
DISABLE LOGIC

ADDRESS 3

MOS-356

4-13

VCC(+5V)

ADDRESS 2

ADDRESS 4

ADDRESS'

WRITE ENABLE

ADDRESS 0

CHIP ENABLE

ADDRESS 5

DATA 1/04

ADDRESS 6

DATA 1/03

ADDRESS 7

DATA 1/02

(GND) VSS

DATA I/O,

Note: Pin 1 is marked for orientation.

MOS-357

Am91121Am91L12 Family
MAXIMUM RATINGS above which the useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
VCC With Respect to VSS, Continuous

-O.SV to +7.0V
-O.5V to +7.0V

DC Voltage Applied to Outputs
DC Input Voltage

-O.5V to +7.0V
1.0W

Power Dissipation

ELECTRICAL CHARACTERISTICS

Am9112/
Am91L12
Family
Min.
Max.

Am9112PC, Am9112DC

vcc=

Am91L12PC, Am91L12DC

+5V ±5%

Parameters

Description

VOH

Output HIGH Voltage

VCC = MIN., 10H = -200J.lA

VOL

Output LOW Voltage

VCC = MIN., 10L = 3.2mA

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

III

Input Load Current

'LO

Test Conditions

VCC

1/0 Leakage Current

VCE

= MAX.,

Volts

VCC

Volts

-0.5

0.8

Volts

OV';; VIN';; 5.25V

10

J.lA

VOUT = VCC

5.0

= 0.4 V

-10

= VIH

VOUT

= 25°C

Data out open
VCC = MAX.
VIN = VCC

Current

TA

ICC2

= O°C

Am9112A/B

50

Am9112C/D/E

55

Am91L12A/B

31

Am91L12C

34

Am9112A/B

55

Am9112CIDfE

60

Am91 L12A/B

33

Am91L12C

36

ELECTRICAL CHARACTERISTICS
Am9112DM

TA = -55°C to +125°C

Am91L12DM

vcc = + 5.0V

Am9112/
Am91L12
Family
Min.
Max.

± 10%

Description

Parameters

Volts

2.0

ICCl

Suppl~

Units

0.4

TA

Power

2.4

Test Conditions

= 4.75V
10H = -200J.lA
VCC = 4.50V
VCC = MIN., 10L = 3.2mA

J.lA

mA

Units

2.4

VCC

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

2.0

VCC

Volts

VIL

Input LOW Voltage

-0.5

0.8

Volts

III

Input Load Current

VIN .;; 5.5V

10

J.lA

= VCC
VOUT = 0.4 V

10

ILO

I/O LC:Jk:Jgc Current

VCC
VCE

= MAX., OV';;
= VIH

0.4

VOUT

-10

TA

= 25°C

Data out open
Power Supply Current

VCC
VIN

= MAX.
= VCC
TA

ICC3

= -55°C

Volts

J.lA

50

Am9112A/B
ICCl

Volts

2.2

Am9112C

55

Am91L12A/B

31

Am91L12C

34

Am9112A/B

60

Am9112C

65

Am91L12A/B

37

Am91 L12C

40

mA

CAPACITANCE
Parameters
CIN

Description
Input Capacitance, VIN

= OV
TA

COUT

Typ.

Max.

Am2112

4.0

8.0

Am9112/Am91 L12

3.0

6.0

Am2112

10

18

Am9112/Am91L12

8.0

11

Test Conditions

Output Capacitance, VOUT

= 25°C, f = 1 mHz

= OV
4-14

Units
pF

pF

Am9112/Am91L12 Family
SWITCHING CHARACTERISTICS

over operating temperature and voltage range

Output Load = 1 TTL Gate +100pF
Transition Times = 10ns
Input Levels, Output References = 0.8V and 2.0V

Am9112A
Am91L12A

Parameters

Description

Min

Am9112B
Am91L12B

Max

Min

Max

Am9112C
Am91L12C

Min

Max

Am9112D

Min

Max

Units

tRC

Read Cycle Time

tA

Access Time

teo

Output Enabled to Output ON Delay
(Note 1)

5.0

toH

Previous Read Data Valid with Respect
to Address Change

40

tOF

Output Disabled to Output OFF Delay
(Note 2)

5.0

twc

Write Cycle Time

500

400

300

250

ns

tAW

Address Set-up Time

0

0

0

0

ns

tWR

Address Hold Time

0

0

0

0

ns

twp

Write Pulse Width (Note 3)

175

150

125

100

ns

tcw

Chip Enable Set-up Time

175

150

125

100

ns

tow

Input Data Set-up Time

150

125

100

85

ns

tOH

Input Data Hold Time (Note 4)

0

0

0

0

ns

400

500
500

300

5.0

175

150

40
5.0

125

SWITCHING WAVEFORMS

250

5.0

125

5.0

40
100

ns

300

400

5.0

250

ns

100

ns
ns

30
100

5.0

75

ns

(Note 5)

READ CYCLE

WRITE CYCLE

'""'1. -,--------tRc--------·-f-o·--------twc--------~1
ADDRESS

~~----~~~----~r=

I

I

I

~\_I'----tc-o_tc-O==~---I-:I ----'1 ~~ ~'--ll ~JrU.~."
J

------';""11--'
!WRITE ENABLE

J
DATA 1/0

tOH~

~

2.0~

---....;..------------O-.B~

j---tDW----l

rtDH

"~ATAINPUT~
\
STABLE
/>------

~-------tA-------------~1

Notes: 1. Output is enabled and tco commences only with both CE LOW and WE HIGH.
2. Output is disabled and tOF defined from either the rising edge of CE or the falling edge of WE.
3. Minimum twp is valid when CE has been HIGH at least tOF before WE goes LOW. Otherwise tWP(min.) = tOW(min.) -: tOF(max.).
4. When WE goes HI GHat the end of the write cycle, it will be possible to turn on the output buffers if CE is still LOW. The data out will be
the same as the data just written and so will not conflict with input data that may still be on the I/O bus.
5. See "Application Information" section of this specification.

MOS-358

4-15

Am9112/Am91L12 Family
DEFINITION OF TERMS
FUNCTIONAL TERMS
CE Active LOW Chip Enable. Data can be read from or written
into the memory only if CE is LOW.
WE Active LOW Write Enable. Data is written into the memory
if WE is LOW and read from the memory if WE is HIGH.
Static RAM A random access memory in which data is stored
in bistable latch circuits. A static memory will store data as long
as power is supplied to the chip without requiring any special
clocking or refreshing operations.
N·Channel An insulated gate field effect transistor ·technology
in which the transistor source and drain are made of N·type
material, and electrons serve as the carriers between the two
regions. N·Channel transistors exhibit lower thresholds and faster
switching speeds than P·Channel transistors.
SWITCHING TERMS
tRC Read Cycle Time. The minimum time required between
successive address changes while reading.
tA Access Time. The time delay between application of an
address and stable data on the output when the chip is enabled.

4·16

tco Output Enable Time. The time during which CE must be
LOW and WE must be HIGH prior to data on the output.
tOH Minimum time which will elapse between change of address
and any change on the data output.
tOF Time which will elapse between a change on the chip enable
or the right enable and on data outputs being driven to
a floating status.
twc Write Cycle Time. The minimum time required between
successive address changes while writing.
tAW Address Set-up Time. The minimum time prior to the
falling edge of the write enable during which the address inputs
must be correct and stable.
twp The minimum duration of a LOW level on the write enable
guaranteed to write data.
twR Address Hold Time. The minimum time after the rising edge
of the write enable during which the address must remain steady.
tow Data Set-up Time. The minimum time that the data input
must be steady prior to the rising edge of the write enable.
tOH Data Hold Time. The minimum time that the data input
must remain steady after the rising edge of the write enable.
tcw Chip Enable Time During Write. The minimum duration of a
LOW level on the Chip Select while the write enable is LOW to
guarantee writing.

Am9112/Am91L12 Family
POWER DOWN STANDBY OPERATION
large system, memory pages not being accessed can be
placed in standby to save power. A standby recovery time
must elapse following restoration of normal power before
the memory may be accessed.
To ensure that the output of the device is in a high impedance OFF state during standbY, the chip select should
be held at VIH or VeEs during the entire standby cycle.

The Am9112/Am91L12 Family is designed to maintain
storaqe in a standby mode. The standby mode is entered by
lowering Vee to around 1.5-2.0 volts (see table and graph
below). When the voltage to the device is reduced, the
storage cells are isolated from the data Iines, so their contents will not change. The standby mode may be used by a
battery operated backup power supply system, or, in a

STANDBY OPERATING CONDITIONS OVER TEMPERATURE RANGE
Parameters

Description

Max.

Units

1.5
VPD = 1.5V

TA =O°C
All Inputs = VPD

VPD = 2.0V
ICC in Standby Mode

IpD

Typ.

Min.

Test Conditions

Vec in Standby Mode

VPD

VPD = 1.5V
TA = -55°C
All Inputs = VPD

VPD = 2.0V

Am91L12

11

25

Am9112

13

31

Am91 L12

13

31
41

Am9112

17

Am91L12

11

28

Am9112

13

34

Am91L12

13

34

Am9112

17

46

mA

mA

dv/dt

Rate of Change of VCC

tR

Standby Recovery Time

tcP

Chip Deselect Time

0

ns

VCES

CE Bias in Standby

VPD

Volts

1.0

ns

Typical Power Supply Current
Versus Voltage

Typical Output Current
Versus Voltage
24
22

30
TA = 25°e
25

INPUTS = 5.0V
Am9112

,....V
/...-1

20

«

E
I

u

15
10

STANDBY MODE

RECOVERY

1---------,

16

VCC (+5 V)

2 -----,

15

ADDRESS 4

ADDRESS 1

3

ADDRESS 0

14

WRITE ENABLE

13

CHIP ENABLE

12
ADDRESS 5

5

ADDRESS 6

6

DATA 1/°4

J:

~
z

«

11\
I \
I

I

10

,
\

I

oJ

I

/'

\.

STATE

o
o

,

HIGH
\ STATE

f;ow

+"

V ee =4.75V
TA = 25°.e

\/

14
12

0

"-"!-..

I

VOUT-VOLTS

Access Time Versus Vee
Normalized to Vee = +5.0 Volts

Typical Power Supply Current
Versus Ambient Temperature

1.05

--

TA =1 70oe
1.0

J.

\

20
18
16

Vee-VOLTS

~

«

4

E
I

.9

o
o

Metallization and Pad Layout
ADDRESS 3

«

/

READ OR
WRITE
CYCLE

ADDRESS 2

:.--

~

/

.!::'

DESELECT
CHIP

V/J,J.s

tRC

~

30
28

~

26

I

............

24

0.95

~

22

I

20

2

18

Vee=MAX.-

.........

r--....

--

.........

---

16
0.90

14
12

11
ADDRESS 7
(GND) VSS

7

10

8 ------'

DATA 1/03
DATA 1/°2

0.85
4.0

10
4.5

5.0
Vee-VOLTS

DATA 1/°1

5.5

6.0

o

75
50
25
TA - AMBIENT TEMPERATURE - °e

DIE SIZE 0.132" X 0.131"
MaS·3S9

4-17

Am9112/91 L 12 Family

APPLICATION INFORMATION
These memory products provide all of the advantages of
AMD's other static N-channel memory circuits: +5 only power
supply, all TTL interface, no clocks, no sensing, no refreshing,
military temperature range available, low power versions available, high speed, high output drive, etc. In addition, the
Am9112 series features a 256 x 4 organization with common
pins used for both Data In and Data Out signals.

These operational suggestions for write cycles may be of some
help for memory system designs:
1. For systems where CE is always low or is derived directly
from addresses and so js low for the whole cycle, make sure
twp is at least tDW + tDF and delay the input data until
tDF following the falling edge of WE. With zero address
set-up and hold times it will often be convenient to make
WE a cycle-width level (twp = twc) so that the only
subcycle timing required is the delay of the input data.

This bussed 110 approach keeps the package pin count low
allovying the design of higher density memory systems. It
also provides a direct interface to bus-oriented systems, eliminating bussing logic that could otherwise be required. Most
microprocessor systems, for example, transfer information on
a bidirectional data bus. The Am9112 memories can connect
directly to such a processor since the common 110 pins act as
a bidirectional data bus.

2. For systems where CE is high for at least tOF preceeding
the falling edge of WE, twp may assume the minimum
specified value. When CE is high for tOF before the start of
the cycle, then no other subcycle timing is required and WE
and data-in may be cycle-width levels.

If the chip is enabled (CE low) and the memory is in the
Read state (WE high), the output buffers will be turned on
and will be driving data on the 110 bus lines. If the external
system tries to drive the bus with· data, there may be contention for control of the data lines and large current surges
can result. Since the condition can occur at the beginning of
a write cycle, it is important that incoming data to be written
not be entered until the output buffers have been turned off.

3. Notice that because both CE and WE must be low to cause
a write to take place, either signal can be used to determine
the effective write pulse. Thus, WE could be a level with
CE becoming the write timing signal. In such a case, the
data set-up and hold times are specified with respect to the
rising edge of CEo The value of the data set-up time remains
the same and the value of the data hold time should change
to a minimum of 25ns.

Typical tA Versus
Ambient Temperature

Typical VIN Limits
Versus Ambient Temperature
1.8

Typical tA Versus CL

300

260

vcc= MIN.
1.6

z

->

1.4

1.2

-

--

~
~

---

c:
I

25

.--------

.--------

~

./

220
c:

./

200

I

~
180

150

./

/'

/'

V-

160

75

50

TA - AMBIENT TEMPERATURE

200

~

1.0
0

240

250

_·c

100

140
0

50

25

75

TA - AMBIENT TEMPERATURE

0

100

_·c

200

300

400

CL - pF

500

600

MOS-360

ORDERING INFORMATION

Ambient
Temperature

Package

Power

Specification

Type

Type

1000ns

6S0ns

SOOns

300m;

250m;

Standard

P2112

P2112-2

AM9112APC

AM9112BPC

AM9112CPC

AM9112DPC

AM91l12APC

AM91l12BPC

AM91l12CPC

Access Times

Molded DIP

low

Oto +70°C
Hermetic DIP

-55 to + 125°C

Hermetic DIP

Standard

C2112

C2112-2

400ns

AM9112ADC

AM9112BDC

AM9112CDC

low

AM91l12ADC

AM91l12BDC

AM91l12CDC

Standard

AM9112ADM

AM9112BDM

AM9112CDM

low

AM91l12ADM

AM91l12BDM

AM91l12CDM

4-18

AM9112DDC

Am9122/Am91
L22
x
256

4 Static R/W RAMs

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• High performance replacement for 93422/93L422
• 256 x 4 organization for small memory systems
• Fast access times - down to 25ns (Commercial)
- down to 35ns (Military)
• Low operating power dissipation
Standard power: 660mW (Commercial)
745mW (Military)
Low power: 248/440mW (Commercial)
495mW (Military)
• Single 5 volt power supply - ± 10% tolerance
both commercial and military
• 100% MIL-STD-883 reliability assurance testing
• Guaranteed 0.1% AQL

The Am9122/Am91L22 series is aMOS pin-for-pin and
functional replacement for the 93422/93L422 bipolar
memories. These devices are high-performance, lowpower, 1024-bit, static, read/write random access
memories. They offer a wide range of access times including versions as fast as 25ns. Each memory is implemented
as 256 words by 4 bits per word. This organization permits
efficient design of small memory systems and allows finer
resolution of incremental memory depth.
The Am9122/91L22 employs an output enable and two chip
enable inputs to give the user better data control. High
noise immunity, high output drive (4 TTL loads) and TTL
logic voltage levels allow easy conversion from bipolar to
MOS. 10% power supply tolerances give better margins in
the memory system. As with all AMD MOS RAMs, the
Am9122/91L22 is guaranteed to 0.1% AQL.

CONNECTION DIAGRAM
Top View

Am9122 BLOCK DIAGRAM

At!
Al
A2
A3

Vee (+5V)

ADDRESS 3

I

32x8I 32x8
STORAGE STORAGE
ARRAY
ARRAY

I

32X8132X8
STORAGE STORAGE
ARRAY
ARRAY

A4

As

As

ADDRESS 4

ADDRESS 1

WRITE ENABLE

ADDRESS 0

CHIP SELECT 1

ADDRESS 5

OUTPUT ENABLE

ADDRESS 6

CHIP SELECT 2

ADDRESS 7

DATAOUT3

WE

(GND)Vss

CS1

DATAINO

C~

DATAOUT2
DATAIN2
DATAOUTl

DATA IN 1

00 0 010

001 011

00 2 01 2

I]

DATAIN3

DATAOUTO

DE

A7

ADDRESS 2

003 01 3

Note: Pin 1 is marked for orientation.

RAM-019

RAM-020

SELECTION GUIDE

Am9122-25 Am9122-35 Am91L22-35 Am91L22-45 Am91L22-60
Maximum Access Time (ns)
Maximum Operating Current (rnA)

25

35

35

45

60

Ot070°C

120

120

80

80

45

-55to 125°C

N/A

135

N/A

90

N/A

4-19

Am9122/91 L22
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature

-65 to +150°C

Temperature (Ambient) Under Bias

-55to +125°C

Supply Voltage to Ground Potential (Pin 10 to Pin 9) Continuous

-0.5 to + 7.0V

DC Voltage Applied to Outputs

-0.5 to + 7.0V

DC Input Voltage

-0.5 to + 7.0V

Power Dissipation

1.0W

DC Output Current

20mA

OPERATING RANGE
Part Number

Ambient Temperature

Vee

Am9122 DC/PC
Am91 L22 DC/PC

O°C ~ TA ~ +70°C

+5.0V ± 10%

-55°C ~ TA ~ +125°C

+5.0V± 10%

Am9122OM
Am91L22DM

ELECTRICAL CHARACTERISTICS over the operating temperature range unless otherwise specified (Note 1)

Parameters

Description

Am91L22-35
Am91L22-60 Am91L22-45
Min
Max
Min
Max

Test Conditions

VOH
VOL

Output LOW Voltage

VIH

Input HIGH Voltage

2.1

Vil

Input LOW Voltage

-3.0

III

Input LOW Current

Vec = Max, VIN = Gnd

10

IIH

Input HIGH Current

Vec = Max, VIN = Vee

10

VCD

Input Diode Clamp Voltage

Note 4

Note 4

10FF

Output Current (High-Z)

VOL ~ VOUT ~ VOH
Output Disabled

los

Output Short Circuit Current
Note 3

Vee = Max
VOUT= GND

Ice

Power Supply Current

Vee = Max, lOUT = OmA

10H = -5.2mA

Vee = Min

10l = S.OmA

2.4

2.4

Output HIGH Voltage

Vee = Min

2.4
0.4

-50

TA = Max

Am9122-25
Am9122-35
Min
Max

Volts

Vec

Volts

O.S

Volts

10

10

/LA

10

10

/LA

Note 4

Volts

50

/LA

Vee

Vee

2.1

O.S

-3.0

O.S

-3.0

-50

Volts
0.4

0.4
2.1

50

Units

-50

50

Commercial

-70

-70

-70

rnA

Military

-SO

-SO

-SO

rnA

TA = 70°C

40

70

110

rnA

TA = O°C

45

SO

120

rnA

TA = -55°C

N/A

90

135

rnA

CAPACITANCE
Parameters

Description
Input Capacitance. VIN = OV
Output Capacitance, VOUT = OV

Test Conditions

Max

Units

TA = 25°C, f = 1MHz
Vee = 4.SV
levels and -5V undershoot pulses of less than 10ns (measured at 50% point).
5. Test conditions assume Signal transition times of 10ns or
less, timing reference levels of 1.5V and output loading of the
specified 10l/iOH and 30pF load capacitance as in Figure 1a.
6. Transition is measured at VOH -500mV or VOL +500mV
levels on the output from 1.5V level on the input with load
shown in Figure 1b.

Notes: 1. The temperature ranges are guaranteed with transverse air
flow exceeding 400 linear feet per minute. A two minute warm
up period is required for -55°C operation.
2. tw measured at twsa = min; twsa measured at tw = min.
3. For test purposes, not more than one output at a time should
be shorted. Short circuit test duration should not exceed 30
seconds.
4. The NMOS process does not provide a clamp diode. However, the Am9122/91L22 is insensitive to -3V DC input

4·20

Am9122/91L22
SWITCHING CHARACTERISTICS over operating and voltage range (Note 5)
Test Conditions

Description

Parameters
tACS

Chip Select Time

tZRCS

Chip Select to High-Z

tAOS

Output Enable Time

tZROS

Output Enable to High-Z

tAA

Address Access Time

Am9122-25
Min
Max

(Note 6)

tzws

Write Disable to High-Z

tWR

Write Recovery Time

tw

Write Pulse Width

(Note 6)

(Note 6)

(Note 2)

15

Am91L22-35
Am9122-35 Am91L22·45 Am91L22-60
Min
Max
Min
Max
Min
Max Units

15

25

30

35

ns

20

30

30

35

ns

15

25

30

35

ns

20

30

30

35

ns

25

35

45

60

ns

20

30

35

40

ns

20

25

40

45

25

30

ns

40

ns

tWSD

Data Setup Time Prior to Write

5

5

5

5

ns

tWHD

Data Hold Time After Write

5

5

5

5

ns

tWSA

Address Setup Time

5

5

10

10

ns

tWHA

Address Hold Time

5

5

5

5

ns

tWSCS

Chip Select Setup Time

5

5

5

5

ns

tWHCS

Chip Select Hold Time

5

5

5

5

ns

(Note 2)

LOGIC TABLE
Inputs
OE

CS1

CS2

WE

00- 0 3

Outputs

X
X

H

X

Not Selected

L

X
X

HighZ

X

X
X

L

L

H

H

X

X
X

L

H

L

L

H

H

L

H

L

H

L

Mode

HighZ

Not Selected

L

0 0 -03
HighZ

Read Stored Data
Write "0"

L

H

HighZ

Write "1"

H

H

X

HighZ

Output Disabled

H

L

L

HighZ

Write "0" (Output Disabled)

H

L

H

HighZ

Write "1" (Output Disabled)

II
I

Notes: H = HIGH Voltage
L = LOW Voltage
X = Don't Care (HIGH or LOW)
High Z = High Impedance

BITMAP
.-------------~c

Address Designators
External

F!lII!L.L-

Internal

Ao

Ao

A1

A1

A2

A2

A3

A3

A4

~

A5

A5

A6

A6

A7

A7

INTERNAL

Rowa

ROW31

4-21

Am9122/91 L22
AC TEST LOADS AND WAVEFORMS
AC TEST LOADS
Vcc

0-----------,

INPUT PULSES

Vcc
Rl
600n

OUTPUT

Rl
600n

0----_._------+

r

OUTPUT

o-------T-----.
R2

r

R2

30PF

ALL INPUT PULSES

0-----------,

SPF

1200n

1200n

Figure 2.

Figure 1b.

Figure 1a.

RAM-021

READ MODE

~~
/~

~,--

1,----

ADDRESS

TAA

)

-/

J

~

-t

"

J

\
I

\

J

\

-

TAOS
DATA
OUTPUTS

({«««(K

DATA INVALID

0 0 -03

DATA VALID

I

TACS

TZRCS

WRITE MODE
1 CS

RAM-022

F

~

CHIP- SELECT
_
Cs
2

I - TZROS

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......

~

Ao-A7
ADDRESS

:~ITE NABLE
DATA
OUTPUTS

°0-°3

~:_,tf:~=t:'J__

_ _ _

-----r
------

LOAD 1 B

O.SV

RAM-023

(All above measurements implemented to 1.5V unless otherwise stated.)
Note: Timing diagram represents one solution which results in an optimum cycle time. Timing may be changed to in various applications
as long as the worst case limits are not violated.

4-22

Am9122/91 L22
TYPICAL DC AND AC CHARACTERISTICS

Normalized ICC
versus Supply Voltage

Normalized ICC
versus Ambient Temperature
1.25
1.20
1.15
1.10
1.05

1.15
1.10
1.05
1.00
0

9

v

.85

8

./

.95

.90

. /V

V
./

V
./

-

.80
4.5

100

-,
"'-

80

,

~

1.00
.95
.90
.85
.80
'\
.75
.70
-55-35-15 5 25 45 65 85105125

'" "

5.5
Vee- V

.p 40

"

~

$

tAA

~
...I

0.9

0.9

c(

::E

II:

II:

0

z

0.8

0.8

TA = 25°C
0.7
4.0

.

4.5

5.5

5.0

/

I

,;

I

/

0.7
-55-35-15 5

6.0

3.0

4.0

100

c(

VTAA -

r--

V

125

I

E

-

50

I

25

/
o

Vee = 5.0V

1 -I

1

/

/
Vee = 5.0V_
TA = 25°C

I

o

25 45 65 85105125

II

I

~ 75

.p

-,

/

1.0

2.0

TA-oC

Vee- V

3.0

4.0

VOUT - V

Access Time Change
versus Input Voltage

Access Time Change
versus Output Loading
30

I

TA = 125°C
VCC MIN

20
til

til

C

20

C

I

J

2.0

150

V

w

c(

z

1.0

Output Sink Current
versus Output Voltage

//

1.0

c

::E
0

"

o

VOUT- V

1.1

C

::::i

'" '"
........

o

,,/

W
N

Vee = 5.0V
TA =25°C -

20

Normalized Access Time
versus Ambient Temperature

1.1

1.0

~

:z:

TEMP-oC

Normalized Access Time
versus Supply Voltage

---------------

"

DATA OUT

DATA UNDEFINED

HIGH IMPEDANCE

Note: If CS goes high simultaneously with WE high, the output. remains in a high impedance state.

RAM-DD7

BIT MAP
Address Designators
External

Internal

Ao

A2

Al

As

A2

A4

A3

A3

A4

As

As

A7

As

Al

A7

Ao

As

All

A9

A9

Al0

Al0

All

A6

. - - - - - - - - - 18

63

4032

o

" . ''''rl+-- 4095

DIE SIZE:
0.130 X 0.106

Figure 2. Bit Mapping Information

4-42

Am2147
TYPICAL DC AND AC CHARACTERISTICS

Supply Current
Versus Ambient Temperature

Supply Current
Versus Supply Voltage

125

175

100

140

100

r--.. l"- r-

r- I"-

<

<

E

E 105

I

I

75

I

ICC-

f--

r-~ r-

80

~

60

§

40

TA

I

= 5.0V
= 25°C

vec

I-

ID

ID

!!l
ci

Output Source Current
Versus Output Voltage

!!l
ci

70

so

f-- VCC = S.OV

I'"

~

~

35

25

ISB

~

t::: ~

20

o
o

OL..-_...J..._ _l...-_...J..._-..I

4.50

4.755.00

5.25

-55 -35 -15 5

5.50

25 45 65 85 105125

1.0

2.0

vec - v

Normalized Access Time
Versus Ambient Temperature

~

1.0

--

~

 OV)

OV

Power Dissipation

1.0W

Short Circuit Output Current

50mA

The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.

OPERATING RANGE
Part Number

Ambient Temperature

Vss

Voo

Vee

Am9016DC/PC/LC

+12V±10%

+5V ±10%

-5V ±10%

Am9016DL/LL

+12V±10%

+5V ±10%

-5V ±10%

Vee

ELECTRICAL CHARACTERISTICS over operating range (Notes 1,9)
Parameters

Description

Test Conditions

Am9016
Min

Max

Units

2.4

VCC

Volts

VSS

0.40

Volts

Input HIGH Voltage for Address, Data In

2.4

7.0

Volts

VIHC

Input HIGH Voltage for CAS, RAS, WE

2.7

7.0

Volts

VIL

Input LOW Voltage

-1.0

0.80

Volts

IIX

Input Load Current

VSS~Vk7V

-10

10

/.LA

IOZ

Output Leakage Current

VSS ~ VO ~ VCC, Output OFF

-10

10

/.LA

ICC

VCC Supply Current

Output OFF (Note 4)

-10

10

/.LA

VOH

Output HIGH Voltage

IOH = -5.0mA

VOL

Output LOW Voltage

IOL= 4.2mA

VIH

O°C ~ TA ~ +70°C
IBB

VBB Supply Current,
Average

O°C ~ TA ~ +70°C
-55°C ~ TA ~ +85°C

IDD

VDD Supply Current,
Average

O°C ~ TA ~ + 70°C
-55°C ~ TA ~ +85°C
CI

Input Capacitance
Output Capacitance

100
200
200
400

Operating

IDD1

Page Mode

IDD4

RAS ~ VIL, CAS Cycling,
Minimum Cycle Times

27

RASOnly
Refresh

IDD3

RAS Cycling, CAS;;': VIHC,
Minimum Cycle Times

27

Standby

IDD2

RAS,CAS,WE

/.LA

Operating, Minimum Cycle Time
RAS Cycling, CAS Cycling,
Minimum Cycle Times

Address, Data In
CO

Standby, RAS;;': VIHC

-55°C ~ TA ~ +85°C

Typ

35

rnA

RAS;;,:VIHC

1.5

RAS;;,:VIHC

2.25

Inputs at OV, f = 1MHz,
Nominal Supply Voltages

5.0

Output OFF

7.0

4-60

10
pF

Am9016
SWITCHING CHARACTERISTICS over operating range (Notes 2, 3, 5)
Am9016C

Parameters
tAR
tASC

Description

Min

RAS LOW to Column Address Hold Time
Column Address
Setup Time

10°C"" TA "" + 70°C
I -55°C"" TA "" +85°C

tASR

Row Address Setup Time

tCAC

Access Time from CAS (Note 6)

tCAH

CAS LOW to Column Address Hold Time

tCAS

CAS Pulse Width

Max

Am9016D

Min

Max

Am9016E

Min

Max

Am9016F

Min

Max

160

120

95

-10

-10

-10

-10

ns

0

0

0

NA

ns

0

0
185
85

0
165

75

ns

ns

0
135

55

100
45

185

10,000

165

10,000

135

10,000

100

10,000

I-55°C"" TA "" +85°C

185

5000

165

5000

135

5000

NA

NA

Page Mode CAS Precharge Time

tCRP

CAStoRAS
Precharge Time

10°C"" TA "" + 70°C
I-55°C"" TA "" +85°C

ns
ns

10°C"" TA "" + 70°C

tCP

Units

200

ns
ns

100

100

80

60

-20

-20

-20

-20

ns

0

0

0

NA

ns
ns

ns

tCSH

CAS Hold Time

300

250

200

150

tCWD

CAS LOW to WE LOW Delay (Note 9)

145

125

95

70

ns

tCWL

WE LOW to CAS HIGH Setup Time

100

85

70

50

ns

tDH

CAS LOW or WE LOW to Data In Valid
Hold Time (Note 7)

85

75

55

45

ns

tDHR

RAS LOW to Data In Valid Hold Time

200

160

120

95

ns

tDS

Data In Stable to CAS LOW or
WE LOW Setup Time (Note 7)

0

0

0

0

ns

tOFF

CAS HIGH to Output OFF Delay

tPC

Page Mode Cycle Time

tRAC

Access Time from RAS (Note 6)

tRAH

RAS LOW to Row Address Hold Time

tRAS
tRC

RAS Pulse Width

0

60

295

0

60

275
300

45

0

50

250
35

0

40

170

225
200
25

ns
ns

150
20

ns
ns

10°C"" TA "" + 70°C

300

10,000

250

10,000

200

10,000

150

10,000

ns

I-55°C"" TA "" +85°C

300

5000

250

5000

200

5000

NA

NA

ns

Random Read or Write Cycle Time

460

410

375

320

ns

tRCD

RAS LOW to CAS LOW Delay (Note 6)

35

tRCH

Read Hold Time

0

0

0

0

ns

tRCS

Read Setup Time

0

0

0

0

ns

115

35

85

25

65

20

50

ns

tREF

Refresh Interval

tRMW

Read Modify Write Cycle Time

600

500

405

320

ns

tRP

RAS Precharge Time

150

150

120

100

ns

tRSH

CAS LOW to RAS HIGH Delay

185

165

135

100

ns

tRWC

Read/Write Cycle Time

525

425

375

320

ns

tRWD

RAS LOW to WE LOW Delay (Note 9)

260

210

160

120

ns

tRWL

WE LOW to RAS HIGH Setup Time

100

85

70

50

tT

Transition Time

3

tWCH

Write Hold Time

85

75

55

45

ns

tWCR

RAS LOW to Write Hold Time

200

160

120

95

ns

tWCS

WE LOW to CAS LOW
Setup Time (Note 9)

-20

-20

-20

-20

0

0

0

NA

75

55

45

tWP

2

10°C"" TA "" +70°C

50

2

3

50

2

3

50

2

3

ms

ns
35

ns

ns

I-55°C"" TA "" +85°C

Write Pulse Width

85

Notes:
1. All voltages referenced to VSS.
2. Signal transition times are assumed to be 5ns. Transition times are
measured between specified high and low logic levels.
3. Timing reference levels for both input and output signals are the
specified worst-case logic levels.
4. VCC is used in the output buffer only. ICC will therefore depend only
on leakage current and output loading. When the output is ON and
at a logic high level, VCC is connected to the Data Out pin through

4-61

I)

ns

an equivalent resistance of approximately 1350. In standby mode
VCC may be reduced to zero without affecting stored data or refresh
operations.
5. Output loading is two standard TTL loads plus 100pF capacitance.
6. Both RAS and CAS must be low read data. Access timing will
depend on the relative positions of their falling edges. When tRCD
is less than the maximum value shown, access time depends on
RAS and tRAC governs. When tRCD is more than the maximum
value shown access time depends on CAS and tCAC governs. The

I

Am9016
Notes (Cont.)

When the falling edge of WE follows the falling edge of CAS by at
most tWCS, the data output buffer will remain off for the whole cycle
and an "early write" cycle is defined. When the falling edge of WE
follows the falling edges of RAS and CAS by at least tRWD and
tCWD respectively, the Data Out from the addressed cell will be
valid at the access time and a "read/write" cycle is defined. The
falling edge of WE may also occur at intermediate positions, but the
condition and validity of the Data Out signal will not be known.

maximum value listed for tRCD is shown for reference purposes
only and does not restrict operation of the part.
7. Timing reference points for data input setup and hold times will
depend on what type of write cycle is being performed and will be
the later falling edge of CAS or WE.
8. At least eight initialization cycles that exercise RAS should be
performed after power-up and before valid operations are begun.
9. The tWCS, tRWD and tCWD parameters are shown for reference
purposes only and do not restrict the operating flexibility of the part.

SWITCHING WAVEFORMS
READ CYCLE

.RC
.RAS

~r;;:

iL,",~ L

tAR
I-'~

I

.RCD

.RSH

I
I

.CSH

tCAS

~~

JZ

-'
_tRAH_

tASR~
ADDRESS

~

r-- tCAH -

tASC-==i

r--------'- t C R P -

-'--

/

7"
COLUMN ADDRESS

ROW ADDRESS

.\.

~tRCS~

H

tRCH-

y

MhMX~

"

I,A,AMAM\.

tCAC
tRAC

tOFF

-----I

DO

MOS·192

WRITE CYCLE (EARLY WRITE)

tRC
tRAS

~

rL. ,-L

tAR

+

I

tRCD

tRSH

:

.CSH

-'

tCAS

fl

\
f--tRAHtASR--jADDRESS

~
ex

-tCAHtASc---j-

_fflCS-1

fflCR

YYYV

tRWL

I I

lA

I
0:

I
INPUT STABLE

tDS~_
DO

~fflCH~ LIXX
tr

I

01

IYY](
:11'11'11'

COLUMN ADDRESS

ROWADORESS

-tCRP-

(OFF)

:X

'11'11'1
'11'11'11'

I----tDH--=/

tDHR

MOS·193

4-62

Am9016
SWITCHING WAVEFORMS (Cont.)
READ-WRITE/READ-MODIFY-WRITE CYCLE
tRMW
tRAS

~ fL

.AR

..,f_

.RcD----l

.RSH

I
I

tCAS

~K
tASR_~
ADDRESS

~

ROW
ADDRESS

..,~

I..J~

I

f-. CAH _

RAH
-.

.RP _

f-- , - . C R P -

tCSH

tAse---t--

~

COLUMN
ADDRESS
tRWO

I----tCWLtRWL

.CWD

t-.RCS--j

~~
f---.CAC_

I

r---'WP --!

tRAe

DO

I----t-~FF
~
~

OUTPUT VALID

.DS-l

I--'DH

MOS-t94

RAS ONLY REFRESH CYCLE
---------~_I-----.RAS-----l.J~------~L

IVIH)

~----------+~------------------------

r

ADDRESS

tASA

~

oo_~I~OF~F~I

tRAH---1

ROW ADDRESS

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

MOS-195

--------Ie-

PAGE MODE CYCLE

~~t--:--,tARI---_'RAS--q

IF-----.~-H~I--+II---.~-----~I-------~~-------.R-S-H----

I

I--f------.:-RC..,.D--' -

I-- tCp-l

""\ _-tCAS_

tASc-r-

~f--'RAH

ADDRESS

~

IQOO()(X.

ROW
ADDRESS

-~

V~I'--_ ___

""'I'"

t~~...____-j,r

f-

_ _ tCAH

1

COLUMN
,,\ ADDRESS

COLUMN

~ ADDRESS

J.l-tCACI-----.RAC-----.

'\
,

'fif

~.WCH

t - - - - - - - ; - - - t W C R - - _ i I__ _ _ _
'_--iI

r-

WE~m~r---~~~~

r-

f---tOFF

r - - .........

DO------~------~----_

TC =1 23oC
1.1

II

o
2=..
u

~

1.0

~

<
II:

...............

>
U)

1.1

II

U
~
U

0.8

u

<
~

iii"
m
2=..
u

<
11

~ 0.9
6'

0.9

u
2=..
u 0.8

0.8

<

IE

0.7
-4.0

14

13

12

1.0

oct

IE

0.7
10

1.1

u

2=.. 1.0

~

S

-5.0

-4.5

-5.5

0.7
4.0

-6.0

4.5

5.5

6.0

VBB - VOLTS

VCC - VOLTS

Typical Access Time (Normalized)
tRAC Versus
Case Temperature

Typical Operating Current
1001 Versus VOO

Typical Standby Current
1002 Versus VOO

1.4

l?
('II

u

!::.

1.2
1.1

/

~

1.0

U

0.9

/

!::.

S

VV

1

Tc = 23°C

25

l/

~

E

0

e

t--

1.2

<

V

0.8
-55 -35 -15 5

1.4
Tc = 23·C

V

U

<
II:

30

v~

II

('II

o

15

e

1.0
0.8
0.6

L---

25 45 65 85 105125

13

12

11

0.4
10

14

~

----

12

11

~

13

14

TC. CASE TEMPERATURE - ·C

VOO - VOLTS

vee - VOLTS

Typical Refresh Current
1003 Versus VOO

Typical Page Mode
Current
1004 Versus VOO

Typical Operating Current
1001 Versus
Case Temperature

16r---~----~--~--~

16

14r----+----+----4--~

14

voo =
~

5.0

VOO SUPPLY VOLTAGE - VOLTS

IT

<

= 23°C

III

~ 0.9

<

1.2

1

Tc

m

o
2=..
U

1.2

U)

I

o

Typical Access Time
(Normalized)
tRAC Versus VCC

Typical Access Time
(Normalized)
tRAC Versus VBB

oct
E

12 r----+--

M

~

e

e

o

13.2V

<

E

12

o

0

9

5~~~~~~~~~~

12

11

1.4

13

14

0.6

25 45 65 85 105 125

TC. CASE TEMPERATURE - ·C

Typical Standby Current
1002 Versus
Case Temperature

Typical Refresh Current
1003 Versus
Case Temperature

Typical Page Mode Current
1004 Versus
Case Temperature

16

Joo 1= 1~.2J

l

Joo =
14
oct

~ 1.0
o 0.8

-55 -35 -15 5

14

VOO - VOLTS

I-...

e

13

VOO - VOLTS

1.2

('II

12

11

E

I"'- r-.....

12

t"--... r-...

E
e

. . . . r--..

0.4
-55 -35 -15 5 25 45 65 85 105125
TC. CASE TEMPERATURE - ·C

10

....

I

rIC==>7~ f-- ......
I

I

I I

I

_I

'--

. . . . r-.,

+2~

<

E

tRC == 500ns
I
tRC ::75clns
l""-

III

6
-55 -35 -15 5

25 45 65 85 105125

Tc. CASE TEMPERATURE - ·C

5 25 45 65 85 105 125
TC. CASE TEMPERATURE - ·C
MOS-197

4-65

Am9016
TYPICAL CHARACTERISTICS (Cont.)
Input Voltage Levels
Versus VDD
3.0

en

!:i
0

>
I

2.0

....I

W

>
w
....I

1.5

I~
Q.

3!:

3.0

TC = 23·C
VBB = -5V
2.5

I

-

'11HClMIN)

'11\'~~

-

!:i

0

>
I

>
w

l-

3!:

0.5

14

12

11

10

0.5
-4.0

14

13

-4.5

-5.0

-5.5

-6.0

VBB - VOLTS

Input Voltages Levels
Versus vee

Input Voltage Levels
Versus
Case Temperature

Input Voltage Levels
Versus
Case Temperature

3.0
TC = 23·C
VDD = 12V

3.0
VDD = 12V
VBB = -5V

~

2.5

W

1.5

VIL

....I
W

(~AX)

i

I

>

~

W

>

3!:

-4.5

-5.0

-5.5

r--

5

~
Q.

1.0

1.5 -

~

1.5

~

1.0

VBB - VOLTS

:-- t--

1.0
0.5
-55 -35 -15 5 25 45 65 85 105125

0.5
-55 -35 -15 5 25 45 65 85 105 125

-6.0

=ru-

2.0 ;;;;:;:: ~ -V/H(M/N)

I
....I

I-

5

J

>

I

V/LC (MAX)

f--

VDD = 12V
VBB = -5V

2.5

o

vlHcl(MI1)
2.0

I

V!l-i{MIN)

~

2.5

o
>
2.0

0.5
-4.0

1.0

3!:

VDD - VOLTS

....I

~

~
Q.

1.0

VDD - VOLTS

~
;

1.5

....I

~

13

~MAX)

VILC

W

>
W

1.5

....I

ll.

12

2.0

I
....I

W

I-

11

VIHCI(MIN)

>

2.0

....I

1.0

2.5

!:i

0

~

TC =.23·C
VDD = 12V

en

2.5

3.0

I

3.0
Tc = 23·C
VBB = -5V

en

~

0.5
10

~

Input Voltage Levels
Versus vee

Input Voltage Levels
Versus VDD

TC. CASE TEMPERATURE - ·C

T C. CASE TEMPERATURE - ·C

TYPICAL CURRENT WAVEFORMS
LONG RAS/CAs

RAs"

+20
0

IL

__ I

1/\

r
V

-20
-40
+100
+80
+60
+40
100 - mA

+20
0

0

I \

.L

v

"-

j

11

\..

I
I Il

1\ 1\
III

r

I

II

1'1

II \

\

U

'''-

1\

IV

.......

1\

' .......

I
l

In

r~

V

I II
,/\
v I\.~ ~ \

r.

111

f\

I
I \

\
I \

,-J

,

J1

~.

v. .

t-

'v

\1\

L

1,,- 1/'1

f\.

II

III A.

+80
+60
+40
+20

l,= r....·~J.I
'\

/ v \

+100

ISS - mA

...... -

/

CAS

IBB - mA

RAS ONLY

I\.

I

J

~

I \

I-_J

1

1_
Ij

\,

1\

III
J \

1I V

'/
I

(
)

\

50ns/DIV

MOS·19B

4-66

Am9016

V-Address Lines
VSS PAD

LJ
000000 1

I

-X
C\I

')(
<0
....

~

aa

1

')(0 1 a
1 1

3

~xr

-

_I~o1

Data Array Left

a

0

7

Data Array Right

~

~

a

15

1
0

31

1
Row Decode Transition

Column Decode Transition

AO
Al
A2
A3
A4
A5
A6

every
every
every
every
every
every
every

64
16
32
8
4
2
4

columns
columns
columns
columns
columns
columns
columns

a

1 1 1 1 1 1

63

1

aaaaa 1
aa
I 1a

65

1 1

67

~
go

AO
A1
A2

A3
A4
A5
A6

~-I

I

~0

every 64
every 16
every 32
every 8
every 4
every 8
every 8

rows
rows
rows
rows
rows
rows
rows

71

~~
-~
79

0

95

1

AO
A1
A2
A3
A4
A5
A6

(64x)
1
1---(16x)
• 1/ a
1---(32x)
1-(8x)-10
1111
0000
1100
0011
1001
0110

I

::IJ
o

:E

o

.a

1 1 1 1 1 1 1

127

a
(64x)
1--(16X)-11°
1--(32x)
1-(8x)--10
1111
0000
1100
0011
0110
1001

1

. 1a

a
a
a

1
0

• 1

a

::IJ

::IJ

::IJ

::IJ

::IJ

::IJ

:E
w

:E

:E

:E

:E

:E

0>

0>

0

.j:>.

0

-...j

0

:1

0

-...j

<0

X-Decode Right

X-Decode Left

TOPOLOGICAL BIT MAP

4-67

a
a
a
1
1

I

o

. aa

0

<0

U1

::IJ
0

:E

N
-...j

Am9016
ORDERING INFORMATION

Ambient
Temperature

O°C",;; TA"';; +70°C

-55°C",;; TA"';; +85°C

Access Time

Package
Type

300ns

250ns

200ns

150ns

Hermetic DIP

AM9016CDC

AM9016DDC

AM9016EDC

AM9016FDC

Molded DIP

AM9016CPC

AM9016DPC

AM9016EPC

AM9016FPC

Chip-Pak

AM9016CLC

AM9016DLC

AM9016ELC

AM9016FLC

Hermetic DIP

AM9016CDL

AM9016DDL

AM9016EDL

-

Chip-Pak

AM9016CLL

AM9016DLL

AM9016ELL

-

Metallization and Pad Layout
VSS

012-------,
WE

, - - - - - 1 5 CAS

3--'I"-,~",j:-

RAg 4

14 DO
13 A6

AO 5

12 A3

A26

11 A4

A17----'

' - - - - - 1 0 A5
VOO 8 - - - - - - ' ' - - - - - - 9 VCC
DIE SIZE 0.107" X 0.205"

4-68

MOS Read Only
Memories (ROM) Index
Am9218/8316E
Am9232/9233
Am9264
Am9265
Am92128
Am92256

2048 x 8 Read Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
4096 x 8 Read Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-4
64K (8192 x 8) Read Only Memory .............................. 5-8
64K (8192 x 8) Read Only Memory ...........................•.. 5-12
128K (16,384 x 8) Read Only Memory ............................ 5-15
256K (32,768 x 8) Read Only Memory ............................ 5-18

Am9218/8316E
2048 x 8 Read Only Memory

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•
•
•

The Am9218 devices are high performance, 16384-bit, static,
mask programmed, read only memories. Each memory is
implemented as 2048 words by 8 bits per word. This organization simplifies the design of small memory systems and
permits incremental memory sizes as small as 2048 words.
The fast access times provided allow the ROM to service high
performance microcomputer applications without stalling the
processor.

2048 x 8 organization
Plug-in replacement for 8316E
Access times as fast as 350 ns
Fully capacitive inputs - simplified driving
3 fully programmable Chip Selects - increased flexibility
Logic voltage levels compatible with TTL
Three-state output buffers - simplified expansion
Drives two full TTL loads
Single supply voltage - +5.0V
Low power dissipation
N-channel sil icon gate MOS technology
100% M I L-STD-883 reliability assurance testing
Am2716 compatible

Three programmable Chip Select input signals are provided to
control the output buffers. Each Chip Select polarity may be
specified by the customer thus allowing the addressing of 8
memory chips without external gating. The outputs of unselected chips are turned off and assume a high impedance
state. This permits wire-DRing with additional Am9218
devices and other three-state components.
These memories are fully static and require no clock signals of
any kind. A selected chip will output data from a location
specified by whatever address is present on the address input
lines. Input and output voltage levels are compatible with
TTL specifications.

BLOCK DIAGRAM

CONNECTION DIAGRAM

Al0
A9
A8
A7

STORAGE
ARRAY
128 X 128

ROW
DECODER

A6

ADDRESS 7

24

VCCI+5.0VI

ADDRESS 6

23

ADDRESS 6

ADDRESS 5

22

ADDRESS 9

ADDRESS 4

21

CS31CSJ

A5
A4

ADDRESS 3

20

CS11CSl

ADDRESS 2

19

ADDRESS 10

16

CS21CS2

Am9218

ADDRESS 1
A3
A2
Al
AO

ADDRESS 0

17

OUPTUT 8

OUTPUT 1

16

OUTPur7

OUTPUT 2

10

15

OUTPUT 6

OUTPUT 3

11

14

OUTPUT 5

IGNDI VSS

12

13

OUTPUT 4

CSI
CS2
CS3

Top View
01

MOS-515

02

03

04

05

06

07

08

Pin 1 is marked for orientation.

MOS-516

ORDERING INFORMATION

Package Type

Ambient Temperature
Specifications

Access Time
450ns

350ns

Molded

O°C

~

TA

~

70°C

AM9218BPC
P8316E

AM9218CPC

Cerdip

O°C

~

TA

~

70°C

AM9218BCC

AM9218CCC
AM9218CDC

Side-Brazed
Ceramic

O°C

~

TA

~

70°C

AM9218BDC
C8316E

-55°C

~

TA

~

+125°C

AM9218BDM

5-1

Am9218/8163E
MAXIMUM RATINGS (Above which the useful life may be impaired)
Storage Temperature
Ambient Temperature Under Bias
+7.0V

VCC with Respect to VSS
DC Voltage Applied to Outputs

-O.5V to +7.0V

DC Input Voltage

-O.5V to +7.0V

Power Dissipation

1.0W

The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.

ELECTRICAL CHARACTERISTICS
Am9218BDC
Am9218CDC
C8316A

VCC

Parameters

Description

= 5.0V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

±5%

Am9218XDC
Min.
Max.

Test Conditions

9218

= -200).LA
IOH = -100).LA
IOL = 3.2mA

8316E

IOL =2.1mA

9218

IOH

8316E

Min.

C8316E
Max.

Units

2.4

Volts

2.4
0.4

Volts

0.4
2.0

vce +1.0

Volts

-0.5

0.8

Volts

10

10

).LA

Input Leakage Current

10

10

).LA

VCC Supply Current

70

95

mA

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

-0.5

ILO

Output Leakage Current

III
ICC

VCC

+ 1.0

0.8

Chip Disabled

ELECTRICAL CHARACTERISTICS
T.".

Am9218BDM

= _55°e

vee

= 5.0V

to +125°e
±10%

Parameters

Description

Test Conditions

VOH

Output HIGH Voltage

IOH = -200).LA

VOL

Output LOW Voltage

IOL = 3.2mA

VIH

Input HIGH Voltage

Am9218B
Min.
Max.

Units
Volts

2.2
0.45
2.0

VCC

+ 1.0

Volts
Volts

0.8

Volts
).LA

I nput Leakage Current

10
10

VCC Supply Current

80

mA

VIL

Input LOW Voltage

ILO

Output Leakage Current

III

lec

-0.5
Chip Disabled

p,A

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Am9218XDC!e8316E

TA

Am9218BDM

TA

Parameters

= oOe to +70o e
= -55°e to +125°e

Description

= 5.0V

± 5%

vee

= 5.0V

± 10%

Am9218B
Min.
Max.

Test Conditions

ta

Address to Output Access Time

tCO

Chip Select to Output ON Delay

tOH

Previous Read Data Valid with
Respect to Address Change

tr = tf = 20ns
Output Load:
one standard TTL gate

tDF

Chip Select to Output OFF Delay

CI

Input Capacitance

CO

Output Capacitance

Notes: 1. Timing reference levels: High

vee

= 2.0V,

8316E
Min.
Max.

Units

450

350

450

ns

150

130

250

ns

20

plus 100pF (Note 1)

Low

Am9218C
Min.
Max.

-

20

ns

150

130

250

ns

TA = 25°C, f = 1.0MHz

7.0

7.0

7.0

pF

All pins at OV

7.0

7.0

7.0

pF

= O.8V.

SWITCHING WAVEFORMS
ADDRESSES·

~,--

________
ST_A_BL_E_ _ _ _ _ _ _- - ,

I

SEL~~~ ~~~~~DI~SA~B~L_E-D~~~~~I~~~~_-~X:
f--

ENABLED

teO

I
I
I-- -j

--j

tOH

x:

f-

DISABLED

tDF

--j

I
D~~~ -------;...I--------~
~:~,~' ~
5-2

MOS-517

Am9218/8163E
PROGRAMMING INSTRUCTIONS
CUSTOM PATTERN ORDERING INFORMATION
The Am9218 is programmed from punched cards, card coding forms or paper tape in card image format as shown below.
Logic "1" = a more positive voltage (normally +5.0 V)
Logic "0" = a more negative voltage (normally OV)
FIRST CARD
Column Number
10 thru 29
32 thru 37

Description
Customer Name
Total number of "1 's" contained in the data.
This is optional and should be left blank if not used.

50 thru 62
65 thru 72

8316E or 9218
Optional information

SECOND CARD
Column Number
29
31
33

Description
CS3 input required to select chip (0 or 1)
CS2 input required to select chip (0 or 1)
CSl input required to select chip (0 or 1)

Two options are provided for entering the data pattern with the remaining cards.
OPTION 1 is the Binary Option where the address and data are presented in binary form on the basis of one word per card. With
this option 2048 data cards are required.
Column Number
10,12,14,16,18
20,22,24,26,28,30

Address input pattern with the most significant bit (A 10) in column 10 and the least significant bit
(AO) in column 30.

40, 42, 44, 46, 48,
50,52,54

Output pattern with the most significant bit (08) in column 40 and the least significant bit (01) in
column 54.

73 thru 80

Coding these columns is not essential and may be used for card identification purposes.

OPTION 2 is the Hexadecimal Option and is a much more compact way of presenting the data. This format requires only 128 data
cards. Each data card contains the 8-bit output information for 16 storage locations in the memory. The address indicated
in columns 21, 22 and 23 is the address of the data presented in columns 30 and 31. Addresses for successive data are assumed to
be in incremental ascending order from the initial address. Since the address in columns 21, 22 and 23 always points only to the
first data on the card, column 23 is always zero. Columns 21 and 22 take all hex values from 00 through 7F: 128 cards in all. Data
is entered in hex values and may be any combination of 8 bits, that is, hex values from 00 through FF.
A
D
D
R

121122123

OUTPUT VALUES FOR ADDR +
0

1

2

3

4

5

7

6

8

9

30131 3233134 35 36137 38 39140 4142143 44 45146 47 48149 50 51152 53 54155 56 57158

A
5960161

B

C

D

E

F

62 63164 6566167 68 69170 71 72173 74 75176

~

I

1

1

I

1

1

1

I

1

I

1

1

I

1

I

1

~
~

1

1

1

1

1

1

1

I

1

1

1

I

I

1

1

1

I

I

I

I

I

I

I

I

I

I

1

I

I

I

I

I

1

I

1

I

1

I

1

I

I

I

1

I

•
0

•
I---

~

I

I

I

I

I

I

I

I

I

~

I

I

I

I

I

I

I

I

I

1
J

1

1

I

I

1

1

1

1

1

1

I

I

I

1

I

1

I

I

•
•

•

Gl;J

1

1

1

I

I

I

I

•

•
0

~

I

1

1

I

1

I

I

5-3

Am9232
• Am9233
x
4096

8 Read On.y Memory

DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

•
•
•
•
•

The Am9232/33 devices are high performance, 32,768-bit,
static, mask programmed, read only memories. Each
memory is implemented as 4096 words by 8 bits per word.
This organization simplifies the design of small memory
systems and permits incremental memory sizes of 4096
words. The fast access times provided allow the ROM to
service high performance microcomputer applications
without stalling the processor.

•
•
•
•
•
•
•
•

4096 x 8 organization
No clocks or refresh required
Access time selected to 300ns
Fully capacitive inputs - simplified driving
Two mask programmable chip selects increased flexibility
Logic voltage levels compatible with TTL
Three-state output buffers - simplified expansion
Drives two TTL loads
Single + 5 volt power supply
Two different pinouts for universal application
Low power dissipation
100% MIL-STD-883 reliability assurance testing
Non-connect option on chip selects

Two programmable Chip Select input signals are provided
to control the output buffers. Each Chip Select polarity may
be specified by the customer thus allowing the addressing
of 4 memory chips without external gating. The outputs of
unselected chips are turned off and assume a high impedance state. This permits wire-ORing with additional
Am9232/33 devices and other three-state components.
These memories are fully static and require no clock signals
of any kind. A selected chip will output data from a location
specified by the address present on the address input lines.
Input and output voltage levels are compatible with
TTL !';f1flr.ific;Jtion!';.

CONNECTION DIAGRAMS
Top Views

ADDRESS 7

24

VCC (+5.0V)

ADDRESS 7

VCC (+5.0V)

ADDRESS 6

23

ADDRESS 8

ADDRESS 6

ADDRESS 8

ADDRESS 5

22

ADDRESS 9

ADDRESS 5

ADDRESS 9

ADDRESS 4

21

CS2/CS2/NC

ADDRESS 4

ADDRESS 11

ADDRESS 3

Am9232

ADDRESS 2

20

CS1/CS1/NC

ADDRESS 3

CS1/CS1/NC

19

ADDRESS 10

ADDRESS 2

ADDRESS 10

ADDRESS 1

18

ADDRESS 11

ADDRESS 1

CS2/CS2/NC

ADDRESS 0

17

OUTPUT 8

ADDRESS 0

OUTPUT 8

16

OUTPUT 7

OUTPUT 1

OUTPUT 7

OUTPUT 2

OUTPUT 1
10

15

OUTPUT 6

OUTPUT 2

OUTPUT 6

OUTPUT 3

11

14

OUTPUT 5

OUTPUT 3

OUTPUT 5

(GND) VSS

12

13

OUTPUT 4

(GND) VSS

OUTPUT 4

MOS-l03

Note: Pin 1 is marked for orientation.

MOS-l04

ORDERING INFORMATION
Access Time

Package Type

Ambient Temperature
Specifications

450ns

300ns

Molded

O°C.:;; TA .:;; +70°C

AM9232133BPC

AM9232133CPC

Cerdip

O°C.:;; TA .:;; +70°C

AM9232/33BCC

AM9232/33CCC

Side-Brazed
Ceramic

-55°C.:;; TA .:;; +125°C
O°C .:;; T A .:;; + 70°C

AM9232/33BDM
AM9232/33BDC

AM9232/33CDC

5-4

Am9232/9233
MAXIMUM RATINGS beyond which the useful life may be impaired
Storage Temperature
Ambient Temperature Under Bias
vee with Respect to VSS

+7.0V

De Voltage Applied to Outputs

-O.5V to +7.0V

De Input Voltage

-O.5V to + 7.0V

1.0W

Power Dissipation (Package Limitation)

The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations
of static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to
avoid exposure to excessive voltages.

OPERATING RANGE
Part Number

Am9232/33DM

VSS

VCC

Ambient Temperature

Am9232DC/PC/CC

O°C ~ TA ~ + 70°C
-55°C

~

T A ~ +125°C

ELECTRICAL CHARACTERISTICS over operating range
Parameter

Description

VOH

Output HIGH Voltage

IOH

= -200/LA

VOL

Output LOW Voltage

IOL

= 3.2mA

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

III

Input Load Current

ILO

Output Leakage Current

ICC

VCC Supply Current

CI

Input Capacitance

CO

Output Capacitance

Am9232/ Am9233

Test Conditions

~

VSS

VI

~

Min.

= 4.75
VCC = 4.50
VCC

Max.

Volts

2.2
0.4

Volts

2.0

VCC+1.0

Volts

-0.5

0.8

Volts

10

/LA

VCC

VSS ~ VO ~ VCC
Chip Disabled

Unit

2.4

+70°C

10

+125°C (DM)

50

O°C

80

-55°C (DM)

100

TA = 25°C, f = 1.0MHz
All pins at OV

/LA

mA

7.0

pF

7.0

pF

SWITCHING CHARACTERISTICS over operating range

Am9232/338

Am9232/33C

Parameter

Min.

Min.

Description

Test Conditions

ta

Address to Output Access Time

tCO

Chip Select to Output ON Delay

tOH
tDF

450
150

tr = tf = 20ns
Output Load:
one standard TTL gate

Previous Read Data Valid with
Respect to Address Change

Max.

20

Max.

Unit

300
120

ns
ns
ns

20

plus 100pF (Note 1)
150

Chip Select to Output OFF Delay

120

ns

Note 1. Timing reference levels: High = 2.0V, Low = 0.8V.

SWITCHING WAVEFORMS

~DDRESSES~

.

SEL;~~~

~

STABLE

1"'---------------'1

..JX

__
DIS_A_BL_ED_---:-I_ _

ENABLED

I

X
:xxxxxxm-

f--ICO-j~~~-f--IO-H-j

DATA
OUT

I
-----...;..------~
I

OUTPUT

DISABLED

f-IDF-j

~__V_AL_ID_....~
.......................................

~.---------b

I
5-5

MOS·105

Am9232/9233
PROGRAMMING INTRUCTIONS
CUSTOM PATTERN ORDERING INFORMATION

The Am9232 is programmed from punched cards, card coding forms or paper tape in card image format as shown below.
Logic "1" = a more positive voltage (normally +5.0V)
Logic "0" = a more negative voltage (normally OV)
FIRST CARD
Description
Customer Name
Total number of "1 's" contained in the data.
This is optional and should be left blank if not used.
9232 or 9233
Optional information

Column Number
10 thru 29
32 thru 37

50 thru 62
65 thru 72
SECOND CARD
Column Number
31
33

Description
CS2 input required to select chip (0 or 1); If CS2 = NC, column 31 = 2.
CS1 input required to select chip (0 or 1); If CS1 = NC, column 33 = 2.

Two options are provided for entering the data pattern with the remaining cards.
OPTION 1 is the Binary Option where the address and data are presented in binary form on the basis of one word per card. With
this option 4096 data cards are required.
Column Number
8, 10, 12, 14, 16, 18
20,22,24,26,28,30

Address input pattern with the most significant bit (A 11) in column 8 and the least significant
bit (AO) in column 30.

40,42,44,46,48
50,52,54

Output pattern with the most significant bit (08) in column 40 and the least significant bit (01)
in column 54.

73 thru 80

Coding these columns is not essential and may be used for card identification purposes.

OPTION 2 is the Hexadecimal Option and is a much more compact way of presenting the data. This format requires only 256 data
cards. Each data card contains the 8-bit output information for 16 storage locations in the memory. The address indicated in
columns 21, 22 and 23 is the address of the data presented in columns 30 and 31. Addresses for successive data are assumed to
be in incremental ascending order from the initial address. Since the address in columns 21, 22 and 23 always points only to the
first data on the card, column 23 is always zero. Columns 21 and 22 take all hex values from 00 through FF:256 cards in all. Data
is entered in hex values and may be any combination of 8 bits, that is, hex values from 00 through FF.

A
D
D
R
121122123

~
~
~

OUTPUT VALUES FOR ADDR +

0
30

1

13 1 3233134

2

3

4

5

6

7

8

9

A

B

C

D

E

F

35 36137 3839140 41421 43 44 45146 47 48149 50 51152 5354155 56 57158 5960161 62 63164 6566167 68 69170 71 72173 74 75176

1

1

I

1

I

I

I

I

I

I

I

I

I

I

I

1

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

1

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

•
•
•

t--

~
~

I

I

I

I

I

I

I

I

I

I

I

I

I

I

•

•
•

[;l;J

I

I

I

I

I

I

I

•

~

•
•

I

I

I

I

I

I

I
5-6

Am9232/9233
Am9232/Am9233
BLOCK DIAGRAM

A11
A1D
A9
A8

STORAGE
ARRAY
128 x 256

ROW
DECODER

A7
A6
AS

A4
A3
A2
A1
AD

COLUMN DECODER

CSI

01

02

03

04

05

06

07

08
MOS-10e

5-7

Am9264

64K (8192 x 8J Read Only Memory
PRELIMINARY
DISTINCTIVE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

• Enhanced manufacturability with post-metal
programming
• Access time - 250ns (max)
• Single +5V ±10% power supply
• Fully static operation
• Completely TIL compatible
• Standard 24 pin DIP
• Pin compatible with 16K/32Ki64K EPROMs/ROMs
• INT-STD-123 - guaranteed to O.1%AQL
• Military version (- 55 to + 125°C) - Available
- 450ns (max) access time

The Am9264 high performance read only memory is organized 8192 words by 8 bits with access times of less than
250ns. This organization simplifies the design of small memory systems and permits incremental memory sizes of 8192
words. The fast access times provided allow the ROM to
service high performance microcomputer applications without stalling the processor.
The programmable chip select input signal is provided to
control the output buffers. Chip Select Polarity may be provided by the customer thus allowing the addressing of 2
memory chips without external gating. The outputs of the
unselected chips are turned off and assume a high impedance state. This permits wire-ORing with additional Am9264
devices and other three state components.
This memory is fully static and requires no clock signals of
any kind. A selected chip will output data from a location
specified by the address present on the address input lines.
Input and output levels are compatible with TIL specifications.
The ability to program customer code at the last step of
fabrication (Post Metal Programming Technique) will result
in faster turn around time for new or old patterns. This
technique will allow us to test wafers before committing
customer patterns to categorize speed and power dissipation requirements.

CONNECTION DIAGRAM
Top View
A7

C~ P

Vcc(+S.OV)

Ase2

23PAs

AsC3

22PAg

~
A3
A2

C

C
C

4

21

S

20

S

c:::: 7
Ao c:::: S
01 c:::: 9
02 c:::: 10
0 3 c:::: 11
(GND) Vss c:::: 12
Al

P

P

A12

CStCS

19 PAlO

Am9264
IS p A l l
17

16
IS
14

13

P
P
P
P

P

Os

07
06
Os

04

Note: Pin 1 is marked for orientation.

ROM·01O

ORDERING INFORMATION

Package Type

Access Time

Ambient Temperature
Specifications
~

450ns

300ns

250ns

Molded

O°C

TA

.;;

+70°C

AM9264BPC

AM9264CPC

Cerdip

O°C ~ TA

.;;

+70°C

AM9264BCC

AM9264CCC

AM9264DCC

Ceramic
Side-Brazed

O°C ~ TA

.;;

+70°C

AM9264BDC

AM9264CDC

AM9264DDC

+125°C

AM9264BDM

-55°C.;;

TA';;

5-8

AM9264DPC

Am9264
MAXIMUM RATINGS

beyond which the useful life may be impaired

Storage Temperature

-65 to +150°C

Ambient Temperature Under Bias

-55 to + 125°C

VCC with Respect to VSS

+7.0V

DC Voltage Applied to Outputs

-0.5 to + 7.0V

DC Input Voltage

-0.5 to + 7.0V

Power Dissipation (Package Limitation)

1.0W

The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.

OPERATING RANGE
Part Number

Ambient Temperature

VCC

Am9264DC/PC/CC

+5.0V ±10%

Am9264DM

+5.0V ±10%

ELECTRICAL CHARACTERISTICS
Parameter

VSS

over operating range

Description

Test Conditions

Min.

Max.

Unit

VOH

Output HIGH Voltage

IOH = -200JLA

VOL

Output LOW Voltage

IOL = 3.2mA

0.4

Volts

V IH

Input HIGH Voltage

2.0

Vee +1.0V

Volts

V IL

Input LOW Voltage

-O.S

O.S

Volts

III

Input Leakage Current

VSS ~ VI ~ VCC

10

JLA

ILO

Output Leakage Current

Vss ~ Vo ~ ~ Vee
Chip Disabled

10
SO

/LA

lee

Vee Supply Current

2.4

Volts

+70°C
+12SoC (OM)
O°C

80

-SsoC (OM)

100

CI

Input Capacitance

TA = 2SoC, f = 1.0MHz

7.0

Co

Output Capacitance

All pins at OV

7.0

SWITCHING CHARACTERISTICS
Parameter

over operating range

Description

Test Conditions

TA

Address to Output Access time

teo

Chip Select to Output on Delay

tOH

Previous Read Data Valid with
Respect to Address Change

tOF

Chip Select to Output OFF Delay

Note 1: Timing reference levels: High

=

2.0V. Low

tr

Am92648
Min.
Max.

= tf = 20ns

Output Load:
one standard TTL gate
plus 100pF
(Note 1)

pF

Am9264D
Min.
Max.

Unit

450

300

2S0

ns

1S0

120

100

ns

20

20
120

=

Am9264C
Min.
Max.

mA

20
100

ns
SO

ns

O.SV.

SWITCHING WAVEFORMS
ADDRESS
INPUTS

CHIP
SELECT
INPUTS

DATA
OUTPUTS

HIGH
IMPEDANCE

ROM·Oll

5-9

Am9264
ROM CODE DATA
EPROM

AM D's preferred method of receiving ROM CODE DATA is in EPROM. Two EPROMs programmed with identical data should be
submitted. AMD will read the programmed EPROM and generate an Intel Hex paper tape. The second EPROM is compared with
Intel Hex paper tape to insure that both EPROMs have identical data. Then AMD generates a PG tape (Pattern Generation) which is
used to make masks after customer gives a code approval. One of the EPROMs is erased and then it is programmed from AMD's
data base. The AMD programmed EPROM is returned to the customer for code verification of the ROM program. Unless otherwise
requested, AMD will not proceed until the customer verifies the program in the returned EPROM. AMD requests a written verification
form (supplied by AMD with programmed EPROM) signed by customer before proceeding to any further work.
The following EPROMs should be used for submitting ROM CODE DATA:

ROM

Am9208
Am9217/18
Am9232/33
Am9264
Am9265

EPROM

1K
2K
4K
8K
8K

Preferred
2708
2716
2732
2764
2764

x8

x8
x8
x8
x8

Optional

2516/2-2708
2532/2-2716
4-2716/2-2732
4-2716/2-2732

If more than one EPROM is used to specify one ROM pattern, (Le., 4 16K EPROMs or 2 32K EPROMs for one 64K ROM) two complete
sets of programmed EPROMs should be submitted. In this instance, the programmed EPROMs must clearly state which of the two orfour
EPROMs is for lower and upper address locations in the ROM.
CARD FORMAT

If customer prefers to submit punch cards, be sure to provide the industry standard formats, such as:
AMD HEXADECIMAL (PREFERRED)
INTEL HEXADECIMAL
INTEL BPNF
MOTOROLA HEXADECIMAL
EA OCTAL
G.I. BINARY
CHIP SELECT INFORMATION

Regardless of the method of submitting ROM CODE DATA (EPROM or CARDs), the chip select information must be specified at the time
of customer input data. EPROMs do not have programmable chip selects and, therefore, cannot provide the required chip select
information.
KEY POINTS

•
•
•
•
•

Obtain AMD's 5 digit code number from product marketing
Supply chip select information
Supply customer part number and appropriate AMD part number
Supply marking information
Instruction on whether prototype approval is required prior to production or AMD is allowed to go straight to production (in case of code
change or error, customer is liable for all products in line) after customer code approval.

5-10

Am9264
BLOCK DIAGRAM
A12
All
A10
Ag
AS

STORAGE
ARRAY
256 x 256

ROW
DECODER

A7
A6
AS

A4
A3

COLUMN
DECODER

A2
Al
AO

cstcs

CHIP
SELECT
DECODER

OUTPUT
BUFFERS

01 02 03 04 05 06 07 08
ROM-012

5-11

Am9265
x

64K (8192

8) Read Onlv Memorv

PRELIMINARY
DISTINCTIVE CHARACTERISTICS
•
•
•
•
•

•
•
•
•
•
•
•

FUNCTIONAL DESCRIPTION
The Am9265 high performance read only memory is organized 8192 words by 8 bits with access times of less than
250ns. This organization simplifies the design of small
memory systems and permits incremental memory sizes of
8192 words. The fast access times provided allow the ROM
to service high performance microcomputer applications
without stalling the processor.

Enhanced manufacturability with post metal programming
Access time - 250ns (max)
Fully static operation
Single +5V ± 10% power supply
Automatic power down feature controlled by
separate CE pin.
80mA max operating current
20m A max standby current
Separate OE pin for tri-state output control
Two programmable chip selects with no-connect option
Pin compatible with 28 pin 64K and higher density
ROMs/EPROMs
Completly TTL compatible
Standard 28 pin DIP
INT-STD-123 - guaranteed to 0.1% AQL.
Military version (-55 to +125°C) - Available with
450ns (max) access time

Two programmable chip select inputs are provided to control
the output buffers. Chip select polarity may be specified by
the customer thus allowing the addressing of 4 memory
chips without external gating. The outputs of the unselected
chips are turned off and. assume a high impedance state.
This permits wire-~Ring with additional Am9265 devices
and other three state components. No-connect option on
chip selects can be provided if desired by the customer.
This memory is fully static and requires no clock signals of
any kind. A selected chip will output data from a location
specified by the address present on the address input lines.
Input and output levels are compatible with TTL specifications. A !>p.parate OE. output enable pin. controls outputs
providing greater system flexibility and eliminating bus
contention.

CONNECTION DIAGRAM
Top View
NC

C~ P

VCc(+SV)

Au

C

2

27

CS,/CS,/NC

A7

C

3

26

P
P

AeC4

2SpAe

AsCS

24pA9

~C6

23PA"

A3 C
A2

7

C

Am926S

22

8

2'

C

0,

GND

C

C
C

p OE
P

A,o

P

07

18p

06

12

17

0s

13

16

14

15

'0

19

0oC"

02

The ability to program customer code at the last step of
fabrication (Post Metal Programming Technique) results in
faster turn around time for new or old patterns. This
technique also allows testing of wafers to categorize speed
and power dissipation before committing customer patterns.

20PCE:

A,CS

Ao

The Am9265 features an automatic stand-by mode. When
deselected by CEo the maximum supply current is reduced
from 80mA to 20mA. a 75% reduction.

CS2/CS2/NC

P
PO.

P

03

Note: Pin 1 is marked for orientation

ROM'OO1

OPERATING RANGE
Ambient
Temperature

Part Number

I Am9265DC/PC/CC I
l Am9265DM

Vee

OCC ~ TA ~ + 70 c e

Vss

I +5.0V ±10% I OV

I -55°C ~ TA ~ +125 C I +5.0V ±10% I OV
c

ORDERING INFORMATION

Package Type

Access Time

Ambient Temperature
Specifications

300ns

250ns

AM9265BPC

AM9265CPC

AM9265DPC

AM9265BCC

AM9265CCC

AM9265DCC

AM9265CDC

AM9265DDC

450ns

Molded
Cerdip
Ceramic
Side-Brazed

AM9265BDC
AM9265BDM

5-12

Am9265
MAXIMUM RATINGS

beyond which the useful life may be impaired

Storage Temperature

-65 to +150°C

Ambient Temperature Under Bias

-55 to +125°C

VCC with Respect to VSS

+7.0V

DC Voltage Applied to Outputs

-0.5 to

+ 7.0V

DC Input Voltage

-0.5 to

+ 7.0V

Power Dissipation (Package Limitation)

1.0W

The products described by this specification include internal circuitry designed to protect input devices from damaging accumulations of
static charge. It is suggested nevertheless, that conventional precautions be observed during storage, handling and use in order to avoid
exposure to excessive voltages.

ELECTRICAL CHARACTERISTICS
Parameter

over operating range

Description

Test Conditions

Min

= -400J.LA
= 3.2mA

Max

Unit

VOH

Output HIGH Voltage

IOH

VOL

Ouput LOW Voltage

IOL

VIH

Input HIGH Voltage

2.0

Vee +1.0V

Volts

VIL

Input LOW Voltage

-0.5.

0.8

Volts

III

Input Leakage Current

VSS "" VI "" Vee

10

J.LA

ILO

Output Leakage Current

VSS "" Vo "" Vee
Chip Disabled

leC1

Vee Standby Current

ICC2

VCC Operating Current

CI

Input Capacitance

Co

Output Capacitance

Volts

2.4

Volts

0.4

+70°C

10

+125°C (DM)

50

J.LA

O°C

20

-55°C (DM)

25

O°C
-55°C (DM)

80
100

mA

7.0

pF

7.0

pF

TA = 25°C, f = 1.0MHz
All pins at OV

mA

SWITCHING CHARACTERISTICS over operating range (see notes)
Am9265B
Parameter

Description

Test Conditions

Am9265C

Max

Unit

Address to Output Access Time

450

300

250

ns

tco

Chip Select to Output ON Delay

150

120

100

ns

tOE

Output Enable to Output ON Delay

150

120

100

ns

tCE

CE to Output ON Delay

450

300

250

ns

tOH

Previous Read Data Valid with
Respect to Address Change

tOF

Chip Select to Output OFF Delay

Max

20

Min

Max

Am9265D

tA

tr = tf = 10ns
Output Load
One Standard
TTL Gate Plus 100pF
(Note 1)

Min

20
120

Min

20
100

ns
80

ns

Notes: 1. Timing reference levels: High = 2.0V Low = 0.8V.
2. tOF is the worst case OFF delay. If OE occurs before CE and CS/CS are disabled, then tOF is referenced to OE only. If OE, CS/CS and CE are
disabled simultaneously, then tOF is referenced to all three.

SWITCHING WAVEFORMS

~~>CK)~${X)O(~___________________~)O()O(X)(X)3~VC&S.00

b applies between L1 and L2 • 4>b1 applies betWeen L1 and 0.500"
beyond reference plane.

7-15

6

Package Outlines
PACKAGE OUTLINES (Cont.)
MOLDED DUAL IN-LINE PACKAGES

P-10-1

P-8-1

,~I-_I
A

L
L

'

e

f--+e

P-18-1

P-20-1

SEATING

~,

,I

P-16-1

~b,

T:~--:-+

b----H-

I---E2-J

P-22-1

7-16

A

IIL=
-c
0

P-14-1

I1:::::::~
s,---11-tt~~·-·_
. . . ll.?O
-l

~I_b

iSEATING
-PLANE

!_E2~\

Package Outlines
PACKAGE OUTLINES (Cont.)
MOLDED DUAL IN-LINE PACKAGES (Cont.)

P-2S-'

P-24-'

P-40-1

TE::::::::::::::::] .
sl-l~

A

I

L

-t f

~IIUl
-i.i- - f--b1

p·s-,

p·'O·'

P-'4·'

P·'6·'

b_l~

p·,s-,

Parameters

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

A

.150

.200

.150

.200

.150

.200

.150

.200

.150

.200

b

.015

.022

.015

.020

.015

.020

.015

.020

.015

.055

.065

.055

.065

.055

.065

.055

.065

.055

b,

=

Q

-I

AMD Pkg.

SEATING

WPLANE

D

P·20-'
Min.

c~_

t_E2~\

P·22-'

P·24·'

P-2S-'

P-40·'

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

.150

.200

.150

.200

.170

.215

.150

.200

.150

.200

.020

.015

.020

.015

.020

.015

.020

.015

.020

.015

.020

.065

.055

.065

.055

.065

.055

.065

.055

.065

.055

.065

.009

.011

.009

.011

.009

.011

.009

.011

.009

.011

.009

.011

.009

.011

.009

.011

.009

.011

.009

.011

D

.375

.395

.505

.550

.745

.775

.745

.775

.895

.925

.240

.260

.240

.260

.240

.260

.240

.260

.240

.260

.250

.290

.330

.370

.515

.540

.530

.550

.530

.550

E2

.310

.385

.310

.385

.310

.385

.310

.385

.310

.385

.310

.385

.410

.480

.585

.700

.585

.700

.585

.700

1.0101.0501.0801.1201.2401.2701.4501.4802.0502.080

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

L

.125

.150

.125

.150

.125

.150

.125

.150

.125

.150

.125

.150

.125

.160

.125

.160

.125

.160

.125

.160

Q

.015

.060

.015

.060

.015

.060

.015

.060

.015

.060

.015

.060

.015

.060

.015

.060

.015

.060

.015

.060

S,

.010

.030

.040

.070

.040

.065

.010

.040

.030

.040

.025

.055

.015

.045

.035

.065

.040

.070

.040

.070

Notes: 1. Standard lead finish is tin plate or solder dip.
2. Dimension E2 is an outside measurement.

7-17

Package OUtlines
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN-LINE PACKAGES

TOS
i. ,

0·8·1

0·8·2

4

-l 5, I--

-lb,~

I

D

I

t
PLANE
P~15EATINGH

.Ii !I
~
L-=r-\-e

0·14·1

[

Q

-ll-b
0·14·2

0·14·3

0·16·1

7-18

c--

!-E,--j

Package Outlines
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN-LINE PACKAGES (Cont.)

0-18-1

0-18-2

0-20-1

0-20-2

0-22-1

0-22-2

0-24-1 and 0-24-4

7-19

Package Outlines
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN·L1NE PACKAGES (Cont.)

0-24-4*

0-24-2

0-28-1

0-28-2

0-40-1

0-40-2

0-48-2

7·20

Package Outlines
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN-LINE PACKAGES (Cont.)

AMO Pkg.
Common
Name

0-8-1

0-8-2

CEROIP

SIOEBRAZED

38510
Appendix C

0-14-1

0-14-2

0-14-3
(Note 2)

0-16-1

0-16-2

CERDIP

SIOEBRAZED

METAL
DIP

CERDIP

SIOEBRAZED

-

-

0-1(1)

0-1(1)

0-1(3)

0-2(1)

0-2(3)

Parameters

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

A

.130

.200

.100

.200

.130

.200

.100

.200

.100

.200

.130

.200

.100

.200

b

.016

.020

.015

.022

.016

.020

.015

.022

.015

.023

.016

.020

.015

.022

bl

.050

.070

.040

.065

.050

.070

.040

.065

.030

.070

.050

.070

.040

.065

c

.009

.011

.008

.013

.009

.011

.008

.013

.008

.011

.009

.011

.008

.013

0

.370

.400

.500

.540

.745

.785

.690

.730

.660

.785

.745

.785

.780

.820

E

.240

.285

.260

.310

.240

.285

.260

.310

.230

.265

.240

.310

.260

.310

El

.300

.320

.290

.320

.290

.320

.290

.320

.290

.310

.290

.320

.290

.320

e

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

L

.125

.150

.125

.160

.125

.150

.125

.160

.100

.150

.125

.150

.125

.160

.060

.020

.060

.015

.060

.020

.060

.020

.080

.015

.060

.020

.060

Q

.015

Sl

.004

ex

3°

Common
Name

.010

13°

Standard
Lead
Finish

AMO Pkg.

.005

.005

3°

.020

13°

.005

3°

13°

.005

3°

13°

b

bore

b

bore

e

b

bore

0-18-1

0-18-2

0-20-1

0-20-2

0-22-1

0-22-2

0-24-1

CEROIP

SIOEBRAZED

CEROIP

SIOEBRAZED

CEROIP

SIOEBRAZED

CERDIP

38510
Appendix C

-

-

-

-

-

-

0-3(1)

Parameters

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

A

.130

.200

.100

.200

.140

.220

.100

.200

.140

.220

.100

.200

.150

b

.016

.020

.015

.022

.016

.020

.015

.022

.016

.020

.015

.022

.016

.020

.070

.040

.065

.050

.070

.040

.065

.045

.065

.030

.060

.045

.065

Min.

Max.

Min.

Max.

Min.

Max.

.225

bl

.050

c

.009

.011

.008

.013

.009

.011

.008

.013

.009

.011

.008

.013

.009

.011

0

.870

.920

.850

.930

.935

.970

.950

1.010

1.045

1.110

1.050

1.110

1.230

1.285

E

.280

.310

.260

.310

.245

.285

.260

.310

.360

.405

.360

.410

.510

.545

El

.290

.320

.290

.320

.290

.320

.290

.320

.390

.420

.390

.420

.600

.620

e

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

L

.125

.150

.125

.160

.125

.150

.125

.160

.125

.150

.125

.160

.120

.150

Q

.015

.060

.020

.060

.015

.060

.020

.060

.015

.060

.020

.060

.015

.060

Sl

.005

ex

Standard
Lead
Finish

.005

3°

13°
b

.005

.005
3°

bore

b

b or e

7-21

.005

.005
3°

13°

13°
b

.010
3°

bore

13°
b

Package Outlines
PACKAGE OUTLINES (Cont.)
HERMETIC DUAL IN-LINE PACKAGES (Cont.)

AMO Pkg.

0-24-2

Common
Name

SIDEBRAZED

38510
Appendix C

0-24-4/0-24-4 •
CERVIEW

Min.

A

0-28-2

CERDIP

SIDEBRAZED

-

0-3(3)

Parameters

0-28-1

-

Max.

Min.

Max.

.100

.200

.150

.225

.150

b

.015

.022

.016

.020

b1

.030

.060

.045

c

.008

.013

D

1.170

E

.550

E1

.225

.100

.200

.016

.020

.015

.065

.045

.065

.009

.011

.009

1.200

1.235

1.280

.610

.510

.550

.590

.620

.600

e

.090

.110

L

.120

.160

Q

.020

.060

S1

.005

a

CERDIP

SIDEBRAZED

Max.

Min.

Max.

.150

.225

.100

.200

.100

.200

.022

.016

.020

.015

.022

.015

.022

.030

.060

.045

.065

.030

.060

.030

.060

.011

.008

.013

.009

.011

.008

.013

.008

.013

1.440

1.500

1.380

1.420

2.020

2.100

1.960

2.040

2.370

2.430

.510

.550

.560

.600

.510

.550

.550

.610

.570

.610

.630

.600

.630

.590

.620

.600

.630

.590

.620

.590

.620

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.090

.110

.120

.150

.120

.150

.120

.160

.120

.150

.120

.160

.125

.160

.015

.060

.015

.060

.020

.060

.015

.060

.020

.060

.020

.060

.005
13°

.005

3°

3°
b

Notes: 1. Load finish b is tin plate. Finish c is gold plate.
2. Used only for LM108/LM108A.
3. Dimensions E and D allow for off-center lid, meniscus and glass overrun.

7-22

.005

.005

13°
b

Min.

-

Max.

3°
borc

0-48-2

SIDEBRAZED

0-5
Max.

Standard
Lead
Finish

0-40-2

Min.

.010

Min.

0-40-1

Min.

Max.

.005

13°
b

bor c

borc

Package Outlines
PACKAGE OUTLINES (Cant.)
FLAT PACKAGES

F·10·1

F·10·2

F·14·1 and F·14·2

F·16·1 and F·16·2

r-L-j

s

t

I·

t

.1It-'

L

-.-

1-

14t

I

: f
01

D

7

8)

II

I

b

+=I

I

1

I

I--E--I

e

- - L 1- - - - - - i

1--.

Q

L

L
F·20·1

Note: Notch is pin 1 index on cerpack.
F·22·1

F·24·1

b

.L

T
s

L

F·24·3

F·24·2

~
I
b

rli
1. 241
1

L

I

L
r

D

12 13l

I

T
~

T

IIII

e

7·23

F·28·1

Package Outlines
PACKAGE OUTLINES (Cont.)
FLAT PACKAGES (Cont.)
F-42-1

F-28-2

F-48-2

~

!

t'l

A

A

t

a

I

,

t \
AMO Pkg.
Common
NAME
38510
Appendix C
Parameters
A
b
C

0
01
E
E1
e
L
L1
Q

51
Standard
Lead
Finish

F-10-1

F-10-2
METAL
FLAT PAK

CERPACK
F-4

F-14-1

F-14-2
METAL
FLAT PAK

CERPACK

F-4

.F-1

t

I I

I

f t

F-16-1

F-16-2
METAL
FLAT PAK

CERPACK

F-1

F-20-1

-

F-5

-

-

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

lA .... "

~w~;n.

~y'ax.

rY~in.

rv1ax.

.045
.015
.004
.230

.080
.019
.006
.255

.045
.012
.003
.235

.045
.015
.004
.230

.080
.019
.006
.255

.045
.012
.003
.230

.085
.019
.006
.425

.045
.015
.003
.370

.085
.019
.006
.520

.240

.240

.260
.275
.055
.370
.980
.040

.240

.245

.285
.290
.055
.370
.980
.040

.245

.085
.019
.006
.400
.410
.285
.305
.055
.370
.980
.040

.045
.015
.004
.490

.260
.275
.055
.370
.980
.040

.085
.019
.006
.270
.280
.260
.280
.055
.370
.980
.040

.045
.015
.004
.370

.240

.080
.019
.006
.275
.275
.260
.280
.055
.370
.980
.040

.245

.285
.290
.055
.370
.980
.040

Parameters
A
b
0
01
E
E1

e
L
L1
Q

51
Standard
Lead
Finish

.045
.300
.920
.010
.005

c

b

AMO Pkg.
Common
Name
38510
Appendix C

C

.045
.300
.920
.010
.005

F-24-1
CERPACK

.045
.300
.920
.010
.005

.045
.300
.920
.020
.005

b

c

b

F-24-2
METAL
FLAT PAK

F-24-3
METAL
FLAT PAK

F-28-1
METAL
FLAT PAK

F·8

-

F·6
Min.

Max.

Min.

Max.

Min.

Max.

.050
.015
.004
.580

.090
.019
.006
.620

.045
.015
.003
.360

.045
.015
.003
.380

.385
.410
.055
.320
.980
.040

.245

.090
.019
.006
.420
.440
.420
.440
.055
.320
.980
.040

.045
.015
.003
.360

.360

.090
.019
.006
.410
.420
.285
.305
.055
.370
.980
.040

.080
.019
.006
.410
.410
.410
.410
.055
.320
1.000
.040

.045
.265
.920
.020
.005
b

.045
.300
.920
.010
.005

c

.045
.250
.920
.010
0

.360
.045
.270
.955
.010
0

c

c

.300
.920
.020
.005

F-28-2
CERAMIC
FLAT PAK

Min.

.065
.016
.007
.700
.625
.045
.415
1.475
.017
.005

c

F-42-1
CERAMIC
FLAT PAK

.045
.250
.920
.010

.440
.055
.320
.980
.040

c

F·48·2
CERAMIC
FLAT PAK

-

-

Max.

Min.

Max.

Min.

Max.

.085
.025
.010
.720
.720
.650
.650
.055
.435
1.500
.025

.070
.017
.006
1.030

.115
.023
.012
1.090
1.090
.660
.660
.055
.370
1.370
.060

.070
.018
.006
1.175

.110
.022
.010
1.250
1.250
.670
.670
.055
.370
1.365
.055

.620
.045
.320
1.300
.020
.005

c

Notes: 1. Lead finish b is tin plate. Finish c is gold plate.
2. Dimensions E1 and 01 allow for off-center lid, meniscus, and glass overrun.

7-24

.380

!viax.
.090
.019
.006
.420
.440
.420

rv'in.
.045
.015
.003
.380

b

-

Max.

.045

c

-

Min.

.380

.045
.300
.920
.010
.005

F-22-1
METAL
FLAT PAK

CERPACK

Min.

.045
.300
.920
.010
.005

r

.615
.045
.320
1.310
.020
.015

c

Package Outlines

SQUARE CHIP CARRIER FAMILY (L-XX-1)

BOTTOM

R

~---------D--------~
N
PLACES

A

TOP

~

SIDE

Inches

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

A

.064

.100

.064

.100

.064

.120

.082

.120

A1

.054

.088

.054

.088

.054

.088

.072

.088

81

.022

.028

.022

.028

.022

.028

.022

.028

D

.342

.358

.442

.458

.640

.660

.739

.761

D2

.190

.210

.290

.310

.490

.510

.590

.610

E

.342

.358

.442

.458

.640

.660

.739

.761

E2

.190

.210

.290

.310

.490

.510

.590

.610

e

.045

.055

.045

.055

.045

.055

.045

.055

L

.045

.055

.045

.055

.045

.055

.045

.055

L2

.077

.093

.077

.093

.077

.093

.077

.093

N

R
Outline

20 (5 x 5)
.007

.011

L-20-1

28 (7 x 7)
.007

.011

44 (11 x 11)
.007

L-28-1

.011

L-44-1

7-25

52 (13 x 13)
.007

Max

Min

Q

/#-

~--

{5J.;.-

/!-

f#

e

68

.011

L-52-1

L-68-1

Package Outlines

RECTANGULAR CHIP CARRIER FAMILY (L-XX-2)

BOTTOM

R

N
PLACES

~---------D----------~
A

~
Symbol

SIDE

E

TOP

Inches
Min

Max

Min

Max

Min

Max

A

.060

.120

.060

.120

.060

.120

A1

.050

.088

.050

.088

.050

.088

81

.022

.028

.022

.028

.022

.028

D

.280

.305

.342

.358

.442

.458

D2

.140

.160

.190

.210

.290

.310

E

.345

.365

.540

.560

.540

.560

E2

.190

.210

.390

.410

.390

.410

e

.045

.055

.045

.055

.045

.055

L

.045

.055

.045

.055

.045

.055

L2

.077

.093

.077

.093

.077

.093

N
R

Outline

18 (4 x 5)
.007

.011

28 (5 x 9)
.007

.011

L-28-2

L-18-2
7-26

32 (7 x 9)
.007

.011

L-32-2

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Tel: (408) 727-1300

Advanced Micro Devices
8323 Southwest Freeway
Suite 850
Houston, Texas 77074
Tel: (713) 771-3113

Advanced Micro Devices
7000 Broadway, Suite 401
Denver, Colorado 80221
Tel: (303) 426-7100

Advanced Micro Devices
6750 LBJ Freeway, Suite 1160
Dallas, Texas 75240
Tel: (214) 934-9099

Advanced Micro Devices
290 Elwood Davis Road
Suite316
Liverpool, New York 13088
Tel: (315)457-5400
Advanced Micro Devices
2 Kilmer Road
Edison, New Jersey 08817
Tel: (201) 985-6800
Advanced Micro Devices
107 Lakeside Drive
Horsham, Pennsylvania 19044
Tel: (215)441-8210
Advanced Micro Devices
205 South Avenue
Poughkeepsie, New York 12601
Tel: (914) 471-8180

NORTHEAST AREA

Advanced Micro Devices
7850 Ulmerton Road
Suite 1A
Largo, Florida 33541
Advanced Micro Devices
4740 N. State Road #7
Suite 102
Ft. Lauderdale, Florida 33319
Tel: (305) 484-8600
Advanced Micro Devices
6755 Peachtree Industrial Boulevard N.E.
Suite 104
Atlanta, Georgia 30360
Tel: (404) 449-7920
Advanced Micro Devices
8 Woodlawn Green, Suite 220
Woodlawn Road
Charlotte, North Carolina 28210
Tel: (704) 525-1875

Advanced Micro Devices
6 New England Executive Park
Burlington, Massachusetts 01803
Tel: (617) 273-3970
Advanced Micro Devices (Canada) Ltd.
2 Sheppard Avenue East
Suite 1610
Willowdale, Ontario
Canada M2N5Y7
Tel: (416) 224-5193

ADVANCED MICRO DEVICES INTERNATIONAL OFFICES
BELGIUM
Advanced Micro Devices
Overseas Corporation
Avenue de Tervueren, 412, bte 9
B-1150 Bruxelles
Tel: (02) 771 9993
TELEX: 61028
FRANCE
Advanced Micro Devices, S.A.
Silic 314, Immeuble Helsinki
74, rue d'Arcueil
F-94588 Rungis Cedex
Tel: (01) 687.36.66
TELEX: 202053

GERMANY
Advanced Micro Devices GmbH
Rosenheimer Str. 139
0-8000 Muenchen 80
Tel: (089) 401976
TELEX: 523883
Advanced Micro Devices GmbH
Harthaeuser Hauptstrasse 4
0-7024 Filderstadt 3
Tel: (07158) 30 60
TELEX: 721211
HONG KONG
Advanced Micro Devices
1303 World Commerce Centre
Harbor City
11 Canton Road
Tsimshatsui, Kowloon
Tel: (852) 3 695377

ITALY
Advanced Micro Devices S.R.L.
Centro Direzionale
Palazzo Vasari, 3° Piano
1-20090 MI2 - Segrate (MI)
Tel: (02) 2154913-4-5
TELEX: 315286

SWEDEN
Advanced Micro Devices AB
Box 7013
S-172 07 Sundbyberg
Tel: (08) 98 1235
TELEX: 11602

JAPAN
Advanced Micro Devices, K.K.
Dai 3 Hoya Building
8-17, Kamitakaido 1-chomo
Suginami-ku, Tokyo 168
Tel: (03) 329-2751
TELEX: 2324064

UNITED KINGDOM
Advanced Micro Devices (U.K.) Ltd.
A.M.D. House,
Goldsworth Road,
Woking,
Surrey GU21 1JT
Tel: Woking (04862) 22121
TELEX: 859103

Advanced Micro Devices maintains a network of representatives and distributors in the U.S. and
around the world. For a sales agent nearest you, call one of the AMD offices above.

7-27

U.S. AND CANADIAN SALES REPRESENTATIVES
CALIFORNIA (Northern)
12 Incorporated .
3350 Scott Boulevard
Suite 1001, Bldg. 10
Santa Clara, California 95050
Tel: (408) 988-3400
TWX: 910-338-0192
CANADA (Eastern)
Vitel Electronics
3300 Cote Vertu, Suite 203
St. Laurent, Quebec,
Canada H4R 2B7
Tel: (514) 331-7393
TWX: 610-421-3124
TELEX: 05-821762
Vitel Electronics
5945 Airport Road, Suite 180
Mississauga, Ontario
Canada L4V 1R9
Tel: (416) 676-9720
TWX: 610-492-2528
Vitel Electronics
55 Bayhill Ridge
Stitsville, Ontario
Canada KOA 3GO
Tel: (613) 836-1776
CANADA (Western)
Vitel Electronics
185 Baltic Street
Coquitlam, British Columbia
Canada V3K 5G9
Tel: (604) 524-6677
CONNECTICUT
Scientific Components
1185 South Main Street
Cheshire, Connecticut 06410
Tel: (203) 272-2963
TWX: 710-455-2078

IDAHO
Intermountain Technology
2475 Autumn Way
Meridian, Idaho 83642
Tel: (208) 888-5708

MISSOURI
Kebco Inc.
Route 2, Box 98
70A Lake Tapawingo
Blue Springs, Missouri 64015
Tel: (816) 229-3370

ILLINOIS
Oasis Sales, Inc.
1101 Tonne Road
Elk Grove Village, Illinois 60007
Tel: (312) 640-1850
TWX: 910-222-1775

Kebco Inc.
75 Worthington, Suite 101
Maryland Heights, Missouri 63043
Tel: (314)576-4111

INDIANA
SAL Marketing Corp.
5610 Crawfordsville Road, Suite 2304
Indianapolis, Indiana 46224
Tel: (317)241-9276
TWX: 810-341-3309
IOWA
Lorenz Sales, Inc.
5270 N. Park Place, N.E.
Cedar Rapids, Iowa 52402
Tel: (319)377-4666
KANSAS
Kebco Inc., c/o Doug Phillips
524 Deveron Drive
Wichita, Kansas 67230
Tel: (316)733-2117
(316) 733-1301
MICHIGAN
SAL Marketing Corp.
P.O. Box 929
9880 E. Grand River Road
Brighton, Michigan 48116
Tel: (313) 227-1786
TWX: 810-242-1518

NEW JERSEY
T.A.1. Corp.
12 S. Black Horse Pike
Bellmawr, New Jersey 08031
Tel: (609) 933-2600
TWX: 710-639-1810
NEW MEXICO
Thorson Desert States
9301 Indian School, Suite 112
Albuquerque, New Mexico 87112
Tel: (505) 293-8555
TWX: 910-989-1174
NEW YORK
Nycom, Inc.
10 Adler Drive
East Syracuse, New York 13057
Tel: (315) 437-8343
TWX: 710-541-1506
OHIO
Dolfuss-Root & Co.
13477 Prospect Road
Strongsville, Ohio 44136
Tel: (216) 238-0300
TWX: 810-427-9148
Dolfuss-Root & Co.
683 Miamisburg-Centerville Road
Suite 202
Centerville, Ohio 45459
Tel: (513) 433-6776

7-28

OKLAHOMA
Bonser-Philhower Sales
6644 S. Victor
Tulsa, Oklahoma 74136
Tel: (918) 496-3236
PENNSYLVANIA
Dolfuss-Root & Co.
United Industrial Park
Suite 203A, Building A
98 Vanadium Road
Pittsburgh, Pennsylvania 15017
Tel: (412) 221-4420
TWX: 510-697-3233
TEXAS
Bonser-Philhower Sales
~~Tt~72~2 Central Expressway
Dallas, Texas 75243
Tel: (214) 234-8438
TWX: 910-867-4752
Bonser-Philhower Sales
11700 Southwest Fwy., Suite 110
Houston, Texas 77031
Tel: (713)495-3115
TWX: 910-880-4053
Bonser-Philhower Sales
8330 Burnett Road, Suite 119
Austin, Texas 78758
Tel: (512) 458-3569
UTAH
R2
940 North 400 East, Suite B
North Salt Lake, Utah 85054
Tel: (801) 298-2631
TWX: 910-925-5607
WISCONSIN
Oasis Sales, Inc.
1305 N. Barker Road
Brookfield, Wisconsin 53005
Tel: (414) 782-6660

\

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