1982_Burr Brown_Catalog 1982 Burr Brown Catalog

5 ,..,- /' 360 <; 0,1 ~ 0,01 i5 ~V ~ -;"606B INITIAL..., ~FTEi o 0,001 1 16 64 Gain (VN) 4 256 1024 1 OUTPUT STAGE GAIN ERROR 4 USER, TRI~ 16 64 GainlVNI 10 100 32 Source Resistance Imbalance (kfl) E ;§ 3,2 10k 10 3; 6O~---~--~-----+-----f Frequency (Hz) OUTPUT OFFSET VOLTAGE DRIFT VS GAIN u COMMON-MODE R,EJECTIONVS SOURCE RESISTNACE IMBALANCE 120 D G • 'l.Vo 1024 D 1 COMMON-MODE REJECTION VS FREQUENCY 32 to 1024 1/ ~ J:!'" 30 o > 10 ~ 20 o '5 S- WARM-UP RESPONSE 40 Q) c5 ~ 256 50 ~ \-G=1024VN POWER \ TURN-DN "- 10 G=1V-;:'" ~ j'..... 5 10 Timelmin) 1024 - 15 20 OUTPUT STAGE GAIN NONLINEARITY O,02.--...;V~S..;O;.;U;,;T;.;.P..;U~T..;C;,;U;.;R..;R..;E~N..;T,--., 0,01 .-_...:.VfS.;;;O;;;U:.;T.:,P.;;;U:;.T.;C;;.:U;;;R.:;R.;:E,.N:.;T_ _., SETTLING TIME VS GAIN o,o15t----t--+--+-----I Z;- ~ O,01t----t---t---ioI"" c: 'OJ ·m ~ 0,005t----l-----l------::;"''--::-i o Z CJ O,005t;~::!:::::=!;;..-'~-1 c: 'OJ CJ °0~----~2~,5----~--~7~,5~--~10 °0~-~2~,5~---5~--~7~,5~--~10 'INCLUDES GAIN SWITCHING TIME, 0~1--4~--16~-~64--2~56~-1~024 Output Current I mAl Output Current (rnA) GainlVNI WIDEBAND OUTPUT NOISE BANDWIDTH 30 r-;;';;';";;'"T"';"';';;;';;';~--'"""lI G = 1024 10r--~OFU..;T~P~U~T~N;.;O..;IS~E~VS~G~A~IN~__, o 8.----+----~--~~--~--~ ~ 6t---+--+--1--+-I--.t ill z 4 t--+---t-- E ~ ~20t--------1-----~~~---i ill z ~10.--------+~~---i--------i '0 '0 '5 S:J STEP RESPONSE RL = 2kll CL= 1oo0pF '5 o o Rs= 100kll ol!!!~~~~~ 1 4 16 64 256 1024 Gain IVNI 1k 100 Bandwidth I Hz I 2-38 10k 20 60 100 Time lMsee. 140 CM R R (in VI V)]. Common-mode voltage shown as ECM is actually the average of the two voltages appearing at the two inputs (pins 29 and 2) with respect to pin 15 (V 1 and V2). INSTALLATION AND OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS Figure 2 shows the proper analog and digital power supply connections. The analog supplies should be decoupled with I~F tantalum and 1000pF ceramic capacitors as close to the amplifier as possible. Because the amplifier is direct-coupled it must have a ground return path for the bias currents associated with the amplifier inputs at pins 2 and 29. If the ground return path is not inherent in the signal source (floating source) it must be provided externally. The ground return resistance (ROR) should be kept as low as practical. An upper limit of approximately 50M!l is established by the input bias currents of the amplifier and its commonmode voltage. GAIN SETTING Gain is determined by a 4-bit digital word applied to the input Do through 0 3 (see Figure I). Pin 19 provides a latch function for the inputs. When pin 19 is a logic 0, changes on the Do through Odnputsare inhibited. Pin 19 should be at +5V if the latch is not used. A gain state truth table is shown in Table J. Gains are determined by the resistor networks shown in Figure I. For the state 03, O2 = 0, 0, the input stage gain is a function ofthe gain setting resistor RG connected between pins 26 and 27. If gains of 1,2 and 4 are desired, no connection should be made to pins 26 and 27 and the resistance across these pins should be kept high with respect to 40k!l (> 400M!l). Gain accuracy is established by laser-trimming the thimfilm resistor networks during assembly. No external, user trimming is required. , OUTPUT OFFSET Output offset may be varied by either of two methods shown in Figure 4. Sources at pin 9 and pin 14 apply voltages to the noninverting inputs of A. and A3 respectively (see Figure I). Since the output stage gain occurs after these points, the output voltage bias established with VR1 and VR2 will vary with the output gain, G2. Sources connected at pins 9 and 14 must have resistances low with respect to 10k!l in order not to disturb gain accuracy and common-mode rejection. ANALOG COMMON - FIGURE 2. Power Supply and Ground Connections. SIGNAL CONNECTIONS Basic signal connections are shown in Figure 3. The connection to pin 14 completes the difference amplifier of A3 (see Figure I). The 3 to 8 jumper connects the output stage. The pin 9 connection provides a divide-by-two attenuator for the A. stage. This is necessary to limit the signal on the output stage switches to maintain signal linearity. The pin II, 12 and 13 connections to pin 10 close the feedback loop around A.. VOUT =GI G2 IEr' Ell + G2 (VH2 + VRII r "",29 VOUT FIGURE 4. Output Offsetting. LOW-PASS FILTER For low frequency signals, system performance may be improved by reducing noise bandwidth in the amplifier. This may be accomplished with the addition of one or two external capacitors as shown in Figure 5. C2 is connected to a lOki 10k attenuatorand C1is connected as a feedback element across A4 (see Figures I and 5). The transfer function is: LOAD FIGURE 3. Basic Signal Connections. In the equation shown in Figure 3, GI is the input stage gain and G2 is the output stage. gain. CMRR is the common-mode rejection ratio [CMR (in dB) = 20 log Vo v;-, 2-39 [ = J[ 10 x 10·' 100x 10' SIC, +330 x 10''')+ 20 x 10' 10 x 10' 1+ 10 x 10' R, SC, + R, J TABLE I. Gain Sta.te Truth Table. ~~tal D, 0' 0 0 0 0 0 0 0 I I I I I I I I D, 0 0 0 0 I I I I 0 0 0 0 I I I I' ('8:) In p D, 0 0 I I 0 0 I I 0 0 I I 0 0 I I D" 0 I 0 I 0 I 0 I 0 I 0 f 0 I 0 I G, G, (A, and A,) (Pins 2 & 29 to 3) (A,) (Pin g to Pin 10) I 2 4 4 I 2 4 4 I 2 4 4 I 2 4 4 1+ 4Ok(R,; 4 32 256 G,'G, (R,;* = 00) I 2 4 4 4 8 16 16 32 64 128 128 256 512 1024 1024 G,'G, (R,;* '" 00) 1(1 + 4Ok(R,;) 2(1 + 4Ok(R,;) 4(1 + 4Ok( R,;) 4(1 +40k(R,;) 4 8 16 16 32 64 128 128 256 512 1024 1024 *RG connected between pins 26 and 27. The first term is a first order filter. The second term is more complex. R, varies with the output stage gain -1.4k for G2 4 (see Figure I). The "I + ... " nature of the transfer function prevents a true first order filter roll off. For most applications, the first order low-pass filter obtained by C2 provides sufficient filtering. The value C2 required for a desired cutoff frequency(f2 in Hz) is obtained by the equation shown in Figure 5. = '2- 1 - 2n x 5kn le2 + 33OpF) Brown's 3329 will provide ±IOOmA output while BurrBrown's 3553 will supply ±200mA. When either booster is placed inside the feedback loop as shown, the booster's offset voltage produces no significant errors since it is divided by the open-loop gain of the output stage. GUA,RD DRIVE CONNECTIONS Use ofthe guard drive connection shown in Figure 7 can improve system common~mode rejection when the distributed capacitance of the input lines is significant. The ... FIGURE 5. Low-Pass Filter Connections. LARGER OUTPUT CURRENT The output current rating of the 3606 is a minimum of ±5mA. The linearity of the gain is affected by output current. See Typical Performance Curves. Optimu'm linearity is achieved with 10 .;;; I rnA, 10 .;;; 5mA is acceptable. Above 5mA it may be desira,ble to use a power or current booster as shown in Figure 6. Burr- - ±IOOmA TO ±ZOOmA FIGURE 6. Output Current Booster. FIGURE 7. Guard Drive Connections. common-mode voltage which appears on the input lines and on pins 29 and 2 is computed by the 3606 [(VI + V2)/2] and appears at pin 28. It is then fed back to the shield so that the voltage across the distributed capacitances is minimized. This reduces the common-mode current and improves common-mode rejection. The operational amplifier in the voltage follower configuration is used to supply more current than can be obtained from the 20k resistors connected internally to pin 28 (see Figure I). OFFSET TRIM Offset voltages of the 3606 are reduced by laser-trimming during assembly. This reduces the initial offset voltage and the offset voltage change with gain change to levels that are acceptable for most applications. For more critical applications the offset voltages can be externally 2-40 nulled t6 zero. The following steps should be followed (see Figure 8). APPLICATIONS A typical application of 3606 in a microcomputer based data acquisition system is shown in the block diagram below. The purpose of this system is to be able to acquire data from a specific analog input channel. suitably condition it (amplify it and convert it to digital form) and store it or transmit it for f\lrther processing. Initially the Microcomputer loads the RAM (random access memory) with the required coding for various desired gains :via Data Bus. The coding associates the gain state truth table for 3606 with corresponding address locations in the computer memory. So when the computer puts out an instruction to multiplex a specific analog input channel through the multiplexer via the Address Bus. the RA M also receives the same address information and puts out corresponding gain code to the PG IA 3606. The 3606 amplifies the multiplexed signal by the programmed gain value. and outputs it to S/ H (sample and hold). The S/ H holds the output value when it receives the control signal from the computer and the AI D converts it and outputs it to the computer via the Data Bus under computer control. The PGIA 3606 allows the system user to modify and' reprogram gain values for different analog input channels merely by changing the software computer program. Since different dedicated instruments are not required for various input channels. the PGIA also saves space and overall system costs. FIGURE 8. Optional Offset Trim. I. Adjust both R, and R, to mid-range. 2. Set the gain to minimum (I V/ V). 3. Adjust R, to make Vour equal zero. 4. Set the gain to maximum ( 1024 V/ V), 5. Adjust R, to make VO"T equal zero. By using this technique. the change in output offset voltage caused by a gain change of IV/V to 1024V/V may be reduced to. typically ImV instead of IOmV with no external trimming. Trimming may cause the offset voltage drift vs temperature to increase slightly. A MICROCOMPUTER DATA BUS , t-- I ADDRESS BUS CONTROL BUS I ANALOG INPUT CHANNELS r--- . . J. f---- ~ QJ --,I ADDRESS DECODER AND CONTROL LOGIC RAM - - I LATCH ANALOG MULTIPLEXER MPC4D MPCBS ............. PGIA .......... V FIGURE 9. Use of 3606 in Data Acquisition System. 2-41 ~ SHC298 AID CONVERTER ADCBO 3626 BURR-BROWN@ IElElI Low Drift INSTRUMENTATION AMPLIFIER FEATURES • LOW VOLTAGE DRIFT @ LOW GAIN 2pV/"C @ G= 5 (3626CP) • LOW NOISE - 2pV Pop • HIGH CMR - > SOdB @ = 1000 • LOW COST • SMALL SIZE - DIP Package DESCRIPTION The 3626 is an integrated circuit instrumentation amplifier designed for amplifying low-level signals in the presence of high common-mode voltages. Its low drift, high input impedance (5 x 1090), easy gain adjustment (5V IV to lOOOV IV) and high commonmode rejection eliminate the problems and compromises associated with using operational amplifiers to realize the same gain function. Compared to other integrated circuit instrumentation amplifiers it has the unique feature of having low voltage drift versus temperature at low gains. The 3626 offers many benefits to the user for his instrumentation applications: Low voltage drift reduces temperature errors High common-mode rejection preserves system accuracy High input impedance prevents errors due to source loading and source impedance imbalance Small, dual-in-line package conserves board space Laser-trimmed offset requires no nulling Inlernallooal Airport Indllllrill Park· P.O. Box 11400 • Tueaon. Arizona 85734 • Tal. (602) 746·1111 • Twx: 9111-952·1111 • Cable: BBRCORP . Telex: &6-6491 PDS·3SOA / 2-42 DISCUSSION An instrumentation amplifier is basically a closed-loop gain block that exhibits high input impedance and high commonmode rejection. Instrumentation amplifiers are committed devices with differential inputs and accurately predicatable input-to-output relationships - all necessary feedback networks are contained in the circuit package. These characteristics distinguish instrumentation amps from operational amplifiers - open-loop devices whose closed-loop performance depends upon the external networks supplied by the user. In instrumentation amps parameters such as input and output impedances, frequency response, offset voltage drift and common-mode rejection are specified for the closed-loop, committed configuration. One of the few parameters that the user can vary is gain (by choosing the external gain-setting resistor value). Another important difference between an op amp and instrumentation amp is that the instrumentation amp has no summing junction available; you cannot make a summing amplifier or integrator out of an instrumentation amp. In the past few years, choices in instrumentation amplifier designs have ilrown from a number of discrete modular units to include monolithic and hybrid integrated circuit versions which offer high performance at lower cost - and in smaller packages. Monolithic IC's were the first to break the price and performance barrier. Hybrid IC's, such as the 3626, are more expensive than monolithic IC's but they give better performance for the money. Instrumentation amps normally require at least one external resistor - the gain-setting resistor Rc;. Monolithic units usually require two additional- the output feedback resistor and a resistor between feedback common and ground. Since temperature coefficient differences between these two resistors will cause output offset voltage drift, they must be matched to meet the desired drift specification. Hybrid units, such as the 3626, have the advantage that all resistors except the gain-setting Rc; can be included in the package. A simplified circuit diagram of the 3626 is shown in Figure 1. The circuit uses Burr-Brown's high performance bipolar integrated circuit amplifiers and a laser trimmed thin-film resistor network. The excellent initial matching and temperature tracking of these components provide a level of performance difficult to obtain with even expensive discrete amplifiers and resistors. The gain accuracy, linearity and temperature coefficient are particularly attractive. One of the most outstanding features of the 3626 is its low voltage drift, especially at low and medium gains. Figure 2 shows the drift performance of the 3626 series comapred to monolithic integrated circuit instrumentation amplifiers. The guaranteed voltage drift performance is almost two orders of magnitude better at low gains. GAINCVNI FIGURE 2. Input Offset Drift vs Gain. The design of the 3626 is such that output biasing is easily accomplished. See Figure 3 fo! proper connections. The impedance of the reference source should be low compared to 5Ht A current booster such as the 3329 (i 00 rnA) or 3553 (200 rnA) can conveniently be used with the 3626 to increase its output current driving capability. GAIN GAIN 12'1---, REF SENSE 1--¥;rv-+-"""".--..,....W"-+-'W\r---{ 8 Sk 1.2Sk 1.2Sk Sk +IN 14}-_ _ _ _ _ _ _ _ _......l FIGURE 1. Simplified Circuit Diagram. FIGURE 3. Output Offsetting and Power Boosting. SPECIFICATIONS ELECTRICAL MODELS GAIN MECHANICAL Specificatio~1Il~ typical at 25°C and ±IS VDC Power Supply,Unless,Otherwi~e 3626AP Noted. 3626BP 3626CP 203mm Gain Equation G= 5+ (o.~o") !.Q.Jill dotover~' :.t.J. RG Error from Equation (1) Range of Gain; min Gain Temp. Coefficient: G=5 G ~ 10 G = 100 G = 1000 Nonlinearity, max (']f) (2) 12.7mtn 1'(0.50") pin 1 (±0.25 - 0.003G)% 5 to 1000 . (0.18")(7 ~ pin 1 50ppm~C ~4mm 00 000 '.' 4.6mmV 2ppm/oC 25ppm/oC 35ppm/oC --pinI4 (0.25" JLo.51mm (0.020") «0.02 +0.0003G)I±(0.01 + 0.0003G)I+(0.01 +0.003G) OUTPUT Rated Output, min Output Impedance, G == 100 ±IOV @ ±SmA Row Spacing; 7.6mm (0.300") Weight: 3.4 gr.~ (0.12 oz.) 2n INPUT Connector: 0145MC (14-pin DIP) lop.ut I.mpedance. Dirr. &, eM Input Voltage Range, min ,5 x 10 9 n u 3 pF Differential Common-mode CMR. DC to 60H" G = S, min G = 10 to 1000, min Pin"material ±6V 68dB 74dB and ·pletiMo ~O"mpo.ition conform to Method 2003 (solderability) ·of MI L-5TD-883 (except paragraph 3.2). ±IOV with 1kn source unhalance 74dB 74dB 80dB 80dB INPUT OFFSET VOL TAGE Initial Off~et. max(t) ±(0.4 + 0c,4 )mV ±(0.2 + 0c,2 )mV ±(0.2 + 0c,2 )mV vs. Temperature, max ±(6+ 1~)IlV/oC ±(3 +i)IlV/oc ±(I +.2~IlV/oC G vs. Supply 4OIlV/V 3IlV /mo. vs. Time INPUT BIAS CURRENTS ±SOnA ,(either input) ±0.7nA/oC ±O.lnA/V Initial Bias Current, max vs. Temperature. max vs. Supply INPUT NOISE Voltage. p.p, 0.0IHz_I0Hz RMS, 10Hz - 10kHz Current, P-P. O.OIHz - 10Hz RMS, 10Hz - 10kHz 2llV p,p 21lV RMS 150 pA p.p 50 pA RMS Pin Connections 1. Gain 2. ~ No Int~rnal 3. Connection 4. Vos 5. Vos 6. -Vee 7. Ret 8. Sense 9. Out 10. 11. 12. 13.: 14. +Vcc No Internal Connection Gain -In +In DYNAMIC RESPONSE Small Signal, ±3dB Flatness: G=5 G= 10 G = 100 G = 1000 400kHz 160kHz 14kHz 1.4kHz Small Signal. ± I % Flatness; G=5 G= 10 G = 100 G = 1000 Full Power, G = 5 - 100 Slew Rate, G = 5 - 100 Settling Time (0.1 %): G=5 G = 10 G = 100 G= 000 Connection Diagram 76kHz 27kHz 2.1 kHz 250 Hz 19 kHz 1.2 Vllls , 0.02 ms 0.03 ms 0.1 ms 12 m. POWER SUPPL Y Rated Voltage Voltage Range Quiescent Supply Current ±15 VDe ±s to ±20 VDC ±6 rnA, max TEMPERATURE RANGE Specifications, min Operation Storage _25°C to +8SoC _55°C to +125 o C -65°C to + 150°C *OPTIONAL OFFSET TRIM (1 J May be trimmed to zero. (2) Nonlinearity is the maximum peak deviation from the best straightline as a percent of full scale peak-ta-peak output. FIGURE 4 2-44 TYPICAL PERFORMANCE CURVES (TYPICAL@250Cand :!:.15 VOC POWER SUPPLIES UNLESS OTHERWISE NOTED) CMR VS.SOURCE IMPEDANCE UNBALANCE 100 Z w t!l Z 80 iii 12 a: f:::l B ~ 4 .. G-5 ' - G = 10 1 ~ <0: c:: 60 ::. I u 40 fCM RMS INPUT NOISE VOLTAGE VS SOURCE RESISTANCE PEAK·TO-PEAK INPUT NOISE VDLTAG'E VS.SOURCE RESISTANCE .> £\: a: 50 3 w en 20 f-fS ~ 10 Jz to ~O kJZI- 10 / 2 a 20 > ?:Z fB ~ O.OiHZ t~ 10Hl f UJ > f:::l ./ STEP RESPONSE V. ~ 10 5 r-rpot Locus of +1% 1.0 0.1 100 5 I / f- ci 5 > ~ .. f- -5 g -10 I lk 10k lOOk 1M FREQUENCY (Hz) 0 10M ~ o 10 5 f:::l FREQUENCY RESPONSE 100 10 .. / 2 10 15 f- 0 5 w ~ 20 <0: ..J 10 ;; SATURATED OUTPUT VOLTAGE VS. OUTPUT CURRENT t!l 1 10 100 lk 10k 100k 1M SOURCE RESISTANCE(!1) ',,~ 10 lOOk COMMON-MODE INPUT FREQUENCY IH<' :; 10 100 lk 10k lOOk 1M SOURCE RESISTANCE 1m 1000 t!l 50 w en Z - 100 3 .. Z ~ Hz 5 10 15 20 SUPPLY VOLTAGE IVDC) ::. 100 az 40 = 6? 20 u; - G = 100.10001 16 ~ \ I .s ±8 UJ a: a: ±6 u ±4 v fZ G=5tol00 RL = 2kn _ 20 30 TIME IllS) 5 10 15 20 OUTPUT CURRENT ImA) SUPPLY CURRENT VS COMMON-MODE INPUT \ C L ~ 100~ pF 0 \- 40 50 :::l .... ./" V ,/" >- ..J ±2 :::l en o ±2 ±4 ±6 ±S ±10 COMMON-MODE VOLTAGE IV) INSTALLATION AND OPERATING INSTRUCTIONS SETTING THE GAIN (such as imbalanced source impedances), the circuit in figure 5 may be used. In this circuit, Rl is added to intentionally imbalance the inverting and noninverting gains of the amplifier. R2 is then used to rebalance them, which overcomes the effects of any residual CMR degradation due to source impedance imbalance, etc. An improvement of approximately 6 to 10 dB can be typically realized at low gains. Figure 3 shows the normal operating connections for the 3626. The differential gain, G, is determined according to the equation G = 5 + 10kn R(; where R(; is the resistor shown in Figure 4. This gain equation is typically accurate to 0.25%. The temperature coefficient ofR(; will directly affect the stability of G. For high gains, R(; will be quite small (R(; = Ion for G = 1000); thus, the wiring impedance between pins 12 and I should be kept as low as possible. (Trimming of R(; will eliminate the effects of wiring impedances so long as this impedance is constant.) Also, note that VrefSource needs to be low impedance so as not to significantly affect the gain equation. CMRTRIM The 3626 meets its CMR specifications without additional trimming; however, for improved CMR in special situations FIGURE 5. CMR Trim. 2-45 3627 BURR-BROWN@ IElIEII High Accuracy Unity-Gain DIFFERENTIAL AMPLIFIER FEATURES • LOW COST • EASY TO USE • COMPLETELY SELF-CONTAINED • HIGH ACCURACY Gain Error. 0.005% Nonlinearity. 0.0005% CMR.I06dB • NO TRIMMING REQUIRED DESCRIPTION The 3627 is a high accuracy committed-gain differential amplifier. It consists of a high quality monolithic operation amplifier, a low drift thin-film resistor network and laser-trimmed offset circuitryall inside a single integrated circuit package. The fact that the 3627 is completely self-contained in a T0-99 package has several user benefits: The total performance is guaranteed as a single component. No gain adjustments are required. No offset trimming is required .. The whole circuit, including the gain setting resistors and offset trim circuitry, is protected by the environmentally rugged hermetically sealed package. The total amplifier function is very small in size (0.108 square inches of area and 0.025 cubic inches of volume). The 3627 is offered ill two grades: the 3627AM and the 3627BM. They differ only in common-mode rejection (94dB typo vs 1000B typ.) and offset voltage drift (151lV j"C typo vs IOIlV /"C typ.). The 3627 offers excellent total performance with no fuss and a very-low total instaJled cost. Inlarnatlanal Alrporllnduslrlal Park· P.O. 80x 11400· Tuclon. Arizona 85734· Tal. (602) 746·1111· Twx: 911).952·1111· Cable: 88RCORp· Telax: 66-6491 PDS·364A 2-46 used in choosing the trimming sequence a frustrating iterative trimming process can be encountered. With the 3627 these problems no longer exist for the user. They are solved inside the package by Burr-Brown and the user has a completely self-contained plug-in-and-go amplifier to use. The excellent gain accuracy. and common-mode rejection is obtained by using lasertrimming of a thin-film resistor network (R I through R4). The outstanding gain and common-mode rejection temperature coefficients are a result of the excellent TCR tracking properties inherent in Burr-Brown's thin-film resistor networks. The offset voltage is also laser-trimmed to a very low 250~ V max value (I OO~ V typical). This low value of offset eliminates the need for external offset adjust potentiometers which reduces cost and improves reliability. The basic approach of the 3627 as a completely selfcontained amplifier has several cost saving implications. It reduces design, purchasing and inventory cost. It reduces. labor costs because the gain setting resistors do not require installation and adjustment. Also, no potentiometers are required. DISCUSSION The 3627 is a new and unique approach to a widely occurring problem-how to get excellent performance at a low cost in a unity gain differential amplifier circuit. BurrBrown's solution to this problem uses its wide range of integrated circuit expertise; .a high quality monolithic amplifier, low drift high stability thin-film resistor network and state-of-the-art laser-trimming techniques. The result is a completely self-contained amplifier with total guaranteed 25°C accuracy of less than ±0.015% (gain error, nonlinearity, offsets and common-mode . rejection). The simplicity of the unity gain differential amplifier circuit may be deceiving when one considers an error analysis. Consider, for "xample, gain and common-mode rejection errors. The gain is determined by the ratio of R I and R2 and the ratio of R3 and R4. The common-mode rejection of the total circuit is a function of the CM R of the operational amplifier and the matching of the resistors R I to R3 and R2 to R4. Even if the operational amplifier is perfect (infinite CMR), in order to guarantee lOOdB common-mode rejection would require resistor match of approximately 0.0005% (5ppm). This matching (and especially maintaining the match over temperature) can be difficult and expensive to achieve. Packaged matched and tracking resistor networks are available but they are fairly expensive compared to the cost of the complete 3627 amplifier. Of course, matching can be obtained by trimming or padding some of the resistors, but this is difficult to do since each resistor effects· both gain accuracy and common-mode rejection simultaneously. Unless care is Ref FIGURE I. Simplified Circuit Diagram. VARIABLE GAIN DIFFERENTIAL AMPLIFIER UNITY <7AIN DIFFERENCE AMPLIFIER +V < x ecm < 10-5 20V HIGH INPUT IMPEDANCE. VARIABLE GAIN, INSTRUMENTATION AMPLIFIER DIFFERENTIAL IN - DIFFERENTIAL OUT AMPLIFIER Zin = 10Mf! 2-47 ELECTRICAL SPECIFICATIONS MECHANICAL Specifications typical at 2S"C and ±ISVDC power supply unless otherwise noticed. MODELS I 3627AM GAIN Gain Equation Gain Error Gain N onlinearit{:!J Gain Temp. Coefficient. max Gain Temp. Coefficient. typ OUTPUT Rated Output. min Rated Output. typ Output Impedance 3627BM G _IVjV W ±O.OI%•. max (±O.ooS% typ) ±O.OOI%. max (±O.OOOS'I( typ) ±O.OOOS'Ii.. "c (Sppm, "C) ±O.OOO2%!"C (2ppm/ "C) ±IOV at ±SmA ±12V at ±IOmA 0.0111 INI'UT Input Impedance SOkll SOkil Differential Common-mode Input Voltage Range. Linear Operation Differential ±IOV ±20V Common-mode Common-mode Rejection. DC to 6OH1. CMR. at2S"C CM R. -2S"C to +8S"C OFFSET AND NOISE I Offset Voltage. RTO(411 I 9OdB. min (94dB. typ) 8OdB. min (9OdB. typ) I at2S"C vs Temperature, JAV!"C vs Supply vs Time Noise Voltage. RT044Uhl O.OIHzto 10Hz 10Hz to 100Hz 1000B. min (I06imum peak deviation from the best straight line as a percent of full scale peak-la-peak output. 1 With zero source impedance unbalance. 4. Referred to output in unity-gain difference configuration. Note that this circuit has a gain of 2 for the operational amplifiers offset voltage and noise voltage. 5. Includes effects of amplifiers' input bias currents. 6. Includes effects of amplifiers' input current noise. CONNECTION DIAGRAM TOP VIEW TAB -Vcc See Figure I for circuit diagrams. 2-48 TYPICAL PERFORMANCE CURVES (Typical at 2SoC and ±.15 VDC Power Supplies unless otherwise noted.) INPUT RANGE FOR LINEAR RESPONSE 3dB 201~--+---~--~--~---l 151---t---t- ~ et: 1%0 10 z .1% '" ~ .01% °0~--~5--~1~0~~15~~2~0---J SUPPLY VOLTAGE (V) STEP RESPONSE '...,«" f-< f-< ~ 0. / I 0 f-< -5 0 -10 ~: o .001% 100200lk 10k lOOk 1M FREQUENCY (Hz) -60 10M 10 , 3dB ~ '...,«" f-< 0 > f-< ~ 50 0. f-< ~ 0 -20 100 Ik 10k lOOk 1M FREQUENCY (Hz) TYPICAL APPLICATIONS 10M '" ~ 100 Ik 10k lOOk FREQUENCY (Hz) I 20 ~ 20 30 40 TIME (I's) \' i'... MAXIMUM OUTPUT VOL TAGE VS OUTPUT CURRENT SMALL SIGNAL GAIN VS FREQUENCY _\ 10 \ \ AM -70 ,j ~ \BM ::;: -80 ~ V - u \ / -90 - et: ~ j 0 > I '" :::. 1% +5 -100 /' ~ +10 -110 ,;- 10% ll" et: ~ COMMON-MODE REJECTION VS FREQUENCY GAIN ERROR VS FREQUENCY 15 10 - \1.J ~ 8\1 i~ V'~~IO\1 ---x:. ~ ~~\1 o o -....." ~ " 5 10 15 20 25 OUTPUT CURRENT (rnA) IUGH ACCURACY, LOW DRIFT, LOW OFFSET-UNIT GAIN INVERTER el Accuracy .01% Linearity .001 % Offset < 2501'V at output Offset Drift < 20l'V/OC at output @ 10 yoltsand 100mA with 3329 eo ~ (e2 - el) @ 10 yolts and 200mA with 3553 NON-INVERTING SUMMER }-----.....--oeo 2-49 3629 BURR-BROWN@ IElElI Low Drift INSTRUMENTATION AMPLIFIER FEATURES • VERY-LOW VOLTAGE DRIFT oJ5I1V/oC • HIGH CMR - godB (al 60Hz • LOW BIAS CURRENT - 2DnA • LOW NOISE - 1.2\1V POp • SMALL SIZE - OIP Package DESCRIPTION Offering very-low voltage drift versus temperature even at low gains, the 3629 meets critical instrumentation requirements when amplifying low level signals in the presence of high common-mode voltages. This precision integrated circuit instrumentation amplifier offers low bias current and high input impedance (JOlOn). A single resistor sets gain from 5V IV to lOOOV IV. The 3629 exceeds the performance of other Ie instrumentation amplifiers and offers many benefits, for instrumentation applications: Low voltage drift to reduce temperature errors High common-mode rejection to preserve system accuracy High input impedance to minimize errors caused by source loading and source impedance imbalance Small, dual-in-line plastic or hermetically sealed metal package to conserve board space " Laser-trimmed offset to eliminate nulling Use the 3629 to eliminate problems and compromises that arise when attempting to use operational amplifiers to achieve the same gain function. International Airport Industrial Park· P.O. 80x 11400· Tucson, Arizona 85734· Tel. 16021 746·1111 . Twx: 911).952·1111 . Cable: 88RCORP· Telex: 66·6491 PDS-383 2-50 DISCUSSION Instrumentation amplifiers are closed loop gain blocks whose committed circuitry accurately amplifies the voltage applied to their inputs. They respond only to the difference between the two input signals and exhibit extremely high input impedance, both differentially and common-mode. Feedback networks are packaged within the amplifier module. Only one external gain setting resistor must be added. An operational amplifier, on the other hand, is an open loop, uncommitted device that requires external networks to close the loop. While op amps can be used to achieve the same basic function as instrumentation amplifiers, it is difficult to reach the same level of performance. Using op amps often leads to design trade-offs when it is necessary to amplify low-level signals in the presence of common-mode voltages while maintaining high input impedances. Figure I represents a simplified circuit diagram of the 3629. The circuit employs high performance bipolar IC amps and a laser trimmed thin-film resistor network. The 3629 offers excellent performance. Its low voltage drift reduces temperature errors, especially at low and medium gains. Figure 2 illustrates the drift performance of the 3629 compared with competitive monolithic IC instrumentation amplifiers. Note that the drift does not increase at lower gains. Compare the 3629's input offset voltage drift vs temp at 1.75/LV j"C with monolithic IC instrumentation amps in the range of 100/LV rC. Because of its design, output biasing of the 3629 is easily accomplished. See Figure 3 for connections. The impedance of the reference source should be low compared to 10kO. Figure 3 also shows a current booster, such as Burr-Brown's 3329 (lOOmA) or 3553 (200mA), used with the 3629 to increase its output current driving capability while retaining its 5-1000 V / V gain characteristics. If power boosting is not required, connect pin 8 to pin 9. GAIN (V/V) FIGURE 2. Input Offset Drift vs Gain. FIGURE I. Simplified Circuit Diagram. FIGURE 3. Output Biasing and Power Boosting. 2-51 DESIGN VERSATILITY The 3629 offers additional application versatility. Its matched pair of amplifiers can be. used as two independent, uncommitted op amps with a laser trimmed thin-film network present in one package. When amplification must be extended to gains below 5, a 3629 used with a unity gain instrumentation amplifier (Burr-Brown's 3627) is recommended. This connection is shown in Figure 4. MECHANICAL 3629AP. 3629BP. 3629CP Weight: 2.9 grams (0.10 oz.) i 12.7mm (050") S.lm (0.20") 11 ~T ~oS~~~-jI- DESIGN ALTERNATIVES ·To amplify signals in the presence of common-mode voltages and noise while maintaining high input impedance, you can: I) design and build an op amp circuit with a differential input configuration; 2) design and build an instrumentation amplifier made up of multiple op amps or; 3) purchase a ready-to-instalI, committed instrumentation amplifier. Only the third option provides an immediate solution with the elimination of in-house design, assembly and tuning steps. The growing range of lower cost, high quality IC instrumentation amps available has answered the build or buy question. Pin I 3629AM. 3629BM. 3629CM. 3629SM Weight: 3.9 grams (0.13 oz.) 6.4mm (0.25") ·ir 4.8mm 22.0mm (0.87") ~ 1I ) ~n~nH 1 2.5mm Pin I ....._~(O;.;.I...;")~-+... _12.6mm-j (0.19") 1 (0.50") "'I~ G=f-r O.46mm-lI_ (0.018,,) 7.6mm (0.30") Pin 14 +vcc 0000000 Connector: Ol45MC (l4-pin DIP) Pin material and plating composition conform to method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2) FIGURE 5. Mechanical Specifications +vcc * Optional -vec FIGURE 4. 3629 In A Composite Instrumentation Amplifier. -vcc FIGURE 6. Connection Diagram 2-52 Offset Trim ELECTRICAL SPECIFICATIONS Specificalionslypical at 2S"C with ±15VDC power supply unless otherwise noted. 3629.P.3629.M. 3629AP.3629A: MODEL min GAIN Range of Gain Gain Equation Error From Equation. DC Gain Temp. Coefficient G =5 G = 10 G = 100 G = 1000 Nonlinearity. DC RATED OUTPUT Voltage Current OU'pu, Imp"'an", 0 = 100 'yp max min 'yp 295M m., min J629CP. 3629CI 'yp UNITS max 1000 VtV VtV 10 = 5 + 20ktR" I" 12 20 25 ±(O.OO2 + lO,jO) flO ±IO INPUT OFFSET VOLTAGE Initial Offset at 2S"C vs. Temp. vs. Supply vs. Time ppm/"C ppmtC ppm/"C ppm/"C 25 .5 50 + :~O'~_~G) !:~~) :(,~"!'~) ±(O.OOI ±(0.OO3 + 10-'0) + 10-'0) ±12.S ±12.S 0.01 ±25 ±200/G V mA 0 ±50 ±400/G ±3 ±IO{G 10 ±IO ±IOO/G ±IO ±25 ±200/G ±1.5±7.5IG ±IO ±IOO/G ±25 ±200/G ±o.75±5/G ~v IlVrC ",V/V ",V/mo ±o.4 INPUT BIAS CURRENT Initial Bias Current (each input) % p-p FS tiS ±35 \IS. Temp. ±O.30 ±o.60 nA/~C vs. Supply ±o.1 ±IS ±O.2 ±SO ±O.6 ±1.2 nA/V nA nAtC Initial Offset CUrTent vs. Temp. INPU1 Differential V~LTAGE ±30 10 II 3 10113 Common~modc INPUT ±IO ±25 ±5 ±5 ±20 ±20 nA OOllpF RANGE Differential ±IO v Common~mode ±6 V eM R w /1 kfl Source Imbalance DC.G=5 .0= 10 • G = 100 to 1000 60 Hz All Gains 100 106 110 90 INPUT NOISE Voltage. pop. O.OIHz ~ 10Hz rms. 10Hz ~ 1.0 kHz C~rrcnt, pop. O.OIHz ~ 10Hz rms, 10Hz ~ I.OkHz DYNAMIC RESPONSE Small Signal, ±3dB Flatness. 0=5 0=10 0=100 G = 1000 Small Signal, ±1% Flatness, Oe5 G= 10 G = 100 G = 1000 Full Power, G = 5 ~ 100 Slew Rate. G = 5 ~ 100 Settling Time (0.1%) 0=5 G = 100 G = 1000 Settling: Time (.01%) 0=5 G = 100 G = 1000 104 110 120 92 dB dB dB dB 1.2 1.0 70 20 I'V rros pA p~p pA , ... ~V p~p 90 kHz kHz kHz kHz 60 301 3.5 7.2 0.2 kHz kHz kHz Hz kHz 3.' 0.33 30 7.5 0.45 V/Il ilec ."".... ."" .... 35 85 350 40 -"' 120 ...c 400 POW.R SUPPLY Rated Voltage Voltage Range Current, Quiescent specification i21 : RANGE Operation Storage * Specifications same as for 3629API AM. v ±15 ±5 ±5 -25 -55 -65 ±2O ±7 V mA +85 +125 +150 ·C ·C ·C (I) See Typical Performance Curves. (2) -SS·C to +I2.S·C for 3629SM. TABLE 1. 2-53 TYPICAL PERF-ORMANCECURVES COMMON·MODE REJECTION VS SOURCE RESISTANCE IMBALANCE OUTPUT OFFSET DRIFT VS GAIN 140 Go 100· Jl 0 :;- .:I ~ Z line -..... G: IOOC G=5 DC IO.~ ~ G= 5,60H7. ~ 1 0 I..~=;:::::::±-....':!..:.~::.!!!~ 100 Ik 10k 60 Ik SOURCE RESISTANCE(n) FREQUENCY RESPONSE ,, 40 ~ ~ ~.- I'}F Error , ,/ G=5 0 100 Ik 10k ~ 100 10 lOOk 1000 100 5.10 GAIN (V/VI CMR VS FREQUENCY , ""<- \ lOOk J lkn Source Impedance Imbalance Vcm= 20Vp.p 100 G= 10 .:I I;: i , _ G-5 Joo " ,, .......... 3.~k 10k SQURfE RESISTANCE IMBALANCE WI "o ~'OO.'OOO J. Jooo 60 , 1000 ~ ........ I"'---.. G= 10 100 60 H1- 3. t ~ -1.0'~--t-+---+-~-+----I "- "- ,., ffi ~ -o.s'I--+-+---+--~~---l " ~'j' -- 60 iil G=5~ 40 1M I 10 FREQUENCY (Hz) 100 Ik 10k ""i ~ " 'O.S;!-,_--:-!;~_--:-:!;-_~::;:;-_""'" GAIN (Y/V) FREQUENCY (Hz) TYPIC AL SUPPLY CURRENT VS COMMON MOOt: VOL T AG~' QUIESCENT CURRENT VS SUPPLY VOLTAGE STEP RESPONSE is.0 i6 " , .S is1J 'S~ G= 100 ./ / - - P .0 :!:.v.S V ~cr"v :!:.5 ±.75 ±.IO COMMON·MODE VOLTAGE (V) ±3.0 11.,,000 1\ 0 /" S / RL= lkn , CL = IOOOpF G,,/' V / 0 0 '/ !\ ~ -I 0....1 :!:.S :l10 1.15 SUPPLY VOLTAGE (VI ±.10 o 50 ISO _so 350 TIME ($.Istc) INSTALLATION AND OPERATING INSTRUCTIONS OFFSET VOLTAGE ADJUSTMENT Initial offset of the 3629 is trimmed to a very low value during production. In most applications further nulling will not be required. If it is necessary to null offset to the lowest possible value, a low cost single turn potentiometer can be connected between pins 4 and 5 as shown ill Figure 6. Drift changes O.33~V j"C for each lOO~V I of offset voltage nulled. Due to second order effects,' the point of minimum offset drift does not occur at the point of zero offset voltage in approximately 25% of the cases. In these instances nulling the offset voltage may cause a slight increase in voltage drift. A following stage should be used if large system offsets must be nulled. This method results in the lowest possible drift. In the circuit shown in Figure 7, the offset component !>fVoUT due to VI is VIR2/RI. Resistors RI through R4 are selected to provide system scaling Imd to make the offset component of VOUT due to V2 cancel the component of VOUT due to VI. 2-54 Low Pass Filter _ APPLICATIONS r- - - I C I , 1 RZ 1 TRANSDUCER APPLICATION A bridge transducer, Figure 9, with a 0 to O.IY output requires amplification to interface with a 0 to lOY range system. The bridge introduces a lOOn source imbalance and O.2SY of 60Hz noise is present on the ground return. Operating temperature range is lOoe to SO°c. Absolute gain and offset errors can be trimmed to zero. The remaining error sources are tabulated in Table II as a % of Full Scale. FIGURE 7. Multi-stage Amplifier For Offset Null and High Frequency Filtering. Absolute Error NOISE The 3629 offers very low noise at low and midfrequencies. See specifications and performance curves. At frequencies above 100kHz, noise increases and may cause errors if the following circuitry responds to higher frequencies. When high frequency noise must be reduced, a low pass filter should be installed in a stage following the 3629. Figures 7 and 8 illustrate two high frequency filtering approaches. Max -1 - Max Typ Gain Nonlinearity 0.004% 0.002% 0.004% 0.002% CMR 0.008% 0.0063% 0.008% 0.0063% 0.0012% 0.00120/, 0.0\32% 0.0095% 0.1 to IOOH1. Part of ~" System Resolution Error Noise Following ,~~...J>N\....._Mr~ Typ 0.0012% 0.0012% Voltage Offset Drift 0.032% 0.021J<1t Offset Current Drift 0.0048% 0.0024% Gain Drift 0.2IJ 1000). MECHANICAL The optional offset mill capability is shown in Figure 4. ,~ The adjustment affects only the input stage component of the offset voltage~ Thus, the null condition will be disturbed when the gain is changed. Also,the input drift will be effected by approximately 0.33",VloC per 100",V of input offset voltage nulled. Output offsetting ("zero suppression" or "zero elevation") may be more easily accomplished with the 3630 than with most other IC instrumentation amplifiers. 6.4mm 1. Ir= I (0,25")1 27.2mm (1.07") ~ 1 00 0~5!~ uuu 1,: 12'6mm~ (0.50,,) -...i r=:J 4.8mm TT·(O.l9") ....jJo- O.46mm (0.018,,) Pin material and plating composition conform to Method 2003 (solderability) of Mil·Std-883 (except paragraph 3,2), +vcc FIGURE 3. Mechanical Specifications VOUT PIN DESIGNATIONS I. Oain Sense 2. Inverting InpUt , 3. Negative Supply -Vee 4. Common-mode Voltage Sense S.Oain 6. Ground 7. Reference '8. Output of AJ 9. Input to A. FIGURE 2. Basic Connections Figure 5 shows how this is done. The use of the noninvertinginput of the output stage means that CMR of the second stage is not dist~rbed and that any convenient value of variable resistor can be used. The output stage also allows active low pass filtering to be implemented conveniently with a single capacitor. The effect this filtering has on noise reduction can be seen in the Typical Performancp Curves. 10. OUtput II. Sense 12. Summing Junction of A. 13. Positive Supply 14.0ain IS. Offset'Trim 16. Offset Trim 17. Noninverting Input 18.0ainSense The input stage contains extra resistors for the computation of input common-mode voltage. Figure 7 shows how this voltage, available at pin 4, can be used to drive the shield of the input cable. Since the cable is driven at the common-mode voltage the effects of distributed capacitance is reduced and the AC system common-mode rejection may be improved. Amplifier Al is a buffer to supply larger currents than can be supplied ,by the 20kO resistors internally ~onnected to pin 4. 2-58 ELECTRICAL SPECIFICATIONS Specifications typical at 2S"C with ±15VDC power supply and in circuit of Figure 2 unless oth~ise noted. 3630AM MODEL GAIN Range of Gain Gain Equation Error From Equation, DC 1000 G = I +40k/R.. (±O.OS (±O.I ±O.oooIG) ±O.0002G) Gain Temp. Coefficient (I! G= I G= 10 G = 100 G = 1000 Nonlinearity. DC 8 45 50 50 t 0.. f- 0.OOO3~ ::> o _ _....1_ _ __'__ ___1 10 100 1000 GAIN (V/V) GAIN NONLINEARITY VS GAIN 120 G= 100 1000 GJooo =: :2- J " ,~ J I%Error~\ ~ G= 100 40 :z :;: " G=IO 20 \ \ \ G=I =: :2'" ::; ' Gt ~ 80 Balanced Soun:e U Ik 10k lOOk 1M 10% =: :2- 1% .0I% ...._...I,_ _..L.._--1L...._.... 10 100 Ik' 10k lOOk FREQUENCY (Hz) GAIN ERROR VS FREQUENCY G= I I 1 \ " ............. ±8 / / / / V +10 / CL = looopF ~ :l E f- ::> 0. "' 1000 ! I> 3 ISO 250 TIME STEP RESPONSE 350 G=loo > ~ ""' "<"' ~10~----+-----~~-4--- 100 :; ....f0 0 "'is "'is "'0 1 < > 20 :z 0.. f- ::> 0 oI 100 1000 GAIN (V/V) OUTPUT NOISE VS GAIN 2-60 "'~ 0 > > "'fa 30 ~ ~ ~ t; 0.. t; o 10 100 GAIN (V/V) SETTLING TIME VS GAIN \ so 'Ci: Cr=O , .....::::: -10 ~ :z ..io""" T 0.. looor----~------~----__. RL =2k V lt; ±s ±IO ±Is ±20 SUPPLY VOLTAGE. (Volts) QUIESCENT CURRENT VS SUPPLY 4 TIME (Minutes) WARM-UP DRIFT VS TIME ::; i= :;: " = 2S"C \ "' 0 1% '"'"'" :z 10 100 Ik FREQUENCY (Hz) CMR VS FREQUENCY FREQUENCY (Hz) GAIN VS FREQUENCY I '" " \ 100 TA """- \ I 10 G-IO 100 ' 10 100 1000 GAIN (V/II) OUTPUT OFFSET DRIFT VSGAIN I 3.2 10 32 100 SOURCE RESISTANCE IMBALANCE (kO) CMR VS SOURCE IMBLANCE 10 ~ :z f- f- ::> ::> 0.. 0.. f- ::> ::> f- 0 0 0 10 Ik 100 FREQUENCY (Hz) OUTPUT NOISE VS 3dB FREQUENCY APPLICATIONS +Vn Optional Offset Null R VOUT I V 2)(1 +vcc Fp= - - - Hz VOUT - FIGURE 5. Output Offsetting FIGURE 4. Optional Offset Null 211'CF 10" = (VI = any convenient +vcc Cr in farads = (V, - V,)(I + 4Ok/Ro)[I/(1 + 2m 10' x C,)] FIGURE 6. Active Low Pass Filtering FIGURE 7. Use of Guard Drive +VlT -Vee:' -Vee Vou, = (V, - V,)[I + (40kl Ro)Ilk + (R,/I0k)] FIGURE 8. Additional Gain From Output Stage FIGURE 9. Output Power Boosting 2-61 value + 4Ok/RG ) + 2VREF ISOLATION AMPLIFIERS II WHAT IS AN ISOLATION AMPLIFIER? An isolation amplifier is a device with the primary function of providing ohmic isolation (break the ohmic continuity of electrical signal) between the input signal/circuitry and the output of the amplifiers., It usually consists of an input operational amplifier or instrumentation amplifier followed by a unity-gain isolation stage. The sole purpose of the unity-gain isolation stage is to completely isolate the input from the output of the device. Ideally, thEi ohmic continuity of the input signal is broken (at the isolation barrier) yet accurate signal transfer without any attenuation is achieved across the unity-gain isolation stage. An important feature of an isolation amplifier is that it has a completely floating input which helps eliminate cumbersome connections to source ground in several applications. Figures 1 and 2 show typical isolation amplifier applications. The isolationmode voltage Visa is the voltage which exists across the isolation barrier. The contribution of the output referred error caused by Visa is (Visa/IMRR) X Gain where IMRR is the Isolation Mode Rejection Ratio. Vsig is the differential input signal and Vern is the common-mode voltage. The "LeakageCurrent" is the current which flows across the isolation barrier with some specified isolation voltage applied between the input and the output. CHARACTERISTICS OF ISOLATION AMPLIFIERS The following is a discussion of some of the characteristics and terms unique to isolation amplifiers. Common-mode Voltage and Isolation Voltage - Some manufacturers (other than Burr-Brown) treat common-mode voltage and isolation voltages synonymously in describing the use and/or specifications of isolation amplifiers. It is important to understand the significance of these terms and the difference between them. When the input common is grounded, the input signal Vd (see Figure 1) can be floated by the amount Vern above the input ground. Vern is the common- 3-1 mode voltage (CMV) and is generally ±10V~limited by the CMV rating of the input stage amplifier. In applications involving higher systems commonmode voltages, input common terminal is not grounded and the commonmode voltages are referenced across the isolation barrier to the output common terminal. VCM ERROR ~ ERROR CMRR IMRRo " .Ig Vo = I"SIG ± vCM ± vlSO I G.ln CMRR IMRR °IMRR IN AMPS/VOLT °IMRR IN VOLTS/VOLT FIGURE 2. Typical Isolation Amplifier, Voltage (Input) Mode. FIGURE 1. Typical Isolation Amplifier, Current (Input) Mode. The isolation voltage Visa as shown in Figure 1 is the potential difference between the input common and the output common terminals. The isolation voltage rating describes the amount of voltage that the isolation barrier can withstand without breakdown. This feature of the isolation amplifier allows two distinct ground connections to be made when necessary. It allows the isolation amplifier to be used in applications involving very-high commonmode voltages and in applications of breaking ground loops. Many applications involve a large "system common-mode voltage." In such applications, the isolation amplifier's input common terminal is not connected to any ground but the output common terminal is connected to the system ground. In such a case, the term Vern shown in Figures 1 and 2 becomes negligible and Visa determines the safe limit for the system common-mode voltage. In this manner, the isolation amplifier can accommodate common-mode voltages of 2000V or more. Common-mode Rejection and Isolation Rejection -Isolation-mode rejection (I M R) is another term which some other manufacturers refer to as commonmode rejection (CMR). The above discussion on the common-mode voltage and isolation voltage helps recognize the difference between CMR and the IMR. The CMR is the measure of the input stage amplifier's ability to reject common-mode input signals (common-mode with reference to the output common) while transmitting the differential signal across the isolation barrier. The isolation-mode rejection ratio (IMRR) is defined by the equation shown in Figures 1 and 2. Thus, understanding the IMR capability of isolation amplifiers allows their meaningful use in applications requiring very high common-mode rejection ratios such as 100dB to 14OdB. Isolation Voltage Ratings, Test Voltage - It is important to understand the significance of the continuous derated isolation voltage specification and its relationship to the actual test voltage applied to the unit. Since a "continuous" test is impractical in a product manufacturing situation (implies infinite test duration) it is generally accepted practice to perform a production test at a higher voltage (higher than the continuous rating) for some shorter length of time. 3-2 The important consideration is then "what is the relationship between actual test conditions and the continuous derated minimum specification?" There are several rules of thumb used throughout the industry to establish this relationship. For most isolation amplifiers, Burr-Brown has chosen a very conservative one: Vtest = (2 x Vcontinuous rating) + 1000V. This relationship is appropriate for conditions where the system transient voltages are not well defined. - Where the real voltages are well defined or where the isolation voltage is not continuous the user may chose to use a less conservative derating to establish a specification from the test voltage. APPLICATIONS OF ISOLATION AMPLIFIERS When one or more of the following conditions/requirements are present in an application, an isolation amplifier would generally be the right choice as a signal conditioning device: • When ohmic isolation between the signal source and the output is a requirement (isolation impedance between the input and the output> 10MO). • When excellent common-mode noise and voltage rejection is a requirement (CMR > 100dB). • When it is necessary to process signals in the presence of, or riding on, high common-mode voltages (CMV ~ 10V). In general, most applications can be broadly categorized into the following four types: • Amplifying and measuring low level signals in the presence of high common-mode Voltages. • Breaking ground loops and/or eliminating source ground connections. The isolation amplifier provides full floating input, eliminating the need for connections to source ground, and thus allows two-wire hook-up to the signal sources. • Providing an interface between medical patient monitoring equipment and the transducer/devices which may be in physical contact with the patients. Such applications require high isolation voltage levels and verylow leakage currents. • Providing isolation protection to electronic instruments/equipment. Large common-mode voltages occasionally cause hazardous electronic faults. Low leakage currents and high isolation voltage capability of isolation amplifiers help protect instruments against damage caused by such faults. Isolation amplifier performance requirements vary significantly, depending on the type of requirement. In applications where bandwidth and speed of' response are more important than gain accuracy and linearity, the opticallycoupled amplifiers will be the best choice. For applications where gain accuracy and linearity are key parameters, Burr-Brown's family of transformer-coupled amplifiers are the suitable choice. -Reference National Electrical Manufacturers Association (NEMA) Standards Parts ICS 1-109and ICS 1-111. 3-3 SELECTION GUIDE Isolation Amplifiers TRANSFORMERCOUPLED~ArM~P~LI~F~IE~R~S~______. -__-r____~____- .____-r________~--~ Isolation Voltage Isolation Mode contin:I,PUISe/ Ae}8ctlon. min. UQUS Test IV.peak rVlpeak 3656JG 3656KG Power ma. kH, ReqUired Temp. RangeP) Package Price $ ±O.OO5 ±O.oatS 1 + l100/GlI 50nA 1.5 No Com Module 229.50 149.00 3-19 ±500 ±2000 ±2000 ±50CJlf 160 160 120 120 25pA 20pA 20pA 2.5 2.5 25 C::om 120 50 + (l00/G,1 5 + (100/G,) 5 + (loo(Gl I N0I41 160 ±0.025 ±0.005 ±O.D2S· ±0.005 ±0.025 ±D.D05 Com (3) 16 16 16 No (3) 1012 1012 1012 No(4) Com Module Modulf MOdule 121.50 8B,00 162.50 117.50 172.50 127.50 3-19 3-19 1-19 ±2000 ±20oo ±5000 ±5000 160 160 130 130 25 25 1012 1012 14 14 148.00 117.25 168.50 133.65 3-28 3-28 ±3500 ±35oo ±35oo ±8OOO ±8Ooo ±8000 ±8Ooo ±8Ooo 160 160 160 160 160 125 125 125 125 125 O~ 10 12 1012 1012 1012 1012 82.25 101.60 72.60 77.40 95.15 3-40 3-40 3-40 3455 3658HG '!:3dB Freq. 16 3451 3452 3656BG Eltternal Isolation Bias Curreat 1012 Low Bias 3656AG Offset 120 ±500 3456B ~7 Volt. Drift I±IlV/oC, 160 3450 3456A Voltage Gain Nonlinearity mal(. typ .%. % ±2000 Low Orl"(2) True 3-wire In·st.Amp Isolation .dB, Model Highest Isolation Voltage Input atTest 60Hz ,dB, Description FET u~ Leakage Current ±35OO ±3500 ,.A 131 0.5 0.5 0.5 0.5 ±0.02 ±C.08 ±O.Ol ±D.03 2 + I1501G, I 1 + (75/G" 50nA 50nA 2.5 2.5 No No Com Com Module Module ±O.t ±O.03 25 + !500/G!) lOOnA ±O.OS to.tS ±O.03 5 + 1350/G,! ±a.03 200+ (IOOO1G,1 ±O.03 50 + 175O/G11 :to.03 10+ 1350/G, I 30 30 30 30 30 No No No No No Ind Ind OIP DIP DIP DIP DIP Extern,a) Isolation Power Requ1red :to.t ±a.t 1DOnA IDOnA IDOnA lOOnA Com Com Com Unit 100's 55.10 74.15 48.65 51.90 63.75 Page 3-40 3-40 OPTICALLY COUPLED AMPLIFIERS Isolallon Isolation Voltage Mode Contln- Pulse! ReJection. min uous' Test ~ 60Hz (Vlpeak V)peak (dBI (dBI Description Model Balanced Current Input 3650HG 3650JG 3650KG 3650MG ±20oo ±2000 Balanced FET Input 3652HG 3652JG 3652MG Miniature Isolation Amplifier IS0100AP IS0100BP IS0100cP Leakage CiJrrenl al Test Isolation v~:?e r!7Fd7 Gain Nonhnearlty '~I ~~, Input Offset Volt. Drift I±p.VtoC Current t3dB Freq kHz B, .. Yesl 61 Yesl SI ±5000 ±5Ooo ±5000 ±50oo 140 140 140 140 120 120 120 120 0.25t!i) 0.251!i) 0.251!i1 0.25t!i1 1012 1012 1012 1012 1.8 1.8 1.8 1.8 ±0.2 :':01 :to.05 ±0.2 ±0.05 ±0.03 :to.D2 !O05 25+ (900/G, 10+ 145O/GI 5+(3OO/GI 100+ 1900IGI lanA 10nA lDnA lanA 15 15 15 15 ±2000 ±5OOO ±5000 ±50oo 140 140 140 120 120 120 0.251!i) 0.25{5t 0.251!i) 1012 1012 1012 1.8 1.8 1.8 ±0.2 ±0.1 ±0.2 "to.05 ±C.05 to.05 5O+!900/G, 25+145O/GI 100 + (90O/Gl 50nA ±20oo ±2000 15 15 15 ,(eaes! 50nA 750 750 750 1000 1000 1000 5pAN typ.(8) 400 pAN typ.(8) 1012 1012 . 1012 2.5 2.5 2:5 0.4 0.07 0.03 5+15/G1 2+ 12/G\ 1 + I1IG, 10nA(7) 10nA(7) 10nA eo eo eo Ves ±2000 ±2000 0.3 0.3 0.3 50nA Yesesl YeseSI Yeslel Yese61 Yes Yos Temp Rangel 1) Package Pnce .$ Unil 100's Page Ind Ind Ind Ind DIP DIP DIP DIP 51.00 66,30 80.60 44.90 30.60 42.30 59,00 29 10 3-32 3-32 3-32 3-32 lod Ind Ind DIP DIP DIP 66.30 SO.60 52.00 42.30 58 00 38.80 3-32 3-32 3-32 'nd Ind DIP DIP DIP '" '" 'nd ,91 NOTES: 11 Com =ooC to +700 C; Ind = -25°C to +85°C. 21 Bipolar. 31 Isolation voltage tested at 2500V, rms, 60Hz; leakage current tested for 2~A max at 240V, rms, 60Hz. 41 ±15V at ±15mA Isolated power available to power external circuitry. 51 At240Vl60l:lz. 61 Models 722 or724. 71 For 150100 values shown are los. 81 See product data sheet for detai~ed discussion. 9) Advance Intormation. subject to change. contact 3-4 Burr-Br~wn for price and delivery. GLOSSARY OF TERMS & DEFINITIONS Isolation Amplifiers transmitting the differential signal across the isolation barrier. It is the voltage or current that must be applied to the input to force the output to zero when Vi,o is present. ISOLATION AMPLIFIER A device which provides ohmic isolation (breaks ohmic continuity of an electric signal) between the input and the output of the device. Method of coupling may be thermal, magnetic, optical, or any means other than direct ohmic coupling. Such a device allows the input circuit to be referenced separately and independent- of the output circuitry. . For voltage input mode: IMRR = Vo error ISO/O V",; with Vo =0 For current input mode: ISOLATION BARRIER A barrier or region between the input and the output stage of an isolation amplifier, where signal transfer is achieved between the input and the output. IMRR = 10 error ISO, V;,o with Vo = 0 (10 = 0) ISOLATION VOLTAGE The potential difference between the input stage common and output stage common terminals of an isolation amplifier. ISOLATION IMPEDANCE The effective impedance between the input common terminal and the outputcornmon terminal. It is the impedance of the· isolation barrier. (Ii is usually specified as a typical parameter. Leakl!.ge current is related to isolation impedance and is usually specified with .a maximum limit.) ISOLATION VOLTAGE RATING The amount of voltage tha(can be impressed between the input common and the output common terminals (across the isolation barrier) without re.sulting in breakdown. LEAKAGE CURRENT The current that flows between the input common terminal and the output common terminal (across the isolation barrier) with a specified voltage applied acrosS it. (It is usually 100% tested and specified with a maximum limit.) ISOLATION-MODE REJECTION (IMR) The IMR is the measure of an isolation amplifier's ability to reject common-mode input signals (commonmode with reference to the output common), while 3-5 BURR-BROWN® IS0100 IE3IE3II ADVANCE INFORMATION· Subject to Change Miniature Low Drift - Wide Bandwidth ISOLATION AMPLIFIER FEATURES APPLICATLONS • EASY TO USE. SIMILAR TO AN OP AMP VQUT/IIN = RF. Current Input VoUT/VIN = RF/RIN. Voltage Input • INDUSTRIAL PROCESS CONTROL Transducer senSing (thermocouple. RTD. pressure bridges) 4mA to 20mA loops Motor and SCR control GroundlollP elimination • BIOMEDICAL MEASUREMENTS • JEST EQUI~MENT ' • DATA ACQUISITION • KEY PARAMETERS TESTED AT loDDV • ULTRA-LoW LEAKAGE. o.3JLA. max.at24oV/6DHz • WIDE BANDWIDTH. 60kHz • LOW COST • IS-PIN DIP PACKAGE DESCRIPTION Designs uSing the·ISOIOO are easily accomplished with relatively few external components. Since VOUT of the ISOIOO is simply I'NRo llT , gains can be changed by altering one resistor value. In addition, the ISOIOO has sufficient bandwidth (DC to 60kHz) to amplify most industrial and test equipment signals. The ISO 100 is a miniature low cost optically-coupled isolation amplifier. High accuracy, linearity, and time-temperature stability are achieved by coupling light from an LED back to the input (negative feedback) as well as forward to the output. Optical components are carefully matched and the amplifier is actively laser-trimmed to assure excellent tracking and low offset errors. The circuit acts as a current-to-voltage converter with a minimum of750V (2500V test) between input and output terminals. It also effectively breaks the galvanic connection between input and output commons as indicated by the ultra-low 60Hz leakage current of 0.3JLA at 240V. Voltage input operation is easily achieved by using one external resistor. Versatility along with outstanding DC and AC performance provide excellent solutions to a variety of challenging isolation problems. For example, the ISOlOO is capable of operating in many modes, including: noninverting (unipolar and bipolar) and inverting (unipolar and bipolar) configurations. Two precision current sources are provided to accomplish bipolar operation. Since these are not required for unipolar operation, they are available for external use (see Applications section). IREFI 1A.!!..1ICE ·Vee +Vee RF INPUT COMMON IRER B~CE OUTPUT COMMON ,Vee +Vee Inl8rnlllllllll Airport Induslrlal Park· P,O. Bax 11400· Tucson. ArlzolII 85734· Tel. (602) 746·1111 • Twx: 910-95Z·1111 • Cable: BBRCORp· Telex: 66-8491 PDS456 3-6 SPECIFICATIONS ELECTRICAL At TA = +25°C and ±Vcc = t 5VDC unless otherwise noted. PARAMETER CONDITIONS MIN 10sec 750 1000 2500 Voltage Rated Continuous, DC Test, Parametric(1) Test, Breakdown Rejection(2) DC 5 146 400 108 1012 11 RIN =10kn, Gain = 100 60Hz, 480V, RF = 1Mn RIN = 10kn, Gain = 100 AC Resistance II Capacitance Leakage Current IS0100A TYP 240V, rms, 60Hz -I MAX MIN 10100CP 10100 IP TYP MAX I MIN TYP MAX UNITS VDC VDC VDC pAN dB pAN dB n IIpF 0.3 p.A,rms OFFSET VOLTAGE (RTII Input Stage IVoSI) InitialOffset(1) vs Temperature vs Input Power Supplies(l) ysTime Output Stage (Vasa 1 InitialOllset(1) vs Temperature vs Output Power Supplies(1) 200 2 dB 300 2 500 5 105 200 2 dB nAN dB V 90 ±10 Common-Mode Range ~V ~VfOC ~V1kHr 1 3 60Hz, RF = lMn RIN = 10kn, Gain = 100 ~V ~VfOC ~V1kHr 1 vsTime Common-Mode Rejection Ratio(2) 300 2 500 5 105 i CURRENT SOURCES Magnitude Nominal vs Temperature vs Power Supplies Matching 10.5 12 0.3 ~ 12.5 400 3 175 175 nA ppmfOC nAN V n 50 150 0.3 Nominal V5 Temperature vs Power Supplies Compliance Voltage +15 -10 2x lOS Output Resistance Small Signal Bandwidth Full Power Bandwidth Slew Ratell) Settling Time kHz kHz 60 6 0.4 100 Gain= lV1~A Gain = 1V1~A, Va = ±10V 0.1% ppmfOC nAN V1~sec ~sec '''",rcn.. , un': RANGE -25 -40 -55 Specification Operating Storage +85 +100 +100 °C °C °C UNIPOLAR OPERATION GENERAL PARAMETERS Input Current Range Linear Operation -20 -1 Without Damage 0.1 Input Impedance RL = 2kO, RF = lMn DC Output Voltage Swing Output Impedance GAIN Initial Error (Adjustable To Zero )(1) VB Temperature vs Time -10 0 1200 ·· ~A mA n V n · Va =RF lliNI 2 0.03 0.05 0.1 Nonllnearityll)(3) 5 0.08 1 0.01 2 0.04 1 0.005 2 0.03 0.4 0.03 0.1 0.02 0.07 %FS %I"C %/kHr % hN=0.2~A CURRENT NOISE pA, p-p pA/.,rHz pA/.,rHz pA/.,rHz 20 0.01 Hz to 10Hz 10Hz 100Hz 1kHz INPUT OFFSET CURRENT -0.02 +1 1 0.7 0.65 (iosl InitialOllset vs Temperature 1 0.01 0.1 100 vs Power Supplies vsTime 3-7 10 0.05 nA nAlOC nAN pA/kHr ELECTRICAL (CONT) AtTA = +2SOC and ±Vcc = 15VDC unless otherwise noted PARAMETER MIN CONOITIONS POWER SUPPLIES' Input Stage Voltage (rated performance) Voltage (derated performanca, Supply Current IS0100AP TYP MAX MIN IS0100BP TYP MAX MIN IS0100cP TYP MAX ±15 ±7 liN =-0.02!,A liN =-20!,A Output Stage Voltage (rated performance) Voltage I derated performance I Supply Current Short Clrcuil Currenl Limi~') ±18 ±1.1 ±2 +8.-1.1 +13. -2 : ±1.1 Vo=O V V mA mA V V mA mA ±15 ±7 UNITS ±18 ±2 ±40 BIPOLAR OPERATION GENERAL PARAMETERS Input Curre'nt Range Linear Operation Without Damage Input Impedance Output Voltage Swing Output Impedance " +10 +1 -10 -1 0.1 RL = 2kll. RF = lMn +10 -10 1200 I'A mA II mA • n Va =RF (liNI GAIN Initial Error (Adjustable To Zero )(1) VI Temperature vs Time Nonlinearityl')(3) 2 0.03 0.05 0.1 CURRENT NOISE 0.01 Hz to 10Hz 10Hz 100Hz 1kHz 5 0.06 1 0.01 2 0.04 1 0.005 2 0.03 0.4 0.03 0.1 0.02 0.07 %01 FS %I"C %/kHr % liN=0.2!,A nA. pop pA/.jHZ pA/.jHZ pA/.jHZ 1.5 17 7 6 INPUT OFFSET CURRENT, los. bipolarl(4) Initial Ollset(') vs Temperature VB Power Supplies 40 20 200 3 0.7 10 70 1.3 ±18 +3.-2 +13.-2 V V mAo mA ±18 ±2 ±40 V V mA mA ±15 ±7 +2. -1.1 +8. -1.1 liN = +10!'A ioN =-10!,A Output Stage \lonage (rated performance) I/oltage (derated performance, Supply Current Short Circuit Current Limit(') ±15 ±7 ±1.1 Vo=O nA nAloe nAN pAlkHr 250 vsTime POWER SUPPLIES Input Stage Voltage (rated performance, VoHage (derated performance) Supply Currenl 35 0.8 • Same as ISOI OOAP. NOTES: 1. These parameters are tested during the l000V stress test. 2. See Theory of Operation section for definitions. For dB see Ex. 2, eM and HV errors. 3. Nonlinearity is the peak deviation from a "best fit" straight line expressed as a percent of full scale output. 4. Bipolar offset current includes effects of reference current mismatch and unip~lar offset current. MECHANICAL PIN CONFIGURATION .,. MIllIMETERS .990 ...~ R j,L 1.010 .510 0235 .01S .021 l00SA,StC 115 .'" .300SA,SIC .'1& 12."5 ".S3 INPUT COMMON 18 12.95 597 2.5 .. SA.StC 2.03 7.1i2SA,SIC 2.03 292 , NC' 2 +VccA2 3 VOUT 4 -VCCA2 5 BAL 7 RF 8 REF2 NOTE. Leads tn true pOsition within o 10~ O.255mm R at seatingptane. Pin numbers Shown tor ret,renceonty N'umbers not mal'tl;ed on package NC· 11 +VCCA, 10 9 OUTPUT COMMON "NO INTERNAL CONNECTION 3-8 ABSOLUTE MAXIMUM RATINGS ±18V 2500V Supply Volt.ges Isolation Voltage Input Current Storage Temperature Range Lead Temperature (soldering 10 seconds) Output Short-circuit Duration ±1mA -55°C to +100"C +30()oC Continuous to ground TYPICAL PERFORMANCE CURVES (TA = +25°C. ±Vcc = J5VDC unless otherwise noted) 20 SMALL SIGNAL FREQUENCY RESPONSE BIPOLAR INPUT STAGE SUPPLY CURRENT VS INPUT CURRENT +10 OUTPUT SWING - BIPOLAR +20 '"'" 10 +15 Iii '~"" -10 « -20 ~ OUTPUT '" c: STAGE POWER SUPPLY ~ :; 0. E +10 r- S- i5 +5 -30 0 1 ~ () ±7V 00 f - '" (/) -Vee -5 -10 -20 g" 100M +10 -10 +-20 1,0\ OUTPUT SWING - UNIPOLAR +20 k '" 0. +Vee = RF PHASE SHIFT VS FREQUENCY 0 ~ 112~AI(RFI .!: .l: 10M 1M Frequency (kHz \ E ~ ±10V It I V'va 100k ~ >±12V J ..: -20 1: 10k 10 ;{ +5 Ii f f UNIPOLAR INPUT STAGE SUPPLY CURRENT VS INPUT CURRENT .... +1°r---~-----r~~~ir~ Va = (-20pAI HF ~ ~ -5 > 900 '" c: e'"" ~ .<: i :; 1800 a. (/) -10 S- OUTPUT STAGE -15 :-POWER SUPPLY ~ 0 2700 10 100 1000 -20 10k ~ +5 I---"'o,t------hf-f-h'-ith'-f-+-I +7- ,I' ~ ±10 (5 -5: -Vee '" ±15 ~ '" -5 I---+----:---+H'-I-ft-f-h'-fl ~\ ±18 I lOOk 1M 10M Frequency (kHz I 3 liN CONTINUOUS DC ISOLATION VOLTAGE VS TEMPERATURE ISOLATION LEAKAGE CURRENT VS ISOLATION VOLTAGE (#-tAl AC ISOLATION VOLTAGE VS TEMPERATURE 15 ~ 2 ~ 750 t---1i----+---+--I7'-r1l ~ RECOMMENDED OPERATING REGION-+---I-t+H:.,.t ~ () "'" "" ]2 l'l "0 > g 500 "-; RECOMMENDED OPERATING REGION ---+--17~ ~ ...J U 2501--+---\---+--¥-;f.,1 () « « ~2~5--~----~------~--~~ Isolation Vottage (kV) Temperature 3-9 (OC) Temperature (oCI RATE OF GAIN ERROR SHIFT VS ISOLATION VOLTAGE 1.5.---.....,.--....,..--,----, GAIN ERROR VS TEMPERATURE AND ISOLATION VOLTAGE 3.0.----....,..---r---..., NOTES: VT and TT approximate the threshold for the indicated gain shift. This is caused by the properties of the optical cavity. Short term (initial) shift, not cumulative TT~+65°C, VT~200VDC.Shiftdoes not occur for AC voltages. 0.5 t---t--~~--t---1 VIM = Isolation·mode Vottage VT = Threshold Voltage TT = Threshold Temperature ~2~5~---+~2~5~--+~6~5~+~7~5----~+1~ Isolation Voltage IVDCI THEORY OF OPERATION The ISOIOO is fundamentally a unity gain current amplifier intended to transfer small signals between electrical circuits separated by high voltages or different references. In most applications an output voltage is obtained by passing the output current through the feedback resistor (Rd. The ISOIOO uses a single light emitting diode (LED) and a pair of photodiode detectors. coupled together. to isolate the output signal from the input. Figure I shows a simplified diagram of the amplifier. IREFI and IREF2 are required only for bipolar operation. to generate a midscale reference. The LED and photodiodes (D I and D2) are arranged such that the same amount of light falls on each photodiode. Thus. the currents generated by the diodes match very closely. As a result. the transfer function depends upon optical match, rather than absolute performance. Laser-trimming of the components improves matching and enhances accuracy, while negative feedback improves linearity. Negative feedback around A I occurs through the optical path formed by the LED and Dl. The signal is transferred across the isolation barrier by the matched light path to D2. 1-------t------~OUTPIiT COMMON CONNECT PINS 15 AND 16 FOR BIPOlAR CONNECT PINS 7 AND 8 FOR BIPOLA'R AND PINS 16 AND 17 FOR UNIPOLAR. AND PINS BAND 9 FOR UNIPOLAR FIGURE I. Simplified Block Diagram of the ISOIOO. TT Temperature (OC) The overall JSO amplifier is noninverting (a positive going input produces a positive going output). INSTALLATION AND OPERATING INSTRUCTIONS UNIPOLAR OPERATION In Figure I. assume a current, hN, flows out of the ISOIOO(hN must be negative in unipolar operation). This causes the voltage at pin 15 to decrease. Because the amplifier is inverting, the output of Al increases, driving current through the LED. As the LED light output increases, DI responds by generating an increasing current. The current increases until the sum of the currents in and out of the input node (-Input to AI) is zero, At that point the negative feedback through U I has stabilized the loop, and the current IIlI equals the input current plus the bias current. As a result no bias current flows in the source. Since D I and D2 are matched (I", = 11>2), liN is replicated at the output via D2. Thus, AI functions as a unity-gain current amplifier, and A2 is a current-to-voltage converter, as described below. Current produced by D2 must either flow into A2 or RF. Since A2 is designed for low bias current ("'" IDnA) almost all of the current flows through RF to the output. The output voltage then becomes; Vo = (11)2) RF = (l1lI ±Ios) RF "'" -(-lIN) RF = hNRF, (I) where, los is the difference between A I and A2 bias currents. For input voltage operation liN can be replaced by a voltage source (VIN) and series resistor (RIN) since the summing node of the op amp is essentially at ground. Thus, liN = VIN / RIN . Unipolar operation does have some constraints, however. In this mode the input current must be negative so as to produce a positive output voltage from A I to turn the LED on. A current more negative than 20nA is necessary to keep the LED turned on and the loop stabilized. When this condition is not met the output may be indeterminant. Many sensors generate unidirectional signals, e.g .• photoconductive and photodiode devices, as well as some applications of thermocouples. However, other applications do require bipolar operation. of the ISOIOO. 3-10 BIPOLAR OPERATION To activate the bipolar mode, reference currents as shown in Figure I, are attached to the input nodes of the op amps. The input stage stabilizes just as it did in unipolar operation. Assuming lIN = 0, the photodiode has to supply all the IREFI current. Again, due to symmetry, IDI = 1))2. Since the two references are matched, the current generated by 02 will equal IRE". This results in no current flow in RF, and the output voltage will be zero. When lIN either adds or substracts current from the input node, the current 01 will adjust to satisfy IIlI = bN + IREFI. Because IREFI equals IREF' and IIlI equals I"" a current equal to lIN will flow in Re. The output voltage is then Vo= IINRF. The range of allowable lIN is limited. Positive lIN can be asJarge as IREFI (1O.5/lA, min). At this point, 0 I supplies no current and the loop opens. Negative lIN can be as large as that generated by 01 with maximum LED output (recommended IO/lA, max). is the gain error. A, = I Ideal gain/ Actual gain I -I The output then becomes: VIN±VOSI Vm"r = Re [( -IREI' ±Ios) (I + A,) + IREF'] ±Voso RIN (2) The total input referred offset voltage of the ISOIOO can be simplified by assuming that A, = 0 and VIN = 0: ±VOSI VO(lT = RF [ --±Ios ±..lIREF ] ±Vo", (3) RIN where, ..lIREF = IREFI - IREF,. This voltage is then referred back to the input by dividing by RFI RIN. Letting ..lIREF - los = los h,po"", VoslRTlI = (±VOSI ) ±RIN(lOS h,pol") + Voso l (RFI RIN) (4) Example 1: (Refer to Figure 2 and Electrical Specifications Table) RIN = 100kO, RF = I MO (gain = 10), Given: VOSI = +200/lV. los h'pol" = +35nA, Voso = +200/lV Find: The total offset voltage error referred to the input and output when VIN = OV Vos total RTI = ±Vosl ±RIN (los h;pol,,), ±Voso (RFI RIN ) = +200/lV + 100kO (35nA) +200/l VI (I Mnj 100kn) = 0.2mV + 3.5mV + 0.02mV = 3.72mV DC ERRORS Errors in the ISO 100 take the form of offset currents and voltages plus their drifts with temperature. These are shown in Figure 2. Vos total RTO = Vo• total RTI x RF/RIN = 3.72mV x 10 = 37.2mV (Note: This error is dominated by los h;pol,,) 'USE 1Mil OR GREATER TO ACHIEVE A FUU SCALE OUTPUT OF lOV. FIGURE 2. Circuit Model for DC Errors in the ISOIOO. COMMO"!-MODE AND HIGH VOLTAGE ERRORS Figure 3 shows a model of the ISO 100 that can be used to analyze common-mode and high voltage behavior. AI and A2: are assumed to be ideal amplifiers. Voso and VClSI: are the input offset voltages of the output and input stage, respectively. VOS() appears directly at the output, but, VOSI appears at the output as VOSI "&' , RIN see equation (2). is the offset current. This is the currerit at los: the input necessary to make the output zero. It is equal to the combined effect of the difference between the bias currents of A I and A2 and the matching errors in the optical components, in the unipolar mode. IREI' and IREF,: are the reference currents that, when connected to the inputs, enable bipolar operation. The two currents are trimmed, in the bipolar mode, to minimize the los hlpolar error. II" and I",: are the currents generated by each photodiode in response to the light from the LED. r--ISOLATION BARRIER I : RF H I I I I T2.. VOUT I I I H INPUT COMMON FIGURE 3. High Voltage Error Model. 3-11 OUTPUT COMMON Definitions of CMR and IMR los is defined as the input current required to make the ISOIOO's output zero. CMRR and IMRR in the ISOIOO are expressed as conductances. CMRR defines the relationship between a change in the appJled commonmode voltage (VeM) and the change in los required to maintain the amplifier's output at zero: CMRR (I-mode) = ~Iosj~ VCM in nAjV (5) in pA/V Example 3: In Example 2, VIM is an AC signal at 60Hz and IMRR = 400pA VERR RTI = VERR CM + VERR 1M = O.3mV + 200V (400pA/V)(100kO) = 83mV VERR RTO =83mV (with AC IMRR) IMRR defines the relationship between a change in the applied isolation mode voltage (VIM) and the change in los required to maintain the amplifier's output at zero: ~~(:~ IMR = 20 LOG (0.5 x 1O-6VjV) = -126dB at DC V CMRR (V-mode) =[ ...llosJRIN ..lVERR cM inV / V (6) ..lVCM..lVCM . IMRR (I-mode) = CMR = 20 LOG (0.3mV/V) = -70dB at 6O,Hz IMRR in VjV= lMRR (I-mode)(RIN) = SpAjV (lOOk) == O.5p.V jV Example 4: (7) Given: (8) IMRR(V-mode)= [ ..llos ] RI~= ..lVERR'" inV/V Find: ..lV IM ..lVI" CMRR & IMRR in V jV are a function of RIN. VIM is the voltage between input common and output common. VcMis the common-mode voltage (nOise that IS present on both input lines, typically 60Hz). VERR is the equivalent error signal, applied in series with --the input voltage. which produces an output error identical to that produced by application of VCM and VIM. CM RR and 1M RR are the common-mode and isolationmode rejection ratios. respectively. Total error RTO from Examples,1 and 3as 120.2mV (with AC IMRR) Percent error of + IOV full scale output % Error = VERR total x 100 VI'S _ 120.2mV 100 IOV x = 1.2% NOISE ERRORS Noise errors in the unipolar mode are due pnmarily to the optical cavity. When the full 60kHz bandwidth is not needed. the output noise of the ISO 100 can be limited by either a capacitor. CI'. in the feedback loop or by a. low-pass filter following the output. This is shown in Figure 4. Noise in the bipolar mode is due primarily to the reference current sources. and can be reduced by the low-pass filters shown in Figure 5. TOTAL CAPACITANCE (CI and C,) is distributed along the isolation barrier. Most of the capacitance is coupled to low impedance or noncritical nodes and affects only the leakage current. Only a small capacitance (C2) couples to the input of the second stage, and contributes to IMRR. Example 2: Refer to Figure 3 and Electrical Specification Table) Given: Find: VCM = 'I'VAc peak at 60Hz. VIM = 200VDC, CMRR = 3nA/V.IMRR = SpA/V. RIN = 100kO.• RF = I MO (Gain = 10) ,o =-'2.RC The error voltage referred to the input and output when VIR = OV VERR RTI = (VcM)(CMRR)(R IN ) + (VIM) (lMRR)(R IN ) =IV (3nA/V)(I00kO)+ 200V (SpAj V)( 100kO) =0.3mV+0.lmV =O.4mV FIGURE 4. Two Circuit Techniques for Reducing Noise in the Unipolar Mode. lOOk!! IMIl VERI< RTO = VERR RTI (RFjRI~) = O.4mV (10) =4mV (with DC IMRR) (Note: This error is dominated by the CM R R term) For purposes of comparing CMRR and IMRR directly with dB specifications, the following calculations can be performed: CMRRinV/V=CMRR(I-mode)(R IN )=3nAjV(lOOk)=Q3mV/V FIGURE 5. Circuit Technique for Reducing Noise from The Current Sources in the, Bipolar-Mode. 3-12 OPTIONAL ADJUSTMENTS The offset voltage of the input and output amplifiers generally need no adjustment. However, VOSI and Voso can be adjusted independently using external potentiometers. An example is shown in Figure 15. Note that Vos" (500j.LV, max) appears directly at the output, but VOSI causes an error in the input current which is negligible for high source impedances. In general one pot, usually at the input is sufficient. Adjustment Proced ures: In the bipolar mode, remove I,~ and adjust the offset potentiometer for a zero output voltage. In the unipolar mode, set I,N to the lowest expected input current, for example 20nA, and adjust the offset potentiometer for an output voltage equal to I,~ x R,. FIGURE 9. Bipolar Inverting. BASIC CIRCUIT CONNECTIONS APPLICATION INFORMATION The small size, low offset and drift, wide bandwidth, ultra-low leakage, and low cost, make the ISO 100 ideal for a variety of isolation applications. The basic mode of operation of the ISO I 00 will be determined by the type of signal and application. Major points to consider when designing circuits with the ISOIOO. I. Input Common (pin 18) and -IN (pin (7) should be grounded through separate lines. The Input Common can carry a large DC current and may cause feedback to the signal input 2. Use shielded or twisted pair cable at the input, for long FIGURE 6. Unipolar Noninverting. lines. 3. Care should be taken to minimize external capacitance across the isolation barrier. or VOUT = VIN IRF/RINI FIGURE 7. Bipolar Noninverting. 4. The distance across the isolation barrier. between external components, and conductor patterns, should be maximized to reduce leakage and arcing. 5. Although not an absolute requirement, the use of conformally-coated printed circuit boards is recommended. 6. When in the unipolar mode, the reference currents (pins 8 and 16) must be terminated. 7. I"he noise contribution of the reference currents will cause the bipolar mode to be noisier than the unipolar mode. 8. The maximum output I,N and R F. VL swing is determined by VSW1:-,J(I:;;:: L'' 'mJ.X x RF 9. A capacitor (about 3pF) can be connected across R,. to compensate for peaking in the frequency response. The peaking is caused by the pole generated by R, and the capacitance at the input of the output amplifier. Figures 10 through 16 show applications of the ISOIOO. FIGURE 8. Unipolar Inverting. 3-13 L..----L-:--_ _ V·I---+--' COLD JUNCTION COMPENSATION NOT SHOWN ~ Rl AND ~ ARE REQUIRED TO MAINTAIN A3ri1A. MIN. LOAD TO THE 722 FIGURE 10. Two-Port Isolation Photodiode Amplifier (Unipolar). V+ E y. Rl AND R2 ARE REQUIRED TO MAINTAIN A3mA. MIN. LOAD TO THE 722 FIGURE II. Three-Port Isolation Thermocouple Amplifier (Bipolar). VOUT OUTPUT +1~5-V-(-11-·415-y----------------------------~COMMON (II FOR ISOLATED SUPPLIES SEE FIGURES 10 AND II. (21 IN THIS EXAMPLE THE INTERNAL PRECISION CURRENT REFERENCE. IREF PROVIDES BRIDGE EXCITATION. (31 PIN B OF THE INAIOI MUST BE MORE NEGATIVE THAN ·2mV FOR LINEAR OPERATION OF THE IS0100 WITH RI =1OOlu l. FIGURE 12. Precision Bridge Isolation Amplifier (Unipolar). 3-14 TOTAL GAIN =1000 OFFSET AOJ CALIBRATION PROCEDURE: 1. SET VIN = OV 2. ADJUST R2 FOR lOUT = 20mA 3. SET VIN =-5V .VISOLATEO 4. ADJUST RIN FOR lOUT = 4mA FOR ISOLATED SUPPLIES SEE FIGURES 10 AND 11 FIGURE 13. Isolated 4mA to 20mA Transmitter (Example of an isolated voltage controlled current source). GAIN AOJ OFFSETTING ·15V-"'IINJV-+15V lOOkn R4 GAIN = +IOto +1000 APPROXIMATE INPUT OFFSETTING = 0 to ±7.5"A FOR ISOlATED SUPPLIES SEE FIGURES 10 and II FIGURE 14. Isolated Test Equipment Amplifier (Unipolar with Offsetting). 3-15 VOUT t ~.: lOOk VIN2 Vo = IMC I: 10Ie • 'Uti" 'IN2] TO INPUT STAGES OF AMPLIFIERS 2 3 124 ISOLATED POWER SUPPLY "NO ADDITIONAL CONNECTIONS TO OUTPUT AMPLIFIERS NOTE THAT A VARIETY OF INPUT/GAIN CONFIGURATIONS CAN BE USED FIGURE 15. Four-Port Isolated Summing Amplifier (Unipolar). CHANNEL SELECT OPTO ISO· LATOR GAIN SELECT CP CE INPUT CHANNELS +15V ·15V ·15V OUTPUT _ COMMON ... "FOR ISOLATED POWER SUPPLIES SEE FIGURES 10 AND II. FIGURE 16. Multiple Channel Isolation Amplifier (Bipolar) with Programmable Gain (Useful in Data AcquiSition Systems). 3-16 100MS BURR-BROWN IElElI EMI SHIELD DESCRIPTION the output common. Figure 2 illustrates the assembly of the lOOMS. The lOOMS is an epoxy encapsulated electromagnetic electrostatic interference (EMI) shield for use with circuits where sensitivity to EM I is critical. It was designed to attenuate EM I by converting electromagnetic field energy into heat that is absorbed by the shield and by shunting electrostatic fields to common. The lOOMS may be used in applications to either confine or exclude EM I. Its cavity was designed for 28.45mm x 28.45mm x 7.24mm. 20-pin hybrid packages. The shields in the cover and base plate are in two separate halves to maintain the electrical isolation between the adjacent rows of pins of the module it encloses. Because of the spacing between the shield halves and the epoxy flow holes. the lOOMS provides a partial. but adequate low reluctance path for electromagnetic flux. The lOOMS is well suited for use with isolation modules such as the Burr-Brown 3656. 722. and 724. Epoxy Encapsulant BasePlateShield
.....----v'so ---~~I Connection to OutputCommon Connection to Input Common Visa = Isotation Voltage FIGURE I. Cross-Sectional Side View of lOOMS. Cover ASSEMBLY INSTRUCTIONS' Shield Solder Tab Assemble the base plate to the module by pushing the pins of the module through the beveled holes in the base plate until the base plate and bottom of the module are in contact with each other. Place the cover over the module so the tabs are aligned and fit into the slots in the base plate. Bend the four wide shield soldering tabs protruding from the cover to make contact with the bare metal on the base plate. Solder these four tabs to insure the integrity of their connection to the base plate. Module reference only' 'II ~~ The lOOMS and the module it contains are mounted and secured to a printed circuit board (PCB) by soldering the two narrow PCB solder' tabs to the appropriate common. The PCB solder tab closest to the input side of the module should be soldered to the input common. The other tab should be soldered to ~.. - ... , - - - Base Plate .. <~ ~ FIGURE 2. Assembly Diagram. Inlernalional Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 746·1111 . Twx: 911J.952·1111 . Cable: BBRCORp· Telex: 66·6491 PI)S-4~1 3-17 SPECIFICATIONS ELECTRICAL - Specifications apply between solder tabs. PARAMETER .. .CONDITIONS IsolatIon Voltage Rated Continuous. DC Rated Continuous. AC Test Capacitance Resistance Leakage Current lO MIN TYP MAX vac 3500 2000 8000 second~, UNITS V. rms vac 5 10 10 0.23 120V.60Hz pF Il "A MECHANICAL NOTE: 1. Enclosed module lead length minUS O.060~ to 0.80" 1.52mm to 2.03mm . 2. Pin diameter determined by enclosed module. Order Number: 100MS Weight: 17.5 grams INCHES DIM MAX A 1.320 1.380 33.53 35.05 B 1.320 1.380 33.53 35.05 C .350 .450 8.89 11.43 0 .040 .060 1.02 1.52 H .600 .700. 15.24 17.78 .025 0.38 0.64 1.280 29.97 32.51 .150 . 250 3.81 6.35 . .150 .250 3.81 6.35 R .015 .055 0.38 1.40 T .130 .230 3.30 5.84 S .060 .080 1.52 2.03. J .015, L 1.180 N P APPLICATIONS INFORMATION NULTIPLE DEVICE ORIENTATION 20kll 2Mll A typical application for the lOOMS is shown in Figure 3. Using multiple devices within 30mm of each other can cause them to interact by forming beat frequency interference outputs. The lOOMS can reduce this interference by as much asa factor of200: I depending on the distance between the devices and their relative orientation. Minimum EMI results when the gaps of both shields are paralleled as in Figure 3a. 20kll 2Mll Gap in Shield Gap in Shield r a, Optimum PCB Layout. b Isolated Data AcquIsition Input Circuitry. FlGliRE.1. Orientation lor Minimum EM!. 3-18 MILLIMETERS MAX MIN MIN 3450 3451 3452 3455 BURR - BROWN ® 1E3E31 Precision Linear ISOLATION AMPLIFIERS FEATURES • 2000V ISOLATION (3452) • 160dB ISOLATION-MODE REJECTION • DIFFERENTIAL INPUT • 0.005% GUARANTEED GAIN LINEARITY 13450) • l"V/oC INPUTVOLTAGE DRIFT (3450) • 20pA INPUT BIAS CURRENT (3452) • PRECISION WIRE-WOUND RESISTORS FOR LONG TERM STABILITY • LOW INTERFERENCE PICKUP-PW MODULATION DESCRIPTION The Models 3450, 3451 and 3452 are operational amplifiers with the unique feature of having the output completely isolated from the input. This is accomplished by a high accuracy modulation/demodulation stage which isolates the input from the output by IOI2n in parallel with 12 pF of coupling capacitance and provides gain linearity and stability far superior to that offered by ordinary isolation amplifiers. These devices differ from other isolation amplifiers in several respects. They are true differential input operational amplifiers where as other cominercially available isolation amplifiers are simple unity-gain isolators or are capable of a few fIXed gains. Thus they can be connected in all of the com- mon op amp feedback circuits such as summing, inverting, differentiating, etc. The 3452 differs from the 3450 and 3451 in that it h3s higher isolation voltage (2000 volts vs 500 volts) and has isolated t 15 Vdc power available at the input. The 3450 and 3451 differ from each other primarily in their input stage characteristics. The 3450 has a low drift (I MV/°C) bipolar transistor input stage while the 3451 has a low bias current (25 pA) FET transistor input stage_ The 3455 is identical to the 3452 except for additional isolation specifications more well suited for medical applications. International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 - Tel. (602) 746·1111 - Twx: 9111-952-1111· Cable: 88RCORP - Telex: 66-6491 PDS-30SG 3-19 SPECIFICATIONS Typical at 25°C and ±lS Vdc un ess otherwise noted r ELECTRICAL MODEL 3450 3451 94 88 I INPUT STAGE SPECIFICATIONS (1) Open loop Gain Input Offset Voltage vs. Temp. vs. Supply vs. Time (a' dB. Min. fS o C(4) mY. Max. IJV IOC Max. IJV IV jJ.V/mo Input Bias Current Cal 25°C vs Temp. vs. Supply Input Offset Current vs. Temp. vs. Supply (a) Max. Max. ±O.SS ±1.0 ±SO flO 1:20 ±SO nA ±O.S nA/oC -25 pA '. ±0.30 ±S.O ±2S ±IOO ±SO ±SO I .1. -20 pA Max. Input Impedance Differential ('ommon Mode (2) Input Noist' Voltage •. 0 I Hz . 10Hz "v. p.p 10 Hz . I kHz jJ.V rms Current, .01 Hz . 10 Hz pA. p.p 10 Hz - I kHz pA, rms Input Voltage Range Common Mode (2) (operating) V, Min. Differential (w/o damage) V, Min. Common Mode (2) Rejection dB @ 10V Isolated Power Available Voltage Current, Max. Ripple @ 100 kHz 5.1 mm (0.2") m --*-.I ·min. ~i T __ t2 pA doubles/10°C ±O.S pA/V . . 0.8 30 SO 100 80 90 - - tlSV ~~O% ±IOmA 1.2 4 2 0.3. 0.6 ±IO (0.7") f"" 58.4mm 41>1-40 til read 0.2" deep (2 holes) (2.30") -L ~ 2.54 .J mm tv{'" "'- ~ =1......~ • +' • 19.'lmm -.1........6--y:-r-- (\80") ::-I 1-' • ~ci~;';~ L-~. ~~m ---l -, tvP. 1-I , 2 3 0.3 0.6 I 1.01mm (0.040") (0.10")· IOlln 1011 nlllOpF 107n SXI0 9 nlllOpF I 117.8mm dis. ±I pA/V ±30 nA Max. ±0.3 RA/oe ±O.l n~/V '-------7:.:"7 ---ll~ r-- doubl~s/l O~C ±0.2 nA/V 25°C 94· MECHANICAL - • - : I( 7fO")45.7mm ±IS 100 mV p.p ISOLA.TION STAGE SPECIFICATIONS 1 V/V.tMiJ. .±O.I% ±O.S % vs. T e m p . . p p M / o C M a +10 ±SO Nonlinearity(7) @ HOV % Max/typ •. 005/.0.0015 to.02S/±.00S to.02S/±.00S MATERIAL - Black Plastic WEIGHT - 100g (3.5 oz) PINS - Pin material and plating composition meet method 2003 (solderability) of Mil·Std·883 [except paragraph 3.21 Mating Connector - 4!100MC. Gain (without trimming)(4) I Frequency Response,-3 dB(See Fig.9) 1.5 kHz 2.5 kHz (TOP VIEW) Settling Time ·to 0.01% to 0.1% S msec 1 msec DC 60Hz Output Offset Voltage ~ 2S0C(4) mV, Max. vs. Temp. ~. Supply vs. Time Input Power Requirements Voltage Current, quiescent • full load, max. e BAL 160 dB Min. ...120 dB Min. 0 e BAL e +IN ±SOO V Peak 1±2000VPk ±2000V Peak ±SOOOVpk(6) 0.2 n e -IN t:>- eljPCOM . +15 V. -15V • OFFSETe GAINe e FDBK ±IO V Min. ±s mA Min. O/PCOMe OUTPUTe 3450 . MODELS 3450 & 3451 t2 I ±lO~~~/oC Max! ±S PWRCOMe e liP COM ±SOO"V/V ±100I'V/Mo ±l4·to.±16 VDC + 30/-S rnA Max. +lS/-IOmA' j+SS/-IomA(8) TEMPERATURE RANGE Specification Storage Operating PWRCOMe e I/PCOM 1012n 1116»f 2.5J.1A max(~) Isolation Impedance(3) Isolation leaka.se Current at 240V 160Hz Isolation Model3 ) Rejection, G = 10 Isolation(3) Voltage Rated, continuous. (min.) Test voltage(S) Output Voltage Output Current Output Impedance, DC Output Noise .01 Hz to to Hz 10 Hz to I kHz PIN CONNECTIONS _25°C to +SSoC -SSoC.to ·;9S o C -lSoC to +'SSoC I 1 :~ALO e +IN +15Ve ~ e -IN GAINe e FDBK· e +V -15Ve V- OFFSETe OjPCOMe 3452 OUTPUT e MODEL 3452 & 3455 I) For 3450 and 345·1 current drawn from FDBK pin must be.so; 5mA. For 3452 the sUrD .of tbe currcnt drawn from FDBK pin and either "-V IBaI" or "+V" pinl (i.e.• + or. isolated current) musl be.s;; limA. 2) Common-mode parameters are measured althe +IN and ·IN pins with respect to the lIP COM pin. 3) Isolation mode parameters are measured at the lIP COM pin with respect to tbe PWR.COM pin and OIP COM pin. 4) Errors may be trimmed to zero. . 5) All units 100% tested for I p.A max leakqe current at. tes~ vohase. 6) The 3455 is identical to the 3452 except for two additional speciflClllioDl. Eacb unit i, tested to withstand a 2S00V rms, 60 Hz sinewave isolation voltage (Ref. Dielectric Witbl~and Vottaae, paragraph 31.11 of UL 544). Each unit is specified at a maximum leataae current of 2~A with 240V rms, 60 Hz isolation volt. (Ref, Leakqe Cumnt. p&rqrapb 21,5 of UL S44). , 7) Nonlinearity is specified to be the peak deYiation from a best ItraiJbUine expreued u a percent of peak-to-peak. Cull seale output. 8) Includes fully loaded input power, CIRCUIT DESCRIPTION The 3450,345 I and 3452 operate on the same principle, basically that of an operational amplifier followed by a high accuracy isolation stage (Figure la). The high accuracy of the isolation stage is achieved by use of a proprietary feedback technique in combination with high-stability components. Isolated DC power for the input amplifier is provided by an internal DC-DC converter which derives its power from the external + I 5 Vdc supply. Although a DC-DC converter and modulation techniques are used, the output noise is typically less than I mV (peak) as a result of careful design, internal filtering, and a shielded package. The frequency of this noise is approximately 100 kHz which makes it insignificant for many applications. Pulse width modulation minimizes pickup from adjacent units. The symbol shown in Figure ,I b is used to represent the complete isolated operational amplifier. The OIP COM pin must be connected to the PWR COM pin. Figure lOa shows the power supply connections and the optional offset and gain trims. , C-' ,'.... I1 , I o-1==-::!._ _ _ - V/Sal (I) -15V' (a) Simplified Block Diagram +15V ,PWR COM on 3452 only FIGURE 1. Block Diagram and Symbol APPLICATIONS The isolation amplifiers may'be used in the same manner as any operational amplifier except that the feedback signal is taken from the FDBK pin rather than from the output pin. No connection is required or would normally be made from input common (lIP COM) to either the power common (PWR COM) or output signal ground pins. Some typical circuit applications are shown in the following. For signal sources of millivolt levels and low internal impedance, the 3450 will usually be the best choice. Signal sources of this type include thermocouples, thermistors, etc. The 3451 will generally be the best choice for signal sources having large values of internal impedance. The pH cell is an example of this type of signal source. INVERTING CIRCUITS NONINVERTING CIRCUITS The isolation amplifiers can be used for a variety of inverting circuit applica,tions. Figure 3 illustrates the proper circuit connections for summing a number of signals which are all at the same common mode level. An. example of the use of such an amplifier is the computation of a weighted average of several temperature inputs. One of the most useful applications of these amplifiers is impedance buffering and pre-amplification of low-level signals. Such signals may be "riding" on several hundred volts of common mode potential or they may simply have a significant amount of common mode noise (power line "pickup," etc). Figure 2 illustrates the correct signal and feedback connections for such noninverting circuits. Source Ground FIGURE 2. Noninverting Amplifier Circuit. *See note (1) under Electrical FIGURE 3_ Summing Amplifier (or Weighted Averager). S~ecifications. 3-21 DIFFERENTIAL INPUT CIRCUIT CURRENT AMPLIFIER The isolated operational amplifier can be operated in a fully differential mode as shown in Figure 4. The input impedance of the differential amplifier circuit is 2R I and may cause undesirable loading of the signal source unless R I is much greater than the impedance of the signal sources. As with nonisolated operational amplifiers, the isolation amplifiers can be used to convert current source or convert current signals to output voltage. However, with these amplifiers the input signal may have a large voltage associated with it which can be completely isolated from output ground. The circuit of Figure 5 illustrates this technique. Ground FIGURE 5. Isolated Current Source Amplifier. FIGURE 4. Isolated Differential Amplifier. BRIDGE AMPLIFIER The circuit in Figure 6 illustrates a method of amplifying a signal from a balanced bridge which cannot be conveniently used with a nonisolated amplifier. The circuit shown provides a high input impedance so that the bridge is not loaded. The common mode rejection of the bridge excitation voltage is not degraded by the external gain setting resistors as it would be with a difference amplifier. The gain can be changed conveniently by adjusting a single resistor (R2)' Also, the whole bridge circuit may be floated with respect to the output by a voltage equal to the isolation mode voltage specification without creating troublesome ground loop current. eo *Bridge exitation can be supplied by 3452 FIGURE 6. Bridge Circuit with Floating Input. ISOLATION AMPLlFII.:RS USED IN MEDICAL APPLICATIONS When isolation amplifiers are used in patient monitoring medical application the considerations of I) patient safety and 2) protection of the amplifier against defibrillator voltages require the use of additional circuitry. The input resistors must be kept large in order to limit the leakage current in the event of a component failure in the input stage of the amplifier. The 1.2meg. ohm resistors will limit the current to 12.5J.LA (Figure 7). The amplifier must be protected in two areas against possible damage from defibrillator over voltages. Diodes Dl through D4 protect the input stage from excessive voltages and currents. The gas fJ.!16d surge voltage protection (SVP in Figure 7) will protect the isolation barrier of the amplifier from breakdown. A Siemens part number B2-B470 will limit the voltage across the isolation barrier to 470V and has high isolation resistance and low leakage capacitance characteristics. 1k ~ Offset on ~+V i ~ >-+1,-----,;.---1 (1.\3~+,.52 >t ~]I _1"'.2....M...,,::-r.:-+r_ ~~{ ::' Hum Null Pot 20k 1.2M 01 02 05 06 Common J - 0 ~IN( - : 3455 r"'" ,L jIN\,..r""" D3 04 20k L _. I/PCOM on r ~~I~O~k~~-+----~--------~-V~/~BAL 2W / COM I _ J I O/PCOM ~--, SVP l/:"\ Shield Gain I I ~--- < ·em Ideal AmPlifier FDBK EQUIVALENT CIRCUIT (B) (A) ecm ) ( eS + CMRR CMR = 20 10gi0 CMRR IMR = 20 10gIO IMRR FIGURE 8. Common Mode and Isolation Mode Voltage Errors. 3-23 R2 + el so Rl IMRR 100 80 r\-- ~ \ 60 40 ~ \ 20 0° 0 ~ I/Gain ~ ~ 10 100 Ik ...... -20 _ 45° -.... 10k Gain ""l t\. ~ """"P~ase "\. \. ~ ~ ~ ~ iii' Phasr/ o .... ~ -40 ~ lOOk ~ -60 I~ Ik 1M 4k (Hz) 2k (Hz) al Open Loop Frequency Response of Input Amplifier ' , "- (Delay "v I OOl'sec) _90° 10k --- ~, ., 20k b) Frequency Response of Output Stage FIGURE 9. Frequency Response of Input and Output Stages. INSTALLATION and OPERATING INSTRUCTIONS MOUNTING POWER SUPPL Y REQUI REMENTS The isolation amplifiers are plastic cased modules suitable for ~dering directly on toa printed circuit board. Alternatively they may be plugged into the 4400 MC mating connector which may be mounted. on a panel or chassis. The isolation amplifiers have no unusual power supply requirements. A standard low-cost power supply such as the Burr-Brown 551 is recommended. The necessary isolated power for the input stage of the amplifier is derived internally by a DC-DC Converter operating from the externally applied +15VDC power. CALIBRATION ADJUSTMENTS ISOLATION STAGE OFFSET VOLTAGE NULL Gain of the isolation amplifiers is determined primarily by the operational amplifier input stage. This allows a wide range of possible gains with the accuracy determined primarily by the feedback networks and the open loop gain of the operational amplifiers. RF;;;' 10k is recommended for best linearity. The gain of the isolation stage is nominally unity but may be trimmed over a limited range to allow easy ,calibration. Set input signal to zero.< connect +IN to lIP Com) connect lIP Com to OIP Com and measure the voltage between the FDBK and OUTPUT pins with a floating DVM. Null this voltage by adjusting R4., Remove the connection between I/P Com and OIP Com. INPUT STAGE OFFSET VOLTAGE NULL With the input signal set to zero, adjust R5 such that the voltage between the FDBK arid lIP Com pins is zero. (This Offset voltages of both input and output stages are adjustable by use of external components. is best done at a high gain value i.e. , ~ ~ 1000). RG OVERALL GAIN ACCURACY Figure 10 illustrates a typical amplifier circuit where gain and offset voltages are adjusted. Proper calibration procedure for this circuit would normally be as follows: With RF and Rc at the proper values to produce the de- sired gain G = RG' + RF, apply a known calibration voltage Rc VR as the input signal. Adjust R3 for the desired output Vo=VRxG. 3-24 If it is unnecessary to adjust offset voltage of the output stage, R I and R4 may be omitted. If no adjustment of input stage offset voltage is desired, omit R5 and R6' If the specified gain accuracy (see spec table) is adequate without further adjustment, both R2 and R3 may be omitted. The OUTPUT pin must then be connected to the GAIN pin for an output stage gain of unity. Omit R7 if R I through R4 omitted. R ,lOOk Feedback Network ~ Ar 4 utput Offset Adj. .15V FDBK For all applications other than unity gain noninverting, R2 is unnecessary and only R3 is needed to trim the gain. However, it is then necessary to set the first stage gain slightly below the desired overall value and then use R3 for the gain calibration. For· fixed gain applications it may be unnecessary to null offset voltage for both input and output stages. The offset voltage of the output stage, for instance, may be used to compensate for the input stage offset, thus giving an overall null. However, if gain is to be varied over a wide range it will usually be necessary to null both offset voltages. Appropriate safety precautions should be taken when adjusting input stage offset voltage or gain. These points will be "floating" at the isolation mode voltage and appropriate precautions must be taken if this is a high voltage. In particular, any adjustment potentiometers used for input stage adjustment should have insulated shafts with voltage ratings in excess of any expected common mode potential. The outplit stage can be adapted to drive capacitive load of up to 10,000 pF without sacrificing DC gain accuracy. Add RS = loon as shown in Figure lOb; otherwise, Rs =on. Note: All external adjustments are optional. • This terminal labeled "-V /BaI" on Model 3452 FIGURE lOa. External Connections for 3450, 3451 and 3452 lOOk lOOk .....~N'Ir-....--'N~---U GAIN Demod Source >-....-<.J OUTPUT FIGURE lOb. WIRING SHIELDING and ISOLATION MODE REJECTION The capacitive coupling from input common (lIP COM) to output common (OIP COM) for the isolation amplifiers is extremely low. This is an essential element in achieving the isolation mode rejection specifications. Therefore it is essential that care be used in wiring and printed circuit card layout to minimize stray capacitance between input and output circuits. Proper shielding of input leads is also essential in preserving isolation mode rejection. When shielded cable is used the shield should be connected to the common mode potential at the signal-source. Isolation mode rejection at high frequencies will be degraded by resistance in series between the signal source and the lIP COM pin (e.g. wire resistance). Figurel! illustrates the mechanism by which such degradation occurs. The isolation mode voltage "divides" across Rw and Cc creating an isolation mode error voltage ~eIso which appears as an unwanted differential input voltage adding to es. Note that this error occurs even if RN and Rw are equal because the stray capacitance Cc exists only from the lIP COM pin to OIP COM. If this degradation of the isolation mode rejection becomes significant (for Rw = I kn and f =60 Hz, the CMR is still in excess of 97 dB) a capacitance from the +IN pin to alP COM will compensate the effect. A capacitor used in this manner must withstand whatever isolation mode potential exists. 3-25 FIGURE II. Degradation of Isolation Mode Rejection due to Wiring Impedance and Coupling Capacitance. 3456 BURR-BROWN@ 1E3E31 ISOLATED INSTRUMENTATION AMPLIFIER FEATURES • TRUE 3-WIRE INSTRUMENTATION AMPLIFIER INPUT • TRUE INSTRUMENTATION GRADE ISOLATION AMPLIFIER • lpV/"C INPUT VOLTAGE DRIFT • ADJUSTABLE GAIN. 1 to 1ID1 • LOW NONLINEARITY. 0.02% max • ISOLATION VOLTAGE. 2000V PEAK RATED CONTINUOUS • 160dB ISOLATlON·MODE REJECTION • ±2DmA. VOLTAGE OR CURRENT PROGRAMMABLE OUTPUT • 2.5kHz. FREQUENCY RESPONSE • LOW INTERFERENCE PICKUp·PW. MODULATION • FULLY SELF-CONTAINED APPLICATIONS • ISOLATED THERMOCOUPLE & RTD SENSING • INDUSTRIAL PROCESS CONTROL • TEST EQUIPMENT AND INSTRUMENTS • HIGH VOLTAGE INSTRUMENTATION AMPLIFIER • CURRENT SHUNT MEASUREMENTS •. GROUND·LOOP ELIMINATION • BIOMEDICAL PATIENT MONITORING International Alrporllndustrial Pirit . P.O. Box tt400 • TUClon. Arizona 85734 . Tel. (6021 746-1111 . Twx: 91(1.852·1111 • Cabla: BBRCORP • Tellx: 66-6491 PDS·377 3-26 DESCRIPTION The Models 3456A and 34568 are high performance instrumentation amplifiers which have their outputs completely isolated from the input. The front end of the unit is a high performance, DC differential-input instrumentation amplifier stage, designed for data acquisition and instrumentation use. The low drift, low noise and high CMR make it possible to accurately amplify microvolt-level signals with gains of up to 1000. The input stage is followed by a high accuracy unity gain, pulse width modulation/ demodulation isolation stage. This isolation stage isolates its input from the output by 10 12 011 14 pF impedance. The 3456A and 34568 differ from other isolation amplifiers in several respects. They are true instrumentation amplifiers as opposed to differential input op amps or fixed gain isolators. They offer both, the single resistor programmable gain range as well as the true 3 wire instrumentation amplifier input. THEORY OF OPERATION Figure I shows block diagram of 3456. The true 3 wire instrumentation amplifier input section shown needs only one resistor to set the required gain level. It has high input impedance, high CMR and low bias current and allows the use of inverting, non-inverting and differential input configurations. The input offset adjustment shown is optional. Isolated DC power for the input stage is provided by an internal DC / DC converter which derives its power from the external +15 VDC supply. The isolated power is also made available (on +V and -v pins) for external use. The modulation/ demodulation stage isolates the input from the output by 10 12 0 in parallel with 14 pF of coupling capacitance. Pulse width modulation technique is used to minimize pickup from adjacent units. This technique combined with the use of wirewound and laser trimmed thin-film resistors provides high overall accuracy and excellent drift characteristics. --- -----l Output Isolation Stage Input Stage SENSE 12.Sk I - CaMP GAIN ...()---1---4---1 -IN ...JL I " I I -" Pulse Width Modulator R ~ ",moo."ro, ~~ I OUT I I I 101PCOM i I I I +IN I +V liP COM ~. +-________ __ ~~ __-+__ +-~ 0---.1.-----+----------1-11-----4----l Rectifier -V [ - +ISV Oscillator 1.":: PWR I I I I ..J BAL I ~ BAL I '- SOk _~ I __ ____ J 2Skf! G~l+­ R FIGURE I. 3456 BLOCK DIAGRAM 3-27 G = Gain R = Gain Setting Resistor COM -ISV SPECIFICATIONS Typical at 25°C and ± ISVDC supply voltage unless otherwise noted. ELECTRICAL MECHANICAL 345M MODEL GAIN I (BOTTOM VIEW) 34568 .15V. -15V • ISOLATED INSTRUMENTATION SENSE AMPLIFIER CaMP • • O/P COM. 3456A OUT • POWER SUPPLY Voltage Current, Quiescent Full Load(SJ ±14 to ±16VDC +4O/-8mA, max +8S/-30mA, max NOTES: I. The ±IOV input range is subject to the limitation that I Vcc>mmon model +1 Gain x Vdiff /21 ~ IOV. 2. Both the components (input and output) of the offset voltage may be trimmed to zero. 3. Isolation mode parameters are measured aUhe liP COM pin with respect to the PWR COM pin. 4. All units are 100%. tested for 2S",A maximum leakage at test voltage. 5. Includes full isolated power supply. TEMPERATURE RANGE Specification Operating Storage -2S'C to +85'C -25'C to +8S'C -S5"C to +95"C 3-28 VOLTAGE OUTPUT CONFIGURATION The 3456, when connected a5 shown in Figure 2, will provide output signal capable of driving up to ±20mA load. Refer to the block diagram shown in Figure 2. Notice that the demodulated signal is referenced to the alP COM pin. The alP COM pin is connected to the output ground (PWR COM) for voltage output configuration as is shown iii Figure 2. So with this configuration, the demodulated voltage signal is fully applied across the load impedance ZL. If roll-off at a lower frequency (lower than 2.5kHz) is desired, an optional compensation capacitor Ce may be connected as shown between the CO MP pin and the OUT pin. See Figure 4 for the selection ofCe. The output offset controls shown in Figure 2 and Figure 3 are optional. They provide approximately ±15mV offset control at the output. The SENSE and CaMP pins are subject to electrostatic noise pick-up via stray capacitance. To minimize this noise pick-up these pins and connected circuits should be shielded. If these controls are not used, we recommend the unused pins be cut off flush to the 3456 surface. This would help minimize the degradation of Isolation Mode Rejection. Optional Offset Control 15V SENSE IOOMn ~ , 10000F 1000F lOpF 0.1 10 100 1000 H, FIGURE 4. -3dB Frequency Vs Ce (Voltage Output). ALTERNATE GAIN ADJUSTMENT The gain adjustments are normally made by varying the gain setting resistor at the input. Since voltages at high potential may be present at the input side of the isolation barrier, some applications may require that gain adjustments or gain trimming be done at the output side of the isolation amplifier. For the voltage output configuration, such gain trimming can be done at the output. Figure 5 shows a recommended gain adjustment method. This method would provide a ±l% gain trim at the output. 9+ .------l-o--~·fIOOkn COMP - -- .., 6-15V IOMn "'<- *CC OUT ~ 25kn ;; RL O/PCOM soon FIGURE 5. Alternate Gain Adjustment Method For Voltage Output Configuration. 3456 CURRENT OUTPUT CONFIGURATION FIGURE 2. Voltage Output Configuration With Simplified Block Diagram. 1 +15V SENSE IOOkn IOOkn - ~-'" --"NY3456 !JOon IOkn -15V FIGURE 3. Alternate alP Offset Control For Voltage Output Configuration. Current output configuration is a.configuration which gives an output current proportional to the- input signal. The 3456 should be connected as shown in Figure 6 for current output configuration. In this configuration, the alP COM pin is not connected to the output ground (PWR CO M). The a I P CO M pin is connected to RL. The demodulated signal (voltage between the OUT pin and alP COM pin) is thus applied across Rs. With a given demodulated signal and known feedback for the output amplifier, the voltage across Rs can be calculated. With known value of this voltage, the value of Rs can be fixed to give the desired output current to the load resistor RL. The output current is thus programmed by Rs. It does not change with changes in the load resistor RL. The feedback resistor RF paralleled with the internal I OOkfl resistor (see Figure 6) helps achieve the required voltage rescaling at the output (the OUT pin). 3-29 the demodulated signal reference frpnt output ground to .the voltage developed across RL. Hence, as discussed earlier, consistent with the requirements of desired application, it is best to keep the RL to as minimum a value as is possible. Figure 7 shows the maximum additional peak nonlinearity errors in the current .output configuration .expressed as a percent of full scale peak to peak output (40mA) vs RL/Rs. The values of Rs and Rp as calculated above, would program the unit for the desired full scale output current 10 when the gain of 3456 is scaled for ±IOV full scale ouptut. With these values of Rs and Rp the. unit would comply with the performance curves shown in Figures 7, 8 and 9. Deviation from this .selection procedure could result in degraded performance. Due to the output amplifier bias· currents and the demodulator currents, we recommend that the full scale output current value be ±I mA or higher (up to ±20mA). FIGURE 6. Current Output Configuration With Simplified Block Diagram PROGRAMMING FOR CURRENT OUTPUT The selection criteria discussed below is,based on 3456 being gain programmed for ±IOV full scale signal at the OUT pin (the signal as referenced to the PWR CO M pin). With ±IOV full scale signal, best overall accuracy is achieved. RL is defined as the maximum load impedance in ohms and 10 as the maximum peak output current in amperes. The common-mode voltage (an error producing term) is directly proportional to RL. So, it is desirable to keep RL to as minimum a value as is consistent with desired application's requirements. Determine first the valu~ of 10 and RL suitable for the desired application. The v~lues of Rs and Rp in ohms can be obtained by the expressions, IO-IoRL Rs= - - - - - I I V 0.00 I V 0.1 10 100 FIGURE.7. Maximum ActditionalPeak Nonlinearity Errors in Current Output Configuration Expressed as Percent of p-p Output Current Vs RL/Rs. and Rp / I =-----IOS-IoRs. I04 +Rs 10 Ce, expressed in pF, can be calculated by the expression 220. lOS Ce I where Rp is in ohms. The above calculated value of Ce would maintain the -3dB frequency response at 2.5kHz. Roll-off at a frequency lower than 2.5kHz can be achieved by increasing the value of Ce. The maximum allowable voltage across Rs + RL to maintain the specified accuracy, also known as "compliance" is limited to ±IOV·by the output swing capability of the output amplifier. The current output configuration contains all error elements of the voltage output .configuration plus additional common-mode errors introduced by raising 3-30 " > e o. I 0.0 I 0.1 10 100 FIGtJRE 8. Typical Additional Offset in Current Output Configuration Vs RL/Rs. configuration. Gain nonlinearity would not exceed the voltage output specification by more than the value indicated in Figure 7. Current output offset and temperature drift are specified as a voltage quantity appearing across Rs. These parameters each contain two terms. The first term is the total offset voltage RTI (referred to input) specification for voltage output mode multiplied by the input gain u o >-"./ setting, multiplied by ~ . The second term is the Rs + RL .1 value found from Figure 8 for the offset-voltage and from Figure 9 for the offset voltage drift. Adding these two terms would give the offset voltage and the offset voltage drift values appearing across the scaling resistor Rs. To obtain these parameters in terms of the offset current and the offset current drift, they have to be divided by Rs. In short, 0.1 0 FIGURE 9. Typical Additional Temperature Drift in Current Output Configuration Vs RL/Rs. Value from ( vOlta.geO~tPut MOde) (Input) (~)+( + Fig. Fig. SPECIFICATIONS FOR CURRENT OUTPUT When the above discussed current output configuration procedure is followed for selection ofR F , Rs, Cc and RL, the following performance standards would be met by the configuration. Gain accuracy would be maintained within a maximum of 0.1 % above that specified for voltage output SpecIfication Gam = (current ~utPU.1 Rs RL 8 or ) 9 MOde) Specification To obtain the offset or drift in units of current, divide the above equation by Rs. 3-31 3650 3652 BURR-BROWN® 113131 Optically-Coupled Linear ISOLATION AMPLIFIERS FEATURES APPLICATIONS • BALANCED INPUT • INDUSTRIAL PROCESS CONTROL • LARGE COMMON-MODE VOLTAGES ±2000V Continuous 140dB Rejection • INTERFACE ELEMENT • DATA ACQUISITIDN • BIOMEDICAL MEASUREMENTS • ULTRA LOW LEAKAGE 0.25J.LA max at 240V/60Hz 1.8pF Leakage Capacitance • PATIENT MONITORING • TEST EQUIPMENT • EXCELLENT GAIN ACCURACY 0.05% Linearity 0.05%/10ODHours Stability • CURRENT SHUNT MEASUREMENT • GROUND-LOOP ELIMINATION • WIDE BANDWIDTH 15kHz ±3dB 1.2VI J.Lsec Slew Rale • SCR CONTROLS DESCRIPTION The 3650 and 3652 are optically coupled integrated circuit isolation amplifiers. Prior to their introduction commercially available isolation amplifiers had been modular or rack mounted devices using transformer coupled modulation, demodulation techniques. Compared to these earlier isolation amplifiers the 3650 and 3652 have the advantage of smaller size. lower cost. wider bandwidth and integrated circuit reliability. Also. because they use a DC analog modulation technique as opposed to a carrier type technique. they avoid the problems of electromagnetic interference (both transmitted and received) that most of the modular isolation amplifiers exhibit. '--~ Light A2 -~--{1~>-+--' ~ 9 I Flu. A4 2 CDupling --z- 1.6Mn I---- 3652001,----4 1 - - - - - CommDII III 3650 113652 ·1 101llrnatlonll Airport Industrlll Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 746-1111 . Twx: 910-952·1111· Cable: 88RCORp· Telex: 66-64111 © 1976 Burr-Brown Research Corporation PDS·J42D 3-32 SPECIFICATIONS ELECTRICAL Typical at 25°C and ±15VDC supply voltages unless otherwise noted. Isolation Voltage Rated Continuous, (min) Test Voltage, (min! 10sec duration 2000Vp or VDC SOOOVp Isolation-Mode Rejection, G = 10 DC 60Hz, 5000n source unbalance Leakage Current, 240V/60Hz Isolation Impedance Capacitance Resistance 140dB 120dB 0.2S~A, max I.BpF 10'2n G, Resistance, RIN. max Buffer Output Impedance, Ro Gain Equation Error, max(3) Gain Nonlinearity Gain vs Temperature Gain vsTime 1.5% ±O.OS% typo ±0.2% max 300ppmfOC I ~ G, I06VoIVAmp I Not applicable O.S% O.S% ±0.03% typo ±O.I% max ±0.02% typo ±O.OS% 100ppm/'C 50ppm/'C ±O.OS%/l000hrs. Frequency Response Slew Rate ±3dB Frequency Settling Time to ±0.01% to±O.I% 0.7V/~sec ~ 1.00S7 x 106 VoIVAmpl21 I gon ±30n I.S%l4) 0.S%(4) ±O.OS% typo ±0.2% max ±O.OS% typo ±0.1 % max 300ppm/'C(4) 200ppm/'C(4) ±0.05%/l000hrs. min, 1.2V/~sec typo ISkHz 400~sec 200~sec Input Offset Voltage ±lmV ±SmV ±10~VfOC ±SO~VfOC at 25°C, max(3) vs Temperature. max vs Supply vs Time , Input Bias Current at 2SoC vs Temperature vs Supply 100~VN SO~V/l000 hrs. Input Impedance Differential Common-mode Input Noise Voltage, O.OSHz to 100Hz . 10Hz to 10kHz 100.Vll000 hrs. 10nA typ, 40nA max 0.3nA/'C 0.2nAN 10pA typ, SOpA max doubles every +100C lpAN effects included in output offset 10pA doubles every 100 C . 1pAN Input Offset Current vs Temperature vs Supply ±2mV ±2S~VfOC 100~VN "RIN" 25!! max 109!! ~ 10"!! 10"!! B~V, p-p 4p.V, rms 4~, p-p 5p.V, rms ±iI vl-slV Input Voltage Range Common-mode, lin~ar operation, w/o damage, at +,at +1,-1 at+IR, -IR ±V Not applicable Not applicable ±II VI-S) ±V ±300V for 10msec(6) ±3000V for 10msee(6) Differential, w/o damage, at +,Differential, w/o damage, at +1, -I Differential. w/o damage, at +IR, -IR ±V Not applicable Not applicable ±V ±600V for 10msee(6) ±6.000V for 10msee(6) ±BV to±IBV . ±BV to±IBV ±1.2mA(7) +6.SmA or -6.SmA, typ +12mA or -12mA, max ±3mA(7) +B.. SmA or -B.SmA, typ +16mAor-16mA, max Power Supply Iinput Stage OnlYI Voltage lat "+V" and "-V", Current ' Quiescent with ±10V outpull7) 3-33 ELECTRICAL (cont) I MODEL 3650MG/HG(1) I I 3650JG 3650KG I I 3652MG/HGI 11 3652JG OUTPUT STAGE Output Voltage, min Output Current, min Output Offset Voltage ±10V ±5mA at 25°C max(3) ±25mV ±900MV/oC vs Temperature, max vs Supply vs Time I ±10V ±5mA ±10mV ±450MVPC ±500MVN ±1mV/1000hrs Output Noise Voltage 0.05Hz to 100Hz 10Hzto 1kHz I ±10mV ±300MV/oC ±10mV ±450MV/oC ±500MVN ±1mV/1000hrs 50MV, p-p 65p.V, rms Power Supply (Output Stage OnlYI Voltage f"+Vcc" and "-Vee" I Current Quiescent with ±SmA output, max I ±25mV ±900MV/oC 50MV, p-p 65,uV, rms ±SV to ±1SV ±2.3mA typ, ±6mA max ±11mA TEMPERATUREIS) DoC to 85°C Specification Operating Storage -40°C to +100oC -55°C to +125°C 1. All electrical and mechanical specifications of the 3650MG and 3652MG are identical to the 3650HG and 3652HG. respectively, except that the following specifications apply to the 3650MG and 3652MG: (8 1150lation test voltage duration increased from 10sec minimum to SOsec minimum; I bl Input Offset voltage at 25°C max: ±10mV; vs. temp. max: ±100~VloC; IC) Output offset voltage at 25°C max: ±50mV; vs temp. max: ±1.BmV/oC. 2. If used as 3650, see Installation and Operating Instructions. 3. Trimmable to zero. 4. Gain error terms specified for inputs applied through buffer amplifiers I i.e .. ±I or ±IR pins). 5. Input stage specifications at +1 and -I inputs for 3652 unless otherwise noted. 6. Continuous rating is 1/3 pulse rating. 7. Load current is drawn from one supply lead at a time other supply current at quiescent level. for 3652 add 0.2mA/V of pos CMV. B. dT/dt > 1°C/minute below COC, and longwterm storage above 100°C is not recommended. Also limit the repeated thermal cycles to be within the OOC to 85°C temperature range. PIN CONNECTIONS MECHANICAL , . - - - - - - - r < ' "+" denotes missing fl3~++ 0++ 0++ 0++ o++~ I L+ B I I R ~ ~ A t N f I,------, JI~Hli K II GJ~ INCHES DIM A MILUMETERS MIN MAX MIN MAX 1.760 43.18 44.70 1.160 .230 4.32 .018 .021 .035 .050 .100 BASIC .110 .130 .160 .250 .900 BASIC .002 .110 .010 .130 29.46 0.46 ORDER NUMBER: 3650MG 3652MG 3650HG 3652HG 3650JG 3652JG 3650KG 0.53 0.89 2.54 BASIC 3.30 2.79 3.81 6.35 22.86 BASIC 0.05 2.79 Leads in true position within 0.010" 10.25mmlRatMMCat seating plane. JLF 1.700 1.120 .170 for reference only Numbers may not be marked on package. NOTE: :+00+0+000 •• 00.: C pins. Pin numbers shown 0.25 3.30 MATERIAL: A)umina (ceramic) WEIGHT: 14 grams 10.50ZI MATING CONNECTOR: 2302MC (set of two, 16wpin strips) 3-34 TYPICAL PERFORMANCE CURVES Typical at 25°C and ±15VDC power supplies unless otherwise noted. INPUT STAGE SUPPLY CURRENT VS. OUTPUT VOLTAGE 1.5 12r-~ro--'--'~r-, « :Eos 1.4 ~ J " C' ~ § 1.3 e o ~ 1.2 " U >Ci. g- ~ --'3mA- (/) _____ 1__ _ J 1.1 a: o ~ O~. .~~~~~r_~ 3 e ~ 1 I---t----if---f-----j is 0.3:f----7l'-------1~__+-___l ~-2~---=~--~~,~~ e ~ -41-----I-----+-~~ 10 Frequency r kHz I Frequency (kHz I 3650 COMMON-MODE AND ISOLATION-MODE REJECTION VS. GAIN (P -12O~ IO). Use the following procedure if it is desired to null both input and output components (for example. if the gain of the amplifier is to be switched). The input stage offset is first nulled (50k!! adjustment) with the appropriate input signal pins connected to input common and the amplifier set at its maximum gain. The gain is then set to its 3-37 VOUT =PI • IV x IrPv/A + VISO x IMRR" FIGURE 6a. 3650 With Differential Current Sources. A, and A" the input and output stage amplifiers, are considered to ,be ideal. Separate external generators are used to model the offset voltages and bias currents. Ri, is assumed to be small relative to R(;, and R,;, and is therefore omitted from the gain equation. The feedback configuration, optics and component matching are such that I, = I, = h = I,. A simple circuit analysis gives the following expression for the total output error voltage due to offset voltages and bias currents. 10" (I) V"",_,,,,,, = R (il + R(i::! [E"" + (I", R,;, -I", R,;,y+ !J E",,, Offset current is defined as the difference between the two bias currents I", and I",. If I", = I" and I", = I" + I"" 10"·1", then, for Ru, = R,;,. V,w, -I" = -2This component of error is not a function of gain and is therefore included as a part of E",,, specifications. The output errors due to the output stage bias current are also included in E",,,.This results in a very simple equation for the total error: - = IO"E"" f Rtil -- R(i:!. ) 2R o ] + E,1~O (or (2) Vt)ut-lotaJ FIGURE 6b. 3650 With Differential Voltage Source. In summary it should be noted that equation (2) should be used only when R(;, = Rm. When R'd "# Ru,. equation ( I) applies. The effects of temperature may be analyzed by replacing the offset terms with their corresponding temperature gradient terms: V1HlI-t:::. VllU!1 ~ T. Eo~i --~E\,~" 6. T. etc. For a complete analysis of the effects of temperature, gain variations must also be considered. FIGURE 6c. 3652 with Differential Volta/1;e Source. ·1 M RR here is in pAl V. typically SpAt V at 60Hz and I pAl V at DC. ··The offset adjustment circuitry and power supply connections ~ve been omitted for simplicity. Refer to Figure 5 for details. ERROR ANALYSIS A model of the 3650 &uitable for DC error analysis of offset voltage, voltage drift versus temperature, bias current, etc., is shown in Figure 7. OUTPUT NOISE The total output noise is given by E" (RMS) = vicE" G)' + (E,,,j where E, (RMS) = total output noise Eo, = RMS noise of the input stage Eo" = RMS noise of the output stage G = 10", (R,;, + R,d E,,, includes the noise contribution due to the optics and the noise currents of the output stage. Errors created by the noise current of the input- stage are insignificant compared to other noise sources and are therefore omitted. COMMON-MODE and ISOLATION-MODE REJECTION The expression for the output error due to commonmode and isolation mode voltage is: FIGURE 7. DC' Error Analysis Model for 3650. GUARDING & PROTECTION I..... OC/DtCtnvtrtIr. .....17Z! To preserve the excellent inherent isolation characteristics of these amplifiers. the following recommended practice should be noted: I. Use shielded. twisted pair of cable at the input as with any instrumentation amplifier: r---+........'5VDC r---Ir-- ·15VDC 2. Care sould be taken to minimize external capacitance. A symmetrical layout of external components to achieve balanced capacitance from the input terminals to output common will preserve high IMR; 3. External components and conductor patterns should be at a distance equal to or greater than the distance between the input and output terminals. to prevent HV breakdown. 4. Though not an absolute requirement. the use of laminated or conformally coated printed circuit boards is recommended. APPLICATIONS Figure 8 shows a system where isolation amplifiers (3650) are used to measure the armature current and the armature voltage of a motor. FIGURE 9.3652 Used in Patient Monitoring Application (ECG. VCG. EMG Amplifier). The 3652 is ideally suited for patient monitoring applications as shown in Figure 9. The fact that it is a true balanced input instrumentation amplifier with very high differential and common-mode inpedance means that it can greatly reduce the common-mode noise pick up due to imbalance in lead impedances that often appear in patient monitoring situations. The 3kV and 6kV shown in Figure 9 are the 10msec pulse ratings of the +IR and -I R inputs for the common-mode and differential input voltages with respect to input common. The rating of the isolation barrier is 2000V. pk continuous. The nonrecurrent pulse rating of the isolation barrier is 5000V. pk since each unit is factory tested at 5000V. pk. If the isolation barrier is to be subjected to higher voltages a gas filled surge voltage protection device can be used. For multichannel operation. two 3562's can be powered by one Model 722 isolated DC/DC converter. The total leakage current for both channels at 240V 160Hz would still be less than 2p.A. The block diagram in Figure 10 shows the use of isolation amplifiers in SCR control application. FIGURE 8. Isolated Armature Current and Voltage Sensor. The armature current of the motor is converted to a voltage by the calibrated shunt R, and then amplifier (adjustable gain) and isolated by the 3650. The armature voltage is sensed by the voltage divider (adjustable) shown and then amplified and isolated by the-3650. The 3650 provides the advantage of accurate current measurement in the presence of high common-mode voltage. Both 3650's provide the advantage of isolating the motor ground from the control system ground. Isolated power is provided by an isolated DC/DC converter (BB Model 722 or equivalent). FIGURE 10. 3-Phase Bidirectional SCR Control with Voltage Feedback. 3-39 3656 BURR-BROWN® IEEI-=-1 Integrated Circuit - Transformer Coupled ISOLATION AMPLIFIER FEATURES APPLICATIONS • INTERNAL ISOLATED POWER • MEDICAL Patient monitoring and diagnostic Instrumentation • BODOV ISOLATION TEST VOLTAGE .O.5/tA MAX LEAKAGE AT I.20V. 60Hz • INDUSTRIAL Ground loop elimination and off-ground signal measurement • 3-PORT ISOLATION • 125dB REJECTION AT 60Hz • NUCLEAR Input/output/power Isolation • I" x I" x 0.25" CERAMIC PACKAGE DESCRIPTION The 3656 is the first amplifier to provide a total isolation function ... both signal and power isolation .. , in integrated circuit form. This remarkable advancement in analog signal processing capability is accomplished by use of a patented modulation technique and minature hybrid transformer. Versatility and performance are outstanding features of the 3656. It is capable of operating with three completely independent grounds (three-port isolation). In addition. the isolated power generated is available to power external circuitry at either the input or output. The uncommitted op amps at the input and the output allow a wide variety of closedloop configurations to match ihe requirements of many different types of isolation applications. I I I I ____ ..J This product is covered by the following United'States patents: 4.066.974: 4,103,267; 4, 082,908. Other patents pending may also apply upon the allowance and issuance of patents thereon. The product may also be covered in other counhies by one or· mare international patents corresponding to the above-identified U.S. patents. International Airport Industrial Park· P.O. Box 11400 . Tucson. Arizona B5734 . Tel. 16021 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66·6491 P()S-40JA 3-40 THEORY OF OPERATION Details of the 3656 design are shown in Figure I. The external connections shown. place it in its simplest gain configuration - unity gain. noninverting. Several other amplifier gain configurations and power isolation configurations are possible. See Installation and Operating Instructions and Applications sections for details. Isolation of both signal and power is accomplished with a single miniature toroid transformer with multiple windings. A pulse generator operating at approximately 750kHz provides a two-part voltage waveform to transformer T I. One part of the waveform is rectified by diodes D, through D" to provide the isolated power to the input and output stages (+V, -V and V+, V-). The other part of the waveform is modulated with input signal information by the modulator operating into the W, winding of the transformer. The modulated signal is coupled by windings W"and Wto two matched demodulators - one in the input stage and one in the output stage - which generate identical voltages at their outputs, pins 10 and II (voltages identical with respect to their respective commons, pins 3 and 17). In the input stage the input amplifier A I. the modulator and the input demodulator are connected in a negative feedback loop. This forces the voltage at pin 6 (connected as shown in Figure I) to equal the input signal voltage applied at pin 7. Since the input and the output demodulators are matched and produce identical output voltages. the voltage at pin II (referenced to pin 17. the output common) is equal to the voltage at pin 10 (referenced to pin 3. the input common). In the output stage. output amplifier A, is connected as a unity gain buffer. thus the output voltage at pin 15 equals the output demodulator voltage at pin II. The end result is an isolated output voltage at pin 15 equal to the input voltage at pin 7 with no galvanic connection between them. Several amplifier and power connection variations are possible: I. The input stage may be connected in various . operational amplifier gain configurations. 2. The output stage may be operated at gains above unity. 3. The internally generated isolated voltages which provide power to A, and A, may be overridden and external supply voltages used instead. Versatility and its three independent isolated grounds allow simple solutions to demanding analog signal conditioning problems. See the Installation and Operating Instructions and Applications sections for details. P+ PULSE • GENERATOR °2 °4 °3 V+ V· 4 ·V 0.47"Fi Co 17 FIGURE I. Block Diagram. 3-41 SPECIFICATIONS ELECTRICAL At 25°C, V± =.±15V and 15V between P+ and P-, unless otherwise noted. PARAMETER ~6AG,BG,HG,JG,KG CONDITIONS MIN TYP I MAX T I UNITS ISOLATION Voltage Rated Continuous(1), DC Rate Continuous(2), AC Test, 1Osec(') Rejection DC 60Hz, < 1000 in lIP Coml2) 60Hz, 5kO in lIP Com(2) 3656HG 3656AG, BG, JG, KG Capacitance(1) Resistance(1) Leakage Current 3500 11000) 2000 1700) 8000 13000) VDC V. rrns VDC G, =10VN 160 125 dB dB dB dB pF 0 108 112 6.016.31 10'2 110'2) 0.28 120V,60Hz 0.5 ~A 1.S 1.0 0.3 480 120 60 % % % GAIN Equations See Text Accuracy of Equations Initial(3) 3656HG 3656AG, JG, KG 3656BG vs. Temperature 3656HG 3656AG, JG 3656BG, KG VS. Time Nonlinearity External Supplies used at pins 12 and 16, 3656HG 3656AG, JG, KG 3656BG Internal Supplies used for Output Stage OFFSETVOLTAGEI5) InitiaI(3),3656HG 3656AG, JG 3656BG,KG vs. Temperature, 3656HG 3656JG 3656AG 3656KG 3656BG vs. Supply Voltage 36S6HG 3656AG, BG, JG, KG G<100VN 0.0211 + log khrS.1 % RA + RF = Rs;;>2MO ±0.15 ±O.1 ±0.05 Unipolar or Bipolar Output Bipolar Output Voltage Swing, Full Loadl4) % % % % ±O.15 RTI ±[4 + 40/G,I[ ±[2 + 120/G,I[ ±[1 + 110/Gn[ ±[200 + 11000/G,I[ ±[50 + 17S0/G,I[ ±[25 + (500/G,)[ ±[10 + 13S0/G,I[ ±[S + 13S0/G'I[ 1SVp between P+ and P- mV mV mV ~VfOC ~VfOC ~V/oC ~VfOC ~VfOC Supply between P+ and P- ±[0.1 + 110/Gn[ VS. Current(6) ±[0.6 + 13.5/Gn [ ±[0.3+12.1/G,I[ ±[0.2+(20/G,)) ±[10+1100/G,)1 x 11 + log khrS.1 vs. Time AMPLIFIER PARAMETERS ppmfOC ppmfOC ppmfOC mVN mVN mV/mA ~V Apply to A 1 and A2 Bias Current(7) Input Voltage RangelS) Linear Operation Without Damage Output Current 20 nA nAfOC nAN nA Mil II pF ~V, p-p IlV, rrns ±S Supply -SV ±8 Supply V V V V 100 Initial VS. Temperature vs. Supply Offset Currentl7) Impedance Input Noise Voltage O.S 0.2 5 100 liS S S Common-mode fs = 0.05Hz to 100Hz fa = 10Hz to 10kHz Internal Supply External Supply Internal Supply External Supply Your =±5V ±15V External Su pply I nternal Supply Your =±10V ±15V External Supply Your = ±2V, Vp<, p_ = 8.5V Internal Supply rnA rnA ±S ±.2.5 rnA ±2.S ±1 1S0 Quiescent Current 3-42 rnA 4S0 ~A ELECTRICAL (CONT) At 25°C V+ - +15V and 15V between P+ and P PARAMETER unless otherwise noted I 3656AG, BG, HG, JG, KG CONDITIONS I MIN TYP I MAX I UNITS FREQUENCY RESPONSE ±3dB Response Full Power Slew Rate Settling Time Small Signal Direction measured at output to 0.05% 30 1.3 kHz kHz V//Jsec ,usee +0.1, -0.04 500 OUTPUT fs.~ Noise Voltage (RTII 0.05Hz to 100Hz f8 ::;; 10Hz to 10kHz' "V. pop /-IV. rms mV. pop ).5 2 + ,22/G,,2 ).5.2+.11/G, 2 Residual Ripple(9) 5 at P+, p-, pins 19 and 20 POWER SUPPLY IN, Rated Performance Voltage Range(10) Ripple Current(9) Quiescent Currentl 11) Current vs. Load Current(12) 15 Derated Performance 8.5 Average vs. Currents from +V, -V. V+, V- ISOLATED POWER OUT at +V, -V, Y+, VDC VDC rnA. pop rnA. DC rnA/rnA V- pins 15V between P+ and p±5mA I lOrnA suml load (12) vs. Supply between P+ and P- Voltage, no load Voltage. full load Voltage vs. Power Sllpply Ripple Voltage(9) No load Futlload 16 25 18 10 14 0.7 8.5 7.0 9.0 8.0 0.66 40 80 ±5mA load 9.5 9.0 II V VIV 200 mV. pop mV. pop +85 +70 +100 +125' 'C 'C 'C 'C TEMPERATURE RANGE Specification 3656AG, BG 3656HG. JG. KG -25 0 -55 -65 Operation(10) Storage(13) NOTES: 1. Ratings in parenthesis and between P-r pin 201 and OIP Com r pin 17,. Other isolation ratings are between liP Com and OIP Com or liP Com and po. An example of the ratings for 3-port continu04s isolation. Gr-:=::::3500\j~~v . ---3S00v~ MECHANICAL " f, " L+C tA~ , ~ f INCHES , A c 0 , PINS Pin material and plating composition conform to method 2003 (solderability I of MIL-STD-883 (except paragraph 3.21. Jt!Ti. L,J t-l DIM ... " CASE: Ceramic MATING CONNECTOR: None WEIGHT: 10 gra(Tls (0.35 oz., MilLIMETERS MIN MAX MIN MAX 1.080' 1.120 27.43 28.45 1.080 .235 .018 .035 1.120 .285 .021 27.43 5.97 0.46 28.45 7.24 .050 G .100 BASIC H .100 BASIC K , .150 N .900 B,6.SIC .002 .010 R '.100 BASIC .350 0.89 0.53 1.27 2.54 BASIC 2.54 BASIC 3.81 8.89 22.86 BASIC 0.05 0.25 2.54 BASIC 2. May be improved with prop$r shielding. See Performance Curves. 3. May be trimmed to zero. 4. If output swing is unipolar: or if the'output is not loaded, specification same as if external supply were used. 5. Includes effects of A1 anc:t- A2. offset voltages and bias currents if recommended resistors used; 6. Versus the sum of all external currents drawn from V+. V-, +V, -V I =lIso J. 7. Eff~cts of A1 and A2 bias currents and offset'currents are included in Offset Voltage specifications. . 8. With respect to liP Com (pin 31 for A, and w~h respect to OIP Com Ipin 171 for A2. CMR for A, and A2 is l00dB. typical. 9. In configuration of Figure 3. Ripple frequency approximately 750k~z. Measurement bandwidth is 10MHz. • 10. Decrease linearly from 16VDC at 85'C 10 12VDC at 100°C. 11. Instantaneous peak current r.squired from pins 19 and 20 at turn·on is 100mA for slow rising voltages (SOmsec) and 300mA for fast rises 150~secl. 12. Load current is sum drawn from +V, -V. V+, V+I=ilsol. 13. Isolation ratings may degrade if exposed to 12SoC for more than 1000 hours or gooC for more than 50,000 hours. \ PIN DESIGNATIONS NOTE: An accessory part which provides both magnetic and electrostatic shielding is available. Order Number. lOOMS Size: 1.2" x 1.2" x 0.6" Leads in true position. within 0.01" (0.25mml R atMMC at seating plane. 3 4 5 6 8 9 10 3..43 +V MOD INPUT INPUT DEMOD COM -V BALANCE At INVERTING INPUT At NON INVERTING INp'UT BALANCE At OUTPUT INPUTDEMOD 11 12 13 14 15 16 17 18 19 20 OUTPUT DEMOO VA2 NONINVERTING INPUT A2 INVERTING INPUT A2 OUTPUT V.+ OUTPUT DEMOD COM NOPIN P+ P- TYPICAL PERFORMANCE CURVES All specifications typical at 25" C unless otherwise noted. SMALL SIGNAL FREQUENCY RESPONSE PHASE RESPONSE +5 Iii 0 c: 'OJ -5 " Cl OUTPUT SWING VS SUPPLY VOLTAGE l l r -____~~~~--~~~~ II ~ ±± r- - \ '10 - 91---+- -:---'G, :c'" ilr'-l00 0 '" 3QJ!!"o!'" 0 -10 .~ 1;; a; -15 G1 G,<> 1 mIIoOo if= 690 a: ~ " 8 ~10 h F I'- '0 > G, 1000 120 IS ~ 18 p 21 o o V V+,=V- =±1 V 24o VOUT = 30m'('v' rms 27 0 0.1 0.2 0.5 lk 2k Sk 10k 20k SOk lOOk "- iCr-I,W.lili -20 ," 15V.~1~' -25 38~"~~~1~'~~~~~~'~5~16 Frequency I Hz' OUTPUT SWING AND DISTORTION VS FREQUENCY Power Supply Voltage P± ,v OUTPUT VOLTAGE SWING VS TEMPERATURE AND ISOLATED SUPPLY LOAD NOISE VOLTAGE VS FREQUENCY 10k .,. ~ , -~ , I ,il k "co ~ 5 0 > Out'pu;~ '5 5 I 0 0 IIso (see note 12 of electrical specs" 2.2 ~ .;- 2.0 1;; % r8 E 1.8 ~ 8 1.6 C 1.4 M ':; 1.2 o ; 1.0 ~ O. 8 Z O. 6 - io"""" <; -55 -25 0 l/ ~~ L ~ ISOLATED OUTPUT VOLTAGE AND CURRENT VS TEMPERATURE ~ 7 =- i-"'" ~ 2 " 11 +50 +70+85+100 I 0 "3:V at lisa = max :: I .- 0 o -25 Temperature'loCI f0 ~ 7~ 0 -;12 C 8~ ~11 > U 68- ~ 6 al~ ,§ S 5.g i Cl. I > ~14~-+--+--+--;-~--~~~-i El0 Cl. ~ + at Iso I ~Voltage -c1urrer- +25 ~$ ! 4 ~ .~ 4~ o 3~ ~o ~~--~~~~12~~'~3~'~4~1~5~162 +50 +70+85+100 Temperature (oC) ISOLATION-MODE REJECTION VS FREQUENCY ISOLATION-MODE REJECTION VS GAIN 2001r-~~nm~rTTnrnr~~ 10k 2~"5 -::~13t--t--+-t--+,,-l;o,.o;.f-:~"--t 8 t,'S ~1 0:; 5 rtt:ttiT I 10 lao lk Frequency Hz QUIESCENT CURRENT AND ISOLATED I~OL TAGE OUTPUT VS SUPPLY VOL :~Gfo 16 ~1 6 +1 ~ +25 i Temperature (oC I QUIESCENT CURRENT VS TEMPERATURE I. In put St.g~ !=F 1a 0.1 '_~'~S~_::!2S~~0~+~2::5~+~50~+#70~...1.0"+~81::S~+':'!1~OO lk Frequency I Hz I I SO P" J Supply Voltag" at Vp.' V I AC AND DC LEAKAGE CURRENT VS ISOLATION VOLTAGE 140 I- . E i!! ~ 8 30 "" ~ 100 lk 10k Frequency (Hz) 3-44 ~ 1.S~ .oi" V IA It-1 v 10, I lOOk 2.0';;: c: U ~ 20 ~ 2.S ~ j ~ ·· · jL . o Q~ ~~ ........ ..... 1k 2k ~ .& .....• "0' t:.'l' .5g 0 ' • o 3k 4k 5k 6k 7k 8k 9k 10k Isolation Voltage I Vp I INSTALLATION AND OPERATING INSTRUCTIONS The 3656 is a very versatile device capable of being used in a variety of isolation and amplification configurations. There are several fundamental considerations that determine configuration and component value constraints: I. Consideration must be given to the load placed on the resistance (pin 10 and pin II) by external circuitry. Their output resistance is 100k!l and a load resistor of 2M!l or greater is recommended to prevent a voltage divider loading effect in excess of 5%. 2. Demodulator loadings should be closely matched so their output voltages will be equal. (U nequal demodulator output voltages will produce a gain error.) At the 2MO level, a matching error of 5% will cause an additional gain error of 0.25%. 3. Voltage swings at demodulator outputs should be limited to 5V. The output may be distorted if this limit is exceeded. This constrains the maximum allowed gains of the input and output stages. Note that the voltage swings at demodulator outputs are tested with 2M!1 load for a minimum of 5V. 4. total current drawn from the internal isolated supplies must be limited to less than ±5mA per supply and limited to a total of lOrnA. In other words, the combination of external and internal current drawn from the internal circuitry which feeds the +V, -V, V+ and V- pins should be limited to 5mA per supply (total current to +V, -V, V+ and V-limited to 10mA). The internal filter capacitors for ±V are 0.01J.LF. If more than 0.1 mA is drawn to provide isolated power for external circuitry (see Figure 12), additional capacitors are required to provide adequate filtering. ' A minimum of 0.1 J.LF / mA is recommended. 5. The input voltage at pin 7 (noninverting input to A, ) must not exceed the voltage at pin 4 (negative supply voltage for A, in order to prevent a possible lockup condition. A low leakage diode connected between pins 7 and 4, as shown in Figure 2, can be used to limit this input voltage swing. 6. Impedances seen by each amplifier's + and - input terminals should be matched to minimize offset voltages caused by amplifier input bias currents. Since the demodulators have a 100kO output resistance. the amplifier input not connected to the demodulator should also see 100k!1. 7. All external filter capacitors should be mounted as close to the respective supply pins as is possible in order to prevent excessive ripple voltages on the supplies or at the output. (Optimum spacing is less than OS'. Ceramic capacitors recommended,) POWER AND SIGNAL CONFIGURATIONS NOTE: Figures 2, 3 and 4 are used to illustrate both signal and power connection configurations. In the circuits shown, the power and signal configurations are independent so that any power configuration could be used with any signal configuration. ISOLATED POWER CONFIGURATIONS The 3656 is designed with isolation between the input, the output, and the power connections. The internally generated isolated voltages supplied to A, and A, may be overridden with external voltages greater than the internal supply voltages. These two features of 3656 provide a great deal of versatility in possible isolation and power supply hook-ups. When external supplies are applied. the rectifying diodes (0 , through 0,) are reverse biased and the internal voltage sources are decoupled from the amplifiers (see Figure I), Note that when external supplies are used. they must never be lower than the internal supply voltage. Three-Port The power supply connections in Figure 2 show the full three-port isolation configuration. The system has three separate grounds with no galvanic connections between them. The two external 0,47J.LF capacitors at pins 12 and 16 filter the rectified isolated voltage at the output stage, Filtering on the input stage is provided by internal capacitors. I n this configuration continuous isolation voltage ratings are: 3500V between pins 3 and 17; 3500V between pins 3 and 19; 1000V between pins 17 and 19. FIGURE 2. Power: Three-port Isolation; Signal: Unity-gain' N oninverting. Two-Port - Bipolar Supply Figure 3 shows two-port isolation which uses an external bipolar supply with its common connected to the output stage ground (pin 17). One of the supplies (either + or could be used) provides power to the pulse generator (pins 19 and 20). The same sort of configuration is possible with the external supplies connected to the input stage. With the connection shown, filtering at pins 12 and 16 is not required. In this configuration continuous isolation voltage rating is: 3500VDC between pins 3 and 17; not applicable between pins 17 and 19; 3500VDC between pins 3 and 19. 3-45 SIGNAL CONFIGURATIONS Unity Gain Nonlnvertlng The signal path portion of Figure 2 shows the 3656 in its simplest gain configuration: unity gain noninverting. The two 100kfl resistors provide balanced resistances to the inverting and noninverting inputs of the amplifiers. The diode prevents latch up in case the input voltage goes more negative than the voltage at pin 4. Nonlnvertlng With Gain The signal path portion of' Figure 3 demonstrates two additional gain configurations: gain in the output stage and noninverting gain in the input stage. The following equations apply: Total amplifier gain: G = G , 'G, = V(WI, VIS (I) Input Stage: G , = I + (RI, RA) (Select G , to be less than 5V /full scale VIN to limit demodulator output to 5V) (2) R, + R. ~ 2Mfl (Select to load input demodulator with at least 2Mfl) FIGURE 3. Power: Two-port, Dual Supply; Signal: Noninverting Gain. Rc = R" Two-Port· Single Supply Figure 4 demonstrates two-port isolation using a single polarity supply connected to the output common (pin 17). The other polarity of supply for A, is internally generated (thus the filtering at pin 12). 'This isolated power configuration could be used at the input stage as well and either polarity of supply could be employed. In this configuration continuous isolation voltage rating is: 3500V between pins 3 and 17; 3500V between pins 3 and 19; not applicable between pins 17 and 19. II (RI + 100kfl) = (3) R., (RI + 100kfl) ------ RA + RI + IOOk!l (Balance impedances seen by the + and - inputs of A, to reduce input offset caused by bias current) . (4) Output Stage: G, = I + (Rx/ RK) (Select ratio to obtain VOl I between 5V and IOV full scale with VI~ at its maximum) (5) R" II RK = 100kfl (Balance impedances seen by the + and - inputs of A, to reduce effect of bias current on the output offset) (6) RB = R., + Rr (Load output demodulator equal to input demodulator) (7) Inverting Gain, Voltage or Current Input The signal portion of Figure 4 shows two possible inverting input stage configurations: current input and voltage input . . Input Stage: For the voltage input case: G 1 = -RF/Rs (Select G , to be tess than 5V /full scale VIN to limit the demodulator output voltage to 5V) (8) RF = 2Mfl (Select to load the demodulator with at least 2Mfl) (9) + lOOkfl) + Rr + IOOkfl (Balance the impedances seen by the + and Rc = Rs FIGURE 4. Power: Two-port, Single Supply; Signal: Inverting Gains. II (RF + IOOkfl) - inputs of AI.) 346 Rs (R. Rs (10) For the current input case: Vour = -b" R, . G, (II) Rc = R, (12) R, may be made larger than 2Mf1 if desired. The 10pF capacitors are used to compensate for the input capacitance of A, and to insure frequency stability. Output Stage: The output stage is the same as shown in equations (5), (6), and (7). So we will calculate (;, f,)r HlV output and 125% of the maximum input voltage. :. Your = (1.25 x O.I)(GIl(G,) i.e., lOY = 0.12S x 40 x G, :. G, = IOV/SV = 2V/V Step 6 G, = I + (Rx/RK) = 2.0 Rx/ RK = 1.0 :. Rx = RK (IS) Step 7 Illustrative Calculations: The maximum input voltage is 100mV. It is desired to amplify the input signal for maximum accuracy. N oninverting output is desired. Input Stage: The resistance seen by the + input terminal of the output stage amplifier A, (pin 13) is the output resistance 100kf1 of the output demodulator. The resistance seen by the - input terminal of A, (pin 14) should be matched to the resistance seen by the + input terminal. The resistance seen by pin 14 is the parallel combination of Rx and R K. Step I -----rr;-max = 5V /Max Input Signal = 5V /O.IV = 50V jV With the above gain of SOV / V, if the input ever exceeds 100mV, it would drive the output to saturation. Therefore, it is good practice to allow reasonable input overrange. So, to allow for 25% input overrange without saturation at the output, select G, =40V/V G, = I + (RFjRA) = 40 :. RF/R" = 39 :. Rx II RK = 100kf1 i.e., (Rx ' RK/(Rx + R K) = 100kf1 i.e., RK/[I + (RK/Rx)] = 100ka Step 9 (13) Step 2 RA + RF forms a voltage divider with the IOOkf1 output resistance of the demodulator. To limit the voltage divider loading effect to no more than 5%, RA + RF should be chosen to be at least 2Mf1. For most applications, the 2Mf1 should be sufficiently large for RA + R F. Resistances greater than 2Mf1 may help decrease the loading effect, but would increase the offset voltage drift. The voltage divider with R, + RF = 2Mf1 is 2Mf1/ (2Mf1 2/ (2 + 0.1) = 95.2%, i.e., the percent loading is 4.8% The output demodulator must be loaded equal to the input demodulator. :. RH = RA + RF = 2Mf1 (See equation (14) above in Step 2) Use the resistor values obtained in Steps 3, 4,8 and 9, and connect the 3656 as shown in Figure 3. OFFSET TRIMMING Figure S shows an optional offset voltage trim circuit. It is important that R\ + Rr = Rll . CASE I: Input and output stages in low gain, use output potentiometer (R,) only. Input potentiometer (R,J may be disconnected. For example, unity gain could be obtained by setting R \ = Rll = 20M!!, R, = 100Hl. R, = O. Rx = lOOk!!, and RK = x. CASE 2: Input stage in high gain and output stage in low gain, use input potentiometer (R,) only. Output potentiometer (R,) may be disconnected. For example, G, = 100 could be obtained by setting R, = 2M!!, Rll = 2M!! returned to pin 17, RA = 20k!!, Rx = lOOk!!, andRK=x. CASE 3: When it is necessary to perform a two-stage precision trim (to maintain a very small offset change under conditions of changing temperature and changing gain in A, and A,), use step I to adjust the input stage and step 2 for the output stage. Carbon composition resistors are acceptable but potentiometers should be stable. + 100kf1) = Choose RA + RF = 2Mf1 (14) Step 3 Solving equations (13) and (14) RA = SOkf1 and RF = 1.95Mf1 Step~ The resistances seen by the + and - input terminals of the input amplifier A I should be closely matched in order to minimize offset voltage due to bias currents. :. Rc = R/, II (R r + 100kf1) = SOkf1 II (1.95Mf1 + 100kf1) == 49kf1 Output Stage: Step 5 VOUT = V,~ MAX' (16) Step 8 Solving equations (15) and (16) RK = 200kf1 and Rx = 200kf1. G, . G, As discussed in Step I, it is good practice to provide 2S% input overrange. 3-47 APPLICATIONS ECG AMPLIFIER Although the features ofthe circuit shown in Figure 6 are important in patient monitoring applications. they may also be useful in other applications. The input circuitry uses an external. low qui.escent cumint op amp (OPA21 type) powered by the isolated power of the input stage to' form a high impedance instrumentation amplifier input (true three-wire input). R.l and R. give the input stage amplifier of the 3656 a noninverting gain of 10 and an inverting gain of -9. RI and R, give the external amplifier a noninverting gllin of I + 1/9. The inputs are applied to the noninverting inputs of the two amplifiers and the composite input stage amplifier has a gain of 10. The 330kB. I W. carbon resistors and diodes DI • D. provide protection for the input amplifiers from defibrillation pulses. The output stage in Figure 6 is configl1red to provide a bandpass filter with a gain of 22.7 (68MO/3MO).-The high-pass section (0.05Hz cutoff) is formed by the I/oiF capacitorand 3MO resistor which are connected in series between the output demodulator and the inverting input of the output stage amplifier. The low-pass section (100Hz cutoff) is formed by the 68MOresistor and 22pF capacitor located in the feedback loop of the output stage. The diodes provide for quick recovery ofthe highpass filter to overvoltages at the input. The lookO pot and the IOOMO resistor allow the output voltage to be trimmed to compensate for increased offset voltage caused by unbalanced impedances seen by the inputs of the output stage amplifier. FIGURE 5. Optional Offset Voltage Trim. Step I: Input stage trim (R A = R(' = 20kB. R" = RII = 20MB ..Rx = 100kO. RK =~. R2disconnected); AI high. A210w gain. Adjust RI forO,V ±5mV or desired setting at VOUT, pin 15. Step 2: Output stage trim (RA = RH = 20MB. R, 100kO. RF = 0, Rx = lOOkO,RK =~. RI and R, connected); AI low. A,low gain. Adjust R2 forOV±lmV or desired setting at VOUT, pin 15 (±llOmV approximate total range). Other circuit component values can be used with valid results. Note: In many modern electrocardiographic systems. the 3MII R2 100MII 100IUl (4) LA HIGH 33OIc1l IW 01 RA mil 1Ia Dr LOW °4 IW ~ r-~--~-------------=L+ 10TES: 1. BAIIoPASS O.D5Hz TO 100Hz. 2. ADJUSTABLE RESISTOR MAY BE USED TO ACHIEVE MAX COMMON-MODE REJECTIOI BETWEEI LA/RA Ind RL. a IEGATIVE 15V SUPPLY MAY BE C~INECTEO II PLACE OF 0.47~F CAPACITOR IF AVAILABLE. 4. SEE OFFSET TRIMMlla SECTION. FIGURE 6. ECG Amplifier. 3-48 ..:.. 15VOC +V LA AI =A2 =A3 =OP21 01 =~ =03 =04 =IN459 330kll ·V RI 20kll R2 20kn +V RA 3301m 270kll lookn R4 15VOC FIGURE 7. Driven Right-Leg ECG Amplifier. patient is not grounded. Instead, the right-leg electrode is connected to the output of an auxiliary operational amplifier as shown in Figure 7. In this circuit, the common-mode voltage on the body is sensed by the two averaging resistors R, and R" inverted, amplified, and fed back to the right-leg through resistor R4. This negative feedback drives the common-mode voltage to a low value. The body's displacement current id does not flow to ground, but rather to the output circuit of A3 • This reduces the pickup as far as the ECG amplifier is concerned and effectively grounds the patient. G = 1001l/VJ~ ';;; R, R, R" x(RJ + R,) . Rs 100:T';;; ±2.5mA VL ,;;; ±4V (compliance) RL';;; L6kO RF + RA = RJ + R2 ;;" 2MO CURRENT OUTPUT - LARGER UNIPOLAR CURRENTS A more practical version of the current output function is shown in Figure 9. If the circuit is powered from a source greater than 15V as shown, a three-terminal regulator should be used to provide 15V for the pulse generator (pins 19 and 20). The input stage is configured as a unity gain buffer, although other configurations such as current input could be used. The circuit uses the isolation feature between the output stage and the primary power supply to generate' the output current configuration that can work into a grounded load. Note that the output transistors can only drive positive current into the load. Bipolar current output would require a second transistor and dual supply. The value of R4 should be as large as practical to isolate the patient from ground. The resistors R, and R4 may be selected by these equations: R.1 = (R , /2) (V"/V,,,) and R, = (V'M - V,,)/i d (-IOV';;; V,,';;; +IOV and -IOV';;; VCM =I+ +IOV) where V" is the output voltage of A, and VCM is the common-mode voltage between the inputs LA and RA and the input common at pin 3 of the 3656. This circuit has the added benefit of having higher common-mode rejection than the circuit in Figure 6 (approximately IOdB improvement). ISOLATED 4mA TO 20m A OUTPUT Figure 10 shows the circuit of an expanded version of the isolated current output function. It allows any input voltage range to generate the 4mA to 20mA output excursion and is also capable of zero suppression. The "span" (gain) is adjusted by R2 and the "zero" (4mA output for minimum input) is set by the 200kO pot in the output stage. A three-terminal 5V reference is used to provide a stable 4mA operating point. The reference is BIPOLAR CURRENT OUTPUT The three-port capability of the 3656 can be used to implement a current output· isolation amplifier function, usually difficult to implement when grounded loads are involved. The circuit is shown in Figure 8 and the following equations apply: 3-49 FIGURE 8. Bipolar Current Output. FIGURE 9. Isolated I to 5V IN/4 to 20mA connected to insert an adjustable bias between the demodulator output and the noninverting input of the output stage amplifier. DIFFERENTIAL INPUT Figure II shows the proper connections for differential input configuration. The 3656 is capable of operating in this input configuration only for floating loads (i.e., the source VIN has no connection to the ground reference established at pin 3). For this configuration the usual 2MO resistor used in the input stage is split into two halves, R"and R,,_, The demodulator load (seen by pin 10 with respect to pin 3) is sti1l2MO for the floating load as shown. Notice pin,19 is common in Figure II whereas pin 20 is common in previous figures. ' SERIES STRING SOURCE Figure 12 shows a situation where a small voltage, which is part of a series string of other voltages, must be measured. The basic problem is that the small voltage to be measured is 500V above the system ground (i.e., a system common-mode voltage of 500V exists). The circuit converts this system CMV to an amplifier isolation mode voltage. Thus, the isolation voltage ratings and isolation-mode rejection specifications apply. RI lOUT. IMPROVED INPUT CHARACTERISTICS In situations where it is desired to have better DC input amplifier characteristics than the 3656 normally provides it is possible to add a precision operational amplifier as shown in Figure 13. Here the instrumentation grade Burr-Brown 3510 is supplied from t.he isolated power of the input stage. The 3656 is configured as a unity-gain buffer. The gain of the 3510 stage must be chosen to limit its full scale output voltage to 5V and avoid overdriving the 3656's demodulators. Since the 3656 draws a )., 400kU ::~~~)-R-A------------~ Re 200u RIPPLE FILTEP FIGURE 10. Isolated 4mA to 20mA lot'T. 3-50 1 lOUT RL Vour = ,VIN (RF/R1J RF = Rl Your =(VIN + (5OOVI1 MRlll + (RF/RAJI RA + RF = 2Mn FIGURE II. Differential Input, Hoating Source. FIGURE 12. Series Source. significant amount of supply current, extra tiltering for the input supply is required as shown (2 x 0.47 J-LF). between the 3656 and sensitive components may not give sufficient attenuation by itself. In these applications the use of an electromagnetic shield such as the Burr-Brown lOOMS is a must. This shield is especially designed for use with the 3656 package. It provides shielding ir. all directions. Note that the offset voltage appearing at pin 15 may change by 4mV to 12mV with use of the shield; however, this can be trimmed (see Offset Trimming Section). ELECTROMAGNETIC RADIATION The transformer coupling used in the 3656 for isolation makes the 3656 a source of electromagnetic radiation unless it is properly shielded. Physical separation + Your - + 15V -:;:"- FIGURE 13. Isolator for Low-Level Signals. 3-51 FIBER OPTIC DATA LINKS Total noise immunity and electrical isolation are provided by these fiber optic data links designed to convert TTL or analog input signals to output light signals and transmit data - with maximum accuracy -through severe electrical environments. These DC-coupled links are data pattern independent. Special coding is not requi'red and asynchronous data can be accepted. 3714T is a self-contained transmitter whose output is a train of light pulses whose frequency is directly proportional to the magnitude of an analog input signal. It's capable of transmitting analog signals as small as 10mV FS upto 1.7km with a linearityerrorof ±0.005%. SPECIAL OFFER* - COMPLETE DATA LINK Here is an easy and inexpensive way to evaluate fiber optics in your application. Each FODL (Fiber Optic Data Link) contains a transmitter, receiver, two electrical sockets and factory terminated fiber optic cable. Apply power and you have a complete functioning link ready for experimentation in your own application. FODL-K1, $99; FODL-K2, $125; FODL-K3, $155; FODL-K4, $143. F0T110 transmitter/FOR110 receiver are compact IC packages (2.1" x 1.2"xO.4" 143.1mm x 27.9mm x 10.1 mm) that transmit TTL inputs at data data rates of 0 to 2M bits at distances up to 7.4km without repeaters. They also can transmit analog signals as amplitude modulation of the light output in a 10Hz to 1MHz bandwidth. "Limit one or each link per customer. SELECTION GUIDE FIBER OPTICS Transmitter/Receiver FOTll0KG/FORll0KG FOT110KG-IR/FORll0KG 3712T/3712R 3713T13713R 3714T/3713R Input Output Data Rate Wavelength Link Length! 1) TTL TTL TTL TTL Analog TTL TTL TTL TTL TTL(7) Ot02M bits Oto 1M bit to 25k bits to 250k bits to 10kHz 665nm 880nm 870nm 880nm 660nm 19OOM(4) 7400MiS) 2290M(6) 2500M(6) 2500M)6) o o o Auto~ ™ Threshold . Adjustable Light Output Ye~ Yes Yes Yes Yes Yes Yes No Yes ;'Xes Price(2) S tOO's FODLl3i Number Units 218.00 225.00 153.00 193.00 270.00 143.00 147.50 118.00 153.00 208.75 FODL·K4 .. FODL-Kl FODL-K2 FODL·K3 Rage 4-2 4-2 4-14 4-22 4-30 FIBER OPTIC CABLE ASSEMBLIES Model Conditions Core Material OCA100 OCA10l OCA102 " = 880nm A ~ 660nm >.. = 660nm Plastic Plastic Silica Attenuation Numerical Aperature . Rise Time 0.53 0.53 0.40 .. 1300dBm/km 360dBm/km 33dBm/km S.Snsec/km 3.Bnsec/km Price Page $1.80/m + $20 Cable Term. 54.80/m T $20Cilble Term. $8.40/m + $20 Cable Term 4-10 4-10 4-10 NOTES: 11 Withoul repeaters. 21 Transmitter and receiver may be purchased separately. 31 See "Special Offer" above. 41 2OO~M core dia .• 12dB/km attenuation. 5163~M core dia .. 2dB/km attenuation. 61200~M core dla .. BdB/km attenuation. 71 MaY,l)e converted to analog with a Voltage-la-Frequency converter. 4-1 I BURR-BROWN® FOT110 FORt10 leell , J' .3. :. .Hlgh Performance DigitallAnalog FIBER·OPTIC TRANSMITTER AND RECEIVER FEATURES APPLICATIONS • HIGH SENSITIVITY • INTERNAL SQUELCH • TTL (0 lD 2M blUd. typl AND LINEAR AMPLITUDE MODULATION (IMHz. typl • TRUE DC RESPONSE (data pattern Independentl • LOW BIT ERROR RATE (to 10- 141 • AUTO THRESHOLD ™ • LINK MONITORING • UP T07KM IN SILICA OR 100 METERS IN ALL-PlASTIC FIBERS ' • IMMUNE TO EMI AND ELECTRICALLY ISOLATED • INDUSTRIAL/PROCESS CONTROL • REMOTE INSTRUMENTATION SYSTEMS • NUCLEAR POWER PLANT CONTROL • TRANSFER OF FACTORY COMPUTER DATA • MULTIPLEXED DATA LINK (TOM or FDMI • DIGITAL PHONE SYSTEM (standard TIl • HIGH VOLTAGE TRANSMISSION LINE MONITORING • LIGHTNING IMMUNE SYSTEM • SYSTEMS REQUIRING INTRINSIC SAFETY The FOTlIO is a hybrid fiber optic transmitter capable of 0 to 2M baud data rate. Although most The FOTjFORIIO fiber optic transmitter and reapplications will have separate functions, it can ceiver, together with a suitable fiber optic cable, form uniquely transmit an analog signal by amplitude a versatile digital data and analog signal link. TTL modulation (AM) simultaneously with a digital TTL data (up to 2M baud NRZ) applied to the transmitter signal over one cable. Pin-selectable LED phasing input is converted to an optical signal. This is may be used to generate biphase data through the accepted by the receiver and reproduced as TTL data link if desired. Transmitter optical output is specified at its output, The receiyer has Auto Threshold™ as actual power launched and is adjustable allowing adjustment including a squelch function. True DC verycshort links without receiver overload. The LED response i. achieved, and the recovery scheme is .. color is bright red, making troubleshooting easier independent'of the data pattern, for example, Manwithout expensive test or image converter scopes. chester coding is not .required. An analog signal' . The IR transmitter offers higher power for longer (IUHz to I MHz) can also be transmitted with high ' link lengths; although the light is not visible. linearity. No external adjustments are necessary and The FORI 10 is a very-high sensitivity hybrid fiber link lengths greater than 1.7km can be attained with optic receiver capable of 0 to 2M baud NRZ data. silica fibers. Longer lengths, up to 7km witho,ut ' . rate, typical. The Auto Threshold™ circuit conrepeaters, are possible with the infrared (lR) transtinuously sets the Dllta Out threshold for maximum mitter version. In addition, the hybrid package:: noise immunity.' A 'single exter'rial capacitor can permits mounting on printed circuit boards. reduce blind width. This, lowers the bit. error rate and increases sensitivity for lower baud rate applications. DESCRIPTION PHOTO DIODE BIAS LINK MONITOR AMPLIFIER OUT ~=::::'::=r-O DATA OUT SQUELCH OUT SQUELCH DISABLE IN. ~::::::;;=:::;::::}--O SQUELCH LEVEL SET IN DIGITAL COMMON AMPLIFIER COMMON Voo .' DATA IN o--(,==::::::::~ '" CONTROL IN AMIN ENABLE IN o-~==:;:::~ Inmnallonal Alrporllnduslrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (6021 746-1111 - Twx: 910-952·1111 - Cable: BBRCDRP - Telex: 66-6491 PDS-455 SPECIFICATIONS ELECTRICAL Specifications at TA = +25°C. VOD = +5VDC for transmitter and ±Vcc = 15VDC for receiver unless otherwise noted. RECEIVER FORll0KG(1) PARAMETER ....D""'''~ SECTION ::.~'~' ",.hi (665nm to 880nml Fiber Pigtail Core Diameter Fiber Pigtai( NA Output Signallmax undistortedl Output Noise Output Bandwidth Output Offset Power Supply Rejection. Amplifier Output I CONDITION 200~m. I MIN I TYP I MAX V/~W NA '" 0.5 375 0.66 7.5 0.5 5 -10dB RL ~ :s50kO No signal. Caw ~ 47pF. BW ~ 10Hz to 2MHz Bias ~ av. -3dB Input and Bias ~ 0 (darkl ~Vcc ~ ±lVDC ~m VPEAK 0.8 DCtol 1 80 DC to 0.5 2.5 mV. rms MHz mV dB 5 DIGITAL SECTION Bit Rate(2) Duty Cyclel3) Sensitivity(4) Propagation Delay Fan Out. Data Out TTL Output "High" TTL Output "Low" Logic Polarity. Data Out Squelch Out. Data Out NRZ. UNITS OtolM 0 32 -45 Bias~O BER ~ 10 e. Bias ~ OV· 50% )n/Out Without external pull-up resistor 10 ~200~A 10 ~6.4mA No Input ~OO. Ot02M 100 15 -48 0.8 4 3.2 0.3 Low 0.25 2 2.4 10~10mA % nW dBm #,sec Unit Loads V V 0.5 V POWER SUPPLY ~~~:~n~ ±11.5 ;;~ ±Vcc~ 15V[)~ 0 rEMPERATURE RANGE ~:~ m~D;c +70 °C TRAMSMITTER I PARAMETER OPTICAL OUTPUT SECTION Baud Rate Output Power, into fiber<51 Power Adjustment Range Wavelength of LED. A peak(.) Spectral Width of LED(.) Fiber Pigtail Core Diameter Fiber Pigtail NA TR. TF (rise and fall times) Tp (propagation delay I TE (enable delay) MIN CONDITIONS Ot02M 5 -23 16 650 NRZ. Po max NA ~ 0.48 2OO~m. Maximum to Minimum Po max -3dB from Po max -10dB 10% to 90%; Po max 100KB/sec; 50% In/Out; Po max 100KB/sec; 50% In/Out; Po max FOTll0KG TYP Ot04M 10 -20 23 665 25 375 0.66 ·150 120 120 I MAX MIN FOTllOKG-IR TYP MAX oto 0.75M 680 50 -13 16 850 OtolM 90 -10.5 23 880 80 375 0.66 800 250 UNITS Baud ~W 910 850 480 480 dBm dB nm nm I'm nsec nsec nsec DIGITAL TTL INPUT Input "High" Voltage Input "Low" Voltage Input "High" Current Input "Low" Current TA - Oto +700C TA ~ 0 to +700C Vs ~ +5.25V; V(N = +2.7V;Oto+7QOC Vs ~ +5.25V; Y,N ~ +0.4V;01O+7QOC 2 0.8 V V -40 ~A -0.8 mA 2 0.8 -40 -0.8 ANALOG AM INPUT Input Impedance Input Sensitivity Input. Enable and - High, I-1kHz Input. Enable and ~ High,l= 1kHz, AM~l00% AM Bandwidth AM Distortion (total harmonic distortion) Input ~ lV. P-P. Output" -adS, Po max Mod ~ 50%, f = 1 - . 1'0 rn•• 100 100 0 1.1 1.1 V, p-p 0.3 1 0.6 mHz % 4.75 5 10.5 118 1 2.5 1.3 4.75 5 10.5 118 POWER SUPPLY Voltage Current (LED oft) Current I LED on I Voo Voo ~+5.0V ~+5.OV 0 TEMPERATURE RANGE • 665nm (lMB/secl; 880nm I 0.8MB/sec I. 4-3 5.25 17 135 +70 0 5.25 17 135 V mA mA +70 °C NOTES I. FORIIOKG operate. with FOTlIOKG or FOTlIOKG-IR. 2. See Theory of Operation and Application sections regarding operation of Automatic Threshold circuit. For baud rates less than 2, use squ~lch f.unction to eliminate unwanted error due to noise. ' 3. Input should be limited to I~W to avoid duty cycle distortion. 4. May be improved with external threshold voltage trim and bandwidth limiting capacitor (CBWI. See Theory of O..,eration and Application sections. 5. Optical output power is adjustable. See Application Information section. Optical power is measured into an exit numerical aperture I NA I 010.48 and a core diameter of 200",m. For other cable core diameters and NA see Typical Performance Curves and Cable Selection section. 6. The'IA version offers increased optical qutput power and longer links with a decrease in bandwidth. ABSOLUTE MAXIMUM RATINGS TRANIMmER +Voo Data In, Enable In, and Control In AM In Storage Temperature Range Operating Temperature Range Lead Temperature (soldering lOseCI RECEIVER ±Vcc +5.25V +5.25V +I.2Vp -55°C to +85°C -400C to +700C +300o C Squelch Di~ablelnput Squelch and Data Out Pull-Up Voltage Squelch Level Set Photodlode Bias Storage Temperature Range Operating Temperature Range Lead Temperature (soldering lOsecl ±I6V +5.25V +30V +5V +30V, max; f1V, min -55°C to +85°C -400Cto +700C +300o C MECHANICAL FOR110 (RECEIVER) FOT110 (TRANSMITTER) oooooooo •• + . + o o o n 32 17 B DIM INCHES MIN MAX MILLIMETERS MAX MIN A 1.710 1.750 43.43 44.45 NOTES: B 1.106 1.140 28.09 28.96 I. Leads in true position within 0.10" C .370 .430 9.40 10.92 0 .018 .021 0.46 0.53 F G .050 .035 .100 BASIC K .110 .150 H .130 .250 L .900 BASIC N .002 .010 (O.25MMI Rat MMC at seating plane. 2. Pin nur:nbers shown for reference only. 1.27 0.89 2.54 BASIC 2.79 3.81 N umbers may not be marked on package. 3.30 6.35 3. Maximum optical connector torque· Sin/oz. 4. Connector compatible with Amphenol 905 and 906 series or other sim!lar SMA series. 22.86 BASIC 0.05 0.25 R .110 .130 2.79 3.30 S .530 .590 13.46 14.99 T .345 .355 8.76 9.02 U .192 .220 4.88 5.59 PIN CONFIGURATION, TRANSMITTER PIN CONFIGURATION, RECEIVER I. Package Shield 2.AMln 3. Data In 4. Control In" I. Package Shield 2. Data Out 3. Digital Common 4. +Vce 5.-Vee 6. Link Monitor 7. Amplifier Common S. Amplifier Out 14. NC' 15.NC· IS. Package Shield 5. " 15. Power Adj. IS. Common and package shield 17. Package Shield IS. Voo 2S. Enable In"" "These pins are connected together internally. 29. "" ""These pins are connected together Internally, 30. "" I 31. "" 32. Package Shield +No internal connec~on. 4-4 17. Package Shield IS. Photodiode Bias 19.NC· 25.NC· 2S.NC· 27.NC· 28. Squelch·Disableln 29. Squelch Out 30. Squelch Level Set In 31.NC" 32. Package Shield TYPICAL PERFORMANCE CURVES ITA = +25°C, Voo = +SVDC, ±Vcc = 15VDC, unless otherwise noted) OPTICAL OUTPUT POWER VS AMBIENT TEMPERATURE AND +Vcc 1.6 TRANSMITTER OPTICAL OUTPUT POWER VS POWER ADJUST RESISTOR AND TEMPERATURE 1m ~ 0 1111 ~ &. :; Co :; o ~ :; -13 ~ 70°'8/ 11 -208 o :1 0.91----'1- ~ 0.81---~""" . ~ 0.71----l-- II: 26 0.6 -30 1000 10 100 Power Adjust Resistor (ohms) 1.21---1-- ~ 1:01---+-~_""'=-+~~+-1 -23 Qj 0.. -16~ 0.. 0.0 1 0.00 1 ~ _1.31---1- '" -10~ :;; o~ IW. IJrIlII 25°C 8 ~1.4 ~ ~C ~1iII 0.10 8 1• -3 1111 L.1....L.LJ-L..l..-Ll...L.L.J.-L~~ 0.5 L -----L--..l..-----l4.5 4.75 5.0 5.25 +Vcc (vO~sl 100 5.5 Not --.....l.. , lt-- ,'-- +3 4 2 L,'" G~aranteed 8- o. 8 o~ o. 6 0.. V J o.3 o :; o. 2 Qj II: - 0.2 0.3 f-:~~. 1-. ~---~t·-.~· .... +6t----+-+---.. - -.. ,";-----1~ ;----- 1-.- -- - I- :;; +3;----- -- - ~ ...... - ..···FOTll0KG- , ~O§§§l~ ~ -3 ~ T :; ~, 1--1-'-1--+FOTll0KG-IR =a -~ o I\-t \ 1--+--+--' ;----- -- +-.---4--+-1 -9t=t=t=t=i=i=tij 10 100 lk 10k lOOk 1M 10M Modulation Frequency (Hz) lA~rr~rin~.J I. Years at 1M Baud 10-13 TOTAL HARMONIC DISTORTION VS AM INPUT, TYPICAL AT 25°C 4 ~ 3. c P o 3 'e ~·2.5 ~O% - -" 50% '" -~IlbKb :; g. § 1.5 o OJ W 1 .~ 0.5 1;j Qj II: FOTll0KG-IR0.1 0.3 0.5 0.7 0.9 1.1 1.3 AM Input, Volts (p-P) 1.5 PROPAGATION DELAY VS TIME OpticaI Input o 10'" 10-8 10-7 ~ "- I-- 10 iRlH-~~ H II Spe~ified Sensitivity V I 111111 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Relative Optical Input Power (%/100) Data Outpu t Lo FOT110KG-IR- . :1 -0 >- O.5 '" 10- ++ 0 2 OV Amp Outpu t 10-1 1 F~Tlll0~G ~aIlIT"i'e I- FOTll0KG 'Eo o 11 _I -1 -2 -3 -4 oS -6 -7 -8 -9 -10 -1 1-12 Output Power (dBI ~+H+ ~TIO~ -- PERCENTAGE Ci . r t- t- TRANSMITTER SPECTRAL OUTPUT 100% 10-12 II: t1 - .1 .I.. 1 .1 ). o BIT ERROR RATE VS OPTICAL INPUT POWER 4 -+- FOTll0KG Rise Time 2 -10 0.4 0.5 0.6 0.7 FiberNA OUTPUT POWER VS MODULATION FREQUENCY, TYPICAL AT 25°C 1) l- 8 6 4 / O. 1 0.05 0.1 l- 0 II ~ ! - - -+ 6 - -- - FOTll0KG-IR F~II TimeI I I I I I I 4t- t - FOT110KG-IR Rise Timei I2 / :; C. o. 4 :; -10 5~0 400 I .0 ~ Specified 300 OPTICAL OUTPUT RISE AND FALL TIMES VS ADJUSTED OUTPUT POWER LAUNCHED OUTPUT POWER VS CABLE FIBER N A 8 ~ 200 Fiber Core Diameter (micrometers) J II 1\ "- +-- 1~ J ~ Time 4-5 I ·0 600 700 800 900 1000 Wavelength (nanometers) OPTICAL INPUT POWER FOR 10-9 BER VS BAUD RATE 3.6 ---- I-3.4 I-- ---I-- .- f-_ 3.2 I-- . - - -t- I83.01-- _.>:: 2. 8 ~ 2. 6 :;; 2.4 Not Specified in this Reglo~ .... :; 1.8 : c. 1.6 : .;: 1.4 1--;----- Diode Biasi: OV : ~ 1. sensitivity) ii 1. ~~,i.!PeCified 8 Diode Bias: +15V ~ O. H:~ -. ~ ....... O. 6 O.4 O. 2 01 10 100 lk 10k lOOk 1M 10M NRZ Baud Rate INPUT POWER FOR 1~ BER VS CABLE N A .. 2 TYP'~' LOl.. d.J ~ Cab elP,!!lall N."'. Mismatc 8 ~ i " i 1. o.e RESPONSIVITY ,VS WAVELENGTH 8 8 e ~ 4 ~ ; 3 0.8 ~ ~ 2 I 0.4 c 0.3 i :J! 0.2 ~ 0.8 Q. INPUT POWER FOR 10" BER VS CABLE CORE DIAMETER 10 i , ,/ ./ / J /TYPical LOlli due to CableIPlgtall Area Mismatch 1 /' \ 1/ \ 1/ \\ 0.6 o.1 o 0.1 0.2 0.3 0.4 0.5 FlberN.A. 0.6 0.4 o 0.7 200 400 600 600 1000 1200 Fiber Core Diameter (micrometers) THEORY OF OPERATION TRANSMITTER AM IN 600 800 1000 Wavelength (nanometers) EIABlE II ~J DATA II I LOCK IYIICH'DJ 0 .. CONTROL I. I LOCK ITIICII'DI 0 LED ON OFF r · DATAl. 0 .. CONTROLIM 0 400 data to the Data In. This technique reduces the baud rate. but is useful for generating an AC signal. Figure 2 shows a timing diagram. The FOTIIO transmitter, shown in Figure I, consists of digital input gates, a current mirror, and an LED. The open-collector exclusive OR gates are lower power Schottky TTL. This circuit can transmit a data rate of at least 2M baud (0.75M baud FOTlIOKG-IR). ENABLEIN o FIGURE 2. Timing Diagram, The LED is driven by a ratioed current mirror as shown in Figure I. When the voltage at the base of QI is high (~2VBE), the LED is on. With REXT=O, the LED is at the maximum current of 108mA. Increasing the value of REXT reduces the LED current and output power. This will reduce power consumption and extend LED lifetime, This also allows operation over very short links without receiver overload. For selection of REXT see Typical Performance Curves. The LED can also be intensity modulated directly by the voltage level at the Amplitude Modulation (AM) input. The AM signal can be audio or low frequency RF (up to I M Hz). It should be capacitively-coupled to the input to prevent DC levels from disturbing the transistor bias voltage. In effect, the AM input voltage modulates the LED current causing intensity modulation. A I.lVp-p signal through a capacitor to the AM input will provide 100% modulation. ) 0-------.. . . RZ -= POWER ADJUIT FIGURE I. Transmitter Simf>Iified Schematic Diagram. When the Enable In is high ("I''), the Data In will control the state ofthe LED. The data-LED phase relationship is controlled by applying a "I" or "O"to the Control I n, as shown in Table I. . RECEIVER TABLE I. Transmitter Truth Table. ENABLE IN DATA IN .. CONTROL IN LED 0 1 1 1 1 X 0 1 0 1 X 0 0 1 ,1 Off Off The FORI 10 receiver, shown in Figure 3, coosists of a PIN photodiodeand transimpedanceamplifier, followed by two comparators, one for data and one for squelch. The photodiode converts the incident light signal from the optical fiber to a current corresponding to the received power. Sensitivity and bandwidth can be improved by biasing the photodiode to +V cc. However, at temperatures greater than +50°C, sensitivity' will be reduced due to photodiode dark current (see Typical On On Off Biphase modulated data can be generated by applying a clock signal to the Control In and clock-synchronized 4-6 amplifier output and common. Its value is determined by the following relatipnship: Performance Curves). The current is converted to a voltage by a low noise, high speed, trans impedance amplifier. This voltage, appearing in Figure 4 as an eye Caw = - - - - " - - - 21T (2.5) Fe SQUELCH LEVEL SQUELCH DISABLE SET IN IN where Fe is the 3dB cut-off frequency in kHz and C. w is in microfarads. The squelch function allows the data output to be cut off by comparators when the optical input power falls below a preset level. This is accomplished by strapping the Squelch Out to the Data Out. With no external connection to the Squelch Level Set In, the squelch level will be approximately 20n W. Squelch can be turned off with "I " applied to the Squelch Disable In. The Link Monitor output can be used to monitor the continuity of the link. The load impedance should be greater than lOOk!1. AMPLIFIER OUT TRANSIMPEDANCE AMPLIFIER DATA OUT Plr COMPARATOR? DIGITAL . . COMMOI --""1 PHOTOOIODE 2.8kn PHOTODIOOE BIAS 2An LlIK MOIliTOR AMPLIFIER COMMON CABLE SELECTION The FOT / FOR 110 connector is compatible with Amphenol 90S and 906 series or similar SMA connectors and can be used with a wide variety of cable types. The choice of a cable type depends on the particular application. FIGURE 3. Receiver Simplified Schematic. diagram, will be reconstructed into a TIL output through comparator I. Ifthe transmitter is amplitude modulated, then the AM signal can be obtained at the amplifier output. The visible (66Snm) output of the FOTlIOKG is well matched for use with low cost all-plastic cable as well as glass and silica fibers. The high power infrared (880nm) output of the FOTlIOKG-IR provides improved performance with glass and silica fibers. However, use with plastic fibers is severely limited due to high attenuation of these materials in the infrared. The operating temperature range and mechanical integrity of fiber optic cables varies widely. Cons'ult manufacturers' specifications for specitic information; some are shown in Table II. Table III contains calculated link performance for selected fiber optics cables. Performance is based on best available data from fiber optic cable manufacturers at time of printing. The reference of the comparators is automatically set by the Auto Threshold™ peak detector. This threshold voltage, at the Link Monitor output, is equal to one-half of the amplifier peak output level. This assures that comparator I will always switch with maximum noise immunity. Unlike fixed-threshold receivers, this circuit maintains symmetry over a wide dynamic range. In AMPLIFIER OUT TABLE II.. FOT / FORI 10 Compatible Cable Manufacturers. LINK MONITOR THRESHOLD OUT DATA OUT FIGURE 4. Amplifier Output (Eye Diagram) and TIL Data Out. (SOOk Baud, Diode Bias = OV, Caw = 47pF, Receiver Input 2SnWPEAK, A = 665nm). Maxlite Fiber OptiC Div. Raychem Corp. of Arizona 3035 N. 33rd Drive Phoenix, AZ 85017 (602) 269-838i Siecor Optical Cables. Inc. P.O. Box 489 Hickory, NC 28801 (704) 322-3740 E.I.DuPont de Nemours & Company,lnc. DuPont Building 0-13121-5 Polymer Products Dept. Wilmington, DE 19898 Telecommunication Products Corning Glass Works Corning, NY 14831 (607) 974-4411 (302) 774~39' Quartz Products Corporation 688 Somerset St. P.O. Box 1347 Plainfield, NJ 07061 (201) 757-4545 addition, it provides improved bit error rate with larger input signals. Since the FORI 10 is DC coupled, it allows far greater noise immunity than "edge-triggered" systems. Improved sensitivity can be achieved in lower speed applications by adding an external capacitor between the 4-7 Nissho-Iwai American Corp. Broadway Plaza Suite 1900 700 South Flower Street Los Angeles, CA 90017 (213) 688-0684 TABLE III Calculated Link for Selected Cables (at +25°C) III TRANSMITTER FOT110KG IRed LEDI CABLE TYPE FIBER CORE DIAMETER I~ml All Plastic(4) Glass/GlasslSI Plastic Clad Silica(6) Telecom' Silica(7) Telecom Silica(8) Light Duty Plasticl 91 FOT110KG-IR IIR LEDI All Plasticl41 Glass/GlasslSI Plastic Clad Silical101 Telecom Silica(7) Telecom Silica(8) FIBER EFFECTIVE(2) NA FIBER LOSS(2) dB/km TYP MAX 368 200 200 50 100 400 0,42 0,38 0,34 0,20 0,28 0,5 260 12 270 85 15 9 380 12 720 368 200 200 50 100 0,42 0,35 0,33 0,20 0,27 600 850 45 20 2.5 7 80 35 15 2 4.5 LINK LENGTH' m WORST CASEl31 TYPICAL 75 219 1203 NOT RECOMMENDED 871 118 311 2028 ~ 1861 83 42 636 1402 69 948 2259 4533 8588 2873 5767 NOTES: (1) Lengths can be determined on the basis of power launched; losses, and receiver sensitivity for bit error rate. (2) Best estimate of NA at this length. Manufacturer's loss data (could be typical) on fiber. (3) Typical Ii ber loss. worst case = F9T11 0 mi n output power, FOR 11 0 worst case sensitivity. (4) ,Dupont PI FAX PIR-140, lSI Siecor 155 Super Fat 161 Maxlite MSC200A. 171 Corning 2510F. 181 Corning LCF. 191 Burr-Brown OCA-201-XX terminated cable assembly, 110) Maxlite MSC2ooB, The transmitter output power is specified as the power coupled into a 200~m core diameter fiber with an N A of 0.48. Larger NA (up to 0.66) couples more power, and smaller NA less power. Larger core diameter (up to 375~m) couples more power, and smaller core diameter couples less power. Power coupled into various cables can be calculated as follows: ENABLE IN DATA IN '" CONTROL IN Power coupled into cable = Dla NA )2xl (1-0.48') IxFOTJ 10 Rated . )2x (0.48, (200~m ,1 - NA2 I Output Power I POWER ADJUST FIGURE 7. Analog Amplitude Modulated Transmitter. where Dia = cable fiber core Dia (~m) up to 375~m max. NA = effective cable NA up to 0.66 max (effective NA depends on cable length, decreasing with increased length to a "steady state" value). Coupling into graded index fiber results in additional 3dB loss. ·PHOTO DIODE BIAS MAY BE CONNECTto TO .VC C DATA OUT See Typical Performance Curves for Launched Output Power vs Core Diameter and vs Numerical Aperture. BASIC CIRCUit CONNECTIONS 10~F/25V Voo (+IV) TANTALUM + FIGURE 8. TTL and Analog Receiver. 2.5~F/IOV TANTALUM FoT11oK6 POWER ADJUST R=olDlkn "::' Po IlIIXII R=on FIG U RE 6. TTL Transmitter with Output Power Adjust. FIGURE 9. TTL Receiver with Squelch. 4-8 TYPICAL APPLICATIONS The FOT / FOR 110 Fiber Optic Data Link solves such data transmission problems as crosstalk, ringing, and echos. Electromagnetic radiation interference is avoided when using a fiber optic data link in high noise environments. Lightning damage to cables and connected equipment can be eliminated where fiber optic cables replace TTL DATA IN ---t metallic conductors. In refineries and chemical plants which have explosive atmospht;res, sparks from shorted electrical cables are eliminated by the fiber optic cable an inherent safety feature. Figures 10 thru 14 illustrate the use of t'he FOT / FO R transmitter and receiver to replace conventional metal conductor cables. p~ -~ FOTIIO I /' FORIIO t--._-- TTL DATA OUT SQUELC... H'T"T--,J '" CONTROL IN SQUELCH IN OUT FIGURE 10. TTL Transparent Data Link with Squelch. '--_-oJ' COMPUTER TERMINAL '--_-oJ ~ t=~ COMPUTER ~""'_-oJ FIGURE II. RS232 Compatible Fiber Optic Data Link (Full Duplex). , fUTIIO ~AIIN"~ MICROPHONE AlP 9 'P -z.. ""2. q fORl\O AIPURER~UT P 'SPEAKER AlP FIGURE 12. Fiber Optic Voice Link (Optical Intercom). 0.01% UNEARITY PRECISION DC LEVELS DOWN TO 10lllV FULL SCALE FIGURE 13. Remote Transducer Readout. TTl DATA OUT ~) N TRANBOUCER o 0 10NITOR IONITOR IBW AM « BAUD RATE AND AI < 50%) FIGURE 14. Remote Patient/Medical Monitoring (Simultaneous Analog/Digital Transmission System with Megavolts of Isolation). 4-9 BURR-BROWN@ OCA100 OCA101 OCA102 IElE:lI Step-Index FIBER OPTIC CABLE ASSEMBLIES FEATURES APPLICATIONS • • • • • • • • . • • • FACTORY-INSTALLED CONNECTORS USER-SPECIFIED LENGTH· No Minimum Order IMMUNITY FROM EMI AND RFI NO RADIATED RF ELIMINATES GROUND LOOPS AND SHORT.CIRCUITS ELIMINATES EXPLOSION AND FIRE HAZARD GUARANTEED COMPATIBILITY WITH 3712T IR AND 3713T/R • • • • • INDUSTRIAL/PROCESS CONTROL SYSTEMS IMMUNITY TO NOISY ENVIRONMENTS REMOTE INSTRUMENTATION SYSTEMS POWER PLANT CONTROL HIGH VOLTAGE OR ELECTROMAGNETIC FIELD RESEARCH FACTORY DATA COLLECTION SECURITY SYSTEMS INTRINSIC SAFETY MACHINE TOOL CONTROL SHIPBOARD AND AIRCRAFT CABLES GENERAL DESCRIPTION protective jacket is of Hytrel®polyester elastomer. The plastic core is well centered within a thin cladding to which a connector is crimped directly. The OCAIOI is the most rugged cable of this series of cable assemblies. Its large core diameter and large numerical aperture make possible run lengths of up to 90 meters. The OCAI02 is a plastic clad silica tiber optic cable assembly. Its single fiber is protected by two jackets of Hytrel® polyester elastomer and Kevlar® aramid reinforcing fibers to give this cable outstanding strength and ruggedness. The low attenuation of the OC A 102 permits run lengths of over !l50 meters (over I! 2 mile) when it is used with the 3713T transmitter and 3712R receiver mixed data link. The OCAIOO Series Fiber Optic Cable Assemblies are factory terminated cables. They use the AM prM Optimate Single Position Fiber Optic Cable Connector System and Single, Step-Index Optical Fibers. These cable assemblies are individually tested to insure their compatibilitywith Burr-Brown's 3712 and 3713 fiber optic transmitters and receivers. The OCA 100 is an inexpensive, high loss cable assembly suitable for general purpose applications. This plastic core, plastic clad fiber optic cable offers the best price versus performance trade-offs for short lengths. The OCAIOI is a single-channel, plastic core, plastic clad fiber optic cable assembly. This cable is reinforced with Kevlar® 49 aramid fiber. The outer International Airport Industrial Parte· P.O. Box 11400· Tucson; Arizona 85734· Tel. 1602) 746-1111· Twx: 910-952·1111 . Cable: BBRCORP· Telex: 66-6491 PDS-42S 4-10 SPECIFICATIONS Attenuation dB/km dB/km 1 meter test length. Ends wrapped around 1.6cm radius ORDERING INFORMATION To order, specify cable part number (OCAIOO, OCAIOI, or OCA 102) and desired length to the nearest tenth of a meter. SAFETY Do not look at the output end of the fiber optic cable because high radiance LEDs or lasers can inject sufficient MAXIMUM CABLE SPECTRAL ATTENUATION OCA101 '" ill ~ 800 4.000 3,000 E ~ ~ 2,000 0 ~ c: 400 200 c: 0 :; c: :; OCA102 1000m~~m SOO 10.000 8.000 6.000 E power into optical fibers to injure the eye. Reasonable precaution should be observed to avoid undue skin contact when handling the OCAIOI and prolonged contact with the cable should be avoided. The jacketing materials of the OCAIOI have been specially treated with additives which inhibit the propagation of flame along the cable. Wash hands before smoking or eating. Gloves are recommended for extensive handling. 1,000 800 ~ c: " <0: = ~ <0: 100 80 60 40 400 20 200 100 500 500 600 700 SOO SOO SOO 700 SOO Wavelength (nm) Wavelength Inm) 4-11 800 1000 1100 CABLE CONSTRUCTION OCA100 OCA10l Outer Jacket 2.2mm ,0.087", Alathon'" OCA102 "Con~,rlJ;' "". Outer Jacket 1.9mm 10.075", ~ Clad Plastic optical! Fiber 1016J,Lm 10.040" I "Fiber Dia," I nner Jacket 125mm ,0.049". Clad Plastic Optical Fiber 400"m ,0.016" Hytrei® "Fiber Dia." Remforclng Fibers Kevlar ll,49 Pure Silica Fiber 200"m 0.008" "Core Dla" "Fiber 018," CABLE CONNECTOR CONSTRUCTION ~ YPICAL CABLE CONNECTOR ASSEMBLY Jacket o F ptlC Iber ~c"mplng Ring PIN 530526-t AMPTM Ferrule ()~Rela,","g Cap AMP'M PIN 861403-7 '" ~ Prepared Cable Ferrule Shoulder Cap Ferrule I Color coded by AMpTM connector numben COMPONENT PARTS ASSEMBLED CONNECTOR APPLICATIONS INFORMATION CABLE TERMINATION For splicing a damaged cable the following procedure may be used. These procedures will cause an additional loss of about -2dB with the OCAIOO, -4dB with the OCAIOI, and -5dB with the OCAI02 due to coupling losses at the splice. I. Clean ferrules ultrasonically in isopropyl alcohol. Allow to dry 24 hours at +25"C or bake at +50"C for 30 minutes. 2. Strip off 2cm of the outside jacket from the cable. This may be done by using an A WG stripper blade #17 for the OCAIOO, a #22 for the OCAIOI, ora# 16 for the OCA 102. 3. For the OCAIOI or OCAI02, cut back Kevlar® strength fibers to I cm using sharp scissors. 4. For the OCAI02, strip exposed inner jacket to the Kevlar® using a #22 A WG stripper blade. 5. Clean stripped cable end ultrasonically in isopropyl alcohol. At least IOcm of the cable should be cleaned from its end. \Vipe dry with a clean wiping tissue and allow to dry for one hour. 6. Apply an epoxy such as TRA-BOND BA-2114to the inside of the ferrule. Thoroughly coat the small hole in the end of the ferrule. Wipe off any spilled epoxy from the outside of the ferrule. 7. Slip the brass crimping ring and the retaining cap (in that order) over the end of the cable. The open threaded-end of the retaining cap should be facing the end of the cable. 8. On the OCAIOI or OCAI02. fold back the Kevlar®. 9. 10. II. 12. 13. Dip the end ofthe fiber into the epoxy adhesive. Coat between Icm and 2cm with epoxy. Insert cable into ferrule as far as it will go. Do not smear adhesive on the outside of the ferrule. Slide retaining cap and then crimping ring over the ferrule. Position crimp ring about Imm behind cap to allow it to rotate freely when installed. Crimp with AMpTM tool number 90364-1. Allow epoxy to cure 18 hours. Cleave and polish fiber as described in the following sections. FIBER CLEAVING NOTE: Reasonable precautions should be observed when terminating the OCAI02 (silicia core cable). Eye protection is recommended to protect against injury from fragments of silicia core. Avoid skin punctures. Procedure for cleaving OCA 100 or OCA 10 I: I. Cut the fiber completely through with a sharp razor blade so that it protrudes about I mm fro in the end of the ferrule. Procedure for cleaving OCAI02: I. Using a sharp silicon carbide razor blade cut through the cladding and just barely nick the silica core. Do not saw back and forth or allow the fiber to rotate. Do not cut through the fiber. If the fiber is cut all the way through, a crack could propagate into the core 4-12 2. 3. which could result in reterminating the cable. Bend the fiber at the scribe. A clean cleave should result. Examine the end with a magnifier. If the. cleave is smooth. ,the core should appear darkened when viewed at a 45" angle. If a crack did.'progag~te into the· core. the core should. appear white - consider recleaving. 8. 9. polishing bushing immediately surrounding the ferrule is polished to a glossy finish. Remove and discard the polishing bushing - do not reuse. Clean connector in isopropyl alcohol. MINIMIZING SPLICE LOSSES Losses due to lateral misalignment of the optical fibers inside the splicing bushing can be minimized as follows: 1. Blade 2. Alilililililililillllllllllililililcioi,e.> Cladding 3. FIBER POLISHING NOTE: Fine silica powder produced in polishing the OCA 102 may be hazardous if inhaled. Procedure: 1. Screw polishing bushing into retaining cap until ferrule is firmly bottomed. 2. Take connector between thumb and forefinger as if it were a pencil. Connect the spliced cable to a working fiber optic da\a link. Loosen the retaining caps of the cable. If a 3712 or 3713 data link is used. monitor the analog output of the fiber optic receiver. Rotate one of the cables inside the splicing bushing to get a maximum signal from the analog putput. Tighten the retaining caps of the cable. If a data link other than a 3712 or 3713 is used. monitor the optical power out of the spliced cable using a radiometer. Rotate one of the cables inside the splicing bushing to get a maximum signal at the radiometer. Tighten the retaining cap. MATERIAL SUPPLIERS This is a representative list of suppliers for some of the materials mentioned in this product data sheet: 1. Wire Strippers: Ideal Ind ustries. Inc. Sycamore. IL 60178 2. Silicon Carbide Blades: Deane Carbide Co. P.O. Box 118 Trevose. PA 19047 (215) 673-2.21 3. Shears for Cutting Kevlar®: Technology Associates. Inc. P.O. Box 7163 Wilmington. DE 19803 (302) 475-6219 3. 4. 5. 6. 7. 4. Polishing Materials: Glennel Corp. Rt. 100 S. or Rt. 141 Chester Springs. PA 19425 (215) 458-8901 5. Epoxy Adhesive: TRA-CON. Inc. 55 North Street Medford. MA 02155 (617) 391-5550 6. Connectors & Splicing Bushings: AMP. Inc. 449 Eisenhower Blvd. Harrisburgh. PA 17105 (717) 564'{)101 Use a figure 8 pattern when polishing the end of the fiber. The polishing paper should be thoroughly wet with water before beginning. Clean the end ofthe polishing bushing in isopropyl alcohol after each polishing step and before going to finer paper. Polish very lightly with 600-A type silicon carbide paper until polishing lines from fiber are no longer visible. Next polish with 3 micron silicon carbide lapping film. Note: Lapping film must be kept free of dust particles. Accumulated dust and dirt on the surface of the film will act as an undesirable abrasive. Polish with 0.3 micron aluminum oxide lapping film. The polishing is complete when the surface of the 4-13 3712T 3712R BURR-BROWN@ IElElI High Sensitivity "'Low Speed FIBER OPTIC TRANSMITTER AND RECEIVER FEATURES APPLICATIONS • • • • • • • • • • • • INDUSTRIAl/PROCESS CONTROL REMOTE INSTRUMENTATION SYSTEMS POWER PLANT CONTROL HIGH VOLTAGE DR ELECTROMAGNETIC FIELD RESEARCH • FACTORY DATA COLLECTION • SECURITY SYSTEMS • INTRINSIC SAFETY LOW COST HIGH SENSITIVITY TTL INPUT 10UTPUT IMMUNITY TO ELECTROMAGNETIC INTERFERENCE NO EXTERNALLY RADIATED SIGNAL ELECTRICAL ISOLATION DUTY CYCLE INDEPENDENT DOC TO 700 C OPERATION DESCRIPTION The 3712T and 3712R when connected by a suitable fiber optic cable form a 2Sk baud NRZ fiber optic data link capable of operation to 1.5km. The 3712T fiber optic transmitter is an electrical-tooptical transducer designed for digital data transmission over single fiber channels. Transmitter circuitry converts TTL level inputs to optiCal pulses at data rates from DC to 2M baud NRZ. .' The 3712R fiber optic receiver is an optical-toelectrical transducer designed for reception of digital data over single fiber chan mils. The receiver circuitry converts optical pulses to TIL level outputs with a receiver sensitivity of a mere'2n Wand data rates to 25k baud NRZ. ' An integral optical connector, on both the 37l2T and 3712 R, allows easy interfacing between modules and optical fiber without problems of s.ource/ fiber / detector alignment. The metal packages of the 3712T and 37l2R provide immunity to electromagnetic radiation and direct printed circuit board mounting with no additional heat sink required. +Voo TTL INPUT TRANSMITTER PHASING 60 +VCC TTL OUTPUT .37121 ANALOG OUTPUT ANALOG COMMON DIGITAL COMMON TRANSMITTER 6180 DIGITAL COMMON THRESHOLD ADJUST Inlamallonal AII'lJDrt Indlllirial Park· P.O. Box 11400· Tucson. Arizona 85734· Tal. 1802) 746-1111 - Twx: 910-852·1111 • Cabla: BBReoRp· Tallx: 66-6491 PDS:4Ol!A 4-14 SPECIFICATIONS ELECTRICAL Specifications at TA = +25°C, +VOD = 5VDC, ±Vcc = 15VDC and Output Power no threshold trim unless otherwise noted. Coupled into: 1016~m, 368~m, 200~m, 0.S3NA Fiber 0.S3NA Fiber 0.40NA Fiber 2.5 0.33 0.10 Wavelength 10% to 90% 90% to 10% Rise Time Fall Time Detector Active Area Noise Equivalent Power Output Noise A ~ 9OOnm, F ~ 1kHz, BW . 10Hz to 10MHz -3dB Bandwidth Output Offset 25°C 70°C ~ Fan Out TTL Out "High" TTL Out "Low" ~W nm nsec nsec Baud -11 -11.3 mV/nW -3.6 -6 DC to 15 1.7 5.2 x 10-" 0.35 DC to 20 mV/nW mm2 W/.JHZ mV, rms kHz -10 0.2 0.65 -12 0 to 20k oto 25k 1Hz ~ 2kfl NRZ coding Output Rise Time Output Fall Time ~W mV/nW 8.2 X 10-" Total Darkness Rl Duty Cyclel'l Sensitivity(2)(3) Propagation Delay ~W -6.9 -6.7 A ~ 940nm A ~9OOnm A ~ 670nm 3.5 0.46 0.14 670 120 50 o to 2M o BER ~ 10-9, 1kB/Sec,A ~ 670nm, OOC to 70°C Light In, Digital Out 20 Without external pull-up resistor Without external pull-up resistor Without external pull-up resistor Without external pull-up resistor Without external pull-up resistor No Light ±ISVDC NOTES: 1. See "Applications Information" section regarding operation of Automatic Threshold ~ircuit. 2. May be improved with external threshold voltage trim. 3. Input should be limited to O.2p.W to avoid duty cycle distortion. 4-15 0.5 1.3 mVDC mVDC V 100 Baud % nW 30 ~sec 0.4 IJ.sec Unit loads V V ~sec 2.4 0.15 4 3.2 0.2 Low MECHANICAL I' 'I B Order Number. 3712T INCHES MIN MAX MILLIMETERS MIN MAX A 1.610 1.650 40.89 _B C 3.060 .680 78_7 0 3.020 .640 .038 .042 16.26 0.97 F .075 .095 1.91 G .200 BASIC DIM H J .670 17.27 1.07 2.41 5.08 BASIC .770 17 .02 .755 BASIC I 41.91 1777? I 19.56 19.18 BASIC K .250 L p 2.200 BASIC 55.88 BASIC .100 BASIC 2.54 BASIC R .275 at MMC at IICatina S .980 plaDo. T NOTE: Leads in true pooitioD within .OW (.38mm)R U 4-40 thr.ad. .ISO· (3.8Imm) min. depth, 2 p....' in true position within .OW (.38mm)R I .275 .375 V .460 .260 I 6.99 9.53 24.89 25.91 .315 6.99 8.00 22.61 BASIC .500 11.68 .300 .835 .795 8.89 1.020 .890 BASIC W Y 6.35 .350 12.70 6.60 20.19 7.62 I 21.21 atMMC. PIN CONFIGURATION 3712T (Bottom View) 3712R (Bottom View) . +vPP. Transmitter. Phasilll . .tA. TTL Input. .8,10 ~:n~=. Threshold Adjust Digital Common 0 • TTL Output g~~'::on· ,----------. R,o = 7.Skll~ -Vee , ,,r-------· +vcc I , , I , , .------. I ,, ~~~n· R,O = 2sS7f , L__ I 0 ~n:.::~. ·Option Threshold Adjustment APPLICATIONS INFORMATION THEORY OF OPERATION TransmlHer Operation A simplified block diagram of the 3712T transmitter is. shown in Figure I. The input stage uses a Schmitt Trigger EXCLUSIVE OR Gate G, for noise immunity, and its logic is configured so the phasing of the transmitter is pinprogrammable. When the transmitter phasing pin is connected to 00 the light output is in-phase with the digital input signal- the LED is on when the TTL input is high. Connecting the transmitter phasing pin to 0'80 causes the reverse to happen - the LED is on for a digital low. Operating the 3712T with the transmitter phasing to 0'80 makes it possible to detect a break in the fiber optic cable when the data link is idle. This may be particularly useful in the transmission of asynchronous data with an idle state of a TTL low. Programming the phase of the 3712T is discussed- more in "Receiver Operation". Amplifier A, and the current switch drive a light emitting diode (LED). r-------------------- I r--~t__U I +voo -; .......- 0 FIGURE I. 3712TTransmitter. 4-16 DiJitalCommon Receiver Operation A simplified block diagram of the 3712R receiver is shown in Figure 2. Input light is converted to a current by the PIN photodiode CRI which is connected in the photovoltaic mode for maximum sensitivity. A low bias current FET input current-to-voltage converter tranforms diode current into a voltage (V A) which is further amplified by A2 and presented to comparator A3 as VB where it is compared to the threshold voltage VT • For maximum noise immunity it is desirable to have the threshold voltage set to a value corresponding to a level halfway between the high value and low value of input regardless of the actual light level at the input as shown in Figure 3c. In the 3712R this is accomplished by a peak detector type Automatic Threshold Circuit. A pulse of light input causes a voltage pulse at VB which is stored in the Automatic Threshold Circuit, divided in half, and supplied to the comparator as the threshold input VT • Thus, VT is a voltage corresponding to the midpoint of the Light and No Light conditions of the diode. Since the Automatic Thr.eshold Circuit uses a capacitive hold technique the threshold voltage VT' is subject to decay, as in Figure 3c, when light is removed from CRt. A No Light condition of approximately 1/2 second duration (a I baud data rate) can be used with no significant effect on noise immunity. If the light is left off indefinitely, the voltage at VT will drop to the noise floor and the TTL Output will be subject to normal noise pulse outputs, as illustrated in Figure 3d. The first light pulse received will then activate the Automatic Threshold Circuit. The initial transition at the TTL output may be uncertain for this first pulse, but after the first pulse a'ctivates the Automatic Threshold Circuit there will be no uncertainty in the TTL output. It should be noted that the polarity of the transmitter is pin-programmable. Thus, in an application where there are idle states that exceed.1 / 2 second (such as ASCII data transmission) the transmitter may be programmed such that the idle state corresponds to a Light On condition (see Figure 3e). This will keep the automatic threshold activated and there will be no first pulse ambiguity as shown in Figures 3f and 3g. Connecting the transmitter phasing to 8180 has the disadvantage of keeping the LED on during idle periods. LED optical output is a function of operating time as shown in Figure 4. TIL Output Light Flux Input :: L...W......~M_-4n i1~J Threshold Adjust W"l ___X-±r6___, A';;:!mon -Vee Digital Common FIGURE 2. 3712R Receiver. High Low (a) TIL Input to 3712T. High Low (b) 3712T Light Output Pulses (transmitter phasing to 110). ~::~:!' 100 V, (c) Inputs to A". ~ . S High Low 80 s T,\ +is"c IUOC;( los 0 ..! (d) 37!2R TIL Output. ] a. High 60 40 0 Low ,~ (e) 3712T Light ,?utput Pulses (transmitter phasing to 8.10). ~ 20 " 4 (0 Inputs to Z,. Continuous Opemting Time (khrs) High Low (g) 3712R TIL Output. FIGURE 4. LED Operating Life. FIGURE 3. Transmitter Phasing for Improved Noise Immunity. 4-17 10 Figure 5 shows the spectral response of the receiver. I. Provide a No Light input condition to the receiver. (This may be done with a cable connected to an OFF transmitter or by using an opaque cap and no cable.) The TTL Out may now be changing state due to normal receiver noise. 2. Adjust R, for an equal number of high and low states at the TTL Out. This may be done by observing the TTL Out on an oscilloscope or an AC voltmeter. When the voltmeter is used adjust R, for a peak. reading. 100 75 ~ ~ 0 ~ b) Eliminate spurious outputs when the transmitter is idle for long periods of time and the threshold voltage decays to the noise floor of the receiver. Adjustment procedure for maximum receiver sensitivity: 50 '" .~ ]I ~ Adjustment procedure to eliminate spurious outputs: I. Provide a No Light input condition as previously described. 25 2. Adjust R, until the voltage at the TTL Output remains at a low state. (Note: More offset gives better BER, but requires a higher input level to the receiver.) Wavelength (om) FIGURE 5. Receiver Response. 3712R (Bottom View) The Analog Output terminal of the 3712R is the output of the linear amplifier A,. The voltage at this pin is a function of the input power to the receiver. As such, it makes an excellent diagnostic point for testing the fiber optic cable. Monitoring the Analog Output terminal gives a relative measure of cable loss at the transmitted wavelength and a direct measurement of receiver signalto-noise ratio when the transmitter is off. --. Threshold Adjust ,---- ---- Digital Common • • TTL Output 7.5kn~ R'~ _____-~c.:;. , ' I : I---!~~. ·. . . .fRIli : 25kn I : 1. __ 1 ~:::~n· ~~~~~. 0 Optional Receiver Threshold Adjustment The circuit in Figure 6 is used to add a DC bias voltage to the comparator AJ. This bias voltage may be used to: a) Adjust the receiver for maximum sensitivity, or FIGURE 6. Optional Threshold Adjustment. CABLE SELECTION The '37l2T and 3712R with the AMP Optimate Single Position Fiber Optic Cable Connector System can be used with a wide variety of cable types. The choice of a cable type for a particular application of course depends upon the details of that application such as link environment, link length, cable performance characteristics, and cable cost. ENVIRONMENTAL CONSIDERATIONS The mechanical stresses, environmental temperature extremes, and exposure to harsh chemicals must be considered when choosing a particular cable. Such things as jacketing method and the type of added strength members, see Figure 7, determine a cable's mechanical FIGURE 7. Typical Step Index Fiber Optic Cable Construction. 4-18 DETERMINING LAUNCHED POWER Once the mechanical characteristics and cable type have been chosen, it becomes necessary to analyze link performance with various cables. First, analyze the power launched into a particular cable from the transmitter. An advantage of the 3712T over most other fiber optic transmitters is the way output power has been specified. The 3712T specifies the actual power launched into the cable. Thus such complicated effects as LED output power and emission profile, cable numerical aperture (NA), and spacing between the LED transmitter and the cable have all been taken into consideration for the user. For cable other than those specified in the Electrical Specifications Table, the power launched may be determined by: and environmental capabilities. Table I is a list of representative cable manufacturers who make cables compatible with the 3712T/ R. See Table II for details of cable performance. T ABLE I. Representative Cable Manufacturers. BELDEN (312)232-8900 AMP (CONNECTORS) (717)564~IOI AMP, Inc. 449 Eisenhower Blvd. Harrisburgh, PA 17105 Belden Corp. 2000 South Batavia Geneva, II 60 134 DUPONT (CROFON) (302)774-6595 E.1. DuPont De Nemours PP & R Dept .• Room 0-12086 Crafon Fiber Optics Group Wilmington. DE 19898 DUPONT (PIFAX) (302)774-7850 (302)774-6339 E." DuPont De Nemours Plastic Products & Resins Wilmington, DE 19898 GALILEO (617)347-9191 Galileo Electro-Optics Galileo Park MAXLIGHT (602)269-8387 Maxlight Optical Waveguides. Inc. 3035 N. 33rd Drive Phoenix. AZ 85017 Sturbridge. MA OlSJ8 VALTEC (617)835-6082 PI (Fiber 2) = PI (Fiber 1)[(0,)'/(0\)'], where P L (Fiber 2) is the power launched .into the unspecified cable whose core diameter is 02 and P L (Fiber I) is 2.5ILW, minimum, (3.5ILW, typical) the core diameter 0\ of Fiber I is 1016ILm. Valtec Corp. Fiber Optics Div. West Boylston. MA 01583 DETERMINING CABLE TYPE There are three types of optical fibers to choose from: Step Index, Single-Mode, and Graded Index. Each type specifies the profile or variation of the fiber's index of refraction as a function of radial distance from the fiber's center. In a fiber with a step-index profile, the refractive index undergoes an abrupt change (step) in value. This step is caused by the sudden change in the index of refraction between the fiber's core and a surrounding annular cladding, as shown in Figure 8. NUMERICAL APERTURE Numerical aperture differences between fibers will somewhat modify the results obtained by the equation just discussed (e.g., higher N A will increase coupling efficiency, thus increasing the power launched into the cable). However, this effect is minimum for the 3712T because of the physical relationship between the LED transmitter and the fiber optic cable. DETERMINING MAXIMUM CABLE LENGTH Once PL and LA are known, the maximum cable length maybe determined. First the loss margin is found, LM(dB) = 10 log (PL/ PIn min). Step-index fiber with a core diameter of 200ILm or larger is recommended for use with the 3712Tand 3712R. Stepindex fiber offers the best compromise between core diameter, bandwidth, coupling loss, and cost. Singlemode and graded-index fiber is not recommended due to their small core diameter. The wide bandwidth characteristics of these cables are not needed. For the 3712T with CROFON 1040 1016ILm fiber, P L 10-9 BER. Thus, LM == 10 log (2.5ILW/5nW) = 10 log 500 = 27dB. Then Xmax , the maximum cable length that will just present PIn min to the transmitter is found Xmu = [LM(dB)]/[LA(dB/m)]. For CROFON 1040 at AT = 670nm, LA Xm>x = 27dB/l.3dB(m) = 21 meters. f::ne ( Angle .-L = 2.5ILW and for the 3712R, PIn min = 5nW worst case for = 1300dB/ km If this length is too short, a cable with a larger diameter (larger PLl or less attenuation (smaller LA) must be used. 8' Half Core (nl) Acceptance Cone .".:::: ......- Table II shows the link performance for several different cables . ~ _Optically-..:t'- ·Waveguided '"'::t-""::. Light - ,-....... -- ........ DETERMINING MINIMUM CABLE LENGTH Short cable lengths with large core diameter fibers may cause some receiver slew rate limit which will appear as duty cycle distortion. Limiting the power coupled into the receiver from the cable will prevent this from occurring. The minimum cable length may be determined for a FIGURE 8. Step Index Fiber. 4-19 TABLE II. Link ,Performance vs Various ea.ble Types. ' Cable' Characteristics' 'Ca'ble l'iber(l) and Core Oia. Part Number .!pm) (pm) 200 ,300 400 1016 368 368 .'. 1016 200 200 GALILEO 3000LC-P 'MAXLIGHT KSC200A KSC200B VALTEC MD-PCIOO Manufacturer BELDEN 220001 221001 Dia. , Cable Dia. (mm) U(2) at 670nm , Link' Performance Material P,. NA (pw) min typ min typ X Mo, (meters) min typ (dB/km) LM (dB) Recommended AMpTM Connector 3.8 3.8 12 12 0.35 0.35 0.10 0.22 Ocl4 0.31 12.9 16.4 18.3 21.8 1073 1366 1526 1820 Contact Belden 1300 600 600 2.2 1.9 1.9 2.4 2.4 330 43 33 0.53 0.53 0.53 0.4 0.4 2.50 0.33 0.33 0.10 0.10 3.50 0.46 0.46 0.14 0,14 27.0 18.2 18.2 12.9 12.9 32:4 23.6 23.6 18.3 18.3 21 36 55 299 390 25 47 72 426 555 530$30-2 530530-9 530530-9 1-530530-2 1-530530-2 204 245 2.2 100 0.48 0.10 0.14 13:0 18.5 130 185 530530-9 200 200 300 300 2.4 2.4 8 27 0.39 0.39 0.10 0.10 0.14 0.14 12.9 12.9 18.3 18.3 1609 477 2289 678 (3) (3) 250 430 4.1 14 0.30 0.15 0.21 14.8 20.3 1058 1447 530530-9 440 Contact Belden DUPONT Crofoo 1040 PIFAX-PI40 PIF AX-PIR 140 . PIFAX-SI20 PIFAX-SI20 (type 30) i 400 400 500 I) Fiber Diameter =Core Diameter'plus Cladding. 2) Conversion Factors: 100",m = 0.003937 in: IOOOm = 3281 ft. 3) Sold as terminated cable. specific cable by calculating the power launched into it as previously done using: PL (Fiber 2) = PL (Fiber I)Bnd /(DJ)2]. The typical value of PdFiber I) should be used since this will give the most power into the receiver and result in the desired minimum cable length. For example, consider a cable .with a 368J.1m core diameter and a cable loss of. 330dB/ km. The power launched into the cable by the transmitter is: PL (Fiber 2) = 3.5p.W [(368p.m)' /(1016J.1ml] PL (Fiber.2) = 0.46J.1W., The minimum loss margin is found using the typical power launched into the cable and the maximum input to the receiver which is 0.2J.1W for the 3712R. LM = 10 log [(PL (Fiber 2)/ PIn m..)] LM = 10 log [(0A6J.1W /0.2J.1W)] = 3.6dB. The minimum cable length for the specific cable in this Xmin = LMmin/ LA example is: Xmin = 3.6dB/0.33dB/ m = II meter~. ' If this minimum cable length is not short enough for a particular application, use a smaller core diameter cable or a cable with higher loss. DEFINITION OF TERMS ACCEPTANCE ANGLE The critical angle, measured from the core centerline, above which light will not enter the fiber. Itis equalto the half-angle of the acceptance cone. BAUD The number of signaling elements or data bits per second. BIT ERROR RATE The rlltio of incorrect bits to total bits in a received data stream. CLADDING A sheathing or cover ,of a lower refractive index material in intimate contllct with the core of a higher refractive index material. It'serves to provide opticlIl insulation and protection to the total reflection surface. CORE The high refractive index central ~aterial of an optic~1 fiber through which a light is propagated. . , FIBER The materialpath along which light propagates; a single discrete optical transmission element consisting of the core and its c1l1dding. LA Attenuation of a fiber lit a specific wavelength. LM' Loss ,margin. This is t/Ie difference in transmitted power and received power in decibels. NUMERICAL APERTURE (NA) See text. NRZ Nonreturn-to-zero is the term for a transmission code in which the signal does not periodically return to zero. , PL Actual power launched into a specific cable. RZ Return-to-zero. Transmission code for a signal which periodiCally returns to zero. RESPONSIVITY The spectral response of the receiver at the output of the radillnt flux-to-voltage converter. Given in millivolts per nanowatts. 4-20 TYPICAL ApPLICATIONS The 3712T I R Fiber Opti~ Data Link solves such data transmission problems as crosstalk, ringing, and echos. Electromagnetic radiation interference is avoided when using a fiber optic data link in high noise environments. Lightning damage to cables and connected equipment can be eliminated where fiber optic cables replace metallic conductors. In' refineries and chemical plants which have explosive atmospheres, sparks from shorted electrical cables are eliminated by the fiber optic cable an inherent safety feature. Figures 9 thru II illustrate the use of the 3712 transmitter and receiver to replace conventional metal conductor cables. + Computer FIGURE 10. RS232 Compatible Fiber Optic Data Link. FIGURE II. Remote Transducer Readout. 4-21 3713T 3713R BURR-BROWN@ 113191 High Sensitivity - Medium Speed FIBER OPTIC TRANSMITTER AND REC~IVER I FEATURES APPLICATIONS • LOW COST • HIGH SENSITIVITY • TTl INPUT/OUTPUT • IMMUNITY TO ELECTROMAGNETIC INTERFERENCE • NO EXTERNALLY RADIATED SIGNAL • ELECTRICAL ISOLATION • DUTY CYCLE INDEPENDENT • DoC TO 70°C OPERATION • INDUSTRIAL/PROCESS CONTROL • REMOTE INSTRUMENTATION SYSTEMS • POWER PLANT CONTROL • HIGH VOLTAGE OR ELECTROMAGNETIC FIELD RESEARCH • FACTORY DATA COllECTION • SECURITY SYSTEMS ·INTRINSIC SAFETY DESCRIPTION converts optical pulses to TTL level outputs with a receiver sensitivity of 15nWand data rates to 250k baud NRZ. An integral optical connector on both the 3713T and 3713R allows easy interfacing between modules and optical fiber without problems of source/fiber/ detector alignment. The metal packages of the 3713T and 3713R provide immunity to electromagnetic radiation and direct printed circuit board mounting with no additional heat sink required. The 3713T and 3713R when connected by iI suitable fiber optic cable form a 250k baud NRZ fiber ~tic data link capable of operation to 1.7km. . The 3713T fiber optic transmitter is an electrical to opticaf tranducer designed for digital data transmission over single fiber channels. Transmitter circuitry converts TTL level inputs to optical pulses at data rates from DC to 2M baud NRZ. The 3713R fiber optic receiver is an optical to electrical transducer designed for reception of digital data over single fiber channels. The receiver circuitry +VCC +VDD TTL INPUT TRANSMITTER PHASING 80 TIL OUTPUT 3713T TRANSMITIER ANALOG OUTPUT ANALOG COMMON DIGITAL COMMON 8180 Puwlr AdlUlI DIGITAL COMMON THRESHOLD ADJUST Internllional Airport Indullrlal Park· P.O. Box 11400· Tucson. Arlzonl85734· Tel. 1Il02l 7411-1111 • Twx: 9111-952·1111 • Cable: BBRCORP • Telex: 66-6491 I'IlS-418 4-22 SPECIFICATIONS ELECTRICAL at TA = +25DC, +Voo"; 5VDC, ±Vee = 15VDC and no threshold trim unless otherwise noted. Coupled into: O.53NA Fiber 0.53NA Fiber 200p.m, 0.4NA Fiber 1016~m, 368~m, 15 3.5 1.5 20 660 40 75 Oto 2M p.W p.W dB nm nsec nsec Baud -1.6 -1.6 -0.8 DC to 100 -2.6 -2.7 -1.4 1.7 1.2 x 10-13 1.3 DC to 125 mVlnW mVlnW mVlnW mm2 W/.JHz mV.rms kHz -10 0.7 1.6 -12 Output Power Adjustment Range(1) Wavelength Rise Time 10% to 90% Fall Time Bit Rate 9O'!b to· 10% ~W 10 1.5 0.7 Voltage Current Emitter On, with maximum output power Emitter On, with minimum ·output power Emitter Ofl Operating Responsivlty A = 940nm A = SOOnm A = 660nm Detector Active Area Noise Equivalent Power Output Noise Bandwidth Output Ollset 25DC 70DC A = 900nm, F = 10kHz, BW 10Hz to 10MHz -3dB Total Darkne.. RL Bit Rate(2) Duty Cycle(2) Sensitivity(3)(4) Propagation Delay Output Rise Time Output Fall Time Fan Out TIL Out "High" TIL Out "Low" = 1Hz = 2kO NRZ coding BER = 10-9, 100kB/Sec, A = 660nm, 25DC = 10-9, l00kB/Sec, A =66Onm, ODC to 70DC Light In, Digital Out Without external pull-up resistor Without external pull-up resistor Without external pull-up resistor Without external pull-up resistor Without external pull-up resistor No o to 200k 0 o to 250k 30 15 20 40 2.2 100 8 2 2.4 1.7 x 10-13 0.15 4 3.2 0.2 Low 10 Baud % nW nW ",sec p.sec p.sec Unit 0.4 ±15VDC NOTES: 1. Optical output power Is adjustable. See "AppMatlons Information" section. Optical qutput power is measured into an exit NA 01 0.24. 2. See "Applications Information" section regarding operation of Automatic Threshold Circuit. 3. May be improved with external threshold voltage trim. See "Applications Information" section. 4. Input should be limited to 1",W to avoid duty cycle distortion. 4-23 mVDC mVDC V V V VDC mADC ~ECHANICAL I· B '1 [I k '~ EI KC--" =H1 R r------ ~J- L -j\ i E~ ir I I. .1 I I , I U T L\ DIM AMpTM Optimate ',Single Position Fiber Optic Connector PI N 530570·1 5/16 - 32 NEF2A thread. Lead. in true position 1.610 1.650 40.89 3.020 7R -,. C .640 3.060 .680 D .038 .042 16.26 0.97 F :075 .095 1.91 G .200 BASIC .670 (3.8Imm) min. depth, 2 places in true position within .015' (.38mm)R .tMMC. 7? 17.27 1.01 2.41 5.08 BASIC .770 17.02 19.56 19.18 BASIC K .250 6.35 .350 8.89 L 2.200 BASIC 55.88 BASIC p .100 BASIC 2.54 BASIC A .275 .375 6.99 9.53 S .980 1.020 24.89 25.91 .315 6.99 8.00 .275 U' 4-40 thr.ad, .150' 41.91 I 77- .755 BASIC T Y ! MILLIMETERS MIN MAX A- H within .015' (.38mm)R at MMC at seating plane. INCHES MAX MIN B J NOTE: 1I [C= J -==t- o Order Number: 3713T 3713R .890 BASIC V .460 w .260 y 22.61 BASIC .500 .300 '1.68 6.60 12.70 20.19 21.21 .835 .795 7.62 PIN CONFIGURATION 37I3T (Bottom View) 3713R (Bottom View) r_!!~!"!I_A!j~.!. +V IlI) . R}*I ~ 7.SkO Transmitter. Phasinl ./10, Digital Common • ~ ? .. ------~~. I I I: TTl. Inpul • I • TTL Output +Vcc I ,------. L..~ : 1-' I 2" = 25kO L_J ' , I R ·For optional transmitter power adjustment. Analog • Common Analog. Output •• For optional receive,r threshold adjustment. APPLICATIONS INFORMATION THEORY OF OPERATION TransmlHer Operation A simplified block diagram of the 3713T transmitter 'is shown in Figure I. The input stage uses a Schmitt Trigger EXCLUSIVE OR Gate G, for noise immunity, and its logic is configured so the phasing of the transmitter is pinprogrammable. When the transmitter phasing terminal is connected to 60 the light output is in-phase with the digital input signal- the LED is on when the TTL Input is high. Connecting the transmitter phasing terminal to 6180 causes the reverse to happen - the LED is on for a digital low. Operating the 3713T with the transmitter phasing to 6'80 makes it possible to detect a break in the fiber optic cable when the data link is idle. This may be particularly useful in the transmission of asynchronous data with an idle state of a TTL low. Programming the phase of the 37l3T is discussed more in the "Receiver Operation" section. Amplifier A, and the current switch drive a light emitting diode (LED). r----------I . +VDIl I Current Switch .......- 0 -Adjust ------Power FIGURE I. 37 13T Transmitter. 4-24 DigitalCommon Optional Transmitter Power Adjustment 1------ The optical power output of the 3713T transmitter may be adjusted by controlling the resistance between the Power Adjust pin and Ground (see Figure 2). This controls t~e peak or "on" current in the LED as described by the equation ILED ... 0.65 + [lkO II (220 + R I )]. Excessive lead length should be avoided when using the external resistor, R I . I I I Light Flux Input I I ~ I +V 1m • ~~~~i:itter • ell" • TIl. Input • 8 1MI J R,=5r::f__ Power Adjust tp +Vl'( D .:Eb .........,................"."rl--1LJ Threshold ! 6--L-t Adjust IO ;: L___ __ _ ___ An~~!mon -Vn J Dilital Common Dlgital Common • FIGURE 3. 37I3R Receiver. hold technique the threshold voltage VT is subject to decay, as in Figure 4c, when light is removed from CR I. A No Light condition of approximately 1/2 second duration (a I baud data rate) can be used with no significant effect on noise immunity. If the light is left off indefinitely, the voltage at VT will drop to the noise floor and the TTL Output will be subject to normal noise pulse outputs, as illustrated in Figure 4d. The first light pulse received will then activate the Automatic Threshold Circuit. The initial transition at the TTL output may be uncertain for this first pulse, but after the first pulse activates the Automatic ThreShold Circuit there will be no uncertainty in the TTL output. FIGURE 2. 3713T Optional Power Adjustment. When the resistor is minimum the LED output is maximum and as the resistance is increased the LED output asymptotically approaches a minimum value. The relationships are shown in Table 1. T ABLE I. Transmitter Performance vs Optical Power Adjustment. RI(I!) 1r./;/i(mA) % max Power Reduction (dB) 0 10 25 50 100 500 1000 30 20 15 10 6 1.9 1.3 0.65 100 67 SO 33 20 6 4 2 0 -1.7 -3 -5 -7 -12 -14 -17 ~ TTL Output I Normally a link would be operated with RI =0. For short lengths where the cable loss is low, the LED current may be reduced to extend the LED's life .. Receiver Operation A simplified block diagram of the 3713R receiver is shown in Figure 3. Input light is converted to a current by the PIN photodiode CR I which is connected in the photovoltaic mode for maximum sensitivity. A low bias current FET input current-to-voltage converter transforms the diode current into a voltage (Y A) which is further amplified by A2 and presented to comparator A3 as YR where it is compared to the threshold voltage Yr. For maximum noise immunity it is desirable to have the threshold voltage set to a value corresponding to a level halfway between the high value and low value of input regardless of the actual light level at the input as shown in Figure 4c. In the 3713R this is accomplished by a peak detector type Automatic Threshold Circuit. A pulse of light input causes a voltage pulse at YB which is st~red in the Automatic Threshold Circuit, divided in half, and supplied to the comparator as the threshold input YT • Thus, YT is a voltage corresponding to the midpoint of the Light and No Light conditions of the diode. Since the Automatic Threshold Circuit uses a capacitive 4-25 It should be noted that the polarity of the transmitter is pin-programmable. Thus, in an application, where there are idle states that exceed 1/2 second (such as ASCII data transmission) the trllnsmitter may be programmed such that the idle state corresponds to a Light On condition, see Figure 4e. This will keep the automatic threshold activated and there will be no first pulse ambiguity, as shown in Figures 4f and 4g. Connecting the transmitter phasing to 0 180 has the disadvantage of keeping the LED on during idle periods. LED optical output is a function of operating time as shown in Figure 5. High . (a) TTL Input to 371H. Low High..., ..., ..., ,.., L..J L..J L - - - - I Low..J (b) 3713T Light Output Pulses (transmitter phasing to flu). L V.=High~ -(e) Inputs to A1 • VI _ __ _ _ ---, V8= Low High (d) 3713R TTL Output . . . . , ..., r-1 Low.J L.J L.......JUUIJ L L..J nn.,.., FIGURE 4. Transmitter Phasing for Improved Noise Immunity. 100 ~ ... 11 11 80 0 ...~ 60 Q ] lS. 0 T, +2S·C r~N 100% r!,~·=1M ax 40 .~ ~ 20 "" 10 Continuous Operatins: Time (khrs) FIGURE 5. LED Operating Life. Figure 6 shows the spectral response of the receiver. loor------,-------r----~~----_, ~ ~ ...C C Q "".~ a) Adjust the receiver for maximum sensitivity, or b) Eliminate spurious outputs when the transmitter is idle for long periods of time and the threshold voltage decays to the nOise floor of the receiver. Adjustment procedure for maximum receiver sensitivity: I. Provide a No Light input condition to the receiver. (This may be done with a cable connected to an OFF transmitter or by using an opaque cap and no cable.) The TTL Out may now be changing state due to normal receiver noise. 2. Adjust R, for an equal number of high and low states at the TTL Out. This may be done by observing the TTL Out on an oscilloscope or an AC voltmeter. When the voltmeter is used adjust R, for a peak reading. Adjustment procedure to eliminate spurious outputs: I. Provide a No Light input condition as previously described. 2. Adjust R, until the voltage at the TTL Output remains at a low state. Note: More offset gives better BER, but requires a higher input level to the receiver. so ! Waveicngth (om) 3713R (Bottom View) FIGURE 6. Receiver Response. ,_!!~~!,_A,!fj!,~. The Analog Output terminal ot the37l3 R is the output of the linear amplifier A,. The voltage at this terminal is a function of the input power to the receiver. As such. it makes an excellent diagnostic point for testing the fiber optic cable. Monitoring the Analog Output terminal gives a relative measure of cable loss at the transmitted wavelength and a direct measurement of receiver signalto-noise ratios when the transmitter is off. Digital C,ommon • • TTL Output 7.SkD~ R, I -Vee .. -------. ' : : I ___ I I I I I I '-fR.,I 2nD , • _-, !~c.!:. Analo• • Common A••Io• Output • D Optional Receiver Threshold Adjustment The circuit in Figure 7 is used to add a DC bias voltage to the comparator A,. This bias voltage may be used to: FIGURE 7. Optional Threshold Adjustment. CABLE SELECTION The 3713T and 37l3R with the AMP Optimate Single Position Fiber Optic Cable Connector System can be used with a wide variety of cable types. The choice of a cable type for a particular application, of course, depends upon the. details of that application; link environment, link length, cable performance characteristics, and cable cost. considered when choosing a particular cable. Such things as jacketing material and the type of added strength members, see Figure 8, determine a cable's mechanical and environmental capabilities. Table II is a list of representative cable manufacturers who make cable compatible with the 37l3T / R. See Table III for details of cable performance. ENVIRONMENTAL CONSIDERATIONS The mechanical stresses, environmental temperature extremes. and exposure to harsh chemicals must be 4-26 TABLE II. Representative Cable Manufacturers. AMP (CONNECTORS) (717)564-0101 AMP. Inc. DETERMINING LAUNCHED POWER Once the mechanical characteristics and cable type have been chosen, it becomes necessary to analyze link performance with various cables. The first analysis to make is the power launched into a particular cable from the transmitter. . An advantage of the 3713T over many other fiber optic transmitters is the way output power has been specified. The 3713T specifies the actual power launched into the cable. Thus, such complicated effects as LED output power and emission profile, cable numerical aperture (NA), and spacing between the LED transmitter and the' cable have all been taken into consideration for the user. For cables other than those specified in the Electrical Specification Table, the power launched may be determined from the curve in Figure 10. BELDEN (312)232-8900 Belden Corp. 2000 South Batavia 449 Eisenhower Blvd. H.rnlbursh. PA 17105 Gen.... 1160134 DUPONT (CROFON) (302)774-6595 DUPONT (PIFAX) (302)774-7850 (302)774-6339 E.I. DuPont De Nemoun Plastic Products &: Resins E.I. DuPont De Nemoun PP It R Dept .• Room 0-12086 Crofon Fiber Optics Group Wilminston. DE 19898 Wilminlton. DE 19898 GALILEO (617)347-9191 MAXLIGHT (602)269-8387 Maxlight Oalileo Electro..()ptics Galileo Park SturbridI!C. MA 01Sl8 Optical Wavc8uides. Inc. 3035 N. 33rd Drive Phoenix. AZ 8SO 17 VALTEC (617)835-6082 Valtee Corp. Fiber Optics Div. West Boylston. MA 01583 100 ~~~~\ ~IO .3 ~ 1/ 0 0.. )'f'/ V " j 1.0 FIGURE 8. Typical Step Index Fiber Optic Cable Construction. // II, DETERMINING CABLE TYPE There are three basic types of optical fibers to choose from: Step-Index, Single-Mode, and Graded-Index. Each type specifies the profile or variation of the fiber's index of refraction as a function of radial distance from the fiber's center. In a fiber with a step-index profile, the refractive index undergoes an abrupt change (step) in value. This step is caused by the sudden change in the index of refraction between the fiber's core and a surrounding annular cladding, as shown in Figure 9. 0.1 0 L Acceptance Cone /~ ",,~~_Lighl_ .............. .... ....... Cladding (n,) FIGURE9. Step Index Fiber. 600 800 1000 1200 1400 DETERMINING MAXIMUM CABLE LENGTH Once PL and LA are known, the maximum cable length may be obtained. First the loss margin is found by, LM(dB) = 10 log (PL/ PI. m;.). For the 3713T with CROFON 1040 I016~m fiber, PL = . IO"W and for the 37I3R, PI. m;. = 30nW worst case for 10-9 BER. Thus, LM = 10 log (I0~W/30nW) = IO log 333 = 25dB. Then XMax, the maximum cable length that will just present PI. m;. to the transmitter is found by, XMax = [LM(dB)]/[LA(dB/m»). For CROFON 1040 at AT = 670nm, LA = 1300dB/km XM.. = 25dB/ I.3dB(m) = 19 meters. ...,..,., ~ _Optically_ - . _ Waveguided 400 FIGURE 10. Launched Power vs Core Diameter. CI.dding (n,) COle (n,) 200 Core Diameter (JIm) Step-index fiber with a core diameter of 200~m or larger is recommended for use with the 3713Tand371JR. Stepindex fiber offers the best compromise between core diameter, bandwidth, coupling loss, and cost. Singlemode and graded-index fibers are not recommended due to their small core diameter. The wide bandwidth characteristics of these cables are not needed. tne ~\(\\"'O'" VV" 'l! g B H.lf ( Angle - ...... I--'" .... If this length is too short, a cable with a larger diameter (larger Pc) or less attenuation (smaller LA) must be used. Table III shows the link performance for several different cables. DETERMINING MINIMUM CABLE LENGTH Short cable lengths with large core diameter fibers may 4-27 cause some receiver slew rate limit whichwilhppear as. duty cycle distortion. Limiting the power coupl~d il\to the receiver frqm the cable .wiIIprevent this from power lau'nched into the cable and the maximum input to the receiver which i~ IJ.lW fortlle 3713R. . LM = 10 log (PL/ Pin m.. ) LM = 10 logc(3.5J.1W/ IJ.lW) = 5.4dB. The minimum cable length for the specific cable In this example is: XMin = LMMin/LA XMin(5.4qB/0.33dB/m)= 16 me~ers. If this minimum cable length is too long for a particular application. use a smaller core diameter cable. a cable with higher loss. or the power launched into the cable may be reduced as described in the "Optional Transmitter Power Adjustment" section. occurrin~. The minimum, cable length may be determined for a specific cable by calculating the power launched intoitas previously done using the typical curve from Figure 10. The typical value of launched powers!1()uld be used since this will give the most powerinto the receiver, resulting in the desired minimum cable length. As an example. consider, a'cabl<; with a 368J.1m core diameter and a cable loss. of 330dB/ km. ,The. typical power launched into the cable from Figure 10 is 3.5J.1W. The minimum loss margin is found' using the typical TABLE Ill. Link Performance vs Various Cable Types. Cable ManufactuRr' and Part Number BELDEN 220001 221001 Core Oia. ("m) , Cable Characteristics U(2) Fibedl) Cable Materia' NA Link Performance LM Xl<.t;o, (dB) (meters) ("W) min typ min typ min IYP PI. Ree'ommended AMplM Oia. Oi•. at 660nm (I'm) (mm) (dB,km) 200 400 ·300 440 3.8 3.8 12 12 0.35 0.35 0.7 1.1 1.5 2.6 14 16 20 22 1140 1304 1667 1866 Contact Belden Contact Belden IQI6 368 368 200 200 1016 400 400 600 600 2.2 1.9 1.9 2.4 2.4, 1300 500 330 43 33 0.53 0.53 0.53 . 0:4 0.4 10 1.5 1.5 0.7 0.7 15 3.5 3.5 1.5 1.5 25 17 17 14 14 30 24 24 20 20 19 34 51 318 415 23 4.7 465 606 530530-2 530530-9 530530-9 1-530530-2 1-530530-2 204 245 2.2 100 0.48 0.7 1.5 14 20 137 200 530530-9. 200 300 200 300 2.4 2.4 8 27 0.39 0.39 0.7 0.7 1.5 1.5 14 14 20 20 1710 50.7 2500 741 (3) 250 430 4.1 14 0.30 0.9 2.0 15 1055 1518 5j053O-9 Connector " . DUPONT Crofon 1040 PIFAX-PI4O PIFAX-PIRI4O PIFAX-SI20" PIFAX-SI20 (type 30) GAll LEO 3OOOLC-P MAXLIGHT KSC200A KSC200B VALTEC MD-PCIOO I) Fiber Diameter = Core Diameter plus Claddmg. 2) Conversion Factors: IOOpm - 0.003937 1!1: IOOOm ACCEPTANCE ANGLE ft. 3) Sold as termmated, c;ab~. LA Attenuation of a fiber at a specific wavelength. LM Loss margin. This is the difference in transmitted power and received power in decibels. NRZ The ratio of incorrect bits to total bits in a received data stream. CLADDING Nonreturn-to~zero is the term for a transmission code in which the signal does not periodically return to zero. A sheathing or cover of a lower refractive indelS. material in intimate contact with the core of a higher refractive index material. It serves to provide optical insulation and protection to the total reflection surface. CORE PL Actual power launched into a specific cable. RZ Return-to-zero. Transmission code for a signal which periodically returns to zero. ' The high refractive index central material of an optical fiber through which a light is propagated. FIBER The material path along which light propagates; a single , discrete optical transmission element consisting of the \ core and its claddi'ng. \ 4-28 \ (3) DEFINITION OF TERMS The critical angle. measured from, the core centerline. above which light will not enter the fiber. It is equal to the half-angle of the acceptance cone. BAUD The number of signaling elements or data bits per second. BIT ERROR RATE !v 21 = 3281 72. RESPONSIVITY The spectral response of the receiver at the output of the radiant flux-to-voltage converter. Given in millivolts per nanowatts. TYPICAL APPLICATIONS metallic conductors. In refineries and chemical plants which have explosive atmospheres, sparks from shorted electrical cables are eliminated by the fiber optic cable an inherent safety feature. Figures II thru 13 illustrate the use of the 3713 transmitter and receiver to replace conventional metal conductor cables. The 3713T / R Fiber Optic Data Link solves such data transmission problems as crosstalk, ringing, and echos. Electromagnetic radiation interference is avoided when using a fiber optic data link in high noise environments. Lightning damage to cables and connected equipment can be eliminated where fiber optic cables replace + FIGURE II. CMOS Compatible Fiber Optic Data Link . . Computer Computer Terminal FIGURE 12. RS232 Compatible Fiber Optic Data Link. FIGURE 13. Remote Transducer Readout. 4-29 BURR-BROWN® 3714T IElElI Analog Input VOltage-to-Frequency FIBER OPTIC TRANSMITTER APPLICATIONS FEATURES. • REMOTE INSTRUMENTATION SYSTEMS FROM LOW LEVel SENSORS • INDUSTRIAL PROCESS CONTROL • POWER PLANT CONTROL .• MEDICAL MONITORING • HIGH VOLTAGE OR ELECTROMAGNETIC FIELD RESEARCH • LOW COST ANALOG·TO·DlGITAL CONV.ERSION • FACTORY DATA COLLECTION • SECURITY SYSTEMS -INTRINSIC SAFETY • ANALOG SIGNAL CONDITIONING Instrumentation amplifier Input CMR of 106dB min at G= 1000 Input Impedance of 1010n • • • • • • • EXCELLENT DC LINEARITY (±O.05% max of FSRI LONG DISTANCE OPERATION (up to 1.7kml FREQUENCY MODULATED TRANSMISSION IMMUNITY TO ELECTROMAGNETIC INTERFERENCE NO EXTERNAL RADIATED SIGNAL ELECTRICAL ISOLATION SELF·CONTAINED DESCRIPTION The 3714T is a versatile. self-contained. analog input fiber optic transmitter module. When connected to a suitable fiber optic cable and receiver. it is capable of transmitting analog input signals as small as IOmV full scale for a distance up to 1.7km with a typical linearity error of±O.005%. In addition. it will transmit a CMOS logic signal at data rates from DC to 2M baud NRZ. The 3714T contains. a precision instrumentation amplifier (IA). voltage-to-frequency converter (VFC). and fiber optic transmitter section (FaT). The IA provides high input impedance of .lO wn. CMR of I06dB. programmable gain up to 1000V, V. and level shifting for ±5V max bipolar signals. The VFC linearly converts input voltages between 0 and + IOV to an adjustable pulse train ranging from 0 to 50kHz. A DC input produces a fixed frequency output and a dynamic analog input produces a frequency modulated output. The FaT drives the output LED at a resistor programmable power level. A n AM plM optimate optical connector on the metal case (EM I shielding) allows easy interfacing to a fiber optic cable without alignment difficulty. In18rlllllooll Airport Industrial Park· P.O. Box 11400· Tuclon. Arizona 85734· TIl. 16021 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP· Telex: 66.6491 PIlS445 4-30 SPECIFICATIONS ELECTRICAL TA =+25"C, ±Vee =15VDC Inpu~2) Unipolar) Bipolar Gain Range Input Impedance Differential Common-mode Input OIfset Voltage Input OIfset Drill Biaa Currenl Bias Drill Offset Current Linaarity Time(3)10 .OI~of FSR o 10 +5 1000 -5 1010 113 1010 113 ±25 ±12oo/G, ±10 ±0.3 ±10 DC to 80Hz, G = 1 DC to 60Hz, G = 10 DC to 60Hz, G = 1000 ±50 ±r 400/G I ±2 ±(20/GI ±30 ±30 nA nAi"C nA ~of p-p FS ~sec 150 ~sec ~sec 80 96 90 106 dB dB 106 110 ±0.002 ±D.OOS 0.01 ±75 ±1 to within linearity spac ~V ~Vi"C 1000 0.01 Hz S F S 10kHz O.IHzSFS50kHz Output Power Adjust Range(5) Wavelength Rise Time Fall Time Bit Ratele) llil pF llil pF ±D.002+1(J'~ 100 G=5 G=loo G = 1000 V V VN ±5 ±0.01 ±0.05 ±D.05 ±175 ±4 %ofFSR %ofFSR %ofFSR %ofFSR %of FSR/% ppml"C ppml"C 1 pulse of new frequency plus 11l5eC 101~m, O.53NA 368pm, O.53NA 10 1.5 ~m,O.4NK 0.7 30nm spactral half width 10% to 90% 90% to 10% 15 3.5 1.5 ~W 17 660 dB nm nsec nsec baud 50 80 Ot02M ~W ~W %Vee %Vcc V mADC mADC mADC LED on, max power LED on, min power LED off DC DC NOTES: 1. Total Transfer Function is adjustable and is nominally 5kHz/volt. 2. IA capable of ±10V input. VFC limited to 0 to +IOV input. To convert bipolar illPula to unipolar the IA reference is sMted. 3. For low IA gains VFC is predominant for settling. 4. Output power specified is that coupled into three cables shown. Optical output·power is measured into an exit Numerical Aperture INA ,'of 0.24. 5. Output is adjustable, _ Application Information sec~on. . 6. Bit rate refers to spaed of the transmitter In response to a. digital input. 4-31 MECHANICAL • I" II [I J K ..- -I INCHES ""',""""" ....... ~-'----- DIM' Mating Connector 2801MC may be uud. TOP VIEW 5118 -32 NEF-2A thread ~ NOTE: 1. Leads in true position within 0.015" (38mm) Rat MMC at seating plane. RLIH 8 .-6-.-'-!-~-6-A-!-17 I I I I I " I I II l L ---1 -I- 0 - - - I --- l1li "~,, ~ .0_0 8 II1II _....fV I Pin numbers shown , I I !I I I p.~LuJ -----.- I \. A 1.610 1.660 40.8~ 4;.91 3.020 3.060 76.71 77.72 C .880 16.26 17;27 C .640 .038 .042 .D.9!, 1.07 F .075 .096 1.91 2.41 G .200 BASIC H .670 J .365 BASIC 6.08 BASIC .770 19.9_ 9.02 BASIC 17.02 6.35 II.lIL 16.24 BASIC L .260 .360 .600 BASIC p .100 BASIC 2.D4 BASIC R .166 .266 4.19 8.73 s .980 1.020 24.89' 25.91 T .275 6.99 8.00 u v .890SASIC 22.61 BASIC .460 .500 ".68 W y .260 .300 6.60 7.62 .795 .836 20.19 21.21 J .315 12.70 PIN DESIGNATIONS for reference onlv. Numbers are not marked on package. 0 ___ MILLIMETE.8L "MIN MAX MAX 8 K =t", I~UU~UUUUUUUUU~lD AMpTM Optimale Fiber Optic Connector MIN 1.-Vee 2. Logic. 3.lntOut 4. VFC'n 5. VFCs.J. 6.IAout 4 - 40 thread. 0.015-13.81 mm I min. depth 2 places In true position within 0.015- l38mm 1 , RatMMC. , 7.+Vin 8. RO B.RG 10.-Vln 11.Vrof 12.Commcn 13. Pulae width 14. Fout 15; Fin 16.+Ver. 17. Pwr Adi TYPICAL PERFORMANCE CURVES RELATIVE OUTPUT POWER VS CURRENT SETTING RESISTOR o OUTPUT POWER VS TEMPEMTURE Ilaunched into O.25NA. 2OO,.m fiber! r-... 0.05 1.8 r-.. ["'0. ~ 1.6 I " 0 ±15V Supplies i i " 10 100 lK R86istor (pin 1711111 _~.II"!!lPlitude~n'!l!!1:7 IIIllI 111111 111111 -3 r- 111111 111111 111111 Il1!III[ I IllIIlli" 111111 To ;;;:'~armo~i~'Distortion -12 o 10K ""'~ , piles I I 10 20 30 40 50···60 remparaturelOCI 120 7 0.02 ':5 0.01 o 6 ~ 70 H-HItIHrHillI-;;MllflII-tHflIII--t+IIIII-tliHI 3 =~ 50 H-HlihillfllllFr-l-Hlllll-tHflIII--t+I!II-tlH 100 lk 10k Input Frequency (Hz I lOOk 10 20 30 40 50 ~ 60 . 70 Temperature 1°C) . OUTPUT PULSE WIDTH VS . EXTERNAL ONE-8HOT CAPACITANCE lK ~ I ~ 1/ / 60 t+rtIIHt.+f!Hlll-tHlHIH'+f!HHHHI g 40 HfYHfHlH+fHfIH+fHfIH+fHfH-HIIII ~30""'!fIIIl-lrHilill-l-HllII-tH.-t+I!II-+liHI .!!' , rn 20 H-HttIH-HttIII-+-HlllII-+-HIIIH-HItIH+ItIII o ./ oil 8OH-HttIH+llIH-HIIIH ~ 2 .S! 110 t+Httllt-tirtIIHt-ttllll"9tHtllt-ffi.+ttHi 4 2 g0.03 110 I+H!IIII-+IfI!IIII-+I#III4 100 1-+I-I!III-+H!III-++Hl1II-+ 8 5 '! ~ :I SIGNAL TO NOISE RATIO VS FREQUENCY Igain = 5kHzlVI-n_-n'lllll -15 -18 10 +lOVSu 1.0 BANDWIDTH AND DISTORTION OF VFC 12V. POP. sinUSoid on +9VDC 1 I o I:- w ,,~ 0 1.2 5 SJ..,lfic!lIlcn Lmit IL "" .............. ... 1.4 '" ~ 0.04 ~ i o LINEARITY ERROR VS TEMPERAJuRE 2.0 10 t+H!ttIHtHlllt+f!Ht-tHllIII-I'+f!HHHtII 0 L..J.;Wlllu.l.WII....lJ.lIILJ.I.IIILJWIIIL.LJ.IIIII 00.1 10 100 lK 10K lOOK Output Frequency I Hz 1 4-32 10 0.001 , 0.01 0.1 Capacltancalpln 13 to Commonll,.FI connections and external components for a usahle transmitter circuit. THEORY OF OPERATION The block diagram of the 3714T is on the front page of this data sheet. All circuits are pretested and compatible. The precision instrumentation amplifier will accept a differential analog signal input through pins 7 and 10 and produce a single-ended output at pin 6. This section contains low drift. low noise. monolithic operational amplifiers in a three-stage arrangement. The instrumentation amplifier has the advantages of high input impedance (IO,on II 3pF). high common-mode rejection (106dB at G = 1000). low offset voltage (25/lV). adjustable gain up to 1000. and adjustable reference to handle unipolar and bipolar inputs. For further detail see the data sheet on the Burr-Brown 3630AM. The VFC section is a monolithic voltage-to-frequency converter which produces a digital pulse train output at pin 14 with a repetition rate directly proportional to the analog input voltage level at pin 4. The output frequency is initially set at 50kHz full scale by an 820pF capacitor and can be decreased by adding capacitance at pin 13 to Common. pin 12. This capacitor changes the pulse width of a one-shot which controls the direction and duration of a ramping voltage (see Typical Performance Curves). The ramp is produced by an operational amplifier integrator with a nominal capacitor ofO.002/lF. The rise and fall depends on this capacitor in addition to the resistor connected between pin 4 and pin 6 in series with the internal 24.3kn resistor. An external capacitor can be added between the Integrator Output. pin 3. and the operational amplifier Summinglunction. pin 5. to lower the ramp. The VFC has the advantages of high linearity (±0.05% of FSR max at 50kHz full scale). good stability. and frequency modulated output. For further detail see the data sheet on the Burr-Brown VFC32BM. The Transmitter section consists of an Exclusive OR gate which drives a current switch to power the LED. The logic phase input at pin 2 determines whether or not the logic level input at pin 15 will be inverted through the gate. The LED light output intensity (power) can be increased by connecting resistance between pin 17 and Common. pin 12. Shorter cable links require less light power to prevent receiver input saturation. This also prnlongs LED lifetime and reduces power consumpiion in the transmitter (see Typical Performance Curves). I n the fundamental configuration. the optical signal is frequency modulated. It radiates no external energy. is immune to interference. and is electrically isolated. The fiber optic connector is aligned at the factory for optimum performance. This alignment will be disturbed if the connector mounting screws are loosened. FIIIIX.=5OIcHz OV,;VIN'; +IOV PWR OUT: min ·15V +15V FIGURE I. Minimal Connections. OPTICAL POWER ADJUSTMENT The optical power of the 3714T may he adjusted hy controlling the resistance between the Power Adjust. pin 17 and Common. pin 12. The following eljuation shows LED current. IJ.I'/)= 0.65 +[Ik!l II (22+ R,)l (I) where R, is the external resistor shown in Figure 2. OffIll Adl FIIIIX = 50IcHz OV .; Vln .; +IOV PWR OUT. GAIN AND OFFSET ADJUSTABLE FIGURE 2. Typical Connections. The leads on R, should be kept short; When the resistor is minimum the LED output is maximum. and as R, is increased. the output asymptotically approaches a minimum value. This is shown in the performa'nce curve "Relative Output Power vs Current Setting Resistor". LED power should be no greater than that reljuired hv the cable and receiver (3713R). See Cable Selection section for details. FULL SCALE FREQUENCY ADJUSTMENT The full scale freljuency of the 3714T may he reduced for use with lower speed receivers. Two external capacitors shown in Figure 3' are chosen as follows. (2) C , = (4.1 x 10-')1 fm" - 8.20 X 10"'0 farads Select the closest standard value to the capacitance given by the equation. A low drift capacitor such as an NPO ceramic or silver mica type is recommended. The initial tolerance is not critical "ince R, will he adjusted to remove initial gain errors. C, = (10" fm.,,) -2.2 x 10 " farads (3) POWER SUPPLY CONNECTIONS The 3714T requires ± 15Y supplies only. For optimum performance and noise rejection. all required supply bypassing capacitors are internal. A low resistance external ground return path must he provided for the IA input bias currents (pins 7 and 10). This lowers DC offset errors. Figure I shows a configuration with minimal Select one for low leakage and low dielectric absorption. A mylar or polycarbonate type is recommended. 4-33 VFC OFFSET ADJUSTMENT The offset may be adjusted by injecting a small current into the Summing Junction (SJ) of the VFC. This can be' accomplished by connecting a IOkU to 100kU potentiometer, R3, and IOMU resistor to pin 5as shown in Figure 2. IA V"r at pin II can also be used (see Bipolar Operation). Establish the offset by: (I) applying a DC input voltage at pins 7 and 10 to produce an output frequency of 0.00 I x,full scale and (2) adjusting R.i for proper output frequencY at pin 14. CURRENT INPUT CONNECTION A current input. connection can also be achieved by injecting acurrent into the VFC SummingJuncti,onat pin 5. This IS shown in Figure 4. FilII =DHz o" lin" D.25InA GAIN ADJUSTMENT .overall gain is defined in terms of frequency out divided by voltage in. The general transfer function ·of Figure 3 is: _ F u., -=--120 x 10-" [I + (40 + 10) / Ro)l . Gr -(C, + 820 x lO- u )(R2 + 24.3 x 10,,)10 Hz/ V (4) where, [I + (40 x 10" / Roll = G 1A = Instrumentation Amplifier Gain (C, + 820 +10- 12 ) = VFC total one-shot capacitance (R2 + 24.3 x 10) = VFC total gain setting resistance F:: R(; = external IA gain setting resistor in ohms between pins 8 and 9. FIGURE 4. Current Input Connection. BIPOLAR INPUT OPERATION A bipolar input can be accommodated by offsetting the IA output at the V",. pin II. Figure 5 shows how this is done. The offsetting is necessary because the VFC can only accept positive inputs, The effective (jffset is twice the voltage applied to pin II. V", source impedance should be less than 10kn. C, = external one-shot capacitor in farads between pins 3 and 5. 51111 R2 = external VFC gain setting resistor in ohms between pins 6 and 4. 3714T -liV " Vln " +5V 0" Filii" 50kHz FIGU RE 5. Bipolar Input Connection. FIIIX =10kHz Filii =103 Vin II + IO'RalI OV"Vln "IOV FIGURE 3. 10kHz Full Scale Connection. The nominal value of R2 is 5kU, but a IOkH potentiometer with a TCR of 100ppm/"C can be used to minimize gain error. Set gain by: (I) Applying desired full scale DC input voltage at pins 7 and 8 and (1) adjusting R2 for desired frequency at pin 14. LOGIC SELECTION When Logic , pin 2. is + 15V. the LED is on for a logic high at FlO, pin 15. It is opposite when pin 2 is OV. This helps detect cable breaks with idle data inputs. and permits optimizing response of receivers using peak detection for.automatic threshold adjustment. LOGIC INPUT OPERATION Figure 6 shows a CMOS I.ogic Input connection. Once the gain error is zeroed, IA gain may be changed while maintaining a very high overall gain accuracy. Ro then sets the gain according to the equation: G,,\ = I + (40k/ Ro) MIX. Oata Rill =2M a..d CMOS Input ''0'' =OV (5) for calibration of the basic circuit (Figure 2). This, involves an iteration between VFC Offset adjustment and Gain adjustment. OV":; V;n":; +IOV OHz":; F ..", ..:; 50Hz Gr = F"u./ V;n "" 4.994kHz/V calculated "1"= 15V Invlrt lIIg1e by C..nlctlng lIIgle cI> Example: (I) Set V;n = +IOmV ±O.I mV and adjust R, for 50Hz ± I Hz at F""" pin 14. (2) Set V," = + 10V ±I mV and adjust R2 for 50kHz ±I Hz at F""" pin 14. (3) Iterate as necessary. toOV. ·15V +15V FIGURE 6: Logic Input Connection. COMPATIBLE FIBER OPTIC RECEIVER The 3712R and 3713R are compatible receivers for the 3714T transmitter. As shown in Figure 10 .. Application Information section, the recovered FM digital 3713R 4-34 output can be demodulated by a frequency-to-voltage converter to obtain an analog signal. An inexpensi\c analog-to-digital converter is also shown in Figure 10 by using a gate and counter to record pulse over a fixed time period. TABLE I. 3714T Compatible Cable Manufacturers. CABLE SELECTION The 3714Tand 371,3R with the AMPTM Optimate Single Position Fiber Optic Cable Connector System can be used with a wide variety of cable types. The choice of a cable type-for a particular application. of course. depends upon the details of that application: link environment. link length. cable performance characteristics. and cable cost. AMP ICONNECTORS, 1717,546-{)101 AMP, Inc. 499 Eisenhower Blvd. Harrisburg, PA 17105 BELDEN 13121232-8900 Belden Corp. 2000 South Batavia Geneva, 1160134 DUPONT ICROFON, 1302, 774-6595 E.I. Dupont De Nemours PP & R Dept .. Room 0-12086 Crofon Fiber Optics Group Wilmington, DE 19898 DUPONT,PIFAX, 1302,774-7850 1302, 774-8339 E.I. Dupont De Nemours Plastic Products & Resins Wilmington, DE 19898 GALILEO 1617, 347-9191 Galileo Electro-Optics Galileo Park Sturbridge, MA 01518 MAXLIGHT 1602' 26~8387 Maxlight Optical Waveguides, Inc. 3035 N. 33rd Drive Phoenix, AZ 85017 VALTEC 16171 835-6082 ValtecCorp. Fiber Optics Div. West Boylston, MA 01583 ENVIRONMENTAL CONSIDERATIONS The mechanical stresses. environmental temperature extremes. and exposure to harsh chemicals must be . considered when choosing a particular cable. Such things as jacketing material and the type of added strength members. see Figure 7. determine a cable's mechanical and environmental capabilities. Table I is a representative list of cable manufacturers who make cable compatible with the 3714T. See Table II for details of cable performance. DETERMINING CABLE TYPE There are three basic types of optical fibers to choose from: Step-Index. Single-Mode. and Graded-Index. Each type specifies the profile or variation of the fiber's index of refraction as a function of radial distance from the fiber's center. In a fiber with a step-index profile. the refractive index undergoes an abrupt change (step) in value. This step is caused by the sudden change in the index of refraction between the fiber's core and a surrounding anm'lar cladding. as shown in Figure 8. Step-index fiber with a core diameter of 200pm or larger is recommended for use with the 3714Tand 3713R. Stepindex fiber offers the best compromise between core diameter. bandwidth. coupling loss. and cost. Singlemode and graded-index fibers are not recommended due to their small core dialT'eter. The wide bandwidth characteristics of these cables are not needed. FIGURE 7. Typical Step Index Fiber Optic Cable Construction. TABLE II. Link Performance vs Various Cable Types. Cable Characteristics Link Performance Cable Manufacturer and Part Number BELDEN 220001 221001 Core Dia. Fiber(1) Cable Dia. IlAm! Ipm! Dia. Imml LAI21 at 660nm IdB/kml PL Material NA I",WI Recommended AMPTM XMAX LM ,dB, Imeters Connector min typ min typ min typ 1667 1866 Conta~t Belden Contact Belden 23 47 200 300 400 440 3.8 3.8 12 12 0.35 0.35 0.7 1.1 1.5 2.6 14 16 20 22 1140 1016 368 368 200 200 1016 400 400 600 600 2.2 1.9 1.9 2.4 2.4 1300 360 330 43 33 0.53 0.53 0.53 0.4 0.4 10 1.5 1.5 0.7 0.7 15 3.5 3.5 1.5 1.5 25 17 17 14 14 30 24 24 20 20 19 34 51 318 415 465 606 530530-2 530530-9 530530-9 1-530530-2 1-530530-2 GAll LEO 3OOOLC-P 204 245 2.2 100 0.48 0.7 1.5 14 20 137 200 530530-9, MAXLIGHT KSC200A KSC200B 200 200 300 300 2.4 2.4 8 27 0.39 0.39 0.7 0.7 1.5 1.5 14 14 20 20 1710 507 2500 741 (3) VALTEC MD-PC100 250 430 4.1 14 0.30 0.9 2.0 15 21 1055 1518 530530-9 DUPONT Croton 1040' PIFAX-PI40" PIFAX-PIRI40 PIFAX-SI20 PIFAX-SI20*" ,type 30, 1304 72 (3) 11 Fiber Diameter = Core Diameter plus Cladding. 2\ Conversiol"! Factors: 100",m = 0.003937 in; 1000m = 3281 ft. 3, Sold as terminated cable. * Same as Burr-Brown OCA 100. * * Same as Burr-Brown DCA 101. * * * Same as Burr-Brown OCA1 0 2 . · 4-35 . FOI'CROFONI04OatAT=670nm, D,= 1300dBjkm Xma" = 25dBj( 1.3dBjm) = 19 meters. I f thiS length is too short, a cable with a larger diameter (larger PrJ or less attenuation (smaller U)mu's(be used. ClADDIN""2' CORElnl', ","",-:;'-' ~...:;:, OPTICALlY - ~ - WAVESUIOEO "'~-::. lI8HT_ , ....... ... ....... ClAOOIN81n2' FIGURE 8. Step Index Fiber. DETERMINING LAUNCHED POWER Once the mechanical characteristics and cable type, have been chosen, it becomes necessary to analyze link performance with various cables. The first analysis to make is the power launched into a particular cable from the transmitter. An advantage of the 3714T over many other fiber optic , transmitters is the way output power has been specified. The 3714T specifies the actual power launched into the cable. Thus, such' complicated effects as LED output power and, emission profile, cable numerical aperture (N A), and spacing between the LED tran~mitter and the cable have all been taken into ,consideration for the user. For cables other than those specified in the Electrical Spe~ificati!,n Table, the power launched may,be deterc mined from the curve in Figure 9. 100 ~ ~ ; 0 ~ . ." Q, '0 .,u ~ / c: j'f' ..J 1,0 J..oo" ~I<' """" ",,,,,I<', / I/J 200 As an example. consider a cable with a 368/lm core diameter and a cable loss of 330dB ~m. The typical power launched into the cable from Figure 9 is 3.5/lW. The minimum loss margin is found using the typical power launched into the cable and the maximum input to the receiver which is '/lW for the 37iJR. LM = 10 log (PI P.. m,,,) LM = 10 log (3.5/l W 'll W) = 5.4dB. The minimum cable length for the specific cable in this example is: Xmon = LMmon L\ Xmon (5.4dB/0.33dB m) = 16 meters. Parameters of the OCAIOO 101,102 fiber optic cables appear in the Cable Selection section. The 3712R or 3713R are compatible receivers. the 2801 MC is an electrical mating connector. V 0 The minimum cable length may be determined for a specific cable by calculating the power launched into it as previously done using the typical curve from Figure 9. The typical value of lailnched power should be used since this will give the most power into the receiver. resulting i'n the desired minimum cable length. APPLICATION INFORMATION // 0.1 DETERMINING MINIMUM CABLE LENGTH Short cable lengths with large core diameter fibers may cause some receiver slew rllte limit which will appear as duty cycle distortion. Limiting the power coupled into the receiver from the cable will prevent this from occurring. If this minimum cable length is too long for a particular application. use a smaller cQre diameter cable. a cable with higher loss, 9r the power launched into the cable rna\' be reduced as described in the Optical Power Adjustmen't, section. ~ t- ... ~9'C"\ 10 Table II shows the link performance for several different cables. 400 600 800 1000 1200 1400 Core Diameter 'I pm I FIGURE 9. Launched Power vs Core Diameter. DETERMINING MAXIMUM CABLE LENGTH Once PI. and LA are known, the maximum cable length may be obtained. First the loss margin is found by, LM(dB) = 10 log (PI! P;n m;n). (6) For the 37.14T with CROFON 1040 1016/lm fiber, PI. = 10/lW and for the 3713R. p," m;n = 30nW worst-case for 10-' BER. Thus. LM = 10 log (10/lWj30nW)= 10 log 333 = 25dB. Then Xm", the maximum' cable length that will just present P;n mon to the transmitter is found by .. Xm" = [LM(dB»)j[L\(dBj m»). PRECAUTIONS The J ~ 14T contai ns protected CMOS ci rcu it ry: however, to prevent failures, anti-static handling procedures should be observed and the Fon and Logic cf> inputs must be committed to either OV or + 15V prior to turn-on and during operation. Loosening of the cable connector can cause 'misalignment of the LED and fiber. RECEIVERS The 3713R will operate overthefu1l50kHz handwidth of the 3714T. However, the 3712R ~ill allow longer link lengths. but at a lower bit rate of 20k bits sec ( 10k H 1). In this case the full scale frequency of the 3714Tshould be set to 10kHz (see Figure 3). 4-36 APPLICATION CIRCUITS illustrate the use of the 3714T transmitter and 3713R reciever. The 3714T Fiber Optic Data Link solves such data transmission problems as crosstalk. ringing. and echos. Electromagnetic radiation interference is avoided when using a fiber optic data link in high noise environmenis. One major application of the 3714T is a Remote Transducer Readout. Figure 10. This arrangement utili7es the key features of sensitivity and linearity. The transducer can be connected directly to the 3714T input eliminating the requirement for an external precision instrumentation amplifier. Recovery of the analog signal can be achieved by a frequency-to-voltage converter such as the VFC42. A digital display can easily be produced by counting the TTL pulses from the output of the 3713R. In Figure 12. voice can be amplitude modulated and a sensor can be frequency modulated over the same cable. Also. twochannel multiplexing is possible as shown in Figure 13. Lightning damage to cables and connecting equipment can be eliminated where fiber optic cables replace metalic conductors. In refineries and chemical plants which have explosive atmospheres. sparks from shorted electrical cables are eliminated by the fiber optic cable - an inherent safety feature. The unique features of the 3714Tallow it to be used directly with transducers requiring high sensitivity and linearity. Also. an inexpensive analog-to-digital converter can readily be constructed. Figures 10 thru 13 FREQUENCY NOISE IMMUNE HIGHLY LINEAR TRANSDUCER ?J: "''' ,,~ ?. FIBER OPTIC CABLE VFC42 VOLTAGE '2r SEE FIGURE 2 FOR CONNECTIONS INEXPENSIVE AIO FIGURE 10. Remote Transducer Readout. NOISE IMMUNE OIGITAL MOTOR SPEED CONTROL COMPUTER FIGURE II. Monitor and Control System Using a High Speed Rotation Position Sensor. ELECTRICAL ISOLATION FIBER OPTIC CABLE SECURE VOICE LINK HIGH VOLTAGE AREA FIGUR E 12. Monitoring of Parameters from a High Voltage Area with Voice Communication over the Same Cable. ~IOOHZ PATIENTECG CHANNEL A--------<0.1 CONTROL-lkHz---1r---.-.! ELECTRICAL ISOLATION NOISE IMMUNE CHANNEL B - - _ + -_ _ _--' ~OOHZ PATIENT BLOOD PRESSURE LOGIC USED FOR CHANNEL REFERENCE FIGURE 13. Two-Channel Medical Monitoring. 4-37 2-CHANNEL MONITOR SCOPE ANALOG CIRCUIT FUNCTIONS Analog circuits act as building blocks with which to perform a variety of instrumentation, computation, and control functions. They provide a broad range of versatile, proven, and ready to use computational function circuits forthedesignerto use in developing simple or complex systems. The analog circuitfunctions include multiplers, dividers, multifunction converters, true rms-to-DC converters, logarithmic amplifiers, voltage and window comparators, peak detectors, precision oscillators, and filters. The multifunction converter also provide multiply, divide, square root, exponentiate, roots, sine, cosine, arctangent, vector magnitude RMS-to-DC and logarithmic amplifier functions. The availability of these relatively complex functions as precise, versatile, easy-to-use, low-cost building blocks has broadened the scope of practical analog circuit systems and greatly simplified analog circuit designs. The names of most analog ci rcuit functions are self-explanatory and describe the main functions they perform. The functions are used mostly for processing (handing) and/or conditioning of analog signals, and usually (though not always) for simulation of algebraic and/or trigonometrically expressed analog computations. The variety of applications these functions are effectively used for, are limited only by the designer's creative imagination. Some of the interesting applications where analog circuit functions have found wide acceptance are listed in the table on the following page. 5-1 Types of Applications Analog simulation. Algebraic and trigonometric computations. Power series approximation, function fitting andlin~arizing Analog wave shaping. .. VCO and AGC applications. Vector computation. Power and ¢nergy measurements. Moduation and demodulation. Signal compression. log-antilog-log ratio computations. light-related measurements. Analog signal conditioning. Instrumentation and control systems. Variety of test equipment. Transducer excitation Signal reference. ' Alarm circuits. Bang-bang control applications. Control of limit stops. Analog memory and peak detection. Fixed-frequency tuned filters. Recommended Analog Circuit Function Multiplier, Divider, Multifunction Converter, logarithmic Amplifier, ,Oscillator. Multiplier, Divider. Multifunction Converter, Multiplier. Multiplier, RMS-to~DC L().~vei1er .. Multiplier, Divider. logarithmic Amplifier. logarithmic Amplifier. logarithmic Amplifier. All circuit functions. All circuit functions. All circuit functions. Oscillator. Oscillator. Voltage and Window Comparators. Voltage and Window Comparators. Voltage and Window Comparators. Peak Detection. ATF-76 Filters. 5-2 SELECTION GUIDE Analog Circuit Functions These circuits offer a broad range of versatile, proven and ready-to-use analog computational functions designed to work in simple and complex instrumentation and control systems. Primarily they process and/or condition analog signals - usually for simulation of algebraic or trigonometric computations. Burr-Brown has the widest selection of such functions available in the industry. How you apply these circuits is limited only by your creative imagination! MULTIPLIERS/DIVIDERS You can select accuracy from 0.25% to 2% max from this complete line of integrated circuit multipliers. Most provide full four-quadrant multiplication. All are laser-trimmed for accuracy - no trim pots are needed to meet specified performance. These compact models bring the cost of high performancE> down to acceptable levels. MUL TlPLIERS/DIVIDERS Accuracy Temperature max at 25°C Coefficient %, max %fOC Transfer Function Model(t) Offset Voltage mV 1% Bandwidth kHz Temp Range(2} Package Unit Feed- Price 1$1 100'5 Page 2 1 1 0.04 0.04 0.04 50 50 50 20 20 20 40 40 40 Com Com Mil TO-l00 TO-l00 TO-l00 35.20 48.20 77.00 19.00 33.80 -- 5-41 5-41 5-41 0.5 0.5 0.25 0.01 0.01 0.02 10 5 5 15 5 5 32 33 33 Ind Ind Mil DIP DIP DIP 68.00 88.75 101.00 51.00 64.50 82.00 5-43 5-43 5-43 (Xt - X2)(Yt - Y2i110 2 1 1 0.04 0.04 0.04 50 50 50 20 20 20 40 40 40 Com Com Mil TO-l00 TO-l00 TO-l00 31.00 45.15 64.50 19.40 29.35 38.80 5-41 5-41 5-41 XY/l0 0.5 0.25 0.01 0.01 10 5 15 5 33 33 Com Com DIP DIP 47.00 66.80 29.35 41.00 5-49 5-49 1 0.5 0.5 0.008 0.008 0.008 70 70 70 Ind Ind Mil TO-l00 TO-l00 TO-l00 29.35 42.50 55.00 18.90 28.30 37.75 5-55 5-55 5-55 1 0.5 1 0.5 0.02 0.02 0.02 0.02 70 70 70 70 Ind Ind Ind Ind DIP DIP DIP DIP 24.50 36.70 29.60 47.95 16.30 26.50 22.65 35.70 5-62 5-62 5-62 5-62 XY/l0 4203J 4203K 4203S.IQ, 4204J 4204K 4204S.IQ' 4205J 4205K 4205S.IQI through mV 4206J 4206K 4213AM, I Q I [IXt - X211Y1 - Y21/10]+ Z 4213BM 4213SM 4213/M1L Series [IX, - X211Y, - Y21/10j + Z 4214AP 4214BP 4214RM 4214SM 'Same as model above. 30 10 7 30 30 7 See Military Products 30 10 7 30 30 10 30 7 NOTES: 11 ", Q \" indicates product also available with screening for increased reliability 21 Com = a to +70°C; Ind = -2SoC to +85°C; Mil = -55°C to +125°C. DIVIDERS The use of a special log/antilog committed divider design overcomes the major problem encountered when trying to use a multiplier in a divider circuit. Outstanding accuracy is maintained even at very low denominator voltages. DIVIDERS Model DIV100HP DIV100JP DIV100KP Transfer Input Accuracy, max D ~ 250mV Function Range % Temperature Coefficient %/OC N/D 10 250mV to 10V 1.0 0.5 0.25 0.2 0.2 0.2 0.5% Bandwidth 15 15 15 kHz 'Same as model above. NOTES: 11 Ind = ·25°C to +85°C 5-3 Rated Output, min 10V. ±5mA 10V, ±5mA 10V, ±5mA Temp Rangel') Package Ind Ind Ind DIP DIP DIP Price ($1 l00's Unit 2B.75 40.25 57.50 17.25 26.45 40.25 Page 5-6 5-6 5-6 SPECIAL FUNCTIONS This group of models offers. many differentfunctions· that are the quick, easy wayto solve a wide variety of analog computational problems. Model Function Description 4301 4302 Multifunction Converter YIZiXl m LOG100JP log Ratio Amplifier 4127JG 4127KP 4340 4341 4085BM 4085KG 4085SM Logarithmic Amplifier j +.~T j tf GN2(t)dt OTS!N2dt Peak Detector Most are in integrated circuit packages and are laser-trimmed for excellent accuracy. Coroments This function may be used to multiply, divide, raise to powers, take roots ~nd form sine and cosine functions. ~301 is hermetically sealed and shielded in K Log Ihil2) Optimized for log 'ratio of current inputs. Specified over six decades of input Can provide log and log ratio of current or voltage inputs. Also forms antilog. Temp Rang .. ') Package Unit 100's Page Ind )nd D)P DIP 90.75 64.70 50.00 30.60 5-66 5-68 Com DIP 36.00 25.00 5-14 Com Com DIP DIP 46.00 53.00 31.10 39.60 5-34 5-34 Price ($1 a metal package. 4302 is.in a plastic package. Both units are pinfor-pin compatible. (1 nA to 1rnA 1. 5SmV total error; 0.25% log conformity. K Log rhilREF) A more versatile part which contains an internal reference and a current inverter. 1% and 0.5% accuracy. True rms-to-DC conversion based on a log-antilog computational approach. Laser-trimmed, requires no external trimming for r~ted accuracy. Hermetically sealed in a metal package. Ind DIP 90.75 64.20 5-74 True rms-to-DC conversion based on a log-antilog computational approach. Some external trimming required. Lower cost in plastic paeka~e. Pin compatible Ind DIP 27.00 16.85 5-78 with 4340. These are analog memory circuits which hold and provide read-out of a DC voltage equal to peak value of a complex input waveform. Digital mojje control provides reset capability and allows selection of peaks within a desired time interval. May be used to make peak-to-peak detector. Com Ind Mil DIP DIP DIP 78.00 67.65 103.00 56.00 47.05 71.90 5-26 5-26 5-26 Com Module 66.30 46.00 5-32 Ind DIP 48.25 31.00 5-24 4115i04 Window Comparator 4115/04 provides a window ordual limit for comparison. Unit has 3 inputs; one for a voltage that sets upper limit, one for a voltage that sets lower limit, and one for a Signal input. The 3 outputs are capable of sinking up to 200mA of current, indicating if the input voltage is above, below, or in the window. 4062iOO Level Comparator Compares input voltage with user set limit. Provides 2-state logic output that indicates whether one analog voltage is > or < another. Adjustable hysteresis uncommitted collector output can sink up to 100mA. NOTE: 11 Com ~ 0 to +7O"C; Ind ~ -25°C to +85°C; Mil ~ -55°C to +125°C. FREQUENCY PRODUCTS and attenuation. Both fixed frequency and user selected frequency units are available. This group of products consists of precision oscillators .and active filters for both signal generation Temp Rang.. ') Package Ind Module 199.50 148.00 5-22 Com DIP 19.90 13.50 5-82 Add only resistors to determine pole location (frequency and 01. Easily cascaded for complex filter responses. Ind Ind Ind Ind Ind Ind DI~ DIP DIP DIP DIP DIP 18.25 28.95 74.00 81.00 46.35 54.00 9.40 16.00 46.00 56.00 22.75 33.50 5-109 5-101 5-93 5-93 5-93 5-93 Low-pass, bandpass and band reject. Butterworth, Chebyschev and Bessel. Ind DIP 102.00 to 192.00 49.00 to 140.00 5-86 Model Function Description Comments 4023125 Oscillator Fixed-frequency (customer-specified, 10Hz to 20kHz) provides low distortion, stable amplitude sine wave output. Frequency stability vs temperature: O.04%/OC max. Amplitude stability vs temperature: 0.02%,fOC max. 4423 Oscillator Very-lOW cost in plastic package. Provides resistor programmable quadrature outputs (sine and cosine wave outputs simultaneously available I, Frequency range: 0.002Hz to 20kHz. Frequency stability: 0.01 %,IOC. Ouadrature phase error: ±O.1%. These filters provide a complex pole pair. Based on state variable approach, low-pass, high-pass and bandpass outputs are available. UAF41 Universal UAF31 Active UAF21 Filter UAF21H,Q UAF11 UAF11H.Q ATF76 Series Fi'xedFrequency, Actjve F,ilter Over 60 different types of fi Iters are available from combinations of filter type, number of pole$ and type of response. 2 to 8 poles. NOTE: 11 Com ~ 0 to +7O"C; Ind ~ -25°C to +85°C. 5-4 Prices ($) Unit 100'. Page GLOSSARY OF TERMS & DEFINITIONS Analog Circuit Functions positive feedback and resulting in different trip points for the two directions of output transition. ABSOLUTE-VALUE CIRCUIT A circuit that produces a unipolar output signal equal to the magnitude or absolute value of a bipolar input signal. LOGARITHMIC AMPLIFIER An amplifier which develops an output voltage that is proportional to the logarithm of the input signal. ACCURACY The deviation from the ideal output voltage defined as a percent of full scale output voltage. OUTPUT OFFSET The output voltage when the inputs are grounded. COMPARATOR A device with two stable output states which signal if an input current or voltage has crossed a threshold. The threshold may be set by one or more other currents or voltages, either fixed or variable. RMS The root-mean-square value of a time-varying signal E(t) over a time period of T is Enn , = vf-:I=C/T=--.f"'-~=[E:-:-(t=)]'''d:-t CREST FACTOR The ratio of the peak value of a time-varying signal to its rms value. RMS CONVERTER A circuit that develops a DC output voltage equal in rms value to an input signal of arbitrary waveform. CURRENT LIMITING Limiting the output current supplied by a circuit for protection purposes. SETTLING TIME The time required for the output to respond to a step input and to settle within some specified error band around the output final value. FEEDBACK The return of a portion of the output signal from a device to the input of the device. SLEW RATE The maximum rate of change of an output voltage when supplying the rated output. FEEDTHROUGH The input offset parameter applicable to multipliers. It is the output voltage when voltage is applied to one input of the multiplier and the other input is at zero. SMALL SCALE FREQUENCY RESPONSE The -3dB output frequency for a small AC signal (normally IV, p-p) input. For mUltipliers, one input may be held at +IOVDC or -IOVDC and the other input held at small AC signal. FULL POWER FREQUENCY RESPONSE The maximum frequency at which the output will swing full scale peak-ta-peak voltage into a rated load without significant distortion of the output. WINDOW COMPARATOR A compartor that detects levels within a set range or window rather than simply distinguishing between levels above and below a set point. HYSTERESIS The transfer response lag of comparators controlled by 5-5 BURR-BROWN@ DIV100 IElElI ANALOG DIVIDER FEATURES APPLICATIONS • HIGH ACCURACY • DIVISION 0.25% maximum error, 40:1 denominator range • SQUARE ROOT • TWO-QUAORANT OPERATION • RATIO METRIC MEASUREMENT Dedicated log-antilog technique • PERCENTAGE COMPUTATION • EASY TO USE Laser-trimmed to specified accuracy -no external resistors needed • TRANSDUCER AND BRIDGE LINEARIZATION • AUTOMATIC LEVEL - AND GAIN - CONTROL • LOW COST • VOLTAGE CONTROLLED AMPLIFIERS • DIP PACKAGE • ANALOG SIMULATION DESCRIPTION F or those applications requiring higher accuracy than the DIV 100 specifies the capability for optional adjustment is provided. These adjustments allow the user to set scale factor, feedthrough, and outputreferred offsets for the lowest total divider error. The DIVIOO also gives the user a precision, temperature-compensated reference voltage for ext'ernal use. Designers of industrial process control systems, analytical illstruments, or biomedicalinstrumentation will find the DIV 100 easy to use and also a low cost, but highly accurate solution to their analog divider apRlications, The DIVIOO is a precision two-quadrant analog divider offering superior performance over a wide range of denominator input. Its accuracy is nearly two orders of magnitude better than multipliers used for division. It consists offour operational amplifiers and logging transistors integrated into a single monolithic circuit and a laser-trimmed, thin-film resistor network. The electrical characteristics of these devices offer the user guaranteed accuracy without the need for external adjustment - the DIV 100 is a complete, sirigle package analog divider. VREF Output Output NInput 13}-----------4_------------...io#\~ International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 1602) 746·1111· Twx: 910-952·1111 . Cable: B8RCORP· Talex: 66·6491 PDS-427 5-6 SPECIFICATIONS ELECTRICAL Specifications at TA = +25°C and -+Vcc = 15VOC unless otherwise noted MODEL DIV100HP ~ MIN TYP Vo I FUNCTION '~~"""'V ~ DIV100JP ~ ~ ~ .DI~ MAX ~ MAX I . I I 10N/0 TYP MIN I RL;>~k~ lo,all=rror Initial vs. Temperature vs, Supply Warm-up time to rated performance 0.25Vo;;; DO;;; 10V, No;;;l 01 1V0;;; ~O;;; 10V, N.;I 01 0.25V'; ~O;;; IV, N 0;;;101 0.25V'; 0'; 10V, No;;;l 01 0.7 0.02 0.06 0.15 5 1.0 0.05(2) 0.2I')} 0.3 0.5 0.2 0.25 % FSO(1) % FSO;oC % FSO;oC % FSO/% Minutes o ~,+.10\l AC ... 1Bandwid,n 0.5% Amplitude Error 0.57° Vector Error Full-Power Bandwidth Slew Rate Settling Time Overload Recovery INPUT· Input Voltage Range Numerator Denominator Input Resistance OUTPUT Full-Scale Output Rated Output Voltage Current Current Limit Positive Negative sm~~-~~gnal 350 Small-Signal Vo ~ ±IOV. 10 = ±5mA Vo ~ ±IOV, 10 ~ ±5mA E ~ 1%, :J.Vo ~ 20V 50% Output Overload 1000 30 2 IS N.;IOI 0;>+250mV Either Input I~:;U) lo=±5mA Vo ~±IOV ~sec ~sec 25 V V kG ±IO +10 ±IO V ±IO ±5 V mA 2012) 23(2) mA mA ~OV 370 1 o IJ,V, rms mV, rms J!.to;>IOMIl ,VOLTAGE ~~:::~It Voltage At+25DC 6.3(2) vs. Supply Temperature Coefficient OutP~t Resistance 6,6 ±25 ±50 6,9(2) ppm/DC kG ±20 ~gg 7(2) 1012) mA mA +70 +85 +125 :g ±15 Derated Performance ±12 5 8 ,RANGE Derated Performance 0 -25 -55 V ~VN 3 "OWER SUPPLY Rated Voltage Operating Range Quiescent Current Positive Supply Negative Supply AMBIENT i Operating Range Storage VI~sec 4 IS 19 C).U!PUT NOIS~ Is ~ 10Hz to 10kHz O=+IOV -+250mV kHz kHz Hz kHz DC 'Same as OIVl00H, NOTES: 1. FSO is the abbreviation for Full Scale Output. 2. This parameter is untested and is not guaranteed. This specification is established to a 90% confidence level. 3. See General Information section for discussion. 4. For supply voltages less than ±20VDC, the absolute maximum input voltage is equal to the supply voltage. 5. Short-circuit may be to ground only. Rating applies to an ambient temperature of +38°C at rated supply voltage. 5-7 ABSOLUTE MAXIMUM RATINGS ~~~;~~-Ip-o-w-e-r-0-i-ss-iP-a-ti-o-nl-3)------------+:~~; Input Voltage Range(') Storage Temperature Range Operating Temperature Range Lead Temperature (soldering, 10 seconds) Output Short-Circuit Duration(3)(5) Junction Temperature +20VOC -55°C to +125°C -25°C to +85°C +3000C Continuous 175°C TYPICAL PERFORMANCE CURVES (TA = +25°C, Vee = ±15VOC unless otherwise noted.) FREQUENCY RESPONSE VS TOTAl ERROR VS DENOMINATOR VOLTAGE TOTAL ERROR VS QUTP!..!T CURRENT TOTAL ERROR VS AMBIENT TEMPERATURE DENOMINATOR VOLTAGE lM~~ 0 .• 0.5 ~ ! ~ 0.4 ! 0.2 '.1 Denominator Voltage I V ) o~ '0.08 N=i1V,pk O-+IOV eo ~ i't'" \ -1 5 II -20 1Oti: lOOk Frequency (Hzr '"~ J g i \ l(1Jk Frequency 0 I Time (Hz) +50 ~ If I D-+25OmV -50 -100 40 60 \ 50 100 1&0 Time (I'MCJ ZOO I-f-.-I-+-+-+-'---'---'-+-! D=+lOV +50 I-H-t-++_Cj-'_=f-2Op..,F-I-l 0 I-'H-t-++++++-l ~ 8. -; ~ ~ HH-t-+-++++-t-l 1\ 100 50 (~eecl -100 150 t-+-+-H-+'".·-t-H-l 10 200 Time ("sec I OUTPUT NOISE VS DeNOMINATOR VOLTAGE DENOMINATOR VOLTAGE ~ ,; Il r !2 I o. o. J ~ ~ • 40 , 1 '0 '0 '0 00 '0 INCHES MILLIMETERS MIN MAX .190 .810 20.07 20.51 B .490 .510 .190 .260 .01. .021 .100 BASIC .116 .130 .300 12.45 4.83 C MIN MAX . ........ G H L " .300 BASIC . 115 5-8 Al r .t '~ Ambient Temperature 1°C, NOTE: Leads in true position within 0010"1025mm1RatMMCat sealing plane. Denotes Pin 1 A C (Bottom View I ! DIV100HP DIV100JP DIV100KP CASE. Epoxy WEIGHT: 2.7 Grams CONNECTOR: 0145MC DIM 10 Denominator Voltage I V, ORDER NUMBER 0'°, 10 Denominator Voltage I V I 10 20 12 1 50 JNm 40 ~ 60 MECHANICAL 0" 013 012 0 11 ..;: 70 J N=lOV 30 QUIESCENT CURRENT VS AMBIENT TEMPERATURE 60 .. 10 ~ 20 Thne(,.eecl POWER SUPPLY REJECTION VS PIN CONFIGURATION 1. Gain Error Adjust 2. Output 3. -Vcc 4. D Input Offset Adjust 5. Internally Connected to Pin 1 6. Internally Connected to Pin 14 7. I nternally Connected to Pin 8 8. Reference Voltage ·9. Denominator (O) Input 10. Common 11. N Input Ollset Adjust 12. Output Ollset Adjust 13. Numerator (Nllnput 14. +Vcc +100 i 80 I i D=+25QmV RL=2kO- . lOOk 1(1' TRANSIENT RESPONSE Ct.=2OpF -10 ~ Ct.=2OpF / +5 1k 100 Numerator Frequency, Hz LARGE SIGNAL STEP RESPONSE 1 -; 20 10 10 +10 0 1M TRANSIENT RESPONSE +100 1.0 0.05 Denominator Voltage I V. ~ -10 lOtI. 0.1 CL=20pF RL-2tlO O -5 1k 010 .OI=+1'0J_ ~+S 100 '--L-...w..uu.u._.L-Ju...U.JJ.II 0.01 LARGE SIGNAL STEP RESPONSE +10 ~ 0.02 1110. 101< 1k 500~~. " Numerator Frequency 1Hz! DENOMINATOR FEEDTHROUGH VS DENOMINATOR FREQUENCY 100 "~ 1111 II 0.0 1 100 NONLINEARITY VB NUMERATOR FREQUENCY 0.04 :1 ~ 1 10 Denominator Voltage IV, N-Dsinwt C ......-OVo RII VREF Output R7 IROI Common oInput Oulput • Input 1 3 } - - - - - - - - -.....- - - - - - - - - - - - - - " " " - : ' FIG URE 5. DIV 100 Two-Quadrant Log-Antilog Circuit. limitation is not met Vo will try to be greater than the IOV output voltage limit of A•. A limitation that may not be obvious is the effect of source resistance. If the numerator or denominator inputs are driven from a source with more than IOn 'of output resistance, the resultant voltage divider will cause a significant output error. This voltage divider is formed by the source resistance and the DIV 100 input resistance. With RSOI'RCE = Ion and RINPI'T (IlIV'OO, = 25kn an error of 0.04% results. This means that the best performance of the OIVlOO is obtained by driving its inputs from operational amplifiers. Note that the reference voltage is brought out to pins 7 and 8. This gives the user a precision, temperaturecompensated reference for external use. Its open-circuit voltage is +6.6VDC, ±0.075V, typically. Its Thevenin equivalent resistance is 3kn. Since the output resistance is a relatively high value. an operational amplifier is necessary to buffer this source as shown in Figure 6. The external amplifier is necessary because current drawn through the 3kn resistor will effect the OIVlOO scale factor. this last equation in terms of the previously defined variables and taking the antilogarithm of the result yields: (2) V - VREF VN R" RI> 0VI> Rx RN In the OIV 100 VR11 = 6.6V. Ro= R~ = RI>, and Rx is such that the transfer function is: (3) Vo= ION 0 where: N = Numerator Voltage 0= Denominator Voltage Figure 5 is a more detailed circuit diagram for the DIV 100. In addition to the circuitry included in Figure 3, it also shows the resistors (R3, R4 , Rg, R., and RIO) used for level-shifting. This converts the OIV 100 to a twoquadrant divider. The implementation of the transfer function is equation (3) is done using devices with real limitations. For example, the value of the 0 input must always be positive. If it isn't, Q3 will no longer conduct, A3 will become open loop, and its output and theDIV 100 output will saturate. This limitation is further restricted in that if the 0 input is less than +250m V the errors will become substantial. It will still function, but its accuracy will be less. ---t? . .: . . l~_~.;.REF . L._D_IV_l00_...Jbf17a:-_. 3527AM Still another limitation is the value of the N input must always be equal to or less than the absolute value of the 0 input. From equation (3) it can be seen that if this FIGURE 6. Buffered Precision Voltage Reference. OPTIONAL ADJUSTMENTS Figure 7 shows the connections to make to adjust the OIV 100 for significantly better accuracy over its 40-to-1 denominator range. The adjustment procedure is: I. Begin with R" R" and R3 set to their mid-position. 2. With N = 0 = 1O.000V, ±lmV, adjust R, for Vo = +1O.000V, ±lmV. This sets the scale factor. 3. Set 0 to the minimum expected denominator voltage. With N = D, adjust R, for Vo = -1O.000V. This adjusts the output referred denominator offset errors. 4. With 0 still at its minimum expected value make N = +0. Adjust R, for Vo = 1O.000V. This adjusts the output referrred numerator offset errors. 5. Repeat steps 2 - 4 until the best accuracy is obtained. 5-11 FIGURE 7. Connection Diagram for Optional Adjustments. TYPICAL APPLICATIONS CONNECTION DIAGRAM Figure 8 is ~pplicable to each application discussed in this section, except the square root mode. IIREN~c:.~L1H l l i . t~ . TII;~-::~~: ...... OIIIIIIIO .. ' IECIIIloUIYFlOW ruUIlllTTt. AJIIIYOIIDUS -NYDIIIICNLDRIC • GAS [..n1Qll1llw1 RlOIIrce IUTU ut___..JD-t-Raourca < IOn -c=:m:~C=b~~ VOUI UQUID MYDROCMlOfIIC RIGId ;;.2kn "" FIGURE 8. Connection Diagram - Divide Mode. RATIOMETRIC MEASUREMENT -The DIVIOO is useful for ratiometric measurements such as efficiency, elasticity, stress, strain, percent distortion, impedance magnitude, and fractional loss or gain. These ratios may be made for instantaneous, average~ RMS, or peak values. ' PRIMAIIYVARIABI,E Ilnctlll1rolladl FIGURE 10: Ratio Control of Water to Hydrochloric Gas PERCENTAGE COMPUTATION A variation of the direct ratiometric measurements previously discussed is the need for percentage computation. In Figure I I the DIVIOO output varies as the percent deviation of the measured variable to the standard. 'The advantage of using the DIVIOO can be illustr;lted from the example shown in Figure9. lnitrumantatlllll Amplilier f.JURE 9. Weighing System - Fractional Loss. The L VDT (Linear Variable Differential Transformer) weigh cell measures the force exerted on it by the weight of.the material in the container. Its output is a voltage proportional to: Fg W=la I where: W = Weight of material F= 'Force g = Acceleration due to gravity a = Acceleration (acting on body of weight W) In a fractional loss weighing system the initial value ofthe material can be determined by the volume,ofthe container and the density of the material. If this value is then held on the D-input to the DIV 100 for some time interval, the DIV 100 output will be a measure of the instantaneous ,fractional loss: Loss (L) = W1NSTANTANEOLJS/ WINITIAI. Note that by using the D1VIOO in this application the common physical parameters of g and a have been eliminated from the measurement, thus eliminating the need for precise system calibration. The output from a ratiometric measuring system may also be used as a feedback signal in an adaptive process control system. A common application in the chemical industry is in the ratio control of a gas and liquid flow as illustrated in Figure 10. 5-12 DlVlOO 11 %parvoltl FIGURE I L Percentage Computation. TIME AVERAGING The circuit in Figure 12 overcomes the fixed averaging interval and crude approximation of more conventional time averaging schemes. T OIVIOO - If Vout =X=7 xIlt o FIGURE 12. Time Averaging Computation Circuit. BRIDGE LINEAR,IZATION The bridge circuit in Figure 13 is fundamental to pressure, force, strain and electrical measurements. It can have one or more active arms whose resistance is a function of the physical quantity, property, or condition that is being measured; e.g., torce of compression. For the sake of explanation the bridge in Figure 13 has only one active arm. sends a control signal to the denominator input to maintain a constant output, thus compensating for inp~t voltage changes. ~---oA r -.......-Vout FIGURE 13. Bridge Circuit. The differential output voltage V11.\ is: -VEX/) V 8A = VB - V A 2(2 + /» , a nonlinear function of the resistance change in the active arm. This nonlinearity limits the useful span ofthe bridge to perhaps ± 10% variation in the measured parameter. PlllUve DC Ill/ertllGtl VollI.. FIGURE 15. Automatic Gain Control Circuit. Bridge linearization is accomplished using the circuit in Figure 14. The instrumentation amplifier converts the differential output to a single-ended voltage needed to drive the divider. The voltage-divider string makes the p.umerator and denominator voltages: N = (2R, ~V~~n~2\ Il) ,and, D= 2 , respectively, (2R, VEX R,Il + 3RiIl )(2 + Il) VOLTAGE-CONTROLLED FILTER Figure 16 shows how to use the DlVIOO in the feedback loop of an integrator to form a voltage-controlled filter. The transfer function is: ~=_K_._ Vinisl TS + I where: K = ~R2/ R, 10 R, C T = -7,V'-;;("('-)~-"''-'R-O-1. where: RiN = DIVIOO numerator input resistance RiD = DIVIOO denominator input resistance Applying these voltages to the DIVIOO transfer function gives: Vo = ION D = (2R, + 3RiI»(R,~/» 10 , (2R, + 3R,,)(2Rill) which reduces to: Vo = -51l if the divider's input resistances are equal. This circuit may be used as a single-pole low-pass active filter whose cutoff frequency is linearily proportional to the circuit's control voltage. VControl o----4 The nonlinearity of the bridge has been eliminated and the circuit output is independent of variations in the excitation voltage. +VEX VCGIIInII ;;'+2SDmV FIGURE 16. Voltage - Controlled Filter. SQUARE ROOT VOUI= J10il N 13 N;;.+IDOmV FIGURE 14. Bridge Linearization Circuit. AUTOMATIC GAIN CONTROL A simple AGC circuit using the DlV 100 is shown in Figure 15. The numerator voltage may vary both positive and negative. The divider's output is half-wave rectified and filtered by D" R), and C,. It is then compared to the DC reference voltage. If a difference exists the integrator FIGURE 17. Connection Diagram for Square Root Mode. .5-13 BURR-BRoWN LOG100 11511511 Precision LOGARITHMIC AND LOG RATIO AMPLIFIER FEATURES APPLICATIONS • HIGH ACCURACY 0.37'1e FSOmlxTOIIIError over 5 decedll • GOOD LINEARITY O.l'1e mIx Log, Conformity over 5 decadll • EASY TO USE Pln-ulectable GIl". Intarnll Llser-trlmmed Ras/sIDrs • WIDE INPUT DYNAMIC RANGE 6 Decldll.l iiA ID 1mA • LOG. LOG RATIO AND ANTILOG 'COMPUTATIONS " • ABSORBANCE MEASUREMENTS • DATA COMPRESSION" • OPTICAL DENSITY'MEASUREMENTS • DATA LINEARIZATION • CURRENT AND VOLTAGE INPUTS RESISTOR VALUES MOMIIlAL ONLY, LASEft..TRIMMED FOR PRECISION GAIN. DESCRIPTION The LOG 100 uses advanced integrated Circuit technologies to achieve high accuracy ,ease of use,low cost, and small size.' It is the logical choice for your logarithmic-type computations. The amplifier has guaranteed maximum error specifications ov~r the full six-decade input range (InA to ImA) imd forall possible combinations of II and h. Total error is guaranteed so that inVolved error computations are not n~cessary. The circuit uses a specially designed compatible thinfilm monolithic integrated circuit which contains amplifiers, logging transistors, and low drift thinfilm resistors. The resistors are laser-trimmed for ,1.-011101111 Alrportl~duatrlal Park· P,O, Box maximum precisiori"FET input transistors are used for the amplifiers,\:vhose low bias currents (lpA typical) permit signal currents as low as InA while maintaining guaranteed total errors of 0.37% FSO maximum. Because scaling resistors are self-containec!, scale factors of I V; 3V 6r 5V per decade are obtained simply by pin selc::ctions. No other resistors are required for log ratio applicati!>n~. The LOG 100 will meet its guaranteed,accuracy with no user trimming. Provisions are made for simple adjustments of scale factor, offset voltage, and bias current ifenhanced performance is desired. 11400 ·,Tucson. Arizona 85734· Tal. (602) 746-1111· Twx: 911J.952rI111· Cable: BBRCORP,' Talax: ~Jj.649J PDS437 5-14 SPECIFICATIONS ELECTRICAL Specifications at TA = +25°C and ±Vcc = ±15V unless otherwise noted. Log Conformity Errort') Initial Over Temperature Either h or 12 1nA to 100I'A 15 decades) 1nA to 1mA IS decades) 1nA to 100l'A 15 decades I 1nA to 1mA IS decades) 0.04 0.15 0.002 0.001 1.3.5 0.3 0.03 K Range(2) Accuracy Temperature Coefficient Total Error(3) Initial K = 1.(4) Current Input Operation 1,.12=1mA h. 12 = 100I'A h.12=10I'A I,. 12 = 11'A h.12 = 100nA h.12 = 10nA h.12=1nA 0.1 0.25 % % %/"C %/"C Vldecade % %/"C ±55 ±30 ±25 ±2O ±25 ±30 ±37 mV mV mV mV mV mV mV vs Temperature h.12=1mA h. 12 = 100I'A h.12 = 10l'A 1,.12=1I'A h.12= 100nA 1,.12= 10nA h.12=1nA ±O.2O ±O.37 ±O.28 ±O.O33 ±O.28 ±O.51 ±1.28 mV/"C mV/"C mV/"C mV/"C mV/"C mV/"C mV/"C vs Supply h.12=1mA h. 12 = 100I'A 1,.12= 1OI'A h.12=1I'A h. 12 = 100nA h. 12 = 10nA h.12= 1nA ±4.3 ±1.5 ±O.37 ±O.11 ±O.s1 ±O.91 ±2.S mVN mVlV mVN mVN mVN mVN mVN Offset Voltage Initial vs Temperature Bias Current ±0.7 ±80 ±5 5(5) Initial vs Temperature Voltage NOise Current Noise 3dB Response(8). 12 = 1Ol'A 1nA 11'A 10l'A 1mA Step Response(8) Increasing 11'At01mA 100nA to 11'A 10nA to 100nA every 100C 3 0.5 I 10Hz to 10kHz. RTI 10Hz to 10kHz. RTI 0.11 Cc=4500pF Cc= 150pF Cc= 150pF Cc=50pF mV I'VloC pA I'V,rms pA. rms 45 kHz kHz kHz kHz 11 7 110 I'sec I'sec I'sec 38 27 Cc= 150pF Cc ="50pF 45 I'sec 20 "sec 550. Full Scale Output IFSO) Rated Output· Voltage Current Current Limit Positive louT=±5mA VOUT=±10V ±10 V ±10 V mA ±5 12.5 15 0.05 mA mA n VDC VDC mA Derated Performance 5-15 ELECTRICAL (CONrD) - - Specifications at TA - +25°C and +Vcc - +15V unless otherwise noted - I PARAMET£R I CONDITIONS I MIN TVP I MAX I UNITS AMBIEN.T TEMPERATURE RANGE Specification Operating Range Storage I Derated Performance I 0 -55 -55 J I +70 +125 +125 °C °C o.C 'I NOTES: 1. Log Co"nformity Error is the peak deviation from the be~t-fit straight line of the VOUT vs log liN curve expressed as a percent of peak-ta-peak full scale output. 2. May be trimmed to : :i0=~: : ":::l-t~::J~121 Yy'l'-, 5 1 1 -+ __""±: I-_-"_-l __ 1..._..I. __ L , I I I I I " I I O.OOl~F !:..qual amount to keep distortion within specifications. 600~ Long Term (max.) O.OI~F It is important to pad both R, and R, or C, and C, by an 1~ AMPLITUDE STABILITY YS • .T ernperature (max.) Noise and Jitter (max.) 0.1 ~F 10Hz to 100Hz 101Hz to 1000Hz 1001Hz to 20kHz Customer specified, may be any value From 10 Hz to 20kHz. ±l%, (May be trimmed by the user to less than ±1%) 0.04%/oC (max.) Dimensions in millimeters are shown in parentheses. Weight: 4 oz. maximum .(120 gram,) Mating Connector: 1500MC (Optional) I 'UPPfD4.4D,.DSUDfEP, SeREWCLEARANCE JD.19"DEEP,2HDlES EXTERNAL CONNECTIONS External connections are made to the gold-flashed pins on the unit. These connections include the Wien bridge, integrator feedback, output, and power supply termination and are made as follows: Pin I Wien Bridge Terminals Pin 2 Common Pin 3 Pin X Output B Pin 4 Output A Pin 5 Integrator Feedback Pin Y} PinZ Terminals Positive Power, +15VDC (+) Negative Power, -15VDC (-) I OPERATING INSTRUCTIONS With R, = R2 andC, =C2, the Wien-BridgeosciJIatorwiJI provide a sine-wave oscillation of frequency: fo = 1/2rr RC, where R = R, = R2 and C = C, = C2. Thefrequency of oscillation, fo, will be within ±I %ofthe nominal value specified by the customer. The frequency The Model 4023/25 is designed for installation on a flat mounting surface such as .a· chassis or printed circuit board. The gold-flashed pins may be hand or dip soldered; for plug-in installation,. the Model 1500MC mating connector may be installed on the chassis. The unit may be secured to the mounting surface by means of two 4-40 machine screws inserted through the mounting surface not more than 3/16" into the tapped holes in the bottom. Pin I and pin 3 must be shielded from external sources of electrical noise. The module is particularly sensitive to periodic noise near the resonant frequency. Also, if external bridge components are added tothe Wien bridge terniinals they must be physically near the 4023/25 module. 5-23 4082/03 BURR - BROWN ® IElElI GENERAL PURPOSE COMPARATOR FEATURES • RELAY AND LAM~~DRIVING CAPABILITY Up to 100mA LOAD • TRANSIENT PROTECTION T0400mA • RESPONSE TIME AND HYSTERESis ADJUST Input DESCRIPTION Model 4082/03 is a low cost hybrid integrated circuit comparator in a dual-in-line package. It combines a low-cost differential input comparator with an open collector transistor output stage capable of sinking IOOmA. With transient protection of 400mA, this unit is an excellent choice to drive lamps, relays, and other devices with high transient requirements. In addition, the open collector output wilIaccept up to + 30VDC making the 4082/03 compatible with MOS circuitry and high noise immunity logic as well as TTL and DTL devices. The 4082/03 operates from ±15VDC power. Additional outputs are provided for response time control and hysteresis feedback. .OPERATION Model 4082/03 will function when power is applied and the output IQad is connected between Pin 9 and Pin 13. The load may be resistor; lamp, or relay. A simplified diagram in .shown in Figure 1. Either input may be connected to common or to some reference voltage. Whenever the (+In) input is positive with respect to the (-In) input, the output transistor is switched ON. The load power (+VIt) may be any voltage up to + 30VDC. j +In l-In~-..~ -15VDC 0-;:;""'--1 L......_.:.;II~ Response Time Control FIGURE I. Simplified Diagram of Model 4082/03 Comparator. HYSTERESIS Hysteresis may be added by means of positive feedback as shown in Figure 2. The amount of hysteresis is approximately: Hysteresis ... 26V Ro/R r + Ro, Rf~ 10kn Adding hysteresis provides better noise immunity, but at the price of decreased switching resolution. RESPONSE TIME Response time can be decreased if desired by adding capacitance between Pin [[ and Pin [2 (common). This will limit the rise and fall times of the output voltage, which in turn limits turn-on surge currents when driving lamps. . Internallonal Alrpart Indllllrial Park - P.O. Box 11400 - TUClon. Arizona 85734 • Tal. (602) 746·1111 . Twx: 911J.952-11I1 - Cabla: BBRCORP . Talax: 66-6491 PDS-399 5-24 ELECTRICAL SPECIFICATIONS Hysteresis Feedhack Typical performance at 2S"C and with rated supplies unless otherwise noted. MODEL 4082,03 INPUT Signal Levels Either (or both) Inputs ±10 Absolute Maximum ±15 Impedance (both Inputs) Differential. small signal Differential. large signal Common-mode Bias Current af 25"C Over Temperature Range. (max) Differential Offset Current at 2S"C Over Temperature Range. (max) Units V V Input Signal Ro +IN -IN o-------{4 4082/03 Out 300 10 100 400 700 ±30 ±80 kll kll Mll nA nA nA nA FIGURE 2. Connections for Adding Hysteresis. OUTPUT SWitched Current Sink Impedance to common from output OFF state ON state Load Voltage Supply (V R ) Load Current (sinking) Transient (absolute maximum) ACCURACY Sensitivity, (min) Offset Over Temperature (max)iJl at 25"C I 3 Up to +100 +400 Mll II V rnA rnA ±O.I mV o to +30 MODEL 4082/03 ±12 mV mV ±3 ±50 p,V, V 7 ~sec TEMPERATURE RANGE Operating, Rated Specification Operating, Derated Performance Storage -25 to +85 -40 to +85 -55 to +100 "c "c "c POWER SUPPLY REQUIREMENTS (-V and +V) Rated Supply Voltage Voltage Range Supply Drain. (max) ±15 -14 to +16 ±12 V V rnA vs Power Supply FREQUENCY RESPONSE Total Switching Timel"1 at 20mV Step Input MECHANICAL SPECIFICATIONS 6.35mm (0.251 3.81mm (0.151tYp 13.0mm 10.51") I. This offset is referred to the input and includes offset due to common-mode effects. 2. With load supply of +J5VDC and with output load of 300il. Total switching time includes delay time and rise time. The input E1... is a sine wave of frequency f... (Bottom View) WEIGHT: 0.12 oz. (3.40 grams) GRID SPACING: 0.1" (2.51 MATERIAL: Black Epoxy PIN: Pin material and plating composition conform to Method 2003 (solderability) of MIi-Std-883 (except paragraph 3.2) CONNECTOR: Standard 14 pin DIP socket 5-25 4085 BURR-BROWN® IElElI PEAK ~ D\"lH:10~ @~ 4r"8~")K(; HYBRID MICROCIRCUIT PEAK DETECTOR FEATURES • STORES TRANSIENT VOLTAGES • COMPLETELY SELF-CONTAINED • ACCURATE TO ±D.Ol% • LOW DROOP ERRORS • SMALL DIP PACKAGE DESCRIPTION The 4085 is a specialized sample/hold amplifier that tracks an input signal until a maximum amplitude is reached. That maximum value is held at the analog output, and the digital STATUS output indicates that a peak has been detected. The unit can then be commanded to hold that value, ignoring additional peaks, or reset to a user-specified reference voltage. The 4085 detects positive-going peah from -lOY to +IOV and is available in a hermetic metal package and a low-cost ceramic package. Three models are available, specified for temperature ranges 0 to +70°C (4085KG), -25 to +85°C (4085BM), and -55 to +125°C (4085SMt International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 7411-1111 . Twx: 91(1.852·1111· Cable: BBRCORP· Telex: 66-6491 PDS·· 5-26 THEORY OF OPERATION In the PEAK DETECT mode (S I closed, S2 open), the analog output tracks the analog input until a peak value is . reached. When the input voltage falls below the magnitude of the peak voltage, CR I becomes reversed biased, and the feedback loop between AI and A2 is broken. At this point, the status output transistor turns on and the magnitude of the peak voltage is held on the analog output. In the HOLD mode (SI open, S2 open), the current charging path from the output of AI to the capacitor is opened. The output voltage is equal to the Status Return (1) NC NC -- Common NC V S- NC voltage stored in the capacitor even though the input voltage may become larger than the peak voltage. In the RESET mode (S I open, S2 closed), the voltage on the capacitor will charge to whatever voltage is applied to the RESET voltage input. If both S I and S2 are closed at the same time, the output of A I will be connected to the reset voltage input through a low impedance. This represents an illegal mode of operation, but will cause no damage to the unit. NC Status Output NC Logic NC Reset Voltage Analog Output NC t::\ NC 2 Input Notes: Offset Adjust Q NC Power Supply Logic Input 1. Pin 21 internally connected to case on 4085BM and 408SSM. 2. External capacitor: use polystyrene (up to +8S o C). polyproplene, or teflon. Optional External ( Capacitor 2) 3. Pin 13 must be connected to either power supply, common or user-specified reference \!Y ~no:~~ FIGURE I. 4085 Functional Diagram and Pin Configuration. ,. ... ANALOG INPUT (dotted) " ~~g;f----7 " ,, I I "\ ,, I , " I " , ... ., ., .,'" ," '" OV "I" I I LOGIC A "0" INPUT :.- reset _;'---peak-detect - - - ...,t. - - - - - - - hold - - - - - - -... t "I" LOGIC INPUT B "0" STATUS TRAN· SISTOR ·.,i,..._---reset - - I' I L Off On I n I FIGURE 2. Timing Diagram For Peak-Detect Operation 5-27 I I ELECTRICAL SPECIFICATIONS Specifications at TA = +2S oC and ±15VDC and +SVDC power supplies unless otherwise noted. 4085 MOOEL MIN TYP UNITS 4085 MODEL MAX ANALOG INPUT ANALOG OUTPUT Signal Inputs Operating Range Absolute Maximum Range Voltage Range Output Current Output Resist . .go u "= 100 1.0 ,~ ~ f:; o~ = 0 '=" C' ~ 0.1 Iii ;; e .!! " ~ 5 10 IS Input Voltage Step Change (Volts) 0.001 0.01 20 FIGURE 3. Acquisition Time ~ 0.1 >. u ~~ >. Iii I ""~ o·o'>t.'" I .... If 0.1 1.0 10 100 Acquisition Time (msec) ~ 1.0 ~ ~ 1.0 S' ;; ) FIGURE 4. Acquisition Time 10 Q ~ .... 0.01 ~ 10 ~ ) U ~.o~o :3 I. ~II ~ S' " 0 ~ ~~ lvp l_~vp II u 10 .~ = 1/ 0.01 >. Q 1"00. 1'-100.. 100 Ik Input Frequency (Hz, Sine Wave) 1/ < r.;;::: r-.... II 0.01 0.1 ~ liu "''' 0.001 100 10k FIGURE 5. Status Output Delay Ik 10k Input Frequency (Hz, Sine Wave) FIGURE 6. Dynamic Accuracy 5-29 1000 ~_O~,"P......;;.E_B~A_T~~IN~"~G_"_IN...;...S_T_R_U_C...;....T_IO~,'_N...;....s_----JI ',&....I signal track: Zout ""CO; ,peak hold: Vout = +Vs - 0.5 volts. Several configurations are iliustrated in Figures 9 through II. "Inverting" m,eans logic "0" = peak has been detected, "N oninverting" means logic "I" = peak has been detected. OFFSET VOLTAGE ADJUSTMENT The ±2mV input offset voltage of the 4085 may be nulled to zero by using the circuit shown in Figure 7. With the 4085 in the PEAK DETECT mode (logic input A = "I", logic input B = "0") apply zero volts to pin I. Adjust the potentiometer until the output voltage is zero volts. Disconnect pin 12 after adjustment is made. ~ -ISV ,... ~ 10k ....I... f -- To TTL (fan·out = 10) 10k Pin 2 2k'to 10k -llooppm/oC ' S60k 10M - (Remove 2.0kn resistor for 1 SV CMOS logic) Pin 3 Pin 12 FIGURE 9. Inverting TTL (CMOS) STATUS Output. 2SnA FIGURE 7. Offset Adjust Circuit ,+sv 10k POWER SUPPLY CONSIDERATIONS .......""'..-_(. 1-_--.. To TTL The 4085 will operate as specified with power supplies from ±8VDC to ±18VDC. To minimize noise pickup, the supply inputs should be decoupled with Illl"tantalum capacitors located physically close to the unit. FIGURE 10. Noninverting TTL STATUS Output. DIGITAL INPUTS AND LOGIC SUPPLY 10k The digital inputs may be driven with TTL or CMOS' logic. Pin, 8 should be tied to the logic supply. The logic supply voltage (Vd may also be provided by connecting pin 8 through a resistor of value R(kcihms) = 1.67 (Vs Vd/VL to the +Vs supply (Vs;;' Yd. The logic threshold voltage is equal to 0.4 VL - 0.7 volts. FIGURE II. Noninverting CMOS STATUS Outllut INPUT FREQUENCY BANDWIDTH LIMITING DESIGNING IN HYSTERESIS It is recommended that the input bandwidth be limited as much as possible by an RC section such as that shown in Figure 8. This is to limit noise spikes at the input that may cause erroneous readings. If detecting large pulse heights, a 5 Ilsecond time constant should be used. This will not degrade acquisition time or ttacking accuracy for frequencies up to 500 Hz. For input frequencies greater than 500 Hz, a smaller time constant may be used. It may be desirable in some situati'ons to have hysteresis in the circuit such that small peaks will not be detected, eliminating jitter in the STATUS output. This is possible through external components connected as shown in Figure 12. After a peak is detected, the input voltage must be slightly greater (deterinined by R I / R2) than the previous peak to cause the output to resume tracking the input. This hysteresis voltage is expressed by: ,..·w--:t:..-----Q Yin ()--J\."' .. Ik V Pin.1 = (Vin - H ,~4700pF VE Rl - 0.9V) RI + R2 The emitter voltage of the status transistor should be tied to a voltage sufficiently lower than the lowest expected peak to allow proper operation. FIGURE 8. Input Bandwidth Limiting STATUS OUTPUT CHARACTERISTICS "The open-collector, open-emitter output transistor is a small signal, medium speed switching transistor similar to a 2N2222. To facilitate driving a variety of devices, the configuration of the status output has been left to the user's discretion. The internal comparator shown in the block diagram (Figure I) has an output characteristic as follows. Input R Status Output FIGURE 12. Hysteresis 5-30 APPLICATIONS PEAK CATCHER INTERFACING TO A/D CONVERTER This circuit detects and holds the first peak it encounters, After the first peak is detected, it automatically is switched to the hold mode. To reset the circuit for catching another peak, a 10 ILsec or longer positive logic pulse should occur at the "RELEASE" input. This will reset the peak detector to the desired voltage and put it in the peak-detect mode. Interfacing to an AI D converter is straightforward. The gating of the AI D converter command allows a conversion only if a peak has been detected and permits completion of each conversion. Ifa peak occurs while the AI D is converting, it will not be detected. Release 0-......- .... Input 220n FIGURE 15. AID Converter Interface PEAK-TO-PEAK DETECTOR FIGURE 13. Peak Catcher NO-RIPPLE, FAST SETTLING RMS-DC CONVERTER If a waveform is known, the RMS value of the signal may be computed from the peak value. In this circuit, the RMS value is computed by the output amplifier from the peak value held by the 4085. The output in the circuit shown is updated manually. It may be updated automatically by replacing the switch circuit with an oscillator plus timing logic. Figure 16 shows a circuit that will display the peak-topeak voltage of an input waveform. The ST ATUS output indicates that both positive and negative peaks have been detected and that the output is valid. The resistors around A3 should be matched to insure good common-mode rejection. Vin 0---_4 A B FIGURE lb. Peak-to-Peak Detector FIGURE 14. RMS-DC Converter 5-31 4115/04 BURR,BROWN@ 1E3E31 WINDOW COMPARATOR FEATURES APPLICATIONS • ADJUSTABLE LIMITS FOR "HIGH", "LOW", AND "GO" • PRODUCTION LINE TESTING • UP TO 2DDmA LOAD CAPABILITY leach output) • TEMPERATURE CONTROLS • INDUSTRIAL ALARMS • INPUT PROTECTION • LEVEL DETECTORS/CONTROLS DESCRIPTION ModeI4115/04 is a hybrid IC window comparator in a double width DIP. The unit has three inputs - one for a voltage that sets the upper limit, another for a voltage that sets the lower limit, and a signal input. There are three mutually exclusive outputs - HIGH, LOW and GO. When an output is ON it will sink up to 200mA of current. This input diode protected device is designed to work with input voltages of up to ± IOV, and will not be harmed by voltages to ± 15V. The 4115/04 will drive a variety of loads including lamps, relays, MOS circuitry, and high noise immunity logic as well as DTL and TTL devices. r-----.-;-;s-;;;.-- - - --, lIpp~r 2 o-i'w...-......r--. Input 1:' OJ~M~ 'jiKnal -I I I8 L ____________":"1 --.J luwer 5 limit l-: lo-;1 3 Mil II V +200 rnA +400 rnA 0.7 V ·2510 +85 -40 10 +85 ·5510 +100 "C ±15 ·1210 ±18 ±15 VDC VDC rnA OUTPUT Impedance to COMMON from all Outputs OFF state ON state Load Supply Voltage (Y R) load Current Steady State Transient (absolute maximum) I Second Duration Saturation Voltage (Vll) (max) at 200mA TEMPERATURE RANGE Rated Specifications Derated Performance Storage "C :'C POWER SUPPLY REQUIREMENTS Rated Supply Voltage Derated Performance Quiescent Drain (max) To achieve best results use stable quiet reference sources and drive signal input from low impedance source. Noise and drift in input sources readily masks the inherently high resolution of the device. \ 5-33 (Bottom View) ( WEIGHT: 0.24 oz. (6.80 grams) MATERIAL: Black Exoxy PIN: Pin material and plating composition conform to Method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2). CONNECTOR: Fits any commercial dual-in-line connector. 4127 BURR-BROWN@) IElElI lOG AMPlIfllR ~ 1 4111KG ~;iiiJi.IJ;4Y"""''-'1'''« =~ if41ili:-Jifi;l;;; ~.<."._.... ~'!...~LL Ih /1', LOGARITHMIC AMPLIFIER FEATURES • ACCEPTS INPUT VOLTAGES OR CURRENTS OF EITHER POLARITY • WIDE INPUT DYNAMIC RANGE 6 Decades of cu rrent 4 Decades of voltage • VERSATILE . Log, antilog, and log ratio capability • SMALL SIZE Doublewlde DIP • LOW COST DESCRIPTION Packaged in a ceramic doublewide DIP, the 4127 is the first hybrid logarithmic amplifier that accepts input signals of either polarity from current or voltage sources. A special purpose monolithic chip, developed specifically for logarithmic conversions, functions accurately for up to six decades of input current and four decades of input voltage. In addition, a newly-developed current inverter and a precise inter.nal reference allow pin programming of the 4127 as a logarithmic, log ratio, or antilog amplifier. To further increase its versatility and reduce your system cost the 4127 has an uncommitted operational amplifier in its package that can be used as a buffer, inverter, filter, or gain element. The4127 is available with initial accuracies (log conformity) of 0.5% and 1.0%, and operates over an ambient temperature range of -100C to +70 0 C. With its versatility and high performance, the 4127 has many applications in signal compression, transducer linearization, and phototube buffering. Manufacturers of medical equipment, analytical instruments, and process control instrumentation will find the 4127 a low-cost solution to many signal processing problems. Intemllional Airport Industrial Park - P.O. Box 11400· Tucson. Arizona 85734· Tal. (802) 746·1111 . Twx: 910-952·1111 • Cabla: BBRCORP • Talax: 66-8491 PDS-3468 5-34 GENERAL DESCRIPTION The 4127 is a complete logarithmic amplifier that can be pin-programmed to accept input currents or voltages of either polarity. By making use of the internal current inverter, reference current generator, log ratio element, and uncommitted op amp, you can generate a variety of logarithmic functions, including the log ratio of two signals, the logarithm of an input signal, or the antilog of an input signal. The unique FET-input current-inverting element removes the polarity limitations present in most conventional log amplifiers. Utilizing the inherent exponential characteristics of transistor functions, the 4127 calculates accurate log fUnctions for input currents from 1 nA to 1 mA or input voltages from 1 m V to 1 () V. Carefully-matched monolithic quad transistors and temperature sensitive gain elements are used to produce a log amplifier with excel/en t temperature charac teris tics. THEORY OF OPERATION A functional diagram of the 4127 circuit is shown in Figure 1. Besides the basic log amplifier, the 4127 contains a separate internal current source, a current inverter, and an uncommitted operational amplifier. The current inverter accurately converts negative input current to a positive current of equal magnitude. If the transistors Q I and Q2 are at the same temperature and have matched characteristics then E2 = m K T q E2 = -mK T ~~ q IR The output op amp A2 provides a voltage gain of approximately (RT + R2)/RT, and the value of m K T/q is about 26mV at room temperature. Since resistor RT varies with temperature to compensate for gain drift. the output voltage Eo expressed as a log will be The4127 is capable of accurately logging input current over a 120dB range, but to use this full range good shielding prac· tice must be followed. A current source input is, by definition, a high impedance source, and is therefore subject to electrostatic pickups. The input op amps A I and A3 have FET input stages for low noise and very low input bias current. The op amp A I will make the collector current of QI equal to the Signal input current IS, and the collector current of Q2 will be the reference input current IR' Eo=-AIOgIO~ IR RT+ R2 I where A '" ~ (26 mY) 0,434' RT '" 520n From the semiconductor junction characteristics, the baseto-emitter voltage will be The external resistor RI sets the reference current IR and resistor R2 sets the scale-factor "A". The two resistors must be trimmed to the desired values, but graphs in Figures 2 and 3 show the approximate relationships. VBE '" m KT.in!!;;, where IC = Collector current q IL IL = Reverse saturation current q, m, K = Constants T = Absolute temperature and q - EI [k ILIR -A ISJ ILJ Figures 4 and 5 illustrate the relationship between the input current IS and the output voltage Eo in terms of the externally adjusted parameters IR and "A". This relationship is, of course, restricted to values of IS between 1 nA to 1 rnA and output voltages ofless than ±10V. mKT211 IR = --,tAtq IL2 2=520n Thermistor +15V inverter input @ FIGURE 1. Functional Diagram. 5-35 -15V SPECIFICATIONS· Typical specifications at +2S o C with rated supplies unless otherwise specified. MECHANICAL ELECTRICAL 4127KG 4127JG ACCURACY, (I) % of FSR Current Source Input:, 1nA to 1 rnA Voltage Input: ImV to 10V 0.5% max 0.5% max 1% max 1% max INPUT Current Source Input, Pin 4 +lnA to +lmA -InA to -lmA Pin 7 Reference Current Input, Pin 2 Absolute Maximum Inputs +l~A to +lmA ± lOrnA or. ±Supply Volts OUTPUT Voltage Current Impedance ±IOV ±SmA Ion diam. (0.20") - FREQUENCY RESPONSE -3dB Small Signal at Current Input ofIOO"A 10"A I"A 100nA 10nA Step Response to within ± 1% of Final Value (JR ; I"A, A ; 5) 90kHz 50kHz 5kHz 250Hz 80Hz IOmsee Pin 1 2.5mm ....1-_____-++_(0.10 .. ) 00 000 000 (BOTTOM 15.2mm VIEW) (0.60") STABILITY Scale Factor Drift (1\ A/oC) Reference Current Drift (1\ IR~C) Input Offset Current Drift (1\ Isl°C) 000 ±O.0005A~C 00 00 ±O.OO I IR/oC for IR ;;. I"A ±0.003 IR/oC for 400nA < IR < I"A tOpA at +2S o C, Doubles Every IOoe Input Offset Voltage Drift Accuracy VS. Supply Variation Reference Current Input Offset Voltage Input Noise - Current Input Voltage Input CASE: ±I0"V/oC PIN: ±O.OOIIR/V ±300" V/V IpA RMS, 10Hz to 10kHz 10"V RMS, 10Hz to 10kHz WEIGHT: Black Ceramic Mating Connector 245MC Pin material ,and plating co'mposition conform to' method 2003 (!Solderability) of Mil-Std-883 (except paragraph 3.2) 56 grams, (2 oz.) UN.COMMITTEO OP AMP CHARACTERISTICS Input Offset Voltage Input Bias Current Input Impedance Large Signal Voltage Gain Output Current 5mV 40nA IMn 85dB SmA TEMPERATURE RANGE Specification Operating Storage OOC to +60 0 C _10°C to +700 C _55°C to +125 o C POWER SUPPL Y REQUIREMENTS Rated Supply Voltages Su pply Voltage Range Supply Current Drain at Quiescent (max.) at Full Load (max.) '(I) Log conformity at 25°C ±15VDC ±14VDC to ±16VDC ±20mA ±26mA PIN DESIGNATIONS 1. 2. 3. 4. 5. I REF Output I REF Input No Pin Present +1, Input Current Inverter Output 6. No Pin Present 7. 8. 9. 10; 11. 12. Current inverter Input Na Pin Pre~nt Op Amp +Input 13. 14. 15. 16. Make No Connection Negative Suppry Op Amp -Input Op Amp Output No Pin Present No Pin Present No Pin Present 17. No Pin Prasent 18. Log Output 19. Gain Adjust 20. No Pin Present 21. Common 22. Positive Supply 23. I REF Bias 24. No Pin Present NOTE: Pin 4 is internally connectecIto pin 5:. TYPICAL PERFORMANCE CURVES A-Volts 100"A "\ 10V " BV "~ 7V 4V 10nA 10kn 100kn ~ l{ lV ;R l/ o lMn 10Mn o 100Mn EO = -A 10910 I 20kn I W- I-IR 40kn 60kn BOkn FIGURE 3. Relationship of scale factor "A" to gain-setting resiStor R2' FIGURE 2. Relationship of Reference Current IR and external resistor R1' Output Voltage Output Voltage 10V 4A / / 3V 2V EO = -A 10910 ~ " / , 6V 5V ~ 100nA I ~ 9V E o =AI09~ 1IJA A= 10V Eo -Volts +SV 2A Input Current IS -SV -2A -10V -4A FIGURE 4. Log Relationship of~ and output FIGURE 5. Relationship of11S lto output voltage IR for IR = 1/lA and A = 5V and 10V. voltage in terms of "A". DISCUSSION OF SPECIFICATIONS ACCURACY The deviation from the ideal output voltage defined as a percent of the full scale output voltage. INPUT/OUTPUT RANGE The log relationships of -A log ~ and -A log ~ are subIR IRR ject to the constraints specified. The 4127 can be operated with inputs lower than those given, but the accuracy will be degraded. STABILITY The use of a monolithic transistor quad and low·drift op amps minimizes drift, but some drift remains in the scale· factor, reference current, and input offset. Input offset con· sists of a bias current plus the op amp input voltage offset divided by the signal source resistance. Also, there is some slight drift in conformity to the log function and in output amplifier offset, but this is generally negligible. FREQUENCY RESPONSE SCALE FACTOR A AND REFERENCE CURRENT IR' The small-signal frequency response varies considerably with signal level and scaling, so the frequency response is specified under several different operating conditions. Refer to CHOOSING THE OPTIMUM SCALE FACTOR AND REFERENCE CURRENT. 5-<37 CIIOOSING TH,E OPTIMUM SCALE ~ACTOR AND REFERENCE CURRENl To minimize the effects 9f outpu t offset and noise, it is usually best to use the full ± IOV , Qutputrange. Once an output range of±IOV' has been chosen, then "A" and IR 'cari be' determined frortl the min/max of the input current IS. CONNECTION DIAGRAMS Ifcurrent inverter is not used leave pin 7 open. Transfer functiOli is Eo = -A log!! where I I ;s a IR and IR is the resistor-programmed internal reference current. Reference Current Eo = -A log.!§, where 'min < IS < Imax IR The output range of ±IOV for an input range of Imin to Imax means that I . ' I ,+10 = -A log..!!!!!l and -IO=-A log max IR IR Adding these two equations together '" I Imaxlmin;.. 0 I - ~---" og ~ - , or R - / Imax1min po~itive input current - 0 +15V r:' ._. ~:k R .. 4 * Needed on"IV if 'I < 10nA 0 -15V FIGURE 6. ADJUSTMENT PROCEDURE I. Refer to top of rage for choosing optimum scale factor and reference current. The value for A can be found from: 2. Apply I I = IR' adjust R I such that Eo = O. I 10 = A logr.m~ax~= ;Imax l min 4. Repeat steps 2 and 3 if necessary. 3. Apply I I = Imax , adjust R2 for the proper output voltage. S. Ignore this step ifl I min ;;;>IOnA. Otherwise, apply II = InA, In tenns of the input current range for IS, the values for IR and A that will provide a full ±IOVoutputswing are: make R3 = IkMn*and adjust ~for the proper output voltage. 10 Transfer function is Eo = -A logl:~lwhere II is a negativ~jnput current and IRis the reSistor-programmed internal reference cur~ent. Example: Assume that lmin is +IOnA and Imax is + I OOJ.lA. Current This is an 80 dB range. JImaxlmin IR = * Needed· on.ly J(l0-4) (l0-8) = 10-6, or IJ.lA. I +15V 10-4 max=--=IOO IR Icr6 'r log~= if 10k 'I ,<10nA -15V FIGURE 7. ADJUSTMENT PROCEDURE 2 So A=S IR I. 'Refer to'top of page for choosing optimum scale factor and reference 'current. ' 2. Apply II II = IR adjust RI such that Eo = O. Ii = Imax, adjust R2 for the proper output voltage. For an IR of IJ.lA and A of S, 3. Apply II Eo =.:S log ~ 4. Repeat steps 2 and 3 if necessary. IJ.lA S. Ignore this step iftllminl;;;>lOnA. Othe~ise, apply II1I = InA, .. Single r..istor recommended. Voltage divider network make R3 = IkMn and adjust ~ for the proper output voltage. difficult to use due to amplifier offset voltage. RFSOO-I08, , _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J 1k meg resistor available from BUI1.::-Brown. , CONNECTION DIAGRAMS Transfer function is Eo =-A log~, where E, is a positive input voltage and 'R is the resistor-programmed internal R41R reference current. ADJUSTMENT PROCEDURE Reference Current 1. Refer to CHOOSING OPTIMUM SCALE FACTOR AND REFERENCE CURRENT_ 2. Apply El = 'R (lOkn), adjust Rl such that Eo = O. 3. Apply E, = Emax , adjust R2 for the proper output voltage. 4. Apply E, =Emin, adjust R3 for the proper output. S. Repeat steps 2 through 4 if necessary. +lSV -lSV NOTE: If lockup occurs at low input levels, pin 4 should be connected to pin S. 10k FIGURE 8_ Transfer function is Eo =-A log -.!.!! ,where EI is a negative input voltage and IR is the resistor-programmed internal R4 I R reference current. ADJUSTMENT PROCEDURE Reference Current 1. Refer to CHOOSING OPTIMUM SCALE FACTOR AND REFERENCE CURRENT. 2. Apply IEII =IR (I0kn), adjust R, such that Eo =O. 3. Apply IE,I = Emax , adjust R2 for the proper output voltage. 4. Apply IEll 100M =Entin' adjust R3 for the proper output. S. Repeat steps 2 through 4 if necessary. 10k + ISV o--.J>JIIY---(J -ISV FIGURE 9. ADJUSTMENT PROCEDURE Gain * Needed only if 1111< lanA t RS 1. Refer to CHOOSING OPTIMUM SCALE FACTOR AND REFERENCE CURRENT. 2. No further adjustment is necessary if I I min;;;' IOnA, otherwise connect the R3 and ~ network, with ~ =10k and R3 = 109 n. Adjust ~ for proper output voltage after adjusting gain errors. Since the voltage at pin 4 is in the range of tSmV, it is not practical to use a T - network to replace R3' = R6 ±1% FIGURE 10. 5-39 ADJUSTMENT PROCEDURE 1. Refer to· CHOOSING OPTIMUM SCALE FACTOR Gain * Needed only ;fI1 1 1< 10nA AND REFERENCE CURRENT. 2. No further adjustment is necessary ifII Ilmin;;' IOnA, otherwise connect the R3 and R.! network, with R.! = 10k and R3 = 109n. Adjust R4 for proper outl'ut. voltage after adjusting gain errors. Since the voltage at pin 4 is in the range of iSm V, it is not practical to use a T - network to replace R3. FIGURE 11. Transfer function is Eo = -A log.!! with I I and 12 positive; I I ;;. InA, 12 ;;. lilA. 12 -15V ADJUSTMENT PROCEDURE 1. Refer to CHOOSING OPTIMUM SCALE FACTOR Gain * Needed only if I, < 10nA AND REFERENCE CURRENT. ' 2. No further adjustment is necessary if 11 min;;' IOnA, otherwise connect the R3 and R.! network, with R4 = 10k and R3 = 109n. Adjust R4 for proper output voltage after adjusting gain errors. Since the voltage at pin 4 is in the range of iSmV, it is not practical to use a T - network to replace R3. FIGURE 12. ANTILOG OPERATION The 4127 can also perform the antilog function. The output is connected through a resistor Ra into the current input, pin 4. The input signal is connected through a gain resistor to pin 19 as shown in Figure 13. These connections form an implicit loop for computing the antilog function. From the block diagram of Figure 1, the voltage at the inverting input of the output amplifier A2 must equal E2, so RT RES' RT ~S20n E2 "" - R T+ 2 Since the output is connected through Ro to pin 4, the current IS will equal EotRa and E2 will be where RT+ R2 I A "" ~ (26mV) 0.434 Eo = Ro IR Antilog - ES A Setting Ro and IR will set the scale factor. For example, an Ro of I Mn and I R of lilA will give a scale factor of unity and . ES Eo = AntIlog - A E2=_mKTin~ q RaIR Combining expressions for E2 gives the relationship Set A ~ mKTl". Eo Rr +R2 ES = - - q - ' Ra IR Insert O.Ol~F between Pin 18 and Pin 19 if the unit oscillates. ES Eo - -=Iog--' A RaIR -100M +15V 10k Offset Adjust FIGURE 13. 5-40 -15V BURR-BROWN® 4203 4205 IElElI Integrated Circuit MUlTlillIER-DIVIDERS FEATURES APPLICATIONS • LASER-TRIMMED Requires No AdJustment • MULTIPLICATION, DIVISION, SQUARING, SQUARE ROOTS • GUARANTEED ACCURACY -1% or 2% • RMS MEASUREMENTS • SELF-CONTAINED No Additional Amplifiers • FREQUENCY DOUBLER • FAST SLEWING - 25V/Ilsec • SMALL PACKAGE - TO-l 00 • BALANCED MODULATOR AND DEMODULATOR • ELECTRONIC GAIN CONTROL • FUNCTION GENERATOR AND LINEARIZING CIRCUITS • PROCESS CONTROL SYSTEMS DESCRIPTION Burr-Brown Models 4203 and 4205 are integrated circuit multipliers designed for general purpose usage. In addition to four-quadrant multiplication they also perform division and square rooting of analog signals, requiring no additional amplifiers in performing the above functions. They are lasertrimmed prior to final packaging and are guaranteed to their rated accuracy with no external components. This is a distinct advantage from the standpoints of cost and reliability. These multipliers contain their own zener-regulated references and, as a result, are much less sensitive to supply voltage vanatlOn than were earlier Ie multipliers. The fast (25Vj Ilsec) slew rate and I MHz bandwidth are key performance factors for applications where delay phase shift must be minimized. Harmonic distortion of the 4203 and 4205 remain low for freq uencies well above i OOk Hz, an important asset in modulation applications. Other desirable features are hermetic TO-I 00 package (IO-pin version of TO-99) and wide temperature range of operation. The 4203S and 4205S are specified for operation over thefull MIL temperature range. International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 1602) 746-1111· Twx: 911).952·1111 . Cable: BBRCORp· Telex: 66·6491 PDS473 5-41 SPECIFICATIONS ELECTRICAL Typical at +25°C with ,atBd power supplies unless otherwise noted. Percent specifications refer to % of full scale 110VI. MECHANICAL 4203J/420SJ I 4203K14205KI4203SI4205S MODEL 4205 TOTAL ERROR" Internal Trim 2%, max 1% External Trim vs Temperature vs Supply I INDIVIDUAL E R R O R S ' Output Offset at +25°C IX - V - 0) vs Temperature (Operating Range) vs Supply Scale Factor Error vs Temperature IOperating Rangel vsSupply Nonlinearity XIX = 2OV, pop; V = ±10VOC) VIV = 2OV, pop; X = ±10VDCI NOTE; Leads in true position within 0.10" (0.25mm) R at MMC at seating plane. I XV/l0 I IX, - X211V, - V2)/l0 OUTPUT FUNCTION 4203 1% I 0.8%' I I 1%,max 0.6% O.04%fOC 0.2%1% 20mV, max 0.4mVfOC 10inV/% 0.6% O.04%fOC 0.1'%/% 0;5% 0.2% 1%,max 0.6% I 0.6% I 0.5% Pin numbers shown for referen'te only. Numbers may not be marked on package. Feedthrough at 50Hz X = 0, V = 2OV, POP I I nternal Trim, (External Trim 1 V$ Temperature V =0, X = 2OV, pop I Internal Trim, (External Trim) va T~mperature AC PERFORMANCE Slew Rate -3dB Small Signal Bandwidth 1% Amplitude Error . 1% Vector Error (0.57° phase shift) Settling Time 12% of final value, 20V, step' Overload Recovery Time OUTPUT NOISE (X =V =0) 10kHz to 10MHz 10Hz to 10kHz INPUT CHARACTERISTICS Input Voltage Hange Rated Operation Absolute Max Input Impedance, X V Z OUTPUT CHARACTERISTicS Rated Output Output Impedance POWER SUPPLY REQUIREMENTS Hated Voltage Operating Range Quiescent Current 5OmV, pop 20mV, p,p lmV, p-pfOC" 5OmV, pop 20mV, pop 2m\', p-pfOC Storage "JI>~' \ ~~ " 25V1p.sec lMHz , 40kHz 10kHz. DIM A B 1.usec 'c 3psec 0 E ·3~V. F rrns 600p.V, rms G H J K ±10V ±15V 10MII 10MII 36kll L M N ., i '\-...!o .......... H, . ORDER NUMBER; 4203J, 4205J '1203K, 4205K 4203S, 4205S WEIGHT; , 1 gram r---'f.. -J --....., INCHES MIN MAX MILLIMETERS MIN MAX .335 .305 .370 .335 8.61 7.76 9.40 8.61 .165 .016 .010 .185 .021 ,040 4.19 0.41 0.25 4.70 0.53 1.02 .010 .040 .230 BASIC .028 .034 .... .04' - .500 ,160 .120 36° BASIC .110 .120 0.25 1.02 5.B4 BASIC 0.71 0.86 0.74 12.70 1.14 ~.05 '.06 - 36° BASIC 2.79 3.05, CONNECTION DIAGRAM ±10Vat±5mA .10 ±15VDC ±1 2VDC io ±1aVDC ±4.5mA· TEMPERATURE RANGE Operating, Rated Performance ,." , t '.. COC to 7COC I '~",~ v+:u':' :" -55°C to +125°C -65°C to +1SCOC ZIN J OUT • Xo ',,--"..!. X,N V- ,TOP VIEW, 4203 *Total efror is a tested maximum at +25°C and represents the maximum allowed value for the sum of the individual errors. V" V+ , ZIN J J it .:2. ZO 8 COM 7 X2 OUT~X, V,TOP VIEW, 4205 5-42 4204 BURR -BROWN@ IElElI ANALOG MULTIPLER-DIVIDER FEATURES IMPROVE SYSTEM ACCURACY :!;O.25% and :!;O.5% units LOW COST 0.5% accuracy IMPROVE ACCURACY OVER TEMPERATURE - :!;O.o2%/OC max SIMPLIFY ASSEMBLY Laser-trimmed at the factory No external components required ,- - - - - - - - - -- - --....1 I I I 1 1 1 I 1 I I 1 I I ,- - - - - - - - - - " I I 1 I 1 1\. _ _ _ _ _ _ _ _ _ _ _ _ _ .1I Log amp 1- - i - - - - - - - - - - - .... I 1 Output .". 1 1 "- - - - - - - - - - ~ I 1 I 1 1""' I Antilog Amp ___________ _ ,J1 Log amp Inlernallonal Alrportlnduatrlal Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (602) 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 PDS-3 II A 5-43 DESCRIPTION multiplier/divider ever offered. Just as Burr-Brown was first to offer internally laser trimmed Ie multipliers with accuracies of I % and 2% (Model 4203), we have now extended this money saving technology into the accuracy' areas where oilly higher priced modules were previously available. The excellent tracking characteristics of adjacen t monolithic transistors is key element in maintaining the 4204's high accuracy performance over the temperature range. By variation of external pin connections, the 4204 may be used as a divider or square rooter. No external amplifiers are required for either operation. The 4204 is an internally trimmed four quadrant analog multiplier/divider using the log/antilog technique. This method yields excellent accuracy, low noise and moderate bandwidth-at low cost. No external components or amplifiers are required with the 4204. Accuracy speCifications are guaranteed without external adjustments and are verified at Burr-Brown by an automatic tester which scans the X-V plane. Maximum error at any point in the plane is required to be less than the specified values. a The laser trimmed 4204 is the first high accuracy hybrid Ie THEORY OF OPERATION extremely temperature sensitive. The 4204, however, has excellent temperature characteristics because the log and antilog circuitry have equal and opposite temperature drifts which cancel to a first order approximation. The log and antilog circuits will compensate each other to the extent that the various logging transistors are matched to each other. In the 4204 these transistors are placed adjacently on a monolit.hic chip to obtain the best possible matching and so the best possible performance. The 4204's log-antilog multiplication technique is based upon the logarithmic voltage-current relationship in a semiconductor junction. This action is shown by this simplified equation: Vbe =(~T)(ln Ic -In Is) where Vbe is the transistor's emitter base voltage, Ic is the transistor collector current, Is is the collector saturation current, K is Boltzmann's constant, q is the charge of one electron and T is the absolute temperature in degrees Kelvin. As can be seen from the equation, the logarithmic function is BLOCK DIAGRAM ,- - -- -- - - - - - I - - - .... I I I I I Ex ,- - - - - - - - - I I I I '-- ,I - --- -- - - --- - "" I I I I -; Log amp -----------"I I I I Output I ,,----------; Antilog Amp .... - -- --- - - - - . Log amp Functional Diagram of Model 4204. 5-44 SPECIFICATIONS Typical performance at +2S o C with rated power supplies unless otherwise noted. Per cent specifications refer to %of full scale (1 OV). ELECTRICAL MODEL MECHANICAL 4204J ExEy OUTPUT FUNCTION 1il TOTAL ERROR** Internal trim t External trim~ typ vs. Temperature vs. Supply 0.5% max 0.2% O.OI%/oC 0,02%/% · · .. 0.25% max 0.1% IS mV 0.2% 0.005% 0.05% 10 mV pop 10 mV pop AC PERFORMANCE Slew Rate -3 dB Small Signal Bandwidth 1% Amplitude Error 1% Vector Error (O.S~ phase shift) Full Power Response I V/JlSec 250 kHz 33 kHz 2.5 kHz 20 kHz OUTPUT NOISE X =Y =O.OV DC to 10 kHz 300 ,"V rms INPUT CHARACTERISTICS Input Voltage Maximum for Rated Sp~cifications X,Y,Z MaXimum Safe Level X. Y ,Z Input Impedance XIV /Z · Rated Output Voltage. min Current, min Output Impedance :t10 V :tS mA In POWER SUPPLY REQUIREMENTS Rated Supply Operating Range Quiescent Current :tIS VDC :t14 to :t16 V +15 mA, -8.5 mA TEMPERATURE RANGE Specification Operating Storage 5 mV 0.1% 5 mV 0.1% · · · -25°C to +8S o C _55°C to +12SoC -65°C to +12SoC (.25") 2.5mm (.1") typo :j ~m~t: · · 5 mV pop 5 mV pop 5 mV pop 5 mVp-p ~ (.88") 0000000 7.6mm 7 8 1 14 (,30"' BOTTOM VIEW · · • · · · · 12.7mm (.50"' T PIN 1 IS IDENTIFIED BY A BLACK 'DOT ON THE TOP SURFACE Pin material and plating composition meet Method 2003 (solderability) of Mil-Std-S83 (except for paragraph 3.2.( PIN CONNECTIONS -55°C to +12SoC ·· ·Same as for 4204J. * * Total error is a tested maximum and does not represent a sum of the maximum individual errors as the maximum individual errors do not occur at the same X, Y operating point. t With output loading of 10 kn or less. I 2 3 4 5 6 7 8 9 10 11 12 13 14 Ez Output -Vs Feedthrough Adj. Make No Connection Make No Connection Ex Internal Reference Make No Connection Ground Feedthrough Adj. Offset Adj. Ey +Vs . 5-45 dia. ~~ 22.4mm Tr-ooo 0000 · · .46mm (.OlS"' (.6"' · :t10 V :tSupply 2Skn/2Skn/100kn OUTPUT CHARACTERISTICS ~~ -,-- O.2S%,max 0.1% 0.02%/oC,max INDIVIDUAL ERRORS Output Offset X=Y=O Scale Factor Error Non-Linearity X = 20 V,p-p Y=-IOVDC} Y = 20 V, pop X = -IOVDC X = 20 V, pop Y = +10 VDC} Y = 20 V, pop X = +10 VDC Feedthrough @ SO Hz X = 20 V, pop Y = 0 Y = 20 V, pop X = 0 , 4204S 4204K TYPICAL PERFORMANCE CURVES Typical Performance @25 0 C and ±15 VDC I .. .;, .... 0 ~ 20 1\ ~ Z .~ . 10 0 +10 .., 0 ...I>l +5 S -5 0 Ik JOk I>l >. ..'" I>l. .::; I:::> 0 ::> "::; < -10 lOOk 0 1M -60 el -90 < E: .. 0 gJ -30 Ol ,\ -ISO II< lOOk 10M FIGURE 3. Small Signal Frequency Response ~ 1000 ;; ! :I: 100 ~ ::> 0 ..: 0.1 ::; ..: < :1:. lOOk 1M FREQUENCY (Hz) .;, 1.0 ~0 , -\20 10k 10k . 10 Q 1\ Ik 400 200 FIGURE 2. Step Response 8..: 0 s: , II TIME <-c) z 1>0 -IS -20 -25 FIGURE 1. Large Signal Frequency Response . ~ -10 0 FREQUENCY (Hz) €: i"~ Q -5 ::> \ 1"'- ~ ::> i' '0 ~. Ol 15Q 10 -l- I>l I>l 1>0 0.01 1M 100 FREQUENCY (Hz) Ik 10k I lOOk FREQUENCY (Hz) FIGURE 4. Small Signal Fraquency Response FIGURE 5. Output Distortion vs. Fraquency 100 Ik 10k lOOk FREQUENCY (Hz) FIGURE 6. AC Feedthrough vs. Fraquency DISCUSSION OF PERFORMANCE CURVES LARGE SIGNAL FREQUENCY RESPONSE OUTPUT DISTORTION This response curve describes the output voltage capability of the 4204 as a function of frequency. The measurement is made with one input at + 10 or -10 VDC, and with sine wave applied at the other input. An output distortion of 0.5% is allowed. The output distortion of the 4204 is of most interest in modulator applications. The curve of Figure 5 characterizes this distortion with one input of the 4204 held at +IOor-1O VDC. A sine wave is applied to the other input. The sine wave amplitude is held constant at 20 volts pop while frequency is varied. a STEP RESPONSE Step response is measured with one input at + 10 or -I OVDC and with a 20 volt p.p square wave applied at the other input. SMALL SIGNAL FREQUENCY RESPONSE These curves are the amplitude and phase response of the 4204's transfer function, when one input isheldat+IOor -IOVDC.A sine wave signal is applied to the other input. Small signal response requires that the amplitude of the input sine wave be adjusted so that the outP~t signal does not reach the slew rate limitation. 5-46 AC FEEDTHROUGH The variation of feed through as a function of frequency is illustrated by Figure 6. One of the inputs is a zero while a 20 volt pop sine wave is applied at the other input. The output feedthrough generally has substantial harmonic content and is measured in millivolts, peak -to-peak. OPERATING MODES DIVIDE MODE MULTIPLY MODE SQUARE ROOT MODE r. Ez Fy ,... 014 IO- ~ " 0 0 0 0 08 0 0 0 0 n Bout :.n L~14 Bou I" Eout 014 ,... " 0 0 0 0 08 0 0 0 0 0 0 0 0 08 7 Ex Ez 7 Ex ,... ,... - _ ExFy Bout-lO lOEz Bout=~ V 10 Ez Eout = -lOV';;;; Ex';;;; -O.1V -10V';;;; Ez ';;;; +lOV OV;S>;Ez ';;;;+ 10V ADJUSTMENTS Although the 4204 will achieve specified performance in the multiply mode with no external trimming, optimized performance can be achieved with external adjustments. The proper connections and the trim procedures are explained below. Eout = ExEy 10· The 4204 will operate within specification with any combination of input signals. The best perfonnance,however, will be obtained in the 2nd, 3rd and 4th quadrants. That is if four quadrant operations are not needed, the performance of the 4204 can be optimized by constraining operation to quadrants 2, 3 and 4 rather than 1. Eout 20k IMll IMll MULTIPLICATION +IS -IS Ey~ MULTIPLICATION TRIM PROCEDURE (FIG_ 7) 20k 1) Set Ex = 0 and apply a 10 volt peak-peak sine wave (50 Hz) to Ey: Adjust R I for minimum output. 2) Set Ev = 0 and apply a 10 volt peak-to-peak sine wave (50 gz) to Ex: Adjust R2for minimum output. 3) Set Ex = By = 0: Adjust R3 for Eout = 0.000 V. 4) Set Ex = By = +10.000 V :tl rnV: Adjust R4 for Eout = +10.000 V:t2 mY. RI IM!1 ..-IS -IS o-w-o 20k R3 FIGURE 7. Multiplication Trim Procedure. 5-47 DIVISION 2) Set Ez = 0 volt, Ex "" -10 Y, adjust R2 such thitt Eo = 0.000 Y ±2 mY. .. 3) Set Ex = Ez = -1O.000VOC ±2 mY, adjust R3 such that . Eo =+ 1O.000VDC±2 mY. 4) Set Ex =Ez '" minimum value required by application, adjust RI such that Eo =+ 1O.000Voe ±5 mY. 5) Repeat steps (2) through (4) if necessary. The 4204 may' be used as atwo-quadrant divider\vithout the need for an external operational amplifier. It should, however, be noted. that the maximum output error is approximately given by divider error '" I Oem Ex where €m is the total error specification for the multiply mode. Obviously, divider error becomes excessively large for small values of Ex. A 10: 1 denominator range is usually the practical limit. If more accurate division is required over wide range of denominator voltages, the Burr-Brown model DIV 100 is recommended (0.25% max error over 40: 1 range). -IS +15 -IS QJwv-O ()-IH.-O RI> 20k R2. 20k DIVISION TRIM PROCEDURE (FIG. B) 1) Set all potentiometers @ about mid-scale. FIGURE 8.Division Trim Procedure. SQUARE ROOT SQUARE ROOT TRIM PROCEDURE (FIG. 9) I) Set Ez =+1O.000VDC ±2 mY, adjust R2 such that Eo = -1O.000YDC±2 mY. 2) Set Ez '" minimum value required by application (Ezm) adjust Rl such that Eo =-,.110 Ezm ±2 mY. 3) Repeat steps (I) and (2) if necessary. The pin connections for the Square Root mode of operation are similar to those for division, except that the denominator input is connected to the output node. Errors in the Square Root. mOeJe of operation beco~e troublesome for small values of Ez. However, the output error does not increase so rapidly as in the divide mode. The actual output for small values of Ez is given approximately by -:-;;;:;---:--:-:;-- Eout '" --V IOEz + 1Oem where € m is the total error specified for Multiply mode. This equation can be used to determine the feasibility of using the 4204 as a square rooter for a given application. For operation over a much wider dynamic range, with improved accuracy, the Model 4302 multifunction converter is recommended. FIGURE 9. Square Root Trim Procedure. 5-48 4206 BURR-BROWN@ 113131 ANALOG MULTIPLIER-DIVIDER FEATURES • HIGH TOTAL ACCURACY 0.25% and 0.5% max. no external trims 0.1 % and 0.2% typo with external trims • LOW TEMPERATURE DRIFT l00ppm/oC from DoC to +700C • SMALL PACKAGE Dual-in-line saves board space • LOW COST ~---...(,'2 International Airport Industrial Park - P.O_ Box 11400 - Tut:Son. Arizona 85734 - T81.(602I 746-1111 - Twx: 910-962-1111 - Cable: B8RCORP.- Telex: 66-6491 PDS-330B 5-49 DESCRIPTION The 4206 is a four-quadrant analog multiplier offering high accuracy, low noise; and moderate bandwidth at low cost. It uses the log/antilog technique and is internally laser-trimmed and multiply mode accuracies of 0.25% and 0.5% max, are guaranteed with no external components. By following the external trim procedure described in Multiplication section, accuracies can be improved to 0.1 % and 0.2% typo Accuracy specifications are verified at Burr-Brown by an automatic tester which scans the X-V plane. Maximum error at any points in the plane is required to be less than the specified values. The 4206 also performs the diVide function in two quadrants and'the square root function in one quadrant with no external components required. Detailed instructions for these operations are given on the last page. THEORY OF OPERATION The 4206's log-antilog multiplication technique is based upon the logarithmic voltage-current relationship in a semiconductor junction. This action is shown by the simplified equation: Vbe = (K~(ln Ic - in Ig) q . where Vbe is the transistor's emitter-base voltage, Ic is the transistor collector current, Is is the collector saturation current, K is Bolzmann's constan,t, q is the' charge of one electron and T is the absolute temperatuIe in degrees Kelvin. As can be seen from the equation, the logarithmic function is extremely temperature sensitive. The 4206, however, has excellimt temperature characteristics because the log and antilog circuitry haye equal and opposite temperature drifts which cancel to a first order approximation. The log and antilog circuits will compensate each other to the extent that the vilfious logging transistors are matched to each other. In the 4206 these transistors are placed adjacently on a monolithic chip to obtain the best possible matching lIJ\d so the best possible performance. 4}-----~-----------------------, r----------(12 +!5V 11~-----------------------J SPECIFICATIONS Typical performance at +2S o C with rated power supplies unless otherwise noted. Per cent specifications refer to % of full scale (1 OV). ELECTRICAL 4206J MODEL OUTPUT FUNCTION TOTAL ERROR(Multiply Mode)" Internal trim, max t Ex ternal trim, typ vs. Temperature vs. Supply INDIVIDUAL ERRORS (Multiply Mode) Output Offset X=Y=O Scale Factor Error Non-Linearity X = 20 V, p.p Y = -10 VD~} Y = 20 V, pop X = -IOVDC X = 20 V, pop Y = +10 VDC} Y = 20 V, pop X = +10 VDC Feedlhrough @ 50 Hz X = 20 V, pop Y = 0 Y , 20 V, pop X = 0 AC PERFORMANCE Slew Rate -3 dB Small Signal Bandwidth' 1% Amplitude Error 1% Vector Error (0.570 phase shift) Full Power Re~Q!Jnse OUTPUT NOISE DC to 10 kHz OUTPUT CHARACTERISTICS Rated Output Voltage, min Current, min Output Impedance POWER SUPPL V REQUIREMENTS Rated Supply Operating Range IOuiescent Current TEMPERATURE RANGE Specification Operating Storage . .. Leads in true position within 01O"(.25mm) R at MMC at seating 0.25% max 0.1% 0.5% max 0.2% O.OI%/oC 0.02%1% 15 mV 0.2% 5 mV 0.1% · · 0.005% 0.05% Pin numbers shown for reference only. Numbers are not marked on package. 5 mV pop 5 mV pop 10 mV pop 10 mV pop , INCHES MAX MIN DIM I Vlp.sec 250 kHz 33 kHz 2.5 kHz 20 kHz A ·, X = V = O_OV INPUT CHARACTERISTICS Input Voltage Maximum for Rated Specifications X. Y ,Z Maximum Safe Level X, Y, Z [npul Impedance X/Y IZ NOTE: 4206K EXEy 10 300 p.V rms ±.IO V ±.Supply 25kn/25k n /l00kn , MILLIMETERS MIN MAX .810 20.07 .510 .490 .190 .260 .018 .021 .100 BASIC .115 .080 .130 .300 12.45 4.83 .790 .3008ASIC .080 .115 20.57 12.95 6.60 0.53 2.54 BASIC 2.03 2.92 3.30 7.62 0." 7.628ASIC 2.03 2.92 PIN SPACING: 2.5mm(0.1") ROW SPACING: 7.6mm (0.3001 WEIGHT: 3.4 grams (0.12 oz.) CONNECTOR: l4-pin DIP 0145MC ±,S rnA Pin material and piatingcompositionconform to Method 208 (solderability) of Mil- In Std-202. ±.IO V' ±.15 VDC ±14to±.16V +15 rnA, -8.5 rnA OOC to +700 C -25°C to +85 0 C -55°C to + [25°C · · • Same as for 4206J •• Total error is a tested maximum and does not represent a sum of the maximum individual errors as the maximum individual errors dq, not occur at the same X, Y operating point. t With output loading of 10kn ~r less. PIN CONNECTIONS 2 3 4 6 7 S 9 10 II 12 13 14 5-51 Ez Output -Vs Feedthrough Adj. Make No Connection Make No Connection Ex Internal Reference Make No Connection Ground Feedthrough Adj_ Offset Adj. Ey +Vs TYPICAL PERFORMANCE CURVES Typical Performance @250C and ±15 VDC Q: c.. :? "S ~ ~ ...0 "Z~ \ 10 '"f- .. ::> f- ::> 0 ... > ... 20 ~ 0 Ik 10k +10 = S +5 <>l <>l <>l \ .. -5 f- -10 ::> 0 ~ lOOk :> . f- ::> :i ::i! -< ~OO 200 0 -30 5:! -60 '" '"-l . t l: f- I' Ik 10k lOOk 100 l: 1M FREQUENCY (Hz) FIGURE 4. Small Signal Frequency Response 10 ~I- e<>l -120 -ISO I""" "::>~ , 10M 1000 .,; ~ -90 lOOk 1M FREQUENCY (Hz) FIG URE 3. Small Signal Frequency Response ...c.. J 1\ ~ 10k FIGURE 2. Step Response '<." to. , -IS -20 TIME (_c) FIGURE 1. Large Signal Frequency Response f- ~ -10 -25 o 1M FREQUENCY (Hz) ~ r--.", -5 Q 0 f- 0 <>l to. I 100 Ik 10k lOOk FREQUENCY (Hz) FIG URE 5. Output Distortion vs. Frequency 100 Ik 10k lOOk FREQUENCY (Hz) FIGURE 6. AC Feedthrough vs. Frequency DISCUSSION OF PERFORMANCE CURVES LARGE SIGNAL FREQUENCY RESPONSE OUTPUT DISTORTION This re~onse curve describes the output voltage capability of the 4206 as a function of frequency. The measurement is made with one input at + 10 or -10 VDC, and with a sine wave applied at the other input. An output distortion of 0.5% is allowed. The output distortion of the 4206 is of most interest in modulator applications. The curve of Figure 5 characterizes this distortion with one input of the 4206 held at + I 0 or -10 VDC. A sine wave is applied to the other input. The sine wave amplitude is held constant at 20 volts p.p while frequency is varied. STEP RESPONSE Step response is measured with one input at + 10 or -I OVDC and with a 20 volt p.p square wave applied at the other input. SMALL SIGNAL FREQUENCY RESPONSE These curves are the amplitude and phase response of the 4206's transfer function, when one input is held at +IOor -IOVDC. A sine wave signal is applied to the other input. Small signal response requires that the amplitude of the input sine wave be adjusted so that the output signal does not reach the slew rate limitation. ACFEEDTHROUGH The variation of feed through as a function of frequency is illustrated by Figure 6. One of the inputs is a zero while a 20 volt p.p sine wave is applied at the other input. The output feedthrough generally has substantial harmonic content and is measured in millivolts, peak·to·peak. 5-52 OPERATING MODES DIVIDE MODE MULTIPLY MODE SQUARE ROOT MODE ,.. - Ez Ez Fy 014 lO- ~ ~ 0 0 0 0 08 II Eout 014 ,.. '-- 0 0 0 0 ,.... ...., Eout 014 ~ 0 0 0 0 08 7" Ex ro0 Eou 1 0 0 0 0 08 0 0 0 7.., 7 Ex ,... IOEz Eout=~ -IOV';;; Ex';;; -O.IV -IOV';;; E z ';;; +lOV OV';;;Ez ';;;+ IOV ADJUSTMENTS Although the 4206 will achieve specified performance in the mUltiply mode with no external trimming, optimized performance can be achieved with external adjustments. The proper connections and the trim procedures are explained below. The 4206 will operate within specification with any combination of input signals. The best performance,however, will be obtained in the 2nd, 3rd and 4th quadrants. That is if four quadrant operations are not needed, the performance of the 4206 can be optimized by constraining operation to quadrants 2, 3 and 4 rather than I. E out 2.)--r----( 20k 1M!! 1M!! MULTIPLICATION +15 -IS Ey~ MULTIPLICATION TRIM PROCEDURE (FIG. 7) 20k 1) Set Ex = 0 and apply a 10 volt peak-peak sine wave (50 Hz) to Ey: Adjust RI for minimum output. 2) Set By = 0 and apply a 10 volt peak-to-peak sine wave (50 liz) to Ex: Adjust R2for minimum output. 3) Set Ex = Fy = 0: Adjust R3 for Eout = 0.000 V. 4) Set Ex = Fy = +10.000 V ±.I mY: Adjust R4 for Eout = +10.000 V ±.2 mY. R\ 1M!! +15 -IS ~ 20k R3 FIGURE 7 Multiplication Trim Procedure 5-53 2) Set Ez = 0 volt, Ex "" ":10 v, adjust R2 such that Eo = 0.000 V ±2 mV. 3) Set Ex = Ez = -IO.OOOVDC ±2 mY, adjust R3 such that Eo = +10.000VDC±2rilV .. 4) Set Ex = Ez '" minimum value required by application, adjust RI such that Eo =+10.000VDC±5 mY. 5) Repeat steps (2) through (4) if necessary. DIVISION The 4206 may be used as a two-quadrant divider without the need for an external, operational amplifier. It should, however, be noted that the maximum output error is approximately given by divider error "" I Oem Ex where Em is the total error specification for the multiply mode. Obviously, divider error becomes excessively large for small values of Ex., A 10: I denominator range is usually the practical limit. If accurate division is required over a wide dynamic range of denominator voltage, the Burr-Brown model DIVlOO is recommended (0.25%, max., over a 40: I range). DIVISION TRIM PROCEDURE (FIG. 8) FIGURE 8 Division Trim Procedure I) Set all potentiometers near mid·scale. SQUARE ROOT TRIM PROCEDURE (FIG. 9) I) Set Ez = + 1O.000VDC ±2 mV, adjust R2 such that Eo = +1O.000VDC±2mV. 2) Set Ez "" minimum value required by application (Ezm) adjust RI such that Eo = -'1110 Ezm ±2 rnV. 3) Repeat steps (I) and (2) if necessary. SQUARE ROOT The pin connections for the Square Root mode of operation are similar to those for division, except that the denominator input is connected to the output node. Errors in the Square Root mode of operation becoJ:lle troublesome for small values of Ez. However, the output error does not increase so rapidly as in the divide mode. The actual output for small values of Ez is given approxima tely by -:-:-c::--:-:-- Eout "" --../ 10Ez + I Oem where em is the total error specified for Multiply mode. This equation can be used to determine the feasibility of using the 4206 as a square rooter for a given application. For operation over a much wider dynamic range, with improved accuracy, the Model 4302 multifunction converter is recommended. FIGURE 9 Square Root Trim Procedure 5-54 BURR-BROWN® 4213 IElElI MULTIPLIER-DIVIDER FEATURES APPLICATIONS • LOW COST • MULTIPLICATION • DIFFERENTIAL INPUT • DIVISION • ACCURACY 100% TESTED AND GUARANTEED • SQUARING • LOW NDISE 120/LV. rms. 10Hz to 10kHz • SQUARE ROOT • SELF-CONTAINED No additional amplifiers • POWER COMPUTATION • LINEARIZATION • ANALOG SIGNAL PROCESSING • SMALL SIZE Hermetic TO-l00 package • ALGEBRAIC COMPUTATION • TRUE RMS-TO-OC CONVERSION • WIOE TEMPERATURE OPERATION DESCRIPTION The 4213 multiplier-divider is a low cost precision device designed for general purpose application. In addition to four-quadrant multiplication, it also performs analog square root and division without the bother of external amplifiers. The 4213 is lasertrimmed to guarantee its rated accuracy with no external components. The internal zener regulated references make the 4213 much less sensitive to supply variation than earlier Ie multipliers. Hermetic TO-100 package, wide operating temperature range, low output noise, and low cost are some of the desirable features of this versatile device. 4213 FUNCTIONAL DIAGRAM Muillpller Cora OUT Attan"alor Inlernational Alrporllndualrial Parle· P.O. Box 11400 • Tucson. Arizona 85734 • Tel. 1602l 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP • Telex: 66·6491 PDS·3MD 5-55 SPECIFICATIONS ELECTRICAL - Specifications at TA = +25°C and+Vcc= 15VOC unless otherwise noted CONDITIONS PARAMETER M LTIPLIER PERFORMANI E Transfer Function Total Error Initial vs Temperature YS Temperature vs Supply Individual Errors Output Offset Initial vs Temperature va Temperature vs Supply Scale Factor Error Initial vs Temperature '.IS Temperature vs Supply{ Nonlinearity X Input Y Input Feedthrough X Input Y Input vs Temperature '.IS Temperature vs Supply I 4213AM MODEL MIN TYP MAX ±1.0 ±O.02 ±0.OO8 -- TYP MAX .I 4213sM .. MIN TYP I MAX UNITS ±O.5 % FSR % FSRI"C % FSR/oC % FSRI% · IX, - x.;~Y' - Y21 + Z2 y" -10V "X. 10V TA = +25°C -25°C" T A " +85°C -55°C" TA" +125°C I 4213BM MIN ±O.5 -- -- -- ±50 ±2.0 ±7 ±0.3 ±25 ±0.7 ±O.025 -- ±O.OS ±0.05 TA = +25°C -25°C" TA " +85°C -55°C" TA " +125°C ±10 ±0.7 -- -±O.25 TA = +25°C -25°C" T A " +85°C .. ±0.12 ±0.OO8 X = 20V. pop; Y = ±10VDC Y = 2OV. pop; X = ±10VDC 1 = SOHz X = 20V. pop; Y = 0 Y = 20V. pop; X = 0 -25°C" TA " +85°C -55°C" TA" +125°C ±25 ±O.7 - X, %FSR % FSR · -- -- > X2 mV mVioC mVloC mVI% ±O.OB ±O.o1 30 6 0.1 101Z,-Z21 X=-10V -10V" Z ,,+10V X=-W -W" Z" +1V -10V" X" -0.2V -10V "'Z,, +10V -- ±O.OS ,+ Y (Xl - X21 -±O.OO8 -0.1 2 mV. pop mV. pop mV. pop/DC mV. pop/DC mV. p-P/% · ±0.75 ±0.35 ±0.35 % FSR ±2.0 ±1.0 ±1.0 % FSR ±5.0 ±1.0 ±1.0 % FSR I ±0.3 ±O.3 %FSR +v'10,Z2 - Z', ±1 ±O.5 ±0.5 % FSR SQUARER PERFORMANCE Transfer Function Total Error ±7 ±O.3 0.15 DIVIDER PERFORMANCE Transfer Function Total Error (with external adjustments I -- % FSR % FSR/oC % FSR/oC % FSRI% -- -- -55°C E;;; TA:S;;; +125°C -- IX, ~OX212+ Z2 I -10V" X " +10V ±0.6 SQUARE-ROOTER PERFORMANCE Transfer Function Total Error Z, < Z2 W" Z" 10V I I AC PERFORMANCE Small-Signal Bandwidth 1% Amplitude Error 1% [0.57°1 Vector Error Full Power Bandwidth Slew Rate Settling Time Overload Recovery INPUT CHARACTERISTICS Input Voltage Range Rated Operation Absolute Maximum Input Resistance Input Bias Current OUTPUT CHARACTERISTICS Rated 0 utput Voltage Current Output Resistance kHz kHz kHz kHz 5SO 70 5 320 20 2 0.2 ±3dB Small· Signal Small Signal IV~ = 10V, RL = 2kll IV~ = 10V. RL = 2kll , = ±1%. ':;'Vo = 20V 50% Output Overload V/~sec ~sec ~sec ±10 V ±Vcc X, Y. Z(1) X. y. Z 10 = ±SmA Vo = ±10V 1= DC X-y-O OUTPUT NOISE VOLTAGE 10 -1Hz 10 = 10kHz 1/f C':'rner Frequency IB = 10Hz to 10kHz IB = 10Hz 10 10MHz POWER SUPPLY REQUIREMENTS Rated Voltage Derated Performance Operating Range Quiescent Current 10 1.4 V Mil ~A ±10 ±5 V mA 1.5 n 40 1.0 1060 125 ~~;~ Hz ~V, rms mV, rms 3 ±15 ±8.5 ±20 ±5.5 5-56 VDC VDC mA ELECTRICAL (CONT) I MOOEL PARAMETER TEMPERATURE RANGE IAmbient, Specification Operating Range Storage I CONDITIONS I Derated Performance I 4213AM MIN I TVP 4213BM I I I I -25 -55 -65 MAX +85 +125 +150 I I MIN I TVP I 4213SM I I I MAX I I MIN I -5:5 I I TVP I MAX I +1;5 I UNITS DC DC DC NOTES: 1. Z:z input resistance is 10MCl. typical, with Pin 9 open. If Pin 9 is grounded or used for optional offset adjustment, the Z2 input resistance may be as low as 25kU. ·Same as 4213AM specification. The information in this p~blication has been carefully checked and is believed to be reliable; however, no responsibility is assumed for possible inaccuracies or omissions. Prices and specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. CONNECTION DIAGRAM MECHANICAL ·Optlonal component NOTE: Leads in true position witl-lin .010" 1.2SmmJ R @ MMC at ...ting plane. -15VOC PIN CONFIGURATION Y2 I ORDER NUMBER: 4213AM 4213BM 4213SM WEIGHT: 1 gram NOTES: 1. Vas adjustment optional not normally recommended. Vas pin may be left open or grounded. 2. All unused input pins should be grounded. 3. Pin 5 is connected to the case. SfMPLIFIED SCHEMATIC INf:HES DIM MIN MAX MILLIMETERS MIN MAX A .335 .370 8.51 9.40 B .305 .335 7.75 8.51 C .165 .185 4.19 4.70 0 .016 .021 0.41 0.53 E .010 .040 0.25 1.02 F .010 .040 0.25 1.02 G .230 BASIC 5.84 BASIC H .028 .034 0.71 J .029 .045 0.74 K .500 -- 12.70 -- L .120 .160 3.05 4.06 M 36° BASIC .110 I .120 N 0.86 1.14 36° BASIC 2.79 3.05 TYPICAL PERFORMANCE CURVES TOTAL ERROR VS AMBIENT TEMPERATURE a: (/) ~ 10 NONLINEARITY VS FREQUENCY 100 ~ Inplut ffi e w :; 0; O. 1 0> ro -75-50-250 255075100125 Ambient Temperature lOCI 0.00 1 10 OUTPUT AMPLITUDE VS FREQUENCY ./ 500 200H-+-f--f-+-Jo'l--I " ~ 100 ">g> 50 .r:: 10 .r:: 'v / 1 "",0.05 ·c ::; X7 ~ 1 ./ ~ 0.2 "- b.. :> § /' / '0 if. / 8 0.5 ~ "- / "- Sig~al ~ "dv. p-p 10 FEEDTHROUGH VS FREQUENCY 1000...,.-.,.......,r--'"I"'-""""T""'" 20 e ~ " "- 100 1k 10k 100k Frequency I Hz I 10 1M III -5 ~ -10 :; S. " 6 -15 \ 1M 100k Frequency IHzl 70 '-' VcRL~2k!l I----- \ 10 ~ 8 f 1\ 50P CT -10 Y~±10VDC 40 20 10 100 '" ~ 1-"1"" " , "V v,. .' " ~ 1.0 2.0 3.0 Time ij.tsec, 4.0 2 4 6 8 10 12 14 16 18 20 power Supply Voltage I±VCC 5.0 SUPPLY CURRENT VS AMBIENT TEMPERATURE 16 14 ~ 12 i\\ C 10 5mA Load r- ~ - ". ~ \ 30 );1 ~ 12 i2 12V.p-p _\ X ~ ±10VDC - X ~ 12V. p-p ~ 50 o \ .~ Y L1 II a: ::; 10M "- '5 -5 Positive Common-mode DifferentIal Negative Common-mode > 14 COMMON-MODE REJECTION VS FREQUENCY 60 ro ":; r- f'" 6e-=' F 1\ I > Y~' -20 80 / " ~ ~x 18 ".. > 10k 100k 1M 10M INPUT VOLTAGE FOR LINEAR RESPONSE 0 " :e"Q." 1k Frequency I Hz I LARGE SIGNAL RESPONSE 10 100 '-'>, Quiescent Q. !} \ 1k 10k 1OOk 1M 10 M Frequency 1Hz) (/) 16 Output Current l±mAI o -100-75-50-250 2650.75100125150 Ambient Temperature ,oC I ABSOLUTE MAXIMUM RATINGS Supply Internal Power Dlssipation(1) Differential Input. Voltage(2) Input Voltage Range(2) Storage Temperature Range Operating Temperature Range Lead Temperature (soldering, 10 seconds) Output Short-circuit Duration(3) Junction Temperature ±20VDC 500mW ±40VDC ±20VDC -65°C to +150°C -55°C to +125°C +300°C Continuous +150°C NOTES: 1. Package must be derated based on: 8JC = 55°CIW and (jJA "'" 165°C/W. 2. For supply voltages less than ±20VDC the absolute maximum input voltage is equal to the supply voltage. 3. Short-circuit mtiy be to ground only. Rating applies to +85°C ambient. 5-58 DEFINITIONS TOTAL ERROR (Accuracy) Total error is the actual departure of the multiplier output voltage from the ideal product of its input voltages. It includes the sum of the effects of input and output DC offsets, gain error and nonlinearity. OUTPUT OFFSET Output offset is the output voltage when both inputs Vx and Yyare zero volts. SCALE FACTOR ERROR Scale factor error is the difference between the actual scale factor and the ideal scale factor. NONLINEARITY Nonlinearity is the maximum deviation from a best straightline (curve fitting on input-output graph) expressed as a percent of peak-to-peak full scale output. FEEDTHROUGH Feedthrough is the signal at the output for any value of Vx or Vy within the rated range, when the other input is zero. SMALL SIGNAL BANDWIDTH Small signal bandwidth is the frequency at which the output is down 3dB from its low frequency value for a nominal output amplitude of 10% of full scale. 1% AMPLITUDE ERROR The I % amplitude error is the frequency the output amplitude is in error by I %, measured with an output amplitude of 10% of full scale. 1% VECTOR ERROR The I % vector error is the frequency at which a phase error of O.oJ radians (0.57") occurs. This is the most sensitive measure of dynamic error of a multiplier. APPLICATIONS INFORMATION MULTIPLICATION Figure I shows the basic connection for four-quadrant mUltiplication. terminal, as well as the X and Y input terminals, should be grounded. All inputs should be referenced to power supply common. The 4213 meets all of its specifications without trimming. Accuracy can, however, be improved by nulling the output offset voltage using the IOOkfl optional balance potentiometer shown in Figure I. Figure 3 shows how to achieve a scale factor larger than the nominal 0.1. I n this case, the scale factor is unity which makes the transfer function V., = KV"V, = K(XI - X,)(Y 1 - V,) K = [I + (R 1/ R,)]i 10 AC feed through may be reduced to a minimum by applying an external voltage to the X or Y input as shown in Figure 2. O.I:S;; K:S;; I Z" the optional summing input, may be used to sum a voltage into the output of the 4213. If not used, this Vo= lDkll (Xl- X211Yl - Y21 10 +Z2 4213 Va. ±lDV. FS 4213 ·15vnc +15Vu~ FIGURE 3. Connection For Unity Scale Factor. l00kll -15VDC +15VOC "Optional nulling potentiometer. FIGURE I. Multiplier Connection. ~Il___1""'''' !~:'rilte 5I1kllI··+_15_vn_c_ _ ... lk'l Input Terminal ·15VnC This circuit has the disadvantage of increasing the output offset voltage by a factor of 10 which may require the use of the optional balance control for some applications. In addition, this connection reduces the small signal bandwidth to about 50kHz. DIVISION Figure 4 shows the basic connection for two-quadrant division. This configuration is a multiplier-inverted analog divider, i.e., a mUltiplier connectea In the feedback loop of an operational amplifier. In the case of the 4213 this operational amplifier is the output amplifier of the mUltiplier itself. FIGURE 2. Optional Triinming Configuration. 5-59 Vx Denominator .10V<;;IXl- X2I .;-o.2V +15VQC '~I""-~e-. :-I" " "'r- +-' -----'" ·15VQC 'Opllonal Nulling '-_-"-___-=-==-"". . . . . . . -' ComponenlS +15VOC HJ, FIGURE 4. Divider Connection. lDDkIlI r-:-:~-=e!,L-+-..I The divider error with a multiplier-inverted analog divider is approximately Ed"';d" = 10 Emult;p';,,/ (X, - X,). ·15VQC "W' .15VDC +15VDC 'Qpllonl1 Nulling CamponenlS It is obvious from this error equation that divider error becomes excessively large for small values of X, - X,. A IO-to-I denominator range is usually the'practicallimit. If more accurate division is required over a wide range of denominator voltages, an externally generated voltage may be applied to the unused X-input (see Optiomil Trim Configuration). To trim, apply a ramp of +100mY to +1 Y at 100Hz to both X, and Z, if X, is used for offset adjustment, otherwise reverse the signal polarity, and adjust the trim voltage to minimize the variation in the output. An alternative to this procedure would be to use the Burr-Brown DIY 100, a precision log-antilog divider. FIGURE 6. Square Root Connection. This will improve the square root mode accuracy to about that of the multiply mode. BRIDGE LINEARIZATION SQUARING VII' ±IQV. FS Vx ±lQV. FS 'Qptlonal Nulling Component -15VOC Qptional 'Summing Input. ±IQV. FS FIGURE 5. Squarer Connection. SQUARE ROOT Figure 6 shows the connection for taking the square root of the voltage Yz. The diode prevents a latching condition which could occur if the input momentarily changed polarity. This latching condition is not a design flaw in the 4213, but occurs when a multiplier is connected in the feedback loop of an operational amplifier to perform square root functions. FIGURE 7. Bridge Linearization. The use of the 4213 and the instrumentallon amplifier to linearize the output from a bridge circuit makes the output Yo independent of the bridge supply voltage. TRUE RMS-TO-DC CONVERSION 2Qkll The load resistance RI. must be in the range of IOkH':;; RI. I Mn. This resistance must be in the circuit as it provides the current necessary to ,operate the diode. The output offset should be nulled for optimum performance by allowing the input to be its smallest expected value and adjusting R, for the proper output Voltage. ~ Mllched to 0.025% HI H2 Mode Switch FIGURE 8. True RMS-to-DC Conversion. 5-60 The RMS-to-DC conversion circuit of Figure 8 gives greater accuracy and bandwidth but with less dynamic range than most rms-to-DC converters. PERCENTAGE COMPUTATION 1V2-Vl1 Vo = -V-l- 100 1'10 porvoll WIRING PRECAUTIONS In order to prevent frequency instability due to lead inductance of the power supply lines, each power supply should be bypassed. This should bedone byconnecting.a IOJlF tantalum capacitor in parallel with a 1000pF ceramic capacitor from the +Vce and -Vee pins of the 4213 to the power supply common. The connection of these capacitors should be as close to the 4213 as practical. 4213 CAPACITIVE LOADS Stable operation is maintained with capacitive loads to 1000pF in all modes typically, except the square root mode for which SOpF is a safe upper limit. Higher capacitive loads can be driven if a lOon resistor is connected in series with the 4213's output. 9kn lkn FIGURE 9. Percentage Computation. The circuit of Figure 9 has a sensitivity of I V/ % and is capable of measuring 10% deviations. Wider deviation can be measured by decreasing the ratio of R,/ R,. SINE FUNCTION GENERATOR 71.548kn 5.715kn 10kn f-lOV.; VI'; +IOV. and IV =11"1 FIGURE 10. Sine Function Generator. The circuit in Figure 10 uses implicit feedback to implement the following sine function approximation: Vo = (1.571SV, - 0.004317V,))/(1 + 0.OOI398V,') = 10 sin (9V,). SINGLE-PHASE POWER MEASUREMENT FIGURE II. Single-Phase Instantaneous and Real Power Measurement. 5-61 MORE CIRCUITS The theory and procedures for developing virtually any function generator or linearization circuit can be found in the Burr-Brown; McGraw Hill book "FUNCTION CIRCUITS - Design and Applications." 421,4, BURR- BROWN® IElE:lI MULTIPLIER - DIVIDER FEATURES APPLICATIONS • DIFFERENTIAL INPUTS • ,MULTIPLICATION • LASER-TRIMMED • DIVISION • GUARANTEED ACCURACY 0.5% and 1% • SQUARING • SQUARE ROOTING • ADAPTIVE CONTROL • SELF-CONTAINED No additional parts required • ALGEBRAIC COMPUTATION • LOW NOISE 120jlV rms. 10Hz - 10kHz • POWER COMPUTATION • DIP PACKAGES DESCRIPTION The 4214 family of multipliers are low cost integrated circuit multiplier/dividers designed for general purpose usage. In addition to four quadrant multiplication, they also perform division and square rooting of analog signals. They do not require use of additional amplifiers to perform these functions. The 4214 is laser-trimmed prior to final packaging and is guaranteed to its rated accuracy with no external components - a distinct advantage from standpoints of cost and reliability. 4214 contains its own zener regulated references and, as a result is much less sensitive to supply voltage variation than were earlier Ie multipliers. The iii a 10Hz mUltipliers' output n.6ise is only 1201LV to 10kHz bandwidth. nns The unit is available in two 14 pinDIP packages. The plastic version ("P" package) is offered for minimum cost and is specified over the -2Soe to +8Soe range. The hermetic metal package ("M" package option) provides operation over the full -ssoe to +l2Soe temperature range. ' Inllrnatlonll Airport Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel.l602J 746·1\1\· Twx: 910-952·1\1\"· Cable: BBRCORP· Telex: 66-6491 PDS-395 5-62 ELECTRICAL SPECIFICATIONS Typical performance at +2SoC with rated power supplies unless otherwise noted. MODEL 4214AP/RM' OUTPUT FUNCTION TOTAL ERROR(I) Without Trimming Error VI Temperature (-2S"C to +85"C). (AP and BP) (-SS"C to +12S"C). (RM and SM) Error VI 4214BP/SM (X,-X,)(y,- V,) 10 Supply MECHANICAL 4214AP.4214BP Weight: 2.9 grams (0.10 oz.) +z, 1% max 0.5% max 0.OO8%!"C typ., 0.02%!"C max O,02S%!"C typ., O.OS%i"C max 12 7mm j(o.so") VI 7mV typ SOmv max 2SmV max 0.7mV/"C typ 0.3mV(C typ 2mVrC max O.7mV/"C max 0.2SmV/% 0.12% O.OO8%/'C ~os~~~-jl- IOmV typ Temperature Supply Scale Factor Error VI Temperature VI Supply Nonlinearity XiX = 20V p-P. Y = ±IOVDC) Y(Y = 20V P-P. X = ±IOVDC) Feedthroush adO Hz X=20Vp-p. Y=O Y=20Vp-p.X=O VI Temperature VI Supply VI Pin 1 O.OS%/% 4214RM,4214SM Weight: 3.9 grams (0.13 oz.) ±O.08% ±O.OI% 30mV p-p 6mV p-p O.lmV p-p/"C O.ISmV p-p/% AC PERFORMANCE 6.4mm (0.2S") OUTPUT NOISE IX =Y =0) 5SOkHz 70kHz 5kHz 320kHz 2OV/lls -:::-~ INPUT CHARACTERISTICS Input Voltage Range Rated Operation. min. Absolute max Input Impedance, X. Y, ZI2l Input Bias Current. X. Y. Z S.3mm 22.0mm ~ (0.87")' ~"-~"ll-L.... .", (O.SO") N n nn 'I O.46mm_lI_ (0.018") 2.Smm 7.6mm (0.30") 2/115 120"V rms 700.... V rms 10 Hz to 10 kHz (0 Hz to 10,MHz Ir -. I T Small Sipl ±3dB Flatness Small S;,nal ;1:1% Flatness Small Sipl ±I% Vector Error (0.57' Phase Shift) Full Power Bandwidth Slew Rate Settling Time to 1% (20V step) 1-.£ ~T O.OS%/% INDIVIDUAL ERRORS Output Offset S.7mm (0.22S") Connector: 014SMC (l4-pin DIP) Pin material and plating composition conform to method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2) ±IOV ±VI IOMO 1.4IlA OUTPUT CHARACTERISTICS Rated Output Output Impedance CONNECTION DIAGRAM ±IOV at ±SmA min I.SO POWER SUPPLY REQUIREMENTS ±15V ±8.5VDC to ±20VDC ±S.SmA Rated Voltage Operating Range Quiescent Current TEMPERATURE RANGE Rated Performance (specification) Operation Storage AP and BP RM and SM -2S"C 10 +85"C -SS'C to +12S"C -SS"C to +12S"C -6S"C to +I SO"C No internal connections on Pins 4. S. 6 and 8. I. Total error is the maximum allowed value of the sum of the individual errors. 2. Z2 input impedance is 10 MO typ with Pin II open circuit. If Pm II is grounded or used for optional offset adjustment the Z2 input impedance may become as low as 2Skn 5-63 NOTE: Vas adjustment optional. not normally recommended. Pin I I may he left open or srounded, TYPICAL PERFORMANCE CURVES I"'- Y - 70 12V· P-P. \X=±IOVDC'- ~ 11 60 ;0 '"~ ~ , 40 \ 30 20 , , ~ ~ ~ X = 12V P-P. o Y = ±IOVDC 10 " 1: , ~ 0 e- -5 > ;; " 0 0 .f -5 Q. F\ cf=IST e <: -10 r-- ;; Q. ;; -IS 0 -10 10 100 Ik 10k lOOk 1M Common-mode input Frequency (Hz) HGURE 1. Common-mode Rejection VS. R =2k ;0 :;:, \ I I I . '" 1\ o 1.0 I I 2.0 3.0 4.0 Time (I's) FlGURE 2. Step Response. -20 5.0 Frequency. ~ :l, = ~ 16 14 ~ ·i 12 10 .5 "2 o ;; Q. .s ~ Inp~t SigJal=20tp-P 18 10 / I V ./ 0.0 1 > ,S 200 :l, !! \00 '0 > SO '". "e ; / Z 4 \000 Q. b. 500 X/I V o. 1 1M \OM Frequency (Hz) FIGURE 3. Small-signal Frequency Response. lOOk '" .;; Inp1ut Si!nal=~ovJ-P_ ~ II I X-FeedtJrougl 20 \0 Y_Fe!dthrLgh j ~ ., 1/ '/ II £ I)K I OK 1 100 I Frequency (Hz) Fl G U RE S. Nonlinearity vs. Frequency. 10 100 Ik 10k lOOk I M 10M Input Frequency (Hz) FlGURE 6. Feedthrough vs. Frequency. 10 FIGURE 4. Input Range for Linear Response. -+2S 0 C '0 -- -55 C !'0 > ;; Q. ;; 5mA Load II "" ...... o '"~ .."e ....,- V V 8' Quiescent- 1 2 5 til 4 6 8 10 12 14 16 Output Current (rnA) FlGURE 7. Max. Output Voltage v•. -75-50-25 0 2550751001 5 Ambient Temperature (oC) FlGU RE 8. Total Error vs. Ambient Output Current. Temperature. 2 0 75 SO 2S 0 25 SO 75100125 Ambient Temperature ("C) FlGURE 9. Supply Current vs. Ambient Temperature. OPERATING MODES MULTIPLICATION The 4214 is a general purpose multiplier/divider with three sets of differential inputs viz. x, Y, and Z. Its openloop transfer function is 14)-_.,.-_--t:-----", +V. 1 r(XI - X2)(Y 1- Y2) eo=At 10 -(ZI-Z2~ where, A is the open-loop gain of the internal output amplifier (see the simplified equivalent circuit, Figure 10). Due to very high gain (A - 00) of the output amplifier the feedback from the output to any of the inputs will establish the relationship ZI - Z2 = (Xl - Xl) (YI - Y2)/ 10 Taking output at Zl the multiplication mode transfer function is obtained 'and is expressed as (XI- X2)(YI- Y2) eo = 10 +Z2' This connection of 4214 is shown on the previous page. TRANSCONDUCTANCE CIRCUIT FIGURE 10. Simplified Equivalent Circuit. 5-64 DIVISION The4214may be used as a two quadrant divider, without the need for an external op amp. Note that the maximum output error in the divide mode is given approximately by, 10Em Divider error "" - - - , where Em is XI- X2 the total error specified for the multiply mode. The divider error, as shown above, becomes excessively large for small values of (X, - X 2). A 10: I denominator range is usually the practical limit. This is true for all such units, where a multiplier is used in voltage feedback mode to generate "divide function. If more accurate division is required over wide range of denominator voltages, the Burr-Brown model DIV 100 is recommended (0.25% max error over 40: I range). ,oo;r-r--ti~W M For optimum performance, the Z offset should be nulled by letting the input be zero and adjusting R, for zero output. This offset adjustment will improve the divider -ISV FIGURE 12. Square Root Mode Connections - 4214. error to about 3 Em for (X, - X2) much less than 10V. (XI - X2) SINE FUNCTION GENERATOR Two 4214's can be connected with implicit feedback as shown in Figure 13 to implement the following sine function approximation. FIGURE 11. Divide Mode Connections - 4214. = 1.5715 ei - 0.004317 ei 3 =10 Sin 9 ei 1+ 0.001398 e? The theory and procedures for developing virtually any function generator or linearization circuit can be found in the new Burr-Brown/McGraw Hill book "FUNCTION CIRCUIT - Design and Applications." eo SQUARE ROOT By applying feedback from the output to both the X and Y inputs, the square root function can be obtained. The errors in the square root mode become large for small values of Z input. The actual output is approximately eO'= 10 sin ge j )-~O S.71Skn Square root output eo d/IO.(ZI - Z2) + 10 Em where Em is the total error for the multiply mode. Burr-Brown's multifunction converter model 4302 is recommended for applications requiring more accuracy over wider dynamic range. IOkn The output offset should be nulled for optimum performance by allowing the input to be its smallest expected value and adjusting R, for the proper output voltage. (-IOV" ej" +IOV, and IV = 9°) FIGURE 13. Sine Function Connections - 4214. 5-65 BUR.R.-BROWN@ 4301 I~ElI Low Cost MULTIFUNCTION CONVERTER FEATURES DESCRIPTION • LOW COST Burr-Brown's multifunction converter model 430 I is a low-cost solution to many analog 'conversion needs. Much more than just another multiplier/ divider, the 4301 out performs many analog circuit functions with a very-high degree of accuracy at a very-low total cost to the user. • SMALL PACKAGE· Oual·ln·llne • HERMETIC. SHIELDED PACKAGE • UNIVERSAL CONVERTER FUNCTIO,.S MULTIPLY DIVIDE SQUARE SQUARE ROOT EXPONENTIATE ROOTS SINE 8 COSINE 8 TAN-1IY/XI .,f'lT+V2 ACCURACY ±O.25% ±O.25% ±O.D3% ±O.D7% ±O.15% 1m = 51 ±O.2% 1m = 0.21 ±D.5% ±O.8% ±D.6% ±D.07% vyn-......lVVt....J .. r--vEo vxo--....:;;;;;.;..-<~ vzo----~~~~~ I.vz) E1=Vy\v. . POWERS ROOTS III . Inlernltional Alrporllndustrlll Park - P.O. Box 11400 - Tucson. Artzooa 85734 . Tal. 16021 746-1111 . Twx: 910-952-1111 - Cabla: BBRCORP - Talax: 66-6491 PD5-307G 5-66 MECHANICAL SPECIFICATIONS ELECTRICAL NOTE: Leads in true position within 0.OI0"IO.2Smml R at seating plane. Typical at +25°9 and with rated supply unless otherwise noted. MODEL 4301 TRANSFER FUNCTION Eo = Vy IVz/Vxlm RATED OUTPUT Voltage Current +10.0V SmA INPUT Signal Range Absolute Maximum Impedance IX/VIZ) os (Vx. Vy. VZI S +10V (Vx. Vy. VZI :5 ±18V 100klll90kll/l00kll EXPONENT RANGE(1) Roots (0.2 :5 m < 11 Powers (1 < m S 5) Powers (m = 11 R1 = POWER REQUIREMENTS Rated Supply Range Quiescent Current ±ISVDC ±12VDC to ±18VDC ±10mA m m TEMPERATURE RANGE Operating Storage = I R2/1R, + R211 = IIR, + R21/R21 on. R2 not used Pin numbers shown for reference only. Numbers are not marked on package. MILLIMETERS MIN MAX INCHES MIN MAX -2S o C to +8SoC A -25°C to +85°C .... .4S0 .170 NOTE: 1. Refer to Figure 1. o G H .880 21.84 .610 12.46 4.32 12.96 6.35 0.53 0 .• ' 2.54 BASIC 2.92 3.94 .150 .300 .3008ASIC 3.81 7.62 7.62 BASIC .08. 2.03 .016 .120 3.06 CASE: Kovar or equiv. WEIGHT: 0.15 oz. 13.4 grams, CONNECTOR: 14-pin DIP connector Burr;.Brown Model No. 0145MC~ General specifications for the Model 430 I Multifunction Converter are shown above; Figure I is a functional diagram. These specifications characterize the 430 I as a versatile three input multifunction converter. Applications information to help you apply the 4301 to your particular need is shown in the product data sheet for model 4302. The dedicated circuit configurations needed to produce the multiplication, division, exponentiation, square rooting, squaring, sine, cosine, arctangent, and vector algebraic functions are shown along with information for model 4302. Pin material and plating composition conform to method 2003 Isolderability, of MIL-STD-883 lexcept paragraph 3.21. PIN CONNECTIONS +ISVDC YINPUT 014 10 0 0 me 0 0 me COMMON 0 0 0 Z OFFSET 0 08 0 0 70 I BOTTOM VIEW, v,o-.....~M_,U~ Vxo----------o~ruil~----~ Vzo---------~~IUTIO J~ ~--~~~--9P--~ .. 22.36 .021 .100 BASIC .165 .115 .250 ROOTS POWERS FIGURE I. Functional Diagram. 5-67 ED=V,\v. I.vz)m ... X INPUT OUTPUT -15VDC X OFFSET mA ZINPUT 4302 BURR - BROWN ® IElElI Low Cost MULTIFUNCTION CONVERTER FEATURES • LOW COST • SMALL PACKAGE· Dual·in·line • RELIABLE HYBRID CONSTRUCTION • VERSATILE FUNCTIONS ACCURACY :to.25% ±O.25% ±O.03% ±O.07% ±0.15% 1m = 51 :to.2% 1m =.21 MULTIPLY DIVIDE SQUARE SQUARE ROOT EXPONENTIATE ROOTS SINE II COSINE II TAN.1 IY/XI ±O~5% ±O.B% ±O.6% ±O.07% ~ Typical accuracies expressed as a % of output full scale (+IOVDC) at 2S"C. DESCRIPTION Burr-Brown's multifunction converter model 4302 is a low cost solution to many analog conversion needs. Much more than just another multiplier/divider, the 4302 out performs many analog circuit functions with a very high degree of accuracy at a very low total cost to the user. International Airport IndUllrlal Park· P.O. Box 11400 . TueiOll. Arizona 85734 • Tel. (602) 7411-1111 • Twx: 9111-952·11.11 • Cable: .BBRCORP • Telex: 66-6491 PDS·326C 5-68 SPECIFICATIONS Performance typical at 2S o C and with rated supply unless otherwise noted. MECHANICAL ELECTRICAL MODEL + :::.17 I ~~~O~;~)~· O~OD 4302 TRANSFER FUNCTION Vz Eo = Vy (v,-) 12.7rnm 20.3mm (0.80") III RATED OUTPUT Voltage Current . +IO.OV 5 rnA • 0"" (VX, Vy, VZ) ""+10 V (VX, Vy, VZ) ";±.18 V 100 kn/90 ill/ 100 kn Powers (I < m"; 5) (m = I) 6.4mm m=~ Refer to RI +R2 Functional Diagram _ RI + R2 m---below R2 RI = 0 n, R2 not used (0.25") pin 14 --I~ pin 1 EXPONENT RANGE Roots (0.2 ,.; m < I ) -( -'" ~1 INPUT Signal Range Absolute Maximum Impedance (X/Y/Z) (0.50") O.51mm (0.020") Row Spacing: 7 .6mm (0.300") Weight: 3.4 grams (O.12 oz.) Connector: 14-pln DIP 0145MC Pin material and plating composition conform to Method 208 (solderabilitv) of MiI·Std·202. POWER REQUIREMENTS Rated Supply Range Quiescent Current ±15 VOC ±12 to ±18 VDC ±IOmA PIN CONNECTIONS +15 VDe Y fnput TEMPERATURE RANGE -25 0 C to +85 0 C -55 0 C to +125 0 C Operating Storage me mB t:ommon Make No Conn. Z Offset Adj. 414 413 !1211 410 ~ ~8 I*' 2*, X Input Output -15 VDe :t Make No Conn. S*' rnA Z Input 5¢- . X Offset Adj. 7*" (BOTTOM VIEW) 4302 FUNCTIONAL DIAGRAM General specifications for the Model 4302 Multifunction Converter are presented on this page. These specifications characterize the 4302 as a versatile three input multifunction converter. The following pages are applications oriented to help you apply the 4302 to your particular circuit function need. These pages contain dedicated circuit configurations in order to produce the functions of: multiplication, division, exponentiation, square rooting, squaring, sine, cosine, arctangent, and vector algebra. It is the purpose of this product data sheet to enable you to apply the 4302 to your a1ialogconversion needs quickly and efficiently. Vy o-......J1"""--a Vxo---------~lHrr~:l----~ Vzo---------~~ ... POWERS ROOTS (0.2<: m< I) (1 < m <: 5) (m= I) ~..... ~ .... . Many of the following circuit configurations using the 4302 require a reference voltage for scaling purposes. The reference voltage is shown to be +15 VDe (+15 VDe REF.) since in most cases the +ISVDC 'Power source for the 4302 has sufficient time and temperature related stability to achieve the specified typical accuracies_ 5-69 If the particular supplies which are available for powering the 4302 do not have the necessary stability for"the required conversion accuracy. an additional + 15 VDC precision su pply may be required. MULTI PLI ER/D1V'I'DERFUNCTIONS MULTIPLIER ---'----"'"""""--------In multiplier applications. the 4302 provides high accuracy at a low cost. The 4302 accepts inputs up to + 10 VDC and provides a typical accuracy of ±0.25% of full scale. El E2 Eo=+-- Transfer Function 10 ACCURACY Total Errors Typical at +25 0 C Maximum at +2SoC (for input range) vs. Temperature Offset Errors (E I = EJ. = 0) Output Offset (at 25 C) vs. Temperature { ±25 mV ±50mV '0.03V .;; EI .;; 10 V 0.01 V';;E 2 ';;IOV ±I mV/oC * ±10 mY. ±0.2mV/oC NOISE (10 Hz to I kHz) 100 /loV mis BANDWIDTH (EI' E 2) Small Signal ( -3 dB) Full Output 500 kHz 60 kHz (I) Set R I so that with E I =' 112 = +I 0.00 VDC, Eo = +I 0.00 VDC. DIVIDER As a divider, the 4302 outperforms many of the multiplier/ dividers on the market at a much lower cost. In the divider configuration the 4302 boasts ~ typical conversion accuracy of ±0.25% of full scale. E I O-__....,..--{7)ij"'""":""''''''''1'2l J "",Eo +15VDC REF LJ~~V4~~n . ,Transfer Function Eo = +10 (EllE3) ACCURACY Total Errors Typical at +25 0 C Maximum at +2S~C ±25 mV ±SO mV (for EI .;; E3 and input range) vs. Temperature Offset Errors (E 1 = 0, E3 = +10 V) Output Offset (at 25°C) vs. Temperature NOISE (10 Hz to I kHz) E 3 =+lOV E 3 =+0.1 V BANDWIDTH (E 1 , E 3 ) Small Signal (·3 dB) Full Output (E3 = +10 V) E3O----:---<..!.J.~~""lO"'O~ * { 0.03V';; EI .;; 10 V 0.IV.;;E 3 ';;IOV ±l mV/oC -15VDC ±10mV ±1 mV/oC 10kf! +15VDC -15 VDC 10 kf! +15 VDC NOTES: (1) Set RI so that with E I = E3 = +10.00 VDC, Eo = +10.00 VDC. (2) Set R2 so that with EI = E3 = +0.10 VDC, Eo = +10.00 VDC. (3) Set R3 so that with EI = +0.01 VDC and with E3 = +0.10 VDC, Eo = + 1.00 V D C . ' (4) Repeat steps 1 through 3 as necessary to achieve the speCified 100 /loV rms 300 /loV rms 500 kHz 60kHz output voltages. !II The input voltage may be extended below O.03V by connecting a 0.047 ",F capacitor between pins 11 and 5, causing a slight reduction in bandwidth. (Multiply and Divide Modes). EXPONENTIAL FUNCTIONS Model 4302 may be used as exponentiator over a range of exponents from 0.2 to 5. The exponents 0.5 and 2, square rooting and squaring respectively, are often used functions and are treated below. Other values of exponents (m) may be useful in terms of linearization of nonlinear functions or simply for producing the mathematical conversions. Characteristicsofm =0.2 and m =5 are presented on the right. For other values of m the curves presented in Figure 3 may be used to interpolate the error for a nonspecified value of m. Transfer Function Total Conversion Error (typical) m= 0.2 0.5 VDC< E 1 ';; 10 VDC 0.1 VDC < E1 .;; 0.5 VDC Eo=10(~~r ±2 m VDC ±25 m VDC m: S 1.0 VDC < E1 .;; 10 VDC Exponent Range (continuous)· Input Volta:ge Range Output Voltage Range 5-70 ±l5 m VDC 0.2';; m';; 5 o to +10 VDC o to +10 VDC 10r_----,------r--~~------r_~=_. _ Use these connections when taking roots of small input levels. Exponentiator Transfer Characteristics NOTES: (1) Connect a 100 .0. potentiometer as shown in Figure 4 for either roots (0.2 .. m < I) or powers (1 < m .. 5). (2) Set RI so that with EI = +10.00 VDC, Eo = +10.00 VDC. (3) Select a + DC voltage level (E I ) such that the output voltage (Eol. as acted upon by the desired exponent, will not exceed +10.00 VDC. A level which.js mid-range for input values of interest is an appropriate one to use. Set R2 so that the output voltage (EO> is the value expected for the chosen values of input (EI) and exponent (m). SQUARE ROOT As a Square Rooter (m = 0.5), the 4302 provides a typical total conversion accuracy of ±0.07%. Refer to Figure 5 and notes for connections and adjustments respectively. Tnnsfer Function Total Conversion Error (Typical) 0.5 VDC < E 1 .. 10 VDC 0.02 VDC < El .. 0.5 VDC Input Voltage Range Output Voltage Range Eo=10~ 10 ±7mV ±SS mV Oto +10 VDC o to +10 VDC NOTES: (I) Connect pins 12, 11, and 6 together. Set Rl such that with EI = +10.00 VDC; Eo = +10.00 VDC. (2) Connect 100 n resistors as shown in Figure S. (3) For greater conversion accuracy, R2 & R3 may be replaced by a potentiometer as shown in Figure 4. SQUARE ConfIgured as a Square Function Converter (m = 2), the 4302 produces high conversion accuracies of typically 0.03%. Please refer to Figure 6 and accompanying notes. G~ )2 Transfer Function Eo = 10 Total Conversion Error (typical) 0.1 VDC .. EI .. 10 VDC Input Voltage Range Output Voltage Range ±3mV OtO+lO VDC o to +10 VDC NOTES: (I) Set RI such that with EI = +10.00 VDC, Eo = +10.00 VDC. (2) Connect 100 n resistors as shown in Figure 6. (3) For greater conversion accuracy R2 & R3 may be replaced by a potentiometer as shown in Figure 4. 5-71 (4) Repeat steps (2) through (4) as necessary. • When taking roots of smaller input levels, a modified transfer equation lEo = (lOEl)ml will provide improved conversion accuracy. To achieve this transfer function: 1) apply a +1.S VDC REF in place of the +IS VDC REF shown in Figure 4., 2) make R3 a 1.40 Mn resistor, and rearrange Rl and R3 as I.SVDC REF anp 3) follow all notes except in note (2) apply +O.IOVDC to pin 7 to set RI to Eo = +1.00VDC. TRIGONOMETRIC FUNCTIONS SINE Sine functio ns Cl\n be accurately generated from input voltlIge le~els re presenting angular displacement from 0 to 900 • Model 4302 configured as in Figure 7 will produce the sine power serie S approximations with modified coefficients to typically be tter than ±0.5% of full scale. In this circuit, the 4302 is sealed so that when 8 = 0, Eo = 0 VDC, and when 8 =90, Eo = IQ VDC. NOTES: () Adjust R4 if needed so that E) < ) m VDC when E9 = O. (2) Adjust R2 so that EI =+0.8045 VDC when E8 =+5.00 VDC. (3) Adjust R 3 so that E) =+5.709 VDC when E8 =+)0.00 VDC. (4) Repeat 5t eps (2) and (3) as necessary. Transfer Function P~wer Eo = )0 Sin 9E8 Series Approximation Eo E8 Y·827 = ).5708E 8 -1.5924 ~6.366 Total Conversion Enor (typical) ±50mV Input Voltage Range (0 .; 8 .; 90°) Oto+10 VDC Output Voltage Range (0 ';sin·8 .;) o to +10 VDC FIGURE 7 RI +15 Vdc REF 10 kn 137 kn R2 10.0 kn 845 kn 10.0 kn E8LF------------------~~--------------------~ COSINE Connected as in F igure 2, the Model 4302 will generate a cosine function of the inpl,lt voltage. Typical accuracies of ±0.8% can be expected from this conftguration. NOTES: (I) Adjust R) so that Eo =+10.00 VDC when E8 =O. (2) Adjust R2 so that Eo = 0 when E8 = +10.00 VDC. Transfer Function Eo Total Conversion Error (typical) ±80mV Input Voltage Range (0 .; 8 .; 90°) o VDC to +10 VDC Output Voltage Range (l .; cos 8 .; 0) +10 VDC to 0 VDC +15 VDC REF, 20.5 kSl 14.0 kSl 10.0 kSl 37.4 kSl E8()------------------~------------------------~ 5-72 = 10 cos 9E8 Power Series Approximation 'Eo = 10 + 0.3652 E8 -0.4276E 1.504 ARCTANGENT Model 4302 and the associated circuitry shown below will produce the inverse tangent of a ratio. This application is particularly well suited to conversion from rectangular coordinates to polar coordinates where E() Transfer Function Eo=tan -~[Elll lE2l C-~i!.y·2125 ~ =tan-I Ex Power Series Approximation [E21 Eo = 1+ CEil -[ E2 l The accuracy of conversion depends upon the levels of the input signals. Please refer to table at right. Total Conversion Error 2 The above conditions imply. OV e;;; Ei e;;; JOV and -5V e;;; E! e;;; 5V. (b) The above conditions also imply that for applications where EI = I Ell the range would he limited to 4.l42V max. 2. Use of mode13627 as shown in Figure II would directly substitute the eight IOkO resistors and the two model 3S01A op amps. This would reduce the number of components needed to implement vector magnitude function and reduce overall cost. Oto +I0VDC -IOVDC to +I0VDC ~--------~-----r~~ IN4154 or lIquiv. E, IN4lS4orequiv. 5-73 4340 BURR - BROWN ® I~ElI TRUE RMS-TO-OC CONVERTER FEATURES • LOW COST • HIGH ACCURACY :to.3mV ±D.1% Rdg. • HIGH INPUT IMPEDANCE - 5kn • HERMETIC METAL PACKAGE DESCRIPTION The Burr-Brown Model 4340 is a True RMS-to-DC Converter featuring high performance, low cost, and a small hermetic package. The 4340 will compute the True RMS value of a variety of signals applied to the input. The input signal may consist of complex AC waveforms as well as a DC voltage level. The output of the 4340 is a DC voltage, the amplitude of which is equal to the RMS value of the input voltage. The 4340 will accept input voltages from 0 to ±lOV over a wide input. frequency range. The conversion accuracy of the 4340 is specified in terms of error in millivolts (mV) plus a percent of reading, as a function of input signal level over an input frequency range. The 4340 has an input impedance of 5kn and an output impedance of I n. This product will supply up to 5mA of output current at a voltage of+lOVDC. The input is fully protected for conditions of overvoltage up to the supply voltage. The output will withstand short-circuit to power supply common for an indefinte period ·of time. The specified unadjusted performance characteristics of the 4340 are shown in the ELECTRICAL SPECIFICAnONS. Provision for the external adjustment of: gain, voltage offset, DC reversal error, and frequency response performance allow the user to improve upon the specified conversion accuracies to the degree required by the user's application. Inlarnatlonal Airport Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746·1111· Twx: ~10-952·1I11 . Cable: BBRCORP· Telex: 88-6491 PDS-304D 5-74 SPECI FICATIONS r ELECTRICAL (1 ypical at 25°C with rated power supplies unless otherwise noted). MECHANICAL 4340 MODEL TRANSFER F-UNCTION Eo (d.c.) = j I----- EJN2 I INPUT ±10 Vdc t Supply 5kn Peak Voltage Absolute Maximum Voltage Impedance 0.85"--1 (21.6) I BURR-BROWN OUTPUT 0.50" RMS CONVERTER ~~~~~~~4~34~O~~ Oto+IOVdc Voltage Current (min) Impedance T +5 iliA In CONVERSION ACCURACY (TOP VIEW) Total Unadjusted Error (max) Input: 10 mV rms to 7.0 fms 100 Hz to 10kHz sine wave" Total Adjusted Error·" Input: lOmVrmsto7Vrms 50 Hz to 20 kHz' ±2 mV ±O.2% Reading Dimensions in millimeters are shown in parentheses. ±O.3 mV ±O.l% Reading ~--""""~ STABILITY to.OO I % of FS plus Accuracy vs Temperature ±O.O 1%of reading per oc to.OOI% of FS plus ±O.Ol%ofreading per%6V Accuracy vs Supply TEMPERATURE RANGE POWER REQUIREMENTS . tiS Vdc ±14 Vdc to ±16 Vdc ±i2 mA Rated Voltage Voltage Range Quiescent Current J"o" ~ ~ ij ~ ~ T ~D 0 0 0 ~ D 0 0.1O"t-= ~0.018" (2.S) 0.60" dia. -25 0 C to +85 0 C -55 0 C to +ilSOC Operating Storage 1: :; J (15.2) (0.46) (SIDE VIEW) Row Spacing: 0.30" (7.6) Pin material and plating composition meet Method 2003 (solderability) of Mil·Std·883 lexcept for paragraph 3.2.1 * Model 4340 will convert d.c. inputs. Lower frequency a.c. input signals will require the addition of external capacitors to preserve the accuracy. ** Performance with external trims and CL ~ 3 JJF and 20 pF ::;;;; CH ::;;;; 100 pF. PIN CONNECTIONS Averaging Square Rooting ,,--. I I I Eo >-~-IFx I I I Output "I @ @ @ 'Pin Pin 8 I @@'\ I L--fL____ - I ~ -- J R_an_g1_.n_g_C_ir_c_u_it_ _ _. . I : --~ FIGURE 1. Functional Block Diagram of Model 4340. 5-75 Common Reversal . Adjustment (BOTTOM VIEW) INSTALLATION AND OPERATING INSTRUCTIONS -15 Vdc +15 Vdc Eo· -------- 0------- o MODEL 4340 Eo ·= I Output EI2 FIGURE 2. Model 4340 RMS Converter - Connected to produce specified unadjusted accuracy. OPTIONAL EXTERNAL ADJUSTMENTS Although the unadjusted performance of the 4340 is quite high for most applications, optimized performance can be achieved with external adjustments. The following paragraphs and figures will demonstrate the techniques for external adjustments of gain, voltage offset, d.c. reversal error, and frequency response. The unity gain adjustment should be made first, then the offset voltage adjustment. The unity gain adjustment should then be repeated for best results. UNITY GAIN OffSET VOLTAGE -15 Vdc +15 Vdc I k!l MODEL 4340 Output FIGURE 3. Unity Gain Adjustment - Apply +5 V rms Sine Wave to Input. Adjust Rl for +5 Vdc at Output. FIGURE 4. 5-76 Offset Voltage Adjustment - Adjust R2for IOmVdc at Output. fREQUENCY RESPONSE The conversion accuracy of the 4340 over a broad range of input frequencies can be enhanced by the addition of one or more externally connected capaci· tors. Refering to Figure 5, CH will improve the high frequency perfor· mance and CL will extend the low frequency response. HIGH FREQUENCY RESPONSE COMPENSATION MODEL 4340 Input Output FIGURE 5. Frequency Response Adjustments - CH· = 22 pF to 100 pF and CL ;. 3.0 j,LF for "adjusted" frequency response range. LOW FREQUENCY RESPONSE EXTENSION The upper limit of frequency response of the 4340 may be extended to meet the adjusted conversion accuracy speci· fication by the proper selection of CH' Sweep a LO V rms signal from 10 kHz to 20 kHz, measure the output voltage change from LO Vdc. Select a value for CH that minimizes the change in output voltage over 10 kHz to 20 kHz frequency range. * -15 Vdc CH may be selected from 22 pF, 33 pF, 47 pF, or 100 pF. In the 4340, a single-pole, low pass filter provides the averaging function. The time constant of this filter (To) is selected to be 0.005 seconds. Larger time constants should be selected in order to achieve the Conversion Accuracy at frequencies lower than 100 Hz. The external capacitor can be 100's of microfarads, but the shunt resistance of the capacitor must be very large in order to maintain gain accuracy. The best value of CL is inherently a compromise - the larger the capacitor the lower the ripple, but the response time is increased. Calculating the proper CL for a given waveform can be done, but is tedious. The fastest method of chOOSing CL is to apply a representative input signal, and observe the ripple at the out· put. Select various values of CL until the ripple is attenuated sufficiently. The amount of allowable output ripple depends upon the application. For ex· ample, if the output is being read by an integrating DVM, then output ripple won't be critical. ADDITIONAL ADJUSTMENTS NON-UNITY GAIN D.C. REVERSAL ERROR The 4340 may be adjusted to achieve a non-unity gain trans- When the 4340 is utilized with D.C. inputs and a high degree of conversion accuracy is required, a correction for d.c. reversal error may be required. Figure 7 illustrates the method to accomplish this adjustment. fer function: Eo =A JEIN2 for I < A" 10. Figure 6 il- lustrates the technique to achieve this gain change. -15 Vdc +5.000 Vdc Output Input MODEL 4340 Output . FIGURE 6. Non-Unity Gain Adjustment - Set desired gain by selecting R3 such that R3 =(A2_ I)x 10kn. Apply appropriate mid-scale d.c. level to Input and adjust ~ for output equal to A x VInput (V dc). . FIGURE 7. D.C. Reversal Error Adjustment - Alternately switch the input between +5.000 Vdc and -5.000 Vdc, adjust R5 so that the output error voltage from +5.000 Vdc is the same for both input polarities. NOTE: Some minor interaction may be experienced between tpe various adjustments requiring repeating of these adjustments for lowest total error. 5-77 I -.' 4341 BURR-BROWN@ IElElI Low Cost TRUE RMS-TO-OC CONVERTER FEATURES • LOW COST • HIGH ACCURACY iO.2% t2mV • HIGH RELIABILITY Hybrid construction DESCRIPTION The Burr-Brown Model 4341 RMS-to-DC Converter feature~ low cost without sacrificing performance. The 4341 computes a DC voltage proportional to the true rms value of signals which may be complex waveforms, DC levels, or a . combination of both. The input and output are fully protected against overvoltages and short circuits. Provisions for the external adjustmeQt of gain, offset voltage, DCreversal error, and f/'l:quency response make the 4341 versatile enough to fill the majority of your applications. 1 International Alrporllnduslrial Park· P.O. Box 11400· Tucson. ArlzOIIa 85734· Tel. 1602) 746-11 II • Twx: 910-952·11 II . Cable: BBRCORp· Telex: 66·6491 PDS-323A 5-78 13 12 4t-------------~ -, r I Averaging I I C I Capacitor 2 log / I E in I = I Gain I Setting log Ein 2 ~I +15V I I ~ -15V I ... I.. (_R _ _ l E in 2 SCR + 1 e';ut FIGURE I. Simplified Schematic. THEORY OF OPERATION The true RMS value of a time-varying signal E (t) over a time period T is ERMS =l+ f ~ Transistor QI produces a collector current i2 proportional to the antilog of its base-emitter volt"ge, such that [E(t)] 2 dt The required operations are squaring, averaging and square rooting. A simplified schematic diagram of the 4341 is shown in Figure 1. The A I circuit produces a current i I which is proportional to the rectified input voltage. The A2 circuit is a logarithmic amplifier which produces a voltage proportional to 2 log Ein or log Ein 2. The logarithmic gain of the A2 circuit is derived from the inherent exponential characteristics of transistor junctions. By using proprietary monolithic components, the circuit provides an accurate log function over many decades which is relatively insensitive to temperature variations. Amplifier A4 uses the same techniques as A2 to generate log Eout . i2 IX log-I (log Ein 2 - log EouJ = log-I (log E· 2 E" 2 E out Eout ..E!.... ) = ..El.- The A3 circuit which contains the external capacitor takes the time average of the i2 signal and produces Eout which is directly proportional to the RMS value of Ein. Figures 2 and 3 show the effects of the external filter capacitor on ripple m&gnitude and response time. As the frequency ofthe input approaches DC, the 4341 begins to act like a full wave rectifier such that the outpui is the absolute value of the input. While the 4341 will accurately convert dc input voltages, the averaging capacitor must be made very large to minimize ripple at low frequencies. 5-79 SPECIFICATIONS (Typical at 25°C with rated supply voltages, unless otherwise noted.) ELECTRICAL TRANSFER FUNCTION MECHANICAL 4341 MOOEL Eout(DC) =J +f J Ein 2 (1) dl INPUT tlOV tSupply 5 kn Peak Operating Voltage Absolute Maximum Voltage Impedance 20.3mm (O.SO") BANDWIDTH ± I % of Theoretical Output y- pin CONVERSION ACCURACy(2) Input: 500 mV RMS to 5.0 V RMS DC to 10kHz Sine Wave Input: 10 mV RMS 107 V RMS DC 10 20 kHz . 6.4mm (0.25") r7 1~ ~---1 14 JL.51:: (0.020") to.S% of Reading, max(l) t2 mV ±0.2% Reading' STABILITY Accuracy VS. Temperature Accuracy vs. Supply Voltage ~~~~ 4.6mm (0.1S") n,max 80 kHz 450 kHz -3 dB "I 1 pin 1 010 +IOV +SmA,min 1 12.7mm (0.50") dotover~,....->- OUTPUT Voltage Current Resistance t to.1 mV to.OI%of Reading/oC to.1 mVtO.OI%of Reading/%of Supply Voltage Change TEMPERATURE RANGE 0145MC Pin material and plating composition conform to Metfiod 208 {solderability} -25°C to +8S o C -55°C to +12S o C Operating Storage Row Spacing: 7.6mm (0.300") Weight: 3.4 grams (0.12 oz.) Connector: 14-Pin DIP of MiI-5td-202. POWER REQUIREMENTS Rated Voltage Voltage Range Quiescent Current %15 VDC il4 VDC to tl6 VDC il2 mA, typ./±24 mA, max (1) After standard trim procedure (see bolow). (2) Model 4341 will convert DC inputs. Lower frequency AC inputs require a large value of averaging capacitor to minimize ripple at output. (Soe Figure 2) STANDARD TRIM PROCEDURE 1. Set Ein =5.000 V RMS ±O.02% and adjust R 1 such If the 4341 is used to measure sine waves or that Eo =5.000 VDC ±2 mY. 2. Set Ein = 500 mV'RMS ±O.02% and adjust R2 such that Eo =500 mVDC ±0.2 mY. 3. Repeat Step 1. distorted sine waves, only two trims are needed to achieve an accuracy of ±0.5% of reading from 500 mV RMS to 5 V RMS up to 10 kHz. Refer to Figure 1. 5-80 CHOOSING THE AVERAGING CAPACITOR A single-pole low-pass RC filter provides the averaging function. The time constant is 1/2 RC where R is IOkO when the 4341 is adjusted for unity gain. To select the best value of C, make a tradeoff between output ripple and response time. Figure 2 shows the ripple magnitude vs. frequency for several typical values of capacitor. Response time vs. capacitor value is shown in Figure 3. (N ote that rise times and fall times are different for the same value of capacitor). While the ripple magnitude for signals other than sine waves can be analytically determined, it is tedious. The fastest method of choosing C is to apply a representative input signal and observe the output for various value of C. C can be 100's of microfarads, but should have a leakage current less than O.I/LA to minimize gain errors. With very large values of C, the input signals with frequencies approaching DC level could be averaged. Since the output is always a positive voltage, C can be polar capacitor. 10.000 ~ "0 > 0: C. G C. 0. a: 10Hz 30Hz 70Hz 100Hz 300Hz 700Hz 1 kHz 1.0av RMS Sine Wave Input Frequency Averaging Capacitor Value FIGURE 2. Output Ripple Magnitude vs. Input Signal Frequency. FIGURE 3. Response Time vs. Value of Averaging Capacitor. EXPANDED TRIM PROCEDURE FOR GREATER ACCURACY If the 4341 is used in applications to measure complex waveforms, the following expanded trim procedure is recommended. (Refer to Figure 4). First set all potentiometers at mid turn position. 1. DC Reversal Error - Apply +IO.OOOV ±lmV and -1O.OOOV ±lmV to E;n alternatively, adjust R5 such that Eo readings are the same ±2mV. 2. Gain Adjustment - Apply E;n = +IO.OOOVDC ±lmV, adjust Rl such that Eo = +1O.OOOVDC ±lmV. 3. Input Offset - Apply +1O.OmV ±O.lmV and -1O.0mV ±o.1 m V to E;n, adjust R4 such that Eo readings are the same ±o.lmV. 4. Offset - Ground E;n, adjust R3 such that Eo = 0 ±o.lmV. Repeat Step (3). 5. Low Level Accuracy - Apply E;n =+1O.0mV ±o.lmV, adjust R2 such that Eo = +lO.OmV ±o.lmV. c' Averaging Capacitor +15VDC 10:~1~ -15VDC 20% ;OMSlI ~O% ~I;.'\R~ Range f 20%!+15VDC 10MSl R3 +15VDC~-15VDC l~~Sl 110kSl -15VDC FIGURE 4. Expanded Trim Procedure (High Accuracy Applications). NONUNITY GAINS Gain values greater than unity can be achieved by inserting resistor Rx between pin 5 and pin 6. Rx where A is the desired value of gain (I < A .;;; 10). (Rx is in ohms). 5-81 =(A 2 -I) x 10k +2k 4423 BURR-BROWN® IElElI PRECISION QUADRATURE OSCILLATOR FEATURES •. SINE AND COSINE OUTPUTS • RESISTOR PROGRAMMABLE FREQUENCY • WIDE FREQUENCY RANGE O.OO2Hz to 20kHz • LOW DISTORTION 0.2% max up to 5kHz • EASY ADJUSTMENTS • SMALL SIZE • LOW COST DESCRIPTION The Model 4423 is a precision quadrature oscillator. It has two outputs 90 degrees out of phase with each other, thus providing sine and cosine wave outputs available at the same time. The 4423 is resistor programmable and is easy to use. It has low distortion (0.2% max up to 5 kHz) and excellent frequency and amplitude stability. The Model 4423 also includes an uncommitted operational amplifier which may be used as a buffer, a level shifter or as an independent operational amplifier. The 4423 is packaged in a versatile, small, low cost DIP package. International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona B5734· Tei. (602] 746·1111· Twx: 91[J.952·1111 . Cable: BBRCORp· Telex: 66·6491 PDS·365A 5-82 SPECIFICATIONS Specifications typical at 25"C and ±15VDC Power Supply Unless Otherwise Noted ELECTRICAL MIN TYP MAX 20.0k 2k 0.002 21.0k 22.0k 20k 20k ±5 ±IOO MECHANICAL UNITS FREQUENCY Initial Frequency (no adjustments) Frequency Range (using 2 R's only) Frequency Range (using 2 R's and 2 C's) Accuracy of Frequency Equation· Stability vs Temperature Quadrature Phase Error ±I ±50 ±D. I Hz Hz Hz % pprn!"C degree i' ""'IJ I-~ 20.3mm 10.80") Dotov PIn 1 •• DISTORTION ---rJ ~~~~ Sine Output (pin I) O.OO2Hz to 5kHz 5kHz to 20kHz 0.2 0.5 Cosine Output (pin 7) O.OO2Hz to 5kHz 5kHz to 20kHz Distortion vs Temperature J-..-"' % % 0.2 0.8 % % 0.015 %/"C ~7 1 Pin ~J1 OUTPUT Amplitude (Sine) At 20 kHz vs Temperature vs Supply Output Current Output impedance 6.5 I.S 7 0.05 0.4 5 UNCOMMITTED DP AMP Input Offset Voltage Input Bias Current Input ImpedanceOpen Loop Gain Output Current 1.5 275 I 90 ., JLO.51mm 10.020"') rnV nA dB rnA ToWER SUPPLY ±I~ Rated Supply Voltage Supply Voltage Range Quiescent Current ±18 ±18 VDC VDC rnA +70 +85 +125 "C "C "C ±12 ±9 TEMPERATURE RANGE Specifications Operation Storage • May be trimmed for better +. ~ A4 0 -25 -55 5 - 6 ~ccuracy. PIN CONNECTIONS 1. E1, Sine Output 2. 3. 4. 5. Frequency Adjustment Frequency Adjustment +In, Uncommitted Op Amp -In, Uncommitted Op Amp 6., Output, Uncommitted Op Amp 7. E2, Cosine Output 8. Frequency Adjustment 9. -Vee. -15VDC 10. 11. 12. 13. 14. +V cc ' +15VDC Common Frequency Adjustment Frequency Adjustment Frequency Adjustment FIGURE L Equivalent Circuit 5-83 ~042~~ -Pin14 Mn 5 ~ Pin material and plating composition conform to method 2003 (solderability) of MIL-STD-883 (except paragraph 3.2). n I n~~~~ U ROW SPACING - 7.6 (0.300") WEIGHT - 3.4 gms (0.12 0') CONNECTOR· 14 pin DIP connector (145 MC) Vrms %!"C V/V rnA 7.5 12.7mm 10.50") TYPICAL PERFORMANCE CURVES +5% ~ ~~ -5% 100Hz I kHz 10kHz 100kHz Frequency FIGURE. 2. 10Hz 100Hz I kHz 10kHz Frequency 100kHz -5% -50 FIGURE 3. EXTERNAL CONNECTIONS 0 ........ ~ +50 H 00 Temperature °c H 50 FIGURE 4. The frequency f can be expressed by: 42.0S R f = (C + 0.001) (3.78S +2R) I. 20 kHz Quadrature Oscillator The 4423 does not require any external component to obtain a 20 kHz quadrature oscillator. The connection diagram is as shown in Figure S. where, f is in Hz C is in /IF and R is in kO E, = 10 sin 2".(20kll E, = 10sln 2"",, E2 = -10 cos 2".(20kll FIGURES. Eo = -10 cos 2""" 2. Resistor Programmable Quadrature Oscillator For resistor programmable frequencies in the 2 kHz to 20 kHz frequency range, the connection diagram is shown in Figure 6. Note that only two resistors of equal value are required. The resistor R can be expressed by, R - 3.78Sf , R in kO - 42.0S - 2f f in kHz c FIGURE 7. For best results, the capacitor values shown in Table I 'should be selected with respect to their frequency ranges. 20 kHz f E, 'e = 10 sin 2".ft 20 Hz f Eo = -10 cos 2,rl1 e to 2 kHz to 200 Hz to 2 kHz 200 Hz 0 O.OI"F O.I"F 0.2 Hz 0.02 Hz 2 Hz 20 Hz to to 2 Hz to to 0.2 Hz 0.02 Hz 0.002 Hz I"F 10"F 10O"F IOOO"F TABLE I. After selecting the capacitor for a particular frequency the value of the required resistor can be obtained by using the resistor selection curve shown in Figure 8 or by the expression: 3.78Sf (C + 0.001) where, R = 42.0S _ 2f (C + 0.001) RisinkO fis in Hz and C is in /IF FIGURE 6. 3. Quadrature Oscillator Programmable to 0.002 Hz For oscillator frequencies below 2000 Hz, use of ·two capacitors of equal value and two resistors of equal value as shown in Figure 7 is recommended. Connections shown in Figure 7 can be used to get oscillator frequency in the 0.002 Hz to 20 kHz range. 5-84 DISSIPATION FACTOR (OF) A capacitor can be modeled by an ideal capacitor in parallel with an internal resistor whose value depends on its dissipation factor (DF). Mathematically, the internal resistor R is given by, IOkH " , I kll f ...l < i loon ~~ r-9t,,,,V r-:.¢ -9!- <-~ ~v" "'~ ~, "' f0- X ;..; ton v R= ",. v v I 21Tf C(DF) In O.OOIHz O.OIHz O.IHz 1Hz 10Hz 100Hz FREQUENCV 1kHz 10kHz 100kH FIGURE 8. The curves shown in Figure 8 are provided only as a nomographic design aid. The selection of capacitor values is not limited to the values shown in Figure 8. Any suitable combination of Rand C values which satisfies the expression relating R, F and C as shown above, would work satisfactorily with the 4423. NOTES ON TYPES OF CAPACITORS TO USE: There are various kinds of capacitors available for use. There are polarized, also known as DC capacitors and non-polarized, also known as AC capacitors available. Of these two types, the polarized capacitors cannot be used with 4423 to set the frequencies. Commonly available non-polarized capacitors include NPO ceramic, silver mica, teflon, polystyrene, polycarbonate, mylar, ceramic disc etc. A comparison is shown in Table II. Capacitance Temperature Coefficients ppm/"C Dissipation Factor (%) SpF· 0.1 ~F SpF . 0.047 ~F 0.001 . 100 ~F 0.001 • SOO ~F 0.001 . 1000 ~F 0.001 . 100 ~F 30 60 200 100 90 60 O.OS O.OS 0.01 0.03 0.08 0.1 0.001 . 1000 ~F 0.001 . 1000 ~F 0.001 • 2000 ~F SpF • O.S ~F 10 700 700 10.000 0.4 0.7 Range NPO Ceramic Silver Mica Teflon Polystyrene Polycarbonate Metalized Teflon Metalized Polycarbonate Mylar Metalized Mylar Ceramic Disc (~F) where R is in 0, f is the Hz, and C is in farads. For example, the DF of ceramic disc capacitors is of the order of 3%, which for a 0.01 /IF capacitor would look like having an internal resistor of 530kO at I kHz. The 530 kO value resistor is small enough to stop the 4423 oscillator from oscillating. Some capacitor manufacturers use the terms "Power Factor" (PF) or "Q Factor" (Q) instead of the term "Dissipation Factor". These terms are similar in meaning . and are mathematically related by, (DF) (PF)=r=== VI + (DF)' I Q=(DF) OSCILLATION AMPLITUDE It takes a finite time to build up the amplitude of the oscillation to its final full scale value. There is a relationship between the amplitude build-up time and the frequency. The lower the frequency, the longer the amplitude build-up time. For example, typically it takes 250 seconds at I Hz, 30 seconds at 10Hz, 4 seconds at 100 Hz, 400 milliseconds at I kHz, and 40 milliseconds at 10 kHz oscillator frequencies. There are two methods available to shorten this normal amplitude build-up time. But there is also a relationship between the amplitude build-up time and distortion at final amplitude value. When the amplitude build-up time is shortened, the distortion can get worse. One method to shorten the amplitude build-up time is to connect a resistor between pin 3 and pin 14. The lower this resistor is the shorter will be the time to build up amplitude of the oscillation, and worse will. be the distortion of the output waveform. For example, a lOOkO resistor would shorten the amplitude build up time from 15 seconds to I second at 20 Hz frequency, but the distortion could be degraded from tpically 0.05% to 0.5%. The other method is to momentarily insert a I kO resistor via a reset switch betwen pin 3 and pin 14. The amplitude of oscillation is built up instantaneously when the reset switch is pushed. There will be no degradation of distortion with this method since the I kO resistor does not remain in the circuit continuously. I 3 TABLE II. For use with the 4423 oscillator, the choice of capacitors depends mainly on the user's application, error budget and cost budget. Note that the specifications of 4423 do not include the error contribution of the external components. The errors sourced by external components normally have to be added to the 4423 specifications. As a general selection criteria we recommend the use of the above table. Start from the top of the list in the above table. If the capacitor is found unsuitable due to it being too large in size, too expensive, or is not easily available, then move down in the list for the next best selection. In any case do not choose or use any capacitors with dissipation factors greater than I %. Such a capacitor would stop 4423 oscillation. 5-85 ATF76 BURR-BROWN@ 1E3E31 ACTIV,E FILTERS FEATURES • LOW PROFILE PACKAGE • FACTORY TUNED • NO EXTERNAL COMPONENTS REQUIRED • WIDE TEMPERATURE RANGE DESCRIPTION r Burr-Brown's standard series of fixed-frequency active filters is available with a wide range of transfer characteristics and resonant frequencies. These modular units are pre-tuned at Burr.,Brown to the response you specify and they require no external components or adjustments. The ATF76 series includes Bessel, Butterworth, Chebyschev, band pass and band reject filters with up to eight poles. You can save hours of design and analysis, especiaily when your application requires a complex transfer function. These units have applications in communications equipment, servo systems, and process controllers as well as test. equipment. All filters are completely tested at the factory, and all give you the reliability you expect from Burr-Brown. . International Airport Industrial Plrk - P.O. 80x 11400 - Tucson. Arlzllftol 85734 - Tal. 16(2) 746-1111 - Twx: 910-952-1111 - Clbla: 88RCORP - Talex: 66-6491 PDS-345A 5-86 Specifications typical at 25°C and rated supply voltage unless otherwise noted. FIXED FREQUENCY ACTIVE FILTERS Burr-Brown's standard catalog active filters, the ATF76 series, are available with low pass, band pass, and band reject characteristics. The filters in this series are packaged in space-saving 0.4" high modules ranging in size from 1.5" x 1.5" for 2 pole low pass and notch models to only 2.1" x·3.0" for 8 pole low pass models. All filters are complete units that are factory tuned with no external components required. All standard active filters operate from ± 15 VDC power over a -25 0 C to +85 0 C temperature range. 50 Specifications typical at 15°C and rated supply voltage unless otherwise noted MODEL S ± 10'11> 10 ± 10% - 200 "V, RMS In ±5mA ±2mV ±SO "VloC ±l4mA (mJ ±25 "V/oC ±18mA 3'; x 2.1" x 0.4" (7) ±l2 to ± 18 VDC power may be used. (8) The offset may be trimmed to zero. (5) For models with higher IOput Impedance contact Burr-Brown or your local representative. (6) ±9 to ±l8 VDC power may be used. ATF76NI*N 2 ±lOV I to 20kHz ±2% ±O.OS%/oC (non-inverting) OdD, nom -1.6 dB, max N/A ±10mA ATF76-1 NI*M 2 30kO, min I to 20kHz ±2% ±O.OS%/oC (non-inverting) OdD, nom -0.4 dB, "max N/A "vf'c BAND-REJECT (NOTCH) ATF76LS *D 8 ±lOV 30kn,min ±IOV 30kn, min ±6 rnA ATF76L6 *D 6 +IOmA !!HII.S" x I.S" x 0.4" (9) All filters have nomnvertmg outputs except the single tuned band pass and band reject filter which have inverting outputs. M - S8RO T ~ I TYPE OF FILTER RESPONSE Low Pass B '" Butterworth C '" Chebyschev 0.4 dB nom ripple D '" Chebyschev . 1.6 dB nom ripple ·l = Bessel Band Pass K for Q = 1 (2 pole pairs only) M for Q= 2 NforO=5 PforO=10 CUTOFF OR CENTER FflEOUENCY S . Special Order indicate Q on order for 2 pole pairs 1 " a <. 20 1 pole pair 2 " Q < 50 o for 0 = 20 R for 0 = 50 (1 pole pair only: 5-88 Notch M for Q '" 2 N for Q = 5 Pfor Q= 10 S for a :; : Special (indicate Q on order, For frequencies less than 100 Hz, use "A" to indicate decimal point. Por frequencies greater than 100 Hz, the last digit Indicates number of zeros following first 3 digits of frequency. For example: 58Hz = 2 <;0<;10) 58RO, 580 Hz = 5800, 5800 Hz = 5801 Definition of Filter Responses LOW PASS FILTERS AMPLITUDE RESPONSE ~ ·1 ~ S-295G 5-93 SPECIFICATIONS ELECtRICAL Typical at 25°C and with rated supply unless otherwise noted. UAF21 (1 I UAF11 MODEL MECHANICAL UNITS HERMETIC METAL PACKAGE INPUT Input Bias Current Input Voltage Range Input Resistance ±100 ±10 lOOk ±15 ±10 lOOk nA V 0.001 to 20k 0.001 to 200k Hz % %1°C n NOTE: Leads in true ~si~~on within at seating plane. a.1oM 'O.25mml R at MMR TRANSFER CHARACTERISTICS Frequency Range (fol fo Accuracy(2) fo Stability(" (over temp. range I Range(4) Stability{5) al fo 0';104 al fo 0 ';105 Gain Range o o ±1/±5 ±1/±5 ±C.005 0.5 to 500 ±0.005 0.510500 ±0.025 ±0.1 0.1 to 50 ±C.Ol ±O.025 0.11050 %fOC %fOC 0.6 6.0 VI~sec 20 10 2 20 20 20 V V V ±10 2 200 10 ±10 10 mV 200 p.V,rms m.A --- OUTPUT Slew Rate Peak-to-Peak Output Swingle) fo:S;;; 10kHz fo:S;; 20kHz fo'; 100kHz Output Offset (at low-pass oUlput with unity gain) Output Impedance Noise(7) Output Curren«8) 10 n POWER SUPPLIES !l "-~In number shown for reference only: ;..+1_.:. ;N.:.um.:.be:.:. ;,rs are not marked on package. 0000000 0000000 INCHES MIN MAX DIM Rated Power Supplies Power Supply Range(9) Supply Current al ±15V (Oulescent) ±15 ±15 ±5 to±18 ±12, max ±5to±18 ±12, max V V mA TEMPERATURE RANGE Specification Temperature Range Epoxy Hermetic Storage Temperature Range -25 to +85 -5510+125 -5510+125 -25 to +85 -55 to +125 -5510 +125 NOTES 1. The UAF21 includes two internal 0.002~F power supply capacilors. 2. Repealibility of fo using 0.1% frequency determining resistors. 3. T.C.A. of external frequency determining resistors musl be added to this figure. 4. Derated 50% from maximum - see Typical Performance Curves. 5. 0 stability varies wilh both the value of 0 and the resonant frequency fo. 6. Low-pass output - see Typical Performance Curves. 7. Measured at the bandpass oUIPut with 0 = 50 over DC to 50kHz. 8. The current required to drive RF1 and RF2 (external) as well as C1 and C2 must come from this current. 9. For supplies below ±10V. 0 max will decrease slightly; fillers will operate below ±5V. PIN CONNECTIONS Pin 1. High-Pass Output Pin 2. Optional Pin Pin 3. Bandpass Output Pin 4. 0 Adjust Point Pin 5. Common Pin 6. +Supply Pin 7. Low-Pass Output Pin 8. Frequency Adjust Pin 9. -Supply Pin 10. Frequency Adjust Pin 11. Optional Pin Pin 12. Inpull Pin 13. Inpul2 Pin 14. Input 3 °C °C °C . MIN MAX 21.84 22.35 .510 .250 .021 12.45 4.32 0.41 12.95 6.35 0.53 D G .100 BASIC • C MILLIMETERS .880 "80 .490 .170 .016. H .115 .165 2.&4 BASIC 2.92 3.94 K L .150 .•00 ,300 BASIC 3.81 7,62 7,62 BASIC R .080 ,120 ro 2.0. '.05 EPOXY PACKAGE; NOTE: Leads in true position within Q.1Q~ (Q,25mml R at MMC at seating plane. L- . C Dono'e, P;n 1 ORDER NUMBER: UAF11 UAF21 ~5~~~ci:~R~rams 0145MC rH.Jl cJ[Nme. ~···,··~~·. TlG ::te.1, .. • 0 •• DIM INCHES MIN MAX MILLIMETERS MAX 20.51 12.95 .2•• .018 .021 .tOOBASIC 4.83 6.eO 0.48 0.63 ~190 R Note 1: Pin presence optional MIN C D Numbers may 20.07 12.45 .790 .490 G H K L . Pin numbers shown tor reference only. not marked on package, .810 .510 A • 5-94 7 8 1 14 R .080 .130 ."S ••00 .300 BASIC .080 ."5 2.54 BASIC 2.03 2.92 3.30 7.e2 7.62 BASIC 2.03 2.92 be TYPICAL PERFORMANCE CURVES o MAX. VS. RESONANT FREOUENCY FULL POWER RESPONSE 1000 100 80 a. a. '" "": X ~ 5 0 w 60 50 40 30 25 20 "100 ~ 15 ~ 10 8 ~ , x Low-Pass r\ ::il a Bandpass. .~ r'\ 6 10 High-Pass 2.5 i" 1.5 3 4 5 6 78 10 ~ 15 20 30 40 60 80 100 100 lk 10 20 30 40 60 80100 10k lOOk lOOk 1M UAFll UAFll 200 300 400 600 1000 lk 10k UAF21 UAF21 Frequency (kHz) Resonant Frequency, Hz APPLICATIONS INFORMATION T ABLE I. Useful References. TRANSFER FUNCTION The U AF21 uses the state variable technique to produce a basic second order transfer function. The equation describing the three outputs available are: T(Low-Pass) = T(Bandpass) = T(High-Pass) = where Wo = s' + (wo/Q) s + wo' s' + (wo/Q) s + we' 1. Tobey, Gene, et ai, Operational Amplifiers: Design and Applications, Chapter 8. McGraw=-f:lili Book Company, 19h - - - - - 2. Wong. Yu Jen, and William Ott: Function Circuits: Design and l:PRlications, Chapter 6, McGraw-Hili Book Company, 197~ 3. Daniels, Richard W.: ,bpproximation Methods for Electronic Filter Desig!1. McGraw-Hili Book Company, 1974. ABP(Wo/Q)s 4. Zyerev, Anatoll.: Handbook of Filter Synthesis, John Wiley and Sons, 1967. 5. Temes, GaborC., and Sanjit K. Mitra: Modern Filter Theory and Desig~, John Wiley and Sons, 1973. AHP s' s' + (wo/Q) s + wo' 27r£o. Burr-Brown also manufactures a line of completely selfcontained active filters called the ATF76 series. These are available in most popular transfer functions with from 2- to 8-pole responses. They contain all necessary components and do not require any user design effort. To obtain band reject characteristics the low-pass and high-pass outputs are summed to form a pair of jw axis zeros: T(Band-Reject) s' A (s' + Wo') + (Wo/Q) s + Wo' DESIGN STEPS I. Choose the type offunction (low-pass, bandpass, etc.), type of response (Butterworth, Bessel, etc.), number of poles, and cutoff frequency based on the particular application. If the transfer function is band-reject see Band-Reject Transfer Function before proceeding to step 2. 2. Determine the normalized low-pass filter parameters (fn and Q) based on the type of response and number of poles selected in step I. See Normalized Low-Pass Parameters. 3. If the actual response desired is low-pass go to step 4. For other responses a transformation of variables must be made (low-pass to bandpass or low-pass to high-pass). See Low-Pass Transformation. where ALP = AHP = A. The state variable approach uses two op amp integrators and a summing amplifier to provide simultaneous low·pass, bandpass and high-pass responses. One U AF is required for each two poles of low-pass or high-pass filters and for each pole-pair of bandpass or band-reject filters. DESIGN PROCEDURE SUMMARY These procedures give the design steps for the proper application of a UAF and for the selection of the external components. More detailed information on filter theory pertinent to some of the steps can be found in the reference sources listed in Table I. 5-95 4. Determine the actual (denormalized) cutofffrequency, fo, by mUltiplying fn by the actual desired cutoff frequency. See Denormalization of Parameters. T ABLE II. Low-Pass Filter Parameters. Butterwort~1 Numbe of Pol In(1 5. Pick the desired UAF configuration (noninverting, inverting or bi-quad). See Configuration Selection Guide and UAF Configurations and Design Equations. 2 1.0 0.70711 3 1.0 1.0 1.0 7. Calculate RFI and R F2. S~e Natural Frequency and UAF Configurations and Design Equations. 8. Determine QP. See Qp Procedure. 1.32475 1.44993 0.69104 0.626456 1.066853 1.7062 0.388911 0.941326 2.5516 1.0 0.54118 1.0 1.3065 1.43241 1.60594 0.52193 0.80554 0.597002 0.70511 1.031270 2.9406 0.470711 0.9294 0.963678 4:59366 5 .1.0 1.0 0.61805 1.0 1.61612 1.50470 1.55876 1.75812 0.56354 0.91652 0.~83 1.1778 1.017735 4.5450 0.216308 0.627017 1.77509 0.97579 7.23228 6 1.0 0.51763 1.0 0.70711 1.0 1.93349 1.80653 1.69186 1.90762 0.51032 0.61120 1.0233 0.396229 0.66364 0.788121 1.8104 1.011;148 6.5128 0.31611 0.9016 0.730027 2.84426 0.982828 10.4616 1.0 1.0 ~.55497 1.0 ~.60192 1.0 2.2472 1.88713 1.71911 1.82539 2.05279 0.53235 0.66083 1.1263 0.256170 0.503lI63 1.0916 0.822729 2.5755 1.000022 8.8418 0.155410 0.460853 1.84842 0.797114 4.11507 0.987226 14.2802 ~.50980 1.78143 1.85314 1.95845 2.19237 0.50599 0.55961 0.71085 1.2257 0.296736 0.598874 0.861007 1.00S984 0.237889 0.571925 0.842466 0.990142 - 7 S BAND-REJECT TRANSFER FUNCTION The band-reject is achieved by summing the high-pass and low-pass U AF outputs. Either of the configurations in Figures 2 and 3 can be used to provide the band-reject function if they are used as shown in Figure I. 1.0 1.0 1.0 1.0 0.80134 0.89998 ~.5629 - - 1.23134 0.86372 Q 0.57735 -- 9. Select the desired gain for each UAF and calculate the corresponding Ro and RQ. See Gain (A) and UAF Configurations and Design Equations. n(2) 'n(2) 1.2742 4 6. Decide whether to use design equations "A" or "B". See Design Equations "A" and "B". Chebysev 2dB Ripple 0.5 dB RIpple Bessal fn(1) - 0.362i!20 - 0.67656 1.8107 3.4657 11.5308 0.907227 1.1286 - - 0.89236 2.5327 5.56354 18.8873 1. -3dB frequency. 2. Frequency at which amplitude responae pssaes through the ripple band. TABLE III. Low-Pass Chebyschev Program. The 15kO resistor is adjusted for maximum rejection. The circuit in Figure 3 is applicable when using design .equations "A" (ALP = AHp). When design equations "B" are used (ALP = IOAHP), the resistor at pin 7 must be 10 times the resistor at pin I to obtain equal pass-band gains above and below fn. PI=3.1415926536 COMPLEX P(10) READ5,N. R 5 FORMAT (12,FS.61 A=SQRT(EXP(R/4.3429448)-1.) B=1.1A In either case, the four external U AF resistor~ (Ro, RQ, RFI and R F2) should be calculated for fo and Q of the band-reject filter desired and for ALP to equal the desired pass-band gain. An input constraint is that the input voltage times ABP must not exceed the rated peak-to-peak voltage of the bandpass output, or clipping will result. AN=ALOG(B+SQRT(B"2.1.)) AN=AN/FLOAT(N) J=MOD(N,2)+N/2 DO 10K=1, J RP=SINHIANloSINIPloFLOATI2°K-11/FLOAT 12°NII XIP=COSH(AN)OCOS(PIOFLOAT(2°K-1 )/FLOAT(2°N) I WN=SQRT(Rpoo2+Xlp002) Q~WN/(2°RP) P(K)=CMPLX(WN,Q) IOkn IF(MOD(N,21.NE.0.AND K.EQ.JIGO TO 15 UAFwl1ll F..r External RIIllIDra PRINT 20, P(K) 101m GOT010 15 F=REAL(P(K)) InlHll Slgnll, PRINT 30, F NOTE: Language variations between computers may require modification of this program. 10 CONTINUE 20 FORMAT 12X"FN="E20.S"Q="E20.SI 30 FORMAT 12X"FN = "E20.SI STOP END FIGURE· 1. Band-Reject Configuration. Note that for bandpass and high-pass filters complex conjugate pole pairs in the actual filter correspond to single poles in the normalized low-pass model. Thus four poles in Table II would correspond to four-pole pairs in a bandpass or high-pass filter. NORMALIZED LOW-PASS PARAMETERS Usual active filter design procedure involves using normalized low-pass parameters. Table II is provided to assist in this step for the more common filter responses. Table III is a FORTRAN program which allows fn and Q to be calculated for any desired ripple and number of poles for the Chebyschev response. Program inputs are the number of poles (N) and the peak-to-peak ripple (R). Program outputs are fn and Q, which are used exactly as the values taken from Table II. Filters with an odd number of poles show one fn with no corresponding Q value. This represents a simple RC network that is required for odd pole filters. This RC network with a cutoff frequency equal to fn times the overall filter cutoff frequency shQuld be placed in series with the first U AF two-pole section. An external op amp and RC network can be used for this purpose. 5-96 The cutoff frequency determined by the Table II filter parameters is (I) the -3dB frequency of the Butterworth response and ofthe Bessel response and (2) the frequency at which the amplitude response of the Chebyschev filters passes through the maximum ripple band (to enter the stop band). LOW-PASS TRANSFORMATION Low-Palls to High-Pass The following simple transformation may be used for I high-pass filters: fn (high-pass) = "'nf-:(7'lo-w---p-as-s-c-) Q (high-pass) = Q (low-pass) Low-Pass to Bandpass The low-pass to bandpass transformation to generate fn (bandpass) and Q (bandpass) is much more complicated. It is tedious to do by hand but can be accomplished with the FORTRAN program given in Table IV. This program automates the tranformation s = p/2 ± V(p/2)' - I. TABLE IV. Low-Pass to Bandpass Transformation Program. COMPLEX P.S.U READ 5. FN. O. OBP 5 FORMAT 13F12.51 X~FN/O'2.1 P=CMPLXIX.YI U=CONJGIPI DO 30 1=1.2 S=P/12'OBPI P=S"2-1. T=ATAN2IAIMAGIPI,REALIPII IF IT.GE.O.IGO TO 10 T=2.'3.14159+T 10 T=T/2. A=SORTICABSIPII'COSITI SIMPLIFIED DESIGN EQUATIONS "A" B=SORTICABSIPII'SINITI f,,< 5kHz(UAFII) or SOkHz(UAF21) S=S+CMPLXIA,BI I. R" FN=CABSIS) 2. O=-FN/12.'REALISII = RF2 = 10'1",,,= 1.59 x 10'/[" = QA.,p = QAHP = (2Q, - A.. + I) 1Il"/A.. SIMPLIFIED DESIGN EQUATIONS "B" 4. Ro IFIAIMAGIU).EO.O.)GO TO 40 END AIIP 3. RQ = 11)"1 (2Q, - A .. - I) PRINT 20,FN.O 20 FORMAT 12X"FN="FI2.5"O="FI2.51 40 STOP DENORMALIZATION OF PARAMETERS Table II shows filter parameters Jor many 2- to 8-pole normalized low-pass filters. The Q and the normalized undamped natural frequency. fn for each two-pole section are shown. The Q values do not have to be denormalized and may be used directly as described in the Design Procedure Summary. fn must be denormalized by multiplying it by the desired cutoff frequency of the actual overall filter to obtain the required frequency. L for the design formulas. As an example. consider a 4-pole lowpass Bessel filter with a cutoff frequency of 1000Hz. The first stage would be designed to an foof 1432.41 Hz and a Q of 0.52193 while the second stage would have an fo of 1605.94Hz and Q of 0.80554. To combine the two stages into the composite filter the low-pass output of the first stage (pin 9) would be connected to the input resistors (R G ) of the second stage. CONFIGURATION SELECTION GUIDE It is possible to configure the UAF three different ways. Each configuration produces features that mayor may not be desirable for a specific application. The selection guide in Table V is given to assist in determining the most advantageous configuration for a particular application. UAF CONFIGURATIONS AND DESIGN EQUATIONS Nonlnverting Configuration For applicatiO'l1s requiring a bandpass gain of I V / V. the internal resistor RJ" may be used (input at pin 14) as the gain resistor RG ; thus. o,nly three external resistors are m:eded to configure the filter. To use equations "B" connect an Ilk!} resistor between pins 12 and I. Use equations "B" for frequencies above 8kHz or when RQ from equations "A" becomes a negative value. Y=FN'SORTll.-ll.110'2.11"21 30 P=U would result in the pole positions for a three-pole pair bandpass filter requiring three UAF stages. f,> 5kHz (UAFII) or 50kHz (UAF21) NOTE: Language variations between computers may require modification of this program. I. R" = R., = 3.16 x 10'/",,,= 5.03 x 1O'/f" 2. A.. = Q/3.16 A,., = 3.16Q AM, A., - I) A., + I) 10' I A., 3. RQ = 10'/(3.48Q, - ,Program Inputs I. fn - From Table II for the low-pass filter of interest 2. Q - From Table II 3. QBP - Desired Q of the bandpass filter For filters with an odd number of poles aQ of 0.5 should be used where Q is not given in Table II. Enter lOS for Q when transforming zeros on the imaginary axis. The program transforms each low-pass pole into a bandpass pole pair. Thus a three-pole low-pass input. 4. R" = (3.48Q, - Inverting Configuration SIMPLIFIED DESIGN EQUATIONS "A" f, < 5kHz (UAFII) or 50kHz (UAF21) I. RF. = Rf'2 = I09/ wo = 1.59. x 108/f(l 2. Aep = Q Aut = Q .AHP 3. Ro = 10' Q,I A., 4. RQ = 2 x IIt'f(2Q, + A .. - I) 5-97 NON INVERTING INPUT,' Outputs Availl,ble BP. LPand ,HP BI-QUAD' INVERTING INPUT ' BP. LP and HP BPand LP Inverted Outputs BP HP and LP, BP and LP Q & Gain Independent,Of ' F~equency Resistors? Yes Yes No Type of Q Variation With Changes in RF Constant Q Constant Q Const~nt b~ndwidth Other Advantages, May be use,d with only t~J~e external : Parameter Limitations RG and Ra are small at high frequencies resistors{ use internsl A3 as Ro I 2Qp - ABP >1 (fo < IikHi) 3,48Qp - ABP':> 1 (fO> SkHz) 2Qp + ABP > 1 (fo < 8kHz) 3,4SQp + Asp > 1 (fO> SkHz) None . Summary: The BI-Quail fliter is particularly iJseiul asa bandpass filler if the filter bandwidth must be kept constant as the center frequency is varied. If Q must be kept constant (i.e .• constant Q of a bandpasS or maintaining constant response of a low-pass or high~paSs) one of the other two configurations sho,uld ba used .. The Bi-Quadl\lso has the advantage that RG and Ra are smaller than RG and Ra Of the other two configuratiqns (this is especially useful at high frequencies). The noninverting input configuration has the advantage that for A~p = 1, RG = 100kO; therefore Ra (internall may ba used so that only three external resistors are needed (RF1. RF2. Ra). " o 12 Input Signal Input .;!.--C)+~~~~~~==j----' Slgn>I:..1 He llIOkn "External Ritslltora FIGURE 2. Noninverting Configuration. "External Rlliitora FIGURE 3. Inverting Configuration. SIMPLIFIED DESIGN EQUATIONS"B" [0> 5kHz(UAFII) or 50kHz(UAF21) = RF2 = 3.16 x 108/wo = 5.03 x 10 I..RF' 7 /(" 2,. ABP=Qp/3.16=3.16Qp AHP 3. ,R(; = 3.16 X 104 Qpt A RP . 4. R Q =2x 1()"/(3.48Q,+ARP-I) BI-QUAD Configuration SIMPLIFIED DESIGN EQUATIONS "A" [" < 5kHz (UAHI) or 50kHz (UAF21) = RF1 = I. RI'! FIGURE 4. Bi-Quad Configuration. 109 1w" = 1.59 X 108If" 4_ The values of RFI and RF2 calculated with equations "B" are approximately one-third of.thosecalculated with equations "A". Thus there may be an advantage in using equations "B" at low frequencies. Using equations "B" would require use of one more resistor, but that would not alter or affect filter performance in any manner. S. Using the negative gain values for ALP or AHP or Aop could result in the negative values for resistors RG and RQ. So the absolute value ofthe gain should'always be used in the equations_ 2. Q A 1•p = AI'IP 3. R Q = QPRFI 4. R(; = RQi AHP SIMPLIFIED DESIGN EQUATIONS "B" I:. > 5kH, WAFIIi or 50kH, (lIAF21i I. RFI = RF2 = 3.16 X 108 /tv" = 5.03 x 107/f" 2. Q ALP= Asp 3, RQ = 3.16 Q, R" 4. R(, = RQt Asp Design Equations "A" and "B" I. Forfo below 8kHz, either of equations "A" or:"B" may 6. Under some circumstances the value o~ RQ using equations "A" will be negative. If this occurs,'use design equations' "B". ' be used. 2. For fo above 8kHz, equati~'hS "B" must be, dsed:' it equations" A" were used above 8kHz, the filter "could become unstable. Natural Frequency (fo) I.fo for each one pole-pair bandpass filter is the center frequency (fc).fc is defined as fc= where f1 is the lower -3dB point and fi is the upper: ~3dB point of tlie pole-pair response. v'M 3. Equations "A"are for the UAF as it is suppliefL When using equations "B", a I I ko. resistor must be placed in parallel with R2 (between pins 12 and I). 5-98 AHP - for high-pass output,- gain at high frequencies. 2. Refer to the Typical Performance Curves for full power response. When selecting the gain. insure the limits of the curve are not exceeded for the desired voltage range. 2. To obtain f" below 100Hz using practical resistor values. capacitors may be paralleled with C I and C2 to reduce the size of RFI and RF2. If capacitors are added in parallel. RFI (new) =. RF2 (new) = RFI (old) 1000pF C + 1000pF DETAILED TRANSFER FUNCTION EQUATIONS The following equations show the action of all the internal and external UAF filter components. They are not required for the regular design procedure but could be used if a detailed analysis is required. where R" (new) is the new lower value frequency resistor. C is the value of the two external capacitors placed across CI and C2 (between pins 10 and 3 and pins 8 and 7 and RFI (old) is the value calculated in the simplified design equations. NON INVERTING INPUT CONFIGURATION I. Q-Factor I. For bandpass filters Q 3dB bandwidth 2. When designing low-pass filters of more than two poles. best results will be obtained if the two pole sections with lower Q are followed by the sections with higher Q. This will eliminate any possibility of clipping due to high gain ripple in high Q sections. = R: WI): {RI RII (" R,:C~) 2.Q~ I+(!.!.) (_R'_) 11+IO'Ro l = R,+R: RIo 3. R, = 10' + 10' RI) (10' R,R"C,. N"R,,( + Rd 4. Q A, ,. ~ Q A",. R, R, ~ A",.y"'R"".R,....,.""C(.-,I""R"C.RC",.""'c., 5. AliI' = /0' (2 + 10' R,)l RIo INVERTING INPUT CONFIGURATION l.w,,:=R: (RJRIJCR,~C~) 2. Q ~ R, II + 2 x 10' R,,>V"'R-,,"'"C,"""'I"""R-::,R"',R"'-,.""'.c"',l 3.QA ,1·=QR, All" R:=.AHI'JRIRIICI (R"R"C:) Qp Procedure I. If the "fo times Q" product is greater than 104 (or 10' for the UAF21). it is possible for the measured filter Q to be different from the calculated value of Q. This effect is the result of nonideal characteristics of operational amplifiers. It can be compensated for by introducing the parameter Qp into the design equations. 4. AliI' =JRIR:Rr:C: (R,·,C) Q Rt • S. I RI' == I R, +1 R~ + I Rc. BI-QUAD CONFIGURATION 2. Calculate the fo Q product for the filter. If the product is above 104 Hz (or 10' for the UAF21). locate the corresponding foQp product on the curve in Figure 5. Divide foQp by fo to obtain Qp. Use Qp as indicated in the design equations. For foQ products below 104 Hz (or 10' for the UAF21). Qp = Q. OHset Error Adjustment DC offset errors will be minimized by grounding pin 5 through a resistor equal to 1/2 the value of RFI or RF2. The DC offset adjustment shown here may be used if required. Offset errors will increase with increases in RF. 2 106 9 8 7 6 05 l00ka f'~~' w. · To pin 8 for bandpass output . To pin 10 for low-pass or high-pass output. .24 -S~pply 104LR'" 10· 105 3 4 5 6 7 89105 3 4 5 6 7 89106 Design Example It is desired to design a 5"pole Bessel. Low-Pass Filter with fo = 3.3kHz and ALP = I. We will use the UAFII to implement this filter. From Table II the following values of fo and Q are obtained. Complex Poles: fo = 1.55876] Q =0.56354 fo= 1.75812] Q =0.91652 Simple Pole: fo = 1.50470 UAFll 105 2 UAF21 fo 'May be adjusted for best sensitivity. 3 a FIGURE 5. QpDetermination. GaIn (A) I. The gain (V / V) of each filter section is: ALP - for low-pass output - gain at DC ADP - for bandpass output - gain at fo 5-99 Using the ~bove shoWn values of fo and Q. we now wili proceed ~o "esign the three stages of filter separately. Any one'oflthe three configurations can be used. We will select inverting configuration. For Stage L f" - 3.3kiHz x fo = 3.3kHz x 1.55876 = 5144Hz Since f., l>5kHz. equations "8" would be used. thus an II k!l reSistor must be connected between pins 12 and. I. RFI = Rb ± 5.0;1~107 Since f" >5kHz. equations "8" would again be used. and an II krl resistor would be connected between pins 12 and 1 of the second UAF stage. X 10' - 8669n R'-I- = R F1 = 5.03 5802 f"Q = 5802 x 0.91652 = 5.32 x 10) f"Q ~ 5 , ~ 0 w 400 200 x "LOW Pass 150 ~ 100 0 Band Pass 6 5 4 80 60 50 40 3 2.5 2 30 25 20 High Pass I"!.. 1.5 1 1 2 3 I 4 567810 " 1520 15 10 3040 1 6080100 2 Frequency (kHz) PIGURE 2. Pull Power Response 3 4567810 20 30 40 6080100 Resonant Frequency (kHz) FIGURE 3. Q Max. vs. Resonant Prequency ACTIVE FILTER DESIGN PROCEDURE 4. Calculate Qp asshow~.in the Q factor design notes to compensate for amphfler phase shift errors. 5. Determine the filter configuration that will be used (see configuration selection guide on the opposite page for recommendations). 6. Calculate the resistance values required using the design equations for the filter configuration selected. To design filters using the circuits shown on the following pages, these six design steps should be followed: 1. Determine fo , the natural frequency of the pole pair. 2. Determine A, the gain of the filter section (V/V). 3. Determine the Q factor. NATURAL FREQUENCY (fo) DESIGN NOTES fa values for many low pass and high pass filters are given in the filter parameter table on page 5-107. The equivalent resistance if inserted between pins 1 and liar pins 2 and 8 is fa for each one pole-pair band pass filter is the center frequency (fe). fc is defined as fc = {fif2 when fl is the lower 3 dB point and f2 is the upper 3 dB point of the filter. To use the UAP31 with fa above 8 kHz, an 11 kn resistor must be placed in parallel with R2 (between pins 13 and 11). Par the higher frequencies where an 11 kn resistor is required, use simplified design equations "B". Por operation below these frequencies; use simplified design equations "A" or "B". To obtain fo below 100 Hz using practical resistor values, T-networks may be used for the frequency determining resistors (Rp]andRp2)' R = R~~b + Ra + Rb Capacitors may also be paralleled with C 1 and C2 to reduce the size ofRpl and Rp2.1f capacitors are added in parallel, 1000 pP Rpl(new) = Rp2(new) =Rpl ( old) C'+ 1000pF where Rp{new) are the new lower value frequency resistors, C is the value of the two external capacitors placed across C] and C2 (between pins 1 and 2 and pins 8 and 9), Rp] (old) is the value calculated in the simplified design equations. GAIN (A) DESIGN NOTES The gain (VIV) of the filter section is: ALP - for low pass output - gain at DC. ABP - for band pass output - gain at f o . AHP - for high pass output - gain at high frequencies. 5-104 Q FACTOR DESIGN NOTES For band pass filters Q: 3 dB :~dwidth simply use Q. As can be seen in Figure 4, the amplifier phase shift errors cause Q to rise with increasing foQ products. Q values for many low pass and high pass filters are given in the pole position table on page 5-107. 9 8 7 6 5 A FORTRAN computer program to transform low pass pole positions to band pass pole positions is given on page 5-108. 4 When designing low pass filters of more than two poles, best results will be obtained if the two pole sections with lower Q are followed by the sections with higher Q. This will eliminate any possibility of clipping due to high gain ripple in high Q sections. 3 2 <> 0 ~o ~~ 10 5 9 8 7 6 5 Q repeatability (Q change from unit-to-unit) is typically ±5% at foQ products less than 104 . The Q repeatability error increases as the foQ product increases, to approximately ±20% for foQ products near 106 . 4 3 2 Calculate the fo times Q product of the filter. If the product is above 104 Hz, locate the corresponding foQ p product in Figure 4. Divide foQp by fo to obtain Qp. Use Q p as indicated in the equations on page 5-106 to correct for amplifier phase shift errors. For foQ products below 104 Hz, 104 ,/ L I I 3 2 4 5 6789 10 6 FIGURE 4. Qp Determination NOTE: For more comprehensive detailed design procedure and illustrated examples of filter design using the Universal Active Filt€jrs. please re(er to PDS-3S9, product data sheet for .Burr-Brown model No. UAF41. CONFIGURATION SELECTION GUIDE NON INVERTING INPUT INVERTING INPUT BI·QIiAD Outputs Available BP, LP and HP BP, LP and HP BP and LP Inverted Outputs BP HP and LP BP and LP Frequency Resistors? Ves Ves No Type of Q Variation With Changes in RF Constant Q Constant Q Constant bandwidth Q & Gain Independent of Other Advantages May be used with only three external resistors (use internal RG and RQ are small at high fceq uencies R3 as R G ) Parameter Limitations Summary: 2 Q p • ABP > I (fo < 8 kHz) 3.48 Q p - ABP > I (fo> 8 kHz) 2 Q p + ABP > 1 (fo < 8 kHz) 3.48 Qp + ABP > 1 (fo > 8 kHz) NONE The Bi-Quad filter is particularly useful as a bandpass filter if the filter bandwidth must be kept constant as the center frequency is varied. If Q must be kept constant (i.e., constant Q of a band pass or maintaining a constant response of a lowpass or highpass) one of the other two configurations should be used. The Bi-Quad also has the advantage that RG and RQ are smaller than RG and RQ of the other two configurations (this ,is especially useful at high frequencies). The noninv~r:ting input configuration has the advantage that for ABP = 1, RG = 100 k therefore R3 (internal) may be used so that only three external resistors are needed (RF!, RF2, RQ). 5-105 1I0NINVERTING INPUT CONFIGURATION For application. requirin~ a band paaa gain of I (V/V), the internal resistor R3 may be used (input at pin 14) as the gain resistor RG' Thus only three external resistors are needed to configure the filter. • To use equations "B" connect an 11 k resistor between pins 11 and 13. Equations "B" are also valid for frequencies below 8 kHz. SIMPUFIED DESIGN EQUATiONS "A" 11 f o <8kHz 109 1.592 x 10 8 1. RFI == RF2 =~ == - - ' . - - t--tt-:---+--<:J 9 2. ABP=QALP=QAHP 10' Q Op 3. RG= A BP 4. RQ= L.P. 10' A Q 2QP-T- 1 S1MPUFIl:lD DESIGN EQUATIONS "8" f o >8kfiz ~F2 = V'I'tI"x I. RFt == 108 == 5.033 2. x 10 7 fo Wo ABP=~AlP=3.16QAHP 3.RG=~ A DP * External Op 10' •• R Q =3.48 Qp _ A BP Qp/Q _ I Resistors INVERTING INPUt CONFIGURATION SIMPUFIED DESIGN EQUATIONS "A" 11 < 8 kHz fa 109 I. R.'I = RF2 =:;:; 2. A DP == Qp ALP 1.592 x lOB == - - ' - , . - - 9 =Op AUp G L.P. Input = lOS Op 3. R Signal ADP 10' 4. RQ =2Qp+ABP_1 S1MPUFIED DESIGN EQUATIONS "8" 14 fo;ilo 8 kHz R I. .'I=R F2 = 2. ADP = 3 R • V'i'O~ IO~ 5.033 x 10' ~ == -,- ' . - - N/C lOOk ~~6 ALP = 3.16 Qp AHP * External = 3.16. 104Qp G ADP Resistors = ~I,,:O'-::-::,---,-_ _ •. R Q 3.48Qp+AOp-l BI-QUAD CONFIGURATION SIMPUFIED DESIGN EQUATIONS "A" < 8 kHz =~ = 1.592 x fo I. RFI = RF2 Wo 10 8 fo 2. ABP= Q ALP 3. RQ= ~P RFt •• RG=~ A BP SIMPUFIEP DESIGN EQUATiONS "8" f o >8kHz I. RF'l = RF2 == ~x lOS == Wo 5.033 x 107 fo 2. ABP = 3.16 Q ALP 3. RQ = 3.16 Qp R~l •• * External Resistors RG=~ ABP 5-106 BAND REJECT The band reject configuration is achieved by summing the high pass and low pass UAF outputs. The circuits shown in Figures 5 and 6 can be used to provide the band reject function if they are connected as shown in Figure 8. The Figure 8 circuit is applicable when using simplified design equations "A" (ALP =AHP), but when operating with an 11 kn resistor between pins 13 and 11 (AU> =10 AHP), the resistor at pin 9 must be 10 times the resistor at pin 11 to obtain equal passband gains above and below fo . passband gain. An input constraint: the input voltage times ABP must not exceed the rated peak·to-peak output voltage of the band pass output, or clipping and distortion will result. In either case, the four exte,rnal UAF resistors (RG, RQ, RFI and RF2) should be calculated for fo and Q of the band reject filter desired and for ALP to equal the desired Uncommitted Amp HP 11 9 10 k.l1 i-7--(J=.-I UAF with External Resistors Band Reject ·Output 5 6 10 k.l1 FIGURE 8. Band Reject Output FILTER PARAMETERS LOW PASS AND HIGH PASS Table I shows filter parameters for many 2 to 8 pole low pass filters. The Q and the normalized undamped natural frequency, fn, for each two-pole section are sho,¥n. The Q values should be used with Figure 4 and in the design formulas on page 5-106 and fn must be multlplied by the desired cutofffrequency of the overall filter to obtain the required frequency, fo, for the design formulas. As an example, consider a 4-pole low pass Bessel filter with a cutoff frequency of 1000Hz. The first stage would be designed to an fo of 1432.41 Hz and a Q of 0.52193 while the second stage would have an fo of 1605.94Hz and a Q of 0.80554. The low pass output of the first stage (pin 9) should be connected to the input resistor (Ra) of the second stage. Filters with an odd number of poles show one fn with no corresponding Q value. This represents the simple RC network that is required for odd pole filters. This RC network with a cutoff frequency equal to fn times the overall filter cutoff frequency should be placed in series with the first UAF two-pOle section. The uncommitted internal op amp should be used as a buffer to isolate the RC network so that the UAF input resistor will not affect the cutoff frequency of the RC network. The cutoff frequency determined by the Table 1,filter parameters is (1) the 3 dB frequency of the Butterworth response and of the Bessel response and (2) the frequency at which the amplitude response of the Chebyschev filtets passes through the maximum ripple band and enters the stop band. To obtain high pass pole positions, the low pass to high pass transformation may be used: i (high pass) = ,......,...1"--_-:n fn (low pass) Q (high pass) The lOW pass to band pass transformation is much more com· plicated, but it can be done using the low pass to band pass conversi~n program (Table III). ' CHEBYSCHEV NUMBER OF POLES BUTTERWORTH Q fn BESSEL In = Q (low pass) Q 0.5 dB RIPPLE fn 2 dB RIPPLE Q In Q 2 1.0 0.70711 1.2742 0.57735 1.23134 0.B.6372 0.907227 1.1286 3 1.0 1.0 ._------- ----------0.69104 0.626456 1.068853 ------------- 1.0 1.32475 1.44993 1.7062 0.368911 0.1141326 2.5516 4 1.0 1.0 0.54118 1.3065 1.4324', 1.60594 0.52193 0.80554 0.597002 1.031270 0.7051; 2.9406 0:470711 0.963678 0.9294 4.59388 1.0 1.0 1.0 -----------0.61805 1.61812 1.50470 1.55876 1.75812 ------------- 5 0.56354 0.91652 0.362320 0.690483 1.017735 1.1778 4.5450 0.218308 0.627017 0.97579 1.77509 7.23228 6 1.0 1.0 1.0 0.51763 0.70711 1.933,49 1.60653 1.69186 1.90782 0.51032 0.61120 1.0233 0.396229 0.768121 1.011446 0.68364 1.8104 6:5128 0.31611 0.730027 0.982828 0.9016 2.84426 ------------- 1.0916 2.5755 8.8418 0.155410 0.460853 0.797114 0.987226 ------------ 0.53235 0.66083 1.1263 0.2p6170 0.503863' 0.822729, 1.008022 ------------- 0.55497 0.80192 2.2472 1.68713 1.71911 1.82539 2.05279 ------------- 7 1.0 1.0 1.0 1.0 1.64642 4.11507 14.2802 8 1.0 1.0 1.0 1.0 0.50980 0.60134 0.89998 2.5629 1.78143 1.83514 ,1.95645 2.19237 0.50599 0.55961 0.71085 1.2257 0.296736 0.598874 0.C61OO7 1.005984 0.67657 1.6107 3.4657 11.5305 0.237699 0:571925 0.842486 0.990142 0.89236 2.5327 5.58354 18.6873 TABLE 1. Low Pass Filter Parameters 5-107 . -------- ---------- 10~4616' COMPLEX P,S,U READ 5, FN, Q, QBP FORMAT (3FI2.5) . Y=FN*SQRT(I.-(I./(Q*2.»**2) X=-FN/(Q*2.)· .P=CMPLX(X,Y) U=CONJG(P) DO 30 1=1,2 S=P/(2. *QBP) P=S*·2-1. T=Al'AN2(AIMAG(P),REAL(P» IF(l'.GF.O.) GO TO 10 LOW PASS CHEBYSCHEV Table' II d~taiIs a FORTRAN program to' determine fn and Q for '8 ChebYSchev low pass filter. The only inputs are, the number of poles and the ,pea~ to pe~k ripple JdB) of the d.sire~ filter. l'he program outputs are treated exactly as the values on the pole position table (Table I). req~ired BAND PASS l'able 111 details a FORTRAN program that may b. used to transform low pass pote positions into the equivalent band pass pole positions., Program Inputs: 1. f n - From Table I for the low pass filter of interest. 2. Q From Table I. 3. QBP-Desired Q of the band pass filter. TABLE In. Low Pass to Band Pass Transformation Program For filters with an odd number of poles a Q of .5 should be used where Q is not given in Table I. The program tra~sforms each low pass pole into a band pass pole pair. That is. using the two:pole low pass pole pOsitions would result in the pole positions for a two pole pair. band pass filter, requiring two UAF stages. Enter 10 6 for Q when transforming zeros on the imaginary axis. This program automates the transformation s = p/2 ± (P/2)LI. DETAILED TRANSFER FUNCTION EQUATIONS The following eq~atio~s sh'ow.the action of al~ the internal and external UAF31 filter components. They should be used if a detailed analysis, not covered in the simplified equations, is required. NONINVERTING INPUT CONfltiURATION I ""01 _ . ;Rl -lfIlfFi~ l+at.I(RG+RQ) -.ro:~(Rl RFt CI) Y.. I+R2 lfj~ 1. Q.. T,' 3. Q-ALP:: Q PI=3.14IS926S36 COMPLEX P(IO) READ S,N,R S FORMAl'(12,FS.6) A=SQRl'(EXP(R/4.342944S)-I.) fFl./A AN=ALOG(B+SQRT(B··2+1.» AN=AN/FLOAT(N) J=MOD(N,2)+N/2 DO 10 K=I,J RI>.=SINH(AN)*SIN(PI*FLOAl'(2*K-I)/FLOAT(2*N» XIP=COSH(AN)*COS(PI*FLOAT(2*K-I)/FLOAT(2*N» WN=SQRl'(RP**2+XIP*'*2) Q=-WNI(2.*RP) P(K)=CMPLX(WN,Q) IF(MOD(N,2).NE.0 .AND.K.EQ.S} GO TO 15 PRINl' 20,P(K) GO 1"0 10 IS F=REAL(P(K» PRINl' 30,F 10 CONTINUE 20 FORMAT(2X"FN="E20.S" Q = "E20.S) 30 FORMAT(2X"FN="E20.8) Sl'OP END 1" 1, F2 RG(Jo+iQ+~) 1 ~ 5. ,,"p:: ALP - +;r RO (~ + ..!... + ..!.) RG 6. ASp 1 +!L R:z = ~ RQ ~ INVERnlS INPUT CONflGURAnON 1. ""0 1 .. il 1Ft ::1 Cl Cl 1. Q = (1 + ... X "IQ Ii + -.iI + Jo) ( 3. Q ALP = Q AIlP. (:;, = ABP ~:! RFI Rl RJ c. Va R:Fl Cl) ::! ~!)Va .:' fo Accuracy(2). max 0.001 to 25 kHz ±1% ±0.002%/oC 0.5-500 fo Stability(3) Q Range (4) Q Stability(S) @fo Q .; 104 @fo Q .;; 105 Q Repeatability at fQ Q .; 105 ±O.OI%/oC ±0.02S%/oC ±lO% 0.1 to SOV/V Gain Range + (0.140") OUTPUT Peak to Peak Output Swing(6) Output Offset (7) 20V (at L.P. output with unity gain) Output Impedance ±20mV I n 200 IlV (rms) 5 rnA Noise(8) Output Current(9) Offset Voltage Bias Current Impedance Signal Voltage Gain ±IS V ±Sto±18V I 17.62m~ ROW SPACING - 7.63mm (0.300") WEIGHT - I.lgms max CONNECTOR - 14 pin DIP connector 7 rnA TEMPERATURE RANGE Pin material and plating composition conform to method 2003 (solderability) -25 to +8S o C -25 to +8S o C (1) For noninverting input configuration with ABP = 1. (2) The tolerance of external frequency determining resistors must be added to this figure. (3) T.C.R. of external frequency determining resistors must be added to this figure. (4) See Figure 3 for Qmax vs F curve. (5) Q stability varies with both the value of Q and the resonant frequency f o ' (6) See Figure 1 for full power response curve. < 100kn at 2.S4mm (0.100") (.300") Power Supply Range 10) Storage Temperature Range 0.457mm (0.018") min. Rated Power SuPPliet Specification Temperature Range -l 1_ <.ooa") --I- POWER SUPPLIES Supply Current@±ISV(Quiescent).max I -11- ,_ R 5 mV 40 nA I Mn 85 dB 5 rnA Output Current r-- ----.- Non cumulative UNCOMMITTED AMP CHARACTERISTICS Input Input Input Large ~ (.;.~if~max 3.S6mm - - - (7) RFi = RF2 (8) Measured at the band pass output with Q of·MIL-STD-883 (except paragraph 3.2) PIN CONNECTIONS L.P. output with unity gain. @ 50 over DC to 50 kHz. (9) The current required to drive RFl and RF2 (external) as well as C 1 and C 2 must come from this current. (10) For supplies below ±lOV, Qmax will deCl'ease slightly; filters will operate below ±SV. 5-111 Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin I2345678910 II 12 13 14 - Low Pass Output Filter Input 3 Filter Input 2 Auxiliary Amp + Input Auxiliary Amp - Input Auxiliary Amp Output Band Pass Output Frequency Adjust Negative Supply Positive Supply Common Filter Input I High Pass Output Frequency Adjust DESIGN PROCEDURE SUMMARY TYPICAL PERFORMANCE CURVES '00 ,.,HIGH PA.SS Ii ~i This summary gives the design steps for the proper application of UAF41s and for the selection of the external components. More detailed information on filter theory pertinent to some of the steps can be found in the reference sources listed under USEFUL REFERENCES. Burr-Brown also manufactures a line of completely selfcontained active filters called the ATF76 series. These are available in most popular transfer functions with from 2 to 8 pole responses. They contain all necessary components and do not require any user design effort. DESIGN STEPS: I. Choose the type of transfer function (low pass, band pass, etc.), type of response (Butterworth, Bessel, etc.), number of poles, and cutoff frequency based on the particular application. Frequency (kHz) ·If Equations "S" used below 8 kHz. ,oooFIGURE 2. Full Power Response. If the transfer function is band reject see BAND REJECT TRANSFER FUNCTION, before proceeding to step 2. 2. Determine the normalized low pass filter parameters (fn and Q) based on the type of response and number of poles selected in step 1. See NORMALIZED LOW PASS PARAMETERS. 3. If the actual response desired is low pass go to step 4. For other responses a transformation of variables must be made (low pass to band pass or low pass to high pass). See LOW PASS TRANSFORMATION. ~'~1-+-~~+H++~-+-+~-H+H++~ ~'~1-+-~~+H++~-+-+~~+H++~ "1-+-+-H-++++++++~-+-+~---l-lIl+f++~ 40 so 60 100 Resonant Frequency (kHl.) ,,,. FIGURE 3. Q Max vs Resonant Frequency. , 7 • , "/1/. EQNS-'- /.11' , 6 .... 5. Pick the desired UAF configuration (noninverting, inverting or bi-quad) see CONFIGURATION SELECTION GUIDE, and UAF41 CONFIGURATIONS AND DESIGN EQUATIONS . I I ~Nsl_.- 8 , II' , v 10 V I ~ i I 1I I I !I I , , f.. , , 4. Determine the actual (denormalized) cutoff frequency, fo , by mUltiplying fn by the actual desired cutoff frequency. See DENORMALIZATION OF PARAMETERS. .I 7 8910' 6. Decide whether to use design equations "A" or "B". See DESIGN EQUATIONS "A" AND "B". 7. Calculate RFI and R F2 • See NATURAL FREQUENCY, and UAF CONFIGURATIONS AND DESIGN EQUATIONS. 8. Determine QP. See Qp PROCEDURE. 9. Select the desired gain for each UAF and calculate the corresponding RGand R Q • See GAIN (A), and UAF41 CONFIGURATIONS AND DESIGN EQUATIONS. Q FIGURE 4. Qp Determination 5-112 NORMALIZED LOW PASS PARAMETERS Filters with an odd number of poles show one fn with no corresponding Q value. This represents a simple RC network that is required for odd pole filters. This R C network with a cutoff frequency equal to fn times the overall filter cutoff frequency should be placed in series with the first UAF two-pole section. The uncommitted internal op amp with an external RC network can be used for this purpose. The cutoff frequency determined by the Table I filter parameters is (I) the -3dB frequency of the Butterworth response and of the Bessel response and (2) the frequency at which the amplitude response of the Chebyschev filters passes through the maximum ripple band (to enter the stop band). Usual active filter design procedure involves using normalized low pass parameters. Table I is provided to assist in this step for the more common filter responses. Table II is a FORTRAN program which allows fn and Q to be calculated for any desired ripple and number of poles for the Chebyschev response. Consult the USEFUL REFERENCES for other information. Note that for band pass and high pass filters complex conjugate pole pairs in the actual filter correspond to single poles in the normalized low pass model. Thus four poles in Table I would correspond to four pole pairs in a band pass or high pass filter. CHEBYSCHEV NUMBER OF POLES 2 1.0 3 1.0 4 5 6 7 8 0.70711 1.32475 0.626456 0.368911 1.0 1.0 1.44993 0.69104 1.068853 1.0 0.54118 1.43241 0.52193 0.597002 0.70511 1.0 1.3065 1.60594 0.80554 1.031270 2.9406 0.470711 0.9294 0.963678 4.59388 0.362320 0.218308 1.0 0.61805 1.55876 0.56354 0.690483 0.627017 1.77509 1.0 1.61812 1.75812 0.91652 1.017735 4.5450 0.97579 7.23228 1.0 0.51763 1.60653 0.51032 0.396229 0.68364 0.31611 0.9016 1.0 0.70711 1.69186 0.61120 0.768121 1.8104 0.730027 2.84426 1.0 1.93349 1.90782 1.0233 1.011446 6.5128 0.982828 10.4616 0.256170 0.155410 1.0 1.50470 1.0 1.68713 1.7062 1.1778 0.941326 2.5516 1.0 0.55497 1.71911 0.53235 0.503863 1.0 0.80192 1.82539 0.66083 0.822729 2.5755 0.797114 4.11507 1.0 2.2472 2.05279 1.1263 1.008022 8.8418 0.987226 1.0 0.50980 1.78143 0.50599 0.296736 0.67657 0.237699 0.89236 1.0 0.60134 1.83514 0.55961 0.598874 1.6107 0.571925 2.5327 1.0 0.89998 1.95645 0.71085 0.861007 3.4657 0.842486 5.58354. 1.0 2.5629 2.1 9237 1.2257 1.005984 0.990142 18.6873 (1) -3 dB Frequency (2) Frequency at which amplitude response passes through the ripple band. TABLE I. Low Pass Filter Parameters. 5-113 1.0916 11.5305 0.460853 1.64642 14.2802 NORMALIZED LOW PASS CHEBYSCHEV Table II gives a FORTRAN program for the determination of fn and Q for a general normalized Chebyschev low pass filter of any ripple and number of poles. Program inputs are the number of poles (N) and the peak-la-peak ripple (R). Program outputs are fn and Q, which are used exactly as the values taken from Table I. PI=3.14 I 5926536 COMPLEX P(IO) READ 5,N.R 5 FORMAT (12, FS, 6) A=SQRT (EXP(R/4.342944S)-I) B=1./A AN=ALOG(B+SQRT(B'*2+I,» 10kn AN=AN/FLOAT(N) J=MOD(N,2)+N/2 DO 10 K=I, J RP=SINH(AN)*SIN (PI *FLOAT(2 *K-I )/FLOA T(2 ON» FIGURE 5. Band Reject Configuration. XIP=COSH(AN)*COS(PI *FLOAT(2 *K-I )/FLOAT(2 *N» WN=SQRT(RP*'2+XIP'*2) Q=-WN/(2. *RP) OFFSET ERROR ADJUSTMENT· P(K)=CMPLX(WN ,Q) DC offset errors will be minimized by grounding pin 3 through a resistor equal to 1/2 the value of RFI or RF20 The DC offset adjustment shown here may be used if required. Offset errors will increase with increases in RF. IF(MOD(N,2).NE.0 AND.K.E Q.J)GO TO 15 PRINT 20, P(K) GO TO 10 15 F=REAL(P(K» PRINT 30, F + Supply 10 CONTINUE 20 FORMAT(2X"FN="E20.S"Q="E20.S) 1 MO· 30 FORMAT(2X"FN="E20.S) 100 k STOP ~-.-----"NI\r.-----."~ to. pin 14 for band pass output to pin 8 for low pass or high pass output. END Supply TABLE II. Low Pass Chebyschev Program - • May be adiusted for best sensitivity. LOW PASS TRANSFORMATION BAND REJECT TRANSFER FUNCTION The band reject is achieved by summing the high pass and low pass UAF outputs. Either of the configurations in Figures 6 and 7 can be used to provide the band reject function if they. are used as shown in Figure 5. The 15kO resistor is adjusted for maximum rejection. The circuit in Figure 5 is applicable when using design equations "A" (ALP = AHP). When design equations "B" are used (ALP = IOAHP), the resistor at pin I must be 10 times the resistor at pin 13 to obtain equal pass band gains above and below fn. LOW PASS TO HIGH PASS The following simple transformation may be used for high pass filters: fn (high pass) =- - - fn (low pass) Q (high pass) = Q (low pass) LOW PASS TO BAND PASS In either case, the four external UAF resistors (RG, RQ , RFI and RF2 ) should be calculated for fo and Q ofthe band reject filter desired and for ALP to equal the desired passband gain. An input constraint is that the input voltage times ABP must not exceed the rated peak-to-peak voltage of the band pass output, or clipping will result. The low pass to band pass transformation to generate fn (band pass) and Q (band pass) is much more complicated. It is tedious to do by hand but can be accomplished with the FORTRAN program given in Table III. This program automates the transformation s = p/2 5-114 ±~(P/2)' - I. DESIGN EQUATIONS "A" AND "B" I. For fo below 8 kHz, either of equations "A" or "B" may be used. COMPLEX P,S,U READ 5, FN, Q, QBP 5 FORMAT (3FI2.5) Y=FN*SQRT(I.-(I./(Q*2.»**2) X=-FN/(Q*2) P=CMPLX(X,Y) U=CONJG(P) DO 30 1=1,2 S=P/(2. *QBP) 2. For fo above 8 kHz, equations "B" must be used. If equations "A" were used above 8 kHz, the filter could become unstable. p.;::S"'*2-1. 10 20 30 40 3. Equations "A" areforthe UAF as it is supplied. When using equations "B", a S.49kO resistor must be placed in parallel with R2 (between pins 12 and 13). T=AT AN2(AIMAG(P),REAL(P» IF(T.GE.O) GO TO 10 T=2.*3.14159+T T=T/2 A=SQRT(CABS(P»*COS(T) B=SQRT(CABS(P»*SIN(T) S=S+CMPLX(A,B) FN=CABS(S) Q=-FN/(2.*REAL(S» PRINT 20, FN,Q FORMAT (2X"FN = "FI2.5" Q = "FI2.5) IF(AIMAG(U).EQ.O) GO TO 40 P=U STOP END 4. The values of RFI and RF2 calculated with equations "B" are approximately one-third of those calculated with equations "A". Thus there may bean advantage in using equation "B" at low frequencies. Using equation "B" would require use of one more resistor, but that would not alter or affect filter performance in any manner. S. Using the negative gain values for ALP or AHP or ABP could result in the negative values for resistors RG and RQ. So the absolute value of the gain should always be used in the equations. TABLE III. Low Pass to Band Pass Transformation Program PROGRAM INPUTS: GAIN' (A) I. fn - From Table I for the low pass filter of interest 2. Q - From Table I 3. QBP - Desired Q of the band pass filter I. The gain (V / V) of each filter section is: ALP - for low pass output - gain at DC ABP - for. band pass output - gain at fo AHP - for high pass output - gain at high frequencies. For filters with an odd number of poles a Q of 0.5 should be used where Q is not given in Table I. Enter lOs for Q when transforming zeros on the imaginary axis. 2. Refer to Figure 2 for full power response. When selecting the gain, insure that the limits of the curve are not exceeded for the desired voltage range. The program transforms each low pass pole into a band pass pole pair. Thus a three-pole low pass input, would result in the pole positions for a three pole pair band pass filter requiring three UAF stages. NATURAL FREQUENCY (fo) I. fo for each one pole-pair band pass filter is the center frequency (fe). fe is defined as fe = ~ where f, is the lower -3 dB point and f2 is the upper -3 dB point of the pole pair response: DENORMALIZATION OF PARAMETERS Table I shows filter parameters for many 2 to 8 pole normalized low pass filters. The Q and the normalized undamped natural frequency, fn for each two-pole section are shown. The Q values do not have to be denormalized and may be used directly as described in the DESIGN PROCEDURE SUMMARY. fn must be denormalized by mUltiplying it by the desired cutoff frequency of the actual overall filter to obtain the required frequency, fo for the design formulas. As an example, consider a 4-pole low pass Bessel filter with a cutoff frequency of 1000Hz. The first stage would be designed to an fo of 1432.41 Hz and a Q of 0.S2193 while the second stage would have an fo of 160S.94 Hz and a Q ofO.80SS4. To combine the two stages into the composite filter the low pass output of the first stage (pin I) would be connected to the input resistors (Ra) of the second stage. 2. To obtain fo below 100 Hz using practical resistor values, capacitors may be paralleled with C , and C2 to reduce the size of RFI and RF2. If capacitors are added in parallel, Rei (new) = RF2 (new) = RFI 1000 pF (old) C + 1000 pF where RF (new) is the new lower value frequency resistor, C is the value of the two external capacito[s placed across C , and C2 (between pins 7 and 8 and pins I and 14 and R~, (old) is the value calculated in the simplified design equations. 5-115 Q" PROCEDURE Q-FACTOR fo ----.,-I. For band pass filters Q = 3 dB bandwidth. I. If the "fo times Q" product is greater than lOs, it is , possible for the measured filter Q to be different from the calculated value of Q . This effect is the result of non-ideal characteristics of operatiopal amplifiers. It can be compensated for by introducing the parameter Qp into the design equations. 2. When designing low pass filters of more than two poles, best results will be obtained if the two pole sections with lower Q are followed by the sections with higher Q. This will eliminate any possibility of clipping due to high gain ripple in high Q sections. 3. Q repeatability (Q change from unit-to-unit) is typically ±5% for foQ products less than 104 • The Q repeatability error increases as the foQ product increases to approximately ± I 0% for foQ products near 2. Calculate the foQ product for the filter. If the product is above lOS Hz, locate the corresponding foQp product in Figure 4. Divide foQp by fo to obtain Qp. Use Qp as indicated in the design equations. For foQ products below lOS Hz, Qp = Q. lOS. CONFIGURATION SELECTION GUIDE It is, possible to configure the U AF41 three different ways. Each configuration produces features that mayor may not be desirable for a specific application. This selection guide is given to assist in determining the Il}ost advantageous configuration for a particular application. NONINVERTING INPUT INVERTING INPUT BIQUAD Outputs Available BP, LP and HP BP, LP and HP BP and LP Outputs Inverted with respect to the Input BP HP and LP BP and LP Q & Gain Independent of Frequency Resistors? Yes Yes No Type of Q Variation With Changes in RF Constant Q Constant Q Constant Bandwidth Other Advantages May eliminate one external resistor (use internal R3 as %) Parameter Limitations 2 Qp - ABP> I (Eqns. "A") 3.48 Qp - ABP> 1 (Eqns. "B") % Ro and are small at high frequencies 2 Qp + ABP > 1 (Eqns. "A") 3.48 Qp + ABP> 1 (Eqns. "B") NoHP Output Summary: The Bi-Quad filter is particularly useful as a band pass filter if the filter bandwidth must be kept constant as the center frequency is varied. If Q must be kept con-tant (i.e., constant Q of a band pass or maintaining a constant response of a low pass or high pass) one of the other two configurations should be used. The Bi-Quad also has the advantage that RG and RQ are smaller tha'!! with the other two configurations (this is especially useful at high frequencies). The noninvertlng input configuration has the advantage that for ABP = 1, ~ = 50k.Q; therefore R3 (internal) may be used so that only three external resistors are needed (RF 1, RF2, RQ). 5-116 UAF41 CONFIGURATIONS AND DESIGN EQUATIONS NONINVERTING INPUT CONFIGURATION SIMPLIFIED DESIGN BQUATIONS "A" 109 I. RFl = RFl SOk 1.592 X 10 8 =W;=--'.-- 5.0 X 104 Q 3. RG = AB,Op 4. RQ= 5.0x 104 A Q B~ lQp- '_1 SIMPLIFIED DESIGN EQUATIONS "8" Must be used (Of fO ;;;. f 8 kHz .jiOx 10 8 5.033 x 10 7 J. RI'! = RF2 : - - " , - . - " - , - . - Q 2. ASP="3.i6ALP=J,16QAHP 5.0x 1040 3. RG= "B'Op 4. RQ " --..::;.:=-=-5.0x 104 3.48Qp _ AD; Op _ I FIGURE 6. Noninverting Input Configuration. INVERTING INPUT CONFIGURATION SIMPLIFIEn DESIGN EQUAnONS "A" 10' 1.592 x lOB I. RFI :::; RFl "'W;= - - ' . - - 2. ABP '" Op ALP = Op AHP 3. He '" 5.0:1. 104 Op A BP 4.R=~ Q L.P. 20p· ABP-I SIMPLIFIED DESIGN EQUATIONS "a" t MUll be used for fo ;;ao 8 kHz ../10 x 10' _ 5.033 x 10 =--:;:--,-.-7 1. RFi'" Rn Op * External Resistors 2. ABP"'""l.i"6ALP= J.16Qp A HP -- 4. RQ "'J.48Qp+A BP-1 FIGURE 7. Inverting Input Configuration. BI-QUAD CONFIGURATION SIMPLIFIED DESIGN EQUATIONS "A" R .• F2 109 1.592 x 10· I. RF1=Rn=W;=-,-.-- 7 3.RQ =Q p R FI RQ L.P. 4. RC=ABP SIMPLIFIED DESIGN EQUATIONS "8" t Must be used for fo ;;;. 8 kHz .JiG x 10 8 5.033 x 107 I. RFI=RF1=~=-,-.-- 11 2. A BP =3.16QA LP * External Resistors FIGURE 8. Bi·Quad Configuration. t To use equations "8" connect a 5.49k resistor between pins 12 and 13. Equations "B" are also valid for frequencies below 8kHz. 5-117 - DETAILED TRANSFE~R'FUNCTION EQUATIONS The following equations show the action of all the internal and external U AF41 filter components. They are not required for regular design procedure, but could be used if a detailed analysis is. required. NONINVERTING INPUTj:ONFIGURATION INVERTING INPUT CONFIGURATION BI·QUAD CONFIGURATION 2. Q= R Q C2 '-"0 QA LP 3. ASp RQ =Wo RF2 C 2 =- ACTIVE FILTER DESIGN EXAMPLES USING THE DESIGN PROCEDURE OUTLINED IN DESIGN STEPS SECTION. Example I. It is desired to design a 3 pole, 0.5d8 ripple, Chebyschev High Pass Filter; the cut off frequency f. = 2 kHz, Gain A HP = +1. fn(high pass) = t (I I ) , QHP = QLP n ow pass . :. For Complex Poles: Step I. The type of transfer function (high pass), the type of response (Chebyschev), number of poles (3), and the cut off frequency (fe) are chosen depending upon the particular application and are stated in the example. Step 2. Normalized low pass filter parameters fn and Q are obtained from Table I (or from progr~m shown in Table II). Complex Poles: I fn = 1.068853 = 0.935582 and Q = 1.7062 For Simple Pole: fn = 0.62~56 = 1.596281 Step 4. Now, determine the actual (denormalized) frequency. fo ;= f. x fn = 2 kHz x 0.935582 = 1871.2 Hz . Step 5. fn ;= 1.068853] Q =1.7062 Simple Pole: fn = 0.626456 Refer to the CONFIGURATION SELECTION GUIDE. Since the gain required is positive, the HP output is not inverted with respect to the input. Therefore, the noninverting input configuration must be selected. Note that the HP output is not available with the Bi-Quad Step 3: Now, since the actual response desired is high pass,the low pass to high pass transformation must be made as shown in LOW PASS TRANSFORMATION. configuratio~. Step 6. Since fo 5-11S < 8 kHz, Equations "A" would be used. Step 7. For the Complex Poles Stage of the filter, using the equations "A", RFI = RF2 = 1.592 x 108 1871.2 = 85.08 kn Step 8. fo Q = 1871.2 x 1.7062 = 3.19 x 103 :. fo Q < 105 :. Qp = Q = 1.7062 Step 9. ABP = Qp X AHP = I. 7062 x I = 1.7062 RG = 5.0 x 104 X 1.7062 1.7062 x 1.7062 = 29.3 kn 5.0 x 104 RQ = 2 x 1.7062 _ 1.7062 _ I = 70.8kn The above obtained resistor values are for the complex pole pair of the first stage of the required active filter. The simple pole obtained as outlined below, using the uncommitted op amp in the UAF41 makes the second stage of the required filter. For the simple pole fn was obtained in the step 3. fn = 1.596281 The actual (denormalized) frequency = fc x fn = 2 kHz x 1.596281 = 3192.6 Hz Example 2. It is desired to design a 4 pole Butterworth, Band Pass Filter, with Q = 25, fc = 19 kHz and ABP = I. Using the computer program shown in Table III, the following values of fn and Q are obtained. fo = 1.0142435 , Q = 35.36541 and fo = 0.9859565 , Q = 35.35886 Using the above shown values of Q and fn, we now will proceed to design the two stages of filter separately. Anyone of the three configurations shown in the CONFIGURATION SELECTION GUIDE can be used. We will select the noninverting input configuration. For Stage I fo = 19 kHz x fo = 19 kHz x 1.0142435 = 19270.6 Hz Since fo > 8 kHz, equations "B" would be used. RFI = RF2 = 5.033 x 10' 19270.6 = 2.6118 kO foQ = 19270.6 x 35.36541 = 6.815136 x 105 Since foQ > 105, locate the corresponding foQp from Figure 4. . Divide foQp by fo to obtain Qp. Thus Qp = 48.78 _ 5.0 x 104 x 35.36541 _ 2 " RG I x 48.78 - 36. 5ku I Now, f = 21T RC R = :.RC=_I_= =4.9851 x 10- 5 21T f 21T x 3192.6 Q 5.0 X 104 4L78 3.48 x 48.78 - 35.37 -I For Stage 2. Following the same procedure as shown for Stage above, the values shown below are obtained. fo Q = 6.624 X 105, Using Figure 4, Qp = 48.04 RFI = RF2 = 2.6867 kO RG = 36.8 kn and RQ = 303.4 n The overall circuit for the required filte~ is shown below. Choosing C = 2200 pF (or any convenient value), R = 4.9851 X 10- 5 = 22.66 kn 2200 x 10- 12 Note: Rand / or C may be chosen in any convenient manner to obtain the desired RC product. The overall circuit for the requried filter is shown below: -15 +15 -15 +15 85.08k -15 +15 = 298.70 85.0Sk 9 In RG 3 29.3k 11 22.B6k RQ 71.43k RQ -=FIGURE 9. Overall Circuit - Example I. 298.7fl. FIGURE 10. Overall Circuit - Example 2. 5-119 303.4fl. Example 3. It is desired to design a 5 pole Bessel, Low Pass Filter with f, = 3.3 kHz and,ALP = I. From Table I, the followipg values of fo and Q are obtained. Complex Poles: 5 X 104 , RQ = 2 x 0.91652 + 0.91652 _ 1= 28.58 kO For Stage 3. f = 3.3 kHz x fn = 3.3 kHz x 1.50470 = 4966 Hz For the simple pole, I 'I _< RC = 21Tf = 21T x 4966 = 3.2049 x 10 . 3300 pF (or any convenient value) 3.2049 x 10-' R = 3300 x 10-" = 9.71 kO fo = 1.55876 ] Q = 0.56354 fo = 1.75812] Q = 0.91652 Simple Pole: The overall circuit is shown below. fo = 1.50470 Using the above shown values of fo and Q, we now will proceed to design the three stages of filter separately. Anyone of the three configurations can be used. We will select inverting configuration. For Stage I. = 3.3 kHz x fn = 3.3 kHz x 1.55876 = 5144 Hz, < 8 kHz, equations "A" would be used. fo Since fo = RF2 = RFI 1.592 x 108 5144 = 30.95 kO Q = 5144 x 0.56354 = 2.9 x IOJ < 10', :. Qp = Q = 0.56354 Asp = Qp ALP = 0.56354 x I = 0.56354 fo Out fo Q =5X R G 104 x 0.56354 0.56354 = 50 kO FIGURE 11. Overall Circuit - Example 3. USEFUL REFERENCES 5 x 104 RQ = 2 x 0.56354 + 0.56354 _ I 72.4 kO For Stage 2. fo = 3.3 kHz x fo = 3.3 kHz x 1.75812 = 5802 Hz Since fo < 8 kHz, equations "A" would be used. = RF2 = RFI fo 1.592 x 108 5802 = 27.44 kO Q = 5802 x 0.91652 = 5.32 x IOJ f~ Q Asp RG < 105, :. Qp = Q = 0.91652 = Qp ALP = 0.91652 x 1=0.91652 = I. G.E. Tobey, J.G. Graeme ,and L.P. Huelsman, Operational Amplifiers: Design and Applications, (Chapter 8) McGraw Hill Book Co .. 1971. 2. Yu Jen Wong. William E. Ott, Function Circuits: Design and Applications, (Chapter 6) McGraw Hill Book Co., 1976. 3. Richard W. Daniels, Approximation Methods for Electronic Filt~r Design, McGraw Hill Book Co .• 1974. 4. Anatol I. Zverev, Handbook of Filter Synthesis, John Wiley and Sons Inc., New York, N.Y., 1967. 5. Gabor C. Ternes, Sanjit K. Mitra, Modern Filter Theory and Design, John Wiley and Sons, New York, N.Y., 1973. 5 x 104 X 0.91652 _ 5' 0 '0.91652 - 0k 5-120 DATA CONVERSION AND ACQUISITION The Burr-Brown data conversion and acquisition product line includes components necessary to multiplex and convert signals from analog-todigital form and digital-to-analog form. These components are produced in four product types: digital-to-analog converters, analog-to-digital converters, sample/hold circuits, and multiplexers. These products were designed to make their applications easy. Most units are complete, requiring no external components. All D/A converters include an internal reference arid most have an output voltage amplifier. AID converters come with internal clock, reference, and comparator. Many sample/hold circuits have an internal holding capacitor. The multiplexers contain input protection circuitry to prevent damage from input overvoltages. If your system requires data acquisition and conversion, you will want to consider one of our predesigned System Data Modules (SDM). Each contains a multiplexer, instrumentation amplifier, sample/hold circuit, A/D converter, and timing and control logic. The microperipheral components are SDM's that have address decoding and specialized control logic making them compatible with most of the available microprocessors. These subsystems, tested at the factory, have a proven record of reliability. True 16-bit accuracy performance will soon be available in the ADC73, an advanced design successive approximation AID converter, guaranteed to have no morethan ±O.00075% linearity error. Introduction is planned for2nd quarter 1982. Burr-Brown data acquisition components - quality and reliability at low cost. 6-1 .SELECTION GUIDE Data Conve,rsion and AcquisUion Operating temperature range aoc to 700 C and 'parameters are typical unless otherWise noted ANA.LOG-TO-DIGITAL CONVERTERS ConverAccy. Drift sian Time, Btpolar: max max l%ofFSR, maxi/oisec" ppm FS.R/'C· Resalution IBits. Description Model( 1) Low Cost ADC80AG-1013) ADC60AG-1213) Low Cost, High Speed Low Drift. High Speed High Resolution 10 12 21 25 ±0.048 ±0.012 ±23 ±23 8 8 ;''0.2 2.8 2.8 ±75 :!:75 AQC84KG-10 ADC84KG-12 10 12 ±0.048 ±0.012 6 10 ±23 ±23 ADC85C-10 ADC85-10 ADC85C-12, ,a, ADC85-12, 'a, 10 10 12 12 ±0.048 ±0.048 ±0.012 ±0.012 ADC71JG ADC71KG 16 16 ±O.OOS ±0.003 ADC82AG ADC82AM. 'a, In,pl,Jt Linea.rity. i±:O.2 6 6 '10 10 50 50 Range ,V, Package Units 100's Page )nd Ind DIP DIP 85.00 87.00 46.00 48.00 6-48 6-48 ,I·nd Ind 'DIP DIP 69.00 93.80 48.00 62.60 6-56 6-56 Com Com DIP DIP 105.00 '119.00 72.00 75.00 6-84 6-64 Com Ind DIP DIP DIP DIP 119.00 143.00 132.00 '172.00 99.00(7) 120.00'17) 108.00,(7) 129.00 (7) 6-64 6-64 6-64 6-64 :!:2.S. ±S. ±10.. +5. +10 ~2.5. ±5. ±10 +5. +10. ;1-20 :t53 ±2.5. ±5, ±28 ±3O ±19 .:t10, -r-5, +10 Com Ind Com Com ±25 ±25 ±2.5, ADC72AM ADC72BM ADC72JM ADC72KM 16 16 16 16 ±0.006 ±0.003 ±O.OOS ±0.003 50 50 50 50 ADC76JG ADC76KG 16 16 ±O.OOS ±0.003 15 15 ±3O 12 12 ±0.012 ±0.048 50 50 :t63 Very-Wide ADC10HT Temp Range ADC10HT-1 Price $ Temp Rangel') ±5. ±25 ±25 ±10, o to. +5, Oto +10; o to +20 ·:t30 :t;3.0 :t30 ±34 :t5, ±10 ±5, :t10 Ind Ind Com {CeramiC 32-pin DIP { Com Metal Hermetic 32-pin . DIP 168.00' 210.00 122.00 152.00 6-24 6-24 269.00 295.00 225.00 265.00 194.00 213.00 162.00 191.00 6-32 6-32 6-32 6-32 Com Com {CeramiC 32-pin DIP 229.00 , 265.00 165.00 191.00 6-40 6-40 -55°C to -t-200°C ceramiC 485.00 448.00 395.00 365.00 6-8 6-8 2B-pm DIP Very-High Speed ADC60-08 ADC60-10 ADC60-12 Military ADC87/MIL Series High ADC100-SMD ±0.195 ±0.0488 ±0.0244 8 10 12 0.88 1.88 3.50 ±20 :!:20 ::t15 { ±25, ±5 ::!:10. +5 +10, +20 Gom Module Com Com Module Module 285.00 316.00 326.00 207.00 228.00 235.00 6-18 6-18 6-18 Com Module 376.00 285.00(7) 6-72 See Military Products 4 digit + sign ±0.005 30msec ±5 Resolution I :tlO PCM ANALOG-TO-DIGITAL CONVERTERS FOR AUDIO Resolution Total Harmonic Distortion Conversion Time [BitSI 1mB,X I ImaXI PCM75KG 16 0.02% at -1SdB 17l'sec(6) PCM75JG 14(5) 0.05% at -15dB 15I'se<:(6) Description Model Audio Converter(4) Input Range ,V, Temp Range(2) Dynamic Range Units 100's Page ±2.5, ±5, ±10 ±2.5, ±5, +10 Com 90dB 249.00 189.00 6-298 Com 90dB 198.00 145.00 6-298 Price ($1 NOTES: 1) "(OJ" Indicates product also available with screening for increased reliability. 2) Com =Oto +70'C; Ind = -25'C to +85'C; Mil =-55'Cto +125°C. 3) "Z" models operate from ±12VDC supply. 41 Internal 16-bit DAC available to user. 5) Can be operated at 16-bits. 6) Can be reduced to 8l'sec. 7) 25-99 quantity. 6-2 DIGITAL-TO-ANALOG CONVERTERS Resotution IBitsi Accy. Drift, linearity Bipolar max Ippm max 1% of FSR, of FSR/oC, Settling Output Time ,FSR. ±1/2LSB, Temp Range(2} Description Model(1J Monolithic(3) DAC800-CBI-1 DAC800-CB)-V 12 12 ±0.012 ±0.012 ±25(5) ±1, -2mA ±25 {±2.5, ±S. ±10V +5. +10V 300nsec 3,usec Com Com DAC850-CBH DAC850-CBI-V 12 12 ±0.012 ±0.012 ±17(5) ±17 300nsec Ind Ind {Hermetic DAC851-CBH DAC851-CBI-V 12 12 ±0.012 ±0.012 ±30(5) ±30 ±1, -2mA. {±2.5. ±S. ±10, +5. +10V 300nsec Mil Mil {Hermetic DAC80-CBI-1I41 DAC80-CBI-V(4) 12 12 ±0.012 ±0.012 ;1:25(5) ±25 ±1.0. -2mA { ±2.S, ±S, ±10 300nsec 12-Bit Ranges ±l, -2mA. { ±2.5, ±S, ±10. ' 3psec Package { 24-pin DIP 24-pin +5. +10V Low Cost Price 1$, 100's Units Page IH93 23.95 29.95 15.95 19.50 5-183 39.00 47.00 28.00 34.00 6-19U 6-190 105.00 120.00 69.00 79.00 6-190 5-190 DIP 3,usec 24-pin DIP 31lsec Com Com DIP DIP 34.25 36.50 22.00 22.95 6-152 6-152 Com Com DIP DIP 34.50 36.50 22.00 22.95 6-152 6-152 +5. +10V Low Drift DAC80-CCD-j(4) DAC80-CCD-V(4) 3 digits 3 digits ±0.025 ±0.025 ±25(5) ±25 o to -2mA 300nsec o to +10V 3",sec DAC85-CBI-I, ,0, DAC85-CBI-V. ,0, 12 12 ±0.012 ±0.012 ±20(5) ±20 ±l.C, -2mA 300nsec DAC85C-CBI-I., 0, DAC85C-CBI-V.,O, 12 12 ±0.012. ±0.012 DAC85LD-CBI-V 12 ±0.012 3J,tsec Ind Ind 300nsec 3j.1sec Com Com 3,usec Ind Oto -2mA 5Ol-'sec ±lmA 50jJ.sec 50I-LseC 50,usec 50I-Lsec Ind Ind Com Com Ind Com 1,usec 1,usec 1,usec 10I-Lsec 10/-lsec 10,usec Com Com Com Com Com Com 1",sec 1,usec 1.usec 10/-lsec 10,usec 10I-Lsec Com Com Com Com Com Com 1/-1sec 1J,Lsec 1.u sec lOJ,Lsec 10.usec lOJ,Lsec Ind Ind Ind Ind Ind Ind 50/-lsec 50.usec 50.usec 50.usec Com Com Com Com 200nsec 200nsec -55°C to to -SmA ±2.SmA 40nsec lS0nsec Com Com ±5, -lOrnA :±-S, -lOrnA 35nsec 35nsec Ind Ind { ±2.5, ±S, ±lO +5. +10V ±3015) ±1.0. -2m A ±30 { ±2.5, ±S, ±10 +5. +1OV ±5 ±2.5, ±S, ± 10 +5. +10V High Resolution 4 digits 4digils ±0.003 ±0.003 ±0.005 ±0.005 ±O.003 ±0.005 ±9(5) ±9(5) ±21(5) ±21(5) ±9(5) ±21(5) DAC71-CSB-1 DAC71-COB-1 DAC71-CCD-1 DAC71-CSB-V DAC71-COB-V DAC71-CCD-V 16 16 4 digits 16 16 4 digits ±0.003 ±O.003 ±0.005 ±0.003 ±0.003 ±0.005 ±15(5) ±15(5) ±15(5) o to -2mA ±15 ±15 ±15 o to +10V ±1OV Oto +10V DAC72C-CSB-1 DAC72C-COB-1 DAC72C-CCD-) DAC72C-CSB-V DAC72C-COB-V DAC72C-CCD-V 16 16 4 digits 16 16 ±0.003 ±0.003 ±0.005 ±0.003 ±0.003 ±0.OQ5 ±1515) ±1515) ±15151 o to -2mA ±lmA Oto -2mA ±15 ±15 ±15 o to +10V ±8(5) ±8(5) ±8(5) ±8 ±8 ±8 010 -2m A ±lmA Oto -2mA 16 16 4 digits ±0.003 ±0.003 ±0.005 ±0.003 ±0.003 ±0.005 16 16 16 16 ±0.0015 ±0.00075 ±0.0015 ±0.00075 ±10.5 12 12 ±0.012 ±0.048 ±20 ±50 ±0.048 DAC70-CSB-1 DAC70-COB-I. ,0, DAC70C-CSB-) DAC70C-COB-1 DAC70-CCD-1 DAC70C-CCD-1 DAC72-CSB-1 DAC72-COB-1 DAC72-CCD-1 DAC72-CSB-V DAC72-COB-V DAC72-CCD-V HighResolution Highly Accurate DAC73J DAC73K DAC736J DAC736K Very-Wide DAC10HT Temperature DAC10HT-l Range 16 16 16 16 4 digits 16 16 4 digits o to -2m A ±lmA Oto -2mA o to -2m A ±lmA o to -2mA ±10V o to +10V o to +1OV ±10V o to+l0V :'::18 ±10.5 ±18 Very-High Speed DAC60-10 DAC80-12 10 12 ±0.012 ±15(5) ±1515) Ultra-High Speed DAC63BG DAC63CG 12 12 ±0.012 to.012 ±40 ±30 ±2.5, ±5, ±10 +5V. +10V o to -2mA ±lmA {±2.5, ±5, ±10. +5, +10 l ° 50~sec +200°C 1-' 1-' Herm~tic 24-pln DIP Hermetic 24-pm DIP 84.50(6) 6-170 86.50(8) 6-170 77.00 79.00 66.00(6) 68.00(6) 5-170 5-170 142.75 129.5Q{6) 6-170 177.50 177.50 124.25 124.25 177.50 124.25 140.75161 5-101 140.75(8) 6-101 98.53(8) 6-101 98.5316) 6-101 140.75(6) 6-101 98.53(6) 6-101 DIP DIP DIP DIP DIP DIP 62.00 62.00 62.00 65.00 65.00 65.00 '46.00 46.00 46.00 52.00 52.00 52.00 6-109 5-109 6-109 6-109 6-109 6-109 Hermetic 24-pin 79.00 79.00 79.00 87.00 87.00 87.00 52.00 52.00 52.00 58.00 58.00 58.00 6-119 6-119 5-119 6-119 5-119 6-119 89.00 89.00 69.00 101.00 101.00 101.00 60.00 60.00 60.00 67.00 67:00 67.00 6-119 6-119 6-119 6-119 6-119 6-119 Module Module Module Module 242.00 286.00 220.00 280.00 193.00 228.00 175.00 206.00 6-129 6-129 6-129 6-129 ifceramiC 24-pin 295.00 273.00 165.00 150.00 6-80 6-80 Module Module 158.00 172.00 106.00 114.00 6-88 6-88 {CeramiC 108.00 119.00 83.00 92.00 6-93 6-93 r1 DIP M,., Hermetic 24-pin DIP l\ DIP 24-pm DIP 6-3 104.00 107.00 DIGITAL-TO-ANALOG CONVERTERS, continued Aesolution (Bits) Description Model(1) Military DAC87/MIL Accy. Drift. Linearity Bipolar max I ppm max I%of FSAI of FSR/oCI Settling Time FSR. ±1!2LSB Output Ranges Temp Range(2) Package Price 1$1 Units, 100's Page See Military Products Series Low Cost DAC82KG Monolithic 8-Bit DAC90BG, DAC90SG. PCM Audio Converter PCM50KG la' la' 8 ±0.16 ±50. ±2.5, ±5, ±1Q +5. +10. ±0.8. Oto -1.6mA 2.5Jlsec Com DIP 33.90 22.70 6-163 8 8 ±0.2 ±7515) ±7515) ±I. -2mA ±1, -2mA 200nsec 200nsec Ind Mil DIP DIP 19.40 26.50 13.00 17.70 6-178 6-178 ±O.2 See PCM Digltal-Io-Analog Converters for Audio PCM DIGITAL-TO-ANALOG CONVERTERS FOR AUDIO ,Bits, Total Harmonic D.istortion ,maXI 16 16 0.02% al-15dB 0.04% al-15dB Resolution Description PCM-Audio 01 A Converter Model PCM50KG PCM51JG Settling Time Output Range ,V· Temp Range(2) Dynamic Range ±10,±5 Com Com 96dB 96dB 5,.,.sec 5psec +10 +5 Price ,$ Units 100's I b56~acl fa~~o~e Page 6-281 6-289 NOTES: 11 "(01" indicales product also availablewilh screening for increased reliabilily. 21 Com =010 +7()oC; Ind =-25°C 10+85°C; Mil =-55°Clo+125°C. 31 In -v models the output op amp is on a second chip. 4) models operate from ±12VDC supply. 5) When used with an external op amp which uses the internal feedback resistor. 61 25 - 99 quantity. "z" SELF-CALlI'lRATING DIGITAL-TO-ANALOG CONVERTER Description Model Resolution Total Accuracy +15 to +45°C Output Ranges Calibration Time Precision. HighResolution DAC74 16-bils ±O.0015%. max o to +IOV ±10V 2.5 sec Package 7" x 5" x 0.6" metal Price $ Units Page $1495.00 6-137 POWERDACS Description Model Loweost, Open PC Card 4804 Input Coding 12-bil binary Accuracy Output Voltage ,V, Outpul Current ImA, Package Price 1$1 Units 25-99 User-selected to±30 ±2000 PC card 259.00 1182.00 Tempco I ppm FSR/oC, ±0.05%of reading 50, max I 6-381 V/F CONVERTERS Y,N Tempco ppm of FSR/'C max Temp Range(2) Package Price $ Units l00's Page ±O.O1 50 50 Ind Ind Module Module 54.50 57.75 36.50 38.65 6-360 6-360 ±0.005 ±0.005 10 10 Ind Ind Module ModtJle 83.50 85.50 56.75 59.00 6-360 6-360 ±0.01 at 10kHz ±O.05 all OOkHz ±0.2 at 500kHz ±150 '±150 ±150 Com Ind Mil DIP TO-IOO TO-IOO 10.15 14.90 19.70 6.15 8.35 11.85 6-367 6-367 6-367 ±IOO ±10a ±150 ±150 Ind Mil Ind Mil DIP DIP DIP DIP 19.75 14.50 22.75 14.50 22.75 6-375 6-375 6-375 6-375 Frequency Range 1kHz Range V· Linearity %of FSR max Description. Model(1) Low Drifl. Complete VFC12 VFCI5 01010. 01020 o to +10 Oto+20 ±0.01 Very-Low Drift, Com'plete VFCI2LD VFC15LD Oto 10 Ot020 010+10 o to +20 Low Cost. Monolithic VFC32KP VFC32BM. VFC32SM. User-selected, 500kHz. max User-selected Military VFC32/MIL Series Low Cost, Complete, Hybrid VFC42BP VFC42SM VFC52BP VFC52SM Oto 10 01010 Oto 100 Oto 100 010+10 o to +10 010+10 Oto+10 'a, 'a, See Military Products ±0.01 ±0.01 ±0.05 ±0.05 NOTES: 11 "rQ I" indicates product also available with screening for increased reliability .. 2, Com 6-4 33.40 19.75 33.40 = 0 to +70°C; Ind =·-25°C to +85°C; Mil = -55°C to +125°C. DATA ACOUISITON SYSTEMS Resolution Bits Throughput Accuracy ·%of FSR Throughput Rate kHz Package { 16 single-ended 8 differential 12 ±0025 30(1) Module 365.00 256.00 13) 6-308 SDM858 { 16 single-ended 8 differential 12 ±0.025(2) 8(1) Module 369.00 265.00 (3) 6-336 Hybrid ±10V Input SDM854AG SDM854BG {16 single-ended 8 differential 12 12 :to.048 ~0.024 40 29 OIP OIP 220.00 246.00 165.00 185.00 6-314 6-314 Hybrid SDM856JG SDM856KG 12 12 ±0.048 ±0.024 33 25 OIP OIP 174.00 219.00 125.00 158.00 6-330 6-330 12 12 ±0.048 25 18 OIP OIP 194.00 242.00 130.00 162.00 6-330 6-330 Description Model Modular SDM853 Low Level Hybrid Low Level SDM857JG SDM857KG Channels ( 16 single-ended 8 differential ±O.O24 NOTES: 1) Can be increased if short-cycled to 8- or 10-bit resolution. 2, At gain Price $ Units 100's Page = 100. 3, 50 - 99. MICROPROCESSOR INTERFACED ANALOG INPUT SYSTEMS Description Model Channels Resolution Accuracy %of FSR max TempeD ppm/oC max Package 8080- SC/M PCompatible MP20 8 differential 16 single-ended 8 bits ±o.a. high ±40 OIP 280.00 222.0012) 6800-. 6502Compatible MP21 8 differential 16 single-ended 8 bits ±0.8. high :to.4.low ±40 OIP 280.00 222.0012) 6-217 Universal MP22BG 8 differential 16 single-ended 12 bits ±0.4. high ±0.1.low ±25(1) OIP 324.00 241.0012' 6-229 HighAccuracy MP32BG MP32CG 8 differential 16 single-ended 12 bits 12 bits ±0.05 ±0.025 ±60 ±60 OIP OIP 339.00 429.00 267.00 286.00 Price $ Units 100's Page 6-205 ±O.4, low 6-237 MICROPROCESSOR INTERFACED ANALOG OUTPUT SYSTEMS Description Model Channels Resolution Accuracy % of FSR max Tempco ppm/OC max Package 8080-. SC/M PCompatible MP10 2 8 bits ±0.4 ±80 DIP 6800-.6502Compatible MP11 2 8 bits -±:04 ±80 DIP Price $ 100's Units Page 141.00 94.00 6-197 141.00 94.00 6-197 NOTES: 1 ' Unipolar, excludmg IA. 2 25 - 99 quantity. MULTIPLEXERS Description Model Protected Inputs MPC8S MPC4D MPC16S MPC8D High Speed MPC800KG MPC800SG MPC801KG MPC801SG Channels Input Range IV, On Resistance max Crosstalk % of OFF Channel Signal Settling Time ·100.01%· Package 8 single 4 differential 16 Single 8 differential ±15 ±15 ±15 ±15 1.8kll 1.8kll 1.8kll 1.8kll 0.005 0.005 0.005 0.005 5,t.1sec 5,t.1sec 7,t.1sec 7,t.1sec DIP DIP DIP DIP 12.97 12.97 23.21 23.21 9.50 9.50 17.00 17.00 '6-267 6-267 16 single or 8 differential 8 Single or 4 differential ±15 ±15 ±15 ±15 750ll 750ll 75011 75011 0.004 0.004 0.004 0.004 aoOnsec aoOnsec 800nsec aoOnsec DIP DIP DIP DIP 30.71 61.43 16.00 33.12 22.50 45.00 11.72 24.26 6-253 6-253 1 1 Price $ Units 100's Page 6-274 6-274 6-260 6-260 SAMPLE/HOLD CIRCUITS Gain/Offset Error ,%, ,mV, Charge Offset ,mV Droop Rate ImV/msec Tempco ppm of 20VfOC Acquisition Time ,t.Isec (2) Package Price $ Units 100's Page 51.00 6-342 Description Model(1) Low Cost, Complete SHC80KP ±0.01. ±2 max ±2 max 0.5 max 3 1.0 max DIP High Speed. Complete SHC85.10, SHC85ET. 10, ±0.01. ±2max ±0.01, ±2 max ±2 max ±2 max 0.5 max 0.5 max 3 3 4.5 max 4.5 max DIPI3) DIP(3) Low Cost, Monolithic SHC298AM ±0.01, ±7 max ±25 max 10 max(4) 4 lOmax TO-99<3' 6.95 Very-High Speed SHM60 ±0.01, ±1.5 ±1.5 5 2 1 max Module 154.00 34.10 95.00' 75.9015' 129.00 106.0015' 6-346 6-346 4.50 6-350 104.00 6-356 NOTES: 11 "I Q I" indicates product also available with screening for increased reliability. 2, 10V step to 0.01 % of final value. 3 Hermetic. 4· With 1000pF external holding capacitor. 5, 25 - 99 quantity. 6-5 GLOSSARY O'F TERMS & DEFINITIONS Data Conversion and Acquisition ACQUISITION TIME The time the output of a sample/ hold circuit takes to change from its previous value to a new value when the circuit is switched from the hold mode to sample modei It includes the slew time and settling time to within a certain error band ofthe final value and is usually specified for a full-scale change. DROOP RATE A sample/hold circuit in the hold mode has a charge stored on a capacitor that is proportional to the input voltage at the time it was switched to the hold mode. Charge leaks off the capacitor because of the bias current of the buffer amplifier and switch leakage current. The droop rate is an expression of how fast the charge leaks off the capacitor and is given as a voltage per-unit-oftime. APERTURE TIME When a sample/hold circuit is switched from sample to hold, a finite amount of time is required for the internal electronics to turn off. Aperture time is the time between the sample-to-hold command transition and the point at which the output ceases to follow the input. FEEDTHROUGH The measure of the change of the output voltage of a sample/ hold in the hold mode due to a voltage change in the input, expressed as dB of attenuation. GAIN ERROR The error in the input-to-output ratio, usually expressed in percent. It is manifest as a rotation about the most negative full scale point of the transfer function curve. It is nulled in A/D, D/ A, orV /F converters after the offset error is nulled by setting the inpilt for a full-scale output and adjusting an external trim pot for the correct output. APERTURE TIME UNCERTAINTY The possible deviation in aperture time from one sampleto-hold transition to the next. COMPLIANCE VOLTAGE Some D / A converters have an output current proportional to the input digital code. The compliance voltage is that voltage which may be impressed on the output current pin without degrading the specifll!d accuracy of the converter. CONVERSION SPEED The measure of how long it takes an A/D converter to arrive at the proper output code. It is the time between the edge of the convert command pulse that starts conversion and the rising edge of the end-of-convert signal that indicates the conversion is complete. LEAKAGE CURRENT Multiplexer input current that does not flow through to the output but is shunted internally. It is also current that flows from OFF channels into the ON channel. In a . current output D / A converter, there is a digital input code that ideally yields zero output current. If current flows with that input code, it is called leakage current. It is analogous to output voltage offset in a voltage-output D / A conVerter. LEAST SIGNIFICANT BIT (LS8) The lowest-order bit or the bit with the least weight. CHARGE OFFSET During the sample-to-hold transition of a sample/hold circuit, a small amount of charge is transferred to the holding capacitor because of the switching process. This is known as the charge offset and is usually expressed in millivolts. LINEARITY The maximum deviation of an actual output from an ideal output defined by a straight-line drawn through the end points of the transfer function. This is the error that remains after offset and gain errors have been nulled. It applies to A/D, D/ A, and V /F converters. Linearity can be expressed in terms of percent of full scale range or fractions of a least significant bit (LSB). A converter must be linear to within ±I / 2LSB to be accurate to its full resolution. CROSSTALK The measure of effect an off-channel signal has on the Qnchannel signal in a mUltiplexer, expressed in terms of dB of attenuation of the off-channel signal. DIFFERENTIAL LINEARITY The measure of the lInearity from one digital state to the next. It applies to A/D and D/A converters. If th.e differential linearity is specified as +1/ 2LSB, the step size from one state to the next may be from 1/2 to 3/2 of an ideal I LSB step. MONOTONICITY In a D/ A converter, if the output analog signal either increases or stays the same for an increase in input digital code, it is said to be monotonic. In an A/D converter, if 6-6 great as I I 2LSB because of this quantizing effect and the greatest error will occur at the transition voltage where the output changes state. the output digital code increases or stays the same for a I LSB increase in input voltage, it is said to be monotonic. If the differential linearity is within ± I LS B, the device will be monotonic. Monotonicity is especially important in control loops where convergence is necessary. RESOLUTION The number of bits on the input or output of an A I D or D I A converter. The number of discrete steps or states is equal to 2" where n is the resolution of the converter, however, n bits of resolution does not guarantee n bits of accuracy. MOST SIGNIFICANT BIT (MSB) The highest-order bit or the bit with the greatest weight. NO MISSING CODES This is a property of an AI D converter that is related to, but is more stringent than, monotonicity. Ifaconverteris guaranteed to have no missing codes, there will be no output digital state that will be skipped when the input voltage is varied over the entire range. SETTLING TIME The time delay between a change of input signal value and the effected change in the output signal. It is usually expressed in terms of how long it takes the output to arrive at, and remain within, a certain error band around the final value and is often given for several different magnitudes of input step change. OFFSET ERROR This is an error in the reference point of the transfer function. It appears as a constant amplitude error signal at a D I A output or AI D input. It also appears as a constant frequency shift in the output of a VI F converter. It is nulled prior to adjusting gain error by setting the input to the most-negative input and adjusting the output to the proper value. SWITCHING TIME The time it takes for a multiplexer to change from one channel to the next with the new output signal being within a certain percentage of its final value. It is expressed for a maximum voltage transition. THROUGHPUT RATE An AID converter or a data acquisition system has a finite number of points that it can convert in any given time. Throughput rate is an expression of that quantity. It is dependent on the time it takes to make a conversion and the time required to set up to make the next conversion. In a data acquisition system this time includes the composite delay due to switching and settling times of the mux, settling time of the amplifier and acquisition time of the sample-and-hold. POWER SUPPLY REJECTION RATIO The measure of output signal change due to power supply voltage change. It is expressed as dB of attenuation or % output change per % supply change. QUANTIZING ERROR In an AID converter, there is an infinite number of possible input voltages, but only 2" output codes (n = number of bits). Therefore, there will be an error as 6-7 BURR-BROWN® ADC10HT IElElI Wide Temperature Range General Purpose 12-Bit ANALOG-TO-OIGITAL CONVERTER FEATURES • -55°C to +200°C SPECIFICATIONS • FULL 12-BIT RESOLUTION • 5O~sec MAX CONVERSION TIME • NO MISSING CODES OVER FULL TEMPERATURE RANGE • COMPLETE WITH INTERNAL CLOCK AND REFERENCE VOLTAGE • SERIAL OUTPUT DATA AVAILABLE • TTL AND +5V CMOS COMPATIBLE • DUAL-WIDTH HERMETIC CERAMIC PACKAGE • LOW POWER OPERATION WITH EXTERNAL REFERENCE (250mWI DESCRIPTION You'll find this general purpose, 12-bit, successive approximation AI D converter ideally qualified for circuits that must operate over wide temperature ranges. The ADC IOHT incorporates state-of-the-art IC and laser-trimmed thin-film components. It is complete with an internal clock and reference voltage. Internal scaling resistors allow bipolar input voltage ranges of±5V and ±IOV. A pin is provided for serial output data. The ADCIOHT is contained in a compact, dual width, 28-pin ceramic DIL package. To assure consistent performance, 100% screening procedures are conducted on the ADCIOHT at key points during its manufacture. Burn-in and temperature cycling are examples. A clean,room environment is maintained for assembly operations. ~il==~ .POUIIIFFIET J= aF. ' - - - - - - 0 CllMlTcalllAlIII r : = - , . - - - - - o ......UT L = J - - - - - o ..."" .." ...· IL _.DUT ,=========!ITATUI Inlernatlonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746-1111 . Twx: 9I(l.952·1111 . Cable: BBRCORp· Telex: 66-64111 PDS-474 6-8 SPECIFICATIONS ELECTRICAL Specifications at rated power supply voltages and TA = +25°C unless otherwise noted. ADC10HT MODEL RESOLUTION I I MIN 12 I I TYP ADC10HT-l I I MAX I I TYP MIN MAX 12 I I UNITS Bits INPUT I ANALOG Voltage Ranges Unipolar Bipolar Impedance Idirect input) o to +10V, ±SV o to +20V, ±10V I I I o to +10, 0 to +20 o to +10, 0 to +20 ±5, ±10 ±5. ±1Q. V V 2 4 2 4 kll kll 1 1 CMOS Load DIGITALI') Convert Command Logic loading TRANSFER CHARACTERISTICS ACCURACY Gain Error12) ±O,OS ±0,2 ±O,OS ±0.2 % ±C,OS ±C.OS ±C.2 ±0.2 ±0.012 ±O.OS ±O.OS ±0.2 ±0.2 ±0.048 Offset Erron2) Unipolar Bipolar Linearity Error Inherent Quantization Error Differential Linearity Error Total Unadjusted Erron') +2SoC -SsoC to +2000C Total Adjusted Error(S) +2SoC -SsoC to +2000C Total Unadjusted ErronS) Exclusive of Reference +2SoC -SsoC to +200oC Total Adjusted Error(7) Exclusive of Reference +25°C -55°C to +200oC ±0.048 % of FSRI31 %of FSR % of FSR LSB % of FSR ±C.l0 ±C.30 ±0.40 ±1.00 ±O.lS ±0.80 ±0.40 ±1.S0 % of FSR % of FSR ±0.006 ±0.20 ±0.012 ±0.60 ±0.024 ±O.SO ±0.048 ±1.10 % of FSR % of FSR ±C.l0 ±C.20 ±0.40 ±0.80 ±O.IS ±0.50 ±0.4S ±1.10 % of FSR % of FSR ±0.006 ±O.IS ±0.012 +0.40 ±C,024 +0.40 ±C.048 ±0.75 % of FSR % of FSR 30 50 30 50 ,usee ±15 ±5 ±35 ±10 ±25 ±10 ±100 ±20 ppm/oC ±1 ±2 ±2 ±10 ppm of FSR/oC ±10 ±4 ±0.5 ±35 ±10 ±1 ±25 ±8 ±1 ±100 ±20 ±3 ppm Of FSR/o C ppm of FSR/oC ppm of FSR/oC ±1/2 ±1/2 ±0,012 CONVERSION TIME DRIFT I-55°C.; TA .; +2000C I Gain With Internal Reference Exclusive of Reference Offset Unipolar Bipolar With Internal Reference Exclusive of Reference Linearity No Missing Codes' Temp, Range -55°C to +200°C, 12 ppm/oC Bits 10 OUTPUT DIGITAL DATA Parallel Output CodeslB) Unipolar Bipolan S) Output Drive Serial Data Code I NRZ I - 58, OB Output Drive Status Status Output Drive Internal Clock Output Drive Frequency I 1 SB OB, TC I SB,OB I I I I 1 Logic "1" During Conversion 1 1 I SB OB,TC 1 I SB,OB I 6-9 I LSTTL Loads I LSTTL Loads 1 Logic "1" During Conversion 1 LSTTL Loads LSTTL Loads 1 400 I 400 kHz SPECIFICATIONS MOOEL ADC10HT I . TYP MIN POWER SUPPLIES AND REFERENCE ±14.5 +4.75 Rated Voltage, Analog Digital Supply Drain, +15VDCll0) -15VDCll0) +5VDC Power Supply Sensitivity ±15VDC +5VDC Internal Reference Voltage Max External Current with no Degradation of Specs Temperature Coefficient 9.990 ADC10HT-l I MAX ±15 +5 +15 -30 +16 0.01 0.01 10.0 I ±15.5 +5.25 MIN TYP' MAX ±14.5 +4.75 ±15 +5 +15 -30 +16 ±15.5 +5.25 I %of FSR/%Vs %of FSR/%Vs V o.ot 10.010 9.990 10.0 - VDC VDC mA mA mA 0.01 2 ±10 UNITS 10.010 2 ±10 mA ppm/oC TEMPERATURE RANGE -55 -55 -65 Specification Operating Storage +200 +200 +210 -55 -55 -65 +200 +200 +210 °C °C °C NOTES: 1. +5V CMOS compatible. Input current (low to high state I = lp.A max:'Use pull-up resistor when driving convert commahd from TTL. 2. Adjustable to zero I see Table II and Figures 5 and 6,. 3. FSR means Full Scale Range. For example, unit connected-for ±10V has a 20V FSR. 4. Includes Gain, Offset. and Linearity Errors (Bipolar Mode I, 5. Gain and Offset Errors removed af +25°C (Bipolar Mode I, S. Includes Gain, Offset. and Linearity Errors with external +10.0V ±1 mV reference. does not include Reference Drift Bipolar Mode. 7. Gain and Offset Errors removed at +25°C with external +10.0V ±1 mV ·reference, does not include Reference Drift, Bipolar Mode 8. See Table I. SB - Straight Binary, OB - Offset Binary, TC - Two's Complement. 9. TC coding obtained by using MSi! 'pin 13, instead of MSB 'pin 12,. 10. May be reduced. See Low Power Operation, pages 6-16 and 6-17.- MECHANICAL • I [ i L t. I NOTES: 1. LeadI in tAl, poeitlon within 0.01G" 'p (0.26mm1 A atMMC lit Mating ptane. 2. Pin numtleralhOWn lor NfeNnCeonly. Numbers rney not be m,rked on package. ,.~ , INCHES D,M • c C Ilrl~rrr.~~TJP H. LL-J MLLLLMETERS MAX M'N D F • • H L K • .. . TOP VIEW SERIAL OUT ·15VOC SUPPLY +15 VDC SUPPLY Bit 9 REF OUT l+l0V Bit 8 ANALOG COMMON 2QVRANGE lOVRANGE BIPOLAR OFFSET CONVERT COMMAND Bit 3 STATUS Bit 2 CLOCK OUT ,MSBIBlt 1 REF IN MsB 8ii1 CLOCK RATE DIGITAL COMMON +5VDC SUPPLY 6-10 2.'" ,::::.. , 11~il CONNECTION DIAGRAM Bit 7 MAX .... B • r- F .... H M'N 1.430 1.486 38.46 37.11 .810 IA81C IS.41 BAIIC .180 .Ioa a.21 .48 .38 .0111 .01' .oa6 . 040 1.1 • 1.40 .100 IA81C 2.6" BASIC .OU .Olli 1.40 .30 .00' .012 .1U ·1IS .800 BA"C .020 .030 .71 TYPICAL PERFORMANCE CURVES POWER SUPPLY REJECTION VS POWER SUPPLY RIPPLE FREQUENCY LINEARITY ERROR VS CONVERSION SPEED 0.200 -- I - - -- -- 1I2Lkil ,;;. SBt. / 0.175 ;: ~ g €;: '0 0.150 ~ 0.125 w 0.1 0.08 - " 1 I I I ± 1 5 V 0.06 -15V 0.04 - f- 0.075 c . If. ~ ~ "c.::>. ~ Bil 0,J>8ral:on o~ t: c w -- 10 Bil Operalion 0.100 :::; 0.050 maE -, \\ IX -- 0.025 o o - - a:& en c 12 Sil O~eralion I , ~~ ~r-.. 10 15 1/2LSB 'or 10 Bits_~ IL .. --" oll If. = - -- li2tsel~~B~I~, - - ---. :::.-- ~ 20 25 30 35 40 45 0.02 0.01 0.008 0.006 0.004 0.002 0.001 0 50 10 100 lk 10k lOOk Frequency (Hz) Conversion Time (".sec) DISCUSSION OF PERFORMANCE The accuracy of a successive approximation AI D converter is described by the transfer function shown in Figure I. All successive approximation AI D converters have an inherent Quantization Error of±1/2LSB. The remaining errors in the AI D converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off) and Offset.drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AI D converter. A Differential Linearity error of ± I I 2LSB means that the width of each bit step over range of the AI D converter is ILSB,±1/2LSB. The ADCIOHT is also Monotonic, assuring that the output digital code either increases or remains the same for increasing analog input signals. Burr-Brown also specifies that this converter will have nQ missing codes over the full operating temperature range. 1111_.1111 I.. !l .......::>::>.... co -' == ~ 1111-.1110 1100... 1100 1100_.0010 lOO1l-OlDl 0111-.1111 0111-.1110 0000...00111 00lI0_.00lI0 FIGURE I. Input vs Output for an Ideal Bipolar AI D Converter. 6-11 TIMING CONSIDERATIONS The timing diagram (Figure 2) assumes an analog input such that the positive true digital ward 0110 0 III 0110 exists. eannnllJ Co...n InIIrRIl Cluck II1II1 JEIICJ 188 11t2 Ih3 1114 1111 ---~·I· ===J ===J :::J Lj'T' I 'V' Iv Ih8 ~~-_J Ih7 ~=~-Jr---------~LJ"I" IU 1111 IhlO Mil lIB ...11131 Dill Out LJ"I" ~=-=J U"I" =: ~ ~J I "Ir' := =J :-:::J ::=J Lj"I" LJ "I" =-:. -= W~ "Ir' "I" 4 5 I· "1" '--:'V:"..,...!..-='V'-,.J "I" _~I==~v~r--"I" "I" l...!.IIO "Ir' "I" l 11 "I" IJtJfm& V MOTES: I. Thl cluck In Ihl ADCIOItT II running 1lDlll11lUDUl1y. ThI ClllVII'ICDIMIlnd mUll go lew II I_I BOnae bllol'llhl riling eall 0/ Iny clock puilito InlHIII I conVll'llon. 2. 54..... lor 12 bbl. a UlIll'llIIna nUl of clock .. IIr1Ibt ....llllUIpUl FIGURE 2. ADCIOHT Timing Diagram. DEFINITION OF DIGITAL CODES PARALLEL DATA Two binary codes are available on the ADC IOHT parallel output; they are straight binary (SB) for unipolar input signal ranges and offset binary (OB) for bipolar input signal ranges. Two's complement (TC) may be obtained by using MSB (pin 13). Table I shows the LSB, transition values, and code definitions for each possible analog input' signal range for 8-, 10- and 12-bit resoiutions. Figure 3 shows the connections for 12-bit resolution, parallel data output. with ±IOV input. SERIAL DATA Two straight binary codes are available on the serial output line; they are SB and OB. The serial data is available only during conversion and appears with the MSB occurring firsLThe serial data is synchronous with the internal clock as shown in the timing diagram of Figure 2. The LSB and transition values shown in Table I also apply to the serial data output except for the TC code. 6-12 RI ... 11Z .. _ ......_"_1I1• ..... ,...-.,. .............. ,..UI. 1W1I'.xn.ltlllplnlUrI ,...........rInI_lII. . ......... " ...111.... SERIAL OUT ·15V +15V ANALDSSND ANALOG INPUT (-IDYll +lDVJ ADC111tT CONViRT COMMAND STATUS D_I... _ ... _ .. _ ....... ... A11C11I1T'''''''....' ........ p...' .......lj .. D.1j.lF hllllHllllllrllun ClII.eIIIn 1_ .. KD_"".... flllTl.ID4Q. DIGITAL GROUND FIGURE 3. ADCIOHT Connections for ±IOV Analog Input, 12-Bit Resolution, and Serial or Parallel Data Output. TABLE I. Input Voltages, Transition Values, LSB ValJles and Code Definitions. Binary (BINI Oulpul Analog Input Voltage Range INPUT VOLTAGE RANGE AND LSB VALUES Code Designation" One Least Significant Bit (LSBI Transition Values MSB LSB 111...11114) 100...000 000 ... 001 +IOV ±SV oto +IOV Oto +20V OB(1) or tC(2) OB(1) or TC(2) Sill') SBI') Defined As: FSR/2 n 20V/2n IOV/2 n IOVl2 n 20V/2n n=8 n= 10 n = 12 78.13mV 19.53mV 4.88mV 39.06mV 9.77mV 2.44mV 39.06mV 9.77mV 2.44mV 78.13mV 19.53mV 4.88mV +Full Scale Mid Scale -Full Scale +IOV - 3/2LSB 0 -IOV + 1/2LSB +SV-3/2LSB 0 -SV+ 1/2LSB +IOV - 3/2LSB +SV 0+ 1/2LSB +20V - 3/2LSB +IOV 0+ 1/2LSB NOTES: 11 lOB = OIfset Binary (2)TC = Two's Complement - obtained by inverting the most significant bit. MSB (pin 13( (3)SB = Straight Binary (4)Voltages given are the nominal value for transition to the code specified DISCUSSION OF SPECIFICATIONS The ADCIOHT is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an AI D converter are linearity, drift, gain and offset errors, and conversion-speed effects on accuracy. This ADC is factory trimmed and tested for all critical key specifications. POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The ADCIOHT power supply sensitivity is specified for ±O.OI%of FSR I %Vs for±ISV supplies and±O.OI% of FSR / %Vs for+SV supplies. Normally, regulated power supplies with 1% or less ripple are recommended for use with this ADC. See Layout Precautions, Power Supply Decoupling and Figure 4. GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory trimmed to typically ±O.OS% of FSR at 2S"C. These errors may be trimmed to zero as shown in Figures 6 and 7. 6-13 LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AI D converter. Connect the input signal as shown in Table II. See Figure 5 for circuit details. Analog and digital common are not connected internally in the ADC IOHT but should be, connected together ,as close to the unit as possible, preferably to a, large plane under the ADC. If these grounds must be run separately, use wide conductor pattern and a O.OI/lF to O.I/lF non polarized bypass,capacitor between analog and digital commons at the unit: Low impedance analog and digital 'common returns are essential for low'noise performance. Coupling between analog inputs and digital lines should be minimized by car~fullayout. TABLE II. ADCIOHT Input Scaling Connections. POWER SUPPLY DECOUPLING The power supplies should be bypassed with high temperature mica or teflon capacitors as shown in Figure 4 to obtain noise free operation. These capacitors should be located close to the ADC. Input Signal Range Output Code Connect Pin 21 To Pin Connect Pin 23 To ±10V ±5V oto +10V Oto +20V OBorTC' OBorTC' SB SB 25" 25" Open Open InputSig, Open Open Connect Input Signal To Pin Input Sig. 23 22 22 23 ·Obtained by using MSB Ipln 131 •• If optional offset adjustment is not used connect a 2S!l ±O.1% resistor from pin 21 t~ pin 25 to obtain specified gain and" offset errors. .. +5VOC .. 1 r DIGITAL COMMON ® OM • ® ® ® 1 ~'~Fl O.I~F~ @) REF ·15VOC 'OU~' 2& , VREF • RS =2511 ~ I%If glln IdlUII11 nat uud. RG 17 ANALOG COMMON .. REF, IN " TO O/A CONVERTER @ . 21 +15VOC BIPOLAR OFFSET FIGURE 5, ADCIOHT Input Scaling Circuit. FIGURE 4. Recommended Power Supply Decoupling. OPTIONAL EXTERNALGAIN AND OFFSET ADJUSTMENTS A connection diagram for the ADCIOHT in the ±IOV input bipolar mode of operation is shown in Figure 3. The gain and offset adjustment resistors (R I and R2) should be selected discrete metal-film or wirewound resistors and not potentiometers if optimum performance is required under high shock and vibration levels. The internal gam and offset errors are laser trimmed to within a maximum error of ±0.2% with 250, 0.1% resistors in place of R I and R2. Another possible approach in many applications is to simply remove the offset and gain errors with digital techniques after the AI D conversion has taken place. This "Ilproach can virtually eliminate ihe need I'or initial gain and offset adjustment and even the effects of gain and offset drift with time and temperature can often be removed. In some cases it may be desirable to use , potentiometers. Gainan'd Offset errors may be trimmed to 'zero using external gain and offset trim potentiometers connected to the ADC as shown in Figures 6 and 7. Multiturn potentiometers with lOOppm/"C or better TCR's are recommended for minimum drift over temperature and time. These pots may be any value from IOkO to 100kO. ADJUSTM,ENT PROCEDURE OFFSET - Connect the Offset potentiometer or resistance substitution boxes as shown in Figure 6. Sweep the input through the 'end point transition voltage that should cause an output transition t~ 'all bits off E °i~' '. '" Adjust the Offset potentiometer or resistor substitution boxes until the actual end point transition voltage occurs at EOi~F. The ideal transition voltage values of the input are giveh iII Table I. ' GAIN - Connect the Gain adjust potentiometer or resistor substitution boxes as shown in Figure 7. Sweep the input through the end point transition vO,ltagethat should cause an output transition to all bits on (E?~). Adjust the Gain potentiometer until the actual end point transition v,?ltage occurs at EY~. " 6-14 Figure 9 shows the effect of clock rate control resistor (RcR) on clock frequency. Figure 9 is based on a typical initial clock frequency of about 400kHz (conversion time of 30ILseC for f2 bits). To determine the required clock frequency: Table I details the transition voltage levels required. It is also possible to make the adjustments just described with potentiometers and then replace the resistive arms with discrete metal film or wire-wound resistors in order to make a system more rugged before subjecting it to harsh environments. +15VDC III fd,d = Bit Re~oluti~n ConversIOn Time For example. if the ADCIOHT is short cycled to IO-bit operation and a conversion time of 20ILsec is required. then IMn @>-----w..---..-IOknID11ICIcn BIPOLAR OFFSET fbi R UNIPOLAR OFFSET ADJUST :=:r. BIPOLAR OFFSET 21 . 50n RI ·15VDC fd'''k 10 =20ILsec = 500k Hz from Figure 9 a clock rate resistor(RcR ) of about 40kO is required. 2.SM BIPOLAR OFFSET ADJUST REF OUT 25 2.0M ~ " 9 ~l.SM FIGURE 6. Optional Unipolar and Bipolar Offset Adjust Circuitry with ±O.4% of FSR Range of Adjustment. ~ c: ~ ! "" 1.0M ~ " () '- SOOk R OUT E F : = : r . 5 50n R2 REF 17 IN BAIN ADJUST o o 10k 20k 30k40k SOk 80k 70k SOk 90k lOOk Clock Adjust Resistor ill I FIGURE 7. Optional Gain Adjust with ±O.4% Range of Adjustment. CLOCK RATE CONTROL (OPTIONAL) Fasler Conversion If adjustment of the clock rate is desired for faster conversion times. a resistor may be connected between Clock Rate (pin 16) and Clock Out (pin 18) as shown in Figure 8. FIGURE 9. Clock Frequency vs Clock Rate Control Resistor (RcR). Slower Conversion The conversion time can be decreased by connecting a capacitor from the Clock Rate pin to Digital Common (see Figure 10). CLOCK Iji\~ RATE -.::/ CLOCK RATE CLOCK OUT ~ 6 18 RCR CLOCK FREQUENCY ADJUST FIGURE 8. Optional Clock Rate Adjust for Faster Conversion Times. DIGITAL 1 _ _ _ _ _---. ~--'-____--..JJ_ Ii4\- CCR COMMON \:.:I FIGURE 10. Optional Clock Rate Adjust for Slower Conversion Times. 6-15 Figure II shows the effect of. the clock rate control capacitor on the clock frequency. 54COO QUAD 2·INPUT NAND GATE 1M N lOOK CONNECT TO n + , BIT CONVERT 201 ' -_ _ _ _ _ _ _ _ _ _ _......J COMMAND T 1\ J: FIGURE 12. Short-Cycle Circuit which Provides for Lower Resolutions than 12 Bits with Faster Conversion Times and Continuous Conversions. I\, Table III indicates where to connect the short cycle input for 8-bit and 10-bit resolution and gives possible conversion time(s) obtainable by using this feature along with the clock rate pin. "- 10K ~ TABLE III. Short Cycle Connections and Specifications for 8 to 12 Bit Resolutions. Resolution (Bits I lK o Connect SHORT CYCLE to: 4 6 8 10 12 14 16 18 20 22 Conversion Time .Clock Adjust Capacitor I nF I Nonlinearity at +25°C ADC10HT ,'lOaf FSR, ADC10HT-l FIGURE II. Clock Frequency vs. Clock Rate Control Capacitor (Cl"R). The serial output data (pin 28) is synchronous with the internal clock. In some applications the clock frequency must be lowered to 3kHz or 4kHz so that the data can be transmitted over long distances. If 12-bit resolution is required, the conversion time for 4kHz is .. 12 bits conversIOn lime = -4-- = 3msec kHz From Figure II, a clock rate control capacitor, Cl"R, of approximately 16nF is required. In applications requiring such a slow conversion time, a low-pass filter should be used at the analog input to the ADCIOHT. SHORT-CYCLE AND CONTINUOUS CONVERSION OPERATION. The ADCIOHT may be operated at faster speeds for resolutions less than 12 bits by using the clock rate control feature. The conversion time can be further increased by using the short cycle circuit shown in Figure 12. Without this circuit, the status signal (pin 19) will always remain high for 13 clock pulses even if only 8 bits are being used. By connecting the short cycle input of the NAND gate to the n + I bit (connect to bit 9 for 8-bit operation, for example) the conversion will be completed and the status signal will go low after n + I clock pulses (9 pulses for 8-bit operation). It should be noted that with the circuit shown in Figure 12, the ADC 10HT will operate in a continuous conversion mode, i.e .• a new conversion will start on the n + 2 clock pulse without the need for an external convert command. Ip58CI(1) 12 10 8 N/A Pin 2 Pin 4 24 10 6 ±0.012 ±O.O48 ±0.048 ±0:048 ±O.l ±O.l NOTE: (11 Adjust Conversion Time with Clock Rate ContrOl resistor as shown in Figures 8 and 9. For 12-bit operation and' continuous conversion. simply connect status (pin 19) directly to convert command (pin 20). OUTPUT DRIVE Normally the ADCIOHT logic outputs will drive two low power TTL loads or one LSTTL load. Iflong digital lines must be driven. external logic buffers are recommended. The digital outputs are connected directly to the internal CMOS successive-approximation-register and can drive +5V CMOS without the need for pull-up resistors. HEAT DISSIPATION The ADCIOHT dissipastes approximately 750mW and the package has a case-to-case ambient thermal resistance (8",d of 35"C/W. For optimum performance at +200"C, 8"" should be lowered by a heat sink or by forced air over the surface ofthe package. If the converter is mounted on a PC card. improved thermal contact with the copper ground plane under the package can be achieved by using a silicone heat-sink compound. LOW POWER OPERATION The typical supply currents required by the ADCIOHT under normal operating conditions are 15mA (+ 15V). 30mA (-15V). and 16mA (+5V). The average power required (PIl) is therefore PIl = IISmA x ISVi + 130mA x -ISVi + 116mA x 5Vi 755mW. 6-16 The point where the two curves cross is the zerotemperature-coefficient bias current. +Vs and/ or RII should then be adjusted accordingly for this optimum operating current. Under certain operating conditions this power consumption can be reduced to as little as 2S0mW. The ADCIOHT is completely self-contained with an internal + lOY reference voltage. The + ISV supply is used only to supply power for the op amp current source and zener diode used in this reference. Ifan external reference is available. the + ISV supply is not required and it can be removed. This reduces the p" by ISmA x ISV = 22SmW. The average P" for the ADCIOHTis therefore reduced to S30mW. The major contributor to the power consumption is the -ISV supply. As long as a +IOV reference is used. the Vsupply voltage must be between -13V and -16V. If. however, a lower voltage reference is used, this V- supply voltage can be reduced considerably which greatly reduces the power consumption. Lowering the reference voltage will, of course, lower the full scale input voltage by a proportional amount. For example, if the reference voltage is +SV, the full scale input voltage for the lOY range input (pin 22) will be +SV, instead of +IOV with a + IOV reference, in the unipolar mode of operation. Table IV indicates the minimum supply voltages and the typical power consumption obtained when using these supply voltages for various values of VRH. IZ = (Va - VzJ/Ra ~ Ra IZ I +VLOGIC -Vs rPin27) Total Power Consumption VREF (Pin 151 (Minimum) (Typical I +10V +5V -13V 470mW +6.3V +5V -10V 300mW +5V +5V -BV 250mW Vz IZERD T.C. Vz VZERD T.C. FIGURE 14. Simple Techniques for Obtaining a Low Drift Reference Voltage. This procedure is also discussed in a Burr-Brown Application Note: "Squeeze High Performance out 01 Low-Cost Hybrid Data Converters, AN-86. Other Application Notes Burr-Brown also has other Application Notes of interest to the converter user. In particular: "What Designers Should Know About Data Converter Drift." AN-89. "Correcting Errors Digitally in Data Acquisition and Control," AN-IOI. TABLE IV. Minimum Power Supply Voltages and Typical Power Consumption for Operation with External VREF. (Note: +ISV is not required if internal VREF is not used.) External IZ s OPERATION WITH EXTERNAL CLOCK LOW-POWER EXTERNAL REFERENCE A simple external reference voltage can be made with a single resistor and a zener diode as shown in Figure 13. The power consumed by the reference is only about 7SmW with +Vs = +IOV. The power supply sensitivity of this reference is approximately ±O.02% of FSRI %Vs. Figure IS shows the internal clock circuit of the ADCIOHT. To operate with an external clock. first connect the Clock Rate Control (pin 16) to ground. "this will shut off the internal clock and also turn off the open collector output transistor of the LM 119 comparator. The Clock OiJt(pin 18) will then be ina "high"state(+SV) because of the 2kO pull-up resistor to +5V. Now simply use the Clock Out pin for the external clock input. Note that the external clock must have the capability of sinking 2.5mA when it is in the low state due to the 2k!l pull-up resistor. ;>+V. 480n INOMINAlI ...-----<--0 +6.3V ~ CD825 ICOMPENBATED DEVICESI -:::- ±2Oppm/oc - IB.3IU! FIGURE 13. Simple +6.3V External Reference That Requires Only 7SmW. 5kn A very simple procedure can be used to'obtain the lowest possible drift with this reference. First, vary the zener current from about 4mA to II rnA by changing either the bias voltage, +Vs, or bias resistor, RH, and plot Vz versus Iz as shown in Figure 14. Next, heat thle zener (the exact temperature is not important, but it smould be near the desired operating temperature), and repeat the procedure. IOIU! 5kn TOBAR FIGURE 15. ADCIOHT Internal Clock. 6-17 BURR-BROWN@)' ADC60 IElElI High Speed ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • FAST CONVERSION SPEED: 12-blts - 3.5Ilsec. max 10-blts - 1.881l1ec. max 8-blts - O.881l1Ic. max Throughput sampling rates from 250kHz (12-bltsl to 1MHz (8-blts) can be attained • PIN-PROGRAMMA8LE UNIPOLAR OR 81POLAR • ANALOG SIGNALS • SERIAL AND PARALLEL DATA OUTPUTS • SELF-CONTAINED WITH INTERNAL CLOCK 8. REFERENCE Simplifies system design and reduces cost The Model ADC60 is a very high speed, successive approximation AI D converter than is designed for applications requiring system throughput sampling rates from 250kHz to I MHz. The fast conversion speed is accomplished with proprietary fast settling circuits which preserve linearity and drift while permitting conversion speeds up to 100nseci bit. Available in 8-, 10-, and 12-bit resolutions the ADC60 contains an internal reference and clock. Internal components 'are provided for pinprogrammable analog input signal ranges of±2.5V, ±5V, ±IOV, 0 to +5V, 0 to +lOY and 0 to +20V. Digital data is available in both serial and parallel, binary form with corresponding timing signals. All digital input and output signals are bTL/TTLcompatible. The ADC60 operates from ±15VDC and +5VDC power, and is housed in a 2" x 4" xO.7Y module with screened-on pin function identification. • ±1I2LS8 LINEARITY Provides accurate conversion • NO MISSING CODES Gain Adj. Sig.Com RZ Rt j! &i "! u ! BP 0"111 Camp. In ReI. Out Ana. Com ·15VDC +15VDC +5VDC Dig. Com SerlllOut Stitul Conv. Com Clock Out Bit t (MSBI Bit 2 Bit I IMS81 81t3 Blt4 Bit 5 Bit6 Bit 7 81t8 Blt9 Bit 10 Bit 11 81t 12 Short f!E! Status Internltlonll Airport Industrial Park - P.O. Box 11400 - Tllt:Son. Arizona 85734 - Tel.'(IIOZl 746-1nl - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 PDS-319A 6-18 THEORY OF OPERATION TIMING CONSIDERATIONS Data is available in both serial and parallel form. Timing signals are available for the transfer of data to external devices. For parallel data transfer. Status and its compliment Status indicate when the conversion is complete. For serial data transfer. the Clock Out signal starts on the trailing edge of the Convert Command; and serial data is valid before the positive going edge of the Clock Out signal. The Clock ceases operation when the conversion is complete. There will be one more clock pulse than the number of bits converted (resolution). Figu{e I shows the timing details of the ADC60. Upon receipt of an external Convert Command. the previous data sample is cleared from the output register. Each bit is then successively compared against the amplitude of the input signal. and is either held as a "0" or turned on as a "I" until all bits have been tried. The parallel data output is not available for transfer to external devices until the Status output changes from logic "I" to logic "0". Serial data is only available during conversion. and must be transferred to external devices with the Clock and Status signals beginning with the first clock pulse following a change in Status from logic "0" to logic "I ". ~CCH.I. Convert Clock Out I n ----' I I I I I I I Status .....JT,I-: L--- T n . I_I!:T OLY I I t= I 'I I hi I I I -! I -I I--T2 TCT ~T3H n I ~t----j I I I T3L.....I Bit' I (MSB[:-_-.f _-_~J r-L CP----"'Iri.. I ~ -----------\.1 • I TiJw I I I - -_ _ -_ -1- _ - II I_I -_-_-_-_ _ serial Out Bit' TCCL ~ Command i 1'--_ _ _ _-' ~TSET I II I I I-- 1 r - .!!t~· - -,__ J II B:t 2. • ~~---I- I I u Bit2 r'-----; I ::.: I:': J"] !-------:-,-~U: Bit 3 ::: Bit N .: I : Bi: N : n ~---- I I r'-----~-----_, -=.!-='::"J..J ~I I (LSBC: 1.1 : I I -..Il.-T4 I =1 :: ::: ~ _r .----~-7-------.,--~·~ ,.- '.L._____--": FIGURE 1. ADC60 Timing Diagram. TABLE I. Switching Characteristics. PARAMETER SYMBOL TCT TCCH TCCL T1 T2 T3H DESCRIPTION Conversion Time - 12 Bit 10 Bit 8 Bit Width of Convert Command Pulse MIN. 2.50 1.20 0.80 30 Internal Between Convert Command Pulses (TCT + T1 + T DLy ) Delay From Trailing Edge of Conv. Command To Leading Edge of Clock Out Delay from Co~v. Command To Reset Delay From Valid High Output To Trailing Edge of Clock Out TYP. 3.45 1.83 0.84 --- MAX. 3.50 1.88 0.88 UNITS I'SI'c /lSec I'SI'c --- moe (I) 30 41 60 naec 26 40 68 nsee 22 43 70 nsee T3L Delay From Valid Low Output To Trailing Edge of Clock Out 30 51 72 nsee T4 T DLy Delay From Valid Data to STATUS LOW 12 18 37 Delay From Clock Out to S:rATUS HIGH 22 44 60 nsee oSee osee TSET Setup Time from Status to Cony. Command - (2) TCW TCp Clock Out Width Clock Out Period - (3) 12 Bit 10 Bit 8 Bit NOTES: 1. ADC60 internal clock may be inhibited !ly returning the convert command to "1". By this technique, the converter may be cycled'through an entire conversion one clock pulse at a fime. This technique allows the conversion time to be extended to virtually any conversion time. 6-19 0 - -- 40 50 60 192 104 88 265 165 95 270 171 98 mec mec nsec nsec 2. The convert command may rise as soon as the last clock out pulse rises. 3. The clock period for ADC60 it not necessarily constant throughout the conversion time. SPECIFICATIONS ELECTRICAL MECHANICAL NOTE: Lelds in true position wIthin .015" 1.38mm) R @ MMC at seating plane. Typical at 25°C and rated power supplies unless 'otherwise noted. MODEL RESOLUTION I I ADC6C1-10 ADCIO-G8 J 8 10 I I ADC6Cl-12 12 I I UNITS Bill INPUT r--'~ ANALOGINPtJTS ±2.S, ±5, ±10 a to +5. a to +10. a to +20 0.2 V V klliV FSR Positive Pulse 30nsec wide ,min. Trailing edge ·"1" to "a" initiates conversion. 2 TTL Loads Voltage Ranges. Bipolar Voltage Ranges. Unipo.lar Impedance CIJ DIGITAL INPUTS(11 Convert Command Logic Loading ±0.2 ±0.2 ±O.195 ±0.19 ±0.27 ±0.1 ±0.1 ±0.0488 ±0.048 ±0.088 Guaranteed Guaranteed ±0.002 ±O.1 ±0.1 ±0.0244 ±0.012 +0.024. -0.019 % of FSR131 % of FSR % of FSR % of FSR % of FSR C CONVERSION SPEED, max , ••••• +t+t+ttft................... pede!lO 0.88 ±20 +40 L88 ±15 +30 3.5 •c ppm/oC ppm/oC 0 G ",sec H K DIGITAL DATA L p Output Drive Serial Data Output ori.ve Status Status Output Drive of Status and Status Clock Clock Output Drive INTERNAL REF. VOLTAGE Max External Current with no degradation of Specifications R USB straight binary BOB I offset binary I and BTC I Two's Complement, 6 6 "1" During Conversion "0" During Conversion 6 A Positive Pulse Train Used for Strobing Serial Data into an External Register. TTL Loads TTL Loads TTL Loads 9 TTL Loads 6.3 V 200 ~A ±15 and +5 ±14.5 to .±15.5 and +4.75 to +5.25 +50 -50 +270 V V rnA rnA rnA POWER REQUIREMENTS Rated Voltages Range for Rated Accuracy SupplY Drain +15V Supply Drain -lSV I maxI Supply Drain +5V PACKAGE 2" x 4" x 0.75" MAX MIN MAX 1.950 2.010 49.63 51.05 1.950 2.010 49.53 51.05 .350 4.10 8.89 10.41 .021 .019 .100 BASIC .150 .250 .250 .300 1.800 BASIC .200 BASIC .050 .150 °C -25 to +85 -55 to +100 °C °C GllnAd;~ Slg.Cam 3 R2 5 RI~ 8PO"'at~ camp.ln NOTES: 1. All digital inputs in the ADC60 are TTL compatible 1I.e .• Logic "a" ~0.8V max. Logic "1"~ 2.0V. min. 2. Gain and Offset Errors may be adjusted to zero with externa~ trimming. 3. FSR means Full Scale Range. 4. TTL compatible. Logic "a" ~ +0.4V. max. Logic "1" ~ +2.4V. min. g RII.Out 22 AnLC"'~ -15VOC~ 8 +15VOC +5VOC 2. Dig. Com 30 SorlllOut§ SIItu133 Con •. C.m ~ Clock 0.( 3 ·Specifications; same for all models. 0.48 0.53 2.64 BASIC 3.B1 6.35 7.62 6.35 45.72 BASIC 5.08 BASIC 1.27 3.81 CONNECTION DIAGRAM =;:L2kll D/A ~~ Oto +70 MILLIMETERS MIN Material: Case - Diallyl Phthalate Shelf. Weight: 50l. Mating Connector: 2400MC - PC Card & Terminals 2401MC - Set of four la-pin connector strips. Pin spacing located on 2.S4mm 10.10" I grid. Allow 5.08mm 10.20"1 between pins 18-19 and 54-55. Pin material and plating composition meet method 2003 {solderability I of MIL-STo-883 I except paragraph 3.21. TEMPERATURE RANGE Specification Operating COMPARATOR IN L----o REF OUT (+6.3VI I-------~OCLOCK OUT L---------------oSTATUS ' - - - - - - - - - - - - - - - - - 0 SERIAL OUT Internalional Airport Industrial Park· P.O. Box 11400 . Tucson. Arizona B5734 . Tel. (6021 746·1111 . Twx: 910·952·1111 . Cable: BBRCORP . Telex: 66·6491 PDS-432A 6-32 SPECIFICATIONS Typical at +25°C and rated power supplies unless otherwise noted. ADC72JM,KM MODEL MIN I ADC72AM,BM I TYP MAX MIN I TYP le RESOLUTION I MAX UNITS 16 Bits INPUT ANALOG Voltage Ranges Bipolar Unipolar ±2.5, ±5. ±10 o to +5. 0 to +10. o to +20 ±2.5. ±5. ±10 o to +5. 0 to +10, o to +20 V 2.5 5 10 2.5 5 10 kll kll kll Impedance (Direct Inputl o to +5V, ±2.5V o to +10V, ±5.0V o to +20V, ±10V DIGITAL(1) Convert Command Logic Loading V Positive pulse 50nsee wide I mini trailing edge 1"1" to "0" initiates conversion I 1 1 TIL Load TRANSFER CHARACTERISTICS ACCURACY Gain Error(2) Offaet Gainl2) Unipolar Bipolar linearity Error KM,BM JM,AM Inherent Quantization Error Differential linearity Error ±C.l ±C.2 ±C.l ±C.2 % ±C.OS ±C.l ±0.1 ±0.2 ±0.003 ±0.05 ±C.l ±0.1 ±0.2 ±C.OO3 % of FSRI3) % of FSR %ofFSR %ofFSR LSB %of FSR ±1/2 ±C.C03 POWER SUPPLY SENSITIVITY ;t15VDC +5VDC ±1/2 ±0.C03 ±C.OO3 ±C.COl CONVERSION TIMEI4),14 Bits, WARM·UP TIME ±C.OO6 ±C.OO8 % of FSRI%.1Vs % of FSRi%.1Vs ±C.OO3 ±C.COl 50 50 10 10 ~sec min DRln Gain Ottset Unipolar . Bipolar linearity No Missing Codes Temp Range JM, AM 113 bits) KM, BM 114 bits) ±10 ±20 ±7 ±15 ppm/fC ±2 ±8 ±2 ±4 ±10 ±3 ±5 ±2 ±10 ±2 ppm of FSR/DC ppm of FSR/DC ppm of FSRfOC +50 +40 DC +50 +40 0 +10 0 +10 oC! OUTPUT DIGITAL DATA I All codes complementary Parallel Outp~t CodeslS) Unipolar Bipolar Output Drive Serial Data Code, N RZ , Output Drive Status Status Output Drive Internal Clock Clock Output Drive Frequency INTERNAL REFERENCE VOLTAGE Max External Current with No Degradation of Specs Temp Coefficient POWER SUPPLY REQUIREMENTS Power Consumption Rated Voltage. Analog Rated Voltage, Digital Supply Drain +15VDC Supply Drain ·15VDC Supply Drain +5VDC TEMPERATURE RANGE Specification Operating I derated specs Storage I CSB COB, CTC(G) 2 CSB. COB 2 Logic "1" during conversion 2 TTL Loads TTL Loads 2 6.3 6.6 6.0 6.3 ±200 +10 ±14.5 +4.75 0 -25 -55 1.3 ±15 +5 +45 ·35 +70 TTL Loads TTL Loads kHz 6.6 V ±200 ±5 ppm/DC 280 280 6.0 2 2 ±15.5 +5.25 ±14.5 +4.75 +70 +85 +125 -25 -55 -55 6-33 1.3 ±15 +5 +45 -35 +70 ~A W ±15.5 +5.25 VDO VDC, mA mA mA +85 +85 +125 DC DC 'C NOTES: 1. DTL/TTL compatible, i.e., Logic "0" =0.8V, max. Logic "1" = 2.0V, min for inputs. For digital outputs Logic ''0'' = +O.4V: max. Logic "1" = 2.4V, min. 2. Adjustable to zero. 3. FSR means Full Scale Range. For example, unit connected for ±10V range has 20V FSR. 4 ..Conversion time may De snortenea wltn "~non '-'YCIe. set Tur luwer reSOII,Jtlon, see "AOaltional Connections "Required" section. 5. See Table I. CSB -Complementary StralghI'Bi"ary. COB - Complementary Oflset Binary:CTC - Complementary Two's Complement. 6. CTC codina obtained bY invertinQ MSB IPin 11. . MECHANICAL INCHES MIN MAX 1.720 1,7150 DIM A 1.120 .170 D G 1.180 .250 .0115 .001 .100 BASIC .100 .140 .1S0 .300 .9008ASIC .100 .140 MILLIMETERS MIN MAX 43.69 44.70 ..... 4.32 0.41 29.48 6.36 0.&3 2." ..... 3.81 7.82 2.64 BASIC 22.86 BASIC 2." 3.66 rF4 ~~:. . . . . .,:. ~'1 C- "NOTE: Leads in true position within .010" 1.255mm I R at MMC at seating plane. Pin numtMIrslhown for r.terence on1v. lIfumbel'l may no, be marked on pllCk . . . CASE: Nickel·plated kavar MATING CONNECTOR: 2302MC WEIGHT: 13 grams (0:48 oz.) ••• " " " ' . ' •• 11 Denotelpln 1 L-J l ! ) :---Iu Ii Ii 1\11 Ii• iii I 4 -01 I.--&.I.-- , ---oJ T G CONNECTION DIAGRAM TOP VIEW IMSBIBit 1 (1j:::::::::~----~~::::::::::::::t3:0 SHORT CYCLE CONVERT COMMAND- Bit 2 Bit3 +5VDC SUPPLY Bit4 ~AIN BitS' +1SVDC SUPPLY ADJUST lilit6 COMPARATOR IN Bit7 BIPOLAR OFFSET Bit8 10V Bit9 20V Bit 10 fiEF OUT, 6.3V Bitl1 ANALOG COMMON Bit 12 -15VDC SUPPLY ,LSB for 13 bits, Bit 13 CLOCK OUT ,LSB lor 14 bits, Bit 14 DIGITAL COMMON Bit 15 Bit16 t~~~~~~~~~~~~~;t:::::;~ SERIAL STATUSOUT °If an external clock is used, connect the clock to pin 31 ,CONVERT COMMAND TYPICAL PERFORMANCE CURVES POWER SUPPLY REJECTION VS POWER RIPPLE FREQUENCY GAIN DRIFT ERROR ('III OF FSR) VS TEMPERATURE 0.1 +0.10.-------:-------------;---, +O.08+------+-~----------___:o~e---_t ffiu. +0.08 04 .7lfiffIiij;iiiifi1lll/l ~ +0.02 'O+O. 0 w -0.02 #I-I-I+I-,I-I+.f-I-I..st~~=-+_~5i:::;!~!fQllf,R:/ij~tlP.fH1'+Htffi g ~ ~.04~~~~~-4~~------~------~~~~~~~tH+HfH c -0.08 +---------7-----------+----------......;"""~~<---__=t 'iI (!l -0.08 f-.-------l-----i----------=""'I----I -0.10 L..;_ _ _-"-_ _ _ _!..-_ _ _ _ _ _ _" - _..... -25°C OGC +25°C Temperature (OC) +7OGC 0.06 .~ ."'" c -15~~C 0.04 0.02 ti '0 0.0 1 # ~ ),006 e 0.004 35u. 0.002 Ui '0 # L / 1 +'15VDC -L +5VDC b/ ../ 0.001 1 6-34 L L / i£ 10 100 1k Frequency I Hz' 10k lOOk DISCUSSION OF PERFORMANCE 0000.•0000 0000...0001 The accuracy of a successive approximation AI D converter is described by the transfer function shown in Figure I. All successive approximation AI D converters have an inherent Quantization Error of±1/2 LSB. The remaining errors in the AI D converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. I n summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AI D converter. A Differential Linearity error of ± I 12LSB means that the width of each bit step over the range of the AI D converter is ILSB, ±1/2LSB. The ADCn is also monotonic, assuring that the output digital code either increases or remains the same for increasing analog input signals. Burr-Brown also guar- 0111 ...1101 0111 •.1110 0111...1111 h t---~~t--~f1"+--1 1000...0000 1000...0001 1111...1110 1111 ...1111 Off.11 : ;t:Erro\ f~~ L. ·FSR '" Anllog Inpul 2 ElnOFF.. 'Saa Table I lor digital cade dlflnltlons. I I ElnON! _FSR .1 LSB 2 FIGU RE I. Input vs Output for an Ideal Bipolar A D Converter. antees that these converters will have no missing codes over a specified temperature range when short-cycled for 14-bit operation. TIMING CONSIDERATIONS The timing diagram (Figure 2) assumes an analog input such that the positive true digital word 1001 1000 1001 0110 exists. The output will be complementary as'shown in Figu~e 2 (011001 I 10110 1001 is the digital output). Convert command lll Inlemal Clock SlatuaIEOC) MSB BII2 BII3 BII4 BI15 BII6 BI17 BII8 BII9 Blll0 BIl11 BII12 BII13 BII14 BII15 :::::::::J -J~ _______=I"o="~____________________________~r----- -r 1''0' r--- J L-j"I" ==_J ==-=J ==:J __ J ___ J ::::_J -::::J L-j"I" LJ1" .L.J"I" 1"0" L-j''1'' L-j"r' ___ J U"I" ---j~________~~____________________~I= . u=·~~ ___ J BII16 Sari11 13) Data Oul NOTES: 1. The convert command must be al leaal 50nSIC wide and musl remain low during a converilon. The conversion is inllilled by the ..trslling edge" 01 the convert command. 2. 57 "sec for 16 bill. 3. Uae trailing edge of clock to strobe serial output. FIGURE 2. ADCn Timing Diagram. 6-35 __ ~r-- r-- DEFIN.ITION OF DIGITAL CODES SERIAL DATA Two straight binary (complementary) codes are a~ailable on the serial output line CSB and COB. The serial data is available only during conversion and appears with the MSB occurring first. The serial data is synchronous with the internal clock as shown in the timing diagram of Figure 2. The LSB and transition values shown in Table I also apply to the serial data output except for the CTC code. PARALLEL DATA Two binary code.s are available on the ADCn parallel output; th\!y are complementary (logic "0" IS true) straight bin;try (CSB) for unipolar input signal ranges and complementary· offset binary (COB) for bipolar input signal ranges. Complementary two's complement (CTC) .may be obtained by inverting MSB (Pin I). ' Table I shows the LSB, transition values, and code definitions for each possible analog input signal range f~r 12-, 13- and 14-bit resolutions. Figure 3 shows tlte .connections for 14-bit resolution, parallel data outPllt, with ±IOV output. : iHid ilniiira- --, axtlrnel cannlClllIIIl. -tliVDC +15VDC r---I)UJ·-M....... I10. _ _ _ IOknlD lOOkn GAIN ADJUST IOll1lla lOOkn I"F OFFSET ADJUST ADC72 ,---I"F I I I -; AIIALOG COMMON ·15VDC I"F I DIGITAL COMMON STATUS OUTPUT 10 l-----~ CONTROL LOGIC • Cljllc111r lllauid bl cannlClad IVln It allernel glln Idlmll nil und. FIGURE 3. ADCn Connections For: ±IOV Analog Input, 14-Bit Resolution (Short-Cycled). Parallel·Data Output. TABLE I. Input Voltages, Transition Values, LSB Values. and Code Definitions. Binary IBINI Output Analog Input Voltage Range INPUT VOLTAGE RANGE AND LSB VALUES Defined As: Code Designation One Least Significant Bit ILSB, FSR ±10V ±5V ±2.5V oto +10V Oto +5V Oto+20V COBI') orCTC(2) COB(1) orCTC(2) COB(1) orCTC(2) CSBI31 CSB(3) CSB(3) 20V 10V ~ 20 Tn n= 12 . n= 13 n = 14 4.88mV 2.44mV 1.22mV 2" 2.44mV 1.22mV 61O"V 2" d!2mV 610,,11 305"V Tn fN Tn gQy 2.44mV 1.22mV 610"V 1.22mV S10"V 305"V 2" 4.88mV 2.44mV 1.22mV 10V .. Transition Values MSB LSB 000 ... 000141 01Llll 11Lll0 +Full Scale Mid Scale -Full Scale +10V -3/2LSB +5V -3/2LSB +2.5V -3/2LSE 10V -3/2LSB +5V -3/2LSB +20V -3/2LSE . +10V 0 +5V +2.5V 0 0 -10V +1/2LSB -5V+l/2LSB -2.5V +1/2LSB 0+ 1/2LSB 0+ 1/2LSB 0+ 1/2LSB (1)COB = Comp·lementarv Offset Binarv (2) CTC = Complementary Two's Complement - obtained bv inverting the most significant bit. MSB (P-in 1.1 6-36 (3) CSB = Oomplementary Straight Binary (4) Voltages given are the nominal value for.transition to the code specified. DISCUSSION OF SPECIFICATIONS The ADC72 is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an AI D converter are linearity, drift, gain and offset errors, and conversion speed effects on accuracy. This ADC is factory-trimmed and tested for all critical key specifications. connecting external trim potentiometers as shown in Figures 6 and 7. POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The ADC72 power supply sensitivity is specified for ±0.OO3% ofFSR/%~Vs for±15V supplies and±O.OOI% of FSR/%~ Vs for +5V supplies. Normally. regulated power supplies with I % or less ripple are recommended for use with this ADC. See Layout Precautions, Power Supply Decoupling and Figure 4. GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to typically ±O.l% of FSR (typically ±0.05% for unipolar offset) at 25°C. These errors may be trimmed to zero by LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECATUIONS Analog and digital common are not connected internally in the ADC72 but should be connected together as close to the unit as possible, preferably to a large plane under the ADC. If these grounds must be run separately, use wide conductor pattern and a O.oI~F to O.l~F nonpolarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The comparator input (Pin 27) is extremely sensitive to noise. Any connection to this point should be as short as possible and shielded by Analog Common or ±15VDC supply patterns. POWER SUPPLY DECOUPLING INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AI D converter. Connect the input signal as shown in Table II. See Figure 5 for circuit details. TABLE II. ADC72 Input Scaling Connections. The power supplies should be bypassed with tantalum or electrolytic type capacitors as shown in Figure 4 to obtain noise free operation. These capacitors should be located close to the ADC. Bypass I~F electrolytic type capacitors with O.OI~F ceramic capacitors for improved high freq uency performance. +5VDC -4--1. .+--@) I ~4.-------~---~~ I~F DIGITAL COMMON Input Signal Range Output Code Connect Pin 26 To Pin Connect Pin 24 To Connect Input Signal To Pin ±10V ±5V ±2.5V o to +5V o to +10V o to +20V COBo,CTC' COB 0' CTC' COBo,CTC' CSB CSB CSB 27 27 27 22 22 22 InputSig. Open Pin 27 Pin 27 Open Input Sig. 24 25 25 25 25 24 Obtained by inverting MSB I Pm 11. ·15VDC @.---....~-~~~ ..1. I ~F t::\ 1 + ANALOG COMMON CDMP.! ~--"'---I~~ IN J+ ~ I~F ~ @--"'--+-15"'VD~C BI~~.!1 OFFSET +VREF FIGURE 5. ADC72 Input Scaling Circuit. FIGURE 4. Recommended Power Supply Decoupling. OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS external adjustment is required. Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC as shown in Figures 6 and 7. Multiturn potentiometers with 100ppmj"C or better TCR's are recommended for minimum drift over temperature and time. These pots may be any value from 10k!} to lOOk!}. All resistors should be 20% carbon or better. Pin29 (Gain Adjust) and Pin 27 (Offset Adjust) may be left open if no ADJUSTMENT PROCEDURE OFFSET - Connect the Offset potentiometer (make sure R 1 is as close to pin 27 as possible) as shown in Figure 6. Sweep the input through the end point transItion voltage that should cause an output transition to all bits Off (EO,':). 6-37 Adjust the Offset potentiometer until the actual end point transition voltage occurs at EOi~. The ideal transition voltage values of the input are given in Table I. The external clock pulse must be a negative-going pulse with a width between 100nsec and 200nsec as shown in Figure 2, and must be. at a lower frequency than the internal clock. +15VOC II) .. 1.8Mn ® 'M ADDITIONAL CONNECTIONS REQUIRED The ADCn may be operated at faster speeds for resolutions less than 14 or 13 bits, depending on the model selected, by connecting the Short-Cycle Input, pin 32, as shown in Table III. Conversion speeds, linearity, and resolutions are shown for reference. 10kn to lOOkn COMPo tN OFFSET ADJUST ·15VDC +15VDC Ib) lDn 27 TABLE III. ~nort-Cycle Connections and Specifications for 12- to 14-Bit Resolutions. 180kn lOknto lOOkI! COMP.IN 22k1! OFfSET ADJUST FIGURE 6. Two Methods of Connecting Optional Offset Adjust with a O.4l1i of FSR Range of Adjustment. GAIN - Connect the Gain adjust potentiometer as shown in Figure 7. Sweep the input through the end point transition voltage that should cause an output transition to all bits on (E~~). Adjust the Gain potentiometer until the actual end point transition voltage occurs at E~~. Table I details the transition voltage levels required. +15VDC GAIN ADJUST ANALOG COMMON . 510kn f ~ lOkI! to lookn ~l' O.01.F @-' GAIN ADJUST 14 13 12 Pin 15 Pin 14 Pin 13 Maximum Conversion Speed 'Jlsec,(l) 50 46.5 43 Maximum Nonlinearity at 25°C ,% of FSR, 0.003·(21 0.006 0.006 NOTES: 1. Max. conversion time to maintain specified nonlinearity error. 2. 8M and KM models only. ·15VDC -=-=- Resolution I Bits I Connect Pin 32 to OUTPUT DRIVE Normally all ADCnlogic outputs will drive 2 standard TTL loads; however, if long digital lines must be driven, external logic buffers are recommended. HEAT DISSIPATION The ADC72 dissipates approximately 1.3 watts (typical) and the packages have a case-to-amDlent thermal resistance (OCA) of 25"CjW. For operation above 70"C, OCA should be lowered by a heat sink or by forced airover the surface of the package. See Figure 8 for OeA requirement above 70"C. If the converter is mounted on a PC card, improved thermal contact with the copper ground plane under the case can be achieved using a silicone heat sink compound. On a 0.062" thick PC card with a 16 square inch (min.) area, this technique will allow operation to 85"C. ·15VDC 25i----...... ~ FIGURE 7. Connecting Optional Gain Adjust with a 0.6 1ii Range of Adjustment. ~ ~ EXTERNAL CLOCK If an external clock is used, connect the external clock to convert command, pin 31. The convert command shown in Figure 2 is not used. After each conversion is completed, a new conversion cycle will automatically start on the first falling edge of the external clock following the completion of conversion. The clock out signa) will remain as shown in Figure 2 even if an external clock is used. . 10 60 70 80 Ambient Temperature IOC) FIGURE 8.0(.\ Requirement Abov.e 70"C. 6-38 ORDERING INFORMATION MODEL ADC72JM ADC72KM ADC72AM ADC72BM TEMPERATURE RANGE O"C to +70"C O"C to +70"C -25"C to +85"C -25"C to +85"C NONLINEARITY ±O.OO6% ±O.003% ±O.006% ±O.OO3% 6-39 FSR FSR FSR FSR BURR-BROWN8 ADC76 IElElI 3# AID caNV~RTe.H ~. , ADCT$JO , "t¥ Win Wk y;'\ 16-Bit Hybrid ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • lII-BIT RESOLUTION • LINEARITY ERROR :±fI.D03% MAX (KGI • COMPACT DESIGN 32-Pln Ceramic Packlge • LOW COST .15~.ec CONVERSION TIME (l4-BITJ The ADC76 is a low cost. high quality. 16-bit successive approximation analog-to-digital converter. The ADC76 uses state-of-the-art IC and lasertrimmed thin-film components and is packaged in a convenient 32-pin dual-in-line package. The converter is complete with internal reference. short cycling capabilities. and thin-film scaling resistors. which allows selection of analog input ranges of ±2.SV. ±SV. ±IOV. 0 to +SV. 0 to +IOV and 0 to +20V. Data is available in parallel and serial form with corresponding clock and status output. All digital inputs and outputs are DTL/TTL compatible. Power supply voltages are ±ISVDC and +SVDC. ..-----"0 SHORT CYCLE r----oCOIVERT COMUNO \ PARALLEL DIGITAL OUTPUT I IiPUT .......- - 0 RANGE SELECT ~t----------o COMPARATOR II .-:-::-1---------0 CLOCK RATE CDMTROL CLOCK OUT L......-------------o STATUS L......---------------40 SERIAL OUT IntnIllGIIII AlfIIIWllndtlllrlll Plrk· P.O. Box 11400· TUClan. ArlZOlll 85734· Tal. (602( 7411-1111 • Twx: 9111-1152·1111 • Clble: BBRCDRp· Tallx: 66-6491 PDS-446 6-40 THEORY OF OPERATION The accuracy of a successive approximation AI D converter is described by the transfer function shown in Figure I. All successive approximation AI D converters have an inherent Quantization Error of ±I 12LSB. The remaining ~rrors in the AI D converter are combinations of analog errors due to the linear circuitry. matching and tracking properties of the ladder and scaling networks. pO,wer supply rejection. and reference errors. ,In summary. these errors consist ofinitial errors including Gain. Offset. Linearity. Differential Linearity. and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AI D converter. A Differential Linearity error of±1 12LSB means that the width of each bit step over the range of the AI D converter is I LSB. ±1/2LSB. The ADC76 is also Monotonic. assuring that the output digital code either increases or remains the same for increasing analog input signals. Burr-Brown also guarantees that this converter will have no missing codes over 0000...0000 r.. B ~ .... E 0000...0001 00" ... "00 0011._1101 ~ t' 10lI0._0000 OfFIET I I ,.-- f _~ ~~ - : l----;.-+"~-_I'tt+_t 0" Ul11 l11L1110 l11Ul11 :!!!!, I ElnON! ~ .ILSB 2 AIALH IIPUT 2 EINOFF lEE TABLE I FOR DIGITAL COIlE DEFINITIONS. FIGURE I. Input vs Output for an Ideal Bipolar AI D Converter. a specified temperature range when short cycled for 14-bil operation. TIMING CONSIDERATIONS The timing diagram (Figure 2) assumes an analog input such that the positive true digital word 1001 1000 1001 0110 exists. The output will be complementary as shown in Figure 2 (0110 011101101001 is the digital output). CONVERT CauuDllI INTERNAL ClOCK STATU81E1IC1 MSB BIT2 liT 3 lIT 4 liT 5 81T6 IIT7 ~ =--] ''0" =__ .r-L.J=:=~---;;;··I;;:·· ., ~::::::J ___ J =::::::J =:::_J r- 1"'0" U"I" U"I" ==:::J =::::J 81T8 liT 10 BIT 13 BIT 14 81TI5 L..j··I" ~ _______=I"U='~____________________________~r-==_J llTa liT" liT 12 ===================== :::::J LJ"I" 1"0" U"I" ::::_J --- J L_J'I" 1"0" ___ J LJ"I" ::::::::J~ _______________________________~I'='U='~----~rr- :~_-J.,.. 1fT 18 ~ IERIALI3I DATA OUY--=-_ ''0'' I lr _.. , r-.., OPn.ALEmRIAL __ CLOCK l II 2f111n11c, MAX r-- 1"0" LJ -II- 2 : 3 "I" "I" 16 4: 5 "0" "0" "I" "I" "I" "U' "I" "I" "U' "I" ''0'' "u' "I" i-I ,-.., r-, r-"-. r--' r-..., ,---, r-., '--11"'-'" r---, ,..-..., r-l r-'" r-'" i - L.J U LJ Ll U U U U a...J LJ U U ~J L... U "I" L.~ NOTES: I. lbl aMVII1 _Ind 11l1li111111. .15fIIIuc wldl Ind IIIUII nlllltn law during I ClllVlllIall. TbI ClllVlllian IllnHl1lld by l1li "nlllng ad.." _l1li ClllVlrt _mind. 2. 17~. . 1Ir bHl. 3. UII Inlllng 1~lgh II lawl"" _ cl_ II IInIII llah 11I1111111pU1 blL I. FIGURE 2. ADC76 Timing Diagram. 6-41 connections forl4-bit resolution.· parallel data output. with ±IOVinput. . DIGITAL CODES Perellel Dete Two binary codes are available on the ADC76 parallel output; they are complementary (logic~O" is true) straight binary (CSB) for unipolar input signal ranges and complementary offset binary (COB) for bipolar input signal ranges. Complementary two's complement (CTC) may be obtained by inverting MSB (pin I ). Serial Data Two straight binary (complementary) codes are available on the serial output line; they are CSB and COlt The serial data is available only during conversion and appears with MSB occurring first. The serial. data is synchronous with the internal clock. as shown in the timing diagram of Figure 2. The LSB and transition valuesshow.n in Table I also apply to the ~erial data output except for the CTC code. Table I shows the LSB. transition values. and code definitions for each possible analog input signal range for 12-. 13- and 14-bit resolutions. Figure 3 shows the IIOmDUIElm EXTEIItW. I~------------------~--------<~~ CGIIIECTma. 1}---------+-----~~----+---------1_--~~--------<+15WC 10lUlto IlIOiUl r-- 1..--- L--_~S I L-________+ GAtN ADJUST ____ -+_______ tOlm to ~~11IIIIc1l OFFSET ADJUST r-I r--I r I ANALOG ~}---------+---t-----r~l~~F~-~~mMMON I}-_ _ _ _ _ _ _...._ _ -+_____......;.__-....;;...--< .15V~ I I I I DIGITAL COMMON I I __ :--.1 I~_______ NC '"':'". 18 _ _ _ _ _oI'J STATUS OUTPUT TO CONTROL LOGIC 'CAPACITOR SNOUlD IE COIIIIECTED EVElIF EXlERlAlUl1 ADJUST illICIT USED. FIGURE 3. ADC76 Connections For: ±IOV Analog Input. 14~Bit Resolution (Short-Cycled). Parallel Data Output. TABLE I. Input Voltages. Transition Values. LSB Values. and Code Definitions. Binary I BIN I Output Analog Input Vo~age Range INPUT VOLTAGE RANGE AND LS~ VALUES Defined As: ±1011 ±5V ±2.5V o to +1011 Oto +5V Oto+2OII COB(I) orCTC(2) COB(I) orCTC(2) COB(I) orCTC(2) CSB(3) CSB(3) CSB(3) f§B 2Ql! 2n n=12 n=13 n=14 2n 4.88mV 2.44mV 1.22mV !2l! 2n 2.44mV 1.22mV ~ 2n l.22mV !.!!lI ~ 2n 1.22mV +Full Scale MidScale -Full Scale +1011 -3I2LSB 0 -10V +112LSB Code Designation One Least Significant Bit ILSBI ~ 610~V 2n 2.44mV 1.22mV 610~V 305~V 610~V 305~V 4.8amV 2.44mV 1.22mV +5V -312LSB 0 -5V +112LSB +2.5V -3I2LSB 0 -2.5V +112LSB +1011-312LSB +5V 0+ 112LSB +5V -3I2LSB +2.5V 0+ 112LSB +20V -3I2LSB +1011 0+ 112LSB 61O~V Transition Values MSB LSB 000 ...000(4) 011...111 111...110 (I)COB = Complementary Offset Binary (3)CSB = Complementary Straight Binary (')CTC = Complementary Two's Complement - obtained by inverting the most significant bit. MSB I pin 1,. (4)Voltages given are the nominal value for transition to the CodA specified. SPECIFICATIONS ELECTRICAL AI +25"C and rated power supplieS unless olherwise noted. ADC7IKG MODEL ADC7I.IG TYP IIIN MAX I RESOLUTION I MIN TYP I 16 I MAX UNITS 16 Bits ANALOG INPUTS Voltage Ranges Bipolar Unipolar ±2.5. ±S. ±10 Impedance (DirecllnpulJ to +5V. ±2.5V to +10V. ±S.OV to +20V. ±lOV o o o ±2.5. ±5. ±10 V oto +5. 010 +10. o to +5. 0 to +10. 010+20 010+20 V 2.5 5 '10 2.5 5 10 kll kll kll DIGITAL INPUTSlll Convert Command Logic Loading External Clock Positive pulse SOnsec wide (min) trailing edge 1"1" to "0" initiates conversion! I I 1 I I I Negative pulse l00-2OOnsec wide. Frequency < internal clock(21 1 TTL Load TRAN8FER CHARACTERlmCS ACCURACY Gain Erron31 Offset Error Unipolan31 Bipolarl3) Linearity Error Inherent Quantization Error Differential Linearity Error Noise !3a. p-Pl +01. ±D.1/ ±0.1 ±D.2 % ±D.OS ±D.l ±D.l ±D.2 ±D.OO3 ±D.OS ±D.l ±D.l ±D.2 ±D.OO6 ±112 ±112 ±D.OO3 ±D.OO3 ±D.003 ±D.OO3 % 01 FSR(41 %oIFSR %oIFSR LSB %oIFSR %oIFSR 0.003 0.001 0.003 0.001 %01 FSRI%Vs %01 FSRI%Vs POWER SUPPLY SENSITIVITY ±15VDC +5VDC CONVERSION TlMEI5) 114 Bits I WAJIII.UP TIME 15 15 posec min 5 5 DRIFT Gain Offset Unipolar Bipolar Linearity No Missing Codas Temp Range KG I 14-bitl JG 113-bill ±15 ppml"C ±4 ±10 ±3 ppm 01 FSR/oC ppm 01 FSR/oC ppm 01 FSRfOC 50 °C °C I 2 TTL Loads I 2 TTL Loads 2 2 TTL Loads 2 1400 933 2 1400 TTL Loads kHz ±15.5 +5.25 ±14.5 +4.75 ±15.5 +5.25 VDC VDC mA mA mA +70 +85 +125 °C °C °C ±15 ±2 ±2 ±4 ±10 ±2 ±3 ±2 +40 +10 0 OUTPUT DIGITAL DATA (All codes complementary I Paraliel Oulput Codes(8I Unipolar Bipolar Output Drive Serial Dala Code I NRZ I Outpul Drive Status Status Output Drive Inlernal Clock Clock Outpul Drive Frequency(81 CSB COB.CTCI7I CSB COB.CTCI7I I CSB.COB I I I Logic "1" during conversion 933 I 2 CSB.COB I 2 Logic "1" during conversion POWER SUPPLY REQUIREMENTS Power Consumption Rated Voltage. Analog Rated Voltage. Digital Supply Drein +15VDC Supply Drain -15VDC Supply Drain +5VDC ±14.5 +4.75 1.55 ±15 +5 +45 1.55 ±15 +5 +45 -35 -35 +70 +70 . W TEMPERATURE RANGE Specilication Operating (deraled specs I Storage +70 +65 +125 0 -25 -55 6-43 0 -25 -55 NOTES: 1. OTLITTL compatible, i.e., Logic "0" = O.BV, max, Logic "1" = 2.DV, min for inputs. For digital outputs Logic "0"= 0.4V, max, Logic "1" = 2.4V, mili. 2. See External Clock operating instructions. ' 3. Adjustment to zero. See "Optional Extemal Gain and Offset Adjustmenf' section. 4. FSR meens Full Scale RangeiFor example, unit connected for ±10V range has,20V FSR. 5. Conversion time may be· shortened with "Short Cycle" set for lower resolution and with use of Clock Rate Control. See ·Optional Conversion :rIme Adjustment" section. The Clock Rate Control , pin 23) should be connected to Digital Common for specified conversion time. Short Cycle, pin 321 should be left open for 16-bit ,esolution or connected to the n + 1 digitai outputfoi n-bit resOlution: For example, connect Short Cycie to Bit 15, plii15) for 14,1)it resolution" For resolutions less than 16 bits, pin 32 should also ~ tied to +5V througha 2kll resistor.' 6. See Tabl,e I. CSB - Complementary Straight Binary. COB - Complementary Offset Binary. CTC - Complementary Two's Complement. 7. CTC coding obtained by Inverting MSB (pin 1). ' B. Adjustable with Clock Rate Control from approximately Q33kHz to 1.4MH,z. See Figures 12 and 13 and Table'lli. MECHANICAL . OIM A C , 0 G H , , , N INCHES MIN M.X CASE: Ceramic MATING CONNECTOI\: MILLIMETERS MIN "'X 1678 1712 4262 4348 '..""., 1101 274' 2791 2302MC .,. ... ." ... . '",. ."'". ... 1079 m 41)7 " " 2 to. BASIC "'" '00 " '" " condition C step 1 I fluor()oo carboni, of MIL~STo-883 n. 9008ASIC Igross leak I, '" 2286B .... SIC ex" '" HERMET)C)TY: Conform. 10 method 1014 '" '" 100 BASIC , WeiGHT: 13 grams 10.48 oz.' CONNECTION DIAGRAM TOP VIEW e MSBI Bit 1 Bit 2 :,t:=====~---;:========t32) SHORT CYCLE CONVERT COMMAND· Bit 3 +5VDC SUPPLY Bit 4 GAIN ADJUST Bit 5 +15VDC SUPPLY Bit 6 COMPARATOR IN Bit 7 BIPOLAR OFFSET ~8 W Bit 9 20V Bit 10 CLOCK RATE CONTROL Bit 11 ANALOG COMMON Bit 12 -15VDC SUPPLY ILSB for 13 bitsl Bit 13 CLOCK OUT ILSB for 14 bitsl Bit 14 DIGITAL COMMON ~t~~k~~~~~~~~~~~~~~ 15 .:: Bit 16 STATUSOUT SERIAL *If an external clock is used, connect the clock to pin 31 I CONVERT COMMAND I. TYPICAL PERFORMANCE CURVES GAIN DRIFT ERROR 1% OF FSR I +0,1a ..._ _ _ _ _ _ _ _ __ VS_ TEMPERATURE ~ ,.,'" '0 e 0 0.0 1 ::: -{l.04 ~ 0.006 " '0; (!) V 0.02 +0.04 ;5 -15VDC 0.04 +0.08 ~ -{l.oa ;5 0.004 -{l.12 ~ 0.002 -{l.16 -0,18 '0 '# 0 +700 +250 Temperature / 6-44 I +15VDC ./ J 1\./ / +5VDj)7 0.001 1 °c , / 0.08 +0,161=============1 +0.12 ~ W POWER SUPPLY REJECTION VS SUPPLY RIPPLE FREQUENCy 0,1 10 100 1k Frequency IHzl 10k 100k DISCUSSION OF SPECIFICATIONS ACCURACY VERSUS SPEED The ADC76 is specified to meet critical performance criteria for a wide variety of applications. The most critical specifications for an AI D converter are linearity. drift. gain and offset errors. and conversion speed effects on accuracy. This ADC is factory-trimmed and tested for all critical key specifications. GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to typically ±O.I % of FSR (±O.OS% for unipolar offset) at 2S"C. These errors may be trimmed to zero by connecting external trim potentiometers as shown in Figures 7 and 8. POWER SUPPLY SENSITIVITY Changes in the DC power supply voltages will affect accuracy. The ADC76 power supply sensitivity is specified at ±0.OO3% of FSR/%V s for the ±ISV supplies and ±o.OOIS% of FSR/%V s for the +SV supply. Normally. regulated power supplies with 1% or less ripple are recommended for use with this A DC. See Layout Precautions. Power Supply Decoupling. and Figure S. LINEARITY ERROR Linearity error is not adjustable and is the most meaningful indicator of AI D converter accuracy. Linearity is the deviation of an actual bit transition from the ideal transition value at any level over the r.mge of the AI D converter. I n successive approximation AI D converters. the conversion speed affects linearity and differential linearity errors. Conversion speed and its effect on linearity and differential linearity errors for the ADC76 are shown in Figure 4. LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS Analog and digital common are not connected internally in the ADC76. but should be connected together as close to the unit as possible. preferably to a large plane under the ADC. If these grounds must be run separately. use wide conductor pattern and a 0.01/01 F to 0.1/01 F nonpolarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital common' returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The comparator input (pin 27) is extremely sensitive to noise. Any connection to this point should be as short as possible and shielded by Analog Common or ±ISVDC supply patterns. POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum or electrolytic capacitors as shown in Figure S to obtain noise free operation. These capacitors should be located close to the ADC. DIFFERENTIAL LINEARITY ERROR Differential linearity describes the step size between transition values. A differential linearity error of±0.OO3% of FSR indicates that the size of any step may not vary from the ideal step size by more than 0.003% of Full Scale Range. • • -- 0.1 \.U-- == iii ::5 \\f •:::; ... 0.01 CI ILIIDI ~ •c - ; ~ @) ® 1 I~F @ 1+ ANAL06 COMMON • I+I~F .. +15VOC INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the Ai D converter. Connect the input signaf as shown in Table II. See Figure 6 for circuit details. co ...~ @) .. ·15VOC FIGURE S. Recommended Power Supply Decoupling. I!i i!!. •.... II I1+I~F DIGITAL COMMON ~ ... @ +5VOC II2LIBI2...T TABLE 11. ADC76 Input Scaling Connections. \~ 'I ~ DJID3 0.001 IHORT CYCLED TO 12 BITS SHORT CYCLED TO 1'3 BITS ....ORT CYCLED TO 14 BITS 5 I12LSB I3-BIT I/2LSB 14-8IT 15 10 CO.VERBlON TIME 1,.a.1 2IJ FIGURE 4. Linearity and Differential Linearity Versus Conversion Time. Input Signal Range ±10V ±5V ±2.5V a to +5V a to +10V a to +20V Output Code Connect Pin 26 To Pin Connect Pin 24 To Connect Input Signal To Pin COBorCTC' COBorCTC' COB or CTC' CSB CSB CSB 27 27 27 22 22 22 InputSig. Open Pin 27 Pin 27 Open Input Sig. 24 25 25 25 25 24 Obtained by Inverting MSB ! pin 11. 6-45 Table I details the transition voltage levels required lal DIRECT INPUT @) I•• n +ISVDC 111111111 IDIlIen DFFSfT ADJUST ·15VDC • "No CDM'.IN Ibl +ISVDC 1000nl1l 1000n OFFSET ADJUST ·ISVDC ~ COMP.IN -=- 221m .' ' FIGU RE '8. Two Methods of Connecting Optional Offset Adjust With a 0.4% of FSR Range of Adjustment. FIGU RE 6. ADC76 Input Scaling Circuit. OUTPUT DRIVE, Normally all ADC76 logic outputs will drive two standard TTL loads; however. iflong digital lines must be driven. external logic buffers are recommended. +ISVDC GAIN ADJUSTSIOIIiI INPUT IMPEDANCE 29". ANALOG COMMON (§)T The input signal to the ADq6 should be a low impedance. such as the output of an op amp to avoid any errors due to the relatively low input impedance of the ADC76. If this impedance is not low. a buffer amplifier should be added between the input signal and the direct input to the ADC76 as shown in Figure 7. IOtnm 1001111 ~o.OI~F GAIN ADJUST ·15VDC FIGURE 9. Connecting Optional Gain Adjust With a 0.6% Range of Adju~tment. OPTIONAL EXTERNAL GAIN AND .OFFSET ADJUSTMENTS Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC as shown in Figures 8 and 9. Multiturn potentiometers with IOOppmj"C or better TCR's are recommended for minimum drift over temperature and time. These pots may be any value from 10k!! to lOOk!!. All resistors should be 20% carbon or better. Pin 29 (Gain Adjust) and pin 27 (Offset Adjust) may be left open if no external adjustment is required. EXTERNAL CLOCK If an external clock is used. connect the external clock to Convert Command; pin 31. The convert command shown in Figure 2 is not used. After each conversion is completed. a new conversion cycle will automatically start on the first falling edge of the external dock following the completion of conversion. The clock out siBnal will remain as shown in Figure 2 even if an external clock is used. The external clock pulse must be a negative going pulse with a width between 100nsecand 200nsec as shown in Figure 2. and must be at a lower frequency than the internal clock. The circuit in Figure 10 shows a simple technique for generating a'clock signal with the re4uired duty cycle from an external clock with an arbitrary duty cycle. The external clock must operate at a lower frequency than the internal clock for proper operation. This should not present a problem since the fre4ucncy of the internal clock can be increased to any desired value by using the Clock Rate Control. pin 23. Figure II shows a conversion using a continuous external clock. ADJUSTMENT PROCEDURE OPTIONAL CONVERSION TIME ADJUSTMENT AULIIII••UT 8I8I1AL 883507J FIGURE 7. Source Impedance Buffering. Offset - Connect the Off~t potentiometer (make sure RI is as close to pin 27 as possible) as shown in Figure 8. Sweep the input through the end point transition voltage that should cause an output transition to all bits off (E(l~'). The ADC76 may be operated with faster conversion times for resolutions less than 14 bits by'connecting the Clock Rate Control (pin 23) and the Short Cycle (pin 32) as shown in Table III. Typical conversion times ·for, the resolution and connections are indicated. Adjust the Offset potentiometer until the actual end point transition voltage occurs at E()\'~. The ideal transition voltage values of the input are given in Table I." TABLE Ill. Short Cycle and Clock Rate Control Connections for 12- to 16-Bit Resolutions. 16 15 14 13 12 Connect Pin 32' to Open Pin 16 Pin 15 Pin14 Pin13 Connect Pin 23 to Typical Conversion Time Pin 19 Pin 19 16,.sec Pin 19 Pin 30 17~sec 15~$ec lU~sec Pin 30 ..~.ec Resolution! Bits I Gain • Connect the Gain adjust potentiomete~as shown in Figure 9. Sweep the input through the end point transition voltage that should cause an output transitionto.all bits on (E(l~). Adjust the Gain potentiometer until the actual end point transition voltage occurs at E(l,~. For resolullons Ie•• than 16 bits al.o connect a 2kll reSl.tor from +5V to pin 32, 6-46 lkll ADC78 CDllVERT COMMAND EXTERIW.CLOCK If a more precise adjustment of conversion time is desired than can be obtained by simply connecting the Clock Rate Control (pin 23) to Digital Common or +5V. as indicated in Table III. the Clock Rate Control may be connected to an external multiturn trim potentiometer witha TCR of±IOOppmj"C orlessas shown in Figure 12. The typical conversion time versus the Clock Rate Control voltage is shown in Figure 13. The effect of +15VOC 23)-_ _ _-<5kn CLOCK -.~RATE INTERNal CLOCK FREQUENCY ADJUST CLOCK RATE CONTROL CONTROL FIGURE 12. Clock Rate Control. Optional Fine Adjust. 30 oICI --"1 . - 2IIOIuc TYPICAL STATUS - - - - - - - , END Of PREVIOUS TYPiCAL- 125 ....:!o ITO Pli 311 !20 Ii CONVERI~LJmii"Of NEXT CONVERSION. • n ••ldllllllllllck IIIq_ncy liliiii III II1IIr ....... l1li...1cllcklllq_' D1I111AOC7• • ,....,.,... TlIIIIIIInIII . . ........,II_Hz willi l1li CIIct R.. CInInI 1JIt231 . . . . . 11 _ I c..n. H1111...., UIImII clICk ,~ II ,...1nd.1lll1nInI1 . . ',......., eM ~. IIICIIUIIIIIy ___ II pin 2311 +IV. EXIImII click an hnI .., dalnd duly cyciL FIGURE 10. Continuous Conversion Using External Clock With Arbitrary Duty Cycle. ; 15 ~ I'.. Ii I. .. 10 llHlT OPERAnDN- .........:::""'000 .!. 5 lJ4-BIT OPERATIOI 0 2 10 12 8 4 CONTROL VOLTAGE ON PIN 23 • 1415 FIGURE 13. Conversion Time vs Clock Rate Control Voltage. varying the conversion time and the resolution on Linearity Error and Differential Linearity Error is shown in Figure 4. Ikll ADe78 t-+'----{:31 CONVERT COMMAND EXTERlAl CLOCK CLOCK -<§) CONTROL RATE COlVERT COMUID L..-----{l18 STATUS n 1__________ COlVERT COMUllr--.J HEAT DISSIPATION The ADC76 dissipates approximately 1.8 watts (typical) and the packages have a case-to-ambient thermal resistance (Ot,,) of 25"Cj W. For operation above 70"C. OtA should be lowered by a heat sink or by forced air over the surface ofthe package. See Figure 14 fOrOtA requirement, above 70"C. If the converter is mounted on a PC card. improved thermal contact with the copper ground plane under the case can be achieved using a silicone heat sink compound. On a 0.062" thick PC card with a 16 square inch (minimum) area. this technique will allow operation to +85"C. mERIAl CLOCK 1 L" OICl--.....,r--..,,...-~I,......-_Ir--­ (TOPIN3I) - I f-- __ ITYPICALI 60 STATUS _ _"""'"' I11III: 70 80 90 100 AMBIENT TEMPERATURE I"CI FIGURE 14. OtA Requirement Above 70"C. TlllClRVlrt _lIInd IRd l1li .XIImII eillclt liliiii " high lI.alllllllllll, II InlU"IClRnnloa. TIIICDnnnlon wllllllrt on l1li rillag ..... 1II ....1IImI1 clICk. An, _l1li1 ellllllllndllhlllccur during I canvlnllon will "Ignorad. FIGURE II. Conversion Initiated by Convert Command Using Continuous External Clock. 6-47 110 BURR-BROWN@ IElElI A/D CDNVERTER ADC80 ~ EJURR-BROVVN I L ADC8DAG-t2 " " _t....: IC ANALOG-TO-DIGITAL CONVERTERS FEATURES DESCRIPTION • COMPACT DESIGN - Sell-contained with internal clock. comparator. and relerence The Model ADC80AG-IOand ADC80AG-I 2 are 10and 12-bit successive approximation AI D converters. They utilize state-of-the-art IC and lasertrimmed thin-film components, and are packaged in a compact 32-pin ceramic package. Complete with internal reference, the ADC80 offers versatility and performance formerly offered only in larger modular or rack-mount packages. Thin-film internal scaling resistors are provided for the selection of analog input signal ranges of ±2.5V, ±5V, ±IOV, 0 to +5V or 0 to +IOV. Gain and offset errors may be externally trimmed to zero, offering initial accuracies of better than ±O.OI22% (±1/2LSB). The model. ADC80 is specified for -25"C to +85"C operation. 32-pin ceramic package - FAST CONVERSION SPEEDS Provide last signal sampling rates 12-bits - 25JJsec. IO-bits - 21 Jlsec Faster conversion speeds obtainable with "Short-Cycling" and optional external clock -LOW COST - WIDE SUPPLY RANGE - Will operate with ±10.8V to ±16V suppti8S'(Z models) FUNCTIONAL DIAGRAM The fast conversion speeds of 25~sec for 12-bit and 21~sec for 100bit resolution make the ADC80 excellent for a wide range of applications where system throughput sampling rates from 40kHz to 47kHz are required. In addition, the ADC80 may be short cycled and an external clock may be used to obtain faster conversion speeds at lower resolutions. Data is available in parallel and' serial form with corresponding clock and status signals. All digital input and output signals are DTL/TTL-compatible. Two power supply range~ are available: ±15V and ±12V (Z models). A +5V logic supply is also required. Internalional Airport IndUllrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (602) 746-1111 - Twx: 910-952-1111 - Cable: BBRCORp· Telax: 66-64111 PD5-333F 6-48 DISCUSSION OF PERFORMANCE The accuracy of a successive approximation AID converter is described by the transfer function shown in Figure I. All successive approximation AID converters have an inherent QUANTIZATION ERROR of±1/2LSB. The remaining errors in the AID converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including GAIN, OFFSET, LINEARITY, DIFFERENTIAL LINEARITY and POWER SUPPLY SENSITIVITY. Initial GAIN and OFFSET errors may be adjusted to zero. GAIN drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits OFF) and OFFSET drift shifts the line left or right over the operating temperature range. LINEARITY error is unadjustable and is the most meaningful indicator of AID converter accuracy. LINEARITY error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AID converter. A DIFFERENTIAL LINEARITY error of±1/2LSB means that the width of each bit step over the range of the AID converter is 1LSB ±1/2LSB. The ADC80 is also MONOTONIC, assuring that the output digital code either increases or remains the same for increasing analog input signals. A monotonic converter can have missing codes; therefore, Burr-Brown ,specifies no missing codes over a temperature range_ w c 0 000 ... 000 000 ... 001 U III a !:! .. 011 ... 100 011 ... 101 f- :::l f- :::l a oJ « ~ (!l Ci 011 ... 111 100 ... 000 100 ... 001 111 ... 110 111 ... 111 Analog I n put E in Off FIGURE I. Input vs output for an ideal bipolar AID converter. *See Table I for digital code definitions. TIMING CONSIDERATIONS The timing diagram of the ADC80 (Figure 2) assumes an analog input such that the positive true digital word 100110001001 exists. The output will be complementary as shown in Figure 2 (011001110110 is the digital output). Maximum Throughput Time convert(1) Conversion Time (2) Command Internal Clock Status (EOe) ~ MSB Bit 2 Bit 3 8it4 Bit 5 Bit 6 ,Bit 7 Bit 8 Bit9 Bit 10 Bit 11 LSB Serial Oats Out 6: "1" 7: "1" 8 "1" "0" "0" NOTES: (1) The convert command must be between 100 ns and 21J.S wide and must remain low during a conversion. The conversion is initiated bV the "rising edge" of the convert command. (2) 251J.S for 12 bits and 21,.,..5 for 10 bits. FIGURE 2. ADC80 Timing Diagram. 6-49 'i Typical at 2S"C and Tated power supplies unless otherwise nOled. MODEL RESOLUTION INPUT ANALOG INPUTS Voltage Ranges ~ Bipolar - Unipolar Impedance (Direct Inl'.ut) o to +5V. ±2.5V o to +IOV. ±5V ±IOV DIGITAL INPUTS'" ConvC1rt Commaod ADC80AGZ-12 ADC80AG-12 12 V V 2.5 5 10 kll kll kll ±O.012 I % % of FSR'~' % of FSR ±0.048 ±1/2 o to +70 ±15V +5V DRIFT Specification Temperature Range Total accuracy, bipolar (maX)I"1 Gain. (max.) INTERNAL REF. VOLTAGE Max. External Current (with no degradation of specifications) Tempco of Drift (max) POWER REQUIREMENTS Rated Voltages Z models Range for Rated Accuracy Z models Supply Drain +ISV or +12V -15V or -12V +SV TEMPERATURE RANGE Specification Operating (derated spec) Storage ••••••••••• 0 •• r -I.I--H A .1 L 11111111 11111 i. o-+I--,- ~ 25 ±1/2 I o to +70 ~ of FSR LSB LSB "C ±0.0030 +0.0015 % of FSR,%V. % of FSRi%V, -25 to +S5 ±23 ±30 ±3 ±15 ±3 GUARANTEED "C ppm/"C ppm/"C ppm of FSR, "c ppm of FSR. r ppm of FSR;.r I 21 "sec t" INCHES DIM • C .~ .. MILLIMETERS MIN MAX MIN MAX 1.700 1.780 43.18 44.70 1.120 29.46 5,84 1.160 28.45 .170 .230 4.32 .018 .021 0:46 .06. f .03" G .100 BASIC H 0.53 1,27 0.89 2.64 BASIC .110 .130 K .1150 .250 L .900 BASIC 2.79 N .002 .010 O.OS 0.2S R .110 .130 2.79 3.30 3.81 3.30 6.315 22.86 BASIC PI NS: Pin material and plating composition conform to method 2003 (SOlderability) of MiI-5td-883 (except paragraph. 3.2). CASE: Ce~amlc MATING CONNECTOR: 2302MC· Set of two Hi"pin strips ' WEIGHT: 13 grams (0.460'). Connection Diagram TOP VIEW CSB COB, CTC 2 CSB.COB 2 TTL Loads TIL Loads Logic "I'; during conversion 2 TTL Loads 2 500 6.3 TIL Loads kHz V 200 +20 "A ppm!':C ±15. +5 ±12. +5 4.75 to 5.25 and ±14.0 to ±16.0 4.75 to 5.25 and ±IO.S to ±16.0 +20 -20 +70 V V V V rnA rnA mA ,25 to +S5 <55 to +100 -55 to +125 "C "c "c PIN CONNECTIONS 1 BI16 I. OTl/TTL compatible Le .• logic "0" = 0.8V max, Logic "1M = 2.0V min for inputs and for digital outputs. Logic "0" = +O.4V max and .. ," = 2.4V min. 2. FSR means Full Scale Range - for example, unit connected for ±IOV range has 20V FSR. 3. Adjustable to zero with external trimpots. 4. Error shown is the same as ±1/2 lSB max for resolution of AID converter. S.. Conversion time with internal clock. 6. See Table I. CSB - Complementary Straight Binary. COB - Complementary Offset Binary. CTC - Complementary Two's Complementary. 7. For conversion speeds specified. 8. Includes drift due to linearity. gain. and offset drifts. j --I j.:..G f L NOTE: LEADS IN TRUE POSITION WITHIN .010" (.25mmIR (I) MMC AT SEATING PLANE. A ±O.I ±O.05 ±O.I t7 ,. II f" K TIL Load TTl Load I I 1:32. N Positive Pulse lOOns Wide (min) 2#lsec Wide (max). Power Supply Sensitiyity Offset - Unipolar - Bipoilir. (max) Linearity, (max) Monotonicity CONVERSION SPEED(max)'" OUTPUT DIGITAL DATA (all codes complementary) Parallel Output Codeslf>l- Unipolar - Bipolar Output Drive Serial Data Codes (NRZ) Output Drive Status Status Output Drive Internal Clock Clock Out~ut Drive Frequency 71 Bits ±S. ±to ±2.5. L.ogic Loading External Clock No Missing Codes Temp. Range I Units ADC80AGZ-10 ADCSOAG-IO 10 o to +5. 0 to +10 TRANSFER CHARACTERISTICS ERROR Gain Error'" Offset Error'\' - Unipolar - Bipolar Linearity Error (max)141 Inherent Quantilation Error Differential Linearity Error I n ..............,'. MECHANICAL ELECTRICAL SPECifiCATIONS 32. Bit 7 31 BII B 2 BIt 5 3 BIt 4 4 BI13 30 B119 29. BIt 10 (lSB·l 0 Bnsl 28. Bit 11 5 ·B1I2 6 BIt 1 (MSBI ~ ,~~_ Supply 9 ·SV DI911al Supply 10. Dlgllal Common . 27 BIt 12 (LSB·12 Bltsl 26 SenalOul 25 ·TSVor ·12V (l Models) 24 Ref Out 1+6 3Vl 23. Clock Oul 1 1 Comparator IN 12 Bipolar Offsel 22 Status 21 Short Cycle 13 RI 10V Range 14 R2 20V Range, 15 Analog Common 16 Gam AdjUSt 20 Clock Inhibit 19 Exlernal Clock 18 Convert Command 17 .'5Vor ·12V (Z Models) TYPICAL PERFORMANCE CURVES '" 0.175 0 0.150 u. ~ FIGURE 3. Linearity error vs conversion time. - 0.200 ;;: ~ 0: %-J{l for 8 Bits 0.125 0 0: 0: l- 8 Bit Operation 1\ ' . / 10 Bit Operation 0.100 w %LSB for >t: 0.075 \\ I.. \ \, 0.050 w Z 0.025 ::; 0.000 o 2 4 6 B 10 - 12 Bit Operation \' I\. - %LSB for ~ ~ ,.... rJB~J 10j\ 0: « - , 12 - - - 14 16 lB 20 22 24 25 CONVERSION TIME (".ec) 0: 0.200 0: 0: 0.175 >!: 0.150 0 for w FIGURE 4. Differential linearity error vs conversion time. r-- r- 8 Bit Operation -B Bits ,, \ :\. ~"" :s '" \" \ 1\ I'\. /10 Bit Operation 0:«0: 0.125 ~! 0.100 '#. 0.075 w'" .J .J -r-r-r ~lf' 0 «- i= Z w 0: w u. u. a 12 8it Operation %LSB for 10 i~t. I 0.050 -%LSB for 0.025 ~I~~~I- 0.000 o 2 ~ 4 6 B 10 12 I!""!!!' 14 16 - lB 20 22 24 26 CONVERSION TIME (".ec) ;;: +0.3 (I) ADCBO-12 AND ADCBO"10 u. FIGURE 5. Gain drift error (% of FSR) vs temperature. os +0.2 ~ a: +0.1 TYPICAL DRIFT CHARACTERISTIC 0 0: 0: 0 w I- u. -0.1 0: C Z -0.2 CI -0.3 « -25 o +25 +70 +B5 TEMPERATURE (oC) ...0 .. >-.J .04 .. ::l 0: Ul .02 '#. FIGURE 6. Power· supply rejection vs power supply ripple frequency. .1 .OB .06 0: w / 0> a:Z 0:WW o:~ .01 .OOB .006 .~ ~ ~u .004 '#. .000 ±15V (±12V) Volt Supply , /, +5 Volt SupplY .001 100 10 lk FREQUENCY (Hz) 6-51 10k lOOk DEFINITION OF DIGITAL CODES PARALLEL DATA SERIAL DATA Three binary codes are available on the ADCSO parallel output; they are complementary (logic "0" is true) straight binary (CSB) for unipolar input signal ranges and complementary two's complement (CTC) and complementary offset binary (COB) for bipolar input signal ranges. Two straight binary (complementary) codes are available on the serial output line of the ADCSO; they are CSB and COB. The serial data is available only during conversion and appears with the most-significant bit (MSB)occuring first. The serial data is synchronous with the internal clock as shown in. the timing diagram of Figure 2. The LSB and transition values shown in Table I also apply to the serial data output except for the CTC code. Table I describes the LSB, transition values and code definitions for each possible AoCSO amilog input signal range for S, 10 and 12 bit resolutions. Binary (BIN) Output INPUT VOLTAGE RANGE AND LSB VALUES Analog Input Voltage Aange Defined As: Code Designation 2n n=8 n = 10 n = 12 Transition Values MSB LSB 000... 0011'" 011 ... 111 111 ... 11' • COB = Complementary +5V ±2.5V COB COB oreTe· COB or eTC· ...!Q.lL --IDL oreTe· £§..8.. One Least Significant Bit (LSB) •• esa = Complementary ±10V Offset Binary Straight Binary 20V 2n 78.13mV 19.53mV 4.8BmV 2n 39.06mV 9.77mV 2.44mV +Full Scale Mid Scale +10V-3/2LSB -Full Scale -10V +%LSB +5V -3/2LSB 0 0 -5V +%LSB 2n 19.53mV 4.8BmV 1.22mV o to +10V css-· -1!!Y.. 2n 39.06mV 9.77mV 2.44mV +2.5V -3/2LSB +10V -3/2LSB +5V 0 -2.5V +%LSB 0+ }s'LSB • eTC = Complementary Two's complement ~ obtained by using the complement of the most significant bit ('MS'B'). MSB is available on pin 8. o to +5V ess·· 5V 2" 19.53mV 4.BBmV 1.22mV +5V -3/2LSB +2.5V o +%LSB ••• Voltages given are the nOminal val ue for transi- tion to the code specified. TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions. DISCUSSION OF SPECIFICATIONS The ADCSO is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an A/D converter are linearity, drift, gain and offset errors and conversion speed effects on accuracy. The ADCSO is factory trimmed and t~sted for all critical key specifications. GAIN AND OFFSET ERROR ACCURACY VS SPEED Initial GAIN and OFFSET errors are factory trimmed to ±0.1% of FSR (±0.05% for unipolar offset) at 25 0 C. These errors may be trimmed to zero by connecting external trim potentiometers as shown on page 6-53. In successive approximation A/D converters, the conversion speed affects linearity and differential linearity errors. Conversion speed and its effect on linearity and differential linearity errors for the ADCSO are shown in Figures 3 and 4. ACCURACY DRIFT VS TEMPERATURE The ADCSO conversion speeds are specified for a maximum linearity error of ±J.2LSB and a differential linearity error of ±'hLSB with the internal clock. Faster conversion speeds up to 23J.ls for 12 bits, 12J.lsecfor 10 bits and 6J.Ls for S bits are possible with an external clock (see page 6-54). Three major drift parameters degrade A/D converter accuracy over temperature; they are gain, offset and linearity drift. The worst case accuracy drift is the summation of all three drift errors over temperature. Statistically, these errors do not add algebraically, but are random variables which behave as root-sum-squared (RSS) or I a error.s as follows: POWER SUPPL Y SENSITIVITY Changes in the DC power supplies will affect the accuracy of the ADCSO. The ADCSO power supply sensitivity is specified for 1:0.003% of FSR/%Vs for ±15V (±12V) 'supplies and ±0.0015% of FSR/%Vs for +5V supplies. Normally, regulated power supplies with I % or less ripple are recommended for use with the ADCSO. See layout precautions an!! power supply decoupling on page 6-53. RSS =VEg2 + E02 + Ee 2 where Eg =gain drift error (ppm/oC) Eo =offset drift error (ppm of FSR/oC) Ee =linearity error (ppm of FSR/°C) For unipolar operation, the total RSS drift is ±30.3ppm/ o C. 6-52 LAYOUT and OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS INPUT SCALING Analog and digital commons are not connected internally in the ADC80 but should be connected together as close to the unit as possible, preferably to a large ground plane under the ADC80. If these grounds must be run separately, use wide conductor pattern and a O.OlpF to O.lpF nonpolarized by· pass capacitor between analog and digital commons at the unit. Low impedance analog and digital common returns are essential for low noise performance. Coupling between ana· log inputs and digital lines should be minimized by careful layout. Analog and digital +5 volt supplies are also not con· nected internally; they should be connected together at the unit as shown below in Figure 7 (pins 7 and 9). The ADC80 input should be scaled as close to the maximum input signal range aspossible in order to utilize the maximum signal resolution of the AID converter. Connect the input signal as shown in Table II. See Figure 8 for circuit details. 10V Range 1 3 0 - - - - - - - , R2 20V Range 14 O--"N~--" 5kO Rl 5kU. "0----_~+-, Compln 6.3K Sipolar "'-;t:- The power supplies should be bypassed with tantalum or electrolytic type capacitors as shown in Figure 7 to obtain noise free operation. These capacitors should be located close to the ADC80. IpF electrolytic type capacitors should be bypassed with O.OIIlF ceramic capacitors for improved high frequency performance. +5V+,: + 1 F I' Dig. 010 Com. .. I Connect Output Code Signal ±IOV ±5V ±2.5V o to +5V o to +10V 'I'F • Connect Pin 12 To Piri Connect Pin 14 To Input Signal To -15V (-12V) .l! 17 0 -= VRef. Input ! W F .. An.Com. 15 0 >---;;R FIGURE 8. ADC80 Input scaling circuit. Range • 1: ... from Of A 12~conv. Offset , An. Com. 15 ~ POWER SUPPLY DECOUPLING 250 , +15V (+12V) FIGURE 7. Recommended power supply decoupling. 11 11 II 15 15 CDS orCTC COS or CTC COS or CTC CSS· CSS Input Signal 14 13 13 13 13 Open Pin 11 Pin 11 Open TABLE II. ADC80 Input scaling connections. Optional External Gain and Offset Adjustments Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC80 as shown in Figures 9 and 10. Multiturn potentiometers with 100ppm/oC or better TCR's are recommended for minimum drift over temperature and time. These pots may be any value from 10 kil to 100 kil. All resistors should be 20% carbon or better. Pin 16 (Gain Adjust) may be left open if no external adjustment is required. ADJUSTMENT PROCEDURE GAIN - Connect the GAIN adjust potentiometer as shown in OFFSET - Connect the OFFSET potentiometer as shown in Figure 9. Sweep the input through the end point transition voltage that should cause an output transition to all ones. Figure 10. Sweep the input through the end point transition voltage that should cause an output transition to all zeros. Adjust the GAINpotenti9ffieter until the actual end point transition voltage occurs at E : . Table I details the transition voltage levels required. Adjust the OFFSET potentiometer until the actual end point transition voltage occurs at E ~!F The ideal transition volt· age values of the input are given in Table I. (al o I.BMO· "M Compo 11 IN • f -15V (-12V) :~~do Of~set Adjust ·1.5MSl for Z models • -28k.o for Z models (b~ (a) (b) +15V (+12V) +15V (+12V) +15V (+12V) Compo IN -f I'::~ ~~kO C;:O 22kSl". 16 Gain_ Adjust 100kO Offset Adjust .".. An. Com. -15V (-12V) IOMO* II oI . O.OI1'F 10kO to 100kO Gain Adjust +15V (+12V) ~ 270KO 270kO Jo.O I'F l -15V (-12V) • 8.2MU for Z models 15 6.8kO·· ; i'~n to 100kO 3ain Adjust -15V (-12V) .. 9.1kO for Z models FIGURE 10, Two methods of ~nnecting optional gain adjust with a 0.6%range of adjustment. FIGURE 9. Two methods of connectirtg optional offset adjust with a 0.4% of FSR range of adjustment. 6-53 ,>Olock Options The ADC80 is extremely versatile in ,that it can be operated in several different modes witll either internal or external clock. Most of these options call 1)e implemented with nothing more than an inexpensive quad 2-input NAND gate (7400) as'shown in Figures 11 through 14. JL 8 Cony. Com. Convert Command .n.n.rL .a,it 11 I External Clock Short I I Cycle ADC80 1281t Operation "- "+6V CJock inhibit External Clock I +5V JL Digital Common I Convert I Command FIGURE II. INTERNAL CLOCK - NORMAL OPERATING MODE. Conversion initiated by the rising edge of the convert command. The internal clock runs only during conversioJil. FIGURE 13. CONTINUOUS EXTERNAL CLOCK. Conversion initiated by rising edge of convert command. The convert command 'must be synchronized with clock. 470 pF External Clock Bit 11 Clock '~-~-+5V Digital, Common FIGURE 12. CONTINUOUS CONVERSION WITH EXTERNAL CLOCK. Conversion is initiated by 14th clock pulse. Clock runs continuously. ' FIGURE 14. CONTINUOUS CONVERSiON WITH INTERNAL CLOCK. Conversion is initiated by the 14th clock pulse. Clock runs continuously. The oscillator formed by gates 2 and 3 insures that the conversion process will start when logic power is fIrst turned on. Short Cycle Feature The ADC80 may be operated at faster speeds for resolutions less than 10 or 12 bits, depending on the model selected, by connecting the short cycle pin, pin 21, as shown in Table III. ConversioI\ speeds, linearity, and resolutions are shown for reference. B RESOLUTIO,N (BITS) 12 10 connect Pin 21 to Ping Pin 28 Maximum Conversion Time(1) Internal Clock (J'S8C) Extarnal Clock '(,.sec) 25 23 22 12 18 6 Maximum Nonlinearity At +250 C (% of FSR) 0.012(2) 0.048(3) 0.20(3) Pin 30 NOTES: (1) Max conversion time to maintain ±)sLSB Nonlinearity error. (2) 12 81t Models only. (3) 10 or 12 Bit Models. TABLE III. Short cycle coimections and resolutions for 8 to 12 bit resolutions - ADC80. Output 'Drive Notmally all ADC80 logic outputs will drive 2 standard TTL loads; however if long digital lines must be driven, external logic buffers are recommended. 6-54 I APPLICATIONS CHO LOW COST DATA ACQUISITION SYSTEM Analog Data IN Parallel Data OUT 1 -7404 6 ~ Load ENS CountENB----~~~~~~ A~~.SS {===~J FIGURE 15. Low Cost Data Acquisition System. ZERO DROOP SAMPLE/HOLD A zero droop - infinite hold sample/hold can be constructed with the ADC80 with the circuit shown in Figure 16. A sample command will cause the relay to switch the analog input to the ADC80 input and also generate a convert command to the ADC80. The sample pulse width (T A) should be greater than the combined switching and settling time of the relay and driver circuit and the ADC80 conversion time. 10V Range In the HOLD mode, the analog value can be held indefinitely with zero droop. The period of the first one-shot multivibrator. must be equal to or greater than TR, the switching time of the relay. Sample -o~ ..............,...---... 2.2>n Output FIGURE 16. Zero Droop Infinite Hold Sample/Hold using ADC80 and a few external components. ORDERING INFORMATION ADC80AG ~----=---====--==:;::....,,- AID Converter family A = -25°C to +8S o C G = Carom ie Package xx T _______ ::-:=.---:-:-:----:-::-:-. Blank - ±14.0V to ±16.0V supply range Z ± 1 O.SV to ± 16.0V Supply range 6-55 Resolution (No. of Bits) 10"" 1 0 Bits 12= 128its BURR-BROWN\@' ADC82 1E3E31 Ie ANALOG~TO-DIGITAL CONVERTERS FEATURES • FAST CONVERSION SPEED - 2.8~sec. max Throughput sampling rates of over 300kHz Faster conversion speeds obtainable with optional external clock • COMPLETELY SELF-CONTAINED -Internal clock. comparator. and reference • ABSOLUTE ACCURACY - No external gain or offset adJustments are required for 0 to +1 OV or ±1OV signal ranges ' • PRECISION - ±1/2lSB maximum nonlinearity error • COMPACT DESIGN -24-pln ceramic or metal dual-Inline package • lOW COST - Ceramic packaged ADC82AG DESCRIPTION No external adjustments are required, to obtain initial absolute accuracies of better than ±I LSB for the 0 to + IOV or ± IOV signal ranges. Ga:in and offset errors may be externally trimmed to zero to obtain even greater accuracy. Data is available in parallel and serial form with corresponding clock 'and status signals. All digital input and output signals are DTL/TTL-compatible. Power'Supply voltages are ±15VDC and +5VDC. The model ADC82AG and ADC82AG are highspeed, 8-bit silccessive-approximation AI D converters designed for applications requiring system throughput sampling rates of over 300kHz. They utilize state-of-the-art IC and laser-trimmed thinfilm components and are' packaged in a 24-pin ceramic (ADC82AG) or metal (ADC82AM) package. Thin-film internal scaling resistors are provided for the selection of analog input signal ranges of±2.25V, ±5V, ±IOV, 0 to +5, 0 to +IOV, or 0 to +20V. FUNCTIONAL DIAGRAM LOGIC SUPPLY CONVERT COMMAND SERIAL DATA OUT .VCC +VCC COMPARATOR DIGITAL OUTPUT ANALOG COMMON BIPOLAR OFFSET } INPUT RANGE SELECT GAIN ADJUST International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746-1111· Twx: 910-952·1111· Cable: BBRCORP· Telex: 66-6491 PDS·35IC 6-56 DISCUSSION OF PERFORMANCE CONVERT(1) COMMAND The accuracy of a successive approximation AI D converter is' described by the transfer function shown in Figure I. All successive approximation AI D converters have an inherent Quantization Error of ±I 12LSB. The remaining errors in the AI D converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors, including Gain, Offset, Linearity, Differential Linearity and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AI D converter. A Differential Linearity error of± 1/2LSB means that the width of each bit step over the range of the AI D converter is I LSB ±1/2LSB. The ADC82 is also Monotonic, assuring that the output digital code either increases or remains the same for increasing analog input signals. A monotonic converter can have missing codes; therefore, Burr-Brown specifies no missing codes over a temperature range. TIMING CONSIDERATIONS The timing diagram of the ADC82{see Figure 2) assumes an analog input such that the positive true digital word 10011000 exists. The output will be complementary as shown in Figure 2 (OIIOOIII is the digital output). 000 ... 1110 000 ... 001 ~OIl ... IOI ~ 011 •. 110 5 011 ... 111 !; ::: 100 ... 1110 ~ 100 ... 001 !!! CO III •. 1I0 111 ... 111 t. f.---n" THROUGHPUT RATE ------1°1 CONVERSION TlME(2) _l MUST REMAIN "LOW" UNTIL STATUS GOES "LOW: I INTERNAL CLOCK STATUS MSB u u u SERIAL ~O.!!!. 2 : 3 "0" ''1"' "I"' "0" "0" 'T'"T' "I"' NOTE: II) CONVERSION IS INITIATED BY THE "FAWNG EDGE OF CONVERT COMMAND. 12) 2.8"18C FIGURE 2. ADC82 Timing Diagram. ALL BITS ON ---, I----,++---.. U-'-t--l ...t: OFFSET ERROR f K. ~:.:L'f--~-~"""""" ANALOG INPUT ~ -ILSB EIN OFF 2 'SEE TABLE I FOR DIGITAL CODE DEFINITIONS. :f§II ' - 2 FIGURE I. Input vs Output for an Ideal Bipolar AI D Converter. 6-57 rL SPECIFICATIONS MECHANICAL ELECTRICAL ADC82AG Typical at +25°C ana rated power supplies unless otherwise noted. I MODEL RESOLUTION ADC82AM ADC82AG 8 I ~L4. 0 UNITS I Bits •• 1:t reference only. N~mbers 1~,' " B INPUT Pin numbers shown for 0 It', may not be marked an package. :J1~ ~ 0: °AO.. 000.1 ANALOG INPUTS Voltage Ranges Bipolar Unipolar Impedance (Direct Inputs) o to +5V, ±2.5V 010 +10V, ±5V o to +20V, ±10V DIGITAL INPUTS(') Convert Command ±2.5, ±5, ±10 o to +5,0 to +10,0 to +20 V V 3.125 6.25 12.50 kn kn kn Positive pulse 50nsec wide (min) trailing edge NOTE: Leads in· true position within 0.1.0"10.25mm) R at seating plane. rr I tjel~e:,-, ("1" to "0") initiates conversion 1 1 Logic Loading External Clock TIL Load TIL Load . D'M TRANSFER CHARACTERISTICS ERROR Total Accuracy Error max Gain Error(2) Olfser Error(2) Unipolar Bipolar Linearity Error, max(4) Inherent Quantization Error Differential Linearity Error No Missing Codes Temp. Range Power Supply Sensitivity +15V +5Vand-15V I ±1 ±O.1 LSB % ±O.05 ±0.05 ±O.2 ±1/2 ±1/2 Ot070 ,%of FSR(3) % of FSR % of FSR LSB LSB °C ±O.02 ±O.OO6 %of FSR/%Vs %of FSR/%Vs -25 to +65 ±40 °C ppm/oC Unipolar Bipolar, max Linearity, max Monotonicity ±20 ppm of FSRoC ppm of FSRoC ppm of FSRfOC CONVERSION SPEED. maxiS) ±35 ±20 Guaranteed 2.8 "sec OUTPUT DIGITAL DATA(AII codes complementary) Parallel Output Codes(6) Unipolar Bipolar Output Drive Serial Data Codes (NRZ) Output Drive Status Status Output Drive Internal C lock Clock Output Drive Frequency(7) CSB COB,CTC 5 CSB,COB 5 Logic "1" during conversion 5 TTL Loads TTL Loads TTL Loads 4 2.65 TTL Loads MHz ±15, +5 +4.75 to +5.25, ±14.5 to ±15.5 +20 -20 +80 VDC VDC mA mA mA -25 to +85 -55 to +100 -55 to +125 °C °C °C POWER REQUIREMENTS Rated Voltages Range for Rated Accuracy(6) Supply Drain, +15VDC -15VDC +5VDC TEMPERATURE RANGE Specification Operating (derated specs) Storage 6-58 A 1.:no , .018 ° , ....'" . ". ..., 1.27 0.69 2.54SASIC ", .130 .250 .GOOBASIC '" N .0'0 .105 0.65 ." 0.!>3 3.8' 0.46 100 BASIC ," e , ,." 19.56 3.30 II.J5 J.81 1524B"s1C .~ 0.25 2.67 2.16 L: n CASE: Ceramic MATING CONNECTOR: 245MC PIN: Pin material and plating composition con~ form to method 2003 (solderability) of MILSTD-883 (except paragraph 3,2). WEIGHT: 7 grams, (0.25 oz). MILLIMETERS MAX M'N 33.21, u .. ....."'" " G . ADC82AM ~A~ T L a DRIFT .Specification Temp. Range Gain, max Olfset ...... INCHES MAX M'N c .CLl II ~::~ '" ""' ,..;"". withlnO.l0"(0.25mmIRat seating plane. Denotes pm' ) i--:--:IIIIIIIIIIII I G- I J.:-: -1-0 ~ dr-" L .. ~ 1 ooo·oooooo,; .. ~~III~i~!r Pin numbers shown for reference only. Numbers may n~ be marked on package. MATING CONNECTOR: 245MC PIN: material CASE:Pin Nickel Plated and plating composition conform to method 2003 (solderability) of MILSTD-883 (except paragraph 3.2). WEIGHT: 7 grams, 10.25 OZ}. NOTES: 1. DTLITTL compatible i.e., Logic "0" ~ O.8V max, Logic "I" ~2.0V min. 2. FSR means Full Scale Range - for example, unit connected for ±10V range has 20V FSR. 3. Adjustable to zero with external trim pots. 4. Error..shown is the same as ±1/2LSB,max for resolution of AID converter. 5. Conversion time with internal clock. 6. See Table CSB - Complementary Binary. COB - Complementary Offset Binary. CTC - Complementary Two's Complement. 7. For conversion speeds specified. 8. ±14.0V to ±16.0V for ±1-1 /4LSB total accuracy error. i. TYPICAL PERFORMANCE CURVES GAIN DRIFT ERROR 1%1 VS TEMPERATURE -Kl.6 -Kl.4 Maximum Gain Drift l - g w l: (!l Typical Drill Characteristic 0 ..." -- -0.2 -0.4 -0.6 -25 o +70 +25 Temperature IOC) LINEARITY ERROR VS CONVERSION TtME 1.2 1.0 ~ ~ ff 0.8 \ '0 ~ g 0.6 ~. " 0.4 w :::i 0.2 o 1/2LSB for 8 Bils I J r f-- 1.0 0.5 "'" 1.5 2.5 , 2.0 Conversion Time 3.0 (",sec) DIFFERENTIAL LINEARITY ERROR VS CONVERSION TIME 1.2 ~ ff 1.0 \ \. '0 ~ g , "" 0.8 w . ~ 0.6 " Oi :ee 0.4 is 0.2 .S; ...J ~ 1I2L~B t- o for 8 Bils r 0.5 l- 1.0 " """"-"= f-- 1.5 Conversion Time 6-59 (llseC) 2.0 I-- 2.5 3.0 CONNECTION DIAGRAM PIN ASSIGNMENTS CLOCK B-BIT SUCCESSIVE APPROXIMATION REGISTER 1. Clock Out 2. Digital Common' 3. Status 4. Bit BILSB) 5. Bit7 6. Bil6 7. Bit.5 8. Bit 4 9. Bit3 10. Bit 2 11. BitllMSBI 12. BitllMSsI a: w fa: !::~ 'l'z 24. 23. 22. 21. 20. 19. 18. 17. 16. 15. 14. 13. +5V Convert Command Clock In Serial Out -15V +15 Comparator Input Analog Common Bipolar Offset R2 (2OV Range I Rt 110V Rangel Gain Adjust *Internally connected to case on AOC82AM. "0 t.l ~ DEFINITION OF DIGITAL CODES PARALLEL DATA SERIAL DATA Two straight binary (complementary) codes'are available on the serial output line of the ADC82; they are CSB and COS. The serial data is available. only during conversion and appears with the most significant bit (MSB) occurring first. The serial data is synchronous with the internal clock as shown in the timing diagram of Figure 2. The LSB and transition values shown in Table I also apply to the serial data output except for the CTD code. Three binary codes are available on the ADC82 parallel output; they are complementary (logic "0" is true) straight binary (CSB) for unipolar input signal ranges and complementary two's complement (CTC) and complementary offset binary (COB) for bipolar input signal ranges. Table I describes the LSB, transition values and code definitions for each possible ADC82 analog input signal range. TABLE I. Input Voltages, Transition Values, LSB Values, and.Code Definitions. , Binary (BIN) Output Analog Input Voltage Ranges INPUT VOLTAGE RANGE AND LSB VALUES Defined As: Code Designation One Least Significant BitlLSBI FSR ±10V ±SV ±2.SV Oto +10V Oto+SV o to+20V COB orCTC' COB orCTC' COB orCTC' CSB" CSB" CSB" 20V SV ·10V SV 20V 2If 2fI 2If 39.06mV 19.53mV 78.13mV +SV -3/2LSB +2.SV 0+ 1I2LSB +20V -3/2LSB +10V 0+ 1I2LSB 2" 2" n~8 7B.13mV 10V 2n 39.06mV +Full Scale Mid Scale -Full Sc~le +10V -3I2LSB 0 -10V +1I2LSB +SV -3/2LSB 0 -SV+1I2LSB 2fI 19.53mV Transition V'a/ues MSB LSB 000 ... 000'" 011 ... 111 111 ... 110 , COB "CSB ~ ~ +2.S -3/2LSB . +IOV -3/2LSB 0 +SV -2.5V +1I2LSB 0+ 1I2LSB ***0 is the Transition Bit. Complementary Offset Binary ·CTC = Complementary Two's complement - obtained Voltages given are the Complementary Straight by using the complement of the most-significant bit nominal value for transition Binary IMSBJ. MSB is avaliable on pin-12. to the code specified. 6-60 DISCUSSION OF SPECIFICATIONS to the unit as possible, preferably to a large ground plane under the ADC82. If these grounds must be run separately, use wide conductor pattern and a 0.0 IJ.lF to O.IJ.lF nonpolarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines. should be minimized by careful layout. The ADC82 is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an AI D converter are linearity, drift, gain and offset errors, and conversion speed effects on accuracy. The ADC82 is factory trimmed and tested for all critical key specifications. GAIN AND OFFSET ERROR Initial gain and offset errors are factory trimmed to ±0.05% ofFSR at +25"C for both theO to+ 10 and ±IOV ranges. No external adjustment is required to obtain initial absolute accuracies of± I LSB. When using one of the other input signal ranges or when even greater initial accuracy is desired these errors may be trimmed to zero by connecting external potentiometers as shown in Figures 9 and 10. ACCURACY DRIFT VS TEMPERATURE Three major drift parameters degrade AI D converter accuracy over temperature; they are gain, offset and linearity drift. The worst-case accuracy drift is the summation of all three drift errors over temperature. Statistically, these errors do not add algebraically, but are random variables which behave as root-sum squared (RSS) or 10 errors as follows: POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum or electrolytic type capacitors as shown in Figure 3 to obtain noise free operation. These capacitors should be located close to the ADC82. IJ.lF electrolytic type capacitors should by bypassed with O.OIJ.lF ceramic capacitors for improved high frequency performance. @f---:l~-4.. -.15V 1! @ "" I"F r.\ +5V • DIG. COM • ...... _ -.......... --\!.I Ijj\ \:,:J ! I"F .. ANA. COM. -n,1"F .... @--_...u:...-_ 15V FIGURE 3. Recommended Power Supply Decoupling. J f/ + f/ + f/ RSS = Where fg = gain drift error (ppm/"C) fo = offset drift error (ppm of FSR/"C) f, = Linearity error (ppm of FSR/"C) For unipolar operation, the total RSS drift is ±49.0ppml °C and for bipolar operation, the total RSS drift is ±56.8 ppm/"c. ACCURACY VS SPEED In successive approximation AI D converters, the conversion speed affects linearity and differential linearity errors. Conversion speed and its effect on linearity and differential linearity errors for the ADC82 are shown in Typical Performance Curves. The ADC82 conversion speeds are specified for a maximum linearity error of ±I 12LSB and a differential linearity error of± I I 2LSB with the internal clock. Faster conversion speeds are possible with an external clock (see Figures 6 and 7. POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect the accuracy of the ADC82. The ADC82 power supply sensitivity is specified for±0.OO6% ofFSR/%Vs for-15V and +5V supplies and ±0.02% of FSR/%Vs for +15V supplies. Normally, regulated power supplies with 1% or less ripple are recommended for use with the ADC82. See layout precautions and power supply decoupling below. INPUT SCALING The ADC82 input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AI D converter. Connect the input signal as shown in Table II. See Figure 4 for circuit details. IOVRANGE @ RZ ...,.,...-----~ ZOY RANGE @---~.", 6.Z5kn COMP IN 18)-----~-~~ to SAR BIPOLAR~ OFFSET ANA. COM. ~ ... ~ t VREF FIGURE 4. ADC82 Input Scaling Circuit. TABLE II. ADC82 Input Scaling Connection. LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS Analog and digital commons are not connected internally in the ADC82 but should be connected together as close 6-61 Inpul Signal Range Output Code Connect Pin 16 To Pin Connect Pin 15 To. Connect Input Signal To ±10V ±5V ±2.5V 010 +5V 010 +10V 010 +20V COB orCTC COB orCTC COB orCTC CSB CSB CSB 18 18 18 17 17 17 Input Signal 15 14 14 14 14 15 Open Pin 18 Pin 18 Open Input Signal CLOCK OPTIONS The .. ADC82 is extremely versatile in that. it can be operated in several different modes with either internal or external clock. Most of these options can be implemented with nothing more than an inexpensive quad 2-input NAND Gate (7400) as shown in Figure 5 through 8. EXTERNAL CLOCK CONVERT COMMAND Jl 23 JUlJl CONVERT COMMAND CONVERSION INITIATED BY FALLING EDGE OF THE CONVERT COMMAND. THE INTERNAL CLOCK RUNS ONLY DURING CONVERSION. CONVERT COMMAND ~~NNECTION CLOCK OUT ~~O 1 CONNECTION CONVERSION IS INITIATED BY 10TH CLOCK PULSE. CLOCK RUNS CONTINUOUSLY. FIGURE 5. Internal Clock-Normal Operating Mode. n CLOCK @ IN FIG U RE 6. Continuous Conversion with External Clock. ~NVERT -! L-COMMANO JumO-----;:::::E»-------=::t2J EXTERNAL . CLOCK CONVERT COMMAND NO CONNECTION CLOCK OUT NO CONNECTION CONVERSION INITIATED BY RISING EDGE OF CONVERT COMMAND. THE CONVERT COMMAND MUST BE SYNCHRONIZED WITH CLOCK. CONVERT COMMAND MUST BE LOW DURING CONVERSION. FIGURE 7. Continuous External Clock. . 70PF ~ 6BDkn 470pF 3 CLOCK OUT . CONVERT COMMAND CLOCK IN CONVERSION IS INITIATED BY THE 10TH CLOCK PULSE. CLOCK RUNS CONTINUOUSLY. THE OSCILLATOR FORMED BY GATES 2 AND 3 INSURE THAT THE CONVERSION PROCESS WILL START WHEN LOGIC POWER IS FIRST TURNED ON. (THESE VALUES liVE A2OOnl8C CONV~RT COMMANDJ. FIG U R E 8. Continuous Conversion with Internal Clock. 6-62 OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS Ibl lal +15V Gain and offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC82 as shown in Figures 9 and 10. Multiturn potentiometers with 100ppm/"C or better TCR's are recommended for minimum drift over temperature and time. These pots may be any value from IOk!1 to 100k!1. All resistors should be 20% carbon or better. Pin 13 (Gain Adjust) may be left open if no external adjustment is required. +15V lOkllTO lOOkn OFFSET ADJUST lOkllTO 100kn OFFSET ADJUST ·15V ·15V FIGURE 9. Two methods of Connecting Optional Offset Adjust with a ± 1.0% of FSR Range of Adjustment. ADJUSTMENT PROCEDURE Offset - Connect the Offset potentiometer as shown in Figure 9. Sweep the input through the end point transition voltage that should cause an output transition to all bits off (Eoi~F). '" ! Ibl +15V Adjust the Offset potentiometer until the actual end point transition voltage occurs at E(~J~F. The ideal transition voltage values of the input are given in Table I. - 3.6Mn 10kn TO ~lOOkn GAIN ADJ Gain - Connect the Gain adjust potentiometer as shown in Figure 10. Sweep the input through the end point transition voltage that should cause output transitions to all bits on (E?::J). Adjust the Gain potentiometer until the actual end point transition voltage occurs at E?::J. GAIN ADJUST +15V .. lDkn TO lOOkn GAIN ADJUST ·15V Table I details the transition voltage levels required. FIGU RE 10. Two Methods of Connecting Optional Gain Adjust with a ±107f Range of Adjustment. ORDERING INFORMATION ADC82A x ~ ~ AI D Converter Family A = +25"C to +85"C G = Ceramic Package M = Metal Hermetic Package 6-63 ADC84 ADC85 BURR-BROWN 8 IElElI IC ANALOG-TO-DIGITAL CONVERTERS FEATURES • COM PACT DESIGN -Self-contained with Internal clock. comparator. reference. and Input buffer amplifier 32-pln ceramic or hermetic metal package • FAST CONVERSION SPEEDS Provide Fast Signal Sampling Rates 12-blts - 1D/lsec. 1D-blts - 6/lsec Faster conversion speeds obtainable with "Short-Cycling" and adJustable clock rate • LOW COST - ADC84KG-12 DESCRIPTION The ADC84 and ADC85 families of 10- and 12-bit analog-to-digital converters utilize state-of-the-art IC and laser-trimmed thin-film components, and are packaged in a compact 32-pin dual-in-Iine packages. Complete with internal reference and input buffer amplifier, they offer versatility and performance formerly offered only in larger modular or rackmount packages. Thin-film internal scaling resistors are provided for the selection of analog input signal ranges of ±2.5V, ±5V, ± 10V, 0 to+5V or 0 to + 10V. Gain and offset errors may be externally trimmed to zero, offering initial accuracies of better than ±O.O 12% (± I j 2LSB). The fast conversion speeds of IO/lsec for 12-bit and 6/lsec for 10-bit resolution make these ADC's excellent for a wide range of applications where system throughput sampling rates from 100kHz to 120kHz are required. In addition, they may be short cycled and the clock rate control may be used to obtain faster conversion speeds at low resolutions. Data is available in parallel and serial form with corresponding clock and status signals. All digital input and output signals are DTLj TTL-compatible. Power supply voltages are ±15VDC and +5VDC. Internatlanal AlrlHlrt Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 746·1111 . Twx: 910.952·1111 . Cable: BBRCORP· Telex: 66·6491 PDS-355C 6-64 the same for increasing analog input signals. Burr-Brown also guarantees that these converters will have no missing codes over a specified temperture range. DISCUSSION OF PERFORMANCE The accuracy of a- successive approximation AI D converter is described by the transfer function shown in Figure I. All successive approximation AI D converters have an inherent Quantization Error of ±II 2LSB. The remaining errors in the AI D converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure 1) about the zero or minus full scale point (all bits OFF) and Offset drift shifts the line left or right over the operating temperature range. Linearity error is unadjustable and is the most meaningful indicator of AI D converter accuracy. Linearity error is the deviation of an actual bit transition from the ideal transition value at any level over the range of the AI D converter. A Differential Linearity error of±1/2LSB means that the width of each bit step over the range of the AI D converter is ILSB ±1/2LSB. The ADC84 and ADC85 are also monotonic, assuring that the output digital code either increases or remains 000 ._0011 ........ E.r u ... ......... !:i!. ..... 000 ... 0111 Oil ... 101 Oil ... liD ::0 Oil ._ '" ::0 1011 ... 000 ~ a; a 1011 ... 0111 '" ... liD '" ... '" I ON EI. +FSR ·ILSB 2 FIGURE I. Input vs Output for an Ideal Bipolar AI D Converter. TIMING CONSIDERATIONS The timing diagram of the ADC's (see Figure 2) assumes an analog input such that the positive true digital word 10011000100 I exists. The output will be complementary as shown in Figure 2(011001110110 is the digital output). CONVERTI') COMMAND INTERNAL CLOCK STATUS (EOC) MSB BI12 BIT 3 BI14 BIT 5 BIH BIT7 BITB BITU BIT 10 BIT II LSB SERIAL(3) KW --- -l.r--Lf -lJ-l.J o ~~t~"~~ Lr-1I-l.f-l[-l[ -If-lf-LJ---LJ--1J CLOCK I I NOTES: 1188 pg. ~OOnBec. mlX....j I I. The convert commlnd mUlt be Il1ealt5Onlec wIde Ind mUll remlln low during a conversion. The conversion IIInHIllad by the '1rllllng Idg," of the convert commanD. 2. Jo.51J1ec lor 12·blll.nd 6ApllC lor' IJ.blll. 3. Use trilling edga 01 clock bJ strobe Berlal OUrpUL r-- FIGURE 2. ADC84 and ADCl!5 Timing Diagram. 6-65 SPECIFICATIONS ELECTRICAL Typical al +25°C and rated power supplies 'olherwise noled MO'DEL, ADC85 RESOLUTION INPUT ANALOG INPUTS ADC84KG ADC85C I 12 10 Vollages H~nges Bipolar Unipolar Impedance (Direcl Inpull 10 +5V: ±2.5V' 010 +IOV. ±5V ±IOV Buffer Amplifier 10 I 12 10, 12 UN!TS BITS ±2.5. ±5. ±IO 010+5.010+10 V V 2.5 5 10 kll kll kll 100 50 Mil ,nA " o Impedance. min Bias Current SelllingTime 100.01'110 lor 20V slep(1) 2 , .1 ~sec DIGITAL INPUTS(2) Convert Command Posilive pulse 50nsec wide. min, Trailing Edge ("1" to "0" initiates conversion I . Logic Loading Exlernal Clock TTL Load 1 See Exlernal Clock paragraph nANSFER CHARACTERISTICS ERROR I Gain Error Ollsel Error Unipolar Bipolar Linearity Er~or,' max(4) Inherent Quantization Error Differential Linearity Error No Missing Codes Power Supply Sensiliv~y ±15VDC +5VDC ±a.048 ±a. I (Adjustable to zero I Adjuslable to zero ±0.05 ±O.I ±0.012 I I ±a.048 I ±a.012 '110 ±D.048 1 ±0.012 ±112 ±112 ' -25 10 +85 I 0 10 +70 I 010 +70 010 +70 1 010+70 1010+70 '110 01 FSl:t13) 'IIooIFSR 'IIooIFSR LSB LSB LSB 0c. '110 01 FSRI'IIoVs '110 01 FSRI'IIoVs ±a.OO4 ±a.001 DRIFT Specification" Temperature Range Gain, max -25 'to +85 ±20 ±15 ±40 ±25, Offset Unipolar Bipolar Linearity. max Monotonicity ±3 ±IO ±3 ±3 ±7 ±2 ±3 ±20 ±3 ±3 ±12 ±3 6 10 6 CONVERSION SPEED /maxl/SI(6) OUTPUT DfGITAL DATA 010+70 010+70 ±30 ±3 ±15 ±3 Guaranteed I 10 6 I I °C ppmfOC ±3 ±15 ±3 ppm of FSR/oC ppm of FSR/oC ppm of FSR/oC 10 ~sec All codes complementary Parallel Output Codes(7) CSB COB.CTC Unipolar Bipolar Serial Dala Codes / NRZ I Output Drive Status Status Output Drive Internal Clock Clock Oulput Drive Frequency(6) TTL Loads 2 Output Drive CSB.COB 2 Logic "1" during conversion 2 1.9 I 1.35 1 1.9 +5 1 +5 1 +10 INTERNAL REF. VOLTAGE 2 1 6.3 TTL Loads TTL Loads 1.35 1 1.9 11.35 TTL Loads MHz V ±IO J ±20 1 ±20 ppm/oC Max External Current With no degradation 01 Specificalions T empco of Drift. max ~A 200 I POWER REQUIREMENTS Rated Voltages Range for Rated Accuracy Supply Drain +15VDC -15VDC +5VDC TEMPERATURE RANGE ±15.+5 4~; to 5,25 and ±14,5 to ±15r -35 +120 Specification Operating (derated specs I -25 to +85 Storage -55 to +125 ' o to +70 -55 to +85', 110°C case Temp. -55 to +125 +45 -35 +70 o to +70 -55 to +125 PACKAGE (see Mechanical Specifications) Metall·Hermetic) deramic V V mA mA mA °C °c °c 4. Error shown is the same as ±1I2LSB max linearity error in %of FS.R. 5. Conversion time may be shortened with "short cycle" set' for lower .; resolution, 6. Internal Clock is externally adjustable. 7. See Table II. CSB - Complementary Straight Binary. COBComplementary Ollset Binary. CTC - Complementary Two's Complement. . NOTES: 1. Thissettling time adds to conversion speed when buffer is connected to Input. 2. OTLITTL compatible; i.e., Logic "0" =O.BV max, Logic "1" =2.OV, min lor inputs. Fordigital outputs, Logic "0" = +O.4V max, Logic "I" = 2.4V, min. 3. FSR means Full Scale ,Range -lor example, unit c,onnected lor ±10V range has 20V FSR. CONNECTION DIAGRAM Bit 121LSB lor 12 bits) Bitll Serial Out Bit ,I 0 I LSB lor 10 bits) Bit9 Buller In -15VOC Supply Buller Out BitB +15VOC Supply .. Bit7 Gain Adjust BitS Analog Common BitS R220V Range Bit4 R,10V Range BII3 Bipolar Ollset Bit2 Comparator In BllllMSBI Convert Commandt BTt1 iMsB) Status ShortCvcle Clock Out Dig. Common e +5VDC • ReI. Out 1+6.3V! SUP~IY Clock Rate Control ·Oigital Common is internally connected to case. (ADC85 and AOCB5C only) t If external clock is used. connect the clock to Pin 21 Iconv. 'command.), an -. .. w (See Figure 2 and External Clock paragraph}, - TYPICAL PERFORMANCE CURVES LINEARITY ERROR VS CONVERSION SPEED -1'- 1- -t l"tB-Bit Operation 0.20 0.175 Ir , For8Blts '"g 0.150 w e w ~ "" c: :J \ 0.125 ~ 0.20 ;;21~SB I It 0.10 0.075 r-~;rL~BBIt. 0.05 1\ lo-~1I - - i I ,, ~ \ ~ 1-'21"·_~ 1!~SBfi r- tBit 6peration e 0.150 ~ 0.125 " 0.10 w .~ c: :J ~ 12-BII is ~~ - 5 6, 7 234 Conversion Time 1"Ilsec l Forl~Bits 0.05 8 - 0.025 llBit ~ o~era~ion' . \' ~ ,~ 0.075 _'/2LSB 'E ~ Operation , , l \ ForBBlls Operation 1/2LSB-For 0.025 0.175 DIFFERENTIAL'LINEARITY VS CONVERSION SPEED .... ~ 1/2LSB - - 12-lm ~ Operation - ,:orrBl'!!. 3 10 4 S B POWER SUPPLY REJECTION VS POWER SUPPLY RIPPLE FREQUENCY / 0,06 +0:,5 "> e~ ~~ 0.04 ~ ~ e.G. ~ G. +0.10 IL +0.05 " ~ (/) ILO> _ c: g 0 "'~ -0.05 w '15VDC , :'1 0.02 0.01 o .. 0.006 "'tl 0.004 ~ / 0.001 -0.15 o +25 +70 +85 V 6-67 ~ +15VDC h.../ 10 100 1+5VOC b/ lk Frequency (Hz I Temperature (OC) " .J 0.002 -0.10 -25 ,10 (;onverslon 'I mie (Ilset I 0.1 Ii (/) - - \~ ~- 10k lOOk " DEFINITION OF DIGITAL CODES PARALLEL DATA SERIALDAT~ Three binary codes are available on the ADC84 and ADC85 parallel outpUt~' they are complementary (logic "0" is true) straight binary (CSB) for unipolar input signal ranges and complementary two's complement (CTC) and complementary offset binary (COB) for bipolar input singal ranges. Table I describes the LSB, transition values and' code definitions for each possible analog input signal range tor 8-, 10-, and 12-bit resolutions. Two straight binary (complementary) codes are available on the serial output line; they are CSB and COB. The serial data is available only during convers,ion and, appears with the most significant bit (MSB) occurring ,first. The serial data is synchronous with' theinternai clock as shown in the timing diagram of Figure 2. The LSB and transition values shown in Table I also apply to the serial data output except for the CTC code. TABLE I. Input Voltages, Transition Vaiues, LSB Values, and Code Definitions Binary (BINI Output Analog Input Vo~age Ranges INPUT VOLTAGE RANGE AND LSB VALUES ,±5V ±2.5V COB' orCTC'" COB' orCTC'" 'COB' orCTC'" FSR 2n n=8 20V 2n 78.13mV 10V 2n 39.08mV n=10 n=12 19.53mV 4.88mV +FuliScale MIL Scale -Full Scale +10V -3/2LSB 0 -IOV +1/2LSB Defined As: Code Designation One Least Significant Bit (LSBI Transition Values MSB LSB 000 ... 000···· 011 ... 111 111 ... 110 'COB - Complementary Offset Binary "CSB = Complementary Straight Binary Oto+l0V Oto+5V CSB" 10V 2n 39.08mV CSB" 5V 2n 19.53mV 5V 2n 19.53mV 9.77mV 2.44mV 4.88mV 1.22mV 9.77mV 2.44mV 4.88mV 1.22mV +5V-3I2LSB 0 -5V+ 1/2LSB +2.5 -3f2LSB 0 -2.5V +1/2LSB +10V -3/2LSB +5V 0+ 1/2LSB ±10V' "'CTC = Complementary Two's complement - obtained by using the complement 01 the most~significant bit IMSBI. MSB is available on pin-13. +5V-3/2LSB +2.5V 0+ lf2LSB ····Voltages given are the nominal value for transition to the code specified. DISCUSSION OF SPECIFICATIONS The ADC84 and ADC85 are specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an AI D converter are linearity, drift, gain and offset errors and conversion speed effects on accuracy. These ADC's are factorytrimmed and tested for all critical key specifications. GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to ±O.I% of FSR (±0.05% for unipolar offset) at 25°C. These errors may be trimmed to zero by connecting extenial trim potentiometers as shown on next page. ACCURACY DRIFT VS TEMPERATURE Three major drift parameters degrade AI D converter accuracy over temperature; they are gain, offset and linearity drift. The worst-case accuracy drift is the summation of all three drift errors over temperature. Statistically, these errors do not add algebraically, but are random variables which behave as root-sum-squared (RSS) or 10 errors as follows: RSS = .J Eg' + EOi + Ee2 where Eg ""gain drift error (ppm/"C) EO = offset drift error (ppm 01 FSRI"c) Ee = linearity error (ppm of FSR/"C) For the ADC85-12 operating in the unipolar mode the total RSS drift is ±15.42ppm/"C and for bipolar operation the total RSS drift is ±16.7ppm/"C. ' ACCURACY VS SPEED In successive approximation AI D converters, the conversion speed affects linearity and differential linearity errors. Conversion speed and its effect on linearity and differential linearity errors for the ADC84 and ADC85 are shown in Typical Performance Curves. The conversion speeds are specified for a maximum linearity error of±1 12LSB With the mternai clock .... aster conversion speeds are possible (see Clock Rate Control Alternate Connections). POWER SUPPLY SENSITIVITY, Changes in the DC power supplies will affect accuracy, The ADC84 and the ADC85 power supply sensitivity is specified for±O.003% ofFSR/%Vsfor±15VDC supplies and ±0.OOI5%of FSRI.%Vs for HVDC supplies. Normally. regulated power supplies,with 1% or less ripple are recommended for use with these ADC's. See Layout Precautions and Power Supply Decoupling on next page. 6-68 LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AI D converter. Connect the input signal as shown in Table II. See Figure 4 for circuit details. Analog and digital commons are not connected internally in the ADC84 and ADC85, but should be connected together as close to the unit as possible, preferably to a large ground plane under the ADC. If these grounds must be run separately, use wide conductor pattern and a O.OI/lF to O.I/lF nonpolarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. BUFFER INPUT COMPo IN POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum or electrolytic type capacitors as shown in Figure 3 to obtain noise free operation. These capacitors should be located close to the ADC. I/lF electrolytic type capacitors should be bypassed with O.OI/lF ceramic capacitors for improved high frequency performance. COMPARATOR TO LOGIC FIGURE 4. Input Scaling Circuit - ADC84 and ADC85. TABLE II ADC84andADC85 Input Scaling Connections. For For DlNCllnput (_nolll) Connect Connect Input Pin 29 SIgMI To Pin To Pin Bun.red Inpur +liVDC 016. COM. .. • ::!f. II~F @) @) @ @ @) ~ • Input Signal Range Connect Connect Pin 23 Pin 25 TO Pin To Input ±10V COB or CTC Signal" 22 ±5V COB or CTC Open 22 ±2.5V COBorCTC 22 Pin 22 010 +5V CSB Pin 22 26 010 +10V CSB Open 26 ·15VDC I~F I+ • I~F I+ • ANA. COM. +15VOC FIGURE 3. Recommended Power Supply Uecouphng. Output Code 25 24 24 24 24 25 24 24 24 24 ·Connect to Pin 29 or Input signal as shown In next two COlumns. **The input signal is connected to Pin 30 if the buffer amplifier is used. NOTE: If the buffer amplifier is not used, the input Pin 30 must be groundf IPin26). OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the ADC as shown in Figures 5 and 6. Multiturn potentiometers with 100ppmj"C or better TCR's are recommended for minimum drift over temperature and time. These pots may be any value from IOkO to 100kO. All resistors should be 20% carbon or better. Pin 27 (Gain Adjust) and Pin 22 (Offset Adjust) may be left open if no external adjustment is required. (I) (b) +15VDC t IIICO f-\........!~~~ TO ~vv..--- lookn OFFSET ADJUST COMP.IN ·15VOC ADJUSTMENT PROCEDURE Offset - Connect the Offset potentiometer as shown in Figure 5. Sweep the input through the end point transition voltage that should cause an output transitIOn to all bits +15VOC 1IICO I@ 180kn COMP.IN ' llIIkn l~n f TO lOOkn OFFSET ADJUST ·15VOC FIGURE 5. Two Methods of Connecting Uptlonai Offset Adjust with a 0.4% of FSR Range of Adjustment. off (EoM'). (I) +15VOC Adjust the Offset potentiometer until the actual end point transition voltage occurs at E~~F. The ideal transition voltage values of the input are given in Table I. ::~UST f~:n 10Mn rz.n..~ .1. 'iii'T O.oI~F Gain - Connect the Gain adjust potentiometer as shown in Figure 6. Sweep the input through the end pomt transition voltage that should cause an output transition voltage to all bits on (EY~). Adjust the (Jain potentiometer until the actual end point transition voltage occurs at E?~. Table I details the transition voltage levels required. 'C/ ANA.~ lookn GAIN ADJUST ·15VDC COM. FIGURE 6. Two Methods of Connecting Optional Gain Adjust with a 0.6% Range of Adjustment. 6-69 CLOCK RATE CONTROL ALTERNATE CONNECTIONS If adjustment of the Clock Rate is desired for faster conversion speeds, the Clock Rate Control' may be connected to an external multi turn trim poterltiometer with TCR of ±IOOppmtC or less as shown in Figures 7A and 78. If the potentiometer is connected to -15 VDC, conversion time can be increased as shown in Figure 8. If these adjustments are used, delete the connections shown in Table III for pin 17. See Typical Performance Curves for nonlinearity error vs. clock frequency, and Figure 8 for the effect of the control voltage on clock speed. CLOCK ~TE CONTROL t:::\ +SVOC \1.!1- - - - - t' 2ko ADDITIONAL CONNECTION~ REQUIRED The ADC84 and ADC85 may be opera~ed at faster speeds for resolutions less than 12 or 10 bits depending on the model selected, by conm;cting the Short Cycle input, pin-14, as shown in Table Ill. Conversion spe~ds, linearity and resolutions are shown for reference. TABLE Ill. Short Cycle Connections and Specifications for 8- to 12-Bit Resolution RESOLUTION (BIts, 12 10 8 ponnect Pin 17 to 11) .Pin.I.5, Pin16 Pin 28 Connect Pin 14 to PinJ6 Pio,2. Pin,4, 10 6 4 0.01213) 0.04814) 0.2014) A4aximum Conversion ~peed (~seC)(i!1 Manimum Nonlinearity a1 25°C 1% of FSR I CLOCK FREQUENCY ADJUST NOTES: _ - (12-11IT RESOLUTION) RANGE OF ADJUSTMENT IS lO~11I: \a 6.8~_ FIGURE 7A. 12-Bit Clock Rate Control Optional Fine Adjust. CLOCK t:::\ RATl CONTROL +SVDC t CLOCK 5110 FREQUENCY ADJUST 18- OR I NIT RESOLUTION) 808fOJ: MlJUSTM.ENT IS ":' 1I.Ii~1C 11 4.o~1II: I... lO-bn Ind l5ullC FOR 8-BIT RESOLUTIONS. \1.!1----.... FIGURE 7B. 8-Bit Clock Rate Control OptIOnal J-me Adjust. 20 1'15' ! lO·~~~~~--~--;---+---r--;---+--~~ i!!i i ·5 '·4' 1. Connect only if clock rate control is not used. 2. Max. conversion speeds to maintain ±1I2LSB nonlinearity error. 3. 12·bi! models only. 4. 10· or 12·bit models. OUTPUT DRIVE Normally all ADC84 and ADC85 logic outputs will drive 2 standard TTL-loads; however, if long digital lines must be driven. external logic buffers are recommended. HEAT DISSIPATION The ADC84 and ADC85 dissipate approximately 1.2W and the packages have a case-to-ambient thermal resistance «oleA shOUld be lowered by a heat-sink or by forced air over the surface ofthe Plickage). See Figure 9 for ~CA requirement above 70°C. If the converter is mounted on Ii PC card. improved thermal contact with the copper ground plane under the case can be achieved using a silicone heat-sink compou,nd. On a O.062-inch thick PC card with 16 square-inch minimum area, this technique will allow operation to 85°C. Z 4 f 8 CONTROL VOLTAGE ON PIN 17 FIGURE 8. Conversion Time vs Clock Speed Control Voltage. 25~--_",,-- EXTERNAL CLOCK If an external clock is used, connect the external clock to convert command, pin 21. The convert command shown in Figure 2 is not used. After each conversion is completed, a new conversion cycle will automatically start of the first falling edge of the external clock fQllowing the completion of conversion. The clock-out signal will remain as shown in Figure 2 even if an external clock is used. The external clock pulse must be a negative going pulse with a width between IOOnsec and 200nsec as shown in Figure 2. 10 60 70 80 90 100 AMBIENT TEMPERATURE lOCI FIGURE 9. 6-70 (}CA ReqUIrement Aoove 70"C. liD HIGH RELIABILITY AID CONVERTERS Each of the ADC85 models are available screened to the requirements of the Burr-Brown Q-Program, which consists of a sequence of ihermal and mechanical stress High Temp. Storege I (MIL-STD-883) Method 1008 Condition B +125°C 24 Hours procedures, plus a verification of package hermeticity. The diagram below illustrates the screening sequence which is applied to 100% of the Q-Screened AID converters. Temperature Cycling (MIL-STD-883) (MIL-STD~) HermlUcIly Fine Leak (MIL-STD-883) Method 1010 Condition B -55 to +25°C 10 Cycle. Method 1014 Conditione Step 1 Fluorocarbon Method 1014 Condition A Helium 5 x 1 ([7cc/sec Hermetlclly GrOll Leak Bum-In (MIL-STD-883) Centrifuge (MIL-STD-883) Method 1015 Condition 0 168 Hours +700C (ADC85CI +85°C (ADC851 Method 2001 2,000 G Y1 Axis MECHANICAL ................ .. ADC85. ADC85C I-----A ---""" 17 IE=J "'--.. . I I :--1 t!!.111111111111 T o-el D-I, -t!--" ~ c- , " NOTE: Leads in true position within 0.010' (0.255mml R at MMC at seating plane. . - .- INCHES MAX . ,.,. DIM A 1.700 1.7. C ..... .... .oz• D F 0 " K L N " 1.'. .170 .IM .1OO.Alle .- .."0 .'10 .'30 .....AlIC .01. ."0 .• 30 ................ .••.•.•....•.•.. 32 MlWMETERS MIN NOTE: Leads in true position within 0.010' 10.255mm I Rat MMC at seating plane. MAX ".70 ........ ............... 43." .... .... ..... .... .... ..... 1.27 2. . . . . .C 2.7' I.al PINS: Pin material and plating composition conform to method 2003 I~olderabilityl of MILSTD-883 1except paragraph 3.21 CASE: Ceramic MATING CONNECTOR: 2302MC Set of two l~-pin strips WEIGHT: 13 grams (0.46 oz. 1 17 pin numbers shown for reference only. Numbers may not be marked on package. ?INS: Pin material and plating :::omposition conform to method DIM MININCH~ :~e:: ~~Og~~'~:~:~~~~~~g~!~~ 3.21 A '.720 '.710 ~~~~~0~~N~~~~6~:t~02MC ~ ':::: '::: Set of two 16-pin strips WEIGHT: 13 grams 10.46 OZ. 1 22_ItAIIC 2.7' D G " .0'1 .021 .1DO.ASIC Ai D Converter Family: .1110 .300 " .1DO .'40 ADC"85 AD("84 XX ~ Grade: Blank (·25"(", +85"C"XA[)C"85 only) C" (0"(", +70"OADC"85 only) KG (0"(", +70"C")(ADC"84 only) 6-71 "::: Resolution: 10= 10 bits 12= 12 bits ".7. -::. 0.41 0.13 2.M.ASIC 2." K ORDERING INFORMATION ADCXX 43." .... .... 3.1' 7.12 22. . . .ASIC 2." BURR-BROWN® ADC100 IEiIaI High Resolution - Integrating ANALOG-TO-DIGITAL CONVERTER FEATURES· -16-BIT RESOLUTION -SELF-CONTAINED MODULAR PACKAGE -LOW DRIFT .USER-ADJUSTABLE LINEARITY - EXPANDABLE TO 5-OIGIT BCD RESOLUTION DESCRIPTION The Burr-Brown Model ADClOO AID Converter is an integrating AID Converter that utilizes the delta sigma modulation principle. The digital equivalent of analog signals is developed by counting a number of pulses whose average repetition rate is proportional to the amplitude of the input signal over a fixed integration period. The internal clock is externallyadjustable to provide integration periods which are integral multiples of 50Hz or 60Hz periods for maximum power line noise rejection. The closed conversion loop assures linear performance of ±o.005% ±I count that is independent of clock frequency deviations over the specified temperature . range of ODC !o ±70°C. The ADClOO is housed in a rx4"x0.4"moduleand operates from ±15VDC and +5VDC power. All digital input and output signals are TTL-compatible. Four basic models are offered: Unipolar 4-digit BCD, 4-digit plus sign BCD, unipolar and bipolar 16-bit binary. The binary units are pin-programmable for 12-, 14-, or 16-bit resolution. The ADCIOO is excellent for applications which require good accuracy and high resolution, but where speed is not too important. Conversion speeds range from 12msec for 12-bit binary to 30msec for 4-digit plus sign BCD· codes. . Digital Output Code Inl8rnlllon.1 Alrplll1lnd..IrI.1 Parte· P.O. Box-1I400· Tuclon. ArlZlln. 85734· TIl. (602) 746-1111· Twx: 910-952·1111 . Cable: BBRCORP· Telex: 66-6491 PDS·286D 6-72 SPECIFICATIONS Typical at 25°C and rated power supply unless otherwise noted. NOTE, ELECTRICAL r---- R. LeD in true ~Ion within .015" (.38mm1 MMC at Meting plene. MODEL DECIMAL ADC100 BCD· RESOLUTION 4 digits BINARY Unipolar p'ipolar USB BOB SMD 4 digits 14 or 14 or 16 bils 16 bits + sign A --- UNITS INPUT ANALOG INPUT Voltage Range Maximum Safe Input Signal Input Bias Curren,t typ max Impedance Buffered Unbuffered Settling Time (to 0.003%) FSR(2) stepi Buffered, inax Unbuffered, max [ DIGITAL ."ru. Convert Command External Clock o to +10 ±10 OtO+IO 1±10 V ±2SVor supply vol~:, whichewris l~$s nA 200 nA MO 200 200 200 200 10(1) 10 10 25 kO ~ OJ ACCURACY DRIFT Temperature Coefficient (max) POWER SUPPLY SENSITIVITY Power Supply Sensitivity, max ±15VDC +SVDC CONVERSION TIME (maximum with Internal Clock) End of Conversion elL H lor,.,.... only. Numben "+" INCHES DIM .05 .02 ±0.005 +10 .05 .05 .02 .02 ±0.005 ±0.005 ±l count .05 .05 ±0.005 +5 +10 ±10 MAl.. A 3 .... 1,860 ".010 2,010 100,53 -"- .02' 0.48 . %ofFSR %ofFSR %of FSR(2) c . 351 0 .019 ~mofFSR/oC o.no... mi_i"" pins. MILLIMETERS MIN MAX MIN ... 49.53 '0' 61.05 '0.., 0.53 ,.S, BASIC .150 3.81 .250 6.36 .250 .350 1.BOO BASIC B.B9 6.35 45.72 BASIC .200 BASIC .000 .150 5.08 BASIC 1.27 3.B1 NOTE: to.007 to.002 ±0.004 to.0002 to.0002 % of FSR/% of. P.S. Volta~e(l 5V) to.OOI to.002 to.OOI 30 30 L.... in truepo,itiOn wit";n .015" (.3BmmJ R .. MMC.t _.tln9 pl.ne. ~. ! ~~ For 12 !>its - l2.5 14 bits - SO msec 16 bits - 200 E~.~ I. 111111 ... ~ml"'l11 IE] r-. . I...... p-.l --L...o L-...I Cl r units) which will drive 4 TTL loads. "0" during conversion L .......... H Pin numbtlrsshown for r.ferenee onl .... Nu,:,beu m.vnot btl m.rked on p.ek ••. +t ....................... . , .36 R °c °c °c o to +70 ~25 to +85 -55 to +100 i 1--1"_ A . ~s~~~~~j~5'tf) TTL/DTL Compatible All digital outputs will drive 6 TTL loads except the sign bit (for SMD TEMPERATURE Specification Operati"g(reduced specs) Storage POWER SUPPL Y Rated Voltage Range (max) Supply Drain +15VDC -15VDC +SVDC 0 1--.- L---.i,I Pin nurnt.'llhown fMY not bII...,.rUd 25 SO 25 SO ,",sec I I I I ~sec TTL/DTL Compatible Logical U 1" for atlesslone cJocIIGITAL DATA STABLE---..J DISCUSSION OF SPECIFICATIONS ANALOG INPUT SETTLING TIME is the time required after a F .S.R. input step for the converter's input circuitry to settle to specified accuracy. The CONVERT COMMAND should be delayed by this period of time after any large input voltage change to preserve the converter's.accuracy. ACCURACY - The basic accuracy of the ADCloo is defined by linearity and quantizing errors. When gain and offset errors are adjusted as described on page 6-77, the accuracy of the ADCIOO is 0.005% ±I count. LINEARITY ERROR is a measure of the deviation of the converter's actual transfer characteristic from the ideal. It is defined as the maximum deviation of the actual converter transfer function from the best fit straight line throug.h it. If the linearity error is also adjusted (see page 6-78) the accuracy will typically be 0.002% ± I cou~t. QUANTIZING ERROR is inherent in any AID converter simply because a converter's analog input is continuous while its digital output must be discrete codes. The ADC 100 is designed such that increased resolution may be obtained by interpolation of several successive conversions of the same input voltage. For example, if the output code is zero for three conversions and. one LSB for one conversion, the actual input voltage is one quarter of an LSB. ACCURACY DRIFT is the maximum change with temperature of any point on the converter's transfer characteristic. OFFSET ERROR is the deviation from the ideal input required to produce an output of all logical zeroes (all bits OFF). GAIN ERROR is the deviation from the ideal input required to produce an output of all logical ones (all bits ON) with the offset error adjusted to zero. SERIAL OUTPUT The serial output of the ADC I 00 may be used to transmit data remotely over a single line. Details for implementing this method of data transmission are shown on page 6-79 of this data sheet. DI.sJTAL OUTPUT CODES For unipolar analog input signals, 4 digit BCD or 16 bit straight binary (USB) digital output codes are offered; for bipolar analog input signals, 4 digit plus sign BCD (SMD) or 16 bit offset binary (BOB) digital output codes are offered. The LSB & full scale aralog values arid equivalent digital codes are shown in Table I. 6-74 ORDERING INFORMATION The ADC 100 may be ordered by using the ordering code below. =t=Converter Family xxx T OUTPUT CODE BCD - Binary Cod.ed Decimal SMD - Sign Magnitude BCD USB - Unipolar Straight Binary BOB - Bipolar Offset Binary INSTALLATION and OPERATING INSTRUCTIONS EXTERNAL CLOCK An external clock may be used by leaving CLOCK OUT, CLOCK OPERATION The ADCIOO may be operated from the internal clock, or from a user supplied external clock. pin 26, open and connecting the external clock to CLOCK IN ,pin 28. The duty cycle of the external clock should be 80% to 90% as shown in Figure 3. A clock period faster than 2.5 ILseconds or slower than 25ILseconds will degrade the performance of the ADC 100. 50 Hz or 60 Hz rejection may be achieved by adjusting the clock frequency such that the CONVERT COMPLETE pulse is an integral number of 50 or 60 Hz periods (i.e., a multiple of 16.67 ms for 60 Hz rejection or 20.00 ms for 50 Hz rejection). For example, SMD or BCD units convert in 30 millisec with a clock period of 3 ILsec. The closest multiple for 60 Hz rejection is 33.33 ms integration time. INTERNAL CLOCK If the internal clock is used, CLOCK OUT, pin 26, and CLOCK ~N, pin 28, must be connected together. The approximate period of the internal clock is 3 ILseconds. The internal clock frequency may be adjusted using the circuit shown in F"igure 5 over a range of approximately 2.5 ILsec to 25 ILsec. If the clock frequency is not adjusted, pin 21 should simply be left open. 6-75 CONNECTION DIAGRAMS TOP VIEW TOP VIEW Convert Command NOTE 1. See Figure 3 for details of clock. FIGURE 2a. BCD and SMD Models. .NOTE 1; See figure 3 for details of clock. *To pins 60, 69 and 70 FIGURE 2b. USB and BOB Models. ANALOG COMMON, pins 3 and 23, are connected together internally as are DIGITAL COMMON, pins 30, 40 and 41. Digital and Analog Common are not connected internally; but they should be tied together at some point in the system as close as possible to the ADC 100 to prevent any difference voltage between them. INATE IN, pin 42. The LSB will always be on pin 44, the MSB for 16 bits is on pin 72, for 14 bits is on pin 67, for 12 bits is on pin 63. BCD and SMD units are marked as shown in Figure 4, the SMDunits only will have connections for ADJ, pin 1 and pin 5, and SIGN OUT, pin 9. All units have available a spare inverter (SN7404) whose input is pin 22 and output is pin 24. For BCD and SMD units, TERMINATE OUT, pin 69, should be connected to TERMINATE IN, pin 42, for 4-digit operation (see page 6-79 for increased resolution). USB and BOB units are marked as shown in Figure 3, the BOB units only will have a connection for BIPOLAR OFFSET, pin 19. The BOB units must have pin 19 externally connected by the user to SUMMING JUNCTION, pin 20. NOTE: For SMD units, the output sign bit operates continuously. That is, the sign bit output will change with the input voltage polarity even though the end of conversion output is "high". Therefore an output flip flop (such as the 7474 IC shown on page 6-77) may be used to store the sign bit at the end of conversion. (The PC mount option includes this flip-flop). For USB and BOB units, either 16-BIT TERMINATE, pin 69, 14-BIT TERMINATE, pin 70, or 12-BIT TERMINATE, pin 60, must be connected to TERM- 6-76 CONNECTIONS FOR INPUT SIGNAL, EXTERNAL GAIN and OFFSET TRIM 10 Mn .....'VI.A. .~ GAIN TRIM IO?:11 I Mil FIGURE 3. GAIN and OFFSET Adjustments for all Converters. BOB MODELS The connections shown in Figure 3 illustrate various input and trim connection options; it is not necessary to include switches or jumpers as indicated unless that level of flexibility is desired. If linea"ity is 'not externally adjusted. the transfer characteristic of the. ADC.I00 can be adjusted for minimum errors using only the GAIN and OFFSET adiustments. Table I shows the input voltage and respective output codes for these adjustments. Using the OFFSET adjustment, adjust to the output code of 0100 . . . . 00 with an input of -5.0000 volts; then find the input voltage. (near +5.00 volts), that causes an outP1:lt.code of 1100 ... 000. Set the input voltage to a point halfway between e and 5.0000 volts. Use the GAIN adjustment to provide an output "f 1100 . . . 000. Repeat the OFFSET adjustment at -5.0000. volts and check to see that an input of +5.00000 volts produces an output code of 1100 ... 000. (See Table I). Repeat until both are optimum. BCD and USB MODElS Adjust to the proper output code with an input of +2.5000 volts using ·the OFFSET adjustment; then adjust to the proper . output code with +7.5000 volts input using the GAIN adjustment (see Figure 3 for circuitry and Table I for input/output values). Repeat until both are optimum. WIRING PRECAUTIONS All connections between the ADCI00 and external components should be as short as possible to minimize coupling effects and noise pickup. The +5 V logic supply must be bypassed with a 100 to 200 ~F tantalum capacitor to digital common to preserve ADC 100 linearity, particularly near mid-scale. Experimenting by setting full scale and zero exactly correct and checking at or near mid-scale while varying the power supply decoupling will demonstrate the quality of the bypassing. This should be done first without any of the clock and/or linearity adjust circuitry, and then with the circuitry if it is to be used. SMD MODELS Adjust,to'the proper output codes as described above for BCD and USB models at 2.500 and +7.500 volts; then use the negative OFFSET adjustment (as shown in Figure 4) to provide the proper output code with -10 mV input and the negative GAIN adjustment (also in Figure 4) to provide the proper output code with -9.9900 volts input (see Table I). SMD SIGN BIT STORAGE FIGURE 4. Additional NEGATIVE GAIN and OFFSET Adjustments required for SMD Converters. {see note on page 6·76l. UNUSED ADJUSTMENTS To Pin 9 D All unu80ed adjustments should be left open except OFFSET adjust which should be grounded. (Sign Out) To Pin 39 Endof~ ____________~ ClJnv CODE BCD 4 digit USB 12 bils 14 bits 16 bits SMD Positive Negative One LSB (mV) 12 bits 14 bits 16 bits OUTPUT CODE MSB LSB 00100101 00000000 1.00 +2.5000 2.44 0.61 0.15 +2.5000 +2.5000 +2.5000 010000000000 01000000000000 0100000000000000 1.00 +2.5000 -0.0100 I 00100101 00000000 0000000000001 0000 4.88 1.22 0.31 NOTE: Negative full scale is O.OOOV for BOB 1/4 Scale OFFSET Adiust Input Voltage 3/4 Scale GAIN Adiust Input Voltage +7.5000 +7.5000 +7.5000 +7.50000 +7.5000 -9.9900 OUTPUT CODE LSB MSB 0111 0101 00000000 110000000000 11000000000000 1100000000000000 10111 0101 00000000 01001 1001 10010000 II 0000000000 +5.0000 11000000000000 +5.0000 1100000000000000 +5.00000 unipolar and -10.000V for bipolar models. Positive full scale is +10.000V -1 LSD. -5.0000 -5.0000 -5.00000 010000000000 01000000000000 01 00000000000000 TABLE 1. GAIN and OFFSET Adjustments without LINEARITY Trim. 6-77 - , CLOCK and LINEARITY ADJUSTMENTS CLOCIADJUST It may be necessary to adjust the clock frequency if optimum noise rejection to 50 or 60 Hz power line frequency is de~i~ed, or else a specific conversion period is desired. Otherwise, an external clock adjustment is not required. The ,CLOCK ADJUST trim circuitry shown in Figure 5 may affect linearity', particularly where there is already a bypassing problem with the 5 volt logic suppiy. If clock trim is employed, it may also be necessary to perform the linearity adjustment de~cribed below. The external wiring at pin 21 should be as short as possible to minimize this problem. NOTE 1. Use tantalum capacitor. NOTE: The 400 kHz clock frequency will vary up to I % per degree Centigrade. This will have a very small affect on the accuracy of the ADC 100, but it can cause problems in some systems applications since the total conversion time will vary inversely with this frequency. FIGURE 5. CLOCK ADJUST Circuit. LINEARITY ADJUSTMENT Linearity errors can typically be adjusted to less than 0.002% with the circuitry shown in Figure 6. This adjustment can be done only when the internal clock is used. If the LINEARITY adjust circuitry is used, the OFFSET adjustment should be made near negative full scale, the GAIN adjustment should be made near positive full scale, and linearity adjusted near mid-scale. See Table II for the proper input voltages and output codes. NOTES: 1. This wire should be as short as possible 2. This connection required only when external clock is used. With GAIN and OFFSET adjusted per above, the linearity error should be adjusted to zero near mid-scale. Supply the ADClOO input with the mid-scale voltage shown in Table II and adjust the linearity potentiometer to obtain the output code also specified in Table II. FIGURE 6. LINEARITY Adjustment Circuit. OFFSET Adjustment CODE BCD 4 digit USB 12 bits 14 bits 16 bits Input Voltage Output Code +0.0100 MSB LSB 0000 0000 0001 0000 +0.00976 +0.00976 +0.00976 Positve Negative +0.0100 -0.0100 BOB 12 bits 14 bits ,16 bits -9.99024 -9.99024 -9.99024 GAIN Adjustment Input Voltage Output Code Mid·Scale LINEARITY Adjust Input Voltage Output Code +9.9900 MSB LSB 1001 1001 1001 OOQO +5.010 MSB LSB 0101 00000001 0000 000000000100 00000000010000 0000000001000000 +9.9878 +9.9896 +9.9901 111111111011 11111111101111 1111111110111111 +5.00488 +5.00488 +5.00488 100000000010 10000000001000 1000000000 I 00000 I 000000000001 0000 0000000000001 0000 +9.9900 -9.9900 1 1001 1001 1001 0000 01001 1001 1001 0000 +5.010 1 0101 00000001 0000 +9.9854 +9.9890 +9.9898 111111111101 11111111110111 1111111111011111 +0.00976 +0.00976 +0.00976 SMD 000000000010 00'000000001000 000000000010000 TABLE II. GAIN and OFFSET Adjustments with LINEARITY Trim. 6-78 -- - 1 000000000 I 0 10000000001000 10000000001 Qqooo APPLICATIONS VOLTAGE TO FREQUENCY CONVERTER The CURRENT output, pin 32, and the CI1i'CR output,pin 34, may be used to provide a continuous serial output pulse train whose average repetition rate is proportional to the analog input voltage. This circuitry is shown in solid lines in Figure 8. The END OF CONVERSION output, pin 39, can be gated with the serial output using the additional circuitry shown with dotted lines. The gated output pulse train is available only during conversion and the number of pulses in that period is proportional to the input voltage, as shown in Figure 7. Ci:iR"REN"T ~ I I CLOCK 32 1/47400 CLOCK 39 END OF CONVERT , I I , b-- L""L_./ : I LJ I I r- rl ~ I r----...J I I I : 1/47400 1/47402 L~, n SERIAL OUTPUT I n Serial Output Serial Vin Where C ::;: Clock Frequency Output Rate = C x V full scale ;;:: 400 kHz. FIGURE 7. Typical Output Waveforms. 5 DIGIT ADC100 o-~ ----I- ,,'Gated FIGURE 8. Voltage to Frequency Converter The components required in addition to the ADC I 00 are: The resolution of BCD and SMD models may be expanded to 4-1/2 or 5 digits with a minimum of external circuitry. Expansion to 4-1/2 digits will double the conversion time to about 60 milliseconds while 5 digit conversion will require 300 milliseconds. Figure 9 shows the application of two SN 7490 decade counters to provide an extra digit output. (I) (2) If the ADC 100 is used for five digit operation, it is recom· mended that the linearity adjustment cirCUitry shown on page 6-78 be used to provide accuracy consistent with the resolution. With five digit operation, the positive full scale input voltage is +9.99990 volts while the negative full scale input is 0.00000 volts (BCD) or -9.99990 (SMD). A good mid·scale input voltage to use for the linearity adjustment is 5.00500 volts (output code 0101 000000000101 0000). ADC100 PREAMPLIFIER (3) (4) Two decade counters (such as TI's SN7490) Five BCD to seven segment decoders (such at Tl's SN7447A) A display (such as RCA's DR2100 Numitron series) Power Supplies, ±15 volts and +5 volts (such as Burr· Brown's Model 551 and Model 562). An instrumentation amplifier may be used as the input to the ADC I 00. An input instrumentation amplifier such as Burr·Brown's 3625 will provide differential inputs with common mode rejection as well as gain. The circuitry shown below will provide a gain of 10 (Le., I volt instead of 10 volt input range) and 74 dB CMR. Linearity Correction Network 36 Adjustment Circuitry 35 FIGURE 10. Differential Input ADCIOO. FIGURE 9. Extending ADC 100 to 5 Digits. The ADCIOOmay be used as the heart of a 5 digitDPMwith accuracy much better than that of any moderately priced digital panel meters at a lower cost. The offset adjustment of the ADC I 00 has enough range to compensate for the small output offset of the 3625 and its' gain adjustment can compensate for the gain errors of the 3625 The 3625B will add no more than 10 ppm/oC gain drift and I ppm/oC offset drift while contributing only 0.002% linearity errors. 6-79 BURR-BROWN® DAC10HT IElElI Wide Temperature Range General Purpose 12-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES • -55°C to -t:2O()OC SPECIFICATIONS • FULL 12-BIT RESOLUTION • 200nsec SETTLING TIME. TYPICAL • MONOTONIC OVER FULL TEMPERATURE RANGE . • TTL AND CMOS COMPATIBLE • HERMETIC DUAL-WIDTH CERAMIC PACKAGE DESCRIPTION Designed for use in circuits that operate over a wide temperature range, DAC IOHT is a general purpose, 12-bit P / A converter. The design uses state-of-theart integrated circuit and laser-trimmed thin-film techniques for maximum accuracy. Compatible with TTL and CMOS logic, ·DACIOHT is monotonic over the full "55"C to +200°C temperture range. Special design techniques minimize output glitches. The package is c.ompact, dual-width, 24-pin ceramic DlL. 100% screening operations are conducted at key manufacturing steps. Burn-in and temperature cycling are examples, and the product is assembled ina clean-room environment. GAIN SETTlING RESISTOR . . . . . - - -.....- - 0 DIGITAL INPUTS Il·BIT LADDER RESISTOR . NETWORK AND CURRENT SWITCHES I EXTERNAL OUTPUT AMPLIfiER BIPOlARC OffSET RESISTOR .REfERENCE CONTROL . CIRCUIT EXTERNAL } REfERENCE Inlernatiooal Airporllnduslriai Park· P.O. Box 11400· Tucson. Arizona 85734· TeI.160Zl746·1111· Twx: 910.952·1111 . Cable: BBRCORp· Telax: 66·6491 PIlS-475 6-80 SPECIFICATIONS ELECTRICAL Specifications at Vee ~ +15VDC VEE ~ -15VDC Reference ~ +10VDC and TA ~ +25°C unless otherwise noted MODEL MIN DAC10HT TYP MAX I MIN 'DAC10HT-1 TYP I MAX I UNfTS fNPUT DIGITAL INPUTS Resolution TTL-Logic "I" at l00nA, max Logic "0" at -100~A, max CMOSI1I-Logic "I" at 100nA, max Logic "0" at -1 OO~A, max 12 2.0 12 2.0 Bits 30% Vee V V V V ±1/4 ±1/2 LSB LSB 0.05 0.05 0.2 0.2 0.2 LSB LSB % % of FSR %ot FSR +200 °C °C ±1/2 ±1 LSB LSB 0.8 70% Vee 0.8 70% Vee 30% Vee TRANSFER CHARACTERISTICS ACCURACY Linearity Error at +25°C 12-Bit lo-Bit at -55°C to +2000C 12-Bit lo-Bit Gain Error(2) Bipolar Offset Error I input all O's (2) Unipolar Offset Error I input all 0'S(2) Monotonic Temperature Range 12-Bit lo-Bit Differential Linearity Error 12-Bit IO-Bit Total Unadjusted Error(3) +25°C ·55°C to +2O()OC Total Adjusted Erron4) +25°C -55°C to +2000 C ±1/4 ±1/2 ±2 ±2 0.05 0.05 0.2 0.2 0.2 -55 +200 -55 ±1/2 CONVERSION SPEED Settling Time to 1/2LSB 1+FSchange 1(5) ±1 ±0.1 ±o.3 ±0.4 ±0.8 ±0.15 ±0.90 ±0.45 ±1.30 %of FSR % of FSR ±0.008 +0.015 ±o.012 ±o.40 0.024 +0.40 ±o.048 +0.90 %of FSR %of FSR 200 Major Carry Glitch Duration I to 90% complete I 200 35 nsec nsec 35 DRI" I-55°C to +200oC 1 Gain I exclusive of reference drift) Bipolar Offset Unipolar Offset Differential Linearity ±5 ±5 ±2 ±3 ±10 ±10 ±1 ±3 ±2 ±2 ±0.5 ±2 ±25 ±25 ±5 ±4 ppm/oC ppm of FSR/oC . ppm of FSR/oC ppm of FSR/oC OUTPUT ~2~:~:251 Current ~ Unipolar 1±10%1 Aesistance Capacitance Compliance Voltage ~2.~ :~ o to +5, 0 to +10, -2.5 to +2.5, -5 to +5, -10 to +10 1.0 20 -3 +10' :2.51 o to +5, 0 to +10, -2.5 to +2.5 -5 to +5, -10 to +10 1.0 20 -3 +10 ±0.25 ±0.25 ±0.25 ±o.25 ±o.25 ±O.25 30 30 Current - Bipolar I ±lO%J Selectable RangeslB) I EXTERNAL ADJUSTMENTS Gain Adjust Range Bipolar Offset Adjust Range Unipolar Offset Adjust Range NOISE 10.IHz to 10Hz, all "1"sl I I I mA mA V kll pF V % of FSR % of FSR % of FSR .~V, POp MULTIPLYING MODE PERFORMANCE Number 01 Quadrantsl7) Reference Voltage Range Accuracy(8) 2 +10.24 0 ·±0.05 Feedthrough(9) Output Slew Ratel lO) Output Settling Time Ito 0.01% of FS(ll0) Control Amplifier BW I small-signal, closed-loop I 2 +10.24 0 ±0.05 V ±0.02 6 3 ±0.02 6 3 % of FSR % of FSR mAl#,sec ,usee 10 10 MHz POWER SUPPLIES AND REFERENCE Reference Input Impedance Reference Voltage Range Power Supply, Voltage ~ Vee Voltage - VEE Current· Vee Current· VEe Power Supply Sensitivity Vee at +5VDC VEE at -15VDC 8±10% 8±10% 0 +4.75 -13.5 -15 +9 -28 +10.24 +15.0 -16.5 +15.0 -40.0 1 3 5 10 6-81 0 +4.75 -13.5 -15 +9 -28 kU +10.24 +15.0 -16.5 1 5 3 10 V VDC VDC mA mA ppm/%t.V ppm/%t.V SPECIFICATIONS MODEL I MIN DAC10HT I TVP I MAXI MIN +200-1 +200 +210 -65 DAC10HT-1 I I TVP MAX I UNITS TEMPERATURE RANGE . Specification Operaling Siorage 1 -55 -55 -65 I 1 NOTES: 1. +4.75V < Vee < +15.0V and pin21ied 10 pin 1. 2. Adjuslable 10 zero 1_ Figures 4 and5). 3. Includes Gain, Offsel, and Linearily Errors wilh exlernal +10.0V ±1 mV reference. Does not include Reference Drift. 4. Gain and Offsel Errors removed al +25°C wilh exlernal +10.OV ±1 mV reference. Does not include Reference Drift. 5. Current settling into short circuit. 6. Using inlernal scaling' resislors and OPA 11 HT oulpul op amp. 7. Bipolar operalion at digital inputs only. 8. For WDC reference voltage 1sea Figure 21. Full. Scale Range = W. 9. Voltage at reference input: 0 10 +IOV. 2kHz sine wave 1see Figure 31. 10. All "1"s.10V stepan reference input. -55· -55. I I +200 +200 +210 ·1 °C °C dC PIN DESIGNATIONS -tVee 1 LOGIC THRESHOLD 2 VREF INPUT I LO I 3 N/C 4 VREF INPUT IHI, 5 -VEE 6 BIPOLAR OFFSET 7 BIPOLAR OFFSET 8 CURRENT OUTPUT 9 10V RANGE 10 20V RANGE 11 COMMON 1'2 24 BIT llMSBI 23 BIT2 22 BIT3 21 BIT4 20 BIT5 19 BIT6 18 BIT7 17 BITe 16 BIT9 15 BIT10 14 BIT11 13 BIT 12ILSB, MECHANICAL 2' 01 I. 0 A 13 12 F-J~'I . 3:! Jmmtffftd l=:'-oJaL ~SealingPlane -LJ Pin numbers shown for reference O~IY. Numbers may nol be marked on package. L NOTE: Leads in Irue position within 0.010· 10.25mmIR.et MMC al sealing plane. CONNECTION DIAGRAM - UNIPOLAR ~ INCHES DIM 0 a MIN MIN MAX 1.215 30.10 30.86 .105 .015 .035 .170 .021 2,67 0.38 0.53 0.89 1.52 .100 BASIC .030 .070 .008 ,012 .120, .. 240 .025 .060 4.32 2.54 BASIC 0.76 178 0.20 3.05 6.10 15.24 B SIC 0.30 100 100 M 0.64 CASE: Ceramic with hermetic seal CONNECTION DIAGRAM - BIPOLAR Bill Bit 12 \MSBI III 2 .BII 3 Bit 4 Bit 5 Bn 6 BII 7 BII B Bit 9 Bill 0 BII II (LSB) 12 -15VDC .060 .600 BASIC ~~ Bit 1 . B1112 \MSBI 1112 Bit 3 BII 4 BII5 Bit 6 Bn 7 Bit 8 BII 9 Bit 10 Bit UtaBI +51+15VDC MAX MILLIMETERS '.185 12 +15VDC +5/+15VDC D.l"F .15VDC -In high temperature environments with high levols 01 shock and vibration it is recommended that discrete wirewound or 'metal film resistors be used instead of potentiometers. 6-82 ~ISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES DACIOHT accepts a positive-true straight binary (BIN) input code. Offset-binary code is created by offsetting the output amplifier with the DAC reference. Two's complement code is obtained from offset binary by inverting bit I (the most significant bit) externally. See Table I. DACIOHT. Leakage Current is measured at the converter output with logic 0 on all digital inputs. It appears as part of offset error, both at room temperature and over the specified temperature range. In the unipolar configuration, virtually all offset error is due to leakage current. ACCURACY Linearity ofthe DAC 10 HT is guaranteed to be within the specification over its temperature range. This is the measure of the deviation of the actual transfer curve from the ideal transfer curve expressed graphically as a straight line drawn between the end~point values. For the DACIOHT the maximum deviation is ±1/2LSB at 2SoC and ± I LSB over the full specification temperature range from -SSoC to +200"C. DRIFT Gain Drift is a measure of the change in the full scale range output due to a change in temperature and is expressed in parts per million per °C (ppm/"C). It is calculated by determining the full scale range value at high temperature, then at low temperature. The difference in the two values is divided by the difference in the two temperatures. Differential Linearity error is the deviation from an ideal I LSB output voltage change from one adjacent state to the next. An error specification of ± 1/2LSB indicates that output voltage step size can range from 1/2LSB to J/2LSB between adjacent states. Monotonicity is an important property for a 01 A 'converter, especially one used in a closed control loop. A converter is monotonic if the output signal increases or remains the same for an increase in digital input. A converter's differential linearity determines whether or not it is monotonic. If differential linearity is <±I LSB, the converter will be monotonic. Monotonicity is guar~ anteed over the entire specified temperature range for the Offset Drift is a measure of the actual change in output over the specified temperature range with logic 0 on all digital inputs. It is calculated by measuring offset voltage at the temperature extremes. The maximum change referred to the offset voltage at +2SoC is divided by the temperature excursion from +2S°C. Offset drift is expressed in parts per million of full scale range per °C (ppm of FSR/"C). Differential Linearity Drift (the change in differential linearity over the specified temperature range) is calculated in a manner similar to offset drift and is expressed mppm of FSR/"C. TABLE I. Digital Input Codes. DIGIT....L INPUT CODES ....N....LOG OUTPUT LOGIC INPUTS VOLT....GE· CURRENT Binary o to +10V -10V to +10V o to -2m.... ·lm .... tO+lm.... "11,,,,',1, 100000000000 011111111111 OOOOOOOOOOOO +9.9878V +5.0000V +4.9878V O.OOOOV +9.98S1V O.OOOOV -o.0048V -10.0000V -1.9895mA -1.0000mA -O.9895m.... O.OOOOm.... -O.9895m.... O.OOOOm.... +O.OOO5m .... +1.0000m .... B1na!l Two'. Coml!tement·· lLSB IBINI -O.9895m.... O.OOOOm .... +O.OOO5m.... +1.0000m.... +9.8951V O.OOOOV -0.0048V -10.000V 0"",,1',11 OOOOOOOOOOOO 1111111111" 100000000000 2.44mV 'TO obtlln v.I .... 'or other bln.ry r.nee.: 010 +5V r.nge: divide 0 to +IOV ranee v.lue. by 2. ±5V r.nee: dlvlda ±10V r.nge v.lues by 2. 4.88mV 0.488,..... 0.488,..... ±2.5V range. divide ±10V range values by 4. '-MSB must be inverted externally 'or this code. CONVERSION SPEED Settling Time is the time required for the output to enter and remain within an error band of the final value measured from the time the digital input is changed. internal current switches. For a I LSB change at the major carry point, settling time to within 0.0 I% will typically be 2OOnsec. The settling time for a I LSB change at the input is naturally less than for a full scale change. It is greatest at the major carry point (the point at which all of the bits change states) due to nonuniform switching times of the COMPLIANCE VOLTAGE This is the maximum voltage which can be impressed on the current output node and still remain within the specified accuracy. These voltages are -J.OV and +IOV. 6-83 POWER SUPPLY SENSITIVITY This measure of the effect of a power supply voltage change on the D/ A converter output is defined as a percent of FSR/percent of change in either the +SV, + ISV or -ISV power supplies about the nominal supply voltages. Figure I shows power supply rejection vs frequency. 'Feed through of the DAC IOHT is the amount ,of reference signal that appears at the output when all digital inputs are logic O. Expressed in % of FSR, it increases with increasing reference frequencY'(see 'Figure 3). . .0.08 o.rn 1000 0.06 ii ~ "0 +15 :; 100 and Current Switches tL Bit 10@ Bit 11@ (4) FSR means fulL~1e range and is lOV for ±IOV range. IOV f~r 0 to +IOV range. etc. (S) Gain and offset are externally adjustable to zero (see page S~S2). (6) Worse case conditions measured at the worst case major carry (mid~scale). (7) With external Burr~Brown Model3500C op amp or equivalent. using internal feedback resistors., (8) The current output should be connected to the vinual ground of an amplifier summing junction to obtain specified accuracy, .(9~ W,ith no degre Bit IS IiY Bit 14 ~BitU *. 6.3k Bipolar Offset Resistor (COli only) DISCUSSION OF SPECIFICATIONS OFFSET DRIFT DIGITAL INPUT CODES OFFSET DRIFT is a measure of the actual change in the vg~~)over the specified temp· The DAC70 accepts complementary digital input codes in either binary (CBI) or decimal (CCD) format. The COB model may be user connected for either complementary offset binary (COB) or complementary two's complement (CTC) codes as shown in Table I. output with all bits OFF( erature range. vg~~ is measured at -25 0 C or OOC, +25 0C and +700C or +85 0C. The maximum charge in OFFSET is referenced to the OFFSET at 25 0C divided by the temperature range. This drift is expressed in parts per million of full scale range per °c (ppm of FSR/°C). DIGITAL INPUT CODES Logic Inputs ...i MSB LSB ~" All bits OFF 0000 ••• 000 ~ Mid Scale All bits ON. CSB COB Compl. Compl. Offset Binary Straight Binary CTCCompl. Two's Complement +Full Scale +Full Scale -1 LSB 0111 ••• 111 . +%Full Scale Zero -Full Scale -Full Scme Zero Zero 1111 ••• 111 1000 ..• 000 Mid Scale-1 LSB -1 LSB +Full Scale ..... " :E e JII CCD (Complementary Coded Decimal) 4 Digi'b F.S.bits OFFOll0 ••• 0110 ... All bits ON 1111 ..• 1111 +Full Scale Zero -Invert the MSBofthe COS code with an external inverter to obtain eTC code. TABLE I. Digital Input Codes. ACCURACyt SETTLING TIME t The settling time for each model DAC70 is the total time . (including slew time) for the output to settle to within an error band about its final value after a change in the input. Two settling times are specified to ±0.003% of full scale range (FSR); one for a maximum full scale range change of20V and also for a I LSB change. The I LSB change is measured at the major carry (0111 ... 11 to 1000 ... 00) since this is the point where the worst case settling time occurs. This measurement is made with an external BB3500C op amp. (See Figure 3.) OUTPUT SIGNAL RANGES LINEARITY For optimum operation and performance to specification, an external operational amplifier (BB Model 350OC) should be u~d with the DAC70. A laser trimmed low-drift thin fIlm feedback resistor (RF) is provided in each DAC70 to provide an outpul'voltage range of ±IOV for the COB model or Oto+IOV(orthe CSB or CCD models. The internal feedback resistor must be used to obtain low gain drift. This specification describes one of the truest measures ofD/A converter accuracy. As defined it means that the analog out· put will not vary by more than ±.0.003% of FSR max (DAC 70) or ±.0.005% of FSR max (DAC70C) from a straight line drawn through the end points (all bits ON and all bits OFF) at 25 0 C. DIFFERENTIAL LINEARITY Differential linearity error of a D/ A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±1/2 LSB means that the output voltage step sizes can be anywhere from 1/2 LSB to 3/2 LSB when the input changes from one adjacent input state to the next. COMPLIANCE The compliance voltage of the .DAC70 is the maximum voltage swing allowed on the current output mode in order to maintain the specified accuracy; it is ±2.5V and is compatible with an external op amp summing junction. The maximum safe voltage swing allowed with no damage to the DAC70 output is ±5 volts. '. MONOTONICITY Monotonicityover 10 to+40oC is guaranteed in the DAC70. This insures that the analog output will increase or remain the same for increasing 14 bit input digital codes. It is 13 bits over the same temperature range for the DAC7OC. POWER SUPPLY SENSITIVITY DRIFT t Power supply sensitivity is a measure of the effect of power supply voltage change on the D/A converter output, It is de· fmed as ppm of FSR per percent of change in either the +15 volt or -IS volt and +5 power supplies about the nominal power supply vbltll!!es. Figure 2 shows Power Supply rejection vs. Frequency. GAIN DRIFT is a measure of the change in the full scale range analog output over temperature expressed in parts per mi\lj.on per °C (ppm/0C). The GAIN DRIFT is determined by testing the end point differences at -25 0C or OOC, +25 0C and +700C or +85 0C for each model and 'calculating the GAIN ERROR with respect to the 25 0C vaiue and dividing by the temperature change. This specification is expressed in ppm/°C and is shown in Figure 1. rt All specifications are tested with a BB3500C operational] Lamplifier connected to the DAC70 output. 6-103 +0.061--I----;.---------::~-_t TYPICAL PERFORMANCE CURVES 1.0 r-----,_---.,.....,r----. ~.08~1;:2::5--~0~..,.........· +:':2!:5~-----+~7!-:0::-':"+8~'5 Temperature fOC) '5 FIGURE 1. Gain drifterror (%1 vs. temperature. & ~ 1/.~ Co ~ a. !~ e>'"c .1 0 .08 to 'SO 1/.1; 0 ~ .02 ~ '" •c u. ~ -15V Supply +6V Supply w·- a: !I. 0.1 f .06 .04 .01 .008 .006 .004 / ...'" ~~ 1; .01 1/. e .:; +15V Supply ./ .002 a: ./ .001 /'" , / .001 1 ~ ___ ~~ ___ ~~ __ ~ 0.1 100 Ik 10k 10 Powe,.'8\1pply Ripple Frequ.ncv (Hz) Settling Time lpsac) lOOk FIGURE 2. Power supply rejection vs. power supply ripple frequency. FIGURE 3. Full scale range settling time vs. accuracy. + Full Scale Gain Adj. rotates the line All ON the line bit~ . ~-+-+-+-+4H-++-+-+--i.1 Digital·.I.nput FIGURE 4. Relationship of OFFSET and GAIN adjustments fora UNIPOLAR O/A converter. FIGURE 5. Relationship of OFFSET and GAIN adjustments for a 81PO LAR 0/A converter. U UT D VO TAG DIGITAL I..PUT CODE U ENT 16 Bit Resolution 14 Bit R"'utlon 16 Bit Resolution 4 Bit Reloluilon DIGITAL INPUT AND ANALOG OOTPUT RELATIONS.HIPS Complementary UrUpol., Str.'ght 81nuv (CSS) o to +1DV or 0 10 -2mA .... On. LSB +16311V All Bits off +9.99985V All Bltlon +610JaV +9.99939 z... D.031mA O.122pA -'.9999lmA ZVo -1.999B8mA 0.031"A -D.99997mA +1.0000mA O.122"A -O.9918BmA +1.0000mA z..• Complementllry Bipolar 0ffMt Blnilrv (Coa) :t1OV or,:l:1mA One LSS All Bits off All Bluon Comple....,ury Blnerv Coded Decimal (CCD) o to +10V or Oto -1.26mA One LSB F.S. Bits off All BitS on +305IIlV +9.9996!n; -:10.0oooy +1.22mV +9.99B7BV -10.0000V 4 Digit Resoludon +1.OmV +9.999V 4 Digit Aesotutlon N/A z... TABLE II. Ideal output voltage and current. 6-104 D.12S"A -1.24987mA .. "" N/A OPERATING AND INSTALLATION INSTRUCTIONS INSTALLATION CONSIDERATIONS The DAC70 is laser trimmed to 14 bit linearity. The design ofthe device makes the 16 bit resolution available on binary units. If 16 bit resolution is not required, bit IS (pin IS) and bit 16 (pin 16) should be connected to +5 V through a single I k n resistor. Figure 6. The lead and contact resistance, Zi' is reduced by the loop gain to acceptable values. The DAC70 and the wiring to its connector should be located so as to provide optimum isolation from sources of RFI and EMI. The key word in elimination of RF radiation or pickup is loop area. Therefore, signal leads and their return con· ductors should be kept close together. This reduces the external magnetic field along with any radiation. Also, if a signal lead and its return conductor are wired close together they present a small flux·capture cross section for any ex· ternal field. This reduces radiation pick·up in the circuit. The metal case of the unit is internally connected to the com· mon pin to further minimize pick-up. The DAC70 case is made of gold plated Kovar which also provides some electromagnetic shielding. Due to the extremely high resolution and linearity of the DAC70, system design problems such as grounding and contact resistance become very important. For a 16 bit converter with a +10 volt full scale range, one LSB is 1531lV. With a load current of 5 rnA and series wiring and connector resis· tance of only 30 mn, the output will be in error by I LSB. To understand what this means in terms of a system layout, the impedance of #18 wire is about 0.064 n/ft. Neglect· ing contact resistance, less than 6 inches of wire will produce a I LSB e{ror, in the analog output voltage! Although the problems involved seem enormous, care in the installation planning can minimize the potential causes of error. NOTE: It is recommended that the digital input lines at the OAC70 be driven from inverters of TTL input registers to obtain specified accuracy. The output can be made essentially independent of lead resistance by sensing the output at the load itself as shown in ~1 ) Feedback Current (Independent of Load) Output Here ±ISV Supply "'R B should be equal to the output impedance at Pin 21 to compensate for the bias current drift of AI' Use standard 10%, 1/8 in carbon compos· ition or equivalent resistors. +SV Supply RB = 3k (COB) '" 10k 1I1Sk II 6.3k RB = 3.9k (CSB) '" Sk 1I1Sk RB = S.lk (CCO) '" 8k 1I1Sk FIGURE 6. Output CIRCUIT for making LOAD VOLTAGE essentially independent of LEAD RESISTANCE. SUPPLY DECOUPLING For best performance and noise rejection, power supply decoupling capacitors should be connected as shown in Figure 6. These capacitors should be located close to the DAC70 and should be tantalum or electrolytic types bypassed with a O.OIIlF ceramic capacitor for best high frequency performance. 6-105 EXTERNAL OFFSET AND GAIN ADJ. Offset and gain may be trimmed by the user with externally connected offset and gain potentiometers. Connection of. these potentiometers-and the method of adjustment is outlined below. In each case a simplified schematic of the DAC 70 as seen from the adjustment pOint is given to assist the user in designing his own adjustment networks. Adjust offset first and then gain to avoid interaction (see Figures 4 and 5). GAIN ADJUSTMENT For eithe~ unipolar (CSB. CCD) or bipolar (COB) models. apply the digital input that should give the maximum positive current or voltage output. Adjust the gain potentiometer for this full scale value. The positive full scale voltage and currents for the DAC70 are 'given in Table II. ,------I I Reference Output 6.3V OFFSET ADJUSTMENT For unipolar (CSB. CCD) D/ A converters. apply the digital input code that should give zero volts output and adjust the offset potentiometer for zero volts output. For bipolar (COB) D/ A converters. apply the digital input code that should give minus full scal,e (-10 volts) and adjust the offset potentiometer for an output voltage of -10 volts. Two methods of offset adjustment are shown in Figures 7 & 8. +15V I I 24 +15VDC 510kf! 22 DAC70 +15VDC -15VDC ,..._ _~3\;.9~M,..,f!_-< ~ Okf! to 100kf! FIGURE 9. Gain adjustment circuit with ±O.I % of FSR range of adjustment. Figure 9, shows how the gain adjust works on the DAC70. TIle gain of the DAC70 is determined by the reference current Iref- Due to the high gain and low bias current of A I. the voltage at the positive input of A I is approximately equal to the voltage 'at the gain adjust pin VG. Therefore. the reference current is 6.3 V _ V IREF= G 50 k Since VG is approximately equal to zero initially. a simple formula for determining the voltage range necessary at the gain adjust pin for a given percentage change in gain is FIGURE 7. Offset adjustment with ±0.2% of FSR range of adjustment. DAC70-CSB-I with external op amp. In some applications the use of such a large offset adjustment resistor might be undesirable. An alternative method of offset adjustment is shown in Figure 8: = % Gain Change x 6 3 volts G 100 . The full scale output voltage of the DAC70 with an external output amplifier and internal feedback resistor is laser trImmed to less than ±0.05% of FSR. I'N REFERENCE SUPPLY ·10kf! -15VDC 150kf! 6.2kf! All DAC70 and DAC70C models are supplied with an internal +6.3V reference voltage supply. This reference voltage (pin 24) has a tolerance of ±5% and is connected internally for 'specified operation. The zener is selected for a gain drift of typically ±3 ppm/oC and is burned in for a total of 160 hours for guaranteed reliability. This reference may also be used externally but the current drain is limited to 200 MA. An external buffer amplifier is recommended if the DAC70 internal reference will be used externally in order to supply a constant load to the reference supply output. FIGURE 8. Alternative method of offset adjustment with ±0.2% of FSR range of adjustment for DAC70- CSB-I ~ith external op amp. ' , NOTE: An external reference cannot -be used. The DAC70 internal reference must be used. * High quality multi-turn (J 0 turns if possible) potentiometers with less than 100ppm/oC, T.C.R. should be used. 6-106 APPLICATIONS DRIVING AN EXTERNAL OP AMP The DAC70 can be scaled for any desired voltage range with an external feedback resistor, but at the expense of increased drifts of up to ±25 ppm/oC. The resistors in the DAC70 are chosen for ratio tracking of ±I ppm/oC and not absolute T.C.R. (which may be as high as ±25 ppm/oC). The DAC70 is a current output device and will drive the summing junction of an op amp to produce an output voltage (see Figure 10). The op amp output voltage is: V out =.,-I out Rf Where lout is the DAC70 output current and Rf is the feedback resistor. Use of the internal feedback resistor (pin 17) is required to obtain specified gain accuracy and low gain drift. An alternative method of scaling the output voltage of the DAC70 and preserving the low gain drift is shown in Figure 11. 5kO Oto 2mA 15kO FIGURE 10. External op amp using internal feedback resistors. 5kO o to 2mA 15kO FIGURE 11. External op amp using internal and external feedback resistors to maintain low gain drift . . . . - - - - -... 17 OUTPUTS LARGER THAN 20 VOLT RANGE For output voltage ranges larger than ±1O volts, a high voltage op amp may be employed with an external feedback resistor. Use lout values of fI mA for bipolar voltage ranges and -2 rnA for unipolar voltage ranges (see Figure 12). Use protection diodes when a high voltage op amp is used. V out FIGURE 12_ External op amp using external feedback resistors. 6-107 ORDER INFORMATION XXX - X DAC 70 X Output L...."..,L:.....~.I-_--~,~~~~---9 I = Current Output 16 Bit D/A Converter Family Complementary Straight Binary Blank = -250C to +85 0C C= 00 to + 700C COB =16 Bit Complementary Offset Binary CCD = 4 digit Complementary BCD NBS TRACEABILITY The reference zener is burned-in for a total of 160 hours. The entire unit is burned-in for 96 hours at +1000 C to age and stabilize the components and insure long life, excellent stability, and high quality performance. NBS CERTIFICATION • EPPLEY 121 STANDARD CELL SN3271 ~ FLUKE B45AR NULL DETECTOR SN489 KELVIN VARLEY BRIDGE FLUKE 720A SN 412 J, JULIE RES. LAB RVD 106 AUTOMATIC VOLTAGE DIVIDER SN 33 + DAC70 6-108 TE 1449 TEST CONSOLE BURR-BROWN® DAC71 113131 High Resolution 16-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • 16-BIT. 4-DlGIT RESOLUTION The DAC71 is a high quality 16-bit hybrid IC Dj A converter available in a 24-pin dual-in-line ceramic package. • ±O.003% MAXIMUM NONLINEARITY • LOW DRIFT ±7ppm/o C. (TYPICAL) • CURRENT AND VOLTAGE MODELS • LOW COST VOLTAGE MODEL fi.3V REF. OUT +15VOC GAIN ADJUST SUMMING JUNCTION The DAC7l with internal reference and optional output amplifier offers a maximum linearity error of ±0.003% of FSR at room temperature and a maximum gain drift of ±15ppmj"C over a temperature range ofO"C to +70"C. Three basic models accept complementary l6-bit binary or complementary 4-digit BCD TTLcompatible input codes. Packaged within the DAC71 are fast-settling switches and stable laser-trimmed thin-film resistors that let you select output voltages 0 to+IOV (CSBand CCD) or±IOV (COB)and output currents of±1 rnA orO to -2mA. Input power is ±15VDC and +5VDC. COMMON ·15VOC +5VOC V OUT L..._ _ _ _ _ _. - } =~ International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. 16021 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66·6491 PDS-4JO 6-109 SPECIFICATIONS ELECTRICAL Typical at TA - 25°C and rated power supplies unless otherwise noted MODEL I MIN DAC71 TYP MAX I UNITS MECHANICAL INPUT DIGITAL INPUT Resolution, CGO CSB. COB Logic Levels, TTL-Compatiblel(l} Logical "I" •at +40~A· Logical "0" rat -1.6mAI Digits Bits 4 16 +2.4 0 +5.5 +0.4 VDC VDC ±0.OO5 ±0.003 ±O.I ±0.25 ±2 ±5 ±I ±5 +50 % of FSRI2, % of FSR % % mV mV ±15 ±50 ppm of FSR/oC ppm of FSR/oC ±0.083 ±O.O71 ±0.23 ±0.23 ±15 ±45 %of FSR % of FSR %of FSR % of FSR ppm/oC ppm/oC TRANSFER CHARACTERISTICS ACCURACY Linearity Error at 25°C. CGD COB. CSB Gain Error,(3) Voltage Current Offset Error,(31 Voltage, Unipolar Voltage, Bipolar Current. Unipolar Current. Bipolar Monotonicity Temperature Range t 14 bitS) ±0.01 ±0.05 ±O.I 0 ~A ~A in true position. within 0.10" I O.25mm I R at MMCat, seating plane. shown for reference only. Numbers may not be marked on package. °C DRIFT Over specified temp. range Total Bipolar Drift includes gain, offset, and linearity drift ',(4) Voltage Current Total Error over Temperature Range(S) Voltage, Unipolar Bipolar Current. Unipolar Bipolar Gain, Voltage Current Offset Voltage, Unipolar Bipolar Current. Unipolar Bipolar Differential Linearity over Temperature Linearity Error over Temperature I ±7 ±15 ±I ±2 ±10 ±I ±40 ±2 ±2 5 3 20 10 5 ppm of ppm of ppm. of ppm of ppm of ppm of n FSR/oC FSR/oC FSR/oC FSR/oC FSR/oC FSR/oC SETTLING TIME INCHES .DIM Voltage Models to ±0.003% of FSR Output; 20V Step I LSB Step'.' Slew Rate Current Models Ito ±O.003% of FSR, Output; 2mA step 100 to 1000 Load I kO Load Switching Transient I 3 500 MAX MIN MAX A 1.310 1.360 33.27 34.54 J.lsec V/p,sec 8 .770 .150 .810 19.56 3.B1 20.57 c· 0 .018 .u sec F .03" J,tsec mV .210 .021 0.89 G H .110 K 2.79 3.81 .130 .250 L .150 .600 BASIC N .002 Voltage Models Ranges - CSB. CCD COB Output Current Output Impedance DC Short Clrct.it Duration Current Models Ranges - CSB. CGD COB Output Impedance - Unipolar Bipolar Compliance R 0.85 INTERNAL REFERENCE VOLTAGE Maximum External Current(7) Temperature Coefficient of Drift Oto+10 ±IO V V mA 0 0.05 Indefinite to Common o to-2 mA mA kO kO V ±I 15 4.4 +2.5 6.0 6.3 6.6 V ±200 ~A ±10 ppm/oC 6-110 0." .050 .100 BASIC ANALOG OUTPUT OUTPUT ±5 MILLIMETERS MIN ~sec .010 .105 5.33 0.53 1.27 2.54 BASIC 3.30 6.35 15.24 BASIC 0.05 2.16 0.25 2.67 CASE: Black Ceramic MATING CONNECTOR: 245MC WEIGHT: 8.4 grams, 0.3 oz. 1 HERMETICITY: Conforms to method 1014 condition C step 1 I fluorocarbon I of MIL-STD-883 (gross leak 1. MODEL DAC71 TYP MIN MAX UNITS POWER SUPPLY SENSITIVITY Unipolar Offsel ±15VDC +15VDC Bipolar Offset ±15VDC +5VDC ±O.OOOI ±O.OOOI % of FSR/%Vs % 01 FSR/%Vs ±0.0004 ±O.OOOI %ofFSR/%Vs % of FSR/%Vs Gain ±15VDC +5VDC ±0.001 ±0.0005 % of FSR/%Vs % of FSR/%Vs POWER SUPPLY REQUIREMENTS Voltage ±14.5. +4.75 ±15.+5 ±25 +20 Supply Drain. ±15VDC InO load I +5VDC (logic supply I ±15. +5.25 ±35 +35 VDC mA mA +70 +B5 +100 °C °C °C TEMPERATURE RANGE 0 -25 -55 Specification Operating (double above Drift Specs I Storage NOTES: 1. Adding external CMOS hex buffers CD4009A will provide 15VDC CMOS input compatibility. The percent change in outputll.l. Va las 10gieO varies from O.OV to +O.4V and logic 1 changes from +2.4V to +S.OV on all inputs is less than 0.006% of FSR. 2. FSR means Full Scale Range and is 20V for ±10V range, 10V for ±5V range, etc. 3. Adjustable to zero with external trim potentiometer. 4. See "Computing Total Accuracy over Temperature", 5. With gain and offset errors adjusted to zero at 25°C. 6. LSB is for 14-bit resolution. 7. Maximum with no degradation of specifications. CONNECTION DIAGRAM PIN ASSIGNMENTS 1.0~F~ I Models -=- +VS 10k!! to lOOk!! ·Vs 10kll to 100kll +Vs L......-_p-_ _-o +VL IMSBI Bitl Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 BitB Bit9 Bitl0 Bitll Bit12 Bit13 Bit14 Bit15 ILSBI Bit 16 RF +5VDC -15VDC COMMON lOUT GAIN ADJUST +15VDC 6.3V REF. OUT Current Model does not "RF ~ 5kll (CSBI. 10kIlICOBI. BkIlICCD •. 6-111 Pin No. 1 2 3 10 1'1 12 13 14 15 16 17 lB 19 20 21 22 23 24 V Models BitllMSBI Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 BitB Bit9 Bitl0 Bit II Bit 12 Bit13 Bit14 Bit15 Bit 161LSBI VOUT +5VDC -15VDC COMMON SUMMING JUNCTION GAIN ADJUST +15VDC 6.3V REF. OUT DISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES +0.08 The DAC71 accepts complementary digital input codes in either binary (CSB, COB) or decimal (CCD) format. The COB model may be connected by the user for either complementary offset binary (COB) or complementary two's complement (CTC) codes (see Table I). +O.08t---------------~~ TABLE I. Digital Input Codes. DIGITAL INPUT CODES CSB COB ~ w Compl. 0 ..8 AlibitsON 13 All bits OFF 0 2 Compl. Offset Binary Straight MSB ai Mid Scale LSB txm ...oot 0111 ... 111 1111...111 1000... 000 Binary +full Scale +112 Full Scale Zero Mid Scale -lLSB +Full Scale Zero -Full Scale· ·1LSB CCD ~ .:!l Complementary Coded Decimal 4 Digits 0 2 0 0 o F.S. bits ON AIIBit80Ff 0110 ...0110 1111...1111 +Full Scale Zero CTC' Compl. Two's Cample- -0.06 Characteristic -0.08 0!---+~2:'::5-----~+70 menl -llSB Temperature (OCI -Full Scale Zero +Full Scale FIGURE I. Gain Drift Error (%) vs Temperature. The maximum change in offset is referenced to the offset at +2S"C and is divided by the temperature range. This drift is expressed in parts per million offull scale range per "c (ppm of FSRj"C). O'nvert the MSB of the COB code with external inverter to a" oblainCTC code. SETTLING TIME ACCURACY i I. \": I ! LINEARITY This specification describes one of the truest measures of 0/ A converter accuracy. As defined it means that the analog output will not vary by more than ±o.003% max (CSB, COB) or ±O.OOS% max (CCD) from a straight line drawn through the end points (all bits ON and all bits OFF) at +2S"C. DIFFERENTIAL LINEARITY Differential linearity error of a D / A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±I /2LSB means that the output voltage step sizes can be anywhere from 1/2LSB to 3/2LSD when the input changes from one adjacent input stage to the next. MONOTONICITY MonotQnicity oVer O"C to +SO"C is guaranteed. This insures that the analog output will increase or remain the same for increasing 14-bit input digital codes. DRIFT Gain Drift is a measure of the change in the full scale range output over temperature expressed in parts per million per"C (see Figure I). Gain Drift is "stablished by: I) testing the end point differences for each DAC71 model at +2S"C and the appropriate specification temperature extremes; 2) calculating the gain error with respect to the +2S"C value; and 3) dividing by the temperature change. This is expressed in ppmj"c. Offset Drift is a measure of the actual change in output with all "I"s on the input over the specified temperature range. Settling time for each DAC71 model is the total time (including slew time) required for the output to settle within an error band around its final value after a change in input (see Figure 2). 10 Settling Time 100 (~sec l FIGURE 2. Full Scale Range Settling Time vs Accuracy. VOLTAGE OUTPUT MODELS Settling times are specified to ±O.003% of FSR; one for maximum full scale range changes of 20V and one for a I LSD change. The I LSD change is measured at the major cllrry (0 II 1...11 to 1000 ...00), the' point at which the worst-case settling time occurs. CURRENT OUTPUT MODELS Two settling time are specified to ±0.003% of FSR. Each is given for current models connected with two different resistive loads: Ion to loon and 1000!}. COMPLIANCE Compliance voltage is the maximum voltage swing 6-112 allowed on the output of the current models while maintaining specified accuracy. The typical compliance voltage of all current output models is ±2.5V and maximum safe voltage swing permitted without damage is±5V. POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the D/ A converter output. It is defined as a percent of FSR per percent of change in either the positive. negative. or logic supplies about the nominal power supply voltages (see Figure 3). adjust as described below. TCR of the potentiometers should be 100ppmj"C or less. The 3.9Mn and 510kn resistors (20% carbon or better) should be located close to the DAC71 to prevent noise pickup. Ifit is not convenient to use these high-value resistors. an equivalent "Tn network. as shown in Figure 4. may be substituted in place of the 3.9Mn. A O.OOIJ.LF to O.OIJ.LF ceramic capacitor should be connected from Gain Adjust (pin 22) to common to prevent noise pickup. Refer to Figures 5 and 6 for relationship of offset and gain adjustments to unipolar and bipolar D/ A converters. 3.9Mn ~ '"Q. 0.1 C. 0.08 ~ en 0.06 > 0.04 .5 " -15V Supply ~ 0> ~ '" .c () 0.02 +5V SUPPly';; 0.01 '0 0.008 if. ~ Q. e W a: en LL '0 if. / ~ 0.006 0.004 V FIGURE 4. Equivalent Resistances. +15V Supply ./ 0.002 0.001 1 // ,/' "/ I 10k 1k 100 10 Power Supply Ripple Frequency IHzl +Full Scale lLSB 100k I f FIGURE 3. Power Supply Rejection vs Power Supply Ripple Frequency. REFERENCE SUPPLY' All DAC71 models are supplied with an internal +6.3V reference voltage supply. This reference voltage (pin 24) has a tolerance of ±5% and is connected internally for specified operation. The zener is selected for a Gain Drift of typically ±3ppm/"C and is burned-in for a total of 168 hours for guaranteed reliability. This reference may also be used externally but the current drain is limited to 200J.LA. An external buffer amplifier is recommended if the DAC71 internal reference is used externally in order to provide a constant load to the reference supply output. All bill Logic 0 Oigi18llnpul FIGURE 5. Relationship of Offset and Gain Adjustments for a Unipolar D/ A Converter. lLSB .L ....L T ~ - +Full Scale ?~; T i. All blls Logic 1 OPERATING INSTRUCTIONS I POWER SUPPLY CONNECTIONS F'or optimum performance and noise rejection. power supply decoupling capacitors should be added as shown in the Connection Diagram. These capacitors (IJ.LF tantalum or electrolytic recommended) should be located close to the DAC71. Electrolytic capacitors. if used. should be paralleled with O.OIJ.LF ceramic capacitors for best high frequency performance. /,. -: '" ~ - .:i! Range of Offsel Adj. 'l Offsel Adj. -L Transiates --,Ihe line r ~ ! Rangl of ~'}\-' :f /:;'?/ Gain AlIi. ro18tes Ihe line 1-++-:1_1-+1;tr+-+-..:-"' .+-if-I..-+~ All bill r~iI!i~4"-+Bipolar V Offsal ../ " . ~ /il- "MSB ON all others OFF III /~! Logic 0 Offsel Scale OIgnallnput FIGURE 6.--~--------------~ Relationship of Offset and Gain Adjustments. for a Bipolar D/ A Converter. EXTERNAL OFFSET AND GAIN ADJUSTMENT Offset and gain may be trimmed by installing external offset and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and OFFSET ADJUSTMENT For unipolar (eSB. CCD) configurations. apply the digital input code. that should produce zero potential 6-113 output and adjust the' 'offset p'otentiometer for zero output. For bipolar (COB, CTC) configurations, apply the digital input code that should produce the maximum negative output voltage. The COB model is internally connected for a 20Y FSR range where the maximum negative output voltage is-lOY. See Table II for corresponding codes and the Connection Diagram for offset adjustment connections. Offset adjust should be made prior to gain adjust. TABLE II. Digital Input and Analog Output 'Relationships. OUTPUT CODE DIGITAL INPUT CODE VOLTAGE CURRENT l6-Sit Resolution 14-Bit Resolution -t-153,.V +9,99985V Zero +6tO/.N O.031J'A All Bits ON 00 ...00 All SIS OFf 11...11 +9.99939V -1 tMm97mA Zero Complementary Bipolar Ott.t Binary. COB :tl0Vor :!:lmA' OneLSB All Sits ON 00..00 AIIB.tsQfF 11 ... 11 +305",V +'.22mV +9.99969v -1O.0000V +U9878V Complementarv Unipolar Straight Binary eSB a to +10VorO to -2mA' One LSB Complementary Binary Coded Oecim.al ceo Zero -10.0000V 4-019 11 Resolution o to +IOV or 0 to -1.25mA "".OmV Full Scale 0110 .. OliO All SllsOFF 1111 .. 1111 ·'9.999V O.031",A -0 99997mA +'.OOOOmA 14-811 Resolution o 122"A -l.99988mA Zero O.122j.1A -o.99988mA "".000DmA 0(.. 019 11 Resolullon Nt' OnelSB 16-Bit Resolution output voltage! 'Although the problems involved seem enormous, care in the installation planning can minimize the potential causes, of error. Figure 7 shows the 'conneCtion diagram for a voltage output OAC71. Lead and contact resistances are rep~ resented by RI through Rs. As long as the load resistiince (RL) is constant. R2 simply introduces a gain error than can be removed during initial calibration. R3 is "part of RL if the output voltage is sensed at Common (pin 20) and therefore introduces no error .. If. RL is variable then R2 should be less than RLmin/i 6 to reduce, voltage drops due. to wiring to less than I LSB. For example, if RLmin is 5kO then R2 should be less than 0.080. RL shOUld be located as close as possible to the DAC71 for optimum performance. . Zero o Nt. 125j.1A -124987mA Zero • To obtain IIalues tor other bmar,y eBI ranges: 0 to +51/ range. dlll,de 0 10 +10V range by 2; :t5V range, diVide :tl0V range by 2: !:2.SV range. d,"\de ~10V range by 4. . . , ID Pin 23 GAIN ADJUSTMENT For either unipolar or bipolar configurations. applY,the digital input that should give the maximum positive output voltage. Adjust the gain potentiometer for this positive full scale voltage. See Table II for positive full scale voltages and the Connection Diagram for gain adjustment connections. T.plilla To Pin Iii +V + l#F COM + l#F ·V ±15VDC Supply +V + I#F COM +5VIIC Supply 'Ra =3kllIC081 Ra =3.9kIlICSal Ra =5.1kll1CC01 FIGURE 7. Output Circuit'for Voltage Models. INSTALLATION CONSIDERATIONS The DAC71 is laser-trimmed to 14-bit linearity. The design of the device makes the 16-bit resolution available on binary units: If 16"bit resolution is not required, bit 15 (pin IS) and bit 16 (pin 16) should be connected to +SYDC through a single IkO resistor. Due to the extremely-high resolution arid linearity of the DAC71, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +IOV full scale range, ILSB is IS3j.1V. With a load current of SmA. series wiring and connector resistance of only 30mB. the output will be in error by I LSB. To understand what this means in terms of a system layout. the impedance of #23 wire is about 0.02i!lj ft. Neglecting contact resistance. less than 6 inches of wire will "produce a I LSB error in the analog Figures 8 and 9 show two methods of connecting ciJrrent model DAC71 's with external precision output op amps. By sensing the output voltage at the load resistor (i.e., by connecting RF to the output of A I at Rd the effect of R\ and R, is greatly reduced. R\ will cause a gain error but is indePendent of the value of RI and can be eliminated during initial calibration. The effect of R, is ne-gligible because it is inside the feedback 'loop of the output op amp and is therefore greatly reduced by the loop gain. If the output cannot be sensed at C'ommon(pin 20). then the differential output circuit shown in Figure 9 is recommended. In this circuit the output voltage is sensed at the load common ani! not at the DAC' common as in the previous circuits. The value of R. and, R7 must be adjusted for maximum common-mode rejection at RI.. Note that if R., is negligible the circuitnf Figure 9 can be reduced to the one shown in Figure 8 because RII = (R, + Rj) II R •. In all three circuits the effect of R" is negligible. 6-114 H2 NOTE: It is recommended that the digital input lines of. the DAC71 be driven from inverters or buffers of TTL input registers to obtain specified accuracy. +V To Pin 23 ±15VOC Supply COM To Pin 19 -V To Pin 18 +V COM + '~F +5VOC Supply "Ha should be equlllo the oulput Impedance It Pin 2110 compenale lor the bill current drift 01 A'- Use standard 10%. 1I4W carbon composition or equivalent reslslorl_ The DAC71 and tlte wiring to its connectors shouid be located to provide optimum isolation from sources of RFI and EM I. The key word in elimination of RF radiation or pickup is loop area. Therefore_ signal leads and their return.conductors should be kept close iogether. This reduces the external magnetic field along with any radiation. Also. if a signal lead and its return conductor are wired close together they present a small flux-capture cross section for any external field. This reduces radiation pickup in the circuit. Ha =31m (COal H8 =3.9kn (CSOI Ha =5.1 kn (CCOI DRIVING A RESISTIVE LOAD UNIPOLAR A load resistance. RI.. with the current output model connected as shown in Figure 10. will gel'\erate a voltage range. V(WI'. determined by: V(WI' = -2mA[(I5kO x Rd/( 15kO + Rd] Where RI. max = 1.36k!l and V(WI' max = -2.5V FIGURE 8. Preferred External Op Amp Configuration. \I l Currant cllllroliad by dlgllellnput + 0 to 21Jn)A 15kn FIGURE 10. Equivalent Circuit DAC71-CSB-1 Connected for Unipolar Voltage Output with Resistive Load_ H5 + 87 =HF + HI H6 = HOAC H4 Add an external low T.e. «IOppmj"C) resistor (R.) as shown in Figure ( ( to obtain a 0 to -2V full scale output voltage range for tCD input codes. +V To Pin 23 To Pin 19 To Pin 18 83 + I~F COM -V ±15VOC Supply +V COM +5VOC Supply \r Currant controlled by digital Input + 15.6kn FIGURE 9. Differential Sensing OUtput Op Amp Configuration. FIGURE (I. DAC7(-CCD-I Connected for Voltage Output with Resistive Load. 6·,1 15 VOlrr = -1.2SmA[(IS.6kfl x Rdl(lS.6kfl + Rd] . Where RI. max 1.79kO . and VOlrr max -2.0IV = = DRIVING A RESISTIVE LOAD BIPOLAR The equivalent output circuit for a bipolar output voltage range is shown in Figure 12. VOUT is determined by: VOUT = ±lmA[«(44kfl x RL)/(4.44kfl + Rd] Where RI. max = S.72kfl and VOUT max = ±2.5V \I The DAC71 can be scaled for any desired voltage range with an external feedback resistor, but at the expense of increased drifts of up to ±2Sppm/ "c. The resistors in the DAC71 are chosen for ratio tracking of ± I ppm/"C and not absolute TCR (which may be as high ai ±2Sppm/"C.) An alternative method of scaling the output voltage ofthe DAC71 and preserving the low gain drift is shown in Figure 14. CUrrent GGII\IlIIld by dlgllllllQlUl + Ukn FIGURE 14. External Op Amp Using Internal and External Feedback Resistors to Maintain Low Gain Drift. FIGURE 12. DAC71-COB-1 Connected for Bipolar Output Voltage with Resistive Load. APPLICATIONS DRIVING AN EXTERNAL OP AMP WITH CURRENT OUTPUTDAC OUTPUTS LARGER THAN 20-VOLT RANGE For output voltage ranges larger than ±IOV, a high voltage op amp may be employed with an external feedback resistor. Use lOUT values of ± I rnA for bipolar voltage ranges and -2mA for unipolar voltage ranges (see Figure IS). Use protection diodes when a high voltage op amp is used. r----_ The DAC7I-(CSB, COB, CCD)-l are current output devices and will drive the summing junction of an op amp to produce an output voltage (see Figure 13). The op amp output voltage is: 17 VOUT = -lOUT RF where louT is the DAC71 output current and RF is the feedback resistor. Use of the internal feedback resistor (pin 17) is required to obtain specified gain accuracy and low gain drift. VOUT FIGURE IS. External Op Amp Using External Feedback Resistors. COMPUTING TOTAL ACCURACY OVER TEMPERATURE FIGURE 13. External Op Amp Using In\ernal' Feedback Resistors. The accuracy drift with temperature of a DAC71 consists of three primary components:· gain drift, unipolar or bipolar offset drift, and linearity drift. To obtain the 6-116 worst-case accuracy drift, most users would assume that all drift errors are random and would simply add them algebraically. However, the worst-case accuracy drift for a DAC71 operating in the bipolar mode is about one-half of the algebraic sum of the individual drift errors. To explain this fact, it is necessary to consider the unipolar and bipolar modes of operation separately. In the unipolar mode of operation, offset drift (±Ippm/ "C) is due primarily to voltage offset drift ofthe output op amp and, to a lesser extent, to the leakage current through the quad current switches. Gain-drift consists of several components: I) ±Sppmj"C due to ratio drift of current switch VilE to the reference transistor, 2)±IOppmj"C due to the zener reference and, 3) ±2ppmj"C linearity drift due to ratio drift of current weighting resistors and V BE of the quad current switches. The sum of these 'three components, ±17ppmj"C, is the maximum gain drift. Since the DAC71-COB-V is operating in the ±IOV range this equivalent to (-IOOp,V j"C) -;- (20V range) = -Sppm of FSRj"C. Now consider the effect of reference changes on gain drift. When all of the bits are turned on ilcan be shown that: ~ V. FU I.I. SCAI.E/~T = +(RF/ RHPo)' (~VREF/ ~T) = +( IOkOj6.3kn). (63p,V /"C) = + I00", V j"c. and (+IOOp,V/"C) 20V Range = +Sppm/"C of FSR. This result indicates that the drift of the minus full scale voltage will be equal in magnitude to, and in the opposite direction of, the drift ofthe plus full scale voltage and that zener reference variations have virtually no effect on the zero point (see Figure 17). This equation also indicates that the gain drift is equal to the VREI' driftin ppm/"C, and the magnitude of the minus full scale drift and plus full scale drift is equal to one-half of the VU1' drift. Because the parameters described could all drift in the same direction, the worst-case accuracy drift in the unipolar mode is simply the sum of the components, or ±18ppmj"C. ~ ,. t , , ii! '5 I' '; In the bipolar mode the major portion of gain drift is due to the zener reference. The gain and offset drifts caused by reference drift are always in opposite directions. Therefore, the accuracy drift will be the difference rather than the sum of these drifts. ';; .i / • ~> ' I' ...... drlfl t---; , _1IIII1IIIcI un . . .. .1 ----------~,.~------JlltlIIII ... Input (bll . First, consider the effect of reference variations on offset drift. Figure 16 shows a simplified circuit diagram of a DAC71-COB-V with all bits off. The current switch leakage current is negligible, so . .lV+fS - '.lV.FS ~ IIIIn 0rIfI =.lV+fS '.lV.FS ~ ~/ ~ I 1/ V- Fl 'I.I, S("AI.E = (-RF/ RBPo)' VREF = (-lOkO/6.3kn). 6.3V = -IOV =il IIII -2.lV+FS ' i ,-,-II. 01-.-.-....,...,....,.,..........u....I...I.. +Vcc Ibl llIeu :~ -3 FIGURE 17. (a) Effect of a Positive Reference Drift on the Ideal Dj A Transfer Function: (b) Error Distribution Due to Reference Voltage Drift in a DAC71. VOUl =·Iav FIGURE 16. Simplified Diagram of DAC71-COB-V with "All Bits Off' (±IOV Range). This equation shows that if VRH increases. the output voltage will decrease and vice versa. If the VRI'I' drift is +IOppmj"C, this equivalent to(+IOppmj"C)x (+6.3V)= +63p, V rC. This will result in a voltage drift at the amplifier output of .lV-FS/ ~ T = -(R F / RHPo)' (~VREF/ ~T) = -( IOkO/6.3k!l). (63p,V j"C) = -IOOp,V j"c. Using this relationship. the worst-case accuracy drift for a DAC71-COB-V can be computed. The maximum TCR of the zener reference is ±IOppm, "c. The gain drift due to the reference then is also ± IOppm/"c. The full scale drift and bipolar offset drift are each half that amount or ±Sppm('C. The maximum gain and offset drifts of the DAC71. exclusive of the reference. are ±5 and ±3ppm,' "c respectively. Adding this to the full scale drift due to the reference plus the linearity drift of ±2ppmj"C gives a worst-case total accuracy drift of±15ppm;"C. (Random drifts. which these are. can be in the same direction so they add directly.) This is much less than the total drift obtained by simply adding the maximum gain. bipolar offset. and linearity drifts (±27ppm, "C). The maximum 6-117 zero point drift is equal to one-half of the,gain drift exclusive of the reference plus the offset drift exclusive of the reference. or ±5.5ppm of FSR/"C. The DAc71 is specified over a O"C to +70"C temperature range giving a maximum excursion from room temperature (+25"q of 45"C. Assuming that gain and offset errors have been adjusted to zero at room temperature. total worst-case accuracy error = Linearity error + Accuracy drift x aT = ±0.003%+ ±15ppm/"C (45") (100) = ±0.07% total worst-case bipolar zero point error = Bipolar zero drift x 4T = ±5.5ppm of FSR% (45"C) (100) = ±0.025% ORDERING INFORMATION MODEL INPUT CODE CURRENT MODELS DAC71-COB-1 DAC71-CSB-1 DAC71-CCD-1 Complementary Offset Binary Complementary Straight Binary Complementary Coded Decimal VOLTAGE MODELS Df.C71-COB-V DAC71-CSB-V DAC71-CCD-V Complementary Offset Binary Complementary.StraightBinary Complementary Coded Decimal 6-118 DAC72 BURR-BROWN@ IEaElI High Resolution 16-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • 16-BIT. 4-OIGIT RESOLUTION The DAC72 is a high quality 16-bit hybrid IC D/ A converter in a 24-pin dual-in-line metal package. The DAC72C with internal reference and optional output amplifier offers a maximum linearity error of ±O.003% of FSR at room temperature and a maximum gain drift of ±ISppm/"C over a temperature range of O°C to + 70°C. The DAC72 offers a maximum linearity error of±O.OO3% ofFSR at room temperature and a gain drift of ±7ppm/oC from + 2SoC to +85°C and ± ISppm/"C from -25°C to +2S°C. Three basic models accept complementary 16-bit binary or complementary 4-digit BCD TTLcompatible input codes. Packaged within the DAC72 are fast-settling switches and stable laser-trimmed thin-film resistors that let you select output voltages 0 to + IOV (CSB and CCD) or±IOV (COB) and output currents of±lmA orO to -2mA. Input power is ±ISVDC and +SVDC. • ±O.003% MAXIMUM NONLINEARITY • LOW DRIFT ±5ppm/oC, TYPICAL • AVAILABLE IN TWO TEMPERATURE RANGES: ODC to +70°C -25°C to +85°C • CURRENT AND VOLTAGE MODELS • LOW COST • METAL HERMETIC PACKAGE VOLTAGE MODEL 6.3V REF. OUT +15VDC GAIN ADJUST SUMMING JUNCTION .... '" ::0 a.. ~ .... c .... e; 6 COMMON ·15VOC +5VDC V OUT } .",m INPUTS Inlernalional Airporllnduslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 746-1111 . Twx: 91(J.952·1111 • Cable: BBRCORP· Telex: 66·8491 PDS4) I 6-119 SPECIFICATIONS ELECTRICAL Typ;~a' at TA - +25°C and rated power supplies unless otherwise noted MODEL I I I DAC72C MIN TYP MAX DAC72 MIN TYP MAX UNITS INPUT DIGITAL INPUT Resolution, CCO CSB, COB Logic Levels rTTL-Compatible·(l) Logical "1" 'at +40~A' Logical "0" I at ~1.6mA' ! 4 16 +2.4 0 +5.5 +0.4 4 16 Digits Bits +2.4 0 +5.5 +0.4 VDC VDC ±0.005 ±0.003 ±0.15 ±0.25 ±2 ±10 ±1 ±5 +70 % of FSRI21 % of FSR % % mV mV ±11/±19 ±40 ppm of FSR/'C ppm of FSR/'C ±0.072/±0.10 ±0.072/±0.10 % of FSR % of FSR % of FSR %of FSR ppm/'C ppm/'C TRA.NSFER CHARACTERISTICS ACCURACY Linearity Error at 25°C, CGO COB, CSB Gain Error( 3), Voltage Current Offset Error(3), Voltage. Unipolar Voltage, Bipolar Current, Unipolar Current, Bipolar Monotonicity Temp. Range r 14-bits I ±0.05 ±0.05 ±0.1 ±0.OO5 ±0.003 ±0.15 ±0.25 ±2 ±0.05 ±0.05 ±0.1 '±1Q ±1 ±5 +50 0 0 ~A ~A 'C DRIFTIOver specified temp. ranger I Total Bipolar Drift I includes gain, offset, and linearity drift 1(4), Voltage I hot/cold 1(5) Current Total Error over Temp. Range(e) Voltage, Unipoiar rhoVcold,(5) Bipolar I hot/cold 1(5) Current, Unipolar Bipolar Gain, Voltage (hoVcoldl(5) Current Offset Voltage, Unipolar Bipolar Current, Unipolar Bipolar Differential Linearity over Temperature Linearity Error over Temperature ±7 ±15 ±15 ±50 ±5 ±10 ±0.083 ±0.071 ±0.23 ±0.23 ±15 ±45 ±0.24 ±0.24 ±5 ±71±15 ±35 ±1 ±2 ±10 ±1 ±40 ±2 ±2 ±1 ±2 ±8 ±1 ±35 ±1 ±1 5 3 20 10 5 5 3 20 10 5 ppm ppm ppm ppm ppm ppm of of of of of of FSR/'C FSR/'C FSR/'C FSR/'C FSR/'C FSR/'C SETTLING TIME Voltage Models I to ±0,OO3% of FSR' Output: 20V Step 1LSB Stepi71 Slew Rate Curre~t Models I to ±O.OO3% of FSR Output: 2mA step 10ll to 100ll Load 1 kll Load Switching Transient 1 3 1 3 500 500 Oto+10 ±10 o to+10 ~sec J.tsec V/J.tsec J.tsec j.tsec mV OUTPUT ANALOG OUTPUT Voltage Models Ranges - CSB, CCD COB Output Current Output Impedance DC Short Circuit Duration Current Models Ranges - CSB, CCD COB Output Impedance - Unipolar Bipolar Compliance INTERNAL REFERENCE VOLTAGE ±5 ±5 0.05 Indefinite to Common 0.05 Indefinite to Common o to-2 Oto -2 ±1 15 4.4 ±2.5 ±1 15 4.4 ±2.5 6.0 V V mA II ±10 6.3 Maximum External Current(8) Temp. Coeff. of Drift 6.6 ±200 ±10 6-120 6.0' 6.3 mA mA kll kll V 6.6 V ±200 ±5 ~A ppm/'C DAC72 DAC72C MODEL MIN TYP MAX MIN TYP MAX UNITS POWER SUPPLY SENSITIVITY Unipolar Offset -t15VDC +15VDC ±0.0001 ±O.OOOl ±a.Oool ±O.OOOl %of FSR/%Vs % of FSRI%Vs ±0.O004 ±0.0001 ±a.OOO4 ±O.OOOl %of FSR/%Vs %of FSR/%Vs ±O.ool ±a.0005 ±0.001 ±O.0005 %of FSRI% Vs % of FSRI%Vs Bipolar Offset ±15VDC +5VDC Gain ±15VDC +5VDC POWER SUPPLY REQUIREMENTS Voltage Supply Drain, ±15VDC (no load I +5VDC Ilogic supplYI ±14.5, +4.75 ±15, +5 ±15.5, +5.25 ±25 ±35 ±14.5, +4.75 ±25 +20 +35 ±20 ±15,+5 ±15.5, +5.25 ±35 +35 VDC mA mA +85 +100 +110 DC DC DC TEMPERATURE RANGE Specification +70 +85 +100 0 -25 Operating Idouble above Drift Specs I Storage -55 -25 -55 -55 NOTES: 1. Adding external CMOS hex buffers CD4oo9A will provide 15VDC CMOS input compatibility. The percent change in output I ~ Vo I asJogicOva~ieslromO.OVtoO.4Vand Ilogic 1 changes from +2.4V to +5.0V on all inputs is less than 0.006%01 FSR. 2. FSR means Full Scale Range and is 20V for ±10V range, 10V for ±5V range, etc. 3. Adjustable to zero with external trim potentiometer. 4. See "Computing Total Accuracy over Temperature", 5. Hot'" +25DC to +850 C; Cold'" -25DC to +25°C for DAC72. 6. With gain and offset errors adjustt,d to zero at 25°C. 7. LSB is tor 14-bit resolution. S. Maximum with no degradation of specifications. MECHANICAL CONNECTION DIAGRAM r-A~ 1.0"FI LL~1 NOTE: +Vs Leads in true position within .010'" (.25mm I R at MMC at seating plane. 10kll to 100kll -Vs DeFlotespin 1 b rJl!!lIllIii[ R -, j'"" LL +Vs 0 I.-L-J 0-.1 .00.000000 •• 1 ,;.. 2. '3 R r' Pin numbers shown for reference only. Numbers may not be m"rked on package. '---..-----o+VL 000000000000 A DIM INCHES MAX MILLIMETERS MIN MAX 1.365 1.385 34.67 35.18 B .790 .S10 20.07 20.57 C 0 .170 .250 4.32 6.35 .016 .021 0.41 0.53 G .100 BASIC "K MIN .126 .150 .150 .300 L .600 BASIC R .080 .110 Current Model does not contain.A1. 2.54 BASIC 3.18 3.81 3.S1 7.62 15.24 BASIC 2.03 2.79 'RF =5kll(CSBI, 10kll ICOBI, 8kll(CCDI. CASE: Nickel Plated Steel MATING CONNECTOR:245MC WEIGHT: 8.4 grams (0.3 oz. I HERMETICITV: Conforms to method 1014 Condition C Step 1 (fluorocarbon) of MIL-STD-883Igross leak I. 6-121 DIFFERENTIAL LINEARITY Differential linearity error of a D/ A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±1/2LSB means that the output voltage step sizes can be anywhere from 1/2LSB to 3/2LSB when the input changes from one adjacent input stage to the next. PIN ASSIGNMENTS Pin I Model. IMSB' Bit1 Bit2 Bit3 Bit4 BitS Bit6 Bit7 Bit8 Bit9. Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 ILSBI Bit 16 RF +5VDC -15VDC COMMON lOUT GAIN ADJUST +15VDC 6.3V REF. OUT No. V Models 1 2 3 4 5 6 Bit11MSBI Bit2 Bit3 Bit4 BitS Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 BiU3 Bit14 Bit15 Bit 16 ILSBI VOUT +5VDC -15VDC COMMON. SUMMING JUNCTION GAIN ADJUST +15VDC 6.3V REF. OUT 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MONOTONICITY Monotonicity over O"C to +50"C (DAC72C) and O"C to +70"C (DAC72) is guaranteed. This insures that the analog output will increase or remain the same for increasing 14-bit input digital codes. DRIFT Gain Drift is -a measure of the change in the full scale range output over temperature expressed in parts per million per"C(see Figure I). Gain Drift is established by: I) testing the end point differences for eachDAC72 model at +25"C and the appropriate specification temperature extremes; 2) calculating the gain error with respect to the +25"C value; and 3) dividing by the temperature change. This is expressed in ppmj"c. DISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES ~ +0.04 The DAC72 accepts complement'arydigital input codes in .either binary (CSB, COB) or decimal (CCD) format. The COB model may be connected by the user for either complementary offset binary (COB) or complementary two's complement (CTC) codes (see Table I). g +0.02 w = ;§ c: 'iii 0 -0.02 c: ~ a: 0.1 >-- C. 0.1 c. 0.08 ~ (/) 0.06 > For .optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagram. These capacitors (I I-' F tantalum or electrolytic recommended) should be located close to the DAC72. Electrolytic capacitors, if used, should lJe paralleled with O.OII-'F ceramic capacitors for best high frequency performance. +FUllscN IL;;rrr I J f i'3 .. lk 10k lOOk Power Supply Ripple Frequency I Hz I FIGURE 3. Power Supply Rejection vs Power Supply Ripple Frequency. REFERENCE SUPPLY All DAC72 models are supplied with an internal +6.3V Range 01 Dffset Ofl8el ... All bits logic I " ,,0'/"" , ""T ~~ ~ .,,,.,,/ ~ ~J'" _-t-?-" et-' .1"'" Gain Adj. rotates the time ~ Rangaal GaIRActI. Adl'lll ,~ Adl. r-Kv,+'+-+-+-I-IID-H-+-+-+-.f Translates the line I All bill Logie 0 Dlgltellnput FIGURE 5. Relationship of Offset and Gain Adjustments for a Unipolar Df A Converter. GAIN ADJUSTMENT F or either unipolar or bipolar configurations, apply the digital input that should give the maximum positive output voltage. Adjust the' gain potentiometer for this positive full scale voltage. See Table II for positive full scale voltages, and· the Connection Diagram for gain adjustment connections. capacitor should be, connected from Gain Adjust (pin 22) to common to prevent noise pickup. Refer to Figures 5 and 6 for relationship of offset and gain adjustm,ents to unipolar and bipolar D/ A converters. If the full (absolute) accuracy capability of the DAC72 is required, recalibration of gain and offset every 2 months is recommended. IlSB !:-r T~ All bits logic 1 I " go +Full Scali /"-L INSTALLATION CONSIDERATIONS Hlngeal ./' G.ln Ad/. ~r/T ~.J {~ ., The DAC72 is laser-trimmed to 14-bit linearity. The design of the device makes the 16-bit resolution available on binary units. If 16-bit resolution is not required, bit 15 (pin 15) and bit 16 (pin 16) should be connected to +5VDC through a single I kfl resistor. G81n Ad/. rotates :f /~./ the line HH-tH-rl-+-"""I!i/++-+-:Irt-lH-j,.. All 'bill logic 0 -: ! ! 011111 Range 01 Ollsa! Ad/.1. 011111 Ad/.-L. Tr8nslall. -rlhe line • Dlgllallnpul FIGU RE 6. Relationship of Offset and Gain' Adjustments for a Bipolar D/ A Converter. OFFSET ADJUSTMENT For unipolar (CSB, CCD) configurations, apply the digital input code that should produce zero potential output and adjust the offset potentiometer for zero output. For bipolar(COB, CTC) configurations, apply the digital input code that should produce the maximum negative output voltage. The COB model is internally connected for a 20V FSR range where the maximum negative output voltage is -IOV. See Table II for corresponding codes and the Connection Diagram for offset adjustment connec- , tions. Offset adjust should be made prior to gain adjust. Due to the extremely-high resolution and linearity of the DAC72, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +IOV full scale range; 1LSB is 153/tV. With a load current of 5mA, series wiring and connector resistance of only 30mfl, the output will be in error by / LSB. To understand what this means in terms of a system layout, the impedance of #23 wire is about 0.021 fl/ ft. Neglecting contact resistance, less than 6 inches of wire will produce a 1LSB error in the analog output Voltage! Although the problems involved seem enormous, care in the installation planning can minimize the potential causes of error. Figure 7 shows the connection diagram for a voltage output 'DAC72. Lead and contact resistances are represented by TABLE II. Digital Input and Analog Output Relationships. OUTPUT CODE DIGITAL INPUT CODE VOLTAGE 16-8il Resolution CURRENT 14-8i1 Resolution 16-8it Resolution 14-8it Resolution +610,uV +9.99939V Zero O.031,uA -1.99997mA O.122.uA -1.99988mA Zero Complementary Unipolar Straight Binary' csa I to +10V orO to -2mA· o OneLSB An Bits ON 100 ...00, AU BisOFF 11"1...11 +153,.N +9.99985V Zero Zero COM Complementary Bipolar Offset Binary' COB ±1QVor±1mA" OneLSB All Bits ON '00 ...00 All BitsOFF.l1...11 Complementary Binary Coded Decimal. CCO o to +10Vor 0 to -1.25mA OnelSB Full Scale ,0110 ... 0110 All Bits OFF, 1111 ... 1111 +Y to Pin 23 .y To Pin 19 +305.uV +9.99969V -10.0000V +1.22mV +9.99878V -10.0000V 4-0igit Resolution O.031.u A -O.99997mA +l.0000mA O.12.2.uA -o.99988mA N/A +1.0mV +9.999V Zero To Pin IB +l.0000mA 4-Digit Resolution ±15YDC Supply +Y + II'F COM +5VDC Supply N/A O.12S#lA -'.24987mA Zero • To obtain values for other binary .CSI, ranges; 0 to +SV·range, divide 0 fb +10V range by 2: ±5V range, divide±10V range by 2: ±2.5V range, divide ±10V range by4. ORB =31mlCOBI RB = 3.9kn ICSB) Ra =5.lkn ICCO) FIGURE 7. Output Circuit for Voltage Models. 6-124 R t through R" As long as the load resistance (RLl is constant. R, simply introduces a gain error that can be removed during initial calibration. R., is part of RI. if the output voltage is sensed at Common (pin 20) and therefore introduces no error. If RI. is variable then R, should be less than I LSB, For example. if Rl.m;" is 5k!1 then R, should be less than 0.08!1. RI. should be located as close as possible to the DACn for optimum performance, Figures 8 and 9 show two methods of connecting current model DACn's with external precision output op amps. By sensing the output voltage at the load resistor (i.e .. by connecting R,.. to the output of A I at RJ) the effect of R t and R, is greatly reduced. R t will cause again error but it is independent of the value of RI. and can be eliminated during initial calibration. The effect of R, is negligible because it is inside the feedback loop of the output op amp and is therefore greatly reduced by the loop gain, If the output cannot be sensed at Common (pin 20). then the differential output circuit shown in Figure 9 is recommended. In this circuit the output voltage is sensed at the load common and not at the DAC common as in the previous curcuits. The value of R, and R7 must be adjusted for maximum common-mode rejection at RI.. Note that if R., is negligible the circuit of Figure 9 can be reduced to the one shown in Figure 8 because R" = (R7 + R,) II R,. In all three circuits the effect of R, is negligible. R2 +y To Pin 23 To Pin 19 To Pin 18 • IMF COM .y ±15VDC Supply .y +5VDC Supply COM °RS should be equal 10 Ihe oulpul Impedance al Pin 21 10 compensate lor the bias currenl drill of AI. Usa standard 10%, 1/4W carbon compoaHlon or equivalent resistor•. RS =3kniCOSI RS =3.9knICSDI RS =5.lknICCDI DAC72·CS8·1 'J R2 R ~Sen.e L;-Ouipul R5 • R7 = RF • RI R6 = RDAC .V,-----, To Pin 23-."T-I-M-F--f--C-OM-i t-.,,---+--=~ To Pin Ig _ _4-'-_ _+-_....;·V~ To Pin 18-'7.lt":""-:--+---+V-t + IMF COM ±15VDC Supply .5VOC Supply FIGURE 9. Differential Sensing Output Op Amp Configuration. The DACn and the wiring to its connectors should be located to provide optimum isolation from sources of R FI and EM I. The key word in elimination of R F radiation or pickUp is loop area. Therefore. signal leads and their return conductors should be kept close together. This reduces the external magnetic field along with any radiation. Also. if a signal lead and its return conductor are wired close together they present a small flux-capture cross section for any external field. This reduces radiation pickUp in the circuit. The metal case of the, DACn is internally connected to the common pin to further minimize pickup, The DACn is made of nickel plated steel which also provides some electromagnetic shielding. NOTE: It is recommended that 'the digital input lines of the DACn be driven from inverters or buffers of TTL input registers to obtain specified accuracy. DRIVING A RESISTIVE LOAD UNIPOLAR A load resistance. RI.. with the current output model connect as shown in Figure 10. will generate a voltage range. VOl't. determined by: VOl" = -2mA[( 15k!1 x RI.), (15k!1 + RLl] Where RI. max = 1.36k!l and VOl"t max = -2.5V Add an external low T.e. « IOppm "C) resistor (RI.) as shown in Figure II to obtain a 0 to -2V full scale output voltage range for CCD input codes. VOlt = 1.25mA [(l5.6k!l x RLl (l5.6k!l Where RI. max = 1.79k!l and VOlt max = -2.0IV FIGURE 8. Preferred External Op Amp Configuration. 6-125 + Rl.l] APPLICATIONS \i DRIVING AN EXTERNAL OP AMP WITH CURRENT OUTPUTDAC The DAC72-(CSB, COB, CCD)-I are current output devices and will drive the summingjunction ufan op amp to produce an output voltage (see Figure 13). The 01' amp output voltage is: Current controlled by digital Input + , Oto 2mA 151m VOl·., = -IOIT R ... FIGURE 10. Equivalent Circuit DAC72-CSB-I Connected for Unipolar Voltage Output with Resistive Load. \r Current controlled by digital Input FIGURE 13. Ext.ernalOp Amp Using Internal Feedback Resistors. 15.6kn Where 100T is the DAC72 output current and R ... is the feedback resistor. Use of the internal feedback resistor (pin 17) is required to obtain specified gain accuracy and low gain drift. FIGURE II. DAC72-CCD-1 Connected for Voltage Output with Resistive Load. DRIVING A RESISTIVE LOAD BIPOLAR The equivalent output circuit for a bipolar output voltage range is shown in Figure 12. VOlT is determined by: VOl·., = ±lmA [(4.44kO x RLl/(4.44kH + RIl] Where RI. max = 5.72k!l and VOl·., max = ±2.5V The DAC72 can be scaled for.any desired voltage range with an external feedback resistor, but at the expense of increased drifts of up to ±25ppmj"C. The resistors in the DAC72 are chosen for ratio tracking of ±I ppml"C and not absolute TCR (which may be as high at ±25ppmj"C.) An alternative method of scaling the output voltage of the DAC72 and preserving the low gain drift is shown in Figure 14. Current controll. by dlgltllinput \I~--t---K.J--t--o + '±lmA 4.4kn FIGURE 12. DAC72-COB-1 Connected for Bipolar Output Voltage with Resistive Load. FIGURE 14, External Op Amp Using Internal and External Feedback Resistors to Maintain Low Gain Drift. 6-126 OUTPUTS LARGER THAN 20-VOL T RANGE For output voltage ranges larger than ±IOV, a high voltage op amp may be employed with an external feedback resistor. Use 1011 values of ±lmA for bipolar voltage ranges and -2mA for unipolar voltage ranges (see Figure is). Use protection diodes when a high voltage op amp is used. In the bipolar mode the major portion of gain drift is due to the zener reference. The gain and ofrset drifts caused by reference drift arc always in opposite directions. Therefore, the accuracy drift will be the difference rather than the sum of these drifts. First, consider the effect of reference variations on ollsct drift. Figure 16 shows a simplified circuit diagram of a DACnC-COB-V with all bib 01T. The current switch leakage current is negligible, so ......----....... 17 V-I'll" .\11 = (-RI RIII'R)' VRII = (-IOkll 6.3k!l) • 6.3V = -lOY +Vcc IOku VOUT VOUT = ·IOV FIGURE 15. External Op Amp Using External Feedback Resistors. FIGURE 16. Simplified Diagram of DACnC-COB-V with "All Bits Off' (±IOV Range). COMPUTING TOTAL ACCURACY OVER TEMPERATURE The accuracy drift with temperature of a DACn consists of three primary components: gain drift, unipolar or bipolar offset drift, and linearity drift. To obtain the worst-case accuracy drift, most users would assume that all drift errors are random and would simply add them algebraically. However, the worst-case accuracy drift for a DACn operating in the bipolar mode is about one-half of the algebraic sum of the individual drift errors. This equation shows that if VRI'I- increases, the output voltage will decrease and vice versa. If the VRII drift is + IOppm/ "c, this is equivalent to (+lOppm "C) x (+6.3V) = +63V;"C, This will result in a voltage drift at the amplifier output of .l V-lSI .l T = -( RI , RIIPo ) .(.l VRI'F .l T) = -( IOk!l 6.3k!l). (631lV "C) = -IOOIlV "C. Since the DACnC-COB-V is operating in the ±IOV range this is equivalent to (-IOOIlV "C) 7 (20Y range) = -5ppm of FSR "c' To explain this fact, it is necessary to consider the unipolar and bipolar modes of operation separately. The following analysis is for the DACnC although it applies to both models by simply substituting the proper temperature coefficients from the electrical specifications. Now consider the effect ofreferenc.e changes on gain drift. When all of the bits are turned on it can be shown that: In the unipolar mode of operation, offset drift (±l ppm/ "C) is due primarily to voltage offset drift of the output op amp and, to a lesser extent, to the leakage current through the quad current switches. Gain drift consists of several components: I) ±5ppmj"C due to ratio drift of current switch V BE to the reference transistor, 2) ±lOppm('C due to the zener reference and, 3) ±2ppmj"C'linearity drift due to ratio drift of current weighting resistors and VIII of the quad current switches. The sum of these three components, ±17ppmj"C, is the maximum gain drift. This result indicates that the drift of the minus full scale voltage will be ~qual in magnitude to, and in the oppposite direction of. the drift of the plus full scale voltage and that zener reference variations have virtually no effect on the zero point (see Figure 17). This equation also indicates that the gain drift is equal to the VRII drift in ppm. "C, and the magnitude of the minus full scale drift and plus full scale drift is equal to one-half of the V RII drift. Because the parameters described could all drift in the same direction, the worst-case accuracy drift in the unipolar mode is simply the sum of the components, or ±18ppmj"C. 6-127 .l V+I·I'!.I SCAli .l T = +( R", RllPo)' (.l VRII' .l T) =+(IOk!l/6.3k!l).(63IlV"C)=+IOOIlV"C and (+IOOIlV,"C) 20V Range = +5ppm. "c of FSR. Using this relationship, the worst-case accuracy drift for a DACnC-COB-V can be computed. The maximum TCR of the zener reference is ± IOppm. "c. The gain drift due to the reference then is also ± IOppm "C. The full scale drift and bipolar offset drift are each half that amount or ~ i '" II' i ~ I I ' /; .. ,,.~ ±5ppmj"C The maximum gain and offset drifts of the DACnC, exc\usiv~ of the reference, are ±5 and ±3ppmj"C respectively. Adding this to the full scale drift due to the reference plus the linearity drift of±2ppm/"C gives a worst-case total accuracy drift of ±15ppmj"C (Random drifts, which these are can be . in the same direction, so they add directly.) This is much less than the total drift obtained by simply adding the maximum gain, bipolar offset, and linearity drifts (±27ppmj"C). The maximum zero point drift is equal to one-half of the gain drift exclusive of the reference plus the offset drift exclusive of the reference, or ±S.5ppm of FSRj"C The DAC72C is specified over a O"C to+70"C temperature range giving a maximum excursion from room temperature (+25"C) of 45"C Assuming that gain and offset errors have been adjusted to zero at room temperature, , . t , Ralaranca drift not affact dOli ,~ zaro point. (II Digital Input (bll ., . .lV+FS= ·.IV.FS Gain DrHt = .lV+FS, -.lV. FS ~ ~ ~ I ~ = 2.lV+FS I 1/ Error ~ (LSDI (bl t --r-r-r-r",..............~1~II. total worst-case accuracy error = Linearity error + Accuracy drift x ~ T = ±0.003% + ±(Sppmj"C (45") (100) =±O.07% total worst-case bipolar zero point error Bipolar zero drift x .l T = ±Sppm of FSR% (4S"C) (100) =±0.025% 0 L-._ :JTII ·3 FIGURE 17. (a) Effect of a Positive Reference Drift on the Ideal Dj A Transfer Function; (b) Error Distribution Due to Reference Voltage Drift in a DAC72. ORDERING INFORMATION MODEL CURRENT MODELS DAC72C-COB-1 DAC72C-CSB-1 DAC72C-CCD-1 DAC72-COB-1 DAC72-CSB-1 DAC72-CCD-1 TEMP RANGES PKG INPUT CODE aoc to +7aoC aoc to +7aoC aoc to +7aoC -25°C to +85°C -25°C to +85°C -25°C to +85°C Metal Metal Metal Metal Metal Metal Compl. Offset Binary Compl Straight Binary Compl. Coded Decimal Compl. Offset Binary Compl. Straight Binary Compl. Coded Decimal aoc to +7aoC aoc to +7aoC aoc to +7aoC -25°C to +85°C -25°C to +85°C -25°C to +85°C Metal Metal Metal Metal Metal Metal Com pI. Compl. Compl. Compl. Compl. Compl. VOLTAGE MODELS DAC72C-COB-V DAC72C-CSB-V DAC72C-CCD-V DAC72-COB-V DAC72-CSB-V DAC72-CCD-V 6-128 Offset Binary Straight Binary Coded Decimal Offset Binary Straight Binary Coded Decimal DAC73 DAC736 BURR- BROWN@ IElElI High Resolution 16-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES ,------------_._---------------,, , • 16-BIT RESOLUTION 6V Refaranca • ±lI2LSB MAXIMUM NONLINEARITY • LOW DRIFT • CURRENT OR VOLTAGE OUTPUT • INTERNAL GAIN, OFFSET, AND LINEARITY ADJUSTMENT Output t-_-,---.8round Sansa • LATCHED INPUTS [DAC73) • LOW COST ! is Precision RlIlllDr NllwDrk Hybrid DESCRIPTION The DAC73 is a 16-bit modular high performance digital-to-analog converter in a 2" x 4" x 0.4" (50.8mm x 101.6mm x 1O.2mm) package. The low drift and ultra-high linearity of the DAC73 provide voltage or current output signals that are accurate to ±0.00075% of full scale input range at 25°C ambient. The critical components including the current steering switches, the temperature-compensated zener reference, and the precision laser-trimmed bit resistor network are contained in a single ceramic hybrid package. The feedback and reference resistors are laid out for maximum stability with low current density and ±lOppm/oC maximum temperature coefficient with ± I ppm/ "C tracking. This insures very-low superposition errors and low temperature coefficient. of gain. The inputs are TTL-compatible CMOS and contain level triggered latches in an 8-bit format for microprocessor data bus compatibility. No external components are required to achieve full 16-bit accuracy. Gain and offset potentiometers are also included in the DAC73. The DAC736 has electrical specifications identical to the DAC73, but it is pin-compatible with the AD1136. The input latches, bit adjust pins, ground sense pin, and internal offset adjust pot are not included. International Alrporllndustrlal Park· P.O. Box 11400· Tucson. Arizona B5734· Tal. (6021 746·1111· Twx: 911).952·1111 . Cable: BBRCORp· Telax: 66-6491 PDS419 6-129 SPECIFICATIONS ELECTR.ICAL TA = 25°C and rated power supplies unless otherwise noted. I I MODEL MIN .. ;" DAC73JIDAC738J TVP I I MAX I I DAC~.3K/DAC736K MIN I I .TYP MAX T I UNITS INPUT DIGITAL INPUT Resolution - CSB, COB Logic Levels (TTL-Compatible CMOS) Logical "I" (at +1.0"A) Logical "0" (at-O.5mA) t6 +3.5 -0.5 +5.5 +1.5 +3.5 -0.5 16 Bits +5.5 +1.5 VDC VDC ±O.OOO75 ±0.02 ±O.OS ±0.25 ±O.B ±10 ±1 ±5 +35 %01 FSRll) % % % mV mV TRANSFER CHARACTERISTICS ACCURACY Linearity Error at 25°C .Gain Error,12) Voltage CSB CIDB Current Offset Error,12) Voltage, Unipolar Bipolar Curren~. 'I ±0.005 ±0.Q1 ±O.05 U,nipolar Bipolar Monotonicity Temp. Range 16 Bits lor K, 15 Bits lor J ±o.o015 ±0.02 ±0.05 ±0.25 ±0.8 ±10 ±1 ±5 +5 ±15 DRIFT Over specilied temp. ranael Total Drill (includes gain, ollset, and linearity drill) CSB COB Total Error over Temp. Range(3) Voltage, Unipolar to 70°C Bipolar Voltage, Unipolar 15°C to 35°C Bipolar Gain (Exclusive 01 relerence drift I Offset (Exclusive 01 relerence drift I Unipolar Bipolar acc Differential Linearity over Temperature Linearity Error over Temperature SETTLING TIME Voltage (to ±O.OOO75% 01 FSRI Output: 20V Step I LSB Stepl') Slew Rate Current (to ±O.00075~ 01 FSR I Output: 2mA Step COB Switching Transient Magnitude COB Switching Transient Energy ±0.005 ±O.01 ±O.OS "A "A °C ±9.5 ±9 ±24 ±22 ±9.5 ±9 ±24 ±22 ppm 01 FSRfOC ppm 01 FSRfOC ±0.043 ±O.040 ±O.010 ±0.009 ±4 ±0.108 ±O.099 ±O.024 ±0.022 ±10· ±0.043 ±O.040 ±O.010 ±O.009 ±4 . ±0.108 ±O.099 ±0.024 ±0.022 ±10 % 01 FSR %01 FSR % 01 FSR % 01 FSR ppmfOC ±O.5 ±2 ±1 ±1 ±2 ±5 ±2 ±2 ±0.5 ±2 ±1 ±1 . 50 6 18 10 6 18 6 4.5 5 ±2 ±5 ±2 ±2· 50 10 ppm :ppm ppm ppm 01 01 01 01 FSR/oC FSR/oC FSRfOC FSRfOC "sec pSsc VI"sec 6 4.5 5 ",sec Oto +5 Oto+l0 ±2.5, ±5, ±10 V V V mA mA V nJ OUTPUT ANALOG OUTPUT Voltage Output Ranges - CSB Oto+5 Oto+l0 ±2.5, ±5, ±10 COB Output Current - Unipolar Bipolar +4 ±2 O.OS 0.03 Indefinite to Common 0.03 0.05 Indelinite to Common Output Impedance (DCI Short Circuit Duration Current Output Ranges - CSB COB Output Impedance - Unipolar oto-2 Oto -2 ±1 15 Bipolar Compliance INTERNAL REFERENCE VOLTAGE +4 ±2 5.990 4.4 4.4 -1.5 to +10 6.000 6.010 5.990 6.000 ±10 6.010 +4 +4 Maximum External Current(S) mA mA kll kll V ±1 IS -1.5to+l0 ±4 Il ±10 V mA ppm/oC Temp. Coeff. ±4 OUTPUT NOISE Current, COB O.IHz to 10Hz 10Hz to 100kHz Voltage, COB, ±10V Range 0.1 Hz to 10Hz 10Hz to 100kHz 1 1 4 4 nA, pop nA.rms 10 70 10 70 ",V. rma 6-130 "V, pop ELECTRICAL (CONT) MODEL MIN DAC73J/DAC736J TYP STABILITY, LONG TERM Gain (Exclusive of reference) Offset COB I Exclusive of reference I MIN MAX DAC73K/DAC736K TYP CSB POWER SUPPLY SENSITIVITY Unipolar Offset :t15VDC +SVDC Bipolar Offset ±15VDC +5VDC Gain ±15VDC +5VDC ±5 ±5 :to.25 ±10 :to.25 :t10 :to.OO01 POWER SUPPLY REQUIREMENTS Rated Voltage Range Supply Drain. :t15VDC • no load +5VDC ' logic supply :t20 :to.OO01 :to.OO01 %of FSR/% Vs % of FSR/% Vs :to.OOO4 ±O.OO01 :to.OO04 :to.OO01 % of FSR/% Vs % of FSR/% VS ±0.001 :to.OO05 :to.OO1 :to.OOO5 % of FSR/% Vs % of FSR/% Vs :t15. +5 +35. -45 :t15.5. +5.25 +50. -60 ±15. +5 :t1S, +5 +35. -45 :t14.5, +4.75 9 TEMPERATURE RANGE SpecificallOn Storage ppm of FSR/ 103hr ppm of FSR/ 103hr LSB/103hr ppm/103hr :to.OOO1 ±15. +5 ±14.5. +4.75 UNITS ppm/103hr ±30 ±30 ±30 ±30 Linearity Reference MAX 9 +70 +100 0 -55 ::!::15.5, +5.25 +50. -60 NOTES: 1. FSR means Full Scale Range and is 20V for ±10V range, lOV for ±5V range. etc. 2. Adjustable to zero with internal trim potentiometer (offset adjustment external on OAC736l, °c +70 +100 0 -55 VDC VDC mA mA °C .4. LSB is for 16~bit resolution. 5. Maximum with no degradation of specifications. 3. With gain and offset errors adjusted to zero at 25°C. MECHANICAL DAC73 I" IJ ~I r-::-::nUII I IIII G ....J I.- r 1 1 I lUI I I IIII I lou p....J \... NOTE: Leads in true , NOTE: Leads in true position within .015" 0 .38mm oR at MMC at seating plane. position within .015" l.38mmlR at MMC at seating plane. I I ....JI.-o DAC736 I I I I I.--L -J L.::1 r-" c- "==A=J:+.. ... , .,:,:"-:.-:,:",:,:,,--,::-:-.,...,.=:-:-:-:-:-,, • •••• • • • '360 I.--L -J Pin numbers shown for reference only. Numbers may not be marked on package. " " INCHES DIM G MILl.IMETERS INCHES MIN M"X MIN Mo.X DIM 3.950 ".010 100.33 101.85 A 1.950 .3&0 2.010 .410 "9.63 51.06 MILLIMETERS MIN M"" MIN 3.960 4.010 100.33 101.86 1.950 .350 Mo.X 2.010 .410 49.53 8.89 51.06 .019 .021 .100 BASIC .160 .250 0.63 0."8 2.54 BASIC 3.B1 6.36 .021 .019 .100 BASIC .160 .260 0.48 0.53 2.&4 BASIC 3.81 6.36 .260 .360 1.BOO BASIC 6.36 B.89 46.72 BASIC .250 .350 1.800 BASIC 6.36 8.89 46.72 BASIC .200 BASIC 0.60 .160 8.89 5.08 BASIC 1.27 I .200 BASIC 3.Bl 0.50 6-131 .150 5.08 BASIC 1.27 3.81 I . CONNECTIONDIAGRAM1UnipoiarO to +10V) * ltV! "'1tV1 " . PIN ASSIGNMENTS * RV3 • /-:0; ..",,,,..-,,,,.,,,,,,--,,,,.,,,,,;-,;,,.,,,,,,..., V4 0000 1111 IU el81T1IM", ellllTI 5kn • ,lin e,111T7 .'!IITI BIT UlIJ &II • '"ITD • ,utI! ."UTCII 1lI1{:: ...... e24I1T14 _2&IITI5 -1I.ln. ell AM'"44. e34C0111 • ui I 0 + .---_--+-_~--I Vout + Skll To Pin 34 CONNECTION DIAGRAM (Blpolar±10V) DISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES The DAC73j736 accepts complementary digital input codes in CSB or COB format. The COB model may be connected by the user for either complementary offset binary (COB) or complementary two's complement (CTC) codes (see Table I). T ABLE I. Digital Input Codes. DIGITAL INPUT CODES +15VOC r-......~..., t-.,.,.,----1l111-~::~~ CSB '" ;;l +--+---liii1~ -15VOC C .. 8 Com pI. Straight Binary 0 5kn ;:;; 5kn iii '" U Precision Hybrid III-B" OAC h5 0 'Internll Llnurlly AdJustment PolanHomliarl 12kn Common 134IIf---" UA1rJII$T IJlT rFlETAIUUIT liS 0 o\IIPlIIT47. 1IPCIUI\IfFfE' • • e.-till .u:~" 22Mn t6~ • • +IM IIIIIUIIDIEIIEG. ell+15V allf.:: .... .. 44. .D11T13 "OOT47. IlPOUIQFfIlT4Ie ...'.·r- 22Mn 22Mn ellllTll .'111'" R:E~=' eniiTIS _2411T14 -2S11T15 -ZIIlInl 22Mn .'IIITO _I7I1TIO IITt.IUY. IITilL/a. 'lilT 11 DAC73 e II13ADoI57 • , 17I1Tl0 . Precision , Hybrid I6-Blt OAC u. cUllRElrau' •• .IUIYI ,IIIiTl IIIIU Skn III" ZEIIDMLl71e 10l • • ,.,,' .UI1I 1113 • niTa enlT4 tuRllElITlUT • • 10k • • • IUTtI! IU eUln ZEIOAIIHI.·· .UITa e.m4 1111 .1I1T1j_" .,.. enlTt 10M!! 0000 au 1113 DAC736 MSB LSB I I COB CTC' Compl. Offset Binary Compl. Two's Complement +Full Scale +Full Scale All bits ON 0000 .. ,000 -lLSB Zero 0111...111 +1/2 Full Scale -Full Scale Mid Scale -Full Scali. Zero Zero All Bits OFF 1111...111 -lLSB 1000...000 Mid Scale-1LSB +Full Scale *lnvert the MSB of the COB code with an external·inverter to obtain CTC code. INPUTS Each bit input of the DAC73 consists of a buffered CMOS D type latch (see Figure I). Bits I (MSB) through 8 are latched by a low level on pin 6. Bits 9 through 16 (LSB) are latched by a low level onpin 21. The latch inputs maybe left ope~ for transparent transfer of data. 12kn +5VOC IOkll, OAC73 6lcn Vout Input Commana----. Bullared CMOS Latch FIGURE I. DAC73 Input. 6-132 The DAC736 inputs are CMOS inverters with 10k!! pullup resistors (see Figure 2). oAC736 +5VOC 10ku end point differences for each DAC73 model at +25"C and the appropriate specification temperature extremes; 2) calculating the gain error with respect to the +25"C value; and 3) dividing by the temperature change. This is expressed in ppm/ "C. Offset Drift is a measure of the actual change in output with all "I Us on the input over the specified temperature range. The maximum change in offset is referenced to the offset at +25"C and is divided by the temperature range. This drift is expressed in parts per million of full scale range per "C (ppm of FSRj"C). CMOS Inverter FIGURE 2. DAC736 Input. The DAC73 and DAC736 can be driven directly by open collector or totem pole TTL logic. +0.10 ACCURACY +0.05 Linearity e: ~ This specification describes one of the truest measures of Dj A converter accuracy. As defined it means that the analog output will not vary by more than ±0.00075% max (CSB, COB) from a straight line drawn through the end points (all bits ON and all bits OFF) at +25"C (see Figure 3). c '" -ll.05 ·0.10 FIGURE 4. Gain Drift Error (%) vs Temperature. SETTLING TIME Settling time for each DAC73/ 736 model is the total time (including slew time) required for the output to settle within an error band around its final value after a change in input (see Figure 5). O. 15 25 35 , 1 70 Temperalura 1°C) ;: FIGURE 3. Nonlinearity vs Temperature. 0.1 8'! ~ Differential Linearity ~ Differential linearity error of a Dj A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±I j 2LSB means than the output. voltage step sizes can be anywhere from I j 2LSB to 3j2LSB when the input changes from one adjacent input stage to the next. - 0.01 ------ ! I.J- \ I ±2OV SlID lLSB j'e?- I-ti-SB 16 I -- 1~~{~L~2~~---__ _JI2LSB _ 15 BIts __ oS 0.001 0.0001 I 1I2LSB 12 Blta 3 8t;"- 10 30 SeHllng Timel"Bec) 100 FI G U R E 5. Full Scale Range Settling Time vs Accuracy. Monotonlcity Monotonicity over a ±5"C range for the DAC73 and DAC736 is guaranteed when ambient linearity is calibrated. This insures that the analog output will increase or remain the same for increasing 16-bit input digital codes. Settling times are specified to ±0.00075% of FSR; one for maximum full scale range changes of 20V and one for a I LSB change. The I LSB change is measured at the major carry (0111...11 to 1000 ... 00), the point at which the worst case settling time occurs. DRIFT Gain Drift is a measure of the change in the full scale range output over temperature expressed in LSB's per "c (see Figure 4). Gain Drift is established by: I) testing the COMPLIANCE Compliance voltage is the maximum voltage swing allowed on the current output while maintaining 6-133 • specified accuracy. The ,maximum compliance voltage is -1.5V to +IOV. could be switched in by relays to null bipolar gain and offset. An alternate offset adjustment is shown on the DAC736 connection diagram. POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the D/ A converter output. It is defined as a percent of FSR per .percent of change in either the positive, negative, or logic supplies about the nominal power .supply voltages (see Figure 6). OAC73 48 lOMI! Rs lOOtl! RVI 1000 .,;;~ ~ 0ZI and 0Z2lre IN4104. RVI is 2Q.lUrn. lOOppm/"C I·I5!0~~S.u ~',Y, 100 FIGURE 7. External Gain Adjustment. '"'" '0 E ! '"'" 0.. 10 W ... i ~ = OAC73 IIl1l1i o ·'1 :uIT 111111 10 100 It lOt lOOt Analog Common Frequency (Hz) FIGURE 6. Power Supply Rejection vs Power Supply Ripple Frequency. REFERENCE SUPPLY All models are supplied with an internal +6V reference voltage supply. This reference voltage (pin 52) has a tolerance of ±O.05% and is connected internally for specified operation. The z,ener, is selected for a Gain Drift of typically ±4ppmj"C and is burned-in for a total of 48 hours for guaranteed reliability. This reference may also be used externally but the current drain is limited to 4mA and constant load conditions. 0ZI and 0Ulre IN410l. RV2ls 2Q.lurn. lOOppm/"C FIGURE 8. External Offset Adjustment. ILSB ~ .. J Rangeo' .,'" Saln Adl. ~-=-)'t -:~~ ~ '};7o1ln Adj. :f {'Y rm:..esthe line Tf '; All Bits logic I I ' .. All BIts logic ~ INSTALLATION AND OPERATING INSTRUCTIONS ,POWER SUPPLY CONNECTIONS For optimum performance and noise rejection the DAC73/736 decoupling capacitors, areinc1uded internally. Refer to Figure 13 for correct grounding connections. OFFSET AND GAIN ADJUSTMENT Before taking measurements or making adjustments, the DAC73/736 should be warmed up for at least 25 minutes. The DAC73 has internal gain and offset potentiometers that are connected to an internal regulated supply. In most applications no external adjustment will be required. External offset and gain adjus,tment of the DAC736, or DAC73 if the application requires, maybe accomplished as shown in Figures 7 and 8. These external circuits could be used in an application using both unipolar and bipolar modes. Refer to Figures 9 and 10 for relationship of offset and gain adjustments to unipolar and bipolar D/ A converters. The internal potentiometers could be used to null the unipolar gain and offset, and the external null +Full SClle ° 011181 Dlgllllinpul FIGURE 9. Relationship of Offset and Gain Adjustments for a Bipolar D/ A Converter. ...~ /", i ;El -! ~ :f Range~ DffIBlAdl. Off8B1AdI.L Trensilles orthe'lina T All bits logic I ~ ::e :X ...... ~~"T ;' RangeDl k;;{ Gain Adl. ...~ ~ rataleslhe Slln Adl. line , ° fi- 'if' All bill logic Digital Input FIGURE 10: Relationship of Offset and Gain Adjustments for a Unipolar D/ A Converter. OUTPUT RANGE CONNECTIONS Internal scaling resistors in the DAC73j736 provide a wide range of output voltage range connections. These internal resistors may be connected to provide three bipolar output voltage ranges of±IOV, ±5V, or±2.5V or two unipolar voltage ranges of 0 to +5V or 0 to + IOV. Since the internal scaling resistors are an integral part of the DAC73/736, gain and offset drift are minimized by their use. Connections for DAC73j736 are shown in Table II. Figure II is a connection diagram. LINEARITY ADJUSTMENT Internal If it becomes necessary to adjust the linearity of the DAC73 or DAC736 after an extended time period or for operation under temperature extremes, the 4MSB's may be user-adjusted. For optimum operation the unit should be calibrated in its operating environment. Calibration is performed by a differential linearity adjustment at the first four major carries. This method of calibration is possible since the DAC73 .and DAC736 have almost no superposition error. The calibration procedure including gain, offset, and linearity adjustment is outlined in Table III. Steps I and 10 may be omitted for linearity adjustment only. TABLE II Output Range Connections. Digital Connect Input Codes Pin 47 to Output Range ±10V ±5V ±2.5V o to +10V o to +5V Connect Pin 46 to Connect Pin 44 to Connect Pin 68 to 44 44 44 NC NC 69 69 69 69 69 47 NC 69 NC 69 66 COB COB COB CSB CSB 70 70 70 70 External(DAC73 only) The linearity adjustment of the first 4MSB's of the DAC73 may be accomplished externally either with potentiometers or with D/ A converters. Using a DAC to adjust linearity will allow computer controlled accuracy adjustments of the DAC thus giving the capability of maintaining 16-bit accuracy over all environmental variations. Gain and offset may also be adjusted in this manner. Eight-bit bipolar voltage output DAC's can be used for all of the adjustments. Each circuit is shown in Figure 12. In all cases pins 52 and 53 and pins 48 and 49 should be shorted together with low resistance, capacitance connections. 5kn ~: 5kl! I' ",.,., 6kn 53 0 0 "'No INSTALLATION CONSIDERATIONS To maintain the extremely-high accuracy of the DAC73 and DAC736 when installed in a system environment, careful attention must be paid to grounding and to connection resistances. Figures 13 and 14 are examples of correct connection configurations to yield maximum accuracy. The effects of various wiring and contact resistances R .. R2, RJ, and R. are reduced or eliminated as follows. R, appears in series with the feedback resistance and therefore introduces only a gain error that can be nulled during calibration. R2 is inside the output amplifier feedback loop and its effect will be reduced by the loop gain. In Figure 13 for the DAC736, R, is in series with the load :: it> 46 FIGURE II. Output Amplifier Voltage Range Scaling Circuit. TABLE III Calibration Procedure ;' DVM READING STEP HEX INPUT CODE ADJUST POTENTIOMETER"I UNIPOLAR MODE ±10 VOLT BIPOLAR MODE DESCRIPTION 1 FFFF Rv6(2) O.OV -10.0000V Null Offset 2 FOOO N/A V4 V4 Read Output Voltage 3 EFFF RV4 4 EOOO N/A V3 V3 Read Output Voltage 5 DFFF RV3 V3 + 153~V V3 +305~V Adjust RV3 until DVM reads V3 + 1LSB < 6 COOO N/A 7 BFFF RV2 V4 + 153~V V4 + V2 V2 V2 + 1S3~V 305~V V2 + 305~V Adjust RV4 until DVM reads V4 + 1LSB Read Output Voltage Adjust RV2 until DVM reads V2 + 1LSB 8 8000 N/A V1 V1 Read Output Voltage 9 7FFF RV1 V1 + 153~V V1 +305~V Adjust RV1 until DVM reads V1 + 1LSB 10 0000 RV5 +9.999847V +9.999895V Adjust Gain NOTES: I. For potentiometer locatIOn see Pm ASSignments. 2. External offset adjustment on DAC736. 6-135 resistor and will cause an error in the voltilge across RI.' One-half LSB error would result at full load for R,. = 0.020. Therefore. if possible. sense the output voltage to include R,. Range: ±O.5mV Adjustment Resolution: ±4~Y (Bipolar Moda) Figure (4 illustrates the optimum connection made possible. by the ground sense pin on the. DAC73. In the configuration shown ItF = RF and R'R II RR = RIlAC II RRPO. This causes any signal developed across R, to be rejected as a common-mode input. and R, will not affect the voltage across RI.. This configuration will also reject noise present on the system common. R. is negligible in both circuits when ground connections are made as shown. ------'-, ,68 Rr GAIN ADJUST (Manual coarse adjust requll'l\l). Range: +25LSB. -4LSB. Resolution: ±O.I LSB »)-------® ±tOV Range Sanla Oulput LINEARITY ADJUST (Repaat lor each 01 the bit adjust Inputs). FIGURE 12. External Accuracy Adjustment.. r~ f.6~ , ,,, , , i9 ,, __________ J 44 "---:------~ ~E ~ ROle , , I 1.- - - - - - - - 15k!! 15k!! RB ------34( \)/ ~ ~ , ,:- R2 , ,,, , ______ ___ J ~ ~ R4 Ra VL To Pin 2B .y ~-: FIGURE (3. DAC736- Unipolar Mode. .- FIGURE 14. DAC73 - ±IOV Bipolar Mode . RL ~ Sansa Oulput +V ±15YDC Supply Rl ,:-- +liYDC Supply The DAC73f736 and the wmng to their connectors siiould be. located to provide optimum isolation from sources of RFI and EM!. The key word in elimination of RF radiation or pickup is loop area. Therefore, signal leads and their return conductors should be kept close together. This reduces the external magnetic field along with any radiation. Also, if a signal lead and its return conductor are wired close together they present a small flux-capture cross section for any external field. 6-136 BURR-BROWN® DAC74 IElElI Self-Calibrating High Resolution True 16-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • 16-BIT RESOLUTION • SELF-CALIBRATION MAINTAINS ACCURACY OF ±1/2LSB NONLINEARITY } . ±O.00035DfD 6AIN ERROR +15°C TO +45OC ±40jlV OFFSET • UNIPOLAR OR BIPOLAR VOLTAGE OUTPUT • OOUBLE BUFFEREO FOR AN a. OR 1I1-BIT BUS The DAC74 is a self-contained true 16-bit Digital-toAnalog converter designed for applications requiring high resolution and accuracy such as displays, frequency synthesizers, automated test equipment, analytical instruments; and high resolution controllers. Furthermore, in applications where equipment is inaccessible or frequent calibration is impractical the DAC74 is ideal because the self-calibration accuracy depends only on the long term stability of a heated zener reference diode. Using self-calibration circuits, the DAC74 maintains typically ± I LSB total error over + I S"C to +4S"C! Compare this with other high resolution converters which can only maintain this accuracy over a ±2"C or ±3"C range. A patented microprocessor-controlled differential measurement technique is the key contributor to the DAC74's drift performance. This technique allows use of low cost hybrid and monolithic circuits to remove linearity, gain, and offset errors resulting from ambient temperature variations, component aging, and varying load conditions. DIGITAL IIPUT CDITRDL IIPUTAID OUTPUT CONTRIIL CIRCUIT WITH RDM AID RAM MEASUREIlEIT CIRCIIT This product is covered by United States patents4.222.I07 and 4.272.760. Other patents pending may also apply upon the alluwance and i~~uancc ufpatcnts thereon. The product may also be covered in other countries by one or more international patents corresponding to the a.bo\C' idcnlii'iL'li LJ .S. patent!.. International Alrparllnduslrlal Park· P.O. Box 11400· TUCIon. Arizona 85734 • Tel. (602) 748·1111 . Twx: 910-952·1111 . Cable: BBRCORP • Telex: 66-6491 PDS-442 6-137 SYSTEM DESCRIPTION·· The OAQ4is a self,;calibrating, 16-bit digital-to-analog convertet'in 5"x: 7~x(J;6· ( 127mm x 178mm x 15.2mm) package. This OJ A converter provides either a unipolar or a bipolar voltage output that is linear to within ±I j2LSBofthe Full Scale Range(FSR). The FSR in the 'unipolar mode is set by the internal + IOV reference. The FSR in the bipolar mode is set by the difference between the + IOV and the -IOV references. With respect to the internal references, the offset and gain errors are. also less than ±lj2LSB. The settling time to ±I j2LSBis typically 6p.sec fora··1 LSB step. A microprocessor-con~rolled calibration circuit retrims the OJ Aconverterto this accuracy in the face of drift over·. temperature and time. The; lIbsolute .lIccuracy of the calibration is dependent upon the accuracy oCthe internal voltage references. The drift of the reference is typically ±O:5ppm/"C. a The linearity and accuracy of the OAC74 versus temperature is illustrated in Figures I and 2., The calibration was performed at 5°C intervals. It' can be seen that the calibration greatly increases the useful temperature range of the 0; A converter. The OAC74 (see Figure 30} consists of(l)a"16"bit, latched input main O! A converter, which pe,i:forms tbe digital-toanalog conversion, (2) a stable, temflerature-co'mpensated voltage reference, (3) an~ error~measuring circuit whiclil compares the OJ A converter output to known references. and (4) a microcomputer-based controller that stores the outppt, of .theerror measuring circuit and calculates cQrrection factors for offset. gain, and linearity. The controller stores these correction factors in RAM and these are used to adjust errors when an input data word selected by the· user is ·presented at the input ttl the main OJ A converter. The criticar(:ompo~ents,' including the 'current steering switches and the, la~er-trimmed' resistor network. arc 'co~tained in a sing-ie ceramic hybrid package for improved thermal tracking. The zener reference is maintained at a constant temperature· to reduce drift due toambierit temperature fluctuations. The OAC74 is housed in a steel package which prQvides excellent electromagnetic shielding. The package can be mounted from eitherside for socket mounting Or for use of ribbon cable connect~rs. ,.'" f· ., TEMPERATURE rei FIGURE I. OAC74 Linearity Versus Temperature. II.OOfI .0.004 E ~ 0,1102 1/21.88 ';; .:. i :i 0 ·112lS8 .0.002 .0.004 TEMPERATURE 1"&1 FIGUREi'pAC74 A~cu.racy versus Temperature: ,6-138 VOUT MAIN OIA CONVERTER BlSB', ~--~R A 3 STATE • _ M B~ . .~ OIREC- . . ._ . TIONAL... .~===~ 1'1 k CALIBRATION CONTROLLER r-----~Tij~..IE~.....~.K.HIEIEIEIE~! ERROR MEASUREMENT CIRCUIT ·IOV MANUAL ADJUST FIGURE 3. DAC74 Block Diagram. A user initiates a calibration by applying a negative pulse to the reset input RES with the RUN ffi input held low. After an initial system check. the ffi status goes low and a 2.5 second calibration cycle is started. During calibration. the external inputs are disabled and the R Ul'\ status is high. The D; A converter returns to the RUl'\ mode at the end of the calibration cycle. 'ffi remains low in the RUN mode if the calibration was successful. The R"ijN status output is low during normal D A converter operation; in this state. the external digital data inputs are routed to the main D; A converter. THE MAIND/A CONVERTER The 16 data inputs to the main D A converter arc buffered by two octal latches that are enabled by a high input to ENMSB. In addition. the 8LSEfs are double buffered by a latch with an enable input labeled ENLSB. This·arrangement allows transparent operation. a l6-bit interface. or an 8-bit interface. The data inputs are positive true. The MSB is labeled DI5 and the LS.B is labeled DO. Both latches transfer their inputs to the output when the enable ishigh. The input data is held in the latch when the enable is low. Four potentiometers adjust the bit currents for the 4MSB's. Two more potentiometers allow the Offset and Gain to be adjusted manually. After a calibration period of I year, these potentiommeter adjustments may be required to trim the D/ A converter to within the error range which can be trimmed by the self-c;tlibration circuits. The procedure is given in the Manual Calibration section. The output operational amplifier converts the 0 to 2mA current from the bit switches into a voltage output. A 5-wire output connection to the main D/ A converter is described in the Installation section. All five wires MUST be installed to the load as indicated to obtain the full specified accuracy. The output connection diagrams for 0 to + IOV unipolar operation or ±IOV bipolar operation are shown in the I nstallation section. Jumpers must be. installed to configure the main D/ A converter and the calibration circuits for each of these output configurl\tions. PRECISION VOLTAGE REFERENCES The+IOV and -IOV references .. shown in Figure 3. supply the voltage standards for calibrating the main D/ A converter. The -I OV reference is required only for bipolar operation. The ± IOV references derive their outputs from a heated zener reference diode. I n addition. both reference circuits are temperature compensated to cancel variations caused by drift in the other components of the reference. The accuracy of these references over temperature and time determine. the accuracy of the D/ A converter after calibration. These reference voltages are available for external use but the load must remain constant. Alternatively, external +IOV and -IOV references may be used with the DAC74. 6-139 ERROR MEASUREMENT CIRCUIT ,The error measurement circuit ofthe DAC74 includes an analog switch, differential instrumentation amplifier, pedestal offset D/ A converter, and ail analog-to-digital converter. The circuit measures a sequence of voltage pairs. The error of the main D / A converter trim is derived from the differences in each pair ofvoliages. For instance, the Offset error is the difference between the minus full scale D/ A converter output and the minus full scale ref~rence (RTN for unipolar and -IOV for bipolar). The Gain error is the difference between the plus full scale D/ A converter output and the + 10V reference less I LSD. The analog switch selects one of three sources as the input to the instrumentation amplifier. These sources are the main D/ A converter output, minus full scale reference, and the plus full scale reference. The analog switch is controlled by the calibration c,ontroller. The difference amplifier derives one of its inputs from a pedestal offset D / A converter which provides a voltage roughly comparable to the other input. The other input comes from the analog switch. During any pair of measurements, the pedestal offset D/A converter output remains the same. Since the gain of the instrumentation amplifier is 512, small differences (20,:.iV) in the voltage pair are detected by the arialog-to-digital converter connected to the output of the difference amplifier. The input to the pedestal offset D/ A converter is set to the same value as that sent to the main D/ A converter so that the high gain difference amplifier will stay within its linear range. The accuracy of the pedestal offset D / A converter does not affect the calibration accuracy. The 10-bit analog-to-digital converter translates the output of the difference amplifier into a digital code for the microcomputer-based controller. Only the difference in the readings between a pair of measurements is used by the controller. The Gain and Offset of this 10-bit analogto-digital converter are preset at the factory. The control signals to the A/ D converter are generated by the controller during a calibration cycle. CALIBRATION CONTROLLER The Calibration Controller consists ofa microcomputer which has three functions; (I) interpret commands from the control inputs and terminal interface, (2) conduct measurements by sending control signals to the error measurement subsystem, and (3) calculate the trims to be sent to the trim D/ A converters. In the RUN mode, the microcomputer is idle; in fact, it can be turned off to reduce noise by asserting the MPUOFF control input high or leaving it open. The user may initiate a calibration cycle with a negative pulse to the RES control input with the MPUOFF and the RUN/CAL control~ts both low. At the end of the pulse to REs, the RU status output goes high indicating the main D/ A converter is no longer tinder user' control. As discussed in the Manual Calibration section, the CAL. output goes low indicating that the calibration process is underway. At the end of the calibation, the RUN status will return low. lfand only if the calibration succeeds, the CAL status will remain low. The two status outputs RDiii and CAL are open-collector TTL outputs (7406) which can drive an LED,indicator directly. At the end" of the calibration, the controller automatically returns to the RUN mode and control'of the main D/ A converter inputs is returned to the user. The Offset is first adjusted with respect to the minus full scale reference. Then a sequence of four differential linearity measurements are conducted on the four MSD's of the D/ A converter. Starting with the LSD of these four bits, each bit is trimmed to be linear with respect to all the lesser significant bits. Afler the linearity is established, a 'final gain correction is made with respect to the full scale reference. If the calibration fails, either a component has failed, or the internal drift of the system has exceeded the range of the trim circuit. (fcalibration under normal operating conditions fails, adjustments of eight potentiometers must be made to restore the D / A converter to its original accuracy. A detailed description of the calibration procedure is contained in the Manual Calibration section. The trim circuits of the DAC74 consist 'of 16 RAM locations, Linearity/Offset trim D/A converter, and a Gain trim D/ A converter. As shown in the block diagram, the RAM address inputs are taken from either a latch connected to the controller bus or from the four MSD's of the data input to the main D/ A converter. In the RUN mode, the four inputs from the main D/ A converter select one of 16 digital codes. The 8-bit code selected by the address inputs constitutes the sum of the corrections for the Offset error and the sum of the bit errors for those bits of the upper foul' which are logic ones. For instance, the RAM location 0 contains the digital code for just the Offset correction since none of the upper four bits are turned on. The RAM location 8 contains the digital code for the sum of the Offset correction and the correction for the MSD error. During calibration, the controller addresses the RAM. It first zeros the RAM and then adds the correction for the Offset error to all the RAM locations. Then the corrections for the bit errors are added to those locations which have that bit turned on. For instance, the correction) for the MSD is added to all locations whose address starts with one (I XXX). The 8-bit digital code from the RAM is the input to the Offset/ Linearity trim D/ A converter. The output of the trim D/ A converter makes a slight adjustment in the total current of the main D/ Aconverter(one part in 2048). The maximum trim in the unipolar mode is ±2.44ImV. With an 8-bit resolution trim Dj A converter, the minimum possible trim is Ij8LSD orO.019mVat the main Dj A converter output. A final Gain trim is made by sending a separate 8-bit trim word to the Gain Dj A converter. The Gain error is the deviation of the full scale output from the full scale reference (+lOV -ILSD). The maximum and minimum correction range in the full scale output are the same as the linearityj offset maximum and minimum, 2.44lmV. 6-140 SPECIFICATIONS ELECTRICAL MECHANICAL TA = 25°C rated power supplies and after 30 minute warm up unless otherwise noted DAC74 MODEL MIN TYP MAX UNITS Resolution 16 Bits +5.5 VDC VDC r·L Vo~age Levels Logic 1. V,H LogicO. V,L Current 00-015. ENLSB. ENMSB ISN74LS3731 hH. V, = 2.7V hL. V, = 0.4V RUN/CA!:. UNIPOLAR CAL hH. V, =2.4V hL. V, = 0.4V MPUOFF I inc. 10kll puliupi hH. V, =2.4V hL. V, =0.4V +2 o +0.8 m. 20 ~A ,0.4 mA 40 ~A -1.6 mA -0.3 -2.1 mA mA ANALOG OUTPUT Ranges. Unipolar Bipolar Output Impedance I DC I Short Circuillo Common I Duration I Load Current Selliing Time Ito ±1/2LSB, 20VStep lLSB StepP} SlewR.te NOise Voltage. Bipolar O.IHz to 10Hz 10Hz to 100Hz V V Oto+l0 ±10 0.03 0.05 II Indelinite mA ±5 20 50 Ilsac 10 ~sec 18 V/~sec 10 70 ~V. pop ",V.rms DIGITAL OUTPUT Open COllector ISN7406, Iwith 10kll Puliupi Voltage ~evels Logic 1 Logic 0 Current ,with lOkI! Puliupi -----II r------,.--- A AAT r-E~ - - F - DIGITAL INPUT • H 16-32ITHRUI (2 PLIo SEE NOTE 2. r---¥------. I ~~1 "'.":~~"':::.:::::I~ I MJ IT~~~ ~ :1 ~J' JJLG +0.4 V V '6- 32 0.263 DEEP 10.188 MIN DEPTH I 14 PL.I SEE NOTE 2. D! ~ ~ 6:1 V] K I~ : CUT-AWI\Y SHOWING PIN DETAIL NOTES: AB 1. Leads in true position within 0.015" W 10.38mm I R at MMC at seating plane. 2. Holes in true position within 0.015" • 10.38mm I Rat MMC. CASE MATERIAL: Epoxy coated steel , AC LABEL: Me1alfoil Cjl Z. WEIGHT: 2Ooz. I 257gm.I max. Cjl ~ li ~ 10L 1 -15 mA rnA e; shipped with DAC74: AMP86418-1 20 pin. Pl Test Interlace AMPI-81418-8 34 pin. P2 Digital AMP86418-2 40 pin. P3 Analog M.RON loit DIM /NCHES MIN MAX MIUIMETERS MIN MAX TRANSFER CHARACTERISTICS AFTER SELF-CALIBRATION CYCLE A 8.880 7.020 177.29 178.31 Accuracy(2) Total Error Unipolar Bipolar Linearity Error Gain. Error. Unipolar Bipolar Offset Error, Unipolar Bipolar Monotonicily after Calibration. 16 bits 8 4.NO 5.020 126.4' 127.151 C .1550 .600 13.97 15.24 D .02' .028 .sa .71 ±0.OOI5 ±O.OO15 ±1/2 ±0.OOO35 ±O.OOO35 'IIIofFSR LSB 'III of output 'III of output ±40 ~V H ~V J .353 \ .373 8 .• 7\ 9.47 K .3,*\ .328 7.8.\ 8.33 ±ao Guaranteed DRIFT Total Error Drift (includes gain. offset and linearity drift(4) I Unipolar Bipolar Total Error over Temp Range Voltage. Unipolar IO'C to 70'CI Bipolar Voltage. Unipolar I +15°C to +45°C I Bipolar Gain (exclusive 01 reference drift) Offset cexclusiv8 of reference drift) Unipolar Bipolar Differential Linearity over Temperature linearity Error over Temperature PRECISION 10Y REFERENCES Voltage(S} Drift VB Temperature External Current(6) '11101 FSR(3} ±9.9995 ±4 ±5 ±9 ±11 ppm of FSRfOC ppm of FSR'-C ±2 ±O.06 ±0.06 ±O.013 ±0.013 ±5 'IIIofFSR 'lbofFSR 'IIIofFSR 'lbofFSR ppmfOC ±O.5 ±1 ±2 ±3 ±1 ±1 ±2 ±10.00 ±O.5 ±2 ±10.0005 ±1 +4 6-141 ppm of ppm of ppm of ppm of FSRfOC FSRfOC FSRfOC FSRfOC 1 U--t T PIN: Golo;l Flashed Mating Connectors +2.4 ~ "'.::•.:.,... • 1.112 BASIC 28.24 BASIC F 4.150 BASIC 105.41 BASIC G .100 BASIC 2.MBASIC 2.837 BASIC n.M.ASIC L .tOOBASIC M .'.3 \ .'83 3.63\ 4.6& N .•73 \ .813 ,•.'5\ 15.&7 p .730 \ .770 '8.•• \ ".66 Q .9008ASIC 2.54 BASIC 22.888ASIC R 1.200.ASIC 30.. BASIC S 1.100 BASIC "0••• BASIC T 3.800 BASIC sn."BASIC u 1.800 BASIC ".268ASIC V .020 .040 .5' 1.Q2 W .287 .287 •. 7. 7.29 Y .83' .851 21,11 21.82 Z .430 .470 10.82 11.94 AA .293 .333 7." 8M V A8 .240 .280 8.10 ppmfOC mA AC .585 ." 8.10 '''.3& , • .as . I tZc =¥-tt Z __ e, !"-nUZ' I l MECHANICAL (CONT) ELECTRICAL (CONT) TYP MINI UNITS MAXI Unipolar Bipolar Li'nearity Precision 10V Referenoss ±30 pprri/103 hr ±5 ±30 ±O.25 ±20 ppm of FSR/103 h ppm of FSR/103 h LSB/103 hr ppml103 hr ±O.5 POWER SUPPLY SENSITIVITY Unipolar Offset +15Vand -1SV Supplies +5V Supply Bipolar Offset +15V and -15V Supplies +5V Supply Gain +1SV and -15V Supplies +5V Supply ±O.OOO1 ±O.OOO1 %ofFSR/%Vs %ofFSR/%Vs ±O.OOO4 ±O.OOO1 %ofFSR/%Vs %ofFSRI%Vs ±O.001 ±0.OOO5 %of FSRI%Vs %ofFSR/%Vs . POWER SUPPLY REQUIREMENTS ±15, +5 ±14.5, +4.75 Range Supply Drain, ±15VDC Inot including output load) Current Surge, +15V Supply(7) +5VDC Supply ±15.5, +5.25 V V 200 400 800 mA mA mA ±45 +70 +100 DC DC DC RERANOE Seif-calibration Operation Drift Specification Storage +15 0 -55 TIMINO SPECIFICAnONS ContrOl and Status TiminglS) ton IRes tiN tdo td, tRUN (self-cal model tRUN msec 50 14 ~sec 500 (service mode I . Data Input Timing tENLSB. ENMSB I pulse width tw I lou Idata input setup time I t. Idata input-hold time I "sec IAsec 100 100 2.5 3 sec 300 350 msec IAsee nsec nsec 15 20 10 nsec : . FHSCREW I~-=-_~COVER STABILITY, LONO TERM Gain (exclusive 01 reference J Offset lexlusive 61 reference I ~-32XO.44· 1 DAC74 MODEL ~.. : _ :~KAPTON ADJUSTMENT'J.' POTENTIOMETERS.i. , _-:;(if.!. ~~ _L.:t!i"· : : INSULATOR. ./iSOLDER SIDE ::'A ~'JIIIif*_ : PCB : COMPONENT : SIDE II ..iT': '" : ~ BASE Screws holding the package together s're coVered by the top label I not shown I. if the. package must be opened, the top label must be peeled back at the corners. The package is mounted through inserts in the corners when the connectors are mounted pins-down·or through the two holes in the center of the package when the connectors are mounted pins-up. Manual calibration potentiometers are' located on one end of the package. The potentiometers are accessed by peeling off the label on the edge of the package. NOTES: 1. 1LSB at 16 bits = 0.00152% of FSR, = 15.2ppm of FSR, 152~V unipolar, 304~V bipolar. 2. Self-calibration can operate over +15°C to. +45°C. DAC74 meets these specifications after the calibration cycle. These assume that the ±10V references have been adjusted to ±10.ooooV ±101AV after 3O·minute warm·up. 3. FSR means Full Scale Range and is 20V for bipolar and 10V for unipolar. 4. DAC74 will operate as aO/A converter over to + 700C. Self·callbratlon feature may be out of correctable range over a temperature range wider than +15DC to +45DC . 5. Manually adjustable to +10.00000 and -10.00000 after 30-minute warm-up. 6. Maximum with constant load for no degradation of specificatiops. 7. The heater current of the heated zener reference momentarily causes the initial power-up current of the +15V supply to approach 400mA. The +15V supply current then tapers to less than 200mA within 3 seconds. 8. See Operation section for timing diagrams. acc PIN CONFIGURATION Connector P1 is a special service and test connecto,' used by the factory. P2 is the Digital 110 connector containing the 16 input lines to the D/A converter, the control and status signals, and the +5V supply pins. Connector P3 contains all analog function pins for output. output sense, references. options, analog test paints, and ±15V power supply input. ' The DAC74 is delivered complete with mating connectors for printed Circuit mounting. . 20 21 UNIPOLAR GAIN ,OFFSET DACI • voL. T AGE OUT I OFFSET DAC). UNIPOl.AR CAL UNIPOLAR GAIN TRIM rOFFSET CAC,. OFFSET TRIM ,OFFSET OAC,. UNIPOLAR OFFSET TRIM IOFFSET OAC • • • • BIPOLAR GAIN rOFFSET OAC, -10VREF OUT -F.S, REF ,AI,..~ BITS OFF BIPOl.AR GAIN TRIM IOFFSET DACI +1OVREF IN +10VAEF OUT I. . N/C • • AOCVOLTAGE IN ,TEST, BIPOl.AR GAIN. CURRENT OUTPUT. CAL SENSE • UNIPOLAR GAIN • BIPOLAR OFFSET .pae OAC VOLTAGE OUTPUT BIPOl.AR RTN SENSE • • +F.S, REF IALL BITS ONI UNIPOLAR RTN SENSE. • CMR TRIM RTN • • RTN RTN • • RTN ANALOG COMMON. ANALOG COMMON. +15VIN. -15VN. NlC. N/C. • ANALOG COMMON • ANALOG COMMON ~ +'5VIN • ·-15VIN • +12V TEST • -12V TEST 140 6-142 CONNECTION DIAGRAM - UNIPOLAR 7 UNIPOLAR GAIN DAC YOLTAGE OUTPUT ~ 30 100--+~D,-,1,,-5--..!M"'S"'._--lr .... , AV7 RVI 0 0 ____~ .0--1-~D~1~3_ _ _~ +10V REF 26 D12 8 011 21 DlO 1~: -lOY REF CMRTAIM ENLSB ': D1 RY2 RV3 0 0 014 ~ D. 4 D3 31 02 3 D1 32 013 STATUS OUT { 20 CAL 21 RV40 14 D12 CONTROL { IN RVI 0 RV50 T ~r- r-L-_ GAIN )(, 12 I ___~'F~,S~.R~EF~(~A~LL~.~IT~S~O~FFL)__~'3~-+~ ~-------:CC:A-:-L-:CSEC:CN::-SE::---II-c,-o, 22 UNIPOLAR OFFSET TRIM (OFFSET DACI OFFSET TRIM (OFFSET CAe) +10VREFIN r-- __ _ UNIPOLAR GAIN (OFFSET OAC) VOLTAGE OUT (OFFSET OAC) _ _ _ _ _ _ _ _ _ _-I -" -" "251 26 +10Y REF OUT UNIPOLAR GAIN TRIM (OFFSET DAC ,4 20 19 21 UNIPOLAR CAL " IAQ MPU OFF 13g~~R~U~N~/C~~~~===============1 15 RES 23 KEY T He ~0--+--'-+5VIN 2 ~ ~: I OFFSET 1 33 29 r---~ ~~~=; r- ~:. 22o--+.,·~U~ii' 32 CURRENT OUTPUT r- ==; %r--%:::::: ~: 29 10 BIPOLAR OFFSET r=:: _e- 11 o--+-"",'N=M=S.~_ _ _.l D15MSB RTN RTN RTN RTN 5 e:r-'t= r=:: % DIGITAL INPUT 0 RL Ho--+~D'-'14~ 2B RV1 28 UNIPOLAR ATN SENSE n 8 18 1.&=t:==:::t a ~ ~ -- 31 -~ ~ Q +f.S. REF (ALL BITS ON) '---------'=~~~=~=:f~;t------! 15V + IN 1.-- ~;7 -15YIN L-- LA~ ~ ANALOG COMMON SELF-CALIBRATING D/A CONVERTER >-- DAC74 ~: 35 36 ~ CONNECTION DIAGRAM - BIPOLAR IIPOLAR GAIN 28 DAC YOLTAGE OUTPUT ~ 30 HL 1Do--+~D,-,f5~-,M",S=·_--lr""" AY7 0 ____... 0--+~D,-,1,-3_ _ _--I +lOV REF t-t-'o-I---:'-':,.'------I-~ f:: 2: Ava (2) ~10Y REF 012 011 D 0 11 ENMSI ~ ENLSI 015MSI D1 .. D. ~: ~ 014 D3 31 RV3 0 0 CONTROL IN Ave 0 { f::: 5 r-~ 5..f::_...._~---. r-- ~o-~~~~Sj~~N· __------------------------i CAL 0 GAIN "22 -10V REF OUT CAL SENSE 11 ~---:-:======-~-+-o" OFFSET TRIM (OFFSET DAC) 1-____________~.~'.~V~RE~F~O=U"-T_+'·40 ,y" +10V REF IN ,s ~ ] t==~~a2420 VOLTAGE OUT (OFFSET OAC) 19 21 BIPOLAR GAIN (OFFSET DAC) 18 13~~~R~U~NI~C~A;L:;;==============1 15 RES KEY 23 34 NC +F.S. REF (ALL IITS ONI "r- "8::::l ~ 330-+--. " "1.0--+--' ....:!.. ANALOG COMMON SELF-CALIBRATING D/A CONVERTER DAC74 6-143 J I .... IIPOLAR GAIN TRIM (OffSET DAC) 12 Ava 211 ----~------~,F~,S~,R=E~FI~.=LL~.~IT~S;O~FF~)--_F~~ %I-c-%~ 1C,--~If-:-'T-+5VIN OFFSET 32 , 33 BIPOLAR OFFSET ~'g:~j,~RQ~~==================~ 14 MPUOFF D12 10 '--_ _ _ _ _ _ _--'C'-=U"RR"'E"'N"'T"'OU"'T"-P"'UT'---IHl12 3 D1 »o-+~D~• .-~_1r_~-1 D13 STATUS OUT { RV4 D' r-- RTN RTN RTN RTN - =.'-------I f:: f:: 1 1 r,..L.t-- D' 5 AV20 J: ';o--1--:D 2B OIGITAlINPUT RV1 BIPOLAR RTN SENSE CMRTRIM 25o-+-,D,-,14~ " DESCRIPTION OF PIN FUNCTIONS CONNECTOR P1 Connector P I is a test connector used by the factory. It is not described in this data sheet. CONNECTOR P2 (Digital Signal Connector) ~ Deslgnation ~ +SVI~ +SV supply input. Connected internally to pin 34. DIGITAL COMMON +SV supply return. Connected internally to pins. 12. 16. 17. 18. 19, 33. 3 through 10 01. 1>3. 1>5. 1>7. 1>9. I>II.DI3.DI5 Data input to the Main D, A. DJ5.is the MSB. Logic I is a high II ENMSB Enable forthedata input latches. Controls the MSB byte latch and the 2nd latch in the double-buffered LSD byte. I.cvel triggered on high level. 12 DIGITAl. COMMON +SV supply return. 13 RUNiCAL Control input. Low input for SEl.F·CALI BRATION mode. High input for SERVICE. the manual calibration mode. i~put logic level. RES is asserted. 14 MPU Off Controls roicroprocessor oscillator. l.ow - ON, High - OFF. Must be low for 50msec before 15 iES Control input. Resets the DAC74 controller and subsequently causes the RAM to be cleared and "calibration" or "service" to begin. Input is a logic 0 (low) pulse with 141'sec minimum width. 16.17.18. 19 DIGITAL COMMON +5V supply return. 20 CAL Status Output. Informs the user if calibration failed. l.ogic low means calibration 21 iRQ An internal microprocessor control input. Not used by user. 22 RUN Status Output. This is high during the time the calibration controller has contrul of the main 23 KEY This pin may be used to key the module to protect against incorrect plug-in alignment. 24 ENLSB Enable input for LSD byte latch. Level triggered on high level. 25 through .32 1>14.1>12.010. DB. 06. 04. 02. DO Data input to the main 01 A. DO is the 33 DIGITAl. COMMON +5V supply return. 34 +5V 1s +5V supply input. LS~. succe~sful. n A cunverter. Logic I is high logic level. CONNECTOR P3 (Analog Connector) ~. 1.2 Designation Function NC No connection. ·15V II.; ·15V supply input. Connected internally to pin 38. +15V 1N +15V supply input. 5.6 ANALOG COMMON Return for ±15V supply. Connected internally to pins 35 and 36. Connect~ internally to pin 37. 7.8 RTN Analog return for the analog output. Connected internally to pins 33 and 34. 9 UNIPOLAR RTN SENSE Unipolar Return Sense. Analog load sense for unipolar output configuration. 10 BIPOLAR RTN SENSE Bipolar Return Sense. Analog load sense for bipolar output configuration. II CAL SENSE Calibration Sense. A connection to sense the 0, A output at the load and pro\'ide an input to the error me~surement circuil. 12 CURRENT OUTPUT A connection to the current output of the bit switches. Used to connect Bipolar Offset. pin 29. 13 BIPOLAR GAIN 14 NC Connection to scale the output amplifier for bipolar output range (-I 0 to + IOV) and to provide a sense input from the load. No connection. 15 UNIPOLAR OffSET TRIM (OffSET DAC) Connects an internal trim network to pin 16 for unipolar operation. This network is factory sel. 16 OffSET TRIM (OFfSET DAC) Offset trim input connection to the pedestal offset DI A converter. 17 UNIPOLAR GAIN TRIM (OffSET DAC) Gain trim input connection to the pedestal offset 0,' A converter for unipolar operation. 18 UNIPOLAR CAL A digital option line selecting the software routine calibnuing the main Di A converter for the bipolar or configuration. 19 VOLTAGE OUT (OffSET I>AC) Analog output of the pedestal offset D/ A converter. 20 UNIPOLAR GAIN (OffSET DAC) Connects the pedestal offset D/ A converter forO to +IOV output range. Connect to pin 19. 21 BIPOLAR GAIN (OffSET DAC) Connects the pedestal offset O,_A converter for -IOV to +IOV output range. Connect to pin 19. 22 -IOVltu·QUT -IOV precision reference output. 23 -f.S. REf (ALL BITS Off) .BIPOLAR GAIN Minus Full Scale input to analog switch of error measurement circuit. Connect to pins 7. 8. 33. 34 for unipolar. Connect to pin 22 for bipolar. 24 Gain trim input connection to the pedestal offset 0 1 A converter for bipolar operation. Connect to pin 25. 6-144 unip{~lar 25 +IOV k l:l IN Connection to provide precision +IOV reference to the () A converter I.:ircuih. CUIlIlCCIIO pin 26. 26 +IOV,u,1 OUT +IQV precision reference output. 27 AOC VOLTAGE IN (TEST) The analog output of the difference amplifier in the error measurement ('in;uil. 28 UNIPOLAR GAIN Connection to scale the output amplifier for unipolar output range (0 to +IOV) and load. 29 BIPOLAR OFFSET Connects the bipolar offset current source lathe current output of the main I) A (on\cr!cr to pro\ ilk hipul:t!" 1I11~ct, Connect to pins 7. 8, 33, 34 for unipolar. Connect to pin 12 for bipolar. 30 OAt' VOLTAGE OUTPUT Analog voltage output of the main 0 A converter. 31 +F.S. REF (ALI. BITS ON) Plus Full Scale input to analog switches of the error measurement circuit. Connect 10 pin 25. 32 CRM TRIM Common~mode rejection trim for the output amplifier for bipolar operation only. Connect to pins 7. 8. 33. 34 for unipolar. Connect to pin 12 for bipolar. 33.34 RTN Analog return for the analog output. Also connected internally to pin!! 7 and 8. 35.36 ANALOG COMMON Return for ± 15V supplies. Connected internally to pins 5 and 6. 37 +ISV no + 1SV supply 38 -ISVI!>. ~15V 39 +12V TEST Test pin for internal +12VOC. 40 -12V TEST Test pin for internal ttl prmidc a ~cn~1,! inpullrulll the input. Connected internally to pin 4. supply input. Connected internally to pin 3. ~12VDC. INSTALLATION The three connectors described in the previous section have three separate functions; analog interface. digital interface. and the terminal interface. The terminal interface is used only for factory test. Connection to a printed circuit board can be made using female printed-circuitmounted connectors supplied with the DAC74. They should be positioned relative to the four internallythreaded mounting holes at the corners of the DAC74 as shown in Figure 4. Mount the DAC74 with four #6 external tooth lock washers and four #6-32 screws using 0.156" diameter holes. Be sure to leave clearance for screwdriver adjustment of the trim potentiometers. Alternatively. the DAC74 can be mounted on a chassis With the connectors facing upward using two #6 lock- washers and two #6-32 screws by means of the two internally-threaded holes near the center of the DAC74 as shown in Figure 4. In this orientation. connection to ribbon cable can be made with mass terminated. female. flat cable connectors (3M. 3421-0000. 3414-0000. 34170000). Individual wires may also be connected to the DAC74 in this orientation using female wire-applied connectors (AMP 1-87456-6.3-87456-0.3-87456-6 housings plus appropriate crimp snap-in pins). In either case. the jumpers for the unipolar or the bipolar configuration should be made right at the analog connector P2 as described in the following paragraph. The potential drops due to long jumpers cause a degradation in th\:accuracy of the calibration circuit. 7000- \lri.8Ollllll~ 11.375- 0:313· 17.1IinI1l1f" \l81.11311U11 1-11.112. 128.2411111 4.150" _1105.4111111 -. -$- 2.837(72_1 5.375- \l38.1i3nI1i1 .01lIl111 -$-_(l.32IhrUd \lllrul (2PLI -$- 1r(2~=~1 -. 1··-·20-··-"·:1=~ ..•••......•....•..·1 ·.....·..·1··..·•..·..· ··1 ................... ~.4}1. (1~~~I--I (22 I 1.800· )I-.J '":..0..::;.Ill., /.200· (411.114I11III1 -\311."111 3..... IIIA4IIIII FIGURE 4. DAC74 Package Mounting Hole Locations. 6-145 ,.J=-II!---- - II-32lhrud 0.188- IIln dltllh 14Pll POWER SUPPLY CONNECTIONS A typical configuration is shown in Figure 5. Regardless of the local grounding. bring two separate return lines from the common near the power supplies to the DAC74. Connect one to Digital Common and the otherto Analog Common. The load return line should be connected only to RTN (pins 7. 8.33.34) on P3 as shown in the unipolar and bipolar Connection Diagrams. Other connections to local grounds should be made with caution as they may cause ground loops which induce undesirable voltages at the common return points. The case is tied internally to Analog Common. Normally it should not be connected to any local grounds. Besides the power supply connections. other connections to the DAC74 should be limited to the digital inputs with a single digital current return and the 5-wire connection to the load. The external connections should be made so as to minimize the conduction paths to external noise sources. Internal bypass capacitors are included in the DAC74; no other bypass is needed nor recommended. The power supply voltages may be sequenced on or offin any order provided that the power supply inputs have no transient voltages of polarity opposite to the normal DC input with respect to Analog or'Digital Common. The power supply requirements are listed below. During power-up. an initial surge of 400mA is required by the +15V supply input. . Input Voltage +5V +15V -15V Current, max typ SOOmA 500mA 200mA 150mA 200mA 150mA Precautions I. Provi"n in the Connection Diagrams. For either unipolar or bipolar. it is very important to provide both a current-carrying wire and a sense wire to both sides ofthe load in order to minimize the errors caused by induced potentials and losses in the wiring to the load. The fifth wire, CAL SENSE, returns the output voltage at the load to the error measurement circuit. In a noisy environment these wires should be enclosed in a shield that is connected only to the RTN pins of the DAC74. The return line from the load to the RTN pin of the DAC74 must be separate from other grounds in order to avoid potential drops due to shared current path~. The resistance of this path must be low so that the voltage drop is less than 20",V. For example, at 5mA one foot of 16-guage copper wire (40/ lOOOft.) produces a 20",V drop. TO PIN 13 (BIPOLAR BAlli OR PIN 28/UIIPOLAR BAlNI TO PIN 11 (CAL SENSEI VOLTAGE OUTPUT DIGiTAl COMMON TO PIN 10 (BIPOLAR R1lI SENSEI OR PII'(UNIPOlAR RTI SEIIEI TO PIN 4 +15VOC-------COM TOPIU ·15VOC TO PII I +5VOC ±15VIIC SUPPlY +5VOC SUPPLY COM FIGURE 5. Power Supply and Common Connections. 6-146 Unipolar Connection. The output connections and jumpers are listed below. The pin numbers refer to the analog connector P3. The first five connections constitute the 5-wire connection to the load. Connection Purpose 30 to load (top) DAC VOLTAGE OUTPUT Output connection to the load. 28 to load (top) UNIPOLAR GAIN Output sense to the inverting input of the output amplifier. Sets unipolar range. 7 to load (bottom) RTN Current return from the load. This return impedance must be low - equivalent of 16-gauge wire. 9 to load (bottom) UNIPOLAR RETURN SENSE Return sense to the noninverting input of the output amplifier. II to load (top) CAL SENSE I nput to the error measurement circuit from the load. RTN TO ANALOG COMMON Connect common returns. This jumper is essential to prevent damage to the internal reference. 33 to 6 23 to 34 -F.S. REF (ALL BITS OFF) Set minus full scale to 0 volts. Keep as short as possible. 29 to 34 BIPOLAR OFFSET TO RTN Maintain the same current drain on the +10 volt reference as bipolar connection. 26 to 25 +IOV REF OUT TO +IOV REF IN Keep as short as possible. 15 to 16 UNIPOLAR OFFSET TRIM TO OFFSET TRIM Connect offset trim to offset adjust input of the pedestal offset D; A converter. 17 to 25 UNIPOLAR GAIN TRIM (OFFSET DAC) to + 10 VOLT REF Connect the full scale gain reference of pedestal offset D / A converter. 19 to 20 VOLTAGE OUT (OFFSET DAC) output to UNIPOLAR GAIN (OFFSET PAC) Return sense to inverting input of the pedestal offset D I A converter. 18 to digital common UNIPOLAR CAL to DIGITAL COMMON Set software to unipolar mode. 31 to 25 +F.S. REF to +IOV REF IN. Bipolar Connection. The output connections and jumpers for bipolar operation are listed below. The pin numbers refer to the analog connector P3. The first five connections constitute the 5-wire connection to the load. Connection Purpose 30 to load (top) DAC VOLTAGE OUTPUT Output connection to the load. 13 to load (top) BIPOLAR GAIN Sense to the inverting input of the output amplifier. Sets bipolar range. 7 to load (bottom) RTN Current return from the load. This return impedance must be low - equivalent of I foot 16-guage wire for 5mA output. 10 to load (bottom) BIPOLAR RETURN SENSE Return sense to the noninverting input of the output amplifier. II to load (top) CAL SENSE Input to the error measuring circuit from the load. 32 to 7 CMR to RTN Match the equivalent impedance to RTN for both inputs of output amplifier for the bipolar configuration. 7,8,33,34 RTN Tied together internally. 33 to 6 RTN to ANALOG COMMON Connect common returns. This jumper is essential to prevent damage to the internal references 6-147 Connection 23 to 22 31 to 25 Purpose -F.S. REF (ALL BITS OFF) to -IOV REF OUT Set minus Full Scale to -10 volts. Keep as short as possible. BIPOLAR OFFSET to CURRENT OUTPUT Bipolar offset for output amplifier. +IOV REF OUT to +IOV REF IN Keep as short as possible. OFFSET TRIM (OFFSET DAC) to +IOV REFERENCE IN Connect bipolar offset of the pedestal offset D/ A converter to +IOV REF. BIPOLAR GAIN TRIM (OFFSET DAC) to +IOV REF Connect the Full Scale gain reference of the pedestal offset D / A converter. VOLTAGE OUTPUT (OFFSET DAC) to BIPOLAR GAIN (OFFSET DAC) Return sense to inverting input of the pedestal offset D I A converter. +F.S. REF to +IOV REF IN. Internally Connected Pins. Function DIGITAL COMMON +5V1N ANALOG COMMON +15VIN -15V1N RTN The following pins are connected internally: Pin No. 2,12,16, 17, 18, 19,33 1,34 5,6,35,36 4,37 3,38 7,8,33,34 29 to 12 26 to 25 16 to 25 24 to 25 19 to 21 DIGITAL INPUTS Data inputs DO - DI5 and enable inputs, ENMSB and ENLSB, are low power Schottky (74LS373). Control inputs RES: RUN/CAL and UNIPOLAR CAL are standard TTL inputs. M PUOFF is a standard TTL input with a IOkO pullup resistor connected to +5V volts. Timing specifications on the digital inputs are listed in the Specifications table and discussed in the Operation section. OPERATION DAC74 data inputs, control signals, and status lines are shown in Figure 6. MPUOFF will usually be tied to DIGITAL COMMON permitting the internal crystal ocsillator to run continuously. However, one may wish to control the oscillator to remove all possible sources of noise during D/ A converter operation. MPUOFF must be asserted low 50msec before the RES pulse is asserted. The RES line resets the calibration controller and starts controller operation when it returns high after being asserted low for at least 14!-,sec. RUN/CAL is a mode control line. When high, RUN/CAL enables the controller to set up the SERVICE mode. In this mode, the user performs a coarse m!!!.!!!!1 adjustment of the D/A converter. When RUN/CAL is low, the controller is informed to set up the SELF-CALIBRATION mode, the normal mode of operation. Data input latches are level-triggered by ENSMB and ENLSB. These are used to strobe-in data from an 8-bit bus with DO through D7 connected to 08 through 015 respectively. For 16-bit bus operation ENLSB can be permanently connected to +5V. Since all three latches are octal transparent latches (74LS373), their inputs may be transferred directly· to their outputs by setting their respective enable inputs high. The table below indicates four common interfaces. A high input refers to a logic I input (2V to 3.5V) and a low input refers to a logic 0 input (OV to 0.8V). Mode ENMSB ENLSB Description Transparent High High l6-bit Positive Pulse High Inputs are tra~sferred directly to the MAIN Df A converter. All 16 bits are latched at the end of the Low Positive Pulse interface g·bit interface g·bit interface Positive Pulse ENMSB pulse. Capture 8lSa's from the data bus in low bvte buffer. Transfer 8MSB:s from the data bus and transfer latched 8LSB's to the MAIN D/ A converer at the end of the pulse. The three-state output in the second rank of latches is disabled by RUN, a status output signal, during the time the calibration controller has control of the main 0/ A converter. INITIAL SETUP It is necessary to trim the +IOV and -IOV reference as close to 10V as possible using the potentiometers located at the edge of the module. The procedure is described in Manual Calibration section. 6-148 It should not be necessary to manually adjust OFFSET. GAIN. and LINEARITY on units received from the factory. However. after a year or more of operation it may be necessary to adjust these parameters to within the range which can be trimmed by the self-calibration circuits. The manual adjustment procedure is described in the Manual Calibration section. It is important that either the load be connected or that a dummy load be switched in during calibration or adjustment. Self-Calibration Mode After power-up. a 1/ 2-hour warm-up period must be allowed. This permits the heated zener reference and other critical circuits to stabilize. The next step is to initiate the SELF-CALIBRATION routine. Self-calibration is initiated by providing a pulse (low. 141'sec min) from the host equipment to the RES line. Self-calibration typically takes 2-1/2 seconds. and R'ii"N inform the user on the internal status of the calibration controller. The operation of these is best explained by a timing diagram. Figure 7. Upon application of the reset pulse. CAL goes (or remains) low and goes high about IOOl'sec after RES is returned high. CAL remains high for 500l'sec maximum. If it remains high. self-calibration has failed. If it goes low. self-calibration will be successful. The fact that calibration has failed means that either a noise transient has interferred with system operation or that the maximum correction factors have been used and that the main D j A m converter con not be corrected to within specification. However. the converter will still operate. It will be necessary to perform manual adjustments described in the Manual Calibration section. R UN goes high about lOOl'sec after the RES pulse returns high and remains high until all calibration controller operations are complete and control of the main Dj A converter is returned to the digital data inputs. It is important to be aware oftwo facts during self-calibration: ( I) the main D j A converter is being exercised. its output is moving and changing the voltage on the load; and (2) the three-state output enable of the main Dj A converter input latches is held high by RUN thereby disconnecting the data inputs from the main Df A converter. Service Mode Before one can manually adjust the GAIN. OFFSET and LINEARITY of the DAC74. it must be put in a mode called the SER ~ mode. This is accomplished by ~hing RUN/CAL high and asserting a pulse on the RES line. The result of going into this mode is that all corrections in the RA M are set to zero before control is returned to the user data input lines. does not return The timing is illustrated in Figure 7. low as it did in the SELF-CALIBRATION mode but remains high. RUiii returns low indicating that control has been returned to the data inputs. RUN time is about 300msec. Manual calibration may proceed as described in the Manual Calibration section. m -- 015,.881 '-- I I I al LATCH 741.S373 I I E.... EILII D7 I I J DE -+- LATCH 74lB373 I DO IlSll 1 E. 1Ir E. I 1 I II[ I-- MAl. alA CO.VERTER 1 E. ,.---- LATCH 74lS373 I I '-- RUN/CAL REB .PUOfF ~ :n RU. -- CAl FIGURE 6. DAC74 Inputs. 6-149 I REI I ~----~\ 1~--------------------~-------------- I--:-:-laEB ---l 14~....In ~. I '*' I 1110,.... IYP : /...--------,------.\ i_. '-------' 1 'cAL 1"'1.. - - - - : :51I1 : 1' - - - - - - - - - - - - - - -.----"tl _______________~==~~:: 1Ir---------------------------~: ~I ~~----------lUll -: t - - I .... IYP 1 ... , •_ _- - - - - - : : - I R U I I - - - - - -.....~I 1 311c._ RUIIICAL law .PlNlFF IIw FIGURE 7. Self-Calibration Mode Timing. I REB Y ===-----..\ I : - - - tREB----i I~III. -------: I Ir-------------------------~ iiiii ~~----------------------~--ri ~~I I I RUl/CALhlgh .PUOFFlow I I. i l iI I I~----------~--- I ...... typ IRUI 3&0lIl... mIX : ---_ ..~, FIGURE 8. Service Mode Timing. I .PUOFF I ~~----"""'\~ I~~---------------------------------------------------------------- RES --i ~.•In :-- I I ~------------~\ I 1_ RUltCiL I I ,fJ...'n ---'l-- ':. I !I FIGURE 9. Control Timing Diagram. 6-150 ........ 1 .-l i \I~----------------------- Full Automatic Control If the user wishes to automatically control the total operation of the DAC74 including the SERVICE mode as well as the SELF-CALIBRATION mode. additional timing considerations apply. An additional timing diagram is shown in Figure 8. Note that the M PUOFF must be asserted low 50msec before RES is asserted and the RUN/CAL must be asserted within 500/lsec of the time that the RES pulse returns high. MANUAL CALIBRATION Manual adjustment of the DAC74 is accomplished by eight potentiometers located at one end of the package. Space for screwdriver access must be provided on the mounting surface. A label marked "REFER TO MANUAL BEFORE REMOVING LABEL"must be removed from the end ofthe package to access the potentiometers. Put the DAC74 into the SERVICE mode as descrihed in the Service Mode section. Adjustments will he made in the following order: OFFSET. preliminary GAIN. 4MSB's (I.INEARITY). and final GAIN. Output voltage readings will he different for bipolar and unipolar configurations. Table I shows the data word to be strohed into DAC74. the potentiometer to be adjusted. and the output reading to he attained for unipolar and bipolar configurations. After these adjustments are made, put the DAC74 in the SELF-CALIBRATION mode as described in the SelfCalibration Mode section. The DAC74 is now ready for normal operation. TABLE I. Calibration Voltages. Data Input 10V Reference Adjustment After the DAC74 has been installed. the load connected. and a 1/ 2-hour warm-up period has elapsed. the references may be adjusted. The reference voltages should be set to 10V. ±IO/lV. A 6-1/2 digit voltmeter. which has been calibrated as accurately as possible may be used to adjust the reference and coarse calibrate the D/ A converter. Adjust Poteniometer O/A Out ut Reading Unipolar Bipolar Step Word (hex) 1 2 3 4 5 6 7 0000 0800 1000 2000 4000 8000 OFFSET GAIN O.OOOOV.±50~V -10.0000v.±100~V O.3125V.±50~V -9.3750V.±100~V 012 013 014 015 O.6250V.±50~V -8.7500V.±100~V 1 .2500V.±50~V -7.5OOOV.±100~V 2.5000V.±50~V -5.0000V.±100~V 5.0000V.±50~V O.OOOOV.±100~V FFFF GAIN 9.99985V .±50~V ~9.9997V·.±100~V OPERATIONAL CHECKLIST ADJUSTMENT PROCEDURE I. Connect the voltmeter between the +IOV REF OUT pin (26) and an ANALOG COMMON pin(5. 6. 35.36). Adjust the + IOV REF potentiometer to obtain a reading of 10.OOOOOV. ±IO/lV. 2. Connect the voltmeter to the -IOV REF OUT , pin (22) and adjust the -IOV REF potentiometer to read -IO.OOOOOV, ±IO/lV. Needed for bipolar only. Note: Ifthese reference voltages are to be used to provide references to "ther circuits, those loads must be connected before the above adjustments are made. External reference loads must remain constant for accurate operation of the DAC74. Coarse Calibration of the Main D/A Converter. The self-calibration controller can correct main D/ A errors within a limited range. If the gain, offset or linearity shift due to initial installation environment. such as load return wire voltage drops, power supply voltage line regulation, or component aging, a manual coarse adjustment will be necessary. These six adjustments are made using potentiometers at the edge of the DAC74 package. Coarse adjustments bring the errors of the DAC74 to within the operating range of the self-calibration circuit. It is sufficient to adjust the DAC74 output to within norminal values. ADJUSTMENT PROCEDURE After the DAC74 had been installed. the load connected. a 1/ 2-hour warm-up period has elapsed. and the reference voltages have been set, manual calibration may proceed. I. Be sure that all pins and jumpers are connected properly as discussed and illustrated in the Installation section. Careful layout and shielding is necessary to keep digital noise out of the analog circuits. 2. The load return line from the load to RTN ("pin 7. P3) must have less than 20/lV voltage drop across its length for proper operation. See Installation section. 3. Be sure and wait about 1/ 2-hour for warm-up. 4. Check power supply voltages at the module pins. +15V and -15V. ±0.5V +5V, ±0.25V 5. Check +12V and -12V voltages generated internally. +12V. ±0.6V pin 39. P3 -12V. ±0.6V pin 40. P3 6. Check + IOV and -IOV references. The D, A converter accuracy is directly dependent on these voltages. See Adjustment Procedure in the Manual Calibration section. +IO.OOOOOV, ±IO/lV pin 26. P3 -1O.00000V. ±1O/lV pin 22, P3 7. Check MPUOFF (pin 14. P3) to be sure it is low. It must be low for at least 50msec before attempting self-calibration. 8. Be sure i"lU'i:Nl7I~P;;O~L"'A:-;R~C:-:A~L (pin 18. P3) is high for bipolar operation or low for unipolar operation. 9. ~ pulse must be at least 14/lsec wide. 10. IfCAt status does not return low during an automatic self-calibration. the D/ A converter may be out of tolerance. Adjust it using the procedure in the Manual Calibration section. An unsuccessful self-calibration can result from a voltage or current transient in the 0/ A converter system. Attempt a second selfcalibration. 6-151 BURR-BROWN@ DAC80 IElElI IC DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • WIDE POWER SUPPLY RANGE MODELS AVAILABLE IZ MODELS) Use this popular 12 bit digital-ta-analog converter for low cost precision performance applications. OAC80. with internal reference and optional output amplifier. offers a maximum nonlinearity error of ±0.012%. ±30ppmj"C maximum gain drift, and monotonicity - all over a 0 to 70°C operating range. In the bipolar configuration, total accuracy drift is guaranteed to be less than ±25ppmj"C. Select TTL compatible complementary 12 bit binary (CBI) or. 3 digit BCD (CCO) input codes. Packaged within OAC80's 24 pin dual-in-line ceramic case are fast settling switches and stable. laser trimmed thin-film resistors that let you select output voltage ranges of±2.5, ±5, ±IO, 0 to +5, 0 to +10 volts (V models) or output current ranges of ±lmA or 0 to -2mA (J models). Voltage output models settle to ±0.01% of FSR in 3 microseconds for a 10 volt step change. By specifying the new OAC80Z model with a supply range of ±11.4 to ±16.0volts. you can use this proven 0/ A converter in microprocessor and semiconductor memory systems. • 12·BIT. 3 DIGIT RESOLUTION • ±if2LSB MAXIMUM NONLINEARITY • COMPLETE WITH INTERNAL REFERENCE AND OUTPUT AMPLIFIER IV MODELS) • FAST SETTLING· 300nsec 10 ±.Ol% II MODELS) • CERAMIC DUAL·IN·LlNE PACKAGE • LOW COST Intamlliooll Airport Indualrlll Plrk· P.O. Box 11400· Tucaon. Arizona 85734· Tel. (6021 748·1111 . Twx: 910.952·1111 • Cable: BBRCORP· Telex: 66-6491 @ Burr-Brown Research Corporation 1978 PDS-.322E 6-152 Printed in U.S.A. July. 1978 SPECIFICATIONS ELECTRICAL Typical at 2S"C and rated power supplies unless otherwise noted DACSO-CDI MODEL MIN DACSO-CCD TYP MAX DIGITAL INPUT Resolution Logic Levels (TIL/Compatible)(l) Logici"." (at +4OIlA)m Logic,"O"(at -1.0mA)!.1I MIN TYP MAX UNITS J Digits +5.5 +O.S VDC VDC ±1/4 ±1/2 ±0.3 ±0.15 +70 LSD LSD % Bits 12 +2 0 +5.5 +O.S +2 0 ACCURACY Linearity Error at 2S"C ±1/4 ±1/2 ±O.I ±0.05 Differential Linearity Error Gain Error 4j Offset Error 4 ) Monotonicity Temp. Range, min ±1/2 +1, -3/4 ±O.3 ±O.15 +70 0 ±I/S ±1/4 ±O.I ±O.05 0 % ofFSR(~1 "c DRIFT''' (O"C to + 70"C) Total bipolar drift. max (includes gain, offs~t. and linearity driftsf l Total error over O"C to +70"C IR ) ±25 ±O.OS ±O.06 ±15 Unipolar Bipolar Gain Exclusive of internal reference Unipolar Offset Bipolar Offset Differential Linearity O°C to' +70ue Linearity Error O"C to +70"C CONVERSION SPEED/V models Setlling Time to ±O.OI% of FSR For FSR Change with IOkO Feedback(9) with 5kn Feedback For I LSB Change Slew Rate ±I ±7 ±1/2 10 10 ±2.5, ±5, ±IO, 0 to +5, 0 to +10 ±5 ±5 0.05 Indefinite to Common I I ±I, 0 to-2 4.4 IS ±IO 300 I ~sec ±14, +4.75 ±11.4, +4.75 ~sec ~sec nsec o to+IO Volts mA ohms O,OS ±2,5 ±IO ±0.02 ±O.002 ~A ppm/"C % of FSR/% V, % of FSR/% V, ±15, +S ±12, +5 ±16, +16 ±16, +16 VDC VDC ±3S ±2S +20 ±35 ±30 mA ±30 +70 +S5 +100 ·C ·C ·C ±IS, +5 ±12, +5 ±16, +16 ±16, +16 ±25 +20 +70 +SS +100 -S5 mA kn kn Volts Volts ±200 ±20 ±O.02 ±0.002 0 -25 %ofFSR % of FSR ppm/"C ppm!"C ppm of FSR!"C ppm of FSR/"C LSD LSD V/~sec +6.3 ±200 ±20 ppm of FSR!"C ,.,.sec o to-2 4.4 15 +6.3 POWER SUPPLY SENSITIVITY +15V Supply -IS and +5V Supplies ±O.IS ±0.12 ±30 ±IO ±3 ±IS +1, -7/S ±1/2 5 3 I.S 20 ±2.5 INTERNAL REFERENCE VOLTAGE Max.imum Exter~1 Current1101 Tempco of Drift, max TEMPERATURE RANGE Specification Operating (double above specs) Storage ±I ±7 ±1/2 300 I ANALOG OUTPUT/I models Ranges Output Impedance - Bipolar Output Impedance - Unipolar Compliance POWER SUPPLY REQUIREMENTS DACSO DACSOZ'" Supply Drain ±15/±12V (including 5mA load) +SV (logic supply) ±O.OS ±0.06 ±IS S 3 1.5 20 CONVERSION SPEED/I models - of FSR Settling Time to ±O.OI% For FSR Change 10 to lOon Load Ikn Load ANALOG OUTPUT/V models Rangesl61 Output Current Output Impedance (DC) Short Circuit Duration ±25 ±O.IS ±0.12 ±30 ±IO ±3 ±IS +1, -7/S ±1/2 ±14, +4.75 ±11.4, +4.75 0 -25 -55 rnA TABLE L Electncal S peclficatlOns NOTES: I. Adding external CMOS hex buffers CD 4009A will provide CMOS input compatibility. 2. Logic "'" current = 40JLA max at V IN = +S.OV 3. Logic "0" current = -1.6mA max at V IN = +O.4V, 4. Adjustable to zero with external trim potentiometer. 5. FSR means "Full Scale Range" and is lOY for ±IOY range, JOV for ±SV range, etc. 6. To maintain drift spec internal feedback resistors must be used for current output models. 7. See discussion on page 6·161. 8. With gain and offset errors adjusted to zero at 2S"C, See discussion 011 page 6-162 9. DAC80Z supply range is±12.0V min to±16.0V max forO to+JOV and±IOV. 10. Maximum with no degradation of specifications. 6-153 CONNECTION DIAGRAM CURRENT MODEL VOLTAGE MODEL +Vs 10k!! to 100kH -Vs 10k!! )-~W'v-_< to lOOk!! +Vs -Vs FIGURE 2. External Adjustment and Voltage Supply Connection Diagram, Current Model. FIGURE I. External Adjustment and Voltage Supply Connection Diagram, Voltage Model. NOTES: I. 3kn for CCO models, Skn for CBI models. 2. If connected to +Vs• which is permissible, power dissipation increases 200mW. 3. CSI model. 2kfi; CeD model.On and pin 20 has no internal connection. 4. 6.3k!l resistor internally grounded on ceo models. 5. Resistor required only for Z models, see page 6-156. Make no conneCtion to power supply for regular models. PIN ASSIGNMENTS .. MECHANICAL Pin I Models (MSB) Bit I 2 3 4 5 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit II (LSB) Bit 12 Logic Supply 101"1 Ref. Input Bipolar Offset Scaling Network Scaling Network Scaling Network Common +vs Gain Adjust 6.3Y Ref. Out - I Bit 2 Bit 3 Bit 4 Bit S \0 II 12 13 14 IS 16 17 18 19 20 21 22 23 24 3S.6mm (/.40") -~I.L I Bit I (MSB) Bit Bit Bit Bit Bit ~Vs V Models I I 1- 2O.3mm (0.80")-j r==J .-UUUUUIUHI H 6Imm U . 1-1 ~.2S") 2.S4mm (0.10") I I Slmm (0.20,,) Bit 6 Bit 7 Bit 8 Bit 9 Bit \0 Bit II Bit 12 (LSB) Logic Supply " " 0 0 " 0 0 0 " 0 0 o-r--r- 121.X I ) I OSlmm (0.020,,) dia. 15.2mm (0.60,,) ~4o " " \l" " "" " " ~3 ~ (BOTTOM VIEW) ~Vs VUI'"! CASE: Black Ceramic MATING CONNECTOR: 24SMC PIN: Pin material and plating composition conform to method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2). WEIGHT: 8.4 grams (0.3 oz.) HERMETICITY: Conforms to method Ii1l4 Condition C Step I (tluorO 7.4kO ~tF1.~ . ". + -e= f ~lovRaD8C c: ~t..I ~20VR"" ~ ~ @laEF (Int.) ~~ U < 0 -lic- ~ SCommon ". @)-ISV - IREF @laEP(Ext.) r (iDBit 8 (LSB) @>Bit7 DISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES DRIFT The DAC82 accepts digital inputs in complementary binary (CBI) format and may be connected for complementary straight binary (CSB) or complementary offset binary (COB) operation. By using one external inverter, the user can operate the DAC82 in the complementary two's complement (CTC) mode. DIGITAL INPUT CODES OUTPUT RANGE VOLTAGE' o to +IOV ±IOV OOOOOODO o1 1 1 1 1 1 1 10000000 1 1 1 1 1 1 1 1 +9.961 V +5.000V +4.961 V O.OOOV one LSB 39.06mV +9.922V O.OOOV ·78.12mV ·IO.OOOV 78.12mV MSB GAIN DRIFT GAIN DRIFT is a measure of the change in the analog output over temperature expressed in parts per million per °C (ppmtc). The GAIN DRIFT is determined by testing the end point differences at the high and low temperature extremes and at 25°C for each mOdel, calculating the GAIN ERROR with respect to the 25°C value, and dividing by the temperature change. OFFSET DRIFT CURRENT OFFSET DRIFT' is a measure of the actual change in output voltage at zero volts output over the specified temperature range. The offset voltage is measured at the temperature extremes, and the maximum change referenced to 25°C is divided by the temperature range. This drift is expressed in parts per million of full scale range per °C (ppm of FSRtc). Oto 1.6mA ±0.8mA LSB .().794mA O.OOOmA ·1.594mA -0.800mA .().792mA O.OOOmA +O.800mA 6.248~A 6.248~A +6.248~A • To obtain values for other binary (CDI) ranges: SETTLING TIME o to +SV range: divide 0 to + IOV range values by 2. ±5V range: divide ±IOV range values by 2 ±2.SV range: divide ±IOV range values by 4. Settling time is the time required for the output to enter and remain in an error band equal to ±0.2% offull scale range measured from the time the digital input is changed. Typical settling time values for full scale changes are a function of the load resistor and are shown in the figure below. TABLE I. Digital Input and Analog Output Relationship. 300ns ACCURACY -"'" LINEARITY 200ns The LINEARITY of a D / A converter is the true measure of its performance. The DAC82 analog output will not vary by more than ±1/2 LSB from an ideal straight line drawn between the end points (alll's and all O's) over the specified temperature range. - JII'~ lOOns loon Ikn lOW load Resistor 100kn DIFFERENTIAL LINEARITY FIGURE I. Settling Time for FSR Change vs Load. The DIFFERENTIAL LINEARITY error of a D / A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A DIFFERENTIAL .LINEARITY error specification of ±1/2 LSB means that the output voltage can change anywhere from 1/2 LSB to 3/2 LSB when the input changes from one adjacent digital state to the next. COMPLIANCE The COMPLIANCE VOLTAGE of th. DAC82 is the maximum voltage swing allowed on the current output in order to maintain the specified accuracy. It is -4.0 to +4.0 volts for the unipolar and bipolar current ranges. 6-165 POWER SUPPLY SENSITIVITY .1 ,/ .06 .04 +ISV Supply ...... ~ POWER SUPPLY SENSITIVITY is a measure of the effect of a power supply voltage change on the D / A converter ~utput. It is defined as a percent of FSR/percent of change in either the +15 volt or.-15 volt power supplies about the nominal power supply voltages. Figure 2 shows Power Supply Rejection vs Frequency. ~ 1 > §- .s "' u " 1!' ff!.fi .02 ~ .01 / / ./ / .006 .004 ./ / 'Q'Q ~ .002 " -ISVSrPIY .001 10 100 Ik 10k Power Supply Ripple Frequency (Hz) I lOOk FIGURE 2. Power Supply Rejection vs. Power Supply Ripple Frequem;y. OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS }-~~ DECOUPLING DACS2 For best performance and noise rejection, power supply decoupling capacitors should be connected as shown in Figure 3. These capacitors should be located dose to the DAC82 and should be tantalum or electrolytic types bypassed with a 0.01 ~F ceramic. capacitor for best high frequency performance. }-~~ }-_~ '--_ _ _.J...- _ _ _ _ TO +ISVDC Supply _ _ _ _ (:ommon _ _ _ _ To-ISVDC Supply· FIGURE 3. Recommended Power Supply Decoupling. OPERATION IN THE CURRENT OUTPUT MODE On the. current output pin, the DAC82 provides a unipolar output current of 0 to -1.6mA and a bipolar output current of ±O.8.mA. Refer to Figure 4 and Table II , for prQper connections. In appliqations requiring the use of the DAC82 in the current output mode, such as an A / D converter, the internal scaling resistors should be used to generate currents corresponding to analog input voltages. OUTPUT RANGE CONNECT PIN 1 TO: o to -1.6mA N.C. :±1l.SmA Pin IS TABLE II. Connections for Current Output Mode. FIGURE 4. Current Output Mode Connection Diagram 6-166 DRIVING AN EXTERNAL OP AMP UNIPOLAR OR BIPOLAR UP TO 20V OUTPUT RANGE The DAC82 .will drive the summing junction of an op amp (the op amp being used as a current to voltage converter) to produce an output voltage (see Figure 5). VOUT = -lOUT X RF where louT is the DAC82 output current and RF is the feedback resistor. The internal feedback resistors should be used to maintain the temperature drift specification. Refer to Table III and Figure 5 for proper connections. OUTPUT RANGE DIGITAL INPUT CODES CONNECT @TO CONNECT PIN ITO CONNECT PIN 16TO ±10V COB orCTC 16 18 ® ±5V COB orCTC 17 18 N.C. ±2.5V COB orCTC 17 18 18 Olo+IOV CSB 17 Common N.C. 010 +5V CSB 17 Common 18 V OUT FIGURE 5. External Op Amp - Using Internal Feedback Resistors. REF InpU;.:I~L..~rL-_ _"';"'_ _-.. TABLE III. Voltage Ranges of Current Output DAC82 with External Op Amp. OUTPUTS LARGER THAN 20 VOLT RANGE VOUT For output voltage ranges larger than ±10 volts, a high voltage op amp may be employed with an external feedback resistor. Use lOUT values of±o.8mA for bipolar voltage ranges, and 0 to -1.6mA for unipolar voltage ranges (see Figure 6). Use protection diodes when a high voltage op amp is used. FIGURE 6. External Op Amp - Using External Feedback Resistors. VOLTAGE OUTPUT OPERATION USING INTERNAL AMPLIFIER integral part of the DAC. Connections for DAC82 output voltage ranges are shown in Table IV and Figure 7 below. The DAC82 contains internal scaling resistors to provide a wide range of output voltage ranges. These resistors may be connected to provide 3 bipolar output ranges of ±1O, ±S, or ±2.5 volts or two unipolar output voltage ranges of 0 to +5 or 0 to + I0 volts. Gain and offset drift errors are minimized since these scaling resistors are an CONNECT PIN 16TO OUTPUT RANGE DIGITAL INPUT CODES CONNECT PIN 2 TO CONNECT PIN ITO ±IDV COB orCTC 16 18 2 ±5V COB orCTC 17 18 N.C. ±2.5V COB orCTC 17 18 18 Olo+lOV CSB 17 Common N.C. 010 +5V CSB 17 Common 18 V OUT TABLE IV. Voltage Ranges of Current Output DAC82 with External Op Amp. FIGURE 7. Voltage Output Using Internal Amplifier. 6-167 OPERATION AS MULTIPLYING DAC By using an external voltage reference, the DAC82 can be connected as a multiplying DAC, such that the analog output represents the product of the digital input and the analog reference input. To operate the DAC82 as a two quadrant MDAC, coimect the unit as shown in Figure 8. If R2, the bipolar offset resistor, is replaced with an open circuit, the DAC will operate in one quadrant. Table V below shows the digital input and analog output DIGITAL INPUT CODES MSB LSD oooooooo 0111111 10000000 11111111 I LSD relationships for one quadrant and two quadrant multiplication and Figure 8 shows the connection for output voltage or output current. Since the absolute temperature coefficient of the internal feedback resistors (6.25k) is typically 30 ppm("C, improved temperature stability can be achieved by using an external 13.5k resistor connected between pins 2 and pins IS, making no connection to pins 16 or 17. R2 (Bipolar operation only) OUTPUT RANGE CURRENT VOLTAGE' o to +IOV o to ·J.6mA ±IOV (4 V.)(R,)(O 9961) (4 V.)(Rd (R,) ~(0.9922) . (4 V.)(Rd(O.sOOO) (4 V.)(R,) ~(0.4961) 0.0000 (4 v.) ~0.9961) "('R,)(0.9922) (R,) (4 V.)(O.SOOO) 0.0000 (R,) ±O.8mA (R,) 0.0000 (4V.) (4 V.)(R,) (4 V')(0.4961) (R,)'(.().0078) (R;)<.().0078) (R,) (4 V.)(R,) 0.0000 ~('I) VmrT (4 v.) (R,)'(.I) ~ (4 v.)(R'100039) (4 V.)(R')(0.0078) (4 V.,(O 0039) (R,) 0.0078) (R,) . (R,) , (R,) " TABLE V. Digital Input and Analog Output Relationship for Multiplying C;onfiguration. FIGURE S. Connection for MUltiplying Mode. OPTIONAL EXTERNAL OFFSET AND GAIN ADJUSTMENTS The DACS2 has been laser trimmed atthefactory to insure absolute accuracy of I LSB at +25°C. However, externally connected offset and gain potentiometers may be used to null these error components to zero. If these adjustments are not used, simply leave the pins open. Adjustment networks should be located physically closed to the DACS2 to minimize signal pickup. OFFSET ADJUSTMENT Range of adjustment: ±O.2% of FSR For unipolar operation, apply the digital input code that should give zero volts output and adjust the OFFSET, potentiometer for zero volts output. For bipolar operation, apply the digital input code that should give the maximum negative voltage output. Example: If the FULL SCALE RANGE is connected for 20 volts, then the maximum negative voltage output is -10 volts. See Table I for corresponding codes. • I LSBr ~ ~ o' Offset Adj ISO kO 180 ui CW L :::~i~:tes t ·15VDC "'''' .... , 1?' -:- ~ All bits "'-' Logic I A. ~ ~. 7J" 1 ~ 0 Offset Adj. .... , ~'" ~ ~ 100 kO Alternate Ih . " ~ -'l3~'#'.O--C-CtW--< I~~~DC ",. ~ = !l RanOffset if_l'_in_I_8_ _ _ ......L 1 +FuU Scale ~T Range of Gain Adj. Gam Adj. rotates the hne ,J I All bits Logic 0 ~+-+-+-+-+-+il+-+-+-+-+-~ Digital Inp~t networkfor~ 3.9 MO resistor: 10 kO FIGURE 9. Relationship of OFFSET and GAIN Adjustments for a UNIPOLAR D / A Converter. 6-168 GAIN ADJUSTMENT Range of Offset Adjustment: ±o.2%ofFSR For either unipolar or bipolar D J A converters, apply the digital input that should give the maximum positive voltage output. Adjust the GAIN potentiometer for this positive full scale voltage. The positive full scale voltages for the DAC82 are given in Table Y. Pin 12 Gain Adj. Common 33 MO CCtW to _ 7 -ISVDC ~ .001 ~F c..Y"" ~ T Bipolar V Offset ~ rotales .~ '"~ 'All Bits ~~:t'''' MSB f/ I'L = 0 all othen = I f.'P 0""; Ad'/ Offset AdJ - 1 . - 270 kO T;:;~::~esT network for ~ 33 MO resistor. , {/ '~~~~~~~~4~1'/~~~'_h'~line " .. ",of 270 kO " .. ",of ~ ,(~~ ~,/ ;.)fGain Adj. ,4.11 Bits LOlLic I Pin 14 Alternate '" T~- +F""S"'~'lTj 100 kO CW to .01 JolF ~ itJSk~C Q.....------N.r.,.---I-.... I'..l- I LSO -= 3.9 kn Logic 0 Offset ~ -Full Scale DiJitallnput FIGURE 10. Relationship of OFFSET and GAIN Adjustments for a BIPOLAR DJ A Converter. APPLICATIONS Two DAC82's can be connected as shown to construct a digitally-controlled attenuator which will accept bipolar input voltages. Since the input to the DAC is a summing junction (pin 12), input voltages greater than ± I OY can be used if RIN is increased proportionately. The transfer function is: YOUT YIN = ( 4 RFB.\(ABINAR') RIN } 256 To remove initial gain errors, the two 15k resistors should be adjusted such that 0.2 rnA flows into pin 12 of each DAC82 when YIN = O. R'N (SOk) ~""" 12 • ISk~ 16h ~ 2 DAC82 VIN ABlfIIlY R'N 2S6 Vot"r=4(-) ( - - ) RFB O.2mA _I 18f----4 - S 6 7 8 9 10 II MSB_ ;: A { -'" '" R.. ,.. LSB_ . V,0.2mA • ISk..c 4 5 6 7 8 9 10 ' - - - 12 Adjust for O.2mA II 161-----< 2f--DAC82 bias into pin 12 of each DAC with zero volts input. DIGITALLY CONTROLLED ATTENUATOR WITH BIPOLAR INPUT 6-169 BURR-BROWN® DAC85 IElElI Hybrid Microcircuit DIGITAL-TO-ANALOG CONVERTER FEATURES - 12-BIT RESOLUTION -LASER-TRIMMEO TO ±112LSB LINEARITY -CURRENT OR VOLTAGE OUTPUT - FAST SETTLING - 300nsec to t.Ol % (Current Output Model) - HERMETIC DUAL-IN-LiNE PACKAGE -LOW COST DESCRIPTION The DAC85 12-bit D I A converter offers quality performance usually found in larger modular units. Housed in a 24-pin dual-in-line metal case, this D I A converter is complete with internal reference and output amplifier and is engineered to preserve the performance normally found only in much larger, higher cost modular units, while providing sealed protection from rugged environments. Highly stable laser-trimmed thin-film resistors and our Model 4550 quad current switches provide low nonlinearities of ±0.012% over O°C to 70°C (DAC85C) and ±o.012% over -25°C to +85°C (DAC85 and DAC85LD) operating temperature ranges. Current output models settle to ±O.O I% in 300nsec while voltage output models settle to ±O.O I % in 5JLsec, permitting throughput rates as high as 3MHz for full scale range changes. The small size of the DAC85 makes it an ideal choice as the heart of your AID converter design or for applications where space or weight is at a premium, such as CRT displays, aircraft instrumentation and portable instruments. The wide choice of performance models allows you to choose the right unit for your application and budget. International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 746·1111 . Twx: 910-852-1111 . Cable: BBRCORp· Telex: 66-64!Il PDS·300D 6-170 SPECI FICATIONS Typical at 25°C and rated power supplies unless otherwise noted. MECHANICAL Units TrL - - 35.6mm~20.3mm:::-i 5.6mm ~ (1.40") ) (0. 80 T~ -r 12 ~~0.46mm di.. (0.02") tl/2 tl/2 .Ranle for 5.1mm (0.20") 2.5mm (0.10") 1----,--------+--"--....;.;--1 (BOTTOM - - - - t - VIEW) Gain DoC to +700 C (max) -25°C to +8S o C (max) :!:20 t20 >20 Offset Unipolar DoC to +700 C -25°C to +8SoC tiD tlO " Bipolar tS ppm/OC ppm/DC ppm of FSR/oC ppm of FSR/oC D/ACONVERTER ppm of FSR/oC ppm of FSR!"C (TOP VIEW) DAC85-CBI-V Voltage Models Settling time to to.OI% of FSR for FSR chaRle with 10 k51 Feedback with 5 kn Feedback for I LSB chanle Slew Rate Current Models SettliRa time to to.Ol% of FSR for FSR chenle 10 to lOOn load 1 k5l load 5 3 I.S 20 _c V/JJHc CASE: Kovar, Gold or Nickel Plated MATING CONNECTOR 245MC PIN: Pin material and plating composition conform to method 2003 (solderabilitv) of MI L·STD·883 (except paragraph 3.2) WEIGHT: 8.4 grams (0.3 oz,) v CONNECTION DIAGRAM ~ ..c ~sec 300 ANALOG O.uTPUT Voltage Models Ranges -·CRI Units CCD Units Output Current (min) Output Impedance (de) Current Models Ranges Output Impedance - Bipolar Unipolar Compliance Internal Reference Voltal.' (V r) Max. External Current(6) t2.S, H. tiD. +5. +10 +10 ±S or Drift V rnA 0.05 n tl. -2 rnA 4.4 IS U.S 6.3 200 kn kn (VOLTAGE MODELS) (MSB) Bit I V V 3 Gain Adjust ~A Bit 3 +15 Vdc Bit 4 1 Common Bit s Summing luetion V V Bit 6 mA Hit 7 10V Rang o to +70 Bit 8 -25 to +85 -S5 to +100 ~?f~!~r Bit 9 Bit 10 I. loJic ". "current 2. Logic "0" current 6.3V Ref. Out 9 20V Range Ref. Input 5 Voltage Output = 40pA max at VIN ::; +S.OV = ~1.6mA max at VIN = +O.4V 3. Adjustable to zero with external trim potentiometer. 4. FSR means"fullscaleranae"and i.lOV for±IOV range. IOV for±SV range etc. S. To maintain drift spec internal feedback resistors must be used for current +5 Vdc Bit 12 (LSB) Note t: Amplifier not included in current output models. Note 2: 3 kn for CeD models 5 kn for CBI models output models. 6. With no degradation of specifications. 7. Operating losic supply at +1!Ii.!liV increases power dissipation 2OOmW. 6-171 DISCUSSION OF SP'ECI FICATIONS OFFSET DRIFT OFFSET DRIFT is a measure of the actual change in the output with all bits OFF (vg~~)over the specified temperature range. vg~i is me,asured at -25°C or DoC, +25 0C and +70 0C or +85 0C. The maximum change in OFFSET is referenced to the OFFSET at 25°C divided by the temperature range. TWs drift is expressed in parts per million of full scale range per °C. (ppm of FSR/OC). DIGITAL ,NPUT CODES The DAC85 accepts complementary digital input codes in either binary (CBI) or decimal (CCD) format. The CBI model may be user connected for anyone 'of three complementary binary codes: CSB, CTC, or COB_ 1>IGITALINPUT MSB I.SB i OOOOOOOOOOOO e;; DIIIIIIIIIII 100000000000 ~ " ~ ~ E 111111111111 ANALOG OUTPUT CSR COB CTC" Compl. Compl. Compl. Straight Orrset Two's Binary Binary Compl. +Full Scale +Full Scale -LSB +112 Full Scale Zero -Full Scale -ILSB +Full Scale Mid Sca~ -I I.SB Zero -Full Scale SETTLING TIME The settling time for each model DAC85 is the total time (including slew time) for the output to settle to witWn an error band about its final value after a change in the input. VOLTAGE OUTPUT MODELS Three settling times are specified to ±O.O I % of full scale range (FSR); two for maximum full scale range changes of 20V and 10V and also for a I LSB change. The I LSB change is measured at the major carry (Dill ... 11 to 1000 ... 00) since this is the point where the worst case settling time occurs. Zero CCD MSB LSB 0110 OI1D DIID 1111 1111 1111 • Invert lhe MSB ere code. Complementary Coded Decimal - 3 Digits + uu ~cae Zero or the COB code with an external invener to obtain TABLE I. Digital Input Codes. CURRENT OUTPUT MODELS Two settling times are specified for current output models; each specified settling time to ±0.01 % of FSR is given for the DAC85 current models connected with two different resistive loads - i.e., 10 to 100 ohms and 1000 to 1875 ohms. Internal resistors are provided for connecting nominal load resistances of approximately 1000 ohms to 1800 ohms for output voltage ranges of ±I volt and 0 to-2 volts. (See Table 4) ACCURACY LINEARITY The linearity of a 0/ A converter is the true measure of its performance. The linearity error of the DAC85 and DAC85C is specified over the entire specification. temperature ranges. The definition of this specification means that the analog output will not vary by more than ±1/2LSB from an ideal straight line drawn between the end points (all bits ON and all bits OFF) over the specified operating temperature range. COMPLIANCE The compliance voltage of the DAC85 is the maximum voltage swing allowed on the current output mode in order to maintain the specified accuracy; it is ±2.S volts for the bipolar current range of ±1.0 mA and is -2.5 volts for the unipolar current range of 0 to -2 mAo The maximum safe 'voltage swing allowed with no damage to the DAC85 output is ±S volts for current output models. DIFFERENTIAL LINEARITY Differential linearity error of a 0/ A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±1/2 LSB means that the output voltage can change anywhere from 1/2 LSB to 3/2 LSB when the input changes from one adjacent input state to the next. 0.11--+--+-+""'"-+---1------1 DRIFT .D3 I--~k--'H-+-'k--I------I GAIN DRIFT GAIN DRIFT is a measure of the change in the full scale range analog output over temperature expressed in parts per million per °c (ppm/oC). The GAIN DRIFT is determined by testing the end pOint differences at-250C or DoC, +25 0 C and +70 0C or +SSoC for each model and calculating the GAIN ERROR with respect to the 25°C value and dividing by the temperature change. This specification is expressed in ppm/oC. .003 .001,L,-_ _ _+--::!I"--3I"-:~-...3~_:_!. 0.1 10 100 Settling Time (,.sec) FIGURE 1. Full Scale Range Settling Time vs. Accuracy. 6-172 POWER SUPPLY SENSITIVITY .1 lI'", .06 to. .04 " iii 0> .02 ~ ~ .o! .006 .004 j 0.0. POWER SUPPLY SENSITIVITY is a measure of the effect of a power supply voltage change on the 0/ A con· verter output. It is defined as a percent of FSR per percent of change in either the + 15 volt or -15 volt and +5 power supplies about the nominal power supply voltages. Figure 2 shows Power Supply rejection vs. frequency. ~c "'.- g:; ... .c .001 L ~ ./ .......- OU .002 ~:o +ISV Supply I 10 1"'0 -15V Supply + 5V Supply I 100 10k Ik Power Supply Ripple Frequency (Hz) _ ....... lOOk FIGURE 2. Power Supply Rejection vs. Power Supply Ripple Frequency. REFERENCE SUPPLY All OAC85 models are supplied with an internal 6.3 volt reference voltage supply. This reference voltage (pin 24) has a tolerance of ±5%, and must be connected to the Reference Input (pin 16) for specified operation. This reference may also be used externally, but the current drain is limited to 200 !LA. An external buffer amplifier is recommended ifthe OAC85 internal reference will be externally used in order to provide a constant load to the reference supply output. ORDERING INFORMATION DAC85 xx - ____~~=-T 12-Bit O/A Converter Family Example: OAC85-CBI·V OAC85 with voltage output, Binary code and -25 0 C to +85OC temp. range. C = 0 to +70OC Model LO = Low drift -25 0 C to +85 0 C Model Leave blank for-25 0 C to +85 0 C Model XXX"- ------..0:=-._ X ~ INPUT COOE OUTPUT CBI = Complementary V = Voltage I 2-bit binary I = Current CCO = Complementary (not available 3-digit BCD (not available for LD model) for DAC85LD OPERATING INSTRUCTIONS DIGITAL INPUT AND ANALOG OUTPUT RELATIONSHIP Output Range Digital Input Codes Voltage * Oto+10V ±10V Current Oto-2mA ±1mA Binary (CBI) 12 bit resolution +2.44mV 4.88mV One LSB 0.488/lA 0.488 "A +9.9976V +9.99SIV -1.9995mA -0.9995mA All bils ON All biisOFF -IO.OOOV Zero Zero +1.0000mA Decimal (CCD) 3 digit resolution One LSB IOmV + FS bils ON +9.99 V t All bits OFF Zero N/A 1.25 "A -t.249mA POWER SUPPLY CONNECTIONS DECOUPLING For best performance and noise rejection, power supply decoupling capacitors should be connected as shown in Figure 3. These capacitors should be located close to the OAC85 and should be tantalum or electrolytic types by· passed with a O.Ol!LF ceramic capacitor for best high fre· quency performance. r----------~2~421:nl~e~rn~a~IR~e:f~er~e:nc~e~ Connect to Pin 16 J - _ , . . . : - - - - - _ T o +15 Vdc Supply N/A Zero ...._ ..._ _• )-~ Common DAC85 TABLF 2. Ideal Output Voltage and Current. -15 Vdc }:.;.....- ....1'----~ ToSupply tNormal full scale range with correct codes;,output can go to +12 volts if illegal codes are applied. "To obtain values for other binary (CBI) ranges: ~~ o to +5V range: divide __-t____ ~To+SV Supply 0 to +lOV range values by 2. ±5V range: dMde ±IOV range values by 2. ±2.5V range: divide ±IOV range values by 4. FIGURE 3. Recommended Power Supply Oecoupling. 6-173 EXTERNAL OFFSET and GAIN ADJUSTMENT OffSet and gain may be trimmed externally by the user with externally connected OFFSET and GAIN potentiometers. If gain and offset adjust circuits are not used, pins 15, 20, and 23 should be connected as described in other sections herein. (Do not ground.) Connection of the potentiometers and the methods of adjutments is as outlined below. Potentiometer resistance values indicated are range of values. Potentiometers should have TCR of IOOppmtC or less. The 3.9MO and 18MO resistors can be 20% carbon composition or better. These two resistors should be located close to the DAC85 to prevent signal pickup. OFFSET ADJUSTMENT GAIN ADJUSTMENT For unipolar (CSB, CCD) Df A converters, apply the digital input code that should give zero volts output and adjust the OFFSET potentiometer for zero volts output. For bipolar (COB, CTC) Df A converters, apply the digital, input code that should give the maximum negative voltage output. Example: If the FULL SCALE RANGE is connected for 20 volts, then the maximum negative voltage output is -I 0 volts. See Table 2 for corresponding codes. For either unipolar or bipolar Df A converters, apply the digital input that should give the maximum positive voltage output. Adjust the GAIN potentiometer for this positive full scale voltage. The positive full scale voltages for the DAC85 are given in Table 2. +15 Ydc A~ n~~~~~-"'3""'.9"M'n"""--+-""'--< ~Ol~ 18Mn 2J07·0~0jJ.F +15 Vdc 10 kn (~~ ~~ ~~~ y~d~~!S' Offset 10 kn to 100 kn -IS Vdc Gain Common :go kn Range of Adjustment: ±O.3% of FSR -15 Vdc Range of Offset Adjustment: ±Q2%ofFSR AB"'" OFF "'t-++-g.++++'~'"it+-+-t "'-.. Anbl'l ON Gain Adj. 0_ rotates the line All hits ON ~I-I-+-+--+I~++-I-il T,.lUbt.. tbeOne Digital Input Dlptallnput FIGURE 5. Relationship of OFFSET and GAIN Adjustments for a BIPOLAR Df A Converter. FIGURE 4. Relationship of OFFSET and GAIN Adjustments ' for a UNIPOLAR Df A Converter. VOLTAGE OUTPUT MODELS OUTPUT RANGE CltNNECTIONS volts. Since these internal scaling resistors are an integral part of the DAC85, gain and' offset drift is minimized. Connections for DAC85 output voltage ranges are shown , in Table 3. Internal scaling resistors are provided in the DAC85 to provide a wide range of output voltage range connections. These internal resistors may be connected to provide three bipolar output voltage ranges of ±IO, ±5 or ±2.5 volts or two unipolar output voltage ranges of 0 to +5 or 0 to + IO To Reference 16 Ref. Input Settling time for these voltage ranges is specified for a full scale range change, and is 5 microseconds for 8 kU or 10 kU and 3 microseconds for a 5 kU feedback resistor. 6.3 ill 17 Control Ckt. From Weighted Resistor - Network Output Range ()21 ~Com 18 5 kn (CBI) ':' 19 3ill'(CCD) IS Output fIGURE 6. Output Amplifier Voltage Range Scaling Circuit. "'pin .7 not connected for CeD models. The 6.3 kn resistor is internally connected to common. 6-174 Digital Connect Connect Connect Connect Input Codes Pin 15 to Pin 17 to Pin 19 to Pin 16 to ±to COBorCTC 19 20 15 24 ±5 COB orCTC 18 20 N.C. 24 ±2.5V COB or CTC 18 20 20 24 o to +lOV CSB 18 21 N.C. 24 Oto+5Y CSB 18 21 20 24 o to +lOY CCD 19 N.C. IS 24 TABLE 3. Output Voltage Range Connections - Voltage Model DAC85. CURRENT OUTPUT MODELS Internal resistors are provided either for scaling an external op amp to the same voltage ranges as the voltage model DACS5 or for configuring a resistive load to provide two output voltage ranges of ± I volt or 0 to -2 volts. These internal resistors (RU) are an integral part of the DACS5 design, and are required to maintain the gain and bipolar offset drift specifications of the DACS5. If the internal resistors are not used, external RL or RF resistors should have ±25 ppm/oC or less temperature coefficient to minimize drift. C Ref. In 16 The current model DACS5 equivalent output circuit and resistive scaling network is different from the voltage model DACS5, and is shown in Figure 7 and S for reference. Instructions for using the DACS5-xxx-I with either a resistive load or an external op amp are on the following pages. External RLS or RLP resistors are required to give exactly o to -2V or ± I V output range. These resistors should have a TCRof±100 ppm/oC or less. If these exact output ranges are not required, RLS (or RLP) need no'. be used as discussed below. Torer.controlckt. -------017 OI---4--~W..... 6.3kn IS Q---..--'lM,-----~-~M~-___{:) 19 ' -_ _ _ _ _ 6.3kU ~20 Internally >---e-----Jo"N.....------,:f:ed 10 Common JkU ":" I s Q -......-----IIM.----·----O 19 020N.C. Skn o (B) DAC85-CCD-! IS 17N.C. FIGURE 7. Internal Scaling Resistors. FIGURE S. DAC85 Current Model Equivalent Output Circuit. Voltag. Output Using Resistiv. Load UNIPOLAR BINARY INPUT CODE (eSB) A load resistance RL connected to the output as shown in Figure 9, will generate a voltage range, VOUT, determined by: Vour =-2 rnA (15kXRL) IS k + RL where RL max = 1.36 kn and Vour max = -2.s volts FIGURE 9. Equivalent Circuit DAC85-CBI-I connected for Unipolar Voltage Output with Resistive Load. For minimum drift as specitled, the internal scaling resistor (RU) should be connected as shown in Table 4 for the CSB code with a series connected external me.tal film full scale trim resistor (RLS) to provide a full scale output voltage range of 0 to -2 volts. With RLS = 0, VOUT = -1.82V. '""_ _ Internal Resistance RU CSB o to-2V 0.968 k!l. 105 !l. CCD o to-2V 1.875 k!l. N/A COB or CTC ±lV 1.2k!l. 1% Metal Film External Resistor RLS RLP 90.9 !l. N/A 36.5 k!l. N/A Connect Pin 15to \ ~ t:~ '~'"t • Oto Connect the internal scaling resistors as shown in Table 4, and add an external parallel connected metal film resistor (RLP) as shown in Figure 10 to obtain a 0 to-2 volt full scale output voltage range for CCD input codes. With RLP = "", VOUT = -2.0SV. Output Voltage Range ",ro'~ by digital input lleD INPUT CODE (CeO) Input Code V OUT RI.s Ru 1.2SmA + RI., Vour 21 '-Com FIGURE 10. DAC85-CCD-I Connected for Voltage Output with Resistive Load. RU Connections Connect Connect Pin 18 to Pin 20 to Reference Connect Connect Pin 16 to Pin 17 to 20 19 & R LS 15 24 21 (Com) 19 21 (Com) N.C. 24 N.C. 18 19 R LS 24 IS Bipolar Offset RLS Between pin 18 & 21 N/A Between pin 20 & 21 TABLE 4. DACS5X - XXX - I Resistiye Load Connections. 6-175 RLP N/A Between pin IS & 21 N/A BIPOLAR COB and eTC INPUT CODES The equivalent output circuit for a bipolar output voltage range is shown in Figure II. VOUT is determined by: Vour =±I mAx ( RLX4.44k) . RL + 4.44k \r Current controlled by digital input + where RL max = 5.72 kn VOUT max = ±2.5 volts ±lmA For minimum drifts (as specified) the internal scaling resistors (RU) are connected as shown in Table 4 for the COB or CTC codes and an external series connected metal flIm resistor (RLS) is added to obtain a full scale output voltage range Qf ±I volt. With RLS = 0, VOUT = ±0.944V. V OUT RI.S SETTLING TIME FIGURE II. DAC85-CBI·I Connected for Bipolar Output Voltage' with Resistive Load. The current output DAC85 models have a specified settling time of 300 nanoseconds with a 100 ohm load. Settling time increases as the load resistance increases due to the RC time constant of RL and the summing junction capacitance. Driving an External Op Amp UNIPOLAR or BIPOLAR - Up to 20V Output Range The current model DAC85 will drive the summing junction of an op amp (the op amp being used as a current to voltage converter) to produce an output voltage (see Figure 12): lOV ranse(CBI) SkOCBI.3kIlCCD no VOUT=-lxRF o where lOUT is the DAC85 output current and RF is the feedback resistor. Use of the internal feedback resistors of the DAC85 will provide the same output voltage ranges as the voltage model DAC85. Table 5 must be used for con· necting the external op amp to obtain the desired output voltage range. Output Range ±IOV Digital Connect Connect Connect Connect Input Codes @to Pin 17 to Pin 19to Pin 16 to COBorCTC 24 19 15 @ ±SV COBor CTC 18 15 N.C. 24 ±2.SV COB orCTC 18 15 15 24 010 +IOV CSB 18 21 N.C. 24 o to +SV o toHOV CSB 18 21 15 24 CCD 19 N.C. @ 24 VOUT FIGURE 12. External Op Amp - Using Internal Feedback Resistors. TABLE 5. Voltage Ranges of Current Output DAC85 with External Op Amp. OUTPUTS LARGER THAN 20 VOLT RANGE For output voltage ranges larger than ±IO volts, a high volt· age op amp may be employed with an external feedback resi$tor. Use lOUT values of ±I rnA for bipolar voltage ranges, and -2 rnA for unipolar voltage ranges (see Figure 13). Use protection diodes when a high voltage op amp is used. FIGURE 13. External Op Amp - Using External Feedback Resistors. 6-176 BUILDING AN AID CONVERTER The small size and good performance of the DAC85 makes it an excellent component for building A/D converters. The most popular medium speed (1 /-tsec/bit to 10 /-tsec/bit) A/D converter is the sue· cessive approximations type, in which the digital output equivalent of the analog input is formed by comparing a programmed 0/ A converter output with the analog input. The digital output is sue· cessively compared one bit at a time until the final comparison is within ± 1/2 bit of the resolution of the 0/ A convertef. The conversion speed of a successive approximation AID converter constructed around a DAC85 is de· termined by the settling speed to ± 1/2 LSB, the speed of the comparator, and the switching speed of the successive approximations logic. The A/D converter shown in Figure 14 will convert at speeds in excess of 60 kHz for 12 bits and near 80 kHz for 10 bits. Convert ------'1rc====:;------------, D Gnd Clock S Successive Approximation DO Logic CP AM 2504 cc Serial Data Out Status (MSB) ~~~~gcr---------J (0 to +IOV) FIGURE 14. J2·Bit Successive Approximation A/D Converter. 6-177 BURR-BROWN@ DAC90 IElElI Monolithic Microcircuit DIGITAL-TO-ANALOG CONVERTER FEATURES • 8-81T RESOLUTION • CURRENT OUTPUT • FAST SETTLING 200nsec to ±D.2% • HERMETIC DUAL-IN-LiNE PACKAGE • LOW COST • INTERNAL REFERENCE AND SCALING RESISTORS DESCRIPTION The DAC90 is an 8-bit D I A Converter that offers performance usually found only in larger, modular units. Housed in a l6-pin ceramic dual-in-line package, the DAC90 is complete with its own internal reference and scaling resistors. Two versions are available: the DAC90BG (-25°C to +85°C) and DAC90SG (-55°C to +1 25°C) both offer ±o.2% nonlinearity over their respective temperature ranges: Settling time to ±o.2% is typically 200nsec. The small size of the DAC90 makes it an ideal choice as the heart of your AID converter design or for applications where space or weight is at a premium, such as CRT displays, aircraft instrumentation, and portable instruments. Intlmatlonal Airport Industrial Park· P.O. Box \1400· Tucaon. Arizona 85734· Tel. (6021746-1111 . Twx: 910·952·1111 . Cable: BBRCORP . Telax: 66-6491 PDS-347B 6-178 Printed in U.S.A.July,1978 SPECIFICATIONS MECHANICAL Typical al 25°C and rated power supplies unless otherwise noted. ELECTRICAL MODEL DAC90BG DAC90SG UNITS 8 Bits DIGITAL INPUT • Resolution 8 Logic Levels (TIL-compatible) Logic "I" Logic '"0" +2 < .. < +5.5 at +4O~A 0< .. < +O.~ at ·I.OmA V V TRANSFER CHARACTERISTICS ACCURACY Linearity Error at 25°C, max -2S'C to +8S"C, max -SS"C to +125°C. max ±1/2 ±1/2 ±1/2 Differential Linearity Error ±112 Gain Error (I) 5 I ·25 to +85 Offset Error(l) Minimum Temperature Range for Guaranteed Monotonicity LSB LSD LSD LSD % % of FSR(2) ±1/2 ±I 2 5 I ·55 to +125 NOTE: Laad5 in trua p05ition within .010" @ MMC It saeting pla"a. (.25mmt R INCHES DIM 'e DRIFT (3) Gain ·25'e to +85'e ·55'C to + 125'C Offset Unipolar ·25'C to +85'e ·55'C to +125'C Bipolar ·25·C to +85'C ·55'C"to + I 25'e A 0 ±50 ppm/"e ppm/"C ±I ppm of FSR/"e ppm of FSR/"C +50 ppm of FSR/"e I ppm of FSR/"C ±50 ±) ±50 CONVERSION SPEED Settling time to ±O.2% of FSR for FSR change 100 to lOon load Ikn'load nsec nsec 200 300 ANALOG OUTPUT Ranges Output Impedance - Bipolar Unipolar Compliance Internal Reference Voltage (V.) Tempco of Drift F MIN .790 .105 .... .015 MAX 20.57 4.32 .021 0.38 0.53 ,060 1,22 1.52 2.54 BASIC 0.76 . 1.78 0.20 0.30 6.10 3.05 K L .300 BASIC M .026 'D· .060 7.62 BASIC 0.64 'D· 1.52 CONNECTOR: None CASE: Ceramic, with hermetic seal. PI N: Pin material and. plating'composition conform to method 2003 (solderability) of MI L-STD883 (except paragraph 3.2) HERMETI.CITY: Fluorocarbon (gross leak) and Helium 5 x 10-7cc/sec (fine leak). ±I. 0 to-2 rnA k!l kfi I.K 2 -4 to +4 7t ±50 V V ppm ofv./"e ±50 CONNECTION DIAGRAM DAC90 POWER SUPPL Y SENSITIVITY +15VDC ·15VDC ±O.02 ±O.002 %ofFSR/%Vs % of FSR/%Vs ±15 ±14.S to ±IS.S VDC VDC 7 rnA POWER SUPPL Y REQUIREMENTS Rated Voltage Range Supply Drain +15VDC MIN 20.01 2.67 .810 .100 BASIC .070 .030 .012 .OOS .240 .120 G MILLIMETERS .170 MAX Bit 1 (MSB) +1SV Common TEMPERATURE RANGE Specification Operating Storage ·25 to +85 ·55 to +125 ·55 to +125 ·55 to +125 ·55 to +125 ·55 to +125 ·'C ··c ..c 10V Range I. 2. 3. 4. Adjustable to zero with external trim potentiometer. FSR means "full scale range" and is 20V for ±IOV range, IOV for"±5V range, etc. To maintain. drift spec internal feedback resistors must be used. Connect to sround if pi. adjust circuit is not Used. 20V Range Bipolar Offset Bit 8 (LSB) ~ _ _ _ _ _ _ _-I.9 ;~~ -15V 4. Connect to ground if gain adjust circuit is not used. 6-179 (4) DISCUSSION OF SPECIFI,CATIONS DIGITAL INPUT CODES OFFSET DRIFT The DAC90 accepts digital inputs. in complementary binary (CBI) format and may be connected for complementary straight binary (CSB) or complementary offset binary (COB) operation (see Table I). By using one external inverter, the user can operate the DAC90 in the complementary two's complement (CTC) mode. OFFSET DRIFT is a measure of the actual change in output voltage (using an external amplifier) at zero volts output over the specified temperature range. The offset voltage is measured at the temperature extremes, and the maximum change referenced to 25"C is divided by the temperature range. This drift is expressed in parts per million of full scale range per "c (ppm of FSR/,'C). DIGITAL INPUT CODES MSB OUTPUT RANGE CURRENT VOLTAGE* Dto +lDV ±.lDV Dto ·2mA ±.lmA SETTLING TIME Settling time is the time required for the output to enter and remain in an .error band equal to ±0.2% of full scale range measured from the time the digital input is changed. Typical settling time values for full scale changes are a function of the load resistor and are shown in the figure below. . LSB 00000000 "+9.961 V 01111111 +5.000V O.OOOV +9.922V -1.992mA 10000000 +4.961V -78.12mV -O.99mA 11111111 O.OOOV one· LSB 39.06mV 78.12mV -10.000V -O.992mA -1.000mA O.O.OOOmA +7.81IJA O.OOOmA +1.000mA 7.BlIlA 7.BlIlA * Requires exte~nal amplifie"r. To 'obtain values for other binary (CBI) ranges: o to +5V. ran~e: div.ide 0 to + 1 OV range values by 2 t.5V ran,ga: divide ±10V range values by 2. ±2.SV range: divide ±10V range values by 4. TABLE 1.0igital Input and Analog Output Relationship. 300 .." U " c: ACCURACY ._E a: I-(f) LINEARITY := 0 .....~ 200 --- ClU. c:- =#. ~~ The'LINEARITY of a D I A converter is the true measure of its performance. The DAC90 analog output will not vary by more than ±1/2LSB from an ideal straight line drawn between the end points (all l's and all O's) over the specified temperature range. +1 B 100 100 lk 10k Load Resistor I n DIFFERENTIAL LINEARITY DIFFERENTIAL LINEARITY error of a. D/A converter is the deviation from an ideal ILSB voltage change from one adjacent output state to the next. A DIFFERENTIAL LINEARITY error specification of ±1/2LSB means that the output voltage can change anywhere from 1/2LSB to 3/2LSB when the input changes from one adjacent digital state to the next. lOOk I FIGURE l. Settling Time for FSR Change vs Load. COMPLIANCE The COMPLIANCE VOLTAGE of the DAC90 is the maximum voltage swing allowed on the current output in order to maintain the specified accuracy; it is -4.0V to +4.0V for the unipolar and bipolar current ranges. The maximum safe voltage swing allowed with no damage to the DAC90 output is -4.0V to +lS.0V. DRIFT GAIN DRIFT GAIN DRIFT is a measure of the change in the analog output over temperature expressed in parts per million per "c (ppm/"C). The GAIN DRIFT is determined by testing the. end point differences at the high and low temperature extremes and at 25.HC for each model. calculating the GAIN ERROR with.respect to the 25"C value, and dividing by the temperature change. 6-180 POWER SUPPLY SENSITIVITY .1 .. POWER SUPPLY SENSITIVITY is a measure of the effect of a power supply voltage change on the D I A converter output. It is defined as a percent of FSR I percent of change in either the +15 volt or -IS volt power supplies about the nominal power supply voltages. Figure 2 shows Power Supply Rejection vs Frequency. ~ g UJ a: Ul u. i5. ,'" >" E + 15V Supply ....... .02 .01 ~ ,/ '"~ .006 0 -£ 0 . .04 > /" .004 V .002 .001 ,, ,/ ./ / .06 1 10 " ' -15V 100 rpP1Y 1k 10k 100k Power Supply Ripple Frequency (Hz) FIGURE 2. Power Supply Rejection vs. Power Supply Ripple Frequency. OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS >--....- - - - _ DECOUPLING DAC90 For best performance and noise rejection, power supply decoupling capacitors should be connected as shown in Figure 3. These capacitors should be located close to the DAC90 and should be tantalum or electrolytic types bypassed with a 0.0 I IlF ceramic capacitor for best high frequency performance. To +15VDC· Supply Common >--....- - - - _ To -15VDC Supply FIGURE 3. Recommended Power Supply Decoupling. OPERATION IN THE CURRENT OUTPUT MODE In the current output mode, the DAC90 provides a unipolar output current of 0 to -2mA and a bipolar output current of ±I rnA. Refer to Figure 4 and Table II for proper connections. In applications requiring the use of the DAC90 in the current output mode, such as an AI D converter, the internal scaling resistors should be used to generate currents corresponding to analog input voltages. Oto -2mA Output Range o to -2mA ±1mA Connect Pin@to: N.C. Pin 10 TABLE II. Connections for Current Output Mode. FI G U R E 4. Current Output Mode Connection Diagram. 6-181 VOLTAGE OUTPUT using an EXTERNALOP AMP UNIPOLAR OR BIPOLAR OPERATION The DAC90 wil drive the summing junction of an op amp (the op amp being used as a current-ta-voltage converter) to produce an output voltage. VOUT = -I X RF where lOUT is the DAC90 output current and RF is the feedback resistor. Refer to Table III and Figure 5. Output Range Digital Input Codas. SkU Connect Pin@to CDB 11 10 ±5V CDB 12 10 ±2.5V 10,11 ±10V V out Connect to ® CDB 12 o to +10V CSB 1'2 N.C. o to +5V CSB 12 11 ! FIGURE 5. External Op Amp Using Internal Feedback Resistors. TABLE Ill. Voltage Ranges of Current Output OAC90 With External Op Amp. EXTERNAL OFFSET and GAIN ADJUSTMENT Initial offset and gain errors may be trimmed by the user with externally connected OFFSET and GAIN potentiometers and an operational amplifier. Refer to Figures 5 and 6 for proper connectiol)s. The adjustment procedures are described below. Potentiometer resistances are shown as a range of values and should have a temperature drift coefficient of 100 ppmj"C or less. The trimming networks should be located as close to the OAC90 as possible to minimize noise pickup. The ceramic capacitor shown in Figure 6 will further reduce noise pickup at the gain adjust point. OFFSET ADJUSTMENT Offset adjustment should be made prior to gain adjustment. Connect the unit as shown in Figure 5 for thtl desired output range and add the offset adjust network shown in Figure 6. Offset adjustment is the same procedure for either bipolar or unipolar operation. Apply the digital input code which should give zero volts output and adjust the offset potentiometer for zero volts output. See Table I for the corresponding codes. I :t1~V ~O""' 100kn 9 O.OOII'F to O.OII'F Adjust 13 9 10kU to 100kU 1R GAIN ADJUSTMENT The gain adjust procedure is the same for either bipolar or unipolar operation: An external amplifier should be connected as shown in Figure 5. Connect the unit for the desired output range and add the gain adjust network shown in Figure 6. Apply the digital input code which should give the maximum positive output voltage and adjust the gain potentiometer for the correct output. Refer to Table I for the corresponding: codes. ~&.geOf ~ "iii -',/' Cf,l' ~ ~ B ~ q: I -' ~~ l Range Offset A~ '" ,. All l's I ~ ,~, Gain Adj. ~ rotates I //;' ~ '" 0 "iii < .. q: the line Adl· Dffsot Adj . the line 11-4--7 All O·s/ t Range of O~fset /~ All O's / Adjust /// ""/// Digital Input FIGURE 7. Relationship of OFFSET and GAIN Adjustment for a UNIPOLAR OJ A Converter. ~q Gain translates ~ I/" 0. Offset Adj . .--~HH--+-+-HH-+++-~· Translates the line u. Ail 1's Gain Adj //,.1 /." "/ ~ ,a: "S-, /. Range of ~;¥ ~/ 1T . rn u '" < _ m ~~// & 1 LSB +Full Scale ,1''' ., 5 ~ R FIGURE 6. Connections for OFFSET and GAIN Adjustment. , L :; Gain Adjust R=lktOl0kQ. -15V -ISV ~ +Full Scal-e +15V 1R -FLlII Scale Digital Input FIGURE 8. RelatIOnship of OFFSET and GAIN Adjustments for BIPOLAR 0; A Converter. 6-182 BURR-BROWN® DAC800 IElElI Integrated Circuit DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • LOW COST HIGH RELIABILITY SINGLE-CHIP REPLACEMENT FOR INDUSTRY-STANDARD DACBO The DAC800 is a third-generation monolithic I ntegrated Circuit that is a pin-for-pin equivalent to the industry-standard DAC80 first introduced by Burr-Brown. It has all of the functions of its predecessor pi us faster settling time and enhanced reliability because of its monolithic construction. The current output model of the DAC800 is a singlechip integrated circuit containing a subsurface zener reference diode, high speed current switches, and laser-trimmed thin-film resistors. The DAC800 provides output voltage ranges of ±2.5V, ±5V, ±IOV,O to +5V, 0 to +IOV (V models) or output current ranges of ±I rnA or 0 to -2mA (I models). • 12-BIT RESOLUTION • ±1I2LSB MAXIMUM NONLINEARITY, DoC TO +70°C • GUARANTEED MONOTONICITY, DoC TO +70°C • DUAL-IN-L1NE PACKAGE WITH INDUSTRY-STANDARD (DACBO) PINOUT VOLTAGE MODEL 6.3V REF OUT GAIN AOJUST +VCC COMMON SUMMING JUNCTION 20V RANGE 10VRANGE This high accuracy converter offers a maximum nonlinearity error of ±1/2LSB, ±30ppmj"C maximum gain drift and guaranteed monotonicity, all over O°C to 70°C. In the bipolar configuration total drift is guaranteed to be less than 25ppm of FSRj"C. The DAC800 is packaged in a 24-pin dual-in-line package with the popular DAC80 pinout. For designs that require a wide temperature range and a hermetically sealed package see Burr-Brown models DAC850 and DAC851. BIPOLAR OFFSET REF INPUT VOUT ·VCC LOGIC SUPPLY Patents pending may apply upon the allowance and issuance of patents thereon. The product may also be covered in other countries by one or more international patenh. Inlarnalional Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. (602) 741H 11 t • Twx: 91IJ.952·1111 • Cable: BBRCORp· Telex: 66·6491 P[)S440 6-183 MECHANICAL SPECIFICATIONS ELECTRICAL 2. Typical at 25°C and rated power supplies unless otherwise noted MODEL MIN DIGITAL INPUT Resolution Logic Levels (over spec. temp range)(1) V,H (Logic "1"1 V,L [Logic "0"1 ItH (VIN = +2.4V I ItL (V,N = +O.4VI ACCURACY Linearity Error at 25°C Differential Linearity Error Gain Erron2) Offset Erron2) Monotonicity Temp. Range, min UNITS +2 0 16.5 +0.8 +20 -0.36 ±1/4 ±1/2 ±1/2 +1. -3/4 ±O.I ±0.05 ±0.2 ±0.15 +70 0 ~A mA LSB LSB % %of FSRI3) ·C ±IO ±25 ppm 01 FSRI"C ±0.06 ±0.05 ±IO ±I ±7 ±0.15 ±0.12 ±30 ±1/2 +1. -7/8 ±1/2 %ofFSR % of FSR ppm/DC ppm of FSRI"C ppm 01 FSRI"C LSB LSB 3 2.5 10 ±3 ±15 5 4 300 1 ,",sec ±2.5. ±5. ±10. 0 10 +5. 010 +10 ±5 0.05 Indefinite V mA !l ANALOG OUTPUTII models Ranges - Bipolar Unipolar Output Impedance - Bipolar Output Impedance - Unipolar Compliance ±0.88 ±1.175. ±1.47 Oto-I.76 010 -2.35 010 -2.94 3.1 7.2 -2.5 +2.5 mA mA TEMPERATURE RANGE Specification Operating Slllrage MIN H INCHES MILLIMETERS MIN MAX 1.215 30.10 30.86 c 0 .105 .015 .170 .021 2.67 0.38 4.32 0.53 F 03. 0.89 1.52 J K L .008 .060 .012 .240 2.54 BASIC 17. 0.76 0.20 3.05 +6.23 1.5 +6.37 ±30 V mA ppm/DC ±O.OOOI ±0.003 ±0.001 ±0.006 % of FSR/% Vee % of FSR/% Vee ±13.5 +4.5 ±15 +5.0 +16.5 +16.5 VDC VOC +8. -20 +7 +12. -25 +10 mA mA 0 -25 -60 +70 +85 +100 °C DC DC 6-184 ~ , ... '" .oM NOTE: Metal Lid connected to ·Vcc internally. CASE: Ceramic MATING CONNECTOR: 0245MC WEIGHT: 8.4 grams 10.30z.' .060 0.64 1.52 PIN ASSIGNMENTS PIN I MODELS NO. V MODELS MSB· BITI BIT2 BIT3 BIT4 BITS BIT6 BIT7 BIT8 BIT9 BIT 10 BIT 11 LSB, BIT 12 LOGIC SUPPLY. Voo -Vee REF. INPUT BIPOLAR OFFSET SCALING NETWORK SCALING NETWORK SCALING NETWORK COMMON +Vee GAIN ADJUST 6.3V REF. OUT V +6.30 2.5 ±10 0.30 6.10 ~. [ lbD 10D .025 i, 1524 BASIC .600 BASIC M N MAX .100 BASIC .030 .070 .120 1 I.- G 1.185 G f Seating Plane A kll kll POWER SUPPLY REQUIREMENTS Vool") Supply Drain +15V. -15V ,no load +5V , logic supply. OIM I lOUT POWER SUPPLY SENSITIVITY +15V and +5V Supplies -15VSupply ±Vcc ..Lo nsec ANALOG OUTPUTN models Ranges Oulpul Current Output Impedance r DC I Short Circuit to Common, Duration A Pin numbers shown for reference only. Numbers may not be marked on package. mmmmL J ,",sec J,Asec VllJ,sec jl.J F -- I ..J ,",sec 1.5 15 _. 12 ~N-1--~ H CONVERSION SPEED/I models Settling Time to ±o.OI % of FSR For FSR Change 100 10 1000 load lkllioad REFERENCE VOLTAGE OUTPUT Current I for externalloadsl, Source Tempco of Drift 1 I!.VDC VDC 0 > 0 12 DRIFTI4)ICOC to +70DCI Bipolar Drift. (±full scale drift for the bipolar connection I, Total error over COC to +700C(5) Unipolar Bipolar Gain Unipolar Offset Bipolar Offset Differenlial Linearity COC to +7COC Linearity ErrorOoC to +700C CONVERSION SPEEDN models Settling Time 10 ±o.D1 % of FSR For FSR Change 20 voll range. 2kO load 10 volt range. 2kllioad For 1 LSB Change. Major Carry. 2kO load Slew Rate. 2kllioad DAceOD-CBI TYP MAX NOTE: Leads in, true position wilhin 0.010" ,0:25mm· R al MMC al sealing plane. 13 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BIT 1 ·MSB BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT 10 BIT 11 BIT 12· LSB· LOGIC SUPPLY. Voo -Vee VOUT REF. INPUT BIPOLAR OFFSET 10V RANGE 20V RANGE SUMMING JUNCTION COMMON +Vce GAIN ADJUST 6.3V REF. OUT NOTES: 1. Refer to Logic Input Compatibility section. 2. Adjustable to zero with external trim potentiometer. 3. FSR means "Full Scale Range" and is 20V for ±10V range. 10V for ±5V range, etc. 4. To maintain drift spec internal feedback resistors must be used for current output models. 5. Includes the effects of gain, offset and linearity drift. Gain and offset errors are adjusted to zero at +25°C. 6. Power dissipation is an additional100mW, max, when Voo is operaled al +15V. CONNECTION DIAGRAMS Current Model Vonage Model ~ +vee 111 IOMll ~ IOkll to lOOkn )-~.Jo.J'Iv""" .Vee IOkn to lOOkn +Vee ·Vee NOTES: 1. DAC80 which may be replaced by DAC800 requires a 33M!} resistor. DAC800 requiresa 10Mn resistor. DACaO's may also be operated with a 10Mn resistor resulting in increased trim range. 2. Pin 16 of OACBOO is used only to connect the bipolar offset resistor. An external reference voltage may not be used with DAC800 as is possible with DAcao. 3. If connected to +Vcc, which is permissible, power dissipation increases 75mW typ, 100mW max. 4. For fastest settling time connect pins 19, 18. and 15 together. DISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES The DAC800 accepts complementary binary digital input codes. The CBI model may be connected by the user for anyone of three complementary codes; CSB, CTC, or COB. TABLE L Digital Input Codes. DIGITAL INPUT MSB LSB 000000000000 011111111111 100000000000 111111111111 ANALOG OUTPUT CSB Compl. Straight Binary +Full Scale +1/2 Full Scale 1/2 Full Scale -lLSB Zero COB CTC' CampI. CampI. Offset Binary Two's Compl. +Full Scale Zero -lLSB -Full Scale -lLSB -Full Scale +Full Scale Zero *Invert the MSB of the COB code with an external inverter to obtain CTC code. ACCURACY Linearity of a D / A converter is the true measure of its performance. The linearity error of the DAC800 is specified over its entire temperature range. This means that the analog output will not vary by more than ± 1/ 2LSB, maximum, from an ideal straight line drawn between the end points (inputs all "I "s and all "O"s) over the specified temperature range ofO"C to +70°C. Differential linearity error of a D / A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±1/2LSB means that the output voltage step sizes can range from 1/ 2LSB to 3/2LSB when the input changes from one adjacent input state to the next. Monotonicity over a O°C to +70"C range is guaranteed in the DAC800 to insure that the analog output will increase or remain the same for increasing input digital codes. DRIFT Gain Drift is a measure of the change in the full scale range output over temperature expressed in parts per million per °C (ppm/"C). Gain Drift is established by: I) testing the end point differences for each DAC800 model at OnC, +25"C and +70"C; 2) calculating the gain change with respect to the +25"C value and; 3) dividing by the temperature change. This figure is expressed in ppm/"c. Offset Drift is a measure of the change in output with all "I "s on the inputs over the specified temperature range. The Offset is measured at O°C, +25"C and +70"C. The maximum change in Offset is referenced to the Offset at +25"C and is divided by the temperature change. This drift is expressed in parts per million of full scale range per "c (ppm of FSRj"C). 6-185 Bipolar Drift is a measure of the change in plus or minus full scale output over the specificlition temperature range for the bipolar connection. Because Bipolar Offset Drift and Gain Drift have canceling interactions, Bipolar Drift is not simply the sum ofthe two. Total bipolar error over temperature is calculated using Bipolar Drift, then adding ±I f2LSB of linearity error. nominal power supply voltages (see Figure 2). u ~ 0.01 =.,...-=----,=",....",.......,..,.......,,=,......___=== .~ w c .c: ." () '0 1: w SETTLING TIME ~ 0.OO11--~--t-- Settling time is the total time (including slew time) required for the output to settle within an error band' around its final value after a change ~n input (see Figure I). ~ e w a: (/) u.. 2iii 0.OO01 ... _~_-.~_~::.....--!.,...-.,...-~.......-J._--J 1 "a; Frequency· Hz I 0. FIGURE 2. Power Supply Rejection vs Power Supply Ripple. FIGURE I. Full Scale Range Settling Time vs Final Value Error Band. Voltage Output Models: Three settling times are specified to ±O.O I% of full scale range (FSR); two for maximum full scale range changes of 20V, IOV, and one for a I LS B change. The I LSB change is measured at the major carry (0111 ... 11 to 1000 ... 00), the point at which the worst case settling time occurs. Current Output Models: Two settling times are specified to ±0.01% of FSR. Each is given for current models connected with two different resistive loads: Ion to loon and 1000n. Internal resistors are provided for connecting a nominal load resistance of approximately 1000n for output voltage ranges of ± I V and 0 to -2V. COMPLIANCE Compliance voltage is the maximum voltage swing allowed on the current output node in order to maintain specified accuracy. The maximum compliance voltage of all current output models is -2.5V to +2.5V. . POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the Of A converter output. It is defined as a percent of FS R per percent of change in either the positive, negative, or logic supplies "bout the REFERENCE SUPPLY All DAC800 models have an on-chip +6.3 volt reference. T'his voltage (pin 24) has a tolerance of±l% and must be connected to the Reference Input (pin 16) for specified operation. Pin 16 is used only to connect the bipolar offset resistor. An external reference may not be used with DAC800. See Connection Diagrams. Th.e. reference voltage may be used to supply external circuits with 2.5mA of curr~~t in addition to the I mA required by the bipolar offset circuit. If a varying load is to be driven, an' external buffer amplifier is recommended to drive the load in order to isolate bipolar offset from load variations. Gain and bipolar offset adjustments should be made under constant load conditions. INSTALLATION AND OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS Decoupling: For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagrams. These capacitors (I/LF tantalum or electrolytic recommended) should be located close to the DAC800. Electrolytic capacitors, if used, should be paralleled with O.OI/LF ceramic capacitors for best high frequency performance .. The metal lid on the top of the package is connected internally to -Vee. EXTERNAL OFFSET AND GAIN ADJUSTMENT Offset and Gain may be trimmed by installing external Offset and Gain potentiometers. Connect these potentiometers as shown in the connection diagrams and adjust as described below. TCR of the potentiometers should be IOOppm/ °C or less. The 3. 9Mn and JOMn resistors (20% 6:.. 186 carbon or better) should be located close to the DAC800 to prevent noise pickup. If it is not convenient to use these high value resistors, an equivalent "T"network, as shown in Figure 3, may be substituted in each case. The Gain Offset Adjustment: For unipolar (CSB) configurations, apply the digital input code that should produce zero potential output and adjust the Offset potentiometer for zero output. FIGURE 3. Equivalent Resistances. For bipolar (COB, CTC) configurations, apply the digital input code that should produce the maximum negative output voltage and adjust the Offset potentiometer for minus full scale voltage. Example: If the Full Scale Range is connected for 20V, the maximum negative output voltage is -IOV. See Table II for corresponding codes and the Connection Diagrams for offset adjustment connections. Adjust (pin 23) is a high impedance point and a O.OOI/lF to O.OI/lF ceramic capacitor should be connected from this pin to Common (pin 21) to reduce noise pickup. Figures 4 and 5 illustrate the relationship of Offset and Gain adjustments to unipolar and bipolar D f A converter output. Gain Adjustment: For either unipolar or bipolar configurations, apply the digital'input that should give the maximum positive voltage output. Adjust the Gain potentiometer for this positive full scale voltage. See Table II for positive full scale Voltages and the Connection Diagrams for gain adjustment connections. 2711m ~ 270kn ~ 10Mn 11IOkn ':'I&n ~ ~ 3,9Mn "L '" ~":":"'T +FULL SCALE != :=.... is RANGE OF Internal scaling resistors provided in the DAC800 may be connected to produce bipolar output voltage ranges of ± IOV, ±5V or ±2.5V or unipolar output voltage ranges of o to +5V or 0 to.+IOV. See Figure 6. J",,'/ ~ 1h' CiU ... i VOLTAGE OUTPUT MODEL Output Range Connections RANGE OF GAIN ADJ. ... ~!ii! ALL BITS !!! il!i LOGIC l:tf' GAIN A~J. "'11 / "I; OFFSET ADJ. OFFSET ADJ. TRANSLATES yTHE LINE I ROTATES THE LINE ALL BITS LOGIC 0 DIGITAL INPUT FIGU RE 4. Relationship of Offset and Gain Adjustments for a Unipolar D f A Converter. ILSB L_J / Gain and. offset drift are minimized because of the thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are shown in Table III. Settling time for a full scale range change is specified as 3/lsec for the 20 volt range and 2.5/lsec for the 10 volt range. +FULL L SCALE/; .. RANGE OF ~:/T GAIN ADJ. Tf.~· ALL BITS LOGIC I . ,,·H-_. . . Lf BIPOLAR V I'MSB ON RANGE OF OFFSET J,'fALL OTHERS OFFSET ADJ'l ' I OFF OFFSET ADJ. I :FULL SCALE TRANSLATES " THE LINE T DIGITALIN PUT /4' L 5.38kn --,.___ @17BIPOLAR OFFSET REF. INPUT Iiii'~-~'N"'. \::J FULL SCALE , ; : } \ _ GAIN ADJ. RANGE /-:,;/" ROTATES ~1:<'4....,.._.. THELINE ~ ALL BITS LOGIC 0 OFFSET RESISTOR TOLERANCES ±25% FI G U R E 5. Relationship of Offset and Gain Adjustments for a Bipolar Df A Converter. FIGURE 6. Output AmplifierVoJtage Range Scaling Circuit. TABLE II. Digital Input! Analog Output. ANALOG OUTPUT DIGITAL INPUT CURRENT VOLTAGE' oto +10V 12-Bit Resolution MSB LSB 000000000000 011111111111 lQOOoooooOOO 111111111111 One LSB COMMON .... FROM WEIGHTED RESISTOR NETWORK +9.9976V +5.0OO0V +4.9976V O.OOOOV 2.44mV ±10V +9.9951V O.OOOOV -0.0049V -10.OOOOV 4.88mV oto-2mA -1.9995mA -1.oo00mA -0.9995mA O.OooomA O.488pA "To obtain values for other binary ranges: 0 to +5V range divide 0 to +10V range values by 2. ±5V range: divide ±10V range values by 2. ±2.5V range: divide ±10V range values by 4. 6-187 ±lmA ~.9995mA D.OOoomA +O.0005mA +1.0oomA 0.488pA Figure 9will generate a voltage range, VOUT, determined by: . TABLE III. Output Voltage Range ConnectionsVoltage Model DACSOO. Output Range Digital Input C~es Connect Pin IS to ±IO ±5 ±2.5V Olo+IOV 010 +5V COB or CTC COB or CTC COB or CTC CSB CSB 19 18 18 18 18 Connect Pin 17to Connect Pin 19 to Connect Pin 16to 20 15 N.C. 20 20 21 21 N.C. 24 24 24 24 20 24 20 RI. x 7.2kO) VpUT = -2.35mA ( RL + 7.2kO CURRENT OUTPUT MODEL The resistive scaling network and equivalent output circuit of the current model differ from the voltage model and are shown in Figures 7 and S. It is important to note 1)----0+ ~!~ FIGURE 9. Current Output Model Equivalent Circuit Connected for Unipolar Voltage Output with Resistive Load. .EF.I.PUT&---YV~ ~ 18 \6 ...." 4.28: [ .."." 'N' RIIIIIDr \DIIIIIICR ±25% @ @ To achieve specified drift, connect the internal scaling resistor (Ru) as shown to an external metal film trim resistor (RLS) to provide full scale output voltage range of oto -2V. If the internal resistors are not used, external RL (or Rp) resistors should have a TCR of ±25ppm/"C or less to minimize drift. This will typically add ±50ppm/"C plus the TCR of RI. (or RFl to the total drift. Tolerances on internal equivalent resistors are wide. RLS will have to be selected for each unit. FIGURE 7. Internal Scaling Resistors. I OTO 2.3511A Driving a ReSistive Load Bipolar The equivalent output circuit for a bipolar output voltage range is shown in Figure 10, RL = Ru + RLS. VOUT is determined by: +25% FIGURE S. Current Output Model Equivalent Output C i r c u i t . ' Vo that there is a relationship between the tolerances of the current source and the scaling resistors. The magnitude of the tolerance tracks very closely but with opposite sign. The tolerance of the internal resistance of the converter (7.2kO unipolar, 3.07kO bipolar) tracks the tolerance of the scaling resistors in sign and approximately proportion" ately in magnitude. That is, if the scaling resistors are high by 10%, the internal impedance is high by about 8%. An external resistor is required to produce exactly 0 to -2V or ± I V output. TCR of these resistors should be ±100ppm/"C or less to maintain the DACSOO output specifications. If exact output ranges are not required, the external resistors are ·not needed. Internal resistors are provided to scale an external op amp or to configure a resistive load to offer two output voltage ranges of± I V or 0 to -2V. These resistors are an integral part of the. DAC800 and' maintain gain and. bipolar offset drift specifications. Driving a Resistive Load Unipolar A load resistance, RL = RLI + RLS, connected as shown in T U = ±1.175mA(RI. x 3.07kO \ RL + 3.07kOJ }-----O+ VOUT FIGURE 10. Current Output Model Connected for Bipolar Output Voltage with Resistive Load. To achieve specified drift, connect 1.71kO and 2.55kO internal scaling resistors in parallel (Ru) and add an external metal film resistor (RLs) in series to obtain a full scale output range of ± I V. ,The tolerances on the internal eq uivalent resistors are wide. Rl.s will have to be selected for each unit. 6-188 Driving An External Op Amp The current output model DAC800 will drive the summing junction of an op amp used as a current to voltage converter to produce an output voltage. See Figure 11. VOUT 4.26kn "FOR OUTPUT VOLTAGE SWINGS UP TO 140V PlI. 4.26kn FIGURE 12. External Op Amp - Using External Feedback Resistors. I 72kn oto The feedback resistor, RF, should have a temperature coefficient as low as possible. Using an external feedback resistor, overall drift of the circuit increases due to the lack oftemperature tracking between RF and the internal scaling resistor network. This will typically add 50 ppmj"C + RF drift to total drift. 2.35mA FIGURE 11. External Op Amp - Using Internal Feedback Resistors. VOUT = 10CT X RF where lOUT is the DAC800 output current and RF is the feedback resistor. Using the internal feedback resistors of the current output model DAC800 provides output voltage ranges the same as the voltage model DAC800. To obtain the desired output voltage range when connecting an external op amp, refer to Table IV. Digital Range Input Codes @nect A to Pin 17 to Connect Pin 19 to ±'OV ±5V ±2.5V oto +'OV o to+5V COBorCTC COB or CTC COB orCTC CSB CSB '9 '8 '8 '8 '8 '5 '5 '5 2' 2' N.C. '5 N.C. '5 Connect 0 DAC800 digital inputs are TTL. LSTTL and 54/ 74HC CMOS compatible over the operating range of VIlI), +5 to + 15 volts. The input switching threshold remains at the TTL threshold over supply range of VJ)J), +5 to + 15V. Logic "0" input curren1 over temperture is low enough to permit driving DAC800 directly from outputs of 4000B and 54j74C CMOS devices over the logic power supply range of +5 to + 15 volts. TABLE IV. Voltage Range of Current Output DAC800. Output LOGIC INPUT COMPATIBILITY Connect Pin 16 to 24 24 24 24 24 Output Larger Than 20V Range F or output voltage ranges larger than ± IOV, a high voltage op amp may be employed with an external feedback resistor. Use louT values of± 1.175mA ±25'1( for bipolar voltage ranges and -2.35mA ±25% for unipolar voltage ranges. See Figure 12. Use protection diodes when a high voltage op amp is used. 6-189 ORDERING INFORMATION DAC800 =r -xxx T -x =s Low Cost 12-Bit [) A Converter INPUT CODE eRI = Complementary Family OUTPUT hample: DAC800-CBI-V I = Current Complementary Binar~ DAC800 with \oJtage output Binary v = Voltage BURR":BROWN® DAC8s0 DAC8S1 IElElI' Integrated Circuit DIGITAL-TO-ANAl,.OG CONVERTER FEATURES DESCRIPTION • LOW COST HIGH RELIABILITY SINGLE-CHIP REPLACEMENT FOR DACB5 AND DACB7 The DAC850 and DAC851 are 12-bit single-chip (current output model) digital-to-analog converters for use in wide temperature high reliability applications. The DAC850 and DAC85 I are packaged in a hermetically-sealedpackage with side-brazed pins.· The DAC850 is specified with a linearity error of±112LSB over _25°C to +85°C and the DAC85 I has a linearity error of ±1/2LSB over -55°C to + 125°C. ,Both converters have guaranteed monotonicity over their specification temperature range. The current output configuration of these Dj A converters is a singlechip integra~ed circuit containing a subsurface zener reference diode, high-speed current switches, and laser-trimmed thin-film resistors. The DAC850 and DAC851 provide output voltage ranges of ±2.5Y, ±5Y, ± lOY, 0 to +5 and 0 to + IOY (V models) or output current ranges of±I.175mA or o to -2.35mA (I models). " • 12-BIT RESOLUTION • HIGH ACCURACY , ±1/2LSB max nonlinearity -25°C to +65°C (DACB50) . -550C 10 +125°C (DACB51) • GUARANTEED MONOTONICITY • DUAL-IN-LiNE HERMETIC PACKAGE WITH SIDE-BRAZED PINS UVREFOUT IAIIADJU8T +Vcc COMIOI i I!! E :::; • 8UIIII. JUleTIOI 2IIVRAIIE IDVIAI.E .IPOUR OFFIET IEFllPUT vOUT ·vee voo. LOGIC SUPPLY Patents pending may apply upon the allowance and issuance of patents thereon. The product may also be covered in other countries by one or more ~nternational patents. Inlarnational Alrporllnduslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 746·1111 . Twx: 9I!H152·1111 . Cable: BBRCORp· Talax: 66·6491 PDS453 6,~190 SPECIFICATIONS ELECTRICAL At 25°C and rated power supplies unless otherwise noted DAC85D-CBI MODEL I MIN I TYP DAC851-CBI I I MAX MIN I I TYP MAX I UNITS INPUT DIGITAL INPUT 12 Resolution Logic Levels (LSTTL Compatiblel(1) Logic"I"(al +20~AI Logic "0" lat -0.36mAI +5.5 +0.8 +2 0 12 Bits +5.5 +0.8 VDC VDC ±1/4 ±1/2 ±1/2 +1, -3/4 ±C. 1 ±C.05 ±C.2 ±C.15 +125 LSB LSB % %of FSR(3) °C +2 0 TRANSFER CHARACTERISTICS ACCURACY Linearity Error Differential Linearity Error Gain Error(2) Offset Error(2) Monotonicity Temp. Range, min ±1/4 ±1/2 ±1/2 +1, -3/4 ±0.1 ±0.05 ±C.2 ±0.15 +85 -25 DRIFT(4) (over spec. temp. range) Bipolar Drift (±full scale drift for the bipolar connection) Total Error(5) Unipolar Bipolar Gain Offset, Unipolar Bipolar Differential Linearity (over spec. temp. range) Linearity Error (over spec. temp. range) -55 ±5 ±17 ±15 ±30 ppm of FSRfOC ±C.l ±c.oa ±10 ±1 ±5 ±0.20 ±C.12 ±2O ±3 ±10 ±1 ±C.15 ±C.15 ±10 ±1 ±5 ±C.3O ±C.30 ±25 ±3 ±15 ±1 % of FSR %ofFSR ppmfOC ppm of FSRfOC ppm of FSRfOC LSB LSB ±1/2 ±1/2 ±1/2 ±1/2 CONVERSION SPEED V Model (settling time to ±C.Ol% of FSRI For FSR Change, 20V Range, 2kn Load 10V Range, 2kn Load For 1LSB Change, Major Carry, 2kn Load Slew Rate, 2kn Load I Model (settling time to ±0.01 % of FSR) For FSR Change, Ion to loon Load lknLoad 3 2.5 1.5 15 10 5 3 2.5 1.5 15 4 10 300 1 nsec ",sec " V Model Output Impedance, Bipolar Unipolar Compliance ,.,.sec jJ.sec p'sec V/p.sec 300 1 OUTPUT ANALOG OUTPUT Ranges Output Current Output Impedance (DCI Short Circuit to Common, Duration I Model Ranges 5 4 ±2.5, ±5 2.5 5.8 -2.5 J, I ±10, 0 to +5.'0 to +10 I 0.05 ±2.5, ±5 Indefinite ±1.175, Oto -2.35 3.1 7.2 3.7 8.S +2.5 2.5 5.8 -2.5 +6.3 2.5 ±10 +8.37 +8.23 1.5 ±C.COOI ±C.003 ±15 +5 ±16.5 +16.5 +8,-20 +7 +12,-25 +10 J, I ±10, 0 to +5,10 to +10 0.05 ±1.175, o to -2.35 3.1 7.2 I 3.7 8.6 +2.5 V mA n mA kn kn V POWER SUPPLIES AND REFERENCE Reference Voltage Output Current (for external loads), Source Temperature Coefficient of Drift Power Supply Sensitivity +6.23 1.5 +15V and +5V Supplies -15V Supply +8.37 ±20 +8.3 2.5 ±10 ±25 V mA ppmfOC ±C.OOI ±C.OO6 ±C.COOI ±C.003 ±C.C01 ±C.COS % of FSRi%Vcc % of FSRi%Vcc ±15 +5 ±16.5 +16.5 VDC VDC +8,-20 +7 +12,-25 +10 mA mA +125 +150 °C °C Power Supply Requirements ±Vcc VooIS) ±13.5 +4.5 ±13.5 +4.5 Power Supply Drain ±Vcc (no load I Voo (logiC supply) PHYSICAL CHARACTERISTICS TEMPERATURE RANGE Specification Storage PACKAGE -25 -60 +85 +150 -55 -60 24-pin hermetic DIP side-brazed ceramic 6-191 '.-:_.. - ' NOTES: 1. Adding external CMOS hex buffers CD 4049A/4050A will provide CMOS input compatibility. Refer to Logic Input Compatibility section. 2. Adjustable to zero with external trim potentiometer. 3. FSR means "Full Scale Range" and is20V for ±1 OV range, 10V for ±5V range, etc. 4. To maintain drift spec internal feedback resistors must be used for current output models. 5. Includes the effects of gain, offset and linearity drift. Gain and offset errors are adjusted to zero at +25°C. 6. Power dissipation is an additionaI100mW, max, when Voo is operated MECHANICAL PIN ASSIGNMENTS ~t+15V. NOTE: ~~~~~~.oo 2' .. [[I] :: PIN I MODELS NO. V MODELS rMSBI BIT 1 BIT 2 BIT 3 BIT4 BIT 5 BIT6 BIT? BIT 8 BITS BIT 10 BIT 11 rLSBI BIT 12 LOGIC SUPPLY, Voo -Vce 'It; ~~';;:::;;::;=;::;;;:::;"~RIl-';>.~I ref.rence only. Numbers • A _ J L-:loJGL ~----..I may not be marked on package. N~ r;;-;;-;mmmm~~-~~_T] OIM 'INCHES MIN MAX MIN MAX 30.86 1.215 30.10 .105 .015 .170 2.67 .021 .060 .100 BASIC . 030 ~ MILLIMETERS 1.185 .035 G Seating Plane OOB .120 03. 4.32 0.53 0.89 1.52 2.54 BASIC 0.76 0.20 0.30 3.05 6.10 .240 .600 BASIC .Q60 l NOTE: Metal Cap connected to ~Vcc internally. lOUT REF. INPUT BIPOLAR OFFSET SCALING NETWORK SCALING NETWORK SCALING NETWORK COMMON +Vee GAIN ADJUST 6.3V REF. OUT CASE: Ceramic MATING CONNECTOR: 0245MC WEIGHT: 8.4 grams {O.30z.1 15.24 BASIC 10° 10° .025 17 • .070 .012 iJ 0.64 3 4 5 6 7: 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BIT llMSBr BIT2 BIT3 BIT4 BITS BIT6 BIT? BIT8 BITS BIT 10 BITII BIT 121LSBr LOGIC SUPPLY, Voo -Vee VOUT REF. INPUT BIPOLAR OFFSET 10V RANGE 20V RANGE SUMMING JUNCTION COMMON +Vee GAIN ADJUST 6.3V REF. OUT 1.52 CONNECTION DIAGRAMS VoMege Model Current Model 10kn 10 IOOkn .VCC NOTES: I. DAC850/851 use a 10M II rallllDr. Thala models can replaca tha DAC85 which ulal an 18MIl rulllDr and \hi DAC87 which UIII a 33M II rallslnr. 2. Pin 160' DAC8501851 II iliad only 10 connactlhl blpollr offill rallllDr. An alllrnal raleronca vollaga may nOi ba usad with DAC850/851. 3. If connactad In .Vec ' which II parmlalbla. powar dlalpallon !ncraaas 75mW Iyp.. 1000Wmax. 4, For '111111 laIIIlng tima connact plna Ig, Ia. Ind 15 IOgathar. 6-192 SETTLING TIME Settling time is the total time (including slew time) required for the output to settle within an error band around its final value after a change in input (see Figure I). DISCUSSION OF SPECIFICATIONS DIGITAL INPUT CODES The DAC850 and DAC851 accept complementary binary digital input codes. They may be connected by the user for anyone of three complementary codes; CSB, CTC, or COB (see Table I). TABLE I. Digital Input Codes. DIGITAL INPUT MSB ~ LSB 1 OOOOOOOOOOOO 011111111111 100000000000 111111111111 ANALOG OUTPUT CTC' Compl. CSB Compl. Straight Binary COB Compl. Offset Binary Compl. +Full Scale +Full Scale Zero -1LSB -Full Scale -LSB -Full Scale +FuliScale Zero +112 Full Scale Midscale -1 LSB Zero Two's 0.003I--R-L +=-1+01-lj~~~::"Ik-++~!lt.l.liooo...--+--+-+-+++I+I 10 100n ~..... ~~Ioo 0.001 .........I.....I......~.I.I.I.....;;. ...I.,;l. . .u.i.u..~'-'~II.I..u.u 10 100 0.1 'Invert the MSB 01 the COB code with an external inverter to obtain CTC code. Settling Time (",sec I FIGURE I. Full Scale Range Settling Time vs Final Value Error Band. ACCURACY Linearity of a 01 A converter is the true measure of its performance. The linearity error is specified over its entire temperature range. This means that the analog output will not vary by more than ± 1/2LSB, maximum, from an ideal straight line drawn between the end points (inputs all "I"s and all "O"s) over the specified temperature range. Differential linearity error of a 01 A converter is the deviation from an ideal I LSB voltage change from one adjacent output state to the next. A differential linearity error specification of ±1/2LSB means that the output voltage step sizes can range from l/2LSB to 3/2LSB when the input changes from one adjacent input state to the next. Monotonicity over the specification temperature range is guaranteed to insure that the analog output will increase or remain the same for increasing input digital codes. DRIFT Gain drift is a measure of the change in thefull scale range output over temperature expressed in parts per million per °c (ppm/"C). Gain drift is established by: I) testing the end point differences at -25°C, +25°C, and +85°C for the DAC850 and at -55°C, +25°C, and + 125°C for the DAC851; 2) calculating the gain error with respect to the +25°C value and; 3) dividing by the temperature change. This is expressed in ppmj"c. Offset drift is a measure of the actual change in output with all .. I "s on the input over the specification temperature range. The offset is measured at -25°C, +25°C, and +85°C for the DAC850 and at -55°C, +25°C, and + 125°C for the DAC851. The maximum change in offset is referenced to the offset at +25°C and is divided by the temperature change. This drift is expressed in parts per million of full scale range per °c (ppm of FSR/"C). Voltage Output Models: Three settling times are specified to ±0.01% offull scale range (FSR): two for maximum full scale range changes of 20V and IOV, and one for a I LSB change. The I LSB change is measured at the major carry (0111 ... 11 to 1000 ... 00), the point at which the worst-case settling time occurs. Current Output Models: Two settling times are specified to ±0.01% of FSR. Each is given for current models connected with two different resistive loads: IOn to loon and 10OO!1. Internal resistors are provided for connecting a nominal load resistance of approximately 1000n for output voltage ranges of ±I V and 0 to -2V. COMPLIANCE Compliance voltage is the maximum voltage swing allowed on the current output node in order to maintain specified accuracy. The maximum compliance voltage of all current output models is +2.5V to -2.5V. POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the 01 A converter output. It is defined as a percent of FSR per percent of change in either the positive, negative, or logic supplies about the nominal power supply voltages (see Figure 2). REFERENCE SUPPLY All models are supplied with an internal 6.3V reference voltage supply. This voltage (pin 24) has a tolerance of ± I% and must be connected to the Reference Input (pin 16) for specified operation. This reference may be used externally also. The external current drain is limited to sourcing 2.5mA up to +85°C and I rnA up to + 125°C not including current required by the bipolar offset circuit. 6-193 An external buffer amplifier is recommended if this reference will be used to drive other system components because variations in a load driven from the reference will result in bipolar offset variations.of the DJ A converter. Gain and bipolar offset adjustments should be made under constant load conditions. 5 illustrate the relationship of offset and gainadjlistments to unipolar and bipolar DJ A converter output. +FUll SCALE ~ ~ o ~ 0.01 => :;: Vee ~+Vec ., .E ... ~ g: - c: ~., 0.001 Q. ~ --- 0-- - 0--. (J) Q) c~ ~" ~!i! AllBITS ~.' .... ... lOGIC 1 ,;;;RANGE OF :I .. • ::.. GAIN AOJ. OFFSET AOJ. OFFSET ADJ. TRANSLATES THE LINE 0.000 1 10 I RANGE OF GAIN.ADJ. L "'111t.-o-.,,# f ROTATES THE LINE All alTS lOGIC 0 DIGITAL INPUT FIGURE 4. Relationship of Offset and Gain Adjustments for a Unipolar DJ A Converter. I / ./ u. ~ IVee c---- e a: on I " '" ,,/:":"-T ,.-,,;/ ~ C ~ .<: o '0 ~r- lLSB 100 ~ If / 1k 10k Frequency (Hz) 1M r:::.: 10M FIGURE 2. Power Supply Rejection vs Power Supply Ripple. All BITS lOGIC I " ; c POWER SUPPLY CONNECTIONS For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagrams. These capacitors (I/LF tantalum or electrolytic recommended) should be located close to the case. Electrolytic capacitors, if used, should be paralleled with O.OI/LF ceramic capacitors for best high frequency performance. The metal cap on the toP. of the package is connected internally to -Vee. EXTERNAL OFFSET AND GAIN ADJUSTMENT Offset and gain may be trimmed by installing external offset and gain potentiometers. Connect these potentiometers as shown in the Connection Diagrams and adjust as described below. TCR of the potentiometers should be 100ppmj"C orless. The 3.9MO and IOMO resistors (20% carbon or better) should be located close to the case to prevent noise pickup. If it is not convenient to use these high value resistors, an eq uivalent "T" network, as shown in Figure 3, may be substituted in each case. Figures 4 and 2711110 3.9MIl t,/ " o'./ ROTATES 0 THE LINE All BITS lOGIC 0 OFFSET Offset Adjustment: For unipolar (CSB) configurations, apply the digital input code that should produce zero potential output and adjust the offset potentiometer for zero output. For bipolar (COB, CTC) configurations, apply the digital input code that should produce the maximum negative output voltage and adjust the Offset potentiometer for minus full scale voltage. Example: If the Full Scale Range is connected for 20V, the maximum negative output voltage is -IOV. See Table II for corresponding codes and the Connection Diagrams for offset adjustment connections. TABLE II. DigitallnputJ Analog Output. ANALOG OUTPUT DIGITAL INPUT LSB Aoooooooooob 27ll1m 011111111111 100000000000 111111111111 OneLSB ~ -= .laOIUl ~ ,;l'~ GAIUDJ. FUll SCALE RANGE FIGURE 5. Relationship of Offset and Gain Adjustments for a Bipolar Dj A Converter. MSB 10MIl ,'/ T- BIPOLAR V r'MSB ON RANGE OF OFFSET j ,'iALL OTHERS OFFSET ADJ·l '~L I OFF OFFSET ADJ. /. -FUll SCALE TRANSLATES ~ THE LINE T DIGITALINPUT INSTALLATION AND OPERATING INSTRUCTIONS ~ +FUll .L SCALE /;. RANGE OF ~ GAIN ADJ. IlSB 100k lOll ~ VOLTAGE' 010+1OV +10V CURRENT Oto -2mA *To obtain values for other binary ranges: o to +5V range divide 0 to +i OV range values by 2. ±5V range: divide ±lOV range value. by 2. ±2.5V range: divide ±10V range values by 4. FIGURE 3. Equivalent Resistances. 6-194 +1mA +9.9976V +9.9951V -1.9995mA -{).9995mA +5.0000V o.OOOOV -1.0000mA O.OOOOmA +4.9976V -o.o049V -{).999SmA +O.0005mA O.OOOOV -10.0000V O.OOOOmA +1.000mA 2.44mV 4.88mV 0.488~A 0.488~A Gain Adjustment: For either unipolar or bipolar configurations. apply the digital input that should give the maximum positive voltage output. Adjust the gain potentiometer for this positive full scale voltage. See Table II for positive full scale voltages and the Connection Diagrams for gain adjustment connections. ± IOOppmj"C or less to maintain the output specifications. If exact output ranges are not required. the external resistor is not needed. VOLTAGE OUTPUT MODELS Output Range Connections Internal scaling resistors provided in the DAC850 may be connected to produce bipolar output voltage ranges of ± IOV. ±5V or ±2.5V or unipolar output voltage ranges of o to +5V or 0 to + lOY. See Figure 6. REF. INPUT ~L __ & OFFSET Internal resistors are provided to scale an external op amp or to configure a resistive load to offer two output voltage ranges of ± I V or 0 to -2V. These resistors (Ru) are an integral part of the DAC850j851 and maintain gain and bipolar offset drift specifications. If the internal resistors are not used, external RL (or RF) resistors should have a TCR of ±25ppmj"C or less to minimize drift. This will typically add ±50ppmj"C plus the TCR of RL (or RF) to the total drift. @COMMON FROM WEIGHTED RESISTOR NETWORK 2.35mA ±25% FIGURE 8. Current Output Model Equivalent Output Current. ---Jo~·~~._n_ _ _ _r,';\ BIPOlAR n~ I oTO OUTPUT RIllstor toilranCl1 ±25% FIGURE 6. Output Amplifier Voltage Range Scaling Circuit. Gain and offset drift are minimized because of the thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are shown in Table III. Settlingtimefor a full scale range change is specified as 3/Lsec for the 20 volt range and 2.5/Lsec for the 10 volt range. Driving a Resistive Load Unipolar A load resistance, RL = Ru + Rl.s, connected as shown in Figure 9 will generate a voltage range, VOUT, determined by: RL x 7.2kn) VOUT = -2.35mA ( RL + 7.2kn TABLE III. Output Voltage Range Connections - . Voltage Model. Digital Connect Connect Connect Input Codes Pin15to Pin 17 to Pin19to 15 ±10 COBorCTC 19 20 NC COBorCTC 18 20 ±5 COBorCTC 18 20 20 ±2.5V 18 21 NC o to+1OV CSB 21 20 CSB 18 Oto+5V Output Range Connect Pin 16to 24 24 24 24 24 }------4t)+ 'OUT CURRENT OUTPUT MODELS The equivalent output circuit and resistive scaling network of the current model differ from the voltage model and are shown in Figures 7 and 8. An external Rl.s resistor is required to produce exactly 0 to -2V or ± I V output. TCR of this resistor should be REF. INPUT ~~~k!~ & - -..~-& t:;\. 2.66kn FIGURE 9. Current Output Model Equivalent Circuit Connected for Unipolar Voltage Output with Resistive Load. To achieve specified drift. connect the internal scaling resistor (Ru) as shown to an external metal film trim resistor (RLS) to provide full scale output voltage range of o to -2V. Tolerances on internal equivalent resistors are wide. RLS will have to be selected for each unit. t.7~lkn l' ~J 4.2~; 18 @ RllllIOr tolerance. ~ 20 FIGURE 7. Internal Scaling Resistors. Driving a Resistive Load Bipolar The equivalent output circuit for a bipolar output voltage range is shown in Figure 10, RL == Ru + RLs. VOUT is determined by: 6-195 Output Larger Than 20V Range For output voltage ranges larger than ±IOV, a high voltage op amp may be employed with an external feedback resistor. Use IouI' values of ± 1.175mA for bipolar voltage ranges and -2.35mA for unipolar voltage ranges (see Figure 12). Use protection diodes when a high voltage op amp is used. The feedback resistor, RF, should have a temperature coefficient as low as possible. Using an external feedback resistor, overall drift of the circuit· increases due to the lack of temperature tracking between RF and the internal scaling resistor network. This will typically add 50ppm/"C + RF drift to total drift. V ,.=±1.I75mA(RI.X3.17kO) OUI RI. + 3.17kO }-----o+ FIGURE 10. Current Output Model Connected for Bipolar Output Voltage with Resistive Load. To achieve specified drift, connect the 1.71 kO and 2.55kO internal scaling resistors in parallel (RI.I) and add an external metal film resistor (Rl.s) in series to obtain a full scale output range of ± I V. The tolerances on the equivalent internal resistors are wide. Rl.s will have to be selected for each unit. Driving An External Op Amp The current output model will drive the summingjunction of an op amp used as a current-to-voltage converter to produce an output voltage (see Figure II). VOUT = louT X R" where louT is the output current and RF is the feedback resistor. Using the internal feedback resistors of the current output model provides output voltage ranges the same as the voltage model. To obtain the desired output voltage range when connecting an external op amp, refer to Table IV. *Flr ..\paI valllll'Wlna' up ID 140V II-P. FIGURE 12. External Op Amp - Using External Feedback Resistors. LOGIC INPUT COMPATIBILITY DAC850 and DAC851 digital inputs are LSTTL compatible as shown in the specification table when V"" is operated over 4.5 to 16.5 volts. Figure 13 illustrates using CMOS hex buffers with DAC850 to provide CMOS input compatibility. This combination will operate together over a wide range of logic power supply Voltages. 4.26kll 426kll 0 VOUT I DID 2.35mA OF.. lullll\llna a_. FIGURE II. ExternalOp Amp - Using Internal Feedback Resistors. TABL.E IV. Voltage Range of Current Output Dj A Converter. Output Range Digital Input Codes ®nect ±10V ±5V ±2.5V oto +10V oto +5V COB orCTC COBorCTC COBorCTC CSB CSB 19 18 18 18 18 A to Connect Connect Pin 17to Pin 19 to 15 15 15 21 21 0NC 15 NC 15 Connect Pin 16to 24 24 24 24 24 FIGURE 13. Using DAC850j851 with CMOS Hex Buffers Over a Wide Range of Logic Power Supply Voltages. ORDERING INFORMATION DAC8S0 DAC851 -xxx -xxx -x -x D/A Converter Family Input Code CBI= Complimentary 12-Blt Binary Output V = Voltage Example: DAC851-CBI-V 6-196 I = Current BURR-BROWN@ MP10 MP11 IElElI Microprocessor-I nterfaced 8-BIT ANALOG OUTPUT SYSTEM MP10. MP11 BLOCK DIAGRAM ADDRESS ~~IER~I~:r~~~OI t { t ADDRESS DECODER All ti2 1 AD Al R/W ¢21MP11l I of 2 DECODER .nd Write Control logic 1 STROBE STROBE 1\ V 07 liD L A T C H IIIIIl O/A CONVERTER ANALOG OUTPUTS '---l 1\ Y L A T C" H ODD O/A CONVERTER FEATURES • USE AS ANALOG INPUT AND OUTPUT • EASY TO USE Completely compatible with most microprocessors No external logic required Timing compatible Memory-mapped • SAVES DEVELOPMENT MONEY AND TIME • COMPLETELY SElF-CONTAINED • COMPATIBLE WITH: BoBo (lntell 9080A (AMO) Z-8o (Zilog) 6800 (Motorola) 8008 (lntell F-8 (Fairchild) SC/MP (National) 650X (MoS Technology) International Airport Industrial Park· P.O. Box 114110· Tucson. Arizona 85734· Tel. 16021 746·1111 • Twx: 910·952·1111 . Cable: BBRCORp· Telex: 66·6491 PDS-363A 6-197 DESCRIPTION connected to the address bus of an 8080 or 8008. All other input lines require standard TTL voltages. The address lines A2 through An and B2 of the MPII are LSTTL compatible so they can be directly connected to the address bus of a 6800 or 650X. All other input lines require standard TTL voltages but are high impedance . and require only microamp drive currents. These microprocessor peripherals provide an analog. interface compatible with most microprocessors. The MPIO and MPH are electrically and functionally microprocessor-compatible in static or dynamic situations. . These units are complete analog systems packaged in 32pin triple-wide dual-in-line packages. They contain two 8-bit D/A converters which are internally trimmed for gain and offset so that no external trimming is required. All necessary interface, timing and address decoding logic is also included. The MPIO is designed to be used with 8080A and 8008 type microprocessors. It can be used with SC / MP if pullup resistors are added to the address bus, with the F-8 Dynamic or Static memory interface chip if the. RAM WRITE signal is a minimum of 430nsec and with the Z-80 iftw (4)H) = ~ (4)L) = 500nsec. The MPII is designed to be used with 6800 and 650X type microprocessors. THEORY OF OPERATION When programming these peripherals, the user treats them as memory. Because the D / A converter input is an 8 bit word, one 8 bit memory location is required for each channel. Since these units are treated as memory, a single instruction is all that's needed to write to an output channel. For instance, when the MPIO is used with an 8080, a single instruction, SHLD, can be used to output data to both D / A converter channels from the Hand L register pair. Likewise, when the MPII is used with the 6800 or 650X, a single STX instruction can be used to output data to both D / A converter channels from the index register. The MPIO and the MPII require an initialization as would any programmable peripheral. The address lines A2 through An, B2 and B3 of the MPIO are CMOS compatible so that they can be directly MP10, MP11 BLOCK DIAGRAM ADDRESS D~TERMIINATIDN B2 B3 (MP10) t Ap 112 ...... ...a:: ... C( I- ~ a:: Q en en ...... H ~ AO A1 RJW 4>2 (MP11l ADDRESS DECODER 1 1 of 2 DECODER and Write Control Logic 1 STROBE STROBE Q a:: a.. Q ...iiia:: ~7 DO t ~ ,J IV L A T C H D/A .... CONVERTER ANALOG OUTPUTS ~ ~ V 6-198 L A T C H I11III D/A CONVERTER ELECTRICAL SPECIFICATIONS (Typical at 25"C and rated supplies unless otherwise noted.) MP10/MP11 MP10/MP11 ANALOG OUTPUT DIGITAL INPUTIOUTPUT All signals compatible with the microprocessor bus An analog output channel selected by: Input data bits read by: 2 ±IOV In Number of analog outputs Output voltage Tange Output impedance Output settling time lSpsec AO 00-D7 POWER REQUIREMENTS +SVDC ±S% al 90 rnA +lSV ±3% al 30 rnA -ISV ±3% al 30 mA TRANSFER CHARACTERISTICS Resolution TEMPERATURE RANGE 8 bit binary (complementary binary) 78.lmV ±o.4% FSR 11 • 21 One LSD Throughput accuracy (max) Throughput accuracy (typtcal) Temperature coefficient of accuracy. IfCl07lfC -5S·C 10 +8S·C Operating temperature range Storage temperature range ±0.2S% FSR ±0.OO8% FSR re- I. FSR is Full Scale Range = 20V. 2. Accuracy components are: LlOearity Error = ±O.2o/c FSR; Gain Error = ±O.lo/c FSR. Offset Error = ±O.I% FSR. MECHANICAL SPECIFICATIONS Pm numbers shown for reference onLv_ Numbers may not be marked on Pilckaga. 0000000000.00000 f Ia' 17 ~ I. -~~ooooooooooo INCHES MAX MIN MILLIMETERS MIN MAX 1.700 1.760 43.18 44.70 1.120 1,160 28.45 29.46 .170 4.32 5.84 D .018 .230 .021 0.46 0.53 0.89 G .035 .050 . laO BASIC .110 .130 2.79 3.30 .150 .250 3.81 6.35 A N OTE' LE ADS IN TRUE POSITION W'''I-IIN .01 0" (.25mm)R@MMCATSEATINGPLANE . B 1 DIM C ·K .900 BASIC 1.27 2.54 BASIC 22.86 BASIC .002 .Q10 0.05 0.25 .1tO .130 2.79 3.30 MATERIAL: Cerami< WEIGHT: 14 grams (O.S OZ) PINS: Pin material and plating composition conform to Method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2). MATING CONNECTOR: 2302MC (Set of IWO. l6-pin '!rips) PIN CONNECTIONS 8080 Pin Connections I 2 3 4 5 6 7 8 9 10 12 18 26 25 - IAIO 2 Common 304 4 05 5 06 6 07 7 03 8 02 MPIO 901 10 00 ~ II Reset 12 R/W 13 Al 14 AO 15 +ISVDC 16 -ISVDC All 32 AI3 31 AI2 30 A 9 29 A 8 28 A 7 27 A6 26 A 5 25 A 4 24 A 3 23 A 2 22 B 2 21 B 3 20 +5V 19 Out I 18 Out 2 17 8080 Pin Connections 40 38 37 35 34 33 32 31 30 29 27 6800 Pin Connections - 8 37 9 10 20 II 12 13 14 15 16 17 18 - f9 - - - 20 6-199 6800 Pin Connections I 2 3 4 5 6 7 8 9 10 11 12 13 14 IS 16 Output I Output 2 +SVDC Enable AO Al A2 A3 A4 AS A6 A7 A8 A9 AIO All -lSVDC +lSVDC R/W Reset 00 01 02 03 MPII 04 lIDO D5 06 07 Common B2 A13 AI2 -- 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - -34 40 33 32 31 30 29 28 27 26 21 - 23 22 .1-- TWp~ \ RtW _TWO I-TDW-I 07 ) DO ::I I TAW TWA "I ~ Address AU - A? K= L TCW I'll INTERNAL TOMPIO·_ TWC "I r- - I. j.-TAC TAC- I OUTPUT INTERNAL TO MPIO ) I TWB xt .1 " : ANALOG OUTPUT Symbol Min TWp TOW TWO TAW TWA TWD TWC TWB TAO TAC 430 100 65 620 35 30 35 Max --- ns ns ns ns ns ns ns ns ps ns -635 -16 25 600 - ,- Units TAO (analog otuput data stable) FOR THE 8080 ITSELF TAW TAW =2tcy - tD3 - tR42 = 670ns Min 140ns FIGURE 1. MPlO Timing Diagram. I'!::.TE~ "'j\VSS+ 2.4V 0.4V J Enable = tl2 Address AI3 - A~ --.l J t- 1- .. TAEW. 2.4V 0.4V TWE...., Read/Write I- \ 0.4V - D~ta BU!J 2.4V I 0.8V !-THW ~~VK DO-D7 ~~ TpDW _ Peripheral Data - INTERNAL TO MPII I+- )d - ANALOG OUTPUT TAO (analog otuput data stable) Symbol Min Max 0.450 25 jI.S TAEW ·180 - ns TDSU 300 TWE 130 THW 10 - Unit ns ns - ns TPDW - 1.0 ps TAO 17 25 jI.S O.4V 2.4V 0.4V I TE 2.4V FIGURE 2. MPll Timing Diagram. 6-200 PROGRAMMING DATA = 80 Loads initialization data (80,,) to initialization address MVI M. DATA; These units are easily programmed since all are treated as memory locations. They use any memory reference instruction that can write data from internal registers or the accumulator. A single instruction can be used to write data to one or both channels. When the MPIO is used with an 8080, a single SHLD instruction referenced to the lower of the two addresses will automatically transfer the data in the H register to DACI and the data in the L register to DAC2. An ST A instruction will transfer the data in the accumulator to either DAC. When the MPII is used with a 6800, a single STX instruction referenced to the lower of the two addresses will automatically transfer the eight upper bits of the index register to DAC I and the eight lower bits to DAC2. An STAA instruction will transfer the contents of the accumulator to either DAC. Of course, if direct addressing is not desired. MOV instructions may be used to transfer data from internal registers to a specific DAC memory location. As with any programmable peripheral, the M P 10 and M P II must be initialized. The initialization sequence assigns internal registers to function as input registers for the Dj A converters. Now data can be written into the MPIO. This is accomplished by outputting the correct MPIO address: --- a I a 0 0 User Defined OUTPUT I a a 0 User Defined OUTPUT 2 The B, and B, inputs determine the address to which the M PIO will respond. Thefour memory locations which are possible are outlined below: MP10 INITIALIZATION The RESET input controls the status of the control register of the M P I O. An active high on this line will reset the control register to all "zeros". The M P 10 will require initialization every time RESET is activated. If RESET is connected to ground, the MPIO must be initialized only once before output of the data. Bz 0 0 B, I I 0 0 I I Az 0 0 I I A3 0 I 0 I At the time that the address appears on the address bus, data will appear on the data bus and a RjW pulse will be generated by the microprocessor. After 25~sec, the analog voltage will be stable at the selected output. Timing requirements shown in Figure I must be satisfied in order for the MPIO to be initialized and operate correctly. These timing requirements are completely compatible with the 8080. MPIO INITIALIZATION SEQUENCE: I. Load initialization address 2. Load initialization data MPIO INITIALIZATION ADDRESS: MP11 INITIALIZATION x -- The RESET input controls the status of the control and peripheral registers of the M P II. The initialization sequence will differ if RESET is connected to a master reset line of a microprocessor or if it is hard-wired to V". The MPII will require initialization every time the RESET line is activated low. If the RESET line is hard wired to V", the MPII must be initialized only once before output of the data is attempted. a a X I User Defined X = don't care, not connected to MPIO I = True MPIO INITIALIZATION DATA MPII ADDRESS STRUCTURE o o o o o o A" AI4 An All All AIO A. As A7 A. A, A. A, A, Al Ao XX .10aYY For 8080 the sequence may look as follows: ADDR ,,; Initialization address LXI H, ADDR; AI" AI4 - don't care, not connected to MPII A, - Address is user selectable Au, Al - Addresses control the initialization sequence Loads H & L registers with initialization address 6-201 Initialization sequence when RESET is hard wired to V,,: I. Load accumulator with "zeros" 2. Store accumulator at memory locations: AI,AI4A13AI2AlIAIO A. A. A, A. A, A4 A, A2 AI Ao XXIIII 10al0 AI,AI4A13AI2AlIAIOA. A. A, A6 A, A4 A, A2 AI Ao XXIIII I 1IIIIOal1 Address of Control register A Address of Control register B 3. Load accumulator with "ones" 4. Store accumulator at memory locations: AI,AI4A13AI2AlIAJOA. As A, A. A, A4 AJ Al AI Ao XXllllllllllOaOO XXllllllllllOaOI XXllllllllllOalO X X I I I I I I I I I lOa I I Address Address Address Address of Peripheral register A of Peripheral register B of Control register A of Control register B For the 6800 this sequence can be written as follows: LDAA STAA STAA LDAA STAA STAA STAA STAA Or as: LDX STX LDX STX STX "zeros" Address Address "'ones" Address Address Address Address of control register A of control register B of peripheral register A of peripheral register B of control register A of control register B # $0000 $ Address control register A # $1111 $ Address peripheral register A $ Address control register A Initialization sequence when REm line is connected to master reset (control registers A and B are al~ays set to zero after master reset and only ones need to be stored in the registers): LDAA STAA STAA STAA STAA zero's in index register zero's in C.R. A and B one's in index register one's in P.R. A and B one's in C.R. A and B OUTPlJT I OliTPl" 1 At the time that the address appears on the address bus, data will appear on the data bus, and if the RjW and Enable pulses are correctly timed, 251'sec from the true address the analog voltage will be stable at the selected output. Peripheral register A Peripheral register B Control register A Control register B Timing requirements shown in Figure I must be satisfied for the MPII to be initialized and opeiate correctly. All timing requirements are completely compatible with 6800 microprocessors. User definable address line A2 used in conjunction with the B2 input 1l1l0ws the user to place the MPII in two different memory locations .or use two different M P II's in order to expand the analog system'to four outputs. When B, is wired to logical I, the M P II responds t.o an A2 address of 0 and when B, is wired to a logical 0, the M P II responds to an A, address of I. or as: LDXX STX STX Loads Stores Loads Stores Stores XXIIIIIIIIIIOaOO XXIIIIIIIIIIOaOI "ones" Address Address Address Address Loads Zeros in accumulator Stores zero's in C.R.A. Stores zero's in C.R. B Loads one's in accumulator Stores one's in P.R.A Stores one's in P.R.B. Stores one's in C.R.A Stores one's in C.R.B # $1111 $ Address Periphera1 register A $ Address Control register A Now data can be written into MPII. This is accomplished by outputting the correct MP II address: 6-202 TEST PROGRAMS The test circuit and test programs following allow the user to test the operation ofthe MP 10 or MP II. The test may be conducted by setting up the MPIO/MPII as shown in Figure 3. The microprocessor system should have a teletype/CRT terminal interface. The programs will step through several output voltage levels for each DAC output (see Figure 4). Notice how the software is different for the two test programs to illustrate two software approaches. Store the following codes in memory beginning with location ADDR X: ADDR X - FF ADDR X + 1- BF ADDR X + 2 -7F ADDR X + 3 - 3F ADDR X+4 - 00 ADDR 2 is the address of output I, ADDR 3 is the address of output 2: MPII Test Program LDX STX JSR LDX STX JSR LDX STX JSR LDX STX JSR LDX STX JSR LDAA r-;:::""~.., DACI OUTPUT MP101 MPll tJ.P System DVM DAC2 L-....,..,-..... OUTPUT FIGURE 3. Test Circuit for MPIO/MPII. INP MPIO Test Program LOOP I LOOP 2 Initialize MPIO LXI H ADD R X Address of the first byte of data. MOV A, M Load ACC with flTSt byte of data. STA ADDR2 Output to MPIO DACI INX H Increment ADDRI CALL CI Call Input routine CPI Wait for any character 8D except carriage return JNZ LOOPI LXI ADDR X [~T~VA'i;~3 Output to MPIO DAC2 INX H Increment ADDRI CALL CI ~ CPI Wait for any character 8D except carriage return JNZ LOOP2 RET Bit A #01 BEQ INP LDAA ADDRX+ I CMP A 8D BNE Back JMP Return BACK RTS Initialize MP II Load index register Store FF in each DAC Load index register Store BF in each DAC Load index register Store 7F in each DAC Load index register Store 3F in each DAC Load index register Store 00 in each DAC Lood Sbtm of ACIA I W~ ,TTY input L~~b From ACIA} Jump back to test program or return to main program The MPII test program will output -IOV from both DACI and DAC2 then wait for an input from the TTY. Any character except CR will advance both DAC's of the MP II to the next value as defined in Figure 4. CR terminates test program by jumping to RETURN. ADDR 1 is the address of output I, ADDR X is the address of the ACIA. Step I The MP I 0 test program will output five different voltages from DACI and then from DAC2 (see Figure 4). DACI will initially output -lOY. To step through the other values for DACI enter any character other than carriage return (CR). To transfer control to DAC2, enter CR. DAC2 will output -lOY. To step through the other values for DAC2 enter any character except CR. To exit the test program, enter CR. # $ FFFF; ADDR I; INP # $ BFBF; ADDR I; INP # $ 7F7F; ADDR I; INP # $ 3F3F; ADDR I; INP # $ 0000; ADDR I; INP AD DR X Ideal Output -IOV Actual Output Limits -9.922V to -10.078V 2 -5.0V -4.922 to -5.078 3 O.OOOV -0.078 to +0.078 4 +5.0V +-4.972 to +5.078 5 +9.922V +9.844 to +10.000 FIGURE 4. Output Voltages for Test Programs. 6-203 • Reprinted [rom Ekt.'lronic.l. July 6. 1978. Copyright @ Me Graw-Hill. Inc., 1978. APPLICATIONS FLOWCHART USING 8080 and MP10 ANALOG INPUT AND ANALOG OUTPUT Although the MPIO and MPII are analog output peripherals, they can be easily adapted to provide both analog inputs and outputs. With (he addition of a few external components. these units can each provide one analog input and one analog output for your system as shown· below: MP10 ANALOG INPUT/OUTPUT II ADDRESS BUS 8080 8255 PPA System Il ~.t ~J. r- IIDII MPIO IMel Oul I>A('I CO Oul I l J DATA BUS +15VDC I Analog - Output - -15VDC ~ LM111 Comparator _ }iOkf! J Analog Input 10k!} (A· =0) MP11 ANALOG INPUT/OUTPUT II ..J..J- 6800 System lI ....-lJ - ADDRESS BUS r- PIA 6820 INo OUI DI\('I OUI J I L DATA BUS FLOWCHART USING 6800 and Mf>11 Analog Output MPll DAn - I +15VDC~ LM111 Comparator _ +l fl5VDC 10kSl'· 10k!} ,Apalog Input These systems use the microcomputer system to perform the logic of a successive approximation AID converter;using one channel of the MPIO or MPII to provide the Dj A converter reference function required. In a successive approximation converter:the analog input is compared to known outputs of a 0/ A converter. First,. the microcomputer turns the MSB on. waits for the settling time o(the MPIO or MPI I. and the switching time of the comparator, then reads the status. If the comparator indicates that the MSB voltage is smaller than the analog input. the MSB input to the MPIO/MPII stays "on" and the next most significant bit is turned on. If the comparator indicates that the MSB value is larger than the analog input, the microcomputer will turn the MSB "ofr and turn "on" the next most significant bit. In this way all '8 bits ofthe 0/ A converter are tested, When the conversion is complet~. the input of ,the 0/ A converter will be a digital representation of the analog input. This v~lue will also be stored .in the microprocessor's accumulator (complementary binary). Low The A/O conversion will require approximately 900 microseconds when performed in this manner. Burr-Brown will shortly have available a detailed application note describing this process including all software required. * Enter if MPI O/MPII and syst~m PPA/PIA were initialized previously 6-204 BURR-BROWN® MP20 IElElI Microprocessor-I nterfaced 8-BIT DATA ACQUISITION SYSTEM FEATURES • COMPATIBLE WITH: BOBOA BOB5 B008 B048 l-80 SCIMP • EASY TO PROGRAM Choice of ways to interface: Memory-mapped or 110 mapped Only one instruction to acquire data • EASY TO USE Completely compatible with aOBOA microprocessors PPA is not needed No external logic needed No external adjustments Low or high level analog inputs Unlimited expansion • COMPLETELY SELF-CONTAINED • LOW COST • SAVES DEVELOPMENT TIME AND MONEY International Airporllndustrial Park - P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746·1111 - Twx: 910-952·1111 - Cable: BBRCDRp· Telex: 66-64111 PDS-37IA 6-205 DESCRIPTION The MP20 is a complete analog input system packaged in an 80-pin quad-in-Iine package. It is completely compatible with 8080A and 8008 microprocessors. It is also compatible with SC/MP and with the Z-80. The MP20 contains a high speed 8-bit AID converter, an instrumentation amplifier, an input multiplexer that can accept up to 16 single-ended signals or 8 differential signals as well as interface, timing and address decoding logic. The gain and offset are internally laser trimmed so that no external adjustments are required on the ±5V or 0 to +5V input range to obtain an absolute accuracy of better than ±o.4% (I LS8). The system can digitize low level or high level analog signals. The gain of the internal instrumentation amplifier can be programmed with a single external resistor to allow input signal ranges as low as ±IO. mY. This means that the MP20 can be connected to low level sensors such as thermocouples and strain gauges without external signal amplification. The address lines AO through Al5 are low power. Schottky TTL compatible and can be connected directly to the address bus of an 8080A or 8008. All digital input lines require standard LSTTL voltages. PROGRAMMING When programming these peripherals, the user treats them as memory. Each analog input channel occupies one memory location. Any memory reference instruction can be used. Since most microprocessors have been optimized for memory usage, memory reference instructions are the most powerful instructions in a microprocessor's repertoire. The MP20 is treated as memory to simplify software and allow an almost unlimited number of systems to be connected to a single processor. Pins A4 to Al4 are made available so that the microperipheral address can be hardwired for almost any possible memory location. Since these units are treated as memory, a single instruction is all that's needed to read an input channel. For instance, when the MP20 is used with an 8080A, a single instruction, LHLD, can be used to input data to the Hand L registers from two consecutive analog inputs. Likewise, a single LDA or MOV instruction will input data from one channel to the CPU. ANALOG INPUTS . MP20 BLOCK DIAGRAM oj ~ "cc . 0_ """.,.W)I()r-. o _N to) ~ III 1100._ ............ _ ~! !~!~!! is!~!!!!!i < 0 AO AI A2 ...,r!l Latch A3 A4 77 AS A. A7 A8 A. AIO AU All AI3 AI4 A" gj '~" C ~ MUXOUT HI Address Decoder I- ~ Ali X§" An AI4 fi1 } GAIN ADJUST MEM'R .. g a {RESET 0 DDIN ENABLE 0 ,. READY Q" 3 0 ~:;, U., Control Logic Status !{ lAIN LO Sele(.~ IH E-

Vn , 10 II STABILITY OVER TEMPERATURE System accuracy drif{') (max) linearity (max) Monotonicity (O"e to +70"C) ±40 ppm/"C ±20 ppmrC Guaranteed DIGITAL INPUT/OUTPUT All signals are compatible with Microprocessor bus Output coding Logic loading Output drive (DO - D7) An analog- input channel is selected by: The output data bits are read into: Binary or Binary two's complement AU digital inputs are one LSTTL load 5 TIL loads or 20 LSTTL loads AO- A3 DO- D7 POWER REQUIREMENTS Rated voltages Range for rated accuracy Supply drain ±15V +5V ±15V, +5V 4.75 to 5.25 and ±14.5 to ±15.5V ±30mA TEMPERATURE RANGE +9OmA O'C to +70'C (I) Includes 35~sec for mux and amplifier settling time and 51-'sec for ADC conversion time. (2) (3) (4) (5) (6) (7) REX,. is the resistance between pins I and 3. With power applied. Gain = 2. with no external adjustments. FSR is Full Scale Range (FSR is 10V for ±5V range). Gain = 100 with external gain and offset trim. Includes gain drift. offse~ drift and linearity drift. 6-207 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 IA GAIN ADJUST IA IN HI IA GAIN ADJUST MUX OllT HI IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN I IN 0 MUX ENABLE I MUX ENABLE 2 SIN. DIF AO AI A2 A3 A4 A4 A5 A5 A6 A6 A7 lIT A8 A8 A9 A9 AIO AIO All AIT AI2 ill AI3 AI3 ADDR DECODE OUT Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 AI4 ill AI5 MEMR DBIN ENABLE Rffii' READY DELAY ADJ +5V DIG. COM OUTPUT SELECT D7 (MSB) D6 D5 D4 D3 D2 DI DO (LSB) -15V +15V COMP IN ANA. COM Bro R2 RI IAOUT IN 8 RET 0 IN 9 RET I IN 10 RET 2 IN II RET 3 IN 12RET4 IN 13 RET 5 IN 14 RET 6 IN 15 RET 7 MUX OUT LO OFFSET NULL IA IN LO OFFSET NULL PIN FUNCTIONS IA GAIN ADJUST (Optional). Pin I and Pin 3. By connectirg a resistor between pin I and 3 the gain of the internal instrumentation amplifier can be varied as follows: Gain = 2+ SOkll/R where R is t he gain setting resistor. The I A is factory adjusted for a gain of 2 without any external resistor. Important: If a gain greater than lOis required an external capacitor must be connected from "DELAY" (pin 49) to +SV. This increases an internal delay to allow for the increased settling time of the instrumentation amplifier. IA IN HI Pin 2. This is the positive input of the internal instrumentation amplifier. This should be connected to pin 4 (MUX OUT HI) for normal operation. MUX Pin 4. This is the high output of the analog OUT HI input multiplexer. This is connected to pin 2 (lA IN HI) for differential operation. It is connected to pin 77 (MUX OUT LO) and pin 2 for single-ended input operation. IN7- INO Pins S - 12. The first 8 (of 16) analog inputs for single-ended operation or the 8 positive inputs for 8 channel differential input operation. MUX Pin 13. Leave open for single-ended input ENABLE I operation. Connect to pin 14 (MUX ENABLE 2) for differential input operation. Pin 14. Connect to pin IS (SIN/DIF) for MUX ENABLE 2 single-ended input operation. Connect to pin 13 (MUX ENABLE I) for differential input operation. SINjDIF Pin IS. Single/ Differential input operation connect to pin 14 (MUX ENABLE 2) for single-ended operation. Leave open for differential input operation. AO-A3 Pin 16 -19. Address lines that select one of 16 analog input signals (I NO - INIS). 0000 selects channel 0 and IIII selects channel IS when the correct address is presented to the MP20. Connect A3 to ground for 8 channel differential operation. A4 - AIS Address lines. Pins 20, 22, 24, 26,28 30, 32, 34,36,38,41, and 43. When the proper address is presented to the MP20 in addition to the MEMR (pin 44) pulse, the conversion is initiated. Address select lines. Pin 21, 23,.2S, 27, 29, 31, 33, 3S, 37, 39 and 42. By connecting these lines to DIG COM or +S volts (through a I kll resistor) almost any address can be assigned to the MP20. For example if A4 is connected to GND., the correct (valid) address for A4 is a "I" (> + 2.0). ADDR DEC Pin 40. A positive pulse will appear when a valid address appears on the M P20 address lines and MEMR (pin 44) is low. The rising edge of this pulse strobes the input channel select information (AO - A3) into a latch. It can also be used for external purposes. Pin 44. Memory read. A "Low" pulse on this line along with a correct address will enable DO - 07 (data lines). Also used to initiate a conversion. DBIN Pin 4S. Connect to DBIN on 8080. ENABLE Pin 46. Enables MP20 output. Connect to ground for normal operation (see figure 7). RESET Pin 47. A "Low" on this line is required to RESET the MP20. Connect to RESIN input of the system's 8224 or invert 8080's RESET input. Pin 48. When the MP20 is "Read" by the READY microprocessor, the READY line will go "Low" until conversion is complete. If the READY line is used to halt the CPU, the 8080 will enter a "Wait" state (Tw) until the multiplexer, instrument amp, and A/D converter have completed converting the analog data to a binary 8 bit code (40 f.lsec with gain ~ 10). The READY line will then return to its "High" state which releases the processor from the Tw state. The output data appears on the data bus (DO - 07) during the T 3 state. DELAY ADJ Pin 49. When the MP20 is addressed, an internal delay of approximately 3Sf.lsec is initiated to allow for multiplexer and instrumentation amplifier settling time. When the IA is operated with gain> 10 this delay must be increased (see figure 4 and figure S) to allow for the increased settling time of the IA. +SV Pin SO. +S volt at 140 rnA maximum, 90 rnA typical. Pin SI. Digital common. This pin should DIG COM be connected to analog common (pin 64) as close to the MP20 as possible for optimum perforinance. OUTPUT Pin S2. This pin should be connected to SELECT DIG COM to obtain binary data at DO D7. To obtain two's complement data (bipolar mode) connect pin S2 to +SV through a I kO resistor. 07 - DO Pin S3 - 60. 8 bit data bus; Tri-state low power Schottky TTL compatible. MEMR 6-208 -15V +15V COMP IN Pin 61. -IS volt at 30 rnA typical. Pin 62. + IS volt at 30 rnA typical. Pin 63. Comparator input of S bit AID converter (successive-approximation). Leave open for unipolar operation or connect to "BPO" (pin 65) for bipolar operation. NOTE: This point is extremely sensitive to noise. Any conn~ction to this line should· be as short as possible and shielded by ANA COM or ±15 volt supply patterns. ANA COM Pin 64. Analog common should be connected to digital common (pin 51) as close to the MP20 as possible for optimum performance. BPO Pin 65. AI D converter bipolar offset. It should be connected to ANA COM (pin 64) for unipolar operation of COMPIN (pin 63) for bipolar operation. R2 Pin 66. AI D converter input resistor. Connect to IA OUT (pin 6S) for 0 to +5V input unipolar operation or ±2.5V input bipolar operation. Leave open for ±5V input bipolar operation. F RI Pin 67. AID converter input resistor. Connect to IA OUT for ±5 volt operation. IA OUT Pin 6S. Instrumentation amplifier output. Connect to Rl (pin 67) or R2 (pin 66) for normal operation. INS - INI5 Pin 69 -76. Analog inputs S through 15 for RETO-RET7 single-ended operation or analog returns 0 through 7 for differential input operation. MUX Pin 77. Multiplexer output for OUTLO INS - INI5 RETO-RET7 Connect to "MUX OUT HI" (pin 4) and "IA IN HI" (pin 2) for single-ended input operation or connect to "IA IN LO" (pin 79) for differential input operation. Pin 7S, SO. Optional instrumentation OFFSET amplifier offset adjust (see figure I). NULL IA IN LO Pin 79. Negative input of instrumentation amplifier. Connect to ANA COM (pin 64) for single-ended input operation or "MUX OUT LO" (pin 77) for differential input operation. M4 Machine Cycle 1. X"""L_-_-_-_-_ _ OL D DATA (Pr.vi~s ;-on-;.,:;io-;;) NEW DATA ~---~~-----~- D7-DO MEMR ADDRESS DECODE~R~_ _ _ _ _ _~~ ___________~~tAD ----·--~f~--------~\L--------~- READY DBIN tENABLE tREADY-------- All waveforms shown are for an 8080A - I microprocessor operating at: CLOCK PERIOD (tCY) = 320 ns INSTRUCTION CY(lLE = 1.3 j.lS '1 and'2 clock signds are shown for reference only. They are not required for operation of MP';!O. MP20 Timing Diagram Normal Operation (LOA Instruction using READY to stop microprocessor during conversion)_ 6-209 M4 Machine' Cy·cle I 'I . • 1 - - -:- X__ M.!'2!!A.QD~E~S _ _ _ _ _ _ _ _ _ _ ~ ......--'"T""-~---""T-"""T-......,r---f 11.15 - AO SYMBOL D7-DO \~-----~/ ADDRESS DECODERl_ _ _ _ _ _ DBIN ~____ j r - - - - - - - - - - , \ _____ ~. ------~------~--/ \ PARAMETER MIN MAX UNIT . Delay from MEMR to ADDR. DEC. 2S ns Delay from MEMR and correct address to READY 100 ns Delay from READY toj,. 90 ns Output Data stable from DBIN 40 ns Conversion time (READY low) 40 ~s The LDA Instruction will "READ the data from the previous conversion and start a new conversion. The ne~ data can be read in 40 IJS (max). CAU.TION: Do not read the MP10 while a conversion is in progress or an erroneous, outp~i:. m~y result. MP20 Timing Diagram (LOA Instruction without stopping microprocessor during conversion). OPERATING INSTRUCTIONS PROGRAMMING The MP20 is easily programmed since it is treated as memory. It uses any memory reference instruction that can read data. A single instruction can read data from one channel (LDA) or two adjacent channels (LHLD): Example: MP20 used with.an 8080. MP20 base address· FF70; acquire dataTrom channels FF70 through FF72. Normal operation. LHLD FF70 Acquires data and transfers channel 0 (FF70)data·t9 L register and channel I (FF71) data to H register. LDA FF72 Acquires data from channel 2 (FF72) and transfers to the accumulator. The MP20 may be operated in several programming modes. The minimum. software approach (i.e., one instruction to acquire data as described above) is to halt the CPU during conversion (40 ,",sec). This mode of operation is effected by connecting the READY line (pin 48) of the MP20 to the 8080's READY input. The MP20 may also be operated without halting the CPU. In this mode of operation conversion may be initiated by a memory read instruction referenced to the proper channel. When the conversion is complete, the data value may be acquired by another read instruction. The second read instruction can be referenced to any channel address of the MP20. This instruction should be addressed t(Hhe next channel to be acquired since it will start a conversion cycle. LDA FF70 Starts conversion pf channel 0 (FF70). { At least 40 micros~conds of software here to insure that conversion is complete. LDA FF71 Transfers conversion data from ch:mnel 0 (FF70) to accumulator and starts conversion of channel I (FF71). At least 40 microsecond~ of software. LDA FF72 Transfers conversion data from channel 1 (FF71) to accumulator nnd starts conversion of channel 2 (FF72). At least 40 microseconds of software. LDS FF7X Transfers conversion data from channel 2 (FF72) to accumulator and starts conversio . of any other channel of data. The time required for conversion may be between 40 and 200 microseconds depending upon the gain of the internal instrumentation amplifier. Therefore, the 40 microsecond time between LDA instructions shown above could be as long as 200 microseconds for a system used in the highest gain mode. If desired, the READY line may be polled to determine that conversion is complete and the data output valid. Of course, if direct addressing is not de~ired, MOV instructions may also be used. . Example: MP20 used with an 8080. MP20 base address FF70. Normal Operation. Read ·and Print the value of all 16 input channels and then stop. Example: MP20 used with an 8080. MP20 base address·· FF70; acquire data from channels FF70 through FF72. Do not halt CPU. 6-210 CROUT NMOUT BEG 1: EQU OlF3H (OIEEH) EQU 02C2H (02C3H) LXI SP 3FFF H (13EDH) LXI H OFF70 H :Address for channel zero MOV D, M :Read data from board CALL CROUT :Print CR & LF MOV A, D CALL NMOUT :Print data INXH MOV A. L CPI HI :Next channel 8~ :Have all 16 channels been read? -ISVDC )OOkn ~ JZ WHOA JMP BEG) WHOA: MP20 HLT This program assumes that the system is under the control of the SBC80/ to prototype package monitor (M80P, version 1.0, March I, 1976). The locations in parenthesis are used with the MCS-80 system design kit. The base address of the MP20 is set by inputs A4 through A14. Address lines A4 through AI4 respond to the inverse of inputs A4 through A14. For instance, if A6 is grounded, A6. will respond to a "high" input. A 15 is internally connected to respond to a "high" input. ANALOG INPUT RANGE SELECTION The MP20 may be set for any range between±5V and ±IO mY. Table I shows the pin connections for the various high level ranges available. MP20 Input Gain ADC Range Pin Connections ±5V 2 ±IOV 65 to 63; 66 open; 67 to 68 ±2.SV 2 ±5V 65 to 63; ±L2SV 2 ±2.5V O· SV 2 O·IOV 65 to 64; 66 to 68; 67 open O·2.SV 2 O·SV 65 to 64; 66 to 68; 63 to 67 Range 78 ~ to 68; 67 open G=2+~ FIGURE I. (a) MP20 Gain Adjust; (b) Offset Adjust SINGLE ENDED VS. DIFFERENTIAL INPUTS The MP20 analog inputs may be connected as singleended, differential or pseudo-differential. Single-ended operation may be used for high level (over one volt full scale) signals in low noise environments (Figure 3). Differential operation will reject common-mode noise appearing on both inputs (Figure 2). It should be used in noisy environments or with any low level signal (less than one volt). In the pseudo-differential mode, the MP20 is connected as for the single-ended mode in Figure 3 except the I.A: low input, pin 79, is not grounded. Pin 79 is connected to an external ground that is common to all of the analog inputs. In cases with a noisy remote ground where little noise will be picked up between sensor and MP20, the pseudo-differential mode may be used. The M P20 is set for single-ended operation when wired as shown in Figure 3. The microprocessor address lines are connected as indicated in the Pin Connections table on page 6-207. Differential operation occurs when the unit is connected as in Figure 2. However, address line A3 (Pin 19) should be grounded and A3 on the microprocessor connected to A4 on the MP20. The remainder of the higher ordered microprocessor address bits should be connected to the next higher bit on the MP20. The internal instrumentation amplifier is factory set for a gain of 2. This gain can be increased to 250 by adding an external resistance (R",) between pins I and 3. R", should be a stable resistor (10 ppm/"C) since this temperature drift will add to the accuracy temperature coefficient. The gain of the amplifier can be determined by this formula: Analog Inputs MP20 + + I I , Pin Connections Gain = 2 + 50k With pins I and 3 open. the gain is 2. 15 Open • D to 14 since the amplifier input offset will be multiplied by the amplifier gain. an offset adjust may be required (see figure Ib). 8 channel differential analog multiplexer 4 2 ~ ~~J fft 77 IA ~ 3 bit Channel Select 4 to 2 77 to 79 FIGURE 2. Differential Input ConnectIOns DIGIT AL OUTPUT Straight Binary Code (b) 65 to 63; 66 to 68; 63 to 67 Table I. Analog Input Range Pin Connections The M P20 may be set to output data with straight binary coding (pin 52 grounded) or two's complement coding (pin 52 to +5VDC through a I kn resistor). Straight binary coding is typically used with unipolar input ranges and two's complement coding with bipolar input ranges. Table II describes the coding. R ex, R) + R2 R2 is fine adjust (a) ANALOG INPUT Two's Complement Code ±5V o to +5V ±lOmV +9.92mV 1111 11I1 Wh.) 0111 1111 (7h~) +Full Scale +4.961 V +4.9KOV 1000 0000 (KO,.) 0000 OO-..--0 +5V Ro then Rll ~ IK RI ADDRESS BUS Al2 All AI3 30 31 SC/MP NWDS DACI DAC I OUT OUT 12 MPIO DAC 2 DAC2 OUT OUT FIGURE II. MPIO and MP20 Used With the SC/MP FIGURE 12. MPIO and MP20 Used With the Z-80 6-216 BURR-BROWN® MP21 113131 Microprocessor-I nterfaced 8-BIT ANALOG INPUT SYSTEM ANA.LO(, INPUTS = - ... .., ...... - <0 ... .;..; == .... !- !-I-I- 1-'" ;,..:.;;..;;..;;.,;..; ::a:::.:::a::=.::a::::a:: o - ... .., ...... -cr-ooo, _____ _ ::!:~~~~~~:!!:~~!:~~~~~ A< MUX OUT 1.0 "" " AlO MUX OUT 11/ A9 All IA IN LO AIJ IA IN HI AI2 A" AU I /-----,''-O} ~ ~A { ~ ; " .s -.'-.Sf-:Y o-------~~--_, HALT 0-------+1 iN'f' o------H I GAIN Af)JUST 78 v-___----'s",OO} OJ.'·FSF.T Af)JUST (AOUT R2 (AI)(" IN I) .7 R-I (AI)(" IN 2) COMP.IN ., 00 :;; ,"PO ~ 0' D. m FEATURES -EASY TO USE PIA is not needed No external logic needed No external adjustments Low or high level analog inputs Unlimited expansion - COMPATIBLE WITH: 6800 650X F-8 - EASY TO PROGRAM Choice of ways to interface: Memory-mapped Interrupt capability -COMPLETELY SELF-CONTAINED -LOW-COST - SAVES DEVELOPMENT TIME AND MONEY International Airport Industrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (602) 746·1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 PDS-37S 6-217 DESCRIPTION gauges without external signal amplification. fully compatible with the All control lines microprocessor bus and operate at .Iowpower S~hottky , TTL levels. The MP21 input lines present one LS TTL load while all outputs can drive up to 20 LS TTL loads. are The MPZ.l is a complete analog input system packaged in a SO-pin quad-in-Iine package. It is com{,letely compatible with 6S00 microprocessors. It i~.aJso.' compatible with the 650X and with the F-S. The MP21 contains a high speed S-bit AID COnverter, an instrumentation amplifier, an input multiplexer thatcan accept up to 16 single-ended signals or S differential signals as well as interface, timing and address decoding logic. The gain and offset are internally laser trimmed so that no external adjustments are required on the ±5V or 0 to +5V input range to obtain an absolute accuracy of better than ±O.4% (I LSD). The system can digitize low level or high level analog signaJs. The gain of the internal instrumentation amplifier can be programmed with a single externaJ resistor to aJlow input signaJ ranges as low as ±IO mY. This means thatthe MP21 can be conneeted to low level sensors such as thermocouples and strain PROGRAMMING 'When programming these peripheraJs, the user treats them as memory. Each analog input channel occupies one memory location. An~em. ory reference instruction can be used. Pins A4 to m are made available so that the microperipheraladdress can be hardwired for any of 1024 possible memory location bands. Since these units are treated as memory, a minimum of instructions are needed to read an input channel. The MP21's versatile memory mapped operation allows it to be used with or without halting the CPU or in the interrupt mode. . AN.ALOG INPUTS - MP21 BLOCK DIAGRAM M .. Wl '0.;: ~I-o~f-of-of-o t-f-o 0_ C"oI ~~~~Io&:E&:i~~ Cl:ac:ac:ClC:ac:a::ac:ac: o _NI"\'" WI O-f"I M ... .,...,"" C l C J I - - - - - - . !i!!i~!!i!iS!!!i!i!i!!! o AD AI A2 A3 '" ::> II ...'"'" Q Q < ... A4 AS A6 A7 A8 A9 AIO All AI2 AI3 AI4 AU 8 Channel AnaJol Multiplexer 8 Channel Analoa Multiplexer 77 MUXOUT LO MUXOUT HI 79 lAIN LO IAINH, Control LolJic 3 78 80 68 } GAIN ADJUST } OFFSET ADJUST IAOUT R2 (ADC IN I) 6.2Sk .7 RI (ADC IN 2) 63 COMP.IN .s BPO StatuI 8 Bit Anllos-to·DiIltal Converter 6-218 SPECIFICATIONS MECHANICAL Typical at 25°C unless otherwise noted. ELECTRICAL Pin TRANSFER CHARACTERISTICS :n.=--. Resolution Number of channels Throughput ratecn (max) Bias current 25°C o -70'C Amplifier output noise Gain = 100, Rs = 5000 Amplifier input offset'voltage (max) Amplifier offset voltage drift Amplifier settling time (to .1% FSR) G =2 G = 10 G = SO G = 100 G'= 200 CMRR (for differential inputs) (G = 2) 8 bits binary 16 singie-ended/8 differential 4{}p.secl channel TEMPERATURE RANGE ' ... 0 0 ••• 0.00.0 •••• 0 [ nos (10 Hz to 10 kHz) ±lmV ±(6 + SOIG)~V /'C C -1~H .~~ A~ .-lL~JJ 20p.s 2S~s SO~s 100l-'s 2001's 70 dB (DC to 60 Hz) INCHES DIM A B MAX MIN MAX 2.180 53.85 1.720"- 42.42 55.37 43.69 .170 .018 .230 4.32 5." .02' 0." 0.53 F .03' .050 0.89 1.27 G .100 BASIC .100 BASIC H K L N p R T u .150 .250 1.5C)0 BASIC .010 .002 .050 .100 .200 1.100 BASIC BASIC BASIC BASIC NOTE: LEADS IN TRUE POSITION WITHIN .OW (.38mm) R AT MMCAT SEATING PLANE. MILLIMETERS MIN 2.120 1.1570 0 c ±o.4% of FSR'" ±o.4% of FSR ±o.8% of FSR ±o.8% of FSR ±o.2% ofFSR ±0.2% of FSR ±112 LSB ±o.I% ±o.I% ofFSR MATERIAL: Ceramic WEIGHT: 32 grams (1.2 oz) PINS: Pin material and plating composition conform to Method 2003 (solderability) of Mil-5td-ll83 (except paragraph 3.2) MATING CONNECTOR: 2350MC (Set of four 20 pin strips) 2.54 BASIC 2.64 BASIC 3.B1 6.35 38.1 BASIC 0.05 0.25 1.27 BASIC 2.54 BAS)C 5.08 BASIC 27.94·BASIC ±o.02%1%<1Vcc ±o.002%1%<1Vcc PIN CONNECTIONS ±40 ppm/,C ±20 ppm/,C Guaranteed .!l.!!. .,,, I 1 Binary or Binary two's complement All digital inputs are one LSITL load 5 ITL loads or 20 LSTTL loads AO - A3 DO- D7 POWER REQUIREMENTS Rated voltages Range for rated accuracy Supply drain ±ISV +SV 41 400~V DIGITAL INPUTIOUTPUT All signals are compatible with Microprocessor bus Output coding Logic loading Output drive (00 - 07) An analog input channel is selected by: The output data bus are read into: 42 I~~ '...... ..." ±6volts S • 10'fl II 10 pF - OFF channel S • 10'flll 100 pF - ON channel 100 nA 200 nA STABILITY OVER· TEMPERATURE System accuracy drift C1l (max) Linearity (max) Monotonicity (O"C to +70°C) ,. o. 79 Numbers ()'SV, ()'IOV, ±2.SV, ±SV, ±IOV 2 to 2S0 G = 2 + SOkOl RU I(2 ) ±23 volts ACCURACY Throughput accuracy ±5V, ±2.5V, ±1.25V range (maxi 4 ) ()"5V, ()"2.5V range (max)c 4 ) ±SO mV range (maxt'l 0-50 mV range (maxi') Linearity (max)(·) Differential linearityc.) Quantizing error Gain error(max)14 1 Offset error (max)C 41 Power supply sensitivity ±15V +SV jB61 only. ANALOG INPUTS AOC gain ranges Amplifier gain. ran&!," Amplifier gain equation Max input voltage without damagem Max input voltage for multiplexer operation Input impedance r;I •••••• • •••••••••••• numbers , !:.!.2. IA GAlS AI>Jl"ST IA IS HI IA GAl!\, ADJUST MUX Ol'T HI 1"7 1'\i6 IS 5 ," '" 10 II 12 IS 3 I"oil 1,,"1 1,,"0 MI'X ""'ABI.F I Ml'X f. ... ABI.E 2 SIS !lit "",." " ,.'"" " A4 "-- AS" " """ """ '" Ai "'"'" A< "" Ai1i " AIT """ ill "'" AO AO ±ISV, +SV 4.7S to S.2S and ±14.S to ±IS.SV ±30mA ~OmA AI A' M ~., O·C to +70'C M A9 (I) Includes 3Sp.sec for mux and amplifier time and S",ec for AOC conversion time. (2) Rut is an external resistor connected between pins I and 3. (3) With power applied. (4) ·With no external adjustments. (S) FSR is Full Scale Range (FSR is IOV for ±~V range). (6) Gain = 100 with external gain and offset trim. (7) Includes gain drift. offset drift and linearity-drift. 6-219 AIO J.l All AI2 AO " AI>DR DECO!)F OlIT 41 .."" ."""" ""'" """ "'"" "'" " ,."" """ " ""'" "" "" " "" ... "' AI' RW AIS N V"A ;, RESEr iWT I)~I.AY AI>} +~\' I>I(i("OM 01 TPI·rSfI.FCT O1cMSBI I~ ))l ,~ ., DJ In OOCI.SB) ·15\' +IS\" COMP I... A"'A ("OM .PO R2 cAlX" IS II RI CAlX" IS 21 IAOt'l I!'KRFT 0 I~q RFI ) 1:'10 IORET 2 1!'Ii II RET J 1"'12 RET 4 l'\i 13 RET S 1!Ii 14 RET-6 ISISRHl MI:X 0("110 O ......SEI'il'l.l IA" 1.0 O ......SH :'Iil'l.I r' PIN FUNCTIONS (Optional). Pin J and Pin 3. By connecting a resistor between pin I and 3 the gain of the internal instrumentation amplifier can be set as follows: Gain = 2 + 50kO/Re.. Where Rex! is the gain setting resistor. The IA is factory adjusted for a gain of 2 without any external resistor. Important: If a gain greater than 10 is required an external capacitor must be connected from "DELAY" (pin 49) to +5V. This increases an internal delay to allow for the increased settling time of the instrumentation amplifier. (See page 6-224) Pin 2. This is the positive input of the IA IN HI internal instrumentation amplifier. This should be connected to pin 4 (MUX OUT HI) for normal operation. MUX Pin 4. This is the output of the analog input multiplexer. This is connected to pin OUT HI 2 (IA IN HI) for differential operation. It is connected to pin 77 (MUX OUT LO) and pin 2 for single-ended input operation. IN7 - INO Pins 5 - 12. The first 8 (of 16) analog inputs for single-ended operation or the 8 positive inputs for 8 channel differential input operation. Pin 13. Leave open for single-ended input MUX ENABLE I operation. Connect to pin 14 (MUX ENABLE 2) for differential input operation. MUX Pin 14. Connect to pin 15 (SIN/DIF) for ENABLE 2 single-ended input operation. Connect to pin 13 (MUX ENABLE I) for differential input operation. SIN/DIF Pin 15. Single/ Differential input operation connect to pin 14 (MUX ENABLE 2) for single-ended operation. Leave open for differential input operation. AO- A3 Pin 16 - 19. Address lines that select one of 16 analog input signals (INO - INI5). 0000 selects channel 0 and 11I1 selects channel 15 when the correct address is presented to the MP2J. Note: A3 should be connected to DIG COM for 8 channel differential input operation. Address lines. Pins 20, 22, 24, 26, 28, 30, 32, A4 - AI5 34,36,38,41, and 43. Connect to A4 - AI5 of the 6800. Address select lines. Pin 21,23,25,27,29, 31,33,35,37, and 39. By connecting these lines to DIG COM or +5 volts (through a IkO resistor) any of 1024 address bands can be assigned to the MP2J. For example, if A4 is connected to GND., the correct (valid) address for A4 is a "I" (> + 2.4V). IA GAIN ADJUST ADDR DEC VMA ~2 RESET DELAY ADJ +5V DIG COM OUTPUT SELECT 6-220 Pin 40. A positive pulse will appear when a valid address appears on the MP21 address lines and when R/W (pin 42), and ~2 (pin 46) and VMA (pin 45) are high. The rising edge of this pulse strobes the input channel select information (AO - A3) into a latch. It can also be used for external purposes. Pin 42. Read/Write control line. Connect to R/W of 6800. Pin 44. Interrupt output. Connect to IRQ or NMI of the 6800 if interrupt operation is desired. When conversion has been completed, a lO"sec pulse (negative) is generated on this line. (Not an open collector output.) Pin 45. Connect to VMA on 6800. Pin 46. Connect to 112 on 6800. Pin 47. A "Low" on this line is required to reset the MP2J. Connect to the RESET input of the 6800. Pin 48. When the MP21 is "Read" by the microprocessor via any memory reference instruction the HALT line will go "Low" until conversion is complete. If the HALT line is used to halt the CPU, the 680Q will halt upon completion of the next instruction. When the multiplexer, instrument amp, and A/D converter have completed converting the analog data to a binary 8 bit code (40"sec with gain";; 10) the HAL'f line will then return to its "High" state which releases the processor. The output data can then be read with a second memory reference instruction. (Not an open collector output.) Pin 49. When the MP21 is addressed, an internal delay of approximately 35"sec is initiated to allow for multiplexer and instrumentation amplifier settling time. When the IA is operated with gain> 10 this delay must be increased (see Figure 4) to allow for the increased settling time of the IA. This is done by adding a capacitor between pin 49 and +5V. (See Figure 5) Pin 50. +5 volt at 140 rnA maximum, 90 rnA typical. Pin 51. Digital common. This pin should be connected to analog common (pin 64) as close to the MP21 as possible for optimum performance. Pin 52. This pin should be connected to DIG COM to obtain binary data at DOD7. To obtain two's complement data (bipolar mode) connect pin 52 to +5V through a IkO resistor. 07-DO Pin 53 - 60. 8 bit data bus. 3-state low power Schottky TTL compatible. -15V Pin 61. -15 volt at 30 rnA typical. +15V Pin 62. + 15 volt at 30 rnA typical. COMP Pin 63. Comparator input of 8 bit AID IN converter (successive-approximation). Leave open for unipolar operation or connect to "BPO" (pin 65) for bipolar operation. NOTE: This point is extremely sensitive to noise. Any connection to this line should be as short as possible and shielded by ANA COM or ±15 volt supply patterns. ANA COM Pin 64. Analog common should be connected to digital common (pin 51) as close to the MP21 as possible for optimum performance. BPO Pin 65. A I D converter bipolar offset. It should be connected to ANA COM (pin 64) for unipolar operation or COMP IN (pin 63) for bipolar operation. Pin 66. AID converter input resistor. R2 Connect to IA out (pin 68) for 0 to +5V input unipolar operation or ±2.5V input bipolar operation. Leave open for ±5V input bipolar operation. Pin 67. AID converter input resistor. RI Connect to IA out for ±5 volt operation. Connect to Pin 63 for Oto +2.5V and ±1.25Vranges. IA OUT Pin 68. Instrumentation amplifier output. Connect to RI (pin 67) or R2 (pin 66) for normal operation. IN8-INI5 Pin 69-76. Analog inputs 8 through 15 for RETQ-RET7 single-ended operation or analog returns 0 through 7 for differential input operation. Pin 77. Multiplexer output for MUX IN8-INI5 or RETO-RET7. OUTLO Connect to "MUX OUT HI" (pin 4) and "IA IN HI" (pin 2) for singie-ended input operation or connect to "IA IN LO" (pin 79) for differential input operation. Pin 78, 80. Optional instrumentation OFFSET amplifier offset adjust (see Figure I). NULL Pin 79. Negative input of instrumentation IA IN LO amplifier. Connect to ANA COM (pin 64) for single-ended input operation or "MUX OUT LO" (pin 77) for differential input operation. 4th cycle LDA ~ ~ IU R~----------j-----------t-~~;;:~ __-J~~~-------- YMA Add Bus Data Bus _ _ ~New ~Data Add Dec HALT --------1t~======~tH~A~L~T~~~====~~~~~------tj~----------tHT tON tHT ------I tAD-II- Clock freq. = I Mhz tHT = 200ns min before falling edge of pi tHAL T = 40_c (max) tON = 70nsec (max) tAD = 30nsec (max) MP21 Timing Diagram (using HALT to stop microprocessor during conversion). 6-221 4th cycle ,1 ~ 11 R/'ii ------11,' - - - - - VMA Op Code +2 Add Bua "Per. Add X_"'----JX , .>q, :x Op Code 0' ""--ll =>< "Per. Add >C ~New Data Bus ~Data Add II Dec MP2l Timing Diagram (without stopping microprocessor during conversion). 13 Last cycle 1st cycle 1st cycle INT LOA Data Bus r--->. Add ~c ----------------------~l'~I----------------~f~f----~' ~ tpcs = 200ns min bofore fallingedce of next to last, 2 clock pulse of instruction tiNT = 12,,"oc (max) MP2l Timing Diagram (using Interrupt). OPERATING INSTRUCTIONS PROGRAMMING to the MP21 to read the converted data. This mode uses the least amount oftime; it should be used when software time is at a minimum. (MP21's HAI:'i' line, pin 48, is open.) The MP2l is easily programmed since it is treated as memory. It uses any memory reference instruction that can read data. The MP21 can be operated in four modes: I) Start data conversion, halting the microprocessor for the 4OJ.'sec* conversion time. This is the simplest approach. It should be used if 4OJ.'sec of software time is available. (MP21's iiALT line, pin 48, connected to the 6800's HALT input, pin 2.) Example: Example: LOA XXXX starts conversion of the channel at location XXXX : {at least 40llsec* of software here LOA XXXX transfers data from channel at location XXXX to accumulator LOA XXXX starts conversion of channel at location XXXX NOP CPU halts at the end of this instruction LOA XXXX transfers data from channel at location XXXX to accum~ator * The conversion time of the MP21 may be between 40 and 200 microseconds depending upon the gain of the internal instrumentation amplifier. See Figure 4. 2) Start data conversion, then go to a different part of the program. When 4OJ.'sec* or more. have passed, come back 3) Start data conversion, then go to a different part of the program. Periodically, check the MP21's iiAL'fline(pin 48) to detect if conversion is complete. This mode should 6-222 I be used if a positive check of a complete conversion is needed. (MP21 's HALT line, pin 48, could be interfaced to a 6820 PIA for instance.) Example: LOA $XXXX starts conversion of channel at location XXXX : tother software ANALOG INPUT RANGE SELECTION LOA $YYYY1IOOP to determine if conversion is complete AA ANOA $ZZ YYYY is location of 6820 PIA with HALT information ZZ is mask used for determin· ing if end of conversion bit is set BEQAA LOA $XXXX transfers data from channel at location XXXX to accumulator 4) Start conversion, then go to a different part of the program. The MP21 will interrupt at the end of conversion. The interrupt mode is very useful when the MP21 is at high gains with convers::m times longer than 40!-,sec, see Figure 4.(MP21's INT line, pin 44, connected to the 68oo's IRQ line, pin 4.) Example: MP2l used with a 6800. MP2l base address 92EO. Processor haIted operation. Read and Print the value of all 16 input channels and then stop. EOBF FlOI EIAC 0100 0100 CE 92EO 0103 SF 0104 A600 0106 0101 0107 A600 0109 FF 0137 OlOC F70139 OIOF B70138 0112 CEOl3B OilS BOEOBF 0118 860D OIIA BO EIDI 01lD860A OIIF BOEIDI 0122 F60139 0125 FE 0137 0128 5C 0129 ClIO NAM MP21 OUT2H EQU $EOBF OUTEEE EQU $EIOI INEEE EQU $EIAC ORG $100 START LOX #$92EO CLR B CONV LOA A,X NOP LOA A, X STX STREI STA B STRE2 STA A STRE3 LOX #STRE3 JSR OUT2H LDA A #$OD JSR OUTEEE LDA A #$OA JSR OUTEEE LDA B STRE2 LDX STREI INC B CMP B #$10 012B 012D 012E 0131 2704 08 7E 0104 BD EIAC STOP BEQ INX JMP JSR 0134 0137 0139 013A 7E 0100 0002 0001 0001 JMP RMB RMB RMB END STREI STRE2 STRE3 STOP CONY INEEE ADDRESS SELECTION The base address ofthe MP21 is set by inputs A4 through A13. Address lines A4 through Al3 respond to the inverse of inputs A4 through A13. For instance, if A6 is grounded, A6 will respond to a "High"input. AI4 and A 15 are internally connected to respond to a" H igh"input. The MP2l may be set for any range between ±5V and ±10 mY. Table I shows the pin connections for the various high level ranges available. MP21 Input Range Gain ±5V ±2.5V ±1.25V 0- 5V 0- 2.5V ADC Range ±IOV ±5V ±2.5V 0- IOV O·5V Pin Connections 65 65 65 65 65 to 63; 66 open; 67 to 68 to 63; 66 to 68; 67 open to 63; 66 to 68; 63 to 67 to 64; 66 to 68; 67 open to 64; 66 to 68; 63 to 67 Table I. Analog Input Range Pin Connections The MP21 may be set to output data with straight binary coding (pin 52 grounded) or two's complement coding (pin 52 to +5VDC through a IkO resistor). Straight binary coding is typically used with unipolar input ranges and two's complement coding with bipolar input ranges. Table II describes the coding. The internal instrumentation amplifier is factory. set for a gain of 2. This gain can be increased to 250 by adding an external resistor (R",) between pins I and 3, R", should be a stable resistor (10 ppmj"C) since this temperature drift will add to the accuracy temperature coefficient. The gain of the amplifier can be determined by this formula: Gain = 2 + 50kO . With pins I and 3 open, the gain is 2. R ext Base address for MP21 Clear Counter Initia~e Read Store Store Store Conversion Data Index Reg. Counter Data Since the amplifier input offset will be multiplied by the amplifier gain, an offset adjust may be required at high gains (see Figure I b). Print Data MP21 SOkn G=2+--- Next Channel Have 16 channels been read? Yes Do another conversion Input character to begin again START 2 I I This program assumes that the system is under the control of the MIK BUG monitor, Revision 9. To read and print the value of all 16 channels again, input any character from the key board. 6-223 (a) RI + R2 R2 is fine adjust (b) FIGURE I. (a) MP2l Gain Adjust; (b) Offset Adjust SINGLE-ENDED VS. DIFFERENTIAL INPUTS The MP21 analog inputs may be connected as singleended, differential or pseudo-differentiaL Single-ended operation may be used for high level (over one volt full scale) signals in low noise environments (Figure 3), Differential operation will reject common-mode noise appearing on both inputs (Figure 2), It should be used in noisy environments or with any low level signal (less than one volt), In the pseudo-differential mode, the MP21 is DIGITAL OUTPUT ±SV ANALOG INPUT o to +SV ±IOmV +4.961 V +4.980Y +9.92mV Straight Binary Code Two's Complement Code 1111 1111 (FF,,) 0111 1111 (7F,,) 1000 0000 (801') 0000 0000 (00,,) Mid-8cale O.OOOV 2.500V O.OOOV 0000 0000 (001') 1000 0000 (80,,) -Fun Scale -S.OOOV O.OOOV -1O.00mV One LSB 39mV 19.5mV 78"V +FuU Scale TABLE II. Analog Input Values connected as for the single-ended mode in Figure 3 except the IA low input, pin 79, is not grounded. Pin 79 is connected to an external ground that is common to all of the analog inputs. In cases with a noisy remote ground be picked up between sensor and where little noise MP21, the pseudo-differential mode may be used. ,il Analog Inputs + + MP21 8 Channel 4 Differential Analog Multiplexer ~ , Pin Connections IS Open 13 to 14 4 to 2 77 to 79 19 to DIG COM ! 77 79 3 Bit Channel Select time constant can be calculated with the formula: T = (R, + Ro.+ Ro.*)Co. ForR.= IkOand Co = 50pF, T=(1.5 + I) kO x 50pF = 125ns (single-ended operation). Thus 0.75"s is needed to settle to ±O.l%. For high input impedances requiring more than 10 microseconds for multiplexer settling time, the required delay time may be calculated with this formula: T D =ff2 mu. + T2IA, where T mu. is the settling time of the multiplexer and TIA is the settling time of the instrumentation amplifier as shown in Figure 4. If the source bandwidth can be limited, high impedance sources may be accurately handled by placing a large capacitance across the multiplexer input. An analysis of such a circuit shows that a capacitor ofO.5"F is sufficient. For such a capacitance the multiplexer time constant becomes SOns. 250 FIGURE 2. Differential Input Connections . Analog Inputs 1 200 ." 0:: g:=~1=~f~~~~~ , " j" MP21 .,L ISO .s I ~ Pin Connections IS to 14 13 Open 77 to 4 4 Bit Channel Select 4to 2 79 to ANA COM ::!! 1= "... 25 o-l ... '":!i ~ FIGURE 3. Single-ended Input Connections V L 10 50 0 ~ / V 100 50 0 V 200 ISO 250 GAIN (V/V) DELAY TIMING A delay time between channel selection and start of conversion is built into the MP2l to allow the analog multiplexer and instrumentation amplifier (IA) time to settle before starting the AID converter. As the gain of the amplifier is increased, the settling time required increases. The factory set delay time (35"sec) is sufficient for gains of up to 10. At higher gains, a capacitor must be added from pin 49 to the +5 VDC supply to increase the delay time. Figure 4 shows the settling time ofthe MP21 vs. gain. Figure 5 shows the value of capacitance required to increase the delay. The only external factor, other than gain, that affects the MP2l settling time is the impedance of the source connected to a channel. Figure 6 shows a circuit model of an "ON" channel. The signal at the output of the multiplexer must be allowed to settle to ±O.l% (six time constants) to maintain the full accuracy of the system. The multiplexer FIGURE 4. Typical IA Settling Time vs. Gain (Output Settling to ±O.l %). 300 ... J ." 0:: " e " II 200 L ! ~ o-l ~ 100 80 50 39 35 -/ L lL ". ". ". (i ,I o on,.. 00 1000 2000 3000 4000 5000 ~M CAPACITOR VALUE (Picofarads) FIGURE 5. Typical Delay Time vs. Capacitor Value. 6-224 Source Resistance souree~ RS - RON Supply fCo 1.5kSl RON result in 07 - DO being in a high impedance state (see Figure 7). All that is required to use the MP21 with a system other than a 6800, is that these signals be brought to their active levels. When this occurs, operation begins as previously described. Applications using the MP21 with other processors are shown in Figure 10 and II. +Supply MP21 J.5kSl . +Supply RESET Co:: SOpF for single-ended mode Co:: 12.SpF for differential mode RON* = 0 for single-ended mode FIGURE 6. "ON" Channel Circuit Model. It is important to reset the MP21 on startup with a low pulse on the RESET line (pin 47). The reset pulse clears an internal flip-flop and guarantees that the next read instruction to the unit will start conversion. Thereafter, every other read instruction will initiate a conversion as previously described. a INPUT OVERVOLTAGE PROTECTION As shown in Figure 6, the analog inputs have reverse biased diode circuits which protect from damage by overvoltage (such as static). It is still advisable to take precautions against static discharge. The same circuitry protects the inputs from steady-state overvoltage damage during operation. The MP21's overvoltage protection can be increased by adding series resistors at each input. The input resistance must limit the current flowing through the input protection diodes to lOrnA. For instance, if 15kO resistors are added to each input, the protection is increased to 165V (16.5kO x lOrnA). Increased input resistance will, of course, increase the amount of time necessary for the multiplexer to settle as described in the previous section and increase the offset voltage by the drop caused when the bias current passes through this resistance. NON 6800 OPERATION The circuitry used to enable the 3-state output lines (07 DO) and begin conversion on the MP21 can be connected in such a way as to meet a wide variety of timing requirements. The output is enabled only when a valid address appears on the address inputs and when VMA (pin 45), R/W (pin 42), and 02 (pin 46) are high. Any other combination of digital signals on these lines will HIGHER SPEED OPERATION The MP21's internal instrumentation amplifier requires 35 microseconds to allow for settling time. If this internal amplifier is not used, substantial improvements in throughput rate can be obtained. This is easily done since neither the inputs nor the output of the instrument amplifier are internally connected. The total delay time necessary may be calculated by this formula: where T MUX is the settling time of the multiplexer (750ns) and TIA is the settling time of the instrument amplifier. For a TIA of I!-'secwe have To = 1.3!-,sec. Using 3!-,sec for the delay time to allow for unit to unit variation, the totlll throughput time will be 8!-,sec (including 5 microseconds for ADC conversion time) or 125 kHz. A resistor between pin 49 and +5 VDC will reduce the delay time from the factory set value of 35 microseconds (see Figure 8). ToADDR DEC ADDRDEC 40 25 Lope D'7·DO ENABLE ~ '"8c 20 l! e IS !>- ....< VMA «l Q ,,2 10 7 5 3 ./ / ~ ,..... ....-~ '(0,1 III o:::g~1 00 200 300 400 500 RESISTOR VALUE (kilohms) FIGURE 7. Output Enable Circuitry FIGURE 8. Typical Resistor Value to Decrease Delay Time. 6-225 CALIBRATION The· MP21 is laser trimmed at the factory to ±O.4% accuracy when using the ±5V, ±2.5V, ±1.25V, 0 to +2.5V or 0 to +5V ranges. If one of these ranges is used, no adjustments are required. For other ranges (G # 2), both the gain and offset must be adjusted. Figure I shows the adjustment connections. The offset adjustment should be made such that the transition to minus full scale output (0000 0001 to 0000 0000 for straight binary) occurs with an input of negative full scale plus 1/2 LSD. One least significant bit (LSD) is equal to the full scale range (FSR) divided by 2" where Ii is the number of bits ofthe A/D converter. For the MP21, I LSD is FSR/28 = FSR/256. The gain adjustment should be made such that the transition to a full scale output (llll III 0 to llll llll for straight binary) occurs with an input of positive full scale less 1/2 LSD. Since 128 states are used for negative inputs and one state is used for zero, only 127 states are available for the remaining positive range. Thus the positive full scale voltage is I LSD less than nominal full scale. Fora range of±50 mV, I LSD = lOOmV/256=0.39 mY. The gain adjustment should be made at +49.6ImV* -(0.5)(0.39 mY) = .+49.42 mY. The offset adjustment should be made at -50 mV +(0.5)(0.39mV) = -49.80 mY. Table III shows offset and gain calibration values for typical ranges. • (SOmV· I LSB = 49.6ImV) MP21 Input Raoae Instrument Amp Gain ±SV Oto+SV ±2.SV o to +2.SV 2 2 2 ±l.lSV O· SOmv ±2SmV O-lSmV 2 2 (00 100 200 ADC Range ±IOV o to +lOV ±SV o to +SV ±2.SV o to+SV ±2.SV Oto +SV Calibration Values Gain Offset -4.980V +9.8mV -1.490V +4.9mV +4.941 V +4.97IV +2.47IV -1.24SV +2.48SV +1.23S +98"V -24.9mV +49"V +49.1mV +24.7mV +24.9mV Table III. Calibration Values. The following program may be used to adjust gain and offset. ORG $100 START 0100 0102 CONY 0105 0106 0107 010A 010B 010E 0110 AA 0112 0113 0116 0118 COUNT OIlA 86 64 B7 01 ·lA 4F SF B6 92 EO 01 B6 92 EO 81 REF :26 01 5C 7A 01 IA 26 EF 20 E6 LDAA #$64 STA A COUNT CLRA Clear Accumulators. CLRB LDA A $92 EO Begin Conversion. NOP LDAA $92 EO Re.d Dat •. CMPA#REF IS D.t. = REF? BNEAA No. Do not count. INCB DEC COUNT Yes. Do cQunt. Have 100 conversions been done. BNE CONY No. Do another. BRA START Yes. Begin next run. RMB END This program assumes that the program is under control of the Motorola EXORciser EXbug monitor. If the Mikbug monitor is available, the following printout software may be added by using it to replace all codes starting from location 0118. In addition the references to count at 0104 and OilS must be replaced withi2E. OUT 2H EQU SEO OUT EEE EQU $EI BF DI 0118 F7 STA B STRO 01 2E CE 011B LDX #STRO 01 2E OIIE BD JSR OUT2H Print no. of true conversions. E.9 0121 0123 012E 012F BF 86 OD BD EI DI LDAA JSR #OD OUTEEE RMB I RMB I END COUNT STRO This program may be used for both offset and gain calibration. The system offset should be adjusted first, followed by the gain adjustment . The address of channel zero is assumed to be 92EO. If it is not, the LDA instructions should reflect that change. The reference values for Ref assume straight binary coding, Offset Ref = 00 and Gain Full Scale Ref = FF. For two's complement binary coding, Offset Ref= 80 and Gain Full Scale Ref = 7F. A lOO;G command to Exbug will begin program executiolL For Mikbug the user's stack must be loaded with l~ and then a G command executed to begin program execution. For those applications not using the printer portion of the program insert a breakpoint via a l18;V command. After 100 conversions have been made, the value .(in hex) of the D accumulator will be printed if using Mikbug program. This value represents the number of times the data read from the board w~s equal to "REF' (00 for offset; FF for gain). Calibration is performed by connecting a voltage source capable of 0.01% accuracy to input channel zero (this could also be a DC voltage source of less absolute accuracy whose output is monitored by a 0.01 % DVM). The offset adjustment is made first by using the appropriate offset calibration voltage and REF value. Run the calibration program and adjust the offset potentiometer until the B register contains a value between IE 16 and 4616 (3010 and 7010). To perform the gain adjustment, change the data labeled "REF' in the calibration program to its correct gain value. Set the input voltage to the correct value as shown in Figure 8 and adjust the gain potentiometer.in the same manner as described for offset. If EXbug is used the program will halt and the D accumulator can be examined from the program register display produced by the breakpoint. 6-226 THERMOCOUPLE TEMPERATURE ACQUISITION Thermocouples are often used as temperature sensors for process control systems. Thermocouples are characterized by temperature coefficients of 10 to 70po Vj"C and operating ranges of minus hundreds to plus thousands of degrees centrigrade. When the MP21 is operated with an instrumentation amplifier gain of 100 or more, it may be connected directly to these devices. The wire runs from thermocouple to measuring device often pick up large common-mode noise signals of 60 Hz or higher frequencies. When the MP21 is used as an eight .channel differential input system, the high commonmode rejection of the instrument amplifier will reject common-mode noise. To minimize differential mode noise, the signal wire should be twisted and if possible shielded. Asa rule, an unshielded twisted pair is better than a coax, and a shielded, twisted pair is still better. In applications where these wiring practices cannot always be observed, a differential RC filter may be used. Figure 9 shows such a system. The 10 kO resistors and 10poF capacitor provide low pass filtering (f, = 0.8 Hz) while the optional I MO resistors supply bias current to the instrumentation amplifier. The remote sensor should be earth grounded to prevent common-mode voltages from exceeding the ±5 volt range of the multiplexer. If the sensor is earth grounded, the lMO resistors are not required. The I MO resistors do not enter into an error calculation for input errors because the low resistance of the sensor shorts any differential voltage that might be caused by the offset (difference current) of the amplifier. Offset or difference current is merely the difference between the bias current of each input. See the overvoltage protection section for a discussion of the effects of the 10kO resistors in the input filter. The IMO resistors could have been put on the output side of the multiplexer eliminating the need for repeating them for each input; however, this would have loaded the IOkO resistors of the filter causing a possible 1% error for static conditions. To complete a thermocouple system it is necessary to terminate all th~rmocouple wire pairs at an isothermal box or connector strip of some type. An ordinary barrier strip may be monitored to allow the observed thermocouple emf to be cold junction. compensated. Figure 9 shows an excellent circuit for this purpose. Its output is connected to one of the input channels to supply ambient temperature data to the system computer. Its output sensitivity is approximately 2 mV j"C. MP21 CHN IMSl 10k CHN RTN ... IMSl , OJ Cable Run Isothermal Barrier Strip _ .... - - - . . - Optional I Hz Low Bias Current Pass Filter Supply Resistors +15 +15 L 200k BB3500B Rc Rd RakT E = Rc + Rd (I + Rb ) q In 10 { EdE Rd. RaK (iff) = - Rc + Rd (1 + Rb) q In 10 Rd !.15V T = OK, k/q = 8.67 x 10~5 Dual monolithic transistor pair (National LM 114) Mounted Near Isothermal Barrier Strip FIGURE 9. Thermocouple Input System Using MP21. 6-227 +5V -15 +5 PIN CONNECTION SUMMARY Single-ended Multiplexer Differential MUltiplexer Ampli(ier Input Range ±5V ±2.5V ±1.25V 0- 5V 0- 2.5V JUMPER Address Bus (AO - A15) 4 to 2; 4 to 77; 79 to 64; 15 to 14; 13 open 4 to 2; 77 to 79; 13 to 14; Address Select (A4 - A13) 15 open I and 3 open for G = 2; Control Bus R,,, between I and 3 for G i- 2. 65 66 65 65 65 to to to to to 63; 63; 63; 64; 64; 66 66 66 66 66 open; 67 to 68 to 68; 67 open to 68; 63 to 67 to 68; 67 open to 68; 63 to 67 52 to 51 for binary; 52 to 50* for two's complement. • Through a I kO resistor. Output Coding Data Bus (DO - 07) JUMPER Connect to 6800's address bus AO - AI5 Connect to +5V· or Ground 42 to 6800's R/W (pin 39) 44 optionally to 6800's IRQ (pin 4) 45 to 6800's VMA (pin 5) 46 to 6800's f,J2 (pin 37) 47 to 6800's RESET (pin 40) 48 to 6800's HALT (pin 2) open for operation without halting CPU. Connect to 6800's data bus. MICROPROCESSOR INTERCONNECTION The following diagrams show interconnections ofthe MP21 (described in this data sheet) and also of Burr-Brown:s MPIO and MPII analog output iriicroperipherals (PDS-363) with Motorola's 6800, MOS Technology's 650X, and Fairchild's F-8. Although Burr-Brown's analog mjcroperipherals are optimized for 8 bit microprocessors, with the addition of a few external components, they can be used with any 4 through 16 bit microprocessors. Steps For Operation of MP21 with F-8 1. Start conversion by addressing and reading MP21. 2. Initialize Timer 3. Use timer initialized interrupt to read data. FIGURE 10. MP21 and MPlI Used With the 6800 or 650X. FIGURE II. MP21 and MPIO Used With the F-8. 6-228 BURR-BROWN® MP22BG IElElI· Microprocessor-I nterfaced 12-BIT DATA ACQUISITION SYSTEM MULTIPLEXER SINGLE-ENDED/ DIFFERENTIAL liP ADDRESS BUS GAIN r---O ADJUST /lP CONTROL BUS AID liP DATA BUS CONVERTER FEATURES DESCRIPTION elNTERFACES WITH 8080A. 8048. Z-80. SCIMP MICROPROCESSORS WITHOUT ADDITIONAL COMPONENTS A ccimplete analog input system, the MP22 interfaces to most microprocessors without requiring additional external components. Contained in an 80-pin quad-in-line package, it inclUdes a 12-bit CMOS AID converter, instrumentation amplifier, input multiplexer that accepts up to 16 single-ended signals or 8 differential signals, an address decoder and control logic. Logic to generate interrupt, halt and direct memory access request signals are also included. The system can digitize low level or high level analog signals. Gain of the internal instrumentation amplifier can be programmed with a single external resistor allowing input ranges as low as ±5mV/. • INTERFACES WITH 6800. 650X. FB. 8085 MICROPROCESSORS WITH MINIMAL EXTERNAL LOGIC • EASY TO PROGRAM One instruction acquires data as a memory mapped device Two Instructions acquire data as an accumulator 110 device • COMPATIBLE WITH PDP·B. PDP·II. NOVA. ECLIPSE MINICOMPUTERS Inl8rnlllOlllI Alrpart Indllllrill Plrk - p.o. Bex 114111- TUClan. AriZlllll 85734· Tel. (602/ 74fi.1111 • Twx: 910-952·1111 . Clbla: BBRCORP· Tal.x: 66-6491 PDS- 387A 6-229 Printed in U.S.A. July,l978 The MP22's address decoder is made up of exclusive-or gates which have open collector outputs so that the outputs of several gates inay be· connected together' through a single pull-up resistor. The address of the MP22js de~ermined by wiring the address select lines to either. grQund or +5 volts. Only when all of the address lines (A inputs) are in opposite states of their respective address select lines (A inputs) will the address decoder output go high. ANALOG MULTIPLEXERS Two B-channel CMOS analog multiplexers are,used on, the input which permits seiection of 16 single-ended orB differential inputs. A pseudo 16 channel differential mode of operation can also be achieved by connecting the amplifier's inverting input to a common, remote signal ground. Channels are'addressed by the address decoder which is connected directly to the microprocessor address bus. The number of input channels can be expanded without limit using external multiplexers. DELAVTIMER A time delay between chanriel selection and start of conversion is built into the MP22. This allows the analog multiplexer and the instrumentation amplifier time to settle before starting the AjD converter. As amplifier, gain increases, settling time increases, See Figure B. Factory set delay time ( 15/lsec) is sufficient for gains from unity to 50. At higher gains a capacitor must be added between pins 49 and 50 to increase delay. Figure 7 indicates the capacitance required to increase delay time. INSTRUMENTATION AMPLIFIER The instrumentation amplifier is a low drift, differential amplifier featuring high speed at gains above unity and gain programming with an external resistor. Gain may be selected from unity to 500. ANALOG-TO-DIGITAL CONVERTER The l2-bit AjD converter is a CMOS, successive approximation device with 45/lsec conversion time and three-state outputs. Laser-trimmed, compatible thin~film networks are used to assure linearity and siability over wide temperature ranges. CONTROL LOGIC The control logic generates signals to halt or interrupt the CPU while conversion takes place and to signal the CPU when conversion is complete and data can be read. Enable signals are also generated to gate the data onto the data bus. . ADDRESS DECODER Typical microprocessor systems have several thousand memory locations, teletype or CRT terminals, and possibly several MP22s. By using 12 address lines the microprocessor can communicate with as many as 212 or 4096 memory locations or peripheral devices, with each having its own unique address. REFERENCE The internal voltage' reference of the MP22 has been optimized for stable outputs with respect to temperature. Output current up to 2mA can be drawn externally from the reference outputs. . . ~ • !l {~~ 7 8 Lotc:h i ;.; o ~ " m: A103 A113 Add_ •• D....... CS .. AS 23 All .. 7:127 n. All.• • m.• • lnG. ~ !l~ !E 8a. . ~-~ A728 . >---- . DRQ43 AD. 60 LogIc BCheMei A_ Mulap..... :::: ~ ~~ ,J.~ -~ 48 DELAY OUT S2 'START CONY t An.1og To FIGURE I. Block Diagram "'''OUT 7IIA IN LO CONVERT COMMAND GAIN ADJUST .. 0 0 87 ADCIN N/C 6-230 ADC • .Rof Digital Convert... .7 DELAY ADJ. 51 DIGITAL COM -0 84 ANALOG COM n.o. Am • 7 ~ 31 • MUX SUP OUT 78 OFFSET NULL rV=N.. 1& - 37 +MUX SUP OUT I T1 MUX OUT LOW 2 IA IN HI/IIUX Dl,IT HI 1 IA QAIN SELlCJ 3 I" GAIN SELECT ii Logic .1 -Vee 12 +Ycc E- -0 50 LOGIC SUPPLY r- .--Co- Anol. . r ~ ftIIR44 RESET3I READY. 8 Control I }Ad_' ..... 1-48 Dr:: J, • Chenn.' Multiplexer .. 0 REF OUT . C 8.0 MICROPROCESSOR CONNECTION DIAGRAMS A. A. A" An Address Bus Address } Select A";"l 8080A Data Bus" MP22 A.'7 A, D, Reset Reset D,,\===::=.;::::;:==I A, Ready D,~------~~~------i 8080A ....._R_e_ad-=y-f MP22 A;;- As : 1/0 Select A; • "R:.:;E:::S",I:..:N_iReset 1-::==-fReady RDYIN DBIN Reset +SV A, A, A;;; MEMR System Reset LHLD Will initialize conversion and store data in HL registers MP22 Ba.. Address; • 10k pull down resislors required. IN FIGURE 2. MP22 Used with 8080 Halt Mode Memory Mapped V l ,(· AO = 0 A 1 ~ A4 channel select As - A, 1/0 select initializes conversion and reads 8 LSB's Store 8 LSB's in REG C Ao = I AS - A7 I/O select reads 4 MSB's MP22 Ba.. Address; MOVC,A IN MP22 Ba.. Address; • 10k pull down resistors required. DBIN Address Bus All CSt-----tVMA MP22 Logic Input FIGURE 4. MP22 Used with 8080 Halt Mode Accumulator I/O Riw 6800 Address Bus A, A" Z-80 A" A, 1m I-- I\1EM1f WAIT Do I-- ro.-", 0,1 AI2 An cs I-- MP22 Ready MEMW Do Bus' 0, ORIN Optional 4 Bit Address Decoder 74LS136 tpSV Prol!l:am to READ and STORE 16 channels of data using mock Transfer Instruction. STAA AO= 1 DO ;; 0 Destination Address ,NOP "-DA Destination Address NN paints to channel 0 MP22 LDHL,NN LDDE,MM MM points to the rust location of the destination LD BC,OIOOH byte counter (2 bytes/channel x 16) = 3210 LDI Load and increment Total Execution Time with tcy = .4#lS and conversion rate 40lo's is T = 3 (4jls) + 16 (6.4 + 40jls) = 7S4.4jlS. Starts conversion Halt AO = 0 8 LSB's, Resets MP22 AO= I 4 MSB's LOA Destination Address • 10k pull down resistors required . • 10k pull down resistors required. FIGURE 3. MP22 Used with 6800 FIGURE 5. MP22 Used With Z-80 (Halt Mode) DELAY TIME COMPONENT SELECTION CURVES TYPICAL PERFORMANCE CURVES 12 ~IO @8 e FIGURE 6. Typical Resistor. Value to Decrease Delay V 6 Time.~ -4 I ~ II ~ f 33 00 ./ I-""'" FIGURE 8. Differential Amplifier Settling Time vs Gain 66 100 133 166 200 10 RESISTOR VALUE (kilohms) 120 ':<100 "8 FIGURE 7. Typical Dela} Time vs Capacitor Value @ 80 .~ 00 1:1 >::40 :s ~ 0" o 1/ " ~ ~ 100 AMPLIFIER GAIN IL FIGURE 9. Differential Amplifier Common-mode Rejection vs Gain 0·.0017 .0033.00S .0067.0083 .01 CAPACITOR VALUE (microfarads) 6-231 1000 ELECTRICAL SPECIFICATIONS Typical at +25"C and rated supplies unless otherwise noted. MP22BG MOI)EL TRANSFER CHARACTERISTICS Resolution! I ~ Number of Channels Throughput Rate'" at G = I ANALOG INPUTS ADC Gain Ranges Bipolar'-" UnipolarO) Amplifier Gain Range Min Typ Max Units 12 12 : 16 Single-Ended/S Differential 45 12 Bits 55 I's/Channel 40 ±5 0-5 I to 500 REXT Input Voltage Without Damage Input Voltage for Multiplexer Operation Input Impedance Off Channel On Channel Bias Current 25"C O"C to +70"C Amplifier Output NoiseG= IOO,R,= 1500 ±16 ±6.0 Volts Volts 300 400 ±7.0 t(26 +190/G) nA nA mV, rms mV, POp mV I'V/"C 10 110 120 120 ppm/"C ppm/"C ppm/"C ppm/"C 15 I's I's I's p.s dB ±O.os ±O.I %FSR %FSR % FSR ±O 39 %FSR ±3 ±IO ppm/"C ppm/"C ±15 ±25 ppm/"C ppm/"C ±25 ±6O ppm/"C ppm/"C 5 x lO'n II 10pF 5 x lo'n II IOOpF 1.2 7.0 ±0.5 ±(7 + 9O/G) Amplifier Input Offset Amplifier Offset Drift (Rmu = 15k) Amplifier Gain Drift, (R EXT "IO ppm/"C) G= I G=IO G= 100 G = 1000 Gain Error Offset Error System RSS Accuracy at Gain = 500 and I kHz Throughput ADC Accuracy Drift Linearity Gain Reference Drift Ref Out (Pin 63) BPO (Pin 65) System Accuracy Drift (Excluding l.A.) Unipolar Bipolar Monotonicity (-25 to +85"C) Volts Volts (I + 25kn) Gain Equation Amplifier Sell ling Time to ±0.05% of FSR G= I'" G=IO G= 100 G =500 CMRR for Differential Inputs Dc to 60Hz ACCURACY System RSS Accuracy(2) at 25kHz Throughput ,G= I Linearity Differential Linearity J 20 25 100 84 74 ±O.os Adjustable to Zero Adjustable to Zero Guaranteed No Missing Codes (-25 to +85"C) (10 bits only) Power Supply Sensitivity (Excluding l.A.) ±Vcc Logic Supply Instrumentation amplifier Power Supply Sensitivity Guaranteed 6-232 ±O.OO8 ±O.OOO2 . %FSR/%~V (1+2/G)IO-' %FSR/%~V %FSR/%~V MPi2BG MODEL Min Typ Max Units ~iPolar DIGITAL INPUT/OUTPUT Bipolar Code Unipolar Code Logic Loading Pin (21) Pin (60) Output Drive Analog Input Channels Selected By: Offset Binal Unipolar Straight Binary 3LSTIL 2LSTTL I TIL Load AI-A4 Output Data: DO-D7 POWER REQUIREMENTS Rated Voltages(l) Range for Rated Accuracy (l.ogic Supply. ±V,,) ±V •.• Operating Range ±JO ±15, +5 4.75 to 5.25 and ±IIA to ±15.75 ±18 Volts Volts Volts Supply Drain +V" -V" Logic Supply Power Dissipation (±V n , = ±12V) JO 15 80 20 20 160 700 1300 rnA rnA rnA mW +85 +100 +125 "C TEMPERATURE RANGE -25 -40 -55 Specification Operating Storage "C "C NOTES: L These parameters are 100% tested. 2. Gain and offset adjusted to zero. 3. External amplifier required. PIN CONNECTIONS MECHANICAL P Pin I 2 ~4ti2;~=1 2.54mm (0.10") o~oo 2.54mm~oI2 ·L (0.10") : •• 0 0 7980o~ : : o 0 _!!.....L T -0 2.54mm (0.10") : 0 : 0 0 0 0 S4.61mm (2 15") : ~ ~ 00° 0:::: (TOP VIEW) : : o o o : : : 0 0 0 : ~9 40 41 42 .0 5.08mmt-- 27.9mm (0.20") I - (1.10") 0 : 10 II 12 13 14 IS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 T ,l J.27mm (0.05") 0 : 0 0 : I -I -38.lmm(1.5") "1-----..,.-----1 5.6mm I UU I -....... O.51mm (0.02") I~ (0.22") T 3.8mm (0.15") MATERIAL: Ceramic WEIGHT: 32 grams (1.2 oz.) PINS: Pin material and plating composition conform to Method 2003 (solderability) of Mil-S'd-883 (except paragraph 3.2) MATING CONNECTOR: 2350MC (Set of four 20 pin strips) HERMETICITY: fluorocarbon (gross leak) 6-233 IA GAIN SELECT Pin 41 DACK7IN'fA 42 INT IA IN HI/MUX OUT HIGH 43 DRQ IA GAIN SELECT 44 MEMR ADC GAIN ADJUST 45 DBIN IN7 46 MEMW IN6 47 DELAY ADJ. INS 48 READY IN4 49 DELAY OUTPUT IN3 50 +SY LOGIC SUPPLY IN2 51 DIG. COMMON INI 52 START CONY. INO 53 D7 (MSB) MUX ENABLE I 64 D6 MUX ENABLE 2 55 D5 SIN/DIF 56 D4 AD 57 D3 Al 58 D2 A2 59 DI A3 60 DO (LSB) A4 61 -Yee LOGIC INPUT 62 +Yee AS 63 REF OUT AS 64 ANA. COMMON A6 65 BPO A6 66 NO CONNECTION A7 67 ADC IN A7 68 IA OUT A8 69 IN8 RETD AS 70 IN9 RET! A9 71 INIO RET2 A9 72 INII RET3 AIO 73 INI2 RET4 ITo 74 INI3 RET5 All 75 INI4 RET6 Ail 76 INI5 RET7 CHIP SELECT (CS) 77 MUX OUT LOW +MUX SUPPLY OUTPUT 78 OFFSET NULL -MUX SUPPLY OUTPUT 79 IA IN LO RESET ADDR DECODE 80 ENI OPERATING INSTRUCTIONS The MP22 is designed to be used as a memory-mapped or an accumulator 1/0. Since there are many powerful memory reference instructions, the MP22 is used most efficiently as a memory-mapped device. Pins A5 through All are provided so that the microperipheral can be hardwired for any base address within a 4096 word block of the memory field. The address decoder output is available and can be easily expanded to 16 bits. If used as a memory-mapped microperipheral, the MP22 can provide three modes of operation: HALT Mode, INTERRUPT Mode and .DMA Mode. More detailed application instructions are given in the operating manual. available upon request. Example: HALT MODE After power up (or manual) reset, the MP22 is automatically set for operation in the HALT Mode. This mode requires minimum software to acquire data. To use the MP22 in the HALT Mode connect the MP22 READY line to the 8080 READY input (see Figure 2). When a memory reference instruction such as LHLD is executed, the READY line goes low, halting the CPU for the duration of the data conversion (45 p.sec, gain = I). When the convursion is complete the READY line goes high, signaling the CPU exit the wait state and enter the T3 state to read the 8 LSB's. After reading the 8 L8B's, the CPU increments the memory address register and reads the 4 MSB's. When the most significant data byte has been read, the internal logic resets and the MP22 is ready for the next conversion. MP22 base address IF72H_ MVIA oOH STA IF72H ST AR T conversion Continue with program. INT will arrive 40 ~sec after start of conversion. INCA INT arrives here User will jam RST instruction which will provide address of an interrupt hand· ling routine and store program counter. CPIA INTERRUPT Subroutine: PUSH psw Store Ace. and Flags PUSH H PUSHD PUSH B EI LHLD IF72H ~:~ t AlS AI4 AIJ AU All AID A9 AS A7 A6 AS A4 A3 A2 AI AO x Store reg. if necessary Enable interrupt READ DATA from MP22 Channel 10 L = 8 LSB's H= 4 MSB', Process data Example: x ~ x I 0 M P22 Base Address I I == I 0 0 I 0 POP H Channel Select ~ POPPsw Restore registers an d flags Restore program counter RET MP22 used with 8080; read MP22 base address: IF72H channel 10. LHLD IF72H acquires and transfers data to CPU from channel 10. The 8 LSB's (at location IF72H) are transferred to register L and the 4 MSB's (at location IF73H) are transferred to register H. Total time: 16 tcy +40p.sec = 47.8p.sec(fortcy =488nsec [8080A]). The user must supply an instruction op code to the processor during the next DBIN time after the INTA status appears. This is usually done through use of an RST instruction. INTERRUPT MODE To use the MP22 in the INTERRUPT Mode connect the INT and DACK/INTA lines to the 8080's INT input and INTA output respectively. Conversion is initiated by writing DO = 0 into the MP22. When the conversion is complete the MP22 generates an INT signal which will remain low until INTA is received from the 8080. DIRECT MEMORY ACCESS MODE To use the MP22 in the D MA Mode connect the MP22 to the DMA controller. The controller is initialized by the CPU before reading data from the MP22. To accomplish a block move the CPU loads the 8257 with the starting address of the source block (the MP22 location) with AO = 0 and the length of the block (L = I) into channel O. Channell is programmed with the starting location of the destination block and the length (L = I). 6-234 N ext, start conversion by writing DO = 0 into the MP22. When the conversion is complete, the MP22 will generate a DRQ request on channels 0 and I. The 8257 is initialized to the rotating priority mode, therefore the first DMA cycle is from channel 0 which latches data from the first location of the source block into the 8212. The second cycle will be from channel I which will store the latched data in the first location of the destination block. The next cycle will return to channel 0 and the sequence will start over again until the terminal count is reached. When the terminal count for channell is reached, DACKI and TC signals are generated and MP22 DRQ line is reset. divides the magnitude of the input by two, and the connection of a 12.5kO resistor between pin 63 (ref out) and pin 78 (offset nUll) offsets the signal such that the AID converter sees a unipolar voltage from 0 to +SV. ANALOG INPUT RANGE SELECTION The MP22 may be set for any range between ±5V and ±lOmV. Pin connections for the high level ranges available are shown in Table I. POWER SUPPLV CONSIDERATIONS For best performance and noise rejection, power supplies should be decoupled with 1.0p.f tantalum or electrolytic capacitors in parallel with 0.0 I p.F ceramic capacitors. To insure proper power supply sequencing, a diode should be connected between the pins 50 and 62 with the anode connected to pin 50. A 0.1 p.F ceramic capacitor is required on each of the lines +MUX SUPPLY OUT (pin 37) and -MUX SUPPLY OUT (pin 38). Each is tied from the respective pin to ground. MP22 Input Range Gain ADC Range Pin Connections ±5V I ±5V See bipolar operation 0-5V I 1I-5V 65, 63 open; connect 67 to 68 To null the gain and offset errors of this circuit, follow this procedure: I. Input - 5.0000V to any MP22 channel. 2. Adjust R I until a digital output of all zeros is lbtained. 3. Input +4.99817V to that MP22 channel. 4. Adjust R2 until a digital output ofOFFFH is obtained. TABLE I. Analog Input Range Pin Connections In the unipolar mode the MP22 output data is straight binary. In the bipolar mode it is bipolar offset binary. If two's complement output is needed an external threestate inverting buffer is required. Gain of the internal instrumentation amplifier (without external gain adjust) is 1.0. This gain can be increased to any value between 1.0 and 500 by adding an external resistor between pins I and 3. This external resistor (R) should be stable (10 ppm;oC or better) because its drift will add to the system accuracy temperature coefficient. Gain of the amplifier is determined by this formula: External resistor R.. t connected: Gain = I + 25kOI Rext Pins I and 3 open: Gain = 1.0 ±O.02% IOOkO OPERATION WITH BIPOLAR INPUT VOLTAGES To operate the MP22 with bipolar input voltages of±5V, connect the unit as shown in Figure 10. Amplifier AI FIGURE 10. Connection for ±5V Input ANALOG INPUT ±5V +Full Scale o to +5V 50kO R, DIGITAL OUTPUT ±5mV OFFSET BINARY STRAIGHT BINARY TWO"S COMPLEMENT 4.9975V O.ooooV 4.9988 V 2.5000 V 4.9975 mV 0.0000 FFF. FFF. 7FF. Mid Scale 800. 800. 000. -Full Seale -5.OOOOV 0.0000 V -5.0000 mV 000. 000. 800. One LSB 2.44mV I.22mV 2.44I'V TABLE II. Analog Input, Digital Output Relationship 6-235 APPLICATIONS DATA ACQUISITION FROM THERMOCOUPLE INPUTS Thermocouples are often used as temperature sensors for process control systems. Thermocouples are characterized by temperature coefficients of 10 to 70p. VI·C and operating ranges of minus hundreds to plus thousands of degrees centrigrade. When the MP22 is operated with an instrumentation amplifier gain of 100 or more, it may be connected directly to these devices. The wire runs from thermocouple to measuring device often pick up large common-mode noise signals of 60 Hz or higher frequencies. When the MP22 is used as an eight channel differential input system, the high commonmode rejection of the instrument amplifier will reject common-mode noise. To minimize differential mode noise, the signal wire should be twisted and if possible shielded. As a rule, an unshielded twisted pair is better than a coax, and a shielded, twisted pair is still better. In applications where these wiring practices cannot always be observed, a differential RC filter may be used. Figure II shows such a system. The 10 kO resistors and 10p.F capacitor provide low pass filtering (fo = 0.8 Hz) while the optional I MO resistors supply bias current to the instrumentation amplifier. The Isothermal Barrier Strip remote sensor should be earth grounded to prevent common-mode voltages from exceeding the ±Svolt range of the multiplexer. If the sensor is earth grounded, the IMO resistors are not required. The I MO resistors do not enter into an error calculation for input errors because the low resistance of the sensor shorts any differential voltage that might be caused by the offset (difference current) of the amplifier. Offset or difference current is merely the difference between the bias currents of the two inputs. The I MO resistors could have been put on the output side of the multiplexer eliminating the need for repeating them for each input; however, this would have loaded the IOkO resistors of the filter causing a possible I % error for static conditions. To complete a thermocouple system it is necessary to terminate all thermocouple wire pairs at an isothermal box or connector strip of some type. An ordinary barrier strip maybe monitored to allow the observed thermocouPle emf to be cold junction compensated. Figure II shows an excellent circuit for this purpose. Its output is connected to one of the input channels to supply ambient temperature data to the system computer. Its output sensitivity is approximately 2 mV rC. ___"': ... Optional --IH"':"'Lo-W-" Pass FUter Bias Current Supply Resistors +15 10k L lOOk 8835008 Dual monQlithic transistor pair (National LM1l4) mounted near isothermal barrier strip FIGURE 11. Thermocouple Input System Using MP22 6-236 ------+15 -15 +5 BURR-BROWN® MP32 IElElI Microprocessor-Interfaced 12-BIT DATA ACQUISITION SYSTEM DESCRIPTION FEATURES • INTERFACES WITH 8080A. 8048. Z-80. SCIMP MICROPROCESSOR WITHOUT ADDITIONAL COMPONENTS • INTERFACES WITH 6800. 650X. F8. 8085 MICROPROCESSORS WITH MINIMAL EXTERNAL LOGIC • COMPATI8LE WITH PDP-8. PDP-11. NOVA. ECLIPSE MINICOMPUTERS • EASY TO PROGRAM One instruction acquires data as a memory-mapped device Two instructions acquire data as an accumulator liD device The MP32 is a complete analog input system and interfaces to many microprocessors without additional external components. Contained in an 80-pin quad-in-line package, it includes a l2-bit CMOS AID converter, instrumentation amplifier, input multiplexer that accepts up to 16 single-ended signals or 8 differential signals; an addess decoder, and control logic. Logic to generate interrupt, halt, and direct memory access request signals is also included. The system can digitize low level or high level analog signals. Gain of the internal instrumentation amplifier can be programmed with a single external resistor allowing input ranges as low as ±lOmV. pP ADDRESS BUS GAIN 1 - - - 0 ADJUST pP CONTROL BUS AID pP DATA BUS CONVERTER Intemlliooal Airporl Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021746·11 I1 . Twx: 9111-952·1111 • Cable: BBRCORp· Telex: 66-6491 PDS-424A 6-237 DESCRIPTION (CONT) ANALOG MULTIPLEXERS ANALOG-TO-DIGITALCOt.lVERTER Two 8-channel CMOS analog multiplexers are used on lhe inp.ut which permits selection of 16 single-ended or 8 differential inputs. A 16-channelpseudo-differential mode of operation can also be achieved by connecting the amplifier's inverting input to a common, remote signal ground. Channels are addressed by the address decoder which is connected directly to the microprocessor address bus. The number of input channels can be expanded without limit using external multiplexers. INSTRUMENTATION AMPLIFIER The instrumentation amplifier is a low drift, differential amplifier featuring high speed at, gains above unity and gain programming with an external resistor. Gain may be selected from unity to 500. The 12-bit A/D converter is a CMOS, successive approximation device with 40j.lsec conversion time and three-state outputs. Laser-trimmed, compatible thin-film " networks are 'used to assure linearity and stability over wide temperature ranges. ADDRESS DECODER The 12-bit address decoder has been included in the MP32 so the device can be uniquely specified within 4k bands of the address field. Iffurther decoding is required, the chip select (CS) pin can provide a 13th bit or the output of an external decoder can be connected to the internal address decoder output "wired-AND" node. --- ;;:.;...., Decoder } ~ 1== ~ RESET 39 CJ \. READY 48 DRQ43 ~ I Select rl Multlplex.r Control Logic Multiplexer ~ - 0159 ~ ~ 61·ISVDC 62 +15VDC 3'l:NC . . NC ~ 5O+5YDC ,),..r f.o I- fiji' + :: ~ ~ r I Delay Control Logic 0 .... ~ ~ Analog 51DIGeOM 64 ANA COM 77 MUX OUT LO 2 IA IN HI/MUX OUT HI 1 IA GAIN SELECT ' 3 IA GAIN SELECT Add.... D~~~: i!c {::: Analog r-r-n Address ,-Channe' B~Ch.nnel Latch ~ 78 OFFSET NULL BIIA OUT IV' 79IA IN LO 49 DELAY OUTPUT • CONVERT COMMAND 52 START CONY 12-BII 0258 D357 +Rel AID Converter \ g:: 4 ADC GAIN ADJUST DO .. 0753 0 0 47 DELAY 0 0 07 ADCIN 66 NC . ADJUST FIGURE I. System Block Diagram. , 6-,238 0 C os 63 AEFTEST BIPOLAR POINT OFFSET DELAY TIMER A time delay between channel selection and start of conversion is built into the MP32 and is described in detail in the Analog Input Configuration section. Enable signals are also generated to gateth.edata onto the data bus. REFERENCE The internal voltage reference of the MP32 has been optimized for stable outputs with respect to temperature. Output current up to 2mA can be drawn externally from the reference outputs. CONTROL LOGIC The control logic generates signals to halt or interrupt the CPU while conversion takes place and to signal the CPU when conversion is complete and data can be read. SPECIFICATIONS ELECTRICAL Typical at +25°C and rated supplies unless otherwise noted. MP32BG AND MP32CG I MODEL I MIN TVP I MAX I UNITS TRANSFER CHARACTERISTICS Resolution(1) Number of Channels Throughput Rate(') at G 12 If ~ 1 50 Single-end!~/8 Differentilal 70 I 12 Bits 80 ,",sec/Channel ANALOG INPUT/OUTPUT ADC Voltage Input Ranges(2) Bipolarl') Unipolan') Amplifier Gain Range Gain Equation Input Voltage Without Damage Input Voltage for Multiplexer Operation Input Impedance Off Channel On Channel Bias Current +25°C OOC to+7ooC Amplifier Output Noise G ~ 100. Rs ~ 15000 ±10 Oto+l0 1 to 500 1 + (25kO/ReXT) 1.5 1.2 7.0 ±O.5 ±17 + (go/G)I Amplifier Input Offset Amplifier Input Offset Drift (Rsource == 1.Skfl max) Amplifier Gain Drift. (ReXT '" 10ppm/oC) G~1 G~10 G~I00 G~500 Amplifier Settling Time to ±O.OI% of FSR G ~ 1(1) G~10 G~I00 G ~500 CMRR for Differentiallnpuls DC to 60Hz Instrumentation Amplifier Power Supply Sensitivity 80 V V VIV ±35 ±10 V V 10'· 1.8 0 kO 300 400 nA nA mV, rrns mV.p-p mV ±7.0 ±126+(lgo/G)[ ~VloC ±10 ±110 ±120 ±120 ppmfOC ppmfOC ppmfOC ppmfOC 15 ",sec ",sec 20 25 100 84 ",sec ",sec dB [1 + (2/G)[10-4 % FSR/%.l.V ACCURACY System RSS Accuracy(4) at 25kHz Throughput G~I.BG ±o.05 ±0.025 ±o.025 ±o.0125 CG Linearity. BG CG Differential Linearity. BG CG ±O.025 ±o.0125 Gain Error %FSR %FSR %FSR %FSR Adjustable to Zero Adjustable to Zero Offset Error System RSS Accuracy at 1kHz Throughput G~500 ±o.39 %FSR ±3 ±10 ppmfOC ppmfO ±15 ppmfOC ppmfOC ADC Accuracy Drift Linearity Gain Reference Drift Ref Out (Pin 63) Bipolar Offset (Pin 65) 'System Accuracy Drift (Excluding IA) Unipolar ,Bipolar No Missing Codes (-25°C to +85·CIIBits 1 thru 12)CG (Bits 1 thru 11 )BG ±25 ±25 ±60 Guaranteed Guaranteed 6-239 ppmfOC pprT'fOC ELECTRICAL (CO NT) MP32BG AND MP32CG MODEL MIN TYP MAX Power Supply Sensitivity (Excluding IAI ±t5VDC +5VOC UNITS %FSR/~V ±O.OOS ±O.OOO2 % FSR/%.lV DIGITAL INPUT/OUTPUT Bipolar Offset Binary Unipolar Straight Binary Biopolar Code Unipolar Code Logic Loading Pin (21) Logic Loading Pin 160) All Other Digital Inputs Output Drive Analog Input Channel. Selected By: Output Data 3LSTTL 2LSTTL 1LSTTL lTTL Load Al-A4 00-07 POWER REQUIREMENTS Rated Power Supply Voltages(') Power Supply Range. for Rated Accuracy Power Supply Operating Range 1±15VOC only) Supply Drain +15VOC -15VDC +5VDC Power Dissipation (at rated supplies) J.75 to +5.25±~~;/:11.4 to ±15.~5 ±10 10 15 80 700 ±18 VDC VOC VDC 20 20 160 1300 mA mA mA mW +85 +100 +125 ·C ·C ·C TEMPERATURE RANGE -25 -40 -55 Specification Operating Storage NOTES: 1. These parameters are 100% tested. 2.lnput voltage must be kept 2V below supply voltage. 3. External amplifier required. 4. Gain and offset adjust to zero, MECHANICAL n PIN ASSIGNMENTS ir' ~l··· ................ 79 41 • ~. r IA GAIN SELECT IA IN HIIMUX OUT HI IA GAIN SELECT ADC GAIN ADJUST IN7 IN6 IN5 IN4 IN3 IN2 IN' INO MUX ENABLE' MUX ENABLE 2 SIN/DIF AD A1 A2 42 . 0 I C 3. -Lt:oooooo:oOOOOO"~1 L E. ~' L G INCHES DIM D MAX MIN MAX A 2.120 2180 53.85 55.37 B 1.S70 .,. 1720 42.42 43.69 C .110 .230 4.32 5.84 .021 0.46 0.53 .050 08 • 1.21 F .035 G .100 BASIC H .100 BASIC 2.54 BASIC K .150 3,81 L N p R .250 1.500 BASIC .002 010 .050 BASIC .100 BASIC A4 LOGIC INPUT A5 MILLIMETERS MIN 0 A3 ,-tL~JJ AS AD AS A7 A1 AS 2.54 BASIC 6.35 38.1 BASIC 0.05 0.25 AS NOTE: LEADS IN TRUE POSITION WITHIN 0.015" ,0.38mm, R@ MMC AT SEATING PLANE . A9 AS A'O A'O Al1 Al1 CHIP SELECT, CS, NC NC RESET ADDR DECODE 1.27 BASIC 2.54 BASIC T .200 BASIC 5.08 BASIC u 1.100 BASIC 27.94 BASIC Pin numbers shown for reference only. Numbers may not be marked on package. MATERIAL: Ceramic WEIGHT: 32 grams 11.2 OZ. I MATING CONNECTOR: 2350MC Iset of four 20 pin strips I 6-240 Pin 1 2 3 4 5 6 7 8 9 10 11 12 '3 '4 '5 '6 17 '8 '9 20 2' 22 23 24 25 26 27 28 29 30 31 No. 4' 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 6' 62 63 64 65 66 67 68 36 69 70 7' 72 73 74 75 76 37 77 38 78 79 32 33 34 35 39 40 60 DACKIINTA INT ORO MEMR DBIN MEMW DELAY AOJUST READY DELAY OUTPUT +5VDC DIG COM STARTCONV D7,MSB D6 OS D4 D3 02 D1 DO ,LSB -15VDC +15VOC REF TEST POINT ANA COM BIPOLAR OFFSET NC ADCIN IAOUT IN8/RETO IN9/RET' IN'O/RET2 IN11/RET3 IN'2/RET4 IN'3/RET5 IN14/RET6 IN'5/RET7 MUX OUTLO OFFSET NULL IAINLO EN1 DESCRIPTION OF PIN FUNCTIONS NUMBER DESIGNATiON DESCRIPTION Pins I and 3 IA GAIN SELECT (Optional). By connecting a resistor between pins I and 3, the gain of the internal instrumentation amplifier can be varied as follows: Gain = I + (25kClj R) where R is the gain setting resistor. Gain can be set from I to 500. Important: If a gain grea,ter than 50 is required. an external capacitor must be connected from DELA Y ADJUST (pin47) to+SVDC (pin 50). This increases an internal delay to allow for the increased settling time required by the Instrumentation ampliHer. Pin 2 lAIN/HI MUXOUTHI This is the positive input of the internal instrumentation amplifier, and the "high side" of the multiplexer. Fordifferential operation this pin is left open. For single-ended operation connect pin 2 to pin 77 and pin 79 to pin 64. Pin4 ADC GAIN ADJUST This pin is used to adjust gain of the ADC (see F~gures6 and 7). !fno external gain adjustment is needed, this pin is left open. Pins 5 thru 12 IN7-INO The firstS (of 16)analog inputs for single-ended operation orthe 8 positive inputs for8-channel differential input operation. Pin 13 MUX ENABLE I lea~e open for singJe-ended ope,ration .. Connect to ~UX ENABLE 2 (pin Pin 14 MUX ENABLE 2 Connect to SIN/ DIF (pin IS) for single-ended input operation. Connect to pin 13 (MUX ENABLE I) for differential input operation. Pin 15 SIN/DiF Connect to MUX ENABLE 2 (pin 14) for single-ended operation. leave open for differential input operation. Pin 16 AO In the Halt Mode AO = "Oft'and ~R ="0" will start conversion and enable 8lSB's; AO ="1" enables 4MSB's. At the start of conversion, the output registers are not cleared. Pins 17 thru 20 AI-A4 Address lines that select one of 16 analog input signals (INO-I N IS). 0000 selects channel 0 and 1111 selects channel 15 when the correct address is presented to the MP32. A4 is connected to DIG COM (pin SI) for differential operation. Pin21 LOGIC INPUT Connect to pin 40. See signal description under pin 40. Pins 22,24,26, 28, 30, 32, 34, 36 AS-All, CS Address lines. When the proper address is presented to the MP32, the internal logic is enabled for conversion or data output. CS is used as a chip select or the most significantaddress bit. It must be'" "to enable the unit. Pins 23, 25, 27, 29,31,33,35 A5-Aii Address select lines. These lines are used to program the address decoder to respond to a particular address. This is done by connecting these pins to +SVDC or ground such that the bit pattern is the complement ofthe desired address that appears on the corresponding bit lines. Pin 37 NC No connection. Pin3! NC No connection. Pin 39 RESET A "low" on this line is required to RESET the MP32. Connect to system reset line. Pin 40 ADDRDECODE A positive pulse will appear when a valid ad~ress appears on the M P32 address lines. This pin is usually connected to lOGIC INPUT (pin 21). The rising edge of this pulse strobes the input channel select information (AI:-A4) into an internal latch. It can also be used by the user for other system timing. Pin41 DACK/INTA I n the Interrupt M ode, this pin is connected to the microprocessor interrupt acknowledge pin. This is an active low signal. If not used. connect to +SVDC through a I kIl resistor. Pin 42 INT In the Interrupt Mode', this signal is connected to the microcomputer system interrup~. Once the conversion is completed the MP32 generates an INT signal which will remain high until an u:.rr:J:' signal is received from the microcomputer. This is an open--collector LSTTL signal and must ~e pulled up with an external resistor. Pin 43 DRQ In the DMA Mode, this pin is connected to the direc~ memory access request line of the microcomputer system. Once conversion is complete, the MP32 will generate a DRQ signal which will remain high until'i5A£1( is Pin 44 MEMR Memory read. A "low" pulse on this line is used to start a conversion in the Halt Mode. If not used, connect to +SVDC through a IkO resistor. Pin 45 DBIN Connect the DBIN on 8080A. If used with any other microprocessor, connect through I kO resistor to +SVDC. Pin 46 MEMw' Memory write. A "low" pulse on this line along with DO = 0 will start conversion in the Interrupt or DMA Modes provided that lOGIC INPUT (pin 21) is "I", If not used, connect to +SVDC through a Ikl} resistor. Pin 47 DELAY ADJUST When the IA is operated with gain greater than SO, the delay time must be increased (see Figure II) to allow for the increased settling time of the lAo Pin 48 READY In the Halt Mode connect this output signal to the input that will cause the microprocessor to enter the"Wait" state (such as the READY input on the 8080). A 10gic"'O" causes the microprocessor to halt to allow time for the analog circuitry to settle and the conversion to be completed (70l£sec with gain E; SO). After conversion. the READY line will return to logic "I" which releases the microprocessor from the "Wait" state. The output data then appears on the data bU:i. Pin 49 DELAY OUTPUT When the M P3~ is addressed, an internal delay of approximately ISl£sec is initiated to allow for multiplexer and instrumentation amplifier settling time. Pin 49-must be connected to START CONY (pin S2). This point may be connected to a sample/hold control inpu:t if an external SIH is used. Pin SO +SVDC +SVDC at l60mA, max. PinSI DIG COM Digital commmon. This pin should be connected t,o ANA COM (pin 64) as clo~ to the MP32 as possible for optimum performance. Pin 52 STARTCONV This pin should be connected to DELAY OUTPUT (pip 49). Pins S3 thru 60 D7-DO 8-bit data bus. Tri-state low power Schottky TIL--compatible. -ISVDC at lOrnA, max. 14) for differential input operation. rece~ved. Pin 61 -ISVDC Pin 62 +I5VDC + I5VDC at 20mA, max. Pin 63 REF TEST POINT Test point for reference testing. Pin 64 ANA COM Analog common. This should be connected to DIG COM (pin SI) as close to the MP32 as possible for optimum performance. Pin 65 BIPOLAR OFFSET +SVDC voltage reference output. 2mA can be supplied from this pin without degradation. 6-241 DESCRIPTION OF PIN FUNCTIONS (CONT) DESCRIPTION NUMBER Pin 66 DESIGN...110N Pin 67 ADCIN Pin 68 IAOUT Pins 69 thru 76 IN8/RETO -INIS/RET7 Pin 77- MUX OUT LO Pin 78 OFFSET NULL Pin 79 IAINLO Instru'mentation amplifier offset adjust (see Figures S, 6, and 7). Negative input of the instrumentation amplifier. Conn~t to ANA COM (pin 64) for single-ended input operation PinKO ENI Output signal which enables 4MSB's. See Figure 14 for "'-Hization to obtain two's complement. For a straight. No connec.tion. AID converter input.. Connect to lA OUr (pin 68). If external SI H used. connect to SI H output. NC Instrumentation amplifier output. Connect to ADC IN (pin 67) for normal operation. If external SI H used, connect to SIH input. Analog inputs 8 through I S (or singlMnded operation or anaJog returns 0 throuah 7 for differential input operation. Multiplexer output for IN8/RETO -INIS/RET7. Connect to IA IN HI/MUX OUT HI (pin 2) for single-ended input operation or connect to IA IN LO (pin 19) for differential input operation. or MUX OUT LO (pin 77) for differential input operation. biliary oUtput this pin is left open. OPERATING INSTRUCTIONS ADDRESSING MODES In the memory-mapped addressing mode, the MP32 is regarded as a block of memory locations, each with its own uniq ue address. Since the outpUt data word is 12 bits long, it req uires two address locations for each word. The M P32 is connected to the microprocessor just as though it were memory, using the memory control lines. The address word format is illustrated in Figure 2. Address bits A5 through A 12 (A 12 is connected to CS, or CS can be used as a chip select) identify a particular M P32 unit. The bit pattern of A5 through A 12 is selected by the user by connecting inputs A5 through A 12 to logic I or logic O. A I through A4 select the particular analog input channel. AO is used as a byte select (see Description of Pin Functions). The byte select bit is sequenced as specified in the discussion on operational modes. The advantage of using memory-mapped addressing is the flexibility of programming. All of the many memory reference instructions can be used to control MP32 operation. AI5 AI4 AI3 AI2 All AID A9 AS A7 AS AS A4 A3 A2AI AD I I I I I 1II I I I· II I I I I X X X v MPaz Addr.. '~Y Channel Byle SelIC! Selacl FIGURE 2. Address Word Format are not used by the MP32. If it is necessary to expand the addressing capability to include these 3 additional bits, .the output of an external 3-bit address decoder can be used in conjunction with the ADDR DECODE signal output of the MP32, to provide the LOGIC INPUT signal required by the MP32. OPERATIONAL MODES (Memory-Mapped) Halt Mode After powerup (or manual) reset, the MP32 is automatically set for operation in the Halt Mode. This mode . requires minimum software to acquire data. To use the MP32 in the Halt Mode connect the MP32 READY line to the 80S0READY input (see Figure 15). When a memory reference instruction such as LHLD is executed, the READY line goes low, halting the CPU for the duration of the data conversion (50"sec, gain = I). When the conversion is complete the READY line goes high, signaling the CPU to exit the wait state and enter the T 3 state to read the SLSB's. After reading the SLSB's, the CPU increments the memory address register and reads the 4MSB's. When the most significant data byte has been read the internal logic resets and the MP32 is ready for the next conversion. Example: AIS AI4 AIJ A12 All AtO A9 A8 A7 At) AS A4 AJ A2 AI :\0 x x x I M P32 Input/Output Addressing Input/ output addressing is accomplished by considering the MP32 as an input/ output or peripheral device. Thus . the 110 control signals are used to operate the unit. The addressing scheme is the same as that described in the Memory-Mapped Addressing section. The user may be forced to use I/O addressing if all of the available memory addresses have been taken up with memory or other memory-mapped devices. Addr..s Expansion The 8-bit MP32 base address (A5 through All and CS) enables one of 256 bands of locations in the address field. The top 3 bits of the 16-bit microprocessor address bus Ba~e 0 " I Address I 0 0 I == 0 Channel Select MP32 used with SOSO; read MP32 base address: IF72H channel 9. LHD IF72H acquires and transfers data to CPU from channel 9. The 8LSB's (at location IF72H) are transferred to register L and the 4MSB's (at location I F73H) are transferred to register H. Total time: 16tcy + 50"sec = 57.S"sec (for tcy = 4SSnsec 8080 A) InterrUpt Mode To use the MP32 in the Interrupt Mode connect the INT and DACK/INTA lines to the 80S0's INT input and 6-242 INTA output respectively (see Figure 16). Conversion is initiated by writing DO = into the MP32. When the conversion is complete the M P32 generates an INT signal which will remain low until INTA is received from the 8080. Example: MP32 base address lF72H MYl A.OH OOH STA IF72H cycled repeatedly by inserting the desired memory starting address and the terminal count into the program. Programming For DMA Operation 3TAR T conversion Continue with program. INT will arrive 50~sec after start of conversion. INT arrives here User will generate RST instruction (usually done with an 8227) which will provide the address of an interrupt handling routine and store program counter. INTERRUPT Handler: PUSH psw PUSH H } PUSH D PUSH B El LHLD IF72H POP B POP D POP H POP f psw Store ace. and flags ISIIIII conVlrllln when '--_,--_...J DMA Store reg. if necessary Inlbledl Enahle interrupt READ DATA from MP32' Channel 10 L= 8LSB's H = 4MSB's Process data Restore registers and flags Restore program counter ENTER: RET Polled Mode The electrical connections for the Polled Mode are the same as that for the Halt Mode, except that the MP32 READY line is not connected. Programming in the Polled M ode is also similar to that of the Halt Mode except that after starting the conversion with a memory reference instruction, the program continues to run. After sufficient time has elapsed for the' com pletion of the conversion, the most significant data byte is read. If the MSB is set, the conversion is still in progress. When it has been determined that the conversion has been completed, the least significant, arid then the most significant data bytes are read. Reading of the data will begin a new conversion which may either be ignored or it can access the next analog channel of interest. In either case, the data from the first conversion will not be affected. Direct Memory Access Mode Data from the MP32 can be updated automatically and stored in a dedicated part of system memory by using the Direct Memory AcceSs (DMA) mode of operation. Figure 3 illustrates the DMA connection for an8080 microprocessor. Since the MP32 address decoder is not needed for this mode of operation it can be used to provide address selection for the DMA controller (model 8257). This interface is designed to operate on the I/O bus. The following program can be used to operate the DMA interface. Any number of adjacent M P32 channels can be MVI A. XX OUT X4H MVI A. YY OUT X4H MVI A. XX OUT X6H MVI A. YY OUT X6H MVI A. XX OUT X7H MVI A. OUT X7H MVI A. 0 OUT X5H MVI A. 0 OUT X5H MVI A. 84H OUT X8H ;Lold Chlnnel 2 wilh DMA Starting Addrlll ;Load Channel 3 with DMA Starting Address ;Load Channel 3 with Terminal Counl a ;Load Channel 2 with 0 Tuminal Count ;Set Mode Reg. for Autolllld and enable Channel 2 The interface is designed to always start on analog input channel O. The interface requires one pass through all channels to intialize. The data put in memory through this initial pass will most likely be erroneous and should be dis~egarded. OPERATIONAL MODES (Input/Output) Each memory-mapped operational mode can also be used on the I/O bus. When used with the I/O bus the appropriate address lines and timing signals (i.e., I/OR instead of MEMR) must be applied. In addition, the appropriate READ and WRITE instructions must be used. For the 8080 this would mean substituting the following sequence for LHLD XXXXH: INXXH MOVL,A INXX+1.H MOVH,A 6-243 07 8080 System (BOiIO. B224. and 8228) 07 DATA BUS DO A7 A6 rio CS All ADDRESS BUS AD A5 A4 A3 A2 IIOR A1 RESET Bm DBIN AD RESET BUSEN 1---;------' 1~~---+------r-------+-------~ MP32 LOGIC INPUT ADDR DECODE DACK2 MEMW 8257 MEMR DRQ2 t-----t---------------j READY RESET FIGURE 3. MP32 /8080 Connection for DMA Operation (I/O Mapped). TIMING The unipolar input connection diagram is shown in Figure 7. Table II gives a summary of circuit configurations for several input ranges. The internal timing diagram and timing constraints of the MP32 are shown in Figure 4 and Table I. The MP32 is compatible with any digital system that can operate within the timing constraints shown. TABLE II. Analog Input Configurations. CONFIGURATION UNIPOLAR AND BIPOLAR OPERATION The MP32 will convert either unipolar bipolar voltage inputs. Unipolar input ranges vary from + IOmV to + IOV (full scale). Bipolar ranges are from ±lOmV to±IOV. For bipolar input signal ranges from ±5V to' ±IOV, an external amplifier is used to divide the input signal by 2 and an offset is introduced to give a 0 to +5V input to the ADC. Use the connection diagram shown in Figure 5. For bipolar input signal ranges of±5V down to ±lOmV, the external amplifier is not used. Use the connection diagram shown in Figure 6. or Parameter tad Delay - Valfd Addr. 10 Addr. Decoder Oul IT Delay - MEMW 10 DELAY Oul tr Delay -. ~ 10 DELAY Oul tdelay Analog Settling Time IR Delay - DELAY 10 READY Oul tconverslon Total Channel Conversion Time Circuit Configuration Delay Adjusl Required 1 1.33 1 5 25 250 Figure 5 Figure 5 Figure 6 Figure 6 Figure 6 Figure 6 No No No No No Yes o 10+10V o 10+5V 1 2 500 Figure 7 Figure 7 Figure 7 No No Yes 010+20mV INSTRUMENTATION AMPLIFIER GAIN SELECTION TABLE I. MP32BG/CG Timing Diagram Parameters. Symbol IA Gain ±10V ±7.5V ±5V ±1.0V ±100mV ±20mV Input Range ANALOG INPUT Min 10 45 Max Unit 30 128 nsec nsec 98 nsec 1000 J,l.sec 52 nsec 55 ,usee 10 Q Delay - End of Conversion 10 ORO 25 nsec Delay - End of Conversion 10 INT 70 IDa Delay - ~ 10 ORO Oul 60 nsec nsec Qa Delay - DACK/INTA 10 INT Oul 75 nsec The internal instrumentation amplifier gain may be set to any value between I and 500 by connecting an external gain resistor between pins I and 3. With the pins open the gain is I ±O.02%. The gain of the amplifier is determined by: G = I + (25kO/ R oxt), where Raxt is the gain resistor value. The external resistor should be stable (lOppmj"C or beter) since its drift will add to the gain temperature coefficient. SINGLE-ENDED VERSUS DIFFERENTIAL INPUTS The MP32 analog inputs may be connected in singleended, differential, or pseudo-differential configurations. Single-ended operation may be used for high level (over I V full scale) signals in low noise environments (see Figure 8). Differential operation will reject commonmode noise that appears on both inputs (see Figure 9). It should be used in noisy environments or with any low level signal (less than I V). In the pseudo-differential mode, the MP32 is connected the same as single-ended 6-244 AD-All ~'=-:2!~,! ~~~~ ________________________________ ~~ ADDRESS DECODER OUT -..;:- tad , . MEMW ' MEMR DELAY tad _ i.- ~_ _ _ __ ~1": ____.Jf tT+ i--~I!-'----------~~ _________________ ...f-------tdelay--------i .. 1 tR-+! 14- tconverslon---------<~"lI:----------- _ _ _ _ _-'\\ ho- }________________-J/ READY DRO tDjl ' _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __+' I \ , - -_ __ r. J-~-' tl: INT tDa_ -----------------------------' ,.lla I ~ DACK/INTA FIGURE4. MP32 Timing Diagram. For clarity. only connections significant to the analog Input conflguretion are shown. Set gain of Internal amplifier to give ±IDV range at IA OUT. r---------------'fl:A~OU:,T~-=~=......:;;L.~=====:\ Analog Inpula MP32 >4-__-=67:i ADC IN ~--''--------I .-_----'.7"'1B OFFSET NULL 60 '---_--=65"'1 BIPDLAR OFFSET 58 55 54 57 NOTES: I. Resistor networlc - lotn pull down (Bourns 4116R-001-I04 or Allan Bradley 316B). 2. IN914 or equlvalanl 3. Cermet potanllometer and thln·fllm resistors with lOOppm/·C TCR or less. Bipolar Data } Bus OHaet (II Ad)ust FIGURE 5 Connection Diagram for Bipolar Input Ranges Between -+5V and -+IOV of +5VO f=!f!. f-l . . . Sel gain of Internal amplifier to give ±5V range et IA OUT. 51 G +15VOC ["1, -15VOC Ht=< f!,.': (21 ..., .... HI- _ 50 ~ 64 4.7 pF Tantalum 0.01 pF Ceramic 61 IAOUT Bipolar Offsel (31 37.4k!! Ad)usl 250!! f~ Bipolar ~: 50kn NOTES: Gain (31 I. Resistor network· 10k!! pull down Ad)uet (BaurnI4116R.(J01-I04 or Allen IMn Bradley 3168). 2. IN914 or equlvalenl 3. Cermet POIanIlometer and Ihin-lilm resistors with 100000pm/"C TCR or lesl. AOC IN 78 OFFSET NULL For clarity. only connections significant to the analog Input configuration are shown. } Analog Inputs MP32 }.. 60 65 BIPOLAR OFFSET Bus ~ REF TEST POINT ADC GAIN ADJUST ~ o(1J "i7 FIGURE 6. Connection Diagram for Bipolar Input Ranges of ±5V or Less. 6-245 -t5VDC +15VDC f8t! ~ 121 51 66 Unipolar 011111 Ad/ull For clarily. ani y c:onnectlllll8 IlgnllicaRiIo Ihe analll!l Inpul conllguralion are Ihown. 5D~ G 0.01 "F Cerlmlc 64 61 IAOUT ADC IN } Analog Inpuls MP32 65 81POLAR OFFSET 50kn:lp~~ OFFSET NULL 63 REF TEST POINT 4 AOC GAIN ADJUST NOTES: IMn I. Resillor nllwork . lOkI 1 pull down 1800rn14116R-001·104 or Allin Bredley 31681. 2. 1N914 or equlvalenl. 3. Cermll polanliomBlllr Indlhln·fIIm rasllm wltlll OOppm/OC TCR or 1811. 'r ·15VDC ~..: ~.: _4.7"F Tanlalum f-;ISII gain of Inlernal am plilierio give 0 10 10V rlnge II IAOUT. n.- 60 59 58 57 56 55 .~ Unipolar Gain 5 Ad/ull 131 Dais ) 8us l III ~7 FIGURE 7. Connection Diagram for Unipolar Input Ranges. mode except the IA low input (pin 79) is connected to a remote ground that is common to the analog inputs. 15b" Analll!l Inpuls e e en Analog Signal Groond I 614 III-Channal Single-Ended analll!l Muiliplaxar 2 7~ 4 ol31openl il D>- 165V (16.5kU x IOmA). Care should be taken to .insure safe power dissipation in these resistors. In this case, the power dissipated is 1.65 watts. Increased input resistance will, of course, increase the amount oftime,necessary for . the multiplexer to settle as described in the following section. r- - Source Rasillance sllllrca~- 64 MP328G/CG 1.5kn RS FIGU RE 8. Smgle-ended Input Connecttons. lopanl 15 Analog 14 Co =50pF for Iingle·ended mode Co = 12.5pF fur dillorenlill mode 13 +llnnIP~UIa~~~r:~;,;;=~~----~------~ : II-Channal Dlileraniial Analog Muiliplaxor +Supply l;> RON ·Supply . 1• f CO . +Suptlly ·Theae compOllenlB IIDI preseRiln lingle-ended connecllon. FIGURE 10. "ON" Channel CirCUit Model. SETTLING TIME AND DELAY TIME ADJUST 79 FIGURE 9. Differential Input Connections. INPUT OVERVOLTAGE PROTECTION As shown in Figure 10, the analog inputs have reverse biased diode circuits which protect them from damage by overvoltage (such as static). It is still reasonable to take precautions against static discharge. The same circuitry protects the inputs during operation against damage by steady-state differential or common-mode overvoltage. The MP32 overvoltage protection can be increased by adding series resistors at each input. The input resistance must limit the current flowing through the input protection diodes to IOmA. For instance, if l5kU resistors are added to each input, the protection is increased to A delay time between channel selection and start of conversion is built into the MP32 to allow the analog multiplexer and instrumentation amplifier time to settle before starting the AID converter. As the gain of the amplifier is increased, the settling time req uired increases (see Figure II). The factory-set delay time (l5j.1sec) is sufficient for gains of up to 50. At higher gains, a capacitor must be connected between pin 47 and pin 50 to increase the delay time. Figure 12 shows the value of capacitance required to increase the delay. The only external factor, other than gain, that affects the MP32 settling time is the impedance of the. source connected to a channel. Figure 10 shows circuit model of an "ON" channel. The signal at the output of the multiplexer must be allowed to settle to ±0.01% (9.2 time constants) to maintain the full accuracy of the system. The multiplexer a 6-246 inputs nor the outputs of the instrumentation amplifier are internally connected. For instance, Burr-Brown's model 3507J high speed op amp may be used, with a settling time of IJLsec for gains of up to 100. For a T'A of IJLsec we have T D = 1.3/Lsec. Using 3/Lsecfor the delay time to allow for unit-to-unit variation, the total throughput time will be 18JLsec (including the delay time from the factory-set value of 15JLsec (see Figure 13). 100 12 Ampllfllr Gain 10 FIGURE II. Differential Amplifier Settling Time vs Gain. / 120 100 1/ 20 , I I / 0.0033 0.DD67 0.0100 Capacitor Valul I~FI FIGURE 12. Typical Delay Time vs Capacitor Value. time constant can be calculated with the formula: T = (Rs + RON)Co • For Rs = IkO and Co = 50pF, T = (1.5 + l)kO x 50pF = 125nsec. The 1.5JLsec is needed to settle to ±o.OI%. For high input impedances requiring more than IOJLsec for multiplexer settling time, the required delay time may be calculated with this formula: T D = VT="zm-u-x""'+""'T=2.-,-A., where Tmux is the settling time of the multiplexer and T'A is the settling time of the instrumentation amplifier as shown in Figure II. If the source bandwidth can be limited, high impedance sources may be accurately handled by placing a large capacitance across the multiplexer input. An analysis of such a circuit shows that a capacitor of 0.5JLF is sufficient. For such a capacitance the multiplexer time constant becomes 80nsec. . Rulstor Valullk!~ FIGURE 13. Typical Resistor Value to Decrease Delay Time. DATA OUTPUT CODING Table III gives the relationship of various input voltage levels to corresponding output digital words. The coding for unipolar input ranges is called Unipolar Straight Binary; bipolar input ranges yield Bipolar Offset Binary codes. Another popular output code used with bipolar input is Two's Complement. It is identical to the Bipolar Offset Binary except the MSB is inverted. TABLE III. Voltage Input/ Digital Output Relationship. The MP32 internal instrumentation amplifier requires 15JLsec to lOOJLsec for settling time. If this internal amplifier is not used, improvements in throughput rate can be obtained. This is easily done since neither the Digital Output Analog Input Unipolar Straight Binary Bipolar Offset Binary +Full Scale -ILSB +Full Scale -1 LSB +1/2 Full Scale Zero +1/2 Full Scale -ILSB -ILSB -Full Scale Zero Bipolar Two's Complement -ILSB -Full Scale +Full Scale-1LSB Zero 1601 1591 1581 D3 1571 04. 1561 551 OS I I MSB LSB 111111111111 100000000000 011111111111 000000000000 DO 01 02 F or switching oflarge signals it must be remembered that the "ON" resistance is the channel resistance of a FET which is a nonlinear function of the applied voltage. As a result the previous calculations are only an approximation derived from a linearized model. Another factor not considered is the addressing delay of the multiplexer. This is typically 250nsec and is additive to the above calculated times. For differential units the same considerations apply. Even though two input circuits are involved there is sufficient component matching within the multiplexer to prevent measurable differences in the transfer functions for each half of the signals. Therefore, the time constant for only one circuit can be considered the time constant for the entire channel. - 33 6& 100 133 166 200 / /~ ~ MP32 1'= ~PBua -lill =c! FIGURE 14. Two's Complement CodingOutput Circuit. The two's complement output code may be obtained by software programming or by hardware, using a 4-bit 6-247 tri-state inverter as shown in Figure 14. The EN I (pin 80) signal is used to gate MSB on the microprocessor bus during the time when the second byte of data is enabled. Thus MSB replaces MSii· in this byte. The top four bits (D4-D7), normally not used in the second byte, are made equal to MSB to make two's complement addition easier. SETUP AND CALIBRATION RESET It is important to reset the MP32 on start-up with a low pulse on the RESET line (pin 39). The reset pulse clears internal control logic and guarantees that at start-up all control lines are in the proper state. GAIN AND OFFSET ADJUST CIRCUITS The components required to null gain and offset errors for unipolar and bipolar inputs are shown in Figure 5, 6, and 7. The offset is adjusted at the lowest input voltage transition point. (The input voltage at which the output code changes from 000000000000 to 00000000000 I.) The gain is adjusted at the highest input voltage transition point. Offset is adjusted first, then gain. CALIBRATION WHEN USED WITH INTEL MODEL 8080 Before calibration, the MP32 should be allowed to warm up for 15 minutes (power applied). Calibration is performed by connecting a precision voltage source (capable of 0.005% accuracy) to an input channel. (This could also be a DC voltage source of less absolute accuracy whose output is monitored by a 0.005% DVM.) The offset and gain adjustments on the MP32 are made while applying the voltages shown in Table IV. The following program is used to calibrate: Gain adjustments require that this process be repeated until the approximately equal count is reached. CALIBRATION WHEN USED WITH MOTOROLA MODEL 6800 The procedure is the same in concept as that described in the 8080 calibration procedure. Again the unit should be allowed to warm up (power applied) for 15 minutes. The MP32 is connected as shown in Figure 21. The 6800 calibration program is: START ORG $100 LDAA #$64 STAA COUNT CONY CLRA CLRB LOX #0000 STX $IF70 NOP LOX $IF70 CPX AA AD #sxxxx· 86 64 B7 01 21 4F SF CE 00 00 FF IF 70 01 FE IF 70 8C 00 00 BEQ AA 27 03 INCB BRA AB 5C 20 INCA DEC COliNT BNE CONY BRA START ctcanlccumulator~ Begin converS1On Read data Is Data \;0. = low Ref Incn:ment count 01 4C yc~. 7A Have comcr:-.ions reached IOD'! 01 21 26 FO 20 Increment count '\ o. Do another conversion Yes. Begin next run OF COli NT END AD: AC: AA: AD: ORG LXI LHLD MOV SUI JZ INR JMP INR MOV IOH DO I F70H A. L XXXX' AA C AD B A.B ADD CPI JNZ JMP END C 64H AC AD ;Clear Band C Reg. pair :Read data from :Is Data = Low Ref'! ::"1:0. Increment count ;Yes. Increment count :H.nc 100 cOn\cr\lom. been made AE: *XXXX i~ ;Yes. Begin proW-am again 0000 for offset. OFFF for gain. The program assumes that the MP32 is wired for channel IF70H. If the MP32 is wired for a different address, the address associated with the LHLD instruction AC must reflect this change. After assembling and loading the program, set a breakpoint at AE. The program is then started using a G I0 Command. After 100 conversions, the breakpoint,will be reached and control will return to the monitor. The Band C registers are then examined for an approximately equal count (within 1016 of each other). Both the Offset and o located at ·XXXX is 0000 for offscl. OFFF for gam. The program assumes that the MP32 is set for channel located at I F7016 and I F71 16. If the MP32 has been reprogrammed for some other address this value should be reflected in the program's STX instructions that refer to the MP32. After assembling and loading, insert a breakpoint at location II C via a "V" command. Calibration is performed by connecting a precision voltage source capable of 0.005% accuracy to CHO. (This could also be a DC voltage source of less absolute accuracy whose output is monitored by a 0.005% DVM.) The offset adjustment is made first by using the appropriate offset calibration voltage. The calibration program is then run and after 100 conversions will halt at the breakpoint. Control will return to the monitor which will then print the contents of all of the program registers at the time of the breakpoint. The contents of each accumulator should be compared for approximately equal values. If a difference of more than 1016 is present, slightly readjust the offset control and restart the program with a ;P command. Repeat this procedure until the accumulators' contents are within 1016 of each other. 6-248 TABLE IV. Calibration Input Voltages. Input Voltage Unipolar Bipolar General Equation Range(1) Full Scale Range LSB Value Vin for Offset Adjustment Vm for Gain Adjustment o to +10V o to +5V Oto+1V 10V 5V W 2.44mV 1.22mV 244"V +1.22mV +O.610mV +O.122mV 9.99634 4.99617 +O.99963V -10V to +10V -5Vto +5V -Wto +W 20V 10V 2V 4.88mV 2.44mV 488"V -9.99756 -4.9988 -O.99976V 9.99268 4.99634 +O.99927V V, toV2 V2-V, V2 - V,(2) V, + 1/2LSB V2 -3/2LSB -2-'- NOTES: 1. For other ranges, compute the proper input voltages using the general equation. 2. n = resolution 112 bits for MP32BG/CG 1. The gain adjustment is made in much the same manner. However, the data associated with the CPX instruction in the calibration program must be changed from 0000 16 to OFFFI6. CALIBRATION WHEN USED WITH OTHER MICROPROCESSORS The same technique used in calibrating the MP32 with the 8080 and 6800 can be used with any processor. Repetitive conversions are made around the "edge" of an output digital step or transition (the lowest for offset, the highest for gain), and then look for 50% of the conversions to be on each side of the edge. The program should be written to convert with the input at·the transition voltage a large number of times and record in two registers the number of conversions that fall on each side of the transition voltage. When the numbers are approximately equal (within 10 16 ), the converter is calibrated. This must be done for offset first, then gain. Refer to Table IV for the high and low transition voltages. Again, the unit should be allowed to warm up for 15 minutes with power applied prior to calibration. INTERFACE CONNECTION DIAGRAMS The MP32 is designed to easily interface with most micoprocessors. The following pages illustrate the use of the MP32 with several different CPU's. The basic software to operate the units is also shown except where previously discussed in the text. \ All • • · 8080 / AD V ORIN RESET C)-<~ RESET READY READY SYNC SYNC 2 2 - - 8224 1 1 J All ORIN H • "H" 07 07 " " " 00 DO 07 1 ' - - - - - - '~\ A STSTR MP32 . 07 \ /: ;0 \ \ , . - - - - - , / 00 " " / ~ 8228 Y lMEMii .MEMW iiEMiilO---.-J? MEMR STSTR RESIN RESET • • • AD MEMW r '( NOTE: For ciM'1ty. only \tIaIIslanll. ,"ul,. 10 connect lha MP32111I11a 808D s"lIm hm bill! shown. All othlr connlctions are made IS explainad alsa.hara in this manual or in tha 8080 IIlaratura. FIGURE 15. MP32 Used With 8080 in Halt Mode. 6-249 READy All ~---------------'~\ . All \ • • • • . -_ _ _ _ _ _ _ _ _ _ _ _ _--,1, AD• All 8080 OBIN VCc~ RESET V DBIN MP32 • NOTE: Far cllrlty. only lhole 81gnal8 required ID connect Ih, MP32 hllhe 8080 1,IIIm hIVe bean Ihowil. All othar connactlonllre mlde II explained allawhare In this mlnull Dr In tha 8080 literature. FIGURE 16. MP32 Used With 8080 in Interrupt Mode. AI5 AD Opllonll Hit Addr. A15 Wi iiii MEMW MEMR INT INT l-liO AD A15 RD Will MEMR MEMW Rudy OBI~ +&VDC MP32 l·aO Ikn 10RO M1 MP32 iiA57Im 00=0 N1lTE: F., .Iarlly. only Ih•••• lgn.l. dlre..ly lov.lved 10 Ihe 101....00...1.0 hay. bean shown. F., NDTE: ,1"lIy.•oly Ih..e .lgo.l. directly 1...lved 10 Ihe IntIr,ono,,".o h.ve bee~ .h.wo. Z·BO I. 101ll.Um I. 10lllrrupi MDDE 2 C......I.o I••I.rted by 1h... lolI,u..lon.: LDA. D LD IXXXXI. A The 1.1I ••log 'DUlio' IS u••d I.....Icolh. lolerrupl: INTR: PUSH HL :Sa.. HL 'agl'Ie' p.I, LD HL. IXXXXI :R.1d del. LD Iyyyn HL :SIo" dill 10 m....ry' PDP HL :RIII.,. HL 'agl.Ie, pal, p'.gram I. READ .od STDRE LD HL. NN LD DE. MM LD BC. 4DH LDI Jp PE. LDAD RElI 16 ....00.1. 01 dliluslog BI.,k Transler 10.lru..l.o. :NN p.lnlio .... 00.1 DMPS2 ;MM p.lol.1o Ih.Ursll ...U.o .11h. delllo,lIon :Byllloouniar 12 byIIII,h.oo.1 x 161 =32 1D :LoId and I.....manl ;HIS 1..1byte bee~ lra"'arred? XXXX Islh. lI.rtlog .dd .... oIlhe d.. I,.d ,h.oo.1. yyyy 1.lh. 'IIIrtlog .dd .... oIlhe 1.,111.0. io m.m.ry where dll.l••Iored. FIGURE 17. MP32 Used With Z-80 (interrupt Mode). FIGURE 18. MP32 Used With Z-80 (Halt Mode). 6-250 AI5 MEMi MEMW AD +5VOC NRDS ADDR DECODE BOB5 MEMR ..'" Do MP32 ~ NHOLD MP32 DBD AO,A7 +5VOC OBIN NOTE: For clarity, only those signals directly Involved In the Interconnection hIVe been lhown, Ready DO DB7 LD F7D XPAL LD XPAL DO F71 01 START Conversion CHO and Halt processor, READ 8LSB's AC EA AC (PTR7:01 Store 8LSB's in Pointer Reg. DO READ 4MSB's and RESET MP32 AC (PTR t5:BI Store 4MSB'I In Pointer Reg; 01 NOTE: For clarity, only thole Ilgnlll directly Involved In the Interconnection have been shown, MP32 connected In the Hilt Mode, Interrupt or OMA Mode can be usad with 8085, with or without using 8257 PDMAC or 8259 PIC, Will operlle only when Icy il laB than 630RBec (1.50MHz .clock Irequlftcyl, FIGURE 19, MP32 Used With 8085. FIGURE 20, MP32 Used With SCj MP (Halt Mode), Addrm Bus Vcc tOBIN AI2~----; Logic Input STH Datlnatlon Addresl NOP LOA Oeltlnatlon Address LOA Datlnatlon Address VMA 6800 MP32 Ready 1-----+1 iiiii Addr811 Decoder Outpul AO= I 00=0 Startl Converlion Halt AD = 0 8LSB's, Resets MP32 AO= I 4MSB'I 2 00 NOTE: For clarity, only those signals directly involved in the interconnection have bean shown. ...1'1.... 0 74LSt23 74LSI23 ~-+------------~O +5VD~L-J+. DV tDOnlec FIGURE 21. MP32 Used With 6800, 6-251 APPLICATION NOTE DATA ACQUISITION FROM THERMOCOUPLE INPUTS Thermocouples are often used as temperature sensors for porcess control systems. Thermocouples are characterized by temperature coefficients of lOJ.! V/"C to 70p. V/"C and operating ranges of minus hundreds to plus thousands of degrees centrigrade. When the MP32 is operated with an instrumentation amplifier gain of 100 or more, it may be connected directly to these devices. The wire runs from thermocouple to measuring device often pick up large common-mode noise signals of 60Hz or higher frequencies. When the MP32 is used as an 8-channel differential input system, the high common-mode rejection of the instrumentation amplifier will reject common-mode noise. To minimize differential mode noise, the signal wire should be twisted and if possible shielded. As a rule, an unshielded twisted pair is better than a coax, and a shielded, twisted pair is still better. In applications where these wiring practices can not always be observed, a differential RC filter may be used. Figure 22 shows such a system. remote sensor should be earth-grounded to prevent common~irtode voltages from exceeding the ±5V range of the mUltiplexer. If the sensor is earth-grounded, the I MO resistors are not required. The I MO resistors do, not enter into lin error calculation for input errors because the low resistance of the sensor shorts any differential voltage that might be caused by the offset (difference current) of the amplifier. Offset or difference curtent is merely the difference between the" bias currents of the two inputs. The I MO resistors could have been put on the output side of the multiplexer eliminating the need for repeating them for each input; however, this would have loaded the lOkO resistors of the filter causing a possible I% error for static conditions. To complete a thermocouple system it is necessary to terminate all thermocouple wire pairs at an isothermal box or connector strip of some type. An ordinary barrier strip may be monitored to allow the observed thermocouple emf to be cold-junction compensated. Figure 22 shows an excellent circuit for this purpose. Its output is connected to one of the input channels to supply am bient temperature data to the system computer. Its output sensitivity is approximately 2mV The lOkO resistors and lOJ.!F capacitor provide low-pass filtering (f, = O.8Hz) and the optional I MO resistors supply bias current to the, instrumentation amplifier. The rc. MP32 . Cable Run lsathermal Barrier Strip opiiOnii -"'--.._-" Bias Current Supply Resistors 2OkO 200ku lBO 1Hz LowPass Filter +5V BB3500B • ·12VOC Dual monolithic transistor pair (National LM114) mounted near Isothermal barrier strip. FIGURE 22. Thermocouple Input System Using MP32. 6-252 BURR-BROWN® MPC800 IElElI High Speed CMOS ANALOG MULTIPLEXER FEATURES DESCRIPTION • HIGH SPEED lDDnsac acc.s time BODnsac sattllng to 0.01 % 250nsac sattllng to 0.1 % The MPC800 is a high speed multiplexer that is user-programmable for l6-channel single-ended operation or 8-channel differential operation and for TTL or CMOS compatibility. The MPC800 features a self-contained binary address decoder. It also has an enable line which allows the user to inhibit the entire multiplexer thereby facilitating channel expansion by adding additional multiplexers. High quality processing is employed to produce CMOS FET analog channel switches which have low leakage current, low ON resistance, high OFF resistance, low feedthrough capacitance, and fast settling time. Two models are available, the MPC800KG for operation from O°C to +75°C and the MPC800SG for operation from -55°C to +125°C. • USER·PROGRAMMABLE 16·channel slngle-anded or B-channel differential • SELECTABLE TTL or CMOS COMPATIBILITY • WILL NOT SHORT SIGNAL SOURCES Break·befora·make switching • SELF·CONTAINED WITH INTERNAL CHANNEL ADDRESS DECODER • 28·PIN HERMETIC DUAL·IN·LlNE PACKAGE A DECIIIER Aa 0 ij ~-~INIA EN>+---~H-I Ao>-l----+-H Al >--'-----.+4-+-l Az >+---.+H-+-I DUTA i---+"- 125 >75 2.5 18 0.02 dB dB pF pF pF MIN MIN MAX A 1.360 1.475 34," 37.47 .500 .550 12.70 13.97 220 - - 5.59 .015 .02' 0.38 0.53 .030 .07"0 0.76 MAX c .100 BASIC G .030 .09' ,007 .013 .100 - - .600 BASIC ". M .020 090 1.78 2.54 BASIC' 0.76 O.lB 2.41 0.33 2.54 - - 15.24 BASIC ". 0.51 2.29 nsec nsec TOP VIEW +Vec OUTB NC , INI6/8B IN1S/7B IN14/6B IN13/5B IN12/4B INll/3B IN10/2B IN9/1B GND VREF A. 6-254 MILLIMETERS DIM PIN CONFIGURATION DYNAMIC CHARACTERISTICS ,Gain Error Cross Talk!71 TOPEN (Break before make delay I ~ r- L" _~c , DIGITAL INPUTS Over Tempe~ature Range TTU') Logic "0" (VAll Logic "1" (VAH) IAH IAL' TTL Input Overvoltage CMOS Logic "0" (VAll Logic "1" (VAHI CMOS Input Overvoltage Addr.... A3 Overvoltage Digital Input CapaCitance Channel Select!S) Single-Ended Differential Enable Pin numbers shown for refer.nce on IV. Numb.... ma.,. not be merked on package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 ' 23 22 21 20 19 18 17 16 15 OUTA -Vee IN 8/8A IN7/7A IN6/6A INS/5A IN4/4A IN3/3A IN2/2A IN1/IA ENABLE Ao A, A2 MOOEL MPC800KG,MPC800SG PAIIAMETEII MIN TYP MAX UNITS 0 -65 +75 +150 °C °C -55 -65 +125 +150 °C °C TEMPEIIATUIIE MPC800KG Specification Storage MPC800SG Specification Storage NOTES: 1. Reference voltage controls noise immunity, normally left 'open for TIL compatibility and connected to VDD for CMOS compatibility. 2. V,N = ±10V, lOUT = 100"A. 3. Single-ended mode. 4. Logic levels specified for VREF (pin 131 open. 5. For single-ended operation. connect output A (pin 28) to output B (pin 2) and use A3 (pin 14) as an address line. For differential operation connect A:J to -Vee. 6. Derate BmW/"C above TA = +75°C. 7. 10V, p-p, sine wave on all' unused channels. See Typical Performance Curves. 8. For 20V step input to ON channel, into 1 kO load. TYPICAL PERFORMANCE CURVES CROSS TALK VS SIGNAL FREOUENCY 'iii 1 c:: '" iii ~c:: 0.1 as q... ... 0.01 V o "0 0.001 .>< ~ 0.0001 e ~ lk "ON" CHANNEL ~ J I 10 r----;;-OFF"OUTPUT " " , ~ 11'" as I"'~ " O. 1 . - ~ .--' \l~ ...J / () 0.00001 100 - 100 () V ~ ~ v < 5 COMBINED CMR VS FREOUENCY FOR MODEL 3630 AND MPCBOO LEAKAGE CURRENTS VS TEMPERATURE 1000 10k lOOk 1M Signal Frequency (Hz) 500 10M 0.01 25 35 RON DRIFT VS TEMPERATURE '"(5z a a: 1000 - 400 § 55 45 65 Temperature (OC) 300 75 SETILING TIME VS SOURCE RESISTANCE 110V STEP CHANGE. RL - lkO - 800 - 200 \1"0 0.01'101 - ~ \~O 100 200 o 25 35 65 45 55 Temperature (OC) 75 6-255 o / - /' 10 0.01 0.1 Source Resistance (kH) 100 ON resistance and source resistance. A load bias current of IOnA, a leakage current of I nA. and an ON resistance of7000 will generate an offset voltage of 19p. V if Ii 10000 source is used, and 118p.V if a 10kO source is used. In general. for the M PC800 the Offset voltage at the output is determined by: DISCUSSION OF PERFORMANCE STATIC TRANSFER ACCURACY The static or DC transfer accuracy of transmitting the multiplexer input voltage to the OUtput depends on the channel ON resistance (RoN). the load impedance. the source impedance. the load bias· current. and the multiplexer leakage current. VOFFSET = (18 + iL)( RON + R.oorc'l where 18 = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance R,o""" = Source resistance Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for single-ended multiplexers are: Source resistance loading error Multiplexer ON resistance error DC offset error caused by both load bias current and multiplexer leakage current. RESISTIVE LOADING ERRORS The source and load impedances will determine the ON resistance loading errors. To minimize these errors: • Keel1 loading iml1edance as high as 110ssible. This minimizes the resistive loading effects of the sourpe resistance and multiplexer ON resistance. As a guideline. load impedances of 108 0 or greater will keep resistive loading errors to 0.002% or less for 10000 source impedances. A 106 0 load impedance will increase source loading error to 0.2% or more. • Use. sources with imP.5:dances as low as 110ssible. A 10000 source resistance will present less than 0.002% loading error and IOkO source resistance will increase source loading error 0.02% with a 10 8 0 load impedance. I nput resistive loading errors are determined by the following relationship (see Figure I): Differential Multiplexer Stalic Accuracy Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low level signals with full scale ranges of 10mY to IOOmY. The matching properties of the multiplexer. source and output load playa very important part in determining the transfer·accuracy of the multiplexer. The source impedance unbalance, common-mode impedance. load bias current mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch. leakage current mismatch and ON resistance also contribute to differential errors. Referring to Figure 2. the effects of these errors can be minimized by following the general guidelines described in this section, especially for low level mUltiplexing applications. I BIASA RSIA RONIA r""J""'~"""""1-",;;;;;;;;"o----.....,-- ~) IL _________ ...JI Rs + RON x 1009'1 (Rs+ RON) - Rs+ RON + RL 0 where Rs = R,o""" RL = Load Resistance RON = Multiplexer ON resistance RSI RON ILl ROFF8B FIG URE 2. M PC800 Static Accuracy Equivalent Circuit (Differential Operation). I BIAS -, Vm I I IMEASURED RSI6 ROFF VCCI6 I I I CCM I I I Source and Multiplexer Resistive Loading Error E - - ZLDADI '::' FIGURE I. MPC800 Static Accuracy Equivalent Circuit (Single-ended Operation). Input Offset Voltage Bias and leakage currents generate an input Offset voltage as a result of the IR drop across the multiplexer Load (Output Device) Characteristics • Use devices with very low bias current. Generally, FET input amplifiers should be used for low level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mY FSR. Bias current matching will determine the input offset. • The system DC common-mode rejection (CMR) can never be better than the combined CM R of· the mUltiplexer and driven load. System CM R will be less than the device which has the lower CMR figure. • Load impedances, differential and common-mode, should be 10 1°0 or higher. 6-256 Source Characteristics • The source impedance unbalance will produce offset, common-mode and channel-to-channel gain scatter errors. Use sources which do not have large impedance unbalances if at all possible. • Keell source imlledances as low as possible to minimize resistive loading errors. --• Minimize ground 1001lS. If signal lines are shielded, ground all shields to a--;;ommon point at the system analog common. If the MPC800 is used for multiplexing high level signals of I V to IOV full scale ranges, the foregoing precautions should still be ta/<:en, but the parameters are not as critical as for low level signal applications SETTLING TIME Settling time is the time required for the multiplexer to reach and maintain an output within a specified error band of its final value in response to a step input. The settling time of the MPC800 is primarily due to the channel capacitance and a combination of resistances which include the source and load resistances. 'If the parallel combination of the source and load resistance times th'e total channel capacitance is kept small, then the settling time is primarily affected by internal RC's. For the MPC800 the internal capacitance approximately 20pF differential or 40pF single-ended. With external capacitance neglected, the time constant of source resistance in parallel with load resistance and the internal capacitance should be kept less than 40nsec. This means the source resistance should be kept to less than 2kO (assume high load resistance) to maintain fast settling times. IS SWITCHING TIME This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a IOV signal change between channels. CROSSTALK Crosstalk is the amount of signal feedthrough from the 7 differential or 15 single-ended OFF channels appearing at the· multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel, 0 FF resistance, and junction capacitances in series with the RON and R,o""" impedances of the ON channel. Crosstalk is measured with a 20V, pk-pk, 1000Hz sine wave applied to all OFF channels. The crosstalk for these mUltiplexers is shown in the Typical Performance Curves. COMMON-MODE REJECTION (DIFFERENTIAL MODE ONLY) FIGURE 3. Settling Time Effects (Single-ended). The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CM R is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. Protection is provided for common-mode signals of ±2V above the power supply voltages with no damage to the analog switches. The CMR of the M PC800 and Burr-Brown's model 3630 Instrumentation Amplifier is 120dB at DC to 10Hz with a 6dBI octave roliofft080dBat 1000Hz. This measurement of CM R is shown in the Typical Performance Curves and is made with a Burr-Brown model 3630 instrumentation amplifier connected for a gain of 1000 and with source unbalance of 10kO. IkO and no unbalance. Factors which will degrade multiplexer and system DC CMR are: • Amplifier bias current and differential impedance mismatch. FIGURE, 4. Settling and Common-Mode Effects ( Differential). 6-257 • Load impedance mismatch. • M ultjplexer impedance and leakage current mismatch. • Load and' source common~mode impedance. AC CMR rolloff is determined by the amount of common-mode capacitances (absolute and mismatch) ftom each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines imd multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible. remaining three address lines (Ao. AI and A2)Jo address the correct channel. The differential inputs are the pairs of AI and BI, A, and B2, etc. TRUTH TABLES M PCSOO used as 16-channel single-ended multiplexer or 8-channel dual multiplexer. USE to,. AI DIGITAL ADDREISINPUT INSTALLATION & OPERATING INSTRUCTIONS The ENABLE input, pin IS, is included for expansion of the number of channels on a single-node as illustrated in Figure 5. With the EN ABLE line at a logic I, the channel is selected by the Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the EN ABLE line is not to be used, simply tie it to logic I. For the best settling time. the input wiring and interconnections between multiplexer output and driven devices should 'he kept as short as possible. When driving the digital inputs from TIL, open collector output with pullup resistors are recommended. To preserve common-mode rejection of the M PCSOO use twisted-shiel!fed pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as close as possible to system analog common or to the common-mode guard driver. OUT A OUTB X X X NONE NONE L L 1A L L H 2A NONE NONE L L H L 3A NONE L L H H 4A NONE H L H L L 5A NONE H L H L H SA NONE H L H H L. 7A H L H H H SA NONE NONE H H L L L NONE 18 H H L L H NONE 28 L X H L L H L H H '. H H L H L N9NE 38 H H L H H H H H L L NON" NONE 5B 48 H H H L H NONE 68 H H H H L NONE 78 H H H H H NONE 88 Mpesoo used as S-channel differential mUltiplexer. Aa CONNECT TO -VCC The logic level is user-programmable as either TILcompatible by leaving the VREF (pin 13) open or CMOScompatible by connecting the VREF to VOl) (CMOS supply voltage). a-CHANNEL DIFFERENTIAL OPERATION To use the MPC800 as an 8-channel differential multiplexer, connect address line A3 to -Vee then use the Az At to, For l6-channel single-ended function, tie "out A" to "out B. for dual8-channell.unction use the A3 address pin to select between MUX A and MUX 8. where MUX A is selected with A3 low. LOGIC LEVELS 16-CHANNEL SINGLE-ENDED OPERATION To use the MPCSOO as a 16-channel single-endeiJ multiplexer, output A (pin 28) is connected to output B (pin 2) to form a single output, then all four address lines (Ao, AI, A2 and A3) are used to address the correct channel. The M PC800 can also be used as a dual8-channel singleended multiplexer by not connecting output A and B, but then only one channel in one of the multiplexers can be' addressed at a time. "ON" CHANNEL TO A, ENABLE ''ON'' CHANNEL TO ENABLE Az A, At OUT A OUTB L X X X NONE NONE H L L L 1A 18 H L L H 2A 2B H L H L 3A 3B H L H H 4A 4B H H L L 5A 5B H H L H 6A 68 H H H L 7A 78 .H H H H 8A 8B CHANNEL EXPANSION Single-tier Expansion Up to four M pesoo's can be connected to a single node to form a 64-channel single-ended multiplexer or up to eight M pesoo's can be connected to two nodes to form a 64-channel differential multiplexer. Programming is' accomplished with a six-bit address and a I of 4 decoder for 64-channel single-ended expansion (see Figure 5) or an eight-bit address and a I of S decoder for 64-channel 6-258 differential expansion. The decoder drives the enable inputs of the M PC800, turning on only one multiplexer at a time. Two-tier Expansion Up to seventeen M PC800's can be connected in a two-tier structure to form a 256-channel single-ended multiplexer (see Figure 6) or up to nine M PC800's can be connected in a two-tier structure to form a 64-channel differential mUltiplexer. Programming is accomplished with a 8-bit address. Single vs Multltlered Channel Expansion In addition to reducing programming complexity, twotier configuration offers the ad.ded advantages over single-node expansion of reduced OFF channel current leakage (reduced Offset), better . CMR, ·and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the singlenode configuration, data cannot be taken from any channel, whereas only one-channel group is failed (8 or 16) in the multitiered configuration. II II-BIT CHANNEL II ADDRESS GENERATOR III r INI AD Al A2 A3 IN2 IN3 MPC80D I I ENABLE I OUlA IN16 DUTB r-l ~ DECODER o! MULTIPLEXER OUTPUT I<> t-...-t+-t-t----:---/ INI AD Al A2 A3 IN2 IIN3 I MPC800 I ENABLE I IIN16 III INI AD Al A2 A3 IN2 IN3 MPC80D I I ENABLE I OUTA DUTB J IN16 ~ o!- .... , TO MUL TIPLtxERS 3 AND 4 64-CHANNEL SINGLE·TIER EXPANSION [Slngla·Endad) FIGURE 5.32- to 64-Channel, Single-tier Expansion. TO MULTIPLEXERS 3 THROUGH 16 25I1-CHANNEL TWO-TIER EXPANSION [Slngla-l:ndad/ FIGURE 6. Channel Expansion up to 256 Channels using 16 x 16 Two-tiered Expansion_ 6-259 BURR-BROWN® IEWElI .. MPC801 High Speed CMOS ANALOG MULTIPLEXER FEATURES DESCRIPTION • HIGH SPEED BOnsee access time BOOnsee seHllng to 0.01% 250nsee seHllng to 0.1% The MPC801 is a high speed multiplexer that is user-programmable for 8~channel single-ended operation or 4-channel differential operation and for TTL or CMOS compatibility. The M PC80 I features a self-contained binary address decoder. It also has an enable line which allows the user to inhibit the entire multiplexer thereby facilitating channel expansion by adding additional multiplexers. . High quality processing is employed to produce CMOS FET analog channel switches which have low leakage current, low ON resistance, high OFF resistance. low feedthrough capacitance. and fast settling time. Two models are available. the MPC80lKG for operation from Onc to +7S"C and the MPC80lSG for operation from -SS"C to + l2Snc. • USER-PROGRAMMABLE 8-channel slngla-ended or 4-channel differential • SELECTABLE TTL or CMOS COMPATIBILITY • WILL NOT SHORT SIGNAL SOURCES Break-before-make switching • SELF-CONTAINED WITH INTERNAL CHANNEL ADDRESS DECODER • 18-PIN HERMETIC DUAL-IN-LiNE PACKAGE Af 0 0 ~-~INIA EN >+------<0+-1 OUlA Au >4-----1o+-H Al > - ' - - - -.......~ ;--+..l..< IN 4A AZ ~-+- 125 DC >75 60Hz OFF Channel Input Capacitance, Cs (offl 1.9 OFF Channel Output Capacitance, Co ,off) 10 OFF I nput to Output Capacitance, CDS' off 0.02 -- % nsec nsec nsec nsec nsec dB dB pF pF pF b IN2/2A b b IN1/1A ENABLE b b Ao A1 ELECTRICAL (CO NT) MPC801KG, MPC801SG MODEL PARAMETER MIN TYP NOTES: MAX UNITS TEMPERATURE MPC801KG Specification Storage MPC80ISG Specification Storage 0 -65 +75 +t50 ·C ·C -55 -65 +125 +150 °C ·C 1. Reference voltage controls'noise immunity. normally left open for TTL comp~tibil,ity and connected to Voo for CMOS compatibility. V,N ~ ±IOV. lOUT ~ 100~A. Single-ended mode. Logic levels specified for VREF (pin 8) open. For single..:ended operation. ·connect output A (pin 18) to output B pin 2, and use A2 (pin 9) as an address line. For differential operation connect A2 to -Vee. 6. Derate 6mWfOC above TA ~ +75°C. r 7. lOV, p-p. sine wave on all unused channels. See Typical Performance Curves. B. For20V step input to ON channel. into Ikllioad. 2. 3. 4. 5. TYPICAL PERFORMANCE CURVES CROSS TALK VS SIGNAL FREQUENCY LEAKAGE CURRENTS VS TEMPERATURE 1000 COMBINED CMR VS FREQUENCY FOR MODEL 3630 AND MPCBOI +v b-v d--_-_-_-_-_-_-_-_-_-_--I___ J FUNCTIONAL BLOCK DIAGRAM - MPC4D ' Enable Decoder Ao I FUNCTIONAL BLOCK DIAGRAM - MPC8S EN Pair A2 None X L L L L X X L L L H I L H H 2 H L H 3 H H H 4 TRUTH TABLE -MPC4D - 1 16 EN - 2 IS -Vsup - 3 14 INIA 4 13 - AO EN On Switch X X L H L H L H L H L H H H H None I 2 3 4 H L L H H L H H H H H L H 5 H H H 6 7 8 Al AO - I 16 -AI GND EN - 2 IS - A2 t-- +Vsup -Vsup - GND I-- INIB INI t-t-- - IN2A - 5 12 - IN2B IN2 IN3A - 6 11 - IN3B IN3 IN4A - 7 10 - IN4B IN4 - OUTA- S 9 - OUTB· OUT -"' MPC4D PIN DIAGRAM Al TRUTH TABLE - MPC8S AO MPC8S PIN DIAGRAM 6-268 b GND b >V _ _ _ _ _ _ _ _ _ _ _ _ .J 6'~~~~~~~~~P-v "On" Switch Al I 3 14 - 4 13 :-- +Vsup 5 12 :-- INS 6 11 :-- IN6 7 10 S 9 r-- IN7 f-- INS SPECIFICATIONS R..._" 1000 n. T. = unless noted Typical for fonowi", conditio...' V+ = +ISV V- = -ISV 2S'C otherwise ELECTRICAL .MPC4D AND MPC8S MODELS INPUT ANALOG INPUT Volta.. R.... I MPCBS Maximum OvervoltaF Current at Maximum Overvoltage V V V ±IB mA per channe~I' 4 Differential kn kn 0.2S %/,C vs. SO Channcl·to-channel Differential SO I NfA Input Leaka.. (IL) Input Leaka.. Drift n n SO 0.1 nA See Figure 9 OFF Characteristics OFF Resistance Output Leah.. (All channels disabled) Input Leakqc''' Leaka.. Drift " "14 1011 n 0.2 0.02 nA nA I I +4V :Il!it VH Enable 'Il1O;; 3 bit binary I 12 11 f 10 8 ) 2 3 4 5 6 7 L.J L.J U U U L.J f'"~' "'~;:;~m I ··O.55mm ~.d r-~,+ (0.100") (O.OIS") NON~CUMULATIVE 1.02mm (0.04") ~7'62mm~ (0.300") 6.350mm 1--10.250") .J min . . . +I~.~;~~ +.002 -.002 V V I nA 2 bit binary I (0.02") (0.700") ~A + V supply at 13 n 1 nA .-V supply" V, < O.B at I nA LOlic ..... (VH)IIN~I n 9 See Figure 9 Channel Select n 16 I Output Leakage with Input Overvolta.. of+3SV of -JSV DIGITAL INPUTS Logic "'0" (Vd 'lll' TOP VIEW r1 S.08mm I.S I.B Maximum Temperature (O'C to +7S'C) RoN Mismatch 16 Pin Ceramic Lead Frame .J B ON Characteristics ON Resis.ance (RoN) Typical RON Drift Units ±JS +V supply +20 -V supply -20 Number of Input Channels SinaJe-ended MPC4D !9.52mm (0.375")max I- 7.62mm .j (0.300") min ,code· onc of code - one of eight four logic "0" (low) disables all channels. Logic "I" (hiah) enables channel select to turn on selected channel. POWER REQUIREMENTS ±IS V +S to +20 -S to -20 V V +4. -2 ±o.S mA mA 7.S mW Rated Power Supply Volt.s Supply Ran.. +Supply -Supply Supply Drain At I MHz Switching Speed AT 100 kHz Switching Speed Typical Power Consumption DC to 10 kHz DYNAMIC CHARACTERISTICS 0.01 O.OOS Gain Error (20 Mfl load) maximum Crosstalk!)1 % %ofOFF channel signal Settling Time'·' To ±2mV ±(0.01%) To ±2OmV ±(O.IO%) Common-mode Rejection (minimum) Switching Time S 2 N/A I Turn ON Turn OFF ~s 0.3 To 0.01% To 0.10% OUTPUT Volt... RanF Capacitance to Ground dB O.S Recovery Time from Input Ovcrvoltagc Pulse of ~SV for 100 ,.sec ~Pacitance Mismatch ~s ~s 120 ~s ISO IS ±IS 2S I NfA ~s ~s V pF % 11~1 +10 TEMPERATURE Specification Storage o to +7S to +ISO -6S 'C "C 6-269 NOTES: I. Total power dissipation due to input overvoltage current flowing in the input protection circuitry m\.lst be limited to 0.75 watt for both (a) normal operation with power supplies turned on or (b) during a fault condition when the supplies are shorted to ground. 2. Maximum overvoltage is ±Vsupply ±4 volts at ±15 mAo 3. 20 volt peak-to-peak 1000 Hz sinewave; RSOURCE = 10000, same signal on all unused channels. 4. For 20 volts between switched channels, RsoURcE = 10000. See Figure 5 for settling ti~e vs. source impedance (Rs). 5. From each side of MPC4D to ground. 6. Leakage measurement made with all OFF channel inputs fed in parallel to +20 volts. DISCUSSION OF PERFORMANCE Static Tran$fer ,Accuracy The static or DC transfer accuracy of transmitting multiplexer input voltage to the output depends'on channel ON resistance (RoN), the load impedance, source impedance, the load bias current and multiplexer leakage current. the the the the SINGLE·ENDED MULTIPLEXER STATIC ACCURACY The major contributors to static transfer accuracy for single-ended mUltiplexers are: Soutce resistance loading error Multiplexer ON resistance error DC offset error caused by both load bias current and multiplexer leakage current. Resistive Loading Errors The source and load impedances will determine the input resistive loading errors. To minimize these errors: • Keep loading impedance as high as possible. This mininuzell the resistIVe loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedances of 108 ohms or greater will' keep resistive loading errors to 0.002% or less for 1000 ohm source impedances. A 106 ohm load impedance will increase source loading error to 0.2% or more. • Use sources with impedances as low as possible. A 1000 ohm source resistance will present less than 0.001% loading error and 10,000 ohm source resistance will increase source loading error to 0.0 I % with a 108 ohm load impedance. Input resistive loading errors are determined by the following relationship: (see Figure I) Sour~e and Multiplexer Resistive Loading Error RS + RON E(R + R )= x 100% S ON RS + RON + RL where RS = source resistance RL load resistance RON = multiplexer ON resistance = INPUT OFFSET VOLTAGE Bias current generates an input OFFSET voltage as result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10 nanoamperes will generate an offset voltage of 20" V if a 1000 ohm source is .used, and 200"V if a 10,000 ohm source is used. In general, for the MPC8S, the OFFSET voltage at the output is determined by: VOFFSET = (Ib + I L ) (RON + Rsl impedance unbalance, common-mode' imped~nce, load bias current mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON, resistance also contribute to differential errors. The effects of these errors can be minimized by following the general guidelines described in this section, especially for low level mUltiplexing applications. Refer to Figure 2. LOAD (OUTPUT DEVICE) CHARACTERISTICS • Use devices with very low bias current. Generaly, FET input amplifiers should be used for low level signals less than 50mV RSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine the input offset. • The system DC common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. • Load impedances, differential and common-mode, should be 1010 ohms or higher. SOURCE CHARACTERISTICS • The source impedance' unbalance will produce offset, common-mode and channel-to-channel gain-scatter errors. Use sources which do not have large impedance unbalances if at all possible. • Keep source impedances as low as possible to minimize resistive loading errors. • Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system " analog common. If the MPC4D is used for multiplexing high-Ieve\signals of ±I volt to ±10 volts full scale ranges, the foregoing precautions should still be taken, but the parameters are not as critical as for low-level signal applications. ~Ibias Ron' IL Raff r- -, I I ~I~d Vm I measured (voltage I -.J FIGURE I: MPC8S Static Accuracy Equivalent Circuit. where Ib = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance Z load RSOURCE = Source resistance DIFFERENTIAL MULTIPLEXER STATIC ACCURACY Static accuracy errors in a differential mul~plexer are difficult to control, especially when it is used for multiplexing low-level signals with full scale ranges of 10 to 100 millivolts. The matching properties of the multiplexer, source and output load playa very important part in determining the transfer accuracy of the m,ultiplexer. The source ccm L.. I _ _, _ _ _ FIGURE 2: MPC4D Static Accuracy Equivalent Circuit. 6-270 I SETTLING TIME MPC8S CHANNEL The gate-to-source and gate-to-drain capacitance of the CMOS FET switches, the RC time constants of the source and the load determine the settling time of the mUltiplexer. Governed by the charge transfer relation i = C ~~, the charge currents transferred to both load and source by the analog switches are determined by the amplitude and rise time of the signal driving the CMOS FET switches and the gate-to-drain and gate-to-source junction capacitances as shown in Figure 3 and 4. Using this relationship, one can see that the amplitude of the switching transients seen at the source and load decrease proportionally as the capacitance of the load and source increase. The tradeoff for reduced switching transient amplitude is increased settling time. If effect, the amplitude of the transients seen at the source and load are: FIGURE 3: Settling Time Effects - MPC8S "* "!Y,< node A i dV load =~ dt _>--1 load ....... dV where i = edt of the CMOS FET switches node B C = load or source capacitance The source must then redistribute this charge, and the effect of source resistance on settling time is shown in Figure 5. This graph shows the settling time for a 20 volt step change on the input. The settling time for smaller step changes on the input will be less than that shown in Figure 5. SWITCHING TIME This is the time requiredJor the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the SO percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10 volt signal change between channels. CROSSTALK Crosstalk is the amount of signal feed through from the three (MPC4D) or seven (MPC8S) OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel OFF resistance and junction capacitances in series with the RON and,RsouRcE impedances of the ON channel. Crosstalk is measured with a 20 volt pk-pk 1000 Hertz sine wave applied to all OFF channels. The crosstalk for these multiplexers is shown in Figure 6. COMMON-MODE REJECTION (MPC4D ONLY) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer' and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. Forthe MPC4D, protection is provided for common-mode signals of ±20 volts above the power supply voltages with no damage to the analog switches. FIGURE 4: Settling & Common-Mode Effects - MPC4D. The CMR of the MPC4D and Burr-Brown's model 3660 Instrumentation Amplifier is 120 dB at DC to I Hz with a 6 dB/octave rolloff to 70 dB at 1000 Hz. This measurement of CMR is shown in Figure 8 and is made with a Burr-Brown model 3660 Instrumentation Amplifier connected for a gain of 1000 and with source unbalance of I k!1 and no unbalance. Factors which will degrade multiplexer and system DC CMR are: • Amplifier bias current and differential impedance mismatch • Load impedance mismatch • Multiplexer impedance and leakage current mismatch • Load and source common-mode impedance AC CMR rolloff is determined by the amount of common-mode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and 'multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible. TYPICAL PERFORMANCE CURVES 1000r-----~----~----~----, 100~----+_----+_----+__.~~ .. . o. l i -__-:JL,-__-!____~,..._--".,! 0.01 §, Cii c ~ 0.1 FIGURE 5. Settling time vs source resistance for 20 volt step change. .c' U ""- 0 140r-----~----~----~----, 0.1 Source Resistance (Rs) (kn) 120 iC 2 a: :;; 100 0.01 U '0 ~ BO " ~o (j O.OOOl ......K-__~(dII:..--....____...L..____...I 1 10k 140r-----r---~r---~----_, Frequency (Hz) Signal Frequency (Hz) FIGURE 7. CMR vs frequency for Model 3660 IA and MPC40 (G = 1000). FIGURE 6. Crosstalk vs Signal frequency. iC .!! 1 oot---+~~-+-""'::I11111.-----1 a: :;; U BO~----r---~r-~~-----i 0.9 Frequency (Hz) , O.B FIGURE 8. Combined CMR vs frequency for Model 3670 IA (G = 1000) and MPC40. '0 O. 7 !E i= ~ 8 ~ 0.6 O. 5'1', 0.4 0.3 0.2 1.5 Temperature (oC) FIGURE 9. Leakage current vs tern perature. 3 ~ '0 1.4 > "'+1 ~ ~ -g ~ ~ ~.~ ~ §~ S z~~ : ; 't ! 1.3 1.2 1. 1 1.0 "- , '\. ooc :s:;;; T A ~ 75°c I' 0.9 O.B ±5 5 10 V H (High) Logic Level (Volts) f10 ±15 Supply Voltage (Volts) FIG URE 11. Normalized "ON" resistance vs supply voltage. 6-272 FIGURE 10. Accesstimevs logic level (high). 15 OPERATION & INSTALLATION INSTRUCTIONS The ENABLE input, pin 2, is included for expansion of the number of channels on a single node as illustrated in Figure 12. With ENABLE line at a logic I, the channel is selected by the 2 bit (MPC4D) or3 bit(MPC8S) Channel Select Address (see the Truth Tables on' page 5-136) If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to +V supply. If the +15 volt and/ or -15 volt supply voltage is absent or shorted to ground, the MPC4D and MPC8S multiplexers will not be damaged; however, some signal feedthrough to the output will occur. Total package power dissipation must not be exceeded (see Footnote I, page 5-137). For best settling speed, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pull-up resistors are recommended. See Figure 10 (access time). To preserve common-mode rejection of the MPC4D, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as closely as possible to system analog common or to the common-mode guard driver. Single vs. Multi-Tiered Channel Expansion In addition to reducing programming complexity, twotier configuration offers the added advantages over single node expansion of reduced OFF channel current leakage (reduced OFFSET), better CMR, and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the single node configuration, data cannot be taken from any channel, where as only one channel group is failed (4 or 8) in the multi-tiered configuration. ' 0. C "5{ o '" ~ ,a: Out 8r--------------, I : Multiplexel" Output Group 1 I N8 A 2 A, AO 21-=-..,...,----, Enable Direct 5 Bit 2 0- ' Binary 2' Icounter TG O roup 22 1 2 23 124 L I r---, III .... I I I I... I L:~ I \,00" I >. . -0 Buffered _~ Group 4 Enable MPC8S Group 4 Ch2532 8 Out Settling time to !:O.Ol% for Rs ~ lOOn CHANNEL EXPANSION Two MPC8S units in parallel: 1 O~s Four MPC4D units in parallel: 12~s SING LE·ENoEo MULTIPLEXER (MPC8S) Up to 32 channels (4 multiplexers) can be connected to a single node, or up to 64 channels using 9 MPC8S multiplexers on a two-tiered structure as shown in Figure 12 and 13. FIGURE 12.32 Channel, Single·Tier Expansion. '"2,,?" I~ DIFFERENTIAL MULTIPLEXER (MPC4o) Single or multi-tiered configurations can be used to expand multiplexer channel capacity up to 32 channels using a 32 x I or 16 channels using a 4 x 4 configuration. ~o- INI IN2 IN3 En 2~ INS AOA1A2 ".,c 111 4: SINGLE NODE EXPANSION The 32 x I configuration is simply eight MPC4D units tied to a single node. Programming is accomplished with a 5 bit counter, using the 2 LSB's of the counter to control Channel Address inputs Ao and AI and the 3 MSB's of the counter to drive a I of 8 decoder. The I of 8 decoder then is used to drive the ENABLE inputs (pin 2) of the MPC4D multiplexers. s~ MPC8S ~ f ~b~. c I S Direct S MPCBS I f i N S AOA1A2 INI IN2 IN3 .,4: 1 Out Inputs 0 TWO TIER EXPANSION Using a 4 x 4 2-tier structure for expansion to 16 channels, the programming is simplified A 4-bit counter output does not require a I of 8 decoder. The 2 LSB's of the counter drive the Ao and AI inputs of the four first tier multiplexers and the 2 MSB's of the counter are applied to the Ao and AI inputs of the second tier mUltiplexer. Outputs INI I o~h:r ~PC8S Ch To Multiplexer 'T 1"--' ,I " En L ., 2~ ...... I )LO ' .... s:ffered BB 3550 3505 or 3401 OU MPC8S En INS AOA1A2 II 2 ~ Settling Time to :to.01 % is 20 Ils with Rs .. lOOn -" ~ 3LSS's 3MSB' 6 Bit Channel Address Gen. FIGURE 13, Channel Expansion Up to 64 Channels U~ing 8X8 Two-Tiered Expansion, 6-273 BlJRR-BROWN@ MPC8D MPC1·6S IElElI CMOS ANALOG MULTIPLEXERS FEATURES • LOW POWER CONSUMPTION CMOS;analog switches 15mWat 100kHz . 7.5mW standby power • COMPACT DESIGN . Self-contained with internal channel iddress decoder 8-channel dual IMPC8D) for differential inputs or 16-channeIIMPCI6S) for single-ended.inputs 28-pin 0.600 Inch-wide space-saving package , :.~ • WILL NOT SHORT SIGNAL SOURCES Break-before-make switching • FAST SWITCHING SPEEDS PROVIDE HIGH THROUGHPUT RATES 711Sec settling to 0.01 % 311sec settling to 0.1 % • WIDE SUPPLY RANGE ±7VDC to ±20VDC Inllrnallanal Airport Industrial Park· P.D.Boi 11400· TUClon. Arizona 85734· Tel. (602) 746·1111 . Twx: 91(1.952·1111· Cable: BBRCDRp· Telex: 6s.6491 PDS-31S 6-274 High quality processing is employed to produce CMOS FET analog channel switches which have low leakage current, high OFF resistance, low feedthrougi1 capacitance and fast settling time. DESCRIPTION The MPC 16S is single-ended monolithic 16 channel analog multiplexer and the MPC8D is ,a monolithic dual 8 channel analog multiplexer constructed with failure protected CMOS devices. Transfer accuracies of better than 0.01% can be achieved at sampling rates up to 200 kHz from signal sources of up to ± 10 volts amplitude. These devices are housed in compact 28 pin dual-in-line packages, and are specified for operation over a OOC to +75 0 C temperature range. They are pin and package compatible with the.506/507 series. These DTL/TTL/CMOS compatible devices feature selfcontained binary channel address decoding. An ENABLE line is also made available which allows the user to individually enable a 16 channel group (MPC 16S) or an 8 channel group (MPC8D) facilitating channel expansion in either single-node or multi-tiered matrix configurations. 2S0UT 27 -V. SUPPLY 26IN'S 25 IN 7 24 IN 6 23 IN 5 221N 4 21 IN 3 20 IN 2 19IN 1 IS ENABLE 17 ADDRESS Ao 16 ADDRESS Al IS ApDRESS A2 +V SUPPLY I NC 2 NC 3 INI64 INISS INI46 INI37 INI2 S INI19 INIO 10 IN 911 GNDI2 VREFI3 ADDRESS A3 14 Digital and analog inputs are failure protected from either overvoltages that exceed the power supplies or from the loss of power. ., . MPC16S PIN DIAGRAM A3 16 ANALOG INPUTS Lr---....,! I I I L---~~ ~ __ .J __ Iv REF I I AO CHANNEL{ ~lCf-----------------I SELECT A DECODER' ADDRESS 2 (MSB) ~ ENABLE A2 X X X X L L L L H H H H L L L L H H H H L L H H L L H H L L L H L H L H L H L H L H L H L H b +v I b~ L.,---"" a--_-_--_-_--_-_--_--_-_--_-_---' ______ I ~ H H H H H EN L H H H H H H H H H H H H H H H H AO L L L L L L L L H H H pGND Al H H L L H H "ON" CHANNEL NONE I 2 3 4 5 6 7 S 9 10 11 12 13 14 15 16 TRUTH TABLE-MPC16S FUNCTIONAL BLOCK DIAGRAM-MPC16S 2S0UTA 27 -VSUPPLY 26 IN SA 2.6 IN 7A 24 IN 6A 23 IN SA 221N.4A 21 IN 3A 20 IN 2A i'9IN IA ISEIilABLE 17 ADDRESS Ao 16 ADDRESS Al 15 ADDRESS A2 +V SUPPLY 1 OUTB2 NC3 INSB4 IN7Il5 IN6B6 IN5B 7 IN4B S IN3B9 IN2B 10 INIBII GND 12 VREF13 NCI4 5 . ~ CI g c( zc( MPC8D PIN DIAGRAM -I' c( j: zw a: --~~I w II. II. I 1i I I ~~~~~====-=~~~'PGND p+v or~(M~S~B~)-------------1-r____Jp-v o!----------------------fDECODE R ENABLE _______________ ..1 FUNCTIONAL BLOCK DIAGRAM-MPC8D Ao A2 Al x X X L L L L L H H H H L L H H L L H H L H H H H H H H H H L H L H L H TRUTH TABLE-MPC8D NOTE: 1 Inputs protected. 6-275 EN ON' SWITCH PAIR NONE I 2 3 4 5 6 7 S ELECTRICAL SPECIFICATIONS ~. Typical for following"conditions:' V'+ = + 15 V. V-:;::: -J·S V•. Rsource ~ (-000 fl, TA ::. 2S o C unless o'therwise noted~ MODELS INPUT MPC16S IVIECHANICAL SP,ECIFICATIONS Units MPC8D ANALOG INPUT Voltage Range Maximum Dvervaltage Current at Maximum Overvoltage per Channel (I) .. Number of Input Channels Single-Ended Differential Reference Voltage Range(2) ON Characteristics ON Resistance (RON) Typical Maxiinum RON Drift vs. Temperature (OOC tl> +7S°C) RON Mismatch Channel-ta-channel[)ifferential Input Leakage (lL) Input Leakage Drift OFF Chara4=teristics OFf' Resistance Output' Leakage (an channels disabled) Input Leakage (7) I.eakage Drift OutPijt L.akag. ,with Input . Overvoitage of +35 V: of·3S V ±IS +Vsupply' +'20 -V supply -20 ± 18 Enable , , .;,,, 16 8 +6to+l0 V 1.3 1.8 kn 'kn 0.25 -MoC SO N/A I 'n n nA SO SO 1.0 See Fig un~ ,9 0.2 0.02 (0,54") -V supply", VL -!I-o": < 0.8 @ InA V V I nA I:J bit binary (!'! tIS V +7 to +20 V V -7 to -20 to.S rnA rnA 7.5 mW +4. ·2 I 0.01 0.005 % %ofOFF ·channel signal 7 JAS JAS 3 I 120 0.5 0.3 dB jA~ JAS ISO IS JAS ±IS I 30(6) ±IO o to +75 -65 to +150 2. ,Refe·rence, voltage controls noise' im· munity level. Normally not used (pin 13 left open). 3, Maximum overvoltage is ±Vsupply ±4 volts @ ±15 rnA. ~gic levels specified are forVREF(pin 13) 9pen: ForVREF = +10 V, VHMIN=+6V. 4. 20 volt peak-peak 1000 Hz sinewave; Rsource '? 1000 nisaine signal on all unused' chaimels. ' 5. For 20 volts between switched channels, Rsource = 1000 n. See Figure 5 for settling time vs: source impedance (Rs). 6 .. From each side of MPC8I;> to ground. V pF 7. Leakage measurement made with all OFF . channel 'inputs fed in parallel to +20 volts. % o,C °c 6-276 NOTES: 1. Total power dissipation due to input , ,overvoltage current flowing in the input protection circuitry must be limited to one watt for both (a) normal operation with power supplies turned on or (b) during a fault condition when the supplies are shorted to ground. us OUTPUT' SO N/A - , - (0,010") nA code - one of code - one of sixteen eight Logic "o"(low) disables all channels. Logic uJ" (high) enables channel select to turn on selected channel~ N/A '.254mm 15" ',jA,~ +4", VH '" +Vsupply 4 bit binary I ii ' nA 'nA I I DYNAMIC ,CHARACTERISTICS Specification Storage j' (~.~~) 3i.II~~~ 15.88mm' ~W:625') ·1 See Figure 9 Gain Error (20 Mn load) maximum Crosstalk ~4'> TEMPERATURE t , 1-13,7mm-j n POWER REQUIREMENTS Voltage Range CapaCitance to G:round Capacitance Mismatch .4S~mm (,018") 1011 Rated Power Supply Voltages Supply Range + Supply - Supply Supply Drain At I MHz SWitching Sp.ed At 100 kHz SWitching Speed Typical POwer Consumption DC to 10 kHz Setiling Tim'.(S) To 2 mV (0.01%) To 20 mV (0.10%) Common.Mode Rejection (mini~um) SWitching Time . Turn ON Turn OFF Recovery Tim.e from Input Overvoltage Pulse of 35 V for 100 "sec To 0.01% To 0.10% i=i:;~~;:;':;;p;j, ;:;;:;;:;;:;:,,:;:;, * -1_ _I~-r i=i=i, DIGITAL INPUTS Lo~ic "0"(VJJ(I)(3) Logic ., I "(VIi,)(I)(3) Channel Select V V V DISCUSSION OF PEFORMANCE mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differential errors. STATIC TRANSFER ACCURACY The static or DC transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (RON), the load impedance, the source impedance, the load bias current and the multiplexer leakage current. Referring to Figure 2, the effects of these errors can be minimized by following the general guidelines described in this section, especially for low level multiplexing applications. SINGLE-ENDED MULTIPLEXER STATIC ACCURACY LOAD (OUTPUT DEVICE) CHARACTERISTICS The major contributors to static transfer accuracy for single-ended multiplexers are: Source resistance loading error Multiplexer ON resistance error DC offset error caused by both load bias current and multiplexer leakage current. • Use devices with very low bias current. Generally, FET input amplifiers should be used for low level sigrIais less than 50 mV FS~. Low bias current bipolar input amplifum are acceptable for signal ranges higher than 50 mV FSR. Bias current matching will determine the input offset. • The system DC common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. • Load impedances, differential and common- mode, should be 10 10 ohms or higher. Resistive Loading Errors The source and load impedances will determine the input resistive loading errors. To minimize these errors: • Keep loading impedance as high as possible. This minimizes the resistive loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedances of lOS ohms or greater will keep resistive loading errors to 0.002% or less for 1000 ohm source impedances. A 106 ohm load impedance will increase source loading error to 0.2% or more. SOURCE CHARACTERISTICS • Use sources with impedances as low as possible. A 1000 ohm source resistance will present less than 0.001 % loading error and 10,000 ohm source resistance will increase source loading error to 0.01% with a lOS ohm load impedance. Input resistive loading errors are determined by the following relationship: (see Figure 1) Source and Multiplexer Resistive Loading Error E:(R + Ito)= Rs + RON x 100% where s N RS + RON + RL Rs = Rsource RL = load resistance RON = multiplexer ON resistance. • The source impedance unbalance will produce offset, common- mode and channel-to-channel gain-scatter errors. Use sources which do not have large impedance unbalances if at all possible. • Keep source impedances as low as possible to minimize resistive loading errors. • Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. If the MPCSD is used for multiplexing high-level signals of I volt to 10 volts full scale ranges, the foregoing precautions should still be taken, but the parameters are not as critical as for low-level sigrIai applications. RS 1 Ron INPUT OFFSET VOLTAGE Bias current generates an input OFFSET voltage as a result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10 nanoamperes will generate an offset voltage of 20pVoits if a 1000 ohm source is used, and 2oopVoits if a 10,000 ohm source is used. In general, for the MPC 16S, the OFFSET voltage at the output is determined by: VOFFSET = (Ib + 10 (RON + RSOURCE) where Ib =Bias current of device multiplexer is driving IL =Multiplexer leakage current RoN =Multiplexer ON resistance RSOURCE =Source resistance I L' - I bias ,...-- --, I I I I RS t6 I I '::"' Roff Vm I • measured I voltage . Z_ load L.. _ I I I - ..... FIGURE I: MPCI6S Static Accuracy Equivalent Circuit. AS lA I~ .. _ _ _ _ - - - - , I D!FFERENTIAL MULTIPLEXER STATIC ACCURACY Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low-level signals with full scale ranges of 10 to 100 millivolts. "'---------- The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current FIGURE 2: MPC-SD Static Accuracy Equivalent Circuit. 6-277 SETTLING TIME MPCI65 CHANNEL The gate-to-source and gate-to-drain capacitance of the CMOS, FET switches, the RC time constants of the source and the load determine the settling time ofthe multiplexer. Governed by the charge transfer relation i = C~~ , the charge currents transferred to both load and source by the analog switches are determined by the amplitude and rise time of the signal driving the CMOS FET switches and the gate-todrain and gate-ta-source junction capacitances as shown in Figure 3 and 4. Using this relationship, one can see that the amplitude of the switching transients seen at the source and load decrease proportionally as the capacitance of the load and source increase. The tradeoff for reduced switching transient amplitude is increased settling time. II! effect, the amplitude of the transients seen at the source and load are: FIGURE 3: Settling Time Effects-MPCI6S. x<"l"~ dVload = ~ dt where i = C ~~'Of the CMOS FET switches node A LOAD C = load or source capacitance +--+_..., node B Rd B The source must then redistribute this charge, and the effect of source resistance on settling time is shown in Figure 5. This graph shows the settling time for a 20 volt step change on the input. The settling time for s,maller step changes on the input will be less than that shown in Figure 5. SWITCHING TIME This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10 volt signal change between channels. CROSSTALK Crosstalk is the amount of signal feed through from the seven (MPC8D) or fifteen (MPCI6S) OFF channels appearing at the multiplexer output. Crosstalk is caused by the , voltage divider effect of the OFF channel OFF resistance and junction capacitances in series with the RON and RsoURCE impedances, of the ON channel. Crosstalk is measured with a 20 volt pk-pk 1000 Hert2; sine wave applied, to all OFF channels. The crosstalk for these multiplexers is shown in Figure 6. COMMON·MODE REJECTION (MPC8D ONLY) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. For the MPC8D, protection is provided for common-mode signals of ±20 volts above the power supply voltages with no damage to the analog switches. FIGURE 4: Settling & Common-Mode Effects-MPC-8D. The CMR of the MPC8D and Burr-Brown·s model 3660 Instrumentation Amplifier is 110 dB at DC to 1k Hz with a 6 dB/octave rolloff to 70 dB at 1000 Hz. This measurement of CMR is shown in Figure 8 and is made with a BurrBrown model 3660 instrumentation amplifier connected for a gain of 1000 and with source unbalances of 10k, I k!l and no unbalance. Factors which will degrade multiplexer and system DC CMR are: • Amplifier bias current and differential impedance mismatch • Load impedance mismatch • Multiplexer impedance and leakage current mismatch • Load and source common-mode impedance AC CMR rolloff is determined by the amount of commonmode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible. 6-278 TYPICAL PERFORMANCE CURVES 1000 / 100 --- TO , \ 0 1 / ~ KoO.l% 0.1 0.01 ;; c co 10 0.1 iii ;; 140r-----r----,-----r----~ 100 Source Resistance (A ) (kn) c c .r:= S FIGURE 5. Settling time vs source resistance for 20 volt step change. U u. u. iii .., o ocl00~----~~~~--~----~ 1; ~ U :; . sO~----~--~--~~----~ I u 140r----,----~----~----, Frequency (Hz) Signal Frequency (Hz) FIGURE 7. CMR vs. frequency for Model 3660 IA and MPCBD (G =1000). FIGURE 6. Crosstalk vs signal frequency. so~--~----_+--~· 60 0.9 1 Frequency (Hz) FIGURE B. Combined CMR vs. frequency for Model 3670 IA and MPCBD (G =1000). . c ~ 6~ ..= o.s II 0.7 -= ~ 0.6 !!= u 0.5 j:: &.5 ~ « , 1\ ,~ 0.4 0.3 1.5 0.2 i .'+ 5 3 FIGURE 9. Leakage current vs temperature. > !! 11 c ~ j ~2 1.3 oOC .;; T A· .. 75°C 1.2 1"- l!: ¥ 1.0 ~ : ~ 0.9 0: o.s 15 FIGURE 10. Access time vs logic level (high). \ 1. 1, 0: o 10 V H (High) Logic Level (Volts) Q 1.4 Temperature (oC) ±7 +10 :!:15 Supplv V-ortaga (volts) FIG URE 11. Normalized "ON" resistance vs. supply voltage. 6-279 OPERATION & INSTALLATION INSTRUCTIONS. The ENABLE input, pin 18, is included for expansion of the number of channels on a single node as illustrated in Figure 12. With the ENABLE line at a logic I, the channel is selected by the 3 bit (MPC8D) or 4 bit (MPCI6S) Channel Select -Address (see the Truth Tables on page 6-275. If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to +V supply. Single vs. Multi-Tiered Channel Expansion In addition to reducing programming complexity, two-tier configuration offers the added advantages over single node expansion of reduced 0 F F channel current leakage (reduced OFFSET), better CMR, and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the single node configuration, data cannot be taken from any channel, whereas only one channel group is failed (8 or 16) in the multi-tiered configuration. If the +15 volt and/or -IS volt supply voltage is absent or shorted to ground, the MPC8D and MPCI6S multiplexers will not be damaged; however, some signal feedthrough to the output will occur. Total 'package power dissipation must not be exceeded (see Footnote I, page 6-276). For best settling- speed, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pull-up resistors are recommended. See Figure 10 (access time). IN2 IN3 28 "'O;.,u::..;t'--_ _ _ _ _-, MPC16S Group 1 Ch1 -16 18.I;G;;::r~0;:.up;::_:_1--...., IN16 Enable A3A:!A1Ao To preserve common-mode rejection of the MPC8D, use twisted-shielded pair wire for signal lines and inter-tier connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as closely as possible to system analog common or to the common-mode guard driver. Multiplexer output Direct. I I To I ~ ~ :>-1_-0 I \ .... ,. Buffered I BB 3550 I 3505 or 3401 GrouPI 2 I ~A:!A1Ao I "... I .3r8 UP I" Group 4 18 Enable CHANNEL EXPANSION r----, ':.! To I I MPC16S Group 4 I Ch49-64 28F0::..;u;.:t_ _ _ _ _ _..... Settling tl ma to 0.01 % for R < 100 n -Two MPC16S units in parer'el: 10 #Ls SINGLE ENDED MULTIPLEXER (MPC16S) Up to 64 channels (4 multiplexers) can be connected to a single node, or up to 256 channels using 17 MPCI6S multiplexers on a two-tiered structure as shown in Figures 12 and 13. -Four MPC8D units in parallel: 12 #LS FIGURE 12. 32 To 64 Channel, Single-Tier Expansion. ~ ,C)o INl !~e «U DIFFERENTIAL MULTIPLEXER (MPC8D) o~ Single or multi-tiered configurations can be used to expand multiplexer channel capacity up to 64 channels using a 64 x I or 8 x 8 configuration. ;;~ IN2 IN3 28 Out MPC16S C.c .~- 'C)o IN16 18 ~n AoA1A:!~ Multiplexe~ +V ill SINGLE NODE EXPANSION The 64 x I configuration is simply eight MPC8D units tied to a single node. Programming is accomplished with a 6 bit counter, using the 3 ISB's of the counter to control Channel Address inputs AO, Al and A2 and the 3 MSB's of the counter to drive an 8 or I decoder. The 8 of I decoder then is used· to drive the ENABLE inputs (pin 18) of the MPC8D multiplexers. To I I I I ot~e~ JpJ16 Ch ! 10lOt ~ g~ ~~ ~§ ~ TWO TIER EXPANSION 1.-- - ., MPC16S II," .... En,'" - I .... >'0 I 18~~ I" I" J'IN16 AoAl A:!A3 I+V .. Buffered B83550 3505 or 3401 I' 28 ~ L..!.+ . MPC16S 'C)o IN16 18 AoA1A:!~ ~: II Using an 8 x 8 2-tier structure for expansion to 64 channels, the programming is simplified. The 6 bit counter output does not require an 8 of I decoder. The 3 LSB's of the counter drive the AO, A I and A2 inputs of the eight first tier multiplexers and the 3 MSB's of the counter are applied to the AO, A I and A2 inputs of the second tier multiplexer. Direct 28 Out I Enable Inputs INl IN2 IN3 Outputs INl Settling time to 0.01 % is 20 ~s with Rs S lOOn I III 4LSB's 4MSB's 8 Bit Channel Address Gen. I FIGURE 13. Channel ExpanSIOn Up To 256 Channels Usmg 16 x 16 Two Tiered Expansion. 6-280 BURR-BROWN® PCM50KG I &lEi I DESIGNED FOR AUDIO ADVANCE INFORMATION Subject to Change 16-Bit Hybrid DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • 1I1·BIT RESOLUTION • 5ltae SEmlNG TIME Typ .• 0.003% THD (FS Inpul18 Bltl) Typ • 0.02% THD (·l5dB. 18 Bill) Max • 96dl DYNAMIC RANGE • EIAJ STC-007·COMPATIBLE • LOW COST The PCMSO is designed for PCM audio applications and is compatible with EIAJ STC-007 specifications. The PCMSO may be operated as either a l6·bit or a 14-bit converter. It features wide dynamic range, low distortion, and has a very-fast settling time . The PCMSO contains an internal voltage reference. It uses state-of-the-art IC and laser-trimmed thin-film components. The converter combines high quality and high performance with low cost. • PIN"cOMPATIBLE WITH DAC71·COB·V IHITLADDER RESISTOR NETWORK AND CURRENT SWITCHES AUDIO OUTPUT Intlrnlllooll Alrparllndullrlal Park· P.O. Box 11400· Tuclon. Arizooa 85734· Tel. 1602) 746-1111 • Twx: 911J.952·1111 . Cabla: BBRCORp· Talax: 66-8491 PDS4SO 6-281 SPECIFICATIONS ELECTRICAL (TA = +25"C and rated power sU'pplies uriless otherwise noted ..1 ,. MODEL I MIN MECHANICAL . PC_KG I TYPI, .AXI U"", "', INPUT DIGITAL INPUT Resolution Dynamic Range Logic Levels ,.TTL-Compatiblel(') Logic "1" lat +~i'AI Logic "0" (at '1.6mAI 16 Bits .dB 96 +2.4 0 +5.5 +0.4 VDC VDC ±0.5 .±25 '!I. mV f ,. 0 ±O.1 ±10 0.0015 %01 FSR(4) 0.004 0.003 '!I. '!I. TOTAL HARMONIC DIITORTION(31 Vo = ±FS at I = 400Hz 1,4,1111 Resolulion Hl-Bit Resolution Vo = -15dB at I ='4OOHz 14-Bit Resolution 16-Bit Resolution Vo = -&OdB at I = 400Hz 14-Bit Resolution 16-Bit Resolution 0.02 0.01 0.02 '!I. '!I. '!I. '!I. 4.2 1.9 DRIFT (Over Specilied Temparature Rangel Total Bipolar Drift tincludes gain, offset, and linearity drift)· ±25 ±50 ppm 01 FSR/oC SETTUNG TIME ITo ±O.OO6'!I. 01 FSRI WARM-UP TIME i'sec i'S8C Vii'S8C 5 ,3 Oulput: 20V Step 1LSB Step(5) Slew Rate 20 1 Min A~O":J~ n ANALOG OUTPUT Ranges Output Current Output Impedance I DC I Short-Circuit Duration ±10 ±5(6) ±5 0.05 Indelinite To Common L r t1e'T'1. . Voltaga, Vs ±14.5 +4.75 +5 33.27 34.54 .810 19.56 20.57 c .210 3.81 5.33 0 .01e .021 0.46 0.53 F .035 0.89 0 G .080 .100 BASIC H .110 .130 2.79 ±15.5 +5.25 VDC VDC mA mA +70 +85 +100 °C °C °C ±25 ±20 MILLIMETERS MIN MAX 1.360 ,150 '!I. 01 FSR/'!I.Vs '!I. 01 FSR/% Vs . %oIFSR/'!I.Vs ±15 INCHES MIN MAX 1.310 .770 POWEll SUPPLY REQUIRMENTS Supply Drain, ±15VDC (no loadl , +5VDC (logiC supply I . B SENSITIVITY ±O.002 ±0.02 ±O.002 Pin numbers shown lor reference only. Numbelll may not be marked on package. V V mA POWER SUPPLY +5VDC -15VDC +15VDC I Note: Leads in true position within 0.010" 10.25mml Rat MMC at seating plane. DIM OUTPUT " ~' TRANSFER CHARACTERISTICS Gain Error(2) Offset Errorl2) Differential Linearity Error (at major carry) 0 B 1.27 2.54 BASIC 3.30 6.35 , K .150 .250 .600 BASIC N .002 ,010 0.05 0.25 DB. .105 2.16 2.67 A 3.81 15.24 BASIC CASE: Black Ceramic MATING CONNECTOR: 245MC WEIGHT: 8.4 grams (0.3 oz. I HERMETICITY: Conloo:ms to method 1014 condition C step 1 (fluorocarbon I of MIL-STD-883 (gross leak I. TEMPERATUIIEIIANGE Specilication Oparating (derated specs I Storage 0 -25 -55 NOTES: 1. Adding external CMOS hex buffers CD4009A will provide 15VDC CMOS input compatibility. The percent change in output I Vo las logic 0 varies Irom O.OV to +O.4V and logic 1 changes Irom +2.4V 10 +5.0V on all inpuls is less than 0.006% 01 FSR. 2. Adjustable zero with external trim'potentiometer. (Applies only ±lOV operation.) _ 3. The measurement of total harmonic distortion is highly dependent on the characteristics of the measurement circuit. A block diagram of a measurement circuit is shown in Figure 3. Burr-Brown calculates THD1rom the measured linearity errors using equation (2) in the section on ''Total Harmonic Distortion", and spacilies that the maximum THO measured with the circuit shown In Figure 3 will be less than the limits indicated. 4. FSR means Full Scale Range and is 20V lor ±10V range and 10V lor ±5V range. 5. LSB is lor 14-bit resolution. 6. An externall0kn ±O.l resistor (TCRE:;; ±50ppmfOC) must be connected from pin 21 to pin 17 to obtain a ±5V output range. to to 6-282 . CONNECTION DIAGRAM PIN ASSIGNMENTS Pin No. Bitl (MSBI Bit2 Bit3 Bit4 BitS Bit6 Bit7 Bit8 Bit9 Bitl0 Bitll Bit12 Bit13 Bit14 Bit15 Bit 16 (LSBI AUDIO OUT +5VDC .15VDC COMMON SUMMING JUNCTION GAIN ADJUST +15VDC TEST POINT 1 3 4 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ·±O.1% resistor (required only for ±5V output range I. THEORY OF OPERATION The accuracy of a OJ A converter is described by the transfer function shown in Figure I. The errors in the OJ A converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling mi'tworks, power supply rejection, and reference errors. In summary, these errors consist of initial errors Including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the minus full scale point (all bits Oft), and Offset drift shifts the line left or right over the operating temperature range. Total Harmonic Distortion (THO) is a measure of the magnitude and distribution of the Linearity Error, 0111 ... 1101 0111 •. 1110 0111_.1111 h 1101•.01lI0 1Il10...1011 OFFSET ERRO\. 1JIIII...01110 01lI0...101. 5 i~ 1111...1110 1111..11;1 + ALL BITS ON, GAIN ERROR, • i • . '\ ,---~~-+__I I - - - -..... t • I ~,. • . '. ·FSR 12 BIPOLAR ZERO Differential Linearity Error, and Noise, as well as Quantization Error, that is useful in audio applications. To be useful, THDshould be specified for both high level and low level input signals. This error is unadjustable and is the most meaningful indicator of 0/ A converter accuracy for audio applications. The resolution of a 0/ A converter can be expressed in terms of Dynamic Range. The Dynamic Range is a measure of the ratio of the smallest signals the converter can produce to the full scale range and is usually expressed in decibels (dB). The theoretical dynamic range of a converter is approximately 6 x n, where n is the number of bits of resolution, or96dB for a 16-bit converter. The actual or useful dynamic range is limited by noise and Imearity errors and is therefore somewhat less than the theoretical limit. DIGITAL INPUT CODES The PCM50 accepts complementary digital input codes in binary format. It may be connected by the user for either complementary offset binary (COB) or complementary two's complement (CTC) codes. See Table I. TABLE I. Digital Input COdes. DIGITAL INPUT CODES I MSB I~AI:":A:-:L06~OU=T:::PU=T'11~I+~FS:":R~/~21~'I~LSB All bits ON MidScale All b~sOFF "SEE TABLE I FOR OlGITALCODE DEFIIITIONS. FIGURE I. Input vs Output for an Ideal Bipolar 0/ A Converter. LSB L. .J 0111...111 1111 ... 111 1000...000 COB CTC' Complementary Ollset Binary Complementary Two's Complement +FuliScale Zero -Full Scale -lLSB -lLSB -Full Scale Zero +FuliScale • A TTL Inverter must be connected between the MSB ,"put Signal and bit 1 (pin 1) to obtain eTC input code. 6-283 DISCUSSION OF SPECIFICATIONS 0.3 The PCMSO is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for a DI A converter in audio applications are total harmonic distortion, drift, gain and offset errors, and settling-time effects on accuracy. This DAC is factory-trimmed and tested for all critical key specifications. ~ 0.1 ,., 0.03' '0 ~ (J ~ 0.01 (J (J < 0.003 GAIN AND OFFSET ERROR Initial Gain and Offset errors are factory-trimmed to typically ±o.I% of FSR at 2S"C. These errors may be trimmed to zero by connecting external trim potentiometers as shown in Figure S. POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The PCMSO power supply sensitivity is specified for ±0.02%ofFSR/% Vs, for-ISVDC supplies and ±o.002% of FSR/% Vs, for +SVDC and +IS.YDC supplies'. Normally, regulated power supplies with 1% or less ripple are recommended for use with this DAC. See also Power Supply Connections paragraph in the Installation and Operating Instructions section. SETTLING TIME Settling time is the total time (including slew time) required for the output to settle within an error band around its final value after a change in input (see Figure 2) . BB OPAI03 OR EQUIVALENT + ---, I I SIMPLIFIEDSCH~ :J;: [ OF OERLITCHER 2X 741.S181 BINARY COUNTER - 2X 2718 PROM'S' FIGU RE 2. Full Scale Range Settling Time vs Accuracy. Settling times are specified to ±0.006% of FSR; one for maximum full scale range changes of 20V and one for a I LSB change. The I LSB change is measured at the major carry (0111. .. 11 to 1090 ... 00), the point at wl)ich the worst-case settling time occurs; TOTAL HARMONIC DISTORTION The Total Harmonic Distortion (THD) is defined a!!. the ratio of the square rooi of the sum of the squares of the value of the rms harmonics to the value of the rms fundamental and is expressed in percent or dB. A block diagram of the test .circuit used to measure the TJ:l D of the PCMSO is shown in Figure 3. A timing diagram for the control logic is shown in Figure 4. TI\e digital input code 101m LC..J 5pF 100 Settling Time I ~sec I •• 3IiIiOK OR EQUIVALENT ANALOR SWITCH IMP71t12 OR EQUIVALENT) ~--,....... 0.001 0.1 VOUT ± DESLITCHER CONTROL 4X " "- "DUT (PCM5O( LATCH 741.875 USE 400Hz HIBH·PASS FILTER AND 30ldtz LOW·PASS FILTER. "" DISTORTION METER HP 3SBA OR . EQUIVALENT " LOW.pASS FILTER DESLITCHER DEBLITCHER CONTROL. o,....,.....,...,.~., TlMIN. COIITROL LOIIC .201t-+-+-+--+l-'-I SEE CONTROL LOGIC TlMINS (Flgur. 4~ i: -4D1--1--1--1--H-t i-80t-+-+-+-++-I .aD1t-t-HH+-i LOW.pAIS FILTER CHARACTERISTIC 'SEE TABLE III. FIGURE 3. Block Diagram or'Distortion Test Circuit. 6-284 ·IOO......~.................. I 101 102 1031 FREQ. (Hzl 10& stored in the PROM as well as the output obtained from an ideal PCM50, the value of an ideal sine wave, and the inherent quantization error are given in Tables III and IV. If we assume that the error due to the test circuit is negligible, then the rms value of the PCM50error referred to the input can be shown to be (I) where N is the number of squares, EL(i) is the linearity error of the PCM50 at each sampling point, and EQ(i) is the quantization error at each sampling point. The THD can then be ex pressed as meters as shown in Figure 5 and adjust as described below. TCR of the potentiometers should be 100ppmj"C or less. The 3.9MB and 270kB resistors (20% carbon or better) should be located close to the PC M50 to prevent noise pickup. If it is not convenient to use these high value resistors, an equivalent "T" network, as shown in Figure 6, may be substituted in place of the 3.9MB. AO.OOIIlFto 0.0 IIl F ceramic capacitor should be connected from Gain Adjust (pin 22) to Common (pin 20) to prevent noise pickup. Refer to Figure 7 for relationship of offset and gain adjustments for bipolar D/ A converters. (2) trm, THD=-= Erm~ -----:::----- X Erm.. +VS 100% GAIN ADJUST This expression indicates that, in general, there is a correlation between the THD and the square root of the sum of the squares of the linearity errors at each digital word of interest. However, this expression does not mean that the worst-case linearity error of the D/ A is directly correlated to the THD. For the PCM50 the test period was chosen to be 22.7JJ.sec (44.056kHz) which is compatible with the EIAJ STC'{)07 specification for PCM audio. The test frequency is 400Hz and the amplitude ofthe input signal is -15dB down from full scale. OFFSET ADJUST FIGURE 5. External Offset and Gain Adjust. 3.9M!! IlIOkn l80kn ~=~ llOkIl . ---'n. .__---'~ B: LATCHI£NA8L£n'-_ _ I C: O£GLlTCH£Rl :,,..~ _ _ _....., CONTROL tW FIGURE 6. Equivalent Resistances. U -. r- 2.5,... . -L- ILSB :!:r- RANG£ OF +FUU SCALf,.;' " ,.. GAIN A~J. ~~-'t /X T... ! ~ FIGURE 4. Control Logic Timing for PCM50 Distortion Test Circuit. ~~ OFFSET AOJ.-L POWER SUPPLY CONNECTIONS Offset and gain may be trimmed by installing external offset and gain potentiometers. Connect these potentio- GAINADJ. ROTATES THELINE Ii f . .J I" MSB ON ..... I~ ~ ~07 : TRANSLATES-. THE LINE '., EXTERNAL OFFSET AND GAIN ADJUST ~.. ~< BIPOLAR OFFSET· INSTALLATION AND OPERATING INSTRUCTIONS 0::::: For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagram. These capacitors (lJJ.F tantalum or electrolytic recommended) should be located close to the PCM50. :: :::l ~ ALL BITS L06~ I " ; )( ;"1/ ALL OTHERS OFF ~iG~t: OFFS£T /.01 :DJy. L V "FULL SCALE DIGITAL INPUT FIGURE 7. Relationship of Offset and Gain Adjustments for a Bipolar Dj A Converter. OFFSET ADJUSTMENT Apply the digital input code that should produce the maximum negative output voltage. The PCM50 is internally connected for a 20V FSR range where the maximum negative output voltage is -IOV. See Table II for corresponding codes and Figure 5 for offset ·adjust- 6-285 ment connections. Offset adjust should be completed prior to gain adjust. GAIN ADJUSTMENT Apply the digital input that should give the maximum positive output voltage. Adjust the gain potentiometer for this positive full scale voltage. See Table II for positive full scale voltages and Figure 5 for gain adjustment connections. TABLE II. Digital Input and Analog Output Relationships. DIGITAL INPUT CODE ; Complementary Bipola, Offset Binary COB ±1OV OneLSB All Bits On 00..00 All Bits ofi 11 .. 11 ±5V' One LSB All Bits On 00 ..00 All Bits 011 11..11 'HIIT IIESOLunON '4-II1T IIESOLUTION +30S~V +9.99969V -10.0000v +1.22mV +9.99878V -10.0000V +1S2~V +610~V +4.99848V -S.OOOOV +4.99939V -S.OOOOV 'An external10kO ±O.1'111 ,esislo, must be connected f,om pin 17 to pin 21 to obtain ±5V ,ange (see Connection Diagram). should be less than RJ.m;n/ i 6 to reduce voltage drops d;ue to \Viringto less than I LSB. For example. if RJ.mm is 5kU. then RJ should be less than·0.08H. RJ. should be located as close as possible to the PCM50 for optimum performance. The PCM50 and the wiring to its connectors should be located to provide optimum isolation from sources of RFI and EMI. The key word in elimination of RF radiation or pickup is loop area; therefore. signal leads and their return conductors should be kept close together. This reduces the external magnetic field along with any radiation. Also. if a signal lead and its return conductor are wired close together they present a small flux-capture cross section for any external field. This reduces radiatior. pickup in the circuit. (NOTE: [t is recommended that the digital input lines of the PCM50 be driven from inverters or buffers of TTL input registers to obtain best results.) APPLICATIONS A single PCM50 can be used for both the [eft and right channel as shown in Figure 9. Note that a Samp[e/ Ho[d is not required. INSTALLATION CONSIDERATIONS If 16-bit resolution is not required. bit 15 (pin 15)and bit 16(pin 16)should be connected to+5VDC through a I kO resistor. ,Figure 8 shows the connection diagram for a PCM50. Lead and contact resistances are represented by RJ through R3. As long as the load resistance (Rd is constant. RJ simply introduces a gain error that can be removed during initial calibration. R2 is part of RJ. if the output voltage is sensed at Common (pin 20) and therefore introduces no error. If RJ. is variable. then RJ PCMSO FIGURE 9. PCMSO Used for Stereo. ~~~l '----_.nMJJ Tab[e III shows the hex code loaded into the PROM's of the Distortion Test Circuit, Figure 3, for 14-bit va[uesand Tab[e [V shows the hex code for [6-bit values. Va[uesare for a 400Hz sine wave (-[5dB offull scale); all values are in volts. +II t-1;.."F4 I"F >--_ _ _-=C::OM=-I . -v ±15VOC SUPPLY +V COM -t6VOC SUPPLY FIGURE 8. Output Circuit for PCM50 6-286 TABLE III. Hex Code for 14-Bit Values (-15dB Output in 20V Full Scale Range), COOE. ] 2 3 4 5 6 7 e 9 ]0 ]1 ]2 ]3 ]4 ]5 ]6 17 ]8 ]9 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 HEX CODE IDEALDAC OUT (Volts) IDEAL SINE VALUE (Volts) 7FFF 7EB3 7D67 7C1F 7AD7 7997 7857 7723 75F3 74CF 73AF 729F 7197 709B 6FAB 6ECB 6DF7 6D33 6C7F "6BDF 6B4B 6AC? 6A5B 69FB 69AF 6977 6953 693F 693F 6953 6977 69AF 69FB 6A5B 6AC7 6B4B 6BDF 6C7F 6D33 6DF7 6ECB 6FAB 709B 7197 729F 73AF 74CF 75F3 7723 7857 7997 7AD7 7C1F 7D67 7EB3 0.000000 .101318 .202637 .302734 .402832 .500488 .598145 .692139 .784912 .874023 .961914 1.044922 1.125488 1.202393 1.275635 1.343994 1.408691 1.468506 1.523438 1.572266 1.617432 1. 657715 1.690674 1.719971 1.743164 1.760254 1.771240 1.777344 1.777344 1.771240 1.760254 1.743164 1.719971 1.690674 1.657715 1.617432 1.572266 1.523438 1.468506 1.408691 1.3'43994 1.275635 1.202393 1.125488 1.044922 .961914 .874023 .784912 .692139 .598145 .500488 .402832 .302734 .202637 .101318 0.000000 .101520 .202709 .303236 .402775 .500999 .597.590 .692231 .784614 .874439 .961410 1.045246 1. 125673 1.202428 1.275261 1.343934 1.408223 1.467920 1.522828 1.572769 1.617580 1.6571:5 1.691244 1.719857 1.742861 1.760179 1.771756 1.777554 1.777554 1.771756 1.760179 1.742861 1. 71985.7 1.691244 1.657115 1. 617580 1.572769 1.522828 1.467920 1.408223 1.343934 1.275261 1.202428 1.125673 1.045246 .961410 .874439 .784614 _ .692231 .597590 .500999 .402775 .303236 .202709 .101.520 QUANTIZING ERROR (Volts) 0.000000 .000201 .000072 .000502 -.000057 .000511 -.000555 .000092 -.000298 .000415 -.000504 .000325 .000185 .000035 -.000374 -.000060 -.000468 -.000586 -.000610 .000503 .000148 -.000600 .000570 -.000113 -.000303 -.000075 .000516 .000210 .000210 .000516 -.000075 ~--'----r------.-------r---~, HEX IDEAL DAC QUANTIZING IDEAL SINE CODE. OUT I Volts , ERROR {Voitsl CODe VALUE I Volts , 56 57 58 59 150 61 62 63 64 65 66 67 68 69 ;'0 ;-1 ;-2 ;'3 ;-4 -,~ (._1 ;-6 ('7 ;'8 '('9 ~:0 €: 1 &:2 .:3 €:4 .:5 .:6 -.00030~ E:7 -.000113 .000570 -.000600 .000148 .000503 -. ,000610 -.000586 -.000468 -.000060 -.000374 .000035 .000185 .000325 -.000504 .000415 -.000298 .000092 -.000555 .000511 -.000057 .000502 .000072 .000201 .:8 .:9 ~18 ~Il ~12 ~13 ~14 ~15 ~16 ~17 :18 ','9 ]00 101 102 i03 104 105 106 107 108 109 110 6-287 7FFF 814B 8297 83DF 8527 8667 87A7 88DB 8A0B 8B2F 8C4F 8D5F 8E67 8F63 9053 9133 9207 92CB 937F 941F 94B3 9537 95A3 9603 964F 9687 96AB 96BF 96BF 96AB 9687 964F 9603 95A3 9537 94B3 941F 937F 92CB 9207 9133 9053 8F63 8E67 8D5F 8C4F 8B2F 8A0B 88DB 87A7 8667 8527 83DF 8297 814B 0.000000 -.101318 -.202637 -.3027:34 -.4028:32 -.500488 -.598145 -.6921:39 -.784912 -.874023 -.961914 -1.044922 -1. 125488 -1. 202393 -1.275635 -1.343994 -1. 408691 -1.468506 -1.523438 -1.572266 -1.617432 -1. 657715 -1.690674 -1. 719971 -1.743164 -1.76025'4 -1. 771240 -1.777344 -1.777344 -1. 771240 -1.760254 -1. 743164 -1. 719971 -1.690674 -1.657715 -1.617432 -1,572266 -1.523438 -1.468506 -1. 408691 -1.343994 -1.275635 -1.202393 -1.125488 -1.044922 -.961914 -.874023 -.784912 -.692'1:39 -.598145 -.500488 -.402832 -.3027:34 -.2026:37 -.101318 0.000000 -.101520 -.202709 -.303236 -.402775 -.500999 -.597590 -.69223, -.784614 -.874439 -.961410 -1.045246 -1.1256;'3 -1.202428 -1.275261 -1.343934 -1.408223 -1.467920 -1.522828 -1.572769 -1.617580 -1.657115 -1. 691244 -1. 719857 -1.742861 -1.7601;'9 -1.771756 -1.777554 -1.777554 -1. 771756 -1.760179 -1.742861 -1.719857 -1.691244 -1.657115 -1.617580 -1.572769 -1.522828 -1.467920 -1.408223 -1.343934 -1.275261 -1.202428 -1.125673 -1.045246 -.961410 -.874439 -.784614 -.692231 -.597590 -.500999 -.402775 -.303236 -.202709 -.101520 0.000000 -.000201 -.000072 -.000502 .000057 -.000511 .000555 '-.000092 .000298 -.000415 .000504 -.000325 -.000185 -.000035 .000374 .000060 .000468 .000586 .000610 -.000503 -.000148 .000600 -.000570 .000113 .000303 .000075 -.000516 -.000210 -.000210 -.000516 .000075 .000303 .000113 -.000570 .000600 -.000148 -.000503 .000610 .000586 .000468 .000060 .000374 -.000035 -.000185 -.000325 .000504 -.000415 .0'00298 -.000092 .000555 -.800511 .000057 -.000502 -.800072 -,000201 TABLE IV, Hex Code for 16-Bit Values (-15dB Output in 20V Full Scale Range), CODE. I 2 3 4- 5 6 7 8 9 ]0 ]1 12 13 14 15 ]6 ]7 18 19 ~:0 ~: 1 ~:2 ~::3 ~:4 ~:5 ;:6 ~? ;:8 ~:9 ::0 ,:1 ~l2 :::3 ::4 :::5 :::6 :::7 :;:8 ,:9 40 41 42 43 ,44 45 46 47 148 49 ~;0 ~; 1 ~;2 ,..., ,'~ ~;4 ~;5 HEX CODE IDEAL DAe OUT IVolts) IDEAL SINE VALUE (Volts I 7FFF 7EB2 7D67 7CID 7AD7 7995 7859 7723 75F4 74CE 73Bl 729E 7196 709B 6FAC 6ECB 6DF9 6D35 6C81 6BDD 6B4B 6AC9 6A59 69FB 69B0 6977 6951 693E 693E 6951 6977 69B0 69FB 6A59 6AC9 6B4B 6BDD 6C81 6D35 6DF9 6ECB 6FAC 709B 7196 729E 73Bl 74CE 75F4 7723 7859 7995 7AD7 7CID 7D67 7EB2 0.000000 .101624 .202637 .303:345 .4028:32 .5010'39 .5975:34 .692139 .784607 .874329 .961304 1.045227 1.125793 1.202:393 1.275:330 1.343994 1.408081 1.467896 1.522827 1.572876 1.617432 1.657104 1. 691284 1.719971 1.742859 1.760254 1.771851 1.777649 1.777649 1. 771851 1.760254 1.742859 1.719971 1.691284 1.6571134 1.617432 1.572876 1.522827 1.467896 1.408081 1.343994 1.275330 1.20n93 1.125793 1.045227 .961304 .874329 .7846137 .692139 .597534 .51310':19 .4028:32 .3133345 .202637 .101624 0.000000 .101520 .202709 .303236 .402775 .500999 .597590 .692231 .784614 .874439 .961410 1.045246 1.125673 1.202428 1. 275261 1.343934 1.408223 1.467920 1.522828 1.572769 1.617580 1.657115 1.691244 1.719857 1.742861 1.760179 1.771756 1.777554 1.777554 1.771756 1.760179 1.742861 1.719857 1.691244 1.657115 1.6175813 1.572769 1.522828 1.4679213 1 . 4082;~3 1.343934 1.275261 1.202428 1. 125673 1.045246 .961410 .874439 .784614 .692231 .597590 .500999 .402775 .303236 .202709 .101520 QUANTIZING ERROR (Voitsl 0,.000000 -.000104 .000072 -.000109 -.000057 -.000099 .000056 .000092 .000007 .000110 .000107 .000019 -.000120 .000035 -.000069 -.000060 .000142 .000024 .000001 -.000107 .000148 .000010 -.000040 -.000113 .000002 -.000075 -.000094 -.000095 -.000095 -.0000.94 -.000075 .000002 -.13013113 -.0013040 .130130113 .13013148 -.130131137 .001313131 .13001324 .1300142 -.1300060 -.1300069 .000035 -.0013120 .0001319 .1300107 .1313131113 .000007 .1300092 .131301356 -.000099 -.000057 -.0013109 .000072 -.000104 CODE. ~i6 ~;7 ~;8 ~;9 ,:0 ,: 1 ,:2 ,:3 ,:4 ,:5 E;6 E;7 1:8 1:9 ('0 ('1 -;"2 ('3 ,'4 '('5 7'6 "('7 7'8 ('9 t:0 (:1 (:2 E:3 (:4 t:5 E:6 El7 E:8 E:9 ~10 ','I ~12 ':1:3 ~'4 HEX CODE 7FFF 814C 8297 83E1 8527 8669 87A5 88DB 8A0A 8B30 8C4D 8D60 8E68 8F63 9052 913:3 9205 92C9 937D 9421 94B3 9535 95A5 9603 964E 9687 96AD 96C0 96C0 96AD 9687 964E 9603 95A5 9535 94B3 9421 937D 92C9 ~15 '3205 ':16 9133 9052 8F63 8E68 8D6a 8C4D 8B3a 8A0A 88DB 8lAS 8669 8527 83El 8297 814C ':'7 ~1:3 ':1'3 ]00 ] 01 ]02 ]03 liH 105 ]06 1137 ]08 ]09 110 6-288 lDEALDAC OUT (VoltS) 0.000000 -.101624 -.2026:37 -.303345 -.402832 -.5010'39 -.5975:34 -.6921:39 -.784607 -.874329 -.961304 -1.045227 -1. 125793 -1.202393 -1.275330 -1.343'394 -1.408081 -1.467896 -1.522827 -1.572876 -1.617432 -1. 657104 -1. 691284 -1.719'371 -1.742859 -1.760254 -1.771851 -1.777649 -1.777649 -1.771:351 -1.760254 -1.742859 -1..71'3'371 -1. 691284 -1.657104 -1. 617432 -1.572876 -1.522827 -1.467896 -1.4081381 -1. 343'394 -1.2753313 -1.202:393 -1.125793 -1.045227 -.9613134 -.874329 -.7846137 -.692139 -.597534 -.501099 -.4028:32 -.3133345 -.202637 -.101624 IDEAL SINE VALUE (Volts) 0.000000 -.101520 -.202709 -.303236 -.402775 -.500999 -.597590 -.692231 -.784614 -.874439 -.961410 ~1.045246 -1.125673 -1.202428 -1.275261 -1.343934 -1.408223 -1.467920 -1.522828 -1.572769 -1.617580 -1.657115 -1.691244 -1.719857 -1.742861 -1.760179 -1. 7717~)6 -1.777554 -1.777554 -1.771756 -1.7601?9 -1.742861 -1.719857 -1.691244 -1.657115 -1.617580 -1.572769 -1. 5228;~8 -1.467920 -1.408223 -1. :3439:34 -1.275261 -1.202428 -1.1256;':3 -1.045246 -.961410 -.874439 -.784614 -.692231 -.597590 -.500999 -.4£12775 -.30:3236 -.202709 -.10152(J QUANTIZING ERROR (Volts) 0.000000 .000104 -.000072 .000109 .000057 .000099 -.000056 -.000092 -.000007 -.000110 -.000107 -.000019 .000120 -.00003'5 .000069 .000060 -.000142 -.000024 -.000001 .000107 -.000148 -.13013010 .000040 .1300113 -.1300002 .000075 .000094 .000095 .0001395 .000094 .0130075 -.000002 .000113 .000040 -.000010 -.000148 .000107 -.000001 -.000024 -.000142 .1300060 .01301369 -.1313131335 .130131213 -.000019 -.000107 -.0001113 -.13001307 -.0013092 -.0130056 .1300099 .1313131357 .01313109 -.130131372 .0001134 BURR-BROWN® PCM51JG 11511511 DESIGNED FOR AUDIO ADVANCE INFORMATION Subject to Change 16-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • 16-BIT RESOLUTION • 350nlac SETTLING TIME. typ (I Modal) • 5ltSBC SETTLING TIME. typ (V Modal) • 0.006% OF FSR MAX DIFFERENTIAL LINEARITY ERROR (0.0025% typ) • 0.0025% THO (FS Input. 16 Bits). typ • 0.012"10 THO (-15dB. 16 Blls). Iyp • 96dB DYNAMIC RANGE • EIAJ STC-007 COMPATIBLE • PIN COMPATIBLE - oAC71 & PCM50 The PCM51 is designed for PCM audio applications and is compatible with EIAJ STC'{)07 specifications. The PCM51 may be operated as either a 16-bit or a I 4-bit converter. It features wide dynamic range, low differential linearity error, low distortion, and has a very-fast settling time. The PCM51 contains an internal voltage reference. It uses state-of-the-art IC and laser-trimmed thin-film components. The converter combines high quality and high performance with low cost. • LOW COST BOTH VO~TA8E·OUTPUT IPCM6IJG-VI AND CURRENT·OUTPUT IPCM5IJG-11 MODELS ARE AVAILABLE. PCM5IJG·1 DIlES NOT CONTAIN OUTPUT OPERATIONAL AMPLIFIER. REFERENCE VOLTAGE RF PARALLEL DIGITAL INPUT III-BIT LAODER RESISTOR NETWORK AND CURRENT SWITCHES AUDIO OUTPUT International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. 16021 746·1111 • Twx: 9·10-952·1111 . Cable: 8BRCORp· Telex: 66·6491 PDS-462 6-289 MECHANICAL SPECIFICATIONS ELECTRICAL (TA = +25'C,and rated power supplies unless otherwise noted.) MOOEL MIN NOTE: Leads PCMS1JG TYP JIAX UNITS INPUT I DIGITAL INPUT Resolution • Dynamic Range Logic Levels (TTL-Compatible)(') Logic "1" at +401lA Logic "0" at -1.6mA . 16 I Bits dB 96 +5.5 +0.4 VDC VDC ±O.1 ±10 ±O.5 ±loo % mV 0.0025 0.006 %01 FSR(3) 0.004 0.0025 0.005 % % 0.06 0.04 % % +2.4 0 Bipolar Zero Error(2) Differential Linearity Error at Bipolar Zero TOTAL HARMONIC DISTORTION(') Vo = ±FS at 1 = 400Hz 14-Bit Resolution 16-Bit Reso)ution Vo = -15dB at 1 = 400Hz 14-Bit Resolution 16-Bit Resolution Vo = -2OdB at f = 400Hz 14-Bit Reso)ution 16-Bit Resolution '. Vo = -60dB at f = 400Hz 14-Bit Resolution 16-Bit Reso)ution 0.023 0.012 DRIFT (Over Specified TemperatureRange) Total Bipo)ar Drift (includes gain, oflsst, and linearity drift) 0.04 0.025 % % 4.2 1.9 % % ±25 SETTLING TIME (To ±0.006% of FSR) Voltage Model, PCM51JG-V Output: 20V Step 1LSB Step(S) Slew Rate Current Model, PCM51JG-1 Output: 1 mA Step 100 to 1000 load lkO Load(S) ;-. 1>- ,3' :L' , "~A~ B ±SO NL fMe'Tip CASE: Black Ceramic MATING CONNECTOR: 245MC WE)GHT: 8.4 grams (0.3 oz.) HERMETICITY: Conforms to method 1014 condition C step 1 (fluorocarbon) of MIL-STD-683 (gross leakl. ppm of FSRI"C INCHES DIM 5 3 20 "sec "sec VI"sec nsec nsec 350 350 Min 1 OUTPUT ±10 ±5(7} ±5 0.1 IndeTte ; : CT MILLIMETERS MIN 'MAX MIN MAX A 1.310 1.360 33.27 34.54 •c .770 .810 19.56 20.57 .150 .210 0 .ens .021 3.81 0.46 0.53 F .00S .050 0.89 1.27 . N " G .100 BASIC H ."0 .130 ,160 .250 L .600 SA Ie .002 ANALOG OUTPUT Voltage Model, PCM51JG-V Ranges Output Current Output Impedance (DC) Short-Circuit Duration Current Model, PCM51JG-1 Range Output Impedance ...... . f •• 0.00 •••• TRANSFER CHARACTERISTICS Gain Error WARM-UP TIME Pin numbers ahownl(lr reference only. Numbers may not be marked on package. in true position~ Within 0.10" (0.25mm) R at MMCat seating plane. OBS .010 .105 5.33 2.54 BASIC 2.79 3.81 3.30 6.35 15.24 BASIC 0.05 0.25 2.16 2.67 V V mA 0 mon mA kn POWER SUPPLY SENSITIVITY -15VDC +15VDC POWER SUPPLY REQUIRMENTS Voltage, Vs Supply Drain, +15VDC (no load) -15VDC ±O.02 ±O.002 ±14.5, ±15 ±25 -40 %ofFSRI%Vs % of FSR/%Vs ±15.5 VDC mA mA +70 +85 +85 'c 'c TEMPERATURE RANGE· Specification Operating {derated speCS} 'Storage 0 -25 -55 'C NOTES: 1. Adding external CMOS hex buffers CD4009A will provide 15VDC CMO's input compatibility. The percent change in output (Vo) aslogicOvaries fromO.OVto+O.4Vand logic 1 changes from +2.4V to+5.OV onall inputs is less than 0.008% of FSR. 2. Adjustable to zero with external trim potentiometer. 3. FSR means Full Scale Range and is 20V fOr ±10V range and IOV for ±5V range. 4. The measurement of total harmonic distortion is highly dependent on the characteristics of the measurement circuit. A block diagram of a measurement circuit is shown in Figure 3. Burr-Brown calculates THO' from the measured linearity errors using equation (2) in the section on "Total Harmonic Distortion", and specifies that the maximum Tt:tD measured with the circuit shown· in Figure 3 will be less than the limits indicated. 5. LSB is for 14-bit resolution. 6. Measured with an active clamp, as shown in Figure 10, to provide a low impedance for approximately 200nsec. 7. Connect,pin 24 to pin 17 to obtain ±5V range. PIN ASSIGNMENTS CONNECTION DIAGRAM PCM51JG-1 Pin J::!2. +Vs 1 7 S 9 10 11 12 13 14 15 16 -Vs 17 18 19 20 21 22 23 24 Pin ~ Bit 1 (MSBI Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 BitS Bit9 Bltl0 Bitll Bit12 Bit 13 Bit 14 Bit15 Bit 16 (LSBI ±10V RANGE SELECT NO CONNECTION -15VDC COMMON lOUT NO CONNECTION +15VDC ±5V RANGE SELECT !:!2. PCM51JG-V 1 2 3 4 5 6 7 S 9 10 11 12 13 14 15 16 17 16 19 Bit 1 (MSBI Blt2 Bit3 Bit4 Bit5 Bit6 Bit7 BitS Bit9 Bit 10 Bit 11 Bit12 Bit 13 Bit14 BitlS Bit 16 (LSBI AUDIO OUT NO CONNECTION -15VDC COMMON SUMMING JUNCTION NO CONNECTION +15VDC ±5V RANGE SELECT 20 21 22 23 24 "Note: Leave Pin 24 open lo( ±10V Range. THEORY OF OPERATION The accuracy of a Df A converter is described by the transfer function shown in Figure I. The errors in the D f A converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Offset or Bipolar zero errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the minus full scale point (all bits Off), and Offset drift shifts the line left or right over the operating temperature range. Most of the offset and gain drift with tc;mperature or time is due to the drift of the internal reference zener diode. The converter is designed so that 0111...1111 h IOOO••.~ OFFSET ~"~I ~...11II11 .... ... :2 aa :::I ~ 'n~n" 0111...1110 AlLBITSON 1 BAIN ERROR, • . • \ -----ll-- r--- • these drifts are in opposite directions. This way the bipolar zero voltage is virtually unaffected by variations in the reference voltage. Total Harmonic Distortion (THD) is useful in audio applications and is a measure of the magnitude and distribution of the Linearity Error, Differential Linearity Error, and Noise, as well as Quantization Error. To be useful, THD should be specified for both high level and low level input signals. This error is unadjustable and is the most meaningful indicator of Df A converter accuracy for audio applications. The resolution of a Df A converter can be expressed in terms of Dynamic Range. The Dynamic Range is a measure ofthe ratio of the smallest signals the converter can produce to the full scale range and is usually expressed in decibels (dB). The theoretical dynamic range of a converter is approximately 6 x n, where n is the number of bits of resolution, or96dB for a 16-bit converter. The actual or useful dynamic range is limited by noise and linearity errors and is therefore somewhat less than the theoretical limit. DIGITAL INPUT CODES The PCM51 accepts complementary digital input codes in binary format. It may be connected by the user for TABLE I. Digital Input Codes. I\IPOLAR ZERO DIGITAL INPUT CODES '~~ I 1111..1110 • MSB LSB 1111...1111. .FSR / 2 I ANALOG OUTPUT I (+FSR / 21·llSB ·SEE TABLE I FOR DIGITAL CODE DEFINITIONS. FIGURE I. Input vs Output for an Ideal Bipolar Df A Converter. All bits ON Mid Scale All bits OFF J~. ! COB CTC· Complementary Complementary Offset Binary Two's Complement +Full Scale -ILSB 0111 ... 111 Zero -Full Scale 1111 ... 111 -Full Scale Zero 1000... 000 -ILSB -Full Scale "A TTL inverter must be connected between the MSB Input signal and bit 1 (pin 1) to obtain eTC input code. 6-291 either complementary offset binary (COB) or complementary two's complement (CTC) codes. See Table I. SETTLING TIME (PCMS1JG-V) Settling time is the total time (including slew time) required for the output to .settle within an error band around its final value after a change in input (see Figure DISCUSSION OF SPECIFICATIONS 2). Settling times are specified to ±0.OO6% of FSR; one for maximum full scale range changes of 20V and one for a I LSB change. The I LSB change is measured at the major carry (0111...11 to 1000 ... 00), the point at which the worst-case settling time occurs. SETTLING TIME (PCMS1-JG-I) Two settling times are specified to a ±0.006% of FSR. Each is given for current model connected with two different resistive loads: Ion to 200n and looon. Current-output model settling time is particularly important if the PCM5IJG-I is going to be used to build a successive-approximation AI D converter. See Figure II. The PCM51 is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for a DI A converter in audio applications are total harmonic distortion, differential linearity error, bipolar zero error, parameter shifts with time and temperature, and settling-time effects on accuracy. This DAC is factory-trimmed and tested for all critical key specifications. BIPOLAR ZERO ERROR Initial bipolar zero error (Bit I "ON" and all other bits "0 FF'') is factory-trimmed to typically ±20m V (± 100m V maximum) at +25°C. This error may be trimmed to zero by connecting the external trim potentiometer shown in Figure 6. . 1.0 0.3 i! DIFFERENTIAL LINEARITY ERI\OR Differential Linearity Error (DLE) is the deviation from an ideal I LS B change from one adjacent output state to the next. DLE is important in audio applications because excessive DLE at bipolar zero (at the "major carry'') can result in audible crossover distortion for low level output signals. Initial DLE on the PCM51 is factory-trimmed to typically±0.OO25% ofFSR (±0.006% of FSR, maximum). I ir ... !ia J=.5!. 0.1 0.13 1 ~IIIE .... t!-1iV HAlliE V~?D:L I:O~~ r\\ 11 I ODI HL=lkH O·DD3H~ HL = 2DDll 0.001 0.1 STABILITY WITH TIME AND TEMPERATURE The parameters of a DI A converter designed for audio applications should be stable over a relatively wide temperature range and over long periods oftime to a void undesirable periodic readjustment. The most important parameters are Bipolar Zero Error, Differential Linearity Error, and Total Harmonic Distortion. Most ofthe offset and gain drift with temperature or time is due to the drift of the internal reference zener diode. The PCM51 is designed so that these drifts are in opposite directions so that the bipolar zero voltage is virtually unaffected by variations in the reference voltage. Both DLE and THD are dependent upon the matching and tracking of resistor ratios and upon VBE and hFE of the current-source transistors. The PCM51 was designed so that any absolute shift in these components has virtually no effect on D LE or TH D. The resistors are made of identicallinks of ultra-stable nichrome thin-film. The current density in these resistors is very-low to further enhance their stability. \.'\.. l\. ~ ""I 10 100 Milia TIno'I...1 FIGURE 2. Full Scale Range Setthng Time vs Accuracy. TOTAL HARMONIC DISTORTION The Total Harmonic Distortion (THD) is defined as the ratio of the square root of the sum of the squares of the value of the rms harmonics to the value of the rms fundamental and is expressed in percent or dB. A block diagram of the test circuit used to measure the THD of the PCM51 is shown in Figure 3. A timing diagram for the control logic is shown in Figure 4. The digital input code stored in the PROM as well as the output obtained from an ideal PCM51, the value of an ideal sine wave, and the inherent quantization error are given in Tables III and IV. If we assume that the error due to the test circuit is negligible, then the rms value of the PCM51 error referred to the input can be shown to be Emu = POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The PCM51 power sup.ply sensitivity is specified for ±0.02% of FSR/% Vs, for -15VDC supplies and ±o.OO2% ofFSR/% Vs, for+ 15VDC supplies. Normally, regulated power supplies with 1% or less ripple are recommended for use with this DAC. See also Power Supply Connections paragraph in the Installation and Operating Instructions section. j II N ~ (I) [EL(i) + EQ(i)]' i= J where N is the number of squares, Edi) is the linearity error of the PCM51 at each sampling point, and EQ(i) is the quantization error at each sampling point. The THD can then be expressed as (2) jl I Nf:_[EL(i)+EQ(i)]' THD=E.m./E.m• :_ _~ic:=:.!.I_ _ _ _ _ _ _ _ x 100% Enn. This expression indicates that, in general, there is a correlation between the THD and the square root of the 6-292 880PII03 OR EQUIVALENT r---' ~O""'T"""" I + IIMPLIFIED8CH~ OF DElUTCHER 2X 741.8111 IINMY COUlTER 1831i1iOK OR EQUIVALENT AULOG SWITCH IMP7512 OR EQUIVALENT) *[ I LL...J zx 1l1li11 5pF ..... ~ ...... DEILITCHER CONTROL 2711 4X LATCH l'I!DII'r 74LB75 USE 400Hz HISH-PASS FILTER ANa 30kHz LOW·PASS FILTER. VOUT ...... ..... OUT IPCM51) ..... OISTOIITION METER HP 33IIA OR EQUIVALENT ..... LOW·PASS FILTER OEGLITCHER DEILITCHER CONTROL 0 _ _ _ _Pl"""'1 TI. . . CDIITD. UIIIC .2O~+-+-+---I+-I BEE CONTROL UIIIC TIMI161Fltllrt 4/. §:-4Ilt-+-+-+-tt-f 1-IOt-+-+-+-tt-f .ao~+-+-+--+t-l LOW.PASS FILTER CHARACTERllnc 'SEE TA8LE III AND TABLE IV. .100 1 101 102 103 I FREO.IHz) Ir/I FIGURE 3. Block Diagram of Distortion Test Circuit. B: LATCH EIlABLE !lL..__........InL..___~ C: DE8L1JCHERI:;"'~ _ _ _""'" CONTROL --! ,-2.5.... U tW FIGURE 4. Control Logic Timing for PCMSI Distortion Test Circuit. 10.0 4.0 1.0 0.4 r\.\ "2\ 0. I 0.D4 '0 14-8111 r\.'\ i" ~ 0.0 I ltall' 0.004 sum of the squares of the linearity errors at each digital word of interest. However, this expression does not mean that the worst-case linearity error of the D / A is directly correlated to the THD. For the PCMSI the test period was chosen to be 22.7!,sec (44.0S6kHz) which is compatible with the EIAJ STC-007 specification for PCM audio. The test frequency is 400Hz and the amplitude of the input signal is -ISdB down from full scale. Figure S shows the typical TH D as a function of output voltage. INSTALLATION AND OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS For optimum performance and noise rejection, power supplydecoupling capacitors should be added as shown in the Connection Diagram. These capacitors(l!'F tantalum or electrolyticiecommended) should be located close to the PCMS1. EXTERNAL BIPOLAR ZERO ADJUST (OPTIONAL) In some applications the bipolar zero error may re9uire adjustment. This error may be adjusted to zero by installing an external potentiometer as shown in Figure 6. ~ ~. 0.00 I .l1li ·50 IIdB aquall Full Selle RlngaIFSR) -4Il .au ·20 VOUT Id8) ! +v s l;.fi!'1P ~ ~H-----' 10 FIGURE S. Total Harmonic Distortion (THD) vs VOUT. . 10kn TO l00kll BIPOlAR ZERO ADJUST ,VS FIGURE 6. Optional External Bipolar Zero Adjust. 6-293 The TCR of the potentiometer should be 100ppmj"C or. less. The I.SMO resistor (20% carbon or better) should be . located. close to thePCMSI to' prevent noise pickup . . 'Refer to Figure 7 for the relationship ·of bipolar zero adjust on the D / A converter transfer function. AU BITS LOGIC 1 +V~......- - - . , r-~--+---------~ • COM /~~~R / // / / /~ RAN8E OF OFFSET ADJUS~ / / ~/// ':;::/ ; -v DIGITAL INPUT __ ±15VDC SUPPLY ZERO (MSB OHAND ALL OTHER BITS OFF) Ii FIGURE 8. Output Circuit for PCMSIJG-V. =1;1 ii! t _ -FULL SCALE ToFFSET ADJUST TRANSLATES THE UNE FIGURE 7. Affect of Offset Adjustment on a Bipolar D/A Converter Transfer Function. ADJUSTMENT PROCEDURE Apply the digital input code that should produce zero volts output (bit I or MSB ~ON" and all other bits "OFF''). Adjust the offset potentiomet~r until zera volts is obtained. Table II shows the ideal plus and minus full scale voltages and LSQ values for both 14- and l6-bit resolution and ±IOV, ±SV, and ±lmA output ranges .. TABLE II. Digital Input and Analog Output Relationships. The PCMSI and the wiring to its connectors should be located to provide optimum isolation from sources of RFI and EM!. The key word in elimination of RF radiation or pickUp is loop area; therefore, signal leads and their return conductors should be kept close together. This reduces the external magnetic field along with any radiation. Also, if a signal lead and its return conductor are wired close together they present a small flux-capture cross section for any external field. This reduces radiation pickUp in the circuit. See Figure 9forthe connection diagram ofa PCMSIJG-I ourrent-to-voltage converter. R, through R. represent lead and contact resistances. . . OUTPUT CODE VOLTAGE' ,.... ' ....811 'DlGITAL INPUT CODE IIeeoIuIIan R...._ Complementary Bipolar 0ffae1 Binary COB ±1OVor:t1mA OneLSB All Bits On 100..001 All Bitl Off 111..1,. ±5Vor:tlmA" OneLSB AIiBitlOn [00..001 AI,I Bitt Off 111 .. 111 +305,.V +1.22mV CURRENT , .... ......_ , ...... R""'- O.122,.A Q,031 ... A -o.la'1iftA +1.0000mA -a._mA +4.99839V 0.031,.1\ -o.99987mA 0.122,.1\ -o.99888mA -S.OOOOV +1.0000mA +~.OOOOmA +9._ +e.9987ev -10.0000v -10.0000v +152#'V +4.98848V -5.0000V +610l'V Tl.0000mA +vr-----, ~~--~-------------; COM 'Connect pin 24 to pin 17 to obtain tfJV RIIt9!. INSTALLATION CONSIDERATIONS If 16-bit resolution is not required, bit IS (pin IS) and bit 16 (pin 16) should be connected to +SVDC through a I kO resistor. Figure 8 shows the connection diagram for a. PCMS.1. Lead and contact resistances afe represented by ,R, through R3. As long as the load resistance (Rd is constant, R, simply introduces a gain error. R, is part of RL if the output voltage is sensed at Common (pin 20) and therefore introduces no error. If RL is variable, then R, should be less than RLmin/ 2'6 to reduce voltage drops due to wiring to less than ILSB. For example, ifRLmin is SkO, then R, should be less than 0.080. RL should be located as close as possible to the PCMSI for optimum performance. -v ±15VDC SUPPLY 'RS SHOULD BE EQUAL TO THE OUTPUT IMPEDANCE AT PIN 21 TO COMPENSATE FOR THE BIAS CURRENT ORIFT OF AI. USE STANOARO 10'10 114W CARBON COMPOSITION' OR EQUIVALENT RESISTORS. RS =3.3kll FIGURE 9. Preferred External Op Amp Configuration for PCMSIJG-I APPLICATIONS A single PCMSI can be used for both the left and right channel as shown in Figure 10. Note that a Sample/ Hold is not r~quired. 6-294 PCM5IJG·V An AI D converter can be constructed using the PCMSIJG-I shown in Figure II. ~310 +5V +15V't FIGURE 10. PCMSI Used for Stereo. 27kll ANALOG INPUT .~, ~V It II 2.IN914, , ~~:-;;.;Ir------------~ 24.:±liVRANGE:~7. 8 10 ~ 17·±IOVRANGE '\I' 6 1N9:~: ~ *I~~ 560:1;(" 5 ; ~ ",. f~~.I u.~ ",7' PCM5IJG·1 I 10 1112 13 415 16 12345678 ,+ 2kn 2k1l +15V' PMI MAT·ell ·15V ·15V I12lM311 3Akn 3.4kn 3 .,,. SPRAGUE TH7615 . "'f-I 2 4 r .~r,-1 RCA3019H ::I- ·15V 3.4k1l 22tn 3.4kn ·15V .' +15V +5V 16 BITS ----++-H-+++-t--H++-t-t-H I SWI BIT RESOLUnON SWI 74LSOO 14 1 i 141312 11 6 5 4 3 16 f.i18 • ANAlOG COM "DIGITAL COM AM2502 7 10 .I p?14 BITS AM2503 2l.!:!S[!1 7 10 I 2L 7 14ka I ~ 10 6 .-+-~~ 5 ~ " .--+----113 r--14 • 47pf r---15 r-16 .3 Yf-_.+5V ~ - - Itka STATUS ~---+-4-------+-~-----------~ 74LSI23 I l +5V +5V CONVERT COMMAND FIGURE II. AI D Converter Usmg PCMSIJG-1. 6-295 +5V 87- +5V ~ +5V 141312 11 6 5 4 3 v.:- r---""';'., Table III shows the hex code loaded into the PROM's of the Distortion Test Circuit, Figure 3, for 14-bitlvalues and Table IV shows the hex codefor 16-bit values, K'alues TABLE Ill. Hex Code for I4-Bit Values (-ISdB CODb I 2 3 "I'5 EO 7 B 9 18 11 12 13 14 J5 J6 17 J8 19 20 21 22 23 24 25, 26 27. 28 29 38 31, 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 "958 51 52" 53 54 55 HEX CODE 7F,FF 7EB3 7D67 7C1F 7AD7 7997 7857 7723 75F3 74CF 73AF 729F 7197 709B 6FAB 6ECB 6DF7 6D33 6C7F 6BDF 6B4B 6AC7 6A5B 69FB 69AF 6977 6953 693F 693F 6953 6977 69AF 69FB IDEALDAC OUT(VoItIl, IDEAL SINE VALUE (VoItIl &.,000000, 0.000000 .101318 .101~20 .202637 .282709 ~302734 ';303236 .402832 .402775 .~00488 .~00999 .~9814~ .~97:590 .692139 .692231 .784912 , .784614 .874823 ' .874439 .961914 .961410 1.044922 1.04~246 1. 12~488, 1.12~673 1.202393 1.202428 1.27~635 1.275261 1.343994 1.343934 1.408691 1.408223 1.468~06 1.467920 1.5234:38 ' 1.~22828 1. ~72266 1. ~72769 1. 617432 1. 617~80 1.6~7715 1.657115 1.698674 1. 691244 1.719971 1.719857 1. 743164 1.742861 1.7602~4 1. 760179 1. 771240 ,1.771756 1.777344' 1. 777~54 1.777344 1.777554 1. 771240 1.771756 1; 7602,54 1.760179 1.743164 1.742861 1.719971 1. 7198507 6A~B 1.690674 1;691244 6AC7 1. 6~7715 1.657115 6B4B 1.617432 1. 617588 6BDF 1.572266 1.572769 6C7F 1.523438 1;522828 6D33 1.468586 1.467928 6DF7 1.408691 1.408223 6ECB 1.343994 1.343934 6FAB 1.275635 1.275261 789B 1.282393 1.202428 7197 1.125488 1.125673 729F' 1.844922 1.045246 73AF .961914 .961418 74CF: .874823 .874439 .784912 .784614 75F3 7723 .692139 .692231 7857 .598145 .597598 7997 .588488 .508999 7AD7 .482832 .482775 7C1F :382734 .383236 7D67 .202637 .202789 7EB3 .181318 .101520 are fora 400Hz sirie wave (-ISdB of full scille); aU'values are in volts, ~utPut in 20V Full Scale Range), oUANTIZING ERAOR(V.... I e.,e00000 .000201 .000072 i.e00502 -'.eee057 :.ee0~1l j.eee~~5 .000092 ~.000298 .88841~ -.000504 .000325 .000~85 .00003~ ~.000374 ~.000060 ~.000468 ".008~86 ".080610 ; .000~03 1.,000148 "'.000680 : .088578 "'.e88113 -'.000303 -.eeee75 .e00516 .000210 .088210 .000516' -.000075 -.00038~ -.000113 .000570 -.000600 .008148 .000583 -.000610 -.000586 -.000468 -.000060 -.000374 .080835 .000185 .880325 -.888584 ' .088415 -.008298 .000892 l.008555 : .088511 .1..088857 .888582 .000072 .080281 CODe. 56 57 :S8 59 S0 61 62 63 64 65 66 67 68 69 1"0 1"1 ,'2 ;'3 ,'4 1"5 ,'6 ,'7 ,'8 ,'9 e:8 e: 1 E:2 E:3 e:4 e:5 E:6 e:7 e:8 E:9 ~10 ~Il ~12 ~'3 ~14 ~15 ~16 ~17 ~18 ~19 188 181 102 103 184 105 186 187 188 109 118, 6-296 HEX CODE 7FFF 810' 8297 83DF 8~27 8667 87A7 88DB 8A0B 8B2F 8C4F 8DSF 8E67 8F63 IDEALDAC OUT (VoItIl IDEAL SINE VALUE (VoItIl 0.eeee00 -.101318 -.202637 -.302734 -.402832' 0.000000 -.101~20 -.202709 -.303236 QUANTIZING ERAOR(VoItIl 0.000000 -.00e201 -.000e72 -.0ee~02 -.40277~ .00e0~7 -.~0e488 -.~0e999 -. 00e~11 -.598145 -.692139 -.784912 -.874823 -.961914 -1.044922 -.~97590 .000~55 -.692231 -.784614 -.874439 -.961410 -.000092 .000298 -.880415 .000504 -.000325 -1.12~488 -1.04~246 -.00018~ -1.202393 -1. 12~673 -1.282428 90~3 -1.27~635 -1.27~261 9133 9207 92CB 937F 941F 94B3 9537 95A3 9683 964F 9687 96AB 96BF 96BF 96AB 9687 964F 9,683 95A3 9537 94B3 941F 937F 9,2CB 9287 9133 9053 8F63 8E67 8D5F 8C4F 8B2F 8A8B 88DB 87A7 8667 8527 83DF ,8297 814B -1.343994 -1.408691 -1.343934 -1.408223 -1.467928 -1.522828 -1.572769 .080374 • 00e060 .800468 -1.468~06 -1.~23438 -1.~72266 -1.617432 -1.657715 -1.698674 -1.719971 -1.743164 -1.760254 -1.771248 -1.777344 -1.777344: -1.771240 -1.768254 -1.743164 -1. 719971 -1.698674 -1.617~80 -1. 657115 -1.691244 -1.719857 -1.742861 -1.760179 -1.771756 -1.777554 -1.777554 -1. 771756 -1.760179 -1. 742861 -1.719857 -1.691244 -1.6~7715 -1.657115 -1.617432 -1.!S17588 -1.572266 -1;572769 -1. 523438 -1.522828 -1.468506 .,.1.467928 -1.408691 -1.488223 -1.343994 -1.343934 -1.275635 -1. 275261 -1.282393 -1.282428 -1.125488 -1. 125673 -1.044922 -1.845246 -.961914 -.961410 -.874823 -.874439 -.784912 -.784614 -.692139 -.692231 -.598145 -.597598 -.580488-.588999 -.48283:? ' -.482775 -.302734 -.383236 -.282637 -.282789 -.181318 -.181520 -.0000~5 .8e0~86 .8e0610 -.000503 -.080148 .888688 -:-.880578 .800113 .808383 .000075 -.000516 -.808218 -.008218 -.000~16 .000075 .000383 .800113 .,..088570 .000680 -.888148 -.800503 .800610 .000586 .800468 .800060 .088374 -.888835 -.088185 -.888325 .000584 -.888415 .8'88298 -.808892 .888555 -.088511 .888857 -.080582 ':.088872 -.88828i CODE. 1 2 3 4 5 G 7 ,e 10 11 12 13 14 15 16 17 18 19 ;~e ~~ 1 ~:2 ;~3 ;:4 ~:5 ~:6 ~:7 ~:8 ;:9 ,:9 ,: 1 ::2 ::3 ,:4 ,:5 ,:6 ,:7 ,:8 ,:9 40 41 42 43 44 45 46 47 48 49 ~i0 ~i 1 ~i2 ~i3 ~14 ~i5 HEX CODE IDEALDAC OUT (VOttsl 7FFF o.oooeoo 7EB2 .101624 7D67 .292637 7CID .303345 7AD7 .492832 7995 .501099 7859 .597534 7723 .692139 75F4 .784607 74CE .874329 73Bl .961304 1.045227 729E 7196 1.125793 709B 1.202393 6FAC 1.275330 6ECB 1.343994 6DF9 1.498981 6D35 1.467896 6C81 1.522827 6BDD 1.572876 6B4B 1.617432 6AC9 1.657194 6A59 1.691284 69FB 1.719971 69BO 1.742859 6977 1.769254 6951 1.771851 693E 1.777649 693E 1.777649 6951 1.771851 6977 . 1.7692'54 69BO 1.742859 69FB 1.719971 6A59 1.691284 6AC9 1.657194 6B4B 1.617432 6BDD 1.572876 6C81 1.522827 6D35 1.467896 6DF9 1.408081 6ECB 1.343994 6FAC 1.275330 709B 1.202393 7196 1.125793 729E 1.045227 73Bl .9.61304 74CE .874329 75F4 .784607 7723 .692139 7859 .597534 7995 .501099 7AD7 .402832 7CID .303345 7D67 .202637 7EB2 .101624 IDEAL SINE VALUE (Volts) o.ooeooo .101529 .292709 .303236 .492775 .509999 .597590 .692231 .784614 .874439 .961410 1.045246 1.125673 1.202428 1.275261 1.343934 1.498223 1.467920 1.522828 1.572769 1. 617589 1.657115 1. 691244 1.719857 1.742861 1.769179 1.771756 1.777554 1.777554 1.771756 1.769179 1.742861 1.719857 1.691244 1.657115 1.617580 1.572769 1.522828 1.467929 1.408223 1.343934 1.275261 1.292428 1.125673 1.045246 .961410 .874439 .784614 .692231 .597590 .500999 .402775 .303236 .202709 .101520 QUANTIZING ERROR (Voila, e.000090 -.90eI94 .909972 -.909199 -.909957 -.909099 .090056 '.899092 .099097 .900110 .999197 .090019 -.000120 .000035 -.000069 -.000969 .990142 .909924 .999991 -.999197 .990148 .999919 -.€l99949 -.090113 .990992 -.999075 -.990994 -.990995 -.990995 -.990994 -.999075 .999992 -.099113 -.990949 .999910 .000148 -.000107 .000001 .999924 .000142 -.990060 -.000969 .900935 -.000120 .990919 .090107 .900119 .000007 .000092 .000056 -.900999 -.000057 -.000109 .oooon -.000104 COD..~i6 ~i7 ~i8 ~i9 E:O E: 1 E:2 E:3 E:4 E:5 66 E:7 E:8 E:9 ('0 ,'I ,'2 ('3 ('4 ,'5 ,'6 i'7 ;'8 ('9 E:O E: 1 E:2 ~:3 E:4 ~:5 E:6 ~:7 E:8 89 ~10 ~Il 0: 12 :13 ~14 ~15 :16 ":17 :18 :19 100 101 J02 103 104 105 106 107 108 109 110 6-297 HEX CODE IDEALDAC OUT (Volta, 7FFF 814C 8297 83E1 8527 8669 87A5 88DB 8A0A 8B30 8C4D 8D69 8E68 8F63 9052 9133 9295 92C9 937D 9421 94B3 9535 95A5 9693 964E 9687 96AD 96CO 96C9 96AD 9687 964E 9603 95A5 9535 94B3 9421 937D 92C9 9205 9133 9052 8F63 8E68 8D60 8C4D 8B30 8AOA 88DB 87A5 8669 8527 83El 8297 814C 0.000900 -.191624 -.202637 -.303345 -.492832 -.591099 -.597534 -.692139 -.784607 -.874329 -.961304 -1.045227 -1.125793 -1.292393 -1.275330 -1.343994 -1. 408981 -1.467896 -1.522827 -1.572876 -1.617432 -1. 657104 -1.691284 -1.719971 -1.742859 -1.760254 -1. 771851 -1.777649 -1.777649 -1. 771851 -1.760254 -1.742859 -1.719971 -1. 691284 -1.657104 -1.617432 -1.572876 -1.522827 -1.467896 -1.408081 -1.343994 -1.275330 -1.202393 -1;125793 -1.045227 -.961304 -.874329 -.784607 -.692139 -.597534 -.501099 -.402832 -.303345 -.202637 -.101624 IDEAL SINE VALUE (Volta, 9.009900 -.191520 -.292709 -.303236 -.492775 -.509999 -.597590 -.692231 -.784614 -.874439 -.961410 -1.045246 -1. 125673 -1.202428 -1. 275261 -1.343934 -1.408223 -1.467920 -1.522828 -1.572769 -1.617580 -1.657115 -1.691244 -1. 719857 -1.742861 -1.760179 -1.771756 -1.777554 -1.777554 -1.771756 -1.7691 79 -1.742861 -1.719857 -1.691244 -1.6571 f5 -1.617580 -1.572769 -1.5228'?8 -1.467920 -1.408223 -1.343934 -1.275261 -1.202428 -1.125673 -1.045246 -.961410 -.874439 -.784614 -.692231 -.597590 -.500999 -.402775 -.303236 -.202709 -.101520 QUANTIZING ERROR (Volta, 0.900000 .000104 -.000072 .000199 • 90005i' .000099 -.000056 -.900992 -.000907 -.900110 -.990107 -.000019 .000120 -.00003'5 .000069 .000060 -.000142 -.000024 -.000001 .900107 -.000148 -.090010 .090940 .000113 -.000002 .090975 .000094 .009095 .000095 .900994 .000075 -.000002 .090113 .000040 -.000010 -.000148 .000107 -.000001 -.000924 -.000142 .000060 .000069 -.000035 .000120 -.000019 -.000107 -.000110 -.000007 -.000092 -.000056 .000099 .000057 .000109 -.oooon .000104 BURR-BROWN8 IElElI PCM75 DESIGNED FOR AUDIO ADVANCE INFORMATION Subject to Change 16-Bit Hybrid ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • 16-BIT RESOLUTION The PCM75 is designed for PCM Audio applications and is compatible with EIAJ STC-007 specifications . The internal l6-bit digital-to-analog converter is available for the de~igner to utilize in the playback mode. thus saving the cost of an additional DAC. The conversion time can be reduced from l5~sec to 8~sec with some increase in distortion. Distortion is specified on the data sheet to assure performance in critical audio applications. The PCM75 is a low cost. high quality. l6-bit successive approximation analog-to-digital converter. The PCM75 uses state-of-the-art IC and lasertrimmed thin-film components and is packaged in a bottom-brazed ceramic 32-pin dual-in-line package. The converter is complete with internal reference and clock. • 90dB DYNAMIC RANGE .0.004% THO (FS Input, 16 Bits) .0.02% MAX THO (-l5dB, 16 Bill) .17~Iec • MAX CONVERSION TIME (16 Bits) 15~secMAX CONVERSION TIME (14 Bits) • 8~ec CONVERSION (Reduced Specs) • EIAJ STC-007-COMPATIBLE • INTERNAL 16-BIT OAC AVAILABLE TO USER ..----d~SHORT CYCLE CONVERT COMMAND PARALLEL DIGITAL OUTPUT } AUDIO INPUT a RANGE SELECT 1---...-l----oCOMPARATOR IN Ir ;;;;==~~--='!:!:.~:g BIPOLAR OFFSET Sf RIAL OUT CLOCK 1 - - - - - - - 0 CLOCK OUT ' - - - - - - - - - - 0 CLOCK RATE ' - - - - - - - - - - - - - 0 STATUS Internatlollli Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. (802) 746·1111 . Twx: 911).952·1111 • Cable: BBRCORP . Telex: 66·6491 PDS-44 I 6-298 SPECIFICATIONS ELECTRICAL At 25°C and rated power supplies unless otherwise noted MODEL PCM75KG MIN PCM75JG TYP MAX MIN TYP 16 RESOLUTION DYNAMIC RANGE{I) 90 MAX UNITS 16 Bits 90 dB INPUT I ANALOG Voltage Ranges, Bipolar Impedance IDirect Input) to +5V, ±2.5V to +IOV, ±5V o to +20V, ±10V I I I ±2.5, ±5, ±10 ±2.5, ±5, ±10 V 2.5 5 10 2.5 5 10 kO kO kO o o DIGITAL(2) Convert Command Positive pulse SOnsec wide I min I trailing edge 1"1" to "0" initiates conversion I Logic Loading I I 1 I I I 1 TTL Load TRANSFER CHARACTERISTICS ACCURACY Gain Error Offset Error, Bipolar ±O.1(3) ±O.H3) Differential Linearity Error I major carry' Inherent Quantization Error ±O.0015 ±O.1(3) ±O.1131 ±O.OO3 ±1/2 ±1/2 % % of FSR{O) %01 FSR LSB 0.006 0.004 0.006 0.006 % % TOTAL HARMONIC DISTORTION (THD)(1) VIN = ±FS at 1 = 400Hz 14-Bit Resolution 16-Bit Resolution Y,N = -15dB at 1=400Hz 14-Blt Resolution 16-Blt Resolution 0.025 0.015 POWER SUPPLY SENSITIVITY ±15VDC +5VDC 0.003 0.001 0.05 0.03 0.021 0.02 0.003 0.001 CONVERSION TIME!S) 114 Bits) 116 Bits) % % %oIFSR/%Vs % 01 FSRI%Vs 15 15 17 #£seG ~sec WARM-UP TIME min DRIFT Gain ±20 ±15 Offset, Bipolar ±20 ±15 ppml"C ppm 01 FSRI"C OUTPUT DIGITAL IAII codes complementary} Parallel Output Codes(6) Bipolar Output Drive Serial Data Code INRZ} Output Drive Status Status Output Drive Internal Clock Clock Output Drive FrequencylB) I COB,CTC(7) I I I I I I I COB,CTC(7) CSB,COB I I I TTL Loads I TTL Loads CSB,COB : Logic"II" during con vlerslon TTL Loads TTL Loads kHz 933 POWER SUPPLY REQUIREMENTS Power Consumption Rated Voltage, Analog Rated Voltage, Digital Supply Drain +15VDC Supply Drain -15VDC Supply Drain +5VDC ±14.5 +4.75 1.55 ±15 +5 ±15.5 +5.25 ±14.5 +4.75 +45 -35 +70 1.55 ±15 +5 +45 W ±15.5 ~.25 -35 +70 TEMPERATURE RANGE Specification Operating Iderated specs} Storage o -25 -55 +70 +85 +100 6-299 o -25 -55 +70 +85 +1.00 VDC VDC mA mA mA NOTES: 1. The measurement of total harmonic distortion (THO) and Dynamic Range is highly dependent on the characteri'sties of the sample/hold amplifier, the dlgital-to-analog converter. the deglitcher, and the low-pass filter. To accurately measure THO and Dynamic R~nge. the accuracy of e,~c~·d~vice. should be better than l6-bit accuracy. A block diagram showing the measurement technique 8u,rr-Brown uses i~ shown in Figure 4. 2. DTLITTL compatible. i.e .. Logie "0" =O.BV max. Logie "I" =2.0V min for inputs. For digital outputs Logic "0" = +O.4V max. Logic "I" = 2.4V min. 3. Adjustabl.e to zero. 1See "Oplional External Gain and Offsel Adjuslment."1 ' 4. FSR means. Full Scale Range. For example. unit connecled for ±10V range has 20V FSR. 5. Conversion time may be shortened with '~Short Cycle" set for lower resolution and with use of Clock Rate Control. See "Additional Optional. Connections" section. The Clock Rate Control (pin 2~) should .be.connected to Digital Common for specified max conversion time. Short Cycle I pin 321.~hould be left open for 16~bit resolution or connected to the n + 1 digital output for n~bit resolution. For example, connect Short Cycle to bit 15 (pi!) 151 fqr 14~bit resolution. 6. See Table I. CSB - Complemenlary Slraighl Binary. COB - Complementary Offsel Binary. CTC - Complementary Two's Complement. 7. CTC coding oblained by inverting MSB 1pin 11. 8. Adjustable wilh Clock Rate Control from approximately 933kHz to 1.4MHz. See Figures 12 and 13 and Table III. MECHANICAL Pin numbers:' shown for reference only. Numbers may not be marked on package. . OJ -f= CASE: Ceramic MATING CONNECTOR: 2302MC WEIGHT: 13 grams 10.460z.1 HERMETICITY: Conforms 10 melhod 1014 condition C step 1 (fluorocarbon) 01 MIL-STD-B83 1gross leak I. I1 J DIM I--- l-------1 INCHES M1LL1METERS MIN MAX MIN MAX A 1.678 1.7.12 42:62 "43.48 B C 1.079 1.101 27.41 'Z7.97 .180 .~10 4.57 5.33 0 .... .020 .4' .51 .055 1.14 '.40 F G .016 .100BASIC 2.54 BASIC T H -.089 - .'06 .009 .012 .23 2." .30 K .200 .4!10 5.~ '.33 L .900 BASIC N •015 .,. ... 2.26 22.86 BASIC .035 LEADS IN TRUE POSITION WITHIN .010 1.25 MMJ R @I Mllt'C AT SEATING PLANE CONNECTION DIAGRAM TOP VIEW IMSBIBitl Bit2 Bit3 (i' ~ >;< 'Bit4 ~ BitS >s< Bit6 ~ (1Bil8 (i< Bit9 ~ Bill0 (fi Bit7 ~ Bit 12 ~ ILSB for 13 bits) Bil13 ~ (LSB for 14 bits) Bil14 ~ Billl Bil15 Bil16 '32 SHORT CYCLE ~. +SVDC SUPPLY ~ Reference :raJ GAIN ADJUST ~ II ~ ,IL "c"> 6.3kO 0 (J J, JI affi rill Iffi U 16-BiISAR Comparator irs ~ "" *If an external clock oJ, :i '" ... 5kOl5kO >fa) +15VDC SUPPLY ~ COMPARATOR IN ~) BIPOLAR OFFSET ~ 10V} AUDIO INPUT &: RANGE SELECT ~) 20V ~ ~ ~ ~ ~ ~ CLOCK RATE CONTROL AUDIO COMMON -15VDC SUPPLY CLOCK OUT DIGITAL COMMON STATUS ~ SERIAL OUT Clock IS CONVERT COMMAND' "'" used, connect the cloCk to pm 31 (Convert Commandl. THEORY OF OPERATION The accuracy of a successive-approximation AI D converter is described by the transfer function shown in Figure I. All successive-approximation AI D converters have an inherent Quantization Error ±1/2LSB. The remaining errors in the Ai D converters are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including Gain, Offset, Linearity, Differential Linearity, and Power Supply Sensitivity. Initial Gain and Offset errors may be adjusted to zero. Gain drift over temperature rotates the line (Figure I) about the zero or minus full scale point (all bits Off), and Offset drift shifts the line left or right over the operating temperature range. Total Harmonic Distortion (TH D) is a measure of the magnitude and .. distribution ofthe Linearity Error, Differential Linearity Erro,r, and Noise, as well as Quantization Error, that is useful in Audio Applications. To be useful, THD should be specified for both high level and low level input 6-300 signals. This error is unadjustable and is the most meaningful indicator of AI D converter accuracy for Audio Applications. The resolution of an AI D converter can be expressed in terms of Dynamic Range. The Dynamic Range is a measure of the ratio of the smallest signals the converter can resolve to the full scale range and is usually expressed in decibels (dB). The theoretical dynamic range of a converter is approximately 6 x n, where n is the number of bits of resolution, or 96dB for a 16-bit converter. The actual or useful dynamic range is limited by noise and linearity errors and is therefore somewhat less than the theoretical limit. TIMING CONSIDERATIONS The timing diagram in Figure 2 assumes an analog input such that the positive true digital word 1001 1000 1001 0110 exits. The output will be complementary as shown in Figure 2 (0110 011101 io 1001 is the digital output). DEFINITION OF DIGITAL CODES Parallel Data Two binary codes are available on the PCM75 parallel output; they are complementary (logic "0" is true) straight binary (CSB) for unipolar input signal ranges and complementary offset binary (COB) for bipolar input signal ranges. Complementary two's complement (CTC) may be obtained by inverting MSB (pinl). Table I shows the LSB, transition values, and code definitions for each possible analog input signal range for 14-, 15-, and 16-bit resolutions. Figure 3 shows the connections for 14-bit resolution, parallel data output, with ±5V input. 0000 ... 0000 0000 ... 0001 ..... w 0111 ... 1101 co co 0111 ... 1110 co ~ .... = ........ = co .... 0111 ... 1111 I 1000 ... 0000 Serial Data Two straight binary (complementary) codes are available on the serial output line; they are CSB and COB. The serial data is available only during conversion and appears with the MSB occurring first. The serial data is synchronous with the internal clock as shown in the timing diagram of Figure 2. The LSB and transition values shown in Table I also apply to the serial data output except for the CTC code. I 1000 ... 0001 ;!: ;;; 1111 ... 1110 I I I 1111 ... 1111 E'n ON : is ·FSR A/lAL08 INrUT EINOFF 'See 'Table I lor dlgltll code dennallons. T +FSR .1 LSB 2 FIGURE I. Input vs Output for an Ideal Bipolar AI D Converter. I~ BIT 8 BIT1 BIT8 BITO BITIO BITII BIT 12 BITl3 BIT 14 BITl5 BIT 16 ::::::J L..J"I" =::J:;"~------'LJ"'I" ===J L..J"I" =::-] 1"0" ----TJ______________________LJ"'" ~ =::J y::~: r- ::::J] -,-----------===IIr.;r.;=====~-L...j .. , .. ~~=Jj~------------------------~I=.V=M.r_--__J~ ::::J~-----------~=__~::;_LsB~~ :;.. I 1"0" MSB ! 13) ----~~ 4 ! 5 I U 17 i 8 SERIAL OATA OUT I ·v· "I'" "I" "0" "0" "'" "I" "I" "0" OPTIONAL _J - - - --- ---, .--, j""-'I_,j - 'i1-'.---,1..1r--.,--, r-'1-11--'LIr-,I_Ir-,U r--,..)'-' r--Em.IAl CLOCK L! U U '-I 1-1 1-' '_I '-' ,_, I 1-1 II NOTES: 200naec. MAX --' I.- I. lbe convert command musl be at leul50111C wide and mull remain low during I CIIIIVIInIOtl. The convenlon II Inlilalld by lhe '1railing edge" 011111 convert command. 2. 17l'1ec lor 16 bits. a 1II1tnillng (hIgh II lawlldga aI clack II Itrollllerill output. c--. 1--' FIGURE 2. Timing Diagram. 6-301 i DoTTED liNES ARE: EXTERNAL : CONNECTlIiIIs. ~----~~------------~----------------~---<+5WC I I I }-~;-::--+-----1'-:G::A"'IN"-+----~--------------< I I I ADJUST I (optlonall I I : ~~~~~~~~~~tO~~~SE~T·~ PCM75 +15VDC 1000llio lOOkll ADJUST I I I (Optlonlll I I I H-____________-t______+ I ____+---::-::-:t--:LAUDIOCOMMON J-t-----------......__- - t - - - 4 - - -I.::.• .:...F4----.::----<-15VDC I I I I I I __ oJI - L_ _ _ _ _- - - ' 17 NC DIGITAL COMMON 'Capacltor should be connecl8d lYetll! external gain adlustls not used. FIGURE 3. PCM75 Connections For: ±5V Au'dio Input. 14-Bit Resolution (Short-Cycled). Parallel Data Output. TABLE I. Input Voltages, Transition Values, LSB Values, and Code Definitions. Binary r BIN I Output Audio Input Voltage Range Code Designation One least Significant BitllSBr INPUT VOLTAGE RANGE AND LSB VALUES Defined As: ±10V FSR COBil) orCTC(2) 20V n = 16 n = 15 n = 14 305.V 61.0"V 1.22mV 2" ±5V COBll) orCTC(2). 10V 2" 2" 153"V 305"V 610"V ±2.5V oto +10V Oto +5V Oto+20V COBll) orCTC(2) 5V CSB(3) 10V CSB(3) 5V 2" CSBl3) 20V 2n 153"V 305"V 6.0"V 77p.V . 153"V 305"V 305"V 610"V 1.22mV 2" 77"V 153"V 305~V 2" Transition Values MSB lSB 000 ...000(4) 011 ... 111 111 ... 110 +Full Scale +1OV -3/2lSB +5V-3/2lSB +2.5V -3/2lSB +10V -3/2lSB +5V -3/2lSB +5V +2.5V Mid Scale 0 0 0 0+1/2lSB -Full Scale -10V +1/2LSB -5V +1/2LSB -2.5V +1/2lSB 0+1/2lSB .. (1) COB = Complementary Offset Binary (2) CTC = Complementary Two's Complement - obtained by inverting the most significant bit. MSB (pin 11. +20V -3/2lSB +10V o +1/2lSB (3) CSB = Complementary Straight Binary Volta,gas given are t~e nominal value for transition to the code specified. (4) DISCUSSION OF SPECIFICATIONS The PCM75 is specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for an AI D converter in audio applications are total harmonic distortion, drift, gain and offset errors, and conversion time effects on accuracy. The ADC is factoTy~trimmed and tested for all critical key specifications. . GAIN AND OFFSET ERROR I nitial Gain and Offset errors are factory trimmed to typically ±o.l % of FSR (typically ±O.05% for unipolar offset) at 25°C. These errors may be trimmed to zero by connecting external trim potentiometers as ·shown in Figures 10 and II. POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The PCM75 power supply sensitivity is specified for ±O.003% of FSR/%V, for ±15VDC supplies and ±O.OOI5% of FSR/%V, for+5VDC supplies. Normally, regulated power supplies with 1% or less ripple are recommended for use with this ADC. See Layout Precautions, Power Supply Decoupling, and Figure 7. TOTAL HARMONIC DISTORTION The Total Harmonic Distortion (THD) is defined as the ratio of the square root of the sum of the squares of the value of the rms harmonics to the value of the rms fundamental and is expressed in percent or dB. A block diagram of the test circuit used to measure the THD of the PCM75 is shown in Figure 4 along with a timing diagram for the control logic. Ifwe assume that the error due to the test circuit is negligible, then the rms value of 6-302 II oPA 1113 AIALOG OR EQUIVALENT SWITCH r----lilltll IB 3550K OR EQUIVALENT HP 339A OR EQUIVALENT -lV--r'''''-o--!-''I'h-_,;:;{;~"",VOUT Ll--r"DE8L1TCHER~5PF - '-< CONTROL - ~MPl.IFIED SCHEMATIC OF DEBLITCHER LOW·PASS FILTER CHARACTERISTICS ----------.., I CONVERT COMMAND I I I I I DAC73KOR EQUIVALEIT ·20 -40 :-&0 I i-a0 DEGLITCHER CONTROL I SEE SIH SCHEMATIC IFI8URE 51 ~"j ·100 SEE CONTROL LOGIC TIMINS IFIGURE 81 ·120 I " 101 102 103 104 FREQUEICY IHzl 105 FIGURE 4. Block Diagram of Distortion Test Circuit. the PCM75 error referred to the input can be shown to be Erm~ = ..L N ~.!. j=1 [EI.(i) + Eo(i)f sion time of the PCM75 from 15}.1sec to 8}.1sec increases the distortion level due to dynamic linearity errors resulting from insufficient settling time for the internal 01 A converter and comparator. where N is the number of samples, Edi) is the linearity error of the PCM75 at each sampling point, and Eo(i) is the quantization error at each sampling point. The TH D can then be expressed as .!. THD = E ~ Erms ~ N j": I SIH CONTROL _.JWIr---I [Edi) + Eo(i)]' = ..:!...---'--'---;r;-----X 100% Erms This expression indicates ihat there is a correlation between the TH D and the sq uare root of the sum of the squares of the linearity errors at each digital word of interest. However, this expression does not mean that the worst-case linearity error of the AI D is directly correlated to the THD because the digital output words from the AI D vary according to the amplitude and frequency of the sine wave input as well as the sampling frequency. For the PCM75 the test sampling period was chosen to be 22.7}.1sec which is compatible with the EIAJ STC:-007 specification for PCM audio. The test frequency is 400Hz and the amplitude of the input signal is OdB (full scale) and -15dB. +15VOC-~'---t Ukn ·15VDC ·CAPACITORS WITH HI8H INSULATION REIISTANCE Ala LOW DIELECTRIC A880RPTIOISUCH AS TEFLON. POLYSTYRENE. OR POLYfROPYLENE SHOULD BE USED. FIGURE 5. Schematic of Sample I Hold Amplifier. 22.8983I'18C h r-, A: S/H CONTROL ---.J L.....J L.....J L - B: COlVERT COMMAla --.lL-...JL-...JL-- C: D: IFOR REFERENCE) LATCHEIAILE ~ DESUTCHER - : - - 5OOII111C CONTROL --..: ~2.5~11C -U-I,.uc _ _ STATUSOFAIIC~ ACCURACY VS CONVERSION TIME Figures I4and 15 show the relationship of THO vs input voltage level for the PCM75 with both l4-bit and l6-bit resolution and conversion times of 8}.1sec and l5}.1sec. Notice that the distortion level is reduced by increasing the resolution from 14 to 16 bits due to the reduced quantization error. Conversely, decreasing the conver- -- 5~I.C~ --v-u---u----u FS=44.IIIiIkHz~ IFOR REFEREICEI FIGURE 6. Control Logic Timing for PCM75 Distortion Test Circuit. 6-303 LAYOUT AND OPERATING INSTRUCTIONS LAYOUT PRECAUTIONS Analog and Digital Common are not connected internally in the PCM75 but should be connected together as close to the unit as possible, preferably to a large plane under the AOC. If these grounds must be run separately, use wide conductor pattern and a 0.0 I~F toO.I~F nonpolarized bypass capacitor between analog and digital commons at the unit. Low impedance analog and digital common returns are essential for low noise performance. Coupling between analog inputs and digital lines should be minimized by careful layout. The comparator input (pin 27) is extremely sensitive to noise. Any connection to this point should be as short as possible and shielded by Analog Common or ±15VOC supply patterns. POWER SUPPLY DECOUPLING The power supplies should be bypassed with tantalum or electrolytic type capacitors as shown in Figure 7 to obtain noise free operation. T~ese capacitors should be located close to the AOC. Bypass the I~F electrolytic type capacitors with O.OI~Fceramic capacitors for improved high frequency performance. ! COMPo IN 27J-:-:-----......-----+--t 8.31U1 26 ~ ~m:: VREF FIGURE 8. PCM75 Input Scaling Circuit. INPUT IMPEDANCE The input signal to the PCM75 should c'Ome from a low impedance source, such as the output of an op amp, to avoid any errors due to the relatively low input impedance of the PCM75. If this impedance is not low, a buffer amplifier should be added between the input signal and the direct input to the PCM75 as shown in Figure 9. ~l +5VDC.. . 1 r .. - 1pF DIGITAL CDMMON 1 • ® +. r.ol\. +'CI 22 . @ IPF + LM310 AUDIO INPUT DR EQUIVALENT SISNAL ·15VDC TABLE II. PCM75 Input Scaling Connections. ±10V ±5V ±2.5V Oto+5V Oto+10V Oto+20V COBo,CTC' COBo,CTC' COBo,CTC' CSB CSB CSB loPin Connect Pih 24 To Connect Input Signal To Pin 27 27 27 22 22 22 InputSig, Open Pin27 Pin27 Open Input Sig. 24 25 25 25 25 24 Connect Pin 26 PCM75 --- FIGURE 9. Buffer Amplifier for PCM75 Input. OPTIONAL EXTERNAL GAIN AND OFFSET ADJUSTMENTS INPUT SCALING The analog input should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the AID converter. Connect the input signal as shown in Table II. See Figure 8 for circuit details. Output Code '@}r- 5kn .+15VDC FIGURE 7. Recommended Power Supply Oecoupling. Input Signal Range ,, --- 5kn AUDIO COMMON I'pF @+ , /.@ Gain and Offset errors may be trimmed to zero using external gain and offset trim potentiometers connected to the AOC as shown in Figures 10 and II. M ultiturn potentiometers with 100ppmj"C or better TCR;s are recommended for minimum drift over temperature and time. These pots may be any value from IOkO to 100kO. All resistors should be 20% carbon or better. Pin 29 (Gain Adjust) and pin 27 (Offset Adjust) may be left open if no external adjustment is required. ADJUSTMENT PROCEDURE OFFSET - Connect the Offset potentiometer (make sure Rl is as close to pin 27 as possible) as shown in Figure 10. Sweep the input through the end point transition voltage that should cause an output transition to all bits off (Eor:)· Adjust the Offset potentiometer until the actual end point transition voltage occurs at EOt:. The ideal transition voltage values of the input are given in Table I. 'Obtalned by inverting MSB (Pin 1). 6-304 Table III. the Clock Rate pin may be connected to an external multiturn trim potentiometer with a TCR of ± 100ppmj"C or less as shown in Figure 12. The typical conversion time vs the Clock Rate Control voltage is shown in Figure 13. The effect of varying the conversion time and the resolution on the total harmonic distortion is shown in Figures 14 and 15. /., @~~I;y~",!~l ~! +::~~IO I~n _ _.... COMPo IN OFFSET ADJUST ·15VDC . i +15VDC .. 1 10knID IIDn •OFFSET ADJUST ·'15VDC +15VDC CLOCK RATECONTRGL@--- 5kn CLOCK FREOUENCY ADJUST FIGURE 10. Two Methods of Connecting Optional Offset Adjust With a 0.4% of FSR Range of Adjustment. -=FIGURE 12. Clock Rate Control, Optional Fine Adjust. GAIN - Connect the Gain adjust potentiometer as shown in Figure II. Sweep the input through the end point transition voltage that should cause an output transition to all bits on (E~:,). Adjust the Gain potentiometer until the actual end point transition voltage occurs ,at E~~. Table I details the transition voltage levels required. I I... ! ..I ~ 8 TYPICAL 20 5~t£1e'.a1T OPERATION OL~4-8IT~ OPERATIOII 5 +15VOC GAIN ADJUST @ 510kn 1 -. AUDIO COMMOII~ o.Ol~F • t lOknlD IOOkn GAIN ADJUST :15VOC o I I 4 10 12 CONTROL VOLTAlE l1li PIN 23 14 15 FIGURE 13, Conversion Time vs Clock Rate Control Voltage. FIGURE II. Connecting Optional Gain Adjust With a 0.6% Range of Adjustment. l~~~~~~~~~IN~P~UT~L~EVEL~ ·fi ~ ~ ~ ~ LSB AOC CLOSE CLOSE 53 CLOSE OPEN 55 C OSE 56 0 PEN 57 0 PEN BUFFER CONTROL 01 SABLE >ii ~ ~ +15VDC ~ S6 ~ Sz~ ~ ~ ;r,>- ? ADC I.PUT I±5VDCI DIGITAL CIIMMDN AUDIO COMMON ~ ~ ~17 - S4 ~ ~ • +5VDC s1 • 27 PCM75 CONVERT COMMAND -" ~~ OAC OPEN OPEN OPEN CLOSE OPEN CLOSE CLOSE ENABLE - S7 j2.7knj :&S3 -,h ~ LF356 J Is FIGURE 19. PCM75 Used Both as an A/ D Converter and as a D/ A Converter. 6-307 DAC OUTPUT I±5VDCI STATUS OUTPUT ·15VDC BURR-BROWN@> SDM853 , IElEtI ' DATA ACQUISITION SYSTEM FEATURES • SAVES DESIGN TIME '. RELIABLE - 168-hour bake • LOW LEVEL DR HIGH LEVEL INPUTS • SAVES SPACE • FLEXIBLE - Up to lour modes 01 operation • LOW COST DESCRIPTION The SDM853 is a complete 8- or l6-challnel data acquisition system in a compact 4.6" x 3.0" x 0.375" metal case. This system differs from most in that it can acquire and digitize low level or high level analog signals. A built-in high quality instrumentation amplifier allows input signal ranges of ±IOmV to ±IOV. This means that the SDM853 can be connected to low level sensors such as thermocouples and strain gauges without external signal conditioning. This expandable module accepts either 16 singleended or 8 differential inputs and converts the multiplexed data signals into 12-bit digial words with an accuracy of ±0.025% at throughput rates of up to 33,000 samples per second. Internallonal'Alrport Industrial Park - P.O. Box 11400 - Tucson. Arizona 85734 - Tel. (6021746-1111 - Twx: 910-952-1111 • Cable: 88RCORP - Telex: 66-6491 PDS-354A 6-308 DISCUSSION OF PERFORMANCE The SDM853 is a complete modular "off the shelf' data acquisition system. With this system it is possible to configure complete data acquisition systems in one-fourth the space for a fraction of the cost previous~I' possible. These systems contain all the components necessary to multiplex and convert ±lOmV to ±10V analog data into equivalent digital outputs yielding resolutions of 204p. V 10 204m V. The minimum throughput sampling rates are up to 30 kHzfor 12 bit and up to 43 kHz/or 8 hit resolution. The model SDM853 contains an analog multiplexer which can be connected in a 16 channel single ended or 8 channel differential mode, instrumentation amplifier, sample/hold, 12 bit successive approximation A/ D converter and programming logic. The amplifier and sample/hold are not internal~v interconnected. This allows maximum application flexibility. These systems can be expanded without limit using Burr-Brown's M PC-16S and M PC-8D monolithic multiplexers. Figure I shows the components of the SDM853. The system is designed 10 be mounted on a printed circuit card. The on(v requirement for system operation are input signals, power and the interconnection of the system components into the desired operating configuration. . Gain MUX MUX Amp Amp Selection Out Out IN IN + + 11 66 25 28 26 27 • a. .: co RTNO °c 1ii « RTN1 RTN2 RTN3 RTN4 RTN5 RTN6 RTN7 CHO 3 CH1 4 CH2 5 CH3 6 CH4 7 CH5 B CH6 9 CH7 10 CHB 74 CH9 73 CH1072 CH11 71 CH12 70 CH13 69 CH14 68 CH15 67 Amp S/H Out IN 29 51 Gain Offset Adj. Adj. Con- S/H trol Out 50 4B ~ 40 Clock Out 37 Serial Out 47~ 31 MSB1 I 46 I 32 a. I 45 I 33 0 I 44 I 34 I 43 I is 35 I 42 I 36 I 41 LSB12 •!• Hold ... 8 Channel Multiplexer 49 Short Cycle • Ai 14 15 16 A1 17 ~ "C AB 63 "C ,, 62 « 61 Al 60 Count Enb. 13 Ct'iirEi6. 65 i:OiiaE'n6_ 12 Strobe 19 ::: 30 Status 0 52 Ext. Gain Adj. .: Stro6ir 5B Delay Adj_1 Delay Adj.2 21 56 ---..0 38 +5V 18 59 Delay Delay Out Out 75 SID 64 MUX Enb. Enb. 23 Neg. Ret, Out 24 Pas. Ret, Out 54 BPO 20 AID Tri 1 l-A ! 76 1 57 AID +15V -15V TrIg 2 Ana. Gnd. 39 Dig, Gnd. FIGURE 1. SDM853 Block Diagram. ANALOG MULTIPLEXER INSTRUMENTATION AMPLIFIER Two one of eight CM OS analog multiplexers are used to allow user selection by external jumpers of 16 single ended channel or 8 double ended channel operation. In 16 channel operation the multiplexer may be used in a pseudo differential mode by connecting the amplifier inverting input to a common, remote, signal ground. Channel selection is by a 3 or 4 bit binary word stored in a presettable address counter. Channel capacity is expandable without limit. The instrumentation amplifier is a low drift, differential amplifier featuring high speed at gains above unity, and external gain programming with an external resistor. With the gain programming pins open, the gain is unity. Gain may be selected from unity to 60 dB. 6-309 C.HANNEL EXPANSION The number of analog input channels of these systems can easily be increased using Burr-Brown's MPC8D and MPCI6S CMOS multiplexers. the MPC8D is an 8channel differential model and the MPCI6S is a 16channel single-ended model. These are latch-free devices which contain internal binary decoding, TTL or MOS logic levels, and may be integrated into a system with minimum external logic. SAMPLE AND HOLD AMPLIFIERS The sample an"d hold' /!.mplifier is a complete, stand alo~e, sample and hold circuit featuring buffered output, 7p.sec acquisition time, and 30nsec aperture time. Input, output and mode control Junctions are brought to separate connector pins. This·allows maximum System flexability for' performing such functions as automatic gain ranging with no loss of aperture time. ANALOG-TO-DIGITAL CONVERTER The ADC is a ceramic packaged, l2-bit converter featuring 24p.sec conversion time and 0.01% accuracy. Thin-film networks and current switching are used to assure linearity over wide temperature ranges. SYSTEM PERFORMANCE The SDM853 can be. configured to continuously sequence through all anal'og channels, to accept random addresses or to sequence through all analog channels on command from ~n external trigger. ADDRESS COUNTER A 4-bit binary adrl'ress counter is connected to the multiplexer. This counter may be externally loaded, cleared, clocked or enabled. The address outputs are brought to connector pins for convenient system control. The status signal, pin 30, is connected to the strobe not input of the delay timer, pin 58, for normal program sequencing with a minimum throughput sampling rate of 30kHz for 12"bit resofution. By using "overlap" programming, the settling time effects of the analog multiplexer and instrumentation amplifier can be reduced, extending throughput sampling rates up to 32kHz for l2-bit and 43kHz to 8-bit resolution. This mode of operation is most useful when converting low level inputs to accommodate the increased settling time of the instrumentation amplifier. Overlap programming is accomplished by conne!;:ting the status signal, pin 30, to the strobe input of the delay timer, pin 19, and extending the delay time. The internal logic will then select analog channel (n + I) while channel n is being converted. DHAYTIMER The delay timer is provided to allow for the settling time of the mUltiplexer, amplifier, and sample and hold circuits. The delay time is adjustable over a wide range by an external potentiometer andl or external capacitor. This allows for the longer settling time of the instrument amplifier at high gains. CONTROL LOGIC Delay and ADC trigger functions are edge-triggered and gated. Counter control functions are synchronous with the counter clock which is internally connected to the delay timer output. SYSTEM PERFORMANCE (Typical at 2SoC and rated supplies) !'" u.. ~ ~ 201-----~----_I--~~~~ 0.21------4-----_I----~200].~ ~ ,';: >E 50r-------~--------~--------., r---------T---------~--------, II: 1/1 0.1 z 100.3"i E~ ~ 0.05 ~ '0 ::> j: 1----~~~--~. .~~~--~20 . '0 o ~ ~ ~ E ~ ~ ~ ~ B ~~~. .~~~~~~--~1~0~0~~~~1~006° FIGURE 2. Nonlinearity and Settling Time vs. Amplifier Gain. System Gain System Accuracy VN 1 10 100·· 1000 Throughput Rate (Channels/sec) Normal Overlap ;:0.025% FSA 30k 32k ;:0.035% FSA ;:0.08% FSA 25k 20k .10k 32k 32k 14k ;:0.1% FSA FSR Normal Overlap 31 ~1 70 TABLE I. Throughput Rate vs. Gain for Normal and Overlap Modes. 2~----~~~~----4-~~----i 1~1--~~~~~~~~~--~~~~ FIGURE 3. Delay Time (IlSec) 9 18 25 70 10~----4_----~~~---i o eo AoC Ampli· Range fier Gain ±10V 1 20V IV O.1V o to 10V ld a to 10V 100 10mV o to 10V 1000 Reso· lution 4.88mV 2441lV 24.41lV 2.441lV* Delay for Delay for Delay for Settling Settling Settling to to.2% to to.05% to 0.01% (psee) (!lIee) (/.ISee) 7 10 20 60 8 15 9 18 25 70 30 - TABU': II. This table shows the delay timer setting required to allow for the settling time of the instrumentation amplifier to the accuracies specified.. Add the 24j.!sec conversion time of the AID converter to the above delay times to obtain channel conversion times. * Depends on desired SIN ratio. 6-310 ELECTRICAL SPECIFICATIONS Typical at 2S"C and rated power supplies unless otherwise noted I MODEL SDM8S3 TRANSFER CHARACTERISTICS 30kHz. 33,."sec/channel 12 Bits J6 single-endedj8 differential Throughput Rate. min Resolution Number of Channels ANALOG INPUTS (}-SV. (}-IOV. ±2.SV. ±SV. ±IOV I to 1000 G = I + 20kO/R,.XI ±16V ±IO.24V 100MO. IOpF OFF channel 100MO. 100pF ON channel ADC gain ranges Amplifier gain range Amplifier gain equation Max. input voltage without damage Max. input voltage for multiplexer operation f6J Input impedance '" Bias current 2S"C 20nA O"C to 70"C Differential Bias Current (25"C, Differential Bias Current Drift Amplifier output noise (Gain = 100. R. Amplifier input offset voltage. max Amplifier voltage offset drift SOnA IOnA O.lnA/"C = 5000) 1.2mV. rms; 7mV. p-p 400pV 2 + 20/GpV/"C ACCURACY''' System RSS accuracy at 25"C (Gain Linearity (Gain = I) Differential linearity (Gain = I) Quantizing error Gain error Offset error Power supply sensitivity = I) ±o.025% FSRClI at 30kHz throughput ±1/2LSB. at 30kHz throughput ±1/2LSB. at 30kHz throughput ±1/2LSB Adjustable to zero Adjustable to zero ±o.OO5% FSR/% change of supply voltage STABIUTY OVER TEMPERATURE System accuracy drift. max linearity drift ±30ppm/"C of reading ±Jppm of FSR/"C DYNAMIC ACCURACY Sample & Hold apertUre time Aperture time uncertainty Error for full scale transition between successively addressed channels Differential amplifier CMRR (Gain = I) Channel cross talk Sample'" Hold feedthrough Sample & Hold decay rate 30nsec ±5nsec I LSB at 30kHz 74dB at I kHz 65dB at 3kHz (IOOdB at 60Hz Gain = 1000) SOdB down at 2kHz. for OFF channel to ON channel SOdB down at 5kHz IOpV""ec OUTPUT Output Coding (Complementary) Gaintriml-4 t Offsettriml-4 t AID Conversion Time Delay Unipolar Straight Binary. Bipolar Offset. Binary Two's Complement Adjustable to zero error Adjustable to zero error 24",sec 9",sec nominal, externally adjustable from 5.5",sec to 14",secl~1 ±ISVDC ±3% at +50mA .. SmV. nns, ripple -ISVDC ±3% at -7SmA. SmV. rm •• ripple +SVDC ±S% at +300mA, 25mV. ems. ripple POWER REQUIREMENTS ENVIRONMENTAL Operating temperature Storage temperature Relative humidity O"Cto 70"C -2S"C to +8S"C 95% noncondensing I. With RExT between pins 26 and 27. 2. No missing codes guaranteed. 3. FSR means Full Scale Range. 4. Gain and Offset controls are located in the module. The adjustment ranges are ±O.I% FSR for Gain and ±o.I% FSR for Offset. S. Adjustable to 10 seconds with external capacitor. 6, For differential operation with gain> I. the common-mode input voltage range is ±5V. 6-311 DIGITAL INPUT SPECIFICATIONS One standard TTL load, positive true 4--bit binary One standard ITl load. negative true, address loaded with strobe inputs. One standard TTL load. negative true, address loaded with strobe inputs. One stal1dard ttL load. STROBE and m<5'irn edge trigger the delay timer and clock the address counter. STROBE must be hi.e:h to enable ~ and STRUBE must be low io enable STROBE. Two standard TIL loads. positive true, logic --0" al~ows the Strobe inputs to trigger the delay timer. but prevents the MUX address counter from being clocked. One standard TTL load. a positive going edge at TRIG initiates conversion. a negative going edge atiRJ(j initiates conversion; TR:m' must be "0" to enable TRIG: TRIG must be "I" to enable'T'R]"(j. One standard TTL load. logical I for 12-bit resolution. connected to the N + I bit output for N bit resolution. Address inputs ~ load Enable Clear Enable S'i'ro6:e Strobe & Count Enable ADC trigger Short cycle Multiplexer Enable Multiplexer Enable SID selec' Two standard TTL loads. logical I enable multiplexer output and logical 0 turns off all channels. Two standard TIL loads. logical 1 enables l6-channel sjngl~nded operation and logical 0 enable s.channel differential operation. DIGITAL OUTPUT SPECIFICATIONS Uata outputs Parallel BI. 81 . .. 812 Serial out Address outputs Delay out (Delay Out) Clock Status 2 Standard 2 Standard 5 Standard 5 Standard 5 Standard 5 Standard TTL TTL TTL TTL TTL TTL loads. negative true. loads. negative true. time serial data output beginning with B 1. (see timing diagram). loads. positive true. 4-bit binary code. internal 2k!l pull-up resistors. loads high (low) during the delay period. triggered by Strobe and Strobe inputs. loads for synchronizing serial out data (see timing diagram). loads. high during the A. D converison. SYSTEM TIMING DIAGRAMS u MUX ADDRESS OUT DELAY TIMER OUT ::.-::>E __-_-~_-_-Ch~neT;, ::dd=::.~_--_----_---:.---~3E .0=::el F9~sec --~I STATUS B3 I' --I - - - "'7"""\.·1 _ _ _ 1- _ _ - ' - I - - - " " \ . !t - --~! ~ i'~ I 1 I ,I I ---1--------,~I B12(LSB) SERIAL DATA OUT +FS ___ 1_ _ -FS - - - - - - - - - - -- - - - - - - - - -"r,-'---. "r\.--..:. --1'--' ' - - -- ____________~1\.......1'~-'-- n----\. J.'-----~-- ---..I ~ II Ch n data vali~ . ~MSB::!:'\11 0: 0 -"'T~!,--I-,-T":-r- I ~LS~ _ _ _ I ---"T:'--.-- ~ 1 (Sampling) 24#Lsec conversion - Ch n ----F- '-{ r..2. --I----'\...!.......J B2 ~1Ed=S ~d~ =t:I (Sampljn~l DATA BIT 1 (B1) - MSB S/H OUT u 8 ___I_YiJ_.L...I.._I_ 17 1 8 1 9 1213141 14 1 101111121 - ....... Serial data valid ...,j-- .1 / - --- ~ FIGURE 4. Timing Diagram for Sequential Addressing Normal Programming Mode. TRIG (START) (Runs while high -stops when low) . _ _ _ _...;~,-~-24#Lsec convert~,-_ _ s_.m...;.p_le_ _" STATUS DELAY OUT ~~~ ADDRESS _ _ _ -:..-_~;:n~I_-;_-_~_ OUTPUT DATA VALID DIFF. AMP. OUT +FS -FS +FS S/H OUT (See Tablel) -FS Channel n -1 ~ _:':_= : -:.. : X I \ Convert Channel n / Sample -=- -:.-=-:. -=- -=-__-_-= ~a~1 n~ \ ~ __________--,I \ Channel n + 1 -' / :FIGURE 5. Timing Diagram for Sequential Overlap Programming Mode. (Delay must be adjusted to status pulse.) 6·312 PACKAGE AND PIN CONFIGURATION SDM853 CONNECTOR PIN DIAGRAM +15V ANA. GND. CH 0 IN CH liN CH 2 IN CH 31N CH41N CH 51N CH 61N CH 7 IN MUX OUT HI LOAD ENB COUNT ENB A80UT A40UT A2 OUT Al OUT iITV. STROBE ADCTRIG DLY. ADJ. 1 Rl NEG REF OUT POS. REF OUT AMP IN HI G2 131 AMP IN LO AMP OUT STATUS Bl MSB B3 85 B7 B9 Bl1 SER OUT +5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 3B 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 -15V SID ENB CH 8 IN (0 RTN) CH 9 IN (1 RTN) CH 10 IN (2 RTNI CH 11 IN (3 RTNI CH 12 IN (4 RTNI CH 13 IN (5 RTN) CH 14 IN (6 RTNI CH 15 IN (7 RTNI MUX OUT LO CLR ENB MUX ENB ASIN A41N A21N A1 IN DLY. S'i'ROliE ADC Ti'fiG DLY.ADJ.2 R2 BPO COMP IN GAIN ADJ. S/H IN S/H OUT SHT. CYC. S/H CONTROL Bf B2 B4 86 B8 Bl0 B12 LSB CLK.OUT DIG RTN 5.1mm (0.20"1 rI ... ~ "' t * 5 6 (Ii.;';:':') typ f,':....... ~ .. (4.60") 94.0mm (3.70") ~ """OM ""., == :==:: . . :: :::1 ~ T 25.8mm (i.015") 7.6mm (0.30") -~ l f=J 16.5mm (0.65") . -G, Tapped Screw Hole use 4-40 x 3/16" Hardware 101.6mm (4.00") 7. 6mm (~ ~O~;;~')O 111111 __- - ___1111111 ~ (EDGE VIEW) 76mm (3.00"1 J 0- L 4 7.6mm (0.30") typ 8.4mm (0.33"1 CASE MATERIAL: Insulated Steel CONNECTOR PINS: Gold Flashed WEIGHT: 145 grams (5 oz.) MOUNTING INSTRUCTIONS: MOUNTING FLUSH. ON PC CARD 1. Use strip connectors or two 14 pin and three 16 pin low profile Ie sockets (shipped with e8~h unit). 2. Use 4-40 x 3/16" (4.8mm) LG Pan HD Hardware to secure the SDM853 to PC Card. 6-313 SDM854 BURR-BRoWN@' IElElI HYBRID DATA ACQUISITION SYSTEM FEATURES DESCRIPTION - MINIATURE SIZE - LOW COST -12·BIT. ±D.OI2% LINEARITY ERROR -INPUTS UP TO ±IO VOLTS - WIDE TEMPERATURE RANGE - SELECTABLE 16 SINGLE.B DIFFERENTIAL INPUTS - THREE·STATE OUTPUT BUFFERS OutputJ The SDM854 is a complete data acquisition system contained in a miniature 2.2" x 1.7" x 0.22" (55.9mm x 43.2mm x 5.6mm) ceramic package. This system offers all the functions available in large modular data acquisition systems. Inputs up to ±IOV can be accepted and low·level inputs can be accommodated by connecting an external instrumentation amplifier . to the output of the multiplexer and to the input of the sample/ hold amplifier. Digital re~olution is 12 bits with accuracy of±0.024% at a throughput rate of 27kHz. StH ~ r--_ _ _ _ _ _ ::II Stalua } - - - - - - - - o and Control Digital Outpull Output } L~==~ Enable Unn Clock Rail Adj. Clock Out Internllianal ~Irport Induatrllll'lrk - P.O. Box 11400 - ~UCBOII. ~rlzana 85734 - TIl. 16021 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-8491 PDS-423A 6-314 SYSTEM DESCRIPTION The SDM854 contains all components necessary to mUltiplex and convert analog signals up to ±IOV into equivalent digital outputs. Throughput sampling rates are from 27kHz (I2-bit resolution) to 70kHz (8-bit resolution) in the overlap mode of operation. The SDM854 can be configured to accept either 8-channel differential or 16-channel single-ended signals and can be expanded almost without limit with external multiplexers. Three-state outputs are provided for easy interface to microprocessor and other bus-structure systems. The system components are illustrated in Figure I and described in the following paragraphs. THREE-STATE OUTPUT BUFFERS Digital outputs of the ADC are internally buffered by LSTTL three-state buffers. Three separate enable lines are brought out for easy interfacing t04-, 8- or 16-bit data buses. MSB and BUSY are also buffered by separate three-state devices, each with its own enable line. ADDRESS LATCH Outputs of the 4-bit TTL register latch are connected to the address inputs of the multiplexer. This latch serves as an address storage register for the selected analog input. It may be loaded through 4 address inputs. Other inputs are LOAD and CLEAR. The 3 lellst significant bits are used for 8-channel differential mode addressing. ANALOG MULTIPLEXER The analog multiplexer consists of two CM OS integrated circuits. Pin interconnects are used to select 16-channel single-ended or8-<:hannel differential operation. In single-ended operation the multiplexer can be used in a pseudodifferential mode by connecting an external amplifier's inverting input to common remote signal ground. Channel selection is made by an internally latched 3- or 4-bit binary word, for differential or single-ended operation respectively. DELAY TIMER A delay timer allows settling time for the multiplexer and sample/ hold circuits before conversion,begins. The delay is adjustable over a wide range by use of an external resistor or capacitor. This allows for longer settling time if an external instrumentation amplifier is used and is operating at high gains, or shorter settling time for lower resolution operation. SAMPLE/HOLD A complete stand-alone circuit, the sample/hold amplifier features buffered output, IOl"sec acquisition time, and 100nsec aperture time. Input, output, and mode control lines are brought out to separate pins. This allows maximum system flexibility for performing functions. such as automatic gain ranging, with no loss of aperture time. The number of analog input channels of the S DM854 can be easily increased by using Burr-Brown's MPC8D (8channel differential) and MPCI6S (l6-channel singleended) multiplexers. These are latch-free devices which contain internal binary decoding at TTL or MOS levels and may be integrated into a system with minimal externallogic. ANALOG-TO-DIGITAL CONVERTER The ADC is a 12-bit, 251"sec converter with 0.01% linearity error. Its features include positive and negative reference voltage outputs, external gain and offset adjustments, straight binary or two's complement output, serial data and clock outputs, status output, a short cycle feature, and a clock rate control for higher throughput rates at lower resolution or accuracy. 6-315 CHANNEL EXPANSION SYSTEM PERFORMANCE The SDM854 is configured for random channel selection. With the addition of an external counter they can be IIIXIIIIX l1lil1li II LO Ott T- y. .SIII·::.r I/H I/H llllnplllllalj ~ EllABlE I 011 DID D9 DB EiAiIT2 07 DB OS 04 CNB/RETO ClIII/RETI CHlolRETZ CHll/REn CHI2IRET4 CHI3/HETS CHI4IRETB CH16/lIET17 ABOUT A20UT .UX EIIABl£ II Al OUT AU OUT 03 +5V D2 +5V 01 00 oom 3§~~~~~@Wftl lll~~~~~~fm 1iil!mlI AU III Z7 AllN ArIN· -6.4V SERIAL OUT SHORT CYCl£ B-B1T RESOLUTIOI IIJ.BIT RESOlunON A31N lOAolCLEAR MUX EllABlE2 ClOCK CLOCK RATE OUT ADJUST DELAY TlIIG OUT FIGURE I. SDM854 Block Diagram. configured to continuously sequence through all analog channels or sequence through all analog channels on command from an external trigger. With the appropriate 4-bit (singJe-ended) or 3-bit (differential) channel address on the latch inputs. and DELAY OUT (pin 45) tied to the LOAD input (pin 23).a negative going edge is applied to the STROBE input (pin 48). This starts the delay iimer. latches the multiplexer address. and allows the input signal to pass through the mUltiplexer. and sample/ hold before starting the AI D conversion. The DELAY OUT signal (pin45) is also connected to the i"RiG input (pin 46) and the A/ D conversion is initiated on the negative-going edge. The S I H CONTROL input (pin 66) is connected to iITiSY (pin 24) so that the sample/hold is in the HOLD mode during the AI D conversion. DIGITAL INPUT SPECIFICATIONS Address Inputs (AO- A3) Address Coding LOAD SHORT CYCLE One standard LSTTL load. positive true 4-bit binary One standard LSTTL load. positive true. address loaded on positive edge. One standard lSTTL load. negative true. low level clears address latch. One standard TTL load. high-to-low transition triggers the delay timer. One standard TTL load. a negative going'edge initiates the A. D conversion. One standard LSTTL load. logic I for 12-bit resolution. Connect to "8-bit" or "JO-bit" for 8- or IO-bit resolution. ENAiiiTi. EN'Aiiffi. ENAiiiTI. on ENAii'i::E BU SY EiiAiiLE SIH CONTROL MUX ENABLE 2 One standard LSTTL load. a low level enables the 3-state output. TTL compatible. JO~A maximum input current. Logic 0 = Hold mode. Logic I = Sample (t~ack) mode. TTL compatible. 2~A input current. logic 0 enables multiplexer 2 (channels 8-15). DIGITAL OUTPUT SPECIFICATIONS By using overlap programming the settling time effects of the analog multiplexer and external instrumentation amplifier (if used) can be reduced. extending throughput sampling rates up to 27kHz for 12-bit and 70kHz for8-bit resolution (ADC short-cycled). This mode of operation is most useful when converting low-level inputs to accommodate the increased settling time of the external instrumentation amplifier. Overlap programming is accomplished by connecting BUSY to STROBE and Sf H CONTROL; DELA Y OUT to LOAD and TRIG. In this mode of operation the address ofthe next channel to be converted is latched and the output of the external instrumentation amplifier allowed to settle to a new value during the present conversion. Parallel Data Outputs Serial Output i5ii BUSY BUSY CLOCK OUT 5 standard TTL loads. positive true 3-state. 2 standard TTL loads. positive true. NRZ. time serial data output beginning with DII (see Timing Diagram), 5 standard TTL loads. positive true. 3-state. S standard TTL loads. low during AI D conversion. S standard TTL loads. high during Ai D conversion. 3-state S standard TTL loads. for synchronizing serial out data (see Timing Diagram). 5 standard TTL loads. positive true Address Outputs (AO-A3) DELAY OUT 's standard TTL loads. high during delay period. triggered SINj D1F S standard TTL loads. high while addressing channels 0-7. by~input. low while addressing channels 8-IS. This output can go as high as 12V. It is still TTL-compatible with 101; limited to <20~A above 5V. 6-316 SPECIFICATIONS ELECTRICAL Typical at TA = +25°C and rated power supplies unless otherwise noted. PARAMETER TYP MIN MAX UNITS Resolution 12 Number of Analog Channels Throughput Rate I Normal mode I SDM854AG SDM854BG 1 Bits Rated Voltage for Specified Accuracy Quiescent Current +15VDC -15VDC +5VDC !6SIN/8DI F 33 25 35 27 kHz kHz 38 27 40 29 kHz kHz o to +10, ±5, ±10 V Throughput Rate I Overlap mode I SDM854AG SDM854BG ANALOG INPUTS ADC Input Voltage Ranges PARAMETER MIN TYP MAX UNITS ±14.S +4.75 ±15 +5 ±15.5 +5.25 V V +10 -35 +170 1300 +20 -50 +220 1750 mA mA mA mW +85 +85 +125 °C °C °C POWER REQUIREMENTS TRANSFER CHARACTERISTICS Mux Input Voltage Range Absolute max without damage For linear operation Mux Input Impedance, OFF Channel Mux Input Impedance, ON Channel I nput Leakage, OFF Channel Output Leakage, All 1.5 0.02 Channels Disabled Output Leakage with Input Overvoltage of +35V -35V ±35 ±15 1011 1.8 Power Dissipation ENVIRONMENTAL -25 -40 -55 Specification Temperature Range Operating Temperature Range Storage Temperature Range V V II NOTES: kll nA 2. Adjustable to zero. 0.2 nA 1 1 nA 1. FSR means Full Scale Range rFSR is 20V for ±1 OV range I, 3. Conversion time and clock frequency can be extern'ally adjusted from 13p.sec rfclock = 1.0MHzl to 110,usec rfClock = 118kHzl. rConv. times are for 12~bit resolution.) rSee Figure 9.1 4. Can be externally adjusted from 3p.sec to 300p.sec. ~A TEMPERATURE STABILITY System Accuracy Unipolar Bipolar Linearity Drift ±15 ±10 ±25 ±20 ±2 ppm/OC ppm/oC ppm/oC ofFSR REFERENCE VOLTAGES Positive Output Positive Output Drift Negative Output Negative Output Drift +2.490 -6.0 +2.500 ±5 -6.4 ±15 +2.510 ±10 -6.8 ±10 V ppm/oC V ppmloC ACCURACY Throughput Accuracy ±0.048 % of FSRP) ±0.024 % of FSR o to +10V, ±5V, ±10V, AG o to +10V, ±5V, ±10V, BG Linearity AG BG ±O.024 ±O.012 %ofFSR %01 FSR ±0.048 ±0.024 ±0.012 ±0.3 ±O.3 %of FSR % of FSR % of FSR % % of FSR Differential Linearity A!3 BG Quantizing Error System Gain Error(2) System Offset Error(2) Power Supply Sensitivity +15V Power Supply Sensitivity -15V Power Supply Sensitivity +SV ±0.024 ±0.012 ±0.1 ±0.1 ±0.OO07 ±0.OO07 ±0.OO1 %I%..IV %I%..IV %I%..IV DYNAMIC ACCURACY Sample/Hold Characteristics Aperture Time Acquisition Time Feedthrough /1 OV step I 100 10 ±1.4 nsec p'sec mV OUTPUTS Digital Output Coding Serial Output Coding ADC Conversion Time(3) Clock Frequency(3) Delay!') Binary, Offset Binary, Two's Complement Nonrer ~ zerr r N3~ZI ,usec 520 15 p'sec kHz 6-317 PIN DESIGNATIONS NC MUX OUT HI NC CH7 CH6 CH5 CH4 CH3 CH2 CHl CHO MUX ENABLE 2 MUX ENABLE IIA3 OUT SIN/DIF A20UT Al0UT AOOUT CLEAR AOIN AllN A21N A31N LOAD BUSY DIG COM SHORT CYCLE 10-BIT RESOLUTION 8-BIT RESOLUTION DO LSB Dl D2 D3 D4 D5 D6 D7 D8 D9 Dl0 Dll MSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC NC MUXOUT LO CH15IRET7 CH14/RET6 CH131RET5 CH121RET4 CHll1RET3 CH10lRET2 CH91RET1 CH8/RETO NC SIHIN SIH OFFSET ADJUST SIH CONTROL +15VDC -15VDC ANA COM SIHOUT -6.4V REF OUT 10VRANGE BIPOLAR OFFSET 20VRANGE +2.5V REF IN ENABLE 2 +2.5V. REF OUT ENABLE. 1 ENABLE 3 SERIAL OUT CLOCK OUT CLOCK RATE ADJUST +5VDC STROBE DELAY ADJUST TRIG DELAY OUT 51T BUSY BUSY ENABLE ENABLE on • n.... MECHANICAL lL P ott········ .. ···· .. ·:, 19 NOTE: "', ~~: . .:. :=s Pin num.bers shown for 'reference only . Leads in true position within 0.015* (O.38mmIR at MMC at seating plane. DIM A ·, • · · MIN MAX 1.1570 1.120 153.86 42.42 155.37 a..118 .230 4.32 5.8" .021 0.48 0.89 0.153 .110 ,018 0 , N .... .03' H l 2.501 BASIC .100 a.4SIC 2.54 BASIC 3.11 11.35 38.1 BASIC 0.05 0.215 .250 .1110 1.II00Blt.SlC .002 .010 P .0&0 BASIC .100IASIC .200 BASIC 1.1008ASIC MATERIAL: Alumina WEIGHT: 32 grams (1.2 OZI MATING CONNECTOR:, 2350MC (set of four 2O-pin stripsi or 0422MC (assembled unit I 1.21 .100 BASIC T U MILLIMETERS 2.180 c [ L t-[-._::JIIIDIIUIIIIRlHlpDllmaail GJL -1-0 INCHES MIN MAX 2.120 1.27 BASIC 2.54 BASIC 5.08 BASIC :n.9 h15vDC ~ II I 0.04 0.02 e ~ LJ 0.01 IL V 0.002 J L V .£ 0.001 0.0004 0 10 100 lk 10k 1;ONTROL VOLTAGE, 12-BIT RESOLUTION +0.15 r;:,:;r_;,;_::u~n:::i!::po;'.=:ar~;;:;:;;:::::::;=.::B::;iP~o~la;r > .l5VDC I j. ~ I: \ 1M V ~ ~ -5 ~ = i 201-----r-----r-____r -__--i E ~ 10t-----t-----~-----r----_i Time (min) 15 ! 'I'-- f·· 0 -, - j 20 '0 ~ ~ 1/2LSkl+8'-'-B'tit'-----1f--~ 0.2 0.195 8_8;t -- --- -+-+-+-+--+----l 0.15 ....... I ..... ~~~~;~r-I ~ '" "~~ " Temperature (oC) AID CONVERTER DIFFERENTIAL LINEARITY ERROR VS CONVERSION TIME ~ I Bf-it----ic--+_--I 0.2 1/2LS'BI+8--~ 0.195 '0 a-Bii g 0.151--+-t-+--+--H w 0.1 ,., j - ~V .~~t::'-- , 0.05 :::; 0.0485 0.0122 Z: 10-Bit \ 1\ 12-Bit 1/2~B;---t-l:l~\=!\::=±::-I iO-Bit\/2~~~"L\... -rf2'-B1I o 5 10 15 20 Conversion Time (",sec) 6-318 . -O.15 ....-_.. 40-_2,L,5~---l0~---:2!:5--5tO~-:7~0~B5 AID CONVERTER LINEARITY ERROR VS CONVERSION TIME :-s,_ .5-q> -0.1 ~+),;:~ . ~~~~lif' :';-0.05 - - -1o0!--~1!:-0--;:2~0--:i30:;-""'::!40~-5tO~-:6:':i6r' ~ 10 ~,: r' Conversion Time lJ.lseC), 12-Bit Resolution 30t------r-------i__----t------i o ~_ +0.05 \ CASE TEMPERATURE VS TIME WITH NO HEAT SINK OR AIR FLOW ~ +0.1 .......-I-~I---l--t--+--t--t ~ Frequency 1Hz,. () 40 - U lOOk I / : 1\ 1:.10 > .:j5VDC ~0.004 SYSTEM ACCURACY DRIFT. AID CONVERSIONTIME VS CLOCK RATE 0.2 0.1 .~ ~ ~ ~ 10-Bit \ 1\ Q)' i3 12-Bit 0 05 -1f2L~B ~ L~ 0.0485 =lO-Bit=·..... ~=-!r::::'::t'rk::::::·= _1'=:1 0 0122 -ll/~L.m! .......'L \... • 0 ---j l2:.t:Siti 5 10 15 20 Conversion Time (,usee) DESCRIPTION OF PIN FUNCTIONS NUMBER DESIGNATION Pin I N<;: Pin 2 MUXOUTHI DESCRIPTIDN No connection. High output of the analog input multiplexer. Connect to pin 78 (M UX OUT LO) and pin 68 (SI H/ IN)for single- ended input operation. Pin 3 NC No connection. Pins 4 thru II CH7·CHO The first 8 (of 16) analog inputs for single--ended operation or for 8-channel differential input operation. Pin 12 MUX ENABLE2 Connect to pin 14 (SIN/ DIF) for singJe-ended input operation. Connect to pin 13 (MUX ENABLE I) for differential input operation. Pin 13 MUX ENABLE 1/ A30UT Leave open for single-ended input operation. Connect to pin 12 (MUX ENABLE 2) for differential input operation. Also. A3 output line. Pin 14 SIN/DIF Single/ Differential input operation. Connect to pin 12 (MUX ENABLE 2) for single..ended operation. Leave open for differential input operation. Pin. 15, 16, 17 AO OUT· A2 OUT Output lines from input channel address latch (A3 OUT is on pin 13). Pin 18 a:EAR A low on this line clears the address latch causing the SOM8S4 to address channel 0 regardless of the information present on AO IN· A3 IN. Connect to +SVDC or to user logic circuitry. Pin. 19,20,21,22 AO IN ·A3IN Address lines that selec::t one of 16 analog input signals (CHO·CH 15).0000 selects channel 0 and I I II selects channell S. Connect A3 to ground for 8.channel differential operation. The address is latched with a positive TTL edge on .he LOAD (pin 23). Pin 23 LOAD A positive TIL edge on this pin latches the input channel address present on AO IN· A31N (pins 19.20.21.22). Pin 24 iiUsV This signal will be low during the AID conversion (-25",sec). Output data is not valid while this signal is low. Pin 25 DIG COM ~igital Pin 26 SHORT CYCLE This pin allows short cycling the A/ 0 converter for lower resolutions thereby obtaining faster conversion times. Connect to +SVDC (pin 49) for 12·bit resolution, (pin 27) for l()"bit resolution. or (pin 28) for 8·bit resolution. Pin 27 I()"BIT RESOLUTION To short cycle to lO..,it resolution connect to pin 26. Otherwise. make no connection. Pin 28 8·BIT RESOLUTION To short cycle to 8-bit resolution, connect to pin 26. Otherwise. make no connection. Pjns 29 thru 40 DO·DII 12·bit data bus, 3-state low power Schottky TTL-<:ompatible. Pin41 on (pin 44) is enabled when i5ii ENABLE is low. Pin 42 i5ii ENAiiL'E BUSY ENAiilE Pin 43 BUSY 3-state output that will be high only while an AI Dconversion is in process. Outpurdata is not valid while this signal is high. Connec••o S/ H CONTROL (pin 66). common. Connect to ANA COM (pin 63) as close to the SDM854 as possible. BUSY (pin 43) is enabled when BUSY ENABLE is low. Pin 44 D!i MSii. Pin 45 DELAY OUT This pulse is used ·to delay the beginning of the AJ 0 conversion to allow for the settling of the multiplexer and samplel hold. Pin 46 TRiG A negative TTL edge on this pin initiates the AID conversion. Connect to DELAY OUT (pin 45). Pin 47 DELAY ADJUST When the SOM8S4 is addressed. an internal delay of approximate,y IS",sec is initiated to allow for multiplexer and sample/ hold set~ling time. The delay can be shortened for filster lower·resolution operation. Use instead of 011 when two's complement output is required. Pin 48 S'I"iUm A negative TTL edge on this pin initiates the DELAY OUT pulse. Pin 49 +5VDC +SVDC at 2OOm'A maximum, 170mA typical. PioSO CLOCK RATE ADJUST Varying the voltage at this pin changes the clock frequency and thereby ,!hanges the conversion speed of the AI D converter. Connect to DIG COM (pin 25) for 12-bit operation (25J.'sec A/ D conversion time). Connect to +5VDC for lO·bit operation and connect to +15VDC for 8-bit operation (see page II). Pin 51 CLOCK OUT A/ D converter clock output. Output is present only during AI D conversion. N + ITTL pulses are output at a 520kHz rate where N is the resolution. . Pin 52 SERIAL OUT Serial output data in NRZ format is synchronous with CLOCK OUT (pin 5 I) signal. Use negative edge of CLOCK OUT to strobe each bit. Pin. 53, 54, 56 ENA'iii:E'3/ EN'AiiiTi1 EFIA'lim 3--state enable lines for data bus 011 • DO (MSB = 011). ENAiii:"Ei (pin 54) enables DII ·08; ENAiiiTi (pin 56) enable. D7 • 04; ENABLE 3 (pin 53) enables OJ • DO. A low on .he enable line enables data outputs. Pin 55 +2.5V REF OUT Positive voltage reference output. Connect to REF IN (pin 57) (through SOH) for unipolar or bipolar operation (unless an external reference is used). Also connect to BPO (pin 59) (through 250) for bipolar operation. Pin 57 +2.5V REF IN Reference voltage input. Connect to +2.5V REF OUT (pin 55) (through SOO resistor or loon pot) or use external +2,SV reference (+2,SV ±lOmV at O'smA required). Pin 58 20V RANGE AID converter input resistor. Leave open unless an externallA with a gain greater than 2 is used. (Input multiplexers are limited to ±6V maximum input voltage.) Pin 59 BIPOLAR OFFSET AI D converter bipolar offset. Connect to REF OUT (pin 55) through a 25!l resistor or a operation. Leave open for unipolar operation. son pot for bipolar Pin 60 IOV RANGE AID converter input resistor. Using without IA: connect to SI H OUT (pin 6;2) for ±5V max input operation. Pin61 ..fi.4V REF OUT Negative voltage reference output. Maximum current drain from this point without degradation of speCifications is200",A. Pin 62 SIH OUT Sample/hold output. Connect to IOV RANGE (pin 60) or 20V RANGE (pin 58) for normal operations. 6 6-319 DESCRIPTION OF PIN FUNCT'IONS DESIGNATION NUMBER DESCRIPTION Pin 63 ANA COM Analog common. Connect to DIG COM (pin 25) as close to the SDM8S4 as possible. Pin 64 -ISVDC -ISVDC at 30mA typical. Pin 65 +ISVDC +ISVDC at 30mA typical. Pin 66 SIHCONTROL A low signal on this line £auses the sample; hold 10 e~ter the hold mode. Connect to iiUSV (pin 24). Pin 67 SI H OFFSET ADJUST Offset adjust for sample! hold (see Figure 8), Pin 68 SIH IN Input to sample! hold amplifier. Connect to MUX OUT HI (pin 2) and MUX OUT LO (pin 78). Pin 69 NC No connection. Pins 70 theu 77 CH8-CHIS RETO - RET7 operation. Analog inputs 8 through 15 for single-ended operation or analog returns 0 through 7 for differential input Multiplexer output for CH8-CHIS (single-ended) or RETO-RET7 (differential). Connect to MUX OUT HI MUX OUT La Pin 78 (pin 2) and Sf H,IN (pi," 68) for single-ended operation. Pin 79 NC No connection. Pin 80 NC No connection. NC ,..------------ ...... UXOUTHI .......... Analog Ch. 7 ConnaCiIO Analog InpUla 0 Ihru 7. Tie unuud Inpullo Analog Common. ............... " . ANALOG INPUT .................... ANALOG INPUT I 1 1 1 ~:~~a: ~UlPUI {---~ logic or NC +5VDC --=----~II ConnBCIlo Addrall [ Salacl Linea Load J --L ] '9' Analog Common rh Dlgllal Common ConnlCllo Analog Inpuls 81hru 15. Tie unused.inpullo Analog Common. 1 1 SIH IN 1 SIH CONTROL 1 SIH OFFSET ADJUST ~_ _ _-"IO.:;.;PI;;:.lon;;:.a,,-II_--, r -1- --+i5viii::1i!i~--, I -15VOC 19------, - - - - ;;:NACOM 1 r----S7iiIiiiT 1 1 1 1 I 1 . No conneclion Connection path under package I 1 LOAD I I BUSY 1 I DIGCllIr-----' 1 +5VDC -------<~ SHOiii' CYCLE - - --' IO-BIT RESOLUTION 8-BIT RESOLUTION '--1-----.---+-- -6.4V REF OUT IOV RANGE BIPOLAR OFFSET 20V RANGE. +2-5V' REF IN ...,------,_t ENABLE 2 5011 +2.5V REF OUT ~~+-+-=""--'Bipolar Ollsel ENABLE 1 ) To Oulpul Enabla Logic. ENABLE 3 Tie 10 Logic Low 10 Enable. SERIAL OUT SERIAL DATA OUT CLOCK OUT CLOCK OUT Dt-+----. D------'~ STROBE To DlglllllIaIa Bus 3-STATE DIGITAL OUTPUTS DELAY ADJUST TRIG DELAY OUT 011 BUSY~---­ BUSY ENABLE I S I - - - - - } 011 ENABLE 4 To Control logic or NC °Analog and Dlgllal Common should be connecled IOgelher close 10 Ihe unll. FIGURE 2. Connection Diagram for SDM854 Operating Under These Conditions: Analog Input: Bipolar, single-ended; Reference Voltage: Internal; Resolution: 12-bits; Mode: Normal; Digital Output: Binary. 6-320 SETUP PROCEDURE INPUT CONNECTIONS Unused analog inputs must be connected to ANA COM, pin 63. When long leads are connected to the inputs, care must be taken that leads do not pick up excessive noise from external equipment and wiring. When low-level applications are undertaken. it is usually advisable to operate the system as an 8-channel. differential input system. This will req uire an external differential amplifier to be wired in between the output of the multiplexer and the sample, hold amplifier. In this way any noise will be common to both input wires, and will be rejected by the instrumentation amplifier. For best noise rejection use twisted shielded pair cable. The inputs of the SDM854 are protected from damage by voltage as high as ±35 volts and from short spikes well in excess of this for a few microseconds; however, careful wiring and cable routing practices are recommended. obtained by using pin 44, D II, as the most significant bit. One's complement code may be obtained by a different offset adjustment in the calibration procedure. Two's complement and one's complement codes are usually used only for bipolar signal ranges. For 12-bit resolution, SHORT CYCLE (pin 26) is left open or taken to +5VDC. Connect pin 26 to pin 27 (IO-bit) or pin 28 (8-bit) to obtain lower resolution. The conversion time will be shortened by the following formula: (Conversion Time) = (25/lsec) x [I - (12-Rj 13)] where R is the resolution desired. ·6.4V REF OUT +2.5V REF OUT +2.5V REF IN Single-Ended Inputs BIPOLAR OFFSET ·15VDC For single-ended inputs connect pin 2 and pin 78 (M UX OUT HI and MUXOUTLO)topin68(SAMPLEj HOLD amplifier input), all unused inputs to the multiplexer and all signal returns to pin 63 (ANA COM). 10V RANGE 5kn 20V RANGE 2,5kn 5kn 5kn Differential Inputs With External Instrumentation Amplifier Connect the signal inputs to pins 4 through II, and their returns to 77 through 70. Connect pin 12 to 13. Connect' pins 2 and 78 to the noninverting and inverting input of the amplifier respectively. The output of the amplifier is connected to pin 68. Successive Approxlmltlon Raglstllr SAMPLE/HOLD Connect SI H CONTROL, pin 66, to the ADC BUSY output, pin 24. ANALOG-TO-DIGITAL CONVERTER INPUT VOLTAGE RANGE NORMAL AND OVERLAP MODE The analog-to-digital converter is essentially a current input device having a current input range of 0 to 2mA. The input may be considered a virtual ground summing point. To convert voltage to current, a center tapped 10kH resistor is internally connected to this summing point. This is illustrated in Figure 3. The interconnection of the ADC pins and the SI H OUT, pin 62, are shown in Table I. TABLE I. ADC Range Jumpers. Inpul Range IVI 010+10 -510+5 ·1010+10 FIGURE 3. Analog-to-Digital Converter. Jumper 59 Open, 60 10 62, 58 Open 59 10 55, 60 10 62, 58 Open 59 10 55, 58 10 62, 60 Open NOTE. Input ranges In Table I apply to ADe only. OUTPUT CODE For unipolar binary and offset binary use D II (pin 40) for the most significant bit. Two's complement binary is The two basic modes of system operation are normal and overlap. In normal operation the channel address, N, is loaded or clocked into the address latch. The addressed channel will remain selected during its analog-to-digital conversion. In overlap mode channel N + I is selected while channel N is being converted. This can be used to increase the system throughput rate by allowing the multiplexer and external instrumentation amplifier to settle while a conversion is being made. In this way the throughput rate is limited by the samplel hold acquisition time and the analog-to-digital converter conversion time. For this reason, the overlap mode is more desirable for low-level signals. Table II and Figures 4and 5 provide additional timing details. At high signal levels a high source resistance may increase the multiplexer settling time to an extent which makes the overlap mode desirable. Normal Mode Connections Connect DELAY OUT, pin 45 to TRIG, pin 46. 6-321 OUTPUT INPUT IUSY ii'IiiIiE DELAY BUT lUX m lOAD SIR CONTROl ::)E:::-:.:=:~i!.~n:.:. ADDRESS OUT :..3E::::'[~C:.":";:.:-3<:: :Jl---------n -- ------r: lh-------] n------=' c OI1IISII 010 ::LiJ L 01 =,::: _____ ~-----L CC,-1 il : ~ UJ l·! ( I : : 1112131 ::1 10 111 112 1 Id 2 13 1;lIITIlill== 1111 SERIAL OUT I : : I I I : I I I >fS S/MOUT .fS ENABI£ III OATAOUT FIGURE 4. System Timing for Overlap Operation. OUTPUT INPUT STROBE NUX ADDRESS OUT DELAY BUT LOAD TRIG SIR CONTROl BUSY OI1IISII 110 .. ~------~----------~u~------- 1...._1ftI1 I 25_ ......,Ion· Ch n _ _ _ L.. _ _ ~ '~.L ---~--"' ---!-__ i ~, ~ ---1---" ( IIOIl811 )nmplloal ~~~~~~0-------------1'=~~~ - - -1- - -liir _ _ _ _ _ _ _ _ _ _ _ _ :~_/-"~ __ 1 r~ . \l ____________ ,.-..-- ~ \~_ n..£II.!!...~V!!ld ~ I' 1 01 1 I I U . j' LB1I " " " \ . ' - - - - - -- ---1-~~41;'T7:8:_;T1o'1i1iif- - - - - - - t - __ ~.!.l.!.L...l..jI"'-'-.J.- ..., - - - - - - - - IE~AlOUT I- ~DIoC',"", CM",,,,I Ii 2LSB 4. Offset voltage drift < Ii 2LSB/ (GAIN) ol T 5. High input impedance> R"",,,., x 10" The IOkfl resistors and a IOI'F capacitor provide lowpass filtering (L = 0.8Hz) while the I Mfl resistors supply bias current to the instrumentation amplifier. The remote sensor should be earth grounded to prevent commonmode voltages from exceeding the ±15V range of the mUltiplexer. This will usually supply bias current: however. the resistors provide a back up. It is not obvious what resistance the bias currents of the amplifiers will see. The I Mn resistors do not enter into an error calculation for input drift because the low resistance of the sensor shorts any differential current of the amplifier. Offset or difference current is merely the difference between the bias currents of each input. See page 15 for a worst-case error analysis of the input filter for multiplexed data acquisition systems. The I MH resistors could have been put on the output side of the multiplexer eliminating the The importance of initial offsets are somewhat minimized by the capability to cancel out offset at several points in the system. The Burr-Brown 3630 was chosen for this application because of its high linearity, good drift spec and CM R R characteristics. Some of the accuracy calculations for the Burr-Brown 3630 are as follows: Nonlinearity = ±0.002 + 10-; (Gain) % FS at G ~ 100 nonlinearity is ~ 0.003%FS Input impedance = 109 n so source impedance up to 100kn can be used. Voltage offset drift at Gain = 100 0.251' V;"C ~ I.22m V 1000l T so ol T ~ 49"C for errors ~ I 2LSB. CMRR at Gain = 100 is II0dB CM range = 10V i I.22mV = 78dB. RG =4Dll Thermocouple ~ '--........-"'_____o_--' I' '---v-----' Lona Cable Run _ '-y--I ' - - - - - y - ' I Rc Ra ~ 4D.2Im Rb IOkll ·15VDC = Dual Rd Monoli~ic I I SOMB54 : External : Amplifier I Instrumentation : Optional IHz Low-Pass : I Bias Curren! Filter I =+15 -15 +5 I Supply Resistors ,,-- ---- - ___ J E 27kll CHN RTN: : : E' R. ( :~d 11+ ~ I~ ~ 10 .!!.._---.!!!!....11+.!!!1~1O Rc+Rd Rb q Transistor Pair aT Mounted Near Isothermal Barrier Strip T' OK. k/q. 8.67 x 10-5 FIGURE 18. Thermocouple Inputs. FIGURE 19. Ambient Temperature Sensor. 6-327 I need for repeating them for each input; however, this would have loaded thc 10k!! resistors ofthe filter causing a possible I % error for static conditions. proportional to the size of the filter resistors (E = los x 2R). Of course, this is a static crror and asfor loading error, may not be important for some opcrating conditions. Ifall chanhels have the same resistance most of this error may be corrected by the offset adjustment of the analog-to-digital converter. If the offset current drift is 0.1 nA "c the error is 2R x 0.1 nV "c. For 10k!! resistors this would be 21lV "c. To' complete a thermocouple system it is necessary to terminate all thermocouple wire pairs at an isothermal box or connector strip of some type. An ordinary barrier strip in an enclosed cabinet with even air circulation is usually adequate. The temperature of this barrier strip must be monitored to allow the observed thermocouple emf to be cold junction compensated. Figure 19 shows an excellent circuit for this purpose. Its output is connected to one of the input channels to supply ambient temperature data to the system computer. When the multiplexer scans, charge will be transferred from the filter capacitor to the 25pF output capacitance of the mUltiplexer. For less than 0.1 \', of full scale error, the filter capacitor must be large than 25000pF. This assumes that adjacent channels may differ by the full scale voltage. Pumpout current refers to charge being transferred from the filter capacitor to the multiplexer capacitance at time intervals short enough that the filter capacitor does not have time to recharge between scans. At high scan rates this may be considered a DC current which may add to the offset current. Assume a 10M F capacitor sampled once per millisecond. For a 20m V full scale range, the maximum effective current is (20mV x 25pF) Imsec = 0.5nA. If the filter resistors are 10k!!. a 0.5nA x 20k!l = 10M V error is created. INPUT FILTER DESIGN FOR LOWLEVEL SYSTEMS When the SDM854 is used to acquire low-level sensor data, it is often desired to place a low-pass, passive filter on each input. This is usually done to reduce any differential mode, power line frequency pickup. Figure 20 shows such a circuit. r---------, I Mux When no input filter is used, the signal source must be able to charge the multiplexers and any cable capacitance during the channel acquisition time of the multiplexer and external amplifier. This is discussed on page 13. When all of these errors as well as the basic 2.0M V "c input offset voltage drift of the external amplifier are considered, the overall system accuracy may be estimated. I 100Mnl I SOM854 lo6Mnl 6800 AI5 FIGURE 20. Input Filter Design for Low-Level System. A5 t +5VDC .... =~ e.g ... u lkn SDM854 c .. 02 This circuit is deceptive in its simplicity. Actually four errors sources should be considered in its design. They are loading, offset current, charge transfer, and pump out current. R/W AI A2 A3 A4 The static loading error is simply the resistive divider created by the filter resistors and the 100M!l input resistance. For low-level sensors, 0.1 % system accuracy is usually adequate. Thus R should be less than 10-.1 x (IOOM!l)= 100k!l. However, if the inputs are scanned at a high speed, and between scans the multiplexer can be addressed to a unique channel having a lower resistance, higher filter resistance can be tolerated because the large filter capacitor will act as a voltage source during the 30M sec to I OOMsec period required to read each channel. The filter capacitors will then recharge between scans. AD HALT I The input offset current caused by the bias currents ofthe external instrumentation amplifier as well as any leakage current of the multiplexer will cause an error voltage FIGURE 21. SDM854 Interfaced to 6800 Microprocessor. 6-328 6800 Address Select SDM854 AI5 +5VDC +5 DC Ik!l SDM854 Ik!l ICI:74lSIO IC2: 74LS04 1C3-5: 74LS 136 LOAD R/W STROBE STROBE ENABLE I AD ENABLE 2 ENABLE 3 ENaBLE I ENABLE 2 ENABLE 3 A31N A21N AI IN AOIN DO 01 02 03 04 05 06 07 08 BUSY DO 8~ 03 04 It DELAY OUT AOIN AI IN A21N A3IN MUX OUT HI MUXOUTLO ADO ADI AD2 AD3 A04 ADS A06 AD7 /rurr.Brown 3606 PGA S/H IN 8? l DO DID 011 FIGURE 24. SDM854 Interfaced to 8085. Slam Conversion ~ Sirobes Chlnnel FIGURE22. SDM854and 3606 PGA Interfaced to 6800. ,-LOAD SBC80 IMultlbusl ADRFI ADR51 MRDCI ADROI SDM854 ICI: 74lS04 IC2: 74LS06 IC3: 74LSOO IC4: 74LS74 1C5·7: 74LSI36 E2 , El STlIlIB£ - DATI~ mil lim FIGURE 23. SDM854 Interfaced AD IN .AIIN A21N A31N -- 221'B8C + Wall ~ Typ. II to SBC80 Multibus. 000102 03 WAif. STB2 P20 P21 P22 P23 P24 ZS P25 P26 P27 - Initialize Port 2 P20 • P27 As Outputa Oulpul P20 = 0 P2 • P24 Channel Dala • Stam Conversion BUSY ENiiIT1 ADRII ADR2I ADR31 ADR41 DATOI J--< STROBE AD IN AI IN All" A3IN ~ SOM854 . EI ENABLE 2 ENABLE 3 XACKI r--( : 1ProcHsor Entars Wall Siale Output P20 =I Prevents Start of Another Conversion InlUalize P21 • P24 As Inpula Output P27 = 10 P26. P25 =I Input P21 • P24 Read 4 MSB's Output P26 = 10 P21, P25 = I Input P21 • P24 Read 4 Mid Blta Output P25 = 10 P27, P26 =01 Inpul P21 • P24 Read 4 LSB's Insufflclenllnlo on ZB to do beller program or diagram. FIGURE 25:SDM854 Interfaced to Z8. 6-329 BURR-BROWN@) IElElI ~ SDM856 SDM857 HYBRID' DATA ACQUISITION SYSTEM FEATURES DESCRIPTION - MINIATURE SIZE The SDM8S6 arid SDM857 ate complete data acquisition systems contained in a miniature 2.2" x 1. 7" x 0.22" (55 x 43 x 5.6mm) ceramic package. These systems offer all the functions available in large modular data acquisition' systems and are available with an optional internal instrumentation amplifier (SDM857). Inputs as low as ±50mV can be accepted by ,theSDM857; thermocouples, strain gages, and other low level signal sensors don't require external signal conditioning. Both models are fully expandable from the basic 16 channel single-ended or 8 channel differential input capability. Digital resolution is 12 bits with accuracy of ±O.024% at a throughput rate of-25kHz (SDM856KG). -LOW COST -12·BIT; 0.024% ACCURACY , ; -INSTRUMENT AMP OPTION - LOW"LEVEL lNPUTS (S~M8571' - SELECTABLE 16 SINGLE. 801HERENTIAL INPUTS - THREE·STATE OUTPUT BUFFERS - 60kHz THROUGHPUT RATE WITH 8·BIT ACCURACY S/H -Oiiipullln~put COIItrOIOU"lpUt OUlputa IiniiUtl- I~I I I I I I I t : + ~.A. I I : ' " r-_ _ _ _ _ _-<>g:~11 t-------o Status' Ind Control S/H I L_SO~!i~~_J ':: ~===~} Enables Strobe • , 'r '>,. Inlarnalional Alrportlndua!rial Park· P.O. Clock OUt • ~ox , --, Relel'lllCl Outputs , - ~ 11400· Tucson. Arizona 85734 . Tel. (602)746.1111 '. T"x: 9111-852·1111 . Cable: 88RCO,RP • Talax: 66~1 PDS402 6-330 DISCUSSION OF PERFORMANCE INTRODUCTION SDMS57 contains all components necessary to multiplex and convert analog signals as small as 0 to +50mV and as high as ±5V into equivalent digital outputs. Throughput sampling rates are from ISkHz (12 bit resolution) to 40kHz (S bit resolution). A complete low drift instrumentation amplifier allows selection of gains from 2 to 1000 with one external resistor. SDMS56 is identical to SDMS57, but does not include the instrumentation amplifier. This provides the option of adding an external instrumentation amplifier for specific requirements such as high speed, digital programming, etc. Throughput sampling rates as high as 60kHz (S bit resolution) can be obtained with the SDMS56. Both models can be configured to accept either S channel differential or 16 channel single-ended signals and can be expanded almost without limit with external multiplexers. Three-state outputs are provided for easy interface to microprocessor systems. Figure I illustrates all system components. ANALOG MULTIPLEXER The analog multiplexer consists of two CMOS integrated circuits. Pin interconnects are used to select 16 channel single-ended or S. channel differential operation. In single-ended operation the multiplexer can be used in a pseudo-differential mode by connecting the amplifier inverting input to common remote signal ground. Channel selection is macle by an internally latched 3 or 4 bit binary word, for differential or single-ended operation respectively. INSTRUMENTATION AMPLIFIER (SDMS57 only) Offering low drift and high accuracy, the internal instrumentation amplifier may be programmed by a single external resistor for gains from 2 to 1000. With gain programming pins open, the gain is two. SAMPLE AND HOLD A complete stand alone circuit, the sample and hold amplifier features buffered output, lO~sec acquisition time, and lOOnsec aperture time. Input, output, and mode control lines are brought out to separate pins. This allows maximum system flexibility for performing functions, such as automatic .gain ranging, with no loss of aperture time. ANALOG TO DIGITAL CONVERTER The ADC is a 12-bit, 25~sec converter with 0.01% linearity error. Its features include positive and negative reference voltage outputs, external gain and offset adjustments, straight binary or two's complement output, serial data and clock outputs, status output, a short cycle feature, and a clock rate ·control for higher throughput rates at lower resolution. SDM857~ Mux Out ~G.'. -,,;l WH Adlust Out lin OIfoet WH Adj. Control Muxr.-...Outlln In HI, ; ; WH!!!!X """ Out Enable Busyli:iiY Com :~l ~t tr11 h:!~" j" ., =101 I ~ I~) L ____ --1 I~ 43 Dig 20V IOV +'.5;' Com Range Range Rtf Ref ·t~r631~f·r25 +15 . r;::==-...Js<, -15 <5 Eoablol Instrulr8ntaHon Amplifier Dll ~!O 1281t D. 07 .vb 06 Can.r., f,d;i;1 ~ 05 D. 03 Mux (2) 0' 01 IN'/RE," IN9/RETI INIO/RET2 INI1/RET3 INl2/RET4 .... 7 INI3/RET5 7S DO :~:~~:~~ ~ ~ !m !mEoable -6.4V Serial Out il3i==!:bt:==:tEil MIx 1/A3 Enab A2 Out· Ou~'; 15 Short Cycle Ouf::!l'6:=:=t~====t1 I AI AOOut '7" AGIn Alln A2 I. Al .. 12 Mu. EneD 2 '4 47 51 SIn! Delay SJiCi&i 0.1ay olff Adj. Out FIGURE I. SDMS56/SDMS57 Function Diagram. 6-331 clack Clack Rate Out Adjust. 10 Bit a 81t DISCUSSION OF PERFORMANCE (CONTINUED) THREE-STATE OUTPUT BUFFERS Digital outputs of the ADC are internally buffered by LSTTL three-state buffers. Three separate enable lines are brought out for easy interfacing to 4, 8 or 16 bit data buses. DII (MSB) and BUSY a~e also buffered by separate three-state devices, each with its own enable line. SYSTEM PERFORMANCE SDM856 and SDM857 are configured, for random channel selection. With the addition of an external counter they can be configured to a) continuously sequence through all analog channels or b) sequence through all analog channels on command from an external trigger. With the appropriate 4"bit (single-erided) or 3-bit (differential) channel address on the latch inputs, and DELAY OUT, pin 45, tied to the LOAD input, pin 23, a negative going edge is applied to the STROBE input, pin 48. This starts the delay timer, latches the multiplexer address~ and allows the input signal to pass through the mUltiplexer, instrumentation amplifier and sample/ hold and settle to its final value before starting the A/D conversion. The DELAY OUT signal (pin 45) is also connected to the TRIG input (pin 46) and the A/D conversion is initiated on the negative-going edge. The S/H CONTROL input (pin 66) is connected to BUSY (pin 24) so that the sample/hold is in the HOLD mode during the A/ D conversion. By using overlap programming the settlirigtime effects of the analog multiplexer and instrumentation amplifier cim be reduced, extending throughput sampling rates up to 29kHz for 12-bit and 67kHz for 8-bit resolution (ADC short-cycled). This mode of operation is most useful when converting low level inputs to accommodate the increased settling time of the instrumentation amplifier. Overlap programming is accomplished by connecting BUSY to STROBE and S/H CONTROL and DELAY OUT to LOAD and TRIG. In this mode of operation the address of the next channel to be converted is latched and the output of the instrumentation amplifier allowed to settle to a new value during the present conversion. ADDRESS LATCH Outputs of the 4-bit TTL register latch are connected to the address inputs of the mUltiplexer. This latch serves as an address storage register for the selected analog input. It may be loaded through 4 address inputs. Other inputs are LOAD and CLEAR. The 3 least significant bits are used for 8 channel differential mode addressing. DELAY TIMER A delay timer allows settling time for the mUltiplexer, amplifier and sample/hold circuits before conversion begins. The delay is adjustable over a wide range by,use of an external resistor or capacitor. This allows for longer settling time of the instrumentation amplifier when operating at high gains, or shorter settling time for'lower resolution operation. CHANNEL EXPANSION The number of analog input channels of the SDM856 and SDM857 can be easily increased by using BurrBrown's MPC8D (8 channel differential) and MPCI6S (16 channel single-ended) multiplexers. These are latchfree devices which contain internal binary decoding at TTL or MOS levels and may be integrated into a system with minimal external logic. SYSTEM TIMING DIAGRAMS OUTPUT INPUT STRODE MUX ADDRESS OUT DELAY OUT LOAD TRIG BUSY S, H CONTROL (sampling) - DII (MSB) - -l- ! ===t=..-=-=""\. ___ L ___ 010 I 2SjASeCconversion-Chn --:7).0 - - - - - - - - - I; ~ .~.l. (sampling)!L _ _ _ __ ----h---- ;;=== _________ .___ _,'\..J J \ __ _ - - _L.. - -""""' ! i ti'..L · ________ .____"~,......,----i----'-.L.l, \-- D9 1 --, 1 - - - 1- - - - 01 (LSD) - - -1- - +FS ---1- _ MSB 1 ~ ---1:---~ 1--t o~~1 -FS 1..../ _ _--L SERIAL OUT S,H OUT 1 1 n"r'=--- 1.----"hndataval~'d 1 1 .J 1 I1 II --dlT-,-,-..-:;-.,.::'!.!:'!!!..___ _ 2' 3 , 4 I ' 7 ' 8 , 9 ' 10J. II 1 12 , -T~-------, • I -..J._-'-J...!l-'-J..,;.L;...!Serial data valid : '------- 1 I ENABLE 1,2. J DATA OUT FIGURE 2. Normal Operation 6-332 r:.==-= OUTPUT INPUT STROBE S/H CONTROL TRIG LOAD DELAY OUT MUX ADDRESS OUT Ott (MSB) DIO D9 DO SERIAL OUT +FS StH OUT -FS ENABLE 1,2,3 DATA OUT FIGURE 3. Overlap Operation ELECTRICAL SPECIFICATIONS Typical at 25°C and rated power supphes unless otherwise noted MODEL TRANSFER CHARACTERISTICS Resolution Number of Channels Throughput Rate SDM856JG SDMS56KG SDMSS7JG SDM857KG TVP 12.1 "~"'r"T··· UNITS Bits DYNAMIC ACCURACY Sample Hold Characteristks Aperture Time Feedthrough (IOV step) Amplifier CMRR at 60Hz G::= 2 Amplifier CMRR at 60Hz G '" 1000 AmpJifter Overload Recovery Time kH, kH, kH, kH, OUTPUTS Digital Output Coding o to +5, ±S, ±IO Serial Output Coding ADC Conversion Time l '» Clock Frequencyl") DelaylMSDMSS6 ±20 ±. 1,,'0"""' 5 x 10'11100 I 2 I v ClllpF ClllpF '"±50 ±1.1 oA nArC ±20 oA ±O.6 ±O.I nA/"e ±. ",V/"C 400 j.lVrms dB dB mV 90 97 ENVIRONMENTAL Specification Temperature Range Storage Temperature Range n 10 1" so oA -6.0 J +2.500 ±S -6.' +, JG +2.510 ppm/"C -6.' ±O.048 ±O.024 ±O.II ±O.OS ~ ofFSR(~) ±O.024 ±O.O12 % of FSR % of FSR ±O.012 % of FSR % of FSR % of FSR ±O.024 ±O,O12 ±O.I ±O.I ±O.0007 ±O.OOO7 ±OJ)()I V ppmf"C % of FSR % of FSR % of FSR nse, mV dB dB 9' 200 "' Binary, Offset Binary. Two's Complement Noo""r;~ 520 15 30 "'I (NR~' j.lse, kH, j.lse, j.lsec ±14.5, +4.75 +15, +5 +15.5, +5.25 I I +10 mA mA mA mA mA mA mW mW ,,)5 +120 +15 -40 +120 1300 1400 0 +70 "C "" +85 "c TABLE I. Electrical Specifications mV +2.490 100 ±IA 90 Delayl~ISDM857 POWER REQUIREMENTS Rated Voltage for Specified Accuracy Quiescent Current SDMS56 +15 SDMSS6-15 SDMSS6+5 SDMSS7 +15 SDMSS7-IS SDMSS7 +5 Power Dissipation SDMSS6 Power DissipatIOn SDMSS7 1000 G "" 2 + 20kn/R", KG Differential Linearity{G = I) JG MAX .1 ACCURACY Throughput Accuracy o to +5V, ±5V ranges JG o to +5V, ±SV ranges KG o to +50mV, ±sOmV JG (SDM857 only) o to +SQmV, ±SOmV KG (SDM857 only) Linearity (G "" I) KG Quantizing Error System Gain Error(1) System Offset Error l !! Power Supply Sensitivity + J5V Power Supply Sensitivity -ISV Power Supply Sensitivity +SV ppm/"C ppml"C ppm of FSR/"C +" ±20 ±2 SDM856ISDM857 MIN ANALOG INPUTS ADC Gain Ranges Input Voltage Range Absolute max without damage For linear operation Input Impedance, OFF Channel Input Impedance, ON Channel Amplifier Characteristics (SDMSS7 only) Gain Range Gain Equation Input Bias Current at +25"C o to +70"C Offset Current at +2S"C o to +70"C Input Offset Voltage Input Offset Voltage Drift (G > 100) Output Noise (10Hz - 10kHz) G::= 100, Rs=.sooO Common-mode Rejection (DC) G = 2 G == 1000 Sample/Hold DC Characteristics Input Impedance Bias Current Output Offset Voltage REFERENCE VOLTAGES Positive Output Positive Output Drift Negative Output Negative Output Drift TEMPERATURE STABILITY System Accuracy Driftl41Unipoiar System Accuracy Drift l4 )Bipolar Linearity Drift NOTES: I. REXI' is the external gain-setting resistor. (Connect between pins I and 80,) 2, FSR means Full Scale Range, e.g., FSR is lOY for ±5V range. 3. Adjustable to zero. 4, Includes gain, offset, and linearity drifts. 5. Conversion time and clock frequency can be externally adjusted between 13p.sec (f = 1.0MHz) to IIOJ,lsec (f = 118kHz). (Conv. times are for 12-bit resolution.) 6. Can be externally adjusted from 3IJSec to 300lotsec. 0; % of FSR %/%.l.V %/%.l.V %/%.l.V 6-333 DIGITAL INPUT SPECIFICATIONS DIGITAL OUTPUT SPECIFICATIONS Address Inputs (AO- A3) One standard LSTTL load. positive true Parallel Data Address Coding 4-bit binary Load One standard LSlTL load. positive true, address loaded on positive edge. Clear One standard LSTTl load. negative true, low level clears latch. One standard LSITL., load. high-to-low transition triggers TRIG One standard LSTTL load. a negative going edge initiates the the delay timer. AI D conversion. . Busy Enable Mux Enable 2 TIL compatible. 2jJA input current, Logic 0 enables multiplexer 2 (channels 8-15). ~ "20 5 standard TTL loads. pos.itive true. 3-state. Busy 5 standard TIt.: loads. low during AI D conversion. 5 standard TTL loads. high during AI D conversion. 3-state Clock Out 5 standard TTL loads. for synchronizing serial out data (see Timing Diagram). Address Outputs 5 standard TTL loads. positive true Delay Out 5 standard TTL loads. high during delay period. triggered by S'ir'O'beinput. Sin Diff 5 standard TTL loads. high while addressing channels 0-7. low while addressing channels 8-15. . TTL compatible. IO~ maximum input current. Logic 0 = Hold ~ode. Logic I = Sample (track) mode. ~ iiTI ~~~a:~a~~~~~t~STTL load,;, a I,O~ level ena~les the S, H Control ·f 2 standard TTL loads. positive true, NRZ. time serial data output beginning with DII (see Timing Diagram). . (AO- A3) Short Cycle One standard LSTTL load. logical I for 12-bit resolution _ _ _ _ _ connect to "8-bit" or "to-bit" for 8- or lO-bit reso)uti .! g ! e i= 1l' ~ <5 ~ 21------+---- ~« I en 10 100 1000 FIGURE 5_ Output Noise vs. Amplifier Gain FIGURE 4. Nonlinearity and Settling Time vs_ Amplifier Gain THROUGHPUT ACCURACY AND TIMING RELATIONSHIPS System Gain I 2 10 100 500 V/V 856 857 857 857 857 Throughput Rate System Accuracy only only only only only Delay Time (Channels/sec) (/Lsec) KG JG Norrnal Overlap ±O.O24% ±O.024% ±O.035% ±O.08% ±O.I% ±O.048% ±O.048% ±O.O6% ±O.II% 25k 18k 18k 29k 29k 29k Ilk 2.6k 9k 2.4k ±O.15% Normal Overlap 15 30 30 90 390 35 35 35 90 390 TABLE II. Throughput rate and delay time vs gain for normal and overlap modes. Full Scale Input Range IOV IV O.IV 20mV ADC Range Amplifier Gain -10 t,o +10 o to +10 o to +10 o to +10 2 10 100 500 Amplifier 1M uliiplexer Settling Time (jJSec) Resolution 2.44mV* 244/LV 24.4/LV 4.88/LV· To ±O.2% 8 12 65 320 To ±O.05% 10 14 80 390 To ±O.OI% 20 24 90 450 TABLE III. This table shows the delay timer setting required to allow fonhe settling time of the instrumentation amplifier to the accuracies specified_ *Depends on desired SIN ratio. In overlap, when the Amplifier / Multiplexer settling time is less than the ADC conversion time, set the delay timer for the ADC conversion time plus the sample and hold acquisition time (lOlLS). When the Amplifier/ Multiplexer settling time exceeds the ADC conversion time plus the S / H acquisition time, set the delay timer for . the Amplifier/Multiplexer settling time. 6-334 CONNECTION DIAGRAM 0 0 0 0 0 0 0 0 0 0 0 0 1-025 0 0 0 0 0 0 0 .. .. o I 0 79 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 800 0 0 0 0 0 65 63 0 0 0 49 0 0 o 39 o· . . 40 41 0 42 0 • 15YPC ff 0 0 0 IJ;F 0 0 ~64° 59 57 55 0 +15VDC 0 0 0 0 0 0 0 0 0 0m;F, Ceramic J t tI~F 18Mn ~ E +5VDC +15VDC IOkn 15VDC 100nf t!on Unipol Offset Bipolar Gain 0 Offset 0 0 0 0 NOTE' Mllititurn potentio~eters with IOOppm "C or better TCR's are reeom mended for minimum drift over lime and temperature . FIGURE 6. Connection Diagram for power supply decoupling and gain and offset adjustment. PACKAGE AND PIN CONFIGURATION PIN CONNECTIONS Pin '1 2 ·3 4 5 MECHANICAL SPECIFICATIONS .fi!!. IA Gain Adjust Mux Out High Amp In High CH7 CH6 CH5 CH4 CH3 CH2 10 CHI II CHO 12 Mux Enable 2 13 A3 Out 14 Single; Differential 15 A2 Out 16 AI Out 17 AOOut 18 Clear 19 AO In 20 Alln 21 A21n 22 A31n 23 Load 24 Busy 25 Dig. Common 26 Short Cycle 27 IO-bit Resolution 28 8-bit Resolution 29 DO (LSB) 30 DI 31 D2 32 D3 33 D4 34 D5 35 D6 36 D7 37 D8 38 D9 39 DIO 40 DII (MSB) 41 42 43 i5Ti Enable Busy Enable 44 DII 45 46 47 48 49 50 51 52 53 54 55 56 57 58, 59 60 61 62 63 ~Out 64 65 66 67 68 '69 70 71 72 73 74 75 76 77 78 .79 .80 *For SDM857 only. Make no connection 5.lmth (020") 1.3mm -11-(0.05,,) Busy ~ bj""""""'" "', 00000000000000000000 TRIG Delay Adjust Strobe +5V Supply Clock Rate Adjust Clock Out Serial Out Enable 3 Enable I +2.5V Ref Out t 42' '80 .79 41' TOP VIEW .2 .1 0 L 40' 39. .... 0 .... 0 0 0 0 0 0 .... 0 .... 0 0 0 .. 0 0 0 0 0 0 0 . . . . 0 .... j 38.lm (1.50 ") ~l 2.5mm -11- 0.10")typ All Pins t2.5mm (0.10") Enable 2 0 .... 0 0 0 0 t 27.9mm (1.10") +2.5V Ref In 20V Range BPO lOY Range -6.4 Ref Out S/H Out Analog Common -15V Supply +I5V Supply S/H Control S/H Offset Adjust S/H Input IAOut CH8/RETO CH9/RETI CHIO/RET2 CHII/RET3 CHI2/RET4 CHI3/RETS CHI4/RET6 CHI5/RET7 -43.2mm(1.70")-1 1 I Iii -u- I O.5lmm dia. (0.02,,) i t ~~~08~~ t MATERIAL: Ceramic WEIGHT: 32 grams (1.2 oz.) PINS: Pin material and plating composition comform to Method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2) MATING CONNECTOR: 2350MC (Set of four 20 pin strips) Mux Out Low Amp In Low fA Gain Adjust in SDM856. 6-335 SDM858 BURR-BROWN@ IEaElI Low-Level Input, 12-Bit DATA ACQUISITION SYSTEM FEATURES DESCRIPTION • HIGH ACCURACY WITH LOW lEVELINPUlSlGNAlS The SDM858 is a 'complete 'S: or l6-channel data acquisition system in a compact 4.6" x 3.0" x 0.375" metal case. This system is specifically designed to give high accuracy with low level analog input signals. A; 'built-in, high· quality instrumentation amplifier allows input signal ranges of ±5m V to ±IOV. It is especially useful with thermocouple and strain gage inputs since it yields only±O.025% (of Full Scale Range) error at a gain of 100. This expandable module accepts either 16 singleended or 8 differential inputs and converts the multiplexed ,data signals into 12-bit digital words with an accuracy of ±O.025% at throughput rates of up to 8000 samples ~er second. • lOW COST • SAVES DESIGN TIME • RELIABLE -70"C BAKE FOR 160 HOURS • SAVES SPACE • FLEXIBLE • FOUR MODES OF OPERATION IA Input ~.r-~ Glln IA SIH Select Output Input SIH AOC IIU\puI Input tlBJ 8....-----. 12·BIt AID Cnnr Olgllli Output Serlll Output Cia Output TIming Adlust Slngl..endld/Olll1ll'1lntlll Mode Select SIIIIII Stl'1lbe Internallonal Airport Industrial Park· P,O. Box 11400 . Tucson. Arizona 85734 . Tel. 1602) 746·1111 • Twx: 911).952·1111 • Cable: BBRCORP • Telex: 66-6491 PDS-406 6-336 featunng 24~sec conversion time and 0.01% accuracy. Stable thin-film networks and current switching are used to assure linearity over wide temperature ranges. SYSTEM DESCRIPTION The SDM858 contains all the components necessary to multiplex and convert ±5mV to ±IOV analog data into equivalent digital outputs yielding resolutions of 2.4~ V to" 4.88mV. It has been designed specifically to acquire and convert low level signals. The throughput sampling rate is 8kHz for 12-bit resolution at a gain of 10. This system contains an analog multiplexer (which can be connected for l6-channel single-ended or 8-channel differential signals), instrumentation amplifier, sample/hold circuit, 12-bit successive approximation A/D converter, and control and timing logic. The amplifier and sample/hold are not internally connected, allowing maximum application flexibility. These systems can be expanded almost without limit using BurrBrown's MPCI6S, MPC8D, MPC8S, and MPC4D monolithic mUltiplexers. The SDM858 is designed to be mounted on a printed circuit card. The only requirements for system operation are input signals, power, and the interconnection of system components into the desired operating configuration. The components of the SDM858 are shown in Figure I and described in the following paragraphs. ANALOG MULTIPLEXER Two, one-of-eight, CMOS analog mUltiplexers are used to allow user selection (by external jumpers) of 16 singleended channel or 8 differential channel operation. In 16channel operation the multiplexer may be used in a pseudo-differential mode by connecting the amplifier inverting input to a common, remote, signal ground. Channel selection is by a 3- or 4-bit binary word stored in a presettable address counter. INSTRUMENTATION AMPLIFIER The SDM858 instrumentation amplifier has been optimized for low drift and high accuracy with analog inputs as low as ±5m V full scale. Input noise and thermal feedback have been minimized to improve accuracy when amplifying such signals as thermocouple and strain gage outputs. The gain is programmed with an external resistor connected between pins 26 and 27. Gain may be selected from I to 2000. The amplifier used in the SDM858 is the Burr-Brown Model 3630. More information is available in the 3630 product data sheet. ADDRESS COUNTER A 4-bit binary address counter is connected to the multiplexer. This counter may be externally loaded, cleared, clocked, or enabled. The address outputs are brought to connector pins for convenient system control. DELAY TIMER The delay timer is provided to allow for the settling time of the mUltiplexer, amplifier, and sample/hold circuits prior to start of conversion. The delay time is adjustable over a wide range by an external potentiometer and/ or external capacitor. This allows for the longer settling time of the instrumentation amplifier at high gains. The timer is adjusted at the factory for optimum operation at a gain of 100. CONTROL LOGIC Delay and ADC trigger functions are edge-triggered and gated. Counter control functions are synchronous with the counter clock which is internally connected to the delay timer output. . CHANNEL EXPANSION The number of analog input channels of these systems can easily be increased using Burr-Brown's CMOS multiplexers. These latch-free devices contain internal binary decoding, TTL or MOS logic levels, and may be integrated into a system with minimum external logic. The following devices offer a variety of input channel configurations. 4-channel differential MPC4D 8-ehannel differential MPC8D 8-ehannel single-ended MPC8S l6-ehannel single-ended MPCI6S SAMPLE/HOLD The sample/hold circuit is a complete monolithic unit featuring buffered output and maximum acquisition and aperture times of 52~sec and 200nsec. Input, output, and mode control functions are brought to separate connector pins. This allows maximum system flexibility for performing such functions as automatic gain ranging with no loss of aperture time. ANALOG-TO-DIGITAL CONVERTER The ADC is a ceramic-packaged, 12-bit converter 6-337 SYSTEM PERFORMANCE The SDM858 can be configured to continuously sequence through all analog channels, to accept random addresses or to sequence through all analog channels on command from an external trigger. The STATUS signal, pin 30, is connected to the STROBE input of the delay timer, pin 58, for normal program sequencing with a minimum throughput sampling rate of 2kH2: for 12-bit resolution and a gain of 100. A throughput rate of 8kHz with 12-bit resolution can be achieved for a gain of 10 by decreasing the delay time. By using "overlap" programming, the settling time effects of the analog multiplexer and instrumentation amplifier can be reduced slightly. Overlap programming is accomplished by connecting the STATUS signal, pin 30, to the STROBE input of the delay timer, pin 19, and extending the delay time. The internal logic will then select analog channel (n + I) while channel n is being converted. MUX ~W I r 1 CHO 3 CH1 CH2 CH3 4 5 6 eH. o-.r---, " MUX OUT LO IA IN HI IA IN L.O 66 25 28 G2 IA 01 S;" 5/H CON OUT IN 26 27 29 51 4fb] 7 g~~: g~~ ~~ 0:::)-----1 ~~~~. g~~o ~~ ATNO . . ,5tH TAOL OUT 48 50 40 CLOCK OUT 37 Hold 17 :~ .. 33 I a ~ : g ~ 41 ~ ! LS81~ 49 SHORT CYCL.E Ai ~i~:::::j:::~h. A1 I' ;: ! RTN6 eH1. 68 FlTN7 eH1S 67 Af OUT ;~~11 ~~ : ~ .m"" - , Inttrunwn1.tlon Amplifier FlTN3 eHU 71 FlTN4 CH12 70 RTN6 CH1369 se RIAL 46 30 SiT~TUS, 0....,...................., 52 EXT GAIN ADJUST A:' :~ DELAVADJUST1 [)ELAY ADJUST 2 <>.:=====~n~ 21 0 56 ~ 59 DELAY DELAY 0iJT OUT 75 SIC 64 MUX 23 NEG 24 pas 54 .PO SELECT ENB REf OUT AEF OUT 20 67 1 Ace Aoe +15 TRIG 76 -15 l"R'iG vee vee 3. 2 ANA ",G COM COM FIGURE I. Detailed Block Diagram of SDM858. SPECIFICATIONS ELECTRICAL Typical at +2S'C with ±ISVDC and +SVDC power supplies unless otherwise noted. MODEL TRANSFER CHARACTERISTICS Throughput Rate. min G=I G= 100 G = 1000 G = 2000 Resolution Number of Channels ANALOG INPUTS ADC Voltage Input Ranges Amplifier Gain Range Amplifier Gain Equation Max. Input Voltage without Damage Mai<. Input Voltage for Multiplexer Operation Common-Mode Input Voltage. max G=I G>I Input Impedance SDM8S8 8kHz. 12S"scc/channel 2kHz. SOO"sec / channel 1kHz. Imsce/channel SOOH·z.2msec/channel 12 bits 16 singt.,.ended or pseudo-differential/8 differential o to +SV. 0 to +IOV. ±2.SV. ±SV. ±IOV I to 2000 G = I + (40kfi/ R.xT)(11 ±16V ±10.24V ±IOV ±5V 100Mfi. IOpF OFF channel lOOMfi, 100pF ON channel'" Bias Current +2S'C O'C to +70'C Differential Bias Current Differential Bias Current Drift Amplifier Input Offset Voltage, max Amplifier Voltage·Offset Drift. max vs Supply. max vs Time Amplifier Input Noise Voltage 0.01 Hz to 10Hz 10Hz to 1kHz Currerit 0.01 Hz to 10Hz 10Hz to 1kHz' Amplifier Output Noise (G = 100. Rs = SOOn) 0.01 Hz to 10Hz 10Hz to 10kHz Thermal Feedba~k'" Channel-to-Channel I np~t Voltage Error'" ±IOnA. typ; ±30nA. max ±20nA, typ; ±60nA. max ±IOnA, typ; ±30nA. max ±O.4nA,"C typ; ±LOnA/"C. max ±25 ±(200jG)"V ±O.7S ±(lOIG)"V "C ±2 ±(200jG)"V V ::+::2 ±(40,G)"V mo L2"V, p-p LO"V. ,ms 70pA. p-p 20pA. rms 0.12mV. p-p 0.32mV, rms O..Ip.V V1nrU ! ±5,.,y 6-338 . ACCURACY'" System Accuracy, max (Gain - 1(0) Linearity Differential Linearity (Gain = 1(0) Quantizing Error Gain Error Offset Error Power Supply Sensitivity ±o.025% FSR'" at 2kHz throughput rate ±[1/2 + (G/2400)) LSB ±1/2LSB at 2kHz throughput rate ±1/2LSB Adjustable to zero Adjustable to zero ±o.005% FSR/% change of supply voltage STABILITY OVER TEMPERATURE System Offset Drift, max (Z.N ~ 4000) G= I G=IO G = 100 G = 1000 G = 2000 System Gain Drift,!1I max G= I G = 10 G= 100 G = 2000 ADC Offset Drift (U nipolar) ADC Offset Drift (Bipolar) ADC Linearity Drift ±5ppm of FSR/,C ±7ppm of FSR/,C ±30ppm of FSRj"C ±300ppm of FSRj'C ±600ppm of FS R j"C ±35ppm of readingj"C ±80ppm of readingj"C ±85ppm of readingj"C ±85ppm of reading/'C ±3ppm of FSR j"C ±15ppm of FSRj"C ±3ppm of FSRj"C DYNAMIC ACCURACY Sample/Hold Aperture Time Sample/Hold Acquisition Time (to 0.025%) Error for Full Scale Transition Between Successively Addressed Channels G= I G = 100 G = 1000 G = 2000 Amplifier CMRR, min; IkO Source Imbalance G = I, f= 60Hz G=I,f=lkHz G = 10, f = 60Hz G;;' 100, f= 60Hz Channel Cross Talk Sample/Hold Feedthrough Sample/Hold Decay Rate, (+70'Q 125nsec, typ; 200nsec. max 26l'sec. typ; 52l'sec. max ±I LSB at 8kHz ±I LSB at 2kHz ±2LSB at I kHz ±4LSB at 500Hz 86dB 70dB 96dB 1000B -80dB at 2kHz. OFF channel to ON channel ±o.007% of 20V II'V / I'sec, typ; 101' V/ I'sec, max OUTPUT Output Coding (Complementary) Unipolar straight binary. bipolar offset binary. binary two's complement Adjustable to zero Adjustable to zero 241'sec typ, 30l'sec max 470l'sec nominal. externally adjustable'" +I5VDC ±3% at +65mA. ripple < 5mV. rms -15VDC ±3% at -75mA. ripple < 5mV"rms +5VDC +5% at 300mA. ripple < 25mV. rms Gain Error/81 Offset Error'" A/D Conversion Time Delay POWER REQUIREMENTS ENVIRONMENTAL Operating Temperature Storage Temperature Relative Humidity O"C to 70"C -25"C to +85"C 95% noncondensing NOTES: J. With 2. 3. 4. S. 6. 7. RUT between pins 26 and 27. With multiplexer output connected to IA input. Drift due to internal heating. Error due to thermoelectric effects of dissimilar metal junctions. No missing codes guaranteed. FSR means full scale range. Exclusive of gain resistor drift. 8. Gain and offset controls are located in the module. The adjustment ranges are ±O.l% FSR for gain and ±o.I% FSR for offset. 9. Adjustable to 10 seconds with external capacitor, to 50",sec with an external resistor. 6-339 DIGITAL INPUT Address inputs One standard TIL load, positive true LOAD ENABLE CLEAR ENABLE STROBE & STROBE 'One standard TTL load. negative true, addres!o. loaded with strobe Inputs. One standard TIL load, negative true, address cleared with strobe inputs. One standard TTL load. STROBE and ~ edge trigger the delay timer and clock the address counter. STROBE mU!o.t be hl~h to enable ~ and ~ must be low to enable STROBE Two standard TTL loads. po!oitive true, logic "0" allow~ the Strohe inpub to trigger the delay timer. but COUNT ENABLE prevent!. the MUX address counter from bemg clocked. One standard TTL load, a positive going edge at TRIG mitlate!> conver~lon. a negative gomgedgeat TRIG initiates conversion; T'R.1lr must be "0" to enable TRIG; fRIG must be "I" to enable TIn<:'i. One standard TTL load, logic "I" for 12-bit resolution, connected to the N + I bit output for N bit ADC TRIGGER SHORT CYCLE resolution. MULTIPLEXER E~ABLE MULTIPLEXER E~ABLE S D SELECT Two standard TTL loads, logic "I" enables multiplexer output and logic "0" turns off all channels. Two standard TTL loads, logic "I" enables 16-channel single-ended operation and logic "0" enables 8-.channel differential operation. DIGITAL OUTPUT LJata outputs Parallel BI. Bl. . B12 SERIAL OUT Address outputs DELAY OlJl and DELAY OliT CLOCK OcT STATUS 2 Standard TTL loads. negative true. 2 Standard TTL Joad~. negati"e true. time serial data output beginning with BJ. 5 Standard TTL loads. positive true. 4-blt binary code, Internal 2kn pull-up resistors. 5 Standard TTL loads high (low) during the delay period, trtggered by STROBE and STROBE InpUb 5 Standard TTL loads for synchroniling sertal out data, 5 Standard TTL loads. high during the A 0 comemon, PIN DESIGNATIONS +I5VDC ANA COM CHO IN CHI IN CH21N CH31N CH41N CH5 IN CH6lN CH71N MUX OUT HI LOAL> ENABLE COUNT ENABLE A80UT A40UT A20UT ~ DELAY OUT STROBE ADCTRIG DELAY ADJUST I RI NEG REF OUT POS REF OUT IA IN HI G2 GI JA IN LO IAOUT STATUS BI MSB B3 B' B7' B9 BII SERIAL OUT +5VDC I 2 3 4 , 76 75 74 73 72 6 7 71 70 69 9 10 II 12 13 14 68 , I' 16 17 I' 19 20 21 22 23 24 2' 26 27 2' 29 30 31 32 33 34 3' 36 37 3' 67 66 6' 64 63 62 61 60 '9 58 57 '6 " 54 '3 '2 '1 50 49 48 47 46 4' -15VOC SID SELECT CH' IN (RTNO) CH91N (RTNl) CHIO(RTN2) CH II IN (RTNJ) CH 12 IN (RTN4) CH J3 IN (RTN5) CHI41N (RTN6) CHI5 IN (RTN7) MUX OUT LO CLEAR ENABLE MUX ENABLE A81N A41N A21N AI IN DELAY OUT STROiiE ADCTRIG DELAY ADJUST 2 R2 BPO COMP IN GAIN.-ADJUST S;H IN 51H OUT SHORTCVClE SIH CONTROL Bi (MSB) 44 B2 B4 B6 43 42 41 40 39 B' BIO 812 LSD CLOCK Qur DIG COM MECHANICAL INCHES Li==Y-f o::=Q I =Q lw"1 ~ (1j" A WI DIM I I RF t~""""""''''''':'''''''''''''''''::r 1 J J -jTrl ........................................... L • I L -IMI 'U I CASE MATERIAL: Insulated Steel CONNECTOR PINS: Gold Flashed WEIGHT: 145 grams (5 oz.) '" no , n, , no , ''" ,c w '" '" , '" 3980 ~ 7671 .380 '" '" D" ,n '" ,,, '" 300QASIC 1480 1980 MA> 1173S 7569 ." Q M,. 3020 ~ on MILLIMETERS 116.33 100 BASIC M I [11111111111111111111.1111111,11111111 r.t:l=:r:Pc O-+- MA> 4620 G , j G--!I-- 4590 2980 l ~ MIN , , '" ,D ,,, '" '" '" A 0.53 254BASIC 1067 1219 0.43 n, 762SASIC 6.85 1520 3759 m '" ", ,,, ", ,,, 5.97 An 4020 10109 ''" '" '"' '" '" 2020 2362 5029 ''" '" 3661 ." '" '" '" 10211 '" '" 2464 5131 Pin numbers shown for reference only. Numbers may not be mark.ed on package. NOTE: Leads in true position within .OW (.38mm)R at MMC at seating plane, 4-40 thread, 190" (4.83mm) min. depth. 2 places, MOUNTING INSTRUCTIONS: (Mounting flush on PC Card.) I. Use strip connectors or two l4-pin and three l6-pin low profile IC sockets (shipped with each unit). 2. Use 4-40 x 3/ 16" (4.8mm) LG Pan HD Hardware to secure the SDM858 to PC Card. 6-340 TYPICAL PERFORMANCE CURVES AMPLIFIER COMMON-MODE REJECTION VSSOURCEIMPEDANCEIMBALANCE AMPLIFIER COMMON-MODE REJECTION VSSOURCEIMPEDANCEIMBALANCE 120 120 _ - - - - - - , . - - - - - - . , ," G-IOO ..- """ ~ Q ....t; f=DC ~=~ z 100 ;:;J ".... • Q G=I 0 ~ 0 ~ 80 :Ii :Ii 0 u 60 60 . I - - - - - -.... IO------~IOO I SOURCE IMBALANCE (kn) 100 SYSTEM NOISE VS AMPLIFIER GAIN AMPLIFIER SETILING TIME VS GAIN 1000 10 SOURCE IMBALANCE (kO) .----"'T""---...,..---'"7""71 100 ,...---"T""---"T"---""'T'-, Rs = soon Bandwidth = 30kHz i ~ 10 ~--:-----t------+----:~-"-~-t ; 320~--------+---------r---~~~~-I :Ii i= "~ E til 32~ ___ I ~ 10 ___ ~ 100 ___ ~~ 0.1 1 .. - -....."--,.l.O----.. 1001o...----1~000~2~000 1000 2000 GAIN (V/V) AMPLIFIER GAIN (V IV) AMPLIFIER OUTPUT OFFSET VOLTAGE DRIFT VS GAIN AMPLIFIER NONLINEARITY VS GAIN 0.01 r----~r-----""T"---::Il,.....T""~ 100r----...,..---""'T'---..,.~ Rs = Source Impedance 2 ~ ~ 0.003.---------+-----~~+_~~----~-f ~ )0- f- Max 02 ~ +-..~____}-________~~ ~ QOOI . .___T.Y.P__ ~ z 0.0003 LI----":'IOI:----":'100!:----~1O=00-::2OOO~ 10 GAIN (V/V) 100 GAIN (V/V) 6-341 1000 2000 SHe80 BURR-BROWN® IElElI Fast Ie SAMPLE/HOLD AMPLIFIERS FEATURES • 14-PIN DIP PACKAGE • 10)Jsec ACQUISITION TIME • COMPLETE WITH HOLDING CAPACITOR • .:to.Ol% ACCURACY • ·25°C TO +85°C TEMPERATURE RANGE (SHC808M) Ultra-linear performance and fast acquisition speeds - that's the combination that makes the SHCSO models ideal for your demanding data acquisition and control applications. The SHCSO acquires and holds up to ±lOV analog signals to an accuracy of ±O.OI% of full scale. Acquisition time is J2~sec for a 20V step of lO~ec for a IOV step. High performance results from the use of internally compensated circuits normally found only in larger, more expensive sample/holds. Two models· give you a choice of operating temperature range: the SHCSOKP(O°C to +70°C) in all epoxy package, also the SHCSOBM (-25°C to +S5°C) in a hermetic metal case. You'll find these units well suired for: Data Acquisition Systems Data Distribution Systems Analog Delay Circuits Pulse Amplitude Modulation Circuits Waveform Amplitude Measurement Internalional Alrporllndustrial Park - P_O_ Box 11400 - Tuuon. Arizona 85734 - Tel. (6021 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 PDS-348 6-342 Printed in U.S.A. July. 1978 SPECIFICATIONS Typical at 25°C with rated supply and 1000pF internal capacitor unless otherwise noted. • EPOXY ECHAILICAL PACKAGE ELECTRICAL MODELS SHC80KP SHC80BM Units INPUT ANALOG INPUT ...-I~2.7mm 20.3mm· (0.5") IO .S " ) . ~ -K SHC80KP :J "."-~ Pin 1 ' Voltage Range Maximum Safe Input Signal Impedance Bias Current ±IO ±is lOB II 5 400 DIGITAL INPUT (TTL/MaS Compatible) Mode Control "Sample" - Logic "1" "Hold" - Logic ,"0" Voltage +5V Logic Supply 2 < e < BV 0< e < O.BV current Voltage + I SV Logic Supply 5.5 T :-11--20k!l 220!l . 10k!l ~.~~-S~itch ~ +5 +4.75 to +1 S.S I V V rnA S20Pl r~ Driver 1.5k!l Q) +5 +4.75 to +15.5 I Logic A6clirn SU(!)@/C sation ±IS ±14.S to ±IS.S +20 10.30") V;15V TEMPERATURE Rated Voltage Range Current +~V /ls ±IO '5 0.5 7.62mm o o----r- TOP VIEW ~2-5kU Offset Adj. ,.( Voltage Range (min) Current Range (min) Impedance· Rated Voltage Range Current 0 00 0 Connection Diaaram % of Input Step mV OUTPUT ANALOG OUTPUT Specification Storage o 7 S Metal Pin Material and plating Composition conform to Method 2003 (solderability) of MiI-5td-8S3 (except paragraph 3.2) ns ns /lS 14 oo-~ Ca~: kHz /ls ll :)0 0 1 V//ls 10 12 '0.005 2 O.46mm 10.01S") di •. 0 : DYNAMIC CHARACTERISTICS Full Power Bandwidth(2) Output Slew Rate Aperature Time Aperature Time Jitter Acquisition Time to 0.0 I % 10V Step (max) 20V Step (max) Feedthrough in Hold Mode Charge Offset (max) Sample "to Hold Transient Peak Amplitude Settling to ImV 5.1mm 10.20") _Pin14 2.54mm ACCURACY ORIH Gain Drift Offset Drift Droop Rate(I) @700C(max) @ B50C (max) '"]'J- ~13.2mm SHC80BM '0.01(3) 1000 +1.0 0.01 2 +In . -Wv M~e ~ .~ • Control Com. N/C .... ~ S!. C Output Ext. ~j--..-J Optional Ext. C Note: No connection should be ~de to pins 11 & 5. Pin 8 is not internally connected. ( I ) Ma double evet" I oOe over tern perature. ( 2 ) Small si nal bandwidth 750kHz. (3) '0.015 including feed through for SHC80KP. 6-343 DEFINITION OF SPECIFICATIONS DYNAMIC NONLINEARITY ACQUISITION TIME This is the total nonadjustable input-to-output error. It includes errors due to throughput nonlinearity, droop, thermal transients and feedthrough; in short, all errors Utat cannot be adjusted to zero for a 10 volt input change after a IOllsec acquisition time and a one millisecond hold time. Offset errors may be adjusted to zero by the offset control, but gain errors must be removed by a gain adjustment elsewhere in the system. (Gain adjust not included in SHC80.) the time required for the output to settle to its final value within a given error band when the Mode control Is switched from "hold" to "sample". See Fillure 2. GAIN ACCURACY APERTURE TIME The time required to switch from "sample.',' to "hold". It is ,measured from the 50% point of the mode control transition to the time at which the output stops tracking the input, The difference due to amplifier gain errors between INPUT and OUTPUT voltage,when in the "sample" mode. Sample rI' MOde. contr~ DROOP RATE I I t The voltage decay at the output during the "hold" mode due to storage capacitor. FET switch leakage currents, and output amplifier bias current. Analog Input ~ I I Sample-to-Hold Switching Transient .BI Charge Offset I ! -If.J FEEDTHROUGH The amount ofinput voltage change that appears at the outpHt when the amplifier is in the "hold" mode. THROUGHPUT - NONLINEARITY The total charge offset and gain nonlinearity. i.e., the inac' curacy due to these two errors that cannot be corrected by gain and offset adjustments. Throughput - nonlinearity is specified over the 20 volt input range. Acquisition Time FIGURE I. Definition of Specifications. THROUGHPUT OFFSET I; : :1 I I The sum of sample offset and charge offset. CHARGE OFFSET The offset that results from charge transferred from the holding capacitor to the gate capacitance of the switching FET~ This charge is partially restored by a special compensation circuit when the unit goes into the "hold" mode. -'1 ffi ~~ 0.005;1-o---I:4-~~6--~S~-~10:--"'1~2 0- Typical Acquisition Time 1 OV Step. lI'sec) FIGURE 2. Acquisition Time vs. Fun Scale Range Error. OPERATING INSTRUCTIONS a max TCR or 150 ppm/oC as shown in the Connection Diagram. and adjust the offset with the input grounded. During the adjustment. the sample/hold,should be switching continuously bet~een the "sample;: and the "hold" mode. Adjust the error to zero when the unit is in the "hold" mode. This procedure insures that charge offset as well as amplifier offset error will be removed OPTIONAL EXTERNAL CAPACJoTOR SELECTION The value of the external capacitor determines the dropp. charge Offset, and acquisition time of the sample/hold. Both droop and charge offset will vary linearly with capacitance from the values given in the specification table. Figure 3 shows the behavior of acquisition time with added external capacitance. The behavior of droop with external C is determined by: dv (0.5 x 10-9 ) , mV Droop=dt"= SOOpl' +cextppiiiS 160 U !• so I - -+-20)lnput Step" 40 E Capacitors with high insulation resistance and low dielectric absorption, such as teflon or polystyrene shou,ld be used as storage elements' (polystyrene should not be used above +85 0 C). Care should be taken in the printed circuit layout to minimize leakage currents from the capacitor to minimize droop errors. i= 20 ~ ....... c 0 ~, 10 8" « 5 ~ .001 V / V ~ ~ 10V Input I - - .002 .004 Step .OOS .016 .032 .064 .12S External Capacitor (p.F) OFFSET ADJUSTMENT FIGURE 3. Acquisition Time vs. External Capacitor. Connect a 2k ohm to 5k ohm multi-turn potentiometer with 6-344 LOGIC THRESHOLD PROGRAMMING Pin 10 is normally connected to the logic return and pin 9 to a positive logic supply. The logic threshold is determined by the 4.3kQ and 10kQ resistors shown in the connection diagram. The threshold is 1.5V for logic operated on a +5V supply and 4.5V for a +15V logic supply. If it is not convenient to connect a logic return and supply to the SHC80, pin 10 may be connected to the analog return and pin 9 to +15V for 15V logic or to +15V, through a 27kQ resistor for 5V logic. The mode control switching transistors have sufficient current gain to allow the mode· control pin to be driven from MOS logic. The mode control polarity may be reversed by connecting an externally-derived threshold voltage to pin 3 and by connecting pins 9 and 10 to the mode control source. APPLICATIONS DATA ACQUISITION SYSTEM SIMULTANEOUS SAMPLE/HOLD The SHC80 makes an excellent device for reducing aperture time and eliminating conversion noise from high gain circuitry in data acquisition systems. When it is combined with Burr-Brown's 16 channel MPC-16S Analog Multiplexer and ADC80 A/D Converter, you have a compact 16 channel data acquisition system with 25 kHz throughput sampling rates and iO.02% (RSS) system accuracy. Time correlation of sampled data signals may be implemented by using one sample/hold for each analog signal prior to input to an analog multiplexer. The SHC80's low aperture time of 40 nanoseconds practically eliminates channel-tochannel time slew. The throughput sampling rate and the number of data channels will determine the -maximum "hold" time and hence, the worst case droop error of the sample/hold in the last channel to be sampled prior to the next "refresh" or sample/hold command. This droop error may be minimized by adding external capacitance to the SHC80 as shown in Figure 3. M~ ~ c 1 ~ 2 U 3 • 1: 4 I I • I ;t , 13 -- 1 c MAX DROOP ERROR (CHANNEL N)= (T x n)(Droop rate) I Where T = System Sampling Rate and n = number of multiplexer data channels. AID Converter - Sw~tch : . 1- - N/C -, Ext Output ~ . r- -- . . Optional External C NOTE: Pins5,8,9,10and 11 are not internally connected. (I) Small signal bandwidth is 3MHz. 6-347 i ~C-20-3 -4f-iof!'67-70-~ Analog -15V Mode Analog In Control co";,mon POWER SUPPLY Rated Voltage Range t r~ 'Offset I _ _ :Adjust: : TEMPERATURE Specification 1- 2- kn-t ,,-: +15V I'S 1" % of step change mV OUTPUT ANALOG OUTPUT Voltage Range Current Range :TOPVIEW) n. DEFI NITION OF SPECI FICATIONS DYNAMIC NONLINEARITY ACQUISITIQN TIME This is the total nonadjustable input to output error. This specification includes throughput nonlinearity and errors due to droop, thermal transients and feed through, in short, all errors that canriot be adjusted to zero for aiD volt input change after a 5 Ilsecond acquisition time and a one milli· second hold time. Offset errors must be adjusted to zero by the offset control and gain errors must be adjusted to zero by a gain adjustment elsewhere in the system (gain adjust not included in SHC85). The time required for the output to settle to its final value within a given error band, when the Mode control is switched from "hold"'to "sample". See Figure 2. APERTURE TIME The time required to switch from "sample" to "hold". The time is measured fiom the 50% point of the mode control transition to the time at which the output stops -tracking the input. ~ __ GAIN ACCURACY Mode. contro~ The difference due to amplifier gain errors between INPUT and OUTPUT voltage when in the "sample" mode. DROOP RATE The voltage decay at the output when in the "hold" mode 'due to storage capacitor, FET switch leakage currents, and output amplifier bias current. Analog .. ~ I I I I !-II-" Sample-to-Hold Switching Transient and Charge Orrset --t Ti!",--';~-:':-:':-:':-: Input i FEEDTHROUGH \\ The amount of the input voltage change that appears at the output when the amplifier is in the "hold" mode. \ , , THROUGHPUT - NONLINEARITY Acquisition Time The total charge offset and gain nonlinearity. That is, the inaccuracy due to these two errors that cannot be corrected by gain and offset adjustments. Throughput. nonlinearity is specified over the 20 volt input range. ' FeedthrouBh (change In solid line) ,~" ..,. " , * , * ,... Figure 1. Definition of Specifications. 'E:~ THROUGHPUT OFFSET c 0 The sum of sample offset and charge offSet. g~ CHARGE OFFSET .- Zit u "' "- L'1 The offset that results from charge transferred from the hold· ing capacitor to the gate capacitance of the switching FET. This charge is partially restored by a speCial compensation circuit when the unit goes into the "hold" mode. c- ~ L::==I I ~hJ~II o 1 2 3 4 5 Typical Acquisition Time 10V StePS (/lsec) Figure 2. Acquisition Time vs. Full Scale Range Error. OPERATING INSTRUCTIONS OPTIONAL EXTERNAL CAPACITOR SELECTION Diagram. The offset should be adjusted with the input grounded. During the adjustment, the sample/hold should be switching continuously between the "sample" and the "hold" mode. The error should then be adjusted to zero where the unit is in the "hold" mode. In this way, charge offset as well as amplifier offset will be adjusted. The value of the external capacitor determines the droop, ·charge offset and acquisition time of the sample/hold. Both droop and charge offset will vary linearly with capacitance from the values given in the specification table. Fig..3 shows the behavior of acquisition time with added external capacitance. The behavior of droop with external C is determined by: dv' 0.5 x 10-9 . Droop="dt = 1000 pF +C ext Capacitors with high insulation resistance and low dielectric absorption, such as teflon or polystyrene .should be used as storage elements (polystyrene should not be used above +85 0 C). Care should be taken in the printed circuit layout to minimize leakage currents from the capacitor; this will minimize droop errors. 'g 160 3. V/ 80 20 Volt w Input Step ;:!; 40 j: ~ 20 ~ j: !!1 10 ~ ::l 8 « Connect a 2k to 5k ohm multi-turn potentiometer with a TCR of 150 ppm/DC or less as shown in the Connection ~ V SteP 5 o OFFSET ADJUSTMENT / .) ' l "'" 10 Volt Input- .001 .002 .004 .008 .016 .032 .064 EXTERNAL CAPACITOR (/IF) Figure 3_ Acquisition Time vs. Externai Capacitor. 6-348 .128 APPLICATIONS DATA ACQUISITION SYSTEM SIMULTANEOUS SAMPLE/HOLD The SHC85 makes an excellent device for reducing aperture time in a data acquisition system. When combined with Burr-Brown's 16 channel MPC·16S,Analog Multiplexer and ADC85 100r 12 bit A/D Converter, you can have a compact 16 channel data acquisition system with 50 kHz to 65 kHz throughput sampling rates and 0.02 percent (RSS) system accuracy. Time correlation of sampled data signals may be implemented by using one sample/hold for each analog signal prior to input to an analog multiplexer. The SHC85 low aperture time of 30 nanoseconds practically eliminates channel-tochannel time slew. The throughput sampling rate and the number of data channels will determine the maximum HOLD time and hence, the worst case droop error of the sample/hold in the last channel to be sampled prior to the next "refr~sh" or sample/hold command .. This droop error may be minimized by adding external capacitance to the SHC85 as shown in Figure 3. ~ '"zz g{ ~ « ... c« 5 .. ~ " g The droop error is computed by: 3 4 Clock .' .' MAX DROOP ERROR (CHANNEL N)=(T x n)(Droop rate) A0C85 AID Converter 13' 14 Where T = I and System Sampling Rate n = number of multiplexer data channels Serial 15 16 Mode ft:::::::::::11I'+t.ITTITTTn,.J 0 ... Control Convert « z EXAMPLE: Parallel Digital Data « Channal Addr... For a 10 bit, 32 channel system with throughput sample rate of 50 kHz, assuming no external capacitance, the droop error of channel N is: PROGRAMMER LOGIC or COMPUTER 1/0 Droop Error(ED)=(s6kx 32XSOO x 10-3 ) = 320 IJ.V For ±IO volt input signal range and 10 bit resolution, the resolution of ±\-2 LSB is ±9.77 mY. This droop error is less than 0.016 LSB (negligible), and no external C need b.e added to reduce the droop of the SHC85. ANALOG DATA ACQUISITION SYSTEM 6-349 BURR-BROWN® SHC298AM IElElI Low CQst Monolithic SAMPLE/HOLD AMPLIFIER FEATURES • 12:BIT THROUGHPUT ACCURACY • LESS THAN 10psec ACQUISITION TIME • WIDEBANO NOISE LESS THAN 20pV, RMS • RELIABLE MONOLITHIC CONSTRUCTION • 1010 .0. INPUT RESISTANCE • TTLlPMOS/CMOS'COMPATIBLE LOGIC INPUT '';,': DESCRIPTION The SHC29SAM is a high performance monolithic sample/hold circuit which features very high DC accuracy with fast acquisition times and a low droop rate. With the addition of one external ltolding capacitor, 12-bit accuracy can be achieved with a 6msec acquisition time. Droop rates less than SmVI mi,n can be achieved with a one microfarad holding capacitor. The fully differential logic inputs have low input current, and are compatible with TTL, PMOS, and CMOS logic families. The input offset adjustment can be made using a single external potentiometer and resistor, and the adjustment does not degrade input offset drift. The SHC29SAM will operate with power supplies ranging from ±SDC to ±ISVDC. It is available in a hermetically sealed S lead low profile package, and is specified for a temperature range from -2SoC to +SSoC. The SHC29SAM is the best price I performance bargain in its class. It is well suited for use in data acquisition systems, data distribution systems, analog delay circuits, and pulse amplitude modulation circuits. International Aif\Hll'tlndustriai Park· P.O. Bex 11400· Tucson. Arizona 85734· Tel. 1602) 746-1111· Twx: 9t1Hl52·t11l . Cable: BBRCORp· Telex: 66-6491 PDS-373 6":350 SPECIFICATIONS Specifications at TA = +25°C w~h rated supplies with 1000 pF holding capacitor unless otherwise noted. ~--------------------~ ELECTRICAL MODELS MECHANICAL SHC29BAM I I MIN UNITS MAX TYP INPUT ANALOG INPUT ±(Vcc-2.5) Voltage Range Maximum Safe Input Signal Resistance Volts Volts Ohms nA ±Vcc 1010 10 Bias Current DIGITAL INPUT Mode Control Truth Table 50 Pin 7 Pin 8 Circuit State OV OV +2.4V +O.8V +2.4V· +O.8V +2.8V +2.8V Sample (Track) Hold Hold Sample (Track) Mode Control and Mode Control Reference Input Current Differential Logic Threshold I TRANSFER CHARACTERISTICS ACCURACY /25°) Throughput No'olinearity for'Hold Time < Ims Gain Gain Error Input Voltage Offset (adj to zec,o) Droop, Rate Charge Offset Noise(rms) 10 Hzto 100kHz Power Supply Rejection 1.4 I 10 ±O.OIO ±O.015 +1.0 ±0.004 ±2 ±25 ±15 10 ±25 ±O.OIO ±7 ±125 ±25 20 ±50 I ~A Volts % of 20V V/V % mV p,V/ms mY ~V ~V/V ACCURACY DRIFT 3 15 50 20 I G.ain Drift Input Offset Drift Charge Offset Drift C = 1000 pF C= 10,000 pF Droop Rate at T A = +85°C 4 45· ISO 50 10 ppmtC ~vtc ~vtc ~vtc mV/ms Full Power Bandwidth, C = 1000 pF 75 C = 10,000 pF 10 Output Slew Rate, C = 1000 pF 7 C = 10,000 pF 1.4 Aperture Time Negative Input Step Positive Input Step AcquiSition Time (C = 1000 pF) .to ±O.O I %. IOV step to ±O.O I%. 20V step to ± 0.1%, IOV step to ±O.I %, 20Y step Sample-to-HoJd Transient Peak Amplitude Settling to I mV Feedthrough (Response to IOV Input Step) kHz kHz 125 16 10 2 125 30 200 45 6 8 5 7 10 12 9 II 160 1.0 ±O.007 ns ns "s ~s "s ~s mY 1.5 ±O.015 ±(Va-2.5) ±2 ~s %of20V Volts rnA 0.5 4 Ohms TEMPERATURE Specification Operating Storage ·C ·C ·C -25 to +85 -55 to +125 -55 to +150 POWER SUPPLY ±15 ±4.75 ±4.5 Connector: None V/~s V/~s OUTPUT, ANALOG OUTPUT Rated Voltage Range 111 Current MIL-STD-883 method 2003 (solderability) Hermeticity: ~'Iuorocarbon (gro~s leak) and Helium 5 x 1O-8 ccjsec (fine leak) DYNAMIC CHARACTERISTICS Voltage Range Current Range Impedance Pin Material and Plating Composition: Conforms to ±18 ±6.5 VDC VDC rnA (I) Logic ~~Ita~ on pin 8 should not exceed V~ - I volt. 6-351 PIN CONFIGURATION TYPICAL PERFORMANCE CURVES so 25 00 -vi. = V~= I!V IL 75 Negative 5 0 - Input Step'/ 25 / L 50 25~ I.4 ~ ...... -~ I / ";::'" / Positive Inp~t_ Siepi ~r:V+=V!= IS~ Set!1ing to 1 mV I. 6 IIVIN = 10V l/ 75/ I. ../[ AVOUT '" ImV i..;o" " I o. 8i--' ", i"""'" ~ " i""'" O.6 - o.4 o. " I 0 ·50 -25 0 25 so 75 100 125 150 AMBIENT TEMPERATURE (OC) 0 ,~S SO 75 100 125 150 -50 -25 0 AMBIENT TEMEPRATURE (OCl FIGURE 1. Aperture Time I. FIGURE 2. Charge Offset I 11111" I FIGURE 3. Sample·to·Hold Transient Settling Time 160 VIN=Oto±lovll 140 120 0 ""'-!% III "Hold" Mode 0 0.1% 0 O.D!jf I' 0 Mode 1000 0.001 om HOLD CAPACITOR (PF) HOLD CAPACITOR FIGURE 4. Output Droop Rate I o. :;- 6 .e... o.o. :;- 0 > '"::>z Si z '" >" -0. RL - 10k I :mple Mode , ....... 4 ~A.~:is.~clJH-tHIt-+.~IHII--H4H11ll1 140 , V+=V-=15V ~ 120 :mt~tt-HrttttlH-++ttttII-++++H!!I o lOOk!'Tf'I.:+tH1It11f-+l-+lfHII--t++Il!IlI ~ 80~ Negative 60 Supply Positive ~oPpIY I. 6 tt: I........... ~ ~ "~ I.4 Ik 10k FREQUENCY (Hz) lOOk -10 -5 0 10 IS VIN(V). . .. ""'..... ...... T;' =+ SoC I -'" ....... ~ ....... O. 8 i" O.6 - I-T~=-'~ ........ 1. 2 O. 4 C o. INPUT SLEW RATE (Y/ms) 160 n-m""'!-rTTrl!lll'"-n"TTTntr"T"'r1TTTm I. 8 j ;j ~ 1"0... -0. 8 FIGURE 7. Dynamic Sampling Error 8' '"~ -0. 6 I -15 100 , 0 -0. I III FIGURE 6. Output Noise TA'" :!SOC 4, , " .e '0" ''"" 0.1 FIGURE 5. Acquisition Time O. 8 o 10 , 0 -IS I I -10 I I -5 10 INPUT VOLTAGE (V) is FIGURE 9. Charge Offset FIGURE 8. Gain Error 5 0 ...... 5 ...... 0 1'-0... ....... 5 0 ..... ....... ..... 5 -I 0 ~'~OO~~~lk~~~IO~k-U~I~OO~k~UUI~M FREQUENt Y (Hz) FIGURE 10. Power Supply Rejection -I 5 ~ ~ 0 ~ m n 100 I~ 1m AMBIENT TEMPERATURE (OCl FIGURE II. Input Bias Current 6-352 -SO!'"IL.W.±'-"':~"'-!\-'"'~IO::'k"":I';:OO:tk~IM' FREQUENCY (Hz) FIGURE 12. Feedthrough Rejrctioll' (Hold Mode) DISCUSSION OF SPECIFICATIONS THROUGHPUT-NONLINEARITY is defined as total Hold mode, non-adjustable, input to output error caused by charge offset, gain non-linearity, one millisecond of droop, feed through, and thermal transients. It is the inaccuracy due to these errors which cannot be corrected by offset and gain adjustments. Throughput nonlinearity is tested with a 1000 pF holding capacitor, 10 volt input changes, lO/Lsec acquisition time, and one millisecond Hold time. CONTROL SIGNAL SAMPLE HOLD ~--------------~----------~L---~TIME INPUT VOLTAGE GAIN ACCURACY is the difference between INPUT and OUTPUT voltage (when in the Sample mode) due to amplifier gain errors. DROOP RATE is the voltage decay at the output when in the Hold mode due to storage capacitor, FET switch leakage currents, and output amplifier bias current. FEEDTHROUGH is the amount of the input voltage change that appears at the output when the amplifier is in the Hold mode. APERTURE TIME is the time required to switch from Sample to Hold. The time· is measured from the 50% point of the mode control transition to the time at which the output stops tracking the input. ACQUISITION TIME is the time required for the Sample and Hold output to settle within a given error band of its final value when the mode control is switched from Hold to Sample. CHARGE OFFSET is the offset that results from the charge coupled through the gate capacitance of the switching FET. This charge is coupled into the storage capacitor when the FET is switched to the "hold" mode. OUTPUT VOLTAGE FIGURE 13. Sample-Hold Errors OPERATING INSTRUCTIONS EXTERNAL CAPACITOR SELECTION Capacitors with high insulation resistance and low dielectric absorption, such as teflon, polystyrene or polypropylene units, should be used as storage elements (polystyrene should not be used above +85°C). Care should be taken in the printed circuit layout to minimize AC and DC leakage currents from the capacitor to reduce charge offset and droop errors. The value of the external capacitor determines the droop, charge offset and acquisition time of the Sample/ Hold. Both droop and charge offset will vary linearly with capacitance from the values given in the specification table for aO.OOI/LF capacitor. With a capacitor ofO.OI/LF the droop will reduce to approximately 2.5 /LV / ms lind the charge offsetto approximately l.5m V. Figure 5 shows the behavior of acquisition time with. changes in external capacitance. OFFSET ADJUSTMENT The offset should be adjusted with the input grounded. During the adjustment, the Sample/Hold should be switching continuously between the Sample and the Hold mode. The error should then be adjusted to zero when the unit is in the Hold mode. In this way, charge offset as weU as amplifier offset will be adjusted. When a O.OOI/LF capacitor is used, it will not be possible to adjust the full offset error at the Sample Hold. It should be adjusted elsewhere in the system. 6-353 APPLICATIONS DATA ACQUISITION The SHC298AM may be used to hold data for conversion with an analog to digital converter or used to provide Pulse Amplitude Modulation (PAM) data output. PAM Output ,Analog Input / _ ., \~-_-i·~i ~j .. ~ Mode Control HoldJL...-_ _...Jnt.._ _ _....nL...-_ _...J Analog Inputs toA/D Converter r - - -.. FIGURE 15. PAM OutP4t PAM Output Analog Ol~ Multiplexer Storage Capacitor ·15V +15V FIGURE 14~ Analog Output SHC298AM .D-~-+- pata Acquisition DATA DISTRIBUTION The S HC298AM may be used to hold the output of a digital to analog converter whose digital inputs are multiplexed. Digital Inputs D/A Converter TEST SYSTEMS The SHC298AM is also well suited for use in test systems to acquire and hold data transients for human operators or for other parts of the test system such as comparators, dtgital voltmeters, etc. With a 0.1 ~F storage capacitor, the output may be . held 10 seconds with less thanO.I%error. Witha I ~F storage capacitor, the output may be held more than 15 minutes with less than 1% error. FIGURE 16. Data Distribution 6-354 HIGH SPEED DATA ACQUISITION The minimum sample time for one channel in a data ·acquisition system is usually considered to be the acquisition time of the Sample and Hold plus the conversion time of the analog to digital converter. If two or more Sample and Holds are used with a high speed multiplexer, the acquisition time ofthe Sample and Hold can be virtually eliminated. While the first channel is in hold and switched on to the ADC, the multiplexer may be addressed to the next channel. The second Sample and Hold will have acquired this data by the time the conversion is complete. Then, the Sample and Holds reverse roles and another channel is addressed. For low level systems, an instrumentation amplifier and doubleended multiplexer may be connected to the Sample and Hold inputs. The settling time of the multiplexer, instrumentation amplifier, and Sample and Hold can be eliminated from the channel conversion time as before. Digital ...._ _..Output CHI BI CH2 Analog to Digital 82 Converter CHN 1(0) :\ High Speed Switch FIGURE 17. "Ping-Pong" Sample/Holds 6-355 BI2 BURR-BROWN® SHM60 IElElI ·High Speed SAMPLE/HOLD FEATURES DESCRIPTION -l~sec Designed for use with fast A/D and D/ A converters and analog multiplexers, the Burr-Brown Model SHM60 high-speed sample/hold acquires analog signals of up to ±IOV amplitude and settles to 0.01% in less than 1.51'sec for a 20V input step, and in less than ll'sec for a lOY input step. Both analog input terminals are available for user selection of gains from unity to 1000. Internal compensation of charge storage effects and dielectric absorption are provided to assure accurate and fast operation. The SHM60 dynamic nonlinearity of 0.01 % is specified for hold periods of up to l51'sec to simplify the user's task of computing system throughput error for specific operating conditions. The 2" x 2" x 0.4" encapsulated modular package operates from ±15VDC power and is compatible with Burr-Brown's line of fast A/D and D/A converters such as Models ADC85 and ADC80 and ADC84 A/D converters, and DAC85, DAC80 and DAC85 D / A converters. A few of the more popular applications for the SHM60 are: A / D converter aperture error reduction Time correlation of sampled signals i.e., simultaneous sample/hold Multiplexing D/ A converter outputs Generation of pulse-amplitude-modulation (PAM) telemetry signals Analog memory f()r an!ilog computations .,. and many more. ACQUISITION - .01% ACCURACY -SELECTABLE GAINS - ±1 to ±1000 -12nsec APERTURE TIME - LOW FEEOTHROUGH - 0.005% International Airport Industrial Park - P_O. Box 11400 - Tucson, Arizona·85734 - Tel. (602) 746-tllt - Twx: 910-952-1111 - Cable: 88RCORP - Telex: 66·649t PDS-3IOA 6-356 SPECIFICATIONS Typical at 25°C and rated supplies unless otherwise noted. MECHANICAL ELECTRICAL MODEL I Min TVp SHM60 Max I I Units INPUT ANALOG INPUT Signal Voltage Maximum Safe Input 1 Impedance Bias Current -10 -15 +10 +15 pA DIGITAL INPUT (Mode eontrol)2 at SO nA Sink Rise Time for Specified Performance +2.4 +5.0 V 0.0 +0.8 5 V nsec +14.55 -14.55 +15 -15 +15.45 -15.45 2.S4mm (BOTTOM (.10") 25 17 15 15 Vdc Vdc rnA rnA rnA rnA 'i. Ilimensio,ns in parentheses are in inches. TRANSFER CHARACTERISTICS ACCURACY al Gain of I V/V3 Dynamic Nonlinearity 4 ±o.o] ±0.005 ±0.005 Gain Error Throughput Offset (Adj. to Zero)5 Droop Rate Dielectric Absorption 4 Noise Common Mode Rejection Ratio Power Supply Rejection 6 . .lSmm (.2S") VII·.W) INPUT POWER +15V Supply Voltage Range -15V Supply Voltage Range Quiescent Current +I 5V Supply - Sample Mode - Hold Mode -15V Supply - Sample Mode -Hold Mold IO.16mm (0.40'') n 1011 50 Sample Mode (Logic I) at 100 IJA Source 'Hold Mode (Logic 0) ----( V V ±0.01 3 I 5 ±0.005 100 10-4 10 30 % of 20V % of 20V mV I'V/I'sec %of l;V J.l.Vrms V/V ppm/% WEIGHT: 56.7 grams (2 oz) MATING CONNECTORS: 2.100· P.C. Card and Terminals 2301· Set of 2 - 16 Pin Connector Strips PINS: Pin material and platinl;!: composition conform to method 2003 (solderability) of Mil-Sld-H83 1except paragraph 3.21. ACCURACY DRIFT (ooe to +70°C) Throughput Drift Droop Rate ±2 doubles every loDe ppm of 20V /oe 400 25 kHz V/psec DYNAMIC CHARACTERISTICS Bandwidth (Full Power) Output Slew Rate Acquisition Time (to ±O.Ol%) 10V Step 20V Step Aperture Time Sample-ta-Hold Transient Peak Amplitude Settling to .01% Feedthrough in Hold Mode 0.8 1.2 12 I 1.5 J,lsec IJsec osee 50 200 ±0.005 mV nsec % of Step Change at input OUTPUT V oltage Range Current Range Impedance (Short Circuit Protected) V rnA ±10 ±20 , 1.0 n TEMPERATURE Specification Storage NOTES: 1. Input should never exceed supply by more than 0.6 volts. 2. Shottky TTL compatible. 3. Gain is user selectable. o to +70 -55to+125 °e °c 4. For I I'sec SAMPLE and IS /J.sec HOLD times. 5. Includes voltage and charge offsets. 6-357 CONNECTION DIAGRAM (TOP VIEW) DISCUSSION OF SPECIFICATIONS ACCURACY All SHM60 sample/hold units are tested for accuracy and are factory trimmed to assure that all units meet critical specifications. DYNAMIC NONLINEARITY This is the unadjustable throughput error from input to output for a 1 microsecond SAMPLE period and a 15 microsecond HOLD period. Errors included in this specification are through·. put nonlinearity, dielectric absorption, droop, therma!trallsients and feed through. Offset errors must.be adjusted to zero with an offset. trim control and gain errors must be adjusted to zero with a gain trim control elsewhere in the system. SAMPLE-TO-HOLD SWITCHING TRANSIENT When the mode control is changed from SAMPLE -to- HOLD, the switching transient that appears on theoutpur is the sample-to-hold switching transient. v' J , Hold scale range when operated as a unity gain voltage follower. THROUGHPUT DRIFT The input to output accuracy drift over a ooe to +70OC temperature range is the throughput drift - it is ±2 ppm/°e or ±0.0002% of 20 volts. THROUGHPUT OFFSET The output offset voltage encountered in the HOLD mode after sampling a grounded input is throughput offset. This error includes charge offset at zero volts input as well as amplifier d.c. voltage offsets. Ac:QUI$ITIDN TIME The acquisition time of the SHM60 is defined as shown in Figure 1. This is the time required for the SHM60 to turn on, slew and settle to 0.01 % of the input voltage when the mode is changed from HOLD to SAMPLE. .l __ Droop ACCURACY - UNITY GAIN·OPERATION The initial accuracy of the SHM60 is ±0.01 % maximum of full GAIN and OFFSET ERRORS - GAINS OTHER THAN UNITY The SHM60 should be treated in the same manner as an operational amplifier when gains other than unity are employed. The gain setting resistor parameters such as absolute accuracy and tracking ratio must be considered when computing error effects for gains other than unity. Sample· to-Hold T~n~n~ _ _ FIGURE 2. Definition of Acquisition Time Droop and Sample-to-Hold Transient. DROOP RATE Droop in a sample/hold is the voltage decay at the output due to output amplifier bias current when operating in the HOLD mode. To determine the effects of droop on system accuracy, the droop rate is multiplied by the HOLD period. FEEOTHROUGH The amount of input voltage change seen at the output when the sample/hold is in the HOLD mode is feedthrough error. The low feed through error ofO.005%preserves the accuracy of the sampled signal and can be used to increase the throughput sample rate, especially in time multiplexed applications. APERTURE TIME Aperture time is the delay between the time the sample/hq\d is given the command to HbLD the input signal and the time that this actually occurs. The SHM60 aperture time of 12 nanoseconds ,is sufficiently small to make aperture errors negligible for. most applications. v -+,,__ ____ 100~,,~,,__ = mV ~ ~~ __+-__ ~ ~ 10 I-----f~ I mV I..-Aperture I Time Sample Hold Acqui~iti()n Tim~ (",sec) FIGURE I. Error vs. Acquisition Time (Unity Gain Follower). SYSTEM ERROR CONSIDERATIONS FIGURE 3. Aperture Error. The I /lsec acquisition time and 12 nanoseconds aperture window of the SHM60 offer an exceIlerit way of reducing system sampling error at high throughput rates for sinusoidal data. Taking the maximum slope of a sine wave at the zero crossing where maximum samp'ling error occurs, the error voltage as a percentage of fuIl scale is proportional to the product of frequency and aperture time (lH): 6-358 % Aperture Error = l::.V x 100= 21Tfl::.t x 100 V where l::. V = Aperture error V =Peak signal amplitude f =Maximum signal frequency l::. t = Aperture time INSTALLATION and OPERATING INSTRUCTIONS OPTIONAL VOLTAGE and CHARGE OFFSET ADJUSTMENTS Output Note 1 NOTES: I. The analog input signal should not be run under or over the module as this may degrade feedthrough in the HOLD mode. -= +0-.....11...... Inp! Throughput OFFSET error may normally be adjusted to zero with a single external VOLTAGE OFFSET adjust control, as shown in Figure 4. A small CHARGE OFF· SET error of J mV to 3 mV in the HOLD mode may occur. This CHARGE OFFSET error may also be ad· justed to zero with an optional external CHARGE OFF· SET adjustment as shown in Figure 4. Analog 2. Potentiometers should ha.ve a TCR of 100 ppm/ DC or less. • Care must be taken to provide a good low impedance common as there is an appreciable amount of current returned to the power supplies. • Power supply bypass capacitors are provided in the module, but additional bypassing may he required if excessive noise is present on the power supply lines. FIGURE 4. Optional CHARGE and VOLTAGE OFFSET Adjustment Connections. CONNECTIONS FOR GAINS OTHER THAN UNITY Output + RF = 10k!! max Although optimum performance is at unity gain, the SHM60 may be operated to provide gains ranging from ±l to ±1000 as shown in Figures 5 and 6. For these configurations" the unit may be treated as an opera· tional amplifier. Acquisition time will get longer as gain increases, approximately 2.5 J.lsec settling to ±0.01% for again of 5 and 4J.lsec for a gain of 10 for 10 volt output steps. Voltage drift can be computed as with an op amp using 10 J.lV/oC as the input drift. FIGURE 5. SHM60 Connections for Inverting GAIN. NOTES: • Gain accuracy and drift is dependent on the absolute accuracy and thermal tracking properties of. the gain setting resistors R 1 and R F. Me,tat film or better quality low drift resistors are recommended. • FIGURE 6. SHM 60 Connections for Non·Inverting GAIN. Charge offset is independent of gain. and is referred to the output. BURR-BROWN® VFC12 VFC16 VFC12LD VFC16LD IElElI VOLTAGE-TO-FREQUENCY CONVERTERS APPLICATIONS AID CONVERSION - 13-bit accuracy oPM FRONT END - 3+ digits accuracy lONG-LINE SIGNAL TRANSMISSION Increase noise immunity using only one transmission line . OPTICAL ISOLATION Use simpler isolation techniques than with analog isolation and with only one isolator FEED RATE GENERATOR ANO CONTROL 0.05% accuracy over O°C to +70°C FEATURES lOW COST ONE SIGNAL LINE TRANSMISSION COMPACT 1.5" x 1.5" x 0.4" module package ACCURATE 0.005% linearity gives you 13-bit accuracy STABLE 10ppm/oC max gain driflilo versions) gives you excellent stability over temperature VERSATilE Many simple-to-Implement scaling options Unipolar or bipolar operation - VFCI5 CONVENIENTlY SCAlEO I kHz per volt Internallonal Airport Industrial Park - P.O. 80x 11400 - Tucson. Arizona 85734 - Tel. (602) 746-1111 - Twx: 910-952-1111 - Cabla: 88RCORP - Telex: 66-6491 PDS-314 6-360 GENERAL DESCRIPTION Voltage-to-frequency conversion is a simple and low cost method of converting analog signals into an equivalent digital form. The output is a TTL/DTL compatible digital pulse train whose repetition rate is proportional to the amplitude of the analog input signal; these pulses have constant width and constant amplitude. The Burr-Brown Model VFC 12 accepts 0 to 10 volt analog signals and is pin compatible with Teledyne Philbrick's Model 4701. The Model VFCIS accepts either 0 to 20 volt or 0 to 20 rnA current analog signals. The VFC 12 operates over a DC to 10 kHz frequency range and the VFC IS operates over a DC to 20 kHz frequency range. The low 0.01% nonlinearity error of these V/F converters makes them excellent for use in applications where digital resolutions of 12 or 13 bits are desired. These 1.5" x 1.5" x 0.4" modular units are completely self-contained and require only ±IS Vdc power and input signal. The gain and offset are adjustable with external potentiometers. A number of optional confIgUrations to scale the input or output for best compatibility with your system are easily realized with simple external circuitry. THEORY OF OPERATION The Model VFCI2 and Model VFCIS are ultra-linear volt· age-to·frequency converters that provide a digital pulse train output whose repetition rate is directly proportional to the analog input voltage. To understand the operation of the circuit consider the block diagram in Figure I. Amplifier Al is connected in an integrator confIguration. The integrator capacitor C begins charging at a constant rate in response- to the input voltage until the output of Al reaches a certain potential Vref. At this time a comparator triggers a frequency-control1ing charge dispenser which reo moves a precision amount of charge from C. The frequency at which this charge transfer occurs is linearly related to the input voltage. Al need not be an exceptionally high-gain or fast slewing operational amplifier. As long as the average current at the summing junction of Al is zero, the frequency of oscillation must be directly proportional to the input voltage with little dependence on the gain or speed of AI. +1SV 22Mn Offset Trim g.----J\f\f\p-'" 33kn Frequency Controlling Charge Dispenser 10kn Output C 4.7kn Voltage C>o---""""""-"-4~--1 Input ..........- ...- - 0 Digital Analog Gnd. Gnd. o--"'-~""'..-----"'" FIGURE 1. Functional Block Diagram of Model VFCI2. 6-361 SPECIFICATIONS ELECTRICAL MECHANICAL Typic~1 at 25°C and rated power supplies unless otherwise noted. UNITS· MODEL FREQUENCY RANGE kHz INPUT ANALOG INPUT Voltage Range Overrange (min) o to +20 10 .33 22 Oto +10 100 33 22 Impedance Maximum Safe Input Voltage V % of FSR(I) lin V INPUT POWER Rated Voltages(2) Supply Drain Typical Maximum ±15 ±IO% Vdc ±l6 t20 rnA rnA Dimensions in inches are shown in parentheses. TRANSFER CHARACTERISTICS Voltage Input 4 Vin fout= 10 10 TRANSFER EQUATION Hz ACCURACY Full Scale Gain Error(3) Offset Error(4) Typicai Adjustable to.002 ±0:01 Maximum Linearity Error (max) Yin = +1 mV to +10 V Yin = +1 mV to +20 V Po~er Supply Sensitivity ±O.O I I ±0.005 ±0.01 ±0.005 ±O.OOI ±0.005 %ofFSR %ofFSR I, ±0.005 %ofFSR %ofFSR %ofFSR/% STABILITY (OOC to +70°C) Full Scale Drift (Gain + Offset) Voltage Input Typi~a1 Maximum Current Input Stability vs. Time Full Scale Drift Per day Per month Input Offset Drift Per day Per month Offset Drift Typical Maximum 20 SO I 20 SO 35 8 10 N/A 8 10 IS ppm of FSR/oC ppm of FSR/oC ppm of FSR/oC I J 20.32mm (0.80") Offset TrimVFCI2 Current Input_ VFCI5 L r MATERIAL: Case: Diallyl Phthalate or Epoxy 'Shell Pin mateJ;'ial and plating composition conform to Method 2003 (solderability) of Mil-Std-883 [exCept paragraph 3.2). Weight: 25 grams (0.875 oz) Mating Connector: 1400 MC C.IRCUIT DIAGRAMS ±I 00 ±200 ppm ofFSR ppmofFSR ±IO ±20 ppm ofFSR ppm ofFSR r-- - --- - - - - - ~--~~ I ppm of FS·R/oC ppm of FSR/oC ±2 t5 I VFC1Z I ,I v:"_ Input RESPONSE Settling Time for 10V Input Step Overload Recovery Tim'e TEMPERATURE RANGE Specification Operating (derated specifications) Storage 2 output pulses of new frequency plus 20 !Jsec 1 to 2 pulses of new'frequency I Analo, God. I I I o to +70' -25 to +85 -55 to +125 r. -'---.- ---- OUTPUT Waveform Pulse Characteristics Logic I (High) Logic 0 (Low) Pulse Width Fan Out . Impedance Capacitive Load (max) (I) (2) (3) (4) OIfoet I ____________ 1.. ~ Train ofTTL/DTL compatible pulses v 4.7 ±0.5 0.2 ±O.I 30 10 TTL Loads 3 1000 V ~sec kn pF FSR = Full Scale Range and is 10V for VFCI2 and 20V for VFCI 5. A regulated supply with I % or less ripple is recommended. Adjusted at faGtory for 9.900V = 10kHz. May be externally adjusted to zero. 6-362 VFC1& I -- I . Vol_, Input 133kn C lOkO -1I Trim DISCUSSION OF SPECIFICATIONS DYNAMIC SIGNAL RANGE 0.3"r--""T"--r---""""""'""T--r--""T"---' The VFC 12 is specified to operate over a DC to 10kHz frequency range for an input voltage of 0 to + I 0 volts. Since this unit has a specified overrange of 100%, it is possible to extend the input signal and output frequency ranges to 20 volts and 20 kHz respectively. However, the linearity is not guaranteed over this range. If the extended range of operation is desired, Burr-Brown recommends using the VFCI5 for greater than 10 volt and 10 kHz operation. In addition to the extended voltage and frequency range, the VFCI5 has its input summing junction made available for applications requiring current-to-frequency conversion and bipolar input signals up to ±.IO volts. FIGURE 3. Frequency Drift vS. Temperature with Calibration made at 25 0 C. Figure 2 depicts the transfer function of these units. The input current-to-frequency transfer function for the VFCl5 is shown for a calibrated 1000 ohm shunt resistor (see page 6-365). FULL SCALE AND OFFSET DRIFT All units are tested for full scale and offset drift over a OoC .&-;; ~ ~ 10k V Ik 2t: r.. .. 100 /" ~:l: ~~ ~ 10 0.1 .0001 .0001 /' /" ~ 0 ~. .001 .001 10 ::'ii' ~ ~ 0.1 ... ~= o~~~~E~"'''. c ~ ~ ~ -O.l~~"'T'--+---t---F'"-I"=:IIl:"t-~"'t-'~~ ~ -O.2t---+--+---t--+---+---F-..QI J: -0.3L---:'::~_~-~:---=--t:---~--::'. Temperature (0C) to +700 C operating temperature range. Internal temperature compensation is provided for ±50 ppm/oC maximum full scale drift and ±.S ppm/oC offset drift for VFC 12 and VFCI5. Maximum full scale drift for VFCl2LD and VFC ISLD is ±.IOppm/oC. If external full scale and offset trim adjustments are provided, the temperature coefficient of the external components must be added to the specified drift components as shown on page 5-183 to determine the total thermal coefficients of drift. lOOk ~ 0.2 .....,;,:,;~,..,..,,.....,,'---:~:;..:.::.;:.::..,,.,....,.,-+--+-:::_!""I 100Y 100mA FIGURE 2. Voltage or Current-to-Frequency Characteristic. ACCURACY The transfer linearity of these V/F converters is one of the most meaningful measures of accuracy since initial full scale and offset errors are externally adjustable to zero. All VFCl2 and VFC IS units are factory calibrated for maxinlUm linearity error of 0.01 % of full scale range input signals. Although Burr-Brown guarantees a maximum linearity error of ±O.OI % of full scale, the linearity error of these units is typically less than ±0.002% of full scale. The use of regulated power supplies with better than I % regulation is recommended in order to maintain the accuracy of these units. The 0.01% linearity makes these units excellent for use as a front end for 10 to 12 bit resolution A/D converters, and for highly accurate transfer of analog data over long lines in noisy environments. RESPONSE The settled response of these units to changes in input signal is specified for an input signal step change of 10 volts and is 20 microseconds plus 2 output pulses of new frequency. For I b volt input signal steps, the VFC 12 operating at 10 kHz full scale frequency range, the step response settling is 220 jlsec; for the VFC 15 operating at 20 kHz full scale frequency range, the step response settling is 120 jlsec. Figure 4 shows the typical response of these units to instantaneous changes in the input signal. +lOY I FREQUENCY STABILITY vs. TEMPERATURE Frequency drift is factory tested with the offset and full scale calibration made at 25 0 C, and is expressed as parts per million of full scale range vs. temperature. Typically, full scale drift is ±20 ppm/oC over the operating temperature range for VFCI2 and VFCI5. VFCI2LD and VFCI5LD have typical full scale drifts of 8 ppm/oC. -I-- ~12S /loS I- ~2S0...j I- 30~ I I II I #is #is 220 -1100 I'S I--- I I JlS FIGURE 4. Typical Response to Instantaneous Changes in the Input Voltage. 6-363 INSTALLATION AND OPERATING INSTRUCTIONS INSTALLATION The VFC12 and VFClS are designed for installation on a flat mountirig surface such as a printed circuit board or a chassis. 'The pins may be hand or dip soldered; for plug in installations, the accesSory connector (1400MC) or mounting jacks may be installed on a chassis or p.c. board. For best results, the power supply should have 1% or better regulation and low ripple and noise. The Burr· Brown Model 550 series ±lS volt output modular power supplies provide excellent regulation, and are recommend· ed for use with these VIF converters. Normally external power supply bypass capacitors are not required. How· ever, if a good quality low ripple power source is not .available, 1 /-IF or larger external bypass capacitors' are recommended in order to prevent interference from power supply effects. Particular attention should be given to wire or p.c. con· ductor path routing. All input signal lines should be as short as possible, and coupling from power supply lines should be minimized CAUTION: Do not short Output to -15 Volt Pin. EXTERNAL CONNECTIONS soon FULL SCALE ADJUST FULL SCALE AND OFFSET ADJUSTMENTS The VFCI2 and VFClS V/F converters are factory cali· brated to meet all specifications. However, FULL SCALE and OFFSET may be user adjusted when absolute ac· curacy better than the specified initial accuracies are required. These units are factory calibrated to Ilrovide a FULL SCALE output frequency of 10 kHz for an input volt· age of 9.900 V ±O.OS% and may be calibrated to provide 10.000 kHz output frequency for an exact input voltage of 10.000 volts. OFFSET is factory calibrated to pro· vide an output frequency of 1 ±0.2 Hz for an input voltage of 1.0 millivolts. Yin + Analog Input Analog Gnd. 10k.to 100kn OFFSET ADJ. -ISV +ISV Dig. Gnd. -ISV Output Offset Trim Output I (BOTTOM VIEW) See Not. I S•• Note I - FIGURE 5. VFC 12 Optional FULL SCALE and OFFSET Adjustments. VFC15 FULL SCALE ADJ. soon ADJUSTMENT PROCEDURE Select external potentiometers with low drift coefficients to preserve the drift characteristics of the V/F converter. The drift effects must be added to the ±50 ppm/oC speci· fied FULL SCALE temperature coefficient. For example, external component contribution of Rl to drift will be: 33k+R1 +ISV RI Normally, OFFSET need not be adjusted unless absolute accuracies of better than ±0.004% are required. [~ VFC12 +ISV 10ktb 100kn OFFSET ADJ. -ISV +ISV Dig. Gnd. -ISV putput Analog Current Gnd. Input 20Mn (BOTTOM VIEW) J x Tempco R ;l/OC To calibrate these units, first apply + 1.0 mV to the analog input terminals and adjllst R2 for fout = 1.0 Hz. Then apply +10.000 volts to the input and adjust R1 for fout = 10.000 kHz. Interaction between R1 and R2 is generally negligible due to the low initial offset voltage; however, repeating the above calibration will insure pre· cise calibration. S•• Note I ~ Output I See Note 1 FIGURE 6. VFC15 Optional FULL SCALE and OFFSET Adjust for Voltage Input Signals. NOTE I: Digital and Analog grounds should be tied together as close as possible to the power supply common. 6-364 OPERATING OPTIONS CURRENT-TO-FREQUENCY CONVERSION A method of obtaining direct conversion of input currents of 0 to 10 rnA for Model VFC12 and 0 to 20 rnA for Model VFCI5 corresponding to output frequency ranges of 0 to 10kHz and 0 to 20 J.diz respectively is described in Figure 7. Figure 7 describes a calibrated 1000 ohm shunt resistance across the voltage input terminals. Full scale output is calibrated by adjusting the 1000 ohm shunt performing the usual offset adjustments. The second technique, described in Figure 8, is a simple current divider into the summing junction (CURRENT INPU1) of the VFCI5. This method offers the advantage of limiting the voltage swing on the input terminal to a 3.8 to 5.55 volt range for a 0 to 20 rnA input current range, depending on the value of the full scale adjustment potentiometer, offering better compliance to the current source. OFFSET may be adjusted as shown on page 6-364. VFC12 or VFC15 VFC15 o o o + Output Analog Gnd. = fout o to 20 kHz fout = 0 to 20 kHz Output Current o--+-~""\r-",,--ofnup~~nt Input loon lin = FULL (BOTTOM VIEW) SCALE o to 20 rnA ADJ. 200n (BOTTOM VIEW) FIGURE 8. VFCl5 Current-to-Frequency Conversion using Current Input Terminal. FIGURE 7. VFC IS Current-to-Frequency Conversion using Voltage Input Terminals. SCALING FOR BIPOLAR INPUT VOLTAGE RANGE kHz for the ±5 volt range and at 10 kHz for the ± 10 volt range. The corresponding output frequency ranges will be: The summing junction (CURRENT INPU1) of the VFCl5 is made available for scaling the unit to accept ±5 volt or ±10 volt input signals. An external reference and scaling resistors must be connected to' the CURRENT INPUT. OFFSET is adjusted as shown on page 6-364. SIGNAL RANGE !INPUT 51 GNAL OUlPUT FREQUENCY (kHz): 0 0 0 Vin + ±IO'V il +10 Volt Reference VFC15 50 kn Input 0 5 10 -IOV OV +10 V 0 10 20 +10 Volt Reference VFC15 FULL SCALE TRIM 0 0 0 Vln 30 kn Output Current OV +5V -5 V ±5 V Figures 9a and 9b show an example with a +I 0 volt reference. The reference regulation and drift should be low in order to preserve signal accuracy. The output frequency range for these input voltage ranges will be centered at 5 20 kn 20 kO Output Output o to 10 kHz Current Input (BOTTOM VIEW) (BOTTOM VIEW) FIGURE 9a. 'Scaling the VFCl5 for ±5 volt Bipolar Operation. Output 01020 kHz FIGURE 9b. Scaling the VFCl5 for ±10 volt Bipolar Operation. 6-365 SQUARE-WAVE OUTPUT SN7474 V/F Converter (V 1) A type D flip-flop in a frequency dividing configuration provides a convenient method of obtaining a variable width square wave output from the VFCI2 or VFCI5 as shown in Figure 10. The output of the VIF converter is used to drive the clock input of the flip-flop. . I-t-J-t-.;.l r--+- Vl~ V2 C Q D Q~ Output r- V2~ \-2t--/ FIGURE 10. Square Wave OUtput Using a Type D Flip-Flop. DRIVING HIGH NOISE IMMUNITY LOGIC i +1SV V/F Converter Output A pullup resistor to + IS volts on the VIF converter output as shown in Figure II provides 4 volt noise immunity for driving high noise immunity logic (HNIL). 2.2kn . 0_-----....----_. . . . To HNIL FIGURE II. Pullup Resistor for Driving HNIL. +SV : +sv OUTPUT ISOLATION Vin + Optical coupling the VIF converter outputs provides an excellent method of obtaining 500 Vdc or 1000Vac POp isolation between the VIF converter and a receiving device. The isolation is accomplished digitally, preserving signal accuracy. The common mode capability of the circuit shown in Figure 12 is limited only by the optical isolator and the power supply. 0 Dig. Gnd. Yin 0 r-o-Output Analog Gnd. 0 L ~7 "* l Note 1 1 --z-( I To TTL Load ECM " SOOVdc or Peak Be . FIGURE 12. Optical Isolation of VIF Converter Output. NOTE I: This +5 V supply is isolated from the +5 V supply used for the diode. SCALING FOR 1 kHZ OUTPUT FREQUENCY RANGE Two methods are described in Figures 13 and 14 for obtaining a 1 kHz full scale VIF converter using the VFCI2 or VFCI5. GAIN ATTENUATION FREQUENCY DIVISION In the circuit of Figure 13 the input is attenuated by a 10: I divider. This technique is the least expensive to implement but has the disadvantage of added thermal drift of the external components and does not permit the VIF converter to operate over the most linear portion of its frequency range. Figure 14 illustrates the best method of obtaining a. I kHz frequency range using an external decade counter. The disadvantages of the gain attenuation technique are overcome, but this technique is more expensive to implement. VFC12 or VFC15 t---I-00+ FULL SCALE TRIM soon o o o o o o fout= o Hz to 1 kHz Outputo-...,t--t Output 0--11--0 o VFC12 or VFC15 o fout= OHztolkHz ,SN 7490 or equivalent FIGURE 14. I kHz Full Sca1~ Output Frequency Range Using Decade Counter. FIGURE 13. I kHz Full Scale Output Frequency Range Using Input Attenuation Network. 6-366 BURR-BROWN® VFC32 IElElI Voltage-to-Frequency and Frequency-to-Voltage CONVERTER FEATURES APPLICATIONS • RELIABLE MONOLITHIC CONSTRUCTION • HIGH LINEARITY ±D.Ol% max at 10kHz FS ±D.05% max at 1110kHz FS • INEXPENSIVE AID AND D/A CONVERTER • DIGITAL PANEL METERS • TWO·WIRE DIGITAL TRANSMISSION WITH NOISE IMMUNITY .• FM MOD/DEMOD OF TRANSDUCER SIGNALS • V/F OR F/V CONVERSION • 6·0ECAOE DYNAMIC RANGE • VOLTAGE OR CURRENT INPUT • OUTPUT OTL/TTL/CMOS COMPATIBLE • PRECISION LONG TERM INTEGRATOR • HIGH RESOLUTION OPTICAL LINK • AC LINE FREQUENCY MONITOR • MOTOR SPEED MONITOR AND CONTROL DESCRIPTION The VFC32 monolithic voltage-to-frequency and frequency-to-voltage converter provides a simple low cost method of converting analog signals into digital pulses. The digital output is an open collector and the digital pulse train repetition rate is proportional to the amplitude of the analog input voltage. Output pulses are compatible with DTL, TTL, and CMOS logic families. The converter requires two external resistors and two external capacitors to operate. Full scale frequency and input voltage are determined by one resistor (in series with -IN) and two capacitors (one-shot timing and input amplifier integration). High linearity is achieved with relatively few external components, e.g., ±O.OI% at 10kHz. The other resistor is a noncritical open collector pull-up (fOUT to +Vcc). The VFC32 is available in three models and two package configurations. The TO-IOO versions are hermetically sealed, and specified for the -25°C to +85°C and _55°C to +125°C ranges, and the epoxy dual-in-line unit is specified from O°C to + 70°C. .VCC ·IN 'OUT .IN ,Vee Internalional Alrporllnduslrial Park· P.O. Box 11400 . Tucson. Arizona 85734 . Tel. 16021 746·1111 . Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66·6491 PDS·372B 6-367 SPECIFICATIONS ELECTRICAL At TA = +25·C and ±15VDC power supply unless otherwise noted. CHARACTERISTICS I CONDITIONS INPUT (VIF CONVERTER) I I VFC32BM VFC32KP MIN I TYP I MAX I MIN TYP I MAX I 1 VFC32SM MIN TYP MAX I UNITS FOUT = VIN 17.5 R,C" Figure 6, Input Amp Voltage Rangel') Positive I "put >0 Negative Input Current Rangel') >0 >0 +O.25mA xR, -10 +0.25 V V mA Bias Current Inverting Input Noninverting Input Offset Voltage(2) Differential Impedance Common-mode Impedance INPUT (FN CONVERTER) 300 1110 20 100 1 6501110 300 113 500 113 100 250 4 nA nA mV kll II pF Mil II pF VOUT = 7.5 R,C, FIN, Figure 9, Comparator Impedance (Camp In) Logic "1" Logic "0" Pulse-width Range 501110 +1.0 -Vee 0.1 kll II pF V V ,",sec 150 1110 +Vee ±C.05 150klFMA ACCURACY Linearity Error,(3l O.OIHz"; oper Ireq,,; 10kHz O.IHz"; oper Ireq ,,; 100kHz a.5Hz,,; oper Ireq ,,; 500kHz ±O.OOS ±O.010( 0) ±O.025 ±O.05 . % 01 FSR(5) %oIFSR %olFSR ±0.05 Offset Error Input Offset Voltage(2) Offset Drift(6) 1 4 mV ppm 01 FSRI"C ±3 Gain Error{2) Gain Drif«6) Full Scale Drift (offset drift & gain driftI(8)(7) Power Supply Sensitivity I = 10kHz 5 ±75 ±50 ±100 ±70 ±150 %oIFSR ppml"C 1= 10kHz ±75 ±SO .:!:100 ±70 ±150 ppm 01 FSRI"C I = DC, ±Vee = 12VDC to 18VDC ±O.015 %01 FSR/% 0.4 V 1.0 ~A OUTPUT (V'F CONVERTER) (open collector output) Voltage, Logic "0" Leakage Current, Logic "1" Voltage, Logic "1" Pulse Width Fall Time ISINK-8mA 0 0.2 o.ot Vo = 15V External pull-up resistor required (see Figure 41 For Best Linearity lOUT = SmA, CLOAD = 500pF . Vpu 0.25/FMAX V sec nsec 400 OUTPUT (FN CONVERTER) VOUT Voltage lo=7mA Vo=7VDC Closed loop Without oecillation Current Impedance Capacitive Load Oto+l0 ; +8 . 1 100 V mA n pF DYNAMIC RESPONSE· Full Scale Frequency Dynamic Range Settling Time 500(8) kHz decades 6 IVIFI to specified linearity for a full scale input step (0) < 50% overload to) Overload Recovery POWER SUPPLY Rated Voltage Voltage Range Quiescent Current ±15 ±11 V V mA ±20 ±5.5 ±S.O TEMPERATURE RANGE Specification Operating Storage . 0 -25 -25 +70 +85 +85 Specilicallon the same as VFC32KP 6-368 -25 -55 ~5 +85 +125 +150 -55 -55 ~ +125 +125 +150 ·C ·C ·C NOTES: 1. A 25% duly cycle 10.25mA inpul currenll is recommended where possible 10 achieve besllinearitY. Up 1050% duty cycle 10.5mA) is recommended above 200kHz. 2 Adjuslable 10 zero. See Oflseland Gain Adjuslmenl seclion. 3. Linearity error is specified at any operating frequency from the straight line intersecting full scale frequency and 0.1 % of full scale frequency. See Discussion of Specifications section. Above 200kHz, it is recommended all grades be operated . below +85°C. 4. ±O.015% of FSR for negative inputs shown in Figure 7. Positive inputs are shown in Figure 6. 5. FSR = Full Scale Range (corresponds to full scale frequency and full scale input voltageJ. 6. Exclusive of external components' drift. 7. Positive drift is defined to be increasing frequency with increasing temperature. B. For operation above 200kHz up to 500kHz, see Discussion of Specifications and Installation and Operation sections, 9. One pulse of new frequency plus 1",sec. ABSOLUTE MAXIMUM RATINGS Supply Voltages Output Sink Current (FOUT) Output Current (VOUT I Inpul Vollage. -Input Inpul Vollage, +Input Storage Temperature Range VFC32BM. SM VFC32KP ±22V SOmA +20mA ±Supply ±Supply -65°C 10 +lS0oC -25°C 10 +85DC MECHANICAL VFC32BM, VFC32SM TO-100 PACKAGE F NOTE: Leads in true position within 0.10" (0.25mml R alMMC at seating plane. y-f1 t:B--< ...... , Stability Analog Input Full Scale Drift (gain.t. offset) Grade: BP (hotlcoJd)CJ' BM SM Offset Drift Grade: BP BM SM Frequency Input Full Scale Drift (gain.t. offset) . Grade: BP (hot/cold) '" BM SM 0.1 0.2 0.005 0.01 0.001 0.001S. 0.002 0.002 ±ISI±SO ±ISI±SO ±30/±60 ±30/±100 ±I ±I ±I ±IS/±SO ±ISI±SO ±30/±60 0.1 0.2 % %ofFSR'" 0.025 0.001 0.0015 0.05 0.002 0.002 ±S01±loo ±2O/±SO ±2O/±SO ±301±60 ±30/±1S0 ±SO/±ISO ppm/'C ppm/'C ppmj'C ±3 ±3 ±3 ±I ±I ±I ±3 ±3 ±3 ppm of FSR/'C ppm of FSRj'C ppm of FSRj'C ±30/±100 ±30/±100 ±30/±100 ±SO/±Ioo ±2O/±SO ~~j~ ±3O/±ISO ±30/±ISO ±30/±ISO :!:50/±ISO % ofFSR %O~~:;: %of (/% ppmj'C ppmrC ppmj'C D~nanlic ~~ponse . . Settling Time to wlthm linearity specification for full ....Ie input step Overload Recovery Time I period of new frequency + I psce I period of new frequency + I,.sec I period of new frequency + I p.sec I period of new frequency + I,..ec OUTPUT Voltas< Output Voltas< Ranse Output Current Output Impedance (closed loop) Capacitive load Frequency Output (open colleetor) Pulse Characteristics Logic "I" LoBic "0" (at"" -8mA Pulse Width Output Sink Current (Logic "0", ., 0.4V) Output L~kas< Current (Logic "I") Fall Time loUT Oto+IO +10 Rated Supplies Supply Range Supply Drain '(independent of operating frequency) V +10 rnA I 100 I 100 +VPULl.... UP 0 20 = -SmA, CLOAD = SOOpF .POWER SUPPLY I oto +10 " .. +0.4 2S 8 8 mA 100 nA 400 400 nsec ±20 V V ±6.5 rnA ±IS ±20 ±S.5 V V ,.sec 2.5 100 ±IS ±9 +0.4 +VPULL-UP 0 2.0 0 pF ±6.5 6-377 ±9 ±S.5 ELECTRICAL SPECIFICATIONS CONTINUED: Specifications at TA = +2S"C and -+ISVDC power supply unless otherwise noted VFC42 MODEL VFC52 MAX MIN -25 -55 +85 +125 -55 -55 -55 MIN TYP TYP MAX 'UNITS -25 -55 +85 +125 "C +125 +100 -55 -55 +125 +100 "C +125 -55 +125 "C TEMPERATURE RANGE Specification Grade: BP. BM SM Operating Grade: 8M. SM BP Storage Grade: BP. BM. SM TABLE I. Electrical Specifications ABSOLUTE MAXIMUM RATINGS aboye which unit may be damaged. Supply Voltages Output Sink Current (F'Ml'u,) Output Current (V"UII"'I) Input Voltage. Pin 14 Input Voltage. Pin I Storage Temperature Range Grade: BP. BM. SM ±22V SOmA "C "c NOTES: I. % of FSR ~ % of Full Scale Range. 2. Rated at full scale input and ±ISV supplies. 3. Hot = +20"C to highest rated temperaturei cold = lowest rated temperature to +20"C. +2OrnA CONNECTION DIAGRAMS ±Supply ±SuJ"lPiy (Gain Adjust (optional) _ _ R,' -55"C to +125"C MECHANICAL SPECIFICATIONS 11 II .' t 0.498" (l2.6mm) VFC42BM, VFC42SM VFC52BM, VFC52SM Hermetic Metal Package l 14 Pin DIP ~~~~~-0-.8-58-"~~~~~~1--L-(2Umm) Rx 200n • ~ 0'160"~ "'.:::;;=;;:::;;=irr-;;:::;;=i;;;:~ (4.06mm) I -- C---O-2I" - -I 1- 0.10" (2.54mm) (S.3·3mm) - '-'-- 0.018" 41- _I 0.30' (O.46mm) . . . . . , (7.62mm) Tolerance (inches): .xxx ±O.OOS; .xx ±O.02 Connector: 14 pin DIP (14SMC) Case Material: Base - gold-plated kovar Cap - nickel-plated kovar or steel Pin material and plating compositions: Conforms to Mil-Std-883. Method 2003 (solderability) except paragraph 3.2 (aging). Hermeticity: Conforms to Mil-Std-883. Method 1014.Condition C. Step I. Fluorocarbon (gross leak) and Condition A. Helium. S x IO-"'cc/sec(fine leak) FIGURE 4. Connection Diagram for V/F Operation Rx 200n Gain Adj. (optional) FIGURE 2. Hermetic Metal Package Specifications T VFC42BP,VFC52BP 0.50" (l2.'7mm) ~.__p_in_I_I_n_de_n_ti_fi_ca_ti_o_n__~~ ~ 0.80" r-(20.3mm) -l 1-~25" lm-n-T ~_~mm) -I Epoxy Package 14 Pin DIP l- (2.54mm) 0.10' Tolerance (inches): .xxx ±o.OOS .xx ±O.02 Connector: 14 pin blP (145MC) Case Material: epoxy - 0.20" (5.08mm) . "-- ,,~~~~ .1 ~w J--+-tf.... f" (7.62mm) Pin material and plating composition: Conform to Method 2003 (solderability) of Mil-Std-883 (except paragraph 3.2). FIGURE 5. Connection Diagram for F IV Operation FIGURE 3. Epoxy Package Specifications 6-378 OPERATING INSTRUCTIONS VFC42 and VFC52 can be connected for either V IF or F I V operation. Only one external component, the output pull-up resistor, is required for V I F operation. F I V operation requires the pull-up resistor and input biasing components. Gain error is the most significant error in either configuration and may be nulled out with the optional trim circuit (Rx and Ry). The offset error is laser trimmed at the factory and no external adjustment is required. Selecting R A , RB, and C A : Input components RA, RB and C A are selected so that the trigger voltage (VT ) is more negative than -0.6V and transition time (t,) is between 0.3 itnd 15 jlsec for VFC42 and between 0.3 and 1.5 jlsec for VFC52. Table II gives values for input components for several common signal sources. Values for R A , RB and C A may be selected by the user when input signal characteristics differ from those listed. Conditions described above for trigger voltage and transition time must be observed. Equations to calculate trigger voltage and transition time are: Power Supply Consideration: Power supplies stable to within ±I % are recommended to maintain conversion accuracy. Each supply should be by-passed with O.OljlF capacitors located as close to the VFC as possible. VOLTAGE-TO-FR EQUENCY OPERATION VB Calculating the Value of Pull-Up Resistor, R p : The open collector output can be used to drive DTL, TTL, CMOS or discrete circuits. The maximum collector current allowed for TTL circuits in logic 0 is 8mA. Rp may be calculated by this equation: Rp min = V pull-up/(8mA - iLoAD). A 10% carbon composition resistor is suitable for this purpose. The collector current may be as great as 30mA if a logic 0 voltage of I.OV is tolerable. pin 10 tl = Input T == Time constant of R A' R B . C A as connected pulse width If input pulse amplitude is greater than +Vs - IV, a voltage larger than +Vs will be applied to pin 10. Since this may damage the unit, a diode connected across RA with the cathode tied to + Vs is required. Gain Adjustment Procedure: Connect Rx and Ry as shown in Figure 4. Apply positive full scale voltage to the input and adjust Rx until 10kHz ±I Hz (VFC42) or 100kHz ±IOHz (VFC52) is obtained at fouT. Rx and Ry should have temperature coefficients of< 500ppm. These external components will add less than 5 ppmj"C to temperature drift. Output Characteristics: Selecting CB: Output ripple voltage amplitude is inversely proportional to the input frequency and to the value of the integrating capacitance, C, + CR. Ripple, therefore, will be greatest at low frequencies and at small values of C2 + CB. Conversely, time required for the output to settle is directly proportional to the value of C, + CB and is least with small values of C, + CB. There is, therefore, a trade-off between output ripple amplitude and output settling time. Because ripple amplitude is greatest at lowest input frequency itis at this point where the trade-off will usually be made. Ripple voltage and integrating capacitance value are related in this manner: FREQUENCY-TO-VOLTAGE OPERATION Input Characteristics: VFC42 and VFC52 can be connected as frequency-to-voltage converters as shown in Figure 5. fIN should be a positive pulse train with minimum pulse width of 1.0jlsec and rise and fall times of ~ 300nsec. The input train (fIN) is differential and applied to the input of the comparator (pin 10). Refer to Figure 6. Threshold voltage of the comparator lies between -0.6 and +1.0V. When comparator input is less than -0.6V it triggers the one shot. cB = -(25 x 1O- 6 )lsec farads Qn [1 _ VRipple I 30V where t is equal to 25 jlsec in the VFC42 and 2.5 jlsec in the VFC52 and C is the integrating capacitance. VFC42 VINPUT(V) VFC52 VBIAS (V) Input Type Low ~+0.5 High ;:, +2.8 ;:'+4.5 +1.1 +1.2 10V CMOS ~+1.0 ;:, +9.0 +1.1 15V CMOS ~+1.5 ;:'+13.5 +1.1 TTL 5V CMOS = Bias voltage on Vin =- Input pulse amplitude ~+0.4 RA (k.o) 12 RB (k.o) CA (pF) RA (k.o) RB (.0) CA (pF) 1.0 1.6 1000 2200 8.2 9.1 680 680 12 1.0 2200 6.2 680 820 510 680 12 1.0 2200 6.2 510 680 18 TABLE II. F I V Input Component Selection. 6-379 Calculating output response time versus integrating capacitance is an iterative process and is plotted in Figure 7. These curves are for zero to full scale input frequency transitions. If faster response time with lower ripple voltage is desired. a low pass filter can. be connected in series with the output Gain 'Adjustment' Procedure: Connect Rx and Ry as shown in Figure S. Apply full scale frequency to the input and adjust Rx until full scale voltage is +IOV ±lmV (discounting ripple). Rx and Ry should have temperature coefficients of < SOO ppm. These external components will add less than S ppm! "c to temperature drift. 1\ '" .3 I, ;;; -------.~I~---- u - 01 ~> IOC. of Final Value E "- ';;)()( ) .,.] 03 05 .~ _~~ of Final Value « - 0.1 U~ ,I" -E.IO .1% of Final Value Q. 0.2.S 0; +Vs 0.5 1_---1, -----o~ ov-.--~--------~~~~~­ '"~ v·, I.C) 10 1.0 100 1000 10 100 10,000 1000 Settling Time (msee) FIGURE 7. F/V Mode Output Settling Time Vs. Ripple Voltage Amplitude for Full Scale Frequency Change APPLICATION VFC42 and VFCS2 can be used to convert analog data into a digital pulse train for transmission over long lines through high EMI environments. Illustrated in Figure 8 is a V/F, F/V combination that can be used to transmit analog data of 0 to + IOV span over a lOon shielded, twisted-pair. The voltage ripple amplitude at the output will be IOmV for a IOV output and the settling time for a full scale 0 to + IOV change is 60 milliseconds. -ISV +ISV +ISV -ISV 4 Oto+IOV sion 13 S Ana. Com. VouTr-.-.....- .. O to +IOV ' - - - hl..... 1 Dig. Com. S.J. 14 I3 10 10 f n, VFCS2 VFCS2 VIN FIGURE 8. V/F, F/V Data Transmission Circuit 6-380 I ~ I.O.E .~ VFC42 1.0 "FC52 0.1 FIGURE 6. F/V Input Waveforms g ~ Q. E BURR-BROWN® 4804 IElElI Low Cost 12-BIT POWER DAC FEATURES • DIGITALLY PROGRAMMABLE VOLTAGE SOURCE ±3OVOC, 1A Continuous Output • RESISTOR-PROGRAMMED VOLTAGE RANGE AND CURRENT LIMIT • LOW COST • INPUT STORAGE REGISTER • ±l12LSB MAXIMUM NONLINEARITY DESCRIPTION The 4804 Power DAC offers versatility and low cost in automatic test equipment and process control applications. The output range is ±30VDC at I A with built in current limiting at ±1.2A. By adding one external resistor, you can select any full scale output range less than ±30VDC and still maintain 12-bit resolution. Also, the current limiting can be varied by changing the value of two easily accessible resistors. The package was designed for mounting on a PC card and can dissipate up to 20W internally in free air with no external heat sinking required. International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tal. [6021 746-1111 . Twx: 9111-952·1111 . Cable: BBRCORp· Talex: 66-8491 PDS-335A 6-381 DETAILEDDES(lRIPTION GENERAL io'reduce gain and offset err6fs below the sp'ecified values, ·QFi'SET ADJUST and GAIN ADJUST trim points are provided. f~llow the procedure shown on 6-385. The 4804 consists of a 12-bit storage register with str<'lbed' inputs, a 12-bit digital-to-analog converter, arid a power output stage. By changing the input code according.to Tll;\)le I, the output voltage may be varied between ±30V with output currents up to 2A continuous. The maximum intetnili power dissipation for various output conditions is described in Figure 3 and 5. Care must be taken not to exceed the power dissipation limits for the thermal environments described in the figures. POWER AMPLIFIER The power amp stage buffers the Df A converter signal and provides the power output capability. Connecting the ±30V RANGE pin to the output will preset the full scale range to ±30V, giving the transfer function described in Table I; i.e. I LSB = 14.65mV. RF and RS were selected for optimum temperature stability to minimize gain drift errors, and the offset of the Power Amplifier has been nulled at the factory. By connecting a resistor between the VOUT RANGE ADJUST pin and the 0lltput, a variety of full scale ranges can be selected while main!ainirigI2-bitresolution. . . No external adjustments or components are required to achieve the specified accuracy. If improved performance is required, two adjustments will null the offset and gain errors. The procedures for adjusting these parameters are described on page 6-385. . ' To minimize noise levels in the 4804 the analog and digital signal returns are not internally connected. For proper operation, these two grounds must be externally connected together. For optimum stability, the external resistor should have a T.C. which is less' than ±10ppmf oC. The ±35V inputs to the power amplifier may be reduced if full scale ranges less than ±30V are desired. To maintain the best accuracy, these supplies should notbe reduced below ±15V. Since the 4804 output current is derived from the ±35V power inputs, the current-carrying capability of these power supply connecting leads should be considered. STORAGE REGISTER The storage register consists of 12 integrated-circuit, positiveedge-triggered flip-flops utilizing TTL circuitry. The logic levels at the register inputs are transferred to the Df A converter on the positive-going edge of the strobe pulse. Strobing occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the strobe input is at either the high or low level, the inputs to the register have no effect on the Df A converter inputs. The strobe and register are fully compatible with most TTL or DTL circuits. Rp and RM determine the output positive and negative current limits, respectively, of the output. They have been preselected for current limiting of ±1.2A, typo The current limiting. can be changed by replacing Rp and RM with other values according to the following formula: 1.2V R=---Icurrent limit DIGITAL-TO-ANALOG CONVERTER It is not necessary that Rp and RM be the same value. Since the output current of the 4804 flows through these resistors, the power dissipation of Rp and RM should be considered. Both resistors are stud mounted for easy accessibility. The DfA converter stage accepts the digital output from the storage register and converts it into a bipolar analog signal according to Table l. Of108' Error Adj. ~­ BIT Gain ~~~j.- ~ MSB. d'~--~r-----~--JL----I~----~ 1 <: 2 3 4 5 6 """,,----., "'-"cv----. ......~---. 'Ul' .v-----. ......,.....---" 7 ,,-'.....----. B ('j1ID---I a: w I!!! C!l w a: a: w I- 30k. r---------~'W-------C9T ±30V RANGE ...---------------<:10T V OUT RANGE ADJ. 10k a: w > z o (J « 9, """",,,'---., 10.....,.,...----. 11 o W-----{:1B,1T 12 -35VDC LSB .......---------------{:3B,3T STROBE ([I1iD-------..J L_ ---<1~D-~- I __ @)-_-@)-_@- ____ J BB,BT No Connection -15VDC +15VDC FIGURE 1. Block Diagram 6-382 +35VDC SPECIFICATIONS = ±30 Typical at 25°C, rated power supplies, and Vout range unless otherwise noted. MECHANICAL ELECTRICAL '" INPUT .. 101 85rnm (4.010")max --- • 12 bits Keso utlOn Logic levels (TTL/CMOS Compatible) ±2V ' ~H:;~:::.''''''fi~J~ f ±29.98SV,(= 30V -ILS8) (see Figure 5 and Note 1.) Output Current '83 4.83 . mm 10.19") I~~ Voltage Range @ [out = LOA j (3.62") ~IN1--J lOO,",sec max, OUTPUT '0 1,0") \ . L2A typ , lOmax ~: ±ISVDC, +SVDC, ±3SVDC ±S% 4804 Connector: POWER SUPPL Y REQUIREMENTS Power Supply Operating Ranges Supply Drain ±15V +S ±3SV T 145mm (5.71") max . Individual Error Contributors Linearity Error (Ooe to +70o C) Differential Linearity Error Rated Voltages ~u.!:'~~ -e- -e- TRANSFER CHARACTERISTICS TOTAL ACCURACY Extruded, black-anodized"alumirlum heat sink and discrete components mounted on glass epoxy printed circuit board. . Amp 2 - 86479 - 3 .. Recommended mating ±2SmA ~: +80mA ±40mA ±output current PC card: 0806MC Flexable: Scotch flex 3417 - 0000 Diameter of mounting holes: 3.56m",;·(O.14")·' TEMPERATURE RANGE Specification Operating Storage OoC to +700 C -2SoC to +8SoC -SSoC to +I2SoC PIN CONNECTIONS 80TTOM NOTE 1: Output amplifier is capable of sourcing or sinking 2 amps: CC;JOtinuously. Resistors RM and .Rp have been selected to current limit the output current to ± 1.2 A typo To increase lout capabnity. or modify the -35V Output +35V N.C. -15V current limit setting, replace RM and Rp according to instructions on page 6-382. Internal power dissipation should be considered. especially at low output voltages. Ana. Com. ABSOLUTE MAXIMUM RATINGS N.C. Offset Adj. +15V Ana. Com. Strobe +5V +SV Supply ±15V Supplies ±3S Supplies Digital Inputs Power Amp Case Temp Output Amplifier Power Dissipation Output Current +7V Dig. Com. Bit 2 ±20V ±40V +7.0V with +5V supply +7V +12S C 20W max in free air .• derate O.2Wl C above +2SoC See Figure Sand Not. 1 6-383 6it4 Bit 6 Bit 8 Bit 10 Bit 12 .!!!Jl! · ··· ··· ··· ··· '·. 1 2 3 4 5 6 7 8 9 • 10 • 11 .12 .13 • 14 • 15 .16 .17 • 18 .19 ·· ···· ··• · !Qf -35V Output +35V N.C. -15V Ana. Com. +15V Ana. Com. +30V Range V out RanS' Adj. Gain Adj. +5V Dig.C.Qm. Bit 1 Bit-3 Bit 5 Bit 7 Bit 9 Bit 11 TYPICAL PERFORMANCE CURVE'S ('rypical @ 2S oC and ±lSVDC Power Supplies unless otherwise noted) h 30 . .=" ~ i5 ~ .S 20 ~ 15 t~. .. 0 f'.... 10 0.. E ~ 6o C/Watt ." ~" = ~ = U ';; fr o= ~ oS 50 25 75 100 125 Ambient Temperature (OC) 150 -30 FIGURE 2. Power Derating Curve. -20 -10 10 20 o Output Voltage (Volts) 30 FIGURE 3. Safe Operating Area. +3 5 ",30 f -30 o~~~~==~~~ ±10 f20 t30 ±40 -3 5 o 25 50 75 Time (!'s) 100 Output Voltage (Volts) FIGURE S. Output Amplifier Power DiSSipation vs. Output Voltage. FIGURE 4. Pulse Response. DIGITAL INPU'T CDDES VS. VOUT NOMINAL OUTPUT VOLTAGE INPUT CODE LSB MSB ±30V RA,NGE VARIABLE RANGE 111111111111 +30.000V +io.OOO(RGI V 10k 111111111110 +29.985V +9.995(R G ) V 10k 100000000000 +i4.65mV +4.8S( 011111111'111 O.OOOV O.OOOV 0111111111 10 c1 4 .651l'1V -4.88( RG ) mV 10k 0000000000001 -29.?1IY -9.99~~~) V 000000000000 -29.985V , (RGI -9.995 10k V TABLE I. 6-384 ~~k) mV " PROCEDURES FOR ADJUSTING OFFSET AND GAIN ERRORS ... OFFSET AND GAIN ADJUSTMENT The offset and gain of the DI A converter stage may be trimmed using externally connected OFFSET ADJUST and GAIN ADJUST potentiometers. The adjustment procedure is outlined below. Since the GAIN ADJUST is connected to a high impedance point in the D/A converter, a ceramic capacitor connected between this pOint and analog common is recommended to minimize noise pickup. The offset error should always be nulled before adjusting the gain error potentiometer. OFFSET ADJUST PROCEDURE GAIN ADJUST PROCEDURE Apply the digital code which could give the maximum positive voltage output and adjust the OFFSET ADJUST potentiometer for the proper output voltage. For example, if the 4804 is connected for a full scale range of ±30V, apply all ones to the input and adjust the potentiometer for an output of+30.000V. Apply the digital code which should give the maximum negative voltage output, and adjust the GAIN ADJUST potentiometer for the proper output voltage. For example, if the 4804 is connected for a full scale range of ±30V, apply all zeros and adjust the potentiometer for an output of -29.985V. +Full Scale Output +15V ~~nTl Analog 6 >f .OOlIlF to .01IlF lOOk (Offset Adjust Translates the Line Vertically) -15V GAIN ADJUST Common Input "'I--+--HI-..cl'++-~~<++-{J-+-t-+-I Input Alii's " ..... All O's +15VDC 1 ~~"a 0 MSB= 0 100k All others = I -15VDC "'''t. ~~~,j ~~b -Full Scale __ " ......_OU---'tP'-u_t==-:-':-=:--f-_ _ _ (Gain Adjust Rotates the Line about x Adj . '..lITRange OFFSET ADJUST FIGURE 6. FIGURE 7. DISCUSSION OF SPEOIFIOATIONS DIGITAL INPUT CODES Lineary Error for the 4804 is specified as a maximum over the temperature range of ooe to +700 C. This means that the analog output will not vary by more than ±~ LSB maximum from an ideal straight line drawn between the "all bits ON" and "all bits OFF" end points. The 4804 accepts TTL and CMOS compatible input codes in binary format. Table I shows the output voltage for selected inputs. ACCURACY Differential Linearity is the deviation from an ideall LSB voltage change from one adjacent output state to the next. A differential linearity error spec of ±~ LSB means that the output voltage step sizes can be anywhere from ~ LSB to 3/2 LSB when the input changes from one adjacent input state to the next. Total Accuracy is the maximum deviation from the ideal output over the full output range. It is tested at 25°C and represents the maximum allowed value of the sum of the individual errors. The total accuracy is specified as a maximum with the 4804 in the ±30V range configuration. If an output range less than ±30V is selected, the accuracy will improve as the power amplifier gain is reduced. Monotonicity over oae to +700 e is guaranteed in the 4804. This insures that the analog output will increase or remain the same for increasing input digital codes. 6-385 The maximum change in OFFSET is referenced to the OFFSET at 25 0 C divided by the temperature range. This drift is expressed in parts per million of full. scale ranges per °c (ppm of FSR/oC). DRIFT Gain Drift is measure of the change in the full scale range analog output over temperature. The GAIN DRIFT is determined by testing the end pOint differences at OOC, +25 0 C and +700 C, calculating the GAIN ERROR with respect to the 25 0 C value, and dividing by the temperature change. This specification is expressed in ppm/oC. POWER SUPPLY SENSITIVITY Power Supply, Sensitivity is a measure of the effect of a power supply voltage variation on the 4804 output. It is defined as a change in output voltage per change in supply voltage with the ±30V output range. Power supply rejection is improved if a full scale range less than ±30V is selected. Offset Drift is a measure of the actual change in the output with all bits OFF (all O's) over the specified temperature range, and is measured at OOC, +25 0 C and +700 C. OPERATING INSTRUOTIONS REMOTE SENSING In applications requiring that the load be located some distance from the Power DAC, the line resistance from the 4804 to the load can cause significant error, especially during operation at high currents. To minimize this problem, connect the circuit with the line resistance inside the feedback 10011 of the output amplifier, as shown in Figure 8. This technique effectively divides the line resistance by the open loop gain of the output amplifier (94 dB min, with RLOAD 5n). To minimize noise pickup, the external feedback resistor should be located as close as possible to the 4804. load voltage will be reduced by approximately ILOAD x RUNE. Proper grounding of the 4804, load, and digital stimulus will also reduce errors caused by ground loops. THERMAL CONSIDERATIONS The absolute maximum internal power dissipation of the output amplifier is 20 watts in free air at 25 0 C. Derate by O.2W/oC above 25 0 C. Thermal resistance from amplifier junction to ambient is 6 0 C/watt. Figure 5 shows internal power dissipation as a function of otuput voltage and load resistance with ±35V supply voltages. Since the amplifier must still overcome the voltage drop in the line inside the feedback loop, the dynamic range of the V out Range External Feedback Resistor Adlust Digital Stimulus ~ _ _ _~~_ _ _ _ _.... V 10ad Digital Com. Power Supply FIGURE 8. Grounding Scheme With Remote Sensing = V out -I load x R L'lne MILITARY PRODUCTS GROUP Wafer Processing Wafer Proceillng High quality products for demanding military and industrial applications are produced by our Military Products Group in a totally separate facility within Burr"Brown's complex. Reliability is designed and manufactured-into our Military Products under the guidance of MIL-M-38510. All product fami lies are fully specified from -5SoC to +12SoC with up to three performance grades arid two product assurance levels (/8838 and /MIL). The/883B models are 100% screened to MIL-STD-88::S, level B, method SOO4 or S008. The/MIL models have additional requirements of 10% PDA and QCI consisting of groups A and B on each inspection lot. How stringently our Military Products group controls and documents the assembly and testing of its products is described in the product flow section that follows. All materials used by the Military Products group have unique component specifications to assure their conformity to MIL-STD-883, methods 201 0 and 2017. Environmental control in our clean room areas meets and often exceeds Federal Standard 209B requirements for particle count. ESD (electrostatic discharge) procedures are fully observed through every stage of material handling, product assembly, testing, storage and shipment. Operator training, certification and re-certification conform to MIL-M-38S1 O. MTTF data is based on actual product performance, not just calculated values. Qualification reports and test data are available. All data sheets follow military slash sheet format and, because of their completeness, can be transferred directly to your drawings with minimal modification. This standard QPL slash sheet format simplifies your requests to government agencies for non-standard parts approval. 7-1 A CONTROLLED MANUFACTURING FACIUTY DEDICATED EXCLUSIVELY TO MILITARY QUALITY PRODUCTION • PERSONNEL - All production and quality control personnel directly involved with fabrication, inspection, testing and handling. perform their functions according to appropriate MILspecs. ' • TRAINING - Operator training and certification programs provide trained personnel qualified to assemble and test the products. Certification requires classroom training and written examinations for initial certification. Periodic written exams must be passed to maintain certification. • WORK-IN-PROCESS ENVIRONMENT - All workin-process is stored in a nitrogen environment. Critical assembly processes; die visual, die attach, wi rebond and all inspections are performed under laminar flow hoods - equipped with ion grids - in a class 100 environment. • ENVIRONMENTAL CONTROL ,- Clean room procedures, which conform.to Federal Standard 209B, provide class 10,000 clean' air exceeding the class of 100,000 requirementon.IIIL~STD-883. • MATERIAL CONTROL - Each product has a complete and current flow chart and flow sheet to assure accurate processing through assembly and test. Each manufactu ri ng lot contains the lot numbers of its components listed by the quality control inspection identification (QCID number) all traceable back to the incoming vendor's lot number. • MANUFACTURING LOT CONTROL - Each lot has a unique flow sheet which documents lot number, parts list, operation, quantity, date of operation and operator's identification. • EQUIPMENT CALIBRATION - Performed under the guidance of MIL-STD-45662. • QUALIFICATION - All/MIL models are initially qualified per MIL-STD-883, method 5004 or5008, groups A, B, C and D as described in the products' detailed specification. • STATIC CONTROL - To minimize static (ESD) damage, antistatic smocks, stainless steel table tops, stainless steel work-in-process trays, ground straps, ion grids under laminar flow hoods and anti-static shipping materials are used. • RECORD RETENTION - All flow sheets containing process data and inspection records are retained for three years. Asiembly Under Lainlnar Hood Wlrebond (Gold) Ole Attach 7-2 Ole Shear, PRODUCT FLOW INCOMING OUALITY CONTROL INSPECTION Assures that all materials meet requirements of the applicable component specification. Usage tests are performed and vendor lot traceability begins. All material is maintained in a bonded stockroom to assure traceability. Orgination of manufacturing flow sheets, bill of material, materials and lot traceability records. ASSEMBLY· MIL·STD-B83 CONDITION B • OC LOT FORMATION GATE • KIT INSPECTION • DIE ATTACH • IPOC DIE SHEAR • INTERNAL LEAD WIRES .,POC WIRE PULL GATE • PRE·CAP VISUAL INSP. • QC Lot Formation Gate - matches flow sheet, bi II of materials and traceability records with materials issued from the stockroom • Kit InsRection - piece parts and die are 100% visually inspected to methods 2010 and 2017. • Die Attach - eutectic (providing low ohmic contact) and non-conductive epoxy (cured at 25°C above storage temperature in nitrogen). • In Process DieShearGate- performed to method 2019 on each manufacturing lot. Assures the integrity of the die attach method. • Internal Lead Wires - Wires are ofthe same metal as the die metalization. Aluminum ultrasonic wirebond machines are mounted on shock tables to insure quality bonds. Gold-to-gold wirebonds are performed with thermosonic wirebond machines. • In Process Wire Pull Gates - bonding operations are monitored at the beginning of each shift, every four hours, with a new lot, new operator or a machine adjustment. Both destruct and nondestruct tests are performed and the length and width of each wirebond is measured to verify conformance to method 2010 or 2017. • Pre-CaR Visual InsRection - Although not required by MIL-STD-883 it is performed by BurrBrown to method 2010 or 2017. Performed on all products that require laser trimming. All products that require laser-trimming receive a 72-hour burn-in, in nitrogen, at +125°C. 7-3 Resistor networks ,are laser-trimmed to meet applicable specifications. FINAL VISUAL • PRE-CAP "B" VISUAL INSP_ • IPOC OC CSI/GSI • Pre-Cap "8" Visual Inspection - a 100% visual inspection to method 2010 or 2017 . • In Process QC Pre-Cap "8" Visual Gate performed to method 2010 or 2017. (Source Inspection performed if required.) Following a vacuum bake at +125°C (to meet method 5004 or 5008 moisture content requirements) products are welded, gold/tin or glass sealed. Marking is in accordance with MIL-M-38510 and , consists of; • Part number • Seal date code • Manufacturer's identification (fl!!!im'"') • Manufacturer's designating symbol (CESS) • Country of origin A 24-t:lOur minimum bake at +150 o C per MIL-STD883, method 1008, condition C. Ten cycles, from -65°C to +150o C per MIL-STD883, method 1010, condition C. Performed to MIL-STD-883, method 2001, in the y, , ax,is only. PRE-BURN-IN ELECTRICAL TEST (OPTIONALI Product performance is compared to the specified DC parameters at 25°C. Total burn-in time is 160 hours minimum at an ambient temperature of +125°C per MIL-STD-883, method 1015. Product performance is compared to the specified DC parameters at 25°C. All 25°C parameters , specified in the data sheets are read and recorded. 7A /883B MOOELS The assembly lot PDA (percent defective allowable) cannot exceed 10%. All drift parameters as specified in the data sheet are 100% tested at -55°C, -25°C, +25°C, +85°C and +125°C. 100% test to Mll-STD-883, method 1014, test condition A. 100% test to Mll-STD-883, method 1014, condition C. FINAL VISUAL -IPQC GATE FINAL VISUAL -IPQC GATE QUALITY CONFORMANCE INSPECTION BONDED FINISHED GOODS STOCK ROOM Bond Measurement 100% external visual inspection to Mll-STD-883, method 2009. • Final Visual Quality Control Gate - to MllSTD-883, method 2009. GroupsAand B inspection of Mll-STD-883, method 5005 or 5008 are performed on each inspection lot. Groups C and D inspections are performed when agreed to by contract. A report of the most recent Groups C and D inspections is available from Burr, , Brown at a nominal chargl;l. This product flow illustrates major operations only. Space does not allow a complete description of the numerous details of all operations. Processes and flows may change to conform to latest revisions or to improved product performance and quality. Wire Pull 7-5 SELECTION GUIDE Military Products ANALOG-TO-DIGITAL CONVERTERS Resolulion Linearity Conversion Time Bits 12 12 12 12 12 ±LSB. max "sec. max 112 8 8 8 8 8 Model ADC871M1l(1) ADC87/883B ADC87 ADC87U1883B ADC87U 1/2 1/2 1/2 1/2 Price(4) Gain Drift Temperature Inpul Range V ±ppmI"C. max 15 15 15 15 15 ($) Range MIL MIL MIL MIL MIL ±2.5. ±5. ±10. 010 +5. 010+10 1 Package { 32-pin DIP Unit Page 415.00 325.00 290.00 270.00 230.00 7-7 7-7 7-7 7-7 7-7 DIGITAL-TO-ANALOG CONVERTERS Price(4) Resolution Model Bits DAC87-CBI-VlMIL DAC87-CBI-VlB DAC87-CBI-V 12 12 12 DAC87U-CBI-VlB DAC87U-CBI-V 12 12 Linearity ±LSB. max 1/2 1/2 1/2 li2 1/2 -55OC/+125OC 20 20 20 Settling Time max 7 7 7 -25°C/+85°C -25°C/+85°C 20 20 7 7 Gain Drift ±ppm/oC, max Monolonlcity -55°C/+125°C -55°C/+125°C Oulpul Ranges ±2.5. ±5. ±10. 1 +5. +10 Temperature Range MIL MIL MIL MIL MIL (S) Package I Unil 275.00 225.00 180.00 24-pin DIP 165.00 125.00 Page 7-23 7-23 7-23 7-23 7-23 MULTIPLIERS Price(4) Accuracy al 250C +%, max Model 112 112 4213VM/MIL 4213VM/883B 4213VM 1 1 1 4 4 4 4 4 4213UMl883B 4213UM 1 1 2' ,2' 4213WM/883B 4213WM Feedlhrough Outpul Offset Accuracyal125°C ±%,m8x ±mV, max ±mV, max 50 50 100 100 100 25 25 30 30 30 100 100 50 50 Oulput V. mA. min 1""~ (S) Temperature Range MIL MIL MIL MIL MIL . Mil MIL Package TO-l00 TO-loo Unit Page 125.00 110.00 TO-l00 TO-l 00 TO-l00 95.00 88.00 53.00 TO-loo TO-l 00 45.00 35.00 7-92 7-92 7-92 7-92 7-92 7-92 7-92 'al+85°C. VOL TAGE-TO-FREQUENCY CONVERTERS Price(4J Linearity % FSR. max Full Scale Drift ppm FSRI"C. max Temperature V FOUTRange kHz, max Range Package VFC32WM/883B VFC32WM ±10 ±10 500 500 ±0.006 at 10kHz ±0.OO6all0kHz ±loo at 10kHz ±loo at 10kHz MIL MIL VFC32VM/MIL VFC32VM/883B VFC32VM ±10 ±10 ±10 500 500 500 ±0.01 all OkHz ±O.OI all0kHz ±0.01 all0kHz -400. +150 al200kHz -400. +150 at 200kHz -400. +150 al200kHz MIL MIL MIL TO-l00 TO-l00 TO-l00 TO-l00 TO-l00 VFC32UM/883B VFC32UM ±10 ±10 500 500 ±D.Ol at 10kHz ±0.01 all0kHz ±150 at 10kHz ±150 at 10kHz MIL MIL TO-l 00 TO-l 00 Y,N Range Model ($) Unil 50.00 40.00 60.00 45.00 35.00 30.00 20.00 Page 7-61 7-61 7-61 7-61 7-61 7-61 7-61 OPERATIONAL AMPLIFIERS Description Model Wideband FET Low Drift OPA600VM/MIL(2) OPA800VM/883B OPA800VM OPA800UM/883B OPA600UM OPA105WMIMILl3)· OPAl05WM/883B OPA105WMI OPA105VM/MIL(3) OPA105VM/883B OPA105V,M OPA105UM/883B OPA105UM General Purpose Bipolar 3500R/MIL 35OOR1883B 3500U/883B Precision 3510VM/MIL 3510VM/883B Bipolar Bias Bandwidlh Offsel Vollage Current Unity Gain drift a125·C ±mV,'max ~vjoC max nA.max MHz. min 2 2 2 20 20 20 5 5 80 80 {~ 2 2 2 5 5 :100pA -100pA -100pA -100pA -100pA -lpA 5 15 15 5 5 5 20 20 20' 0.12 0.12 2 2 ±30 ±30 ±3O ±25 ±25 Slew Rate Vll's,min 400 5OOO.t. A= 1000 400 400 400 400 1 1 1 1 1 1 1 1 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 1 1 1 0.25 0.25 0.6 0.6 0.6 0.5 0.5 Prlce(4) Is ±O.OI% Compen- Outpul ns sation V,mA, min 125 125 125 150 150 ----.------ - 1~' 1,,,Internal t. , MIL. , MIL MIL MIL MIL MIL MIL MIL ("" {±5 {nlernal {±10. ±io internal internal Temp. Range Package MIL MIL MIL DIP MIL MIL ±10.±10 ±10.±10 .. MIL MIL MIL {TO-99 MIL MIL TO-99 TO-99 I (S) Unll 315.00 250:00 225.00 195.00 175.00 Page 7-45 7-45 7-45 7-45 7-45 7-35 75.00 7-35 57.00 7-35 47.00 7-35 55.00 7-35 43.OQ 35.00 7-35 30.00 ",7.,35 25.00 ,\;7-35 45.00 30.OQ 25.00 45.00 30.00 7-73 7-73 7-73 7-84 7-84 tGam-bandwldlh product. -25·C/+85·C. NOTES: 11 ADC87/MIL availabla in Ihe 2nd quarter of 1982. 21 OPA8OOVMlMIL available in the 2nd quarter of 1982. 31 OPA105/MILIavaiiable In Ihe 3rd quarter of 1982. 41 Qty. disc. avaUable. 7-6 BURR-BROWN® IElElI ADC87/MIL SERIES MODEL NUMBERS: ADC87/MIL ADC87U/883B ADC87/883B ADC87U ADC87 REVISION NONE JANUARY, 1982 12-BIT -55°C to +125°C Military ANALOG-TO-DIGITAL CONVERTER FEATURES • HI-REL MANUFACTURE • -55°C TO +125°C OPERATION • ACCURATE ±1I2LSB max linearity Error ±O.l % FSR max Full Scale Absolute Accuracy ±15ppm max Gain Drift • COMPLETE Internal Reference Internal Buffer Internal Clock • B~sec MAX CONVERSION TIME • MIL-STD-B83 SCREENING DESCRIPTION The ADC87/ MIL Series is a high performance, analog-to-digital converter. It features ±1/2LSB linearity, ±O.I% full scale accuracy, ±15ppm drift, 8~sec conversion time, -55°C to + 125°C operation and optional MIL-STD-883 screening. The ADC87 uses successive approximation. It resolves the most significant bit first, then the second bit, then the third, etc. Successive approximation is the most popular high performance design as it is fast and accurate. The ADC87 is a hybrid microcircuit. It is complete with an internal reference, an input buffer amplifier and an internal clock. The converter may be short cycled to provide faster conversions to less resolution. Five analog input ranges, ±2.5V, ±5V, ±IOV, 0 to +IOV and 0 to +20V, are available, and the digital output data is available in parallel and serial format. All digital outputs and inputs are TTL compatible. Standard power supply voltages, ±15VDC and +5VDC, are required. Two electrical performance grades are available. The premium grade operates from -55°C to + 125°C and is designed for military, aerospace, and demanding industrial applications. The U grade has specifications from _25°C to +85°C and from _55°C to + 125°C. Applications include test equipment, shipboard, and ground support equipment where operation is normally between _25°C and +85°C and full temperature range operation must be assured. The ADC87/MIL Series is manufactured on a separate Hi-ReI manufacturing line with impeccable clean room conditions which assures inherent quality and provides for long product life. The ADC87 is hermetically sealed in a metal, welded, dual-in-Iine package. Three product assurance levels are available: Standard, /883B and / MIL. The Standard product assurance level offers Hi-Rei manufacturing where many MIL-STD-883 screens are performed routinely. The /883B product assurance level, /883B suffix, offers Hi-Rei manufacturing plus 100% screen-. ing per MIL-STD-883 method 5008 (class B). The / MIL product assurance level, /MIL suffix, offers Hi-ReI manufacturing, 100% screening per MILSTD-883B method 5008 and 10% PDA. Quality assurance further processes / MIL devices, by performing group A and B inspections on each inspection lot and group C and D inspections periodically and when specified on the customer's purchase order. A report containing the most recent group A, B, C. and D tests is available for a nominal charge. International Alrporllndustrial Park· P.O. Box 114tJ() - TlHlson. Arizona 85734 - Tel. /6021 746-1111 - Twx: 910-952-1111 - Cable: 88RCORP - Telex: 66-6491 PDS-459 7-7 ADC87/MIL SERIES DETAILED SPECIFICATION MICROCIRCUITS, LINEAR ANALOG-TO-DIGITAL CONVERTER HYBRID, SILICON I. SCOPE I. I Scop~ This specification covers the detailed requirements for a precision 12-bit, integrated circuit, analog-to-digital converter. 1.2 Part number. The complete part number is as shown below. ADC87 I Basic model number /MIL T I Grade (see 1.2.1) Hi-Rei product designator (see 1.2.2) 1.2.1 Device typ~ The device isa single, 12-bit, analog-to-digital converter. There are two electrical performance grades. The premium grade has no grade designation in the part number and features specifications and tests from _55°C to + 125°C. The U grade has a U grade designation in the part number and features specifications and tests from _25°C to +85°C, and specifications from -55°C to + 125°C. Electrical specifications are shown in Table I. Electrical tests are shown in Tables II and III. 1.2.2 Device class. The device class is similar to the hybrid class (class B) product assurance level, as defined in MIL-M-38510. The Hi-Rei product designator portion of the part number distinquishes the product assurance levels as follows: Hi-Rei Product Requirements Designator Standard model, plus 100% MIL-STD-883 hybrid class screening with /MIL 10% PDA, plus quality conformance inspection (QCI) consisting of Groups A and B performed on each inspection lot, plus Groups C and D performed initially and periodically thereafter. Standard model, plus 100% MIL-STD-883 hybrid class screening. /883B Standard model including 100% electrical testing. (none) 1.2.3 Case outline. The case outline is as defined in Figure I. The case is metal and is conductive. 1.2.4 Absolute maximum ratin~ Supply voltage, Vee ±18VDC Supply voltage, Voo +7VDC Analog inputs (pins 24 and 25) ±25VDC Buffer input ±18VDC Digital inputs +5.5VDC Storage temperature range _65°C to +150"C Lead temperature (soldering, 60sec) +300°C Junction temperature TJ = 175°C 1.2.5 Recommended operatiilg conditions. Supply voltage range Vee: ±14.5VDC to ±15.5VDC VOIl: +4.75VDC to +5.25VDC -55°C to + 125°C Ambient temperature range 1.2.6 Power and thermal characteristics. Maximum allowable Case outline power dissipation 32-lead can 1500mW at TA = 125°C Figure I 7-8 Maximum 8 J-C 7°C;W Maximum 8 C-A 25"C;W Maximum 8 J-A 32°C;W ADC87jMIL SERIES 2. APPLICABLE DOCUMENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICA nON MILITARY MIL-M-38510 - Microcircuits, General Specification for. STANDARD MILITARY MIL-STD-883 - Test Methods and Procedures for Microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to assure successful compliance with this specification. 3.1.1 Detail sl'ecifications. The individual item requirements are specified herein. In the event of conflicting requirements, the order of precedence will be the purchase order, this specification, and then the reference documents. 3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States of America. 3.2 Design, construction, and pJiysical dimensions. 3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 3.5.1 ofMIL-M-3851O, except that organic and polymeric materials may be used for substrate and die attach. The exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in MIL-M-3851O. 3.2.2 Design documentation. The design documentation is in accordance with MIL-M-3851O. 3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with MIL-STD-38510. 3.2.4 Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel underplating. The lead material and finish is in accordance with M I L-M-385I 0 and is solderable per MI L-STD-883, method 2003. 3.2.5 Glassivation. All dice utilized are glassivated. 3.2.6 Die thickness. The die thickness is in accordance with MIL-M-3851O. 3.2. 7 ~ysical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.8 Circuit diagram and terminal connection. The circuit diagram and terminal connections are shown in Figure 2. 3.3 Electrical Jlerformance characteristics. The electrical performance characteristics are as specified in Table I and apply over the full operating ambient temperature range of -55"C to +125"C unless otherwise specified. 3.3.1 !!tput Rang~ The analog input range is as specified in Table V when externally connected as shown therein. 3.3.2 OutJlut Code. Coding is complementary binary. The digital output codes corresponding to analog input voltages are shown in Table VI. rFA~ ~ NOTE: Leads in true position within 0.010" (O.25mml R at MMC at seating plane. ~ III UUlIIIIIIIIII G -...I I.-0 ---I-- DIM T ~'i+'-------, 0000000000000000 , " INCHES MIN MAX 1.720 Pin numbers shown for reference only. Numbers may not be marked on package. L 3~OOOOOOOOOOODOO"i .100 .140 .150 .300 .9,00 BASIC .100 FIGURE I. Case Outline (Triple-Wide DIP Configuration). 7-9 MIN MAX 44.10 28.45 29.46 4.32 6.35 0.53 .016 .100 BAStC Weight: 25 grams max. MILLIMETERS 43.69 .140 2.54 BASIC 3.56 ADC87/MIL SERIES SERIAL OUTPUT BIT 121LSBI 'Vee BIT 11 BUFFER IN BIT 10 BUFFER OUT BIT 9 +Vee BITB GAIN ADJUST '"' I!:! BIT7 !;l;: z ..... BIT6 ~ BIT5 !is .:. BI14 '"' ANALOG COMMON mv RANGE IOV RANGE BIPOLAR OFFSET BIT3 COMPARATOR INPUT BI12 START CONVERT BIT IIMSBI STATUS BIT IIMSBI CLOCK OUTPUT SHORT CYCLE DIGITAL COMMON Y REFERENCE OUTPUT 18.3V( CLOCK RATE Vuu y Pin 15 Is GlII1l11C11d ID IhI GIl•. FIGURE 2. Circuit Diagram and Terminal Connections (Bottom View). 3.3.3 Transfer Function. An AI 0 converter represents an analog input voltage in a digital output format. The converter resolves the analog input into 12 bits of resolution, or 212 , or 4096 voltage segments. For each voltage segment there is a unique digital output code. The ideal transfer curve, as shown in Figure 3, is a "stair-case"connecting the extremes ofthe analog input range. Minus full scale (-FS) corresponds to digital 1111 1111 1111, the first transition occurs at -FS + 1/2LS B, each bit is I LS B wide, and +FS -I LSB corresponds to digital 0000 0000 0000. An ideal straight line connects each end point and the center of each bit. Note, the coding is complementary. 0000 l1OOO 0000 OODD 0000 0001 ~ 011111111110L !:! 0111 11111111 ll! ~ 10000000 0000 ~'+ fl! 111111111101 111111111110 111111111111 • J<:.J._ _ ~~ _ _ _...I-_ _ ~I _ _ _...J OV ·FS +FS Anllllllinpul IBlpolar Opel'lltilll1l FIGURE 3. 'Ideal AID Converter Transfer Function. 7-10 ADC87/MIL SERIES The 'basic' converter is unipolar in design; that is, OVDC analog input produces one digital extreme and plus full scale VDC produces the other digital extreme. There are two unipolar input ranges. For bipolar operation, a bias (bipolar offset) is introduced into the input such thatOVDC analog input produces midscale digital output. This allows plus and minus analog inputs (see Figure 3). There are three bipolar input ranges. The errors from the ideal transfer function are specified in Table I. Linearity and Differential Linearity are the most meaningful ADC87 accuracy indicators, as they are not externally adjustable. They are factory laser-trimmed. Zero error and gain error are laser-trimmed and may be externally nulled if necessary for the application. The inherent quantization uncertainty due to resolving or quantizing the analog input into bits is ± 1/ 2LSB. 3.3.4 Timing Considerations. The timing diagram is shown in Figure 4. A start convert, positive going pulse, initiates a conversion. The most significant bit (MSB) is determined during the second clock pulse, and each successive bit is determined during the next II clock pulses. When conversion is complete, Status output drops to Logic O. Digital output data is available in parallel or serial format. Serial output data may be strobed out bit-by-bit, during the clock period after the bit is determined. If desired, an external clock may be used. Further infor.mation is available in Applications Information, paragraph 7. - - - - - - - - - - - - - THROUGHPUT TIME CONVERSION TIME START CONVERT INTERNAL CLOCK STATUS 81T IIMS81 "0" 8112 81T3 8114 81T5 81T6 8117 81T 8 r 81T9 81T 10 81T II ··D··r 81T IZILS81 SERIAL DATA OUTPUT ~~~~~~~~ CLOCK W , --- -tr--Lr -lr-Lf-1r-1I-"lf-l[-1[ -If-lf-lf--LJ--lf -1J I I 100!'l.clO200nl8c-ll- I. Slirl Convert musl b.IIIIIII5OnIIC wldllnd musl remain low during con vIRion. Convlrelon Illnltllled by flrl Slert Convlrt trailing Idgl. Oncli convarelon has begun, a IlCOnd Ilirt PUIaI will nol rlllllhe convlrter. Z. Parelill dill will be valid 14On1lC allar ItIIUS gill low Ind remalnl valid untllanolhlr convlrelon Illnltialid. 3. Slrlal dala will bl valid I4On11C aflBr In Internll clock riling Idgl Ind 200nllc IIllr an IXI8rn11 clock filling Idgl. 4. Whln ullng In IXI8rnal cloci. converllon Illnlllalad by flrl failing adgl of the flrll clock PUIII following Illtul going low. Thl converter will continuoosly convert. FIGURE 4. Timing Diagram. 7-11 ADC87/MILSERIES 3.3.5 Zero error and'gain error adjustment. Zero error Imd gain errot may be externally nulled using the circuits shown in Figure 6. See Applications Information, paragraph 7.4.. 3.3.6 Requited external connections. For specified accuracy and speed, connect Clock Rate, pin 17, to OVDC;' pin 1'5. For a 12-bit conversion cycle, connect Short Cycle, pin 14. to Logic I. pin 16. See Applications Information; paragraph 7, for addi.tional. information. 3.4 Electrical testrequirements. Electrical test requirements are as specified inTable·11. The subgroups of Table lII'and limits of Table·IV, which constitute the minimum electricaI.test requirements for screening, qualification, and quality conformance, are specified in Table II.. ' . 3.5 Marking: Marking is in accordance with M IL-M-38510. The following marking is placed on each microcircuit as a minimum. a. Index point' "b. Part number (see paragraph 1.2)' c. Inspection lot identification code JJ d. Manufacturer's id~ntification (~.) e. Manufacturer's designating symbol (CEBS) f. Country of origin (U .S.A.) 3.6 Workmanship," These microcircuits are manufactureQ, processed, and tested in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices, workmanship instructions. inspection and test pr,Qcedures, and training, prepared in fulfillment of Burr-Brow,n's'product a.ssuraoce program. 3.6.1 Rework ~rovisions. Rework provisions, includingrebonding for the / MIL Hi-Rei. product designation, are in accordance with MIL-M-38510. 3.7 Traceability. Traceability, for / MIL, is in accordance with MIL-M-3851O. Each microcircuit is traceable to the production lot and to thecomponent vendor's component lot. Reworked or repaired microcircuits maintain traceability. 3:8 Product and ~rocess change. Burr-Brown will not implement any major change to the design. materials,. construction, configuration, or manufacturing process which may affect the performance, quality. reliability or interchangeability of the microcircuit without full or partial requalification. 3.9 Screening. Screening. for / MIL and /883B Hi-Rei product designations. is in accordance with MIL-STD-883 • . method 5008. hybrid class. except as modified in paragraph 4.3 he~ein. . Screening for the standard model, incJ,uQes Burr-Browl) QC4118 internal visual ins,pectipn and stabilization bake. fine leak. gross leak. burn-in (72 hours performed preseal).constant acceleration (condition A), and external visual inspection per MIL-STD-883. method 5008. hybrid class. For the / MIL Hi-ReJ product designation. all microcircuits will have passed the screening requirements prior to qualification or quality conformance inspection. 3.10 Qualification. Qualification is not required. See paragraph 4.2 herein. 3.11 Quality conformance ins~ection. Quality conformance inspection. for'the! MIL Hi-ReJ product designation. is in accordllnce with MIL-M-38510. except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed quality conformance inspection prior to microcircuit delivery. J:1 A 4-digit date code. indicating ye-.!.r and w~k of seal; is marked on 81BB and (no,ne) Hi::Rel product designations. 7-12 ADC87j MIL SERIES T ABLE I. Electrical Performance Characteristics. (TA = -55°C to +125°C, Supply Voltages ±15VDC and +SVDC, unless otherwise specified.) liN ITS 'n.. ~_ CONDITIONS CHARACTERISTICS MIN 12 RESOlUTION ANALOG INPUTS Input Voltage Ranges: Unipolar Bipolar oto +10V. ±5V ±10V Input Bias Current Offset Voltage Settling Time I I MAX Oto +5. Oto+l0 ±2.5. ±5. ±10 2.5 5 10 ±0.01 50 100 2 2 Direct Input Impedance: 0 to +SV, ±2.SV Buffer Amplifier: Gain Accuracy Input Impedance ADC87 TYP TA = +25'C TA = +25°C TA = +25°C 20V step to ±0.01% FSR MIN I I ADC87U/883B ADC87U TYP I I MAX UNITS Bits V V kll kll kll % Mil nA mV ,.sec 5 DIGiTAL INPUTS Start Convert Command: 11 nsec TTL loadY TTL Load V V 50 Positive Pulse Width Logic Loading 1 1 Short Cycle Logic Loading Logic Levels: Logic "1" Logic "0" (All Digital Inputs , 2 0.8 . DIGITAL QUTPILTS Parallel Data Coding: ~ Unipolar Ranges CSB COB. CTC Bipolar Ranges Output Drive Serial Data Coding (NRZ, ~ CSB.COB Output Drive Status Bit Coding Output Drive Internal Clock Output Drive TTL Loads 2 I Co~version Logic TTL Loads TTL Loads V V 2 2 2.4 Logic Levels: Logic "1" Logic "0" (All OutputS) 0.4 z~r~I~~~~;':~r::~~sition Errorl Full Scale Absolute Accuracy Bipolar §J TTL Loads 2 Error,~ GainError~ Zero Error. Unipolar jJ +25°C -25°C to +85°C -55°C to +125°C +25°C -25°C to +85°C -55°C to +125°C +25°C DriftZ/ +25°C +0.05 ±D.02 ±D.05 ±0.05 ±0.05 ±O.l ±0.02 ±0.05 ±0.1 ±0.1 ±0.05 ±0.2 +10 ..!1§' +0.10 +0.15 ±0.15 ±0.1 ±0.2 ±0.2 ±0.2 +0.3 ±1/2 ±0.05 ±D.l ±0.1 +0.05 -25°C to +85°C -55°C to +125°C Full Scale Absolute Accuracy Error, ~ Unipolar Linearity error +25°C -25°C to +85°C -55°C to +125°C +25"(; -25°C to +85°C -55°C to +125°C Ill' ±1/2 ±1/4 +25.o C -25°C to +85°C -55°C to +125°C Monotonicity Zero Adjustment Range Gain Adjustment Range ±O.15 ±0.3 ±0.15 ±0.25 ±0.6 ±0.1 ±15 +0.2 ±0.3 ±0.6 ±0.25 ±0.4 ±0.9 ±1 ±2 ±1 ±4 ±1/2 ±1 ±3 ±1 +2 Drift No Missing.GOdeS ±0.1 ±0.2 ±1/2 ±1/2 Drift Inherent Quantization Uncertainty Differential Linearity Error ±0.05 ±10 +0.10 ±0.15 ±0.07 -55 -55 0.3 0.5 +125 +125 0.4 0.55 1.5 ;:~ -25 -25 +85 +85 '%:~~l %FSR %FSR %FSR %FSR % Dpml"C %FSR %FSR %FSR %FSR %FSR %FSR L~~! LSB ppm of FSR/oC LSB LSB LSB LSB ppm of FSR/oC :~ %FSR %FSR DYNAMIC ~~~r~ea7~1~~~~~e~uency '# • ADC87/MIL are available second quarter 1982. 7-13 8 f.tsec MHz ADC87jM[L SER[ES TA TABLE I. E[ectrica[ Performance Characteristics (cont). =-55°C to 1-125°C. SupplY Voltages -I::15VDC and ...-5VDC. unless otherwise specIfied LIMITS CHARACTERISTICS REFERENCE Internal Reference: Voltage Drift External Current CONDITIONS MIN ADC87/MIL ADC87/883B ADC87 TYP I· 6.0 I +6.3 ±14.5 +4.75 Quiescent THERMAL CHARACTERISTICS Operating Temperature Range Storage Temperature Range Thermal Impedance: Case to Ambient, IieA Junction to Case, 8JC Ambient Ambient MIN _l ADC87U/883B ADC87U TYP MAX ±15 +5 35 35 40 1300 ±a.002 ±o.o02 ±O.OOI ppm/OC ~A ±15.5 +5.25 45 45 50 1500 -55 -65 UNITS V 6.6 ±5 200 -55°C to +1 25°C POWER SUPPLY Power Su pply Range: ±15V Supply +5V Supply Quiescent Current: +15V -15V +5V Power Consumption Power Supply Rejection: +15VDC -15VDC +5VDC MAX +125 +150 V V mA mA mA mW % FSRI%Vcc % FSRI%Vcc % FSRI%Vcc -55 -65 +125 +150 20 5 ·Specifications the same as ADCS7!MIL. ··Transfer and dynamic characteristics are specified without the optional buffer amplifiers. NOTES: jJ Trailing edge (logic 1 to logic 0) initiates conversion . .JJ A·TTL Load is defined as 40~A max at V,N = 2.4VDC (logic 11, and -1.SmA max at V,N = 0.4VDC Ilogic 01. .§j CSB= Complementary Straight Binary; COB = Complementary Ollset Binary; CTC = Complementary Two's Complement. Serial and parallel output data is in Nonreturn to Zero (NRZ) format. See Output Coding and Timing Diagram. ~ Externally adjustable to zero. This specification is without external adjustment. .§J FSR = Full Scale Range. The ±10V analog input range is a 20V FSR. The ±5V or 0 to 10V input range 15 a 10V FSR . .§J Applies to +Full Scale and to -Full Scale. Y Gain drift is defined as the absolute value of the change from +25°C to the hot temperature, plus the absolute value of the change from +25°C to the cold temperature, and that quantity divided by the temperature span. This is a 3-point drift. The hot temperature change is usually greater than the cold temperature change. ~ ±1 LSB = ±0.024% FSR. .!l/ Conversion time is defined as the width of the status pulse. It is specified using the internal clock, with Clock Rate, pin 17, connected toOVDC and Short Cycle, pin 14, connected to logic 1. TABLE [I. Electrica[ Test Requirements. (The individual tests within the subgroups appear in Table III1 ~ ADC87/MIL ADC87/883B ADC87 ADCB7U/883B ADCB7U Subgroups (see Table IIII MIL-STD-B83 TEST REQUIREMENTS (HYBRID CLASS) Interim electrical parameters ( preburri~iOl (method 5008) Final electrical test parameters (method 5008) Group A test requirements (method 5008 ) Group C end pOint electrical parameters (method 5008) Additional electrical subgroups performed prior to Group C inspections ·PDA applies to subgroup 1 Isee4.3.dl 7-14 1 1 1 1·,2,3,4,7 1,2,3,4,7 I, 2U, 3U, 4, 7 -- 1,2,3,4,7 -- .Table IV delta limits and limits -- -- 5,6 -- -- °C °C °C/W °C ADC87jMIL SERIES TABLE III. Group A Inspection. LIMITS ADC87/MIL ADC87/883B ADC87 ""Dt>Dn".. CONDITIONS J/ PARAMETERS 1 IZera error, bipolar 11 TA = +25°C ,Full scale error, -FS bipolar EJ I Full scale error, +.FS bipolar 11 i Gain error lJ ,~i~~arit~. error Differential linearity error ~ No missing codes Internal reference voltage ,Zero erro" unipolar ~ error, unipolar 11 i Full ! Gain error, unipolar 1/ .Zero error, bipolar 2 TA=+125°C Full scale error, -FS bipolar 1/ Full scale error, +FS bipolar 11 'Gain drift ±10V ±10V ±lOV ±10V range range range MAX MIN ±10 ±20 ±20 ±20 range ±1/2 ±1/2 oto +10V range JJ o to +10V range JJ oto +10V range -HI.O +5 ±10V range JJ ±10V range JJ ±10V range JJ See subgroup 3 UNITS ±14 ±30 ±30 ±20 mV mV mV mV LSB LSB Pass/fail V mV mV mV ±1/2 ±1/2 +6.6 +15 ±20 ±10 +6.0 +5 +6.6 +15 ±20 ±10 ±20 ±40 ±40 mV mV mV ±1 ±1 LSB LSB Pass/fail Pass y Full scale error, +FS bipolar 1/ Gain drift ±10V range JJ ±10V range JJ ±10V range..¥ See subgroup 3U Linearity error Differential linearity error No m~in~codes 3 TA = -55°C MAX Pass Pass Linearity error Differential Li nesrity error No missing codes Zero error, bipolar jj 2U TA = +85°C full scale error, -FS bipolar MIN JJ y JJ ADC87U/883B ADC87U Zero error, bipolar 11 Full scale error, -FS bipolar :y Full scale error, +FS bipolar 11 Gain drift Linearity error Differential linearity error No missing codes 3U Zero error, bipolar 11 TA = -25°C Full scale error, -FS bipolar .11 Full scale error, +FS bipolar 1/ Gain drift ±30 ±50 ±50 mV mV mV ±1 ±1 LSB LSB Passlfail Pass ±10V range ±10V range ±10V range JJ g; JJ mV mV mV mV LSB LSB Pass/fail ±20 ±40 ±40 ±54 ±1 ±1 .§! Pass ±10V range ±10V range ±10V range g; y JJ §I linearity error Differential linearity error No missing codes ±30 ±50 ±50 ±33 ±1 ±1 mV mV mV mV LSB LSB Pass/fail Pass 4 TA=+25°C Conversion time B 8 ~sec 5 TA = +125°C Conversion time 8 8 ,usee 8 8 ,usec 45 45 50 1500 45 45 50 1500 mA mA mA mW mV mV 6 TA = -55°C Conversion time 7 Quiesdmt current TA = +25°C +Vee -Vee Voo Power consumption Zero adjustment range Gain adjustment range MSB inverted output Serial output No load, all bits logic 1 Quiescent ±10V range ±10V range ±60 ±100 ±60 ±100 Pass Pass Pass Pass Pass/fail Pass/fail NOTES: JJ ±Vcc = 15VOC, Voo = 5VDC, no load, without the optional buffer amplifier, unless otherwise specified. The internal clock is used. Clock Rate, pin 17, is connected to OVDC. Short Cycle, pin 14, is connected to logic 1, .EI Without external adjustment. ~ For the ±10V range: bipolar +FS is ideally at +9.9951 17VDC; bipolar zero is ideally at O.OOOVDC; bipolar -FS is ideally at -10,OOOVDC, For the 0 to +10V range: unipolar +FS is ideally at +9.997559VDC; unipolar zero is ideally at O.OOOVDC. Refer to Figure 3 and Table VI. ~ Monotonicity is assured by differential linearity ::5±1 LSB. .§J The absolute value of the gain change from +25°C to +125°C. is added to the absolute valueofthe gain change from +25 0 C to -55°C. This provides a 3-point drift. 2J The absolute value of the gain change from +25°C to +85°C, is added to the absolute value of the gain change from +25°C to -55°C. This provides a 3-point drift. 7-15 ADC87/MIL SERIES TABLE IV. Group C, End Point Electrical Parameters. ITA = +25°C. ±Vcc = 15VOC. Voo = +5VOC, TEST LIMIT DELTA Zero error, bipolar 20mV 10mV +FLiIl scale error, bipolar 30mV 10",V -Full scale error, bipolar 30mV 10mV Gain error, bipolar 30mV 10mV Linearity lLSB 112LSB Differential linearity lLSB 1/2LSB TABLE V. Analog Input Range Selection Connections. DIRECT INPUT Input Signal BUFFERED INPUT 10 Pin Input Impedance ±2.5V 24 2.5kll 30 to 26 29 open 23 to 22 ±5V 24 5kll 30 to 26 29 open 23 to 22 Input Range Input Signal Required £Xtemal Pin Connections to Pin Inpul Impedance 30 50Mll 29 to 24 23 to 22 30 50Mll 29 to 24 23 to 22 30 50MI! 29 to 25 23 to 22 30 50MI! 29 to 24 23 to 26 30 50Mll 29 to 24 23 to 26 22 to 25 ±10V 25 10kll 30 to 26 29 open 23 to 22 o to+5V 24 2.5kl! 30 to 26 29 open 23 to 26 0'10 +10V 24 5kll 30 to 26 29 open 23 to 26 22 to 25 Required External Pin Connections TABLE VI. Ideal Analog Input Voltage vs Digital Output Code. DIGITAL OUTPUT CODE LSB MSB Inpul Range ±2.5V MSB LSB MSB LSB 111111111111 011111111111 0000 0000 0000 lLSB -2.500V OV +2.496779V 1.2207mV ±5V -5.000V OV +4.997559V 2.4414mV ±10V -10.000V OV +9.995117V 4.9626mV o to +5V OV +2.500V +4.998779V 1.2207mV o to +10V OV +5.000V +9.997559V 2.4414mV 'NOTE: Analog voltages are the center of the bit range. Transitions occur 1/2LSB before and 1/2LSB after the bit center. 7-16 22 to 25 22 to 25 ADC87/MIL SERIES 4. PRODUCT ASSURANCE PROVISIONS 4.1 SamRling and insRection. Sampling and inspection procedures are in accordance with M IL-M-38510 and M ILSTD-883, method 5008, except as modified herein. 4.2 9ualification. Qualification is not required unless specified by contract or purchase order. When so required, qualification will be in accordance with the inspection routine of M I L-M-3851 0, paragraph 4.4.2.1 The inspections to be performed are those specified herein for groups A, B, C, and D inspections (see paragraphs 4.4. I , 4.4.2, 4.4.3, and 4.4.4). Burr-Brown has performed and successfully completed qualification inspection as described above. The qualification report is available from Burr-Brown. 4.3 Screening. Screening, for /MIL and /883B Hi-Rei product designations, is in accordance with MIL-STD-883, method 5008, hybrid class, and is conducted on all devices. The following additional criteria apply: a. Constant acceleration test (MIL-STD-883, method 2001) is test condition A, Y, axis only. b. Interim and final electrical test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is optional at the discretion of the manufact urer. c. Burn-in test (MIL-STD-883, method 1015) conditions: (I) Test condition B (2) Test circuit is Figure 5 herein (3) TA = 125°C minimum (4) Test duration is 160 hours minimum d. Percent defective allowable (PDA). The PDA, for the! MIL Hi-Rei product designation only, is 10 percent and includes both parametric and catastrophic failures. It is based on failures from group A, subgroup I test after cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from preburn-in screening may be excluded from the PDA. If interim electrical parameter tests prior to burn-in are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based on the PDA. e. External visual inspection need not include measurement of case and lead dimensions. +15VDC +5VDC FIGURE 5. Test Circuit, Burn-in and Operating Life Test. 4 . 4 9ualit)i conformance ins!,ection. Groups A and B inspections of M I L-STD-883. method 5008, are performed on each inspection lot. Group D, subgroup I, seal test, ofMIL-STD-883, method 5008, is performed on each lot of packages procured. Groups C and D inspections (except for subgroup I, seal test) of M IL-STD-883, method 5008, are not required unless specified by contract or purchase order. Burr-Brown periodicaly performs groups C and D inspections of M I L-STD-883, method 5008. A report of the most recent groups C and D inspections is available from Burr-Brown. 7-17 ADC87/MIL SERIES 4.4. I Grou~ A ins~ection. Group A inspection consists of the test subgroups and LTPD values shown in M I L-STD-883, method 5008, Table I, and as follows: a. Tests are specified in Table II herein. b. Tests previously performed as part of final electrical test need not be repeated. 4.4.2 Grou~ B inspection. Group B inspectionconsists of the test subgroups and LTPD values shown in M I L-STD-883, method 5008, Table II, and as follows: . a. Particle impact noise detection test is not required. 4.4.3 Grou~ C inspection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table III, and as follows: a. Operating life test (MIL-STD-883, method 1005) conditions: (I) Test condition B (2) Test circuit is Figure 5 herein (3) T A = 125°C minimum (4) Test duration is 1000 hours minimum b. End point electrical parameters are specified in Table II herein. c. Additional electrical subgroups are specified in Table II herein. 4.4.4 Group D inspection. Group D inspection consists ofthe test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table IV, and as follows: a. Particle impact noise detection test is not required. 4.5 Methods of examination and test. Methods of examination and test are specified inthe appropriate tables. Electrical test circuits are as prescribed herein or in the referenced test methods of M I L-STD-883. 4.5.1 Voltage and current. All voltage values given are referenced to the external zero reference level of the supply voltage. Currents given are conventional current and positive when flowing into the referenced terminal. 4.6 Ins~ection of p..!!paration for deliver~ Inspection of preparation for delivery is in accordance with M I L-M-38510, except that the rough handling test does not apply. 5. PREPARATION FOR DELIVERY 5.1 Preservation-~ackag!!!g and packing. Microcircuits are prepared for delivery in accordance with MIL-M-3851O. 6. NOTES 6.1 Notes. The notes specified in MIL-M-38510 are applicable to this specification. 6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of screened parts is desirable. 6.3 Ordering data. The contract or order should specify the following: a. Complete part number (see paragraph 1.2). b. Requirements for certificate of compliance, if desired. 6.4 Definitions. Full Scale Absolute Accurac)/ Error. Full scale absolute accuracy error is the difference between the ideal and the actual, unadjusted, analog input voltage at the full scale points. I t applies to unipolar plus full scale, bipolar minus full scale, and bipolar plus full scale. Absolute accuracy includes zero, gain, linearity, and noise errors and, when specified over temperature, includes the drifts of these errors. It is measured at the first or last transition, as appropriate. T!le error is expressed in LSBs or % of FSR. !!!polar Zero Error. Bipolar zero error is the difference between the ideal and the actual analog input voltage for the digital output code 0 III IIII 1111. It is measured at the 100000000000 to 0 III 1111 1111 transition which ideally occurs at OVDC -1/2LSB. Bipolar zero error is also known as bipolar major transition error. Unil'olar Zero Error. Unipolar zero error is the difference between the ideal and the actual analog input voltage for the digital output code IIII1111 I1I1 (unipolar). It is measured at the 111I 11I1 1II1 to 1II1 II1I 1110 transition which ideally occurs at OVDC + Ij2LSB. Gain Error. Gain error is the difference between the ideal and the actual analog input voltage span. It applies to both unipolar and bipolar input ranges. It is measured between the first transition and the last transition which is ideally FSR -2LSB. Gain error in some literature describes what is defined herein to be unipolar full scale error and bipolar plus full scale error. 7-18 ADC87/MIL SERIES Offset Error. This term is not used with the ADC87. Offset error in some literature describes what is defined herein to be unipolar zero error and/ or bipolar minus full scale error. Linearity Error. Linearity error is the difference between the ideal and the actual bit transition when zero error and gain error equal zero. Differential Linearity Error. Differential linearity error is the difference between the ideal and the actual bit step width. Zero differential linearity error means each bit step width is I LS B. A maximum differential linearity error of ± 1/2LSB means a bit step width may be between 1/2LSB and 3/2LSB. Monotonicity. Monotonicity is the condition where the digital output code remains the same or increases for an increasing analog input signal. Quantization Uncertainty...: Quantization uncertainty is the inherent uncertainty of being able to determine the analog voltage which produces a digital code. Because the analog input voltage is divided or quantized into a finite number of bits, each digital code represents an analog voltage span equal to I LSB. Quantization uncertainty is ±1/2LSB. Its magnitude may be reduced only by using a higher resolution converter. 6.5 Microcircuit group assignment. These microcircuits are Technology Group F as defined in MIL-M-38510, Appendix E. 6.6 Electrostatic sensitivity...: These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive precautions should be observed at all times. 7. APPLICATIONS INFORMATION 7.1 h:!yout. To produce clean, noise-free, accurate conversions, high freq uency layout techniques should be used. Wide, low inductance conductor patterns, short and direct external component leads, power supply decoupling, and a ground plane are recommended. Long runs should be avoided. Coupling and runs. which might cause input-to-output coupling. should be avoided. High impedance points should be given special consideration. The input to the buffer. the comparator input (particularly sensitive) and the external adjustment pins are sensitive. Shielding by Analog Common or ±15VDC supply patterns my be helpful. 7.2 Grounding. A ground plane under the ADC87 is recommended. Analog Common (pin 26) and Digital Common (pin 15) must be connected together and to the analog system ground. Preferably, connect both commons directly to the ground plane under the ADC87. If these commons must be run separately, use wide conductor patterns and connect a O.OIILF ceramic capacitor between the commons at the unit. The case is connected to Digital Common, pin 15. 7.3 Power SuPpJy Decoullling. For optimum performance and noise rejection, each power supply should be decoupled by connecting a IILF tantalum capacitor and a 0.0 IILF ceramic capacitor from each power supply to the ground plane. Locate the capacitors close to the converter. 7.4 Qlltional External Zero and Gain Adjustments. The ADC87 zero error and gain error are factory laser-trimmed to position the staircase transfer function within Table I specifications. Optionally. two adjustments null zero error and gain error (see Figure 6). Zero adjustment moves the entire staircase left-to-right. For unipolar ranges, -FS, OV DC, is nulled. For bipolar ranges. midscale, OVDC, is nulled. (Alternately, bipolar -FS may be nulled.) Gain adjustment adjusts the span of the staircase. Adjustment effectively rotates the staircase about -FS. For unipolar and bipolar ranges, zero adjustment should be made first. then +FS error is nulled. Adjustments should be made after a 10 minute warm-up. Fixed. selected resistors may be substituted for the potentiometers after the adjustments have been determined, if desired. If adjustments are not used. pin 22 (zero adjust) should only be connected as required for analog input range selection and pin 27 (gain adjust) should be either grounded (recommended) or open. 7.4.1 Zero Adjustment Procedure. For the selected unipolar range, apply the analog input voltage at which the IIII 1111 IIII toTIiT IIII 1110 transition ideally occurs, OVDC +1/2LSB. While continuously converting. adjust the zero potentiometer until the transition "flickers". For the selected bipolar range, apply the analog input voltage at which the 100000000000 to 0111 1111 IIII transition ideally occurs. OVDC -1/2LSB. While continuously converting, adjust the zero potentiometer until the transition "flickers". 7.4.2 Gain Adjustment Procedure. Make zero adjustment first. For all input ranges. apply the analog input voltage at which the 0000 0000 0001 to 0000 0000 0000 transition ideally occurs, +FS -3/2LSB. While continuously converting. adjust the gain potentiometer until the transition "flickers". For bipolar ranges. repeat zero and gain adjustments as they are interactive. 7-19 ADC87/MIL SERIES JiY Pin 22 l.81!lll +15VIIC +15VDC +15VDC ~ IDknto l00kn y JJY jj Pin 22 122kll ·15VIIC ·I&VDC f II.D~ jj IDknto Y Pin 27 10000n II.II~ Ji 16.8kll Pin 26 Pin 26 -= PinYY 27 J8Dkn 18Dkn _--.,w-.-J.N..-. ..... JIIICIllo JOOtn IIIMn .J5VDC Adlustment Ringe =11.4% FBR (±O.2% FSRI tll ,+15VDC JiY 27Dkn 2711kn, ~ " IlIklllo JOOtn .15VIIC Adjuslmenl Ringe =11.55% FSR (±O.27% FSRI (bl Gain Adlustment (II Zero Adlustmenl Mlllal! 1/ LICIIIII Gioll 0 pllllible to Ihl aanYIIIII"to mInImize nelll pickup. 1/ 5% arban CGllpOllllon or bla,r. 11 U.I mullllUrn pallnJlomllll'l wllllll1lJppm/"C TCR or Ie. 10 minimize drift wAh IImpll1lUra. ~ An .aentullor nllWork lilY bllUbiUlUted 1.. lhe IIrlo reelllDr lor lowlr Impedancelnd I_r nollllusCljl\lbltRy. FIGURE 6. Optional External Zero and Gain Adjustment Circuits. 7.5 Start Convert and Status. To start a conversion, a positive pulse with a minimum pulse width of 50nsec must be applied to the Start Convert terminal, pin 21. The trailing edge (falling edge) resets the converter, starts the.internal clock and initiates a'conversion. The start convert input must remain logic 0 during conversion, as the internal clock is stopped by logic I and the output will be erroneous. Another start convert pulse during a conversion does not reset and restart a conversion; it may momentarily stop the internal clock and produce an erroneous output. Status output, pin 20, is logic I during conversion. When a conversion is complete, Status drops to logic 0 and the internal clock is turned off. Refer to the timing diagram, Figure 4. 7.6 Continuous Conversion. The ADC87 will continuously convert, commencing a new conversion rrnmediatelY after the last conversion, when wired to accept an externa'l clock. See paragraph 7.8 and Timing Considerations, paragraph 3.3.4. Alternately, the internal clock may be used with a new start convert common every 8.7j.tsec or slower. 7.7 Internal Clock and Clock Rate. The ADC87 is specified and tested using the internal clock. The internal clock is factory adjusted to 1.6M Hz with Clock Rate, pin 17, connected to OVDC (Digital Common). Under 'these conditions, the ADC87 will meet all the conversion speed and accuracy specifications. The internal clock frequency may be increased or decreased by applying a positive or negative voltage to Clock Rate, pin 17 (see Figure 7). The circuits shown in Figure 8 may be used. Increasing the clock frequency decreases the conversion time; however, linearity errors increase as shown in Figures 9 and 10. Decreasing the clock frequency is accomplished by using a negative voltage or using an external clock (see paragraph 7.8). 15 ~ ............ ~~ 12·81T HUIT II ·5 II +5 +JII +15 Conlrol Vollage(VDCI FIGURE 7. Clock Rate Control Voltage. 7-20 ADC87/MIL SERIES +6VDC1/ +15VDC -)~ 1 -)~ ! Pln17Y Plnl7Jj = (II Fine Adlullmenl Rangl (bl Coarsa Adlullment Ringe Notal: 1/ USI neOIUvIsupply to dacrealllhe clock Irequlncy. y Pin 17 II not CGoolCled 10 OVDC whln ullng clock rill Idlullmenl potentiometer. :# MultllUrn potentiometer with IOOppm/oC TCR or 1118. FIGURE 8. Clock Rate Adjustment, Optional. 0.150 0.150 = 0.125 t! 0.125 iE. O. I 10-lliT \ \ \ ~l!; 0.075 ! :::; 0.05 0.025 o \, - ~ JBIT I' 0.075 i! 0.05 i ,0.D25 ::::; IO-BIT LIMIT ~ .......... -' 12·BIT LIMIT -- 12-BIT \\ \\ 'I; 10-BIT LIMIT \ \.. o 10 2 I 100BI1 D.I 2 -~ - 12-BIT LIMIT --- 10 4 Conversion Tlm'(~lIcl Convlrslon Time I~sacl FIGURE 9. Linearity vs Conversion Time. FIGURE 10. Differential Linearity vs Conversion Time. 7.8 External Clock. An external clock may be used with the ADC87 for synchronization or special timing applications. The external clock frequency must be lower than the internal clock frequency. However, the internal clock frequency may be increased; see paragraph 7.7. The external clock is connected to the Start ConVert terminal, pin 21. The normal, start convert positive pulse signal is not required. The external clock must be an~gative-going pulse, 100nsec to 200nsec wide, at a frequency lower than the internal clock. The falling edge (leading edge) of the external clock starts the internal clock. The internal clock completes one cycle, then ceases as the Start Convert terminal. pin 21. is logic I at that time. The next external clock falling edge turns on the internal clock again, for one cycle. The Clock Output signal, pin 19, displays the internal clock synchronized to the lower, external clock frequency. A conversion is complete and Status output drops to 10gicO after 13 clock pulses. The converter will provide continuous conversions as long as the external clock signal is present. A conversion is complete when Status output drops to 10gicO. Status remains 10gicO for one external clock period. The next conversion starts on the next falling edge of the external clock following conversion completion. Conversions cease when Start Convert input is logic I. A circuit to generate an external clock signal from a clock with an arbitrary duty cycle is shown in Figure II. A circuit to generate an external clock signal from a convert command is shown in Figure 12. 7-21 ADC87/ MIL SERIES +5VDC &.Bkn +5VDC 5.6kn I I ADC87 START !-i------<- CONVERT, Pin 21 :4 I I I ij :4 I I ADC87 START CONVERT, Pin 21 EXTERNAL CLOCK -- -' 3 CONVERT COMMAND +5VDC EXTERNAL CLOCK AOC87 '--_ _ _ _ _ STATUS, Pin 20 ~ EXTERNAL CLOCK OICI ITO PIN 21) ~ _ STATUS END OF PREVIOUS QICI----'r---u---, ITO PIN 211 150nllc TYPICAL . CONVERS~~ OF NEXT CONVERSION. - I t-- 150nuc TYPICAL NOIe: . Tha aXlllrnal clock lrequency mull b.low.r IlIln ilia Internll cloct lrequancy: Extarnal clock can hlVa any dllirid duty eycle. STATUS _ _--' Nota: Sllrt Converllnd the axlernal clock mUlt be high simultaneously to Inltlll8l convaralon. The conversion will start on the rising adge ollba axlamal clock. Any convart commands that occur during I conversion will bl Ignored. FIGURE 12. Conversion Initiated by Convert Command Using Continuous External Clock. FIGURE II. Continuous Conversion Using External Clock with Arbitrary Duty Cycle. 7.9 Short Cycle. The ADC87 conversion cycle may be stopped prior to converting all 12 bits. This provides faster conversions tOTess resolution. For conversions to n bits. connect the n + I bit output to Short Cycle. pin 14. The remaining bits are truncated. Figure 13 shows a complete cycle and a short cycle to 10 bits. For 10 bits the internal clock frequency has been increased to provide the minimum conversion time. See Clock Rate. paragraph 7.7. RllOlulion (bltal Clock Rltl connect pin 17 t1l pin Short Cycle COMact pin 14 to pin Canvlrslon SPIed iliac. mix 12 15 16 8 10 16 2 5 FIGURE 13. Short Cycle Connections. 7-22 BURR-BROWN@ IElElI DAC87/MIL SERIES MODEL NUMBERS: DAC87-CBI-V/MIL DAC87U-CBI-V/B DAC87-CBI-V/B DAC87U-CBI-V DAC87-CBI-V JJ REVISION B OCTOBER, 1981 12-Bit -55°C to +125°C Military DIGITAL-TO-ANALOG CONVERTER FEATURES • HI·REL MANUFACTURE • COMPLETELY SPECIFIED, -55"C to +125°C • ACCURATE ±1I2LSB mIX Linearity, over temperature ±2Oppm/oCmax Gain Drift ±O.2% Total Error, over temperature Monotonic, over tempentun • OPTIONAL MIL·STD-883 SCREENING • DAC85 PIN·COMPATIBLE • COMPLETE· INTERNAL REFERENCE AND OUTPUT AMPLIFIER DESCRIPTION The DAC87/ MIL Series is a high performance. 12· bit. TTL·compatible. -55"C to + 125"C digital-toanalog converter in a metal. welded. hermetically sealed package. and it is manufactured on a separate hi-reI production line. It is pin-compatible with DAC85 converters and has five user-selected output ranges. Each DAC is a complete device with an internal output amplifier and an ultra-stable reference. The DAC87/ MIL Series is designed for high accuracy. wide temperature applications. The total accuracy without external trim adjustments is ±O.I% of FSR. decreasing to only ±0.3% of FSR over -55"C to +125"C. With external offset and gain trim adjust· ments at +25"C. the total accuracy is less than ±0.2% of FSR over -55"C to + 125"C. Gain drift is less than 20ppmj"C. Linearity error. contributed mostly by the internal current switches and resistive ladder. is reduced by laser trimming to less than ±1/2LSB over temperature. Differential linearity is less than ± I LSB over temperature thereby guaranteeing monotonicity from -55°C to + 125°C. There are two electrical performance grades and three product assurance levels allowing a wide application/ budget choice. The DAC87-CBI-V model/ grade features excellent performance from -55"C to +125"C and finds wide military. aerospace. and industrial applications. The DAC87U-CBI-V model/ grade features excellent performance from -25"C to +85"C. and guarantees specifications from -55"C to + I25"C. Applications include test equipment. shipboard. ground support. and shirt-sleeve environments where operation is between -25"C and +85"C but full temperature operation must be assured. The three product assurance levels available are: standard; / B (100% screened per MIL·STD-883 method 5008. hybrid class. class B); and / MIL (100% screened. plus PDA = 10%. plus Groups A and B testing on each inspection lot. plus Groups C and D performed initially. periodically. and when specified on the customer's' purchase order). See paragraph 1.2.2 for more details. Each device is manufactured in a hi·rel environment with clean room conditions which assures "built-in" quality . .ll Current output models are also available. Contact Burr-Brown. Inlernatlonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746-1111 . Twx: 910-952·1111 . Cable: BBRCORp· Telex: 66-6491 PDS-4S2 7-23 DAC871 MIL SERIES DETAILED SPECIFICATION MICROCIRCUITS, LINEAR DIGITAL-TO-ANALOG CONVERTER HYBRID, SILICON I. SCOPE 1.1 Scope. This specification covers the detail requirements for a 12-bit. TTL-compatible. integrated circuit. digital-toanalog converter. 1.2 Part Number. The complete part number is as shown below. T..l Basic model number v CBI DAC87 T ~ T Hi-ReI product designator (see 1.2.2) 1.2.1 Device type. The device is a single. 12-bit. digital-to-analog converter. The input coding is complementary binary. Thedevice may be externally pin-connected for either Complementary Straight Binary (CSB) or Complementary Offset Binary (COB) coding (see Tables V and VI). Grade (see 1.2.1) Input coding (Complementary Binary) IMIL Voltage output .Jj There are two electrical performance grades. The premium grade has no grade designation in the part number and features specifications and tests from -5S"C to + 12S"C'., The U grade has a U grade designation in the part number and features specifications arid tests from -2S"C'to +85"C, and specifications from -SS"C to + 12S"C, Electrical specifications are shown in Table I; electrical tests are shown in Tables II and III. 1.2.2 Device class. The device class is similar to the hybrid class (class B) product assurance level. as defined in MIL-M-38SlO. The Hi-Rei product designator portion of the part number distinguishes the product assurance levels as follows: Hi-Rei Product Requirements Designator IMIL IB (none) Standard model. plus 100% MIL-STD-883 hybrid class screening. with 10% PDA. plus quality conformance inspection (QCI) consisting of Groups A and B on each inspection lot. plus Groups C and p performed initially and periodically thereafter. Additional electrical testing is performed on I MIL models. Standard model. plus 100% MIL-STD-883 hybrid class screening. Standard model including 100% electrical testing. 1.2.3 Case outline. The case outline is as defined in Figure I. The case is metal and is conductive. 1.2.4 Absolute maximum ratings. Supply voltage. Vee Supply voltage. VIlIl Data input voltage, Output short circuit duration Storage temperature range Lead temperature (soldering. 6Osec) Junction temperature JJ .lJ ±18VDC OVDC to + 18VDC -I VDC to +7VDC Unlimited 11 _65°C to +ISO°C +300°C TJ =,17S"C Current output models are also available. Contact Burr-Brown. Short circuit may be to ground only. Rating ,applies to I case temperature or 65"C ambient temperature. ,soC 7-24 DAC87, MIL SERIES 1.2.5 Recommended operating conditions. Vee: ±14.5VDC to ±15.5VDC VI"': +4.75VDC to+5.25VDC -55"C to + 125"C Supply voltage range Ambient temperature range 1.2.6 Power and thermal characteristics. Maximum allowable Case outline power dissipation Package Figure I 24-lead can l350mW at T" - 125"C Maximum Ii J-C Maximum Ii J-A 7"C/W JJ J7"C'W 2. APPLICABLE DOCUMENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICATION MILITARY MIL-M-3851O - Microcircuits. General Specification for. STANDARD MILITARY MIL-STD-883 - Test Methods and Procedures for Microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to assure successful compliance with this specification. 3.1.1. Detail specifications. The individual item requirements are specified herein. In the event of conflicting requirements. the order of precedence will be the purchase order. this specification. and then the reference documents. 3.1.2 Country of manufacture. These microcircuits are manufactured. assembled. and.tested within the United States of America. 3.2 Design. construction. and physical dimensions. 3.2.1 Package. metals. and other materials. The package is in accordance with paragraph 3.5.1 of M I L-M-385I 0 except organic and polymeric materials may be used for substrate and die attach. The exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in M IL-M-38510. INCHES MIN MAX MILLIMETERS '. MIN MAX A 8 1.365 1.385 34.67 35.18 .790 .810 20.07 20.57 NOTE: C .170 .250 4.32 6.35 Leads in true position within 0.010" 0 .016 .021 0.41 0.53 G .1008ASIC DIM b ~"-"'" ; ..~m 'Rat at seating 111111111111 K f -..I I.U G -L-o H 000000000000 1 12 24 13 MMC . plane. I I 2.548ASIC H ..125 .150 3.18 K 3.81 L .300 .150 .6008ASIC R .080 .110 I 1 3.81 7.62 15.24 BASIC 2.03 I 2.79 I-- L -J Pin numbers shown for reference only. Numbers may not be marked on package. R 000000000000 Weight: 15 grams max. FIGURE I. Case Outline (Double-Wide DIP Configuration). lJ Rating applies to normal device operation. For the output short circuit condition, the maximum 6J-C of the output die of IClO"e, W must be applied to the output short circuit current. 7-25 DAC87/Mll SERIES 3.2.2 Design documentation. The design documentation is in accordance with Mll-M-3851O. 3.2.3 Internal conductors and internal lead wires. The internal conductQrs and internal lead wires are in accordance with Mll-M-38510. 3.2.4 Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel underplating. The lead material and finish is in accordance with MIl-M-38510 and is solderable per MIL-STD-883, method 2003. 3.2.5 Die thickness. The die thickness is in accordance with MIl-M-38510. 3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2. 3.2.8 Glassivation. Allidice utilized are glassivated. 3.3 Electrical performance characteristics. The electrical performance characteristics are as specified in Table I and apply over the full operatmg ambient temperature range of -55"C to +125"C, unless otherwise specified. 3.3.1 Offset and gain error adjustment. The DAC is capable of being externally adjusted to zero offset error and to zero gain error using the circuits in Figure 3. See applications information, paragraph 7.3. 3.3.2 Input coding. The input coding is complementary binary. The digital input code to yield the corresponding output voltageror the output ranges is specified in Table V. 3.3.3 Output range. The output range is specified in Table VI when externally connected as shown therein. 3.4 Electrical test requirements. Electrical test requirements are specified in Table II. The subgroups of Table III and limits of Table IV which constitute the minimum electrical test requirements for screening, qualification. and quality conformance, are specified in Table II. 6.3V ,MSIIBITI REFERENCE OUTPUT BIT2 GAIN ADJUST IIT3 +VCC 11f4 COMMON 11 BIT5 SUMMING JUNCTION liT I 2DV RANGE Bin IOV RANGE OFFSET ADJUSTMENT y 2D1"-"'3.9"'M"'~""I--r,;l~:~ BAil ADJUSTMENT JJ ~~~~--~<1~~~ SUMMING JUNCnON BIT8 BIPOlAR OFFSET BITI REFERENCE INPUT BITIO OUTPUT BIT II .V ·15VDC ee iLSBIBITl2 +15VDC +15VDC ·15VOC .!J ,.;;IODppm/OC. y ±20% carban cumplllltlon or bBIIlr.LDcaII clDn to lha DAC87 VDO to PilOn! nol.1 pickup. 'AI Clramlc. .!J PIn 21 II canneclld III 1111 call. FIGURE 2. Terminal Connections. FIGURE 3. Offset and Gain Error Adjustment Circuits. 7-26 DAC87jMIL SERIES TABLE I. Electrical Performance Characteristics. LIMITS n ,,~ .D .• "TCDISTICS CONDITIONS jJ MIN 12 ""07 I J DAC87U-CBI-VlB _D!or.A7' _r.R'. "D' TYP I I MAX MIN I .TYP 1~ I I MAX UNITS 21 Bits DIGITAL INPUTS Input voltage Logic"1" ~ TA -55°C ~ TA ~+125°C 2.0 2.4 0 0 5.5 5.5 0.8 0.4 V V V V V'N ~ 2.4V V'N ~0.4V -1.6 +40 0 "A mA ~55°C ~ TA Logic"O" Input C~~;~nt Logic ''0'' Total error, untrimmed ~ Unipolar TA +25°C TA ~ +125°C ~ ~ +25°C +25°C . ±O.10 -25°C ~ TA ~ +85°C ±O.25 -55°C.;; TA .;; +125°C TA ~ +25°C Bipolar ±O.30 ±0.10 ,..25°C:S;;; TA ~ +85°C ±O.25 -55°C';; TA';; +125°C Total error. trimmed Unipolar ±O.30 ~ ~ TA ~ +25°C -25°C';; T A .;; +85°C -55°C';;TA';;+125°C TA ~ +25°C Bipolar ±O.OO6 ±O.0122 ±O.OO6 ±O.20 ±0.0122 ±O.50 ±O.15 -25°C ~ TA ~ +85°C -55°C:S;;;TA:e;;+125°C ±O.15 ±O.20 Linearity error TA ~ +25°C -25°C';; TA .;; +85°C -55°C';; TA';; +125°C ±O.25 Differential linearity error .§I TA - +25°C -25°C';; TA .;; +85°C -55°C.;; TA';; +125°C ±0.50 ,range §f Offset error Jjf Unipolar 11 Bipolar %of FSR %ofFSR %ofFSR %of FSR %ofFSR %ofFSR ::;~ ±3 LSB LSB LSB ±O.50 ±O.75 ±1.0 ±3 LSB LSB LSB ±1.0 -55 TA ~+25°C -25°C';; TA .;; +85°C -55°C.;; TA';; +125°C TA ~ +25°C 11 ±O.25 ±O.50 ±O.75 +125 -25 +85 °C ±O.02 ±O.05 ±O.02 ±O.05 ±0.068 ±O.02 ±O.OS ±O.05 ±O.02 ±O.05 ±O.10 %ofFSR %ofFSR %ofFSR %ofFSR %ofFSR %ofFSR ±1 ±3 -25°C:e;; TA:S;;; +85°C -55°C';; TA';; +125°C Offset temperature sensitivity Unipolar ±O.10 11 Bipolar -25°C to +85°C -55°C to +125°C -25°C to +85°C -55°C to +125°C Offset adjustment range ±O.15 Gain error §j.Y Unipolar .JJ TA~+25°C ±1 ±3 ±5 ±10 ±10 ±30 ±O.05 ±O.10 ±O.05 ±0.10 ±O.20 ±0.05 ±0.25 ±O.10 ±O.OS ±O.10 ±O.20 ±10 ±20 ±10 ±20 ±60 -55°C :s;;; TA:e;; +125°C Bipolar !J TA ~ +25°C -25°C:;;;;; TA :e;; +85°C -55°C';; TA';; +125°C Bipolar ppm of FSR/oC ppm of FSR/oC ppm of FSR/oC I ppm of FSR/oC %ofFSR ±O.2 -25°C:;;;;; TA ~ +85°C Gain temperature sensitivity Unipolar %ofFSR %ofFSR %ofFSR %ofFSR %ofFSR %ofFSR ±O.25 %ofFSR %ofFSR %ofFSR %ofFSR %ofFSR %ofFSR y -25°C to +85°C -55°C to +125°C -25°C to +85°C -55°C to +125°C Gain adjustment range ±10 +10 ±O.2 ±O.3 _10 20 ±20 +20 . . ppmfOC ppmfOC ~~;~~ %ofFSR DYNAMIC' Slew rate Settling time 5 3 1.5 avo - 20V to±112LSB t.Vo ~ 10V to±1/2LSB t.Vo ~ 1LSB to +112LSB VI"sec 7 6 "sec "sec "sec 3 ANALO.G OUTPUT Output voltage range Output current 1JY y Output reslsfllnce, DC Output short circuit current ±10 V mA ±5 0.05 TA ~+25°C ±5 7-27 0.2 ±40 . n mA DAC87/MIL SERIES ,TABLE I. Electrical Performance Characteristics (cont). LlM'ITS DACB7-CBI-v/MIL DACB7-CBI-v/B DACB7-CBI-V CHARACTERISTICS CONDITIONS JI MIN I TYP I DACB7U-CBI-VIB DACB7U-CBI-V MAX MIN .1 TYP .1 MAX UNITS Y INTERNAL REFERENCE Internal reference voltage (VRl Internal reference temperature sensitivity ±6.D Output current from internal reference ±6.3 ±6.B ±5 ±IO 200 ±5 -25°C to +85°C -55°C to +1 25°C for specified VR V ppm of VRfOC ppm of VR/oC ±ID ±30 "A POWER SUPPLY Pow~r supply range +Vee -Vee Voo +14,0 -14.0 +4,75 +15 -15 +5 +16.0 -IB.O +15.5 V V V ±Vee." 15V ±O.5V Voo = 5V ±0,25V ±O.002 ±O.OOI ±O,OO4 ±O.OO2 % of FSR/%Vee % of FSRI%Voo TA =+25°C -55°C';; TA';; +1 25°C ±20 ±30 ±30 25 25 rnA mA mA mA +125 +150 °C °C . P~wer supply sensitivity ±Vee Voo Power supply current (quiescent; ±Vcc TA Voo = +25°0 20 -55°CE:;;TAE;;;+125°C TEMPERATURE RANGE -55 Operating Storage -65 ·Specificatlon same as DACB7-CBI-V NOTES: jJ ±Vee = 15V, Voo =5V, -55°C';;TA';; +125°C. un I... otherwise specified. FSR = Full Scale Range (Example: TheFSR is 20Vfor ±IOV range, 10V for±5V range, and IOV forO to +IOV range,; LSB= Least Signilicant Bil. ;Y Tota! error includes all errors at any fixed power supply voltage within the r~ommended supply voltage range, including the internal reference, linearity error, offset error, and gain error. Y Offset and gain externally trimmed to zero error at TA = +25°C. ~ Monotoniclty Is assured by tasting dilferentiallinearity to ±I LSB §J Externally adjustable'to zero, Y maximum. Y The reference error is included. ~ The ollset error Is specified separately and is not included herein. The output voltage range is determined by external conditions (see Table Vii. ~ Limit is assured by testing output resistance where RLOAO = 2kn, ~ . T ABLE II. Electrical Test Requirements (The individual te.ts within the subgroups appear in Table 1111 MODELS DAC87-CBI-V/MIL MIL-STD-883 tel' requlremenll (hybrid cl...) DAC87-CBI-VIB DAC87-CBI-V DACB7U-CBI-v/B DAC87U-CBI-V :;ubgroups I see Table IIII Interim electrical parameters (preburn-in) (method 5008), Final electrical test parameters (method 50081 Group A test requirements (method 500BI Group C end !>oint electrical parameters (method 50081 Additional electrical subgroups performed prior to Group C inspections I I 1 1·,2.3,4 1,2,3 1,2U,3U 1,2,3,4 -- -- Table IV delta limits and limits -- -- 2C,3C, 5, 6 -- -- ·PDA applies to' subgroup 1 (see4.3,dl 3.5 Marking. Marking is in accordance with M IL-M-38510. The following marking is placed on each microcircuit as a minimum. a. Index point b. Part number (see paragraph 1.2) c. Inspection lot identification code .11 d. Manufacturer's identification (f.IIi") e. Manufactuer's designating symbol (CEBS) f. Country of origin (U.S.A.) 3.6 Workmanship. These microcircuits are manufactured, processed. and tested in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices. workmanship instructions. inspection and test procedures, and trainings. prepared in fulfillment of Burr-Brown's product assurance program. 3.6.1 Rework provisions. Rework provisions. including rebonding. for the J MIL Hi-.Rel product designatton are in accordance with MIL-M-38510. l' A ·4~igit date code. indicating year and week of seal. is marked on I B and (none) Hi-Rei product designatio~s. 7-28 DAC87 MIL SERIES 3.7 Traceability. Traceability is in accordance with MIL-M-38510. Each microcircuit is traceable to the production lot and to the component vendor's component lot. Reworked or repaired microcircuits maintain traceability. 3.8 Product and process change. Burr-Brown will not implement any major change to the design. materials. construction. configuratIOn, or manufactunng process which may affect the performance. quality. reliability or interchangeability of the microcircuit without full or partial requalification. 3.9 Screening. Screening, for 1M IL and I B Hi-Rei product designations. is in accordance with M I L-STD-883. method 5008. hybrid class. except as modified in paragraph 4.3 herein. Screening for the standard model, (none) Hi-Rei product designation. includes Burr-Brown QC4118 internal visual inspection and stabilization bake, fine leak, gross leak. burn-in (72 hours performed preseal). constant acceleration (condition D). and external visual inspection per MIL-STD-883. method 5008. hybrid class. For the I MIL Hi-Rei product designation. all microcircuits will have passed the screening requirements prior to qualification or quality conformance inspection. 3.10 Qualification. Qualification is not required. See paragraph 4.2 herein. 3.11 Quality conformance inspection. Quality conformance inspection. for the MIL Hi-Rei product designation. is in accordance with MIL-M-38510, except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed quality conformance inspection prior to microcircuit delivery. TABLE III. Group A Inspection. TEST 1 TA = +2SOC CONDITIONS PARAMETERS SUBGROUP OIlsei error. bipolar Gain error, bipolar Linearity error, bipolar Differential linearity error, bipolar Total error, untrimmed, bipolar Totalsrrar. trimmed. bipolar Internal reference voltage Input voltage 5 5 5 5 5 Output resistance 5 2 Logic-"I". ali inputs. Yin = 5.0VDC to 2.0VDC. measure .!.vo Logic "0". ali inputs. Yin = OVDC to O.aVDC. measure .lVo Logic "I". each input. Yin = +2.4VDC Logic "0". each input. Yin = +O.4VDC No loed +Vee No loed -Vee No loed Voo Ro 5 Total error, untrimmed. unipolar 5 Offset error. bipolar (VOE I Gain error. bipolar (GEl OIlset temperature sensitivity. Bipolar 5 5 ±10V range [ideal value = -lO.000V, ±10V range [idSal value = +9.995117VI Gain temperature sensitivity, Bipolar linearity error, bipolar 5 .lVOE ±10V range.""'IT = VOEI25 - VOE25 .lGE ±10V range, -:iT = GEI25 - GE25 l000C ±10V range. *Vo 5 +2.44 -2.44 ±3.89 ±20 mV mV mV mV +6.6 V ±4 ±4.8 mV ±4 +40 0 ±4.a +40 0 30 mV +6.6 +6.0 -1.6 30 25 25 0.2 ±5 ±4O ±5 ±2.6 ±2.0 0.2 !l ±40 mA ±2.S mV ±2.0 ±5 ±5 mV mV mV mV ±10 ±10 ±10 mV mV ±3O ±30 ±4O ±40 ±10 ?J ~A mA mA mA mA ±20 ±50 mV mV ±0.20 mV/oC ±0.4O mV/oC +2.44 ±2.44 ±4.89 ±60 mV mV mV mV Yjj For + bit errors For - bit errors Differential linearity error, bipolar Total error, untrimmed, bipolar l000C mV mV 30 30 5mA Offset adjustment range Gain adjustment range Offset error, unipolar Gain error, unipolar 4 4 -1.6 [Yo no loed) - [Vo2kllload)' Rload = Ill. Vo = +FS and -FS ±10V range. Vo = +FS • .l Vee = +O.5V and -{).5V ±10V range. Vo = +FS • .l Voo = +0.25V and -{).2SV ±10V range ±10V range oto +10V'range [ideal value = O.OOVI o to +10V range [ideal value = +9.997559VI'y oto +10V range Output short circuit current Power supply sensitivity TA=+125°C +6.0 5 5 5 5 ±10 ±20 +2.44 -2.44 ±3.66 ±20 !!I Input current Power supply current UNITS ±10V range (ideal value = -10.000V I ±10V range [ideal value = +9.995117V, ±10V range ¥ ~ For + bit errors For· bit errors ±10V range ~ ~ ±10V range jj2/ ±10V range = +1ull scale 7-29 DAC87 MIL SERIES TABLE III. Group A Inspection (cont). LIMITS SUBGROUP PARAMETERS Total error, trimmed, bipolar Internal reference voltage Internal reftlrence temperature sensitivity TA ~ Power supply current 2C +125°C TEST CIRCUIT FIGURE 5 5 .5 5 5 TA 2U +85°C ~ Offset error, bipolar (VOEI Gain error, bipolar (GEl Offset temperature sensitivity, Bipolar 5 5 .- CONDITIONS ±lOV range 11 +6.0 ~V. VR125 - VR25 3 TA ~ ·55°C .- Linearity error, bipolar 5 Differential linearity error, bipolar Total error, untrimmed, bipolar Total error. trimmed. bipolar Internal reference voltage Internal reference temperature sensitivity .. Offset error. bipolar Gain error, bipolar 5 5 5 5 5 5 No load +Vee No load -Vee No load Voo 6()OC 3U TA~·25°C Gw -'GE25 ~VGE ±10V range, -:rr --eooc ~ ±lOV range. "J/ ~ For + bit errors For - bit errors ±lOV range Y §f ±lOV range ±lOV range !/ +6.0 ~V. V.os· V.,s ±lOV range· ideal value ~ ·lO.OOOV ±10V range, ideal value ~ +9.995117V·1I Gain temperature sensitivity, Bipolar .- ±lOV range. .iGE .iT Linearity error, bipolar 5 ±lOV range 1I.Y For + bit errors For - bit errors ±lOV range .Y.§1 ±10V range ±lOV range !/ Power supply current ~ GE2S - GE-5S - VA25 - VA 55 5 ±lOV range (ideal value ±lOV range I ideal value ~ +9.995117V Offset temperature sensitivity, Bipolar .- Gain temperature sensitivity, Bipolar .- linearity error, bipolar 5 Differentiallinear;ty error, bipolar Total error, untrimmed bipolar Total error, trimmed bipolar Internal reference voltage Internal reference tem.perature sensitiv'ity 5 5 5 ±O.20 mVI"C 100.40 mV/oC +2.44 ·2.44 !4.88 "!:50 !3O +6.6 mV mV mV mV mV 'V "VI"C ±20 mV ±50 mV ±0.2O mVloC ±0.40 mVloC +2.44 ·2.44 "t4.88 :t60 ±40 +6.6 mV mV mV mV mV V ~VloC ±63 No load +Vee No load -Vee No load Voo 5 mV sooC 5 5 5 Offset error. bipolar Gain error, bipolar mV 6()OC +6.0 ~V. ±20 NO ±63 -:rr~~ ~T 3C mA mA mA ~ ±lOV range. ~ ~ V0E25 - VOE-55 sooC .iT TA~'SSOC "VI"C V0E85 - VOE25 ~ ±10V range, UNITS mV V ±10V fange I ideal value = -10.000V ±10V range I ideal value ~ +9.9951 17V , 11 -- 5 5 5 5 ±40 +6.6 30 30 25 Offset temperature sensitivity, Bipolar Differential linearity error, bipolar Total error, untrimmed bipolar Total error, trimmed bipolar Internal reference voltage Internal reference temperature sensitivity DAC87U-CBI-V/B DAC87U-CBI-V MIN MAX ±63 --~---lOO"C ~T .iT Gain temperature sensitivity, Bipolar J/ DAC87-CBi'ViMIL DAC87-CBI-VlB DAC87-CBI-V MIN MAX mA rnA mA 30 30 25 ~ -1O.000v) !"20 Y ±lOV range. o1VOE o1T ±lOV range • .iGE .iT ~ ~ V0E25: VOE-25 SOOC GE25-GE-25 mV +40 mV ±0.20 mVloC +0.40 mVloC +2.44 ·2.44 ±4.88 :!:50 ±3O +6.6 mV mV mV mV mV V ±63 ~VfOC SOOC yy ±lOV range For + bit errors For - bit errors ±lOV range §/ ±1QV range ±lOV range 1/ .y 5 +6.0 .lVR ~T = VR3.: - VA 25 sooC 7-30 DAC87 MIL SERIES TABLE III. Group A Inspection (cont). LIMITS PARAMETERS SUBGROUP ~ TA T. TEST CIRCUIT FIGURE 4 +25°C Settling time Slew rate 6 6 To ±1/2LSB. :;vo " 20V :;Vo = 20V. 10% to 90% 10 5 Settling time 6 6 To ±1/2LSB. :;Vo " 20V :;Vo = 20V. 10% to 90% 10 6 6 To.±1/2LSB. :;Vo " 20V Vo = 20V. 10% to 90% 10 = +125°C Slew rate 6 TA CONDITIONS V DAC87-CBI-VlMIL DAC87-CBI-VlB DAC87-CBI-V MIN MAX = -55°C Settling time Slew rate 7 DAC87U-CBI-VlB DAC87U-CBI-V MIN MAX UNITS j.lsec V/lAsec 7 po see V//J.sec 7 JJ.sec V/p,sec NOTES: y ±Vcc = 15VDC. VDD =5VDC. Logic 1 = 4V. Logic 0 = 0.2V. no load. unless otherwise specified. Y Offset error corrected to zero. ~ The individual bit errors that are positive are switched on and compared to 1/2LSB. The individual bit errors that are negative are switched on and compared to 1/2LSB. This guarantees ±1/2LSB maximum linearity error. Y Offset error and gain error correction factors for the Device Under Test r OUT I. if any. are applied to the OUT output voltage before comparing the OUT output voltage • to the ideal output voltage. This Is the basis for linearity error and differential linearity error relative to a straight line through the end pOints of the transfer function. Differential linearity error is tested at all combinations of the four most significant bits. ~ 'l/ Total error, trimmed, (bipolar! is the same as linearity error, bipolar. y Offset and gain errors adjusted to zero at TA = +25°C. TABLE IV. Group C, End Point Electrical Parameters. (TA = +25°C, ±Vcc = 15VDC, VIlIl = +5VDC) Test Total error. untrimmed. bipolar Limit Delta ±O.15% of FSR ±O.l2% of FSR ±1.0LSB ±0.75LSB +1.2LSB. -1.0LSB ±0.6LSB Linearity error, bipolar Differentlall,inearityerror. bipolar Yes -- Offset error. bipolar ±O.125% of FSR ±0.10% of FSR Gain error, bipolar ±O.25% of FSR ±O.25% of FSR Monotoniclty TABLE V. Ideal Output Voltage vs Digital Input Code. Digital Input Code rComplementary 12-Bit BlnarYI' Output Range -2.5V to +2.5V -5Vto +5V -10Vto +10V Oto+5V Oto+l0V 111111111111 011111111111 0000 0000 0000 -2.500V -5.000V -10.000V 0 0 0 0 0 +2.500V +5.000V +2.498779V +4.997559V +9.99S117V +4.998779V +9.997559V NOTES: 1. One LSB = 1.2207mV for a 5-volt full scale range. One LSB = 2.4414mV for a 10-volt full scale range. One LSB = 4.8828mV for a 20-voll full scale range. 2. Digital input codes are shown with the MSB listed first. T ABLE VI. Output Range Selection. Output Range -2.5V to +2.5V -5V to+5V -10V to +10V o to+5V o to +10V Required External Pin Connectior'lS 17 to 20 19t020 17 to 20 19NC 17 t020 19to15 17 t021 19 t020 17 t021 19NC 15to18 15 to 18 15to19 15to18 15 to 18 7-31 16to 24 16 to 24 161024 16 to 24 16t024 DAC87/MIL SERIES .IOVOC--o r"" ,,}, ,... I I .L../ I DIGITAL VOLTMETER I I -""'" I :" I/""~ Va ISLEW RATEI FIGURE 6. Slew Rate and Settling Time Test Circuit. FIGURE 5. Test Circuit - Simplified. 4. PRODUCT ASSURANCE PROVISIONS 4.1 Sampling and inspection. Sampling and inspection procedures are in accordance with M IL-M-385 10 and MILSTD-883, medhod 5008, except as modifed herein. 4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. When so required, qualification will be in accordance with the inspection routine of M IL-M-38510, paragraph 4.4.2.1. The inspections to be performed are those specified herein for groups A, B, C, and D inspections (see paragraphs 4.4.1, 4.4.2,4.4.3, and 4.4.4). Burr-Brown has performed and successfully completed qualification inspection as described above. The qualification report is available from Burr-Brown. 4.3 Screening. Screening, for / MIL and / B Hi-ReI product designations, is in accordance with M IL-STD-883, method 5008, hybrId class, and is conducted on all devices. The following additional criteria apply: a. Constant acceleration test (MIL-STD-883, method 2001) is test condition B, V, axis only. b. Interim and final test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Burn-in test (MIL~STD-883, method 1015) conditions: (I) Test condition D (2) Test circuit is Figure 7 herein (3) TA = +125°C minimum (4) Test duration is 160 hours minimum 2kn .5V OV FIGURE 7. Test Circuit-Bum-in and Operating Life Test. d. Percent defective allowable (PDA). The PDA, for / MIL Hi-ReI product designations only, is 10 percent and includes both parametric and catastropic failures. It is based on failures from group A, subgroup I test after 7-32 DAC87/MIL SERIES cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from preburn-in screening may be excluded from the PDA. If interim electrical parameter tests prior to burn-in are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based on the PDA. e. External visual inspection need not include measurement of case and lead dimensions. 4.4 Quality conformance inspection. Groups A and B inspections of M I L-STD-883. method 5008. are performed on each inspection lot. Group 0, subgroup I, seal test. of M I L-STD-883. method 5008. is performed on each lot of packages procured. Groups C and D inspection (except for subgroup I. seal test) of M I L-STD-883. method 5008. are not re4uired unless specified by contract or purchase order. Burr-Brown periodically performs groups C and D inspections of M IL-STD-883. method 5008. A report of the most recent groups C and D inspections is available from Burr-Brown. 4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in M II.-STD-883. method 5008. Table I. and as follows: a. Tests are specified in Table II herein. b. Tests previously performed as part of final electrical test need not be repeated. 4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in MIL-STD-883. method 5008, Table II and as follows: a. Particle impact noise detection test is not required. 4.4.3 Group C inspection. Group C inspection consists of the test subgroups and LTPD values shown in M I L-STD-883. method 5008, Table III, and as follows: a. Operating life test (MIL-STD-883, method 1005) conditions: (I) Test condition D (2) Test circuit is Figure 7 herein (3) TA = +125"C minimum (4) Test duration is 1000 hours minimum b. End point electrical parameters are specified in Table II herein. c. Additional electrical subgroups are specified in Table II herein. 4.4.4 Group D inspection. Group D inspection consists ofthe test subgroups and LTPD values shown in M I L-STO-883. method 5008. Table IV and as follows: a. Particle impact noise detection test is not required. 4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables. Electrical test circuits are as prescribed herein or in the referenced test methods of M I L-STD-883. 4.5.1 Voltage and current. All voltage values given. except the input offset voltage (or differential voltage) are referenced to the external zero reference level of the supply voltage. Currents given are conventional current and positive when flowing into the referenced terminal. 4.6 Inspection of preparation for delivery. Inspection of preparation for delivery is in accordance with M I L-M-385·1O. except that the rough handltng test does not apply. 5. PREPARATION FOR DELIVERY 5.1 Preservation-packaging and packing. Microcircuits are prepared for delivery in accordance with M IL-M-38510. 6. NOTES 6.1 ~ The notes specified in MIL-M-38510 are applicable to this specification. 6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of screened parts is desirable. 6.3 Ordering data. The contract or order should specify the following: a. Complete part number (see paragraph 1.2) b. Requirement for certificate of compliance, if desired. 6.4 Definitions. Offset error. Offset error is the difference between the ideal analog output voltage and the actual output voltage, when all the input bits are off (digital input code IIII IIII 1111). Gain error. Gain error is the difference between the ideal analog output voltage span and the actual output voltage span. between when all the input bits are off (digital input code II1I IIII 1111)and when all the input bits are on (digital input code 0000 0000 0000). Linearity error. Linearity error is the difference between the ideal analog output voltage and the actual output voltage. when the offset error and the gain error equal zero. 7-33 DAC87i MIL ~ERIES Differential linearity. Differential linearity is the difference between the ideal (I LSB) analog output voltage change, for I-bit change in digital input code, and the actual output voltage change. Adifferentiallinearity of± I LSB means that the output can change anywhere from OLSB to 2LSB when the input changes from one adjacent input code to the next. Differential linearity of ±I LSB or less guarantees monotonicity. Monotonicity. Monotonicity is the condition where the analog output increases or remains the same for an increase in input codes. Unipolar output. Unipolar is an output characteristic that displays zero volts output at one input extreme and full scale volts output at the other input extreme. Bipolar output. Bipolar is an output characteristic that displays full scale output voltage at one input extreme and the opposite full scale output voltage at the other input extreme. 6.5 Microcircuit group assignment. These microcircuits are .in Technology Group F as defined in M I L-M-38510, Appendix E. 6.6 Electrostatic sensitivity. These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive precautions should be observed at all times. 7. APPLICATIONS INFORMATION 7.1 Power Supply Decoupling. For optimum performance and noise rejection, each power supply should be decoupled by connectmg a II'F t.antalum capacitor from each power supply pin to the ground plane. 7.2 Power supply sensitivity. Power supply sensitivity is specified in Table I. Power supply sensitivity versus ripple frequency IS shown IIi Figure 8. 0.1 lI.OII ~"i 0J14 ::.i 11.02 II!! 0.01 0.1116 :::~ 0.D04 ~I!i IJ.OO2 ;I' ;... I ........00·- / ~ .J' ' I '..~ \.Ollt $11' '- +15V SUPPlIES 0.001 I 10 "" 100 Ik POWER SUPPLY RIPPLE FREQUENCY 1Hz) 10k lOOk FIGURE 8. Typical Power Supply Sensitivity vs Power Supply Ripple. 7.3 External offset and gain error adjustment. The untrimmed accuracy of the DAC87/ MIL Series is very good and is adequate for many applications. However, when the initial offset and gain errors are greater than what can be allowed in the application, the circuits shown in Figure 4 may be connected and the offset and gain errors may be adjusted to zero. 7.3.1 Offset adjustment. Apply the digital input code, IIII IIII 1111, which should produce zero volts output for the unipolar ranges, or mmus full scale for the bipolar ranges. Adjust the offset potentiometer until the output, for the output range being used, is exactly as depicted in Table V. 7.3.2 Gain adjustment. Apply the digital input code, 0000 0000 0000, which should produce positive full scale. Adjust the gain potentiometer until the output, for the output range being used, is exactly as depicted in Table V. 7-34 BURR-BROWN® 113131 OPA10S/MIL SERIES MODEL NUMBERS: OPA10SVM/MIL OPA10SVM/883B OPA10SVM OPA10SWM/MIL OPA105WM/883B OPA105WM OPA10SUM/883B OPA10SUM REVISION NONE FEBRUARY, 1982 FET Input Military OPERATIONAL AMPLIFIER FEATURES APPLICATIONS -LOW BIAS CURRENT, lpA, max - HIGH INPUT IMPEDANCE, 10130 - CURRENT TO VOLTAGE CONVERSION - ULTRA-lOW DRIFT, 2/o1V/oC, max -LOW OFFSET VOLTAGE 250/oIV, max - PRECISION VOLTAGE AMPLIFICATION FOR HIGH INPUT IMPEDANCE APPLICATIONS -LONG TERM PRECISION INTEGRATION -LOW QUIESCENT CURRENT, 1.5mA, max - HERMETICALLY SEALED TO-99 PACKAGE DESCRIPTION The OPAI05/MIL Series is a low bias current operational amplifier. Guaranteed low initial offset voltage (250/01 V. max) and associated. drift versus temperature (2/01 v!"e. max) is achieved by laseradjusting the amplifier during manufacturing. This feature. and guaranteed low bias current (1 pA. max). allow greater system accuracy with no external components. Quiescent current (1.5mA. max) is unaffected by changes in ambient temperature or power supply voltage. Other characteristics of the OPA 105/ MIL Series include internal compensation for unity-gain stability and rapid thermal response for quick stabilization after turn-on or temperature changes. The amplifier is free from latch-up and is protected for continuous output shorts to common. As an added protection feature. either of the trim pins can be accidentally shorted to a potential greater than the negative supply voltage without damage. The standard pin configuration (741 type) of the OPAI05/MIL Series allows the user drop-in replacement capability. A pin 8 case connection permits the reduction of noise and leakage by employing guarding techniques. International Airport Industrial Parte· P.O. Bex 11400· Tucson. Arizona 85734· TaI.1602H46·1111 . Twx: 910-952·1111 . Cabla: BBRCORp· Talex: 66-6491 PDS468 7-35 OPAOI5/ MIL SERIES DETAILED SPECIFICATION MICRQqIRCUIT:S, LINEAR OPERATIONAL AMPLIFIER . HYBRID, SILICON I. SCOPE 1.1 Sco!,e. This specification covers the detail requirements for a FET input. low bias current, low drift, integrated circuit operatio~al amplifier. " 1.2 Part N urnber. The complete part p~mber is, asshown below. O'PAI05 V Basic model number M iMIL T lGrade lMetal (see' 1.2,) package I Hi-ReI product designator (see 1.2.2) 1.2.1 Device typ~ The device is a single opera,tional amplifier. Three electrical performance grades are provided. The W grade features ±2/L V/"C drift (-55"C to +125"C). the V grade features ±5/LV InC drift (-SS"C to + 12S°C). The U grade features excellent performance (±IS/LV /"C), from -2S'C to +8S"C and guarantees performance f~om -S5"C to +12S"C. Electrical specifications are shown in Table I. Electrical tests are shown in Tables II and III. 1.2.2 Device class. The device Class issi~ilar to the hybrid class (class B) product assurance level, as defined in M I L-M -38S1 O. The Hi-ReI product designator .portion of the part number distinguishes the product assurance levels as follows: Hi-ReI product Requirements designator Standard model, plus 100% MIL-STD-883 hybrid class screening;.with 10% PDA, /MIL plus quality conformance inspection (QCI) consisting of Groups A and B on each inspection lot, plus Groups C and D performed initially and periodically thereafter. Additional electrical testing is performed on j MIL models. /883B (none) Standard model, plus 100% MIL-STD-883 hybrid class screening. Standard model including 100% electrical tes~ing. 1.2.3 Case outline. The case outline is A-I (8-lead can, TO-99) as defined.in MIL-M-38SI0, Appendix C.Thecase is metal and is conductive. . 1.2.4 Absolute maximum rating~ Supply voltage range Input voltage range Differential input voltage range Storage temperature·.range Output short-circuit duration Lead temperature (soldering, 60sec) Junction temperature ±20VDC ±20VDC! ±40VDC! -6S"C to +ISO"C Unlimited l 300"C TJ = 17S"C 1.2.S Recommended o!,erating conditions. Supply voltage range Ambient temperature range 1.2.6 Power and thermal characteristics. Package 8-lead can 1 .£ Case outline Figure I ±5VDC to ±20VDC -5S"C to + 12S"C Maximum allowable power dissipation 225mW at TA -125"C Maximum 8 J-A 220"C;W The absolute maximum input voltl;l.ge is equal to the supply voltage . Short circuit may be to ground fmly. Ruting apples· to +135"C case temperature or +50"(, amhient temperature at ±15\,DC .supply \ultagc. 7-36 OPAIOS/MIL SERIES 2. APPLICABLE DOCUMENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICA TlON MILITARY MIL-M-38SIO - Microcircuits, general specification for. STANDARD MILITARY MIL-STD-883 - Test methods and procedures for microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to assure successful compliance with this specification. 3.1.1 Detail specifications. The individual item requirements are specified herein. In the event of conflicting requirements the order of precedence will be the purchase order, this specification, and then the reference documents. 3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States of America. 3.2 Design, construction, and PBysical dimensions. 3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 3.S.1 of M IL-M-38SIO. The exterior metal surfaces are corrosion resistant. The other materials are non nutrient to fungus as specified in MIL-M-38SIO. See Figure I for the case outline. Note: Leads in true position within 0.010" rO.2Smm' R at MMC at seating plane. Pin numbers shown 10r reference only. Numbers may not be marked on package. DIM A C D G H INCHES MAX MIN MILLIMETERS MIN MAX .335 .370 B.51 9.40 .305 .335 7.75 8.51 .165 .185 4.19 4.70 .016 .021 0.41 0.53 .010 .040 0.25 1.02 .010 .040 0.25 , .02 .200 BASIC 5.08 BASIC .028 .034 0.71 .029 .045 0.74 .500 12.7 .110 160 2.79 M 45° BAStC N .095 I .105 0.86 1.14 4.06 45° BASIC 2.41 2.67 FIGURE I. Case Outline (TO-99) Package Configuration. 3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38SI0. 3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with MIL-M-38SI0. 3.2.4 Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel underplating. The lead material and finish is in accordance with M IL-M-38SIO and is solderable per M IL-STD-883. method 2003. 3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38SI0. 3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.7 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure 2. 3.2.8 Glassivation. All dice are glassivated. 3.2.9 Schematic Circuit. The schematic circuit is shown in Figure 3. 7-37 OPAIOS/ MIL SERIES -Vee a-LEAD eAN (TOP VIEW] FIGURE 2_ Circuit Diagram and Terminal Connections_ INTERMEDIATE STAGES BIAS NETWORK -Vee OUTPUT STAGE INPUT STAGE FIGURE 3. Simplified Schematic Circuit. 3.3 Electrical Performance Characteristics. The electrical performance characteristics are as specified in Table I and apply over the full operating ambient temperature range of -SS"C to +12S o C unless otherwise specified. 3.3.1 Additional Electrical Performance Characteristics. Electrical performance curves are shown in paragraph 7. 3.3.2 Offset null. The amplifier is capable of being nulled to zero offset voltage using the circuit in Figure 4. If nulling is unnecessary for the application. delete the three components and make no connections. 7-38 OPAI05/MIL SERIES +Vee '''~'lo----{ OUTPUT ~~=:f.;::==== OFFSET NULL .Vee FIGURE 4. Offset :'IIull Circuit. 3.3.3 Frequency compensation. No frequency compensation is required. The amplifier is free of oscillation when operated at any gain and when operated in any test condition specified herein. 3.4 Electrical tests. Electrical tests are shown in Table II. The subgroups of Table III and limits of Table IV. which constitute the minimum electrical tests for screening. qualification. and quality conformance. are shown in Table II. 3.5 Marking. Marking is in accordance with MIL-M-38510. The following marking is placed on each microcircuit as a minimum. a. Part number (see paragraph 1.2) b. Inspection lot identification code 1. f IcatlOn i ' (ii""'!!!!!W d . M anu f acturer's " Identl s s lN ®.J e: Manufacturer's designating symbol (CEBS) f. Country of origin (U.S.A.) 3.6 Workmanshi(l. These microcircuits are manufactured. processed. and tested in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices. workmanship instructions. inspection and test procedures, and training, prepared in fulfillment of Burr-Brown's product assurance program. 3.6.1 Rework provisions. Rework provisions. inc! uding rebonding for the / MIL H i-Rei prod uct designation. are in accordance with MIL-M-38510. 3.7 Traceability~ Traceability for / MIL Hi-Rei product designation is in accordance with MIL-M-3851O. Each microcircuit is traceable to the production lot and to the component vendor's component log. Reworked or repaired microcircuits maintain traceability. 3.8 Product and (lrocess chang!C: Burr-Brown will not implement any major change to the design. materials. construction, configuration, or manufacturing process which may affect the performance, quality or interchangeability' of the microcircuit without full or partial requalification. ! a 4-digit date code. indicating year and week of seal. is marked on R838 and (none) Hi-Rei product 7-39 designati()n~. OPAWS/MIL SERIES TABLE I. Electrical Performance Characteristics. All characteristics at -55"C:5 TA:5 +125"C. ±Vee = 15VOC. unless otherwise specified. CHARACTERISTIC GAIN Open-Loop Voltage Gain SYMBOL Avs OPA105WMIMIL" OPA105WMIII3B OPA1OSWM MIN TYP MAX CONDITIONS RL-2kO Va = ±IOV. F = OHz I TA -+25°C -55"C:5 TA:5 +1 25°C 106 100 112 106 ±IO 500 10 ±12 ±IO 3 1000 25 14 O.g I 20 1.3 OPA105VM/MlL" OPA1OSYMIII38 OPA1OSVM MIN TYP MAX RL=2kO Vo 10 Zo CL los To Ground BW BW SR Ts Ts Tr Unity Gain-Small Signal TA = +25°C Full Power TA = +25°C TA =+25°C RL =2kO. TA = +25°C TA =+25°C TA = +25°C ±5 TA ",+25°C TA=+25OC UNITS · · ·· · RATED OUTPUT Voltage Current Impedance Load Capacitance(1) Short Circuit Current OPA1OSUM/8138 OPA10S1.!M MIN TYP MAX dB dB V mA kO pF mA · DYNAMIC RESPONSE Bandwidth Bandwidth Slew Rate Settling Time 10.1%} Settling Time 10.01%} Overload Recoveryl2} MHz kHz VI~sec 9 20 4 ~sec ~sec 15 ~sec ±250 ~V INPUT OFFSET VOLTAGE Initial Offset Temperature Sensitivity vs Power Supply V,O OV,O VosITA}- Vos (+25°CI TA =+25°C PSRR aT -55:5 TA:5 +1 25°C -25:5 TA:5 +85°C Vee = ±5. Vee = ±20VDC ±2 ±5 ~VJOC ±25 ±15 ~VJOC ±74 dB I pA pAIV INPUT BIAS CURRENT Initial Bias vs Supply Voltage Ib TA = +25°C TA=+25°C 0.005 TA =+25°C ±O.2 Differential TA =+25"C Common-Mode TA=+25°C 1013 11 1.6 1015 11 I.B INPUT OFFSET CURRENT Initial Offset los I · I I pA INPUT IMPEDANCE ;. · 011 pF 011 pF INPUT NOISE Voltage Current en in fo = fo = fo = fo = fa = fa = fa = fo = 10Hz 100Hz 1kHz 10kHz O.IHz to 10Hz O.IHz to 10Hz 10Hz to 10kHz 1kHz TA = +25OC TA = +25°C TA =+25°C TA=+25°C TA=+25°C TA=+25°C TA = +25°C TA =;I-25°C 55 35 30 25 3 0.01 0.03 0.6 nV/v'Hz nVlv'Hz nV/v'Hz nVlv'Hz ~VI,p-p pA,p-p pA, rm. fA/v'Hz INPUT VOLTAGE RANGE Differential Common-Mode Common-Mode Rejection Vai CMRR Y,N =±IOV ±20 TA - +25°C TA =+25"C TA = +25°C ±IO 76 ±12 , 86 V V dB POWER SUPPLY Rated Voltage Voltage Range Quiescent Current ±15 ±5 a 1.0 ±20 1.5 VOC VOC mA +125 +150 °C °C TEMPERATURE RANGE (ambient) Operating Storage -55 -65 'Sameas OPAI05W Grade. "OPAI05WM/MIL and OPAI05VM/MIL available 4th quarter 1982. NOTES: I. Stability guaranteed with Load Capacitance :5500pF and a 1000 resistor In series with pin 6 for units manufactured prior to January 1.1982. 2. Overload recovery is defined as the time required for the output to return from saturation'to linear operation following the rernoval of a 50% input overdrive signal. 3. Bias current is testea and guaranteed at TA = +25°C. For higher temperature the bias current doubles every +100 C. 7-40 OPAJ05/MIL SERIES 3.9 Screening. Screening, for / MIL and /883B Hi-Rei product designations, is in accordance with MIL-STD-883, method 5008, hybrid class, except as modified in paragraph 4.3 herein. Screening for the standard model includes Burr-Brown QC4118 internal visual inspection and stabilization bake, fine leak, gross leak, burn-in (72 hours performed preseal), constant acceleration (condition B), and external visual inspection per MIL-STD-883, method 5008, hybrid class. For the / MIL Hi-Rei product designation, all microcircuits will have passed the screening requirements prior to qualification or quality conformance inspection. 3. JO .Qualification. Qualification is not required. See paragraph 4.2 herein. 3.11 .Qualit)l conformance ins[lection. Quality conformance inspection, for / MIL Hi-Rei product designation, is in accordance with MIL-M-385JO, expect as modified in paragraph 4.4 herein. The mircocircuit inspection lot will have passed quality conformance inspection prior to microcircuit delivery. TABLE II. Electrical Test Requirements. (The individual tests within the subgroups appear in Table Ill) MIL-$TD-883B REOUIREMENTS (hybrid Clall) Interim electrical parameters (pre burn-in 1 {melhod 5008) Final electrical test parameters (method S008) Group A test requirements {method S0081 Group C enp point electrical parameters (method 50081 1,4 1,4 1,4 1,4 1,4 1',2,3,4 1,2,3,4 1',2,3,4 1,2,3,4 1, 2U, 3U, 4 1,2,3,4 1,2,3,4 Table IV Limits and Delta limits Table IV Limits and Delta Limits 4C, 5, 8 4C,5,6 Additional electrical subgroups performed priorloGroupC inspeclions 'PDA applies 10 subgroups 1, 4 (see4.3d) TABLE III. Group A Inspection. LIMITS MIL-STD-883 METHOD OR SUBGROUP SYMBOL .,,'uu. I ...... CONDITIONS ±VCC= 15V unl_ olllerwl.. lpeclfled V,O liB Vo Ie CMRR PSRR 4001 4001 2 TA=+125 OV,O 4001 Vos 1+1251-Vos (25) 100 2U TA=+85"C OV,O 4001 Vos (+85)-Vos (25) 60"C 3 TA = -55"C OV,O 4001 Vos (25)-Vos (-55) 80 3U TA = -25"C OV,O 4001 Vos (25)-Vos (-251 50 4 TA = +25"C Avs SR 4004 4002 f =OHz, RL = 2kO RL = 2kO, Vo = ±10V 4C TA = +25"C T, 1 TA=+25"C OPA105WM/MIL OPA105WM1883B OPA105WM MIN MAX OPA105VMIMIL OPA105VM/B83B OPA105VM MIN MAX ±2SO ±1 RL =2kO 1.5 4003 VCM ±10V Vee = ±5V, Vee = ±20V 76 74 250 ±1 ±2SO ±1 ±10 ±10 OPA105UM/B83B OPA105UM MIN MAX ±10 1.5 76 74 2 1.5 76 74 15 50% Input Overdive 106 0.9 15 106 0.9 15 pA V mA dB dB ~V/"C ~V/"C 5 15 106 0.9 ~V ~V/"C 5 2 UNITS ~V/"C dB V/~sec ~sec 5 TA=+125"C Avs 4004 f =OHz, RL = 2kO 100 100 dB 6 Avs 4004 f = OHz, RL = 2kO 100 100 dB TA = -55°C 7-41 OPAI05! MIL SERIES TABLE IV. Group C, End Point Electrical Parameters ITA ~ +2So C, ±vcc ~ 1SVDC, VCM ~ OV, TEST LIMIT DELTA V,O ±2S0~V ±12S~V liB ±1pA ±O.8pA 4. PRODUCT ASSURANCE PROVISIONS 4.1 Saml'ling and inspection. Sampling and inspection procedures are in accordance with MIL-M-3851O and MIL-STD-883, method 5008, except as modified herein. 4.2 Qualification. Qualification is not required unless specifically required by contract or purchase qrder. When so required, qualification will be in accordance with the inspection routine of MIL-M-38510, paragraph 4.4.2.1. The inspections to be performed are those specified herein for groups A, B, C and D inspections (see paragraphs 4.4.1, 4.4.2, 4.4.3, and 4.4.4). Burr-Brown has performed and successfully completed qualification inspection as described above. The most recent report is available from Burr-Brown. 4.3 Screening. Screening, for / MIL and /883B Hi-ReI product designations, is in accordance with MIL-STD-883, method 5008, hybrid class, and is conducted on all devices. The following additional criteria apply; a. Constant acceleration test (MIL-STD-883, method 2001) is test condition B, Y, axis only. b. Interim and final test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Burn-in test (MIL-STD-883, method 1015) conditions: (I) Test condition B (2) Test circuit is Figure 5 herein (3) TA = +125°C minimum ,(4) Test duration is 160 hours minimum d. Percent defective allowable (PDA). The PDA, for / MIL Hi-ReI product designation only, is 10 percent and includes both parametric and catastropic failures. It is based on failures from group A, subgroup I test after cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from preburn-in screening failures may be excluded from the PDA. Ifinterim electrical parameter tests prior to burn-in are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based on the PDA. e. External visual inspection need not include measurement of case and lead dimensions. FIGURE 5. Test Circuit, Burn-in and Operating Life Test. 4.4 Quality conformance inspection. Groups A and B inspections of MIL-STD-883, method 5008, is performed on each lot. Group D, subgroup I, seal test, of MIL-STD-883, method 5008, is performed on each lot of packages procured. Groups C and D inspections (except for subgroup I, seal test) of MIL-STD-883, method 5008, are not required unless specified by contract or purchase order Burr-Brown periodically performs groups C and D inspections of MIL-STD-883, method 5008. A report of the most recent groups C and D inspections is available from Burr-Brown. 4.4.1 9..!:2E1' A insp'ection. Group A inspection consists of the test subgroups and LTPD values shown in M I L-STD-883, method 5008, Table I, and as follows: a. Tests are specified in Table II herein. b. Tests previously performed as part of final electrical test need not be repeated. 7-42 OPAI05/MIL SERIES 4.4.2 Group. B insp'ection. Group B inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table II, with the exception that particle impact noise detection test is not required. 4.4.3 GrouP. C insp'ection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table III, and as follows: a. Operating life test (MIL-STD-883, method 1005) conditions: (I) Test condition D (2) Test circuit is Figure 5 herein (3) T A= + 125°C minimum (4) Test duration is 1000 hours minimum b. End point electrical parameters are specified in Table II herein. c. Additional electrical subgroups are specified in Table II herein. 4.4.4 Group' D inspection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table IV, with the exception that particle impact noise detection test is not required. 4.5 Methods of examination and test. Methods of examination and test are specified in the appropriate tables. Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883. 4.5.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) are referenced to the external zero reference level of the supply voltage. Currents given are conventional current and positive when flowing into the referenced terminal. 4.6 Insp'ection of p'rep-aration for delivery. Inspection of preparation for delivery is in accordance with MIL-M-38510, except that the rough handling test does ':;:-ot apply. 5. PREPARATION FOR DELIVERY 5.1 Preservation-~g~ packing. Microcircuits are prepared for delivery in accordance with MIL-M-38510. 6. NOTES 6.1 Notes. The notes specified in MIL-M-38510 are applicable to this specification. 6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of screened parts is desirable. 6.3 Ordering data. The contract or order should specify the following: a. Complete part number (see paragraph 1.2) b. Requirement for certificate of compliance, if desired. 6.4 Microcircuit group assignment. These mircocircuits are assigned to Technology Group F as defined in MIL-M38510, Appendix E. 6.5 Electrostatic sensitivity. These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive precautions should be observed at all times. 7. ELECTRlCAL PERFORMANCE CURVES. (Typical at TA = +25°C and ±Vcc = 15VDC unless otherwise specified). 120 OPEN-LOOP FREQUENCY RESPONSE ,~ ~loo .1- ~ .~ ,so (!) Jg 45 60 i\. r\. 40 """ \.. .~ 20 01 VOLTAGE FOLLOWER LARGE SIGNAL RESPONSE RL=2kO CL=500pF :;; Q. 251--+--+-+--+--+--1 ~ 10 OUTPUT VOLTAGE vs FREQUENCY 30~~~~~R~L~_-2~kO~' +90 , r 0 90 13 ~Q.10 ~emf:~llf: :3 ~ '[ -5 S 0 1 10 100 lk 10k lOOk 1M Frequency (Hz} ~ " +40 '" , S 0 1\ CMRR AND PSRR +PSRR t iii!.. ~ o 1 2 3 Time (~sec) 4 TA 100 lk 10k lOOk 1M 7-43 (~sec} in COMMON-MODE REJECTION TALsl.c TAJ+~50C '" Frequency (Hz} 40 60 80 -~ TA~·C ~120'r,;;;+~;;;;;;;;j;;;+;j1 1 ~ 0.5 ~ iii!.. g -PSRR ~ o.~ 0 20 Time QUIESECNT SUPPLY CURRENT ~ 1.5 E ~ I:a.. RL=2kO. CL= JdF 0 Frequency (Hz} <: = -C~~ '" \.. -40 I 1\ \ \ 0-10 5 IS 10 100 lk 10klooklM 10M 0 STEP RESPONSE I I I ~ ~too.,. f:I--+--+-+-+-+--I ~ 401--+--+-+-+-+--1 ~ 201-+-+-+-+-+----1 E 5 10 15 a 20 U Power Supply Voltage (±V} 0 5 10 .15 Common-Mode Input Voltage (±V} OPAOIS/ MIL SERIES 8. APPLICATION INFORMATION 8.1 Offset Voltage Adjustment. Although the OPAIOS/MIL Series has a low intital offset voltage (2S0}lV), some applications may require external nulling of this small offs,t. Figure 4 shows the recommended circuit for adjustment of the offset voltage. External offset voltage adjustment changes the laser adjusted offset voltage temperature drift slightly. The drift will change approximately 0.3}l V j"C for every 100}l V of offset adjustment. 8.2 Guarding and Shielding. The ultra-low bias current and high input impedance of the OPA lOS/ MIL Series are well-suited to a number of stringent applications. However, careless signal wiring of 'printed circuit board layout can degrade circuit performance several orders of magnitude below the capability of the OPAl OS/ MIL Series. As in any situation where high impedances are involved, careful shielding is required to reduce "hum" pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Leakage currents across printed circuit boards can easily exceed the amplifier's bias current of the OP A lOS/ M I('Series. To avoid leakage problems, it is recommended that the signal input lead of the OPAIOS/ MIL Series be wired to a Teflon standoff. If the OPAIOS! MIL Series is to be soldered directly into a printed circuit board, utmost care must be used in planning the board layout. A "guard" pattern should completely surround the two amplifier input leads and should be connected to a low input impedance point which is at the signal input potential. The amplifier case should be connected to any input shield or guard via pin 8. This insures that the amplifier itself is fully surrounded by guard potential, minimizing both leakage and noise pickup. Figure I illustrates the use of the guard . The resistor RJ shown in Figure S is optional. It may be used to compensate effects of very large source resistances. However. note that its use would also increase the noise due to the thermal noise of RJ. 8.3 Thermal Resp'onse Time. Thermal response time is an important parameter in low drift operational amplifiers like the OPAIOS! MIL Series. A low drift specification would be of little value if the amplifier took a long time to stabilize after turn-on or ambient temperature change. The TO-99 package and careful circuit designprovide the necessary quick thermal response. Typical warm-up drift of the OPAlOS! MIL Series is 20 seconds. R2 INPUT o--~Ir-;!T-=::;=~:::::;I GUARD OUTPUT I OUTPUT INPUT ~----I---....J4 +vee(\.7~ ~'\J 01 OUTPUT 05 OUTPUT INPUT ()4 o-----!-L_-_-__-_-_...-H 'V ee NONINVERTING AMPLIFIER "R3 may be used to compensate lor very large source resistances. ~.s-" GUARD R1 R2/(R I + Rzi must be LOW impedance. Board layout for Input Guarding with TO.g9 Package. FIGURE S. Connection of Input Guard. 7-44 2 3~ ~ BURR-BROWN® 113131 OPA600/MIL SERIES MODEL NUMBERS: OPA600VM/MIL OPA600UM/883B OPA600VM/883B OPA600UM OPA600VM REVISION NONE FEBRUARY, 1982 Fast Settling - Wideband OPERATIONAL AMPLIFIER FEATURES APPLICATIONS • FAST SETTLING BOnsec to ±O.I % 115nsec to ±O.D1 % • VOLTAGE CONTROLLED OSCILLATOR DRIVER • FULL DIFFERENTIAL FET INPUT • ·55°C TO +125°C OPERATION • LARGE SIGNAL, WIDEBAND DRIVERS • HIGH SPEED DAC OUTPUT AMPLIFIER • VIDEO PULSE AMPLIFIER • LARGE OUTPUT ±10V, ±200mA (50nl • GAIN·BANOWIOTH PRODUCT· 5GHz DESCRIPTION The OPA600 is a wideband operational amplifier specifically designed for fast settling to ±0.01% accuracy. It is stable, easy to use, has good phase margin with minimum overshoot, and it has excellent DC performance. It utilizes a FET input stage to give low input bias current in contrast to the higher currents usually associated with very-fast amplifiers. Its DC stability with temperature is outstanding. Its ·3dB bandwidth of 100M Hz is available at a closed loop gain of 10. The slew rate exceeds 400V / !-,sec. All of this combines to form an outstanding amplifier for large and small signals. Settling time is the best measure of this amplifier's total dynamic capability. High accuracy with fast settling is achieved by the large open-loop gain, which provides the accuracy at the upper frequencies. The thermally balanced design maintains this accuracy without droop or thermal tail. External compensation allows the user to optimize the settling time in his application. The OPA600 is built to be reliable and is designed to operate from T A = -55°C to + 125°C. It is a hybrid microcircuit in a welded, hermetic, metal package International Alrpo~t and is available with MIL-STD-883 screening. The circuit is built on an alumina substrate which has a metallic attach to the package for good thermal transter and reliable high temperature operatIOn. The metal package provides electrostatic shielding. The circuit uses thin-film resistors and all glassivated, high speed silicon die. The gold or aluminum wirebonds utilized produce a monometallic system wherever possible, eliminating metal migration, a time-temperature reliability problem. The amplifier is actively laser-trimmed and is thoroughly tested. Reliability is emphasized during each phase of manufacture. The OPA600 is useful in a broad range of video, high speed, and ECM applications. It is particularly well suited to operate as a voltage controlled oscillator (VCO) driver. It makes an excellent digital-to-analog converter output amplifier. It is a workhorse in test equipment where fast pulses, large signals, and 50n drive are important. It is a good choice for sample/ holds, integrators, fast waveform generators, and multiplexers. Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 • Tel. (602) 746·1111 • Twx: 91IJ.952·1111 • Cable: BBRCORP . Telex: 66·6491 PDS460 7-45 OPA600/MIL SERIES DETAILED SPECIFICATION MICROCIRCUITS, LINEAR OPERATIONAL AMPLIFIER HYBRID, SILICON I. SCOPE 1.1 Scop~. This specification covers the detail requirements for a hybrid, fast settling, integrated circuit operational amplifier. 1.2 Part Number. The complete part number is as shown below. v OPA600 T Basic model number l M /MIL Metal package Hi-Rei product designator (see 1.2.2) T l Grade (see 1.2.1) 1.2.1 Device typ~. The device is a single, operational amplifier. Two electrical performance grades are provided, the U grade and the V grade. The V grade offers the higher performance. Electrical specifications are shown in Table I. Electrical tests are .shown in Tables II and Ill. 1.2.2 Device class. The device class is similar to the hybrid class (class B) product assurance level, as defined in MIL-M-38510. The Hi-Rei product designator portion of the part number distinguishes the product assurance levels as follows: Hi-Rei product designator /MIL /883B (none) Requirements Standard model, plus 100% MIL-STD-883 hybrid class screening, with 10% PDA, plus quality conformance inspection (QCI) consisting of Groups A and B on each inspection lot, plus Groups C and D performed initially and periodically thereafter. Additional electrical testing is. performed on / MIL models. Standard Model, plus 100% MIL-STD-883 hybrid class screening. Standard model including 100% electrical testing. 1.2.3 Case outline. The case outline (16-lead can) is as defined in Figure 6. The case is metal and is conductive. 1.2.4 Absolute maximum rating~. Supply voltage range Input voltage range Differential input voltage range Storage temperature range Output short-circuit duration Lead temperature (soldering, 60sec) Junction temperature 1.2.5 Recommended op'erating conditions. Supply voltage range Ambient temperature range 1.2.6 Power and thermal characteristics. Packag~ 16-lead can !/ I Case outline Figure 4 ±17VDC ±17VDC.!. ±25VDC..r. _65°C to +150°C A few seconds~ 300"C TJ = 175°C ±9VDC to ±16VDC -55°C to + 125°C Maximum allowable p'ower'dissipation 2.6W at TeASE = +125"C Maximum e J-C See Applications Information The absolute maximum input voltage is equal to the supply voltage. Duration is limited by device heat sinking (thermal resistance). Short circuit may be to ground only. 7-46 Maximum e C-A 35°C/W OPA600jMIL SERIES 2. APPLICABLE DOCUMENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICA TION MILITARY MIL-M-38510 - Microcircuits, general specification for. STANDARD MILITARY MIL-STD-883 - Test methods and procedures for microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to assure successful compliance with this specification. 3.1.1 Detail specifications. The individual item requirements are specified herein. In the event of conflicting requirements, the order of precedence will be the purchase order, this specification, and then the reference documents. 3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States of America. 3.2 Design, construction, and physical dimensions. 3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 3.5.1 of M I L-M -38510, except that organic and polymeric materials (epoxy) are used for attach of some of the die. The exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in MIL-M-3851O. 3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38510. 3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with MIL-M-38510. 3.2.4 Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel underplating. The lead material and finish is in accordance with M IL-M-3851 0 and is solderable per M I L-STD-883, method 2003. 3.2.5 Die thickness. The die thickness is in accordance with MIL-M-38510. 3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.7 Circuit diagram and terrninal connections. The circuit diagram and terminal connections are shown in Figure I. 3.2.8 Glassivation. All dice utilized are glassivated. OFFSET ERROR NULL loptional) j+vCC 11 COMMON lcase) JJ Rller to Figure 4 lor recommanded lrequancy companlallon. 11 Connact pin 9 10 pin 12 and connlCl pm 7 10 pin 8 lor maximum output current. Saa Y Thara II no Internal connecllon. An axlemll connactlon may ba made. !I 1111 recommendad Ihal tha ampllflar ba mounlad wllh Iha casa In contact with a ground plana lor good Iharmal tranlf.r and opllmum AC pelformlnce. AppllcaUon Inlormallon lor furlhar InformaUsn. :u BYPIII aaGh power IUPflly lead II cl... aa pnalble 10 Iha amplifier plnl. A1~f CSI311nlaium capacHur II recommandad. FI G U REI. Circuit Diagram and Terminal Connections. 7-47 OPA600/MIL SERIES 3.2.9 Schematic Circuit. The schematic circuit is shown in Figure 2. OFFSET fREQUENCY COMPENSATION OFFSET FREQUENCY COMPENSATION 5 IZ +VCC (eIsal COMMON ! FREQUENCY COMPENSATION' R7 RI3 5011 CI o.oi"F CURRENT BOOST Rll ·INPUT R4 R3 CURRENT BOOST 3r---------~----------~ RZ +---_---{7 01 RIO R9 OZI RI6 50n I 'Vce COMMON FIGURE2. Simplified Schematic Circuit. 3.3 Electrical Performance Characteristics. The electrical performance characteristics are as specified in Table I and apply over the full operating ambient temperature range of -55"C to +125°C unless otherwise specified. 3.3.1 Additional Electrical Performance Characteristics. Electrical performance characteristic curves are shown in paragraph 7. 3.3.2 Offset error null. The amplifier is capable of being nulled to zero offset voltage using the circuit in Figure 3. If nulling is unnecessary for the application, delete the three components and make no connections. INPUTS FIGURE 3. Offset Null CirCUit. 3.3.3 Freqill:.ill!y..£Q!!!pensation. The amplifier must be externally frequency compensated. See Figure 4. 3.4 Electrical tests. Electrical tests are shown in Table II. The subgroups of Table III and limits of Table IV, which constitute the minimum electrical tests for screening, qualification, and quality conformance, are shown in Table II. 7-48 , \ OPA6001 MIL SERIES 3.5 Marking. Marking is in accordance with M I L-M-385I O. The following marking is placed on each microcircuit as a minimum. a. Index point b. Part number (see paragraph 1.2) c. Inspection lot identification code Jj d. Manufacturer's identification ( E l K ) e. Manufacturer's designating symbol (CEBS) f. Country of origin (USA) 1I""-IIi@) 3.6 Workmanship. These microcircuits are manufaCtured, processed, and tested in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices, workmanship instructions, inspection and test procedures, and training, prepared in fulfillment of Burr-Brown's product assurance program. 3.6. I . Rework provisions. Rework provisions, including rebonding, for the 1MIL H i-Rei product designation, are in accordance with MIL-M-3851O. 3.7 Traceability..: Traceability for IMIL Hi-Rei product designation is in accordance with MIL-M-3851O. Each microcircuit is traceable to the production lot and to the component vendor's component lot. Reworked or repaired' microcircuits maintain traceability. 3.8 Product and (lrocess chang!:, Burr-Brown will not implement any major change to the design, materials, construction, configuration, or manufacturing process which may affect the performance, quality, reliability or interchangeability of the microcircuit without full or partial requalification. 3.9 Screening. Screening for 1MIL and 1883B Hi-Rei product designations, is in accordance with MIL-STD-883, method 5008, hybrid class, except as modified in paragraph 4.3 herein. Screenin for the standard model, includes Burr-Brown QC41 18 internal visual inspection, stabilization bake, fine leak, gross leak, burn-in (72 hours performed preseal), constant acceleration (condition B), and external visual inspection per MIL-STD-883, method 5008, hybrid class. For the 1MIL Hi-Rei product designation, all microcircuits will.have passed the screening requirements prior to qualification or quality conformance inspection. 3.10 Qualification. Qualification is not required. See paragraph 4.2 herein. 3.11 Quality conformance inspection. Quality conformance inspection, for 1MIL Hi-Rei product designation, is in accordance with MIL-M-3851O, expect as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed quality conformance inspection prior to microcircuit delivery. - ., A, A2 A3 A. C"C2 open 100 short open 68 -1 620 620 short open 33 100 1k short open 100 3.3k 3.3k 3.2k 100 3.3k 3.3k 116 a 4-digit date code, indicating year and week of seal .. is marked on /8838 and (none) Hi-Rei product designations. 7-49 C. A5 0 47 56 22 100 Note: Resistance is in ohms, capacitance is in pF, gain is volts/volt. FIGURE 4. Recommended Amplifier Circuits and Frequency'Campensation . .1J C3 100 4.7 100 OPA600/MIL SERIES TABLE I. Electrical Performance Characteristics AU characters from -55°e::;; TA:5 +125°(';, ±Vcc = 15VDC, unless otherwise noted. OPAIOOYM/MIL •• OPAIIIIIYM/883B OPAIOOYM CHARACTERISTICS CONDITIONS MIN TVP OPAIOOUM1883B OPAIOOUM MAX MIN TVP MAX UNITS OUTPUT Voltage (Vo) Current ( 10) Current, pulse (( lop) Resistance (Ro) Short Circuit Current (Iss)' ±IO ±9 ±180 ±180 RL-2kn RL =50nJl RL =50nJl RL=5011'y Open-loop, DC To ground only 1MAX = I sec .y ±II ±IO ±200 ±200 75 250 150 300 V V mA mA n mA DYNAMIC RESPONSE Settling Time, ±O.OI'lb'y (Ts) ±0.1'lb ±I'lb avo = IOV avo avo .lVo .lVo = = = = 20V IOV 20V 5V TA=25°C TA = -25°C 10 +85°C TA = -55°C to +1 25°C TA = +25°C TA =+25°C TA = +25°C .TA = +25°C 115 125 125 105 80 80 55 140 130 105 105 75 0.5 I 125 135 150 185 175 nsec nsap nsec nsec nsec nsec nsec Post Settling Time Stability (Ts+)§j ±0.01'lb t = 11'sec to 500msec Gain-Bandwidth Product (open-loop) (GBP) Cc =OPF,} G=I VN TA = +25°C 150 MHz TA = +25°C 500 MHz TA = +25°C 1.5 GHz TA = +25°C 5 GHz Cc =OPF,} G= 10VIV Cc =OpF, } G= lOOVIV Cc =OpF, G= lOOOVN Cc =OpF, } G= 10,OOOVIV I Bandwidth (BW) -3dB, small signal §/ G =+1V1V G =-IVIV G =-IVIV G=-IOVN G=-IOVN I G=-IOOVN G=-IOOOVN Full Power Bandwidth (BWFP) Slew Rate (SR) Vo = ±5V, G = -1V1V Cc =3.3pF, RL = loon 10 GHz TA = +25°C TA = +25°C TA = -55°C to +125°C TA = +25°C TA= -55°C to +125°C TA = +25°C TA = +25°C 100 75 70 80 70 15 5 125 90 90 95 95 20 6 MHz MHz MHz MHz MHz MHz MHz TA = +25°C 13 16 MHz 500 V/""sec 440 VIllsee TA = +25°C 135 135 Vo =±5V, G=IOOOVN Cc =OpF, RL = HiOll Vo =±5V, G=-IVN Cc =~.31pF, RL = loon Phase Margi n mV G =-IVIV, Cc =3.3pF TA = +25°C TA = +25°C 400 TA = -55°C to +125°C 350 TA = +25°C V/llsee 40 Degrees 94 dB dB GAIN Open-Loop Voltage Gain (AoLl I=D.C" RL = 2kn TA = +25°C TA = -55°C to +125°C 86 74 INPUT Offset Voltage (VIO) 1/ TA = +25°C TA = -25°C to '"85°C TA = -55°C to +125°C Offset Voltage vs TA = -25°C to +25°C TA +25°C to +85°C TA = .:s5°C to +25°C TA = +25°C to +125°C Temperature (VIO vs T) Bias Current (Ie) TA = +25°C TA = +25°C to +125°C Offset Current I10s) TA = +25°G TA = -55°C to +125°C 1 2 2 5 10 15 mV mV mV 50 25 80 80 100 100 "V/oC "V/oC 4 0 0 7-50 "V/DC 10 10 20 20 -20 -20. -100 -100 pA nA 20 20 50 50 pA nA /JV/oC OPA600/MIL SERIES TABLE I. Electrical Performance Characteristics (cant) All characteristics from -55°C::; TA:5. +125°C, ±Vcc = 1SVDC, unless otherwise noted. OPA600VM/MIL •• OPA600VMl883B OPA600VM Vee - ±15V, ±lV TA - +25°C Common-Mode Rejection ICMRI Impedance (Z,N I Voltage Noise (enl MIN CONDITIONS CHARACTERISTICS Power Supply Rejection IPSRI Common-Mode Voltage Range ICMVI TA ~ +25°C -10 -5V to +5V TA ~ +25°C 60 Differential Common-mode TA TA ~ ~ +25°C +25°C f TA ~+25°C VCM ~ ~ 10kHz OPAliOOUM/883B OPAliOOUM TYP MAX 200 500 MIN TYP MAX UNITS "V/v +7 V 80 dB 1011 112 10 11 II 2 nil pF nil pF 20 nV/" 'HZ POWER SUPPLY ±15 Rated Operating Range Quiescent Current TEMPERATURE RANGE (embient) Operating Storage 8JC (junction to case I tJCA (case to ambient) ±9 VDC VDC mA ::t16 ±38 ±30 -55 -65 +125 +150 -55 -65 +125 +150 °C °C See applications information 35 ·Specifications the same as V grade. °CIW "OPA6ooVM/MIL available in 2nd quarter 1982. NOTES: jJ Pin 9 connected to +Vcc, pin 7 connected to -Vee. Observe power dissipation ratings. 11 Pin 9 and pin 7 open. Single pulse t = l00nsec. Observe power dissipatIon ratings. 1/ Pin 9 and pin 7 open. See paragraph 8.8. ~ G'= -lVN, Cc = 3.3pF. RL = 100!1. Optimum settling time may be achieved by individually compensating each device. Refer to paragraph B.3. §! Post settling time stability is a measure of the pulse droop. or thermal tail, after the output has settled. ~ Compensation per paragraph 8.3. Y Adjustable to zero. NOTES: IBllHl . o 0 0 0 0 0 Seatmg Plane -LD 1. Leads in true position within 0.010" 10.25mml R at MMC at seating plane. 2. Pin numbers shown for reference only. Numbers may not be marked on package. DIM A B Denotes Pin 1 C D 16 G 9 GOOOOQ)00 INCHES MIN MAX •••• .783 .201 MIN MAX •• 72 24.58 24.' • .717 20.14 20.24 &.11 &.3' 0.41 0.&1 2.14 BASIC 3.30 3.58 .211 .01' .020 .100 BASIC I I H .130 K .230 L .800 BASIC .083 .102 R MILLIMETERS .140 &.84 .270 8.8a 11.24 BASIC 2.38 2.80 FIGURE 5. Case Outline. TABLE II. Electrical Test Requirements. (The individual tests within the subgroups appear in Table III) ~ MIL-STD·883 TEST REQUIREMENT (hybrid cl...) Interim electrical parameters ( pre burn-in}1 method 500S) OPAllOOVM/883B OPA600VM OPA800YM/MIL OPA600UM/883B OPA800UM Subgroups (see Table 1111 1 1 1 Final electrical test parameters ( method 5008) 1'.2.3.4.7.9.10.11 1.2.3.4.7.9 1.2. 2U. 3.3U.4. 7. 9 Group A test requirements (method 5008) 1. 2. 3. 4. 7.9. 10. 11 Table IV limits and delta limits - -- -- -- None -- - Group C end point electrical parameters I method 500S} Additional electrical subgroups performed prior to Group C inspections PDA applies to subgroup 1 Isee4.3.dl 7-51 OPA600/MIL SERIES TABLE III. Group A Inspection. SUBGROUP 1 "TA=+25"C 2 TA = +125°C 2U TA=+85°C 3 TA = -55°C LIMITS OPA600VM/MIL OPA600VM/883B OPA800UM/883B OPA600VM OPA600UM MIN MAX MIN MAX MIL-STD-883 METHUDOR EQUIVALENT CONDITIONS ±VCC =15V, unl_ otherwise ",ecUled +PSRR -PSRR CMR 10 4001 4001 4003 4003 4003 4005 VeM=O VeM=O +Vee = 15V. ±1V. -Vee = 15V +Vee = 15V. -Vee = 15V. ±lV VeM = -5V to +5V V,O av,o 4001 4001 SYMBOL V,O "" TT 4001 4001 V,O av,o TT 4001 4001 V,O av,o AT -2 0 -500 -500 60 +2 -100 +500 +500 -5 0 -500 -500 60 -4 -20 +4 +20 V,O r+25°C) - V,O (+85°C) 600C -4 -20 V,O r+25°C, - V,O (-55°CI 800C VIO I +25°C +4 +20 VIO r -25°C, UNITS mV pA ~V/v ~V/v 38 dB mA -15 -100 +15V +100 ~v/oC -10 -80 +10 +60 ~VloC -13 -100 +13 +100 ~VjOC -9 -80 +9 +80 #lV/oC 38 V,O (+25°C, - V,O (+125°CI 1000C +5 -100 +500 +500 mV mV mV 3U TA = -25°C V,O aT 4001 4 TA = +25°C Vo 10 Avs 4004 4004 4004 RL =2kn RL = 50n. pin 9 to +Vee. pin 7 to -Vee RL = 2kn. ,= OHz. Vo = ±10V ±10 ±180 86 ±10 ±180 86 V mA dB 7 TA = +25°C Vo Vo 4004 4004 RL = 2kn, ±Vee = 16VOC RL = 2kn, ±Vee = 12VOC ±11 ±7 ±11 ±7 V V 9 TA = +25°C ts 4002 SR 4002 I - 500C To ±O.01%, Figure 10 125 150 final value at t = 1Jlsec G = -1, Vo = ±5V, Figure 10 400 400 . mV nsec V/~sec 10% to 90% Ts+ 10 TA = +125°C ts1/ 11 TA = -55°C tsy 4002 4002 t = 1jlsec to 500msec rts to ±0.01%, :lVo = 10V, 1 mV To ±O.01%, Figure 10 140 "sec To ±O.Ol%, Figure 10 140 nsec NOTE: jJ This test required 'or IMIL suffix only. Sample test per MIL-STO-105 level II. 4.0% AOL, normal inspection. TABLE IV. Group C, End Point Electrical Parameters. (TA = +25"C ,+Vcc = 15VOC, TEST Input Offset Voltage Open-Loop Voltage Gain Settling Time (to'O.Ol%, :lVo = 20V, G = -11 LIMIT DELTA 2mV 86dS lmV 6dS 125nsec 25nsec 4. PRODUCT ASSURANCE PROVISIONS 4. I Samp'ling and inspection. Sampling and inspection procedures are in accordance with MIL-M-38510 and MIL-STD-883, method 5008, except as modified herein. 4.2 Qualification. Qualification is not required unless specified by contract or purchase order. When so required, qualification will be in accordance with the inspection routine of M I L-M-38510, paragraph 4.4.2.1. The inspections to be performed lire' those specified herein for groups A, B, C and D inspections (see paragraphs 4.4.1,4.4.2,4.4.3, and 4.4.4). Burr-Brown has performed and successf\llly completed qualification inspection as described above. The qualification report is available from Burr-Brown. 4.3 Screening. Screening, for / MIL and /883 Hi-Rei product designations, is in accordance with MIL-STD-883, method 5008, hybrid class, and is conducted on all devices. The following additional criteria apply: a. Constant acceleration test (MIL-STD-883, method 2001) is test condition B, Y, axis only. b. Interim and final test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer.' . 7-52 OPA600/MIL SERIES c. Burn-in test (MIL-STD-883. methon 1015) conditions: (I) Test condition B (2) Test circuit is Figure 6 herein (3) T A = + I 25"C minimum (4) Test duration is 160 hours minimum d. Percent defective allowable (PDA). The PDA, for /MIL Hi-ReI product designation only, is 10 percent and includes both parametric and catastropic failures. It is based on failures from group A, subgroup I test after cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from preburn-in screening failures may be excluded from the PDA. If interim electrical parameter tests prior to burn-in are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based on the PDA. e. External visual inspection need not include measurement of case and lead dimensions. FIGURE 6. Test Circuit Burn-in and Operating Life Test. 4.4 Quality conformance inspection. Groups A and B inspections of MIL-STD-883, method 5008, are performed on each inspection lot. Group D, subgroup I, seal test, of M I L-STD-883, method 5008, is performed on each lot of packages procured. Groups C and D inspections (except for subgroup I, seal test) of M IL-STD-883, method 5008, are not required unless specified by contract or purchase order. Burr-Brown periodically performs groups C and D inspections of MIL-STD-883, method 5008. A report of the most recent groups C and D inspections is available from Burr-Brown. 4.4.1 Group A inspection. Group A inspection consists ofthe test subgroups and LTPD values shown in M I L-STD-883, method 5008, Table I, and .as follows: a. Testsare specified in Table II herein. b. Tests previously performed as part of final electrical test need not be repeated. 4.4.2 Group B inspection. Group B inspection consists ofthe test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table II and as follows: a. Particle impact noise detection test is not required. 4.4.3 Group C il)spection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method 5008, Table III, and as follows: a. Operating life test (MIL-STD-883, ~ethod 1005) conditions: (I) Test condition B (2) Test circuit is Figure 6 herein (3) T A = 125°C minimum (4) Test duration is 1000 hours minimum b. End point electrical parameters are specified in Table 11 herein. c. Additional electrical subgroups are specified in Table II herein. 7-53 OPA600/MIL SERIES 4.4.4 Group D insp£ction. Group D inspection consists of the test subgroups and LTPD values shown in M IL-STD-883, method S008, Table IV, and as follows: a. Particle impact noise detection test is not required. 4.S Methods of examiIiation and test. Methods of examination and test are specified in the appropriate tables. Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883. 4.S.1 Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) are referenced to the external zero reference level of the supply voltage. Currents given are conventional current and positive when flowing into the referenced terminal. 4.6 !!!!p'ection of I!reparation for delivery. Inspection of preparation for delivery is in accordance with MIL-M-38SJO, except that the rough handling test does not apply. 5. PREPARATION FOR DELIVERY 5.1 Preservation-I!ackagi!!g and packing. Microcircuits are prepared for delivery in accordance with MIL-M-38SIO. 6. NOTES 6.1 Notes. The notes specified in MIL-M-38SIO are applicable to this specification. 6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of screened parts is desirable. 6.3 Ordering data. The contract or order should specify the following: a. Complete part number (see paragraph 1.2) b. Requirement for certificate of compliance, if desired. 6.4 Microcircuit g!:Q!!p assig~. These mircocircuits are assigned to Technology Group F as defined in MIL-M38SIO, Appendix E. 6.S Electrostatic sensitivity. These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive precautions should be observed at all times. 7. ELECTRICAL PERFORMANCE CURVES '(Typical at TA = +25"C and ±Vcc = 15VDC. unless otherwise specified I. COMPENSATION AND SLEW RATE VS GAIN BODE PLOT 10 700 600 ~ ~ \ , 500~ SLEW RATE ""," . J!I .J( 400 a: ~ (/J "' 300 COMPENSATION "+-I.lll 10 Clo~-Ioop SETTLING TIME 200.-.....;V.;;S..;O;..;U;.;T_P.;;U.;.T..;.V.;;O.;;LT..;A.;.G;;;E;;.C.;.H;.;,A,.;;N.;.G.;.E~., 3OOr-__~S.;.ETT~L.;.IN.;.G.;..;.TI.;.M..;E;,;V,,;SrG.;.A..;I..;N____~ Il.V=20V G= 1V1V _150t----+----+--.....,f----l 1200J----+------,~~---,~y ~ ~ 150t----~~~~~~~~ I SETTLING TIME AND SLEW RATE VS TEMPERATURE 1.2 250r-·------r-------+---. .~~ ! 20n 100 Gain (VIVI = 1 + RF/RIN TS(0.01~1 , 1.1 ~ !100t----b~~_+--- Ts ~ ...... r ~ 100J:::::;;""-'T"::oiiI"'''--t---...,~ 501r-----~~~r-----r_---; 0.9 ~ ~~ ~ / I '~ 50~~----r-------+-------~ o ..1----1~0~----:"100~---1~000 Closed-loop Gain (VIVI = 1 + RF/RIN 0 '----:5r--~1*0~---:'11;o5--~20 0'~75 Output Voltage Change (VI 7-54 -SO -25 o +25 +50.+75 +100+125 Temperature (OC) OPA600jMIL SERIES 30 OUTPUT VOLTAGE VS OUTPUT CURRENT 1.2 OPEN-LOOP GAIN AND QUIESCENT CURRENT VS TEMPERATURE BANDWIDTH 1.4 G=-10VN 25 w20 N' '0 > 15 :; Q. :; 0,0 a 1.2 1.1 :> "- ........ " :> -- 'iii > ~1.0 Vee Vee 50 -- 15 +12 100 150 200 250 iii 'iii II: 10 10 .... ~~ ~ 300 0'~75 "- '" -50 -25 , A~ - 0.9 Output Current (mAl a a O. B 6 +25 +50 +75 +100 +125 0'_75 -50 Temperature (Oel -25 0 "" "- ~ f" +25 +50 +75 +100 +125 Temperature (OC) 8. APPLICATIONS INFORMATION 8. I Wiring_precautions. The OPA600 is a wideband, high frequency operational amplifier with a gain-bandwidth product exceeding 5GHz. This capability can be realized by observing a few wiring precautions and using high frequency layout techniques. Of all the wiring precautions, grounding is the most important and is described in detail in the next section. In general, all printed circuit board conductors should be wide to provide low resistl1nce, low impedance signal paths and should be as short as possible. The entire physical circuit should be as small as is practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the input terminals of the amplifier and compensation pins. Stray signal coupling from the output to the input should be minimized. All circuit element leads should be as short as possible and low values of resistance should be used. This will give the best circuit performance as it will minimize the time constants formed with the circuit capacitances and will eliminate stray, unwanted tuned circuits. 8.2 Grounding. Grounding is the most important applications consideration for the OP A600. as it is with all high frequency circuits. Ultra-high frequency transistors are used in the design of the OPA600 and oscillations at frequencies of 500M Hz and above can be stimulated if good grounding techniques are not used. A ground plane is highly recommended. It should connect all areas of the pattern side of the printed circuit that are not otherwise used. The ground plane provides a low resistance, low inductance common return path for all signal and power returns. The ground plane also reduces stray signal pickup. It eliminates parasitic circuits from what would otherwise be long, component leads. Point-to-point wiring is not recommended. However, if point-to-point wiring is used, a single-point ground should be used. The input signal return, the load signal return and the power supply common should all be connected at the same physical point. This eliminates common current paths or ground loops which can cause unwanted feedback. Each power supply lead should be bypassed to ground as near as possible to the amplifier pins. A IJ-IF CS 13 tantalum capacitor is recommended. A parallel 0.0 IJ-IF ceramic may be added if desired. This is especially important when driving high current loads. Properly bypassed and modulation free power supply lines allow full amplifier output and optimum settling time performance. OPA600 circuit common is connected to pins I and 13; these pins should be connected to the ground plane. The input signal return, load return, and power supply common should also be connected to the ground plane. The case of the OP A600 is internally connected to circuit common, and as indicated above, pins I and 13 should be connected to the ground plane. Ideally, the case should be mechanically connected to the ground plane for good thermal transfer but because this is difficult in practice, the OPA600 should be fully i,nserted into the printed circuit board with the case very close to the ground plane to make the best possible thermal connection. If the case and ground plane are physically connected or are in close thermal proximity, the ground plane will provide heat sinking which will reduce the case temperature rise. The minimum OPA600 pin length will minimize lead inductance, thereby maximizing performance. To repeat, proper grounding is the single most important aspect of high frequency circuitry. 8.3 Compensation. The OPA600 uses external frequency compensation so that the user may optimize the bandwidth or settling time for his particular application. Several performance curves aid in the selection of the correct compensations capacitance value. The Bode plot shows amplitude and phase versus frequency for several values of compensation. A 7-55 OPA600/ ¥IL SERIES related curve shows the recommended compensation capacitanc,e versus closed-loop gain. Figure 4 shows a recommended circuit schematic. Compo~ent values and compensation for amplifiers with several different closed-loop gains are shown. This circuit will yield the specified settling time. Because each device is unique and slightly different, as is each user's circuit, optimum settling time will be 100 ~ 50 t: '"0 os en" ..J 25 50 Compensation Capacitance' pFl FIGURE 7. Capacitive Load Compensation and Response. 8.7 Offset voltage adjustment. The offset voltage of the OPA600 may be adjusted to zero by connecting a Sko. resistor in series with a 10ko.linear potentiometer in series with another Sko. resistor between pins 2 and IS, as shown in Figure 3. It is important that one end of each of the two resistors be located very close to pins 2 and IS to isolate and avoid loading these sensitive terminals. The potentiometer should be a small, noninductive type with the wiper connected to the positive supply. The leads connecting these components should be short, no longer than O.S-inch, to avoid stray capacitance and stray signal pick-up. If the potentiometer must be located away from the immediate vicinity of the OP A600, extreme care must be observed with the sensitive leads. Locate the two Sko. resistors very close to pins 2 and IS. Never connect +Vce directly to pin 2 or IS. Do not attempt to eliminate the 5ko. resistors because at extreme rotation, the potentiometer will directly connect +Vcc to pin 2 or pin 15 and permanent damage will result. Offset voltage adjustment is optional. The potentiometer and two resistors are omitted when the offset voltage is considered sufficiently low for the particular application. For each microvolt of offset voltage adjusted, the offset voltage temperature sensitivity will change by ±O.004/ot V j"c. 8.8 Current boost. External ability to bypass the internal current limiting resistors has been provided in the OP This is referred to as current boost. Current boost enables the OPA600 to deliver large currents into heavy (±200mA at±IOV). To bypass the resistors and activate the current boost, connect pin 7 to -Vee at pin6 with a short to minimize lead inductance and connect pin 9 to +Vcc at pin 12 with a short lead. CAUTION - Activating current boost by bypassing the internal current limiting resistors can permanently damage OPA600 under fault conditions. See paragraph 8.9. Not activating current boost is especially useful for initial breadboarding. The 500. (±S%) current limiting resistor in the collector circuit of each of the output transistors causes the output transistors' to saturate; this limits the power dissipation in the output stage in case of a fault. Operating with the current boost not activated may also be desirable with small-signal outputs (i.e.±IV) or when the load current is small. Each resistor is internally capacitively-bypassed (0.0 I/otF, ±20%) to allow the amplifier to deliver large pulses of current. such as to charge diode junctions or circuit capacitances and still respond quickly. The length of time that the OPA600 can deliver these current pulses is limited by the RC time constant. The internal voltage drops, output voltage available, power dissipation, and maximum output current can be determined for the user's application by knowing the load resistance and computing: V - 14 ( RWAlJ ) OUT 50 + RWAlJ This applies for RWAlJ less than 1000. and the current boost not activated. When RWAD is large, the peak output voltage is typically ±IIV, which is determined by other factors within the OPA600. 8.9 Short circuit p'rotection. The OPA600 is a short-circuit-protected for momentary short to common «Ssec), typical of those encountered when probing a circuit during experimental breadboarding or troubleshooting. This is true only if pins 7 and 9 are open (current boost not activated). An internal son resistor is in series with the collector of each of the output transistors which under fault conditions will cause the output transistors to saturate and limit the power dissipation in the output stage. Extended application of an output short can damage the amplifier due to excessive power dissipation. The OPA600 is not short-circuit-protected when the current boost is activated. The large output current capability of the OPA600 will cause excessive power dissipation and permanent damage will result even for momentary shorts to ground. Output shorts to either supply will generally destroy the OPA600 whether the current boost is activated or not. 7-57 OPA600/MIL SERIES 8.10 Heat sinking and power dissipation. The OPA600 is intended as a printed circuit board mounted device and as such, does not require a heat sink. It is specified for ambienttemperature operation from _55°C to +125°C. However, the power dissipation must be .kept within safe limits. At extreme temperature and under full load conditions, some form of heat sinking will be necessary. The use of a heat sink, or other heat dissipating means such as proximity to the ground plane. will result in cooler operating temperatures, better temperature performance, and improved reliability. The thermal model used to describe the OPA600 is more complete than is usual for operational amplifiers. The thermal resistances for the output stages have been separated from the thermal resistrance for the balance of the OPA600. For most monolithic op amps and hybrids, thermal properties are usually represented by one thermal resistance, 8JC; and in general, that is fairly accurate because the total power dissipation is low and the heat that is generated is in one area. For packaged power transistors, thermal properties are also accurately represented by one thermal resistance, OJC; all the power is dissipated in one point source. The OPA600 op amp however, has a large power handling capability and large power dissipations occur in different locations within the amplifier under differing load conditions. The total power dissipation within the OP A600 is the sum of all the individual sources of dissipation. By making some simplifying assumptions and neglecting second order effects, the dissipations are grouped into three sources'- qUiescent power, NPN output transistor power, and PNP output transistor power. Using the thermal model shown in Figure 8 and the absolute maximum junction temperature rating (derate the maximum, if desired) and solving the Thevenin equivalent simultaneous equations that result, the user can determine junction, internal substrate, and case temperatures. It will be apparent that the output stages contribute significantly to the thermal rise. Under light loading, the requirements to dissipate the generated heat are much less than the requirements to dissipate heat under full load conditions at a maximum temperature. Using this expanded thermal information allows the user to safely apply the OPA600. 84= lZOC/W 81 =3ZOC/W TJN r~ I 1 Jp T 85=1.7oc/W ~:~~ JQ T I 11& =35a C/w ,v-. II 1I TA TC TIN = Junction temperature of NPN output transistor. TIP = Junction temperature of PNP output transistor. TIQ = Worst case temperature of any device in the balance of the amplifier. Tc = Case temperature. T A = Ambient temperature. 0,,02 = Thermal resistance, output transistors. 83, O. = Thermal resistance, substrate. "8 5 = Thermal resistance, substrate attach and package. = Thermal resistance, case to ambient. 86 PN = Worst case power dissipation in the NPN output transistor. Pp = Worst case power dissipation in the PNP output transistor. Po = Quiescent power dissipation. FIGURE 8. OPA600 Thermal Model. Below are two examples of using the thermal model. I. Find the worst case internal junction temperature rise above ambient. Conditions: Po = J W PN= Pp=O.1 W no heatsink 7-58 OPA600/MIL SERIES TJN = 80.7PN+ 48.7Pp + 36.7PQ + TA TJN - T A= 49.6°C as PN= Pp TIP - T A= 49.6°C TIQ = 49.6PQ + 36.7PN + 36.7Pp + TA TIQ - T A= 57"C Answer: 57°C 2. Find the maximum output stage power dissipation allowed with a maximum case temperature of + 125°C and not exceeding the maximum junction temperature of + I75"C. Conditions: PQ= I Watt PN = Pp Solution: 12 Solution: 97". TIN = PN 32 + (PN+ Pp)12 + (PN 175 = 59.4 PN + 1.7 + 125 PN= 0.8I3W Checking TIQ: Answer: + Pp) 1.7 1.7 + Po 1.7 + Tc TIQ = (I) 12.9 + (2x 0.813 + I) 1.7 + 125 TIQ = 142"C (i.e. < 175°C) 0.813W may be dissipated in each output transistor. It may be necessary to physically connect the OPA600 to the printed circuit board ground plane, attach fins, tabs, etc., to dissipate the generated heat. Because ofthe wide variety of possibilities, this task is ieftto the user. For all applications it is recommended that the OPA600 be fully inserted into the printed circuit board and that the pin length be short. Heat will be dissipated through the ground plane and the AC performance will be its best. See paragraphs 8.1 and 8.2 8. I I Testing. For static and low frequency dynamic measurements, the OPA600 may be tested in conventional operational amplifier test circuits, provided proper grounding techniques are observed, excessive lead lengths are avoided, and care is maintained to avoid parasi~ic oscillations. See the above sections, especially paragraphs 8. I and 8.2. The circuit in Figure 9 is recommended for low frequency functional testing, incoming inspection, etc. This circuit is less susceptible to stray capacitance, excessive lead length, parasitic tuned circuits, changing capacitive loads, etc. It does not yield optimum settling time. We recommend placing a resistor (approximately 3000) in series with each piece of test equipment, such as a DVM, to isolate loading effects on the OPA600. To realize the full performance capabilities of the OPA600, high frequency techniques must be employed and the test fixture must not limit the amplifier. Settling time is the most critical dynamic test and Figure 10 shows a recommended OPA600 settling time test circuit schematic. Good grounding, truly square drive signals, minimum stray coupling, and small physical size are important. The input pulse generator must have a flat topped, fast settling pulse to measure the true settling time of the amplifier. A circuit that generates a ±5V flat topped pulse is shown in Figure II. Every OPA600 is thoroughly tested prior to shipment assuring the user that all parameters equal or exceed their specifications. FIGURE 9. Amplifier Circuit for Increased Stability. 7-59 OPA600/ MIL SERIES (21 HP2835 +15VDC (¥, *SIgn + ,619n ..L ... INPUT = ±5V OUTPUT = ±5V ERROR OUTPUT +1I.5mV (±O.ol'lo) *O.D2n MATCHED ·15VDC ·15VDC FIGURE 10. Settling Time and Slew Rate Test Circuit. +15VDC +15VDC IN4148 +15VDC 640n 15U 640u r' 1/2W IOD.F 220ll INPUT =TTL OUTPUT = ·5V °ALT2N3906 2N2!I07 +15VDC '15VDC~ IOD.F 1511 ·15VDC FIGURE II. Flat Top Pulse Generator. S.12 Increased Slew Rate. The OPA600 slew rate may be increased by using an alternate compensation shown in Figure 9. The slew rate will increase between 700 and SOOV / J.lsec typical with 0.0 I% settling time increasing to between 175 and 190nsec typical and 0.1% settling time increasing to between 110 and 120nsec typical. For alternate doublet compensation refer to Figure 9. For a closed-loop gain equal- I, delete C I and C2 and add a series RC circuit (R = 220, C = 0.00 IJ.I F) between pins 14 and 4. Make no connections to pins II and 5. Absolutely minimize the capacitance to these pins. If a connector is used for the OPA600, it is recommended that sockets for pins II and 5 be removed. For a PC board mount, it is recommended that the PC board holes be overdrilled for pins II and 5 and adjacent ground plane copper be removed. Effectively this compensation places the dominant pole at the input stage, allowing the output stage to have no compensation and to slew as fast as possible. Bandwidth and settling time are impaired only slightly. For closed-loop gains other than -I, different values of Rand C may be required. 7;'60 BURR-BROWN® VFC32/MIL SERIES IElElI MODEL NUMBERS: VFC32WM/883B VFC32WM VFC32UM/883B VFC32UM VFC32VM/MIL VFC32VM/883B VFC32VM REVISION NONE OCTOBER, 1981 VOL TAGE-TO-FREQUENCYCONVERTER FEATURES • HIGH LINEARITY ±o.o06% max 113 bits) and ±O.OI% max 112 blt*) it 10kHzFS ±O.05% max at 100kHz FS ±O.2% mix at 0.5MHz FS • HI·REL MANUFACTURE • 6-DECADE DYNAMIC RANGE • OUTPUlDTl/TIL/CMOS COMPATIBLE .V/F OR F/V CONVERSION DESCRIPTION The VFC32 monolithic vo!tage-toCfrequency and frequency-to-voltage converter provides a simple. low cost method of converting analog signals into digital pul~es. The digital output is an open collector and the digital pulse train repetition rate is proportional to the amplitude of the analog input voltage. Output pulses are compatible with DTt. TTL. and CMOS logic families. The converter requires two external resistors and two external capacitors to operate. One external resistor and one external capacitor set up the full scale frequency. with a guaranteed nonlinearity of ±0.2';i maximum at 500kHz. The other capacitor is the oneshot capacitor; for best performance it should have a low temperature coefficient. The other resistor is a noncritical open collector pull-up resistor. The VFC32/ MIL Series converter is available in three electrical performance grades. The V grade has 200kHz specifications and tests. The W grade has premium linearity, ±0.006% of FSR, and premium full scale accuracy temperature coefficient of lOOppm/"C. The U grade is specified from -25°C to +85°C and from -55°C to + 125°C. It is primarily for high performance test equipment, shipboard, ground support and industrial applications, where operation is normally between _25°C and +85°C and full temperature operation must be assured. All are packaged in welded, hermetically-sealed, TO-IOO cans. All devices are manufactured on a separate Hi-Rei manufacturing line with impeccable clean room conditions to assure "built-in" quality. Three product assurance levels are available: standard, /883B, and / MIL. The standard models have many MIL-STD-883 screens performed routinely. The /883 suffixed device.s are 100% screened per MIL-STD-883 method 5004 class B and each / MIL suffixed device is Hi.Rel manufactured, 100% screened per MIL-STD-883 method 5004 class B, and has 10% PDA. Quality assurance further processes / MIL devices, performing group A and B inspections on each inspection· lot and group C and D inspections periodically and when specified on the customer's purchase order. A report containing the most recent group A, B, C, and D tests is available for a nominal charge. Inlernatlonal Airport Induslrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746-1111 . Twx: 910-952·1111· Cabl,: BBRCORp· Telex: 66·6491 I'I>S-44Y 7-61 VI02 MIL SERIES DETAILED SPECIFICATION .MICROCIRCUITS, LINEAR VOLTAGE-TO-FREQUENCY CO""VERTER MONOLITHIC, SILICON I. SCOPE 1.1 Scop.!.: This specification covers the detail requirements for a very linear. voltage-to-frequency conn:rter. For the descripiion of operation see paragraph 3.3.3. 1.2 Part Number. The complete part number' is as shown below. VFQ2 T 8asic model number V ~ M MIL Metal package Hi-Rei product designator (see 1.2.2) T l Grade (see 1.2.1) 1.2.1 Device typ.!.: The device is a single. voltage-to-frequency converter; it will also function as a single. frequency-tovoltage converter. Three electrical performance grades are provided. The V grade features specifications and tests at 200kHz. The W grade features premium linearity(13 bits) and premium full scale accuracy. The U grade features specified and tested performance from -25°C to +85°C and maintains -55°C to +125°C operation. Electrical specifications are shown in Table I. Electrical tests are shown in Tables II and III. 1.2.2 Device class. The device class is similar to the product assurance level class 8. as defined in M IL-M-38SI O. The Hi-Rei product designator portion of the part number distinguishes the product assurance level as follows: Hi-Rei Product Designator /MIL /8838 (none) Re~uirements Standard model, plus 100% MIL-STD-883 class 8 screening, with 10% PDA, plus quality conformance inspection (QCI) consisting of Groups A and 8 performed on each inspection lot, plus Groups C and D performed initially and periodically thereafter. Standard model. plus I()(y;; M IL-STD-883 class. 8 screening. Standard model including 100% electrical testing. 1.2.3. Case outline. The case outline is A~2 (lO-lead can, TO-loo) as defined in MIL-M-38510, Appendix C. The case is metal and is conductive. 1.2.4 Absolute maximum rating~ Supply voltage range Input voltage range. +input. pin I Input voltage range. -input. pin 2 Output pull-up supply voltage (V pt ,) Output sink current, pin 6 Comparator input voltage Output current pin 10 Storage temperature range Lead temperature (soldering. 6Osec) Junction temperature JJ .1J The absolute maximum input voltage is ClIual to the supply vultage . V,.l is the supply voltage conm..-cted to pin (, viii R~. sec Figure 2. 7-62 ±22VDC ±22VDCJj ±22VDC ±22VDCJ11.1 16mA ±22VDCJj ±20mA -65"C to +ISO"C 3OO"C TJ= 17S"C .u VFC32 MIL SERIES 1.2.5 Recommended ofJerating conditions. Supply voltage range Output pull-up supply (V,.,) Input voltage range, (V,~) ±IIVDC to ±20VDC +4.5VDC to +20VDC OVDC to +[0.00025 x (R, + Rd]VDC.1l11 -IOVDC to OVDC 11 OmA to +0.25mA OmA to +0.50mA 11 lOOkHl :J -55"C to + 125"C Input current range, pin 2 Full scale freq uency Ambient temperature range 1.2.6 Power and thermal characteristics. Package Case outline 10-lead can (TO-IOO) A-2 Maximum allowable power dissipation 225mW at T, = 125"C Maximum fJ J-C 70"C W Maximum fJ C-A 150"C W Maximum /lJ-A 220"C W 2. APPl.lC ABLE DOCU MENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICATION MIl.lTARY MIL-M-38510 - Microcircuits, general specification for. STANDARD MILITARY M IL-STD-883 - Test methods and procedures for microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to assure successful compliance with this specification. 3.1.1. Detail sfJecifications. The individual item requirements are specified herein. In the clent of conflicting requirements, the order of precedence will be the purchasc ordcr, this specification, and thcn the rcfercnce documcnh. 3.1.2 Country of manufacture. These microcircuits are manufactured, assemblcd, and tested within the United States of America. 3.2 Design, construction, and pj)ysical dimensions. 3.2.1 Package, metals, and other materials. The package is in accordance with paragraph 3.5.1 of M 11.-M-3X51O. I hc exteri;;;:-;:;;;;tal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in MIL-M-3851O. 3.2.2 Design documentation. The design documentation is in accordance with M II.-M-38510. 3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with M II.-M-38510. 3.2.4. Lead material and finish. The lead material is kovar type (type A). The lead finish is gold plate with nickel underplating. The lead material and finish is in accordance with MIL-M-38510 and is solderable per MIL-STD-883, method 2003. 3.2.5 Glassivation. The microcircuit die is glassivated. 3.2.6 Die thickness. The die thickness is in accordance with M I L-M-38510. 3.2.7 ~ysical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.8 Circuit diagram and terminal connections. The circuit diagram and terminal connections arc shown in Figure I. 3.2.9 Schematic circuit. The functional schematic circuit is shown in Figure I. 3.3 Electrical ~rformancecharacteristics. The electrical performance characteristics are as specified in Table I and apply over the full operating ambient temperature range of -55"C to + I 25"C, unless otherwise specified. 3.3.1 Additional electrical fJerformance characteristics. Electrical performill1ce ~urves are shown within paragraph 7. 3.3.2 Connection diagram. The connection diagrams for voltage-to-frcquency operation are shown in Figures 2 and 3. The connection diagram for frequency-to-voltage operation is shown in Figure 4. 11 JJ For positive input mltages (st.'C Figure 2). For frequencies lookHl to SOOkHl 5{)1':; duty cycle is recommended (scc pYP'ass cap'acitors. Each power supply should be bypassed to ground as close as possible to the converter with O.OIIlF capacitors. 3.3.5. Offset and ~in error null. The VFC is capable of being nulled to zero offset and zero gain error using the circuits shown in Figures 2. 3. and 4. R, effects zero offset error; RJ effects zero gain error. The offset and gain error null adjustment procedure is: a. Apply an input voltage that should produce an output frequency of 0.001 of full scale. b. Adjust Rs for 0.001 of full scale frequency. c. Apply full scale input voltage . .! d. Adjust R3 for full scale frequency. e. Repeat steps a through e. If nulling is unnecessary for the application, delete R. and R" and replace R3 with a short circuit. 3.4 Electrical Tests. Electrical test requirements are as specified in Table II. The subgroups of Table III and limits of Table IV. which constitute the minimum electrical tests for screening, qualification, and quality conformance. are shown in Table'll. 3.5 Marking, Marking is in accordance with MlL-M-38510. The following marking is placed on each microcircuit as a minimum. a. Part number (see paragraph 1.2). b. Inspection lot identification code ..Y c. Manufacturer's identification ( _0). d. Manufacturer's designating symbol (CEBS). e. Country of origin (U.S.A.). 3.6 Workmanshil'. These microcircuits are manufactured. processed. and tested in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices. workmanship instructions. inspection and test procedures. and training. prepared in fulfillment of Burr-Brown's product assurance program. 3.6.1 Rework p'rovisions. Rework provisions for / MIL and 1883B Hi~Rel product designations. including rebonding. are in accordance with MIL-M-38510. 3.7 Traceability. Traceability is in accordance with MIL-M-385 10. Each microcircuit is traceable to the production lot and to the component vendor's component lot. Reworked or repaired microcircuits maintain traceability. 3.8 Product and p'rocess change. Burr-Brown will not implement any major change to the design, materials. construction, configuration, or manufacturi;g process which may affect the performance, quality, reliability or interchangeability of the microcircuit without full or partial requalification. 3.9 Screenin& Screening, for 1MIL and 1883B Hi-Rei product designations, is in accordance with MIL-STD-883. method 5004, class B. except as modified in paragraph 4.3. For the standard model, Hi-Rei product designation (none), routine manufacturing processing includes Burr-Brown internal visual inspection, stabilization bake, fine leak, gross leak, constant acceleration, and external visual inspection per MIL-STD-883, method 5004, class B. For the / MIL Hi-Rei product designation. all microcircuits will have passed the screening requirements prior to qualification or quality conformance inspection. 3.10 Qualification. Qualification is not required. See paragraph 4.2 herein. 3.11 Quality conformance inspection. Quality conformance inspection, for the 1MIL Hi-Rei product designation. is in accordance with MIL-M-38510, except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed quality conformance inspection prior to mircocircuit delivery. NOTE: For optimum linearity it is recommended that gain error nulling be performed at 9()li( of full scale frequency rather than at ..!J 1.' A four-digit date code. indicating year and week of seal. is marked on 8838 and (none) Fli·Rel product designatioru;. 7-67 ({)()l't of full scale frequency. VFC32/ MIL SERIES TABLE I. Electrical Performance Characteristics = -55°C.to +1250C, ±Vcc = 15VDC, unless otherwise specified. All characteristics TA VFC32 V GRADE CHARACTERISTICS CONDITIONS I MIN I TYP I VFC32'w GRADE MAX I !olIN I TYP I VFC32 U GRADE MAX I MIN TYP I MAX I UNITS INPUT (V/F CONVERTER) Bias current Inverting input Noninverting input Offset \loltage jJ Differential impedance TA == +25OC 330 1110 10 50 1 850 1110 300 113 500 113 50 1110 1501110 TA",,+25°C TA = +25°C TA=+25°C Common~mode impedance 40 100 4 nA nA mV kllll pF Mil II pF INPUT (F/V CONVERTER) TA =+2SOC Impedance logic "'" Logic''Q'' Pulse-width range "" Ii pF V +1.0 +Vcc -Vee -0.8 0.1 150klFMAX #lsec ACCURACY Linearity error 11 r~<- fraq" 10kHz . to.a03 ±0.006 to.Ol0 'to.OO5 Ofoof FSR~ :to.005 ±0.010,.¥ :to.025 :to.05O % of FSR :to.05O :to.2OO %ot FSR 10kHzE; oper TA = +25°C fraq.s;;; 100kHz lookHz"E;; oper freq ,s;;; 500kHz Offset error I input offset voltage I Jj Offseldrift.21 TA =+25°C -250 C.lo +85°C -55°C to +125°C Gain error JJ ±4 ±3 TA =+25°C f= 10kHz -2SOC to +85°C Gaindrifl..§l f= 10kHz ±3 ±100 ±100 ±2OO -2SOC to +250C +2SOC to +85°C -5SOC to +25°C +250C to +125°C f = 200kHz -5SOC to +250C +250C 10 +125°C f =10kHz 0 :to.03O :to.04O ISINK =8mA 0.2 0.4 = 0.01 f - DC. ±Vcc ~ 12VDC to 18VDC OUTPUT (V/F CONVERTER) (_" ._lOr outpul) Voltage. logic ''0'' Leakage current. logk: "1" Voltage. logiC "1" -200 +100 +200 0 ±150 Power supply sensitivity t. mV ppm of FSRfOC ppm of FSA/oC ±150 %01 FSR ppmfOC ,ppmfOC 10 -5SOC to +;2SOC f= 10kHz Full scale drift 10ff18t drift & gain driftl§/§/ t3 -100 -50 +50 -400 -200 Vo 15V External pull-up resistor required IS88 Figure 21 -100 0 -100 0 -50 +25 -50 +50 t300 ppm ppm ppm ppm ppm ppm +50 -150 -50 -300 -100 tl00 0 +100 +150 +100 +300 lOUT "" SmA, Q.OAD "" SOOpF FSR/oC FSA/oC FSRfOC FSRfOC FSRfOC FSR/oC %0' FSR/% 1.0 .A VPU V 400 nsec 1 100 mA II pF sec O.2S/FMAX Pulse width Fall time of of of of of of OUTPUT (F/V CONVER1ER) 10 =7mA VO =7VDC Closed lOOp Without oscillation Voltage Current Impedance Capacitive load Oto+l0. +10 DYNAMIC RE8PONSE Full scale frequency Dynamic range Settling time kHz decades 500 8 I Vlf I Overload recovery to s~ecifi.ed linearity .1VIN = IOV <50% overload JI .11 POWER 8UPPL Y Quiescent current I TA =·+25°C I ::t4.5 ±8.0 I I I I I mA TEMPERATURE RAHGE ..m ....nI) Operating Storage -55 -65 +125 +150 °C °C 'Specification the .ame as V grade. NOTES: Adjustable to zero. See paragraph 3.3.5. Linearity error is specified at any operating frequency from the straight line intersecting 90'111 of full scale frequency and 0.1'111 of full scale frequency. See paragraph 7. :y ±O.015'111 of FSR for negal/ve inputs. ~ FSR = Full Scale Range (corresponds to full scale frequency and full scale input voltage). §J Exclusive of external components' drift. §/ Positive drift is defined to be increasing frequency with increaSing temperature. 1/ One pulse of new frequency plus 1je. The device is a single. operational amplifier. Two electrical performance grades arc provided. the R g~de and the U grade. with the R grade offering the higher electrical performance. 1.2.2 Device class. The device class is similar to the product assurance level class B. as defined in MIL-M-38510. Grade (see 1.2.1) The Hi-Rei product designator portion of the part number distinquishes the product assurance level as follows. Hi-Rei product designator Requirements Basic model. plus 100% M I L-STD-883 class B screening with 10(;,( I)DA. plus quality conformance inspection (QCI) consisting of Groups A and B on each inspection lot. plus Groups C and D performed initially and periodically thereafter. 1883B Basic model. plus 100lli, M I L-ST D-883 class B screening. 1.2.3 Case outline. The case outline (8-lead can) is as defined i:1 Figure 4. The case is metal and is conductive. IMIL 1.2.4 Absolute maximum rating!!: Supply voltage range Input voltage range Differential input voltage range Storage temperature range Output short-eircuit duration Lead temperature (soldering. 6Osec) Junction temperature ±20VDC ±20VDC lJ ±40VDC lJ -65"C to + 150"C Unlimited 11 300"C TJ = 175"C 1.2.5 Recommended o(>erating conditions. Supply voltage range _ _ _ _ _ _ _ ±3VDC to ±20VDC Ambient temperature range -55"C to + I 25"C' 1.2.6 Power and thermal characteristics. Case outline Maximum allowable power dissipation Maximum Package 8-lead can FIGURE4 225mW at T, = 125"C' 70"(' W J-C Maximum (J C-A 220"(' W i!oo CqUi11 tn thl' ~upl"ly mhilgc. Shurt circuit may he In ground unly. Rutin!! i1pplic~ tn + 1.'5"(" t,;U.'C h.'mrcmlun: or +50"(' umhiclll tCl1lfll'raturl' al ! 15\' 1)(' ,upl"l) \ultagl', Jj The absolute maximum input voltage lJ (J 7-74 3500/MIL SERIES 2. APPLICABLE DOCUMENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICATION MILITARY MIL-M-3851O - Microcircuits. general specification for. STANDARD MILITARY MIL-STD-883 - Test methods and procedures for microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurancc program adequate to assure successful compliance with. this specification. 3.1.1 Detail sllecifications. The individual item requirements are specified herein. In the event of conflicting requirements the order of precedence will be the purchase order. this specification. and then the reference documents. 3.1.2 Country of manufacture. These microcircuits are manufactured. assembled. and tcstcd within the lJ nited States of America. 3.2 Design. construction. and p.!:!ysical dimensions. 3.2.1 Package. metals. and other materials. The package is in accordance with paragraph 3.5.1 of M IL-M-38510. The exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in MIL-M-38510. 3.2.2 Design documentation. The design documentation is in accordance with MIL-M-38510, 3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with MIL-M-38510. 3.2.4 Lead material and finish. The lead finish is gold plate. The lead material and finish is soldcrable per M I L-STD-883. method 2003. 3.2.5 Glassivation. The microcircuit die is glassivated. 3.2.6 Die thickness. The die thickness is in accordance with MIL-M-38510. 3.2.7 Ph},sical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.8 Circuit diagram and terminal connections. The circuit diagram and terminal connections are shown in Figure I. N.C. N.C. = No Internal Connection. external connection permiued. OFFSET -IN OUTPUT OFFSET NUll -Voc(CASE) 8-lEAD CAN (TOP VIEW) FIGURE I. Terminal Connections. 7-75 3500 MILSERIES. FIGURE 2. Schematic Circuit. 3.3 Electrical performance characteristics. The electrical performance characteristics arc as specified in Table I and apply over the full operating ambient temperature range of -5S"C to + 12S"C. unless otherwise specified. 3.3.1 Additional electrical performance characteristics. Electrical performance curves are shown in paragraph 7. 3.3.2 Offset and gain error null. The amplifier is capable of being nulled to zero offset voltage using the circuit in Figure 2. If nulling is unnecessary for the application. delete the potentiometer and make no connections. +Vn: OUTPUT 111t:::::j:;:==== OfFSET NULL FIGURE 2. Offset Null Circuit. 3.3.3 Freq~y compensation. No frequency compensation is required. The amplifier is free of oscillation when operated at any gain and when operated in any test conditi(lJ1 specified herein. 3.4 Electrical tests. Electrical tests are shown in Table III. The sub-groups of Table III and limits of Table IV. which constitute the minimum electrical tests for screening. qualification. and quality conformance. arc shown in Table II. 3.S Marking, Marking is in accordance with M I L-M-38SIO. The following marking is placed on each micfllciruit a, a minimum. a. Part number (see paragraph 1.2) b. Inspection lot identification code! c. Manufacturer's identification (rLBi"') d. Manufacturer's designating symbol (CEBS) e. Country of origin (U.S.A) 3.6 Workmanship...: These microcircuits are manufactured. processed. and testcd in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices, workmanship instructions. inspection and te,t procedures, and training. prepared in fulfillment of Burr-Brown's product assumnce program. 3.6.1 ~work provisions. Rework provisions for the MIL Hi-Rei product designation. including rebonding. arc in accordance with MIL-M-3851O. 3.7 Traceability. Traceability is in accordance with MIL-M-38SIO. Each microcircuit is traceable to the production lot and to the component vendor's component lot. Reworked or repaired microcircuits maintain traceability. 3.8 Product and processchang~: Burr-Brown will not implement any major change to the design. matcrials. construction. configuration, or manufacturing process which may affect the performance. quality. reliability or interchungeubility of the microcircuit without full or partial requaliflcation. 3.9 Screening; Screening is in accordance with'M I L-STD-883. method S004. clllSS H. except as Illodified in paragraph 4 ..1 herein. For the IMIL Hi-Rei product designator. all microcircuits will have passed the screening requirelllents prior to qualification or quality conformance inspection. 3.10 Qualification. Qualification is not required. See paragraph 4.2 herein. 3.11 Quality conformance insl'ection. Quality conformance inspection furlhe MIl. H i-Rei product designation i, in accordance with MIL-M-3851O, except as modified in paragraph 4.4 herein. The microcircuit inspCL·tion lot will haw passed quality conformance inspection prior to microcircuit delivery. l! A four-digil data code. indicating year and wt.'Ck of seal. is makcd un IlUOU Hi~RL'1 7-76 prudUl't dl'~ign:lti()n~. 3500/MILSERIES TABLE I. Electrical Performance Characteristics. All characteristics at -wc" T. " + IWe::, tV"~"~ = I~V DC. un.... otherwi...pec...... 3SOOR/MIL 3SOOR/883B Characteristics I Conditions Symbol Min Typ ±IO ±IO ±12 I JIOOU/WB' Max I OUTPUT Vokase Current Vo Resistance Current. short circuit Ro RI.= Ikn RL= lUI L, T.=~"C L" To around Avs f= OH .. No load BW Unity pin ±IO 2 ±22 93 106 ·· · · · ··· · ONN-LOOP VOLTAGE GAIN DYNAMIC . ...oNII Bandwidth T.-~"C -WC" T ... +12~"C ilandwidth. full power Slew rate BW.,p T.=25·C SR T.=~"C I I.~ 0,7~ 1.2 25 1.2 10 0.6 0.4 -~~·C"T." +12~"C 2 INPUT Offset voltage Offset vottase temperature sensitivity .'lVoo/.'lT Bia. current Bias cumnt temperature sensitivity I. V(.·M 0 100 V(.·M PSRR Common-mode voltase ranae Common-mode rejection CMV CMR '" T ... +8~"C '" T ... +12~·C ~"C '" T ... +8~"C -~~"C '" T. '" +12~"C ~"C T. 0 -2~"C '" T ... +8~"C -~5·C"T." +125"C ollo./olT Power supply rejection -2~·C -~~·C T. T. URear operation Vn •• = ±IOV z. e. Noise. current i. ±~ ±IO +20 ±JO ±IO +1.5 ±JO T. = 2~"C 0.3Hz to 10Hz 10Hz to 10kHz 0.3Hz to 10Hz 10Hz to 10kHz .... = 2~·C TA=2S"C -~~·C '" T ... +12~"C Ditrerenlial T. Ie, ±II 90 80 ~·C T.=~"C I I ±2,~ I I TEMPERATURE RANGE C.........) Operati", Storage -~~ +12~ -6~ +150 ·· ·· · · ··· ·· I · -55 -6S ·SpeciflCations the same ill 3SOORj MIL. TABLE II. Electrical Test Requirements. (The individual tests within the subgroups appear in Table III.) lSOOR/Mll MIL·ITD-IUT_ ~CcIMa.) Interim electrical parameters (pre bum-inXmethod ~) ~) 3SOOR/88JB 3SOOU/88JB SUBGROUPS (.ee Table III) I I 1·.2.4.~.6 I. 2A.4.~. 6 Group A test requirements (method ~) I. 2.4.~. 6 GrouplC and o end point electrical parametcrs(method SOO~) - Table IV delta limits and limits Additional electricalsubsroups for &roup C inspections 7 Final electrical test parameters (methnd 'POA applies to ,uhsroup I (ICC 4.3d) 7-77 -- - Units V mA kll mA dB MHz MHz "kHz VIp.1CC V/p.tce · · Notes: ~ I · ·· · · · ··· mV p.V/"C p.VrC nA nArC nArC nA ±1.0 ±l.0 · 3 2 JOO 100 ±3.5 Max ±1.0 +3,0 +1.5 10' II 3 10'11 3 2 1.4 200 35 T.=~·C I I · · · · ±12 100 T.=~"C T.=~·C Typ ±20 +60 POWER IUPPLY Quiescent current I ±O.s ±O,7 ±40 ~"C Common mode Noilcvol.... ±2 -2~"C oll./olT Offset current Offset current temperature sensitivity Impedance T.-~·C Vn.1 = 0 VIO Min nArC nArC p.VIV V dB dB 1111 pF 1111 pF p.V.p-p pV.rms pA.p-p pA. rms ·· · I · · +12~ +150 I mA "c "c 3500/ MIL SERIES TABLE Ill. Group A Inspection Limits Subgroup Symbol M Il-STD-883 Conditions method or ±V('(,= ISV unless otherwise specified equivalent I T. ~ 2S"C 2 TA ~ +12S·C to TA ~ -SS"C 3SOOU/883B Min Units Max Vln 4001 ±S ±S I. 4001 ±30 ±30 nA lUI 4001 ±30 ±30 nA ±3.S mA ±3.S mV IQ 400S CMR 4003 .lV •• /.lT 4001 ±20 4001 ±J.S nArC 4001 ±J.S nArC .l1./.lT .l1 •• /.lT I VC:M =±IOV 90 90 dB ---pvre - 2A .1V 1o /.l-T 4001 ±20 pvrc H=+iS"C .lI,./.lT 4001 ±J.O nArC .l1,,/.lT 4001 ±J.O nArC 4 A", 4004 TA~2S"C SR 4002 S Avs 4004 f = OHz. no load SR 4002 G ~ +1 • .lV. ~ IOV. R, to - 3S00R/Mll 3S00R/883B Min Max TA~-2S"C TA~+12S"C f - OHz. no lmil 93 93 dB 0.6 0.6 V/P""" 93 93 dB ~ Itll 0.4 0.4 VIp"'" 93 93 dB ~ Ikll 0.4 0.4 VIp"", ~."-~., 6 Avs 4004 TA~-SS·C SR 4002 7 e, TA~ f=OHz. no load G 2S"C i, ~ +1 • .lV.~ IOV. R, 0.3Hz 1010Hz 3 pV.p-p 10Hz to 10kHz 2 IAV.rms OJHz 1010Hz JOO pA.p-p 10Hz 1010kHz 100 pA.rms TABLE IV. Groups C and D. End Point Electrical Parameters (T A = +25°C. ±Vcc = 15. VCM = OV) Test VIO 1.8 Limit ±5mV ±36nA Delta ±2.5mV ±30nA 4. PRODUCT ASSURANCE PROVISIONS 4. I Sam~Iing and ins~ection. Sampling and inspection procedures are in accordance with M IL-M-385 10 and M I L-STD-883. method 5005 except as modified herein. 4.2 Qualification. Qualification is not required unless specifically required by contract or purchase order. Burr-Brown has performed and successfully completed qualification inspection as described below. The q\lalification report is available from Burr-Brown. When so required. qualification will be in accordance with the inspection routine of M IL-M-385I O. paragraph 4.4.2.1. The inspections to be performed are those specified herein for groups A. B. C. and D inspections (see paragraphs 4.4.1. 4.4.2.4.4.3. and 4.4.4). 7-78 3500/ MIL SERIES 4.3 Screening~ Screening is in accordance with M IL-STD-883, method 5004, class B, and is conducted on all devices prior to qualification and quality conformance inspection. The following additional criteria apply: a. Constant acceleration test (MIL-STD-883, method 2001) is test condition D, VI axis only. b. Interim and final test parameters are specified in Table ILThe interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Burn-in test (MIL-STD-883, method 1015) conditions: (I) Test condition B (2) Test circuit is Figure 3 herein (3) T A= + I 25"C minimum (4) Test duration is 160 hours minimum d. Percent defective allowable (PDA). The PDA, for the / MIL Hi-Rei product designation Only, is 10 percent based on failures from group A, subgroup I test after cool-down as final electrical test in accordance with M I L-STD-883, method 5004, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from pre burn-in screening failures may be excluded from the PDA. If interim electrical parameter test prior to burn-in are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based on the PDA. e. External visual inspection need not include measurement of case and lead dimensions. FIGURE 3 Test Circuit. Burn-in and Oper.ating Life·Test. 4.4 Qualitx conformance insp'ection. Groups A and B inspections of M IL-STD-883, method 5005, are performed on each inspection lot. Groups C and D inspections of. M IL-STD-88J, method 5005, are not required unless specified by contract or purchase order. Burr-Brown periodically performs groups C and D inspections of MIL-STD-883, method 5005. A report of the most recent groups C and D inspections is available from Burr-Brown. 4.4.1 Group. A insp'ection. Group A inspection consists of the test subgroups and LTPD values shown in M IL-STD-883, method 5005, Table I, and as follows: a. Tests are specified in Table II herein. b. Tests previously performed as part of final electrical test need not be repeated. 4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in M I L-STD-883. method 5005, Table II (class B). 4.4.3 GrouP. C inspection. Group C inspection consists of the test subgroups and LTPD values shown in M IL-STD-883, method 5005, Table III, and as follows: a. Operating life test (M I L-STD-883, method 1005) conditions: (I) Test condition B (2) Test circuit is Figure 3 herein (3) TA = 125"C minimum (4) Test duration is 1000 hours minimum b. End point electrical parameters are specified in Table II herein. c. Additional electrical subgroups are specified in Table II herein. 7-79 3500;MILSERIES 4.4.4 Grou~ D ins~ection. Group D inspection consists of the test subgroups and LTPD values shown in M II.-STI>-810. method 5005, Table IV, and as follows: a. End point electrical parameters are specified in Table IV herein. 4.,5 Methods of examination and test. Methods' of examination and test are specified in the appropriate tables. Electrical test circuits are as prescribed herein or in the referenced test methods of M I L-STD-883. , 4.5~ I Voltage and current. All voltage values given, except the input offset voltage (or differential voltage) arc referenced to the external zero reference level of the supply voltage. Currents given are conventional current and positive when flowing into the referenced terminal. 4.6 Ins~ection of ~reparation for delivery. Inspection of preparation for delivery is in accordance with M II.-M-385I O. exceiitthat the rough handling test does ';-ot apply. 5. PREPARATION FOR DELIVERY 5.1 Preservation-p'!!ckligl!lg and ~acking~ Microcircuits are prepared fOJ delivery in ~ccoi"dancc with M 1i.-M-385 Ill. 6. NOTES 6.1 Notes. The notes specified in M IL-M-38510 are applicable to this specification. 6.2 Intended use. Microcircuits conforming to this specification arc intended for use in applications where the use of screened parts is desirable. 6.3 Ordering data. The contract or order should specify tbe following: a. Complete part number (see paragraph 1.2) b. Requirement for certificate of compliance, if desired. 6.4 Substitutability': Mircocircuits furnished under this specification are similar to Burr-Brown model 3500, 6.5 Microcircuit grou~ assig!!!!!E!!: These mircocircuits are assigned to Technology Group [) as defined in M I L-M38510, Appendix E. 6.6 Electrostatic sensitivity..: These microcircuits may be damageil by electrostatic discharge. Electrostatic sensitive precautions should be observed at all times. ' ~Olr: 1.l."at..l~ in true pU)Ioitiull '" Ithin 0.1 ON (25mm) R ill M Me at !,\l'illini! pllll'l" flin number.. ~hil\\ n h)r rcfcrclIl"C ~umhl'r~ ma~ nut he Wci~ht; DIM Seating Plane .\ ~nlm!to unl~. Illi.lrh·d un pi.ld.ililC. max. INCHES MIN MAX MILLIMETERS MIN MAX A .335 .370 8.51 9.40 • .305 .335 7.75 8.51 C ,165 .185 4.19 4.10 D .016 .021 0.41 0.53 .010 .040 0.25 1.02 .010 .040 0.25 G .200 BASIC 1.02 5.08 BASIC .028 .034 0." 0.86 .029 .045 0.74 1.14 12.7 .500 .160 .110 45° BASIC 2.79 M N .095 .105 2.41 4.06 45° BASIC 2.67 FIGURE 4. Case Outline (TO-99 Package Configuration). 7-80 3500, MIL SERIES 7. ELECTRICAL PERFORMANCE CURVES. (Typical at T\.:::: +25"(' and ±Vt ( ::::: J5VI>C unlcs~ othcrwi~ lopccificd). INPUT BIAS CURRENT vs. P-P INPUT NOISE VOLTAGE vs. RMS INPUT NOISE VOL TAGE vs, TEMPERATURE SOURCE RESISTANCE SOURCE RESISTANCE 80 60 ~ C ~ 5 40 20 VV II :; Co 0 <5 > v ~ '0 -20 _fB § 1kHz V V / 11'lfs=10kHz '" > f8 0.1 = 100Hz ~~ lbkJz ~ =- ./ 10 V fB =lkHZ ,r. f8 I I III fB - 10Hz ~ C. ~ Co £ UI Co ~ 0 z :> ~ ~ ~ III I 100 '" J!l <5 V:/ :/:/ z ~ V £ III I 1111 j 10 '" ~ I I ill fB 100Hz I III III = 10Hz -40 -50 -25 0 25 lk 50 75 100 125 10k 1M lOOk Temperature 1°C, Source ReSistance n OPEN-LOOP FREQUENCY OUTPUT VOL T AGE vs. FREQUENCY I RESPONSE 10k lk lOOk Source ReSistance I 1M In, VOLTAGE FOLLOWER STEP RESPONSE 15 120 Iii '~" c 100 80 60 J!l '"'" 40 > 20 <5 r..... 14 ±Vcc =II;ISV ±Vcc.:::: 3V to 20V "' " 0 Co -20 !Vcc 111111111 :; B- ~~,!111~~ > 0 :- (!l Co 0 0 100 -Ic 20 TA - -2SoC - '" 0 ~ - r--- ~ \. TA=85°CTA = 125°C 16 Co 25°C r--t ::-- --.t.. I :> o 12 '" 12 '" !'! > <5 r :; B- 0 ,I ~ I lOV ~ '"~- " I-.... ....< ....< Ir -I-.... 15 20 10 20 / 12 > :; Co :; F'" 16 o - ~ c 20 1\ 0 12 ,V 12 FREQUENCY ~ =- c / 1000 .Q .," U . II: >0. 100 ~ V 60 II: / / 0 20 0';: II "'" J!l <5 COMMON-MODE RANGE vs > 80 40 25 50 I I I RL = lkU SUPPLY VOL TAGE r-- I--- VCM = 10V, pk - r- 40 16 Output Current I mA I 100 :::; ~ Co +Vcc - 5V FREQUENCY '" 30 ::: 11\ COMMON-MODE REJECTION vs. Iii 20 \ SUPPL Y VOLTAGE -r-.. ""'1'"--. ~_Vcc::;; Supply Voltage I ±V I 120 10 20 !Vcc = 20V ±Vcc:=3~ 16 'I OUTPUT VOL TAGE vs. ±Vcc = 15V I 90 i Time (iJ.sec OUTPUT CURRENT =;; o 1M OUTPUT VOL TAGE vs K Co lOOk 10k VOLTAGE GAIN vs. TA \ CL = 100pF Frequency I Hz I TA = -55 a C ...'c" -10 SUPPLY VOLTAGE / -5 0 Al- lkU -15 lk Frequency I Hz I Iii :; \ V- ~ Co \ I <5 > I~IY +Vcc 10 100 lk 10k lOOk 1M 10M 110 '" ~ ='fov <5 if > lHllWI 10 '" ~ " '\ 10 12 ~ :> "" .'R":'= lkU 20 1 10 100 lk 10k lOOk 1M Frequency 35001 MIL SERIES 8. APPLICATIONS INFORMATION 8.1 Offset Adj~ The input offset voltage of the Model 3500 may be adjusted to zero by connecting a SOUl potentiometer between pins I and 5 with the wiper ilrm connected to negative supply (Figure 5a). This provides an adjustment range of approximately ±lOmV. This offset control is optional and may be omitted if the specified offset is considered sufficiently low. Adjustment ofthe input offset voltage of the 3500 will affect the voltage drift to some extent. A rough "rule-of-thumb" is ±3" V /"C change of drift for each 1.0mV of offseladjustment. This is true of other IC op amps; such as the 741. 10 I. etc .• but is usually masked by the greater drift of these units. However. in low drift amplifiers. this effect must be considered. By use of a transistor as in Figure 5b the effect of the offset adjustment on drift can be substantially reduced (by approximately a factor of six). ~ ~.vn a) Simple Offset Adjustment b) I>rift-Compensalcd Onset Adjustment *Optional Component FIGURE 5. Offset Adjustment Techniques. 8.2 Bias Current Effects. Input bias current of the amplifier creates additional offset voltages by flowing in the impedances of the signal source and the feedback network. Although the bias currents of the 3500 are quite small. their effects may be appreciable when these impedances are large. The bias currents at the two inputs tend to be equal and the difference current smaller than either. Thus equalizing the resistance from each input to common. as in Figure 6, is an effective means of reducing DC offset due to bias current. . R. R~ R. + R~ VU!I-OlfR,= - - FIGURE 6. Minimization of Bias Current Effects. 8.3 Q~eration on a Single SuPpJy.: Although virtually any op amp can be operated on a single supply if input and output voltage limitations are observed, the Model 3500 is particularly suitable for such use. Its wide supply range of±3VDC to ±20VDC translates to a single supply operating 'range of 6VDC to 40VDC, plus or minus. Two possible modes of operation on a single supply are shown in Figure 7. The following conditions must be observed to keep the amplifier within its linear region of operation. I) +2 < Vo < (Vee -2) 2) +3 < VIN < (Vec-3). Figure 7b. When operating on a single supply (+Vecl. shorting the output to common is equivalent to a short to supply and the internal power dissipation is approximately twice that which occurs for a short to common with balanced supplies of ±(Ved 2). This dissipation may exceed safe limitsfor single supply voltages greater than 20V and must be prevented by use of a series limiting resistor or other device. if short circuit protection 'is desired. 7-82 3SOO1 MIL SERIES +Ya:. Vee2 - (R') R. Vo= - VIM Vo V,. 0) Inveni", AmpliflOr R'+ RI) 'VIN Vo= ( -R-,- + LOAD Vo It) NGIIi_nina Amplir.., FIGURE 7. Operation on a Single Supply. 8.4 Wiring Precautions. In order to prevent high frequency oscillations due to lead inductance the power supply leads should be bypassed. This should be done by connecting a IOpF tantalum capacitor in parallel with a O.OOlpFceramic capacitor from pins 7 and 4 to the power supply common. 8.S !YP'icaI Applications, Il, Voor= -R.' VoUr :I: ( I + ~ ) VIN It) a) I.ven" AmptiO.r VIN Noninvenina Amp6fler R,IIR,=R,IIR. For IlliaiDlUlll error due to bias currents. ~ 2 V,. 3 6 V, at V, II. VOliT VOUT - .rP....ioion Buffer Amp6r"r R'+R')R' R, ( R) + It. R. V2 -I'; VI d) Difference AmpIiflCr The information in this publication has been carefully checked and is believed to be reliable; however, no responaibility is assumed for possible inaccuracies or ormHions. Pricea and specifICations are subject to change without notice. No patent rights are granted to any oCtile circuits described herein. 7-83 3510VM/MIL REV. NONE BURR -BROWN@ IElElI NOVEMBER, 1978 Amendment 1 Incorporated Aprll,1979 DETAILED SPECIFICATION MICROCIRCUITS, LINEAR OPERATIONAL AMPLIFIER MONOLITHIC, SILICON 1. SCOPE 1.1 SCOP.!1: This specification covers the detail requirements for a monolithic, low offset voltage drift, integrated circuit operational amplifier. 1.2 Part number. The complete part number is as shown below. 3510 V T Basic model number 1.2.1 ~yp.!:. l M jMIL Metal package Hi-ReI product designator l Grade T The device is a single, operational amplifier. 1.2.2 Device class. The device class is similar to the product assurance level class B, as defined in MIL-M-38510. 1.2.3 Case outline. The case outline (8-lead can) is as defined in Figure 5. The case is metal and is conductive. 1.2.4 Absolute maximum rating§: Supply voltage range Input voltage range . Differential input voltage range Storage temperature range Output short-circuit duration Lead temperature (soldering, 6Osec) Junction temperature ±20VDC ±20VDCy ±40VDCl/ -65°C to +l50"C Unlimitedy 300°C TJ = 175°C l/ The absolute maximum input voltage is equal to the supply voltage. Y Short circuit may be to ground only. Rating applies to +13SOC case temperature or +SO"C ambient temperature at ±ISVDC supply voltage. International Airport Industrial Park • P.O. Box 11400· Tucson. Arizona 85734· T81.1602I 748·1111 • Twx: 91~2·1111 • Cable: BBRCORP . Telex: 66-6491 PD&-4IOA 7-84 1.2.5 Recommended operating conditions. Supply voltage range _________________ ±3VDC to ±20VDC Ambient temperature range ____________ -55°C to +125°C 1.2.6 Power and thermal characteristics. Package 8-lead can Case outline Figure 5 Maximum allowable power dissipation 225mWat TA -125°C Maximum 8J-C 70°CfW Maximum 8J-A 220°CfW 2. APPLICABLE DOCUMENTS 2.1 The following documents form a part of this specification to the extent specified herein. SPECIFICAnON MILITARY MIL-M-38510 - Microcircuits, general specification for. STANDARD MILITARY MIL-STD-883 - Test methods and procedures for microcircuits. 3. REQUIREMENTS 3.1 General. Burr-Brown uses production and test facilities and a quality and reliability assurance program adequate to assure successful compliance with this specification. 3.1.1 Detail sl!!ecifications. The individual item requirements are speCified herein. In the event of conflicting requirements, the order of precedence will be the purchase order, this specification, and then the reference documents. 3.1.2 Country of manufacture. These microcircuits are manufactured, assembled, and tested within the United States of America. 3.2 Desilm, construction, and pltysical dimensions. 3.2.1 ~~,~, and other materials. The package is in accordance with paragraph 3.5.1 of MIL-M-38510. The exterior metal surfaces are corrosion resistant. The other materials are nonnutrient to fungus as specified in MIL-M-38510. 3.2.2 DesigJ.! documentation. The design documentation is in accordance with MIL-M-3851O. 3.2.3 Internal conductors and internal lead wires. The internal conductors and internal lead wires are in accordance with MIL-M-3851O. 3.2.4 Lead material and fmish. The lead finish is gold plate. The lead material and finish is solderable per MIL-STD-883, method 2003. 3.2.5 Die thickness. The die thickness is in accordance with MIL-M-3851O. 3.2.6 Physical dimensions. The physical dimensions are in accordance with paragraph 1.2.3 herein. 3.2.7 Circuit diagt:am and terminal connections. The circuit diagram and terminal connections are shown in Figure I. OUTPUT PHASE COMPENSATION 8-Lead Can (Top View) NOTE: -Vel' is connected to the case. ~ (optional - see paragraph 3.3.2) -Vee FIGURE I. Terminal Connections. 7-85 3.2.8 Schematic circuit. The schematic circuit is shown in Figure 2. V+~7·~'~I.~----~----4r--------~.~~------------~--~ lkil ., 'IS I.SkO ~ 7b IkO 8000 .r---------L-~----------------------~~~ .IO RI7 lUI 80011 __ ______ __ __ ~ ~ ~ RIB 1411 ~ NOTE; AllrailtalXlC and c:apacitanclr: Yalues are nomiIYI. FIGURE 2. Schematic Circuit. 3.3 Electrical performance characteristics. The electrical performance characteristics are as specified in Table I and apply over the full operating ambient temperature range of -55°C to +125°C, unless otherwise specified. 3.3.1 Offset and gain error null. The amplifier is capable of being nulled to zero offset voltage using the circuit in Figure 3. H:;::=== OFFSET NULL INPUTS { 0--------\ OUTPUT FIGURE 3. Offset Null Circuit. 3.3.2 Freguengr comp'ensation. The amplifier is free of oscillation when operated at a gain of 10 or greater with no external compensation and a source resistance of 0:;;;1 OkO and when operated in any test condition specified herein. 3.4 Electrical tests. Electrical tests are shown in Table III. The subgroups oCTable III and limits of Table IV, which constitute the minimum electrical tests for screening, qualification, and quality conformance, are shown in Table II. 3.5 Marking. Marking is in accordance with MIL-M-385I O. Thefollowing marking is placed on each microcircuit as a minimum. a. Part number (see paragraph 1.2) b. Inspection lot identification code c. Manufact'urer's identification d. Manufacturer's designating symbol e. Country of origin 7-86 TABLE I. Electrical Performance Characteristics. Symbol Input offset voltage (±VCC = ISV, ;:.::~i~::rwise specifledl VIO Min T.=2S"C ·SS"C';; f.';; +125' "its --r.rax Units +1211 ±3SO uV "V Input offset vol.... temperature sensitivity (1IIIIIUlIod VIO) ~ offset curront ' Input offset current temperature sensitivity Input bias current ::;~:Sur"u:::ivity Power supply rejection ratio .6. VIO "Tf ~ T. from ·SS'C to +2S"C T. from +2S"C to +l2S'C .6.110 "i'T ~ ~ • = 2S'( -SS'C';; T.';; +12S'C 4.11. ~ TI ~ uVl'C "V!'C ±SS DA nA T. from -SS'C to +2S'C T. from +25'C to +12S"C II. ±2 ±2 ,= 2: -SS'C';; T.';; +12S'C 110 :W.4 nA/'C ±0.4 -ill nArC nA nA ±8S T. from -SS'C to +25'C f. from +2n: to +12S'C :W.6 nAl'C ±0:6 nArC +PSRR +Vee = 10V -Vee = -ISV T. = 2S'C 3 "V/V -PSRR +Vee = ISV -Vee = -IOV T. = 2S'C 3 "V/V CMR VCM = -IOV Power supply rejection ratio ~ Input voltate comm()l1o-mode rejection Adjustment for input offset voltage Output short circuit current (for positive output) t~ +IOV T. = 2S'C VIO ADJ(±) Io. (+) 110 dB ±I.S mV +2S"C';; T.';; +l2S'C -SS'C .;; T • .;; +2S"C 10 10 +2S"C';;T.';;+12S"C -SS'C';; T.';; +2S'C 10 10 30 rnA -40 rnA Output short c:ircuit current (for negative output) OC power dislipation (quiaoent) , SinsJe.Voo ~ Short Circuit Current los 10 IRL=2kO,CL=IOO0pF I Closed loop ITA • +25°C 1.5 C~~:~~~~H~z 10 2 1: 0 TA=+25°C -25°C to +85°C -55°C to +125°C -25°C to +85°C -55°C to +125°C ~:;:::~25OC 25 30 100 100 1.0 1.0 ;~ ~ ±V 0 . I'~. rms "V.rms . 50 100 200 1.7 2.0 ±mV ±mV ±mV ±mV/oC ±mV/oC ;~ POWER SUPPLY Power Supply Range Power DiSSipation, Quiescent 8.5 TA =+25°C -55°C to +125°C 15 20 ±V 150 180 225 mW mW +125 +150 °C °C ,RANGE Operating Storage -55 -65 ·Specifications same as 4213WM NOTE: ]J Externally adjustable to zero. 3.3.1 Additional electrical performance characteristics. Electrical performance curves are shown in paragraph 7. 3.3.2 Transfer functions. The transfer functions for multiplier and divider connections are shown in Figure 2. 7-95 4213/MIL SERIES IXI . XzllYl • Y2) 10 b. I. ·IIN .; IX I • X2) .; ·G.2V +Z2 Z2 Z2 c, FIGURE 2, Transfer Functions, 3.3.3 OutJ>ut offset error null. The multiplier is capable of being nulled to zero offset error using the circuit in Figure 3, OUTPUT NOTE: lbe on.. null palentlDllllllr II DpIIonel. 1bI VOl IWmlnllllllY belli! up.. III' lillY bl grounded. IDn FIGURE 3, Offset Null Circuit. 3.4 Electrical tests. Electrical test requirements are specified in Table II, The subgroups of Table III and limits of Table IV, which constitute the minimum electrical tests for screening, qualification, and quality conformance, are shown in Table II. TABLE II. Electrical Test Requirements. (The individual tests within the subgroups appear in Table 1111 ~ 4213WM/883B 4213WM MIL-STD-883 TEST REQUIREMENTS (HYBRID CLASS) 4213VM/MIL 4213VM1883B 4213VM 4213UM/883B 4213UM Subgroups {see Table llil Interim electrical parameters (pre burn-in) (method 5008) 1 1,2,3,4,5,6 Final electrical test parameters (method 5008) -- Group A test requirements (method 50081 Group C end pOint electrical parameters (method 50081 Additional electrical subgroups performed prior to Group C inspections 'PDA applies to subgroup 1 (see 4,3.d) 7-96 1 1', 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6, 4A 1 1,2,3,4,5,6 1 1, 2U, 3U, 4, 5U, 6U - Table IV limits and delta limits - - - 1C,2C,3C,5C,6C,7C -- -- -- 42I3/MIL SERIES TABLE III. Group A Inspection. LIMITS SUBGROUP 1 TA = +25°C lC TA = +25°C 2 TA =+125"C 2U TA = +S5°C 2C TA =+125"C PARAMETER SYMBOL Vee hB Po CMR RIN Ro 10 Vee V::~DE CONOITIONS ±VCC = 15VDC, pln ......n unl... olllerwll. opeclfled MIN X,lnpul X -Y -+IOV 10-4;V MAX W::.:.:oE MAX MIN ±30 2.5 180 ±25 2.5 180 5 X,lnpul aVee Vee 1+125°CI-Vee 1+25°CI ar-= l000C Po CMR X = Y = +IOV 10-4;V Vee 3U TA = -25°C Voo 10 20 ±100 X=Y=+IOVIo-6V ET FTx FTy Each quadranl X = 20V, p-p; Y = 0; I = 50Hz. X = 0; Y = 20V, p-p; I = 50Hz ±1 100 SO 4A TA = +25°C 5 TA = +125°C VeM RL = 2kll, CL = 1000pF ±10 ET Each quadranl ±4 5U TA =+S5°C Er Each quadranl 5C TA=+125°C VeM FTx FTy 6 TA = -55°C Er Each quadrant 6U TA = -25°C ET Each quadranl 6C TA = -55°C VeM FTx FTy 7C TA=+25°C BW,'II BW,'II SR SR BW3dB BW3dB BWFP N N mV ~ mW dB ±100 mV mVI"C 225 mW dB 80 ±1I2 50 40 ±1 100 80 % X = 20V, p-p; Y -IOV X = 10V; Y = 20V, p-p X = +2OV-slep; Y = IOV; RL = 2kll X = 10V; Y = +20V-slep; RL = 2k1l X = IV, rrna; Y=IOV X = 10V; Y = tv, rrns RL = 20kll, Vo = ±10V IB = 1Hz 1010kHz IB = 1Hz 10 10MHz ±3 ±10 200 180 % 200 1000 (TA = 25°C. ±Vcc = 15VDCI Tnt Vee Llmll Delio 1.0% ±BDmV 0.66% 7-97 % V mV, p-p mV, p-p kHz kHz V/p.Sec V/p,.ec kHz kHz kHz 70 (0 20 20 450 450 130 TABLE IV. Group C, End Point Electrical Parameters. ET % V mV, p-p mV. p-p ±2 RL ~ 2kll, CL '" 1~!,F I = 50Hz X = 20V, X = 0; Y = 20V, p-p; I = 50Hz % mV, p-p mV, p-p V ±4 ±2 ±10 200 180 ±3 mV ~A 6 ±1 RL - 2kll, CL -1000pF X = 20V, p-p; Y = 0; I = 50Hz X =0; Y = 20V, p-p; I = 50Hz mV mVI"C ±loo Po CMR 4 TA =+25°C ±loo 225 ±100 ~A mW dB Mil Il mA 80 X,lnpul aVee Vee (-55°CI-Vee (+25°CI' ar-= SQOC hB aVee mV 6 ±1 --:iT 3C TA = -55°C UNITS ±50 2.5 180 ±100 --:iT 3 TA = -55°C MAX 60 3.5 Vee hB avoo U:~DE MIN 25mV }lV, rms /lV, rms 4213/MIL SERIES 3.5 Marking, Marking is in accordance with MIL-M-38510. The following marking is placed on each microcircuit as a minimum. a. Part number (see paragraph 1.2) b. Inspection lot identification code 11 c. Manufacturer's identification ( d. Manufacturer's designating symbol (CEBS) e. Country of origin (U .S.A) raWn 3.6 Workmanship.., These microcircuits are manufactured, processed, and tested in a careful and workmanlike manner. Workmanship is in accordance with good engineering practices, workmanship instructions, inspection and test procedures, and training, prepared in fulfillment of Burr-Brown's product assurance program. 3.6.1 Rework I'rovisions. Rework provisions, for the / MIL Hi-Rei product designation, including rebonding, are in accordance with MIL-M-3851O. . 3.7 Traceability.., Traceability is in accordance with MIL-M-3851O. Each microcircuit is traceable to the production lot and to the component vendor's component lot. Reworked or repaired microcircuits maintain traceability. 3.8 Product and process change. Burr-Brown will not implement any major change to the design, materials, construction, configuration, or manufacturing process which may affect the performance, quality, reliability or interchangeability of the microcircuit without full or partial requalification. 3.9 Screening. Screening, for / MIL and /883B Hi-Rei product designations, is in accordance with MIL-STD-883, method 5008, hybrid class. except as modified in paragraph 4.3 herein. For the standard model, Hi-ReI product designation (none), routine manufacturing processing includes Burr-Brown internal visual inspection, and stabilization bake, fine leak, gross leak, burn-in (72 hours, performed preseal), constant acceleration (condition D) and external visual inspection per MIL-STD-883 method 5008 hybrid class. For the / MIL Hi-Rei product designation, all microcircuits will have passed the screening requirements prior to qualification or quality conformance inspection. 3.10 9ualification. Qualification is not required. See paragraph 4.2 herein. 3.11 9ua1itx conformance insp'ection. Quality conformance inspection, for the / MIL Hi-Rei product designation, is in accordance with MIL-M-3851O. except as modified in paragraph 4.4 herein. The microcircuit inspection lot will have passed quality conformance inspection prior to microcircuit delivery. +15VOC ·15VDC ~1~ Vy FIGURE 4. Test Circuit for Total Error. 11 A four·digit date code, indicating year and week of seal, is marked on /8838 and (none) Hi-Rei product designations. 7-98 4213/ MIL SERIES PROCEDURE: I. Set V, = V, = +IO.OOOVDC ±lmV, measure Eo = Eol . 2. Set V, = V, = -1O.000VDC ±lmV, measure Eo = Eol. 3. Set V, = +IO.OOOVDC ±lmV and V, = -1O.000VDC ±lmV, measure Eo = Eo!. 4. Set V, = -IO.OOOVDC ±lmV and V, = +1O.000VDC ±lmV, measure Eo = E04. 5. Calculate Vol =IEol -101, Vo2 =IEol -101, Vo3 =IEo3 +101 and V04. =IE04 +101. 6. yo, is the largest of Vol, Vol, Vo3 or V04 . ET(%) = Yo, x 100 10 4. PRODUCT ASSURANCE PROVISIONS 4.1 SamQling and inspection. Sampling and inspection procedures are in accordance with MIL-M-3851O and MIL-STD-883, method 5008 except as modified herein. 4.2 Qualification. Qualification is not required unless specified by contract or purchase order. When so required, qualification will be in accordance with the inspection routine ofMIL-M-38510, paragraph 4.4.2. I. The inspections to be performed are those specified herein for groups A, B, C, and D inspections (see paragraphs 4.4.1 , 4.4.2, 4.4.3, and 4.4.4). Burr-Brown has performed and successfully completed qualification inspection as described above. The qualification report is available from Burr-Brown. 4.3 Screening, Screening, for /MIL and /883B Hi-Rei product designations, is in accordance with MIL-STD-883, method 5008, hybrid class, and is conducted on all devices. The following additional criteria apply: a. Constant acceleration test (MIL-STD-883. method 2001) is test condition D. YI axis only. b. I nterim and final test parameters are specified in Table II. The interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Burn-in test (MIL-STD-883, method 1015) conditions: (I) Test condition B (2) Test circuit is Figure 5 herein (3) T A = + 125°C minimum (4) Test duration is 160 hours minimum d. Percent defective allowable (PDA). The PDA, for the / MIL Hi-Rei product designation only, is 10 percent and includes both parametric and catastrophic failures. It is based on failures from group A, subgroup I test alter cool-down as final electrical test in accordance with MIL-STD-883, method 5008, and with no intervening electrical measurements. If interim electrical parameter tests are performed prior to burn-in, failures resulting from pre burn-in screening failures may be excluded from the PDA. If interim electrical parameter tests prior to burn-in are omitted, all screening failures shall be included in the PDA. The verified failures of group A, subgroup I after burn-in in that lot are used to determine the percent defective for that lot, and the lot is accepted or rejected based on thePDA. e. External visual inspection need not include measurement of case and lead dimensions. +IOVDC FIGURE 5. Test Circuit, Burn-in and Operating Life Test 7-99 4213/MIL SERIES .4.4 Quality' conformance inspection. Groups A and B inspections of MIL-STD-883, meth.od 5008. 'are performed on each inspection lot. Group D, subgroup I, seal test, ofMIL-STD-883, method SOO8"isperformed on each lot of packages procured. Groups C and D inspections of MIL-STD-883, method S008, are not.required unless specified by contract or purchase order. Burr-Brown periodically performs groups C and D inspections of MIL-S'fD-883, method S008. A report of the most recent groups C and D inspections is available from Burr-Brown. 4.4.1 Group A inspection. Group A inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method S008, Table I, and as follows: a. Tests are specified in Table II herein. b. Tests previously performed as part of final electrical test need not be repeated. 4.4.2 Group B inspection. Group B inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method SOO8, Table II and as follows: a. Particle impact noise detection test is not required. 4.4.3 Group C inspection. Group C inspection consists of the test subgroups and LTPD values shown in MIL-STD-8~, method 5008, Table III, and as follows: a. Operating life test (MIL-STD-883, method lOOS) conditions: (I) Test condition B (2) Test circuit is Figure S herein (3) T A = 12SoC minimum (4) Test duration is 1000 hours minimum b. End point electrical parameters are specified in Table II herein. c. Additional electrical subgroups are specified in Table II herein. 4.4.4 Group D inspection. Group D inspection consists of the test subgroups and LTPD values shown in MIL-STD-883, method S008, Table IV, and as follows: a. Particle impact noise detection test is not required. 4.S Methods of examination and test. Methods of examination and test are specified in the appropriate tables. Electrical test circuits are as prescribed herein or in the referenced test methods of MIL-STD-883. 4.S.1 Voltage and current. All voltage values given, except the input offset voltage (or, differential voltage) are referenced to the external zero reference level of the supply voltage. Currents given are conventional current and positive when flowing into the referenced terminal. 4.6 Inspection of p~I'aration for delivery.: Inspection of preparation for delivery is in accordance with MIL-M-38S1 0, except that the rough handling test does not apply. S. PREPARATION FOR DELIVERY S.I Preservation-I'ackagl!!g and I'acking~ Microcircuits are prepared for delivery in accordance with MIL-M-38SIO. 6. NOTES 6.1 Notes. The notes specified in MIL-M-38SIO are applicable to this specification. 6.2 Intended use. Microcircuits conforming to this specification are intended for use in applications where the use of screened parts is desirable. 6.3 Ordering data. The contract or order should specify the following: a. Complete part number (see paragraph 1.2) b. Requirement for certificate of compliance, if desired. 6.4 Definitions. Total error. Total error (ET) is the difference between the actual output voltage and the ideal output voltage expressed as a percentage of the maximum output voltage, 10 volts. It is the sum of the individual errors and includes feedthrough and output offset voltage. Feedthroug!!: Feedthrough (FTx or Ffy) is the output voltage when the ideal output voltage is zero (i.e., X = 0, Y = ±V or X=±V, Y=O). 6.S Microcircuit groul' assig~ These mircocircuits are assigned to Technology Group F as defined in MIL-M38SIO, Appendix E. 6.6 Electrostatic sensitivity.: These microcircuits may be damaged by electrostatic discharge. Electrostatic sensitive precautions should be observed at all times. 6.7 Power SuppJiliquencing, Apply, and remove, both supplies together. Alternatively, apply the positive supply first. Permanent damage may occur ifthe minus supply is applied with an input greater than +6VDC. 7-100 4213/MIL SERIES 7. ELECTRICAL PERFORMANCE CURVES. (TypicafatTA = +25°C and ± Vee = 15VDC unless otherwise specified.) TOTAL ERROR VS AMBIENT TEMPERATURE ~ o 10 ~ 5 NONLINEARITY VS FREQUENCY 100 Inplut S,g~., = ~V. p-p e w i o ~ II" / V 0.5 X7 1 / 0.2 '5 O. 1 1 ~ / -75-50-250 255075100125 Ambient Temperature 1°C· 0.00 1 10 OUTPUT AMPLITUDE VS FREQUENCY 100 " ~ ~ = ~ =a ~ -5 1" -10 100k 1M Frequency IHzl I II I I ~50 10M ~ 0 '5 c. '5 -5 o V" - -10 o ~ X = 12V, p-p Y ±10VDC a:: i340 10 100 10k 100k 1M 10M INPUT VOLTAGE FOR LINEAR RESPONSE -- '1 2 &1 c :; 8 c. .5 6 4 2 4.0 0 5.0 [I 1.".4 , ,'i/ n.· ,.' ..' 't., I~ I 2 4 6 8 10 12 14 16 18 20 Power Supply Voltage ±Vee SUPPLY CURRENT VS AMBIENT TEMPERATURE 16 Y 12V.p-p _\X=±10VDC- 14 ~ , -:p..o- i: 10 ~ 5 8 () "- 1k 10k 100k 1M 10M Frequency I Hz, Quiescent 0. go 4 en \ 20 1k fl1 0 1\ 30 100 1 I > 14 I 2.0 3.0 Time •",sec I rt Positive Common-mode ~ Differential 6"":' F' Negative common-mod;, 18 l~f':;l \. 1.0 J :/1 Frequency I Hz \ I ;..- 5mA Load 60 Iii 10 1M ~ II I 10 y _feedthrough COMMON-MODE REJECTION VS FREQUENCY 80 70 I t Y~ \ -20 1 g> 20 e .s:: 20 ~x 6 -15 X-F!....,th'.oug~ 50 .s:: 'v , SI9~.1 = ~v. !-p- ~ I I 100 ~ LARGE SIGNAL RESPONSE ~ '5 S- " §200 / 1k 10k lOOk Frequency! Hz I 10 Iii 0 Inoft :> ;;! 0.05 i'" FEEDTHROUGH VS FREQUENCY 1000 c. /,.500 2 16 Output Current' ±mA o -100-75-50 -25 0 25 50 75100 125150 Ambient Temp.erature °C 8. APPLICATIONS INFORMATION 8.1 Power sUPpJ)! decoupling, For optimum performance and to prevent frequency instability due to power supply lead inductance, each power supply should be decoupled by connecting a I p.F tantalum capacitor from each power supply pin to ground (power supply common). 8.2 Qil1acitive loads. Stable operation is maintained with capacitive loads up to IOOOpF, except for the square root mode which is limited to 50pF. Higher capacitive loads can be driven if a loon resistor is connected in series with the output for isolation. 8.3 !Yl1ical Apl1lications. 8.3.1 Multil1lication. The basic connection for four-quadrant multiplication is shown in Figures 2a and 2b. Optional offset nullling is shown in Figure 3. Feedthrough may be minimized by applying an external nulling voltage to the X and/ or Y input, as appropriate. Usually, the nulling voltage is applied to X, or Y,. If Z, input is not used, it should be grounded. 7-101 4213/MIL SERIES Figure 6 shows how to achieve a scale factor larger than 0.1 (Le., a denominator less than 10). A larger scale factor is electrically advantageous in some applications, but this has the disadvantage of proportionately increasing the output offset voltage. Note, the offset may be nulled as shown in Figure 3. Also, the small signal bandwidth is reduced to about 50kHz. 4213 K=[I + IRI/R21]110 0.1,,;;; K.;I ·15VOC +15VOC FIGURE 6. Connection for Unity Scale Factor. 8.3.2 Division. The basic connection for two-quadrant division is shown in Figure 2c. Divider error is approximately IOEmultiPlier Edividcr = . Xl - X2 Note, the divider error will become very large for small values of (XI - X2). A 10 to I denominator range is a practical limit. 8.3.3 ~quarii1g, The basic connection is shown in Figure 7. XI Xz vI G-+.-t---tYI v2 Y2 4213 ~lZ (VI' V21Z + Zz 1'=--10-- lOOkn ·15VOC +15VOC FIGURE 7. Squaring Connection. 8.3.4 SC(uare Root. Figure 8 shows the connection for taking the square root of the voltage VZI - VZ2. The diode prevents a latching condition which could occur if the input momentarily changed polarity. The load resistance RL must be in the range of IOkO";; RL ..;; I MO to provide the current necessary to operate the diode. The output offset should be nulled for optimum performance; allow the input to be its smallest expected value and adjust RI for the proper output voltage. The square root mode accuracy is then approximately that of the mUltiply mode. +15VOC +15VOC 21"" +D.ZV .; 121 ' Zzl.; +1 OV Zltn-=,I5VOC ,I5VOC ·Optllllllli Nulling ClllptllllnII +16VDC Zz ZI .". ,I5VOC FIGURE 8. Square.Root Connection. 7-102 +II.2V.;12,,2ZI.;+'OV ·15VDC +15VDC Zz 4213/MIL SERIES 8.3.5 Percent. The circuit of Figure 9 has a sensitivity of I V/% and is capable of measuring 10% deviations. Wider deviation can be measured by decreasing the ratio of R2 /R t • Xl Xf 1% plrvoll 4213 Vo '1 91tO '2 V2 Ito FIGURE 9. Percentage Computation. 8.3.6 Sine Function Generator. The circuit in Figure lOuses implicit feedback to implement the following sine function approximation: Vo = (1.5715V 1 - 0.004317V I 3 )/(I + 0.001398V I 2 ) = 10 sine (9Vt). 71.548ko Xl ~""""""'-+-IX2 4213 '1 '2 Illko l·l0V '" VI'" +IOV.lnd IV =11") FIGURE 10. Sine Function Generator. 8.3.7 Sing~~hase Power Measurement. Figure II shows a circuit for measurement of single-phase instantaneous and real power. 0:=R5 /IR4+R&I 'Y = I-Rl Ral/Hz Inlllnllneoul Power Rill Power f loc'Y/1 0)Iqrml'LrmICOl/J) FIGURE II. Single-Phase Instantaneous and ReallPower Measurement. 7-103 MODULAR POWER SUPPLIES Well-regulated DC power is usually required to power modern electronic circuits. Over the years electronic circuits have changed in terms of size and performance. Packaged in small integrated circuit packages or in hybrid modules, more and more electronic circuits now provide significantly improved performance. Burr-Brown encapsulated power supplies have kept up with changing times. We provide a broad line of reliable, self-contained, ready to use power supplies, at low cost, to meet OEM and design engineers' power supply requirements. Burr-Brown standard series AC/DC power supplies and DC/DC converters provide maximum flexibility in systems design. They are particularly useful for powering analog interface circuitry involving operational amplifiers, A/D and D/A converters, instrumentation and isolation amplifiers, analog circuit functions, and so forth, in digital and analog systems. A wide range of output voltage and current ratings are available; international input voltage ratings are also available. The AC/DC supplies are available in both the PC board-mountable and chassis-mountable versions. The chassis mount type provides the same reliable performance as the PC board mount type, but the input and output connections are made on a terminal strip via screw terminals rather than pins. They are useful in applications where use of PC boards or sockets is either undesirable or impractical. The DC/DC converters are available in small encapsulated PC boardmountable packages. They provide high input-output isolation, making them suitable in computer interface applications where, if necessary, the analog circuitry can be "floated" completely independent of digital ground. Specially designed DC/DC converters are available for use with opticallycoupled isolation amplifiers and for applications where isolation voltage ratings of 3000 volts and more are required. All Burr-Brown power supplies are extensively tested before and after encapsulation to ensure reliable operation. Computerized automatic testing equipment is used to implement stringent quality control. Years of linear and digital engineering expertise have gone into the design and manufacture of Burr-Brown products. Most of these power supplies are available from stock in both small and large quantities. 8-1 II .• ,i, ' SELECTION GUIDE Modular Power Supplies .. Rated 'Output Description Model Dual ±15VDC Supply P.C.B. Mount 550 551 552 553 554 ±15V, ±25mA ±15V, ±50mA ±15V, ±100mA ±15V, ±200mA ±15V, ±350mA Dual ±15VDC Supply Chassis Mount 5VDC Supply P.C.B. Mount AC/DC CONVERTERS Rated Input Regulatiqn, No Load to Full Load Regulation Overrated Line Volt. Outputl1l Ripple/Noise 'Package ±o.I% ±0.O5% ±0.05% ±0.05% ±o.02% ±0.05% ±o.o5% ±0.05% ±O.05% ±0.02% 2mV 0.5mV O:5mV 0.5mV Q.5mV Module Module. Module Module Module 105VAC to 125VAC, SOHz to 400Hz 121131141 556 ±15V, ±200mA 558 ±15V, ±500mA 560 561 562 5VI51, ±250mA 105VAC.to 125VAC, 5VI51, ±500mA SOHz· to 400Hz 1211311 41 5VI51, ±1000mA 105VAC to 125VAC, 50Hz to 400Hz 121131141 Price ($) Unit l00's Page 35.25 52.00 .65.50 88.50 106.00 22.50 38.25 46.SO 68.75 84.SO 8-3 8-3 8-3 8-3 8-3 8-3 ±o.05% ±0.05% lri1V Module 75.50 59.00 ±o.o5% ±0.05% lmV Module 107.00 83.75 8-3 ±0.1% ±0.1% ±0.1% ±o.05% ±0.05% ±o.05% lmV lmV lmV Module Module Module 53.50 63.25 86.75 38.25 44.00 63.25 8-3 8-3 8-3 DC/DC CONVERTERS Input Output Isolation Leakage Current Package Unit l00's Page 546 4.5VDC to 5.5VDC 400mA Single-Bipolar ±15V, 120mA 300V Not Specilied Module 92.00 80.25 8-3 700 10VDC to 18VDC 89mA ±10VDC to ±18VDC r±1 V tolerance I at 60mA total 1500Vp 11lA, max Module 43.30 33.80 8-7 700UI61 10VDC to 18VDC 89mA 2000Vp 11J,A, max Module 39.10 28.95 8-7 710171 10VDC to 18VDC l00mA ±10VDC to ±18VDC r±1 V tolerance I at 60mA total Four sets of outputs 1000Vp 1p.A, max Module 52.00 37.50 8-Q 3500VI61 8000V191 '1000VI61 3000V191 1~Aat DIP 240V, 60Hz 1~A at 240V, 60Hz 35.95/ 43.70 47.40 25.95/ 32.30 35.00 8-13 8-13 DIP Description Model Regulated Isolated Price ($\ each set ±10VDC to ±18VDC l±1V tolerance I at 76mA total all outputs 722 722BG 724 5VDCto 16VDC 120mA 5VDC to 16VDC 125mA Two-Bipolar +15V,84mA Four-Bipolar ±8V NOTES: I I At lull load, rms r max I. 21 205VAC to 240VAC, 50Hz to 400Hz option available. 3 r 90VAC to I I OVAC, 50Hz to 400Hz option available. 41 220VAC to 280VAC, SOHz to 400Hz option available. 51 Connect as +5V or -5V. 61 Models 700 and 700M have separate internal input and output shields. Models 700U and 700UM have no internal shields. Model700M and 700UM are similar to Models 700/700U but, in addition, they are 100% screened to patient connected circuit requirements for the leakage current (par. 27.51 and withstand voltage (par. 31.111,01 UL544. Additional charge lor 700M or 700UM. See Product Data Sheet for complete specifications. 7) Model 710 provides 4 channels (sets) of isolated outputs. See Product Data Sheet for complete speCifications. 8) Input to output, continuous. 91 Input to output, 5sec\ minimum. 8-2 8-17 BURR - BROWN ® 113131 MODULAR AC/DC AND DC/DC POWER SUPPLIES FEATURES • PC BOARO-COMPATIBLE • CHASSIS MOUNTABLE • HIGH RELIABILITY, FULLY TESTED • LOW INSTALLED COST • COMPLETELY SELF-CONTAINED DESCRIPTION Burr-Brown standard series power supplies and DC/DC converters provide maximum flexibility in systems design. They are particularly useful for powering analog interface circuitry in digital and analog systems and have a wide range of output voltage and current ratings. They are completely selfcontained, ready to use encapsulated units. For most OEM users they eliminate engineering startup/documentation costs and manufacturing delays at prices generally far below internal manufacturing costs. The ACI DC power supplies have a current limiting circuit in the output stage, designed to withstand output short-circuit-to-common or substantial overload conditions for long periods of time, without .causing damage to the power supply. In applications where isolation between input and output is an essential requirement (such as powering isolation amplifier input and output stages) the BurrBrown isolated DC/DC converters provide up to ISOOVDC of isolation protection. Inlernational Airport Induslrial Park· P.O. Box 11400 . Tucson. Arizona B5734 . Tel. (602) 746·1111 . Twx: 91 ()'952·1llI . Cable: BBRCORP . Telex: 66·6491 POS-.lJ7B" 8-3 MODULAR AC/DC POWER SUPPLIES • PC BOARD/CHASSIS MOUNT TYPE • :l:15VDC DUAL OUTPUTS, +5VDC SINGLE OUTPUT • 25mA TO 1000mA CURRENT CAPABILITY • CURRENT-LIMITED OUTPUTS FOR SHORT CIRCUIT PROTECTION • INTERNATIONAL AC INPUT VOLTAGE OPTIONS AVAILABLE SPECIFICATIONS COMMON TO ALL ACj DC POWER SUPPLIES Input Voltage: 105VAC to 125VAC, 50Hz to 400Hz. For international AC input voltages see options E, F, and H. Input Isolation: 50Mll Breakdown Voltage: 500V; min. Output Voltage: Error, ±I%; temperature coefficient, ±O.02%/"C Output Protection: Current limiting protection for output to withstand overloads and direct short circuits to ground to prevent excessive temperature within the unit. Rated Operating Temperature: -25°C to +71 DC. May be operated at higher temperatures with proper derating. Storage Temperature: -25°C to +85°C. DCj DC CONVERTERS, ±15VDC OUTPUT • REGULATED :t15VDC FROM UNREGULATED DC INPUT • DIFFERENT DC INPUT VOLTAGE RANGES AVAILABLE • HIGH CURRENT CAPABILITY WITH CURRENT LIMIT PROTECTION • ISOLATED DC/OC CONVERTERS, 75% EFFICIENCY AT FULL LOAD , • LOW COUPLING CAPACITANCE (BpFI • HIGH ISOLATION VOLTAGE 11500VDCI • LOW EMI, SHIELDED AND UNSHiElDED UNITS • UP TO FOUR FULLY ISOLATED OUTPUT CHANNELS (Model 710) • SMALL SIZE 8-4 ACIDC CONVERTERS 5VOC Logic Supplies Dual ±15VDC Supplies PC Board Mount Model 550 551 552 Chassis Mount 554 553 556 55S PC Board Mount 560 561 562 RATED OUTPUT 5V('1 ±15V ±15V ±15V ±15V ±15V ±15V ±15V ±25mA ±50mA ±IOOmA ±200mA ±350mA ±200mA ±500mA 250mA Voltage (nom) Current (max) SVI1421 5V{'I(~1 SOOmA HioomA RATED INPUT Voltage 105 - 125VAC. 50 - 400Hz Options!ll 105 - 125VAC 50 - 400Hz E.F.H E. F. H REGULATION No load to full load (max) Over rated line ,voltage (max) OUTPUT RIPPLE AND NOISE At full load. rms (max) 105 - 125V AC. 50 - 400Hz E. F, H ±O.I% ±0.05% ±o.05% ±o.05% ±o.02% ±0.05% ±0.05% ±o.I% ±o.I% ±o.I% ±0.05% ±o.05% ±O.O5% ±o.05% ±0.02% ±o.05% ±o.OS% ±o.OS% ±o.05% ±o.OS% 2mV O.5mV O.SmV O.SmV O.SmV ImV ImV ImV ImV ImV DC/DC CONVERTERS :l1SVDC Output Isolated(6) Low Profile S46 700j700U(4) 71 -5 Equal Loa~ for ", iy ........;:: "" ~ Fixed Ou tpu t· ~ Varying- ~ Output '" J. ....... ........ '" " '" ,,/ Max Safe L.OJIoo. Load - ~ 10 20 30 40 SO Output Current (mA) FIGURE 1. Load Regulation. eo c .!l ~ Output Shield- '700 & 700M Only G,jd: 2.54mm (0.1") Pin: Pin material and plating composition NOTE: Input and Output circuits have separate shields. I ±3mA Loa1 ..... ~ 0 ,;'. ~ -I ';; o > H ... +... -v OUT K>1-~2~n~__~2N2219 ';i 't !:I + :?S MIL-ST0-883 (except paragraph 3.2), eo .:: +t+-- t!~t:::"' Output Common - conform to Method 2003 (solderability) of ~ z ~htl!t.+f.li++ ...... ++ .. - Material: Black Epoxy Weight: 22.67 gm (0.80 oz.) max G,jd: 2.50mm (0.10") NOTES: 1. Derate to 16V max between +Vin and -Vin above 70o e . 2. A medical grade unit is available which is 100% screened to Patient Connected Circuit requirements for the leakage current (par. 27.5) and dielectric withstand voltage (par. 31.11) Olf UL544. Specify 700M or 700UM. 4 ~ r+VOUT d.l~H++t:lli~t+tU~~:t ~!:.++t .. +V (0.40·) Operating g 3~ ~ 20.32mm ± V in with ± 1V tolerance 60 mA max. 120 mA max. TEMPERATURE RANGE ~ 1.02mm (0.040·)di •. 5.08mm (0.20·) OUTPUT V out @ ±3 to ±30 rnA Load, Operating Current total of both outputs Safe Nondestructive Current at 25°C Sensitivity to Input Voltage Load Regulation Ripple Volt'age @ ±3 mA Load Ripple Voltage @ ±30 mA Load Balance of +V and -V @ +I = -I -I~ 1"-· -2 I ~ ~ 10012 ~yoiAtat -55 -35 -15 +5 +25 +55+75 Ambient Temperature (0(') FIGURE 2. Temperature Drift. FIGURE 3. Short Circuit Protection. *For one output with constant 1S rnA load and varying cunent on other output. (A minimum load of 3mA is recommended for ea'ch output). Use with Isolation Amplifiers: When the Model 700/700U is used with isolation amplifiers such as the Burr-Brown 3650 and 3652 special attention should be given to current ratings to avoid over designing. Since the isolation amplifiers do not draw max. current simultaneously from the +V and -V Model 700/700U terminals, it is possible to drive more isolation amplifiers per Model 700/700U than one migh( initially expect, The Model 700/700U is capable of providing a total output current of 60 mA balanced Of unbalanced between the two outputs, A minimum load of 3 rnA is recommended for each output. 8-8 BURR-BROWN@ 710 1E3E11 QUAD-ISOLATED DC-TO-DC CONVERTER FEATURES • FOUR ISOLATED ±10VOC to ±lBVDC OUTPUTS • DRIVES FOUR 3650/3652 ISOLATION AMPS • HIGH BREAKDOWN VOLTAGE. 2200VDC TEST • LOW LEAKAGE CAPACITANCE. BpF • LOW LEAKAGE CURRENT. IpA @ 240V/60Hz • LOW COST PER ISOLATED CHANNEL APPLICATIONS • INDUSTRIAL PROCESS CONTROL • TEST EQUIPMENT • DATA ACQUISITION SYSTEMS DESCRIPTION The Model 710 converts a single IOVDC to 18VDC input into four dual isolated outputs of the same value as the input voltage. The converter is capable of providing a total of 76mA at rated output voltage accuracy and can provide isolated power to four independently isolated 3650/3652 optically coupled isolation amplifiers with the entire assembly mounted on one 5" x 7" card. Extensive use is made of hybrid integrated circuits to reduce size and cost. A self-contained frequency stable 130 kHz oscillator drives switching circuitry which is designed to minimize the common problem of spiking due to transformer saturation. International Airporllndustrial Park· P.O. Box 11400· Tucson. Arizona B5734· T91.16021 746·1111 . Twx: 910·952·1111 . Cable: BBRCORP . Telex: 66·6491 PDS-367A 8-9 DESCRIPTION OUTPUT CURRENT RATINGS ISOLATION VOLTAGE RATINGS The Model 710 is capable of providing a total of76mA of output current divided among its eight outputs. The maximum current available from anyone output is shown in Figure 9. A minimum average current of3mA is recommended for each output in order to maintain output voltage accuracy. Thus, the current may be balanced (such as +9.5mA and -9.5mA) or unbalanced (such as +l6mA and -3mA). The best output voltage accuracy will be obtained under balanced conditions. Channels may be connected in series or parallel for higher voltage or current. For parallel operation connection of channell to 2 or channel 3 to 4 will result in lowest ripple. In some cases the 710 may drive larger loads than would be apparent from a cursory examination of the specifications. For example, see Figures I and 2. The most total current drawn from the pair of +Vo and -Yo output is 1m.. + IQ (not 2 x l ma.). For the 3650 this is a !Ilaximum of 12mA +1.2mA = 13.2mA (instead of 24mA). It is important that the user understand the significance of t he continuous derated isolation voltage specification and its relationship to the actual test voltage applied to the unit. Since a "conti~uous" test is impractical in a product manufacturing situation (implies infinite test duration) it is generally accepted practice to perform a production test at a higher voltage (i.e., higher than the continuous rating) for some shorter length of time. The important consideration is then "what is the relationship between actual test conditions and the continuous derated minimum specification?" There are several rules of thumb used throughout the industry to establish this relationship. Burr-Brown has chosen a very conservative one: V"" =(2 x V,ontinuou. 13 > 11 r" 13to 0 9 > :; Q. .E 11 8 to 9 -<8 V+EXT t6mAto 30mA >30mA 1.3kll 82011 51011 82011 51011 2oo11 51011 200n Oll 200n Oll ;: e § () > 13t----t----+----+-:-, 75~& 8. ~75 'E -I ~ S ~ g ~50 50~~ c: c5 8 I----\---.b"" ~ ~ ~~ . 7.5V 18 ~ 100 r------+---''''''.....;:-----+------\100~· E on 6.SV OUTPUT VOLTAGE VS INPUT VOL TAGE 125 ,...-----r------r----,-----,125 ~ From Any Single Output 13~0----~2~0----~40~--~60~--~8~0--~1~00 13~0----~2~0----~40~---60~--~8~0----'~00 Output Load Current, I ILl ,mA, Output Load Current. IL (rnA I Output load Current, IlL I rnA m PARALLEL OUTPUT UNBALANCED LOAD REGULATION PARALLEL OUTPUT BALANCED LOAD REGULATION OUTPUT·TO·OUTPUT INTERACTION iL V c g V ~ j IF > o ~ 15r-----t---~~----+_----+_--~ r V j ai r g o > ~ o ~ ~ 14r----l--~ Q. ;; 14 t----l""',;,:' o ~ ;; Q. :; o ai 0> S gISI---~~~~t-~~~ ;; Q. :; ~ ~ 14 ~ .!l o 'in 2o Q. 100 13~0----~4~0----~8~O----~12~O~--~1~60~--~200 Output Load Current, IlL I ,mA ,30L----4~O----~8~O----,~2~0--~1~60~--~200 Output Load Current" IL Notes: 111 Using a 104mm x 19mm x 1.6mm aluminum strip mounted to the bottom of the case with heat sink compound. 12, Total output current is the sum of the currents for each individual output. 8-16 mA 724 BURR-BROWN® IElElI QUAD ISOLATED DC/DC CONVERTER FEATURES APPLICATIONS • QUAD ISDLATED t8V DUTPUTS • MEDICAL EQUIPMENT • HIGH BREAKDOWN VOLTAGE. 3000V TEST • INDUSTRIAL PROCESS CONTROL • LOW LEAKAGE CURRENT. CRLF Blanks Display [01] CR [Z] LF CRLF Repeat 9-10 The generated in the computer will determine the length of time the displays are on. The display will remain blanked for the length of the transmission time of the display data. 165msec to 429msec. SERIAL INTERFACE The TM25 serial interface provides both EIA RS232Cj V.24 and 20mA current loop conditioning simultaneously. CONNECTOR A 25-pin female connector (type DB-25S) is provided on the rear of the TM25 (see Figure 5). Both the RS232Cj V.24 and 20mA current loop are available through this connector. The mating 25-pin male connector (type DB25P) with plastic shield assembly and mounting screws is available from Burr-Brown as 2525MC. The 2525 M C consists of: EIA RS232CIV.24 SPECIFICATIONS The EIA RS232Cj V.24 interface is a voltage signal. COMPUTER TO TERMINAL MARK = Logic I - -3V to -15V voltage level SPACE = Logic 0 - +3V to +15V voltage level TERMINAL TO COMPUTER MARK = Logic I - Nominal-IOV SPACE = Logic 0 - Nominal +IOV Interconnection TM25 Terminal to Computer Computer to Terminal I. Male HDP connector - 205208-1 2. Individual pins (solder connector) - 1-66506-0 3. Hand tool to insert pins in connector - 91067-2 4. Male screw retainer kit - 205980-1 5. Shield Assembly - 205718-1 The AMP Inc. part number is listed for each item. +15VDC Ground FI G U R E 6. E IA RS232Cj V.24 Interconnection Diagram. CURRENT LOOP SPECIFICATIONS The current loop is optically isolated. COMPUTER TO TERMINAL & TERMINAL TO COMPUTER MARK = Logic I - 20mA SPACE = Logic 0 - OmA FIGURE 5. TM25 Rear View. Connector Pinout Function Pin Numbe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Ground - Current loop Terminal to computer - EIA RS232CIV.24 Computer to terminal - EIA RS232CIV.24 Not used Interconnection There are two ways of connecting the TM25 current loop to a computer: I. External power source 2. Internal power source EXTERNAL POWER SOURCE (see Figure 7) Not used Not used TM25 Ground - Current,loop Not used Not used Computer Terminal to Computer Not used Current loop power (+) Terminal to computer - Current loop (+) Computer to terminal- Current loop Not used +15VDC power supply input Not used Not used Current loop power Not used Not used Not used Not used Not used (-) Terminal to computer - Current loop (-) Computer to terminal- Current loop FIGURE 7. Current Loop Interconnection Diagram with External Power Source. 9-11 MARK = Logic I - +O.4V SPACE = Logic 0 - +5V With an external power source, the TM25 is electricaIly isolated from the computer. INTERNAL POWER SOURCE (see Figure 8) TM25 To Computer +15VDC Computer 0'.,.,...-----1 Terminal .... to Computer Data In From Computer 1+----- +15VDC o-.M~----I Computer to Terminal Ht----f Data Out FIGURE 10. TTL Interface Diagram - Negative Logic. TRANSMISSION DISTANCE +t5VDC Power Supply TABLE VII. Transmission Standards Distance Limitations Conditioning RS232CIV.24 FIGURE 8. Current Interconnection Diagram with Internal Power Source. When using the internal power sources, of course, the TM25 is not electricaIly isolated. TTL Interface With external puIl upl puIl down resistors, the current loop will interface to TTL levels. POSITIVE LOGIC (see Figure 9) MARK = Logic I - +5V SPACE = Logic 0 - +0.4 V TM25 Current loop Maximum recommended transmission distance 15 meters (SO feet I 1500 meters ,5000 feet I A distance limitation for current loop that should ,be considered is the compliance of the loop power source. The forward voltage drop across the input diode is 1.5V max. The loop power source must be able to drive 1.5V plus the voltage drop produced by the resistance of the wire in the communications line. The resistance of wire Imm indiameter(#18AWG) is40 per 100-meter loop (130 per 1000-foot loop). The voltage drop caused by the resistance of the wire is 0.08V per 100-meter loop (0.25Vper 1000-foot loop). The resistance ofwireO.5mmindiameter(#24AWG)is 160 per loo-meter loop (510 per 1000-foot loop), so that voltage drop will increase by a factor of four. I-+----,.---To Computer 25011, '/4wIU MULTIDROP MODE 1-+_->'_ _ _ From Computar FIGURE 9. TTL Interface Diagram - Positive Logic. NEGATIVE LOGIC (see Figure 10) In the Multidrop Mode, a number of TM25's may be connected to the same serial link. Each terminal has a user-set drop address (0 - 99). Data transmitted to that address by the computer will be displayed by the desired terminal. The computer must poIl the terminals on a loop to check for data to be output. A TM25 wiIl ignore any transaction which is not directed to its addFess. If a parity error is detected in a transmission, the addressed terminal \viIl transmit an error message. When a transmission is received from the computer, the TM25 wiIl transmit an acknowledgement if no errors have been detected. 9-12 DISPLAY The display operates as in the single-drop mode. except that when the ENTER key is depressed. the digit display 'and any active function lights will blink until the computer polls the TM25 to allow it to transmit the data. When the data has been transmitted. the display will stop blinking. It will contain the data that was ENTERed. CR LF Carriage Return Line Feed # Start of Address Character Input Command > $ * KEYBOARD The keyboard is the same as in the single-drop mode. ENTER KEY The ENTER key operates as in the single-drop mode. except that when the ENTER key is depressed. the data entered is transferred to the output buffer. The data remains displayed in the digit display and function lights blink until the computer polls the unit to allow the data to be transmitted. After the microterminal transmits the data. the displays Will stop blinking. but the data will remain. CLEAR KEY The CLEAR key operates as in the single-drop mode. COMPUTER TO TERMINAL DATA TRANSMISSION SEQUENCE Computer to Terminal The following information is transmitted by the computer to a TM25: I # [ADRS] > [DDD] [Delimiter] [ZIZ,] [Delimiter] [Delimiter]: The delimiter may be a CR or LF [DDD]: The digit data may be hexadecimal or numeric regardless of the model of TM25 used. If function data [ZIZ,] is not sent. the first [Delimiter] may beCRLF orCRCR;[ZIZ,]and the second [Delimiter] are eliminated as shown below: I # [ADRS] > [DDD] CR LF I or I # [ADRS] > [DDD] CR CRI MINUS SIGN KEY The minus sign key operates as in the single-drop mode. COMMUNICATIONS PROTOCOL The serial interface transmits standard ASCI I characters with 20mA current loop and EIA RS232C i V.24 conditioning. Parity is even. All commands sent to a TM25 in the multidrop mode begin with the start of address character"#"(ASCII 43.). and two digits representing the terminal address. The command characters ">"(ASCII 76.) or'''?''(ASCII 77.) follow the terminal address. The ">" character indicates data is being transmitted to the terminal. The .",,, character indicates that the computer is polling the terminal (requesting information). COMMUNICATIONS TERMINOLOGY [ADRS] [DDD] Terminal Address - a 2-digit decimalnllmher hetween 00 and 99. Data to or from the 8-character digit display. Zero to eight characters plus optional imbedded decimal point may be transmitted. Leading minus sign is one character. If no characters are transmitted to the TM25. the digit display is cleared. The most significant digit is always transmitted first. Output Command Acknowledgement Parity Error The terminal will "turn off" the function lights with this transmission, If[DDDlis greater than 8 characters. all characters after the first 8 will be ignored. If [DDD] contains no characters. the digit display willbe completely blanked. There should be no hlanks hetween characters. .. Terminal to Computer If the data was properly received at the terminal. an acknowledgement will be sent by the terminal to the computer. If a parity error is detected. a parity error message will be sent by the terminal to the computer. If no transmission is received by the computer from the terminal. the data was not received. ACKNOWLEDGEMENT: # rADRSl $ CRLF PARITY ERROR: # [AD RS] * CRLF The acknowledgement will be sent within 30 communication bit times (IOOmsec) after transmission to terminal. The parity error message will be transmitted as soon as it is detected. (This can be during the original computer to terminal transmission.) If a terminal key is being depr\!ssed while the computer is transmittmg data to the termmal. the data wIll not be received and the terminal will not respond. TERMINAL TO COMPUTER DATA TRANSMISSION SEQUENCE Data to function lights or from function keys. On transmission to the terminal. ZIZ, may be O. I or 2 characters; if no characters. all message lights cleared; if one character. it is interpreted as Zl. In a transmission from the terminal. Zl and Z2 are always transmitted. Computer to Terminal The computer must ask for data from a terminal. It polls each terminal by sending this information: # [ADRS] '? [Delimiter] [Delimiter]: The delimiter may be CR. LF or CRLF There should be no blanks between characters. 9-13 Terminal to Computer The terminal responds by transmitting the data in its output buffer or a parity error message if a parity error was detected. [DDD] CR LF [Z,Z,] CR LF DATA: PARITY ERROR: # [ADRS] * CRLF The minimum [DDD] which can be transmitted to the computer is one character. For transmissions to the computer [DDD] consists of only. the numbers 0 - 9 for numeric keyboards and 0 - F' for hexadecimal keyboards. The terminal will respond within 30 communication bit times (100 milliseconds).' If a terminal key is being depressed while the terminal is heing polled. it will ilOt respond, ~ty error message will be transmitted as soon as it is detected. (This can be during the original computer to terminal transmission.) FUNCTION CHARACTERS Function characters are received and transmitted as in the single-drop mode. CHARACTER CODE The character code used is same as in the single-drop mode except. that parit~· is eyen. 2. I n all other cases, the data is transferred directly to the display after the [Delimiter] is received. The data in the display »,ill remain in the display until the terminal receives another input transmission from the computer or until data is entered from the keyboard. When data keys are depressed and then the ENTER key, the display will hlink uritil polled hythc computer. As digit keys are depressed, the character appears on the right-most position of the digit display. As subsequent keys are depressed, the previously entered characters move to the left while the most recently entered digit appears in the right-most position. This operation is simiiar to that of a calcullitor. DATA . . TRANSMISSION '. When the computer asks for d.ata (# [ADRS]? CR) the terminal. will transmit the contents of its output buffer. The data in the output buffer is not changed with an output transmission. If the computer continues to ask for data, the same information will be sent each time until new data is ENTERed from the keyboard (i.e., until the ENTER key is depressed). (The data in the output buffer remains the same even if the CLEAR key is depressed.) OTHER All other operation isihe same as the single-drop mode. EXTRANEOUS CHARACTERS The TM25 will recognize ~'#" as the start of data transmission. Any ASCII character that occurs in the header during an input transaction, but which does. not conform .exactly to the input format specified, will cause the terminal to ignore the entire data transaction. SERIAL INTERFACE The data in[DDD], [Z,Z,], and [Delimiter] are treated as in the single-drop mode. See the Appendix. NUMBER OF TERMINALS PER LINE # [ADRS]? [Delimiter] # [ADRS] > [DDD] [Delimiter] Z,Z, [Delimiter] In the ahow transmissions from computer to terminal. I. # [ADRS] ? and 2. # [ADRS]> must be transmitted exactly as specified. OPERATION The TM25 in the multidrop mode is intended to be connected via a serial ASCII interface to a computer. DATE ENTRY AND DISPLAY A computer to terminal data input transmission will send data to the terminal's input buffer. I. If data keys have beeii depressed but the'ENTER key has not, the data transmitted to the terminal will remain in the input buffer. When the terminal's ENTER or CLEAR key is then depressed, the data will be transferred from the input buffer to the display. (If ENTER is depressed, the operator-entered data will be transferred to the output buffer to await an output command from the computer.) The serial interface specifications and connector are the same as in the single-drop mode. A number of TM25's can be connected in series on a 20mA current loop (see Figure 11). The number of terminals which can be connected on one communications line is limited by operational, and electrical considerations: Electrical Considerations. The forward voltage drop across the input diode is 1.5V max. The loop power supply must be able to drive 1.5V for each TM25 in series. Thus with four TM25's on a line, 6V'is required to drive the diodes. The current loop circuitry at the computer and the resistance of the wire in the communications line also producevoltagedrops.. Using the internal current source, up to eight terminals can be reliably operated on one communications line. Qp.erational Considerations. A typical data transmission to the terminal requires 0.4 seconds; terminals can be polled at a rate of six per second; a typical data transmission to the computer requires 0.4 seconds. The number of terminals on a single line should be such that you may update or poll at an adequate rate. I n addition, each computer to terminal transmission will cause the displays of all TM25's connected to the serial line to dim. Therefore, the number of computer to terminal transmissions (such as polling) should be minimized to reduce display dimming. 9-14 SPECIFICATIONS . SINGLE-DROP AND MULn.DROP DIGIT DISPLAY Number of Digits Type of. Digit Display Characters Displayed 8 plus decimal point 7 segment 0, " 2,3,4,5,6,7,8,9, A, B, C, 0, E, F, minus sign 7.6mm (0.3") Character Height FUNCTION LIGHTS Number of Lights Type 01 Light 7 Red, LED KEYBOARD Type of Keyboard Number of Function Keys Numeric or Hexadecimal 7 MATERIAL Front Panel Back Panel Case he front cover will be attacked ",y these chemicals. PVC plasticizing agents FIGURE II. Typical Multidrop Connection via Current Loop. . Amines DO NOT USE FLUOROCARBONS (TMC, Freon, etc., TO CLEANI The current loop interface of the TM25 multidrop terminal may be connected to a computer with only EIA RS232C serial ports by using the following EIA/ current loop converters. +5VDC ~~41127lkntOUT ElA RS232C RIC .IIPIlT .oUT 2II2Im +5VIIC CURIEIl LOOP OUT SERIAL INTERFACE IConditioning RS232C1V.24 and 20mA Currant LoOp 300 beud Baud Rate RS232C Output Voltage Logic 1 Logic 0 Input Vollage Logic 1 Logic 0 20mA Current Loop Input Forward Voltage Drop Output Safuration Voltage Breakdown Vollage -IOVOC +10VOC -3VOCto-15VDC +3VOC to +15VDC 1.5V max at 30mAI1.3V max at IOmA 1.3V max at 30mA 30V max_ TEMPEIlATURERANGE Operating Storage OOCto+,u-v ..woC to +85"C POWER SUPPLY Voltage Current .. I Polycarbonate Black Anodized Aluminum ABSPlastic Chlorinated or Fluorinated Hydrocarbons WEIGHT +15vu\,i'!:o'll! 250mAmax I 290 grams (10 OZ) ·'1 CUIIREJT LOOP MECHANICAL II Black FIGURE 12. EIA/Current Loop Converter. ADDRESS SELECTION Two dip switches accessable from the rear of the TM25 select the terminal's address. Any address from 0 to 99 can be chosen: Each digit is BCD encoded as shown below: ~ • • ,,, •• I I)Kili I I 2 I NOTE: Switches on some units may be numbered I throu~8. • ..• 7 N~ N A N A N A SA N A I • • I I 0 I 0 I 0 I , • , • • • ••• 0 I I 0 I I 0 I I 0 • I I 0 0 0 I I I I 0 I I I I 4 • • • • 0 0 0 0 I I I I I I I I ~t:=.. ======~8.51"-====~ ( Dimensions in inches. o..nlfng Screws: #4-40, 711tr - 6 Included wIth each TM25.Burr-Brown model25MK consIsts of sIx #4-40, 711tr mounting screws, if extras are needed. Mill!lmum allowable screw depth: 0.375" 9-15 APPENDIX other characters. ADDITioNAL CHARAcTERS Table Acl shows the'entire I28-character ASCII character set. As indicated in the Communications Protocol section. , transmission from the TM25 to the computer will be: I. [DDDJ: O~,9 (numeric or () - H hexadecimal). decimal p'iint. minus sign. 2.Z,:@.A-O 3. Z,: P - W These are the only characters whi,ch can be transmitted from a TM25. For transmission to a TM,25. the microterminal will respond to eXilctJy the same characters as shown above. ' that is: I. [DD[)]: () - 9 or () - 1-'. decimal point. minus sign. 2. Z,:@.A-O 3. Z,: P - W Table A-II shows the characters which will appear in the digit display fqr each ASCII character transmitted in [DDD]. Notice that all characters in columns I through 7 will appear as, characters 0 - F in the digit display. Any ASCII character from column 0 will be interpreted by the TM25 as a [Delimiter]. Table A-III shows the function lights which will be "turned on" or "turned off" by each ASCII character transmitted to the TM25 in [Z,Z,]. 'If for example. PQRSTUVW were transmitted to the TM25 as [DDD]. 01234567 would 'appear in the digit display, If II were transmitted to the TM25 as [Z,Z,]. function lights FI and F5 would light. The TM25 will also respond to other ASCII characters to. provide the same digit display (0 - F) and to turn on function lights if these characters are transmitted' to the TM25. For Multidrop version. the header protocol must be exactly as specified. The TM25 will not respond to any It is recommended for simplicity. that the computer transmit the same character set to the TM25 as the TM25 transmits to the computer. T ABLE A-I. ASCII Character Set. b, be 0 b3 b2 bl 0 0 0 0 ~ 1 0 1 0 1 0 bs b4 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1 2 3 4 5 0 NUL· DlE SP If @ P RD '1," 1 1 1 0 6 ... • 1 7 P 0 0 0 1 1 SOH DCl ! 1 A Q "0 0 1 0 2 STX DC2 " 2 B R b r 0 0 1 1 3 ETX DC3 # 3 C S c s 0 1 0 0 4 EOT DC4 $ 4 D T c , 0 1 0 1 5 ENQ NAK % 5 E U e u 0 1 1 0 6 ACK IlVN F V f v 0 1 1 1 7 BEL ETB . 6 7 G W 9 w 1 0 0 0 8 BS CAN I 8 H X h x 1 0 0, . 1, 9 HT EM I 9 I Y i Y 1 0 1 ,0 '10 IF SUB : J Z j z 1 0 1 1 11 VT ESC 1 1 0 0 12 FF FS i , 1 1 0 1 1 1 1 1 1 ; 1 13 CR GS 0 14 SO RS 1 15 81 US & + / 9-16 q ; K [ k < = > l \ I M J m N ,\ n - ? 0 0 DEL I 1 TABLE A-II. Digit Display Characters. b7 b6 bs b4 b3 b2 b, 0 0 0 0 0 0 ~ 1 0 1 0 1 0 1 0 1 1 2 1 0 4 3 1 1 1 0 1 1 0 1 6 5 7 AO NUL 0 0 0 0 0 DLE CR SOH 0 0 0 1 1 0 0 1 0 0 0 1 1 CR 0 0 1 1 1 0 0 1 0 1 0 3 CR 1 1 1 CR NAK 5 ENQ CR ACK SYN 6 7 0 0 0 0 0 1 9 0 1 0 0 1 1 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 C d - CR E N F F F d d E 1 I I f E a F A b C d - n 8 C m .\ 0 b C 7 E ? ! A I I 6 d > US CR M 9 z k b 5 C = 9 A , L 8 Y i [ 4 b C - RS SI 1 b 8 9 3 7 x I Z K < GS CR A ; 7 8 2 J 6 w h Y 5 v 6 7 1 9 A ... b CR SO 1 A FS CR 1 9 5 9 X I : ESC CR 8 9 ) 9 CR 11 8 H u f 6 0 7 8 SUB FF 1 8 CR 10 7 ( EM VT 1 7 4 4 5 W G 3 t e V F 6 7 CAN LF 1 6 3 4 E 2 s d U F 6 2 3 D E 5 5 & 6 CR 4 1 r c T 0 q 1 2 C P 0 b S D 5 ETB HT 1 5 CR 8 4 1 B 3 " a R C 4 % A 2 3 0 Q B 3 $ 4 CR BS 1 3 4 1 2 # DC4 BEL 0 2 P 9 A 2 DC3 EOT 0 1 DC2 ETX @ 0 1 1 CR 2 0 I DC1 STX 0 SP 0 E DEL F F This table indicates the character that will appear on the digit display for each ASCii character. 9-17 TABLE A-III. Z, and Z, Characters. b7 0 0 b3 b2 b, ~ 0 1 0 1 1 0 bs b4 0 0 0 be 1 1 0 2 1 1 0 1 1 0 3 4 NUL 0 0 0 0 0 0 0 1 0 1 0 CR OLE 0000 SP 0 DCl 0001 ! 1 SOH CR STX CR DC2 0010 # CR DC3 0011 $ 4 CR DC4 0100 NAK 0101 % 5 ENQ CR SYN 0110 & 6 ACK CR BEL CR ETB 0111 ( CR CAN 1000 ) CR EM 1001 CR SUB 1010 CR ESC 1011 2 ETX 0 0 1 1 3 EOT 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 7 BS 1 0 0 0 8 HT 1 0 0 1 9 LF 1 0 1 0 10 VT 1 0 1 1 11 1 0 0 12 1 0 1 13 1100 CR GS 1101 1 1 1 0 14 1 1 1 15 0101 0110 F G 0111 1000 H 1001 1001 : 1010 + 1011 1100 M 1101 1101 1111 1110 1111 1101 { ,, " 1011 1100 } 1101 1110 1110 1111 DEL 1111 0 1111 1010 1100 1101 1110 0 1111 1011 m .\ N ? 1111 1101 1110 1110 I 1010 1100 ) 1001 z k 1011 1100 1100 = 1001 \ L 1000 Y J 1010 1011 1011 1000 1001 [ K 0111 x i Z 1010 1010 ; 0111 1000 1001 J 0110 w h Y I 0110 0111 1000 1000 9 0101 v 9 X 0100 u 0101 0110 0111 0111 8 0100 f W 0011 t e 0101 0110 0110 7 0011 0100 V 0010 s d U 0101 010r 6 > US CR E 0010 0011 0100 0100 0001 r c T 0000 q 0001 0010 0011 P b S 0 5 0001 0010 7 0000 a R C 0011 0100 .- 0001 0010 4 0000 Q B 3 0011 1110 CR SI 1 2 RS SO 0001 ,0001 0010 . A < CR CR 1 .. 0000 1 6 .. P @ 0000 1 FS FF 1 iI 0000 1 0 5 ROW 0 1 1 0 This table indicates the function lights that will be "turned on" or "turned off" for each ASCII character. Z,: XXXX = F4 F3 F2 Fl Z,: XXXX = Don't Care F7 F6 FS 9-18 TM27 USER'S GUIDE BURR-BROWN@ IElElI International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona B5734· Tel. (6021746-1111 . Twx: 910-952·1111 • Cable: BBRCORp· Telex: 66-6491 PDS-469 9-19 INTRODUCTION up to eight characters plus decimal point. An 8-character display permits review and editing of data entered before' transmission. Thirty-six different characters can be displayed. Two 8-character message buffers are provided to hold output and input messages. ,The keyboard can be locked out by CPU command. Five LED indicators are independently controlled by the CPU. The five independent LED's are driven by TTLcompatible signals which are also available on the back panel connector. These may be used to remotely control external equipment such as audible annunicators. If your system's datal entry / control/ display requirements 'are sophisticated but limited in volume, you don't need to buy big, expensive, and fragile CRT's or printing terminals to do the job efficiently. The TM27 is a low cost approach to the problem of remote data entry, utilizing an RS-422 interface" to accommodate the use of a multiterminal loop arran:gement. While designed as numeric only entry, the availability offunction keys and lights, digital inputs and digital outputs, and the extended character set ofthe unit allows for a wide variety of responses and messages to be communicated. OPERATION The TM27 "microterminal" features a numeric/hexadecimal keyboard and display. The TM27 uniquely flexible in application versatility is designed expressly to fill the human interface demands of widely dispersed control and communications networks in factory data collection, machine and process control, energy management systems, inve'ritorycontrol,and information processing. DESCRIPTION Microterminals, because ,of their interface flexibility, appearance, size, durability, and easy installation, function equally well as consoles and control centers for instruments and small systems. They also perform as " input/ output terininals in diagnostic applications. You don't need interface expertise to, put the TM27 to work for you ... it communicates in serial ASCII with RS-422 conditioning. 'Baud rates are 300 to 4800 bits per second. The intended environment for this unit is "multidropped", host-controlled, polled operation. This operation is inherently half-ewrit~r-style keyboard and multiline display or hard copy output; The TM27 features a du~t ""Jof tront panel including a 2'I-key keyboard, 8-chatacte~ display, and five host,computer-controllable lightemitting,diodes (LED's). The keyboard features' raised embossing with tactile feedback. In additio'll, a 26~l?iJi, rear panel connector features RS-422 data, trlill!imi,t and data receive. The .- connectods also used to provide power, ~ommunications , rltteselection(300 to 4800 bps), remote reset in, and reset 6'ut address. The h6st-cpntrollable LED's are driven by rTL~compatible signals which ate brought out to the back panel connector. Up to six I-character function messages may be defined by the host system. Function messages may be transmitted to the host by pressing the front panel function message keys. For all following descriptions the terms input and output shall refer to inputto and output from the TM27. When the terminal receives a transmission, the data is stored in the input buffer and typically displayed. However, if keyboard data is being entered before the beginning of the host-to-terminal transmission, the input data will remain in the input buffer until either ENTER or CLEAR is pressed, at which time the input data will be displayed. The TM27's very compact design and simple mounting The TM27 utilizes a 12-character input buffer, allowing on any flat surface makes it quickly adaptable to new Or existing applications. It measures only 2l6mm x: 114mm " , the' reception of eight displayable characters and a x 15mm (8.5" x 4.5" x 0.6"). When ordered in ()l;M decimal point. The remaining three bytes are intended to quantities the front panel can contain your corporate or buffer commands from the host. This insures that the system logo. terminal can always respond to input, thus allowing the host to reset it if necessary. You can enter and, display numeric and hexadecimal data. A 21-key keyboard allows you to enter messages of As 'each key is pressed, it iseht~red into the output buffer 9-20 and the display but not transmitted. When the ENTER key is pressed, the output buffer is made ready for transmission, as indicated by the output pending LED. When the host sends the polling command ('Request Buffer,) while the output pending LED is on, the TM27 will transmit the buffer to the host. The buffer is prefixed by its 2-digit address to verify the source of the message. In the event there was an error in the transmission (wrong address, parity error, etc.), the buffer can be requested again by the "Retransmit Buffer" command. If the "Request Buffer" command had been sent again, a null message consisting of the terminal's two-digit address followed by a carriage return would be transmitted to indicate no new data had been entered. This distinguishes between repeated data and new data. When the host sends messages or commands to the TM27, they must be prefixed by two ASCII digits in the range 00 to 63. Address 00 is a special case which is accepted by all terminals addressed from 0 I to 63. This allows a single message to be received by all terminals on the multidrop line atthe same time. A number of microterminals may be connected to a single communications port using the RS-422 interface. OPERATING INSTRUCTIONS READY CONDITION When power is applied to the TM27, the display will show a "0." in the left-most character position as the ready indicator. In addition, pressing RESET and CLEAR will cause the ready condition to be entered. Note that in some installations the RESET key may be disabled when the unit is installed. RECEIVING AN INPUT MESSAGE When the TM27 receives an input message, it will appear in the display from left-to-right when the carriage return is received. The internal message buffer holds up to eight displayable characters. For input messages larger than eight characters, only the first eight characters are retained. The host system must terminate each input message with a carriage return (CR). The carriage return is not displayed in any way and is not included in the eight characters. When the' carriage return is received, the display will be loaded with the eight characters of the message. Receipt of another message after (CR) causes the input buffer to be cleared except for the characters of the new message. Also, if a character key is pressed to start an output message, the display shows the keyboard data only. COMPOSING AN OUTPUT MESSAGE As each character key is pressed, the displayed message grows from left-to-right. After eight keys have been pressed (nine characters including decimal point) the display is full. If more than eight characters are pressed, only the first eight are retained. The message may be edited by pressing CLEAR and inputting the message again. When the operator wishes to end the message, it is only necessary to press ENTER. When the ENTER key is pressed at the end of the line, the display remains until new data is entered from keyboard. FUNCTION KEYS The host system may define up to six l-character function messages to be stored in TM27 random access memory. The operator may send these to the host by pressing the A through F keys. When A through F are pressed prior to being defined by the host, the letters A - F are transmitted. Function messages may not be defined from the keyboard. NONDISPLAYABLE CHARACTERS AND MISCELLANEOUS INFORMATION When ASCII control characters (less than decimal 32) are sent to the TM27, they are not shown on the display. A function message may be any ASCII character greater than decimal 31. DETAILED KEY DESCRIPTIONS NUMERIC KEYS These keys are used for data input from the keyboard. Characters enter the display in the left-most position. After eight characters have been pressed (nine characters including one decimal point) the display is full. FUNCTION MESSAGE KEYS These keys are used to input function messages from the keyboard. The function message may be one of the default letters A through F or it may be one RAM based user-defined character. When no user-specified character definition has been provided, the one character default letter A-F appear. For output, the default letter will be transmitted unless the host has defined the function character. In this case the character will be transmitted as defined. The six function characters are put in the buffer by pressing the A through F keys. RESET The RESET key allows the TM27 operator to initialize the internal functions. Pressing RESET is equivalent to turning on the power. Pressing RESET will cause RAM based message definitions to be initialized to the powerup default characters. A "0." will be displayed in the left-most display position. This key may be disabled at installation. ENTER KEY ENTER is used to enable transmission with a trailing carriage return. 9-21 CLEAR Pressing CLEAR causes the current data in the display to be cleared. Function LED's and defined fUnction messages are unaffected. If no input message is waiting for display, a "0." appears in the left-most display position in the response to pressing CLEAR. APPLICATIONS COMMUNICATIONS PROTOCOL CHARACTER CODES The TM27 sends and receives 7-bit, asynchronous ASCII character codes with a start bit, one parity bit (either even/ odd parity or marking), and at least one stop bit. When in marking state, the parity bit is ignored while receiving, but is set to a logic I while transmitting. Characters with parity error are ignored without notifying the host computer. PI jumpers select the data receive and transmit rate. This rate may be 300, 1200,2400 or 4800 bits per second. PI jumpers are described in the Installation section. Function codes are transmitted as defined or default to the letters A through F. Upon power-up or reset, function keys default to A through F, the keyboard is unlocked, and the display contains "0". ASCII codes less than 20 (hexadecimal) (32 decimal) are not displayed if part of a message. Other codes that are sent as part of a message but not defined in the character set of this terminal have no defined indicator and may appear in the display in any form. To insure that the display does not contain meaningless patterns, the user must make sure only codes defined in the character set are transmitted as part of a message. Examples of compatible host to TM27 connections: HOST 1. 7 bits + 2 stop bits 2. 7 bits + parity + 1 stop bit 3. 7.bits + parity + 2 stop bits 4. 7 bits + mark space + 1 or 2 stop bits TM27 7 bits + mark + 1 stop bit 7 bits + parity + 1 stop bit 7 bits + parity + 1 stop bit 7 bits + mark + 1 stop bit Remember that since communications are asynchronous and the standby state is the marking state, extra stop bits and marking bits are always acceptable. When parity is disabled, the TM27 does not test for parity bit mark or space on input. CARRIAGE RETURN For an input message, the TM27 requires that the message be terminated by a carriage return. Carriage return is not counted as one of the input characters. FUNCTION MESSAGES Function messages l-character in length may be defined by sending XX(ESC)Dz(a)(CR). The z represents the function message number I through 6. The"a" represents any ASCII character greater than decimal 32. Defined messages may be deleted by sending a new definition or XX(ESC)Dz(CR). XX(ESC)DO(CR) deletes all function message definitions. XX is the two-digit address between 00 and 63. The display buffer shows the defined function character when a definition is present in RAM. The defined function message is transmitted on output. When no message has been defined, A through F is shown in the display. COMMAND DESCRIPTIONS The TM27 accepts 12 different types of Escape (ESC) sequences which serve as special commands. to the TM27. These commands consist of character strings starting with the 2-digit address followed (shown as XX below) by the ASCII control character (ESC) and terminated with it carriage return (CR). Intervening characters form the particular command. XX is a decimal number from 00 to 63. XX(ESC)A(CR) The A command polls the TM27 for any new output message which has been entered from the TM27 keyboard. This command may be used only once per message. If another A command is sent before a new message is ready, XX(CR) will be the reply indicating an empty buffer. XX(ESC)B(CR) The B command polls the TM27 for a message in its output buffer. It may be used to cause the TM27 to transmit one entered message any number of times until new data is entered from the keyboard. XX(ESC)C(CR) The C command will clear the input buffer allowing for the input of new data regardless of the previous contents of the buffer. XX(ESC)Dz(a)(CR) The D command used with a message is used to define function characters in the TM27's RAM. The z can be any number character from I through 6 for function characters I through 6. When "a" is not included in the escape sequence, the z function message definition is deleted. If z eq uals 0, all function message definitions are deleted. When function messages are deleted from RA M, they assume the default values A through F. "a" must be an ASCII code above decimal 32. XX(ESC)EYn(CR) The E command controls the function lights: when n= I, turn on function light; when n=O, turn off function light. Y is the number of the function light. Only values of Y from 1-5 are valid arguments, all others are ignored. XX(ESC)Hp(CR) Parity control. For p=O, marking; for p=l, odd parity; p=2, even parity. Default is marking parity. XX( ESC)Jn(CR) The J command will lockout keyboard entry (n= I) until it is turned off (n=O) or reset occurs. XX(ESC)K(CR) The K command transmits the contents of the input buffer. This permits comparison between what the terminal has received and what the host has sent as a check on communications lines and circuits. 9-22 XX(ESC)LD(CR) The L command controls turnaround delay. D is in the range of I to 9, corresponding to 10msec to 90msec turnaround delay. Default is IOmsec. XX(ESC)N(CR) The N command reads the three TTL inputs. The TM27 response is XXr(CR) where r isa value betweenOand 7. r is the octal representation of the three digital inputs (II, 12,13). .L .11 Q 11 0 I 2 3 4 5 6 7 0 0 0 0 I I I I 0 0 I I 0 0 I I 0 I 0 I 0 I 0 I XX(ESC)T(CR) The T command effectively resets the terminal. All buffers are cleared, the display is reset, function lights are turned off, and keyboard activity is interrupted. Function definitions are not altered and the keyboard will not be unlocked if previously locked. XX(ESC)U(CR) The U command combines the operation of the A command and the N command. The U command polls the TM27 for any new output message that has been entered from the keyboard and also reads the three TTL inputs. The TM27 response to the U command is XX(MESSAGE)(CR)XXr(CR). xx is the 2-digit address of the TM27. r is a value between 0 and 7. r is the octal representation of the three binary inputs (bl, b2, b3) as described above. PROTOCOL Computer to Terminal XX(message(CRI XX(ESCIA(CRI XX(ESCIB(CRI XX(ESCIC(CRI XX(ESCIDZa(CRI XX(ESCIDZ(CRI XX(ESCIDOrCRI XX(ESCIEYn(CRI XX(ESCIHp(CRI XX(ESCIJn(CRI XX(ESCIK(CRI XX(ESCILD(CRI XX(ESCIN(CRI XX(ESCIT(CRI XX(ESCIU(CRI Input (messagel lor display Transmit request Retransmit request Clear input buffer Define function as "8" Clear function Delete all function messages Function light and TTL output Y control Parity control Keyboard lock control Remote enter Turnaround delay Read TTL inputs Clearsll Reads transmit buffer and TTL inputs Terminal To Computer XX(MESSAGEIICRI XX(CRI XXnCRI thus if more than one terminal is on the loop a polling command with address 00 should not be transmitted. 2. Function definition "a" limited to one character (any ASCII code above decimal 32 acceptablel. 3. n=O is off (disable leaturel n=1 is on (enable leaturel. 4. Parity p isO t02. 5. Y is a number from 1 to 5. 6.0 is turnaround delay. Values of 1 to 9 are valid. 7. Z is a number from 1 to 6. INSTALLATION The TM27 is connected to a flat panel surface with six #4-40,7/ 16-inch machine screws using the mechanical dimensions given in the Specifications section. A connector cutout should be provided as indicated in the Mechanical Dimensions illustration. BACK PANEL CONNECTIONS The front panel RESET key is disabled until RESET IN and RES ET OUT are connected by a soldered jumper on the back panel mating connector. Figure I shows the 26-pin connector PI. Table 1 is a listing of pin functions for connector PI, Table II is the baud rate table, and Table III is a listing of Polling Addresses. ~~--------------~~~"Dmffi" SQUARE POST PINS PROTRUDE 0.12" FROM BACK PANEL FIGURE I. 26-pin Connector PI Back-Panel View. TABLE I. List of Connector PI Pins. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 PIN FUNCTION GROUND +POWER SUPPLY +OUT rRB-422 I L 1 (Digital Outl -OUT (RS-4221 L2 (Digital Outl -IN (RS-4221 11 (Digitallnl +IN (RS-<4221 121Digitallnl L3 (Digital Outl RESET IN GROUND 14 15 16 17 18 19 20 21 22 23 24 25 26 13 (Digital IN r L4 1Digital Outl RESET OUT b2 (Digital Out I AO TABLE II. Baud Rate Selection. Response to (ESCIA,B,K commands Response to (ESC1A,B,K commands if buffer is empty Response to N command NOTES: 1. XX are any decimal digits. Only multidrop addresses in the range from . 00 to 63 have any significance. 00 as an address is special in that any and all terminals will respond regardless of their preset address. Caution, all terminals will transmit a message if polled with address 00, FUNCTION BAUD RATE B1 300 1 1 1200 1 0 BO 2400 0 1 4800 0 0 1 = connect to power supply . 0= connect to ground. 9-23 AS Ai A4 ~ §II A3 Bl GROUND TABLE III. Polling Address Selection. powered from the same power supply and on the same wire, the length of' wire' is reduced proportionally. Therefore, with two TM2Ts in basically the same location, the length of power supply wire is reduced to one-half. The'following chart indicates the maximum length of power supply wire possible with specific numbers of TM27's at the end of the wire assuming a 12VDCpower supply. Each TM27 is assumed to draw 0.25A. '.j".- POLLING ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - - - Ai; M ,A3 A2 Al Ao 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 0 Universal Address SIZE OF WIRE 1 0 1 0 1 0 ·· ·· ·· ·· ·· ·· ·· · · · · · · · 63 1 1 1 'I 1 1 NUMBER OF TM2Ts 2mm (#12AWG) lmni (#18AWG) O.Smm (#24AWG) 1 1600m/4800' 400m/1200' l00m/300' 2 80Om/2400' 200m/SOO' SOm/1S0' 4 40Om/1200' l00m/300' 2Sm17S' 10 160m/4SO' 4Om/120' 10m/30' 20 8Om/240' 20m/60' Sm/IS' Maximum power supply wiring distance. 1 = connect to power supoply, 0= connect to ground. The maxiqlum power supply voltage applied to the TM27 should be linearly derated from 12VDC at ambient temperatures of 40°C to IOVDC at 60°C as shown below: +5VoC CPU iifsET 12V RESET FRONT PANEL KEY , Maximum Power Supply ,,'....... mn 'wt------------------~ ltv ----------------------. , I I ' .' I. I I FIGURE 2. Reset in and Reset Out Equivalent Circuit. POWER SUPPLY The power supply voltage range accepted by the TM27 is SVDC to 12.YDC. The power supply voltage is this wide a range to allow straightforward distribution oflow voltage operating power. Above 40°C, the maximum power supply voltage applied to the TM27 is linearly derated to IOVDC at 60°C. The 8VDC to l2VDC range allows for use of a power' supply with little regulation and! or for tho power supply voltage drop of the power lines. The length of line from the power supply to the TM27 determines the voltage drop. The voltage at the TM27 must not be les's than SVDC. For example, the resistance of wire Imm in diameter (# ISA WG) is 40 per IOO-meter loop (SO for a 600-foot loop). The TM27typically'draws 0.25A. The voltage drop caused by the current is I V (40 x 0.25A) per 100-meter loop (2V for a 600-foot loop). The resistance and voltage drops of wire 2mm in diameter (# 12A WG) is one-fourth of the above numbers. With a 12VDC power supply, the wire resistance voltage drop must be limited to 4V or less. Therefore, with one TM27, a 400-meter (l200-foot) loop of I mm diameter (# ISA WG) copper wire is the longest run possible. If 2mm diameter (# 12A WG) wire is used, the distance can be four times as great: 1600 meters (4S00 feet). If more than one TM27 is 9-24 If the power supply voltage applied to a TM27 exceeds the recommended levels shown above a resistor must be inserted in series with pin 2 to reduce the power supply ' voltage at the terminal as shown below: 12VoCSUPPLY ,l ~R 2~ TM27 #1 I c§.tR ~ 2 TM27 #2 ' 2 • TM27 , #N' , S4rlBl RBlllIDr IRI uod If amblant tampentura Blellda 400C and.lf POWII . supply voltagl.pplfad to TM27axcaadi IDVoC. The series resistance value (R) should typically be a 50 resistor to reduce the power supply voltage by up to I V Or a 100 resistor to reduce the voltage by up to 2V,ln the example above, assume the power line voltage drop to units #1 and #2 is approximately IV with a 12VDC, power supply; this means that the voltage applied to these units is about II V, Therefore, a 50 r,esistor should be used to provide another I V drop to each TM27 if the ambient temperature exceeds 40°C. With unit #N, however, assuming the power line voltage drop is 3V, the power supply voltage applied to the TM27 is9VDC and no series resistor is required at any temperature. MECHANICAL DIMENSIONS SPECIFICATIONS :~~~ZED DISPLAY NumbEtr of Characters Internal Buffers: Input Buffer Output Buffer Type of Digit Display Character Height I ~LASTIC ABS ALUMIMUM " / 4=-:-~ , 8 Characters 8 Characters 7 Segment LED 7.6mm (0.3"1 TYPICAL OF SIX MOUNTING HOLES. #4-40 INSERT 0300 BACK VIEW___ i==r-r ~2~~ 3.900 4j FUNCTION LIGHTS Host-Controlled Lights Type of Light 3.700 ~ KEYBOARD Type of Keyboard Number of Function Keys User-Programmable 8.51 '--------'t'-r-c~~~ Numeric, A-F 6 Ves, One Character Each 1= 0.12 MATERIALS Front Panel Back Panel Case The front panel will be attacked by these chemicals: ACCESSORIES 26-pin Mating Connector - 2026MC ORDERING INFORMATION TM27 is the full part number for the TM27 SERIAL INTERFACE Transmit +OUT (pin 31 -OUT (pin 51 --ov- Space (Logic 01 ""+'5\f +5V OV OV +5V +5V OV Receive :'iNiPin 71 +IN (pin 91 Baud Rate Parity Bit Number of Terminals per Serial Interface Communications Delay Maximum Transmission Distance RS-422 300. 1200. 2400. 4800 Even. Odd. Mark 1 to 63 1msec between messages 1200 meters (4000 feet I TEMPERATURE RANGE Operating Storage O°C to +60o C· O°Cto +60°C POWER SUPPLY Voltage Range O"C to +4O"C +4O°C to +60°C Current 8VDC to 12VDC 8VDC to 10VDC· 250mA typical 300mA max WEIGHT 290 grams (10pz,1 o.iro " None 5 at 1LSTTL Load TTL-Compatible RS-422 Signal Levels Mark (Logic 11 . OPTIONS Chlorinated Hydrocarbons Fluorinated Hydrocarbons PVC Plasticizing Agents Amines DIGITAL OUTPUTS Conditioning 0 500 DIMENSIONS ARE IN INCHES, SHIPPED WITH SIX #4-40 1118 -INCH PAN HEAD SCREWS. Polycarbonate Black Anodized Aluminum ABSPlastic DO NOT USE FLUOROCARBONS (TMC. FREON. ETC.I TO CLEAN! Digital Outputs -2.12!;' 3J108 ~~12'42 4.250 --0.555 Red. LED *between +40°C and +600C the maximum applied power supply voltage should be linearly derated from 12VDC to 10VDC. 9-25 APPENDIX ASCII AND DISPLAVABLE CHARACTERS The ASCII coded character set is to be used for the general interchange of information among information processing systems, communications systems, and associated equipment. The characters to the right of the slash are the characters which are displayable by the TM27. Transmitting nondisplayable characters from columns 2 through 7 to the TM27 will cause unpredictable characters to appear. Characters from columns I and 2 transmitted to the display will be ignored except for Escape (27 decimal) and Carriage Return (13 decimal). b7 0 ~ \ 0 0 0 bd.lllb! ~ 0 1 1 2 3 4 5 6 7 0.'-11 0/0 AIR ~I P 0 ~J ~ "I' p !.II a q ~/b c/ C; rl, siS T dId ul 'U e OLE 2 STX OC, ' DC2 , , 1 1 3 ETX 0 0 0 0 1 0 1 1 0 0 4 EOT DC3 DC4 5 8 ENO NAK ACK 1 1 1 7 BEL 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 0 8 9 , 1 1 1 , ,, , 1 NUL 1 1 0 SOH 0 1 1 0 1 0 0 1 0 0 " 0 1 1 ,, 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 SP I SPACE I "/,. • 2/2 al 3/3 CI D I 4/'"1 5/S a/EI ~I SYN $ 'lit & ETa 7/' G/ as 'I' CAN ( 8/8 HI HT EM J 9 '0 11 LF sua VT ESC 12 FF FS 13 CR GS 14 SO RS 15 SI US + , -1I ~ FI I I 19 I : ; J / L -/= > M ? NI n 010 I u/u • V f w x 9 w h/h x y I. Y z J z (/[ K < • I k \ III I I] m I '"-l n/ n a/ C I ~ DEL T. . ____ Conlrol (CTRL) characlers. I,e" CTRLX I. CAN, elc, DECIMAL EQUIVALENTS OF ASCII CHARACTERS Decimal Code ASCII Graphic Decimal Code ASCII G,aphic Decimal Code 000 NUL SOH STX ETX EOT ENO ACK BEL as HT LF VT FF CR SO SI OLE DCl DC2 DC3 DC4 NAK 022 023 024 025 026 027 028 029 SYN ETB CAN EM SUB ES FS GS RS US SP 044 045 I 055 001 002 003 004 005 008 007 006 009 010 011 012 013 014 015 016 017 018 019 020 021 LF = Line Feed. FF 030 031 032 033 034 035 036 037 038 039 040 041 042 043 = Form .. # $ % & ( ) + Feed. CR 046 047 046 049 050 051 052 053 054 058 057 058 059 060 061 062 063 ASCII Graphic - ASCII Graphic DeCimal Code ASCII GraphiC DeCimal Code ASCII GraphiC 088 B C D E F G H I 066 092 \ 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 n 091 X y Z [ 067 I 068 069 0 1 2 3 4 5 6 7 8 9 070 071 072 073 074 075 076 077 078 079 : 080 ; < 061 062 > 083 084 = ? 064 @ 065 A = Carriage Decimal Code 085 086 087 Return. DEI. 9-26 J K L M N 0 P a R S T U V W = Ruoout. 069 090 093 I 094 1\ 095 096 097 096 099 100 101 102 103 104 105 106 107 106 109 a b c d e f 9 h I j k I m 0 P q , s t u v w x y z { ,, I cv DEL TM70 AND TM76 MICROTERMINALS USER'S GUIDE BURR-BROWN® 1E3E31 Inlernallonal Airport Induslrlal Park - P_O_ Box 11400 - Tucson, Arizona B5734 - Tel. (6021 746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - Telex: 66-6491 l'I>S448 9-27 TABLE OF CONTENTS INTRODUCTION ............................................................... 9-29 OPERATION ...........•........................................................ TM70 General Description ....................................................... TM76 General Description ....................................................... Operating Instructions ........................................................... Detailed Key Descriptions ............................ 0' •• " • • • • • • • • • • • • • • • • • • • • • • • 9-29 9-29 9-30 9-30 9-31 APPLICATIONS .............. :., ................................................ 9-32 Communications Protocol .............' ......' .................................... 9-32 INSTALLATION ........... , ..........................•......................... 9-33 Back Panel Connections ......................................................... 9-33 Reset In and Reset Out Equivalent Circuit ......................................... 9-34 TM70 RS232C Electrical Specifications ....... .' ........... ,; ........................ 9-34 Current Loop Communications Wiring Connections ................................. 9-35 Current Loop Electrical Specifications ............... '..... ,. ; ...................... 9-35 Loop Power Source .......................... , .......... ,' ........................ 9-35 SPECIFICATIONS .. .'...........................•............. , ................. 9-36 OPTIONS ............................................... '........................ 9-36 ACCESSORIES ................................................................. 9-36 ORDERING INFORMATION .................................................... 9-36 APPENDIX ..................................................................... 9-37 ASCII Codes .............. ;.; .•............................................... 9-37 Displayable Characters ...........................•..............•............... 9-38 Communications Checkout Programs ................' .•........................... 9-39 Microterminal Option Connection Summary .. : .•. , ................................ 9-41 9-28 products productively. Most special features arc invisible to the operator. A typical application consists of a series of host-system-supplied operator prompts. To each prompt, the operator simply keys in a short number or message and pushes the ENTER key. The function message keys may be used to further simplify operator responses. INTRODUCTION If your system's data entry / control! display requirements are sophisticated but limited in volume, you don't need to buy big, expensive, and fragile CRT's or printing terminals to do the job efficiently. The TM70 "microterminal" features a full alphanumeric keyboard and display while the TM76 has an alphanumeric display and a simplified numeric keyboard with larger keys. TheTM70 and the TM76 - uniquely flexible in application versatility-are designed expressly to fill the human interface demands of widely dispersed control and communications networks - in machine' and process control, energy management systems, inventory ,control and factory floor data collection, and ,information processing. Microterminals, bec/luse of their interface flexibility, appearail(~e, size, durability, and easy installation, function equally well as consoles and control centers for instruments and small systems. They also perform as I 0 terminals in diagnostic applications. OPERATION TM70 GENERAL DESCRIPTION The TM70 is an alphanumeric "microtcrminal" '\\ hich may be used as a remote or local data cntry and output terminal for a host computer system. It is intcnded to' provide a low cost, small si/e. altcrnati\'c to a CRI terminal. It is suitable for applications with a limited amount of data interchange. as compared to applications requiring a typewriter-style keyboard and multiline display or hard copy output. The TM76 is the samc as the TM70 with the exception that it features a simplified numeric-only keyboard with larger keys. You don't need interface expertise to put microterminals to work for you ... they communicate in serial ASCII with RS232C or 20mA current loop conditioning. Baud rates are 300 or 1200 bits per second. The TM70 features a dust proof front panel including 52 characters on a 42-key keyboard. 12-character alphanumeric display. two host-computer-controllable light emitting diodes (LED's), and three status LED's. Thc keyboard features raised embossing with tactile fcedback. In addition. a 25-pin, D-style, r.ear. panel conncctor features RS232C and current loop data transmit and data receive. The connector is also used to providc power. communications rate selection (300 or 1200 bps). remote reset in and reset out. and parity selection. The hostcontrollable LED's, labeled A I and A2 on the front panel. are driven by open collector lTi. signals which arc brought out to the hack panel connector. A tough, water resistant front panel protects LED displays and indicators as well as a full alphanumeric keyboard. Tactile feedback, display blinking, and character display confirm operator entry and, because of its design simplicity, the microterminal concept doesn't require special operator skills or training. Depressing a single'function key initiates preprogrammed action by the CPU. These functions may be defined in your CPU's software. Up to eight 4-character function messages may be defined by the host system. After definition by the host. these messages arc called by the host for display by sending a 2-character code (ESC) I; where I may ha\'e the ",IIues I through 8. Function messages may be retransmittcd to the host by pressing the front panel function message keys. Thus. they may be used as extensions of the input message to the TM70 or as function messages to be tqlOsmitted by the TM70 operator to the host system. These microterminals' very compact design and simple mounting on any flat surface make them quickly adaptable to new or existing applications. All models measure only 216mm:; 114mm x 15mm (8.5" x4.5" x 0.6"). When ordered in 'OEM quantities the front panel can contain your corporate or system logo. You can enter and display alphanumeric data. A 42-key keyboard (shiftable to generate 52 characters including A-Z and 0-9) allows you to receive or enter messages up to 36 characters long. A 12-character display - with horizontal scroll-left or scroll-right keyboard controls permits review and editing of data entered before transmission in the polled mode. A 36-character message buffer is provided to hold output and input messages. For all following descriptions the terms input and output shall refer to input to and output from the TM70.lnternal operation of the TM70 is easily conceived as a 12character display and 36-character message huffer. Thc display may he filled. under operator control. with any contiguous 12-character section of the message huffer. Display contents arc displayed to the operator through 12 alphanumeric I.ED characters. A host-sent command may he uscd to cause the 36-character message to continuously scroll across the display. The message buffer is handled difft;rently in non polled mode than in polled mode. Nonpolled mode and polled mode operation arc described in the following paragraphs. Display features include CPU control of scrolling. The keyboard can also be locked out by CPU command. Two LED indicators(A I, A2) are independently controlled by the CPU, three LED's indicate terminal status. The two independent LED's are driven by open-collector TTL signals which are also available on the back panel connector. These may be used to remotely control external equipment such as audible annunciators. NONPOLLED OPERATION In nonpolled operation as each character key is pressed. it is immediately transmitted without heing displayed. Therefore, it is necessary for the host to echo the key to It is important to realize that while the microterminal products including the TM70 and the TM76 have many features, normal operation is very uncomplicated. Virtually untrained operators can use the microterminal 9-29 the terminal for displllY. The ENTER key will transmit the ASCII CR (cllrriage return) character. Nonpolled operation is similar tolhe operation of a standard CRT terminal.. POLLED OPERATION In multidrop mode, as each key is pressed, it is entered into the buffer and the display and not transmitted. The host cannot echo characters in this mode. When the. ENTER key is pressed, the buffer is made ready for transmission, as indicated by the OUTPUT PENDING status LED. When the host sends the polling command ('Request Buffer') while OUTPUT PENDING is on, the TM70 will begin to transmit the buffer to the host. The buffer is prefixed by its.2-digit address to verify the source of the message. In the event there was an error inthe transmission (wrong address, parity error, etc:), the buffer can be requested again by the "Retransmit Buffer" command. If the "Request Buffer" command had been sent again. a null message would be transmitted to indicate no new data had been entered. This distinguishes between repeated data and new data. When the host sends messages or commands to the TM70, they must be prefixed by two ASCII digits in the range 00 to 15. Address 00 is a special case which is accepted by all terminals addressed from 01 to 15. This allows a single message to be received hy all terminals on the multidrop line at the same time. The 20mA current loops should be used in polled operation. See page 7 for suggested connections. A number of microterminals may be connected to a single communications port using the current loops. The number may be limited to less than 15 by electrical considerations on some circuits. At 10mA the forward drop across the output optical coupler transistor is 1.3V. Fifteen of these totaI19.5VDc' If the host current source comes from +12VDC, this obviously won't work. If -12VDC is available, 15 units can be connected as shown in Figure 5. TM76 GENERAL DESCRIPTION The TM76 is intended for those applications where an alphanumeric display terminal with numeric and function keydata input is adequate. The TM76 keyboard has the advantage that it is less complicated for the untrained or inexperienced operator. The TM76 is functionally identical to the TM70 except for the keyboard functions. The TM76 has larger, but fewer keys than the TM70. The TM76 offers a numeric (0-9) keyboard with function keys. Keyboard functions of the TM70 which do not appear on the TM76 are not available. The numeric keyboard and 2nd lights are unnecessary and have been deleted. Figures I and 2 show the front panels of the TM70 and TM76. The keys ofthe TM76 are 38% larger and placed on 0.65inch centers as compared to the O.5-inch centers of the TM70. This is the same spacing ru; used on touch tone telephones and allows operators with gloved hands to easily use the keyboard. As can be seen from Figures I and 2, the keyboard appears mpch larger and easier to use. For a description oftheTM76 key functions, refer to those same keys described for TM70 in the Detailed Key Descriptions section. All matters concerning control features, communications protocol, and product specifications not related to tlie keyboard are as for TM70. FIGURE I. TM70 Front Panel. FIGURE 2. TM76 Front Panel. SELF-TEST MODE The TM70 has provision for performing a self-test diagnostic routine. Self test is entered by holding down any key while RESET is pressed and released. The message 'RAML-...JROM'-J 1/0,--,' is put in the display buffer and the write/ read memory test is performed. If the memory test passes, a '+'is put after'RAM'; if there was a failure, a '-' is put in the display. Similarly, a program ROM checksum is calculated and compared with a ROM stored checksum. The same pass/fail indicator is displayed. The I/O is tested by a write/ read cycle to the internal 1/ 0 device, and a rotating test is performed on the Status LED's. This sequence is then repeated until RESET is pressed and released while no other key is pressed. This will allow the TM70 to perform a normal power-up. The TM70 is off-line and will not receive or transmit while in self-test mode. Self test can be accomplished only if the back panel connector reset jumper is connected between pins 19 and 21. OPERATING INSTRUCTIONS READY CONDITION When power is applied to the TM70. the display will show 9-30 the ready indicator. which i, a /\ in the left-most character position. In addition. pressing RESET and CI.EAR \\ ill cause the ready condition to be entered. Note that in "Ulle installations the RESET key may be disabled when the unit is installed. RECEIVING AN INPUT MESSAGE When the TM70 receives an input message. it will appellf in the display from left-to-right until the 12-chanll:ter display is filled. After 12 characters the message will scroll to the left .as each character is received. The internal message buffer holds up to 36 characters. For input messages larger than 36 characters. only the first 36 characters are retained. The host system must terminate each input message with a carriage return (CR). The carriage return is not displayed in any way. When the carriage return is received. the display will be reloaded with the first 12 characters of the message. In most installations this will appear to happen instantaneously. When an input message has been received. it may he examined by using the message control keys ROJ.. ROR. -. and-. These cause a message up to 36 characters in length to move left and right in the 12-character display. Their functions are further described in the detailed key descriptions. Receipt of another character after (CR) causes the display and message buffers to be cleared except for the characters of the new message. Also. if a character key i, pressed to start an output message. the display and message buffer are cleared of the preceding input message. During normal operation an input message replaces any previous output message. The host may clear the di,play and message buffer by sending a message consisting 01 a single blank and a carriage return. COMPOSING AN OUTPUT MESSAGE As each character key is pressed. the displayed message growslrom left to right. After 12 keys have been pressed. the message scrolls to the left. All characters arc retained until 36 characters have been pressed. If more than 36 characters are pressed. only the first 36 arc retained. The message may be edited by pressing CI.EAR and inputting the message again or by using the delete key. DEI.. Note that upper labels are entered by first pressing 2nd. prior to .each upper label. When the operator wishes to end the message. it is only necessary to press ENTER. When the ENTER key is pressed at the end of the line. the next character entered will cause the message and display buffers to be cleared except for the first character of the new line. FUNCTION KEYS The host system may define up to eight 4-character function messages to be stored in TM70 random access memory. The operator may send these to the host hy pressing the FI through F8 keys. When FI through F8 arc pressed prior to being defined by the host. &z (z = I through 8) is transmitted. Function messages may not be defined from the keyboard. NONDISPLAYABLE CHARACTERS AND MISCELLANEOUS INFORMATION When nondisplayahIc ASCII characters arc M;nt to the TM70. they arc not shown on the display. Howe\Cr. function messages may contain IHlIl~isplayahlc characters. which will be transmitted correctly hut di,played as :H when buffered in multidrop mode. Thi, applie, to all 128 characters of the ASCII set. The decimal point takes a full character position. DETAILED KEY DESCRIPTIONS ALPHABET AND SPECIAL r:Jn CHARACTER KEYS ~~ etc. These keys arc used for data input from the keyhoard. To enter the upper character. press the 2nd key prior to each upper character. Characters enter the display in the leftmost position. After 12 characters have been pressed. previous characters move one character position to the left when a new character is entered. ALPHABET AND NUMERIC KEYS ~~ etc. These keys are used to enter characters from the keyboard. The upper characters arc entered hy pressing 2nd prior to each upper character. This is called the Alpha mode. An alternate mode is called 1'I:umeric mode. In this mode ihese upper characters may be entered by only pressing the key. In the Numeric mode pressing 2nd first will cause the lower character to be entered. The keyboard is put in 1'I:umeric mode by pressing the A ]I; key. The ~umeric Keyhoard LED is on while the keyhoard is in ~umeric mode. To exit 1'I:umeric mode press A 1'1: again. Alpha mode is the power-up and Reset mode. FUNCTION MESSAGE KEYS 00 etc. These keys are used to input function messages from the keyboard. The function message may be one of the default strings &z or it may be a RAM based user defined string. When no user specified string definition has heen provided. the two characters of the default string appear. For a user defined value. th·e one to four characters of the string definition appear in the display. The z denotes I through 8 for function messages I through 8. All function messages are transmitted to the TM70 on the communications line as (ESC)z. For output. the default string will be transmitted unless the host has defined the function message. In this case the message will be transmitted as defined. The eight function messages are put in the buffer by pressing the F I through F8 keys or by the host transmitting (ESC)z. When no message has been defined by the host. default strings appear in the display as &z. The z will be I through 8 for a total of eight values. FUNCTION MESSAGE AND 1-11-'1 DISPLAY CONTROL KEYS ~~ etc. These keys. when used as function message keys. arc the same as the previously defined function keys. When used 9-31 • with the 2nd key. they move the display buffer to the right-most 12 characters (-l. or to the left-most 12 .chamcters (_). of the message buffer. DISPLA V CONTROL AND TERMINAL CONTROL KEVS@@ ROL/ROR . Pressing ROL will cause the message to move one character position to the left or until the last character of the message being examined is in the right-most position of the display. PressingROR causes the message to move one character to the right or until the first character of the message under examination is in the left-most display position. When held down. ROt and ROR auto-repeat. ESCAPE When RO.L is prefixed by 2nd. the ASCII control code (ESC) is produced. In multidrop mode this is displayed as :tf. CONTROL When ROR is prefixed by 2nd. the next alphabetic character is converted to the corresponding ASCII control code which in multidrop mode is displayed as 1:1. RESET.I The RESEt key allows the TM70 operator to initiali(e the internal functions. Pressing RESET is equivalent to turning on the power. Pressing RESET will cause RAM based message definitions to be initialized to the powerup default strings. The ready indicator (1\) .will be displayed in the left-most display position. This key may be disabled at installation. RESET is also used to enter self-test mode. see page 2. SECONDKEVG The .second key. 2nd. is used to enable the upper labels of those keys having upper labels. For example. the key sequence QJ causes+U to be tran~mitted. When the keyboard is in Alpha mode as indicated by the Numeric Keyboard status LED being off. ~ causes 2 to be transmitted. Pressing 2nd prior to a key which has no upper label causes the lower label to be transmitted and the internal 2nd mode cleared. as indicated by the '2nd' LED going off. G W G @ SPACE AND DELETE Space causes a space to be transmitted.The action of the DEL key depends on the mode. In normal mode the DEL key causes the ASCII DEL character to be transmitted when it is pressed. If the host echos the DEL back to the TM70. the last character in the buffer will be deleted. In multidrop mode the DEL key will delete the last character held in the buffer if there is one. ALPHA/NUMERIC KEVEl Pressing the A; N key causes the keyboard to enter the Numeric mode. The upper white on black labels become lower labels not requiring the 2nd key before entry. The lower labels become upper labels and require· the use of the second key for entry. The front panel Numeric LED comes on to indicate the keyboard. is in Numeric mode. Press AI N to return to Alpha mode. Alpha mode is also the power-up and reset mode. ENTERKEV8 ENTER is used to terminate an output message with a carriage return in normal mode and to enable transmission with a trailing carriage return in multidrop mode. See also the sections on Polled and Nonpolled Operation. CLEAR8 Pressing CLEAR causes the message buffer and display to be cleared. The Numeric Keyboard LED goes off meaning the terminal is in Alpha mode. A I. A2 LED's and defined function messages are unaffected. RESET has the same function as CLEAR. but in addition clears A I. A2 LED's and defined function messages. The ready indicator (1\) is displayed in the left-most display posit.ion . in response to pressing clear. APPLICATIONS COMMUNICATIONS PROTOCOL CHARACTER CODES The TM70 sends and receives 7~bit. asynchronous ASCII character codes with a start bit. one pariiy hit. and two stop bits. One. onc and one-half. or two stop bits will be accepted for input. When parity is disahled. a mark or space. as determined by I} I jumpers. is inserted for the parity bit. Parity may be even or o'dd and is selected bv jumpers on P I. Characters with parity errors are displayed as::tl. These jumpers also select the ·data receive and transmit rate. This rate may be 300 or 1200 bps. PI jumpers are described in the Installation section. Examples of compatible host to TM70 connections: Host TM70 1.7 hit.s + 2 stop bib 2. 7 bits + parity + I Joowp hit .l. 7 bils + parity + 2 lItop bib 4. 7 bib +. mark !'opal't,.' + I or 2 stnp hilJoo 7 bits + mark + 2 stop bils 7 ~its + parity + 2 stop bits 7 bits + parity + 2 stop bits 7 hils + mark space+ 2 stop bilS Remember that since.communications are asynchronous and the standby state is the marking state. extra stop bits and marking bits are always acceptable. The TM70 does not test for bit 8 mark or space on input. CARRIAGE RETURN For an input message. the TM70 requires that the message of up to 36 characters in length be terminated by a carriage return. Carriage return is not counted as one of the input characters. FUNCTION MESSAGES Function messages of up to four characters in length may be defined by sending (ESC) Dz(MESSAGE)(CR). The 9-32 represents the function mcssage numher I through K. Defined messages may he deleted hy sending a new definition or (ESC) D z(CR). (ESC) D O(CR) deletes all 'function message definitions. (ESC) In (CR) To call a function message. the host sends (ESC) I within a normal message or merely (ESC) I (CR). This causes the function message to he entered into the 36-character message huffer. The display hutler show, the defined function message when a definition is present in RAM. The defined function message is tntnsmittcd on output. When no message has hccn dcfincd. &1 is shown in the display. &1 is also transmitted in an output message when no function message has heen defined. INPUT MESSAGE SUMMARY Host CPU to TM. I. When n = I the TM70 keyhoard is locked out. The keyhoard is enahled if n = O. (MESSAGE) (CR) (ESC) A(CR) (ESC) B(CR) (ESC) Dz (MESSAGE) (CR) (ESC) Dz (CR) ESC) DO (CR) COMMAND DESCRIPTIONS The TM70 accepts nine different types of Escape (ESC) se4uences which serve as special commands to the TM70. These commands consist of character strings starting with the ASCII control character (ESC) and terminated with a carriage return (CR). Intervening characters form the particular command. (ESC) A (CR) The A command polls the TM70 for any new output message which has been entered from the TM70 keyboard. This command may be used only once per message. (ESC) B (CR) The B command polls the TM70 for any new or old message in its output buffer. It may be used to cause the TM70 to transmit one entered message any number of times. (ESC) Dz (MESSAGE) (CR) The D command used with a message is used to define function messages in the TM70's RAM. The z must be any number character from I through 8 for function messages I through 8. When the MESSAGE is not included in the escape se4uence, the z function message definition is deleted. If z e4uals O. all function message definitions are deleted. When function messages are deleted from RAM, they assume the default values &1.. (ESC) En (CR) This command is used to setthe A I LED on or off. If n = I. the LED is turned on. It is turned off for n = O. The back panel AI TTL output is pulled low when the LED is on. (ESC) Fn (CR) This command serves for A2 as the previous E command does for AI. (ESC) Gn (CR) When n = I the display continuously scrolls through the message buffer. Scrolling is stopped with n = O. (ESC) En (CR) (ESC) Fn (CR) (ESC) Gn (CR) (ESC) In (CR) ; input message ; re4uest huffer ; retransmit huffer ; define function message ; delete function message ; delete all function .messages ; output to A I LED ; output to A2 LED ; set scroll mode ; set keyboard lockout NOTE: Parenthesis are not actually encoded. Shown for copy clarity only. No imbedded blanks allowed. Lower case letters represent variables. OUTPUT MESSAGE SUMMARY TM to Host CPU. (Character) ; response to pressing a .key in nonpolled mode. (MESSAGE) (CR) ; response to ENTER key.(ESC) A (CR). or (ESC) B (CR). (CR) ; response to (ESC) A (CR). when output buffer is empty or has previously been accessed with (ESC) A (CR). (ESC) B (CR) may be used to ohtain previously transmitted messages. If the buffer has been cleared or reset. (CR) is transmitted in response to (ESC)B (CR). NOTES: I. I. = function message number I through 8. 2. n = control character. 0 = off. I = on. 3. I n polled mode all messages. commands. and replies will have a 2-digit address prefix (see Polled Operation section). INSTALLATION The TM70 is connected to a flat panel surface using six. 4-40. 7 i 16-inch machine screws using the mechanical dimensions given in the Specifications section. A connector cutout should be provided as indicated. BACK PANEL CONNECTIONS The front panel RESET key is disabled until RESET IN and RESET OUT are connected by a soldered jumper on the back panel mating connector. The communication rate may be set to 1200 bits per second by connecting pin II to the ENABLE pin. If pin II is left unconnected. the communication rate will be 300bps. Parity and word 9-33 format may be selected by connecting pins 9 to .10 to the. ENABLE pin as indicated by the. zeros in Table I. Logic one is obtairied by leaving the pin uncorinected. The. format is 7 bits plus a mark. space or parity bit: Remember that the communications are asynchronous; therefore. it is always acceptable to have more than the required number of stop and/ or marking bits. TABl.. E III. Setting the Baud Rate. Pin I '- 1 0 TABl E IV I..istingofConnector PI Pins . SeeNote Pin 4 1 2 3 4 5 6 5 5 1 4 1 -v Accepts #4-40 screw 1.852 (REF) eo 300 1200 Nonpolled operlltion is obtained by having AO through AJ open. This represents address 0000. Polling address 0 I is obtained by connecting AO to ENABLE. Connector wiring for PI (see Figure 3) may be accomplished with the aid of Tables I. II. III. and IV. .r--13 Baud Rate ' 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 JX(OOOOO-OOOOOOO_O] • I~ \OOOOOOOOOOOOJ~ 25 14 2 Prolrudes 0.3 inches Irom back panel Mates with· TWR Cinch DB·25P Burr·Brown 2525MC The 2525MC conSists 01 the loIlowing AMP Inc. part numbers: 3 6 3 1. Male HDP conneclor . 2052D8·1 2. Individual pins Isolder conneclor) . 1·66506-0 3. Hand 100110 Insert pins In connector· 91067·2 4. Male screw retslner kit· 205980-1 5. Shield assembly • 205718·1 7 FIGURE 3. 25-Pin D Style Cqnnector PI - Back Panel View. TABLE I. Setting the Parity Bit. PI PO Parity Bit 0 0 Even 0 1 Odd 1 0 Space 1 1 Mark Logic 1 is open. Logic 0 is jumpered to ENABLE I pin 2,. Stop bits: " 1·1/2, or 2 bits on input 2 stop bits on output. Parity errors displayed a.,:H. Mark/space not detected on input. Logic 1 = Mark 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Ali Al } RS232C OUTPUT INPUT PO PI eo ENABLE INO CONNECTION, +5VDC -IN +IN -OUT +OUT RESET IN DATA TERMINAL READY RESET OUT } AD A1 A2 As' 20mA Current Loops OUTPUT } Polling Address NOTES: 1. A 1 and A2 are logic low 1< O.4V at 1.6mA sink t when LED is on. 2.0 = Jumper to ENABLE ,pin 12,; 1 = Open, for PO, PI and BO. 3. To enable RESET, jumper between RESET IN and RESET OUT. 4. Supply RTN and Signal RTN internally connected. 5. Pins 4 and 5 are internally connected. 6. Pin 20 is internally connected to +12V through 1500f!. 7. Nonpolled mode is address 0000 with pins 22 through 25 open. 1 = Jumper to ENABLE. 0 = Open. RESET IN AND RESET OUT EQUIVALENT CIRCUIT +5VOC ZOkn 1 1L047~F TABLE II. Polling Address Selection. Polling Address Function Supply RTN TX RX REQUEST TO SEND CLEAR TO SEND Al LED Signal Ground A2 LED 'Xl! 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 Logic 1 is jumpered to ENABLE Logic 0 is open :G T CPU RESET RESET FRONT PANEL KEY oNonpolled 1 RESET IN a 1 0 1 0 1 0 1 0 1 RS232C ELECTRICAL SPECIFICATIONS Input Equivalent Circuit: RX a 1 0 1 I pin 121 MARK <.3.OV SPACE>+3.OV 9-34 +5VOC CURRENT LOOP ELECTRICAL SPECIFICATIONS Output Equivalent Circuit: 68011 Input Voltage Drop Short circuli protected Output Currenl (ahart circuli to groundl > +.3mA Input Minimum Current lOrnA MARK 0;; .fi.OV with 3tUlIoad SPACE;;, +6.OV with 3tUlIoad Input Maximum Current J5mA Output Voltage Drop ,;;; 1.3 V at 10mA ,;;; I.W at 20mA ,;;; I.4V at 35mA Maximum recommended transmission distance is 15 meters (50 feet). Output Current Minimum 20mA CURRENT LOOP COMMUNICATIONS WIRING CONNECTIONS Output Voltage Drop x Output Current must be ,;;; 250mV. TM70 units may be connected to one or more hosts by using the two 20m A current loop circuits. Optical coupling devices are used to electrically isolate TM70 from these circuits. Figures 4 and 5 illustrate connections to typical host communications circuits. :~I2VOC - -- r -- - - ---- -~ I - 1 I 1 1 1 1 +OUT +IN 47011 ·IN I I I 1 1 I -=I - I ·IN 1C: 1 +OUT 1 1 I 1 ~C:I I 1 1 ·OUT 1 TM70 'FIGU RE 4. Single-drop Connection - Polled or Nonpolled Operation. ,-----------------, +l2VDC I : I I 4700 The forward voltage drop across the output transistor is 1.3V maximum. The loop power source must be able to drive I.JV plus the voltage drop produced by the resistance of the wire in the communications line. 1 -----------I L_______ :HOST Maximum recommended transmission distance is 15UO meters (5000 feet). A distance limitation for current loop that should he considered is the compliance of the loop power source. 1 +IN I I Maximum applied voltage is JOVDe. LOOP POWER SOURCE I 1 +12VOC Output Current must be limited by the external cin:uit. --j I ·OUT I :.".l ,;;; I.W at 35mA ,;;; 1.2V at 20mA ,;;; 1.2V at 10mA + : The resistance of wire I mm in diameter (#18AWG) is 4ll per 100-meter loop (13ll per 1000-foot loop). The \oltage drop caused by the resistance of the wire is 0.08\' per 100-meter loop (0.25V per 1000-foot loop). The resistance of wire 0.5mm in diameter (#24AWG) is 16ll per 100c meter loop (51ll per IOOO-foot loop). so that voltage drop will increase by a factor of four. The sum of output transistor drops and wire resistance drops must be held within the compliance range of the current supplying circuit. As an example. with 10 microterminals and 1000 feet of# 18AWG wire. the loop powersupply must be: 10 terminals x 1.3V per terminal = I3V plus 0.25V for wiring for a total of 13.25V. OUT • ,- -- ---j ~: #15 '- I I I ~: .... _____1 FIGURE 5. Multidrop Connection - Polled Operation. 9-35 SPECIFICATION'S DISPLAY Number of Characters Internal Buffer Type of Digit Display Character Height FUNCTION LIGHTS Host Controlled Lights Status Lights Type of Light 12, alphanumeric 36 characters 16 segment 3.6mm (0.14") 2 3/1 Red, LED KEYBOARD Alphanumeric! Numeric Type of Keyboard Number of Function Keys 8 Yes, up to 4 characters each User Programmable MATERIALS Polycarbonate Front Panel Back Panel Black Anodized Aluminum Case ABS Plastic The front panel will be attacked by these chemicals: Chlorinated or Fluorinated Hydrocarbons PVC Plasticizing Agents Amines DO NOT USE FLUOROCARBONS (TMC, FREON, ETC.) TO CLEAN! TTL OUTPUTS TTL Outputs SERIAL INTERFACE Conditioning Baud Rate Parity Bit Number of Terminals per Serial Interface Communications Delllys Maximum Transmission Distance RS232C! V.24 20mA Current Loop RS232C Output Voltage Logic I Logic 0 Input Voltage Logic I Logic 0 20mA Current Loop Input Forward Voltage Drop I.3V max at 30mAj t.2V max at 20mA Output ,Saturation Voltage I.3V max at20mA 'Breakdown Voltage 30V max TEMPERATURE RANGE O"Cto +60"C Operating O"C to+60"C Storage POWER SUPPLY Voltage Current +SVDC±S% 6()()nA max 290 grams (10 oz.) WEIGHT MECHANICAL DIMENSIONS BLACK ANODIZED ALUMIMUM ABS PlASTIC TYPICAL OF SIX MOUNT INS HOLES. 84-«1IN8£RT rlr 3JOII 2 at I LSTTL Load Open collector RS232C! V.24 and 20mA Current Loop 300, 1200 Even, Odd, Space, Mark I to IS None - TM70j76 do not require delays between messages or commands, IS meters (SO feet) 1500 meters (SOOO feet) OIMENSION. ARE 'IN INCHES. SHIPPEO WITH SIX 84-«17/18-lilCH PAN HEAD SCREWS. OPTIONS None ACCESSORIES -IOVDC +IOVDC -3VDC to +ISVDC +3VDC to +ISVDC 2S-pin Mating Connector - 2S2SMC ORDERING INFORMATION TM70 is the full part number for the TM70 TM76 is the full part number for the TM76 APPENDIX AMERICAN NATIONAL STANDARD CODE FOR INFORMATION INTERCHANGE This coded character set is to be used for the general interchange of information among information processing systems. communications systems. and associated equipment. b7 0 ~ Bits b. b:J b2 b, a a a a a a a a a a a a a 1 a 1 a a 1 1 1 a a 1 a 1 1 1 a 1 1 a a a a a 1 a 1 a a 1 1 1 a a 1 a 1 1 1 a 1 1 1 1 1 1 1 1 1 1 I 0 0 0 a a 1 0 0 1 a 1 1 I 1 1 0 1 1 0 a 1 1 1 a 5 6 7 a Q 1 ~ a NUL OLE SP a @ P 1 SOH DCl I 1 A D 2 STX DC2 2 B R b r 3 ETX DC3 # 3 C S c s 1 2 3 4 ROW. 1 1 P 4 EDT DC4 $ 4 0 T d I 5 END NAK % 5 E U e u 6 ACK SVN & 6 F V f 7 BEL ETB 7 G W 9 v_ w ( 8 H X h x ) I V Iy SUB . 9 J Z I Y z + : ; [ k I 8 BS CAN 9 HT EM 10 LF 11 VT ESC 12 FF FS 13 CR GS 14 SO RS 15 SI US K / ? / T'-.- - - - - Control, CTRL L , M I I I m I N A n 0 - a - DEL characters. I.e., CTRLX IS CAN, etc. DECIMAL EQUIVALENTS OF ASCII CHARACTERS DeCimal Code 000 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 ASCII Graphic Decimal Code ASCII Graphic Decimal Code NUL SOH STX ETX EDT ENO ACK BEL BS HT LF VT FF CR SO SI OLE DCl DC2 DC3 DC4 NAK 022 023 024 025 026 027 028 029 030 031 032 033 034 035 036 037 036 039 040 041 042 043 SYN ETB CAN EM SUB ES FS GS AS US SP ASCII Graphic . 044 045 046 047 048 049 050 051 052 053 054 055 056 # 057 9 $ 058 059 : ! % & 060 061 / 0 1 2 3 4 5 6 7 8 < = > I 062 I 063 ? 084 + 065 @ A Decimal Code ASCII Graphic Decimal Code ASCII Graphic Decimal Code 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 B C 0 E F G H I 088 089 090 091 092 093 094 095 096 097 X Y 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 082 083 084 085 086 087 J K L M N 0 P 0 R S T U V W LF = Line Feed, FF = Form Feed, CR = Carriage Return. DEL = Rubout. 9-37 098 099 100 101 102 103 104 105 106 107 106 109 Z [ \ I /\ a b c d e f 9 h i j k I m ASCII Graphic n a P Q r s t u v w x y z II I I cv DEL DISPLAYABLE CHARACTERS " DD DI "D' D6D5 D4 01 0 0 0 0' 0 0 0' 0 , 0' , 0 0' , , 0 , '0' 0 ,, 0 0 , , , , , 0 1 13 gj % ~y -" II \ * I -- ,-, ,, J L 3 v, eJ 6 1, U , B 0J -- - t_ -- -~ -J, --.-, c ,C- r0 , _u "D .-, ev L JJ L •. LJ n , ,--., , -'-,- vT ~{ '--, , , ,\I LJ T C , u, , v , , F' UI,1 F? _J -, , , L"7 '-r -' I \ I + I I I I \ I , 00 0 , 00 , 0 --I 1\/1 ,\I /I 0 \I \I \ \ 1\ 1\ NOTE: All nondisplayable characters entered from keyboard are displayed as 9-38 VII -I I ~/:':". COMMUNICATIONS CHECKOUT PROGRAMS The following programs are provided as examples of short programs written in high lcvellanguages which might he used to verify that a TM70 is properly connected to a computer communications port. They i1re not intended as full applications programs, although they might be used as seeds for the development ofa particular application. The BASIC programs were tested at 300 baud. Depending upon the speed of the particular BASIC installation. the programs mayor may not he ahk to keep up at 120U baud. This is due to the fact that the polling program inputs and outputs one character per statement. Thc non polled BASIC program should work at the higher data rate since it receives and then echoes character-by-charac:tcr as the operator presses each TM70 key. The third program is written in FORTRAN. It reads and writes entire character lines and works at higher data rates. However, it uses calls to two system programs that are available on many Digital Equipment Corporation PDP 11/34 RSX-II M systems. They are GETADR and WTQIO. GETADR finds theaddresscs of LINE and POL variables. WTQIO sends the polling command and reads the command immediately. It is not intended that these programs will work in systems other than the ones for which they were written. Howe\c!". programs of similar brevity should be possible with any computer system. The nonportahility of the programs is due to their use ofvariou,; system features. The BASIC programs use a terminal driver callcd AT: to iniliali/e the communications port. The FORTRAN program uses calls 10 system-supplied subroutines GETADR and WTQIO. CHARACTER ECHO FROM BASIC 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 OPEN "0"#1, "AT:'''SET UP UART: AT: MUST BE LOADED FROM SYSTEM LEVEL REM FILE "TM70S" USED TO VERIFY COMMUNICATIONS CO]'l;]'I;ECTIO:'l; TO TM70 REM NONPOLLED OPERATION IS ASSUMED REM REM ..................................... MAIN PROGRAM ................................... . REM REM LOOP UNTIL A CHARACTER COMES IN AND THEN ECHO THE CHARACTER REM SUBTRACT 128 SINCE TM70 SETS BIT 8 IF(lNP(229) AND 1)<> I THEN (JOTO 150 C = INP(224) -128 OUT 224,C REM DELAY TIL CHARACTER IS TRANSMITTED FORJ= I TO 20 NEXT J GOT090 STOP END The numbers 224 and 229 are Ii 0 addresses for the communications port. • 9-39 POLLING TM70 FROM BASIC 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 OPEN "0". #1. "AT:"SET UP THE UA~T; AT: MUST BE LOADED AT SYSTEM I.EVEI. REM FILE "TM70P" USED TO VERIFY COMMUNICATIONS CONNECTION TO TM70 REM POLLED OPERATION ASSUMED DIM ('(36) REM REM ..........................., .......... MAI,N PROGRAM ................................... . REM REM POLL FOR INPUT GOSUB 380 REM GET INPUT LINE GOSUB 270 REM PRINT INPUT LINE. BUT SUPPRESS ADDRESS AND CARRIAGE RETlJR'" FOR J = 3 TOI ' PRINT CHR$ (C(J)); NEXT J REM PRINT CARRIAGE RETURN IF MORE THAN ADDRESS HAS BEE'" RECEIVED IF(I>3) THEN PRINT CHR$( 13) GOT090 STOP END REM REM .................................. LINE INPUT RduTINE ....... '.......................... . REM REM TEST INPUT STATUS AND LOOP TIL A CHARACTER IS RECEIVED REM SUBTRACT 128 SINCE TM70 SETS BIT 8 REM RETURN WHEN CARRIAGE RETURN IS FOUND I= I IF(lNP(229) AND I) <> I THEN GOTO 320 C(l) = INP(224) -128 IF«,(I) = 13) THEN GOTO 330 I= I+I GOTO 280 RETURN REM REM ....................•............... POLLING ROUTINE .................................. . REM REM TRANSMIT THE SEQUENCE OI(ESC)A(CR) TO POLl. TM70 OUT 224,48: GOSUB 440 OUT 224.49: GOSUB440 OUT 224.27: GOSUB 440 OUT 224.65 : GOSUB 440 OUT 224.13 : GOSUB 440 RETURN REM REM ....................... DELAY TIL CHARACTER IS TRANSMITTED ...................... . REM FOR K = I TO 20 NEXT K RETURN Note that the OI(ESC)A(CR) sequence is accomplished by outputting 48. 49. 27. 65. 13 to the I 0 address 224. These numbers are merely the decimal equivalents of the ASCII binary values of the corresponding characters of the tables on page 7. For example. 0 is given as 0110000 = i + 2' = 32 + 16 = 48. The numbers 224 and 229 are I 0 addresses of the communications port. 940 POLLING TM70 FROM FORTRAN This program was run on DEC's FORTRAN IV under RSX II M version .1.2. The program continuomly pol" a I M70 addressed as unit I. Any new message from the terminal will he printed on thc console until thc mc"agc STOP is rCL"ci\cd. this ends the program. The TM70 is connected to the host computer as terminal 17 (IT 17:). It uses thc systcm supplicd subroutine GETADR to obtain the address of the I.INE and 1'01. variables. The system supplicd subroutinc WI 010 sends the polling message and receives the response immediately. PROGRAM TMDEMO INTEGER PARAMS(6).TEMP(2) 1.0GICAI.*II.INE(80).POI.(5) DATA PARAMS(2) 80 .PARAMS(.1) 0 .PARAMS(5) 5 .I'ARAMS(6) 0 DATA POI.(I) '0' .POI.(2) '1' ,1}01.(3) 27 .1'01.(4) 'A' .1'01.(5) U CALL GET ADR(TEMP.I.INE.POL) PARAMS( I )=TEM P( I) PARAMS(4)=TEMP(2) C ASSIGN TERMINAL 17 AS LOGICAL DEVICE 6 CAl.L ASSIGN(6:TTI7:') WRITE(5.IOO) 100 FORMAT(,POl.I.ING TERMINAL I') C MAIN PROGRAM - POLl. TIL "STOP" IS RECEIVED 200 I.IN E(3)=' , CALL WTQI0("4400.6 ..1 ... PARAMS) IF (I.INE(.1).EQ.") GOTO 200 WRITE(5.260) I.INE 260 FORMAT(",80AI) IF (L1NE(.1) .NE:S') GOTO 200 IF (LINE(4) .NE.'T') GOTO 200 IF (L1NE(5) .NE:O') GOTO 200 IF (LINE(6) .NE:P') GOTO 200 STOP END MICROTERMINAL OPTION CONNECTION SUMMARY The RS232C and 20mA current loop pin connections are contained in the rear panel DB-25 connector. All options are selected by interconnecting pins on the same connector. The option selections are summarized below. The DB-25 connector pinout is shown in Table IV on page 6. All other tables referred to below are also on page 6. Parity Parity selection (pins 9 and 10) is shown in Table I. With both parity pins open. the microterminal will operate with Mark parity. Baud Rate Baud rate selection (pin II) is shown in Table III. With pin II open. the microterminal will operate at 300 baud. Polling Address Polling address selection (pins 22, 23, 24, and 25) is shown in Table II. With all polling address pins open. the micro terminal will operate in the non po lied mode. 9-41 TM71, TM77, TM71-I/O, AND TM77-I/O MICROTERM.INALS USER'S GUIDE BURR-BROWN@) IElElI l......naU....1Alrpart IndUllrll1 Plrk· P.O. Box 11400· TuclDn. Arlmnl85734· Tal: (1102] 748-1111 • Twx: 916-952·1111 • C.ble: BBRCORp· Taln: 66-8491 PDS433A 9-42 TABLE OF CONTENTS INTRODUCTION •••.•••.•••.••..•.•............•.•........•.•••••.••..•.•.••.•• 9-44 OPERATION .••.••..•..•..••.•..•..•..•.....••..•••••••.••••••••••••....•..•... 9-44 Description .•••••••••••••••.•..••..•..................•..•..•......•..••.•••..• 9-44 Detailed Key Descriptions •..•..•..•.••••••.......................•.............. 9-47 APPLICATIONS ••.••...........•.....•..•..•..•..•...•..•..•..••..•..•.......•• Control Features .•............•..•..••.••••..•••••.••.•••••.•••.•.••••.•••••..• Communications Protocol •.....•..•..•.•.•••.••.' ••..•.••..•.••...•.....••..••••• User Programmable Read Only Memory (PROM) .........................•..••.••• 9-50 9-50 9-52 9-54 INSTALLATION ...•..•.......•.......•.........•.••.••••••••.••...••••..••..•.. Current Loop Communications Wiring Connections .•..•..••.•.••......•..•...•.••• Current Loop Electrical Specifications ...........' ................................. RS-232-C Electrical Specifications ..•..............•••••.•••••.••..••••..•.•..•.. User PROM Installation Instructions .•. , .••.•..•.••..•..•.....•.........•..•••.•• Mechanical Dimensions ...•..•........•..•......••..•..•...•.••..•...•.••.••..•• Power Requiremen!S •....•.....•..•.••....•.....•...............•............... Environmental Specifications ......................•.....•..•.•..•...•....•••.... Factory Options .•...............•...•..........•...•...........•.....••....... Accessories ...................................................•......•..••..... Ordering Information ..............................................•...... '...... 9-55 9-56 9-57 9-57 9-57 9-58 9-58 9-58 9-58 9-58 9-58 APPENDIX ................................................. " ................. ·.9-59 9-43 INTRODUCTION If your system's data entry / control/ display requirements are sophisticated but limited, you don't need to buy big, expensive and fragile CRT's or printing terminals to do the job efficiently. "Microterminals" - uniquely flexible in application versatility -are designed expressly to fill the human interface demands of widely dispersed control and communications networks - in machine and process control, energy management systems, inventory control and factory floor data collection, and information processing. Microterminals, because of their interface flexibili~y, appearance, size, durability, and easy installation, function equally well as consoles and control centers for instruments and small systems. They also perform as 1/0 terminals in diagnostic applications. You don't need interface expertise to put microterminals to work for you ... theycommuriicate in serial ASCII with RS-232-C or 20mA current loop conditioning. Baud rates range from 110 to 19,200. A tough, water resistant front panel protects LED displays and indicators as well as a full alphanumeric keyboard. Tactile feedback, display blinking, and character display confirm operator entry. Buffered data features reduce on-line input/ output time with the CPU and improve accuracy of operator inputs. And, because of its design simplicity, the microterminal concept doesn't require special operator skills ortraining. Depressing a single function key initiates complex preprogrammed action by the CPU. These functions may be defined in your CPU's software or in local read only memory, for ~hich a socket is provided. This user's guide describes four products: TM71, TM77. TM71-I/Oand TM77-I/O. All units feature SO-character buffers, a 16-character alphanumeric display, and serial ASCII interface. The TM71 and TM71-ljO provide alphanumeric keyboards. The TM77 and TM77-I/O provide numeric keyboards. The I/O versions, TM71I/O and TM77-1/ 0, provide additional TTL inputs and outputs for interface to external equipment. Microterminals' very compact design and simple mounting on any flat surface make them quickly adaptable to new or existing applications. All models measure only 216mm x 114mm x 15mm (S.5" x 4.5" x 0.6"). When ordered in OEM quantities the front panel can contain your corporate or system logo. You can enter and display alphanumeric data. The TM71's 42-key keyboard (shiftable to generate SO characters including A-Z and 0-9) allows you to receive or enter messages up to SO characters long. A 16character display - with horizontal scroll-left or scrollright keyboard controls - permits review and editing of data entered belore transmission. In the edit mode you can backspace and advance the cursor position and insert and delete characters. Two SO-character buffers are provided for keyboard generated data. The output buffer holds a message bemg written. reviewed or edited; the transmit buffer holds a prepared message ready for CPU acceptance. This feature allows a second message to be prepared while the first awaits transmission. Similarly, two SO-character buffers are available for incoming CPU-generated messages. The receive buffer holds an incoming message until it can be transferred to the input buffer where it is displayed for the operator's action. With this feature, the operator can visually review a CPU input while a second instruction from the CPU can be received and held until called up for display. DisphiyJeatures include CPU control of scrolling, flashing. or blanking. The keyboard can also be locked out by CPU command. Two LED indicators are independently controlled by the CPU while four LED's indicate terminal status. The TM71-10 and TM77-I/O have an additional eight i'ndependently controlled LED indicators as well as two back panel I/O ports. It is important to realize t'hat while these microterminal products have many features, normal operation is very uncomplicated. Virtually untrained operators can use the microterminal products productively., Most special features are invisible to the operator. A typical application consistS of a series of host-systertJ-supplied operator prompts. To each prompt the operator Slimply keys in a short number or message and pushes the ENTER key. the function message keys may be used to further simplify operator responses. :Function key messages may be transmitted immediately on depression;, OPERATION DESCRIPTION The four models described in this user's guide are TM71. TM77. TM71-I/Oand TM77-I/O. All models operate in basically the same way. They are described below. For simplicity'S sake, only the TM71 will be referred to after the description section. For all matters concernmg control features. communications protocol. user PROM. and product specifications not relating to the keyboard or I/O ports. all units are identical. TM71 The Model TM71 is an alphanumeric "microterminal" which may be used as a remote or local data entry and output terminal for a host computer system. It is intended to provide a low cost, small size, alternative to a CRT terminal. It is suitable for applications with a limited amount of data interchange. as compared to applications requiring a typewriter-style keyboard and multiline display or hard copy output. The TM71 features a dust prooffront panel including SO characters on a 42-key keyboard, 16-character alphanumeric display, two host-computer controllable, light emitting diodes (LED's), and four status LED's. Character height is 0.14". The keyboard features raised embossing with tactile feedback. In addition. a 25-pin, D-style rear panel connector features RS-232-C data transmit. data receive, and modem control functions. The connector is also used to provide power. baud rate 9-44' selection (llO, 300, 600, 1200, 2400, 4800, 9600, 19200 bps), remote reset in and out, parity selection, a polling address, and 20mA current loop. conceived as five buffer memories as indicated in the block diagram in Figure I. In addition, function messages are stored in a separate RAM 01' PROM memory area. The receive buffer receives incoming messages of up to 80 characters and when the message is complete, it is usually automatically transferred to the input buffer. The display buffer is then filled with the first 16 characters of the input message. The operator may then scroll the input message through the display buffer. Alternately, tire host computer can cause the message to continuously scroll through the display buffer. The contents of the display buffer are displayed to the operator through 16 alphanumeric characters. The output buffer which serves as temporary storage for keyboard entries is transferred to the transmit buffer when the ENTER key is pressed. At that time the message is transmitted to the host or, in polled operation, held until the host requests the message. 1;M77 The TM77 is intended for those applications where an alphanumeric display terminal with numeric and function key data input is adequate. The TM77 keyboard has the advantage.that it is less complicated for the untrained or inexperienced operator. The TM77 is functionally identical to the TM71 except for the keyboard functions. The TM77 has larger, but fewer keys than the TM71. The TM71 offers a numeric (0-9) keyboard with function keys. Keyboard functions of the TM71, which do not appear on the TM77, are not available. The numeric keyboard light is unnecessary and has been deleted. The keys of the TM77 are 38% larger and placed on 0.65-inch centers as compared to the 0.5-inch centers of the TM71. This is the same spacing as used on touch tone telephones and allows operators with gloved hands to easily use the keyboard. As can be seen from the following figure, the keyboard appears much larger and less forbidding of use. For a description ofthe TM77 key functions, refer to those same keys described for TM71 in the Detailed Key Description section. FIGURE I. TM71 Buffers. TM71-I/O The TM71-1/0 is identical to the TM71 but with the following additional features. The front panel has eight additional host-computer controllable LED's The rear panel has an additional20-pin connector. This connector provides a TTL-compatible, 8-bit bidirectional port (port A) and 8-bit output only port (port B). The output only port indicates the status of the additional eight front panel LED's. The bidirectional port has input and output strobes and may be used by the host system as a general purpose remote input/ output port. Further insight into the operation of the TM71 can be gained by viewing its operation in terms of modes and status conditions. The TM71 has three major operating modes and four status conditions. Operating Modes Ready Message Composition Edit TM77-I/O The TM77-1/ 0 is identical to the TM77 with the addition of the I/O port features described above far the TM71-1/0. Status Conditions Message Waiting Output Pending Input Display Numeric Keyboard OPERATING MODES Ready The Ready mode is the standby mode; it is entered by pressing CE, 2nd CLR, or RESET. The symbol/\.in the output display indicates the Ready mode. The other display positions are blank. Ready mode is exited when any character or function message is entered into the output buffer from the keyboard or when the terminal is put in Edit mode. The ready indicator will not be visible when an input message is being displayed; however, the terminal may be internally in Ready mode. . Upto 14 function messages may be defined by the host system. After definition by the; host, these messages are called for display by the host sending a 3-character code [ESC) ZZ; whereZZ may have the values 01 through 08 and 21 through 26. Function messages may be retransmitted to the host by" pressing the front panel function message keys. Thus they may. be used as extensions of the input message to the TM71 or as function messages to be transmitted by the TM71 operator to the host system. In addition, a PROM socket is provided for nonvolatile storage of function messages. For all the following descriptions the terms input and output shall refer to input to the TM71 and output from the TM71. Internal operation of the TM71 is easily Message Composition Message Composition mode is entered from the Ready mode or Edit mode. Ifthe terminal is in the Ready mode, entering any character or function message from the 9-45 keyboard causes the terminal to enter Message Composition mode. It is indicated by having a character in the output buffer. A space is the only character that can leave the display buffer blank. Nondisplayable characters are displayed as .±J . Message Composition mode may also be entered from the Edit mode by pressing 2nd ED/EX. Message Composition mode is exited by pressing CE, 2nd CLR, RESET, ENTER, or 2nd ED/ EX. The latter causes the terminal to enter Edit mode. second output message may be composed in the output buffer; however, if ENTER is pressed for the second message before the Output Pending LED goes off, the first message is lost. Input Display The Input Display LED indicates when the display buffer is viewing the input buffer. This can happen in two ways. When the terminal is in Ready mode, an input message will automatically switch the display buffer to the input buffer causing the Input Display LED to come on. The Ready Indicator will no longer be visible; however, the terminal is still in the Ready mode. When the terminal is in Message Composition mode, pressing 2nd RECALL switches the display buffer to the input display causing the Input Display LED to come on. The terminal is still in Message Composition mode. Pressing 2nd RECALL a second time will return the display buffer to its former position in the output buffer. Edit· Edit mode may be used to modify the contents of the output buffer. It is not essential to beable to use the Edit mode in'order to operate the TM71. It is entered by pressing 2nd ED/EX and is exited by pressing 2nd ED/EX again or CE, 2nd CLR, ENTER, or RESET. Edit mode is indicated by the presence of the underscore cursor in the display while the output !>uffer is being displayed. STATUS CONDITIONS Numeric Keyboard Numeric Keyboard status is used to provide a convenient numerical key pad in the center of the keyboard; it is entered by pressing A/N. If the terminal is in Numeric Keyboard mode, it is exited by pressing A/N. Numeric Keyboard is indicated by the Numeric Keyboard LED being on. Message Waiting Message Waiting status is the condition of being in Message Composition mode when the host sends an input message. The Message Waiting LED comes on to indicate a new input message is in the input buffer and may be viewed at the operator's convenience by pressing 2nd RECALL, ENTER, or CEo When any of these actions are taken, the Message Waiting LED goes off until the I\ost sends another message while the terminal is in Message Composition mode. In addition, if the host sends a new message before the input buffer has been examined, the message is held in the receive buffer. The message to be transferred to the input buffer. POLLED MODE Up to 15 TM71's may be operated on one host communication port. This.is referred to as polled operation. This is made electrically possible by \Ising the 20mA communications current loop circuits. These circuits feature optical isolators to allow mUltiple input and mUltiple output loops to be series connected together. The host then uses a 2-digit drop number, unique to each TM71 on the loop, to address each TM71 terminal. Correspondingly, each TM71 prefaces each of its output messages with its drop number. Details of polled operation are contained in the Communications Protocol section and in the Installation Section. Figures 2, 3, 4 and 5 show the front panel of the four models. Output Pending Output Pending status occurs when the terminal is used in a polled configuration, as determined by rear panel connectot jumpers, and an output message has been enabled by the ENTER key. The message is actually transmitted when the host polls the terminal. Until this happens the Output Pending LED comes on. In many installations this will happen so quickly that the operator may never actually see the LED come on. However, if the host were temporarily occupied with another task, the operator ,wopld know that the message had not been transmitted. The message actually enters the transmit buffer and waits there until the terminal is polled. A FIGURE 2. TM71 Front Panel. 9-46 FIGURE 3. TM77 Front Panel. I n Ready mode, when a message is received from the host computer, the first 16 characters of the message appear on the display. The Input Display LED comes on to indicate the display buffer is filled with a section of the input buffer. The entire message may be viewed by using the ROL and ROR keys. When one of these keys is held down, the message will scroll through the display at approximately six characters per second. When any character key is pressed, the Input Display LED goes out and the character appears in the left of the display with the rest of the display blanked. As other character keys are pressed, the message grows from left to right. For upper key characters, the 2nd key is pressed first. It must be pressed prior to each upper key character. 2nd DEL deletes the last character. If DEL is held down, characters will be deleted at approximately six characters per second. To facilitate the composition of long output messages, a line editor is available by using the 2nd ED/ EX key sequence. The Editor is described in the Display Control, Edit, and Control Keys section. FIGURE 4. TM71-I/O Front Panel. Internally, the TM71 consists of80-character receive and input buffers, a 16-character display buffer, and 80character output and transmit buffers. The display buffer is used to scan eitherthe input buffer ortheoutput buffer. It is switched from one to the other by pressing 2nd RECALL. WheQ the display buffer is displayin,g the input buffer, the front panel Input Display LED will be on. Complete operating details are contained in the following sect.ion. DETAILED KEY DESCRIPTIONS ALPHABET AND SPECIAL CHARACTER KEYS OPERATING INSTRUCTIONS When power is applied to the TM71, the Input Display LED will come on and the display will show the Ready I ndicator which is a 1\ in the left-most character position. A message consisting of up to 80 characters, including spaces, may be entered from the keyboard. Pushing the ENTER key causes the message to be transmitted to the host computer. The message will be sent each time ENTER is pressed; this is indicated by the display blinking. In Polled mode the Output Pending LED will come on until the host takes the message. The output buffer may be cleared by pressing CEo Pressing a key to start a new message will automatically clear the output buffer. The Ready Indicator will appear after the output buffer has been cleared by CEo In addition, the Function Message keys may be used to enter up to 14 different function messages into the output buffer. rnrn etc. These keys are used for data input from the keyboard. To enter the upper character press the 2nd key prior to each upper character. Characters enter the display in the leftmost unused position. After 16 characters have been entered. previous characters move one character position to the left when a new character is entered. After 80 characters are input. no more characters are accepted. FIGURE 5. TM77-I/O Front Panel. ALPHABET AND NUMERIC KEYS ~~ etc. These keys are used to enter characters from the keyboard. The upper characters are entered by pressing 2nd prior to each upper character. This is called the Alpha mode. An alternate mode is ca'lIed Numeric mode. In this mode an upper character may be entered by only pressing the key. In the Numeric mode pressing 2nd first will cause the lower character to be entered. The keyboard is put in Numeric mode by pressing the AI N key. The Numeric keyboard LED is on while the keyboard is in numeric mode. To eXit Numeric mode press A 'N. Alpha mode is the power-up and Reset mode. 9-47 GJ GJ FUNCTION MESSAGE KEYS etc. These keys are used to input function messages from the keyboard. The function message may be one of the default strings &XX 'or it may be a host defined string. When no host specified string definition has been provided, the three characters of the default string appear. For a host defined value, the last 16 characters of the string definition appear in the display. Incoming function messages appear with their first 16 characters in the display. The first eight function messages are put in the output buffer by pressing the F I through F8 keys and the remaining six by pressing 2ndFI through 2nd F6. When no message has been defined, default messages appear in the display as &ZZ. ZZ represent 0 I through 08 or 21 through 26 for a total of 14 values. FUNCTION MESSAGE AND DISPLAY CONTROL KEYS r=l r=l characters per second.ROL and ROR'rnove thi: cur~or one p.osition to the left or righUf ROL or ROR are held down, they cause the cursor to scroll left or right. When the cursor PQints to the first or last character, it will not move further to the left o'f right, respectively. When the cursor reaches the left or right end of the display, the message begins to scroll right o~ left, respectively. The cursor continues to point at ~he left-most or right-most character ~f the display. In Edit mode the display is effectively shortened to 15 characters since the underscore cursor does not actllalfy "underscore"the character to which it points. _ causes the display buffer to display the right-most 15.characters with the cursor in the right-most, position. _ does the same for the left-most 15 characters with the cursor in the right-most position. l!!.J L..!!..J These keys, when used as function message keys, are the same as the previously defined function keys. When used with the 2nd key, they move the display buffer to the right-most 16 characters (_), or the left-most 16 characters (_), of the input or output buffer. In Edit mode the display cursor (underscore) goes to the end (_) or start· (_) of the message. When the display buffer is filled with part ofa'host-serit input message, the lI).essage may be transferred to the output buffer without transmission by press'ing 2nd ED I EX. The TM71 will then be in Edit mode with the Edit cursor at the right end of the input, now the output, message section being examined. The previous contents of the output buffer are lost. Fum;tion messages niay,beedited. The following example iIIu,strates the use of the editor. DISPLAY CONTROL, EDIT, AND CONTROL KEYS Display Control Keys Edit Mode Example: KEYSTROKES In normal operation pressing ROL will cause the message to move one character position tat he left or until the last character of the message being examined is in the rightmost position of the display. Pressing ROR causes the message to move one character to the right or until the first character ofthe message under examination is in the left-most display position.' Holding eight key down causes the display to scroll by at approximately six characters per second until the first character is in the left-most, or the last character is in the right-most character -position for messages of more than 116 characters. ~ XXZZYYY Enter Edit, mode 2nd ED EX Display Editing Keys The ED / EX k~y is us.ed to put the TM71 in or out of Edit mode. In Edit mode DJ;:L, ROL, ROR,_ and - may be used for easy editing of any message contained in the 80-character output buffer. Edit mode is.indicated in the display by an underscore which is used as the Edit cursor. The cursor "points"to the immediate character to its left. The key sequence 2nd DEL delt:tes the character. If DEL is held down, characters are deleted at the rate of six 9-48 (underscore cursor) ROI. ROI. ROL XXZZ...YYY 2nd DEI. 2nd DEI. ~_YYY A ACTIOS Delete ZZ'aI1d put ABCD in'its place· XXA_YYY' Move Cursor Delete two characters Enter A BCD XXABCD-YYY Enter B.C D 2nd ED EX XXA8CDYYY Ex.it Edit mode mode as indicated by the Numeric keyboard status LED being off, ~. causes 2 to be displayed and stored. NOTES: I. The underscore indicates Edit mode. 2. The cursor may be moved with ROL and ROR. 3. ROL and ROR stop at the ends of the output line. 4. Filling the 80-character output buffer prevents the display from resppnding to any attempt to insert or append more characters. 5. Holding ROL or ROR down causes the cursor to move toward the beginning or end of the line at approximately six characters per second. 6. When there are no characters in the output buffer, the TM71 will not enter the Edit mode. Deleting all characters causes the TM71 to exit Edit mode. 7. The ASCII underscore is also a valid character. B SPACE AND DELETE KEY ~ Space causes a blank to be entered mto the output buffer. The right-most character becomes a blank. DEL deletes the right-most character. DEL does not enter the ASCII character DEL into the output buffer. In Edit mode DEL causes the character to the left of the cursor to be deleted. ALPHANUMERIC AND NEXT KEY ~ Pressing the AI N key causes the keyboard to enter the Numeric mode. The upper white-on-black labels become lower labels not requiring the 2nd key before entry. The lower labels become upper labels and require the use of the 2nd key for entry. The front panel Numeric LED comes on to indicate the keyboard is in Numeric mode. Press AI N to return to Alpha mode. The Alpha mode is also the power-up and Reset mode. Control Key The key sequence 2nd CTRL followed by any letter ofthe alphabet causes the corresponding 26 ASCII characters to be put in the output buffer. These characters are listed in the Appendix. In addition, 2nd CTRL FI causes the ASCII Escape (ESC) character to be put in the output buffer. The 2nd CTRL D sequence has special meaning to the TM71. It is the ASCII EOT character. This character is an end of transmission character. When the TM71 operates with some host computer operating systems, it is sometimes desirable to send a message without a carriage return. The key sequence, MESSAGE 2nd CTR D ENTER, causes M ESSAG E to be sent without a carriage return. This is often desirable in conjunction with other control characters. For example, in many operating systems CTRL C is used to return from a particular system program to the keyboard monitor program. The keyboard monitor responds with some acknowledgement character or prompt. It will not usually expect a carriage return with control characters since control characters are often used to interrupt other operations. Thus, since the TM71 has a one line display, 2nd CTRL CENTER will cause the prompt to be missed because the CR is interrupted by the monitor as a null line response to the prompt. In fact this causes most operating systems to return to the previous operation and prevents access to the keyboard monitor. Entering 2nd CTRL C 2nd CTRL D ENTER causes the TM71 to suppress the carriage return that is normally appended to output messages. This allows the prompt to be viewed in the TM71 display. A function key may be programmed to provide a CTRL D sequence. RESET. The RESET key allows the TM71 operator to initialize the internal functions. Pressing RESET is equivalent to turning on the power. Pressing RESET will cause host defined messages to be lost. RESET may be disabled when the TM71 is installed. EJ SECOND KEY The second key, 2nd, is used to enable the upper label of the next key ~ssed. For example, the key sequence [I] LiJcauses +v to be displayed and stored in the output buffer. When the keyboard is in Alpha EI Pressing 2nd NEXT causes any input message waiting in the Receive Buffer of the block diagram in Figure I to be transferred to the Input Buffer. This will be necessary when an input message is received while the terminal is holding a previous input message. This condition is indicated by both Input Display and Message Waiting LED's being on. ENTER AND RECALL KEY ~ ENTER is used to send output messages to the host system. When the TM71 is in Ready mode, the receipt of an incoming carriage return, CR, causes the display buffer to be loaded with the first 16 characters of the input message. The Input Display LED will come on. When the TM71 is in Message Composition or Edit mode, receipt of an incoming CR causes the Message Waiting LED to come on. The operator may finish any output message and send it to the host by pushing ENTER. If it is desired to examine the input message before entering or even completing the output message, the RECALL key may be pressed causing the display buffer to be filled with the first 16 characters of the input message. The Input Display LED will come on. The input message may be examined by using ROL and ROR. Pressing RECALL a second time will cause the display register to be filled with the 16 characters of the output buffer it contained when RECALL was pressed the first time. The Message Waiting LED is turned off, and remains off, after the first input message access with the RECALL key. Accessing the input message a second time fills the display buffer with the 16 characters it contained when the output message was accessed. Thus, if required, the operator can work through the input message composing an output message in response to small sections of the input message. Pressing ENTER while in Edit mode causes the TM71 to exit Edit mode and transmit the output buffer. While examining an input message, pressing ENTER will cause the input message to be transferred to the output 9-49 buffer and transmitted to the host. Any previous contents of the output buffer will be lost. The Input Display LED is on when the display buffer contains a section of the input buffer. When the display buffer is filled with part of an input message, the message may be transferred to the output buffer without transmission by pressing 2nd ED/EX; The TM71 will then be in Edit mode with.the cursor at the right end of the input (now the output) message section being examined. The previous contents of the output buffer are lost. The input buffer retains the original message. from right to left at approximately six characters per second when n=1. 0=0 disables scroll. (ESCIHn(CRI Causes any input display message to flash with a 50% data cycle approximately three times pe.second when n=1. When n=Oflash Is disabled, ' (ESClln(CRI Causes any output measage to blank when n=l. The input buffer will still be displayed. n=O disables, blanking. (ESCIJn(CRI Locks out the KeYboara Trom use wnen n=l . The RESET key is not disabled. Keyboard lockout is disabled with n=O. IESCIKICRI Causes ttie input buffer to be transfer(lld to the transmit buffer and transmitted. This command is useful in testing communiC8 tions lines and circuits.' A message transmitted by the host CPU to the tnicrolermlnal will be returned to the host by the terminal after receiru: of th~ K command. lliJ CLEAR ENTRY AND CLEAR ALL KEY Pressing CE causes the TM71 to exit Message Composition mode and the Ready Indicator to come on. The output buffer is cleared. Pressing 2nd CLR causes the TM71 to exit Message Composition mode, clears output and input messages, clears Message Waiting LED, clears Output Pending LED, and causes the Ready Indicator to appear. Host-specified function messages are unaltered. Pressing RESET, if enabled by the back panel jumper, has the same effect; plus, it sets function messages to their default power-up condition. When the TM71 is in Edit mode, pressing CE or 2nd CLR causes the terminal to exit Edit mode and go into the Ready mode. 2nd CLR clears the receive buffer but does not clear the transmit buffer. Although the Output Pending LED goes off, the host may still read the transmit buffer., M (ESCILDDDI CR) Sets turnaround delay. Turnaround delay is the time that the microterminal waits after it receives a command to transmit. before it actually transmits. DOD sets the delay in increments of 10 milliseconds from 0 to 2.54 seconds, Thisdelay has a default value of40 milliseconds. (ESC)MICR) Causes the digital input to port A to be transmitted to the host CPU as a single ASCII character. (ESCIN(CRI Causes the' digital input to port A to be transmitted to the host CPU as three decimal digits - 000 to 255. (ESCIO(CRI APPLICATIONS CONTROL FEATURES Requests the transmit buffer. Used only in Polled Mode, The A command works only once per ENTERed message, The second time the A command is used for the same message, a carriage return only is transRequests retransmission of the transmit buffer, The B command can be used to get a second transmission of a message if for instance the first transmission has a parity error. (ESC)CICRI Clears the input buffer. (ESCIDZZ(MESSAGE(CRI Used to define function messages in RAM, ZZ is the function message number from 01 to 06 and 21 to 26. IMESSAGEI is the function message. If (MESSAGEI is not present, the function message is deleted. (ESCIEn(CRI ControlstheAl LEDandtheAl TTL output. ,For n=1 the LED is "on" and the TTL output "low". For n=O the LED "off" and the TIL output "high". IESC IFn(CR 1 Controls the A2 LED and A2 TIL output. For n=1 the LED is "on" and the TTL output "low". For n=O the LED is "off' ana tne TIL output "high", (ESCIGn(CRI Causes any input message Delng observea through the display to scroll continuously to operate in continuous Causes port A to operate in continuous deCimal mode. In this mode. as data is strobed into port A. It is immediately trans· milled as three decimal digits followed bya, carriage return. Likewise. three decimal digits followed by carriage return from the host CPU is immediately output as the 8 bits of port A. (ESC) terminates continuous mode. IESCIQalCRI Causes one ASCII character, "a", to be output on port A. IESCIRDDDICRI Causes the decim~1 number DOD to control the output of port A. DDD is a number between 000 and 255. (ESCISDDD(CRI Causes the decimal number DOD (000 to 2551 to control the output of port B. mitted, (ESC)BICRI f\ tinuous mode. IESCIPICRI Certain input messages may be used by the host system to put the TM71 in special modes. These messages, which begin with the ASCII Escape charactdl" (ESC), are described below. See also the Input Message Summary part of the Communications Protocol section. (ESC)A(CR) Causes port ASCII mode. In this mode, data strobed into port A is immediately transmitted asa single ASCII character. ASCII characters transmitted from the host CPU to the terminal are output immediately. (ESC) terminates con- Function Messages The TM71's RAM has 415 character locations which may be used for function messages. The function messages may be any length less than or equal to 80 characters as long as the total number of characters does not exceed 415. This memory is assigned dynamically by the TM71 software. This means up to five messages may be 80 characters each if only five are defined. Attempting to exceed this boundary will cause unpredictable results. Alternately. a maximum of 14 messages of29 characters each could be defined; they may be of differing lengths. When a PROM is used to define function messages, 14 messages 80 characters in length may be defined for a total of 1120 characters. RAM definitions may be made even when the PROM is present. The RAM definitiOns 9-50 are used by the TM71 until the RAM definitions are deleted, then the PROM definitions are used. This may be done with the RESET key or from the host. Function messages may contain all 128 characters of the ASCII set. When control ASCII characters are part of normal input messages, they are stripped; however, they may be part of commands such as function message definitions. All function messages are transmitted to the TM71 as (ESC)ZZ where ZZ represents 01 through 08 and 21 through 26 for function messages I through 14. For output &ZZ will be used as a default string if no message definition has been made in RAM or PROM. In this case the message will be transmitted as defined. The sequence (ESC)ZZ is considered part of a message. Do not confuse it with one of the (ESC) commands in the Input Message Summary section. For example, (ESC)OI (CR) is a complete and normal input message; it causes function message 0 I to be put in the input buffer. When the F2 function key is pressed, (MESSAGE) preceded by any contents of the output buffer, is immediately transmitted. (MESSAGE) may include any type of line terminator such as (LF)(CR), (CR)(LF), or (ETX). (CTRL D) prevents the TM71 from adding a (CR) and (RS) causes immediate transmission without the use of the ENTER key. The use of (RS) is especially important for high priority control messages for which it is desired that only one key be pressed. The only restriction on the message is the use of (CR). (CR) may be contained in PROM-defined function messages but not in host-defined messages. This is necessary because an imbedded (CR) will terminate the function defination. CTRLX The control CAN (CTRL X) of the ASCII set has special meaning to the TM71. When it is the first character of an input message, or the first character after the address characters in Polled operation, the TM71 will clear its receive and input buffers of previous messages and blink the Message Waiting LED. The new message will be in the input buffer and a command will be executed. This may be important for high priority messages to the operator. If the operator leaves the TM71 in Message Composition mode and two messages have been received, the first message will be in the input buffer and the second in the receive buffer. A third message or command will not be received unless (CTRL X) is used to clear the receive and input buffers. When the TM71 is in Ready mode, all messages come to the input buffer and the terminal goes to input display status. In this case the (CTRL X) has no effect on operation. See Figure 6 which shows the Displayable Characters. CHARACTER SET DO 01 02 L L L " L L D6D5 D4 D3 L " ~ L L , +I" I L ,-, ! i '-' ,, 0 .L HI H , H -' L=U-, ::H I ([ _u \I I ell , I j:I:lr 8 F: f 1/ -, i 2 13 I y , !-, -0 , L_ ,-_U -,-, -'-' H I JIJ-('L TURN AROUND DELAY When commands that cause an automatic reply are sent from the host, TM71 can delay its reply for a programmable turn around time. The purpose of this feature is to allow the TM71 to operate with any host, terminal handler software which cannot accept input immediately following the carriage return of a host output message. This is the case in many host systems. This delay has a default value of 40 milliseconds. This may be changed by the host by using the command string (ESC)LDDD(CR) where DDD represents 000 through 255. This number sets the delay in increments of 10 milliseconds from 0 to 2.54 seconds. Delay may also be set by the user PROM. RAM-defined delays will override PROM-defined delays. ,--,!'-1 l"i (1 C -,'~ , ,~--+---)---1-'---+--+--+--1 L ":" v I v 7 LL.L-1L_-'--_'_' l_'_~ r , ~_'-~_L_-'--_-'---.J NOTE: All nondisplayable characters entered from keyboard are displayed as I I ::1::'1 • FIGURE 6. Displayable Characters. IMMEDIATE TRANSMISSION OF FUNCTION KEYS A function message can be transmitted immediately if the ASCII control character RS (Record Separator) is the last character of the definition. When this character is encountered while getting the function message from RAM or PROM, it is treated as if the ENTER key were pressed. This causes the function message to be transmitted along with any characters that were in the buffer when the function key was pressed. This feature, when used with CTRL D, allows function messages to have a completely user-determined end of line character string. This is accomplished by defining a function message as follows: (ESC)D02(MESSAGE)(CTRL D)(RS)(CR) TM71 SELF TEST AND DEMONSTRATION The TM71 may be exercised without a host system by connecting +5V DC power. If TX (pin 2) is jumpered to RX (pin 3), the TM71 can receive its own messages and commands. For example, it is possible to send, receive, and scroll a message as follows: Key sequence: (CE)HELLO(ENTER)(2nd)(CTRL)(FI) G I (ENTER)(2nd)(RECALL) 9-51 This key sequence will cause the word HELLO to bam"\er across the display. (CE)HELLO(ENTER) clears .the output buffer and sends HELLO to the input buffer. The TM7I automatically switches to input display indicated by the input display LED coming on. (2nd)(CTRL)(FI) enters (ESC) in the output buffer. The TM7I switches to output display causing the input display LED to go off. Since (ESC) is nondisplayable, a .±J appears in the display. G I(ENTER) then completes the banner command and sends it to the TM7I receive buffer. (2nd)(RECALL) switches the terminal to input display and the bannering HELLO is observed. COMMUNICATION DELAYS Some operations require a delay ,before the TM71 can accept another message or command. When a function message is defined, the TM71 requires at least 150 milliseconds before another message or command can be received. A host message which calls a predefined function message requires 2 milliseconds for each function message called before another message or command can be received. The TM71 provides buffer space for one message and one command. Delays may be required between two commands or between two messages. When software is written in a high level language, delays between messages will normally occur. When programs are written in assembly language on small systems suchas single board computers, it may be necessary to design delays into the system software. Should the need arise, this is easily accomplished for high level languages as well. It is recommended that I/O commands for TM71I/O be followed by a 40 millisecond delay. Note: Delay timing must start after the receipt by the termi.nal of the carriage return delimiter. CTRLD Carriage returns can be suppressed on output by entering (MESSAGE) 2nd CTRL D ENTER. This is useful when interfacing to some host operating systems as was explained in the Display Control, Edit, and Control Keys section. CTRL D is the ADCII end of transmission character (EOT). A function keymay be programmed to provide CTRL D. COMMUNICATIONS PROTOCOL The TM7I sends and receives 7-bit, asynchronous ASCII character codes with one parity bit and two stop bits. One or two stop bits will be accepted for input. When parity is disabled, a mark or space, as determined by PI jumpers, is inserted for the parity bit. Parity may be even or odd and is selected by j um pers on P I. Characters with parity errors are displayed as nondisplayable characters ( ). These jumpers also select the data receive and transmit rate. This rate may be 110, 300, 600, 1200, 2400, 4800, 9600, or 19,200 bps. Each messagetral)smitted from TM7l is terminated with ea carriage r,eturn character. When operated in Polled .mode, each message is preceded with its 2-character polling drop number. This is not counted as part of the SO-character message. For an input message, the TM71 requires that the message of up to 80 characters in length be terminated by 9-52 a carriage return. Line feeds following a carriage return are discarded; otherwise they are' displayed as nondisplayable characters. Line, feed will be ignored as the first character of a message. Carriage return is not counted as one of the input characters. In Polled mode the message must begin with a drop number 00 through 15. This is followed by up to SO characters plus a carriage return. When the, host polls the TM71, it must send XX(ESC)A(CR) where XX is the drop number 01 the partiCuiarTM71 (01 to 15). Drop number 00 causes an input message to be received by all terminals. FUNCT.ION MESSAGES Function messages of up to SO characters in length may be defined by sending (ESC)DZZ(MESSAGE)(CR). In Polled mode this would be XX(ESC)DZZ(MESSAGE) (CR). ZZ represents the function message number 01 through 08 or 21 through 26. When a user PROM has been installed, these definitions are still valid and take the place of any PROM message until RESET is pushed, power-up, or the message is deleted. Defined messages may be deleted by sending a new definition or (ESC) DZZ(CR). (ESC)DOO(CR) deletes all function message definitions. To call a function message to the display from the host, the host sends (ESC)ZZ within a normal message or merely (ESC)ZZ(CR). The display buffer shows the defined function message when a definition is present in RAM or PRoM. The defined function message is transmitted on output. When no message has been defined, &ZZ is shown in the display of input and output messages. &ZZ is also transmitted in output messages when no function message has been defined. It is important to remember the distinction between the host defining a function message and entering a message in the input buffer. The host may define them without entering them' when they are for use by the operator through the function message .keys. INPUT/OUTPUT PORTS The TM7I-I/0 and TM77-I/O have, in addition to all the features of the TM7l and TM77, an 8-line output port (port B) and an 8-line input and output port (port A). These ports connect to a20_pin connector on the back panel. Port A has an input strobe and an output strobe. Port B connects to an a: 3.5V all OO~A. 3. Mating connector Berg 65469-005 or -007. DIIa .::::::x~ ---l I-- TABLE VI. Setting the Baud Rate . BAUD RATE 300 600 1200 2400 4800 9600 19200 110 B2 Bl BO I I I I 0 0 0 0 I I 0 0 I I 0 0 I os DutputSlrobl (J I 0 I 0 I O. ___~x::::: Pori AOutput DIIa BOOnuc, min. ~ ---l I- 1.6p1IC. min. FromTM7I FIGURE 9. Port A Output Timing. Default Baud Rate: 300 o = Jumper to Supply Return. I = Open. Dlta PARITY BIT PI SPACE EVEN. ODD MARK 0 0 I I ==:x x:::=. Pori AInput 0811 --l I- BOOnlle. min. TABLE VII. Setting the Parity Bit. is PO I 0 0 I Input Strobl \, mHHHtH/UUHD L To TM71 FIGURE 10. Port A Input Timmg. I MARK = Logic 1\ Default Partty: MARK U = Jumper to Supply Return. I ADDRESS A3 00 lOon-polled \ 0 01 0 02 0 I ·· AI AO 0 0 0 0 0 I 0 I 0 I I I A2 ··· ··· ··· ··· · 15 Default Address: = Open. au CURRENT LOOP COMMUNICATIONS WIRING CONNECTIONS TM71 units may be connected to one or more hosts by using the two 20mA current loop circuits. Optical coupling devices are used to electrically isolate TM71 from these circuits. Figures II and 12 illustrate connections to typical host communications circuits. I = Jumper to Supply Return. 0= Open. 9-56 f -+12YDc - -1 1 1 1 I I I r--------., 1 4700 1 1 +IN 16 -I 1 1 +Our .our -= +12VOC 4700 :::,C ~N 15 330n ·12VDC Short cln:u" prolllclld Outpul Curnnl (short CIRUll to Ground) > :t3mA Mark.;; ·6.0Y wlih 3knload Space ;;. +6.DY wllh 3knload NOTE: ±12V Irl genarlled Irom +5Y by an Intamll DC to DC convlrtar. , I "-------_-! TM7I HOST 2 1470pF I I 1 _ £ 1 "'I I L_::: ____ rx 1 I ·IN T-1 +12VDC I I 1 1 1 +our 18 +IN I I 1 I I I I I fIGURE II. Single-drop ConnectionPolled Operation. FIGURE 14. Output Equivalent Circuit. In addition to Transmit (pin 2) and Receive (pin 3) the TM71 supports three other RS-232"C signals: Request To Send output. RTS. (pin 4) Clear To Send input. CTS (pin 5) Data Terminal Ready output. DTR. (pin 20) These three modem control signals utilize positive logic. In contrast. the data signals on the Transmit and Receive pins use a negative logic (i.e .. logic I is a negative voltage and logic 0 is a positive voltage). For the modem control signals. the active state (logic I) is a positive voltage and the inactive state (logic 0) is a negative voltage. When the TM7.I is ready to transmit data. it activates the Request To Send output. When the Clear To Send input is activated. the TM71 transmits. The Data Terminal Ready output from the TM71 is always Active indicating to the host that power is applied and the terminal is available. The three modem control signals do not need to be connected for the TM71 to operate properly. The Clear To Send input is Active if left open. FIGURE 12. Multiple-drop ConnectionsPolled Operation. CURRENT LOOP ELECTRICAL SPECIFICATIONS Input Voltage Drop ~ I.3V at 1.2V at ~ 1.2V at lOrnA 30mA ~ I.3V at ~ I.3V at ~ IAV at 20mA ~ Input Minimum Current Input Maximum Current Output Voltage Drop Output Current Minimum USER PROM INSTALLATION INSTRUCTIONS 35m A 20mA lOrnA The TM71 has a 24-pin socket on its printed circuit board which will accept 2716 type parts. To install a user PROM. use the following procedure. lOrnA 20mA 35mA • Set the unit face down on a flat surface. • Remove the six back panel retaining screws. • Carefully pry the back panel away from the case. Output Voltage Drop x Output Current must be~ 250mW. Output Current must be limited by the external circuit. • Remove the four 4-40 nuts which hold the printed circuit board in the case. RS-232-C ELECTRICAL SPECIFICATIONS. Figures 13 and 14 shown the equivalent input and" output circuits. • Do not misplace the nylon spacers which are around the four printed circuit board retaining screws under the printed circuit board. --1f--'-f-~ : +5YDC 3 HX 5.8kn _ ~.,--. 1-= Signal Gnd. • Carefully lift the printed circuit board from the case. Note that the board is connected to the keyboard with a IS-pin. pin and socket connector near the middle of the board. Thus. some resistance will be felt. • Put the PROM in the 24-pin socket taking care to not bend the pins and to avoid static electric discharge. The orientation of the part is shown on the printed circuit board. Mark .;;-3.OV Space;;. +3.DY HGURE 13. Input Equivalent Circuit. 9-57 Note: The PROM sockets may be filled with a protective substance. The PROM should be inserted through this substance. • Inspect the part and socket to be sure all 24 pins went into the socket. • Reassemble in the reverse order.. Tighten the nuts and screws firmly but do not over-tighten. POWER REQUIREMENTS +5VDC±O.25VDC at O.65A for Model TM71and TM77. +5VDC ±O.25VDC at O.85A for Model TM71-1/0 and TM77-I/O. ENVIRONMENTAL SPECIFICATIONS • Avoid using penetrating antiloosening products on the internal nuts as they will make it difficult to change the PROM should that become necessary. A nonpenetrating product, which may be removed if necessary, maybe used. MECHANICAL DIMENSIONS O"C to 60"C. 95% relative humidity noncondensing. Contact factory for extended temperature range. . FACTORY OPTIONS Figure. 15 shows the mechanical dimensions for the TM71 and TM71-10. None ABS PI'lIle ACCESSORIES 25-pin mating connector - 2525MC. 20-pin mating connector for I/O ports - 2020MC. ORDERING INFORMATION TM71 is the full part number for TM71. TM71-1/0 is the full part number for TM71-1/0. TM77 is the full part number for TM77. TM77-I;O is the full part number for TM77-ljO. 2525MC is the full part number for 2525MC. 2020MC is the full part number for 2020MC. ·TM71·I/O or TM7WO Shipped with Ilx 114-40. 3/B-lnch pan he,d 'Crawl. FIGURE 15. Mechanical.Deminsions. 9-58 APPENDIX AMERICAN NATIONAL STANDARD CODE FOR INFORMATION INTERCHANGE. This coded character set is to be used for the general interchange of information among information processing systems, communications systems, and associated equipment. TABLE X. ASCII Character Set. b7 ~ ~ tuba 0 0 0 b2 b, ~ ROW 0 1 0 1 0 1 1 1 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 a q + 0 0 0 0 0 NUL DLE SP 0 @ P 0 0 0 1 1 SOH DCI 1 A Q 0 0 1 0 2 STX DC2 .! 2 B R b r 0 0 1 1 3 ETX DC3 # 3 C S c s 0 1 0 0 4 EOT DC4 $ 4 D T d I 0 1 0 1 5 ENQ NAK % 5 E U e & 6 F V f u v 7 G W 9 w x P '0 1 1 0 6 ACK SYN 0 1 1 1 7 BEL ETB 1 0 0 0 8 BS CAN I 8 H X h 1 0 0 1 9 HT EM I 9 I Y iy Y 1 0 1 0 10 LF SUB J Z j z 1 0 1 1 11 VT ESC K I k I 1 1 0 0 12 FF FS < L \ I I 1 1 0 1 13 CR GS - M I m I 1 1 1 0 14 SO RS 1 1 1 1 15 SI US + / > N A n ? 0 - 0 - DEL .. TL _ _ _ _ _ Conlrol ICTRLI characters. i.e.. CTRLX is CAN, elc. DECIMAL EQUIVALENTS OF ASCII CHARACTERS Decimal Code ASCII Graphic Decimal Code ASCII Graphic Decimal Code 000 001 002 003 004 005 006 007 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI DLE DCI DC2 DC3 DC4 NAK 022 023 024 025 026 027 028 029 030 031 032 033 034 035 036 037 038 039 040 041 042 043 SYN ETB CAN EM SUB ES FS GS RS US SP 044 008 008 010 011 012 013 014 015 016 017 018 019 020 021 ! . # $ % & 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 ASCII Graphic Decimal Code ASCII Graphic DeCimal COde ASCII Graphic DeCimal Code 066 067 068 B C D E F G H I 088 089 090 091 092 093 094 095 096 097 098 099 100 101 102 103 104 105 106 107 108 109 X - 110 111 112 113 114 115 116 117 118 119 120 / 0 1 2 3 4 5 6 7 8 9 060 < 061 - ( ) 062 > 063 ? 064 + 065 @ A 069 070 07.1 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 J K L M N 0 P Q R S T U V W LF = Line Feed. FF = Form Feed, CR = Carriage Return. DEI. = Runoul. 9-59 y Z [ \ J 1\ a b c d e f 9 h I I k I m '21 122 123 124 125 126 127 ASCII Graphic n 0 P q r s t u v w x y z I i rv DEL TM71 B ANDTM77B MICROTERMINAL/BAR CODE READER USER'S GUIDE ADVANCE INFORMATION Subject to Change BURR-BROWN@ 11511511 International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. (6021 146-1111 • Twx: 910-952·1111 • Cable: BBRCORp· Telex: 66·6491 PDS461 9-60 TABLE OF CONTENTS INTRODUCTION ............................................................. 9-62 OPERATION .................................................................. 9-62 Description ................................................................. 9-62 Operating Modes ............................................................ 9-63 Status Conditions ............................................................. 9-65 Detailed Key Descriptions .................................................... 9-65 Audible Output. ............................................................. 9-66 APPLICATIONS ............................................................. 9-66 Control Features ............................................................ 9-66 Self Test Mode .............................................................. 9-67 Communication Delays ....................................................... 9-68 Immediate Transmission of Function Messages .................................. 9-68 Communications Protocol .................................................... 9-68 User Input/Output Port ....................................................... 9-68 Command Descriptions ..................................................•.... 9-70 INSTALLATION ............................................................. 9-71 SPECIFICATIONS ............................................................ 9-73 ACCESSORIES ............................................................... 9-74 --• i. I· I I 9-6\ Five 50-character buffers are provided, if needed, for stacking bar code messages prior to output to the host processor. Similarly, two SO-character buffers are available for incoming CPU-generated messages. The ~eceive buffer holds an incominl! message until it can be transferred to the input buffer where it is displayed for the operator's action. With this feature, the operator can visually review a CPU input while a second instruction from the CPU can be received and held until called up for display. INTRODUCTION If your data collection tracking requirements call for bar code inputs, as well as display and limited keyboard entry, you don't need to buy big, expensive and fragile CRT's with outboard bar code readers. The TM77B and TM71 B "microterminals" provide a display and keyboard terminal integrated with a high performance bar code reader. "Microterminals" - uniquely flexible in application versatility - are designed expressly to fill the human interface demands of widely dispersed control and communications networks - in shop floor control, in factory data collection, inventory control, WIP monitoring, libraries, machine and process control, energy management systems, and information processing. Microterminals, because of their interface flexibility, appearance, size, durability, easy installation, function equally well as consoles and control centers for instruments and small systems. They also perform as input/ output terminals in diagnostic applications. You don't need interface expertise to put microterminals to work for you ... they communicate in serial ASCII with RS-422 or RS-232-C conditioning. Baud rates range from 110 to 19,200. A tough, water resistant front panel protects LED displays and indicators as well as a full numeric keyboard (TM77B) or alphanumeric keyboard (TM71 B). Tactile feedback; audible signals, display blinking, and character display confirm operator entry. Buffered data features reduce on-line input/ output time with the CPU and improve accuracy of operator inputs. Because of its design simplicity the mircroterminal concept doesn't require special operator skills or training. Depressing a single function key initiates complex preprogrammed action by the CPU. These functions may be defined in your CPU's software. Microterminals' very compact design and simple mounting on any flat surface make them quickly adaptable to new or existing applications. All models measure only 21 Smm x 117mm x 34mm (S.6" x 4.6" x 1.35"). When ordered in OEM quantities the front panel can contain your corporate or system logo. You can display alphanumeric data with both units. A 30-key numeric keyboard (TM77B) or a 42-key alphanumeric keyboard (TM71 B) allows you to enter messages up to SO characters long. A bar code reader allows you to input messages up to 50 alphanumeric characters long. A 16-character display - with horizontal scroll-left or scrollright keyboard controls - permits review of data entered before transmission. Two SO-character buffers are provided for keyboard generated data. The output buffer holds a message being written or reviewed; the transmit buffer holds a prepared message ready for CPU acceptance. This feature allows a second message to be prepared while the first awaits transmission. The bar code reader can operate in two modes: Auto Wand and Manual Wand. In the Auto Wand mode, scanned data is transferred to the transmit buffer for transmission. In the Manual Wand mode, scanned data is transferred to the output buffer at which time keyboard data may be added to the buffer. Transmission is then initiated by depressing the ENTER key. In both modes, bar code scanned data is shown in the mircoterminal display. Display features include CPU control of scrolling, flashing, or blanking. The keyboard can also be locked out by CPU command. Two LED indicators are independently controlled by the CPU and three LED's indicate terminal status. It is important to realize that while the microterminal products including this one have many features, normal operation is very uncomplicated. Virturally untrained operators can use the microterminals productively. Most special features are invisible to the operator. A typical application consists of a series of host-system-supplied operator prompts. To each prompt the operator simply scans a bar code or keys in a short number or message. The function message keys may be used to further simplify operator responses. OPERATION DESCRIPTION The TM77B is a numeric keyboard, alphanumeric display "terminal". The TM71 B is an alphanumeric "microterminal". Both units include a bar code reader. They may be used as a remote or local data entry and output terminal for a host computer system. They are intended to provide a rugged, low cost, small size, alternative to a CRT terminal and bar code reader. They are suitable for applications with a limited amount of data interchange, as compared to applications requiring a typewriter-style keyboard and multiline display or hard copy output. Figures I and 2 show the front panel of the TM71 Band TM77B respectively. In the remainder of this User's Guide, only the TM77B will be referred to. All information, however, applies to both the TM77B and the TM71 B. The only difference is the expanded alphanumeric keyboard of the TM71 B. The TM77B features a dust proof front panel including 13 pre-defined characters and eight function keys on a 9-62 30-key keyboard, 16-character alphanumeric display, a bar code reader, two host-computer-controllable light emitting diodes (LED's), and three status LED's. Character height is 0.14". The keyboard features raised embossing with tactile feedback. In addition, a 25-pin, D-style rear panel connector is used to provide power, baud rate selection (110, 300, 600,1200,2400,4800,9600, and 19,200bps), remote reset in and out, parity selection, a polling address, and RS-422 or RS-232-C interface. There is an additional 14-pin connector, located on the rear panel, which supplies an 8-bitbidirectional port, port A, as well as control input and output strobes which may be used by the host system as a general purpose remote input/ output port. Up to eight function messages may be defined by the host system. After definition by the host, these messages are called for display by the host sending a 3-character code (ESC)ZZ, where ZZ may have the values 01 through 08 and 10 through 19. Function messages may be transmitted to the host by pressing the front panel function message keys. Thus they may be used as extensions of the input message to the TM77B or as function messages to be transmitted by the TM77B operator to the host system. complete, it is usually automatically transferred to the input buffer. The display buffer is then filled with the first 16 characters of the input message. The operator may then scroll the input message to continuously scroll through the display buffer. The contents of the display buffer are displayed to the operator through 16 alphanumeric characters. The output buffer which serves as temporary storage for keyboard entries is transferred to the transmit buffer when the ENTER key is pressed. At that time the message is transmitted to the host, or in polled operation, held until the host requests the message. TX RX C::=::::;==::J C::=~=::::J '}' BAR CODE READER BUFFERS r----'"--...., '--_~--....J FIGURE 3. TM77B Block Diagram. FIGURE I. TM71B Front Panel. Further insight into the operation of the TM77B can be gained by viewing its operation in terms of modes and status conditions. The TM77B has four operating modes and four status conditions. OPERATING MODES STATUS CONDITIONS Ready Message Waiting Message Composition Output Pending Auto Wand Input Display Manual Wand OPERATING MODES FIGURE 2. TM77B Front Panel. For all the following descriptions the terms input and output shall refer to input to, and output from, the TM77B. Internal operation of the TM77B is easily conceived as buffer memories for data received and transmitted via the serial interface, as indicated in the block diagram in Figure 3. In addition, the bar code reader provides five 50-character buffer memories for scanned data. Function messages are stored in a separate RAM memory area. The receive buffer receives incoming messages of up to 80 characters and when the message is READY MODE The Ready mode is the standby mode; it is entered on power-up or by pressing CE, CLR, or RESET. The symbol 1\ in the output display indicates the Ready mode. The other display positions are blank. Ready mode is exited when any character or function message is entered into the output buffer from the keyboard or the bar code wand. The ready indicator will not be visible when an input me~sage is being displayed; however, the terminal may be internally iii Ready mode. When the TM77B is in the Ready mode, the receipt of an incoming carriage return CR, causes the display buffer to be loaded with the first 16 characters of the input message. The Input Display LED will come on. 9-63 MESSAGE, COMPOSITION"MODE ' Message Composition mode is entered from the Ready mode. Ifthe terminal is in the Ready mode, entering any character or function message from the keyboard causes the,terminal to enter Message CorripOsition mode. It is indicated by having a character in the output buffer. A space is the only character that 'can leave the display biJffer blank. Nondisplayable characters are displayed as #. Receipt of an incorriing CR caiJses the Message Waiting LED to come on. Message Composition mode is exited by pressing CE,CLR, RESET or ENTER. AUTO WAND MODE Auto Wand mode will append valid data read in the bar code reader to any data in the output' buffer of the TM77B, and transfer the output buffer to the transmit buffer. The data in the transmit buffer will be immediately transmitted,in Single-Drop mode, or transmitted when polled by the host CPU in Polled mode. Buffer). The' Output Pending LED indicates that a message has been transferred to the transmit buffer, but the host has not yet polled the microterminal. In the event there was im error in the transmission (wrong address, parity error, etc.), the buffer data can be requested again by the retra'nSmit buffer command: If the request buffer command is sent again, a null message is transmitted to indicate no new data has been entered. This distinguishes between repeated data and new data. When the host sends messages or commands to the TM77B, they must be prefixed by two ASCII digits in the range 00 to 63 (see Table I). Address 00 is a special case which is accepted by all terminals addressed from 0 I to 63. This allows a single message to be received by all terminals on the multidrop line at the same time. TABLE I. Polling Address Selection. MANUAL WAND MODE ManualWand mode will append valid data read in by the bar code reader to any data in the output buffer of the TM77B. This data will not be transmitted to the host processor until the ENTER key is depressed or until the ENTER command is read by the bar code reader. Keyboard data may be entered before or after bar code data is read. Any number of bar code reads may be accepted to the output buffer up to the 80-character limit. Bar code readings are not stacked in the five bar code buffers. COMMUNICATIONS MODES The TM77B operates in both the Polled and Nonpolled Communcations modes. In the Nonpolled mode, one micro terminal is connected to each host serial communication port. In the Polled mode, up to 63 microterminals may be connected to each host serial communications port. Nonpolled Mode In the Nonpolled mode, when a keyboard message is prepared and the ENTER key del'ressed, the data is immediately transmitted. In the Manilal Wand mode, the data is also immediately transmitted when ENTER is depressed. In the Auto Wand mode, bar code data is automatically transniitted when a valid read is performed. Polled Mode ' In the Polled mode, when a keyboard message is prepared and the ENTER key depressed, the data is transferred to the transmit buffer. In the Manual Wand mode, the data is also transferred to the transmit buffer when the ENTER key is depress~d. In the Auto Wand mode, bar code data is automatically transferred to the transmit buffer when a valid read is performed. The transmit buffer is transmitted to the host processor whe;n the host sends tlie polling command (Request ADDRESS AE A4 A3 A2 A1 AD 00 01 02 0 0 0 0 0 1 1 1, 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 03 31 32 33 63 Nonpolled Addr,esa line. Ali throughAA: Logic Q=open LogiC? 1== jumper to signal ground. Add"ress extension Ae: Log ic 0 = ope" Logic 1;" jumper to ENABLE. pin 18. , The RS...422 interface must be used when more than one TM77B is connected to the conimunications interface. See Illustration section for suggested connections. Up to 63 microterminals may be connected to a single com-' munications part using RS-422. Since terminals are connected to the 'RS-422 interface in parallel, removing one terminal does riot break the, line or interface with operation of the remaining terminals.' '" ERROR CONTROL PROTOCOL The TM?7B has two types of error ,control mod~s Normal mode and Extended Controi mode. In Normal mode. data translllitted totli:e TM77B may contain parity for each character. If the microterminal receives a character with a parity error, that character wiIl be ignored but the remainder of the transmission wiIl be received. In Extended Control mode. the TM77B monit,ors parity for each i\1coming character as well as a checksum for each message. If the message is received correctly. the TM77B wiIl transmit an acknO,*,ledgement to the host CPU. If the TM77B detects a parity or checksum error. the entire message is ignored and a message is sent to the host CPU indicating that a,nerror has been received. 9-64 STATUS CONDITIONS ENTER is pressed; this is indicated by the display blinking. A bar code may be transmitted to the host computer by scanning a valid sequence. In Polled mode the Output Pending LED will come on until the host takes the keyboard or bar code message. The output buffer may be cleared by pressipg CEo Pressing a key to start a new message will automatically clear the output buffer has been cleared by CEo In addition, the Function Message -keys may be used to enter up to 16 different function messages into the output buffer. In Ready mode, when a message is received from the host computer, the first 16 characters of the message appear on the display. The Input Display LED comes on to indicate the display buffer is filled with a section of the input buffer. The entire message may be viewed by using ROL and ROR keys. When one of these keys is held down, the message will scroll through the display at approximately six characters per second. When any character key is pressed, the Input Display LED goes out and the character appears in the left-most part of the display with the rest of the display blanked. As other character keys are pressed, the message grows from left to right. DEL deletes the last character. If DEL is held down, characters will be deleted at approximately six characters per second. The TM77B will power-up in Auto Wand mode. The unit can be software-switched from one mode to another. Internally, the TM77B consists of 80-character receive and input buffers, a 16-character display buffer, 80character output and transmit buffers, and five 50character bar code data buffers. The display buffer is used to scan either the input buffer or the output buffer. It is switched from one to the other by pressing RECALL. When the display buffer is displaying the input bUller, the front panel Input Display LED will be on. Complete operating details are contained in the following section. MESSAGE WAITING \1essage Waiting status is the condition of being in Message Composition mode when the host sends an input message. The Message Waiting LED comes on to indicate a new input message is in the input buffer and may be viewed at the operator's convenience by pressing RECALL, ENTER or CEo When any ofthese actions are taken, the Message Waiting LED goes off until the host sends another message while the terminal is in Message Composition mode. In addition, if the host sends a new message before the input buffer had been examined, the message is held in the receive buffer. The Message Waiting LED ~tays on until the operator presses RECALL. This causes the message to be transferred to the input buffer. OUTPUT PENDING Output Pending status occurs when the terminal is used in a polled configuration, as determined by rear panel connector jumpers, and an output message has been enabled by the ENTER key. The message is actually transmitted when the host polls the terminal. Until this happens the Output Pending LED stays on. In many installations this will happen so quickly that the operator may never actually see the LED come on. However, if the host were temporarily occupied with another task, the operator would know that the message had not been transmitted. The message actually enters the transmit buffer and waits there until the terminal is polled. A second outp!!t message may be composed in the output buffer; however, if ENTER is pressed for the second message before the Output Pending LED goes off, the first message is lost. INPUT DISPLAY The Input Display LED indicates when the displa) buffer is viewing the input buffer. This can happen in two ways. When the terminal is in Ready mode, an input message will automatically switch the display buffer to the input buffer causing the Input Display LED to come on. The Ready Indicator will no longer be visible; however, the terminal is still in the Ready mode .. DETAILED KEY DESCRIPTIONS NUMERIC KEYS The numeric keyboard includes the digits 0 through 9, a minus sign and decimal point. GG FUNCTION MESSAGE KEYS ~ etc. These keys are used to input function messages from the keyboard. The function messages may be one of the default strings &XX or it may be a user-defined string. When no user-specified string definition has been provided, the three characters of the default string appear. For a user-defined value, the last 16 characters of the string definition appear in the display. I ncoming function messages appear with their first 16 characters in the display. The first eight function messages are put in the output buffer by pressing FI through F8 keys and the remaining eight by pressing # / FI through # / F8. When no message has been defined, default messages appear in the display as &ZZ. ZZ represents 01 through 08 for function keys FI - F8 and II through 18 for keys # / FI through #/ F8 for a total of 16 values. When the terminal is in Message Composition mode, pressing RECALL switches the display buffer to the input display causing the Input Display LED to come on. The terminal is still in Message Composition mode. Pressing RECALL a second time will return the display buffer to its former position in the output buffer. OPERATING INSTRUCTIONS When power is applied to the TM77B, the Input Display LED will come on and the display will show the Readv Indicator which is a /\ in the lett-most character position. A message consisting of up to 80 characters, including spaces, may be entered from the keyboard. Pushing the ENTER key causes the message to be transmitted to the host computer. The message will be sent each time 9-65 • I DISPLAY CONTROL GR Composition mode, clears Output Pending LED, and causes the Ready Indicator to appear. The output, input, and receive buffers are cleared. The transmit buffer is not cleared. Although the Output Pending LED goes off, the hQst may still read the transmit buffer. Host-specified function messages are unaltered. Pressing RESET. if enabled by the back panel jumper. has the same effect; plus it sets function messages to their default power-up condition and clears the transmit and five bar code buffers. In normal operation pressi.n~ ~iII cause the. message to move one character posItIOn to the left or until the last character of the message being examined is in the rightmost position of the display. Pressing causes the message to move one character to the right or until the first character of the message down causes the display to scroll by at approximately six characters per second until the first character is in the left-most, or the last character is in the right-most character position. Thus, in the Manual Wand mode, valid bar code data which is transferred to the output buffer can be inspected by pressing and B EJ RESET AUDIBLE OUTPUT The TM77B has audible outputs for the following functions: I. Successful bar code scan audible output. A single tone "beep" indicates that a bar code has been successfully scanned. 2 Buffer full audible alarm. A dual tone alarm signal indicates that the five bar code buffers (in Auto Wand mode) or the 80-character output buffer (in Manual Wand mode) are full and the terminal will not accept further inputs until data is transmitted. 3. BEL code audible output. A single tone "beep" indicates that a key has been depressed. Thisfeature is normally not enabled. It is enabled under control of the host CPU 4. Key depression audible indication. A single tone "beep" indicates that a key has been depressed. This feature is normally not enabled. It is enabled under control of the host CPU (ESC)Un(CR). The audible output signal is available as a TTL level signal, BEEPER. on pin to ofthe PI connector. BEEPER is active whenever the audible alarm is sounding. BEEPER is a positive true level which goes "high" when activated. B. IMUTI The RESET key allows the TM77B operator to initialize the internal functions. Pressing RESET is equivalent to turning on the power. Pressing RESET will cause hostdefined messages to be lost. RESET may be disabled when the TM77B is installed. SPACE KEY I-II SPACE causes a blank to be entered into the output buffer. The right-most character becomes a blank. DELETE KEY IKlml DELETE deletes the right-most character. ENTER KEY 111T1l I ENTER is used to send messages from the output buffer to the host sy'stem. The ENTER key is used to input bar code data when in the Manual Wand mode. RECALL KEY I_CAlli APPLICATIONS If it is desired to examine the input message before entering or even completmg the output message, the RECALL key may be pressed which causes the display buffer to be filled with the first 16 characters of the input message. The Input Display LED will come on. The input message may be examined by using and ~ . Pressing RECALL a second time will cause the di~y register to be filled with the 16 characters of the output buffer it contained when RECALL was pressed the first time. The Message Waiting LED is turned off. and remains off, after the first input message access with the RECALL key. Accessing the input message a second time fills the display buffer with the 16 characters it contained when the output message was accessed. Thus. if required, the operator can work through the input message composing an output message in response to small sections of the input message. CONTROL FEATURES Certain input messages may be used by the host system to put the TM77B in special modes. Much of this is explained by the input messages of the Input Message Summary part of the Communications Protocol section. Additional comments are provided here. SCROLL DISPLAY mode causes any input message. being observed through the display. to circulate continuously from right to left at approximately six characters per second. FLASH DISPLAY causes any input buffer display to flash with 50 percent duty cycle approximately three times per second. BLANK DISPLAY causes any output buffer display to have all segments off. The input buffer will still be displayed. KEYBOARD LOCKOUT inhibits use of the keyboard. except RESET. SCROLL and FLASH may be stopped by use of CE, CLR. or RESET. BLANK DISPLAY and KEYBOARD LOCKOUT may be terminated from the keyboard with RESET. El CLEAR ENTRY AND CLEAR ALL KEY 0 El Pressing CE causes the TM77B to exit Message Composition mode and the Ready Indicator to come on. The output buffer only is cleared. Pressing CLR causes the TM77B to exit message / --.,- j 9-66 REMOTE ENTER causes the input buffer to be transferred to the transmit buffer and sent to the host computer. It will also transmit bar code read data from the output buffer to the host computer if the TM77B is in the Manual Wand mode. REMOTE ENTER may be used to test the TM77B, communications lines and host processor communications circuits. REMOTE CLEAR causes the same action as pressing CLR. That is, the receive, input, and output buffers are cleared. The TM77B RAM has 415 character locations which may be used for function messages. The function messages may be any length less than or equal to 70 characters as long as the total number of characters does not exceed 415. This memory is assigned dynamically by the TM77B software. This means up to five messages may be 70 characters each if only five are defined. Attempting to exceed this boundary will cause unpredictable results. Alternately, a maximum of eight messages of 50 characters each could be defined. The RAM definitions are used by the TM77B until the RAM definitions are deleted. This may be done with the RESET key or from the host processor. Function messages may contain any of the I 28-character ASCII set. When control ASCI I characters are part of normal input messages, they are stripped; however, they may be part of commands such as function message definitions. All function messages are transmitted to the TM77B as (ESC)Z where ZZ represents 01 through 08 and 10 through 19. For output, &ZZ will be used as a default string if no message definition has been made in RA M. In this case the message will be transmitted as defined. The sequency (ESC)ZZ is considered to be part of a message. Do not confuse it with one of the (ESC) commands in the Input Message Summary Section. For example, (ESC)I(CR) is a complete and normal input message; it causes function message I to be put in the input buffer. Refer to Figure 4 which shows the Displayable Characters. DD L H L H L H D1 1 L H H L L H H D2 L L L L H L H H H H D6D5 D4 D3 ~ " ±J , , + L H L L l - I H L H L H H l n 1.1 I I I L H H H 8 H L L L 0] FI H l L H H L H l H l H H 0 J * J L "(I , :. I i- _1.1 L_ 1-( '--' .L T T U , i, LY c F< _J \I I "7 L \I 1\ _u I ,- t % ~~ -- c 6 1, , -J ---- -~ , i[ ,r- LJ I I U I - f I Cf ([ I L T, JJ , t_ T f I J n 1\11 .1 1 1\, ,1/ LJ LJ 1/ V V'I 1\ -- ,, ,, -, -' NOTE: All nondisplayable characters entered from keyboard are displayed as 1 I , I ~/::"I. FIGURE 4. Displayable Characters. TURN AROUND DELAY When commands that cause an automatic reply are sent from the host, the TM77B can delay its reply for a programmable turn around time. The purpose of this feature is to allow the TM77B to operate with any host terminal handler software which cannot accept input immediately following the carriage return of a host output message. This is the case in many host systems. This delay has a default value of 40msec. This may be changed by the host by using the command string (ESC)LDDD(CR) where DOD represents 000 through 254. This number sets the delay in increments of 10msec from 0 to 2.54 seconds. SELF TEST MODE The TM77B has provision for performing a self-test diagnostic routine. Self Test is entered by holding down any key while RESET is pressed and released. The message "RAMxxxROMxxxI/Oxxx" is put in the display buffer and the write/ read memory test is performed. If the memory test passes, a "+" is put after "RAM"; else if there is a failure a "-"is put in the display. Similarly, a program ROM checksum is calculated and compared with a ROM stored checksum. The same pass/fail indicator is displayed. The I/O is tested by a write/ read cycle to the internal 1/ 0 device, and rotating test is performed on the Status LED's. This sequence is repeated until RESET is pressed and released while no other key is pressed, which will then allow the TM77B to perform a normal power-up. During Self Test mode the TM77B is off-line and will not receive or transmit to a host processor. Self Test can only be accomplished if the back panel connector reset jumper is connected between pins 19 and CTRL X (Communication line entry only) The control character CAN(CTRL X) of the ASCII set has special meaning to the TM77B. When it is the first character of an input message, or the first character after the address characters in Polled operation, the TM77B will clear its receive and input buffers of previous messages and blink the Message Waiting LED once .. A new message following CRTL X will be in the input buffer. A command following CTRL X will be executed. This may be important for high priority messages to the operator. If the operator leaves the TM77B in Message Composition mode and two messages have been received, the first message will be in the input buffer and the second in the receive buffer. A third message or command will not be received unless (CTRL X) is used to clear the receive and input buffers. When the TM77B is in Ready mode, all messages come to the input buffer and the terminal goes to input display status. In this case the (CTRL X) has no effect on operation. 21. 9-67 COMMUNICATION DELAYS Some operations require a delay before the TM77B can accept another message or command. When a function message is defined, the TM77B requires at least 150msec before another message or command can be received. A host message which calls a predefined function message requires Imsec for each function message called before another message or command can be received. When software is written in a high level language, delays between messges will normally occur. When programs are writter. in assembly language on small systems such as single board computers, it may be necessary to design delays into the system software. Should the need arise, this is easily accomplished for high level languages as well. It is recommended that 110 commands to control port A for TM77B be followed by a 40msec. IMMEDIATE TRANSMISSION OF FUNCTION MESSAGES A function message can be transmitted immediately ifthe ASCII control character RS (Record Separator) is the last character of the definition. When this character is encountered while getting the function message from RAM or PROM, is is treated as ifthe ENTER key were pressed. This causes the function message to be transmitted along with any characters that were in the buffer when the function key was pressed. This feature, when used with CTRL 0, allows function message~ to have a completely user-determined.end-ofline character string. This is accomplished by defining a function message as follows: (ESC)D02(MESSAGE) (CTRL D)(RS)(CR). When the F2 fL'nction key is pressed, (MESSAGE) preceded by any contents of the output buffer, is immediately transmitted. (MESSAGE) mayinc1ude anv type ofline terminators such as (LF) or (EXT). (CTRL D) prevents the TM77B from adding a(CR) and (RS) causes immediate transmission without the use of the ENTER key. The use of(RS) is especially important for high priority control messages for which it is desired that only one key be pressed. . The only restriction on the message is the use of (CR). (CR) may not be contained in host-defined functio\l messages. This is necessary because an imbedded (CR) will terininate the function definition. COMMUNICATIONS PROTOCOL The TM77B sends and receives 7-bit asynchronqus ASCII character codes with one parity bit and two stop bits. One or two stop bits will be accepted for input. When parity is disabled, a mark or space as determined by P I jumpers is inserted for the parity bit. Parity may be even or odd and is selected by jumpers on PI. Characters with parity errors are displayed' as nondisplayable characters:ll. These jumpers also select tlie data receive and transmit rate. This rate may be 110,300, , 600, 1200,4800,9600, or 19,200bps.· Each message trans~it,ted from the TM77Bis terminated with a carriage return character. When operated in Polled mode, each message is preceded with its 2character polling drop number. This is not counted a.s part of the 80 character message. . Fo~ an input message, the TM77B requires that the message of up to 80 characters in length be terminated by a carriage return. Line feeds following a carriage return are discarded; otherwise they are .displayed as 110ndisplayable characters. Line feeds will be ignored as the first character of a message. A carriage return is not counted as one of the input chara<;ters. In Polled mode the message must begin with a drop number 00 through 63. This is followed by up to 80 characters plus II carriage return. When the host polls the TM77B. it must send (ESC)XXAA(CR) where XX is the drop number of the particular TM77B (01 to 63). Drop number 00 causes an input message to be received by all terminals. Function messages of up to 80 characters in length may be defined by sending (ESC)DZ(MESSAGE)(CR). In Polled mode this would be XX(ESC)DZ(MESSAGE) (CR). Z represents the function message number I through 8. Defined messages may·be deleted by sending a new definition or (ESC)kDZ(CR). (ESC)DO(CR) deletes all function message definitions. To call a function message to the display from the host, the host sends (ESC)ZZ within a normal message or merely (ESC)ZZ(CR). The display buffer shows tne defined function message when a definition is present in RAM. The defined Junction message is transmitted on output. When no message has been defined, &ZZ is shown in the display of input and output messages. &ZZ is also transmitted in output messages when no function message has been defined. It is important to remember the distinction between the host defining a function message and entering a message in the input buffer. The host may define function messages without entering them when they are for use by the operator through the function message keys. USER INPUT/OUTPUT PORT The TM77B has one 8-line input/ output port, referred to as Port A. It is accessed through a 14-pin connector. Each line will drive one TTL load. Port A is a user I/O port; It is a fully bidirectional bus, with an input strobe and an output strobe. It has two data modes - Decimal mode and ASCII mode. In Decimal mode, the data is encoded as three ASCII characters and represents the decimal numbers' 000 through 255. In ASCII mode. port data is encoded as single ASCII characters. Port A has two operational modes - continuous and noncontinuous. In the Noncontinuous mode data is 9-68 transferred one ASCII character (ASCII mode) or three decimal numbers (Decimal mode) per host processor command. In the Continuous mode data may be continuously transferred in and out of the port. The terminal responds only to the input message (ESC) which stops continuous input and output. In this mode, protocol is mostly determined by the host and the device connected to Port A. In the Continuous mode, the display holds the last display data and the keyboard is locked out. The Continuous mode is only usable in the Nonpolled mode. To summarize, port A has two data modes (ASCII and Decimal), two operational modes (Continuous and Noncontinuous) and may be used with or without parity. To characterize the operation of Port A, eight cases must be considered: ~,Noncontinuous, No Parity Decimal mode uses three characters to form a number from 000 through 255. This number gives full control to the eight output bits of Port A. For input from Port A, the eight bits are translated to a number from 000 through 255 and transmitted to the host as three ASCII characters. The most significant digit is received and sent first. This mode is convenient for applications programs written in a high level language such as BASIC or FORTRAN. The I/O statements of such languages will allow the applications program to communicate directly with Port A without the need to call assembly language subroutines. checked and the eighth bit has the same consideration as discussed in Decimal, Noncontinuous, No Parity. Decimal, Continuous, Parity The port operates in this mode exactly as in the previous mode except that parity is used. When a parity error is found in any of the three data characters from the host, the data is not output to Port A. Input from Port A will have the appropriate parity bit added for transmission to the host. ~, Noncontinuous, No Parity I n this mode, a single ASCII character is received from the host and output to Port A. Bit 8 of Port A is not controlled. No check of the eighth bit input to Port A is made. The eighth bit considerations of the serial communications line characters are the same as discussed in the Decimal, Noncontinuous, No Parity. On input from Port A the eighth bit of the serial characters transmitted to the host is set according to the jumpers on PI as a mark or space. A port output is illustrated by the string (ESC)Qa(CR). The "a" represents any of the 128, 7-bit, ASCII characters. ASCII, Noncontinuous, Parity In this mode, the port operates exactly as in the previous mode except that parity is used. When a parity error is detected in the host input data, no output to Port A is made. For input from PortA to the host, the parity bit is set appropriately, and the string (a)(CR) is transmitted to the host. On data input from the host processor, the eighth bit of each character may be a one or zero. If the host cannot control the eighth bit, it merely sends two stop bits. The TM77B will interpret the first stop bit as the eighth bit (B8=1) and the second as the stop bit. On output the TM77B will set the eighth bit to one or zero (mark or space) as determined by its connector jumpers. Use "bit eight equals one" to stimulate two stop bits if the host expects two stop bits. This is the case when no jumpers are connected (Mark parity). ASCII, Continuous, No Parity In this mode the host sends a continuous stream of characters (a)(a)(a) ... Input from Port A to the host is handled in a similar way. Bit 8 is not checked or altered by the TM77B, input from the port is transmitted as received. This means that the TM77B does not alter 8-bit data. The host and the device connected to Port A may send and receive parity if they choose. Thus, the TM77B serves only as a serial-to-parallel and parallel-to-serial converter. This mode is entered by the host sending the string (ESC)O(CR). The continuous operation (ESC) character terminates continuous operation. Decimal, Noncontinuous Parity This mode operates exactly as the previous mode except that parity is used. When parity error are found in Port A data from the host, the data is not output to Port A. Characters are sent to the host with the parity bit set appropriately. ~, Continuous, Parity In this mode, Port A data may be sent from the host as a continuous stream of 3-character data as follows: DDD(CR)DDD(CR) In this mode, the port operates as in the previous mode except that the terminal uses parity. If a parity error is detected in the continuous stream from the host, the character with the error will not be output to Port A. The terminal will set the parity bit on data input from the port. Input from Port A is handled ina similar way. Each input strobe causes DDD(CR) to be sent to the host. If Port A is strobed faster than the transmission line can take the data, more than three characters will be sent between carriage return characters. The last three will indicate the data correctly at the time of the last strobe. Decimal Continuous mode is entered by the command string (ESC)P(CR). Parity is not The decimal numbers from 000 through 255 represent all the 256 possible combinations of eight bits. Thus, each of the 8-bit lines may be individually controlled. To convert from the desired binary bit pattern to the corresponding decimal number the following method may be used. ~,Continuous, ~y DECIMAL MODE 9-69 1~1~1~1~1~1~1~1~1 TABLE II. Input Message Summary - Nonpolled Operation. 8 DDD = l: 2 N - 1= Ib, 2b2 + 4b,+ 8b. + --+128b. N-I (MESSAGEIICR) (ESC)A(CR) (ESC)B(CR) IESC)C\CR) IESC)DZ(MESSAGE)ICR) (ESC)DZ(CR) (ESC)DOICRI (ESC)En(CRI IESC)Fn(CRI IESC)Gn(CRI (ESC)HnICRI IESC)lnICRI I ESC )In( CR I IESC)KICRI I!,SCILDDDICRI IESC)M(CR) (ESCIN(CR) (ESC)D(CR) (ESC)PICR) IESCIOalCRI IESCIRDDDICRI IESCIT(CR) IESC)UnICR) (ESCIVm(CR) (CONTROL)X (ESC) Additional features are illustrated in Tables II, III, IV, and V and in the Control Features section. COMMAND DESCRIPTIONS The TM77B accepts a number of different Escape (ESC) sequences which serve as special commands. These commands consist of character strings starting with the ASCII control character (ESC) and terminated with a carriage return (CR). (ESC)A(CR) The A command polls the TM77B for any new output message which has been entered from the keyboard or bar code reader. This command may be used only once per message and is used only in Polling mode. (ESC)B(CR) The B command polls the TM77B for any new or old message in its output buffer. It may be used to cause the TM77B to transmit one entered message any number of times. NOTES: 1. Parenthesis are not actually encoded. Shown for copy clarity only. 2. (ESC) control commands may not be embedded in messages. 3. n = 1 for ON: n = 0 for OFF. 4. Z is function number, 1 to 8 5. "a" is ASCII character 6. m = 1 for Mlo Wand; m = 0 for Manual Wand. (ESC)C(CR) The C command clears the input buffer. (ESC)DZZ(MESSAGE)(CR) The D command used with a message is used to define function messages in the TM77B RAM. The ZZ must be any num ber character from 0 I through 08 and 10 through 19. When the MESSAGE is not included in the escape sequence, the ZZ function message definition is deleted. If ZZ equals 00 and the message is not included, all function message definitions are deleted. When function messages are deleted from RAM, they assume the default values &ZZ. Input message Request transmit buffer Retransmit transmit buffer Clear input buffer Define function mes:sage Delete function message Delete all function messages Output to A1 LED Output to A2 LED Scroll display control Flash display control Blank display control Keyboard lockout control Remote ENTER Set turnaround delay Read port A ASCII Read port A Decimal Port A continuous ASCII Port A continuous Decimal Output "a" to port A, ASCII mode Output to port A, Decimal mode Clears input, receive and output buffers Keyboard audible indication control Auto Wand/Manual Wand control Clears receive and input buffers Halt continuous I/O. TABLE Ill. Input Message Summary- Polled Operation. XX(MESSAGEIICRI Input message XXIESCIA(CRI Request transmit buffer XXIESC)BICR) Retransmit transmit buffer XXIESCICICRI Clear input buffer XXIESCIZZIMESSAGEIICRI Define function message (ESC)En(CR) This command is used to set the AI LED on or off. If n=l, the LED is turned on. It is turned offfor n=O. The back panel AI TTL output is pulled low when the LED is on. XXIESCIZZICR) Delete function messages XXIESCIDOICR) Delete all function messages XXIESCIEnlCRI Output to A1 LED XXIESCIFnlCRI Output to A2 LED XXIESCIGnlCRI Scroll display control XXIESCIHnlCRI Flash display control XXIESC)lnICRI Blank display control XXIESCIJnlCRI Keyboard lockout control XXIESCIKICRI Remote ENTER XXIESCILDDDICRI Set turnaround delay TM77B (ESC)Fn(CR) This command serves for A2 as the previous E command does for AI. XXIESCIMICRI XXIESC)NICRI XXIESCIOalCRI XXIESCIRDDDICR) XXIESCITICRI XXIESCIUnlCRI XXIESCIVmlCRI (ESC)Gn(CR) When n= I, the display continuously scrolls through the input buffer. Scrolling is stopped with n=O. Read port A, ASCII Read port A, Decimal Output to port A, ASCII mode Output to port A, Decimal mode Clears input. receive, output buffers Keyboard, audible indication control Auto Wand/Manual Wand control NOTES: 1. Continuous 110 not allowea in polled operation. 2. A poll address of 00 on an input message or command will be accepted by all terminals, but any transmission will be suppressed from the terminals. 3. n = 1 for ON; n = Olor OFF. (ESC)Hn(CR) When n=l, the display flashes message in the input buffer. The flashing is stopped with n=O. 9-70 (ESC)RDDD(CR) Outputs three characters, "DOD", to port A, Decimal mode. TABLE IV. Output Message Summary Nonpolled Operation. MESSAGE(CR) Response to ENTER. (ESC)A(CR). (ESC)B(CR) or a(CRI Response to (ESC)M(CR). ASCII mode DDDICR) Response to (ESC)N{CR). Decimal mode (CR) Response to (ESC)A(CR). (ESCIB(CR). or (ESC)K(CR) (ESC)T(CR) The T command clears input and output buffers and places the TM77B in Ready mode. Action is same as using the CLR key. (ESC)K(CR) when output buffer is empty. (ESC)Un(CR) The U command controls the keyboard audible indication signal. When n = I, an audible signal indicates each key depression. When n=O, there is no audible signal on key depression. n=O is default state. TABLE V. Output Message Summary - Polled Operation. XX(MESSAGEIICR) Response to XX(ESCIAICRI. XX(ESCIB(CR). or XX(ESC)K(CR) XXaCR Response to XX(ESC)M(CR). ASCII mode XXDDD(CR) Response to XX(ESC)N(CR). Decimal mode XX(CR) Respons. to XX(ESC)A{CRI. (ESCIB{CR). or (ESC)Vm(CR) When m=I, the Auto Wand mode is enabled. When m=O, the Manual Wand mode is enabled. (ESC)K(CR) when the buffer is empty. NOTES: 1. XX = polling drop number 01 through 16. 2. ZZ = function message number 01 through 08 or 10 through 19. 3. a = ASCII character to or from port A. 4. DOD = Decimal number 000 through 255 transmitted as three CONTROL X The control X command character clears receive and input buffers even if both are full. This command is the only one without the ESCAPE character and not terminated with a carriage return (CR). The sequence (CONTROL X)(ESC)T(CR) guarantees that the receive, input and output buffers are cleared. characters. 5. n =control cnaracterO= Off, 1 =on. (ESC)In(CR) When n= I, data in the output buffer from the keyboard or bar code reader is not displayed. Data from the host processor in the input buffer is displayed normally. Data is transmitted normally even when the output display is blanked. Blanking is stopped when n=O. INSTALLATION Installation of the TM77B consists of mechanical mounting and back panel or edge connector wiring. The TM77B is designed to be mounted on a flat surface. Its back panel provides six threaded holes for attachment; screws are provided. In addition, cutouts must be provided for access and clearance to connectors PI and P2. Required mechanical dimensions are discussed later. Connector wiring for PI (see Figure 5) may be accomplished with the aid of Tables VI, VB, and VIII. It is only necessary to connect +5V power, supply return, data transmit (TX), data receive (RX), and signal ground to make the TM77B functional. Note that supply return and signal ground are internally connected only if the 5VDC power supply option is used. Without further connections the TM77B will operate at 300bps; a marking parity bit, non polled operation, and the front panel RESET key disabled. Baud rate and polling addresses are set by connecting the indicated pins to signal ground (pin 7) on the mating connector. Parity and AE, the polling address extension, are set by connecting the indicated pms to ENABLE (pin 18). The RESET key is enabled by connecting a jumper between pin 19 and pin 21 of PI. Request to Send and Clear to Send RS-232-C functions are operative if required by the host system or modem. Clear to Send input is active if left open-circuited. Data Terminal Ready output is continuously active (detailed connection diagrams are provided in Figures 10 and II). The RESET key will be disabled at installation if no jumperis installed from pin 19 to pin 21 of P I. When this jumper is removed, the RESET function may be done by a remote switch or a TTL signal through Pin 19 (see Figure 6). When the jumper is installed, the front panel (ESC)Jn(CR) When n=I, the keyboard is locked out. The keyboard is enabled if n=O. This command does not affect bar code data. (ESC)K(CR) The K command moves data from the input buffer to the transmit buffer for immediate transmission. This command is used for testing communications circuits and lines. (ESC)LDDD(CR) This command sets the delay time from receipt of a command from the host processor to the automatic replay. DOD is OOOmsec to 255msec. Default is 4Omsec. (ESC)M(CR) Reads port A once in ASCII mode, one character. (ESC)N(CR) Reads port A once in Decimal mode, three characters. (ESC)O(CR) Sets port A to continuous, ASCII mode, non polled only. (ESC)P(CR) Sets port A to continuous, Decimal mode, nonpolled only. (ESC)Qa(CR) Outputs one character, "a", to port A, ASCII mode. 9-71 TABLE VII. Baud Rate Selection: RESET key may be used to initialize external devices. A "wired OR" connection may also be made. aaudRale TABLE VI. Listing of Connector PI pins. R8..zu..C 1 2 3 4 Supply Return } TX RX RS-232-C Request to Send Output 5 6 7 8 Clea, to Send Input 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Al lEO Signa' Ground A2lED ;q, BEEPER BAUD 80 BAUD Bl BAUDB2 24.VAC/5VDC Power In Parity PO ParityP1 Address Extension ENABLE RESET IN Data Terminal Ready Output RESET OUT Aii Ai Ai } Polling Address ~ B1 BO, 1 f 600 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1200 2400 4BOO 9600 19200 110 R_ 1 2 3 4 B2 300 ~~J~YRT} -OUT , RS-422 +IN 5 -IN 6 AllEO 7 Signal Ground 8 A2lED 9 ;g 10 BEEPER 11 BAUD eo '12 BAUD B1 13 BAUD B2 14 24VAC/5VDC Power In 15 Partty PO 16 Parity P1 '17 Address ExtenSIon 18 ENABLE 19 RESET IN 20 Data Terminal Ready Output 21 RESET OUT 22 Jill 23 AI } Polling Address 24 Al! 25 A3 ,0 0 0 Logic 0 = jumper to signal ground (pin 7) Logic 1 = open TABLE VIII. Parity Bit Selection. ,Parity alt PO P1 SPACE 0 1 EVEN 0 0 000 1 0 MARK 1 1 (MARK = logic 1 I Parity errors displayed as # Mark/Space not detected on input logic 0 = jumper to ENABLE l"llic 1 = open (pin lBI ACClpts #4.... Icraw i------ 1.852IREF] - '- - - j I 13 Pin 1 Interface to the P2 I/O ports (shown in Figure 7)' may be accomplished by reference to Figures 8 and 9 and Table 000000000000 000000000000 14 25 IX. r 0.10 TYP MIIII with - lWR Cinch OB-25P Burr-Brown 2525MC 131 0,\0 PIN 1 -t--,I-.·••••••1 L 14 2 1 -······· Tha 2525MC clIIIIllII pf Ibl following AMP Inc, part nURlblrs: 1. Mil. HOP conneclDr . 205208· f 2, Individual plnalaolder connlctor)· 1.fi6508-0 3.. Hind IDDIID Inaart plna in connlctor - 91067-2 4. Mila Icraw ratalnlr kit -205980·1 5. Shield IIlImbly -20571B·l 0.025 SQUARE POST MATES WITH RIBBON CABLE CONNECTORS FIGURE 7. 14-Pin Connector P2 Back Panel View. FIGURE .5. 25-Pin 0 Style Connector PI Back Panel View. DATA. -:===x x==.PORT AINPUT DATA ---l I-- 800nIIC min. IS INPUT STROBE - - - , \ HHJH/UiuHH/JUL FROM TM77B +5VOC I-Hil' R F 8, Output Timing. CPU RESET 20kn RESET FRONT PANEL KEY ,0.. UO~I RESET fN DATA =::x ----I I-- ~..,~ ~ Os OUTPUT STROBE 21 FIGURE 6. Reset In and Reset Out Equivalent Circuit. 9-72 >e:)ORT AOUTPUT DATA BOOnllc. min. ~FROM TM77B ----I1 1I- 1.6.alc. min. FIGURE 9. Input Timing. SPECIFICATIONS TABLE IX Listing of Connector P2 Pins - TM77R 1 2 3 4 5 S 7 8 9 10 11 12 13 14 Signal Ground DISPLAY Number of Characters I nternal Buffers Receiver Input Output Transmit Bar Code Type of Digit Display Character Height FUNCTION LIGHTS AO AI A2 A3 A4 Port A: Input and Output A5 AS A7 OS Output Strobe is Input Strobe Signal Ground 24VAC 24VAC Return NOTES: 1. Logic positive true for port A. 2. Logic low 0.4V at I.SmA. Logic high 3.5V at l00"A. Host Controlled Lights Status Lights 3. Mating connector - Burr-Brown mode12014MC. RS-422 Type of Light KEYBOARD RS-422 electrical connections are in Figure 10. All terminals are connected in parallel. Note that resistors are recommended at the end of the transmission lin". Type of Keyboard Number of Function Keys User Programmable MATERIALS Front Panel Back Panel r ~20011 + OUT ~ +15V lkll HOST CPU + .!!! lkn I ~20011 20011 IN + -lOUT I I +TM17B IN + I FIGURE 10. RS-422 Electrical Connections. 4kn IOkn ~ LJ. TX ~ +12VDC 1I8On 1470PF Polycarbonate Black Anodized Aluminum ABS Plastic Operating Storage POWER SUPPLY O"C to +50"C O°C to +60°C Nominal Voltage Range 15VAC to 28VAC 22VDC to 40VDC 420mA 580 grams'(20 oz.) Current WEIGHT COMMUNICATION INTERFACE Maximum Transmission Distance RS-422 RS-232-C / V.24 RS-422 Differential Output Voltage (open circuit) Output Impedance (when active) Output Impedance (when inactive or (power off) MARK ';;·3.OV SPACE,;; +3.0V FIGuRE II. Input Equivalent Circuit. 2 Alphanumeric! Numeric Si){teen Yes, up to 70 Characters each TEMPERATURE RANGE Figures II and 12 show the RS-232-C equivalent input and output circuits. 3 Two Three message waiting/ output pending/ input display Red, LED DO NOT USE FLUOROCARBONS (TMC, FREON, ETC.) TO CLEAN. RS-232-C RX~ 80 characters 80 characters 80 characters 80 characters 5 x 50 characters 16-segment 3.6mm (0.14") Case The front panel will be attacked by these chemicals: Chlorinated or Fluorinated Hydrocarbons PVC Plasticizing Agents Amines .I *- - OUT +I TM778 16-alphanumeric ·12VDC Short circuit protected Output Current (short circuit to Groundl > ±3mA Mark,;; ·6.0V with 31m load Space:;, +6.oV wllh 3kn load NOTE: ±12V are generaled Irom +5V by an Internal DC 10 DC converter. FIGURE 12. Output Equivalent CIrCUIt. 9-73 1200 meters (4000 feet) 15 meters (50 feet) 5V 100,(1 250k!1 Differential Input Voltage Input Impedance RS-232-C Modem Control Signals Output Voltage Logic I Logic 0 Input Voltage Logic I Logic 0 BAR CODE READER Codes Available Code 39 UPC/EAN Two of five I nterlea ved two of five Coda bar Other codes available upon request 6V or less 60000 (minimum) ACCESSORIES Yes 25-pin mating connector - 2525MC 14-pin mating connector for I/O ports - 2014MC -IOVDC +IOVDC -3VDC to +15VDC + 3VDC to +15VDC MECHANICAL DIMENSIONS Figure 13 shows the mechanical dimensions for the TM77B BlICk Anodized Aluminum ABS Plillic TJPIIIII 01 Six MllHlllna HIIII.I#4-40 In.rt 0.3110" : :.Ll ! 3.900" 0225: *TM7WOor TMm/O Fj 8.51" 1 t TM77B IIlblpped wllb Ilx .4-40. 3IB-lnch pm held IInWi. FIGURE 13. Mechanical Dimensions. DIGITAL INPUT/OUTPUT PORT TTL Compatible Yes Number of I/O Lines Eight Input strobe One Output drive One TTL load ENVIRONMENTAL SPECIFICATIONS O°C to 50°C 95% relative humidity noncondensing Contact factory for extended temperature range MICROCOMPUTER I/O SYSTEMS Thisfulliineof ~Ccompatible 1/0 boards is available off-the-shelf. Design features let you put your microcomputer-based system together fast, using these analog and digital 1I0's that offer: simple software requirements; memory-mapped designs; up to 64 input channels per board; analog inputs and outputs on the same board; 8- or 12=bit resolutions; software programmable gains; relay outputs; isolated digital 1/0. Plug compatible with Intel, DEC, National, Motorola, Rockwell, Zilog, Synertek, AMC and others. SELECTION GUIDE DIGITAL 1/0 Compatible With Microperipheral Model Motorola(1) and RockwelH2) MP701 MP702 MP710 MP710-NS Intel(3) and National(4) MP801 MP802 MP810 MP810-NS i Input Number Channels Output ·· ·· ·· ·· Features ~ Page Relay output Relay output Contact closure input Voltage input 335.00 555.00 410.00 335.00 10-2 10-2 10-4 10-4 Relay output Relay output Contact closure i.npU1 Voltage input 335.00 555.00 410.00 335.00 to-6 10-6 10-8 10-8 Output Features ~ Page 4 General purpose General purpose PGA(8) 550.00 550.00 695.00 10-10 10-12 10-12 General purpo.se 2 AllAp· on ohe board 665.00 825.00 10-15 10-15 4 4 General purpose General purpose General purpose General purpose Low cost Low cost AI/AD on one board Low cost AI/AO on one board Low cost AI/AD on one board Low cost AI/AO on one board Isolated outputs Overvoltage protect. 4mA to 20mA inputs 725.00 608.00 725.00 725.00 450.00 375.00 489.00 289.00 409.00 489.00 609.00 409.00 532.00 695.00 595.00 595.00 10-17 10-17 10-17 10-17 10-21 10-23 10-23 10-23 10-23 10-23 10-23 10-23 10-23 10-25 10-27 10-27 General purpose General purpose General purpose 4mA to 20mA inputs Voltage output General purpose All AO on one board PGA(8) PGA(8) Use with MP8418 Low cost AI/AD on one board Low cost All AD on one board Low cost All AD on one board 695.00 518.00 550.00 650.00 550.00 595.00 795.00 650.00 850.00 495.00 470.00 625.00 375.00 470.00 589.00 750.00 10-29 10-29 10-29 10-33 10-33 10-35 10-35 10-35 10-35 10-39 10-41 10-41 10-41 10-41 10-41 10-41 Isolated ··· ·· ·· · 16 32 24 24 16 32 24 24 ANALOG 1/0 Inputs Compatible With Microperipheral DECIS) MPll04 MPI216 MPI216-PGA ZiI09(6) Motorola(1) and Rockwell(2) Intel(3) and National(4) Model MP2216 MP2216-AO MP7104 MP7105-NS MP7208 MP7216 MP7218 MP7408 MP7408-AO MP7408-NS MP7408-NS-AO MP7432 MP7432-AO MP7432-NS MP7432-NS-AO MP7504 MP7608 MP7608-1 MP8304 MP8305 MP8305-NS MP8316-1 MP8316-V MP8418 MP8418-AO MP8418-PGA MP8418-PGA-AO MP8418-EXP MP860B MP8608-AO MP6616 MP8616-AO MP8832 MP8832-AO Ana)og .Input ·· ·· ·· ·· ·· · ··· · ·· Ana)og Output · ·· · · ~~~;I ·· ·· ··· ·· ··· ·· · ·· ~:I ··· · ··· · ··· ·· ·· · · · ·· ·· ·· ·· ·· ·· ·· ·· · ·· ·· ·· · · ·· · ··· ··· ·· · ·· ·· · · · · Analog Reso- lution ;h~~~:~S _Input 12 12 12 32SE 32SE 12 12 32SE 32SE 12 12 12 12 12 8 8 B 8 8 8 B 8 8 12 12 12 12 12 12 12 12 12 12 12 12 8 8 8 8 B 8 8DIF 16SE 16SE 16SE lSSE 16SE 16SE 64SE 64 SE 64SE 64SE 2 2 2 2 4 8DIF 8DIF 4 4 4 16 16 32SE 32 SE 32 SE 32 SE 96SE 8DIF BDIF 16SE" l6SE 64 SE 64SE 2 2 2 2 2 NOTES: 1) Micromodule and EXORcise"'. 2) SYSTEM 65. 3) MULTIBUS™, SBC80. ICS80 and In!ellec MDS. compatible. 41 BLC80. 51 LSI-11. LSI-11/2. LSI-l 1/23. PDP-l 1/03, and PDP-l 1/23. 6) Z-60 MCB and Z-80 MCZ. 71 Software programmable gain. 10 -1 MP701 MP702 BURR-BROWN® IElElI MICROCOMPUTER DIGITAL OUTPUT SYSTEMS DESCRIPTION The MP701 and MP702 are digital output microperipheral boards designed to be used with Motorola 6800 microcomputer systems. The microperipheral boards are electrically and mechanically compatible with Motorola's Micromodule and EXO Rciser development system. The MP701 has 16 digital output channels, and the MP702 has 32 digital output channels. Each digital output channel is implemented with a protected reed relay. Relays are used to provide low "on-impedance", high output current and output isolation. Each output is isolated from the computer bus up to 600VDC and from channel to channel up to 300VDC. This means that the computer is protected from voltage transients and malfunctions. In addition, since each channel is isolated, the voltage switched by each line is not critical, and ground loops are avoided. The varistors protect each relay contact by suppressing high voltage transients such as those encountered in inductive circuits. These boards appear as memory locations to the user. Data written on the data bus controls the status of each output. A "I" will close an output, a "0" will open an output.Any memory write command may be used. Each write command controls the status of eight channels. Address bits AO and A I on the MP702 and AO on the MP701 select which set of eight outputs are controlled. The remainder of the address lines are used to select the board itself. Because the address block occupied by each board is user selectable, it can be placed anywhere in memory. AI5 A1 VUA VMA ANi :. i:====~~==:L~~fi AD : Internallonal AlrtJtlrt Induslrlal Park· P.O. Box 11400· Tucson. Arizona 85734· T81. 16021 746·1111 • Twx: 910-952·111 I . Cable: 88RCORP . T8lex: 66-6491 PDS·38I 10-2 OPERATING INSTRUCTIONS SPECIFICATIONS Typical at +25°C and rated supplies unless otherwise noted. PROGRAMMING ELE'CTRICAL Each digital output channel appears as one bit of memory to the microcomputer. The channels are selected in groups of eight by AO on the MP701 and by AI-AO on the MP702. Writing a I to an output channel closes the output contact; writing a 0 to an output channel opens the output contact. Once an output is defined, it will remain in that state until redefined by another write to that byte. For example, to open channels 0, 2, 6, and close channels I, 3,4, S, 7 with an MP702 as shipped from the factory execute: NUMBER OF CHANNELS MP701 MP702 16 J2 . DIGITAL OUTPUT Wans DC (resistive load) max Amps (resistive load) max Voltage (resistive load) max Life (resistive load) min Initial contact resistance max Actuate Time De-Actuate time Bounce time 10 watts .5 amps 28 Vrrns IO~ operations .2 ohms 250J.tsec LDA #$BA STA $9IFC where BA (10 II 1010) is the data written to the board and 91 FC is the address of channels 0-7. Refer to Table !for a description of which data and address lines control which output channels. 250llsec 150,",sec TRANSIENT PROTECTION Continuous power rating Discharge capacity 250mW 30 watt-second!. COMPUTER BUS All signals compatible with Motorola EXORciser and Micromodules system Logic Loading Output Coding 1 LSTTL o Open Contact I Close Contact POWER REQUIREMENTS Voltage Supply Drain max, MP701 Supply Drain max, M P702 5V DC, ±5(ii volt!> .4 amp .7 amp ISOLATION VOLTAGE Between microcomputer bus and outputs Between outputs OPERATING TEMPERATURE 600VDC .JOOVDC o to +70"C Data Bus D7 D6 DS ADDRESS LINES (AI, AO) 01 .10 II IS 23 31 14 22 30 21 13 29 D4 12 20 28 i53 II 19 27 ill 18 10 26 DI I 17 9 25 DO 8 16 0 24 Channel Number TABLE I. Data - Address - Channel Relationship. o = open, 1 = close. 00 7 6 5 4 3 2 The M P70 1 and M P702 are passive during a read to their memory locations. Therefore, other memory or I/O devices may be placed at the same address without interfering with the microperipheral's activities. DIGITAL OUTPUT CHANNEL MECHANICAL Compatible-with Micromodules and Exorciser card spacing. Minimum card spacing: 12.7mm (OS'). Microcomputer bus connector required: 86 pin PC edge connector with 0.IS6~ contact centers (SAE-43D / 1-2). SO pin output edge connector on board. A mating connector is available from Burr-Brown: 2250MC (Viking #' 3VH25/ \JNS, solder tab). a Scotchflex connector is available from 3M: 34IS-0001. Each output is capable of switching an inductive load. Transient suppressors are used across each output switch to protect the output relay from damage due to surges when the contact is opened. A typical output circuit and the load circuit that it might drive are shown in the figure below. -+~ + --±J ~. I Top Connector ~-.....~-t.. , "* Transient Suppressor Each relay is rated to .S amps and 100 volts maximum. The transient suppressor reduces the maximum voltage to 28Vrms. 10-3 BURR- BROWN@ IElElI MICROCOMPUTER DIGITAL INPUT SYSTEM A 24-CHANNEL ISOLATED DIGITAL INPUT SYSTEM COMPATIBLE WITH MOTOROLA MICROMODULE/EXORciser@ AND ROCKWELL SYSTEM 65 -12VOC A15-+A :":D=:DR:':"ES:':"S7.'BU:::"S-'\I A2-+==':":":;'-,1I OPTICAL ISOLATOR ~--+-O~ INPUT t---t-o!!! CIRCUITRV --- T vpical of 24 thannels '2·~-----lr::~, A°ot-------L....,._.t-' Alo+-------t ____-t+~12·VDC r -;iiLA-rEii' ISOLATED DC/DC CHANNELS 0·7 -IZVDC DATA BUS CONVERTER (Optional) t--_ _ _-++.'2VDC CHANNELS 8 ·15 -12VDC +12VDC t--:C:-:-:H":":AN::::N-="=EL"::"S:-:,6"""'.2::"3t-o_I-2VDC FEATURES • ISOLATED FROM COMPUTER BUS AND CHANNEl TO CHANNEL • CONTACT CLOSURE OR VOLTAGE INPUTS • REDUCES SYSTEM DEVElOPMENT TIME System engineered and specified Plug compatible Easy to program Operates from computer power supply • 70°C BURN-IN International Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tal. 1602\ 746·1111 . Twx: 910-952·1111· Cable: 8BRCORP· Talex: 66-6491 PDS-386A 10-4 DESCRIPTION SPECIFICATIONS Typical at +25°C and rated supplies unless otherwise noted. This microperipheral board provides 24 digital input channels that interface electrically and mechanically with Motorola Micromodule® and EXORciser® microcomputers. It is contained on a single printed circuit board that operates from the computer's +5VDC power supply. Digital inputs enter through a card edge connector located opposite the bus connector. The MP71 0 operates with dry relay contacts - MP71 Q-NS operates with voltage inputs (wet relay contacts). The MP710 may be modified by jumper selection to operate with voltage or contact closure inputs, or a mixture of both. Inputs are arranged in groups of eight. Each group is isolated from other groups and from the computer bus up to 600 VDC. Isolation between inputs is 300 VDC (MP71Q-NS). Isolation protects the computer from voltage transients and malfunctions. In addition, since each input is isolated, the voltage switched by each line is not critical and ground loops are avoided. MP710's are programmed as memory locations. Each input is one memory bit and any read command may be used. When the board is read, logic 0 represents an open contact (low voltage); logic I, a closed contact (high voltage). Each read command inputs the status of eight channels. Address bits AO and A I select the set of inputs to be read. The remainder of the address lines are used to select the board itself. The address block occupied by each board is selectable and can be located anywhere in memory. ELECTRICAL INPUT CHARACTERISnCS Number of Channels Input Impedance Input Delay Times Open to closed Closed to open MP71~NS Minimum voltage to detect a logic I Maximum voltage to detect a logic 0 17V 4V CONTACT CLOSURE SENSE RdOHd MP710 (on board ±12V supply) 6kO. max MP71~NS at 24V across contacts at 48V across contacts at 60V across contacts 6kfl, max 30kO. max S8kn. max Ropon MP710 (on board ±12V supply) SOkU. min MP71~NS at 24V across contacts at 48V across contacts at 60V across contacts Maximum voltage (Vs) across input without damage MP710 MP7J~NS ISOLATION VOLTAGE Between microcomputer bus and inputs Between inputs (MP7J~NS only) Between groups of 8 inputs POWER REQUIREMENTS MP710 MP71~NS COMPUTER BUS All signals compatible with Motorola Micromodule and EXORciser systems Logic loading Input coding INSTALLATION These units are shipped from the factory ready for immediate use. Installation requires only plugging the card into any empty slot in the computer and wiring the input connector. Compatible with Micromodule and EXORciser card spacing. Minimum card spacing: 12.7mm (0.5''). Microcomputer bus connector required: 86 pin PC edge connector with 0.156" contact centers (SAE-43D j 1-2). Two 50 pin output edge connectors on board. A mating connector is available from Burr-Brown: 2250MC (Viking # 3VH25j lJN5, solder tab). A Scotchflex connector is available from 3M: 3415-0001. 25",5, max lOOps. max VOLTAGE SENSE @Motorola MECHANICAL 24 ISkn TEMPERATURE RANGE Operating SOkIl. min 17Skn. min 23Skn, min 120V AC, nns, max 6OVDC, max J68VAC, rms, max 84VDC, max 600VDC 300VDC 600VDC , +SVDC ±S% at 400mA + 12VDC ±S% at IOOmA +SVDC ±S% at 400mA I LSTTL Load Logic 0: open contact Logic I: close contact o to +70"C TABLE I. Electrical Specifications DEFINITION OF SPECIFICATIONS INPUT DELAY TIME OPEN TO CLOSED ~ The delay required to detect an input contact closure switching from open to closed. CLOSED TO OPEN ~ The delay required to detect an input contact closure switching from closed to open. CONTACT CLOSURE IMPEDANCES Rn.OSED • The impedance of an input contact closure when closed. Rn.OSED specifications are the maximum impedance allowed to reliably detect a closure. See Figure I. ROPEN - The impedance of an input cont.act closure when open. ROPEN specification is the lowest impedance allowed to reliably detect an open contact. See Figure I. 10-5 MP801 MP802 aURR - BROWN ® I E:IE:I I MICROCOMPUTER DIGITAL OUTPUT SYSTEMS A 16- OR 32-CHANNEL RELAY OUTPUT SYSTEM COMPATIBLE WITH INTEL SBC80 AND INTELLEC MDS MICROCOMPUTERS A 0 RF -+-:-:=-=-=-::--:-:-:' AOR2 - - j - - - - - - , ADDRESS DECODER TRANSIENT PROTECTION XACK -+-------i MWTC <:r-t-------t CONTROL AOR1 < : r - t - - - - - - - - - . . . . LOGIC r-~..., TYPICAL Of32 OUTPUTS AORO<:r-~-------~ DO -+-=--DA::-T-:-A-B'-:-:U""S ii7 DATA BUS l-----+~ INTERFACE 1-------+--. FEATURES -ISOLATED FROM COMPUTER BUS AND GHANNEl TO CHANNEl - TRANSIENT PROTECTION • EASY TO PROGRAM AND USE - MEMORY-MAPPED • BURNED-IN International Airport Industrial Park - P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 7411·1111 . Twx: 910-952·1111 - Cable: BBRCORp· Telex: 66-6491 PDS-384 10-6 DESCRIPTION MECHANICAL The MP801 and MP802 are digital output (contact closure) microperipheral boards that are electrically and mechanically compatible with Intel's SBC80 and Intellec MDS microcomputer systems. The MP801 offers 16 digital output channels and the MP802, 32 digital output channels. Each channel is implemented by a protected reed relay and can handle up to 10 watts. Relays provide low "onimpedance" and high output current and isolate output channels from the computer bus and from channel to channel. Isolation insures that ground loop problems are avoided. The computer is protected from component failures caused by voltage transients and malfunctions occurring in the outside world. M P80 I and M P802 appear as memory locations and data written on the data bus controls the status of each output. A logic I will close an output. A logic 0 will open an output. Any memory write instruction may be used. SPECIFICATIONS Typical at +2S oC and rated supplies unless otherwise noted ELECTRICAL NUMBER OF CHANNELS 16 32 MP801 MP802 DIGITAL OUTPUT Watts DC (resistive load) max Amps (resistive load) max Voltage (resistive load) max Life (resistive load) min Initial contact resistance max Actuate Time De-Actuate time Bounce time 10 watts 0.5 amps 28 Vrrns IO~ operations 0.3 ohms ImSec 250psec 150",sec Compatible with SBC 80 and Intellec MDS card spacin~. Minimum card spacing: .I2.7mm (OS'). Microcomputer bus connector required: 86 pin PC edge connector with 0.156" contact centers (SAE-43D/ 1-2). Two 50 pin output edge connectors on board. One is used for MP801, both are used for MP802. A mating connector is available from Burr-Brown: 2250MC (Viking # 3VH25/ IJN5, solder tab). A Scotchflex connector is available from 3M: 3415-0001. OPERATING INSTRUCTIONS PROGRAMMING Each digital output channel appears as one bit of memory to the microcomputer. The channels are selected in groups of eight by ADRO on the MP801 and by ADRIADRO on the MP802. The remainder of the address lines are used to select the board itself. Because the address block occupied by each board is user selectable, it can be placed anywhere in memory. Writing a logic I to an output channel closes the outputcontact; writing a logic 0 to an output channel opens the output contact. Once an output is defined, it will remain in that state until redefined by another write to that byte. For example, to open channels 0, 2, 6, and close channels I, 3, 4, 5, 7 with an MP802 as shipped from the factory execute: MVI A, BAH STA F700H where BA (10 II 10 I0) is the data written to the board and F700 is the address of channels 0-7. Refer to Table II for a description of which data and address lines control which output channels. TRANSIENT PROTECTION Data Continuous power rating Discharge capacity Leakage current through transient suppressor at 28V Bu, 2S0mW 30 watt-second!. D7 D6 SmA OS 54 COMPUTER BUS All signals compatible with I nteI and MDS Systems Logic Loading Output Coding OJ sse 80 52 I LSTTL o Open Contact I Close Contact POWER REQUIREMENTS Voltage Supply Drain max. MP801 Supply Drain max. MP802 SVDC. ±S% 0.3 amp 0.5 amp ISOLATION VOLTAGE Between microcomputer bus and outputs Between outputs OPERATING TEMPERATURE Di Do 00 7 6 5 4 3 2 I 0 ADDRESS LINES (A I, AO) 10 01 15 14 13 12 II 10 9 8 23 22 21 20 19 18 17 16 II 31 30 29 28 27 26 25 24 TABLE II. Data - Address - Channel Relationship. Logic 0 = open, Logic I = close. The MP801 and MP802 are passive during a read to their memory locations. Therefore, other memory or I/O devices may be placed at the same address without interfering with the micro peripheral's activities. 600VDC 300VDC o to +70"C TABLE I. Electrical Specifications 10-7 MP810 BURR - BROWN ® IElElI MICROCOMPUTER DIGITAL INPUT SYSTEM A 24-CHANNElISOlATED DIGITAL INPUT SYSTEM COMPATIBLE WITH INTEL SBC80. NATIONAL BlC80 AND INTEllEC MDS +12VDCCj) Cj)-12VDC F ADDRESS BUS 2 Y rB= -B II " 0",,,, ADDRESS DECODER ISOLATOR INPUT CIRCUITRY Typical of 24 channels , oA ( D7 DATA BUS .. DATA BUS INTERFACE -' CONTROL I f 'oo" -1 ~ BUFFER +12 VDC ISOLATED OC/OC CONVERTER (Optional) A . +12VO C [WETTING] CURRENT SUPPLY -:!:- CHANNELS 0 . 7 -12 VDC +12 VDC CHANNELS B . 15 -12 VOC +12 VOC CHANNELS 16·23 -12 VDC FEATURES • ISOLATED FROM COMPUTER BUS AND CHANNEL TO CHANNEL • CONTACT CLOSURE OR VOLTAGE INPUTS • REDUCES SYSTEM DEVELOPMENT TIME System engineered and specified Plug compatible Easy to program Operates from computer power supply • 70°C burn-in International Airport Induatrial Park· P.O. Box 11400· Tucson. Arizona 85734· Tel. \6021 746·1111 . Twx: 910-952·1111 • Cable: BBRCORP· Telex: 66·6491 PDS-391 10-8 DESCRIPTION The MP810 and MP810-NS are 24 channel, optically isolated, digital input microperipheral boards that are electrically and mechanically compatible with Intel SBC80, National BLC80 and Intellec MDS microcomputer systems. Each printed circuit board operates from the computer's power supplies. Digital inputs enter through card edge connectors located opposite the bus connector. The M P81 0 operates with dry relay contacts. The MP81O-NS operates With voltage inputs (wet relay contacts). The MP810 may be modified by jumper selection to operate with voltage or contact closure inputs, or a mixture of both. Inputs are arranged in groups of eight. Each group is isolated from other groups and from the computer bus up to 600VDC. Isolation between inputs is 3()()VDC (MP81O-NS). Isolation protects the computer from voltage transients and malfunctions. In addition, since each input is isolated, the voltage switched by each line is not critical and ground loops are avoided. MP81O's are programmed as memory locations. Each input is one memory bit, therefore any memory read instruction may be executed. When the board is read, logic 0 represents an open contact (low voltage); logic I, a closed contact (high voltage). Each read command inputs the status of eight channels. Address bits ADRO and ADRI select that set of inputs to be read. The remainder of the address lines are used to select the board itself. The address block occupied by each board is selectable and can be located anywhere in memory. SPECIFICATIONS Typical at +2S"C and fated supplies unless otherwise noted. ELECTRICAL INPUT CHARACTERISTICS 24 15kll Number of Channels Input Impedance Input Delay Times Open to closed Closed to open 25Jls. max IOOJ.ls. max: VOLTAGE SENSE MP81O-NS Minimum voltage to detect a logic I Maximum voltage to detect a logic 0 17V 4V CONTACT CLOSURE SENSE Rd"...d MPHIO (on board ±12V supply) 6kU. max MP810-NS at 24V acros, specification is the maximum impedance allowed to reliably detect a closure See Figure I. The impedance of an input contact closure when open. RupF./Io specification is the lowest impedance allowed to reliably detect an open contact. ROPEN - 10-9 MP1104 BURR~BROWN® I~~I MICROCOMPUTER ANALOG· OUTPUT SYSTEM A 4-CHANNEL ANALOG OUTPUT SYSTEM C()MPATIBLE WITH DIGITAL EQUIPMENT CORP. LSI-11, LSI-11/2, LSI-11/23, PDP-11/03, AND PDP-11/23 MICROCOMPUTERS DESCRIPTION The MPII04 analog output peripheral is electrically and mechanically compatible with and interfaces directly to DEC's Q bus. The MPl104 consists offour 12-bit 0/ A converters with address decoding and control logic. It also includes a DC! DC converter for operation from the computer's 5VDC supply. The MPl104 is burned-in before shipment. ADDRESS SELECT AND CONTROL LOGIC DATA BUS _J------- :'SVDC ........ DC/DC CONVERTER D/A CONVERTER DAC3 GND MP1104 BLOCK DIAGRAM Inmrnatlon.1 Alrporllndustrlal Park· P.O. Box 114110· Tucson. Arizona 85734· Tel. (602) 74ti·111I . Twx: 911l-852-l111 • Cable: B.BRCORp· Telex: 66-54\11 PDS-417 10-10 SPECIFICATIONS PROGRAMMING The MPlI04 is programmed as memory locations and any memory write instruction can be used. The 0/ A converter input occupies the 12 least significant bits of a word. The address block occupied by the M P 1104 is userselectable and can be placed anywhere in the upper 4k of memory. MPl104's arejumpered atthefactorywitha base address of 170440 (channel 0). Channel one is at location 170442, channel two is at location 170444, and channel three is at location 170446 (see Table I). ELECTRICAL Typical at 25°C and rated power supplies ·unless otherwise noted ANALOG OUTPUT OUTPUT CHARACTERISTICS Number of Channels Output Voltage Ranges (Jumper Selectable 111) Output Impedance Short Circuit Protection mANSFER CHARACTERISTICS Resolution Output Settling Time, max(2) I MP1104 4 ±10V, 0 to 10V, ±SV, 0 to SV, ±2.SV at SmA 0.010 Yes 12 bits 10,usec ±30ppm of FSR/oC POWER REQUIREMENTS MPll04 +SV ±S% at 1.2SA ENVIRONMENTAL Operating Temperature Relative Humidity TABLE I. 0/ A Converter Data Assignments. WRITE DATA ACCURACY Output Accuracy. max(3) Temperature Coefficient of Accuracy Drift(5) ±0.02S% FSR(41 DIS DI4 DI3 DI2 DII DIO D9 D8 D7 D6 DS D4 D3 D2 DI X X X X BII BIO B9 B8 B7 B6 BS B4 B3 B2 BI DO BO MEMORY MAP OOC to +70°C Channel 0 Base Address Channel I Base Address +2 Channel 2 Channel 3 Base Add ress +4 Base Add r.ess +6 ADDRESS MODIFICATION 95% of noncondensing The base address of a board can be set to any 4-word boundry by properly jumpering (with push-on sockets) its address selector. The base address set 'at the factory is 170440. To change the sense of a bit simply.remove the present jumper and insert the jumper for that bit (see Tables II and III). NOTES: 1. Factory set for ±10V range. 2. Settling to ±0.01% of FSR for a full scale change. 3. Includes linearity. errors with gain and offset errors adjusted to zero. 4. FSR means Full Scale Range. 5. Includes o~fset drift, gain drift and linearity drift. TABLE II. Base Address Jumpers. ADDRESS l.lNES AI2 All MECHANICAL FACTORY SET VALUE JUMPER MATRIX LAYOUT 0 I 12 II 10 FACTORY SET VALUES 0 I 12 II 10 AIO A9 .Compatible with DEC LSI-II, LSI-II/2, LSI-II/23, PDP-I 1/03, and PDP-II/23 card spacing. Minimum card spacing: 12.7mm (0.5"). Analog Output Connector: one 20-pin PC edge connector on top edge of board. Analog Output Mating Connector: AS A7 o AS Mating connector available from Burr-Brown: 2220MC (Viking #3VH 10/ IJN5, solder tab) A flat cable connector is available from Berg: 65764-001 OPERATING INSTRUCTIONS INSTALLATION MPII04 is shipped from the factory calibrated and ready to use. Installation consists of plugging the card into any empty slot in the computer and wiring the analog connector. 10-11 I o;:p~' ADDRj / 0 ~ I .:1.1 ADDR A4 Jumper inserted Jumper inserted A.1 between these two between these two pins for logic O. pins for logic 1. ANALOG OUTPUT RANGE SELECTION Each 0/ A converter is wire wrap j umpered at the factory for ±IOV operation with two's complement coding. It is possible, however, to alter jumpers on the board for other output voltages and coding. When making a change, just remove those jumpers indicated for the present range and replace them with the jumpers required for the desired range. MP1216 MP1216-PGA BURR-BROWN® IEElElI MICROCOMPUTER ANALOG INPUT SYSTEMS A 32-CHANNEL ANALOG INPUT SYSTEM COMPATIBLE WITH DIGITAL EQUIPMENT CORPORATION LSI-11, LSI-11/2, LSI-11/23, PDP-11/03 AND PDP-11/23 MICROCOMPUTERS FEATURES: DATA Ac.aUISITION MODULE • HIGH AND LOW LEVEL INPUTS • SOFTWARE PROGRAMMABLE GAIN 11 to 1024) AMPLIFIER OPTION - EASILY PROGRAMMED -BURN-IN DESCRIPTION The MP 1216 analog input peripherals are electrically and mechanically compatible with and interface directly to DEC's LSI-ll 12 family. The boards use one dual-wide card slot. These units are 16-channel differential (user strapable as 32-channel single-ended) analog input systems. The MPI216 includes: over-voltage protection to 26VDC; an analog multiplexer; resistor programmed instrumentation amplifier (MP!'216), or a software programmable amplifier with gains of I to 1024 (M P 1216-PGA); samplel hold amplifier and; a 12-bit AI D converter. Gains of I to 1024 are software selectable for the programmable amplifier version (MPI216-PGA), and the gain for each channel is stored in an on-board RAM. The proper gain for each channel is then selected automatically by the MPI216-PGA. The MPI216-PGA is particularly recommended for low-level inputs. International Airport Industrial Park· P.O. Box 11400 - Tucson. Arlzonl85734 - Tal. 1602) 746-11It - Twx: 910-952-1111 - Cable: BBRCORP - Talax: 66-649t POS-416 10-12 SPECIFICATIONS MECHANICAL ELECTRICAL Compatible with LSI-II, LSI-II/2, LSI-II/23, PDP-I 1/03 and POP-II/23 card spacing. Typical at 25°C and rated power supplies unless otherwise noted ANALOG INPUT SECTION INPUT CHARACTERISTICS Number of Channels MP1218/MP1218-PGA ADC Gain Ranges (jumper selectable)11) Amplifier Gain Ranges Resistor Programmable( 2) IMP1216) Software Programmable (MPI216-PGA) Maximum Input Voltage without Damage(3) Input Impedance l00MO, l00MO. Bias Current Resistor Programmable Software Programmable Amplifier Input Ollset Voltage Resistor Programmable Software Progremmable Amplifier Input Ollset Voltage Drift Resistor Programmable Software Programmable TRANSFER CHARACTERISTICS Resolution Conversion Time, max G = 1 Resistor Programmable(4) Software Programmable Conversion Time, max G = 1024 Resistor Programl11llble Software Programmable ACCURACY ::;ystem Accuracy at +25°C, max(5) G 1 System Accuracy at +25°C, max G = 1024 Resistor Programmable Software Programmable System Output Noise G =1, rms Resistor Programmable Software Programmable System Output Noise G =1024, rms Resistor Programmable Software Programmable Linearity Differential Linearity Quantizing Error Gain Error Offset Error Monotonicity(8) 1 to 1000 1 to 1024 ±26V • 10pF OFF Channel l00pF ON Channel ±20nA ±15nA OPERATING INSTRUCTIONS ±400pV ±40pV INSTALLATION MPI216 is shipped from the factory calibrated and ready to use. Installation consists of plugging the card into any empty slot in the computer and wiring the analog connector. See Figure I for the block diagram. ±2pVloC ±O.5pVloC 12 Bits 40psec 375psec l00paec 375psec ;tU.U~'''' ":IRIS) ±O.I'11o FSR ±O.05'11o FSR lmV lmV ISmV 2mV ±1I2LSB ±1I2LSB ±1/2LSB Adjustable to zero(7} Adjustable to zero Guaranteed OOC to +700C STABILITY OVER TEMPERATURE BiDolar 19) System Accuracy Drift, max G 1 ±45ppm of FSRfOC System Accuracy Drift, max G = 1024 Resistor Programmable ±200ppm of FSRloC Software Programmable ±100ppm of FSRloC DYNAMIC ACCURACY Sample/Hold Aperture Time 125nsec Aperture Time Uncertainty ±5nsec Dillerential Amplifier CMRR G = 1 74dB (OCto lkHzl Channel Crosstalk 60dB down at 1 kHz, lor O~'"c~!~n~~, POWER REOUIREMENTS MPI2161MPI216-PGA ENVIRONMENTAL Operating Temperature Relative Humidity Minimum card spacing: 12,7mm (0.5"). Analog Input Connector: One 40-pin analog edge connector on board for analog inputs. Analog Input Mating Connector: Mating connector available from Burr-Brown: 2240MC (Viking #3VH20/ IJN5 solder tab); a flat cable connector is available from Berg: 65764-007. 32 slngle-ended or 16 differential ±10V,0-10V +5V ±5'11o at 1.0A PROGRAMMING This peripheral is programmed as memory locations; any memory reference instruction can be used. Two 16-bit memory locations are used. One for the Read/ Write data register; the other for the Control Status register (see Figure 2). The addresses occupied by each MPI216 are user selectable and can be placed anywhere in the upper 4K of memory. On MPI216-PGA's (with software programmable gain amplifiers) an on-board random access memory (RAM) is used to store the gain for each channel. When the Gain Control bit (08) of the Write Data Register is a logic I, the data contained in bits 09-012 of the same register are written to the on-board RA M to control the gain for the channel also written in the same word (bits 00-04). On subsequent operations if the Gain Control bit is a logic 0, the programmable gain amplifier will use the gain already stored in on-board RAM for that channel. These boards are factory set with Data Register at location 170402 and the Status/ Control Register at location 170400. O°C to +70oC 95'110 noncondensing N.OTES: 1. Factory set for ±10V range. 2. Factory set for Gain = 1. 3. With power off (±36 volts with power on). 4. With delay inhibiied. 22psec. 5. Includes linearity errors with gain and offset errors adjusted to zero. 6. FSR means Full Scale Range. 7. When anyone gain range is adjusted to zero gain error, the gain error for any other range is less than ±O.O2% wnen using the software programmable amplifier. 8. No missing codes guaranteed. 9. Includes offset drift, gain drift, and· linearity drift. A conversion is started by writing the channel number to bits 00-04 of the data register. This write operation selects the proper analog multiplexer channel and starts a delay one-shot which allows time for the multiplexer, instrument amplifier and sample/hold amplifier to settle to the new channel's value. At the end of the delay time, the sample/hold amplifier is switched to the hold mode and the A/ 0 converter starts its conversion. When the conversion is. complete, the board can be operated in one of tWI> modes: 10-13 PROGRAMMED AMPLIFIER CHO _________ ~~~':.~~?~1~1~1?~~~??~~~!~_~! ___ _ . +5VDC DCIDC CDNVERTER GND ·ISVDC 'FIGURE I. Block Diagram. InterruI't Mode Polling Mode In the Interrupt Mode, when the conversion is complete, the MPI216 asserts the bus interrupt request line (BIRO). When the LSI-II responds with a bus interrupt acknowledgement (BIAKI), the MPI216 asserts the bus reply line (BRPY) and gates an interrupt "vector" onto the bus. The vector address is selected by jumpers on the board. The Interrupt Mode is enabled by writing a logic I to bit D6 of the Control Register. In the Polling Mode, the CPU must periodically scan bit D70f the STATUS Register to determine if the conversion is complete. A logic I indicates that conversion is complete. A read of the Data Register will then produce the data word. The board is in the Polling Mode if the Interrupt Mode is disabled by writing a logic o to bit D6 of the Control Register. 10-14 MP2216 BURR - BROWN@ IElElI MICROPERIPHERAL ANALOGINPUT/OUTPUTSYSTEM A 12-BIT 32 CHANNEL ANALOG INPUT /:2 CHANNEL ANALOG OUTPUT SYSTEM COMPATIBLE WITH ZILOG MICROCOMPUTERS FEATURES • ANALOG I/O ON THE SAME BOARO • OPERATES FROM COMPUTER POWER SUPPLY • HIGH LEVEL OR LOW LEVEL INPUTS • BURNED-IN DESCRIPTION Completely compatible with Zilog's Z-80 MCB(~ and ZollO MCS series of microcomputers. MP2216 provides a single board 12-bit resolution analog input; output system. The input section accepts 16 differential or 32 single-ended channels. Inputs ranging from millivolts to volts can be digitized because of MP2216's variable gain instrumentation amplifier. Two optional channels of analog voltage are provided in the output section of the MP2216. The input data for each digital-to-analog converter is double buffered to minimize output glitcbes duringa data update. Several output ranges and bipolar or unipolar operation are selected by on-board programming. Data Bus 'W{;~ I ----r:::l---o+ Power SUpply -.--~_ The MP2216 is mechanically, electrically and logically compatible with the Zilog systems. Power is derived from the +5V logic supply. Logic levels and drive capacity are matched to the system bus. Interfacing is accomplished primarily through a Z-80 PIO contained within the system. Inlarnllionll Airport Industrill Plrk· P.O. Box 11400· Tucson. Arizona 85734· Tel. 1602) 146·1111 . Twx: 910·952·1111 . Clble: BBRCORp· Telex: 66·6491 PDS-392 10-15 ELECTRICAL SPECIFICATIONS THEORY OF OPERATION The MP2216 interfaces with theZ-80 I/O bus occupying 10 locations for the complete input/output system. The first four locations are required for the PIO. The next twb locations transfer input channel address and boa'rd status. The remaining locations are used to pass datiUo the two digital-to-analog converters. Data can be acquired from the analog inputs in either the POLLING or INTERRUPT mode: POLLING MODE - A conversion is initiated by writing the analog channel address to the address register. The prugram must then periodically test the conversion bit in the status register to determine when the conversion is completed. During initialization of the MP2216's PIO. the interrupt enable must be reset (both ports) to prevent generation of interrupts. The following program may be used to input a channel of data to the BC register pair: LDA.XX Load accumulator with channel address(XX) of data to be converted. our (YY). A Outputs channel address to MP2216's address register (location YY), This starts conversion. 1 0,., ~ ••,," ~~ ,- ro_~ , _. Typical at 2S0C and rated power supplies unless otherwise noted ANALOG INPUT SECTION INPUT CHARACTERISTICS Bias Current Differential Bias Current TRANSFER CHARACTERISTICS ACCURACY System Accuracy G = I (maxt ll System Accuracy (I =- 1000 linearity Differential Linearity Quantizing Error MonotonicitylJl OUTPUT CHARAC;:TERISTICS Number of Channels Output Voltage Range (strap selectable) Output Impedance IN A.(WW + I) LD B. A INTERRUPT MODE - After setting the board's PIO interrupt enable and vector address. conversion is initiated by writing to the address register. Program execution may then continue until the conversion is complete. At that point the system PIO generates an interrupt vector causing the CPU to begin execution of the M P2216's interrupt service routine. Software for this mode is the same as that of the polling mode. but without the status loop. Outputting of data from the MP2216's two digital-toanalog converters is straightforward. Each converter occupies two addresses on the I/O bus. The least significant 8 bits of the 12-bit data word are written to the first of these data words while the four most signficant bits are written to the second data word. 30.. J ±Sns 74d8 (DC 10 I kHz) SOd8 down at J kHz. for OFF channel to ON chann ANALOG OUTPUT SECTION Test status bit. Jump to STATUS until conversion is complete. Transfers the least significant byte 10 the accumulator. WW is PIO port A DATA register. Transfers the most significant byte to the accumulator. WW + I is PIO port 8 DATA register. ±30 ppm of FSR,"C ±80 ppm of FSRj"C DYNAMIC ACCURACY Sample and Hold Aperture Time Aperture Time Uncertainty Differential Amplifaer CMR Channel Crosstalk BIT O. A LD C". A :to.02S% FSR'" :to. 1% FSR ±1:2 LS8 ±I,2 LSB ±I,2 LS8 Guaranteed O"C to +70"C STABILITY OVER TEMPERATURE''' System Accuracy Drift (max) G I Syslem Accuracy Drift (max) G = 1000 Input status bit from location ZZ. IN A. (WW) 12 Bits 45",sec. channel IOO",sec.' channel Resolution Throulhpul Time (max) G = I Throulhpul lime (max) G = 1000 STATUS IN A. (ZZ) JP Z. STATUS 32 sin~ended/16 differential O· SV. 0 - 10V. ±2.SV. ±SV. ±IOV I 10 1000 :!:26 volts 100MO. lOpe OFF Channel 100MO. 1000F ON Channel ZOnA 10nA Number of Channels ADC G.in R..... (Jumper Selec:t.blt) Amplifier Gain Ranges (resistor programmable) Maximu~ Input Volt•• Without Damage Inpuc Impedance I I 2 ±IOV. 0 to IOV. ±5V. 0 to SV. ±2.SV al SmA 10 TRANSFER CHARACTERISTICS Resolution Seulin. Time (max) 12 Bits lO~sec O~tput ACCURACY OUI put Accuracy TemperalUre Coefficient of Accuracy :to.012S% FSR ppm of FSR "c ±~,O POWER REQUIREMENTS MP2216. MP2211>-AO +SV ±5% al 1.6 amp ENVIRONMENTAL Operating Temperature Relative Humidity O"'C 10 TABLE I. Electrical Specifications !'OOTES: I. Indudes offset crror~. gain crror~. Imearit,,· errors. '} FS R meam Full Scale Range.' . J. So mi~sjng c()de~ guarantce-d. 4. Indudc~ oH:-.ct dnft, gam drift dnd lmcamy drift. SYSTEM CONFIGURATIONS The MP2216 microperipherai board IS available in two versll>ns. MP2216-AO: All features of the MP2216 system are included in this configuration. MP2216: Provides all features except the two digital·lo·analog converters. MP8004: 10-16 Cable assembly. two required. +70"C 9S% noncondensing MP7104 MP7208 MP7216 BURR - BROWN ® IElElI MICROCOMPUTER ANALOG 1/0 SYSTEMS MP7104 - Analog Output System MP720B - Oata Acquisition System MP7216 - Oata Acquisition System FEATURES • COMPATIBLE WITH MOTOROLA MICROMOOULE ANO EXORciser® • REDUCES SYSTEM DEVELOPMENT TIME System engineered and specified Plug compatible. Operates from +5VOC power supply • EASY TO USE All cabling and connectors are included M I C SOMB~3 R o C o OATA ACQUISITION MOOULE IiI!!iD A1·A4 ~Vl ) M P U T E R ~ A5·A15 ~ .1 B VMARIW ~ U ·82 S 1 CONTROL AND TIMING LOGIC GtH AD .. A A -IVDe " { QD:oli GRD ~ ADDRESS DECODER .... oelDe CONVERTER MOOEL-t4I 11 1 1SELECTION ENABLE z INPUT MUX 3-STATE OUT I ~ f l ··---.·· ~-~~ I -> =If; ="g TATION AMPLIFIER SAMPLEI HOLD I 1 A ~ ANALOG MULTIPLEXER AD= D • LSI'S AD-1 4 MIl'S IZ liT AID CONVERTER ~ -Ilvoe -::'+l5voe International Airport Indusilial Park - P.O. Box 11400 - Tucson. Arizona 85734· Tel. (602/746-1111 - Twx: 910-952-1111 • Cable:.BBRCORP - Telex: 66-6491 PDS-3S2B 10-17 contains the 546 DC/DC converter to assure operation on +5VDC power. The inp.!IJ of the D/A,cqnverters are double buffered so that a ·complete 12 bit ·word can be strobed into a 0/ A convert.er's input register to minimize output glitches. . DESCRIPTIQN, These microcomputer peripherals provide. two much needed functions that interface directly· to Motorola's Micromodule and EXORciser microcomputers. The functions are: I) AriaJog Data Acquisition and 2) Analog Output. The devices are electrically. and mechanically compatible with Motorola microcomputers. Each· analog system is contained on a single printed circuit board that is treated as memory input and output by the CPU. The cards will mate to any memory or 1;'0 slot. The analog interface for each system is at a flat cable connector at the opposite edge of the board from the bus connector. THEORY OF OPERATION When programming with these peripherals, they are treated as memory locations. Both the A/D converter output and the D/A COllverter input are 12 bit words so two 8 bit memory locations are needed for each channel. But, because the address block occupied by each peripheral is switch selectable, it can be placed anywhere in memory. Since these units ate treated as memory,a single instruction is all that's needed to set the input of a 0/ A converter. For instance, the STX (write) instructi.on followed by the proper address is used to write data from the index register to the MP7104. The four most significant bits are written first followed by the eight least significant bits. Through double buffering in the M P71 04 only one 12 bit data transfer is made to the DAC to minimize glitching. All of these systems are jumpered at the factory with the first channel at address EFOO'6 (that's litO IIII 0000 0000 in binary). Each subsequent channel is two memory locations past the start of the last channel so that the second channel is at location EF02'6 (lItO IIII 0000 The Data Acquisition Systems consist of the MP7208, an 8 channel differential input system; and the MP7216, a 16 channel single-ended input system. Burr-Brown's SDM853 modular data acquisition system is used to implement these systems. The data acquisition systems include an input multiplexer, high gain instrumentation amplifier, sample/hold and 12 bit A/D converter along with all the necessary timing, decoding and control logic. The model 546 DC; DC converter (+5V to ±15V) is also used so that only the microcomputer's +5VDC power supply is required. The MP7104, an analog output system, provides four analog output channels (using four of Burr-Brown's hybrid 12 bit DAC80 0/ A converters). This board also 0010)~ ALL SYSTEMS ARE ELECTRICALLY AND MECHANICALL Y COMPATIBLE WITH MICROMOOULE AND EXORCISER MICROCOMPUTERS. 10-18 ANALOG INPUT SYSTEM - MP720S/7216 M I C R o C o SOMa53 DATA ACQUISITION MODULE U,:IE,n -\ 11 L A1·A4 M P ANALOG MULTIPLEXER E R A5·A15 B U S VMA RIW ·112 " y " ~ ~ ADDRESS DECODER CONTROL AND TIMING LOGIC GtH AD A TSElECTION )I ,. ENABLE ( oo.oil '4 Z INPUT MUX 'ElEI' +5VDC DC/DC CONVERTER MOOEL·54I GRD 3-STATE OUT J--1 J f ) \r I • ~,. Y'STRU.". - I • -,. ----Zz I U T •• •• .... ..",0 '" TATION AMPLIFIER SAMPLEI HOLD I I f AD = 0 • LSB'S AD = 1 4MSB'S 1Z BIT AID CONVERTER -15VOC - +15VOC ANALOG OUTPUT SYSTEM·- MP7104 +5VDC ... IElElI DC - DC GRD VMA RIW n H M vi A2 I C A1 R o o AO C ... 112 M P T E ~O R t----' t\. B [ U ~. S I 7 V r- ~H ~l ADDRESS DECODER "- + - OAC 1 STROBE 1 OF 4 DECODER AND WRITE CONTROL lOGIC OAC 3 STROBE OAC 4 STROBE STROBE J.."/ [ t ... a 81T LATCH a LSB'S I ~ 4 MSB'S 10-19 q r-v A T C H ~~ j DAC 2 STROBE I U ~q~ n- CONVERTER MODel 546 -\ ~L ~+15VOC f---+ -15VDC - - ~~ r--v H ~~A - ~ r---v T C H IElElI D/A CONVERTER DAC80 -+ 1 IElE31 D/A CONVERTER OAcao 2 -+ A N A l o G o IElElI O/A CONVERTER OAcao 3 U -+ U T S IElElI D/A CONVERTER DAcao 4 T P f+ OPERATING INSTRUCTIONS SPECIFICATIONS 2S"C All s~cifications typical at unless otherwise noted ANALOG INPUT Number of analog inputs 8 channel differential 16 channel single-ended Input voltage range!1I Input current loop ranges (resistor programmable) ADC gain ranges (strap selectable) ±S. ±2.SV Amplifier gain' range IlolOOOVjV MP7208 MP7216 ±lOmV to ±IOV 4-20mA. lo-50mA ±IOV.Olo IOV. 0 to (resistor programmable) Amplifier gain equation (resistor programmable) Input overvoltage protection Inpul impedance Bias current 25"C 01070"C Amplifier output noise (Gain 100 R, 5000) Amplifier input offset voltage (max)I.] 400~V Amplifier input offset voltage drift (max) 2 = = G INSTALLATION The MP7104, MP720S and the MP7216 are shipped from the factory calibrated and ready for immediate use. Installation requires only plugging the card into any empty slot in the EXORciser or with a Micromodule and routing the board's mating I/O cable to the back panel. The cable supplied witn each board is shielded and, in the case of the MP7104, provided with the proper terminations. ~V = I + 20k!}, RD.. ±15V 100 megohms 20nA 50nA 1.2mV. rms; 7mV. p-p PROGRAMMING -+~ ~Vj"C G TRANSFER CHARACTERISTICS Resolution Throughput accuracy. ±IOV range (max) ±lOmV range Temperature coefficient of accuracy ±IOV range (max) ±JOmV range Conversion lime ±IOV range ±JOmV range" CMRR (for differential inputs) Sample hold aperture time 12 bits binary ±O.025% FSR(~J ±O.I~i- FSR ±0.003~'i FSR "C ±o.Olei;' FSR "c -33 microseconds 100 microseconds 74 dB iI)(' to 2000 H1I 30ns DIGITAL INPUT/OUTPUT All signals are compatible with Micro-computer buli Output coding A n analog input channel is selected by: The output data bils are read into:L'I POWER REQUIREMENTS MP7208. MP7216 MP7217-NS. MP7209-NS Bipolar. Two's Complement; unipolar. straight binary lll'hrough ~ DO Ihrough D7 +SVDC ±S% at I amp. 2SmV ripple { +5VDC ±5% al +500mA. 25mV ripple +ISVDC±3% at +SOmA. SmV ripple -ISVDC ±3% at -7SmA. SmV ripple TEMPERATURE RANGE Temperature 01070"C ANALOG OUTPUT Number of analog outputs: 4 Output voltage range!U Output impedance Output settling time MP7104 ±IOV. 0 10 IOV. ±5V. 0 to 5V. ±2,5V at SmA (strap selectable) III < 10 microseconds TRANSFER CHARACTERISTICS Resolution Throughput accuracy (max) Temperature coefficient of,accuracy Unipolar Bipolar 12 bits binary ±O.O I 259, FS R ±0.003% FS R j"C ±O.0045% FSRf"C Programming of these analog I/O boards is easily accomplished since all are treated as memory locations. The M P7104 uses any memory reference instruction that can write data from the index and stack point registers or the accumulators. In a similar manner a channel in the MP7208 or MP7216 can be read by any memory reference instruction that can read data into the index and stack pointer registers or the accumulators. The voltage data for these boards is represented by a 12 bit two's complement binary number. Each bit has a value of 4.SSmV, with the polarity of the voltage indicated by the sign of the binary number. Since the index, stack pointer and A and B accumulator pair registers are 16 bits long and the data word is 12 bits, the M P720S and MP7216 set these unused bits to the same value as the most significant bit of the data. This assures the proper representation of the data's sign. Each board is set at the factory for a block of addresses beginning at EFOO. Any analog data channel requires two memory locations since the digital data is 12 bits. The most significant 4 bits of data are always located in an even location while the remaining S bits are located in the next higher location. Thus, the first analog channel is located at EFOO and EFOI while the second analog channel is located at EF02 and EF03. When moving data. all boards require that the most significant bits. (even addresses) be referenced first. In addition. the M P720S and MP7216 systems require the most significant data to be read followed by a NOP instruction for proper starting of the conversion process. This can be illustrated as shown below: DIGITAL INPUT/OUTPUT All signals are compatible with Microcomputer bus An analog output channel is seleCted by: The input data" bits are read by: AI and A2 00 Ihrough i57 POWER REQUIREMENTS MP7104 MP710S-NS +5VDC ±S% al +1 amp. 25mV ripple { +SVDC ±5% al +500 mA ±5mV ripple +ISVDC±3% al +IOOmA. SmV ripple -15VDC ±3% al -IOOmA. SmV ripple TEMPERATURE RANGE Temperature 01070"C 10-20 (I) (2) (3) (4) LDAA NOP EFOO LDX EFOO Starts conversion of CHO Allows processor to halt during conversion Reads data as so~n as conversion is complete Connected at the factory for ±IOV range. FSR is Full Scale Range (i.e .• 20V for ±IOV range. IOV for 0 to +IOV range), The 4 MSB's when conversion is complete. followed by the 8 LSB·s. Adjustable 10 zero. BURR-BROWN@ IElElI MICROCOMPUTER ANALOG INPUT SYSTEM A LOW-COST 12-BIT. 16-CHANNEL ANALOG INPUT SYSTEM COMPATIBLE WITH MOTOROLA MICROMODULE AND EXORciser® MICROCOMPUTERS A1 ADDRESS BUS A4 A5 A15 VMA ,82 ~ LATCH -V ---f\ --v' C 16 CHANNEL ANALOG MULTIPLEXER ANALOG INPUTS CH 15 J ADDRESS BUt ADDRESS DECODER AND CONTROL LOGIC •• • Y·STRUMENTAno. AMPLIFIER STATUS ~ I-CI AD CONTROL LOGIC Rfi[ 0- '-0-" 0- ..6-~ 07 a:z "'<[ >:;; z:;; ...... CICI I I ree 12 BIT AID CONVERTER ""7 TRI-STATE OUTPUT DATA BUS D FEATURES • 70°C BURN-IN • OPERATES FROM COMPUTER'S ±12VDC, +5VDC POWER SUPPLY • ACCEPTS LOW LEVEL INPUTS • EASY TO PROGRAM Internatlllllal Alrporllnduslrlal Park - P.O. Bax 11400 - Tucson. Arizona 85734 - Tel. /602) 746·1111 - Twx: 910-952·1111 - Cable: BBRCORp· Telex: 66·6491 PDS-382A 10-21 DESCRIPTION The MP7218 is an analog input microperipherai board designed to be used with Motorola's Micromodule and EXORciser@microcomputersystems. It is electrically and mechanically compatibJe with these systems. The analog system is contained on a single printed circUit board that is treated as memory by the CPU. The analog interface is at a connector on the opposite edge of the board from the bus connector. This data acquisition system includes 2SV input overvoltage protection, an analog multiplexer, high gain instrumentation amplifier, and 12 bit AID converter along with· all the necessary timing, decoding and control logic. The unit operates from the microcomputer's +SVDC and ±12VDC power supplies. The MP7218 is capable of interfacing ±lOmV to ±5V signal levels. When programming with this peripheral, it is treated as memory. The' AID converter output is a 12 bit word so two 8 bit memory locations are needed for .each channel. Address bits AIS-AS select the board and A4-AI select the analog input channel to be digitized. To start a conversion the board is written to using an ST A or similar instruction. After conversion data remains in the output latches waiting to be read until another conversion is initiated. This unit may be used with or without halting the CPU or in the interrupt mode. SPECIFICATIONS All specifications typical at 2S"C unless "otherwise noted. MP7218 ANALOG INPUT Number of analog inputs Input range 8 ·differental/16 single-ended('! ±lOmV to ±5V(2! . ,ADC gain ranges (strap selectable) Amplifier gain range Factory set gain Amplifier gain equation (resistor' programmable) Input overvoltage protection Input impedance, DC Bias current 25°C o to nrc Amplifier output noise (Gain = 100 R, = 5oon) Amplifier input offset voltage, max Amplifier input offset voltage drift, max o to 5V ±5V. ±2.5V I to 1000 I G = I + 20kn/R", ±25V 100 megohms 20nA 50nA 1.2mV. rms; 7mV. p-p 4OO~V (2 + 20,G)~Vf"C TRANSFER CHARACTERISTICS Resolution Throughput acc,:!raC):. (±5V range, max) ±lOmV range Temperature coefficient of accuracy range, max ±5V ±IOmV range Conversion tiJ:l)e ±SV range ±lOmV range CMRR (for differential inputs) 12 bits binary ±O.025% FSR'" ±O.I% FSR ±o.OO4% FSR!"C ±o.OI% FSR!"C 50 microseconds 100 microseconds 90dB (DC to 60 Hz) DIGITAL INPUT/OUTPUT The MP7218 is jumpered at the factory with the first channel at address 93EO'6, the second at 93E2'6, etc. By changing jumpers, the boards may be placed anywhere in memory. All signals are'compatible with Microcomputer bus Output coding logic loading (all inputs) Data bu~tput drive HALT. IRQ. NMI output drive Bipolar. two's compiementl-'I One LSTTL load 20 TTL loads 10 TTL loads POWER REQUIREMENTS Power supply voltages Range for rated accuracy +5VDC at 100mA. +12VDC at 50mA ·12VDC at 75mA 4.75V to 5.25V and ±IIAV to ±12.6V TEMPERATURE RANGE Temperature O"C to 70"C (I) Connected at the factory as 8 channels differential. (2) Connected at the factory for ±SV range. (3) FSR is Full Scale Range (i.e., IOV for ±5V range, 5V for 0 to +5V range). (4) Straight binary jumper selectable. (W80. W81) MECHANICAL CHARACTERISTICS Compatible with EXORciser and Micromodule card spacing. Minimum card spacing: 12.7mm (0.5'') Microcomputer bus connector required: 86 pin PC edge connector with 0.IS6" contact centers (SAE-43DI 1-2). Analog connector: SO pin PC edge connector with 0.100" contact centers. Burr-Brown part number: 22S0MC (Viking #- 3VH2S1 IJNS - solder tab). Scotchflex cable connector also available from 3M (#- 34IS-0001). 10-22 :MP7408 MP7432 BURR-BROWN® IElElI MICROCOMPUTER ANALOG 1/0 SYSTEM A LOW-COST 54-CHANNEL ANALOG INPUT/2 CHANNEL ANALOG OUTPUT SYSTEM COMPATIBLE WITH MOTOROLA MICROMODULE AND EXORciser® SYSTEMS 8 TO 64 ANALOG INPUTS t-. A15 A2 ]I ASO --.l\ ADDRESS OECODER -V -1\ LATCH .L'ONTROLAN' TIMING LOGIC AS1 VMAIVUA vHALT/IRO v Hz DATA BUS D1 .00 1\ ~ AO A1 RiW II ~ \ -V GRD DATA BUS INTERFACE 1\ 11 OAC 1 STROBE r--r--- OAC 2STROBE +15VDC -15VOC ~ - 1\ V :• V ~ INSTRUMEN- :~:.:'" 8 BIT AlO CONVERTER ~ ~ DC/DC CONVERTER (OPTIONAL) Cl lA- REAOIWRITE CONTROL LOGIC I +5VDC I"A"E ? ANALOG MULTIPLEXER 11' L A T C H O/A CONVERTER (OPTIONAL) 1 L A T C H O/A CONVERTER (OPTIONAL) 2 <.:len .cc. ...= al- zlccg FEATURES • EASY TO PROGRAM Systems are treated as memory • REDUCES SYSTEM DEVELOPMENT TIME • EASY TO USE 8 to 64 input channels on one board Analog input and output on one board High level or low level inputs • 71J<>C BURN-IN International Airport Industrial Park - P.O. Box 11400· Tucson. Arizona 85734· Tel. (602) 746·1111 - Twx: 910-952·1111 • Cable: BBRCORP . Telex: 66-6491 PDS-J7B 10-23 " DESCRIPTION SPECIFICATIONS All specifications typical at 25"C unless otherwise noted. This microcomputer peripheral provides two functions that interface directly to Motorola's Micromodule and EXORciser microcomputers. The .fuilctions'are: (I) Analog Data Acquisition and (2) Analog Output. Both analog input and output systems are contained ()n a single printed circuit board that is treated as memory input or output by the CPU. The analog interface is at connectors on the opposite edge of the board from the bus cOilnector. ANALOG INPUT/OUTPUT SYSTEM ANALOG INPUT N umber of analog inputs The Data Acquisition System is available with up to 32 channels differential (64 channels single-ended) on one board. It includes an input multiplexer, high gain instrumentation amplifier, 8-bit AID converter along with all the necessary timing, decoding and control logic. This system can digitize low level or high level analog signals. The gain of the internal instrumentation amplifier can be programmed with a single external resistor to allow input signal ranges as low as ±2.5mV. This means that the MP7400 can be connected to low level sensors such as thermocouples and strain gauges without external signal amplification. A DC/DC converter (+SV to ± ISV) is also available so that only the computer's power supply is required. The Data Acquisition System is available with two optional 8-bit D / A converters to provide analog output in addition to input on the same board. Input o~ervoltage protection Input impedance 8 differential (16 signai-ended)\5 1 32 differential (64 singie-ended)16) MP7408 MP7432 Input voltage raogeH) ADC gain ranges tl ) (strap. selectable) Amplifier gain rangelU (resistor programmable) Amplifier gain equation ±5mV to ±5V ±IOV.Olo IOV 0 10 5V ±5V. ±2.5V I 10 1000 G ±15V 100 megohms Bias current 25'"C(max) O"C 10 70"C +3OOnA -2nA."C ±(5 + A.mplifier input offset voltage drift When programming these peripherals, they are treated as memory locations. Any memory reference instruction can be used. Two memory locations are used by the analog input system. One location is used to select the channel and start conversion. The same location provides status information when read. The other location contains the converted data. The analog output system also uses two memory locations, one for each channel. Because these units are treated as memory, a minimum of instructions are needed to read an input channel or to set the output of a D/ A converter. The MP7400's versatile memory mapped operation allows it to be used with or without halting the CPU or in the interrupt mode. All of these units are jumpered at the factory for address 9SFO through 9SF3. I~) ~V/"C ANALOG INPUT TRANSFER CHARACTERISTICS 8 bit binary ±O.4% FSR'" ±O.5% FSR Resolution Throughput accuracy ±5V range (max) Throughput accuracy ±lOmV range Temperature coefficient of accuracy ±SV range (max) ±IOmV range Conversion time ±SV range (max) Conversion time ±lOmV range (max) CM RR (for differential inputs)PI ±O.02% FSR/"C ±O.07% FSR/"C 44 microseconds 84 microseocnds 66 dB (Gain ~ 2) 86 dB (Gain ~ 100) ANALOG OUTPUT Number of analog outputs Output voltage range l4 ! THEORY OF OPERATION lookll/ R •. x, ~ 2 ±IOV.Olo IOV. ±5V. 0 10 5V, ±2.5V at SmA (strap selectable) III < 5 microseconds Output impedance Output settling time (max.) ANALOG OUTPUT TRANSFER CHARACTERISTICS Resolution Throughput accuracy (max) Temperatur~ coefficient of accuracy Unipolar Bipolar 8 bit binary ±O.4% FSR ±O.005'1c FSR/"C ±O.Ollfi, FSR!"C DIGITAL INPUT/OUTPUT All signals are compatible with Motorola Microcomputer Bus Output coding An analog input channel is selected by: An analog output channel is selected by: The input; output data bits are read through: Bipolar. two's complement; Unipolar. straight binary 00 through OS AO Do Ihrough m POWER REQUIREMENTS M P74Ol1. M P7432 +SVDC +5% at I amp MP74Ol1-NS. MP7432-NS { +5VDC ±5% at 500mA +ISVDC ±S% at 40mA -15VDC ±5% al 40mA { +5V DC ±S% at SOOmA +15VDC ±5% at IOOmA ·l5V[)C ±5(:i' at 100mA With analog output MP7408-AO. MP7432-AO MP74Ol1-NS-AO. MP7432-NS-AO TEMPERATURE RANGE 10-24 +5VDC ±5% at 2 amp O"C 10 70"C MP7504 BURR-BROWN® 113131 MICROCOMPUTER ANALOG OUTPUT SYSTEM A 4-CHANNEL. 8-BIT ISOLATED ANALOG OUTPUT SYSTEM COMPATIBLE WITH MOTOROLA MICROMODULE AND EXORclser® MICROCOMPUTERS VOLTAGE OUT VUA VMA R/WO-~-"""'--I JlJ.O-I----t G/H CHANNEL {AI SELECT AOo-t----t_....-..J--t._ _--' ii7 --+-----'\1 OPTICAL ISOLATORS iiiI--+-==~1 +5VDCo-l------/ GROUND 0-1----- DCIDC CONVERTER FEATURES .OUTPUT ISOLATION/OUTPUT PROTECTION • MOTOROLA MICROMODUlE AND EXORciser " COMPATIBLE • REDUCES SYSTEM DEVElOPMENT TIME System engineered and specified • 4·CHANNEl ANALOG OUTPUT SYSTEM Plug compatible .4mA TO 20mA OUTPUT Operates from computer power supply Easy to program .70D C BURN·IN -COMPATIBLE WITH ROCKWEll SYSTEM 65 Intemilional Airport Induslrlal Parle" P.O. BDl' 11400 - Tucson. Arizona 85734 "Tel. (602) 746-1111 - TWI,910-952-1I11 - Cable: BBRCORP" Telel: 66-6491 PDS-38SA 10-25 DESCRIPTION MECHANICAL This microcomputer peripheral, burned in at 70°C to inqease reliability and reduce aging shift, provides four optically-isolated 8-bit fused analog outputs that interlace directly with Motorola's Micromodule and EXORciser microcomputers. The MP7504, electrically and" mechanically compatible with these MPU's, is contained on a single printed circuit board that operates from the computer's +5 VDC power supply. Analog interface is through a card edge (direct) connector located on the opposite edge of the board from the bus connector. The MP7504 which outputs 4mA to 20mA and Q- IOV on .each channel is programmed as memory locations. The address block used by each peripheral is selectable and can be placed anywhere in memory. A single instruction sets the input of a D I A converter. .OPERATING INSTRUCTIONS ELECTRICAL SPECIFICATIONS All spec:ifications typical at 25°C unless otherwise noted. MOOEL MP7S04 ANALOG OUTPUT Number of anal", outputs Output current ranse 4 4mA to2OmA Maximum load Compliance Output settling time Output voltage r a . Output impedance Output settling time 8V SOjISeC ~IOV ,.SmA 10 30jISeC 4000 TRANSFER CHARACTERISTICS Resolution 0 .. LSB (voltage) 0 .. LSB (curmtt) lbrougbput ac:curacy. max Temperature cocfftcienl of accuracy Voltage output Current output 8 bits binary 39.lmV 62S,.A ±O.4%of FSR ±SOppm of fSR/"C ±ISOppm of FSR/"C ISOLATION Isolation voltage between microcomputer bus and outputs 600VDC DIGITAL INPUT/OUTPUT All sipals compatible with microcomputer bus Lope loadi", (all inputs) Analog output channels ..Ioc:ted by: Input data n:ad by: One LSTIL load AO,AI 00-00 POWER REQUIREMENTS Rated voltage RanF for rated accuracy Supply drain at SVDC +SVDC 4.7SVDC to S.2SVDC 1.2A, 'typical; 1.8A max TEMPERATURE RANGE Operating Compatible with Micromodule and EXORciser card spacing. Minimum card spacing: 12,7mm (0.5j. Microcomputer bus connector required: 86 pin PC edge connector with 0.1 56" contact centers (SAE-43D/1-2). Analog Connecto.r: 50-pin output P.C.B. edge connector. A mating connector is available from Burr-Brown: 2250MC (Viking # 3 VH25/IJN5, solder tab) . A Scotchflex connector (3415-000 I) is available from 3M. PROGRAMMING Because this analog output board is treated as memory, programming is simple. The MP7504 uses any memory reference instruction that can write data from the CPU. Each board is factory set for a block of addresses beginning at 94FC. Each analog data channel requires one memory location. When a data word is written to the MP7504 it is stored in an input latch. The optical isolators following the input latch require 15 microseconds to transfer new data to the D / A converter latches. Do not write to the board during this transmission period. To insure proper operation, use one of these modes: I) HALT mode (shipped in this mode): Jumper W33 is installed. The conversion command (write instruction) is followed with a NOP instruction. In this mode, the board halts the processor during data transfer sequences. For example: STAA 94FE Transfers data in accumulator to MP7504 for channel 2. NOP Allows MP7504 to halt processorfor 15 microseconds during transfer of data to channel 2. 2) COUNT DOWN mode Jumper W33 is removed. Software control does not permit the program to write to the board for 15 microseconds. For example: ST AA 94FE Transfers data in accumulator to MP7504 for channel 2. : { System software does not allow another • write to the MP7504 for 15 microseconds. O"C10 70"C CHANNEL FACTORY SET LOCATION 0 I 2 3 94FC 94FIJ 94FE 94FF TABLE I. Analog Output Channel Locations. 10-26 MP7608 MP7608-1 BURR-BROWN® IElElI MICROCOMPUTER ANALOG INPUT SYSTEMS A 12-BIT, 8-CHANNEl "INDUSTRIAL" ANALOG INPUT SYSTEM COMPATIBLE WITH MOTOROLA MICROMODUlE AND EXORciser® MICROCOMPUTERS 10Hz FILTER i{:~ c( CURRENT INPUTS r---------~--~r=-;-~-~-~'+t~~;l~--~~ ~ LATCH I: ~~_+~~~~~~---hrO~ ANALOG MULTIPLEXER I I : :I <= • CI 250>2: CH7 ~ L ____ :.J L ____ ...l L--~~--~r-i=~~1t~==~----ro~ r------------:-::l RTDO I AS ADDRESS A15 OECODER VMA o-I--~ AND CONTROL VUA o-t---i LOGIC .,;.,---() I I I 1 USER . I SUPPLIED : Nv---O RTD7 1 I1 n. OJ--L_---.J -I - 1 AD RAN • 1 1 I o:t6:;===:!~~ll"§§~...:~r~~J-il@~ ~!..E~~N!~ ______ ..J1 RESET IRQ 0 NMI HALT BRIDGE CIRCUITRY (MP7608 Only) ii7 iiii FEATURES • IMMUNE TO NOISE • CURRENT·LOOP INPUTS • HIGH OR LOW LEVEL VOLTAGE INPUTS • INPUTS PROTECTED TO 200VDC Input filter on each channel Differential inputs • BRIDGE INPUTS • CURRENT INPUTS FUSED • 70°C BURN·IN International Airport Industrial Park· P.O. Box 11400 - Tucson. Arizona 85734 - T81.16021746-1111 - Twx: 910-952-1111 - Cable: BBRCORP - T8lex: 66-6491 PDS-380 10-27 DESCRIPTION The MP7608 and MP7608-I are analog input microperipheral boards designed to be used with Motorola's Micromodule and EXORciser microcomputer systems. They are. electrically and mechanically compatible with Motorola microcomputers. Each analog system is contained on a single printed circuit board that is treated as memory by the CPU. The analog interface for each system is at a connector at the opposite edge of the board from the bus connector. These data acquisition systems include 200V input overvoltage protection, an input filter, analog multiplexer, high gain instrumentation amplifier, sample I hold and 12 bit AI D converter along with all the necessary timing, decoding and control logic. They operate from the microcomputer's +5VDC and±12VDC power supplies. The MP7608 is a voltage input system capable of interfacing ±lOmV to ±5V signal levels. Excitation and bridge circuitry is.also included on this board for interface to sensors such as RTD's and strain gages. The MP7608-I is a current input system designed to interface to 4-20mA current loop signals. The MP7608-I also includes input fuses to protect the 2500 precision input current resistors. THEORY OF OPERATION When programming with these peripherals, they are treated as memory locations. The A I D converter output is a 12 bit word so two 8 bit memory locations are needed for each channel. Address bits A15-A5 select the board and A4-A I select the analog input channel to be digitized. To start a conversion the board is written to using an STA or similar instruction. The data remains in the output latches waiting to be read until another conversion is initiated. These peripherals may be used with or without halting the CPU or in the interrupt mode. The MP7608 I MP7608-I are jumpered at the factory with the first channel at address 93EO l 6, the second at 93E2 16, etc. By changing jumpers, the boards may be placed anywhere in memory. SPECIFICATIONS All specifications typical. at 2S"C unless otherwise noted. ELECTRICAL ANALOG INPUT Number of analog inputs Input range ADC gain ranges (strap selectable) Amplifier gain range Factory set gain Amplifier gain equation (resistor programmable) Input overvoltage protection Input filter Input impedance. "DC Bias current 2S"C o to 70"C Amplifier output noise (Gain = 100 R, = SOOn) Amplifier input offset voltage. max Amplifier input offset voltage drift. max MP760B·1 MP760B 8 differential!!) 8 differentiat n 0-20mA(21 ±JOmV to ±5Y()) ±IOV.Olo IOV.OtoSV ±IOV.Oto 10V.OtoSV. ±SV. ±2.5V ±5V. ±2.5V' Ito 500 Ito 500 I (~J I G =I+ ~Okn{R,,·, ±200V One pole RC. 10Hz 250n G = I + 20kn{ R,CK' ±200V One pole RC. 10Hz 100 megohms 20nA 7nA 50nA 1.2mV rms; 7mV p-p O.5mV rms; 3mV p-p 4OO~V 2 + 20{G ~V("C IOnA 200~V 1+ 20{G ~V("C TRANSFER CHARACTERISTICS Resolution Throughput accuracy. ±5V or o-20mA range. max ±lOmV range , Temperature coefficient of accuracy ±5V or o-20mA range. max ±lOmV range . Conversion time'±SV or O-20mA rang ±lOmV range CMRR (for differential inputs) 12 bits binary 12 bits binary ±o.025% FSR'" ±o.I% FSR ±o.025% FSR'" ±o.I% FSR ±o.OO4% FSR("C ±0.01% FSR("C 60 microseconds 125 microseconds 90<18 (DC to 60Hz) ±o.OO4% FSR("C ±o.OI% FSR("C J 75 microseconds 525 microseconds 9Od8 (DC to 60Hz) DIG!TAL INPUT/OUTPUT All signals are compatible with Microcomputer bus Output coding Logic loading (all inputs) ~u~tput drive HALT. IRQ. NM, output drive unipolar. straight binary one LSTIL load 20 TIL loads 10 TIL loads bipolar.l~) two's complement one LSTfL load 20 TTL loads 10 TTL loads POWER REQUIREMENTS Power supply voltages +SVDC at 100mA. +12VDC at SOmA. -12VDC at 7SmA +SVDC at 100mA. +12VDC at SOmA. -12VDC at 7SmA Ran8e for rated accuracy 4.75V to S:25V and ±11.4V to ±12.6V 4.7SV to S.2SV and ±11.4V to ±12.6V o to 70"C o to 70"C TEMPERATURE RANGE Temperature (I) ·(2) (3) (4) (5) (6) May be connected as 16 channels single-ended without input filtering. May be set up to accept voltage signals. Connected at the factory for ±5V range. FSR is Full Scale Range (i.•.• IOV for ±5V range. SV for 0 to +5V range). Gains of 5 and 100 can be attained by adding jumpers.. Unipolar straight binary is jumper selectable (W80. W81). 10-28 MP8304 MP8408 MP8416 BURR-BROWN® IElElI MICROCOMPUTER ANALOG 1/0 SYSTEMS INTEL - SBCBO and Intellec MOS Compatible NATIONAL BLCBO Compatible MP83D4 - Analog Output System MP8408 - Data Acquisition System MP8416 - Data Acquisition System FEATUR'ES • EASY TO PROGRAM Systems are treated as memory • REDUCES SYSTEM DEVELOPMENT TIME System engineered and speci,lied Operates from computer's +5VOC power supply if desired • EASY TO USE All cabling and connectors are Included SDMI53 DATA ACQUISITION MODULE VI ~ ADR3/--..l\ ADR1/-V ~ ADRFI ADR41 MRDCI CONTROL ANa TIMING LOGIC XACKI ADR" ..~ !i" .,. ~ :3 e iii .". "', -:1 DAT7I ~DATA A +5VOC GRO J. ADDRESS DECODER ~ICONVERTER MODEL 546 OC/DC -IJDC~+IJDC TSELECTION ENABLEI 2 INPUT MUX 3-8TATE OUT A I-- .. · · I: ~~.-.- - !~ =: :~~~I~IER SAMPLEI HOLD T I LSI'S I) ANALOG MULTIPLEXER 4 MSI'S I 12 BIT AID CONVERTER I " InlernlllOl1al Alrporllndualrlal Park, P,O, Box 11400· Tucson, Arizona 85734· T81.1602) 746-1111 . Twx: 91(1.952·1111 • Cable: BBRCORP· Telex: 66-6491 PDS-3538 10-29 DESCRIPTION These microcompu~er peripherals provide two much needed functions that interface directly tointe\'s SBC80/10 ,and JntelIet MDS microcomputers. The ' functions are: I) Analog Data Acquisition and 2) Analog Output. The ,devices are electrically and me~h3tiicany compatible with any SBC80/1O and Inteliec MDS. Each analog system is contained on a single pri~ted circui~ , board that is treated as memory input or output by the' CPU. The cards will mate to any memory or I/O slot. They are compatible with the 0.6" spacing of the SBC80/ iO or the 0.75" spacing of the Intellec MDS. The analog interface for each system is at a flat cable connector at the opposite edge of the board from the bus connector. double. buffered so that a complete 12 bit word can be strobed into aD/ A converter's input registerlo minimize output glitches. All ofthe~e systemS are also offered in an OEM version without. the DC; DC converter and cable. THEORY OF OPERATION When programming with these peripherals, they are treated as memory locations. Both the A/D converter outpUt and the D / A converter input are 12 bit words so two 8 bit memory locations are needed for each chan~e1. But because the address block occupied by each peripheral is user selectable, it can be placed anywhere in memory. Existing memory can be overlapped since the peripherals inhibit all other memory that occupies the same memory locations, The Data Acquisition systems consist of the MP8408, an 8 channel differential input system; and the M P8416, a 16' channel' single-ended input system. Burr-Brown's SDM853 modular data acquisition system is used to implement these systems. The data acquisition systems include an input multiplexer, high gain instrumentation amplifier, sample/hold and 12 bit A/D converter along with all the necessary timing, decoding and control logic. The model 546 DC; DC converter (+5V to ± 15V) is also used so that only the computer's +5VDC power supply is required. Because these units are treated as memory. a single instruction is all that's needed to read an input channel or to set the input of a D/ A converter. For instance. the LHLD (load) instruction followed by the proper address is used to read data from the MP8408 or MP8416. It will automaticaUy select the desired channel. initiate conversion and when conversion is complete. transfer the A/D converter output for that channel to the 8080's H and L registers. The eight least significant bits are read first followed by the four most sil!;nificant bits. The MP8304, an analog output system, provides four analog output channels (using four of Burr-Brown's hybrid 12 bit DAC80 D/ A converters). This board also contains the 546 DC/DC converter to assure operation on +5VDC power. The input of the D / A converters are AU of these systems are jumpered at the factory with the first channel at address F720 16 • Each subsequent channel is two memory locations past the start of the last channel so that the second channel is at location F722 16 • EACH SYSTEM IS ELECTRICALL Y AND MECHANICALL Y CDMPATIBLE WITHTHE INTELLEC MDS AND THE SBC 80 10-30 ANALOG INPUT SYSTEM - MP8408/8416 SDMI53 DATA ACQUISITIDN MODULE ~ II> ADR3I ADR1 I -'\ } -V ~ w a:: g ~ MROCI ~ - XACK I ADRd I ~ DAT7/ II> ~ DATil I ~DATAl BUS 'I I ... +5VDC ..,c ..,a:: C EiI&i I DC/DC CONVERTER MDDEL 546 GRD 3·STATE DUT 111 3ii !--- SELECTION ENABLEI l- => :;; CONTRDL AND TIMING LOGIC 2 INPUT MUX Vt •• •• • • 11 ~ ADDRESS DECODER ANALOG MULTIPLEXER -:I> Zz ~;:""u.'.- I --~~ ;;leo '" TATION AMPLIFIER SAMPLE/j HOLD T I I LSB'S ~ 4 MSB'S ~ 12 BIT AID CDNVERTER -15VDC-=+15VDC ANALOG OUTPUT SYSTEM - MP8304 en => II> ~ W en a:: => c II> C a:: :;; ADR21 ADR11 ..,cc ..,a:: --" .... -'" ADR.I MWTC/ ..... ~ XACKI 3ii r---+ +15VDC n- II> ~ CI I DAT41 ~AT31 I( 'I I_ ~ATil I V - p( A T C jYH ~L + - :J( ---v r- DAC 1 STROBE 1 OF 4 DECODER AND WRITE CONTROL LOGIC 1 DAC 2 STROBE DAC 3 STROBE OAC 4 STROBE I STROBE D,AT71 I - ADDRESS DECODER I en => ~L ~ -15VDC -) I( "- t • I BIT LATCH 4 MSB'S 10-31 ~i r-V H L....A~A I- I LSB'S Ir-o> r- A T C H c< iY' T C H IElElI D/A CONVERTER DACIO 1 r+ IElElI D/A CONVERTER DACIO 2 r+ A N A L o G IElElI D/A CONVERTER DACIO 3 o ... U T P U T S IElElI D/A CONVERTER DACIO 4 r+ OPERATING INSTRUCTIONS SPECIFICATIONS All specifications typical at 25"C unless otherwise noted. ANALOG INPUT SYSTEMS ANALOG INPUT Number of analog inputs 8 differential 16 single-ended Input voltage rangeel ) Input current loop ranges (resistor programmable) ADC gain ranges (strap selectable) Amplifier gain range (resistor programmable) Amplifier gain equation INSTALLATION MP84D8/MP8416 The M P8304, M P8408 and the M P8416.are shipped from the factory calibrated and ready for immediate use. Installation requires only plugging the card into any empty slot in the computer and routing the board's mating I/O cable. Cable placement is shown on page 10-30. The cable supplied with each board is shielded and, in the case of the M P8304, provided with the proper termination. MP8408 MP8416 ±IOmV to ±IOV 4-20mA 100SOmA. etc. ±IOV. 0 to IOV. 0 to 5V ±5V. ±2.5V ItolOOOVV G = I + 20 kO R. XI (resistor programmable) Input overvoltage protection Input impedance Bias current 25"C O"C to 70"C Amplifier output noise (Gain = 100 R, = 500n) Amplifier input offset voltage (maxi'" 400.V Amplifier input offset voltage drift 2 ±15V 100 megohms PROGRAMMING 20nA 50nA 1.2mV. rms; 7mV. p-p +~ Programming of these analog I/O boards is easily accomplished since all are treated as memory locations. The MP8304 uses a single SHLD instruction to load any of its four digital to analog converters from the Hand L registers. In a similar manner a channel in the M P8408 or MP8416 is read by a single LHLD instruction. .V "C TRANSFER CHARACTERISTICS Resolution Throughput accuracy ±IOV range (max) ±lOmV range Temperature coefficient of accuracy ± 1OV range (max; ::!-lOmV range Conversion time ±IOV range ±lOmV range CMRR (for differential inputs) Sample! hold aperture time 12 bits binary ±O.025~,( FSR(~' ±O.IIJ; FSR The voltage data for these boards is represented by a 12 bit two's complement binary number. Each bit has a value of 4.88mV, with the polarity of the voltage indicated by the sign of the binary number. Since the Hand L register pair is 16 bits long and the data word is 12 bits, the MP8408 and MP8416 set these un\lsed bits to the same value as the most significant bit of the data. This assures prop.:r representation of the data's sign. ±O.0039c FSR, "c ±O.OI(ic FSR "C 33 microseconds 100 microseconds 74 dB (DC to 2000 Hz) 30ns DIGITAL INPUT/OUTPUT All signals are compatible with Microcomputer bus Output coding An analog input channel is selected by: The output data -bits are read into:' II Bipolar. Two's Complement; unipolar. straight binary ADRI, through ADR4/ DATO, through DAT7, POWER REQUIREMENTS MP.8408. MP8416 MP8417-NS. MP8409-NS +5VDC ±5% at I amp. 25mV ripple {+5VDC ±59r at +500mA. 25mV rippJ< +15VDC ±3("t at +50mA. 5mV ripple -15VDC ±3r;'r at -75mA. 5mV ripple TEMPERATURE RANGE Temperature range O"C to 70"C ANALOG OUTPUT SYSTEMS MP8304 ANALOG OUTPUT Number of analog outputs Output voltage rangeCll Output impedance Output settling time 4 ±IOV. 0 to IOV. ±5V. 0 to 5V. ±2.5V at 5mA (strap selectable) In < 10 microseconds MECHANICAL CHARACTERISTICS TRANSFER CHARACTERISTICS Resolution Throughput accuracy (max) Temperature Coefficient of accuracy U,nipolar Bipolar 12 bits binary ±O.OI25% FSR Compatible with Intellec MDS and SBC-604/614 card spacing. Minimum card spacing: 12.7mm (0.5'') Microcompilter bus connector required: 86 pin PC edge connector with 0.156" contact centers. 40 pin analog connector (3M - 3432) provided on board. Mating connector (for OEM versions) is 3M - 3417. Recommended cable also by 3M; 3476/40. ±O.OO3% FSR!"C ±O.0045% FSR!"C DIGITAL INPUT/OUTPUT All signals are compatible with Microcomputer bus' An analog output channel is selected by; The input data bits are read by; ADR II and ADR21 DA TOI through DA T71 POWER REQUIREMENTS MP8304 MP8305-~S +5VDC ±5% at +1 amp. 25m V ripple {+5VDC ±5% at +1 amp. 25m V ripple +15VDC ±3% at +IOOmA. 5mV ripple ·15VDC +3% at ·100mA. 5mV ripple (I) Connected at the factory for ±IOV range. (2) FSR is Full Scale Range (Le .• 20V for ±IOV range. lOY forO to +IOV range). (3) The 4 MSB's when conversion is complete. followed by the R LSB's. (4) Adjustable to zero. TEMPERATURE RANGE Temperature range Each board is set at the factory for a block of addresses beginning at F720. Any analog data channel requires two memory locations since the digital data is 12 bits. The least significant 8 bits of data are always located in an even location while the remaining 4 bits are located in the next higher location. Thus, the first. analog channel is located at F720 and F721 while the second analog channel is located at F722 and F723. These boards can occupy the same address space as memory since they inhibit memory whenever they become active. O"C to 70"C 10-32 BURR-BROWN~ MP8316-1 MP8316-V IElElI MICROCOMPUTER ANALOG OUTPUT SYSTEM FEATURES DESCRIPTION .16 CHANNELS Dynamic analog outputs allow the M P83l6 to provide high channel density on a single board. This approach frees system space for other peripherals and minimizes per channel power requirement. An on-board DC-to-DC converter powers the MP8316 from the system +5VDC supply. Channel data is stored in an on-board RAM and used by the refresh circuit to update outputs. Each channel is factory-adjusted to allow system calibration to be accomplished with a single gain and offset adjustment. Memory mapped or I/O operation is a jumper-programmable option on the board. Two models of the M P8316 are available. Both models have 16 analog outputs and l2-bit resolution. The current output model (MP83l6-I) will sink up to 24.57mA on each channel and is well suited for 4mA to 20mA operation. The voltage output model (M P8316-V) can be jumpered for bipolar or unipolar operation. Both units conform to Intel's Multibusl"M specification. .0- 24.57mA or ±lOV OUTPUTS • SINGLE GAIN AND OFFSET ADJUSTMENT • MEMORY MAPPED or lID OPERATION • UP TO 20-BIT ADDRESS BUS • 12-BIT RESOLUTION • MULTIBUSTM COMPATIBLE Multlbul™. InIIl Corp. r----' DATA : BUS I I I I I I I I CHD I I I I I CHI5 I I I L__~ __ J __ .... OC·T(l.DC ~ ...... 0f5VOC GND Intemlllonil Airport Industrial Park· P.O. Box 11400· TuclDA. Arizona 85734· Tel. (602) 746·1111· Twx: 91(1.952·1111 . Cable: BBRCDRp· Telex: 66-6491 PDS-438 10-33 SPECIFICATIONS ELECTRICAL Typical at 25°C and rated power supplies unless othe~ise specified. 'MP8316-1 MODEL MP8316-V OUTPUTS Type Number of Channels Resolution Range ACCURACY Total Accuracy(1) max Offset Error linearity Gain Error Crosstalk Temperature Coefficient Volla~e Current sink 16 12-bit Ot024.57mA 10Vmin 80V max 1Wmax oto+10V oto +5V at 5mA max ±o.I% FSR(2) ±1/2LSB (0.012%1 ±II2LSB 0.1% FSR ±1/2LSB ±50ppm/oC ±0.07% FSR ±1/2LSB (0.012%1 ±1/2LSB 0.05% FSR ±1/2LSB ±30ppm/oC .16 12~bit ±10V,±5V, ±2.5V TIMING Refresh Scan Time Charge Time per Scan Settling Time to 0.1% of FSR to 1/2LSB DATA HOLD TIME ON BUS BUS CONFIGURATION POWER +SV ±5% (system bUSI I TABLE I. Description of Control Lines. Control Line Description INITI This signal resets the system. INH 11 Prevents RAM from responding. INH21 Prevents ROM from responding. comm~nd. 845~sec 645~sec MWTCI Memory write 46.2~sec 46.2/'sec IOWCI 110 write command. 8.5msec 11msec 3.5mseo XACKI Slave acknowledge to host CPU that data has been taken from data bus for write operation or that valid data has been placed on the bus for read operation. BPRNI BUS PRIORITY IN - indicates that no higher pri"orily module is reque~ting the bus. BPROI BUS PRIORITY OUT - passed to BPRNI input olthe next lower priority module. 5msec , 200nsec Multibus TM , Multibus™ , I.SA , 1.5A 200nsec ENVIRONMENT Operating Temperature Relative Humidity .' a write operation to the appropriate channel. When this occurs, the refresh circuit disables the multiplexer to prevent output glitches arid to allow the CPU to change the RAM data: Table I describes the Multibus'I'M control sign~ls~sed by the MP8316. The pinout of the bus cqnnector (PI) conforms to the M ultibus™ specifications, Control lines BPRN/ andBPRO/ are connected so that the MP8316 will not interferewith multiple processor operation when the serial' priority technique is used, The auxiliary connector (P2) is not used, I O°C to +700C 95% noncondensing OPERATING INSTRUCTIONS NOTES: 1. With gain and offset error calibrated as described under Calibration, includes linearity error, channel-ta-channel offset error, channeHochannel gain error and crosstalk. 2. FSR is full scale range. INSTALLATION The M P8316 comes factory-adjusted and ready for use. Analog outputs are available on connector P3. Current outputs require an external current source (see Figure I), The information in this publication has been carefully checked and is believed to be reliable; however, no responsibility is assumed for possible inaccuracies or omissions. Prices and specifications are subject the change without notice. No patent rights are granted to any of the circuits described herein. P3 r---' MECHANICAL , Compatible with Intellec MDS and iSBC-604/614 card spacing. Minimum card spacing: 15.2mm (0.6"1. Microcomputer bus connector required: 86-pin PC edge connector with 0.156'" contact centers." 50-pin analog edge connector on board for analog outputs, 0.100" contact centers. "Mating connectors: Burr-Brown 2250MC (Viking #3VH25I1JNS, solder tab!. 3M Corporation 3415-0001 (Scothflex, for flat cable!. CH15: 1+ : ~------------+---~ , I I , CH14 : I MPB316-1 P3 r--.., THEORY OF OPERATION The dynamic output approach uses a single digital-toanalog converter (DAC) to drive all 16 outputs. Digital data for each channel is stored in an on-board RAM and analog output data for each channel is stored in separate sample/ hold circuits. The refresh circuit contains a channel counter that selects the appropriate DAC input from RAM for the channel being updated and multiplexes the DAC output to the appropriate channel sample/ hold. Thus, the output data is updated independent of the host CPU. The CPU changes data in RAM by 4 ~!, ~~i_____________I ~~i : 48i'+ I , , I L __ ~ I MP8316-V FIGURE I. Connections for Current and Voltage Outputs. 10-34 MP8418 BURR-BROWN® IElElI MICROCOMPUTER ANALOG I/O SYSTEMS A 31-CHANNEl ANALOG INPUT, 2-CHANNEl OUTPUT SYSTEM COMPATIBLE WITH INTEL SBC80, INTEllEC® MDS AND NATIONAL BlC-80 MICROCOMPUTERS FEATURES DESCRIPTION " HIGH AND LOW LEVEL INPUTS The MP8418 series of analog I/O peripherals are electrically and mechanically compatible with and interface directly to Intel's MULTIBUS@ and other microcomputers of similar configuration. These analog systems are treated as memory by the CPU. The analog input portion of the MP8418 includes: overvoltage protection to 26VDC; provision for up to eight 4mA to 20mA inputs; an analog multiplexer; resistor programmed instrument amplifier or, a software programmable amplifier (gain of I to 1024); sample/ hold amplifier and; a 12-bit A/D converter. An optional analog output system is included on the same board. It consists of two 12-bit D / A converters with double buffered inputs to minimize glitches, and control logic. " SOFTWARE PROGRAMMABLE GAIN 11 to 1024) AMPLIFIER OPTION " ANALOG INPUT AND OUTPUT ON ONE BOARD " EASILY PROGRAMMED " MEMORY MAPPED "LOW COST " BURN-IN MP8418 is a IS-channel differential (user strapable as 31 channel single-ended) analog input system. With one expander board the system can be expanded to 63 differential channels (strapable as 127 single-ended channels). Another input channel is grounded on the board so that it may be used as ground reference for automatic calibration. Gains of I to 1024 are software selectable for the programmable amplifiers and the gain for each channel (up to 127 channels) may be stored in an on-board RAM if desired. The proper gain for each channel is then selected automatically by the MP8418. Intlmatlonal Airport Industrial Park· P.O. Box 11400· Tucson. Arizona 85734 . Tel. 1602/746-1111 . Twx: 910-952·1111 . Cable: BBRCORp· Talax: 66.fi4!11 PDS-401 I--...r--'i 1 1 1 1 1 Optional .....'" ~~~~~~~~~:.~~~U:~~~~~~ Programmable 1 ___ J Silltwa.. i +5VOC---..r-~::-, 1 Gain AmpUU" Ftr-::-::--l------. .. 1------ OUT I AD HETI +15VDC Analog Oulpuls GHO-----t_ _ _ _-u ·15VOC 1 - - - - - - DUT2 L.:.~;;.:,=..:.J_------:-- AD Am BLOCK DIAGRAM - MPB41B-AO AI D converter output and D I A converter input are 12- MECHANICAL SPECIFICATIONS Compatible with Intellec MDS and SBC-604/614 card spacing. Minimum card spacing; 15.2mm (0.61. Microcomputer bus connector required: 86-pin PC edge connector with 0.156" contact centers. One 5O-pin analog edge connector on board for analog inputs. Mating connector available from 'Burr-Brown: 2250MC. (Viking #3VH25: IJN5. solder tab); from 3M: 3415-0001 (Scotchflex). Two 20-pin analog edge connectors on board for analog outputs and analog input expansion. Mating connector available from Burr-Brown: 2220MC. (Viking !r3VH 10/ IJN5). OPERATING INSTRUCTIONS INSTALLATION Mp8418 is shipped from the factory calibrated and ready to use. Installation requires only plugging the card into any empty slot in the computer and wiring the analog connector. PROGRAMMING This peripheral is programmed as a memory location and any memory reference instruction can be used. Both the bit words. therefore. two memory locations are needed for each channel. The address block occupied by each MP8418 is user selectable and.can be placed anywhere in memory. Because these peripherals are treated as memory. a minimum of instructions are needed to read an input channel. or to set the input of a DI A converter. For example: when the MP8418 is connected in the HALT mode. the LHLD (loa:d) instruction followed by the proper address can be used to read data from an analog input channel. It will automatically select the desired channel, initiate conversion and when conversion is complete. transfer the AI D converter output to the 8080's Hand L registers. The eight least significant bits (LSB's) of the data word are transferred to the CPU first followed by the four most significant bits (MSB's). The four MSB's are in data bus positionsO-3. A singleSHLD instruction can be used to write data to one analog output channel. The eight LS B's are written first. followed by the four MSB's(in DO-D3). When the four MSB's are written to the board. all twelve bits of the data word are transferred simultaneously to the D I A converter input. AOC{ OAC Bit Placement Low Byte High Byt~ D7 1>6 1>5 1>4 D3 02 01 DO • & ~ ~ ~ • ~ • X X X X BL\ DIU &.. 8M On MP8418's, with the software programmable gain amplifier, an on-board random access memory (RAM) may be used to store the gain for each channel. In this 10-36 mode, (Control Register D4 = I). [he proper gain is automatically selected from the RAM when a channel is converted. If the RAM is not used (Control Register D4 = 0), the amplifier gain must be written to an on-board register (Control Register DO-D3). All these systems are jumpered at the factory with a base address of F700". Each subsequent channel is two memory locations past the start of the last channel, consequently channel one is at location F702'h, channel two is at location F704'h, etc. The input system operates in several modes: INTERRUPT MODE: A read instruction tothe board (ADRO = 0) starts the conversion. An interrupt is generated at the end of the conversion. The interrupt can be connected to any of eight vector locations and may also be disabled by software. Control Register D6 = I enables interrupt for interrupt mode. POLLING MODE: A read to the board starts the conversion. The interrupt is disabled by software and the CPU may then read the status word to determine when conversion is complete. Control Register D6 = 0 disables interrupt for polling mode. HALT MODE: a read instruction to the board starts the conversion. The M P8418 halts the CPU until conversion is complete, at which point the data is transferred to the CPU. Only one instruction is needed to start conversion and to transfer data to the CPU (an LHLD or POP referencedl to the channel's LS8's can be used). CONTINUOUS MODE: A read instruction to the board starts the conversion. The CPU is not halted, but reads the status of the MP8418 to determine when conversion is complete (Control Register D6 = 0) - or the CPU waits for an interrupt (Control Register D6 = I). When conversion is complete, the CPU reads the data. The read instruction is addressed to the next channel to be converted. The data from the last conversion is thus transferred to the CPU and conversion is started for the next channel. EXTERNAL TRIGGER: This mode allows a conversion to be started independent of the CPU. A read instruction is required to set the proper channel. Once the board has been set, a low to high transition of the EXTERNAL TRIGGER input (PS, pin 20) will start conversion. End of conversion can be detected by polling or interrupt technique. Data is obtained by any read command. The external trigger will start conversion independent of other board functions. The busy input (PS, pin 19) goes high at the start of conversion and goes low when the MSB of the converted data is read by CPU. ELECTRICAL SPECIFICATIONS Typ~1 at 2S"C and fated power supplies unless otherwise noted ANALOG [NPUT SECTION MP8418 INPUT CHARACTERISTICS N umber of Channels 31 si~gle-ended/IS differential ADC Gain Ranges (J ~mper Selectable)!" o to SV. 0 to IOV. ±2.SV. ±Sv. ±IOV Amplifier Gain Ranges Resistor Programmablet21 /Software Programmable I to 1000/1 to 1024 Maximum Input Voltage Without Damage(l) ±26 volts Input Impedance IOOMn. IOpF OFF Channel IOOMO. IOOpF ON Channel Bias Current (25°C) ±20nA Bias Current (0 to 70"C) ±50nA Differential Bias Current ±IOnA Amplifier Input Offset Voltage G = 1000 Resistor Programmable/Software Programmable ±400",.V,±4",.V Amplifier Input Offset Voltage Drift G = 1000 Resistor Programmable/Software Programmable ±2"Vi"C/±I"Vi"C TRANSFER CHARACTERISTICS 12 Bits Resolution Throughput Time (max) G = I Resistor Programmable/Software Programmable Throughput Time G = 1024 Resistor Programmable/Software Programmable J8psec/ JSOpsec IOO".ec/ 3S0"sec ACCURACY System Accuracy at +25°C (max)!41 G = I System Accuracy at +25°C'''1 G = 1024 Resistor Programmable! Software Programmable linearity Differenliallinearity Quantizing Error Gain Error Offset Error Monotonicity!7 1 ±O.032S% FSR'" ±O.I% FSR/±O.OS% FSR (max) ±1,2LSB ±1,2LSB ±1,2LSB AdjUitable 10 Zerol61 Adjustable to Zero Guaranteed O°C to +70°C STABIUTY OVER TEMPERATURE (Bipolar)'" System Accuracy Drift (max) G = I System Accuracy Drift G = 1024 DYNAMIC ACCURACY Sample! Hold Aperture Time Aperture Time Uncertainty Differentlal Amplifter CMRR. G Channel Crosstalk =I ±4Sppm of FSRj"C ±IOOppm of FSR/"C I 1 125nsec ±Snsec 86dB (DC to 60Hz) 8 dB down at ~~H~:::n~rF Channel 10 ANALOG OUTPUT SECTION (AO option) OUTPUT CHARACTERISTICS' N umber of Channels Output Voltage Ranges (Strap Selectable) Output Impedance Short Circuit Protection ±)ov.oto IOV.±SV.~tosv. ±2.SV at SmA 10 Yes TRANSFER CHARACTERISTICS Resolution Output Settling Time (max) 12 bits lOp-sec ACCURACY Output Accuracy Temperature Coefficient of Accuracy POWER REQUIREMENTS MP8418/MP8418·PGA MP8418·AO/MP84I8-PGA·AO ENVIRONMENTAL Operating Temperature Relative Humidity NOTES: I. 2. 3. 4. Factory set for ±IOV range. Factory set for Gain = I. With power off. ±36 volts with power on. Includes linearity creon with gain and offset errors adjusted to zero. 5. FSR means Full Seale Rang<. 10-37 ±O.OI2S% FSR ±30ppm of FSRi"C +SV ±S% at 1.2A +sv +5% at 2.0A O"C to +70°C 95% noncondensing 6. When anyone gain range is adjusted to zero gain error, the gain error for any other range is less than ±O.02% when using the software programmable amplifier. 7. No missing codes guaranteed. 8. Includes offset drift. gain drift and linearity drift. FACTORY MODE CONNECTIONS MODEL FACTORY SET MODE HALT MP8418 HALT MP84I8-AO MP8418·PGA POLI.ING INTERRlJPT' MP8418·PGA·AO POLI.ING INTERRUPT> Nok Any model can be connected in any mode. ·Inl I Factol"\' Set TABLE I., PrQgr\lmming Mode Connections. JPI7. JP29. JP81 JPI7. JP31. JP82 INTO, INTI, INn/ INn; INT4, INT5. INn, JPI6. JP29. JP81 INT71 JUMPER REQUIRED Hall Mode JPI7. JP29. JP30. JP81 Polling and Interrupt Mode Continuous Mode External Trigger Mode F71E F71F F710 F711 0001 1110 0001 IIII 00010000 00010001 CHO IN CHI IN CH2 IN CH3 IN CH4 IN CHI5 IN CHI6 IN JP70 JP71 JP72 JP73 JP74 JP75 JP7b JP77 TABLE III. Interrupt Selection. TABLE II. Mode Selection Jumpers. Factory ADR7 ... ADRO Set )'0"700 0000 0000 0000 0001 F701 0000 0010 F702 F703 0000 0011 F704 00000100 F705 0000 0101 F706 0000 OlIO F707 0000 0111 F708 0000 1000 F709 0000 1001 JUMPERS REQUIRED FOR INTERRUPT VECTOR MEMORY MAP READ gLSB's of offset STATUS LSB MSB LSB CHOOUT MSB or GAIN LSB CHI OUT MSB or GAIN .LSB MSB LSB MSB LSB ··MSB WRITE GAIN N/A CONTROL I O*~ GAIN 1* NLA N\A LSB ....... GAIN 2* MSB LSB. •••••••• GAIN 3* MSB NLA _____ GAIN 4* N/A N/A ____ GAIN 15* N/A NLA ..____GAIN 16* N/A ': Nt A - Not used. ·Used only on PGA versions when RAM gain storage is used. A read instruction (other than a STATUS REGISTER read) should not be made to the board during a conversion. Contact factory for more details. STATUSREGISTER D6 D5 D4 D3 02 DI Interrupt --------GAIN X*-------;------::--;. Write* RAM* Enable Enable Enable *Used only on versions with software programmable amplifier. D7 Convert Complete Convert Complete - The bit is low during conversion. It goes high on completion of conversion and remains high until the MSB o,f a data word is read. Interrupt enable: status of interrupt enable Write enable: status of write enable RAM enable: status of RAM enable GAIN X: current value stored in PGA GAIN control register. 10-38 BURR-BROWN® IElElI MICROCOMPUTER ANALOG INPUT EXPANDER FOR MP8418 FEATURES DESCRIPTION • 48 DIFFERENTIAL CHANNELS/ 96 SINGLE·ENDED CHANNELS M P8418·EX P is a bank of multiplexers that expand the analog input channel capacity of the MP8418 series microperipheral. Differential input capability is expanded from 15 channels to 63 channels. Single· ended capability is expanded from 31 channels to 127 channels. Control signals and power are passed to the expander from the MP8418. The analog input signal is passed to the M P8418 from the expander. Multiplexer channel addresses are latched on the expander board. The expander occupies the memory space immediately above the MP8418. Gain, data conversion, and bus interface are performed by the M P8418. Channel gains can be stored in a RAM on the PGA versions. • SOLID STATE MULTIPLEXING • 26V OVERVOLTAGE PROTECTION WITH DIODE CLAMPS • MUL TIBUSTM COMPATIBLE Mult/bu.TI , Inlll Carp, _ '" CH16 ,.. INPUT CONDITIONING MUX ---- !, f I , I I I I I INPUT CONDITIONING TO MP6418 CONTROL fROM MP6418 CONTROL , CH83 t ANALOG SIGNAL - '" ~ ADDRESS BUS International Airport Industrial Park· P.O. Box 11400 . Tucson. Arizona 85734 • Tei. 1602) 746·1111 • Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66·6491 PDS436 10-39 • .. .. ' SPECIFICATIONS , ELECTRICAL Inputs 48 differential 96 single-ended Input Protection 26V Power 110mA (from systembus) 30mA (from MP8418) 20mA (from MP8418) +5V +15V -15V FIGURE l. System Interface. TABLE I. Jumper Requirements for Differential Operation. See MPS41S Specifications for all oth~r input characteristics. Install ' Remove MECHANICAL Compatible with Intellec MDS and iSBC-604/614 card spacing. Minimum card spacing: IS.2mm (0.6"). Microcomputer bus connector required: S6-pin PC edge connector with O.lS6" contact centers. Two SO-pin analog edge connectors on board for ' analog inputs. ' Mating connectors: Burr-Brown 22S0MC (Viking #VH2S/ IJN5),soldertab; 3M Corporation: 3415-0001 (Scotchflex). Interfllce Cable: 2O-conductor ribbon cable with a card edge connector mass terminated on each end, available from Burr-Brown: MPSOOS, I" long SMSOI23-OO1, 9.S" long P5 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 Install Remove MP8418 JP44 JP33,37 JP66, 67, 68 JP2,5 JP39, 42, 43, 36,45 JP3, 4, 7 JP3 JP1 MP8418-EXP JP1 JP2 JP3 INPUT NETWORK The input network is shown in Figure 2. The switch shown represents two CMOS multiplexers in series. Input protection is provided by the series resistors and diode clamps. The clamps prevent the multiplexer inputs from exceeding the supply voltages. An optional resistor ,(R) allows the user to convert current inputs to voltage that can be detected by the MPS4IS. The optional capacitor (C) in combination with the input resistors form a low-pass filter. Low-leakage high-quality capacitors should be used to minimize errors. The optional resistor and capacitor are only useful for differential operation. !!!P. +15VDC AnalogGND -15VDC Addr, Out EXP/ DigGND AnalogGND AnalogGND IAINIAIN+ .,.'! INSTALLATION If possible, adjacent slots in the system should be used for the MPS41S and MPS4is-EXP. This is particularly, important for low level operation where longer cables, introduce noise and offset er(ors. Analog inputs connect to P3 and P4. CoilnectorP5 on the MPS4IS-EXP connects to P4 on the M PS41S to interface the two units (see Figure I). Tables I and II show jumper configurations 'for the expander and additional jumper changes required oo~M~~ MP8418-EXP JP2 TABLE II. Jumper Requirements for Single-ended Operation. INTERFACE CONNECTOR Bottom +15VDC AnalogGND -15VDC DigGND DigGND DigGNO AnalogGND Analog GND Analog GND Analog GND MP8418 JP44,45 JP33,36 JP66,67, JP3, 4, 7 JP42,39 JP2,5 , FIGURE 2. Analog Input Circuit. 10-40 MP8608 MP8616 MP8632 BURR-BROWN® IElElI MICROCOMPUTER ANALOG I/O SYSTEMS FEATURES • • • • INTEl-SBCaO and INTEllEC MDS COMPATIBLE NATIONAl-BlCaO COMPATIBLE lOW COST 70°C BURN-IN • EASY TO PROGRAM Systems are treated as memory • REDUCES SYSTEM DEVElOPMENT TIME System engineered and specified Operates from computer's +5VDC power supply if desired • EASY TO USE a to 64 input channels on one board Analog input and output on one board ~ I''''\,'~"""r-I---+-.11 g DATIl i ADRI' International Airport Industrial Park - P.O. Box 11400 - Tucson. ArlZ1IDa 85734 - Tel. (602) 746-1111 • Twx: 910-952·1111 . Cable: BBRCORP . Telex: 66-6491 PDS-36XA 10-41 DESCR·IPTION These microcomputer peripherals provide two fUnctions that interface directly to Intel's SBC80 andJn~ellec MOS microcomputers. The functions are: (I) Analog ·Data. Acquisition· and (2) Analog Output. The d~vices are electrically and mechanically compatible with anySBC80 . and Intellec MOS. Both analog input and output systems are contained on a single printed circuit board that is treated as memory input or output by the CPU. The cards will mate to any memory or I/O slot. They are cOlJlpatible with theO.6 spacing of the SBC80 or the 0.7S"spacing of the Intellec MOS. The analog interface for each system is a connector at the opposite edge of the board from the bus connector. H The Data Acquisition system is available with up to 64 channels single-ended on one board. It includes an input multiplexer, high gain instrumentation amplifier, 8-bit AID converter along with all the necessary timing, decoding and control logic. A DC I DC converter (1" 5V to ± ISV) is also available so that only the computer's power supply is required. The Data Acquisition System is available with two optional 8-bit 01 A converters to provide analog input and output on the same board. THEORY OF OPERATION When programming with these peripherals. they are. treated as memory locations. Any memory reference instruction can be used. Both the AID converter output and the 0 I A converter input are 8-bit words so one memory location is needed for each channel. Because the address block occupied by each peripheral is user selectable, it can be placed anywhere in memory. '.f' ANALOG INPUT / OUTPUT SYSTEM r-------------~------------------_, Because these units are treated as memory, a minimum of instructions are needed to read an input channel Or to set the input of a 0 I A converter. For instance, the LHLO (load) instruction followed by the proper address.can be used to read data from two successive analog input channels. It will automatically select the desired channel, initiate conversion and when conversion is complete, transfer the AID converter output for the first channel to the 8080's L register and the second channel to the H register. Likewise a single LOA instruction can be used to read one analog input channel. All of these systems are jumpered at the factory with the first channel at address F70016. Each subsequent channel is one memory location past the start of the last channel so that the second channel is at location F70l16. 10-42 _._ SPECIFICATIONS All specifications typical al 2SnC unless otherwise noted. i OPERATING INSTRUCTIONS PROGRAMMING ANALOG INPUT/OUTPUT SYSTEM ANALOG INPUT Number of analog inputs 8 differential 16 singie-ended 32 differential or 64 slOgle-ended \~l Input voltage rangell! ADC gain rangesill (strap selectable) Amplifier gain rangetn (resistor programmable) Amplifier gain equation Programming of this analog I/O board is easily accomplished since all channels are treated -as memory locations. Any memory reference instruction can be used. A single ST A instruction may be used to load the accumulator contents to one of the D / A converters. Likewise a single LDA instruction can be used to read an analog input channel. Single instructions can also be used to set the inputs of both D / A converters and read two adjacent analog input channels. An SHLD instruction referenced to DAC I will load the contents of the L register into DAC I and the contents of the H register into DAC 2. An LHLD instruction will read the channel addressed and the next higher channel. The channel addressed will be transferred to the L register and the next higher channel to the H register. Of course, any MOV instruction may also be used if direct addressing is not desired. MP8608 MP8616 MP8632 ±lOmV to ±SV ±IOV. 0 to IOV. 0 to SV ±SV. ±2.SV Ito 1000 V/V o = IOOkflj REx) Input overvoltage protection ±ISV Input impedance 100 megohms Bias current 2S"C (max) O"C to 70"C +300nA -2nA "C ±2mV Amplifier input offset voltage Amplifier input offset voltage drift ±(S+~) ~V,"C G ANALOG INPUT TRANSFER CHARACTERISTICS ±SV range (max) ±lOmV range Conversion time ±5V range ±IOmVrange CMRR (for differential inputs)(l' The normal operation of this board halts the CPU during the conversion time of the analog input system. This is because the software in this mode is simpler than in any other (i.e., only one instruction required!). If the halt feature is not desirable, it may be disabled. 8 bit binary ±O.4I"'t FSR ':' ±O.S% FSR Resolution Throughput accuracy ±5V range (max) ±10mV range Temperature coefficient of accuracy ±O.02<:t FSR, "C ±O.07lir FSR."C 44 microseconds 84 microseconds 66 dB (Gain ~ 2) 86 dB (Gain ~ 100) ANALOG OUTPUT Number of analog outputs Output voltage rangel41 2 ±IOV. 0 to IOV. ±SV. 0 to SV. ±2.SV at 5mA (strap selectable) Output impedance Output settling time (max) III < 5 microseconds The voltage data for these boards is represented by an 8bit two's complement binary number. With a ±5V range, each bit has a value of 39.lmV, with the polarity of the voltage indicated by the sign of the binary number. ANALOG OUTPUT TRANSFER CHARACTERISTICS Resolution Throughput accuracy (max) Temperature coefficient of accuracy Unipolar Bipolar 8 bits binary ±O.4% FSR ±O.OOS% FSR/'C ±O.OI% FSRtc Each board is set at the factory for a block of addresses beginning at F700. Any analog data channel requires one memory location. Thus the first analog channel is located at F700 while the second analog channel is located at F701. DIGITAL INPUT/OUTPUT All signals are compatible with Microcomputer Bus Output coding An analog input channel is selected by: An analog output channel is selected by: The input/ output data bits are read through: Bipolar. two's complement; Unipolar. straight binary ADRO/ through ADRSi MECHANICAL CHARACTERISTICS ADRO/ DATO/ through DAT7/ POWER REQUIREMENTS M P8608. M P8616. M P8632. +SVDC ±S% at I amp. 2SmV ripple With analog output MP8608-AO. MP8616-AO. MP8632-AO +5VDC ±5% at 2 amp. 2SmV ripple TEMPERATURE RANGE O"C to 7!f'C (I) Connected at the factory for ±5V range (ADC range For operation without halting the CPU, the conversion should be started by using a single channel memory reference instruction (LDA or MOV). Then the CPU should execute a routine which will take longer than the conversion time (44 to 84 microseconds). When the CPU now uses an LDA or MOV referenced to the same memory location, the converted data will be transferred to the CPU. Compatible with Intellec MDS and SBC-604/614 card spacing. Minimum card spacing: 12.7mm (0.5"). Microcomputer bus connector required: 86 pin PC edge connector with 0.156" contact centers. 50 pin analog edge connector on board. = ±IOV. Gain = 2). Mating connector available from Burr-Brown: 2250MC (Viking # 3VH25/ IJN5, solder tab); from 3M: 3415-0001 (Scotchflex). (2) FSR is Full Scale Range (i.e .. IOV for ±5V range). (3) DC to 60Hz with I kn source unbalance. (4) Connected at the factory for ±IOV range. (5) Connected at the factory as 32 differential. 10-43 INDUSTRIAL SYSTEMS PRODUCTS 1082000 A Complete I/O System That Makes I/O Handling Easy... Reduces Control System Costs Vsing its preprogrammed microprocessor. IOS2000 can be the sensory center of your control system. Fully expandable. transparent to CPV and operator. IOS2000 reduces system design I installation costs - is burdenless to your CPU/software. Remotely located. this intelligent front-end collects and conditions sensor inputs - sends them to your CPV already digitized and preprocessed. Operating in a closed loop. IOS2000 responds to CPV commands - generates contact closure outputs to turn on lights. motors ... generates analog output voltages and currents to modulate valves. establish set points. etc. Routine sensor signal conditioning and intelligent internal hou .... keeping programs automatically occur every time an operator communi- cates with IOS2000. Vp to 15 clustered IOS2000 systems can be connected to one ASCII serial comll)unications line. As a reSUlt. up to 10.000 110's can be handled. Vse IOS2000 as extended front ends in stand-alone applications using programmable terminals orCPV·s. Plug-in modules let you ~ add sensors. outputs. more power in the field as demand grows. Rack mounted card cages. remote termination panels. NEMA-4 enclosures plus I/O options let you match IOS2000 exactly to your needs. C8450 A Stand-Alone Measurement and Control System That's Easy To Install, Program, Operate Spell out your process. control. measurement or test steps in logical operational sequence using our BASIC -400 that speaks your language. Vse preprogrammed keyboard "Function" keys to simplify commands for untrained operators. Your program. once written into CS450's memory. is tra nsferred to disk and or cassette tape storage where it becomes a permanent program that can be re-run as you wish. AVTOSTART automatically reloads your stored program into CS450's operating memory. The operator does not load the program and. in fact. CS450 can start up and control processes without operator involvement. Mass storage. printer. alarm. process 1'0. AVTOSTART. real time clock and calendar are built into a compact tahle top or rack mount package. CRT is an option. Up to seven analog. digital and discrete I 0 boards plug into CS450's Multibus"" compatihle card cage. Connect sensor inputs control outputs and you're ready to run! CS430: rugged. lower cost...uses dual minicassette tape drives rather th,;';iijual disk drives which are standard on CS450. All other functions 3re identical. Multibus™ ~ Intel Corp. 11-1 II -.' ; MCS100 DATA ACQUISITION SYSTEM Truly Cost Effective Analog and Digital I/O Now remote I/O is a practical option because MCSIOO significantly reduces the total design. installation and operating costs of data acquisition and control systems. Because of its modular design - and MultibusrM capability - you can purchase a system configured for today's needs. but be assured that you can expand it later with minimum problems and cost. This versatile system eliminates most signal conditioning while maintainingdata accuracy over industrial temperature ranges of 0 to +50·C. It offers both analog and digital inputs and outputs incorporating Burr-Brown's full range of 1:0 functions. Up .to nine of these Multibus™ compatible 110 cards can be placed in each card cage. Memory-mapped I '0 addressing simplifies programming. Open card, cage and' rack mount chassis. plus !'lEMA and explosion-proof enclosures options. add installation flexibility to MCSIOO. Up to 16.320 inputs/outputs can be handled when 15 MCSIOO's are multidropped on one serial communications line. CPU operator involvement as well as maintenance procedures are sharply reduced. Costly fragile calibration equipment is not req'uired. MultibU!rl . Intel Corp. MICROMUX A Two-Wire System That Takes The Cost... Complication Out of Remote Data Acquisition Locate a MICROMUX Remote Transmitter near monitoring points. input up to 16 analog or digiial signals: thermocouples. voltage and current signals. discrete voltage. Inputs are converted to multiplexed digital signals which are tran~mitted. not by 32 wires. but by a single· wire pair to the receiver. Locate the MICROM'UX' Receiver near your CPU. It receives signals from up to four remote transmitters. converts them to three-1_1 · - on t 72.14mm (2.S4") ~=-+---->,--~©~ 5mm (0.2'" Clearance for screw on 4~O ""mm Clearance for 19.D5mm (0.75") center 4-40 3.17mm (D.125")~ IJ - I " I .JO< Screw @ 3.1Smm (D. 125::ll.L IT I • Q~ 12.19mm I 1.94mm (0.47") 12-3 (D.4S") MATING CONNECTORS 2201MC l 62.S7mm !-----(2.475")±O.1o - - - - - - . l 5S.42mm (2.300")±0.015' "---,--.l • 53.34m(T1 , . . (2.100")±0.005 -_...;_-_..J· I [t== 'o-+A!....fl":2"""3:-4:-------------.--"'.Hr-._-__-_-_-_-_-__ 1.37mm -1.80mrn (.054" - .0:71") Accommodates Thick Circuit Board I ......L.+---"ITsmm o (0.33")±0.005 B 1 2 3 4 _-- I --I r ~ -----\\---- 2.54mm j-(O.lO")tyP 1.40mm (0.055")typ II --II--- (Non-accumulative) Oepth .79mm 7S.11mm 1o----~7"'0.... 44"T"m-m:------(3.075")±0.015 (2.775")±0.005 6.1Omm O.64mm (0.24") ± (0.025") '1.52mm '\..(O.06"')typ (0.031") JL Pierced Accommodate 3·26 AWG Wire 2350MC 50.S0mm 1----------(2.00 0") 2 .54mm (0.10")19 places 1t I - - - - - - - - - - -..i 2.64mm ~1~1~1~1~1~1~1~1~1~1~1~I~l®l~l~l~I~I~I~J==f (O.10·:~9mm (0.031") 12-4 HEAT SINKS 0803HS 12°C/WATT 0804HS 4.2°C/WATT (See notes) TOP VIEW (See notes) 1_ I 25.4mm...J (1.0") -I TOP VIEW 'i f 79.5mm (3.13") typo SIDE VIEW 2.3mmffiUTIlT +"·f~ Material: Aluminum 2.3mm Material: Aluminum Finish: Black Anodized Finish: Black Anodized (SIDE VIEW) (0.09") 0805HS 3°C/WATT Ii --1 f+ 6-32 Thread (4 Holes) TOP VIEW o 61I See Oelail1 o (3.99") o o _ JUJIIJIL...~--JIL~·I u.JII 1 1 91.9mm (3.62") I 101.35mm -1--+--- 0° °0 0 +0 o 0 ---1--+--'---;--7" I o 40.4mm (1.59") 46.0mm (1.81") -61-1----1 --61 BOTTOM VIEW END VIEW 64.3mm (2.53") 17.5mm (0.69") ---.- Detail 1 'NOTES 3.86mm (0.152") 1. Thermal resistance specified are for natural connection. Heatsinks 0803HS and 0804HS are mounled on 6" x 6" x 1/16" G-l 0 PC board. 2. A thin-film of heatsink compound(Oow Corning 340 or equivalent) between the heatsink and the TO-3 device is recommended. dia. (2 Holes) Hole Pattern 12-5 Material: Aluminum Finish: Black Anodized ·.:,t·,' INTERNATIONAL SALES DIRECTORY BURR-BROWN OFFICES AUSTRIA Nlederla..ung O..larrelch Burr-Brown R_rch Ge.m.b.H. Sen.leld.rg.... 11 A-1100 Wlen Tel: 0222182 83 71 Tel.x: 134777 JAPAN Burr-Brown Japan Ltd. 5F Inou. Akauka Bldg. 11-8. 1-chome, Aka.aka Mlnato-ku, Tokyo 107 Tel: (03) 588-8141 Talex: 78125911 O.aka: Tel. 08-305-3287 BENELUX Burr-Brown Internallonal B. V. P.O. Box 7735 1117 ZL Schlphol Holland T.I: 020/470590 T.I.x: 13024 SWITZERLAND Burr-Brown AG W.lngart.n.lr.... 9 CH-8803 Rueechllkon/Zurlch Tel: 01-724-09 28 T.I.x: 845 59880 UNITED KINGDOM Burr-Brown InlemaHonal LId. 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