1982_Zilog_Data_Book 1982 Zilog Data Book

User Manual: 1982_Zilog_Data_Book

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1982/83
DafaBook

Zilog
Pioneering the
Microworld

Copyright 1981, 1982 by Zllog, Inc. All rIghts reserved. No
part of thIs publIcatIon may be reproduced, stored In a
retrIeval system I or transmItted, In any form or by any means,
electronic, mechamcal, photocopymg, recordmg, or other~
WIse, wIthout the pnor written permISSIon of 2110g.
The mformatIon contamed herem IS subject to change
wIthout nobce. 2110g assumes no responslblhty for the use of
any CIrcuItry other than CIrCUItry embodIed In a Zilog pro·
duct. No other CircUlt patent heenses are ImplIed

Microcomputers in Every Form
Zilog offers mICrocomputers m
every form: from components and
development systems to board-level
products and complete generalpurpose mICrocomputer systems.
ThIs edItion of the Zi]og Data Book
describes Zilog components,
development systems, and microcomputer boards. You'll also fmd a
section on the m-depth trainmg
courses now offered about most
Zilog products.
Zllog components, the basic
building blocks for our other
microcomputer products, include

the 8-blt Z80® MIcroprocessor and
its famIly of mtelhgent peripherals,
the Z8™ FamIly of Smgle-Chlp
MICrocomputers, and the l6-blt
Z8000™ MIcroprocessor and ItS
family of mtelligent peripherals.
Zllog offers a wide variety of
development envIronments, rangmg from the mexpenslve Z8 and
Z8000 Development Modules to the
more elaborate PDS 8000 and
ZDS-l Development Systems to the
ultra-sophlShcated mulh-user
Z-LAB 8000 Development System.
In addlhon, EMS 8000 and Z-SCAN

III

8000 both provIde in-cIrcuit emulahon for the Z8001 and Z8002
MIcroprocessors.
Our Z80 MCB Board FamIly
offers a complete soluhon for prototype and produchon desIgns in
which you don't want to desIgn a
mIcrocomputer from scratch. ThIs
well-estabhshed famIly mcludes a
Z80 CPU board, several types of
. memory boards, and boards for all
types of dIgItal and analog 110. A
complete set of card cages,
enclosures, and other accessories
makes thIs famIly easy to use.

Table of Contents
zao

Family .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28400 CPU Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28300 CPU Central Processmg Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28410 DMA Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28420 PIO Parallel Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28430 CTC Counter/Timer CIrcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28440/1/2 SIO Serial Input/Output Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28470 DART Dual Asynchronous Receiver/TransmItter .................................................

3
5
27
49
67
81
93
109

zaooo Family ...................................................................................
2800112 CPU Central Processmg Unit ...............................................................
28003/4 VMPU Virtual Memory Processmg Unit .......................................................
28010 2-MMU Memory Management Unit ............................................................
28015 PMMU Paged Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28016 DTC Direct Memory Access Transfer Controller .................................................
28030 2-SCC Serial Communications Controller ......................................................
28031 2-ASCC Asynchronous Serial Communications Controller ........................................
28036 2-CIO Counter/Timer and Parallel I/O Umt .....................................................
28038 2-FIO FIFO Input/Output Interface Unit ........................................................
28060 FIFO Buffer Unit and 2-FIO Expander .........................................................
28065 2-BEP Burst Error Processor ..................................................................
28068 2-DCP Data Ciphering Processor ..............................................................
28070 Floating Point Package ......................................................................
28090 2-UPC Universal Peripheral Controller ........................................................

123
125
153
155
171
173
175
197
217
241
273
281
295
311
313

Universal Peripherals ............................................................................
28530 SCC Serial Communications Controller ........................................................
28531 ASCC Asynchronous Serial Communications Controller ..........................................
28536 CIO Counter/Timer and Parallel I/O Unit ......................................................
28538 FlO-See 28038 2-FIO ......................................................................
28581 Clock Generator and Controller ..............................................................
28590 UPC Universal Peripheral Controller ..........................................................

335
337
359
379
241
403
407

za

Family .................... ..................................................................
2860112/3 MCU Microcomputer ....................................................................
28611/2/3 MCU Microcomputer ....................................................................
28671 MCU Microcomputer with BASIC/Debug Interpreter .............................................
28681 MCU Microcomputer .......................................................................

429
431
449
467
469

Additional Information
2ilog 2-BUS Component Interconnect ...............................................................
2-BUS Backplane Interconnect .....................................................................
Advanced Architectural Features of the 28000 CPU ...................................................
An Introduction to the 28010 MMU ..................................................................
High Reliability Microcircuits ......................................................................

475
493
497
511
531

Package Dimensions
Package Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
18-Pin Packages .................................................................................
28-Pin Packages .................................................................................
40-Pin Packages .................................................................................
48-Pin Packages .................................................................................
28- and 44-Pin Leadless Packages ...................................................................

535
536
537
538
540
541

v

Table of Conlenls (Continued)
zaD Microcomputer Board Products ................................................................ 545
Z80 MCB Single Board Computer ...................................................................
280 RMB RAM Memory Board ......................................................................
Z80 Ala/AlB Analog InpuVOutput and Analog Input Boards ............................................
280 lOB Input/Output Board .......................................................................
280 SIB Serial Interface Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
280 PPB PROM Programming Board ................................................................
280 PMB PROM Memory Board .....................................................................
280 MDC Memory and Disk Controller Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28000 Dual Processor Upgrade Package .............................................................

547
551
553
557
559
563
565
567
571

Zilog Development Products .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
System 8000 2-LAB ...............................................................................
EMS 8000 Emulator Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-SCAN 8000 ....................................................................................
Z8000 Development Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
28000 Cross-Software Package .....................................................................
Z8000 Software Development Package ...............................................................
28000 PLZlSYS Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2RTS 2ilog Real-Time Software .....................................................................
PDS 8000 Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2DS 1/40280 Development System ..................................................................
280 PL2 Compiler ................................................................................
RIO ElectrIC Blackboard ..........................................................................
28 Development Module ..........................................................................
28 Software Development Package ..................................................................

575
577
591
593
597
601
603
605
607
611
615
619
621
623
627

Zilog Technical Training . ........................................................................ 631

VI

Funclionallndex
Single-Chip Microcomputers

Z8601
Z8602
Z8603
Z8611
Z8612
Z8613
Z867 1
Z8681

Z8 8-Bit with 2K ROM .....................................................................
Z8 8-Bit with Memory Interface, 64-Pm, 2K External ROM ......................................
Z8 Prototyping Device with EPROM Interface, Protopack, 2K External ROM .......................
Z8 8-Bit, with 4K ROM ....................................................................
Z8 wIth Memory Interface, 64-Pin 4K External ROM ............................................
Z8 Prototyping Device with EPROM Interface, Protopack, 4K External ROM .......................
8-Bit BASIC/Debug Interpreter ............................................................
8-Blt with No On-Chip ROM ...............................................................

431
431
431
449
449
449
467
469

a-Bit Microprocessors

Z8300
Z8400
Z8410
Z8420
Z8430
Z8440
Z8441
Z8442
Z8470
Z858 1

Z80L Low-Power Central Processmg Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 CPU Central Processing Umt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z80 DMA DIrect Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 PIO Parallel Input/Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 CTC Counter/Timer Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 SIO Dual Channel Serial Input/Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 SIO Dual Channel Serial Input/Output Controller . . . . . . . . . . . . . . . . . . . . . .. .................
Z80 SIO Dual Channel Serial Input/Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 DART Dual Asynchronotls Receiver/TransmItter ...........................................
Clock Generator and Controller ............................................................

27
5
49
67
81
93
93
93
109
403

IS-Bit Microprocessors

Advanced ArchItectural Features of the Z8000 CPU ...........................................
Introduction to the Z8010 MMU .............................................................
Zilog Z-BUS Component Interconnect .......................................................
Z-BUS Backplane Interconnect .............................................................
Z8001/2 Z8000 CPU Central Processmg Unit .........................................................
Z8003/4 Z8000 VMPU Virtual Memory Processing Unit ................................................
Z8000 Z-MMU Memory Management Umt ....................................................
Z8010
Z8015
Z8000 PMMU Paged Memory Management Umt ...............................................
Z8000 DTC Direct Memory Access Transfer Controller ..........................................
Z8016
Z8030
Z8000 Z-SCC Senal Commumcatlons Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z8031
Z8000 Z-ASCC Asynchronous Senal Commumcatlons Controller ................................
Z8036
Z8000 Z-CIO Counter/TImer and Parallel I/O Unit .............................................
Z8038
Z8000 Z-FIO FIFO Input/Output Interface Unit ................................................
Z8060
Z8000 FIFO Buffer Unit and Z-FIO Expander .................................................
Z8000 Z-BEP Burst Error Processor ..........................................................
Z8065
Z8000 Z-DCP Data Clphermg Processor ......................................................
Z8068
Z8070
Z8000 Floatmg Point Package ..............................................................
Z8000 Z-UPC Umversal Peripheral Controller ................................................
Z8090
Z8581
Clock Generator and Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

497
511
475
493
125
153
155
171
173
175
197
217
241
273
281
295
311
313
403

Microprocessor Peripherals
Serial Communications Controllers

Z8030
Z8031
Z8440
Z844 1
Z8442
Z8470
Z8530
Z8531

Z8000 Z-SCC Serial Communications Controller
Z8000 Z-ASCC Asynchronous Serial Communications Controller ...............................
Z80 SIO Dual Channel Serial Input/Output Controller ........................................
Z80 SIO Dual Channel Senal Input/Output Controller ........................................
Z80 SIO Dual Channel Senal Input/Output Controller ........................................
Z80 DART Dual Asynchronous ReceIver/TransmItter ..........................................
SCC Senal Commumcatlons Controller ....................................................
ASCC Asynchronous Senal Commumcatlons Controller ......................................

VII

.
.
.
.
.
.
.

175
197
93
93
93
109
337
359

Functional Index

(Continued)

Microprocessor Peripherals (Continued)
Parallel 1/0 and Counter/Timers

28036
28000 2-CIO Counter/Timer and Parallel I/O Unit .............................................
28038
28000 2-FIO FIFO Input/Output Interface Unit ................................................
28060
28000 FIFO Buffer Unit and 2-FIO Expander .................................................
28536
CIO Counter/Timer and Parallel I/O Unit ....................................................
Universal Peripheral Controllers

217
241
273
379

28090
2809113
28092/4
28590
2859113
28592/4

313
313
313
407
407
407

28000 2-UPC Universal Peripheral Controller ................................................
28000 2-UPC External ROM-Based Universal Peripheral Controller ..............................
28000 2-UPC External RAM-Based Universal Peripheral Controller ..............................
UPC Universal Peripheral Controller .......................................................
UPC External ROM-Based Universal Peripheral Controller .....................................
UPC External RAM-Based Umversal Peripheral Controller .....................................

Clock Products

28581

Clock Generator and Controller ............................................................ 403

Board Products

Dual Processor Upgrade Package for Z80 Systems .....................................................
280 AIO/AIB Analog Input/Output and Analog Input Boards ............................................
280 lOB Input/Output Board .......................................................................
280 MCB Single Board Computer ...................................................................
280 MDC Memory and Disk Controller Board .........................................................
280 PLZlSYS Complier for the 280 ..................................................................
280 PMB PROM Memory Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
280 PPB PROM Programmer Board ................................................................ ,
280 RMB RAM Memory Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
280 SIB Serial Interface Board .....................................................................

571
553
557
547
567
619
565
563
551
559

Development Products

EMS 8000 In-Circuit Emulator Subsystem ............................................................
PDS 8000 Single-User Development System ..........................................................
RIO Electric Blackboard, CRT Editor for PDS and 2DS Systems ..........................................
System 8000 2-LAB Multi-User Development System ...................................................
2DS 1140280 In-Circuit Emulator and Development System .............................................
2RTS 2ilog Real- Time, Multitaskmg Software Tools ....................................................
2-SCAN 8000 In-ClrcUlt Emulator ..................................................................
28 Development Module, Prototyping and Evaluahon Board .............................................
280 Software Development Package, Cross-Assembler for 280-Based Development Systems ..................
280 PLZlSYS Compiler for the 280 ..................................................................
28000 Cross-Software Package, C Cross-Compiler and Assembler for the Z8001 and Z8002 ...................
28000 Development Module, Prototyping and Evaluahon Board ..........................................
28000 PLZ/SYS Compiler for the 28000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z8000 Software Development Package, Cross-Assembler for Z80-Based Development Systems ................

VIIl

591
611
621
577
615
607
593
623
627
619
601
597
605
603

Pari Number Index
Part Number

05-0067-00
05-0069-00
05-0103-00
05-0122-00
05-6003-XX
05-6006-03
05-6007-01
05-6009-XX
05-6011-XX
05-6013-05
05-6015-01
05-6023-01
05-6075-01
05-6101-01
05-6102-01
05-6158-01
05-6168-01
05-6219-00
06-0086-01
07-3028-00
07-3029-00
07 -3301-01
07-3302-01
07-3306-02
07-3309-01
07-3310-01
07-3361-01
07-3362-01
Z8000
Z8001
Z8002
Z8010
Z8015
Z8016
Z8030
Z8031

Description
System 8000 Z-LAB Multi-User Development System, Model20, 50 Hz .......................
System 8000 Z-LAB Multi-User Development System, Model 30, 50 Hz .......................
Z-SCAN 8000 In-Circuit Emulator ......................................................
EMS 8000 In-Circuit Emulator Subsystem ...............................................
Z80 RMB RAM Memory Board .........................................................
Z80 lOB Input/Output Board ..........................................................
Z80 SIB Serial Interface Board .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 MCB Single Board Computer " ....................................................
Z80 MDC Memory and Disk Controller Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ZDS 1140 Z80 In-Circuit Emulator and Development System ................................
Z80 PPB PROM Programmer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z80 PMB PROM Memory Board ........................................................
Z80 AIO/AIB Analog Input/Output and Analog Input Boards ...............................
Z8002 Development Module ...........................................................
PDS 8000 Single-User Development System ..............................................
Z8 Development Module ..............................................................
Z8001 Development Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dual Processor Upgrade Package for Z80 Systems ........................................
Z8000 Cross-Software Package, C Cross-Compiler and Assembler for Z8001 and Z8002,
DEC 11170 with UNIX' ...............................................................
RIO Electric Blackboard, CRT Editor for ZDS Systems .....................................
RIO Electric Blackboard, CRT Editor for PDS Systems .....................................
Z80 PLZlSYS Compiler for use with PDS 8000/05 and PDS 8000/15 ...........................
Z80 PLZ/SYS Compiler for use with ZDS-I Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z8000 Software Development Package, Cross-Assembler for Z80-Based Hard Disk Systems with
Optional Floppy Drives .............................................................. ,
Z8000 Software Development Package, Cross-Assembler for PDS 800/5 ......................
Z8000 Software Development Package, Cross-Assembler for ZDS-I Series ....................
Z8 Software Development Package, Cross-Assembler for use with PDS 8000/5 and
PDS 8000115 ., ......................................................................
Z8 Software Development Package for use with ZDS-l Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ZRTS Z8000 Real- Time, Multitasking Software Tools .......................................
16-Bit, Segmented Central Processing Unit ..............................................
16-Bit, Non-Segmented Central Processing Unit ..........................................
Z8001l3 Z-MMU Memory Management Unit ............................ , .................
Z8000 PMMU Paged Memory Management Unit ..........................................
Z8000 DTC Direct Memory Access Transfer Controller ....................................
Z8000 Z-SCC Serial Communications Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Z8000 Z-ASCC Asynchronous Serial Communications Controller ...........................

"Trademark of Bell LaboratorIes.

IX

577
577
593
591
551
557
559
547
567
615
563
565
553
597
611
623
597
571
601
621
621
605
605
603
603
603
627
627
607
125
125
155
171
173
175
197

Pari Number Index (Continued)
Part Number

28036
28038
28060
28065
28068
28070
28090
28091/3
28092/4
28300
28400
28410
28420
28430
28440
28441
28442
28470
28530'
28531
28536
28581
28590
28591
28592
28593
28594
28601
28602
28603
28611
28612
28613
28671
28681

Description

28000 2-CIO Counter/Timer and Parallel 1/0 Unit ........................................
28000 2-FIO FIFO Input/Output Interface Unit ...........................................
28000 FIFO Buffer Unit and 2-FIO Expander .............................................
28000 2-BEP Burst Error Processor .....................................................
28000 2-DCP Data Ciphering Processor .................................................
28000 Floatmg Point Umt .............................................................
28000 2-UPC Universal Peripheral Controller ............................................
28000 2-UPC Universal Peripheral Controller, External ROM-Based .........................
28000 2-UPC Universal Peripheral Controller, External RAM-Based .........................
280L CPU Low-Power 280 Central Processing Unit ...................................... "
280 CPU 280 Central Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
280 DMA Dual Port, Direct Memory Access Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
280 PIO Dual Port, Parallel InputlOutput Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
280 CTC Four Channel CounterlTimer Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
280 SIOIO Dual Channel SynchronouslAsynchronous Serial I/O Controller ................. "
280 SIOll Dual Channel Synchronousl Asynchronous Serial 1/0 Controller . . . . . . . . . . . . . . . . . ..
280 SIO/2 Dual Channel Synchronousl Asynchronous Serial I/O Controller .. . . . . . . . . . . . . . . . ..
280 DART Dual Channel Asynchronous Serial 1/0 Controller ...............................
SCC Serial Communications Controller .................................................
ASCC Asynchronous Serial Communications Controller ..................................
CIO Counter/Timer and Parallel I/O Unit ...............................................
Clock Generator and Controller .......................................................
UPC Universal Peripheral Controller ...................................................
UPC Universal Peripheral Controller with External ROM ..................................
UPC Universal Peripheral Controller with External RAM ..................................
UPC Umversal Peripheral Controller with External ROM, Protopack .........................
UPC Universal Peripheral Controller with External RAM, Protopack .........................
28 8-Bit, Single-Chip Microcomputer with 2K ROM .......................................
28 8-Blt Microcomputer with Memory Interface, 64-Pin, 2K External ROM ....................
28 Prototyping Device with EPROM Interface, Protopack, 2K External ROM ...................
28 8-Blt, Smgle-Chip Microcomputer with 4K ROM .......................................
28 8-Blt MICrocomputer with Memory Interface, 64-Pin, 4K External ROM .................. "
28 Prototyping Device with EPROM Interface, Protopack, 4K External ROM ...................
28 8-Blt, Single-Chip BASICIDebug Interpreter ..........................................
28 8-Bit, Smgle-Chip Microcomputer with No On-Chip ROM ...............................

*Al! 85XX components are compatJble with processors other than Z110g's 28001,28002,28003,
and Z8004 For further mformatlOn refer to the indIvidual product speClhcatlOns

x

217
241
273
281
295
311
313
313
313
27
5
49
67
81
93
93
93
109
337
359
379
403
407
407
407
407
407
431
431
431
449
449
449
467
469

Zilog Z80® Family

~
Zilog

Sets the Industry
Standard for 8 Bits

June 1982
Zilog remams an industry leader,
thanks to continumg innovation m
mIcrocomputer concepts and integrated desIgn as exemphfied in the
Z80 Family microcomputer
products.
At Zilog, innovahon means usmg
proven, sophisticated mamframe
and minicomputer concepts and
translating them into the latest LSI
technologies. Integration means
more than designmg an evergreater number of functions onto
a single chip. Zllog mtegrates
technologies-LSI design
enhanced by advances m
computer-based system archItecture and system design
technologies.
Zilog offers mIcroprocessor
soluhons to computing problems:
from components and development
systems to OEM board-level products and general-purpose
mIcrocomputer systems.
This gUIde to the Z80 Family of
state-of-the-art microprocessors
and mtelhgent peripheral controllers demonstrates Zllog's continued support for the Z80
microprocessor and the other
members of the Z80 product
famlly-a family first introduced in
1976 that continues to enjoy growing customer support while family
chIps are upgraded to newer and
ever-higher standards.
The Z8400 Z80 CPU Central Processing Unit rapidly established
Itself as the most sopl}isticated,
most powerful, and most versa hIe
8-blt mIcroprocessor in the world.
It offers many more features and

funchons than ItS competitor.
In addItion to bemg source-code
compatible wIth the 8080A
microprocessor, the Z80 offers
more mstruchons than the 8080A
(158 vs. 78) and numerous other
features that simplify hardware
reqUIrements and reduce programmmg effort whIle mcreasing
throughput. The dual-register set
of the Z80 CPU allows hIgh-speed
context sWItching and more efficIent mterrupt processmg. Two
index registers gIve addltlOnal
memory-addressing flexlblhty and
slmphfy the task of programmmg.
Interfacing to dynamiC memory IS
simphfied by on-chip, programmable refresh logic. Block moves
plus string- and bit-manipulahon
instruchons reduce programmmg
effort, program SIze, and execution
time.
Now the Z8300 Z80L CPU extends
the range of Z80 apphcahons. This
low-power version retains all Z80
CPU functions while providmg
dramahc power savmgs and
mcreased rehabihty.
The four tradItional functlOns of
a microcomputer system (parallel
I/O, serial I/O, counting/timmg,
and direct memory access) are
eaSIly implemented by the Z80
CPU and the followmg well-proven
famIly of Z80 peripheral devIces:
Z80 PIO, Z80 SIO, Z80 DART,
Z80 CTC, and Z80 DMA.
The easily programmed, dualchannel Z8420 Z80 PIO Parallel
Input/Output Controller offers two
8-bit I/O ports wIth mdividual
handshake and pattern recognition

logIc. Both I/O ports operate m
either a byte or a bIt mode. In
addition, this device can be programmed to generate interrupts for
various status condlhons.
All common data communications protocols, asynchronous
as well as synchronous, are
remarkably well handled by the

Z8440 Z80 SIO Serial Input/Output Controller. ThIs dual-channel
receIver/transmitter devIce offers
on-chIp parity and CRC generahon/checkmg. FIFO buffermg
and flag- and frame-detechon
generahon logic are also offered.
If asynchronous-only applications are required, the costeffective Z8470 Z80 DART Dual
Asynchronous Receiver/Transmitter can be used in place of the Z80
SIO. The Z80 DART offers all Z80
SIO asynchronous features in two
channels.
Timmg and event-counting funchons are the forte of the Z8430 Z80
CTC Counter/Timer Controller.
The CTC proVides four counters,
each wIth mdivldually programmable prescalers. The CTC IS a
convenient source of programmable clock rates for the SIO.
With the Z8410 Z80 DMA Direct
Memory Access Controller,
data can be transferred directly
between any two ports (typically,
I/O and memory). The DMA transfers, searches, or search/transfers
date in Byte-by-Byte, Burst, or
Continuous modes. This device can
achieve an impressive 2M bits per
second data rate m the Search
mode.

3

Z8400
Z80®CPU Central
Processing Unit

~
Zilog

Product
Specification

June 1982
Features

• The instruction set contains 158 instructions.
The 78 instructions of the 8080A are
included as a subset; 8080A software compatibility is maintained.

may be daisy-chained to allow implementation of a priority interrupt scheme. Little,
if any, additional logIc is required for
daisy-chaimng.

• Six MHz, 4 MHz and 2.5 MHz clocks for the
Z80B, Z80A, and Z80 CPU result in rapid
instruction execution with consequent high
data throughput.

• Duplicate sets of both general-purpose
and flag registers are prOVided, easing
the design and operation of system software through Single-context SWItching,
background-foreground programming, and
single-level interrupt processing. In addition, two l6-bit index registers facilitate
program processing of tables and arrays.

• The extensive instruction set includes string,
bit, byte, and word operations. Block
searches and block transfers together with
indexed and relative addressing result in
the most powerful data handling capabilities
in the microcomputer industry.
• The 280 microprocessors and associated
family of peripheral controllers are linked
by a vectored interrupt system. This system

.n~1

CONTROL

Mi

-1

• On-chip dynamic memory refresh counter.

As
A,
A,

MREQ

.
A,

lORa

RD

w-

A,

RFSH

A,

HAL.T

As
As

Z 80 CPU

A"

A"
A,

A"

A,

A"

A,
A,

A"

A,

CONTROL

• There arl'l three modes of high speed interrupt processing: 8080 compatible, non-Z80
penpheral device, and Z80 Family
peripheral with or without daisy chain.

ADDRESS
BUS

A"

A"
elK

A"

0,

A,

A"

0,

A,

A"

0,

A,

A"

0,

A,

A"

+5V

As

0,

CPU {
BUS
CONTROL

2001·0210, 0211

GNO

0,

RFSH

Do

Mi

0,

RESET

iNT

BUSREQ

NMI

WAIT

HALT

Figure 1. Pin Funciions

A,

SUSACK

MREQ

WR

lORa

AD

Figure 2. Pin Assignments

5

General
Description

The Z80, Z80A, and Z80B CPUs are thirdgeneration single-chip microprocessors with
exceptional computational power. They offer
higher system throughput and more efficient
memory utilization than comparable secondand third-generation microprocessors. The
internal registers contain 208 bits of read/write
memory that are accessible to the programmer.
These registers include two sets of six generalpurpose registers which may be used
individually as either 8-bit registers or as
l6-bit register pairs. In addition, there are two
sets of accumulator and flag registers. A group
of "Exchange" instructions makes either set of
main or alternate registers accessible to the
programmer. The alternate set allows operation
in foreground-background mode or it may be

reserved for very fast interrupt response.
The Z80 also contains a Stack POinter, Program Counter, two index registers, a Refresh
register (counter), and an Interrupt register.
The CPU is easy to incorporate into a system
since it requires only a single + 5 V power
source. All output signals are fully decoded
and timed to control standard memory or
peripheral CIrcuits, and it is supported by an
extensive family of peripheral controllers. The
internal block diagram (Figure 3) shows the
primary functions of the Z80 processors.
Subsequent text provides more detail on the
Z80 I/O controller family, registers, instruction
set, interrupts and daisy chaining, and CPU
timing.

_-_II

ALU

+5V .....

GND .....
CLOCK ....

Figure 3. Z8D CPU Block Diagram

6

2001-0212

zao Microprocessor
Family

each of which has an 8-bit prescaler. Each
of the four channels may be configured to
operate in either counter or timer mode.

The Zilog Z80 microprocessor is the central
element of a comprehensive microprocessor
product family. This family works together in
most applica!Jons with minimum requirements
for additional logic, facilitating the design of
efficient and cost-effective microcomputerbased systems.
Zilog has designed five components to provide extensive support for the Z80 microprocessor. These are:

• The DMA (Direct Memory Access) controller provides dual port data transfer
operations and the ability to terminate data
transfer as a result of a pattern match.
• The SIO (Serial Input/Output) controller
offers two channels. It is capable of
operating in a variety of programmable
modes for both synchronous and asynchronous communication, including
Bi-Sync and SDLC.

• The PIO (Parallel Input/Output) operates in
both data-byte I/O transfer mode (with
handshaking) and in bit mode (without
handshaking). The PIO may be configured
to interface with standard parallel
peripheral devices such as printers, tape
punches, and keyboards.

• The DART (Dual Asynchronous Receiver/
Transmitter) device prOVides low cost
asynchronous serial communication. It has
two channels and a full modem control
interface.

• The CTC (Counter/Timer Circuit) features
four programmable 8-bit counter/timers,

zao CPU
Registers

Figure 4 shows three groups of registers
within the Z80 CPU. The first group consists of
duplicate sets of 8-bit registers: a prinCipal set
and an alternate set (designated by , [prime],
e.g., A'). Both sets consist of the Accumulator Register, the Flag Register, and six
general-purpose registers. Transfer of data
between these duplicate sets of registers is
accomplished by use of "Exchange" instructions. The result is faster response to interrupts
and easy, efficient implementation of such versatile programming techniques as background-

foreground data processing. The second set of
registers consists of six registers with assigned
functjons. These are the I (Interrupt Register),
the R (Refresh Register), the IX and IY (Index
Registers), the SP (Stack Pointer), and the PC
(Program Counter). The third group consists of
two interrupt status flip-flops, plus an additional pair of flip-flops which assists in identifying the interrupt mode at any particular
time. Table I provides further information on
these registers.

ALTERNATE REGISTER SET

MAIN REGISTER SET

ACCUMULATOR

F

FLAG REGISTER

A'

ACCUMULATOR

F'

FLAG REGISTER

B GENERAL PURPOSE

C

GENERAL PURPOSE

B'

GENERAL PURPOSE

C'

GENERAL PURPOSE

D GENERAL PURPOSE

E GENERAL PURPOSE

D'

GENERAL PURPOSE

E' GENERAL PURPOSE

H

L

GENERAL PURPOSE

H'

GENERAL PURPOSE

L'

A

GENERAL PURPOSE

GENERAL PURPOSE

4 - - - 8 BITS - - . .

..._-------168IT5-------_

INTERRUPT FLlp·FLOPS

G

IX INDEX REGISTER

G

~~ :
4

IV INDEX REGISTER

STATUS

INTERRUPTS DISABLED

STORES IFF1

INTERRUPTS ENABLED

DURING NMI
SERVICE

5P STACK POINTER
INTERRUPT MODE FLIP-FLOPS
PC PROGRAM COUNTER

I INTERRUPT VECTOR

I

IMFa

R MEMORY REFRESH

....--8BITS~

IMFb

INTERRUPT MODE 0
NOT USED
INTERRUPT MODE 1
INTERRUPT MODE 2

Figure 4. CPU Registers

2001·0213

7

Z80 CPU
Registers
(Continued)

Register

Size (Bits)

Remarks

A,A'

Accumulator

8

Stores an operand or the results of an operation.

F, F'

Flags

8

See Instruchon Set.

B, B'

General Purpose

8

Can be used separately or as a 16-blt regIster wIth C.

C, C'

General Purpose

8

See B, above.

D,D'

General Purpose

8

Can be used separately or as a 16-blt regIster WIth E.

E, E'

General Purpose

8

See D, above.

H,H'

General Purpose

8

Can be used separately or as a 16-blt regIster wIth L.

L, L'

General Purpose

8

See H, above.
Note: The (B,C), (D,E),
B - HIgh byte C D - HIgh byte E H - HIgh byte L -

and (H,L) sets are combined as follows:
Low byte
Low byte
Low byte

Interrupt RegIster

8

Stores upper eIght bIts of memory address for vectored interrupt

Refresh RegIster

8

ProvIdes user-transparent dynamIc memory refresh. AutomatIcally

processing.

R

Incremented and placed on the address bus during each
Instruchon fetch cycle.
IX

Index RegIster

16

Used for Indexed addressing.

IY

Index RegIster

16

Same as IX, above.

SP

Stack POinter

16

Holds address of the top of the stack. See Push or Pop In Instruchan set.

PC

Program Counter

16

IFF1-IFF2

Interrupt Enable

Fhp-Flops

Set or reset to Indicate Interrupt status (see FIgure 4).

IMFa-IMFb

Interrupt Mode

Fhp-Flops

Reflect Interrupt mode (see Figure 4).

Holds address of next instruchon.

Table I. ZaD CPU Registers

Interrupts:
General
Operation

The CPU accepts two interrupt input signals:
NMI and INT. The NMI is a non-maskable
interrupt and has the highest priority. INT is a
lower priority interrupt and it requires that
interrupts be enabled in software in order to
operate. INT can be connected to multiple
peripheral devices in a wired-OR configuration.
The Z80 has a single response mode for
interrupt service for the non-maskable interrupt. The maskable interrupt, INT, has three
programmable response modes available.
These are:
• Mode 0 - compatible with the 8080 microprocessor.

8

• Mode I - Peripheral Interrupt service, for
use with non-8080/Z80 systems.
• Mode 2 - a vectored interrupt scheme,
usually daisy-chained, for use with Z80
Family and compatible peripheral devices.
The CPU services interrupts by sampling the
NMI and INT signals at the rising edge of the
last clock of an instruction. Further interrupt
service processing depends upon the type of
interrupt that was detected. Details on interrupt responses are shown in the CPU Timing
Section.

Interrupts:
General
Operation
(Continued)

Non-Maskable Interrupt (NMI). The nonmaskable interrupt cannot be dIsabled by program control and therefore will be accepted at
all times by the CPU. NMI is usually
reserved for servICing only the highest priority
type interrupts, such as that for orderly shutdown after power failure has been detected.
After recognition of the NMI signal (providing
BUSREQ is not active), the CPU Jumps to
restart location 0066H. Normally, software
starting at this address contains the interrupt
service routing.
Maskable Interrupt (lNT). Regardless of the
interrupt mode set by the user, the 280
response to a maskable interrupt input follows
a common timing cycle. After the interrupt has
been detected by the CPU (provided that
interrupts are enabled and BUSREQ is not
active) a special interrupt processing cycle
begins. This is a special fetch (MI) cycle in
which IORQ becomes active rather than
MREQ, as in normal MI cycle. In addition, this
special MI cycle is automatically extended by
two WAIT states, to allow for the time required
to acknowledge the interrupt request.
Mode 0 Interrupt Operation. This mode IS
compatible with the 8080 microprocessor interrupt service procedures. The interrupting
device places an instruction on the data bus.
This is normally a Restart Instruction, which
wIll initiate a call to the selected one of eight
restart locations in page zero of memory.
Mode I Interrupt Operation. Mode I operation is very similar to that for the NMI. The
principal difference IS that the Mode I interrupt has a restart location of 0038H only.
Mode 2 Interrupt Operation. This interrupt
mode has been designed to utilize most effectively the capabilities of the Z80 microprocessor and its associated peripheral family. The
interrupting peripheral device selects the
starting address of the interrupt service
routine. It does this by placing an 8-bit vector
on the data bus during the interrupt acknowledge cycle. The CPU forms a pointer using
this byte as the lower 8-bits and the contents of
the I register as the upper 8-bits. This points to
an entry in a table of addresses for interrupt
service routines. The CPU then jumps to the
routine at that address. This flexibility in
selecting the interrupt service routine address
allows the peripheral device to use several different types of service routines. These routines

may be located at any available location in
memory. Since the Interrupting device supplies the low-order byte of the 2-byte vector,
bit 0 (Ao) must be a zero.

Interrupt Priority (Daisy Chaining and
Nested Interrupts). The interrupt priority of
each peripheral device is determined by its
physical location within a daisy-chain configuration. Each device in the chain has an interrupt enable Input line (lEI) and an interrupt
enable output line (lEO), which is fed to the
next lower priority device. The first deVIce in
the daisy chain has its lEI input hardwired to a
High level. The first device has highest
priority, while each succeeding device has a
corresponding lower priority. This arrangement permits the CPU to select the highest
priority interrupt from several simultaneously
interrupting peripherals.
The interrupting device disables its lEO line
to the next lower priority peripheral until it has
been serviced. After servicing, its lEO line is
raIsed, allowing lower priority peripherals to
demand interrupt servicing.
The Z80 CPU will nest (queue) any pending
interrupts or interrupts received while a
selected peripheral is being serviced.
Interrupt Enable/Disable Operation. Two
flip-flops, IFF) and IFF2, referred to in the
register description are used to signal the CPU
interrupt status. Operation of the two flip-flops
is described in Table 2. For more details, refer
to the ZaD CPU Technical Manual and ZaD
Assembly Language Manual.
Action
CPU Reset

Dr

IFFZ

Comments

0

0

Maskable interrupt
INT disabled

0

0

Maskable mterrupt
INT disabled

IFFl

instructlon
execuhon

EI instruction

Maskable mterrupt
!NT enabled

executIon

LD A,I mstruchon

IFF2 - Parity flag

execuhon

LD A,R instruction

IFF2 - Panty flag

execuhon

Accept NMI

RETN instruchon
execution

0

IFF2

IFFl

IFFl - IFF2
(Maskable mterrupt INT disabled)
IFF2 - IFFI at
completion of an

NMI servICe
routine.

Table 2. State of Flip-Flops

9

Instruction
Set

o

The Z80 microprocessor has one of the most
powerful and versatile instruction sets
available In any 8-bit microprocessor. It
includes such unique operations as a block
move for fast, efficient data transfers within
memory or between memory and 1/0. It also
allows operations on any bit in any location in
memory.
The folloWing is a summary of the Z80
instruction set and shows the assembly
language mnemonic, the operation, the flag
status, and gives comments on each instruction. The Z80 CPU Technical Manual
(03-0029-01) and Assembly Language
Programming Manual (03-0002-01) contain
significantly more details for programming
use.
The instructions are divided into the
following categories:

o
o
o

o
o

Mnemonic

Group

1D r, r'
LD r, n

r - r'

LD,. (HLI

, - (HLI

LD r, (IX+d)

r -

LD '. (IY +dl

Operation

H

S

P/V N

··
·
· · ·
X
X

X
X

X
X

X
X

, - (IY+dl

X

X

LD (HLI.'
LD (IX+d). ,

(HLI - ,
(IX+dl - ,

x
x

x
x

LD (IY +dl. ,

(IY+dl - ,

x

x

LD (HL). n

(HL) - n

X

X

LD (IX+d). n

(IX+d) - n

X

X

LD (IY +d), n

(IY+d)-n

· ·

X

(IX+d)

Relative
Extended

Register indirect

C

Bit

Opccd.
No.of No.of M No.of T
76 543 210 Ho. By... Cycl.. Stat..

, ,
,
,
,

X
X
X

X
X
X

X
X
X

X
X
X

-n00 000 010
00 010 010
00 110 010

X

·
· ·
·· ·

A - (BC)
A - (DEI
A - (nn)

LD (BC). A
LD (DEI. A
LD (nnl. A

(BC) - A
(DEI - A

LDA. I

A- I

X

LDA. R

A-R

X

LD I. A

1- A

X

X

LDR. A

R-A

X

X

'.

Register

01
110
00
-n01
110
II Oll 101
01
101
-dII III 101
01
110
-d01 110
II 011 101
01 110
-dII III 101
01 110
-d00 110 110
-nII Oll 101
00 110 110
-d-n11 III 101
00 110 110
-d-n00 001 010
00 Oll 010
00 III 010

LDA. (BCI
LDA. (DE)
LDA. (nn)

A

o

Flags

Symbolic

Load

10

Modified page zero

o Implied

General-purpose arithmetic and CPU
control

NOTES

Immediate extended

o Indexed

8-bit arithmetic and logic operations

(nn) -

Calls, returns, and restarts

o Immediate

o
o
o
o

16-bit loads

8-Bit

Jumps

A variety of addressing modes are
implemented to permit efficient and fast data
transfer between various registers, memory
locations, and input/output devices. These
addressing modes include:

o Exchanges, block transfers, and searches

o
o

Bit set, reset, and test operations

o Input and output operations

o 8-bit loads

o

16-bit arithmetic operations

o Rotates and shifts

r, r' means any of Ihe reglsters A, E, C, D, E, H, L
IFF the content of the mterrupt enable flip-flop, (IFF)
copied mto the PIV flag
For an explanahon of flag notahon and symbols for
mnemOniC tables, see Symbolic Notahon sechon
followmg tables

,

··

·

·

X IFF

0

X IFF

·

,
,
,

II
01
II
01
11
01
11
01

101
010
101
011
101
000
101
001

101
III
101
III
101
III
101
111

7

DD

19

FD

19

DD

19

FD

19

Commentl

~
000
B
001
C
010
D
Oll
E
100
H
101
L
III
A

7

36

10

DD
36

19

FD

19

36
OA
lA
3A

13

02
12
32

13

7
7

7
7

ED
57
ED

SF
ED
47
ED
4F

IS

2001·001

16-Bit Load
Group

Symbolic
OporatloD

Mumomc
LD dd. nn

dd - nn

LO IX, nn

IX - nn

LD IY, nn

IY - nn

LD HL, (nn)

H-(nn+l)

L - (nn)

LD dd, (nn)

ddH - (nn+ 1)
ddL - (nn)

LD IX, (nn)

!XH - (nn+ 1)
IXL - (nn)

LDIY, (nn)

IYH - (nn+ 1)
IYL - (nn)

LD (nn), HL

(nn+1) - H
(nn) - L

LD(nn), dd

(nn+ 1) - ddH
(nn) - ddL

LD (nn), IX

(nn+l) - IXH
(nn) - !XL

LD (nn), IY

(nn+ 1) - IYH
(nn) -

IYL

LD SP, HL
LD SP, IX

SP - HL
SP - IX

LD SP, IY

SP -IY

PUSH qq

(SP-2) - qqL
(SP-l) - qqH
SP-SP-2
(SP-2) - IXL
(SP-l) - IXH
SP-SP-2
(SP-2) - IYL
(SP-l) - IYH
SP-SP-2
qqH - (SP+ 1)
qqL - (SP)
SP-SP+2
IXH - (SP+ 1)
IXL - (SP)
SP - SP +2
IYH - (SP+l)
IYL - (SP)
SP-SP+2

PUSH IX
PUSH IY
POPqq
POP IX
POPIY

NOTES

dd

IS

S

Flu",
H
PIV N

Z

·
·
·
·
·
·
·
·
·
·
·
··
·
·
·
·
·
·
·

X
X

X

X
X

X

X

X
X

X

X

X
X
X
X
X
X
X
X
X

· ·
· ·
· ·
· ·
· ·
· ·
· ·
· ·
·
· ·
· ·
·· ··
· ·
· ·
·
· ·
· ·
· ·
· ·

C

Opcodo
No.of No.oI M No.oI T
78 543 210 Ho. Byt.. Cye'" StClt..

X

00 ddO 001

X

-n11 011 101 DD
00 100 001 21

14

X

-n11 111 101 FD
00 100 001 21

14

3

-n00 101 010 2A

X

3

10

X

20

X

-n11 011 101 DD
00 101 010 2A

20

11 111 101 FD
00 101 010 2A
-n00 100 010 22

X

20

X

-n11 011 101 DD
00 100 010 22

20

X

-n11 III 101 FD
00 100 010 22

20

X
X

III
011
111
III
III
qqO

001
101
001
101
001
101

F9
DD
F9
FD
F9

Il

16

X

11
11
11
11
11
11

DE
HL
SP

20

-n11 101 101 ED
01 ddO 011

X
X

Pair

01
10
11

oo-BC

16

-n11 101 101 ED
01 ddl 011

X

CommoDIa

dd

@J

Q
a

6
10
10
11

X

!l 011 101 DD
11 100 101 E5

15

X

11 III 101 FD
11 100 101 E5

15

X

11 qqO 001

10

X

11 011 101 DD
11 100 001 El

14

X

11 III 101 FD
11 100 001 El

14

~
00
BC
01
DE
10
HL
11
AF

any of the reg:1sler pairs BC, DE, HL, SP.

qq LS any of the register pdlfS AF, BC, DE, HL
{PAIRlH. (PAIR}L refer to high order and low order 61ght bits of the register p<:1.1r respectively,

e,g , BCL

Exchange.
Block
Transfer.
Block Search
Groups

EX DE, HL
EXAF, AF'
EXX
EX (SP), HL
EX (SP), IX
EX (SP), IY

= C, AFH = A

DE - HL
AF - AF'
BC - BC'
DE - DE'
HL - HL'
H - (SP+l)
L - (SP)
IXH - (SP+l)
!XL - (SP)
lYH - (SP+l)
IYL - (SP)

LDI

(DE) - (HL)
DE - DE+l
HL-HL+l
BC-BC-l

LDIR

(DE) - (HL)
DE - DE+l
HL-HL+l
BC - BC-l

··
·
·
·
·
·

·

X
X
X
X
X

X

···
·
·

X
X
X
X
X

··
·
·
·

11 101 011 EB
00 001 000 08
11 011 001 D9

auxiliary register
bank exchange

· ·
X

CD

X

Regtster bank and

X

11 100 011 E3

19

11
11
11
11

DD
E3
FD
E3

23

11 101 101 ED
10 100 000 AD

16

Load (HL) Into
(DE), Increment
the pOinters and

11 101 101 ED
10 110 000 BO

21
16

IfBC .. 0
IfBC =0

011
100
III
100

101
011
101
011

23

decrement the byte
counter (BC)

X

0

X

0

0

Repeat unhl

BC = 0
NOTE

2001·001

 Z flag IS 1 If A :: (HL), othel'WlBe Z ::: 0

8-Bit
Arithmetic
and Logical
Group

ADDA,r

A_A+r

X

X

V

ADD A, n

A-A+n

X

X

V

ADD A, (HL)
A-A+(HL)
ADD A, (IX+d) A - A + (IX+d)

X
X

X
X

V
V

ADD A, (IY +d) A - A + (IY +d)

X

X

V

W~ r
lll@llO
10 (QQQ] llO
II Oll 101
10 IQQl!lllO

-d-rnQl] -

II III 101
WI@110
d

0

~

7

DD

19

FD

19

ADCA,'

A ..... A+s+CY

X

X

V

SUBs

A-A-,

X

X

v

IQiQI

SBCA, s

A - A-s-CY

X

X

V

[Qj]

AND,

A-AAs
A-Avs

X

X

P

[@

X

X

P

IIiQJ

X

X

P

IlIDJ

CPs

A-A. s
A-,

X

X

V

INCr

r-r + 1

X

X

V

00 r

INC (HL)
INC (lX+d)

(HL) -(HL) + 1
(IX+d) (IX+d)+l

X
X

X
X

V
V

INC (IY +d)

(IY+d) (IY+d)+l

X

X

V

0

00 llO IImI
II 011 101 DD
00 llO I!]!lJ
d
II III 101 FD
00 llOm
d

DECm

m-m-l

X

X

V

1

OR,
XORs

000
001
010
Oll
100
101
III

B
C
D
E
H
L
A

any of r, n,
(HL). (IX + d).
(lY + d) as shown
for ADD 1nstruchon.
The Indicated bIts

SIS

replace the EiQQlm

the ADD set above

(iIi]

.

l!QID

- -

1m!

II
Zl

Zl

m

IS

any of r, (HL),

(IX+d). (lY +d)
as shown for INC
DEC SlIme format
and states as INC
Replace IiQQJ wdh

!im]m opcode

12

2001-001

GeneralPurpose
Arithmetic
and
CPU Control
Groups

OperaUon

Opcod.e

Flag.

Symbolic
Mnemonic

H

S

P!V N

76 5t3 ZID lie.

No.of No.of M No.of T
Cycles Stat••

Comments

Bytes

X

X

00 100 III 27

DeCimal adjust
accumulator.

X

X

00 101 III 2F

Complement
accumulator (one's
complement) .

II 101 101 ED
01 000 100 44
00 III III 3F

Negate acc, (two's

00 110 III
00 000 000
01 110 110
II 1l001l
II 111 Oll
II 101 101
01000 110
II 101 101
01 010 110
11 101 101
01 Oll 110

Set carry flag

DAA

Converts ace content
mto packed BCD
following add or
subtract With packed
BCD operands

CPL

A-A

NEG

A-O-A

X

CCF

CY - CY

X

SCF
NOP
HALT
DI
EI
IMO

CY - 1

X
X
X
X
X
X

X
X
X
X
X
X

X

X

X

X

·

C

X
X

V

X

complement) .
Complement carry
flag,

No operahon
CPU halted

*
*

IFF - 0
IFF - 1
Set mterrupt
mode 0

IMI

Set Interrupt

1M2

Set Interrupt

mode 1
mode 2
NOTES

··
··
·
··
·
. ·
·
·

37
00
76
F3
FB
ED
46
ED
56
ED
5E

IFF mdlccltes the mlerrupt enable fhp-flop
CY indicates the carry flip-flop.
mdlcates mterrupts are not sampled at the end of EI or DI

i

*

IS·Bit
Arithmetic
Group

ADD HL, ss

HL - HL+ss

X

X

X

ADC HL, ss

HL - HL+ss+CY

X

X

X

V

@)

II

II 101 101 ED

15

01 ssl OlD
SBC HL,

55

ADD IX, pp

ADD IY, rr

INC IX

IX-IX+pp

lY - IY + rr

INC lY

IY - IY + 1

DECss

ss - 55-1

DEC IX

IX - IX-l

DEC IY

IY - IY-l

NOTES

X

X

X

·

X

X

X

·

X

HL - HL-ss-CY

ss - ss + 1
IX .... IX + 1

INC ss

Rotate and
Shift Group

·

00 ssl 001

X

X
X

X

V

II 101 101 ED

15

·
·

01 ssO 010
11 011 101 DD
01 ppl 001

15

II III 101 FD

15

X
X

·
·
.
· ·
X

X

X
X

X
X

X

X

00 rrl 001

00 ssO

all

11
00
II
00

Oil
100
III
100

101
Oil
101
011

00 ssl

all

11
00
II
00

101
Oll
101
Oil

011
101
III
101

RLA

@J~J

l@j~

·
·

Reg.

BC
DE
IX
SP

rr

Reg.

00
01
10
II

BC
DE
IY
SP

6
10
10
6
10
10

X

0

X

00 000 III

07

Rotate left cIrcular
accumulator

X

0

X

00 010 III

17

Rotate left
accumulator

0

X

00001 III

OF

Rotate nght circular
accumulator

00011 III

IF

Rotate nght
accumulator

11 001 011
00 IQQQJ '
11 001 011
00 I2QiiJ 110

CB

Rotate left Circular
register r

CB

15

II Oil 101
11 001 011
d
00 I§QQJ 110

DD
CB

23

FD

23

RRCA

L~@J

X

RRA

~@}l

X

)(

RLCr

X

0

X

RLC (HL)

X

0

X

X

0

X

RLC (lX+d)

@J~J

·
·
P

dHL),(IX+d).(IY +d)

RLC (IY +d)

- -

X

0

X

P

11 III 101
11 001 011
d
00 I§QQJ 110

-

-

l@j~

X

0

X

P

IQ@]

m.',(HL),(IX+d).(lY +d)
RRCm

DD
2B
FD
2B

pp

00
01
10
II

5S IS any of the register pcllrs Be, DE, HL, SP
pp IS any of the regIster pairs Be, DE, IX, SF
rr IS any of the register pcllrS BC, DE, IY SP

RLCA

RL m

DD
23
FD
23

Q
c:I

~
00 BC
01 DE
10 HL
11 SP

LEbl@J
m-',(HL)'(!X+d),(lY +d)

X

X

@I]

~
000
B
001
C
010
D
011
E
100
H
101
L
III
A

CB
Instrucbon format
and states are as
shown for RLC's
To form new
opcode replace

I§QQJ

0'

RLC's

With shown code

13

2001-001
.-._---

~-

-

Rotate and
Shift Group

Flags
H
P/V N

Symbolic
Mnemonic

S

Operation

(Continued)

LEfJ=@jJ

RRm

C

Opcode
78 543 210

X

X

IQj]

X

X

[@

No.of No.of M No.of T
Cycles Stat..

He. Byte.

Comments

mar,(HL),(lX +d),(IY +d)

@]~o

SLA m

mEr,(HL),(IX +d),(IY +d)

~@]

SRA m

X

0

X

P

[iQj]

X

0

X

P

Iilll

x

P

0

11 101 101
01 101 III

ED
6F

18

X

P

0

11 101 101
01 100 III

ED
67

18

m.r,(HL),(IX+d)'(!Y +d)
SRLm

o~@]
m.r,(HL)'(!X+d),(lY +d)

RLD

C8$

I7jdi- OI

A

(HL)

17-413>1

I/-~ol

A

(Hl)

RRD

Bit Set. Reset
and Test
Group

I

x

I

X

0

Z - rb

x

x

x

X

BIT b, (HL)

Z - (HL)b

X

X

X

X

X

X

X

X

0

11
01
11
01
11
11

001
b
001
b
011
001
d
01 b

011
r
011
110
101
011

X

X

X

X

0

12

DD
CB

20

11 III 101 FD
11 001 011 CB
d
01 b 110

20

110

- -

SET h, r

rb - 1

0

X

0

X

0

SET b, (HL)

(HL)b - 1

0

X

0

X

0

SET b, (IX + d)

(IX+d)b- 1

0

X

0

X

0

11 001
b
11 001
[jJ b
11 011
11 001
d
[!] b
11 III
11 001
d
b

IS

~

CB
CB

- -

BIT b, (lY +d)b Z - (IY +d)b

upper half of

the accumulator
unaffected

BITb, r

BIT b, (IX+d)b Z - (IX+d)b

Rotate digit left and
right between
the accumulator
and location (HL)
The content of the

001
010
011
100
101
111
b
000
001
010
011
100
101
110
111

C
D
E
H
L
A
Bit Tested
0
1
2
3
4
5
6
7

011 CB

[jJ

011 CB
110
101 DD
011 CB

15
23

- -

SET b, (IY +d)

(IY+d)b - 1

0

X

0

X

0

-

RES h, m

0

mb - 0

x

0

I!lJ
l!l!

x

m - f, (HL),
(lX+d),
(IY+d)

NOTES

Jump
Group

IP nn

110
101 FD
011 CB

23

110

To form new
opcode replace
[jJ of SET b, s

rn

With
Flags
and bme states for
SET Instruchon.

The notahon mb indicates bit b (0 to 7) or location m

PC - nn

0

X

0

X

0

11 000 011 C3

lD

- -

11 cc OlD

10

00
00
-

12

cc

n

IP ee, nn

If condition cc

IS

0

X

0

X

X

0

X

0

true PC - nn,

otherwise
conhnue

IR e

PC - PC+e

JR C, e

0

IP (HL)

IIC ~ 0,
contInue
IIC ~ 1,
PC - PC+e
IIC ~ 1,
contmue
IIC ~ 0,
PC - PC+e
II Z ~ 0
contmue
If Z ~ 1,
PC - PC+e
II Z ~ 1,
contInue
liZ ~ 0,
PC - PC+e
PC - HL

0

X

0

X

IP(IX)

PC - IX

0

X

0

X

IRNC, e

IP Z, e

IR NZ, e

14

0

0

0

X

X

X

X

X

0

0

0

X

X

X

0

0

0

0

011 000 18
e-2 111 000 38
9-2 -

000
001
OlD
011
100
lDl
110
III

Condition
NZ non-zero
Z zero
NC non-carry
C carry
PO panty odd
PE pardy even

P

sign positIve

M sIgn negabve

If conditIon not met.
12

If condltIon IS met.

12

If condltIon IS met.

12

If conchbon is met.

If condlbon not met.

00 110 000 30
- e-2 -

If condItion not met.

00 lDl 000 28
- e-2 -

If condItIon not met.

00 100 000 20
- e-2 12

If condlhon IS met.

11 lDl 001 E9
0

11 011 lDl DD
11 101 001 E9

2001-001

Jump Group
(Continued)

Flail"
@
H
PIV N C

Symbollc

S

Operation

Mne.ODic

lP(lY)
D1NZ, e

PC -IY

X

B - B-1

X

II B = 0,
conhnue

· ·
·
X

Opcodo
No.ol No.of M No.of T
76 543 210 Box Byte. eyel.. Stat..
11 III 101 FD
11 101 001 E9
00 010 000 10

X

II B • 0,

- e-2 13

liB" 0,
PC - PC+e
NOTES

e represents the extensIon
e

IS /II

In

Comments

If B" 0,

the rel",hve addressmg mode

Iligned two's complement number

In

the range

< -126, 129 >

e - 2 In the opcode prOVides "'n ef/ecltve <'\ddres9 of pc + e as PC IS mcremented
by 2 pnor 10 the addll10n of e

Call and
Return Group

CALL nn

CALL

CC,

· · ·
· ·

(SP-l) - PCH
(SP-2) - PCL
PC - nn
nn

If condlhon
cc IS false
contmue,

X

X

11 001 101 CD

17

X

X

11 cc 100

10

If cc

IS

false

17

If cc

IS

true

If co

IS

false.

If co

IS

true.

otherwIse same as
CALL nn

·

RET

PCL - (SP)
PCH - (SP+l)

X

X

RET co

If condlhon

X

· ·

co

IS

false

contmue,

11 001 001 C9

10

11 co 000

X

otherwIse

RET
RET!

Return from
mterrupt

RETNI

Return from
non-maskable
mterrupt

NOTE

Input and
Output Group

(SP-l)
(SP-2)
PCH PCL -

X

X

X

X

X

- PCH
- PCL
0

·

·

X

11
01
11
01

101
001
101
000

101
101
101
101

11

t

111

14

ED
4D
ED
45

14

101 PE parity even

110 P
111M
11

~OO
001
010
011
100
101
110
111

p

Sign pOSItive
SIgn negabve

bOH
OSH
10H
ISH
20H
28H
30H
38H

lRETN loads IFF2 - IFFl

A - (n)

X

X

11 011 011 DB

II

IN c, (C)

c - (C)
Ifr = llOonlythe
flags Will be affected

X

X

11 101 101 ED
01 c 000

12

lNl

(HL) - (C)
B - B-1
HL-HL+l
(HL) - (C)
B - B-1
HL-HL+l
Repeat until
B = 0

X

16

C to AO - A7
BtoAB- A15

21

C to AO - A7
B to AS - A15

X

lNIR

OUT (n), A

(C) - c

OUTl

(C) - (HL)
B - B-1
HL-HL+l
(C) - (HL)
B - 8-1
HL-HL+l
Repeat until
8 = 0

X

(C) - (HL)
B - B-1
HL-HL-l

X

OTlR

OUID

CD II the result 01 B-1
@ N Flag

t

X

X

X

X

X

11 101 101 ED
10 100 010 A2

X

X

X

X

X

11 101 101 ED
10 110010 B2

CDt

X

X

X

X

X

X

11 101 101 ED
10 101 010 AA

X

X

X

X

X

11 101 101 ED
10 III 010 BA

X

·

X

16

5
(lf B"O)

4
(If B=O)

OUT (C), c

INDR

CD

X

(HL) - (C)
B - B-1
HL-HL-l
(HL) - (C)
B - B-1
HL - HL-l
Repeat until
B = 0
(n) - A

lND

2001-001

·
·

Condlhon
000 NZ non·zero
001 Z zero
010 Ne non-carry
011 C carry
100 PO parity odd

IN A, (n)

NOTE

S

cc

same as

RST p

I

@

11

CDt

X

CDt

X

X

X

X

X

X

X

X

16

16

C to AO - A7
BtoAS - A15

21

C to AO - A7
BtoAg - A15

16

X

11 010 011 D3

11

·

X

11 101 101 ED
01 c 001

12

X

X

11 101 101 ED
10 100 011 A3

16

C to AO - A7
B to AS - Al5

X

X

11 101 101 ED
10 110011 B3

5

21

(If B"O)
4
(If B=O)

C to AO - A7
BtoAS - Al5

16

X
X

5
Of B"OI
4
(lf B=O)

n to Ar; - A7
Ace hAa - A15
C to AO - A7
BtoAs-A15

X

X

11 101 101 ED
10 101 011 AB

16

n to AO - A7
Acc to AS - A15
C to AO - A7
B to Ag - A15

C to AO - A7
B to AS - A15

zero the Z flag IS set, otherWIse It IS reset

IS 1 If data bit IS I, otheWISe N Flag IS 0

15

Input and
Output Group

Mnemonic

(Continued)

OTDR

Summary of
Flag
Operation

Symbolic

x

(C) - (HL)
B - B-1
HL - HL-I
Repeat unhl
B ~ 0

ADD A, 5, ADC A, s
SUB S, SEC A, s, CP

X
X
X
X

NEG

ANDs
INCg
DEC s
ADD DD, ss

ADC HL, S8
SEC HL, S8
RLA, RLGA, RRA, RRCA
RL m, RLC m, RR m,
RRC m, SLA m,
SRA rn, SRL m
RLD, RRD
DAA
CPL
SCF
CCF
IN, (C)
INI, IND, OUT!, OUTD
INIR, INDR, OTlR, OTDR
LDI, LDD
LDIR, LDDR
CPI, CPIR, CPD, CPDR
LDA, I, LDA, R
BIT b, s

Symbol
S
Z
P/V

H

N
H&N

C

16

, ,,

X
X
X
X

X

,

X

PlY N

H
X

S,

Opcod.

No.of No.of M No.of T
Cycles State.

C

76 543 210 Hex Bytes

X

II 101 101 ED
10 III Oil

5
(If B"O)
4
(If

OR s, XOR s

Symbolic
Notation

x x x x

0.,
S

Instruction

Flags
H
PlY N

Z

Operation

I

X
X

,

,,

I
0

X

,,

X
X
X

X
X
X

X

X

0
0

X

0

X
X
X
X
X
X

X
X
X
X

,

I
0

X

°
X
X

0

°
X

X
X

Operation

X
X
X
X
X
X
X
X
X

V
V
P
P

V
V
V
V

X

X

0
I
0

°

0
I
0
0
I
0

Do
C

,,

n

°
P
X

,
,

X
0

X

IFF

X

X

Comments
eta Ao - A7
B to As - AlS

16

B~O)

Comments

a-bit add or add with carry
8-bi! subtract, subtract with carry, compare and negate accumulator
Logical operahons

8-hlt Increment
B-bit decrement.
16-blt add
16-bl\ add with carry
16-bll subtrae! with carry
Rotate accumulator
Rotate and shift locatJons

X

X
X
X
X
X
X
X
X
X
X

21

:}
:}

Rotate digit left and Tight
Decimal adjust accumulator
Complement accumulator
Set carry
Complement carry
Input regIster mdlfect
Block mput and output Z "'" 0 If B

'* 0 otherWIse Z = a
Be '* 0, otherWIse P/V = a

Block transfer mstructlOns P/V "" 1 If

Block search mstructions Z = 1 If A = (HL), otherWIse Z = 0 P/V = 1
If Be '#J 0, otherWIse P/V = a
The content of the mterrupt enable fhp-£lop (IFF) IS copled mto the P/V flag
The state of bit b of location s IS copled mto the Z flag

S,gn flag. S = I If the MSB of the result IS L
Zero flag, Z = I If the result of the operation 's O.
Partty or overflow flag. Partty (P) and overflow
(V) share the same flag, LogIcal operatIOns affect
th,s flag wIth the partty of the result whIle
artthmet,c operatlOns affect th,s flag w,th the
overflow of the result. If PlY holds partty, PlY
I ,f the result of the operatlOn 's even, PlY = 0 If
result IS odd. If P/V holds overflow, PlY '" I 'f
the result of the operatIon produced an overflow.
Half-carry flag. H = I if the add or subtract
operahon produced a carry mto or borrow from
b,t 4 of the accumulator.
Add/Subtract flag, N = I If the prevIous operahon was a subtract.
Hand N flags are used 10 coni unction wIth the
deCImal adlust mstructlon (DAA) to properly correct the result mto packed BCD format followmg
addItIon or subtractIon usmg operands wIth
packed BCD format.
Carry/Link flag, C = I If the opera\ton produced
a carry from the MSB of the operand or result.

Symbol
I

0
I
X
V
P

ss
11

R
n
nn

Operation
The flag IS affected according to the result of the
operatIon.
The flag IS unchanged by the operation,
The flag IS reset by the operation.
The flag 's set by the operation.
The flag IS a "don't care"
P/V flag affected according to the overflow result
of the operation.
PlY flag affected according to the partty result of
the operatIon.
Anyone of the CPU regIsters A, B, C, D, E, H, L.
Any S-b,t location for all the addressmg modes
allowed for the parhcular Instruchon.
Any 16-blt location for all the addressmg modes
allowed for that mstructlon,
Anyone of the two index reg,sters IX or IY.
Refresh counter.
S-bit value 10 range < 0, 255 >.
16-b,t value 10 range < 0, 65535 >,

2001-001

Pin
Descriptions

Ao-A1S. Address Bus (output, active High,
3-state). Ao-AJ5 form a 16-bit address bus. The
Address Bus provides the address for memory
data bus exchanges (up to 64K bytes) and for
1/0 device exchanges.

BUSACK. Bus Acknowledge (output, active
Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus,
data bus. and control signals MREQ, IORQ,
RD, and WR have entered their highimpedance states. The external circuitry
can now control these lines.

BUSREQ. Bus Request (input, active Low).
Bus Request has a higher priority than NMI
and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU
address bus, data bus, and control signals
MREQ, IORQ, RD, and WR to go to a highimpedance state so that other devices can
control these lines. BUSREQ is normally wireORed and requires an external pullup for
these applications. Extended BUSREQ
periods due to extensive DMA operations can
prevent the CPU from properly refreshing
dynamic RAMs.

00-07. Data Bus (input/output, active High,
3-state). Do-D7 constitute an 8-bit bidirectional
data bus, used for data exchanges with
memory and I/O.

HALT. Halt State (output, active Low). HALT
indICates that the CPU has executed a Halt
instruction and is awaiting either a nonmaskable or a maskable interrupt (with the
mask enabled) before op,eration can resume.
While halted, the CPU executes NOPs to
maintain memory refresh.

INT. Interrupt Request (input, active Low).

MI. Machine Cycle One (output, active Low).
Ml, together with MREQ, indicates that the
"'turrent machine cycle is the opcode fetch
cycle of an instruction execution. Ml, together
with IORQ, indicates an interrupt acknowledge
cycle.

MREQ. Memory Request (output, active
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory write operation.

NMI. Non-Maskable Interrupt (input, negative
edge-triggered). NMI has a higher priority
than INT. NMI is always recognized at the end
of the current instruction, independent of the
status of the interrupt enable flip-flop, and
automatically forces the CPU to restart at location 0066H.

RD. Read (output, active Low, 3-state). RD
indicates that the CPU wants to read data from
memory or an 1/0 device. The addressed 1/0
device or memory should use this signal to
gate data onto the CPU data bus.

RESET. Reset (input, active Low). RESET
initializes the CPU as follows: it resets the
interrupt enable flip-flop, clears the PC and
Registers I and R, and sets the interrupt status
to Mode O. During reset time, the address and
data bus go to a high-impedance state, and all
control output signals go to the inactive state.
Note that RESET must be active for a minimum
of three full clock cycles before the reset
operation is complete.

RFSH. Refresh (output, active Low). RFSH,
together with MREQ, indicates that the lower
seven bits of the system's address bus can be
used as a refresh address to the system's
dynamic memories.

Interrupt Request is generated by I/O devices.
The CPU honors a request at the end of the
current instruction if the internal softwarecontrolled interrupt enable flip-flop (IFF) is
enabled. INT is normally wire-ORed and
requires an external pullup for these
applications.

WAIT. Wait (input, active Low). WAIT

IORQ. Input/Output Request (output, active

WH. Write (output, active Low, 3-state). WR

Low, 3-state). IORQ indicates that the lower
half of the address bus holds a valid 1/0
address for an I/O read or write operation.
IORQ is also generated concurrently with Ml
during an interrupt acknowledge cycle to indicate that an interrupt response vector can be
placed on the data bus.

indicates to the CPU that the addressed memory or 1/0 devices are not ready for a data
transfer. The CPU continues to enter aWait
state as long as this signal is active. Extended
WAIT periods can prevent the CPU from
refreshing dynamic memory properly.
indicates that the CPU data bus holds valid
data to be stored at the addressed memory or
I/O location.

17

CPU Timing

The Z80 CPU executes instructions by proceeding through a specific sequence of operations:
• Memory read or write
• I/O device read or write
• Interrupt acknowledge

The basic clock period is referred to as a
T time or cycle, and three or more T cycles
make up a machine cycle (Ml, M2 or M3 for
instance). Machine cycles can be extended
either by the CPU automatically inserting one
or more Wait states or by the insertion of one
or more Wait states by the user.

Instruction Opcode Fetch. The CPU places
the contents of the Program Counter (PC) on
the address bus at the start of the cycle (Figure
5). Approximately one-half clock ~le later,
MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the
CPU data bus.

The CPU samples the WAIT input with the
falling edge of clock state T2. During clock
states T3 and T4 of an Ml cycle dynamic RAM
refresh can occur while the CPU starts
decoding and executing the instruction. When
the Refresh Control signal becomes active,
refreshing of dynamic memory can take place.

Tw

T,

CLOCK

AO-AU

wm

__

+--J.~

__

~~~'~

__

~+-~+-J~

________+-__

~

--+---------~-'~~

«({ ~

NOTE: Tw-Walt cycle added when necessary for slow ancIlliary devlces.

Figure 5. Instruction Opcode Felch

18

2005·882

CPU
Timing

(Continued)

Memory Read or Write Cycles. Figure 6

MREQ also becomes active when the address
bus is stable. The WR line is active when the
data bus is stable, so that it can be used
directly as an R/W pulse to most semiconductor memories.

shows the timing of memory read or write
cycles other than an opcode fetch (Ml) cycle.
The MREQ and RD signals function exactly as
in the fetch cycle. In a memory write cycle,

T,

T,

T,

Tw

CLOCK

OPERA~~~:

1

iiii

Do-DT

/
;'

______-+__________,~~----~®~------.I~-+------

1

WR

OPER::.1J:

Do-D7

•

--------------1t========~~~D~AT~A~O~UT~==========::)
Figure 6. Memory Read or Write Cycle.

2005-883

19

CPU
Timing
(Continued)

Input or Output Cycles. Figure 7 shows the
timing for an 1/0 read or I/O write operation.
During I/O operations, the CPU automatically

inserts a single Wait state (Tw). This extra Wait
state allows sufficient time for an I/O port to
decode the address from the port address lines.

CLOCK

WAIT __+_--~---+----------~L-~_(J'-"

lIoj

••AII
elilEBATI811

WAI~~
OPERATION

j

WR

Do-D7

___________

(:::::::::::::::::~~::::~~~:::::::}
DATA OUT

NOTE: Tw· = One Walt cycle automatIcally mserted by CPU.

Figure 7. Input or Output Cycles

Interrupt Requestl Acknowledge Cycle. The
CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of
any instruction (Figure 8). When an interrupt
is accepted, a special Ml cycle is generated.
T,

TL

During this Ml cycle, IORQ becomes active
(instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. The CPU automatically adds two
Wait states to this cycle.
Tw'

Tw'

TW

-r__~------------~p~C--4_------~_()----~+_--H_-J\----

AO-A1S ____________

W&H ____________+-________________________-4__

NOTE: 1) TL = Last state of prevIOUS instructIon.

~~-'

2) Two Walt cycles automatIcally Inserted by CPU(*),

Figure 8. Interrupt Request/Acknowledge Cycle

20

2005·884. 885

CPU

Timing
(Continued)

Non-Maskable Interrupt Request Cycle.
NMI is sampled at the same time as the maskable interrupt input INT but has higher priority
and cannot be dlsabled under software control.
The subsequent timing is similar to that of a

normal instruction fetch except that data put
on the bus by the memory is ignored. The
CPU instead executes a restart (RST) operation
and jumps to the NMI service routine located
at address 0066H (Figure 9).

CLOCK

,I ® Ir---------t--+----

RIll - - - - - -

-+[l'-+__-.-.::::....__-+J~'-----+=RE;..FR.:.ES:...H+_---__+'

Ao-A15 _ _ _ _ _ _ _ _ _ _

NMI is an asynchronous mput, to ~antee ds bemg
recogmzed on the followmg machme cycle, NMI's fallmg edge

* Although

must occur no later than the rismg edge of the clock cycle
precedmg TLAST.

Figure 9. Non-Maskable Interrupt Request Operation

Bus Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the
last clock period of any machine cycle (Figure
10). If BUSREQ is active, the CPU sets its
address, data, and MREQ, 10RQ, RD, and WR

lines to a high-impedance state with the rising
edge of the next clock pulse. At that time, any
external device can take control of these lines,
usually to transfer data between memory and
1/0 devices.
T,

CLOCK

®RII'S"

______________-+J

-+_________________

HAU _ _ _ _ _ _ _ _ _ _

NOTE: TL = Lasl slale of any M cycle.

TX = An arbitrary clock cycle used by requesting deVIce.

Figure 10. Z-BUS Request! Acknowledge Cycle
2005·0218, 886

21

CPU
Timing
(Continued)

received. When in the Halt state, the HALT
output is active and remains so until an interrupt is received (Figure 11).

Halt Acknowledge Cycle. When the CPU
receives a Halt instruction, it executes NOP
states until either an INT or NMI input is
M1

•

~

I_

M1

~

~

•

~

~

I•

~

M1

~

CLOCK~

iiiLf==

~

~

Received

1......

t-?£_·____________

W-

MMI

NOTE. INT wIll also force a Halt eXIt.

.. See note, FIgure 9.

Figure 11. Halt Acknowledge Cycle

Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly
accept it. As long as RESET remains active, the
address and data buses float, and the control
outputs are inactive. Once RESET goes

inactive, three internal T cycles are consumed
before the CPU resumes normal processing
operation. RESET clears the PC register, so the
first opcode fetch will be to location 0000
(Figure 12).
_M1--- -

DO-D7

--

-@.I-I-----~~--------~----------~

..J!

FLOAT

,

-@-

iIl _ _ _ _ _ _ _ _ _

~~--------~~,_~_r,_---~
~:~;
JIIZI27
hl-'------------------~\::::~~~~~~

BU~

-

HALT

Figure 12. Reset Cycle

22

2005·887, 888

AC
Characteristics

zao CPU
Min Max

ZaOACPU
Min Max

ZaOB CPut
Min Max

165'

Parameter

Number Symbol

1

TcC

Clock Cycle TIme

400'

250'

2

TwCh

Clock Pulse Width (HIgh)

180'

110'

3

TwCl

Clock Pulse WIdth (Low)

180

4

TIC

Clock Fall TIme

30

30

20

5-TrC

Clock RIse Time

30

30

20-

6

TdCr(A)

Clock 1 to Address Valid Delay

7

TdA(MREQf)

Address Valid to MREQ
j Delay

8

TdCf(MREQf)

Clock

j

2000

145

to MREQ I Delay

65'
2000

2000

90
35'

100

85

100

85
110'

70
70
65'--

220'

135'

11

TwMREQl

MREQ Pulse Width (Low)

12

TdCf(MREQr)

Clock

j

to MREQ 1 Delay

100

85

70

13

TdCf(RDf)

Clock

j

to RD

Delay

130

95

80

14

TdCr(RDr)

Clock 1 to RD 1 Delay

100

j

360'

65

110
65'

125'

TdCr(MREQr) Clock 1 to MREQ 1 Delay
9
10-TwMREQh--MREQ Pulse Width (Hlgh)---170'

15 -TsD(Cr) ---Data Setup Time to Clock 1 - - - 5 0
16

ThD(RDr)

Data Hold TIme to RD 1

17

TsWA!T(Cf)

WAlT Setup Time to Clock

18

ThWA!T(Cf)

WAlT Hold Time after Clock I

19

TdCr(Mlf)

Clock 1 to Ml

0
j

30-0

70

70

70

85
35

0
60

0

0

0

Delay

130

100

80

20 -TdCr(Mlr) --Clock 1 to Ml 1 Delay

j

130

100

TdCr(RFSHf)

Clock 1 to RFSH I Delay

180

130

110

22

TdCr(RFSHr)

Clock 1 to RFSH 1 Delay

150

120

100

23

TdCf(RDr)

Clock

110

85

70

24

TdCr(RDf)

Clock 1 to RD

100

85

21

j

to RD 1 Delay
Delay

j

25-TsD(Cf) ---Data Setup to Clock j durmg--60
M2 , M3, ~ or Ms Cycles
TdA(lORQf)
320'
Address Stable prior to IORQ j
26

180'

Clock 1 to IORQ

Delay

90

75

28

TdCf(lORQr)

Clock I to IORQ 1 Delay

110

85

29

TdD(WRf)

Data Stable prior to WR
j

to WR

j

90
360'

TwWR

WR Pulse Width

32

TdCf(WRr)

Clock

33

TdD(WRf)

Data Stable prior to WR

34

TdCr(WRf)

Clock 1 to WR

to WR 1 Delay
j

Delay

36

TdCf(HALT)

Clock

37

TwNMI

NMI Pulse Width

38

TsBUSREQ(Cr) BUSREQ Setup Time to Clock 1

to HALT I or I

70135'
70

80
-55'
65

80
60'

120'

70

80

-10'

20'

65
25'

220'
100

j

35-TdWRr(D)--Data Stable from WR 1
j

80'

190'

Delay

31

j

j

70

110'

TdCr(IORQf)

j

80-

40

50

27

30 -TdCf(WRf) --Clock

*

110

300

60
30'--

300

260

80

80

70

80

50

50

For clock perIods other than the mimmums shown m the table,
calculate parameters usmg the expreSSlons In the table on the
followmg page.

r Umts In nanoseconds (ns)

All hmmgs are prelimmary and

subject to change.

23

II

@

Q
a

AC
Characteristics
(Contmued)

39
40 41
42
43

Z8D CPU
Min Max

Parameter

Number Symbol

ThBUSREQ(Cr) BUSREQ Hold TIme after Clock t
TdCr(BUSACKf) -Clock t to BUSACK j Delay
TdCf(BUSACKr) Clock j to BUSACK t Delay
TdCr(Dz)
Clock t to Data Float Delay
TdCr(CTz)
Clock t to Control Outputs Float
Delay (MREQ, lORQ, RD,
and WR)
TdCr(Az)
Clock t to Address Float Delay

a

53

a
90-

100
100
90
80

llO
90
110

Clock t to lORQ t Delay
Clock j to Data Valid Delay

TdCf(lORQr)
TdCf(D)

Z8DB cPut
Min Max

a
120

44
45-TdCTr(A)--MREQ t, lORQ t, RD t, and--160'
WR t to Address Hold TIme
46
TsRESET(Cr)
RESET. to Clock t Setup TIme
90
ThRESET(Cr)
RESET to Clock t Hold TIme
47
TslNTf(Cr)
48
lNT to Clock t Setup TIme
80
ThlNTr(Cr)
49
lNT to Clock t Hold Time
50 -TdMlf(lORQf)-MI j to lORQ j Delay
920'
TdCf(lORQf)
Clock j to lORQ j Delay
51
52

Z8DA CPU
Min Max

llO

90
80
70

90

80
35'--

80'
60

a

60

a

a

80

a

70

a

a
365'--

565'
110
100
230

85
85
150

70
70
130

• For clock penods other than the illlmmums shown In the table,
calculate parameters usmg the followmg expreSSlOns Calculated
values above assumed Ire::.;: TfC = 20 ns
t Umts m nanoseconds (ns) All bmmgs are prehmmary and
subject to change. All hmmgs assume equal loadmg on pms with

50 pF

Footnotes to AC Characteristics
Number Symbol

2

Z80

Z80A

Z80B

TcC

TwCh + TwCI + TrC + TIC

TwCh + TwCI + TrC +TfC

TwCh + TwCI + TrC + TfC

TwCh

Although stahc by deslgn,
TwCh of greater than 2001's

Although stahc by deslgn,
TwCh of greater than 200 1'8

Although stahc by deslgn,
TwCh of greater than 200 1'8

is not guaranteed

IS

not guaranteed

IS

not guaranteed

7 -TdA(MREQf)-TwCh + TfC - 75 ----TwCh + TIC - 65----TwCh + TIC - 5 0 - - - 10

TwMREQh

TwCh + TIC - 30

TwCh + TIC - 20

TwCh + TIC - 20

11

TwMREQI

TcC - 40

TcC - 30

TcC - 30

26

TdA(IORQf)

TcC - 80

TcC - 70

TcC - 55

29

TdD(WRf)

TcC - 210
TcC - 170
31-TwWR---TcC - 40 - - - - - - - T c C - 30
33

TdD(WRf)

TwCl + TrC - 180

TwCI + TrC - 140

TwCI + TrC - 140

35

TdWRr(D)

TwCl + TrC - 80

TwCI + TrC - 70

TwCI + TrC - 55

45

TdCTr(A)

TwCI + TrC - 40

TwCI + TrC - 50

TwCl + TrC - 50

50

TdMlf(IORQf) 2TcC + TwCh + TIC - 80

2TcC + TwCh + TfC - 65

2TcC + TwCh + TIC - 50

AC Test Condltions·
VIH = 20 V
VIL = 0.8 V

VIHC = VCC -0.6 V
VILC = 0.45 V

24

TcC - 140
TcC - 3 0 - - - - - - -

VOH=2.0V
VOL = 0.8 V
= ±0.5 V

FLOAT

Absolute
Maximum
Ratings

Standard
Test
Conditions

Storage Temperature ........ -65°C to + 150 °C
Temperature
under BIas ........ Specified operatmg range
Voltages on all mputs and
outputs with respect to ground. -0.3 V to + 7 V
Power DIssipation .................... 1.5 W
The characteristics below apply for the
following standard test condItions, unless
otherwise noted. All voltages are referenced to
GND (0 V). PosItive current flows into the
referenced pin. Available operating
temperature ranges are:

Stresses greater than those hsted under Absolute M8J
Incremented

· · ·
· · ·

(SP-I) - PCH
(SP-2) - PCL

PC

IS

Commeats

X

X

11 001 101 CD

17

X

X

11 cc 100

10

If cc

IS

false

17

If cc

IS

true

If cc

1S

false

otherwise sa.me as
CALL nn

RET

PCL - (SP)
PCH - (SP+ I)

RET cc

If conditlon
cc

IS

· · ·
X

X

11 001 001 C9

X

X

11 cc 000

10

11

RST p

X

X

(SP-l) - PCH
(SP-2) - PCL
PCH - 0
PCL - p

CC 15

true

@

· ·
· ·
X

X

11
01
11
01

101
001
101
000

101
101
101
101

11

I

III

ED
4D
ED
45

14
14

11

010
011
100
101
110
III

NC
C
PO
PE
P
M

9

non-carry
carry
parity odd
parity even

slgn poslhve
Slgn negahve

L....E......
000
001
010
011
100
101
110
111

OOH
OSH
IOH
ISH
20H
28H
30H
38H

IRETN loads IFF2 - IFF]

NOTE

Input and
Output Group

X

X

Return from
mterrupt
Return from
non-maskable
lOterrupt

RETNI

If

cc
Condition
000 NZ non-zero
001 Z ,ero

RET
REn

I

false

conhnue,
otherwise
same as

IN A, (n)

A - (n)

IN r, (C)

r - (C)
If r = 110 only the

· · ·
X

X

X

X

P

n to Ao - A7
Acc to As - Al5
C to AO - A7

11 011 011 DB

11

11 101 101 ED
01 r 000

12

16

C 10 AO - A7

21

C 10AQ - A7
B 10 AS - AI5

BloAg - A15

flags wlll be affected

lNI

(HL) - (C)
B - B-1
HL-HL+l
(HL) - (C)
B - 8-1
HL-HL+l

lNIR

X
X

CD
I

X

X

X

X

X

11 101 101 ED
10 100 010 A2

1

X

X

X

X

X

11 101 101 ED
10 110 010 B2

BtaAS - A15

S
(If B",O)

4

16

(If B.O)

Repeat unbl

B·O
lND

(HL) - (C)
B - B-1
HL- HL-l
(HL) - (C)
B - B-1
HL - HL-l

lNDR

X

CD
I

X

X X
X

X

X

X

11 101 101 ED
10 101 010 AA

X X X

X

11 101 101 ED
10 III 010 BA

Repeat unbl

OUT (n), A

8·0
(n) -A

OUT (C), r

(C) - r

oun

(C) - (HL)

X

OTlR

B - B-1
HL-HL+l
(C) - (HL)
8 - 8-1
HL-HL+l

X

·
·CD · ·
I

16

C to AD - A7

21

Cta AD - A7

BloAg - A15
5
(If B"O)
4
(If B.O)

B 10Ag - A15
16

X

X

X

11 010 OIl D3

11

n to AD - A7
Ace to AS - A15

X

X

X

11 101 101 ED
01 r 001

12

C 10AQ - A7
BloAg - A15

16

C 10 AQ - A7
B 10 Ag - AI5

21

Cta AD - A7

X

X

X

X

X

11 101 101 ED
10 100 011 A3

X X

X

X

X

11 101 101 ED
10 110 011 83

5
(If 8,,0)

4
(If B.O)

Repeat unbl

BloAg - A15
16

B·O
OUTD

(C) - (HL)

X

CDI

X

X

X

X

B - B-1
HL-HL-l
NOTE

CD If the result 01 B-1

CV N Flag

200)·00)
-----

IS ]

X

11 101 101 ED
10 101 011 AB

16

C 10 AO - A7
BloAg - AI5

IS zero the Z flag IS set, otherwise It IS reset
IS I, othewlse N Flag IS 0

If data bit

37

Input and
Output Group

Mnemonic

(Continued)

OTDR

Symbolic
Operation

S
X

IC) - IHL)

X

Flags
H
P/V N

C

X

X

X

X

B - B-1

Opcode
76 543 210 Hex

No.of No.of M No.of T
Byte. Cycl.. Stat..

II lOl 101 ED
10 III 011

5
III B*O)

HL - HL- I

ADD A. ,. ADC A.

III B=O)

0.,
S

Instruction

Do
H

,

SUB s, SEC A, s, CP s, NEG
AND s
OR s, XOR s
INC s
DEC s
ADD DO, 55
ADC HL, 55
SBC HL, S8

RLA. RLCA. RRA. RRCA
RL m, RLC m, RR m,
RRC m. SLA m,
SRA m, SRL m
RLD. RRD
DAA
CPL
SCF
CCF
IN r{e)

Symbolic
Notation

I

IN!. IND. oun aUTO
INIR. INDR. OTlR. aT DR
LD!.LDD
LDIR. LDDR
CPl. CPIR. CPO. CPDR

X
X

LD A. I. LD A.

I
X

BIT b, s

X

X
X

I
I
I
X
X

P/V N

X

X

X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X

X
X
X
X
X

X

X

0

X
X
X
X
X

X
X

X
X

I
I
0

0
0

X

X
X
X
X
X
X
X
X
X
X
X
X

X

V
V

0

P
P

0
0
0

V
V

I

C

Comments

I

S-blt add or add with carry
a-bit subtract, subtract with carry, compare and negate dccumulalor

~}

Logical operatIOns
8-blt Increment
B-blt decrement

I

V

0
0

V

I

16-blt add
16·blt add with carry
16·blt subtract wI!h carry
Rolate accumulator
Rolate and shlft locations

0

0

P

X
X

Rolate digit left and fight
DeCimal adjust accumulator
Complement accumulator
Set carry
Complement carry
Input register mduect

:}
:}

Block Input and output Z

= OliB:t- o otherWise Z

Block transfer InstructIOns P/V

=

1 li Be

=

0

'* 0, otherWise P/V

=

°

Block search Instructions Z = 1 If A = (HL), otherWise Z = 0 P/V = 1
If Be
0, otherWise PlY :=;
The content of the mterrupt enable fhp-flop (IFF) IS copIed mto the PlY ildg
The state of bit b of location s IS copied mto the Z flag

'*

IFF
X

Symbol
Operation
S
Sign flag. S = I If the MSB of the result IS I.
Z
Zero flag. Z = I tf the result of the operatton IS
Panty or overflow flag. Panty (P) and overflow
P/V
(V) share the same flag. Logical operations affect
th,s flag wIth the panty of the resull whtle
arithmetIc operations affect thiS flag wIth the
overflow of the result If P/V holds panty, PlY
I tf the resull of the operatIon IS even, P/V = If
result IS odd. If P/V holds overflow, PlY = I If
the result of the operatIOn produced an overflow.
Half-carry flag H = I If the add or subtract
H
operahon produced a carry mto or borrow from
bIt 4 of the accumulator
N
Add/Subtract flay. N = I If the prevIous operahan was a subtract.
H&N
Hand N flags are used 10 conjunctIon with the
deCimal adjust mstruchon (DAA) to properly cor~
rect the resull mto packed BCD format followmg
additIon or subtractIOn usmg operands with
packed BCD formal.
Carry/Lmk flag. C = I If the operatIOn produced
C
a carry from the MSB of the operand or result.

°

°

38

Comment.

C to AO - A7
BtoAa- A15

16

4

Repeat unhl
B = 0

Summary of
Flag
Operation

21

Symbol
I

°
I
X
V
P

ss
II

R
n
nn

°

Operation
The flag IS affected accordmg to the result of the
operatIon.
The flag IS unchanged by the operatton
The flag IS reset by the operation
The flag IS set by the operatIOn
The flag IS a "don't care."
P/V flag affecled accordmg to the overflow result
of the operation.
PlY flag affected accordmg 10 the panty resull of
the operatIOn
Anyone of the CPU regIsters A, B, C, D, E, H, L.
Any 8-blt location for all the addressmg modes
allowed for the particular InstructIon.
Any 16-blt locatIon for all the addreSSIng modes
allowed for that Instruchon.
Anyone of the two mdex registers IX or IY.
Refresh counter
S-blt value m range < 0, 255 > .
16-blt value m range < 0, 65535 >.

Pin
Descriptions

Ao-A1S. Address Bus (output, acllve High,
3-state). Ao-A15 form a 16-blt address bus. The
Address Bus provides the address for memory
data bus exchanges (up to 64K bytes) and for
I/O device exchanges.
BUSACK. Bus Acknowledge (output, acllve
Low). Bus Acknowledge mdlcates to the
requestmg device that the CPU address bus,
data bus, and control signals MREQ, 10RQ,
RD, and WR have entered their hlghImpedance states. The external circUItry
can now control these lmes.
BUSREQ. Bus Request (mput, acllve Low).
Bus Request has a higher pnonty than NMI
and IS always recogmzed at the end of the current machme cycle. BUSREQ forces the CPU
address bus, data bus, and control signals
MREQ, 10RQ, RD, and WR to go to a hlghImpedance state so that other devices can
control these Imes. BUSREQ IS normally wlreORed and reqUIres an external pullup for
these apphcallons. Extended BUSREQ
periods due to extensive DMA operallons can
prevent the CPU from properly refreshmg
dynamiC RAMs.
0 0 -0 7 , Data Bus (mput/output, acllve High,
3-state). 00-07 conslltute an 8-bit bidlrecllonal
data bus, used for data exchanges with
memory and 110.

HALT. Halt State (output, acllve Low). HALT
indICates that the CPU has executed a Halt
instrucllon and IS awaltmg either a nonmaskable or a maskable interrupt (With the
mask enabled) before operallon can resume.
While halted, the CPU executes NOPs to
mamtain memory refresh.

INT. Interrupt Request (mput, acllve Low).
Interrupt Request is generated by 110 deVices.
The CPU honors a request at the end of the
current instruction if the mternal softwarecontrolled interrupt enable fhp-flop (IFF) IS
enabled. INT IS normally wlre-ORed and
requires an external pullup for these
applicatIOns.
IORQ. Input/Output Request (output, acllve
Low, 3-state). 10RQ indIcates that the lower
half of the address bus holds a valid 110
address for an I/O read or write operallon.
10RQ IS also generated concurrently WIth Ml
during an interrupt acknowledge cycle to indIcate that an Interrupt response vector can be

placed on the data bus.

MI. Machine Cycle One (output, active Low).
MI, together with MREQ, indICates that the
current machine cycle IS the opcode fetch
cycle of an instruction execution. Ml, together
WIth 10RQ, indicates an interrupt acknowledge
cycle.
MREQ. Memory Request (output, active
Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory read or
memory write operation.

NMI. Non-Maskable Interrupt (input, acllve
Low, edge-triggered). NMI has a hIgher priority than INT. NMI is always recognized at the
end of the current instruction, independent of
the status of the interrupt enable fhp-flop, and
automatically forces the CPU to restart at
location 0066H.

RD. Read (output, acllve Low, 3-state). RD indICates that the CPU wants to read data from
memory or an I/O device. The addressed 110
device or memory should use thIS signal to
gate data onto the CPU data bus.
RESET. Reset (input, acllve Low). RESET
initiahzes the CPU as follows: it resets the
interrupt enable flip-flop, clears the PC and
Registers I and R, and sets the interrupt status
to Mode O. During reset time, the address and
data bus go to a hIgh-impedance state, and all
control output signals go to the inactive state.
Note that RESET must be active for a minImum
of three full clock cycles before the reset
operation is complete.
RFSH. Refresh (output, active Low). RFSH,
together with MREQ, indicates that the lower
seven bIts of the system's address bus can be
used as a refresh address to the system's
dynamiC memories.
WAIT. Wait (mput, active Low). WAIT
indICates to the CPU that the addressed memory or I/O devices are not ready for a data
transfer. The CPU continues to enter a Wall
state as long as this SIgnal IS acllve. Extended
WAIT periods can prevent the CPU from
refreshing dynamiC memory properly.
WR. Write (output, active Low, 3-state). WR
indICates that the CPU data bus holds vahd
data to be stored at the addressed memory or
I/O locallon.

39

CPU Timing

The CPU executes instructions by proceeding through a specifIc sequence of operations:

• Interrupt acknowledge

The basIc clock perIOd IS referred to as a
T time or cycle, and three or more T cycles
make up a machine cycle (Ml, M2 or M3 for
instance). Machine cycles can be extended
either by the CPU automatically inserting one
or more Wait states or by the Insertion of one
or more Walt states by the user.

Instruction Opcode Fetch. The CPU places
the contents of the Program Counter (PC) on
the address bus at the start of the cycle (Figure
5). ApprOXimately one-half clock cycle later,
MREQ goes active. When active, RD indicates
that the memory data can be enabled onto the
CPU data bus.

The CPU samples the WAIT input with the
falling edge of clock state T2. During clock
states T3 and T4 of an Ml cycle dynamic RAM
refresh can occur while the CPU starts
decoding and executing the instruction. When
the Refresh Control signal becomes active,
refreshing of dynamIC memory can take place.

• Memory read or write
• 1/0 device read or write

T,

T,

Tw

T,

T.

CLOCK

Ao-Au

MAEQ

AD

WAl'f

ii1

««

~
,,;-

APSH

~

~

NOTE Tw-Walt cycle added when necessary for slow ancllhary devlces

Figure 5. In.truction Opcode Felch

40

2005·882

CPU
Timing
(Contmued)

Memory Read or Write Cycles. Figure 6

shows the timing of memory read or write
cycles other than an opcode fetch (Ml) cycle.
The MREQ and RD signals function exactly as
in the fetch cycle. In a memory write cycle,

MREQ also becomes active when the address
bus IS stable. The WR lme IS active when the
data bus IS stable, so that It can be used
directly as an R/W pulse to most semiconductor memories.

T,

T,

Tw

CLOCK

OPERA~~~:

1

iiD

l

Do-D7

l

)

Figure 6. Memory Read or Write Cycles

41

CPU
Timing
(Continued)

Input or Output Cycles. FIgure 7 shows the
timing for an I/O read or 1/0 write operahon.
During 1/0 operatIOns, the CPU au tomah cally

inserts a single Wait state (Tw). This extra Wail
state allows sufficient hme for an 1/0 port to
decode the address from the port address lines.
T,

T,

CLOCK

+-__-r__-+__________

WAIT __

~~_L

___~

"0\

READ
OPIRATION

1

WR

WRI~:
OPI!RATION

Do-D7

~
-----------t========~===~~~===j
DATA OUT

NOTE Tw" == One Walt cycle automahcally mserted by CPU.

Figure 7. Input or Output Cycles

Interrupt Request/Acknowledge Cycle. The
CPU samples the Interrupt signal with the rising edge of the last clock cycle at the end of
any instruction (FIgure 8). When an interrupt
is accepted, a specIal Ml cycle is generated.

During this Ml cycle, IORQ becomes active
(instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the
data bus. The CPU automatically adds two
Wail states to this cycle.

CLOCK

-+__,~--------------p-C--_r------_H-(.~--~+_--H_-J~---

AO-A15 ____________

-+__________________________

WAIT ____________

~~--~--'

Do-D7

NOTE 1) TL= Last state of prevIous mstruchon

2) Two Walt cycles automatIcally Inserted by CPU(*}.

Figure 8. Interrupt Request/Acknowledge Cycle

42

2005-884, 885

CPU

Timing
(Continued)

Non-Maskable Interrupt Request Cycle.
NMI IS sampled at the same lime as the
maskable Interrupt Input INT but has higher
priority and cannot be disabled under software
control. The subsequent timing IS similar to

that of a normal memory read operalion except
that data put on the bus by the memory IS
Ignored. The CPU instead executes a restart
(RST) operalion and Jumps to the NMI service
routine located at address 0066H (Figure 9).

CLOCK

IIMI------ \J ® ir---

--------H-----

-

AO-&1I1

-----------t-J't-+---.::::....---+..f\------+--+------jJ'-

.. Although NMI IS an asynchronous mput, to guarantee Its bemg
recognized on the followmg machme cycle, NMI's fallmg edge

must occur no later than the nsmg edge of the clock cycle

precedmg TLAST

Figure 9. Non·Maskable Interrupt Request Operation

Bus Request/Acknowledge Cycle. The CPU
samples BUSREQ with the rising edge of the
last clock penod of any machine cycle (Figure
10). If BUSREQ IS aclive, the CPU sets ItS
address, data, and MREQ, IORQ, RD, and WR

lines to a high-Impedance state With the rising
edge of the next clock pulse. At that time, any
external device can take control of these lines,
usually to transfer data between memory and
1/0 devices.

DO-D1

.....1

® __

RFSH _ _ _ _ _ _ _ _ _ _ _ _~-JfJ

HALT

---------------r------------------------

NOTE TL = Last state of any M cycle

IX = An arbitrary clock cycle used by requeshng device

Figure 10. Z-BUS Request/Acknowledge Cycle
2005·0218. 886

43

CPU

Timing
(Contmued)

Halt Acknowledge Cycle. When the CPU
receives a HALT mstruction, it executes NOP
states unhl mther an INT or NMI mput IS

received. When m the Halt state, the HALT
output IS achve and remams so until an mterrupt IS processed (FIgure II).

_ _ _ _ _ o _ _ - - - - - - - - M 1 - - - - - - - _ + _ 0 _ _ - - - - - M1

CLOCK

NM)

----------_I~_·-------V-

NOTE INT will also force a Halt

*See note, Figure 9

eXIt.

Figure II. Halt Acknowledge Cycle

Reset Cycle. RESET must be active for at least
three clock cycles for the CPU to properly
accept It. As long as RESET remams active, the
address and data buses float, and the control
outputs are inactive. Once RESET goes

machve, two mternal T cycles are consumed
before the CPU resumes normal processmg
operahon. RESET clears the PC regIster, so the
first opcode fetch w!ll be to locahon 0000
(FIgure 12).
_M1------

CLOCK

-®....-

--0FLOAT

AO~A15 ______________________________~-l----(;,. System Data Bus (bidirectional,
3-state). Commands from the CPU, DMA
status, and data from memory or 1/0
peripherals are transferred on these lines.
lEI. Interrupt Enable In (input, active High).
This is used with IEO to form a priority daisy
chain when there is more than one interruptdriven device. A High on this line indicates
that no other device of higher priority is being
serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). lEO is High only If IEI is High and the
CPU is not servicing an interrupt from this
DMA. Thus, this signal blocks lower-priority
devices from interrupting while a higherpriority device is being serviced by its CPU
interrupt service routine.

Pin
Description
(Contmued)

Internal
Structure

INT/PULSE. Interrupt Request (output, active
Low, open dram). This requests a CPU mterrupt. The CPU acknowledges the interrupt by
pullmg Its IORQ output Low during an Ml
cycle. It is tYPICally connected to the INT pm
of the CPU with a pullup resistor and tied to
all other INT pins in the system. This pm can
also be used to generate periodIC pulses to an
external devICe. It can be used thIS way only
when the DMA is bus master (I.e., the CPU's
BUSREQ and BUSACK Imes are both Low
and the CPU cannot see mterrupts).
10RQ. Input/Output Request (bidirectional,
active Low, 3-state). As an input, this indicates
that the lower half of the address bus holds a
valid I/O port address for transfer of control or
status bytes from or to the CPU, respectively;
this DMA is the addressed port if its CE pin
and its WR or RD pins are simultaneously
active. As an output, after the DMA has taken
control of the system buses, it indicates that
the 8-bit or 16-bit address bus holds a valid
port address for another I/O device involved in
a DMA transfer of data. When IORQ and MI
are both active Simultaneously, an interrupt
acknowledge is indicated.
MI. Machine Cycle One (input, achve Low).
Indicates that the current CPU machme cycle
is an mstruction fetch. It IS used by the DMA
to decode the return-from-interrupt instruction
(RETI) (ED-4D) sent by the CPU. During twobyte instruction fetches, Ml is active as each
The internal structure of the Z-80 DMA
includes driver and receiver Circuitry for interfacing with an 8-bit system data bus, a 16-bit
system address bus, and system control lines
(Figure 6). In a Z-80 CPU environment, the
DMA can be tied directly to the analogous pins
on the CPU (Figure 7) with no additional buffering, except for the CElWAIT line.
The DMA's internal data bus interfaces with
the system data bus and services all internal
logic and registers. Addresses generated from
this logic for Ports A and B (source and destination) of the DMA's single transfer channel
are multiplexed onto the system address bus.

opcode byte is fetched. An mterrupt acknowledge IS indICated when both MT and
IORQ are achve.

MREQ. Memory Request (output, active Low,
3-state). ThIS indicates that the address bus
holds a valid address for a memory read or
write operahon. After the DMA has taken control of the system buses, It mdicates a DMA
transfer request from or to memory.

RD. Read (bidIrectional, achve Low, 3-state).
As an mput, this indicates that the CPU wants
to read status bytes from the DMA's read
registers. As an output, after the DMA has
taken control of the system buses, it indICates a
DMA-controlled read from a memory or I/O
port address.
ROY. Ready (mput, programmable active Low
or High). This is monitored by the DMA to
determine when a peripheral device associated
WIth a DMA port is ready for a read or write
operation. Depending on the mode of DMA
operation (Byte, Burst or Continuous), the RDY
line indirectly controls DMA activity by causing the BUSREQ line to go Low or High.
WR. Wnte (bidirectional, active Low, 3-state).
As an input, this indicates that the CPU wants
to write control or command bytes to the DMA
write regIsters. As an output, after the DMA
has taken control of the system buses, it
indicates a DMA-controlled write to a memory
or I/O port address.
Speciahzed logic circuits in the DMA are
dedICated to the various functions of external
bus interfacing, internal bus control, byte
matching, byte counting, periodic pulse
generation, CPU interrupts, bus requests, and
address generation. A set of twenty-one
writable control registers and seven readable
status regIsters provides the means by whICh
the CPU governs and monitors the activities of
these logic circuits. All registers are eight bits
wide, with double-byte information stored in
adjacent registers. The two address counters
(two bytes each) for Ports A and B are buffered
by the two starting addresses.

SYSTEM
ADDRESS
BUS
(18 BIT)

CONTROL

\.----,/1

Figure 6. Block Diagram
2032·0130

53

Internal
Structure
(Continued)

The 21 writable control regIsters are
organized mto seven base-register groups,
most of whICh have multIple registers. The
base registers in each wrItable group contain
both control/command bIts and pomter bits
that can be set to address other regIsters withm
the group. The seven readable status registers
have no analogous second-level registers.
The registers are desIgnated as follows,
according to their base-register groups:

system bus, however, may not be pre-empted.
Any DMA that gams access to the system bus
keeps the bus until it is finished.
Write Registers

WRO

Base regIster byte
Port A startmg address (low byte)
Port A starting address (hIgh byte)
Block length (low byte)
Block length (hIgh byte)

WRO-WR6 - Write Register groups 0
through 6 (7 base registers plus 14 associated registers)
RRO-RR6 - Read Registers 0 through 6

WRI

Base regIster byte
Port A variable-timmg byte

WR2

Base regIster byte
Port B varIable-lImmg byte

Writing to a register wlthm a wrIte-regIster
group involves first writing to the base
register, with the appropriate pOinter bits set,
then writing to one or more of the other
regIsters wIthin the group. All seven of the
readable status regIsters are accessed sequentIally according to a programmable mask contained in one of the writable registers. The section entitled "Programmmg" explains this in
more detaIl.
A pipelining scheme is used for reading data
in. The programmed block length is the
number of bytes compared to the byte counter,
which increments at the end of each cycle. In
searches, data byte comparisons with the
match byte are made during the read cycle of
the next byte. Matches are, therefore, discovered only after the next byte is read in.
In multIple-DMA configurations, interruptrequest daisy chains are prIoritized by the
order in which their IEI and lEO lines are connected (Zilog Application Note 03-0041-01, The
Z-80 Family Program Interrupt Structure). The

WR3

Base register byte
Mask byte
Match byte

WR4

Base regIster byte
Port B starlIng address (low byte)
Port B startmg address (hIgh byte)
Interrupt control byte
Pulse control byte
Interrupt vector

WR5

Base register byte

WR6

Base regIster byte
Read mask

RRO

Status byte

Read Registers

RRI

Byte counter (low byte)

RR2
RR3

Byte counter (hIgh byte)
Port A address counter (low byte)

RR4

Port A address counter (hIgh byte)

RR5

Port B address counter (low byte)

RR6

PorrB address counter (high byte)

COMMON:

iN'f
BUSREQ

.--------tBUSACK

iil

CPU

lOiilI

FROM

FROM

I/O

00
DEVICE

DEVICE

Figure 7. Multiple-DNA Inlerconnectlon 10 the Z-80 CPU

54

2032·0131

Programming

The Z-80 DMA has two programmable fundamental states: (I) an enabled state, m whICh
It can gam control of the system buses and
direct the transfer of data between ports, and
(2) a disabled state, m which It can Imtlate
neither bus requests nor data transfers. When
the DMA IS powered up or reset by any means,
It IS automatically placed mto the disabled
state. Program commands can be written to It
by the CPU m either state, but this automatically puts the DMA m the disabled state,
which IS mamtamed until an enable command
IS Issued by the CPU. The CPU must program
the DMA m advance of any data search or
transfer by addressmg It as an 1/0 port and
sendmg a sequence of control bytes usmg an
Output mstructlon (such as OTIR for the
Z-80 CPU).

Writing. Control or command bytes are written into one or more of the Write Register
groups (WRO-WR6) by first writing to the base
register byte in that group. All groups have
base registers and most groups have additional
associated registers. The associated registers
in a group are sequentially accessed by first
writing a byte to the base register containing
register-group identification and pOinter bits
(I's) to one or more of that base register's
associated registers.
This is illustrated in Figure 8b. In this
figure, the sequence in which associated
registers within a group can be written to is
shown by the vertical position of the associated
registers. For example, J! a byte written to the
DMA contains the bits that identify WRO (bits
DO, 01 and 07), and also contains l's in the
bit positions that point to the associated "Port
A Starting Address (low byte)" and "Port A
Starting Address (high byte)," then the next
two bytes written to the DMA will be stored in
these two registers, in that order.
Reading. The Read Registers (RRO-RR6) are
read by the CPU by addressing the DMA as an
I/O port using an Input mstructlon (such as
!NIH for the Z-80 CPU). The readable bytes
contain DMA status, byte-counter values, and
port addresses smce the last DMA reset. The

registers are always read m a fixed sequence
begmmng with RRO and endmg with RR6.
However, the register read m thiS sequence IS
determmed by programmmg the Read Mask m
WR6. The sequence of readmg IS Imtlalized by
wrltmg an Imtlate Read Sequence or Set Read
Status command to WR6. After a Reset DMA,
the sequence must be Imtlalized with the
Imtlate Read Sequence command or a Read
Status command. The sequence of readmg all
registers that are not excluded by the Read
Mask register must be completed before a new
Imtlate Read Sequence or Read Status
command.
Fixed-Address Programming. A speCial Circumstance arises when programming a destination port to have a fixed address. The load
command m WR6 only loads a fixed address to
a port selected as the source, not to a port
selected as the destmation. Therefore, a fixed
destination address must be loaded by temporarily declarmg it a fixed-source address
and subsequently declarmg the true source as
such, thereby Implicitly makmg the other a
destmatlon.
The followmg example Illustrates the steps m
thiS procedure, assummg that transfers are to
occur from a variable-address source (Port A)
to a fixed-address destination (Port B):
1. Temporanly declare Port B as source in
WRO.
2. Load Port B address m WR6.

3. Declare Port A as source in WRO.
4. Load Port A address m WR6.
5. Enable DMA m WR6.
Figure 9 Illustrates a program to transfer
data from memory (Port A) to a peripheral
deVICe (Port B). In thiS example, the Port A
memory startmg address IS 1050H and the Port
B penpheral fixed address IS 05H. Note that
the data flow IS 1001H bytes-one more than
specIfied by the block length. The table of
DMA commands may be stored m consecutive
memory locations and transferred to the DMA
with an output mstructlon such as the Z-80
CPU's OTIR mstructlon.

Read Register 0

Read Register 2

0, 0 6 0 5 0, 0 3 02 0 1 Do

I X 1xliii xii I STATUS BYTE

Iii

I

1'-I.1....J...1...J1-L.1_I'-I.....J......JI BYTE COUNTER (HIGH BYTE)

L-,.
OPERATION HAS OCCURRED
o '" DMA
READY ACTIVE
o=

o=

o '"

INTERRUPT PENDING
MATCH FOUND

END OF BLOCK

Read Register 3

1'-I.1....J...1...J1-L.1_IL......J.....J......JI
..
I ...I1-L.1_IL......J.I....J...I...I..-.l.....J1

Read Register 1

..I ...J1'-I.1....J...1_1'-I.1....J...-'-...I1

PORT A ADDRESS COUNTER (LOW BYTE)

Read Register 4.
PORT A ADDRESS COUNTER (HIGH BYTE)

Read Register 5
BYTE COUNTER (LOW BYTE)

..
I ...I1-L.1_1L.. . .J.1. . J. .1...I..-.l.....J1

PORT B ADDRESS COUNTER (LOW BYTE)

Read Register 6

1........1-,-1_1.........1-,-1-'-~I

PORT B ADDRESS COUNTER (HIGH BYTE)

Figure Sa. Read RegiBters
2032-0132

55

I

I

Programming
(Continued)

Write IIegIotor 4 Group

Write Register 0 Group
Dr DsDsD.DaDJD1Do

D, De Ds D. D3 OJ D1

DO NOT USE

BYT

E.! 1

CONTINUOus = 0
BURST = 1
DO NOT PROGR AM", 1

.. TRANSFER
1 0 '" SEARCH
1 1 - SEARCHITRANSFER
0- PORT I_PORTA
1 .. PORT A_PORTa

I' !

1
0
1

PORT A STARTING ADDRESS
(LOW BYTE)

I

I

~

I

PORT A STARTING ADDRESS
_LJ (HIGH
BYTE)

~

t
0

BLOCK LENGTH

BLOCK LENGTH

Ll 1 I PULSE CONTROL BYTE

I 0 I B.SE REGISTER BYTE

II

PORT • IS MEMORY
1 ... PORT A IS 110

0
1

~

~

VECTOR IS AUTOMATICALLY {D
MODIFIED AS SHOWN
0
ONLY IF "STATUS
1
AFFECTS VECTOR" BIT IS SET
1

'" PORT A ADDRESS DECREMENTS
= PORT A ADDRESS INCREMENTS

I'" PORT A ADDRESS FIXED

L.."-:-,1..;.0,1..;.0-'-;-"-:--'-;-J..,-J PORT A VARIABLE TIMING BYTE

!=I

ViR ENDS'll CYCLE EARLY ...
FRi ENDS'll CYCLE EARLY
iiiiEQ ENDS

0
'h CYCLE EARLY

! !'"

11

101

I I I

I I

101, 10 I BASE REGISTER BYTE

= READY ACTIVE LOW

o '" STOP ON END OF BLOCK
1 - AUTO RESTART ON END OF BLOCK

101010IB'SEREGISTERBYTE

Write Register BGroup

1.

Dr DsOs D403 D2D,Do

B I. MEMORY
I 1 , . PORT
PORTalSIlO

11

o 0 = PORT B ADDRESS DECREMENTS
o , '" PORT B ADDRESS INCREMENTS
~

~} =

I I I I I

! I I 111.

RD ENDS Vt CYCLE EARLY - 0
KIRIli ENDS Vt CYCLE EARLY

=

0
1
1

0
o '"

1
0
1

Imm

11 11 I B.SE REGISTER BYTE

I I I I I=

PORT 8 ADDRESS FIXED

a
1
a

'-:-.L...:-"-:-"-:-.L...:-.L...:-.L...:-",,-:-,PORT 8 VARIABLE TIMING BYTE

Wii ENOS Yo CYCLE EARLY.

IN11!:RRUPT ON MATCH
AND END OF BLOCK

= INTERRUPT ON END OF BLOCK

1

Do

D, D. 0, D2 01

INTERRUPT ON MATCH

=

11 1 ". READY ACTIVE HIGH
~ : gIEIW~ MULTIPLEXED

Write Register 2 Group
De

= INTERRUPT ON RDY

=

Writ. RogIstor5 Group
11 101

o _ imm ENDS 'h CYCLE EARLY

07

0
1
0
1

D7DtD5D4~~D1Do

CYCLE LENGTH'" 4
1 '" CYCLE LENGTH = 3
0 = CYCLE LENGTH = 2
1 .. DO NOT USE

0
1
1

=

I I I I I I I I INTERRUPT VECTOR

I

I I !.
o
o

lllJ INTERRUPT CONTROL BYTE

-.1

01 0 8 Os 04 0 3 02 0 1 DD

11 10

PORT B STARTING ADDRESS
lllJ (HIGH
BYTE)

INTERRUPT ON MATCH
1 = INTERRUPT AT END OF BLOCK
1 ,. PULSE GENERATED

Write Register 1 Group

I I I

~

INTERRUPT ON RDY = 1
STATUS AFFECTS V ECTOR -1

(HIGH BYTE)

101

PORT B STARnNG ADDRESS
BYTE)
lllJ (lOW

I I I I ,.I

(LOW BYTE)

~

00

(, I I I I I I 0 I d BASE REGISTER BYTE

I 0 I I I I I I I I BASE REGISTER BYTE

NO COMMAND NAM.

C3". RESET
RESET PORT A TIMING
RESET PORT I TIMING

= C7 =
= CI '"

1=CF=LOAD
a '" D3 '" CONTINUE

CYCLE LENGTH = •
I

1 = AF '" DISABLE INTERRUPTS
a = AI '" ENAILE INTERRUPTS
o '" AI = RESET AND DISAllE INTERRUPTS
1 ... 87 '" ENABLE AFTER RETI

=
= CYCLE LENGTH = 2

= CYCLE LENGTH

DO NOT USE
ENDS Vt CYCLE EARLY

1 '" BF '" READ STATUS IYTE
o '" 81 '" REINITIALIZE STATUS BYTE

Writ. RegiBlor 3 Group

o

D7DtD&D4o,~D,Do

111

I I I I

II

DMA ENABLE - 1
INTERRUPT ENABLE =

10

0

0

1 = A7 '" INITIATE READ SEOUENCE

1 _ 87 III ENABLE DMA
o ,. 83 '" DISABLE DMA

J = STOP ON MATCH

.-- 0

1

1

1

0 .. BB - READ MASK FOLLOWS

LloT I I I I I I

,

1111

L.."-:-"-:--'TJ....J....J.....I....J MASK BYTE (D = COMPARE)

~

.

L-J....J....J..............................., MATCH BYTE

Figure

56

1

01100""a3=FORCEREADY

I 0 I BASE REGISTER BYTE

ab.

II

I READ MASK (1

= EN.BLE)

L - :~;~Uto~~TiEA (LOW BYTE)

=~1~ ~O:D"oT::sr:E~'::~~E)

PORT A ADDRESS (HIGH BYTE)
POAT B ADDRESS (lOW BYTE)
POAT B ADDRESS (HIGH BYTE)

Write Registe..
2032-0132

~

~'tI

0 ..

o 0

o

:;IQ

CD
2a

is

~a

~~.

Comments

07

06

05

D.

03

WRQ sets DMA to receive
block length, Port A startIng address and temporarily
sets Port B as sou rce

0

1

1

1

1

Block Length
Upper
Follows

Block Length
Lower
Follows

Port A
Upper
Address
Follows

Port A
Lower
Address
Follows

02

0,

0

0

B __ A
Temporary
for
Loading 8
Address"

HEX

1

79

Transfer, No Search

Port A address (lower)

0

1

0

1

0

0

0

0

0

0

0

1

0

0

0

0

10

Block length (lower)

0

0

0

0

0

0

0

0

00

Block length (upper)

0

0

0

1

0

0

0

0

10

WR1 defines Port A as
memory with fixed
incrementing address

0

0

0

1

0

0

14

Address
Changes

1
Address
Increments

0

No Timing
Follows

Port IS
Memory

WR2 defines Port 8 as
peripheral with fixed
address

0

0

0

1

0

28

WR4 sets mode to Burst,
sets DMA to expect Port B
address

1

1
Port BLower
Address
Follows

0

1

C5

Port B address (lower)

0

0

WR5 sets Ready active High

1

0

0

1

No Timing
Follows

Fixed
Address

1

0

1

1

WRQ sets Port A as source"

0

0

50

IS

1/0

0

0

No Interrupt
Control Byte
Follows

No Upper
Address

0

0

0

1

0

1

05

0

0

1

0

1

0

8A

No Auto
Restart

NoWa,t
States

Active High

0

0

1

1

1

1

CF

0

0

0

A _1_ B

0

1

05

Burst Mode

WR6 loads Port B address
and resets block counter *

1

Port

RDY

Transfer, No Search

WR6 loads Port A address
and resets block counter

1

1

0

0

1

1

1

1

CF

WR6 enables DMA to start
operation

1

0

0

0

0

1

1

1

87

NOTE The actual number of bytes transferred IS one more than speCified by the block length
"These entries are necessary only In the case of a fixed destination address

>-.J

Do

Port A address (upper)

No Address or Block
Length Bytes

(}J

I

Figure 9. Sample DMA Program

vila 08Z

In its dIsabled or machve state, the DMA IS
Inactive
State Timing addressed by the CPU as an 1/0 peripheral for
(DMA as CPU write and read (control and status) operahons.
Peripheral)
Write hmmg IS Illustrated in FIgure 10.
Readmg of the DMA's status byte, byte
counter or port address counters IS illustrated

m Figure 11. These operations require less
than three T-cycles. The CE, IORQ and
RD lines are made active over two rising edges
of CLK, and data appears on the bus approximately one T-cycle after they become active.

c:n~1-----

IO~

Do-D7

____ _

-_
__+

!-~

.

Figure 10. CPU-Io-DMA Write Cycle

Active State
Timing
(DMA as Bus
Controller)

Figure 11_ CPl!olo-DMA Read Cycle

mserted walt cycle between T2 and T3. If the
CE/WAIT line is programmed to act as a
WAIT line durmg the DMA's achve state, It IS
sampled on the fallmg edge of T2 for memory
transactions and the falling edge of Tw for 1/0
transactions. If CE/WAIT is Low durmg this
time another T-cycle is added, during which
the CE/WAIT Ime will again be sampled. The
durahon of transactions can thus be indefmitely extended.

Default Read and Write Cycles. By default,
and after reset, the DMA's timing of read and
write operahons is exactly the same as the 2-80
CPU's timmg of read and write cycles for
memory and 1/0 peripherals, with one exception: during a read cycle, data is latched on
the fallmg edge of T3 and held on the data bus
across the boundary between read and write
cycles, through the end of the following write
cycle.
FIgure 12 illustrates the timing for memoryto-IIO port transfers and Figure 13 Illustrates
I/O-to-memory transfers. Memory-to-memory
and IIO-to-IIO transfer timings are simply permutations of these diagrams.
The default hming uses three T-cycles for
memory transachons and four T-cycles for 1/0
transactions, whICh include one automatically

1.....-~

eLK

.... j
j

W'"'

iii>

I

~

---.1..----

j

~

13

I

-\
-n

~

I

I

J
\
\

WR

CEIWAIT

-----1

~

I

IORQ

Do-OJ

1/0 WRITE

~

-fl-r- ~IL 1L1L!Lr-

Ao-A15

MREQ

MEMORY READ

Variable Cycle and Edge Timing. The 2-80
DMA's default operahon-cycle length for the
source (read) port and destination (write) port
can be independently programmed. This
variable-cycle feature allows read or write
cycles consIsting of two, three or four T-cycles
(more if Walt cycles are inserted), thereby
mcreasmg or decreasing the speed of all
signals generated by the DMA. In addition,

-

-

~

MEMORY

1-----1

DRIVES DATA

--

--

r.~::

rr

f-

DATA BUS DRIVEN BY CMA

- - f--- -I ~ --- f---

Figure 12. Memory-Io-I/O Transfer

58

2032-0134. 0135. 0136

Active State
Timing
(DNA as Bus
Controller)
(Continued)

1....- - - -

110 READ - - - -

1
T1

T2

eLK

II

II

READ

j

'ORQ

\

I

AD

\

I
110 DRIVES DATA

II

,-

\

- t--- 1--1--- 1---

11-

DMA DRIVES DATA BUS

I\. L-r

I"-

!--

I

--- ----- - trrt ----- 11 1\
---

!

Figure 13. 1I0-lo-Memory Transfer

the trailing edges of the lORQ, MREQ, RD and
WR sIgnals can be independently terminated
one-half cycle early. Figure 14 illustrates thiS.
In the variable-cycle mode, unlike default
timing, IORQ comes active one-half cycle
before MREQ, RD and WR. CE/WAIT can be
used to extend only the 3 or 4 T-cycle variable
memory cycles and only the 4-cycle variable
I/O cycle. The CE/WAIT lme is sampled at the
falling edge of T2 for 3- or 4-cycle memory
cycles, and at the falling edge of T3 for 4-cycle
I/O cycles.
During transfers, data is latched on the
clock edge causing the rising edge of RD and
held through the end of the write cycle.
1 T, 1 T, I T, I T. I
CLK~
AoMAt.

2d"'-~"'-t"'L_

,- "\
-.!IR~

RD, WR

1_ _

r"T'I I

--,

r-r-r

~

t

2 CYCLE

-'-

t

3 CYCLE

-r

Bus Requests. Figure 15 illustrates the bus
request and acceptance timing. The RDY line,
which may be programmed active High or
Low, is sampled on every rising edge of CLK.
If it is found to be active, and if the bus is not
in use by any other device, the following rising
edge of CLK drives BUSREQ low. After receiv.!!:!2. BUSREQ the CPU acknowledges on the
BAI input either directly or through a
multip1e-DMA daisy chain. When a Low is
detected on BAI for two consecutive rising
edges of CLK, the DMA will begin transferring
data on the next rising edge of CLK.

CLK

1_ _

---

-'-

t

4 CYCLE

11IiIiIlIi ___ ...J

-------rt---f'JO""V

iii ______ ....1

.MA

INACTIVE

...

ACTIVE

EARLY END EARLY END EARLY END

Figure 1.... Variable-Cycle and Edge Timing

2032-0137,0138,0139

Figure 15. Bus Requesl and Acceplance

59

Active State
Timing
(DNA as Bus
Controller)
(Continued)

Bus Release Byte-at-a-Time. In Byte-at-aTime mode, BUSREQ is brought High on the
rising edge of CLK prIOr to the end of each
read cycle (search-only) or write cycle
(transfer and transfer/search) as illustrated in
Figure 16. This is done regardless of the state
of RDY. There is no possibility of confusion
when a Z-80 CPU is used since the CPU
cannot begin an operation until the following
T-cycle. Most other CPUs are not bothered by
this either, although note should be taken of it.
The next bus request for the next byte will
come after both BUSREQ and BAI have
returned High.
Bus Release at End of Block. In Burst and
Continuous modes, an end of block causes
BUSREQ to go High usually on the same rising
edge of CLK in which the DMA completes the
transfer of the data block (Figure 17). The last
byte in the block is transferred even if RDY
goes inactive before completion of the last byte
transfer.
Bus Release on Not Ready. In Burst mode,
when RDY goes inactive it causes BUSREQ to
go High on the next rising edge of CLK after
the completion of its current byte operation
(Figure 18). The action on BUSREQ is thus
somewhat delayed from action on the RDY
line. The DMA always completes its current
byte operation in an orderly fashion before
releasing the b..u""s,.;,'""'''''''
By contrast, BUSREQ is not released in
Contmuous mode when RDY goes inactive .

.u.:~~

Instead, the DMA idles after completing the
current byte operation, awaiting an active RDY
again.
Bus Release on Match. If the DMA is programmed to stop on match in Burst or Continuous modes, a match causes BUSREQ to go
inactive on the next DMA operation, i.e., at
the end of the next read in a search or at the
end of the following write in a transfer (Figure
19). Due to the pipelining scheme, matches
are determined while the next DMA read or
write is being performed.
The RDY line can go inactive after the
matching operation begins without affecting
this bus-release timing.
Interrupts. Timings for interrupt acknowledge
and return from interrupt are the same as timings for these in other Z-80 peripherals. Refer
to Zilog Application Note 03-0041-01 (The Z-80
Family Program Interrupt Structure).
Interrupt on RDY (interrupt before requesting bus) does not directly affect the BUSREQ
line. Instead, the interrupt service routine
must handle this by issuing the following
commands to WR6:
1. Enable after Return From Interrupt (RET!)
Command - Hex B7
2. Enable DMA - Hex 87
3. An RET! instruction that resets the
Interrupt Under Service latch in the
Z-80 DMA.

.DO

1

o.u

r--------------------f,II~
1

-

DMA ACTIVE

I'
-r-

INACTIVE

.u....Q

-----f.I---t'

DMA INACTIVE

Figure 16. Bus Release (Byte-at-a-Tlme Mode)

ACTIVI

oay

Figure 17. Bus Release at End of Block
(Burst and Continuous Modes)

C~~~~
'J
,-.r
____

IIlDY
INACTIVE

iUiJIii

--------~~----~

' - _ _ -I~_-_-

INACTIVE

_ _

__

.ua.... _ _ _ _-I.I.;~._ _ _ _ _ _1
.....
\ - - PlEAD 'N

•

\

•

...

8YTIiIt+1

PlEAD IN

DIM:

INACTIVE

MATCH 'OUND

ON IYTlII

Figure 18. Bus Release When Not Ready
(Burst Mode'

60

Figure 19. Bus Release on Match
(Burst and Continuous Modes)

2032-0140,0141, 0142, 0143

Absolute
Maximum
Ratings

Test
Conditions

Operatmg AmbIent
Temperature Under BIas

Stresses greater than those hsted under Absolute MaxI·

.. As Speclhed Under
Ordermg Informahon.
Storage Temperature. . . . .
-65°C to + 150°C
Voltage On Any Pm wIth
Respect to Ground .
. .. -0.3 V to + 7.0 V
Power Dlsslpahon ................... 1.5 W

mum Ratmgs may cause permanent damage to the devIce.

The charactenshcs below apply for the
followmg test condlhons, unless otherwIse
noted. All voltages are referenced to GND
(0 V). Poslhve current flows mto the referenced pm. AvaIlable operahng temperature
ranges are:
• S* = ooe to +70 oe,
+4.75 V ~ Vee ~ +5.25 V

All ac parameters assume a load capacItance
of 100 pF max. Tlmmg references between two
output sIgnals assume a load dIfference of 50
pF max.

ThIS IS a stress rahng only, operation of the devIce at any
condItion above those mdicated In the operational secbons
of these specifIcations IS not Imphed Exposure to absolute
maXImum rating condItIons for extended penods may affect
devlCe relIabIlIty

+6V

• E* = -40°C to +85°e,
+4.75 V ~ Vee ~ +5.25 V

I

• M* = -55°C to + 125°C,
+4.5 V ~ Vee ~ +5.5 V
* See

i

Ordermg Informahon sechon for package

temperature range and product number

DC
Characteristics

Min

Max

Clock Input Low Voltage

-0.3

0.45

V

Clock Input High Voltage

Vee -· 6

5.5

V

Input Low Voltage

-0.3

O.S

V

VIH

Input HIgh Voltage

2.0

5.5

V

VOL

Output Low Voltage

0.4

V

IoL = 3.2rnA for BUSREQ
IOL = 2.0 rnA for all others

V

IoH

Symbol

Parameter

VILe
VIHe
VIL

VOH

Output HIgh Voltage

Icc

Power Supply Current
Z-SO DMA
Z-SOA DMA

ILl

Input Leakage Current

ILOH
ILOL

3-State Output Leakage Current

In

Float

3-State Output Leakage Current

In

Float

ILD

Data Bus Leakage Current

vee
Capacitance

=

In

150
200

rnA
rnA

10

"A
"A
"A
"A

10

-10

Input Mode

± 10

= 250"A

= 0 to Vee
= 2.4 to Vee
VOUT = 0.4 V
VIN

VOUT

OsVINsVee

5 V ± 5% unless otherWIse speCIfIed, over specifIed temperature range

Symbol

Parameter

Min

Max

Unit

Test Condition

C

Clock CapacItance

35

pF

Unmeasured PinS

~N
C OUT

Input CapaCitance

5

pF

Returned to Ground

10

pF

Output CapaCitance

Over speCIfied temperature range,

8085·0209

2.4

Unit Test Condition

f = 1 MHz

61

Inactive
State
AC
Characteristics

Number Symbol

Parameter

TcC
Clock Cycle Time
2
TwCh
Clock Width (High)
Clock Width (Low)
3
TwCI
4
TrC
Clock Rise Time
- 5-TfC
Clock Fall Time
6
Th
Hold Time for Any Specified Setup Time
TsC(Cr}
7
IORQ, WR, CE I to Clock I Setup
TdDO(RDf)
8
RDI to Data Output Delay
9
TsWM(Cr}
Data In to Clock I Setup (WR or MI)
--10- TdCf(DO}--IORQ I to Data Out Delay (INTA Cycle)
TdRD(Dz}
11
RD I to Data Float Delay (output buffer
disable)
TsIEI(IORQ}
12
IEII to IORQ I Setup (INTA €:ycle)
13
TdIEOr(IElr}
lEI I to lEO I Delay
14
TdIEOf(IEIf}
lEI I to lEO I Delay
_15 _ TdMl(IEO} _MI I to lEO I Delay (interrupt just prior to
Mil)
16
TsMlf(Cr}
MI I to Clock I Setup
17
TsMlr(Cf)
MI I to Clock I Setup
18
TsRD(Cr}
RD I to Clock I Setup (MI Cycle)
19
TdI(INT}
Interrupt Cause to INT I Delay (INT generated
only when DMA is inactive)
_20 _ TdBAlr(BAOr}-BAI I to BAO I Delay
21
TdBAIf(BAOf) BAI I to BAO I Delay
22
TsRDY(Cr}
RDY Active to Clock I Setup
NOTE
1 NegatIve minImUm setup values mean that the

62

hrst~mentIoned

Z-80 DMA

Z-80ADMA

Min Max

Min

400 4000
170 2000
170 2000
30
30
0
280
500
50
340

250 4000
ns
110 2000
ns
110 2000
ns
30
ns
30--ns0
ns
145
ns
380
ns
50
ns
160--ns-

160
140

110
140

210
190

160
130

300
210
20
240

190
90
-10
115

500
200
200
150

Max

100

event can come after the second·menhoned event

Unit

ns
ns
ns
ns
ns
ns
ns
ns

500
ns
150--ns150
ns
ns

Inactive
State
AC
Characteristics

"1"
"0"
CLOCK
42Y oaY
OUTPUT 20 V 0.8 V
INPUT
20V oav

eLK

(Contmued)
Ci
lORa

Yiii

iii)

Do-D7

ii1

,.,

i
E

lEO

iiiT

INTIRRUPT
CONDITION

iAI

BAO

ACTIVE

RDY
INACTIVE

NOTE

SIgnals

2032-0144

In

thIS dlagram bear no relation to one another unless specIfIcally noted as a numbered ltem

63

Active
State
AC
Characteristics

Number Symbol

Parameter

1
TcC
Clock Cycle Time
2
TwCh
Clock Width (High)
TwCl
Clock Width (Low)
3
4
TrC
Clock Rise Time
-5--TfC---Clock Fall Time
Address Output Delay
6
TiiA
7
TdC(Az)
Clock I to Address Float Delay
TsA(MREQ) Address to MREQ J Setup (Memory Cycle)
8
TsA(IRW)
9
Address Stable to IORQ, RD, WR J Setup
(IIO Cycle)
--.!.IO--TdRW(A)--RD, WR I to Addr. Stable Delay
'll
TdRW(Az) RD, WR I to Addr. Float
TdCf(DO)
Clock J to Data Out Delay
12
TdCr(Dz)
Clock I to Data Float Delay (Write Cycle)
'13
TsDI(Cr)
Data In to Clock I Setup (Read cycle when
14
rlsmg edge ends read)
-15-TsDI(Cf)--Data In to Clock J Setup (Read cycle when
falling edge ends read)
'16
TsDO(WfM) Data Out to WR J Setup (Memory Cycle)
17
TsDO(WfI) Data Out to WR J Setup (IIO cycle)
TdWr(DO) WR I to Data Out Delay
'18
19
Th
Hold Time for Any SpeCified Setup Time
-20-TdCf(Mf)-Clock J to MREQ J Delay
TdCr(Mr)
Clock I to MREQ I Delay
21
TdCf(Mr)
22
Clock J to MREQ I Delay
23
TwMl
MREQ Low Pulse Width
'24
TwMh
MREQ High Pulse Width
-25-TdCr(If)-Clock I to IORQ J Delay
TdCr(Ir)
Clock I to IORQ I Delay
26
'27
TdCf(Ir)
Clock J to IORQ I Delay
TdCr(Rf)
28
Clock I to RD J Delay
TdCf(Rf)
29
Clock J to RD J Delay
-30-TdCr(Rr)--Clock I to RD I Delay
TdCf(Rr)
Clock J to RD I Delay
31
TdCr(Wf)
32
Clock I to WR J Delay
33
TdCf(Wf)
Clock I to WR I Delay
34
TdCr(Wr)
Clock I to WR I Delay
-35-TdCf(Wr)--Clock I to WR I Delay
36
TwWl
WR" Low Pulse Width
TsWA(Cf) W1!JT to Clock I Setup
37
TdCr(B)
Clock I to BUSREQ Delay
38
TdCr(Iz)
39
Clock I to IORQ, MREQ, RD, WR Float
Delay

Z-80 DMA
Min(ns) Max(ns)

400
180
180

Z-SOADMA
Min(ns) Max(ns)

250
110

2000
2000
30
30
145

llO

110
90

llO
(2) +(5)-75

(2)+(5)-75

(1)-80
(3) +(4)-40
(3)+ (4)-60

(1)-70
(3) + (4)-50
(3) + (4)-45
150
90

230
90
50

35

60
(1)-210

50
(1)-170

100
(3) +(4)-80

100
(3) +(4)-70
0

0

85-

100
100
100
(1)-40
(2) +(5)-30

85
85
(1)-30
(2) +(5)-20
75-

90
100

85

llO

85

100
130
100
110
80
90
100
100

85
95
85-

(1)-40

85
65
80
80
80(1)-30

70

70
150

100

100

80

NOTES.
1.
2
3
4

64

2000
2000
30
30-

Numbers In parentheses are other parameter~numbers in thls table, theIr values should be substItuted m equatIons.
All equallons lmply DMA default (standard) Ilmmg
Data must be enabled onto data bus when RD IS actIve.
AsterIsk (*) before parameter number means the parameter IS not Illustrated In the AC TIming DIagrams

Aetive
State
AC
Charaeteristies
(Continued)

eLK

f

INPUT

DO-D'louTPUT

----++----++-------++-----+----++,_it+----i--i-t-t--\.
-----H----~------~~------+---~~-~----+__r~~~

iiiii

I

..

II

iii

Wii

iOiiQ

iii

Wii

WAIT

aU.REG

NOTE
Signals

2032-0145

In

this diagram bear no relatIon to one another unless speclhcally noted as a numbered Item.

65

Ordering
Information

Product
Number

Package/
Speed
Temp

Description

Product
Number

Description

28410

CE

2.5 MHz

280 DMA (40-pin)

28410A

CE

4.0 MHz

280A DMA (40-pm)

28410

CM

2.5 MHz

Same as above

28410A

CM

4.0 MHz

Same as above

28410

CMB

2.5 MHz

Same as above

28410A

CMB

4.0 MHz

Same as above

28410

CS

2.5 MHz

Same as above

28410A

CS

4.0 MHz

Same as above

28410

DE

2.5 MHz

Same as above

28410A

DE

4.0 MHz

Same as above

28410

OS

2.5 MHz

Same as above

28410A

OS

4.0 MHz

Same as above

28410

PE

2.5 MHz

Same as above

284 lOA

PE

4.0 MHz

Same as above

28410

PS

2.5 MHz

Same as above

28410A

PS

4.0 MHz

Same as above

'NOTES: C = CeramIc. D = Cerdlp, P = Plashc; E = -40'C to + 85'C, M
MIL-STD-883, Class B processing, S ::::: ooe to + 70°C.

66

Package/
Temp
Speed

= -55'C

to + 125'C, MB

= -55'C

to + 125'C wIth

00-2032-A

Z8420
Z80® PIO Parallel
Input/Output Controller

~
Zilog

Product
Specification

June 1982

Features

• ProvIdes a duect mterface between Z-80
mIcrocomputer systems and peripheral
devICes.
• Both ports have mterrupt-dnven handshake
for fast response.

General
Description

• Programmable mterrupts on peripheral
status condlhons.
• Standard Z-80 FamIly bus-request and
pnonhzed mterrupt-request daisy chams
Implemented WIthout external logIc.

• Four programmable operatmg modes: byte
mput, byte output, byte mput/output (Port A
only), and bIt mput/output.

• The 81ght Port B outputs can dnve Darlmgton transIstors (1.5 rnA at 1.5 V).

The Z-80 PIa Parallel I/O CIrCUIt IS a programmable, dual-port deVIce that provIdes a
TTL-compahble mterface between peripheral
deVICes and the Z-80 CPU. The CPU configures the Z-80 PIa to mterface WIth a wIde
range of peripheral deVIces WIth no other
external logIC. TypIcal penpheral deVICes that
are compahble WIth the Z-80 PIa melude most
keyboards, paper tape readers and punches,
prmters, PROM programmers, etc.
One characterlshc of the Z-80 peripheral
controllers that separates them from other
mterface controllers IS that all data transfer
between the penpheral deVIce and the CPU IS

accomplished under mterrupt control. Thus,
the mterrupt logIC of the PIa permIts full use
of the efficIent mterrupt capablllhes of the
Z-80 CPU durmg 110 transfers. All logic
necessary to Implement a fully nested mterrupt
structure IS meluded In the PIa.
Another feature of the PIa IS the abJ!lty to
mterrupt the CPU upon occurrence of specIfied status condlhons In the peripheral device.
For example, the PIa can be programmed to
mterrupt If any specIfied peripheral alarm condlhons should occur. ThIS mterrupt capabIlity
reduces the hme the processor must spend m
pollmg peripheral status.

PORTA

0,
0,

0,

0,

0,

ee

M1

CIO

Z·80 PIO

0,

lORa

B/A

AD

A,

B,

A,;

B,

A,

B,

A,

B,

GND

PORT B

A,

B,

A,

B,

A,

B,

""

elK

ASTB

BSTB
BSTB 1 - - -

INTERRUPT {
CONTROL
lEO

Figure I. Pin Functions
2006·0297. 0298

HV
lEI

ARDY

INT

0,

lED

0,

BRDY

Figure 2. Pin Assignments

67

General
Description
(Contmued)

The Z-80 PIO mterfaces to perIpherals Vla
two independent general-purpose I/O ports,
deslgnated Port A and Port B. Each port has
elght"data blts and two handshake slgnals,
Ready and Strobe, whlch control data transfer.
The Ready output mdlcates to the perIpheral
that the port lS ready for a data transfer.
Strobe lS an mput from the perIpheral that
mdlcates when a data transfer has occurred.

Operating Modes. The Z-80 PIO ports can be
programmed to operate in four modes: byte
output (Mode 0), byte mput (Mode 1), byte
mput/output (Mode 2) and blt mput/output
(Mode 3).
In Mode 0, elther Port A or Port B can be
programmed to output data. Both ports have
output registers that are indlvldually addressed
by the CPU; data can be WrItten to elther port
at any hme. When data lS WrItten to a port, an
achve Ready output mdlCates to the external
device that data lS avallable at the assoclated
port and lS ready for transfer to the external
devlce. After the data transfer, the external
devlce responds wlth an achve Strobe mput,
whlch generates an interrupt, J! enabled.
In Mode I, elther Port A or Port B can be
conhgured m the mput mode. Each port has
an mput reglster addressed by the CPU. When
the CPU reads data from a port, the PIO sets
the Ready slgnal, which lS detected by the
external devlce. The external device then
places data on the I/O lmes and strobes the
1/0 port, whlCh latches the data into the Port
Input Reglster, resets Ready, and trIggers the
Interrupt Request, If enabled. The CPU can
read the mput data at any hme, whlCh again
sets Ready.
Mode 2 lS bldJrechonal and uses Port A,
plus the mterrupts and handshake slgnals from
both pmts. Port B must be set to Mode 3 and
masked off. In operahon, Port A lS used for
both dala mput and output. Output operation
lS slmdar to Mode 0 except that data lS allowed
out onto the Port A bus only when ASTB lS
Low. For mput, operahon lS simllar to Mode I,
except that the data mput uses the Port B
handshake slgnals and the Port B mterrupt (If
enabled).
Both ports can be used m Mode 3. In this
mode, the mdlvldual blts are defmed as elther
mput or output blts. Thls provldes up to elght
separate, mdlvldually defined blts for each
port. Durmg operahon, Ready and Strobe are

68

not used. Instead, an mterrupt lS generated J!
the condltlOn of one mput changes, or If all
mputs change. The reqUlrements for generahng an mterrupt are defmed durmg the programmmg operahon; the achve level lS
speclhed as elther Hlgh or Low, and the loglc
condlhon lS speclhed as elther one input active
(OR) or all mputs achve (AND). For example,
If the port lS programmed for achve Low
mputs and the loglc funchon 's AND, then all
mputs at the speclhed port must go Low to
generate an mterrupt.
Data outputs are controlled by the CPU and
can be WrItten or changed at any hme.
• Indlvldual bIts can be masked off.
• The handshake signals are not used m
Mode 3; Ready lS held Low, and Strobe lS
dlsabled.
• When usmg the Z-80 PIO interrupts, the
Z-80 CPU mterrupt mode must be set to
Mode 2.
SYSTEM
BUSES

+5V

CPU

iNT

PIO

I

INT

lEI
+5V

T
lEI

ZC/T01

CTC

WIRDYB

510

-

lEO
INT

lEI

ROY

DMA

Figure 3. PIO In a Typical zao Family Environm~nt

2041·0156

Internal
Structure

The internal structure of the Z-80 PIO conSiStS of a Z-80 CPU bus interface, mternal controlloglc, Port A I/O logic, Port B I/O logiC,
and mterrupt control logic (Figure 4). The
CPU bus mterface logiC allows the Z-80 PIO to
mterface directly to the Z-80 CPU with no
other external logIC. The internal control logIC
synchronizes the CPU data bus to the peripheral deVice mterfaces (Port A and Port B).
The two I/O ports (A and B) are virtually
idenhcal and are used to interface directly to
penpheral devices.

Port Logic. Each port contams separate mput
and output registers, handshake control logic,
and the control registers shown m Figure 5.
All data transfers between the peripheral unit
and the CPU use the data mput and output
registers. The handshake logiC associated With
each port controls the data transfers through
the mput and the output registers. The mode
control register (two bits) selects one of the
four programmable operahng modes.
The control mode (Mode 3) uses the remammg registers. The input/output control register
speCifies which of the eight data bils in the
port are to be outputs and enables these bits;
the remaining bits are inputs. The mask regIster and the mask control register control
Mode 3 interrupt conditions. The mask register
specifies which of the bits in the port are
achve and which are masked or inactive.

The mask control register speCifies two
conditions: first, whether the active state of
the input bits IS High or Low, and second,
whether an mterrupt IS generated when any
one unmasked mput bit IS achve (OR condition) or If the interrupt IS generated when
all unmasked mput bits are achve (AND
condl tion) .

Interrupt Control Logic. The interrupt control
logic sechon handles all CPU mterrupt protocol for nested-priority mterrupt structures.
Any devICe's physical location m a daisy-chain
configuration determmes ItS pnority. Two lines
(lEI and IEO) are provided in each PIO to
form this daiSY cham. The deVICe closest to the
CPU has the highest Priority. Withm a PIO,
Port A mterrupts have higher priority than
those of Port B. In the byte mput, byte output,
or bidlrechonal modes, an mterrupt can be
generated whenever the peripheral requests a
new byte transfer. In the bit control mode, an
interrupt can be generated when the peripheral status matches a programmed value. The
PIO prOVides for complete control of nested
mterrupts. That IS, lower prionty deVICes may
not mterrupt higher prlonty deVICes that have
not had their mterrupt servICe routines completed by the CPU. Higher priority deVICes
may interrupt the servicmg of lower priority
devices.

DATA
OR CONTROL
} HANDSHAKE

P.RIPHERAL
INTERFACE
DATA
OR CONTROL
} HANDSHAKE

INTERRUPT CONTROL LINES

Figure 4. Block Diagram

2006-0316

69

II

S

Internal
Structure
(Contmued)

If the CPU (m mterrupt Mode 2) accepts an
mterrupt, the mterruptmg devICe must provIde
an 8-blt mterrupt vector for the CPU. ThIs vector forms a pomter to a 10catlOn m memory
where the address of the mterrupt service
routine is located. The 8-blt vector from the
interruphng devIce forms the least slgmhcant
81ght bIts of the mdirect pointer while the
I RegIster m the CPU provIdes the most slgmhcant eight bits of the pomter. Each port (A and
B) has an mdependent mterrupt vector. The
least slgmficant bit of the vector IS automahcally set to 0 wlthm the PIa because the
pointer must pomt to two adjacent memory
locahons for a complete 16-blt address.
Unhke the other Z-80 penpherals, the PIa
does not enable mterrupts Immedldtely after
programmmg. It walts unhl MI goes Low (e.g.,
durmg an opcode fetch). This condlhon IS
ummportant in the Z-80 envIronment but mIght
not be if another type of CPU IS used.
The PIa decodes the RET! (Return From

Interrupt) mstruchon dIrectly from the CPU
data bus so that each PIa m the system knows
at all hmes whether It IS bemg servICed by the
CPU mterrupt servIce rouhne. No other commumcahon with the CPU is reqUIred.

CPU Bus 1/0 Logic. The CPU bus interface
logic mterfaces the Z-80 PIa directly to the
Z-80 CPU, so no external logic is necessary.
For large systems, however, address decoders
and/or buffers may be necessary.
Internal Control Logic. ThIs logic receives the
control words for each port durmg programming and, m turn, controls the operating funchons of the Z-80 PIa. The control logic synchronizes the port operations, controls the port
mode, port addressing, selects the read/write
function, and issues appropriate commands to
the ports and the mterrupt logIC. The Z-80 PIa
does not receive a write input from the CPU;
instead, the RD, CE, ciI5 and IORQ signals
generate the write input internally.

MODE
CONTROL
REGISTER
(2 BITS)

8-BIT 110 BUS

MASK
CONTROL

REGISTER
(2 BITS)

HAND.
SHAKE
CONTROl.
LOGIC

READY

}

HANDSHAKE
STROBE

CONTROL

·Used In the bit mode only to allow generation of an
Interrupt It the peripheral I/O pins go to the specified state.

Figure 5. Typical Pori 1/0 Block Diagram

70

2006·0317

Programming Mode O. 1. or 2. (Byte Input, Output, or
BJdirectJOnal). Programming a port for Mode
0, I, or 2 requires two words per port. These
words are:
A Mode Control Word. Selects the port operahng mode
(F,gure 6). Th,s word may be WrItten any hme.
An Interrupt Vector. The Z-80 PIO IS desIgned for use wIth
the Z-OO CPU In Interrupt Mode 2 (F,gure 7). When Interrupts are enabled, the PIO must provIde an Interrupt
vector.

Mode 3. (Bit Input/Output). Programming a
port for Mode 3 operation requires a control
word, a vector (If interrupts are enabled), and
three additional words, described as follows:
ItO RegIster Control. When Mode 3 IS selected, the mode
control word must be followed by another control word that
sets the 110 control regIster, whIch In turn defInes whlCh
port lInes are Inputs and whIch are outputs (FIgure 8).

11

Interrupt Control Word. In Mode 3, handshake IS not
used. Interrupts are generated as a logIC funchon of the
mput SIgnal levels. The mterrupt control word sets the
logIC condlhons and the lOgIC levels reqUIred for generatmg an mterrupt. Two logIC condItIons or funchons are
avaIlable: AND (If all Input b,ts change to the achve level,
an mterrupt IS trIggered), and OR (If anyone of the Input
b,ts changes to the achve level, an Interrupt IS trIggered).
BIt De sets the logIC funchon, as shown m F,gure 9. The
achve level of the Input b,ts can be set eIther HIgh or Low.
The achve level IS controlled by BIt DS'
Mask Control Word. Th,s word sets the mask control
regIster, allOWIng any unused bIts to be masked off If any
b,ts are to be masked, then D4 must be set. When D4 is set,
the next word WrItten to the port must be a mask control
word (F,gure 10).

Interrupt Disable. There is one other control
word whICh can be used to enable or disable a
port interrupt. It can be used without changing
the rest of the interrupt control word
(Figure 11).

1",1001·,1·.1, I, I, I, I

c,_O"_,
CONTROL WORD

DON"T CARE

III

S

=::::::::.~

c

04

=

1 MASK WORD FOLLOWS

Ds = 0 ACTIVE LEVEL IS lOW
D6 "" 1 ACTIVE LEVEL IS HIBH

MODE SELECT

MODEO
MODE 1
MODE2
MODE 3

D6 '" 0 INTERRUPT ON OR FUNCTION
De = 1 INTERRUPT ON AND FUNCTION
L -_ _ _ _ _ _ _

~

:

~ ::~~::~~ ~~::~::.

-NOTE. THE PORT IS NOT ENABLED UNTIL
THE INTERRUPT ENABLE IS FOLLOWED
BY AN ACTIVE iiFi

Figure 6. Mode Control Word

Figure 9. Interrupt Control Word

1"'lo.IDeIDeIDeIDeI~IOI

L IDENTIFIES INTERRUPT
VECTOR

L-_ _ _ _

~:~JI~PPLIED INTERRUPT

Figure 7. Interrupt Vector Word

I

MBo-Mar MASK BITS. A
BIT IS MONITORED FOR AN
L-_ _ _ _ INTERRUPT IF IT IS
DEFINED AS AN INPUT AND
THE MASK BIT IS SET TO O.

Figure 10. Mask Control Word

1T

1",1001",10010101,1,1

l"'IDeIDeIDeIDeIDeI~IDeI
0 SETS BIT TO OUTPUT
1 SETS BIT TO INPUT

L

IDENTIFlES INTERRUPT
DISABLE WORD
DON'T CARE
07 - 0 INTERRUPT DISABLE
1 INTERRUPT ENABLE
07

=

Figure 8. 1/0 Register Control Word

2006-0318,0319,0320,0321,0322,0323

II

Figure II. Interrupt Disable Word

71

Pin
Description

Au-A7' Port A Bus (bldlrechonal, 3-state).
This 8-blt bus transfers data, status, or control
mformahon between Port A of the PIO and a
peripheral device. Ao is the least slgmficant
bit of the Port A data bus.
AHOY. RegIster A Ready (output, active
High). The meanmg of this signal depends on
the mode of operation selected for Port A as
follows:
Output Mode. ThIs sIgnal goes achve to mdlCate that the
Port A output regIster has been loaded and the peflpheral
data bus IS stable and ready for transfer to the peflpheral
deVICe.

Input Mode. ThIS sIgnal IS acbve when the Port A mput
regIster IS empty and ready to accept data from the
peflpheral deVIce.
Bldirechonal Mode. ThIS SIgnal IS acbve when data IS
avaIlable m the Port A output regIster for transfer to the
pSflpheral devlCe In thIS mode, data IS not placed on the
Port A data bus, unless ASTB IS acbve.
Control Mode. ThIS Slgnal IS dIsabled and forced to a Low
state.

ASTB. Port A Strobe Pulse From PerIpheral
DeVIce (input, active Low). The meaning of
thiS signal depends on the mode of operation
selected for Port A as follows:
Output Mode. The poslbve edge of thIS strobe IS ISSUed by
the peflpheral to acknowledge the receIpt of data made
avaIlable by the PIO
Input Mode. The strobe IS Issued by the peflpheral to load
data from the peflpheral mto the Port A mput regIster.
Data IS loaded mto the PIO when thIS sIgnal IS acbve
Blduechonal Mode. When thiS slgnal IS achve, data from
the Pori A output regIster IS gated onto the Port A bldlrechonal data bus. The poslbve edge of the strobe acknowledges the receIpt of the data.

Control Mode. The strobe IS mhlblted mternally.
BO-~' Port B Bus (bidirectional, 3-state). This
8-blt bus transfers data, status, or control
information between Port B and a peripheral
deVICe. The Port B data bus can supply
1.5 rnA at 1.5 V to drive Darlington transistors.
Bo is the least significant bit of the bus.
B/A. Port B Or A Select (mput, High = B).
ThIS pin defmes whICh port is accessed durmg
a data transfer between the CPU and the PIO.
A Low on this pin selects Port A; a High
selects Port B. Often address bit Ao from the
CPU is used for thiS selection function.

BHOY. RegIster B Ready (output, active High).
This signal is Similar to ARDY, except that in
the Port A bidirechonal mode thiS Signal IS
High when the Port A input register is empty
and ready to accept data from the peripheral
deVICe.

BSTB. Port B Strobe Pulse From Peripheral
Device (mput, active Low). ThiS signal IS
similar to ASTB, except that in the Port A
bidirectional mode this Signal strobes data
from the peripheral deVICe mto the Port A
input register.

72

C/D. Control Or Data Select (mput,
High = C). This pin defines the type of data
transfer to be performed between the CPU and
the PIO. A High on this pin durmg a CPU
write to the PIO causes the Z-80 data bus to be
mterpreted as a command for the port selected
by the BfA Select lme. A Low on thiS pin
means that the Z-80 data bus is bemg used to
transfer data between the CPU and the PIO.
Often address bit Al from the CPU is used for
thiS function.
CEo ChIp Enable (mput, active Low). A Low
on this pm enables the PIO to accept command or data mputs from the CPU during a
write cycle or to transmIt data to the CPU durmg a read cycle. ThiS Signal IS generally
decoded from four 1/0 port numbers for Ports
A and B, data, and control.
CLK. System Clock (mput). The Z-80 PIO uses
the standard smgle-phase Z-80 system clock.

Do-D? Z-80 CPU Data Bus (bidirectional,
3-state). ThiS bus IS used to transfer all data
and commands between the Z-80 CPU and the
Z-80 PIO. Do is the least sigmficant bit.
lEI. Interrupt Enable In (mput, active High).
ThiS signal IS used to form a Prlorlty-mterrupt
daiSY cham when more than one interruptdriven device is bemg used. A High level on
this pm indICates that no other devices of
higher priority are being serviced by a CPU
mterrupt servICe routme.
lEO. Interrupt Enable Out (output, active
High). The lEO signal IS the other signal
reqUIred to form a daisy chain priority scheme.
It IS High only If lEI is High and the CPU is
not servICmg an mterrupt from thiS PIO. Thus
this Signal blocks lower priOrity devices from
interruptmg while a higher Priority deVICe IS
being serviced by ItS CPU interrupt service
routme.
INT. Interrupt Request (output, open drain,
active Low). When INT is active the Z-80 PIO
IS requesting an interrupt from the Z-80 CPU.
IOHQ. Input/Output Request (input from Z-80
CPU, active Low). IORQ is used in conJunction With BiA, cin, CE, and RD to transfer
commands and data between the Z-80 CPU and
the Z-80 PIO. When CE, RD, and IORQ are
active, the port addressed by B/A transfers
data to the CPU (a read operation). Conversely, when CE and IORQ are active but RD
is not, the port addressed by B/A is written
mto from the CPU With either data or control
information, as speCified by C/O. Also, if
IORQ and Ml are active SImultaneously, the
CPU IS acknowledging an interrupt; the mterruptmg port automatically places Its interrupt
vector on the CPU data bus if It is the highest
priority deVice requesting an mterrupt.

Pin
Description
(Contmued)

Timing

Ml. Machme Cycle (mput from CPU, acllve
Low). ThIs sIgnal IS used as a sync pulse to
control several mternal PIO operallons. When
both the Ml and RD sIgnals are acllve, the
Z·80 CPU IS fetchmg an mstructlOn from
memory. Conversely, when both Ml and
10RQ are acllve, the CPU IS acknowledgmg
an mterrupt. In addlllon, Ml has two other
functIOns wlthm the Z·80 PIO: It synchromzes
The follOWing timing diagrams show typical
hmmg in a Z-80 CPU environment. For more
preCIse speCifications refer to the composite
ac hmmg diagram.
Write Cycle. Figure 12 Illustrates the
hming for programmmg the 2-80 PIO
or for writing data to one of its ports. No
Wait states are allowed for wrihng to the
PIO other than the automatically inserted
TWA. The PIO does not receive a specific write Signal; it internally generates
its own from the lack of an active
RD signal.

the PIO mterrupt logIc, when Ml occurs
wIthout an acllve R"o or lemQ sIgnal, the PIO
IS reset.
RD. Read Cycle Status (mput from Z·80 CPU,
acllve Low). If R"o IS acllve, or an 110 opera·
tlOn IS m progress, RD IS used WIth BIll., cio,
CE, and fORQ to transfer data from the Z·80
PIO to the Z·80 CPU.

T,

T,

T,

TWA

T,

eLK

C/O. B/A

=x

x::=

Ci
lORa

\

DATA

X

r-

\

WR'

'WR

= RD.

E
s•

x=
r-

IN

CE • C/D • IORQ

Figure 12. Write Cycle Timing

Read Cycle. Figure 13 illustrates the hming
for reading the data input from an external
device to one of the 2-80 PIO ports. No Wait
states are allowed for reading the PIO other
than the automatically inserted TWA.
Output Mode (Mode 0). An output cycle
(Figure 14) is always started by the execution
of an output instruchon by the CPU. The WR*
pulse from the CPU latches the data from the
CPU data bus into the selected port's output
regIster. The WR* pulse sets the Ready flag
after a Low-going edge of CLK, indicating
data is available. Ready stays active until the
positive edge of the. frobe lme is receIved,
indicating that data WdS taken by the peripheral. The positive edge of the strobe pulse
generates an INT if the interrupt enable flipflop has been set and if this device has the
highest prionty.

T,

T,

T,

TWA

T,

eLK

eli), BIA

Ci

=x

x:=

\

r
\
\

IORQ

AD

I
I
(

DATA

\

RD·
'RD

= RD'

)-

OUT

I

CE • C/D • IORQ

Figure 13. Read Cycle Timing

eLK

PORT
OUTIIUT

READY

'WR

= RD •

CE • C/D • IORQ

Figure 14. Mode 0 Output Timing
2006·0324, 0325. 0326

73

Timing
(Continued)

Input Mode (Mode I). When STROBE goes
Low, data is loaded into the selected port input
register (FIgure 15). The next rlsing edge of
strobe activates INT, if Interrupt Enable is set
and this is the highest-priority requesting
device. The following falling edge of CLK
resets Ready to an inactive state, indicating

• RD

= RD.

that the input register is full and cannot accept
any more data until the CPU completes a read.
When a read is complete, the positive edge of
RD sets Ready at the next Low-going transition
of CLK. At this time new data can be loaded
into the PIO.

CE • C/D • IORQ

Figure 15. Mode I Input Timing

Bidirectional Mode (Mode 2). This is a combination of Modes 0 and 1 using all four handshake lines and the eight Port A I/O lines
(Figure 16). Port B must be set to the bit mode
and its inputs must be masked. The Port A
handshake lines are used for output control
and the Port B lines are used for input control.

If interrupts occur, Port A's vector will be used
during port output and Port B's will be used
during port input. Data is allowed out onto the
Port A bus only when ASTB is Low. The rising
edge of this strobe can be used to latch the
data into the peripheral.

"RaY _ _ _ _ _ _ _ _ _---'

PQJIIT A _ _ _ _ _ _ _ _ _ _ _ _
DATA aus

-<~~~~>-----_<

8RDY

'WR

= RD.

CE • C/D • IORQ

Figure 16. Mode 2 Bidirectional Timing

74

2006·0327, 0328

Timing
(Contmued)

Bit Mode (Mode 3). The bit mode does not
uhhze the handshake sIgnals, and a normal
port wnte or port read can be executed at any
hme. When wntmg, the data IS latched mto
the output reglSters wIth the same hmmg as the
output mode (FIgure 17).
When readmg the PIO, the data returned to
the CPU IS composed of output regIster data
from those port data lmes assIgned as outputs
and mput regIster data from those port data

elK
PORT
DATA BUS

X

liT

t

i{ ;
X

DATA MATCH \
OCCURS HERE

10"Q

iiii

DO-D1

lmes assIgned as mputs. The mput regIster
con tams data that was present Immedldtely
pnor to the fallmg edge of RD. An mterrupt IS
generated If mterrupts from the port are
enabled and the data on the port data lmes
sahsfy the logIcal equatIOn defmed by the S-blt
mask and 2-blt mask control regIsters. However, If Port A 18 programmed m bldlrechonal
mode, Port B does not Issue an mterrupt m bIt
mode and must therefore be polled.

DATA WORD 2

X

------------~~(--;;:OA~TA;:;';N}------------

*Tlmmg Diagram Refers to Bit Mode Read

LOATA WORD 1 PLACED ON BUS

Figure 17. Mode 3 Bit Mode Timing

Interrupt Acknowledge Timing. Ourmg Ml
tIme, penpheral controllers are inhIbIted from
changmg their interrupt enable status, permItting the Interrupt Enable sIgnal to npple
through the ddlsy cham. The penpheral wIth
IEI HIgh and lEO Low durmg INTACK places
a preprogrammed S-blt mterrupt vector on the
data bus at thIS tIme (FIgure IS). IEO IS held
Low untIl a Return From Interrupt (RETI)
instructIon IS executed by the CPU while IEI IS
HIgh. The 2-byte RETI mstructlOn IS decoded
mternally by the PIO for thIS purpose.

lASTT

STATE

I

T

1

eLK

10.:-,:

;::_LE____±_4-~~----)::~~~tM1

110

~WlEDQ£

INTACK

~I..._ _ _ _ _ _ _ _ _ _ __

Figure 18. Interrupt Acknowledge Timing

Return From Interrupt Cycle. If a Z-SO perIpheral has no mterrupt pendmg and IS not
under serVICe, then ItS lEO = IEI. If It has an
mterrupt under servICe (I.e., It has already
mterrupted and rec81ved an mterrupt acknowledge) then ItS IEO IS always Low, mhlbltmg
lower pnonty deVICes from mterrupting. If It
has an mterrupt pendmg which has not yet
been acknowledged, lEO IS Low unless an
"ED" IS decoded as the first byte of a 2-byte
opcode (FIgure 19). In thIS case, IEO goes
HIgh untIl the next opcode byte IS decoded,
whereupon It goes Low agam. If the second
byte of the opcode was a "40," then the
opcode was an RETI mstructIon.
After an "ED" opcode IS decoded, only the
penpheral deVIce whIch has mterrupted and IS
currently under servICe has Its IEI HIgh and its

IEO Low. ThIS deVIce IS the hlghest-pnonty
deVICe m the daISY chain that has receIved an
mterrupt acknowledge. All other penpherals
have IEI = lEO. If the next opcode byte
decoded IS "40," thIS penpheral devICe resets
ItS "interrupt under servICe" condition.

Do-D,.

110

----------------~;---Figure 19. Return From Interrupt

2006·0329, 0330, 0331

75

AC
Characteristics
CLOCI<

CE

BlA, c/o

Do-D7

f

OUT

liN

lEI

lEO

READY
tARDY OR BRDY)

STROBE
IASTB OR B5TB)

MODE 0

MODE 1

MODE 2

MODE 3

76

2006·0332

Number Symbol

Parameter

Z-80 PIO
Min Max
(ns)
(ns)

Clock Cycle Time
400
Clock WIdth (High)
170
Clock WIdth (Low)
170
Clock Fall TIme
Clock Rise Time
CE, BIA, C/O to RD,
IORQ I Setup Time
50
Th
Any Hold TImes lor Specihed
7
Setup TIme
0
TsRI(C)
RD, IORQ to Clock t Setup
8
Time
115
9 -TdRI(DO) --RD, IORQ Ito Data Out Delay
TdRI(DOs)
RD, IORQ t to Data Out Float
10
Delay
TsDI(C)
Data In to Clock t Setup Time
II
50
TdIO(DOI)
IORQ I to Data Out Delay
12
(INTACK Cycle)
340
13 - TsMI(Cr) - - MI I to Clock t Setup Tlme--210
TsMl(Cf)
14
MI-.-Lto Clock I Setup TIme
(MI Cycle)
0
TdMl(IEO)
MI I to IEO I Delay (Interrupt
15
Immediately Precedmg MI I)
TsIEI(IO)
16
IEI to IORQ I Setup Time
(INTACK Cycle)
140
17 -TdIEI(IEOf)-IEI I to IEO I Delay
TcC
2
TwCh
3
TwCI
4
TIC
5-TrC
TsCS(RI)
6

18

[1]

2000
2000
30
30

Z-80A PIO
Min Max
(ns)
(ns)

Z-80B PIO[g]
Min Max
(ns)
(ns)

250
105
105

165
65
65

[1]

2000
2000
30
30

50

50

0

0

115
430

[I]
2000
2000
20
20
[6]
0

70
380

160

Comment

110
50

[2]--

300
70

N

CL

40

160
90

120
70

[3]

0

0

[8]

300

190
140

[5,7]

100
100

190

130

120

210

160

160

[7]
[5]CL = 50 pF

TdIEI(IEOr)

IEI t to IEO t Delay (after ED
Decode)
TcIO(C)
19
IORQ t to Clock I Setup TIme
(To Achvate READY on Next
220
Clock Cycle)
20 -TdC(RDYr)-Clock I to READY t Delay--200

200
190

[5]

170
170

[5]-

CL
21
22
23

24
25
26
27
28
29

= 50 pF

TdC(RDYf)
TwSTB
TsSTB(C)

Clock I to READY t Delay
150
STROBE Pulse WIdth
150
STROBE t to Clock I Setup
TIme (To Activate READY on
Next Clock Cycle)
220
-TdIO(PD)-- IORQ t to PORT DATA Stable
Delay (Mode 0)
TsPD(STB)
PORT DATA to STROBE t
Setup Time (Mode 1)
260
TdSTB(PD)
STROBE I to PORT DATA
Stable (Mode 2)
-TdSTB(PDr)- STROBE t to PORT DATA Float
Delay (Mode 2)
TdPD(INT)
PORT DATA Match to INT I
Delay (Mode 3)
TdSTB(INT)
STROBE t to INT I Delay

NOTES
[I] TcC = TwCh + TwCI + TrC + TfC.
[2] Increase TdRl(DO) by 10 ns for each 50 pF mcrease m load
up to 200 pF max.
[3) Increase TdIO(DOI) by 10 os for each 50 pF, mcrease In
loading up to 200 pF max.
[4] For Mode 2. TwSTB > TsPD(STB)
[SJ Increase these values by 2 os for each 10 pF Increase m
loadmg up to 100 pF max.

= 50 pF

140
150

120
120

[5]
[4]

220

150

[5]

200

180
230

160

[5]

[5]

190

230

210

180

200

180

160

540
490

490
440

430
350

CL

= 50 pF

[61 TsCS{RI) may be reduced. However, the hme subtracted
from TsCS(RI) wIll be added to TdRI(DO).
[7] 2.5 TcC > (N-2)TdIEI(lEOf) + TdMl(lEO) + TsIEI(lO)
..:t..TTL Buffer Delay, If any.
[8] Ml must be active for a mInImUm of two clock cycles to
reset the PIO.
[9J zaOB PIO numbers are prehmmary and subject to change.

77

I

•0

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3Vto +7.0V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + ISO °C

Stresses greater than those hsted under Absolute MaxImum Ratmgs may cause permanent damage to the devIce.
Th,s IS a stress ratmg only; operatlOn of the devlCe at any
condlllon above those mdlCated m the operahonal sechons
of these speClhcahons IS not Imphed. Exposure to absolute
maxImum rahng condlllons for extended perlods may affect
device rehablhty.

Test
Conditions

The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:

All ac parameters assume a load capacitance
of 100 pF max. Timing references between two
output signals assume a load difference of
50 pF max.
+.v

• S* = O°C to + 70°C,
+4.75 V!S Vee!S +5.25 V
• E* = -40°C to +85°C,
+4.75 V!S Vee!S +5.25 V
• M* = -55°C to + 125°C,
+4.5 V!S Vee!S +5.5 V

21K

"'See Ordermg Informahon sechon for package
temperature range and product number

DC
Characteristics

Symbol
VILe
VIHe
V1L
VIH
VOL
VOH
ILl
Iz
Ice
IOHD

Parameter
Clock Input Low Voltage
Clock Input High Voltage
Input Low Voltage
Input H,gh Voltage
Output Low Voltage
Output H,gh Voltage
Input Leakage Current
3-State Output/Data Bus Input Leakage Current
Power Supply Current
Darhngton Dnve Current

Min

Max

-0.3 +0.45
Vee-0.6 +5.5
-0.3 +0.8
+2.0 +5.5
+0.4
+2.4
-10.0 +10.0
-10.0 +10.0
100.0
-1.5
3.8

Unit
V
V
V
V
V
V

Test Condition

rnA
rnA

IoL = 2.0 rnA
IoH = -250 pA
oxPxT. The minimum lImer resolution IS 16xc/> (4 p.s with a 4 MHz clock). The
maximum timer mtervahs 256 x c/> x 256 (16.4 ms
with a 4 MHz clock). For longer mtervals
timers may be cascaded.

Interrupt Vector Programming. If the 2-80
CTC has one or more mterrupts enabled, It
can supply mterrupt vectors to the 2-80 CPU.
To do so, the 2-80 CTC must be pre-programmed with the most·Slgnlhcant hve bits of
the mterrupt vector. Programmmg consists of
wrltmg a vector word to the I/O port correspondmg to the 2-80 CTC Channel o. Note
that Do of the vector word IS always zero, to
distingUish the vector from a channel control
word. D] and D2 are not used m programmmg
the vector word. These bits are supplied by
the mterrupt logIC to Identify the channel
requestmg mterrupt servICe with a unique
mterrupt vector (Figure 7). Channel 0 has the
highest prIOrity.

V7-V3~

SUPPLIED
BY USER

~

0 ... INTERRUPT VECTOR WORD
1 '" CONTROL WORD
CHANNEL IDENTIFIER

(AUTOMATICALLY INSERTED

BY CTC)

o
o

0

1

1 '" CHANNEL 3

= CHANNEL 0

1 = CHANNEL 1
1 0 '" CHANNEL 2

Figure 6. Time Constant Word

2041-0160,0161

Figure 7. Interrupt Vector Word

85

Pin
Description

CEo Chip Enable (Input, active Low). When
enabled the CTC accepts control words, interrupt vectors, or time constant data words from
the data bus during an 1/0 write cycle; or
transmits the contents of the down-counter to
the CPU during an I/O read cycle. In most
applications this signal is decoded from the
eIght least sigmficant bits of the address bus
for any of the four 1/0 port addresses that are
mapped to the four counter-timer channels.
ClK. System Clock (Input). Standard singlephase 2-80 system clock.

ClK/TRGo-CLK/TRGa. External Clock/Timer
Trigger (Input, user-selectable active High or
Low). Four pins corresponding to the four 2-80
CTC channels. In counter mode, every active
edge on this pin decrements the down-counter.
In hmer mode, an active edge starts the timer.

CSo-CSl' Channel Select (inputs active High).
Two-bIt binary address code selects one of the
four CTC channels for an I/O wrIte or read
(usually connected to Ao and AI).

00-07. System Data Bus (bidirechonal,
3-state). Transfers all data and commands
between the 2-80 CPU and the 2-80 CTC.
SYSTEM
BUSES

CPU_

r

INT...L

1;1.

...l\

~

y
PIO

-0---

-

INT

lEI. Interrupt Enable In (Input, active High).
A High indicates that no other interrupting
devices of higher priority In the daisy chain
are being serviced by the 2-80 CPU.
lEO. Interrupt Enable Out (output, active
High). HIgh only If lEI is High and the 2-80
CPU is not servicing an interrupt from any
2-80 CTC channel. lEO blocks lower priority
devICes from interrupting whIle a higher
priority interrupting devICe is being serviced.

INT. Interrupt Request (output, open drain,
achve Low). Low when any 2-80 CTC channel
that has been programmed to enable interrupts
has a zero-count condition In its down-counter.
IORQ. Input/Output Request (input from CPU,
active Low). Used WIth CE and RD to transfer
data and channel control words between the
2-80 CPU and the 2-80 CTC. During a write
cycle, IORQ and CE are active and RD
Inachve. The 2-80 CTC does not receive a
specific write signal; rather, it Internally
generates Its own from the inverse of an active
RD sIgnal. In a read cycle, IORQ, CE and RD
are achve; the contents of the down-counter
are read by the 2-80 CPU. If IORQ and Ml are
both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places Its interrupt vector on
the 2-80 data bus.
MI. Machine Cycle One (input from CPU,
active Low). When Ml and IORQ are achve,
the 2-80 CPU is acknowledging an interrupt.
The 2-80 CTC then places an interrupt vector
on the data bus If it has highest priority, and if
a channel has requested an Interrupt (INT).

RD. Read Cycle Status (input, active Low).
lEI

Used In conJunchon WIth IORQ and CE to
transfer data and channel control words
between the 2-80 CPU and the 2-80 CTC.

RESET. Reset (input achve Low). Terminates

lEO

-

->---- iNr

$10

1;1.

lEI

ROY

DMA

J...

I"r-v'

all down-daunts and disables
resetting the Interrupt bits in
registers; the ZCITO and the
go Inactive; lEO reflects lEI;
hIgh-impedance state.

all interrupts by
all control
Interrupt outputs
Do-D7 go to the

ZC/TOo-ZC/T02. Zero Count/Timeout (output,
active HIgh). Three 2C/TO pinS corresponding
to 2-80 CTC channels 2 through 0 (Channel 3
has no ZCITO pin). In both counter and hmer
modes the output IS an achve High pulse when
the down-counter decrements to zero.

Figure 8. A Typical Z·80 Environment

86

2041-0156

Timing

Read Cycle Timing. FIgure 9 shows read
cycle hmlng. ThIS cycle reads the contents of a
down-counter wIthout disturbing the count.
During clock cycle T2, the Z-80 CPU Inihates a
read cycle by driving the following Inputs
Low: RD, IORQ, and CEo A 2-blt binary code
at inputs CS j and CSo selects the channel to
be read. Ml must be High to dIstingUIsh thIs
cycle from an Interrupt acknowledge. No addItional walt states are allowed.
T,

T,

CLIllTRO

.NTERIIAL
TI .....
______

~

START TIMING

Figure 11. Timer Mode Timing

T,

T,

TWA

latched Into the appropriate regIster wIth the
rising edge of clock cycle T3.

CLK

eso, CS1, Ci

=::x:

10RO

\ ...._ _ _

~

x:::::

CHANNEL ADDRESS

\~

~r-

______

~r-

., --"',- , . - - - - - - - - - - - - -

DATA - - - - - - - - - - (

Figure 9. Read Cycle TIming

Write Cycle Timing. Figure 10 shows write
cycle timing for loading control, time constant
or vector words.
The CTC does not have a wnte sIgnal Input,
so it generates one internally when the read
(RD) input is High during Tj. During T2
IORQ and CE Inputs are Low. MI must be
HIgh to cilshnguish a write cycle from an interrupt acknowledge. A 2-bJt binary code at
inputs CSj and CSo selects the channel to be
addressed, and the word being written is
placed on the Z-80 data bus. The data word is
T,

CSO. CS1,

CE

==:)(

T,

TWA

CHANNEL ADDRESS

T3

x::=

--r-------------.,- --,.... -------------_oJ

_oJ

___

'N__~X~

_________

Figure 10. Write Cycle Timing

2041·0162.0163.0164.0165

CLIlIT ...

IIIT.RIIAL
COUIlTEIl

----Jf

:lC/TO _ _ _ _...J

Figure 12. Counter Mode Timing

T,

AD

DATA _______~X~

Timer Operation. In the hmer mode, a
CLKlTRG pulse input starts the timer (Figure
11) on the second succeeding rising edge of
CLK. The trIgger pulse IS asynchronous, and It
must have a minimum width. A minimum lead
time (210 ns) is reqUIred between the active
edge of the CLK/TRG and the next rising edge
of CLK to enable the prescaler on the followIng clock edge. If the CLK/TRG edge occurs
closer than thIS, the Initiation of the hmer
function IS delayed one clock cycle. ThIs corresponds to the startup hmlng dIscussed In the
programming sechon. The timer can also be
started automahcally if so programmed by the
channel control word.

Counter Operation. In the counter mode, the
CLKlTRG pulse Input decrements the downcounter. The tngger is asynchronous, but the
count is synchronized WIth CLK. For the
decrement to occur on the next rIsing edQa of
CLK, the trigger edge must precede CLK by a
minimum lead hme as shown in Figure 12. If
the lead hme IS less than specified, the count
is delayed by one clock cycle. The trigger
pulse must have a minImum width, and the
trig'ger period must be at least tWICe the clock
period.
The ZC/TO output occurs immediately after
zero count, and follows the rising CLK edge.

87

Interrupt
Operation

The Z-80 eTC follows the Z-80 system mterrupt protocol for nested pnonty mterrupts and
return from mterrupt, wherem the interrupt
prlOnty of a penpheralls determined by Its
locahon m a daIsy cham. Two lines-lEI and
IEO-m the eTC connect It to the system daISY
chain. The deVIce closest to the + 5 V supply
has the hIghest prlOnty (FIgure 13). For additIOnal mformahon on the Z-80 mterrupt structure, refer to the 2-80 CPU Product SpeclhcatlOn and the 2-80 CPU Technical Manual.
HIGHEST PRIORITY
DEVICE

LOWEST PRIORITY
DEVICE

Figure 13. Daisy-Chain Interrupt Priorities

Wlthm the Z-80 eTC, mterrupt pnority IS
predetermmed by channel number: Channel 0
has the hIghest pnonty, and Channel 3 the
lowest. If a deVIce or channel is being serVICed
wIth an mterrupt routme, It cannot be mterrupted by a deVIce or channel wIth lower
pnonty unhl service is complete. Higher
pnonty deVIces or channels may mterrupt the
servicmg of lower pnonty deVIces or channels.
A Z-80 eTC channel may be programmed to
request an mterrupt every hme ItS downcounter reaches zero. Note that the CPU must
be programmed for mterrupt mode 2. Some
hme after the interrupt request, the CPU sends
an mterrupt acknowledge. The eTC mterrupt
control logic determmes the hIghest prionty
channel that IS requestmg an mterrupt. Then,
If the eTC IEI mput IS HIgh (mdICatmg that It
has pnonty wlthm the system daiSY cham) It
places an 8-blt mterrupt vector on the system
data bus. The hIgh-order hve bits of thIS vector

mmg process; the next two bits are provIded
by the eTC mterrupt control logIC as a binary
code that Idenhhes the hIghest pnonty channel requestmg an mterrupt; the low-order bit
IS always zero.

Interrupt Acknowledge Timing. FIgure 14
shows mterrupt acknowledge hming. After an
mterrupt request, the Z-80 CPU sends an mterrupt acknowledge (Ml and IORQ). All channels are mhlbited from changing theIr mterrupt request status when Ml is achve-about
two clock cycles ear her than IORQ. RD IS
HIgh to dlshnguish this cycle from an mstruction fetch.
The eTC mterrupt logIC determines the
hIghest pnonty channel requestmg an interrupt. If the eTC mterrupt enable input (lEI) IS
High, the hIghest pnonty mterruptmg channel
WIthin the eTC places its mterrupt vector on
the data bus when IORQ goes Low. Two walt
states (TWA) are automahcally mserted at this
time to allow the daISY cham to stabJ!lze. AddItional walt states may be added.
Return from Interrupt Timing. At the end of
an mterrupt serVICe routme the RET! (Return
From Interrupt) instruchon Initializes the daisy
cham enable lines for proper control of nested
pnonty mterrupt handlmg. The eTC decodes
the 2-byte RET! code mternally and determines
whether It is intended for a channel being serviced. Figure 15 shows RET! hming.
If several Z-80 penpherals are in the daiSy
chain, lEI settles active (HIgh) on the chIp
currently bemg serviced when the opcode
ED16 IS decoded. If the following opcode is
4D16, the penpheral bemg serVICed IS released
and its IEO becomes achve. Addihonal walt
states are allowed.

T,

TWA

I

\ ' -_ _ _ _- - J

\--_-11
DO-D7 - - - - - - {

\.====

88

IEI- - - -

ED

- - -,

______ J

DATA--------------------~~~-------

IEO ________________________________J~

Figure 14. Interrupt Acknowledge Timing

Figure 15. Return From Interrupt Timing

2041·0166,0167,0168

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3Vto +7.0V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°e to + ISOoe

Test
Conditions

The characteristics below apply for the
following test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
• S* = ooe to + 70 oe,
+4.7SV:sVee :S +S.2SV
• E* = -40 oe to +8Soe,
+4.75V:sVee:S +S.2SV
• M* = -ssoe to + 12Soe,
+4.S V:s Vee:s +S.S V

DC
Characteristics

Symbol

Capaci lance

VILe
VIHe
VIL

Stresses greater than those lIsted under Absolute MaxImum Ratmgs may cause permanent damage to the devICe.
ThIS 15 a stress ratmg only; operabon of the devICe at any

condItIon above those mdicated In the operahonal sechons
of these specIfIcations IS not ImplIed. Exposure to absolute
maXImum rating condItIons for extended perIods may affect
devIce relIabIlIty.
"See Ordermg Information sectIon for package
temperature range and product number

Parameter
Clock Input Low Voltage
Clock Input High Voltage

Min

Max

Unit

-0.3

+0.45

V

Vee-·6 Vee+· 3
-0.3
+0.8

Input Low Voltage

V
V

VIH

Input H,gh Voltage

VOL
VOH

Output Low Voltage

ICC
ILl

Power Supply Current
Input Leakage Current

+120

rnA

+10

p.A

110H

3-State Output Leakage Current m Float

p.A

110L

3-State Output Leakage Current m Float

+10
-10

IOHD

Darlmgton Dnve Current

Symbol

+2.0

Output High Voltage

Parameter

Vee
+0.4

+2.4

-1.5

Max

Unit

CLK

Clock Capacltance

20

pF

C rN

Input Capacltance

5

pF

C OUT

Output Capacltance

10

pF

Test Condition

V
V

IOL=2mA

V

IOH = 250 p.A
VIN = o to Vee
Your = 2.4 to Vee

p.A

Your = 0.4 V

rnA

VOH = 1.5 V
REXr = 3900

Condition
Unmeasured pms
returned to ground

TA = 25°C, f = I MHz

8085·0239

89

AC

~

,-W-\

Character-

istics

-0-

CLOCK

~

FL 'I'--J nw~
iX

C50, CS1

X

I----- (n-2) TdIEI(lEOf) + TdMI(IEO) + TsIEI(IO)
+ TTL buffer delay, if any
IB] RESET must be achve for a mlnlmum of 3 clock cycles
NOTES;
[II TeC = TwCh + TwCl + TrC + TIC
[21 Increase delay by 10 ns for each 50 pF Increase m loadmg,
200 pF maXImum for data lmes, and 100 pF for controllmes

[2]
III

00
0

n
III
n

[3]
[2]
[3]
[3]
[4]
[5]
[5]
[5]

[5]

[4]

[3J Increase delay by 2 ns for each 10 pF Increase In loadIng,
100 pF maximum.
(4J TImer mode,
[5] Counter mode.
[6] RESET must be actIve for a mlnlmUm of 3 clock cycles.
* All hmmgs are prehmmary and subject to change.

91

Ordering
Information

Product
Number

Package/
Temp
Speed

Description

Product
Number

Package/
Temp
Speed

Description

28430

CE

2.5 MHz

Z80 CTC (28-pin)

28430A

CMB

4.0 MHz

280A CTC (28-pin)

28430

CM

2.5 MHz

Same as above

Z8530A

CS

4.0 MHz

Same as above

28430

CMB

2.5 MHz

Same as above

28430A

DE

4.0 MHz

Same as above

28430

CS

2.5 MHz

Same as above

Z8430A

DS

4.0 MHz

Same as above

Z8430

DE

2.5 MHz

Same as above

Z8430A

PE

4.0 MHz

Same as above

28430

DS

2.5 MHz

Same as above

Z8430A

PS

4.0 MHz

Same as above

28430

PE

2.5 MHz

Same as above

28430B

CS

6.0 MHz

Same as above

28430

PS

2.5 MHz

Same as above

Z8430B

DS

6.0 MHz

Same as above

28430A

CE

4.0 MHz

280A CTC (28-pin)

28430B

PS

6.0 MHz

Same as above

Z8430A

CM

4.0 MHz

Same as above

"NOTES: C = Ceramlc, D = Cercitp, P = Plasltc; E = -40'C to + 8S'C, M = -SS'C to + 12S'C, MB = -SS'C to + 125'C wlth
MIL-STD-883 Class B processmg, S = O'C to + 70'C.

92

OO·2022·A

18440
180® SIO Serial
IDput/Output CODtroller

~

Product
SpeclficatloD

Zilog

June 1982
Features

• Two independent full-duplex channels, with
separate control and status lmes for modems
or other devICes.
• Data rates of 0 to 500K bIts/second in
the xl clock mode with a 2.5 MHz clock
(Z-80 SIO), or 0 to 800K bits/second with a
4.0 MHz clock (Z-80A SIO).
• Asynchronous protocols: everything
necessary for complete messages in 5, 6, 7
or 8 bits/character. Includes variable stop
bits and several clock-rate mulhpliers;
break generation and detection; parity;
overrun and frammg error detechon.

General
Description

• Synchronous protocols: everything
necessary for complete bit- or byte-oriented
messages in 5, 6, 7 or 8 bIts/character,
mcluding IBM Bisync, SDLC, HDLC,
CCITT-X.25 and others. Automatic CRC
generation/checking, sync character and
zero msertion/deletion, abort generation/detection and flag msertion.
• Receiver data regIsters quadruply buffered,
transmitter registers doubly buffered.
• Highly sophisticated and flexible daisychain interrupt vectoring for interrupts
without external logiC.

The Z-80 SIO Serial Input/Output Controller is a dual-channel data communication
interface WIth extraordinary versatihty and
capabihty. Its basic functions as a senal-toparallel, parallel-to-serial converter/controller
can be programmed by a CPU for a broad
range of serial communication applicahons.
The device supports all common asynchronous and synchronous protocols, byte- or

bit-oriented, and performs all of the functions
traditionally done by UARTs, USARTs and
synchronous communication controllers combmed, plus additional funchons traditionally
performed by the CPU. Moreover, it does this
on two fully-mdependent channels, with an
excephonally sophlshcated interrupt structure
that allows very fast transfers.
Full mterfacmg IS prOVided for CPU or DMA

0,
0,
CHANNEL A

0,
0,

INT

'"
W/RDYA

SYNCA

WIRDYB
RxOS

RxCA

DAISY {
CHAIN
INTERRUPT
CONTROL

:~::

DTRB

_j

DCDS_

leO

~r-r---T"r---'
+5V

GNP

TxCA
CHANNEL B
DTRA

MODEM
CONTROL

DTRB

elSA

oeOA

c'"

RESET

eLK

Figure I. Z-80 SI0/2 Pin Functions
2042·0111. 0120

Rxe8

Figure 2. Z-80 SI0/2 Pin Assignments

93

i

s

General
Description
(Continued)

Pin
Description

control. In addition to data communication, the
circuit can handle virtually all types of serial
1/0 with fast (or slow) peripheral devices.
While designed primarily as a member of the
Z-80 family, its versatility makes it well suited
to many other CPUs.

The Z-80 SIO is an n-channel silicon-gate
depletion-load device packaged in a 40-pin
plastic or ceramic DIP. It uses a single + 5 V
power supply and the standard Z-80 family
single-phase clock.

Figures I through 6 illustrate the three pin
configurations (bonding options) available in
the SIO. The constraints of a 40-pin package
make it impossible to bring out the Receive
Clock (RxC), Transmit Clock (TxC), Data Terminal Ready (DTR) and Sync (SYNC) signals
for both channels. Therefore, either Channel B
lacks a signal or two signals are bonded
together in the three bonding options offered:

CEo Chip Enable (input, active Low). A Low
level at this input enables the SIO to accept
command or data input from the CPU during a
write cycle or to transmit data to the CPU
during a read cycle.

ClK. System Clock (input). The SIO uses the
standard Z-80 System Clock to synchronize
internal signals. This is a single-phase clock.
CrSA. CrSB. Clear To Send (inputs, active

• Z-80 SIO/2 lacks SYNCB
• Z-80 SIOIl lacks DTRB
• Z-80 SIOIO has all four signals, but TxCB
and RxCB are bonded together
The first bonding option above (SIO/2) is the
preferred version for most applications. The
pin descriptions are as follows:

B/A. Channel A Or B Select (input, High
selects Channel B). This mput defines which
channel is accessed during a data transfer
between the CPU and the SIO. Address bit Ao
from the CPU is often used for the selection
function.
C/D. Control Or Data Select (input, High
selects Control). This input defines the type of
information transfer performed between the
CPU and the SIO. A High at this input during
a CPU write to the SIO causes the information
on the data bus to be interpreted as a command for the channel selected by BilL A Low
at C/D means that the mformation on the data
bus is data. Address bit Al is often used for
thIS function.

Low). When programmed as Auto Enables, a
Low on these inputs enables the respective
transmitter. If not programmed as Auto
Enables, these mputs may be programmed as
general-purpose mputs. Both inputs are
Schmitt-trigger buffered to accommodate slowrisetime signals. The SIO detects pulses on
these inputs and interrupts the CPU on both
logic level transitions. The Schmitt-trigger buffering does not guarantee a specified noiselevel margin.

Do-D7' System Data Bus (bidirectional,
3-state). The system data bus transfers data
and commands between the CPU and the Z-80
SIO. Do is the least significant bit.
DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if the SIO is programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slowrisetime signals. The SIO detects pulses on
these pins and interrupts the CPU on both
logIC level transitions. Schmitt-trigger buffer-

0,
0,
CHANNEL A

0,
0,

fNf
lEI

M"f
+5V
WIRDYA
SYNCA

OND
W/RDYB

RxOA
"RxCA

TxCA

CHANNEL.

DiM

TIIDB

RTSA

DAISY {
CHAIN
INTERRUPT
CONTROL

eTSA

oeOA
elK

lEO

+5V

GND

elK

Figure 3. Z-80 510/1 Pin Functions

94

RESET

Figure 4. Z-80 510/1 Pin Assignments
2042-0111. 0120

PlD

Description
(Continued)

ing does not guarantee a specific noise-level
margin.
DTRA. DTRB. Data Terminal Ready (outputs,
active Low). These outputs follow the state programmed into Z-80 SIO. They can also be programmed as general-purpose outputs.
In the Z-80 SIOll bonding option, DTRB is
omitted.
lEI. Interrupt Enable In (input, active High).
This signal is used with IEO to form a priOrity
daisy chain when there is more than one
interrupt-driven device. A High on this line
indicates that no other device of higher priority is being serviced by a CPU interrupt service routine.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if lEI is High and the
CPU IS not servicing an interrupt from this
SIO. Thus, this signal blocks lower priority
devices from interrupting while a higher
priority device is being servICed by its CPU
interrupt service routine.

INT. Interrupt Request (output, open drain,
active Low). When the SIO is requesting an
interrupt, it pulls INT Low.
10RQ. Input/Output Request (input from CPU,
active Low). IORQ is used in conjunction with
BIA, C/iS, CE and RD to transfer commands
and data between the CPU and the SIO. When
CE, RD and IORQ are all active, the channel
selected by BIA transfers data to the CPU (a
read operation). When CE and IORQ are
active but RD is inactive, the channel selected
by BIA is written to by the CPU with either
data or control information as specified by
C/iS. If IORQ and MI are active simultane-

cpu{_ ~

DATA
BUS

F~~~

D,

Os

WIRDYA

=

::)
imiA

1 :~:T
_

active Low). If RD is active, a memory or I/O
read operation is in progress. RD is used with
BIA, CE and IORQ to transfer data from the
SIO to the CPU.
RxDA. RxDB. Receive Data (inputs, active
High). Serial data at TTL levels.
RESET. Reset (input, active Low). A Low
RESET disables both receivers and transmitters, forces TxDA and TxDB marking, forces
the modem controls High and disables all
interrupts. The control registers must be

TxDA

== ~:
CONTROL

RD. Read Cycle Status (input from CPU,

RIlD
RiCA
_ A_

_°4

_

ously, the CPU is acknowledging an interrupt
and the SIO automatically places its interrupt
vector on the CPU data bus if it is the highest
priority device requesting an interrupt.
MI. Machine Cycle (input from Z-80 CPU,
active Low). When MI is active and RD is also
active, the Z-80 CPU is fetching an instruction
from memory; when MI is active while IORQ is
active, the SIO accepts MI and IORQ as an
interrupt acknowledge if the SIO is the highest
priority device that has interrupted the Z-80
CPU.
RxCA. RxCB. Receiver Clocks (inputs).
Receive data is sampled on the rising edge of
RxC. The Receive Clocks may be I, 16, 32 or
64 times the data rate in asynchronous modes.
These clocks may be driven by the Z-80 CTC
Counter Timer Circuit for programmable baud
rate generation. Both inputs are Schmitttrigger buffered (no noise level margin is
speCified) .
In the Z-80 SIO/O bonding option, RxCB is
bonded together with TxCB.

Z.80 SlOIO :

CMANN_LA

MODEM
CONTROL

iii

CJ~

Rli
WIROYA

OND

Wiii5Yi

RiTi9 _

AD

TIlDB _
iYNCi

-

c/o

WiRDVB

_BIA

DAISY

INTE:::~~

CONTROL

:~:: _ )

{iNT

-

lEI

OTRB
Deca - - -

lEO

CHANNILa

6Tiil

MODEM
CONTROL

1..--.,....--.--.....---....1
+sv

OND

eLK

Figure 5. Z-80 810/0 Pin Funcllollll

2042·0111, 0120

Figure 6. Z-60 810/0 Pin A8a1gnmenls

95

I

Pin
Description
(Continued)

rewritten after the SIO is reset and before data
is transmitted or received.

RTSA. RTSB. Request To Send (outputs,
active Low). When the RTS bit in Write
Register 5 (Figure 14) is set, the RTS output
goes Low. When the RTS bit is reset in the
Asynchronous mode, the output goes High
after the transmitter is empty. In Synchronous
modes, the RTS pill strictly follows the state of
the RTS bit. Both pins can be used as generalpurpose outputs.
SYNCA. SYNCB. Synchronization (inputs/outputs, active Low). These pins can act either as
inputs or outputs. In the asynchronous receive
mode, they are inputs similar to CTS and
DCD. In this mode, the transitions on these
Imes affect the state of the Sync/Hunt status
bits in Read Register 0 (Figure 13), but have
no other function. In the External Sync mode,
these Imes also act as inputs. When external
synchronization IS achieved, SYNC must be
driven Low on the second rising edge of RxC
after that rising edge of RxC on which the last
bIt of the sync character was received. In
other words, after the sync pattern is detected,
the external logic must wait for two full
Receive Clock cycles to activate the SYNC
input. Once SYNC is forced Low, it should be
kept Low unhl the CPU informs the external
synchronization detect logic that synchronization has been lost or a new message is about to
start. Character assembly begins on the rising
edge of RxC that immediately precedes the
falling edge of SYNC in the External Sync
mode.

In the internal synchronization mode
(Monosync and Bisync), these pins act as outputs that are active during the part of the
receive clock (RxC) cycle in which sync
characters are recogmzed. The sync condition
is not latched, so these outputs are active each
time a sync pattern is recognized, regardless
of character boundaries.
In the 2-80 SIO/2 bonding option, SYNCB
is omitted.
TxCA. TxCB. Transmitter Clocks (inputs). In
asynchronous modes, the Transmitter Clocks
may be 1, 16, 32 or 64 times the data rate;
however, the clock multiplier for the transmitter and the receiver must be the same. The
Transmit Clock inputs are Schmitt-trigger buffered for relaxed rise- and fall-time requirements (no noise level margin is specified).
Transmitter Clocks may be driven by the 2-80
CTC Counter Timer Circuit for programmable
baud rate generation.
In the 2-80 SIO/O bonding option, TxCB is
bonded together with RxCB.
TxDA. TxDB. Transmit Data (outputs, active
High). Serial data at TTL levels. TxD changes
from the falling edge of TxC.

W/RDYA. W/RDYB. Wait/Ready A, Wait/
Ready B (outputs, open drain when programmed for Wait function, driven High and
Low when programmed for Ready function).
These dual-purpose outputs may be programmed as Ready lines for a DMA controller
or as Wail lines that synchronize the CPU to
the SIO data rate. The reset state is open
drain.

}

SERIAL DATA

}

CHANNEL CLOCKS

SYNC
WAIT/READY

INTERNAL
CONTROL
LOGIC

MODEM OR
OTHER CONTROLS

DATA
CPU

BUS 110
CONTROL
MODEM OR
OTHER CONTROLS

INTERRUPT
CONTROL - - - .

LINES

=}

INTERRUPT
CONTROL

LOGIC

}

..-.

SERIAL DATA
CHANNEL CLOCKS

SYNC
WAIT/READY

Figure

96

i.

Block Diagram

2042·0106

Functional
Description

the SIO offers valuable features such as nonvectored interrupts, pollmg and sImple handshake/capablltty.
FIgure 8 Illustrates the convenltonal devICes
that the SIO replaces.
The first part of the following dIscussIOn
covers SIO data-communicalton capabl!tties;
the second part describes interactions between
the CPU and the SIO.

The funcltonal capabl!tltes of the 2-80 SIO
can be described from two dIfferent pomts of
view: as a data communicaltons device, it
transmIts and receives senal data m a WIde
variety of data-communication protocols; as a
2-80 famIly penpheral, It interacts with the
2-80 CPU and other penpheral cIrcuits, sharmg the data, address and control buses, as
well as being a part of the 2-80 mterrupt structure. As a penpheral to other mICroprocessors,

CHANNEL
A

MICROPROCESSOR
INTERFACE

lf

i

S

CHANNEL

B

MICROPROCESSOR

INTERFACE

B

.........

Z.80

CHANNEL
A

SIO

.....- CHANNEL
B

Figure 8. Conventional Devices Replaced by the Z-80 SIO

Data
Communication
Capabilities

The SIO prOVIdes two independent fullduplex channels that can be programmed for
use in any common asynchronous or synchronous data-commumcalton protocol. FIgure 9
Illustrates some of these protocols. The followmg IS a short descnption of them. A more
detatled explanation of these modes can be
found m the Z-80 510 Technical Manual.

Asynchronous Modes. TransmIssIOn and
receplton can be done mdependently on each
channel with five to eight bIts per character,
plus ophonal even or odd panty. The transmItters can supply one, one-and-a-half or two stop
bIts per character and can provide a break
output at any ltme. The receIver breakdeteclton logIC mterrupts the CPU both at the
start and end of a receIved break. Receplton IS
protected from spIkes by a transIent splkerejectIOn mechamsm that checks the SIgnal
one-half a bIt hme after a Low level IS detected
on the receIve data mput (RxDA or RxDB m
FIgure 5). If the Low does not persIst-as m
the case of a transIent-the character assembly
process IS not started.
Frammg errors and overrun errors are
detected and buffered together wIth the parhal
character on whIch they occurred. Vectored
2042-0107

mterrupts allow fast servlcmg of error condlhons using dedIcated routines. Furthermore, a
bUlJt-m checkmg process avoids mterpretmg a
frammg error as a new start bIt: a frammg
error results in the addllton of one-half a bIt
ltme to the pomt at whIch the search for the
next start bit IS begun.
The SIO does not require symmetnc transmIt
and receIve clock signals-a feature that
allows It to be used wIth a 2-80 CTC or many
other clock sources. The transmItter and
receIver can handle data at a rate of 1, 1116,
1132 or 1164 of the clock rate supplted to the
receIve and transmIt clock mputs.
In asynchronous modes, the SYNC pm may
be programmed as an mput that can be used
for functIOns such as momtormg a rmg
mdicator.

Synchronous Modes. The SIO supports both
byte-onented and btt-orlented synchronous
commumcalton.
Synchronous byte-onented protocols can be
handled m several modes that allow character
synchromzatlOn WIth an 8-bit sync character
(Monosync), any 16-bit sync pattern (BIsync),
or WIth an external sync sIgnal. Leadmg sync

97

Data
Communication
Capabilities
(Continued)

characters can be removed without interrupting the CPU.
Five-, six- or seven-bit sync characters are
detected with 8- or 16-bit patterns In the SIO
by overlapping the larger pattern across multiple in-coming sync characters, as shown in
Figure 10.
CRC checking for synchronous byteoriented modes IS delayed by one character
time so the CPU may disable CRC checking on
specific characters. This permits implementation of protocols such as IBM Bisync.
Both CRC-16 (X16 + XIS + X2 + 1) and
CCITT (X16 + XI2 + X5 + 1) error checking
polynomials are supported. In all non-SDLC
modes, the CRC generator is initialized to O's;
In SDLC modes, it is initialized to l's. The SIO
can be used for interfaCing to peripherals such
as hard-sectored floppy disk, but it cannot
generate or check CRC for IBM-compatible
soft-sectored disks. The SIO also provides a
feature that automatically transmits CRC data
when no other data is available for transmission. This allows very high-speed transmissions
under DMA control with no need for CPU
intervention at the end of a message. When
there IS no data or CRC to send in synchronous modes, the transmitter inserts 8- or
16-bit sync characters regardless of the programmed character length.
The SIO supports synchronous bit-oriented
protocols such as SDLC and HDLC by performing automatic flag sending, zero insertion
and CRC generation. A speCial command can
be used to abort a frame in transmiSSIOn. At
the end of a message the SIO automatically
transmits the CRC and trailing flag when the
transmit buffer becomes empty. If a transmit

_____.STr
..
II

MARKING LINE

DATA

PAPlop
II I 1""1
I

underrun occurs in the middle of a message,
an external/status interrupt warns the CPU of
this status change so that an abort may be
issued. One to eight bits per character can be
sent, which allows reception of a message with
no prior information about the character structure In the information field of a frame.
The receiver automatically synchronizes on
the leading flag of a frame in SDLC or HDLC,
and provides a synchronization signal on the
SYNC pin; an interrupt can also be programmed. The receiver can be programmed to
search for frames addressed by a single byte to
only a speCified user-selected address or to a
global broadcast address. In this mode, frames
that do not match either the user-selected or
broadcast address are ignored. The number of
address bytes can be extended under software
control. For transmitting data, an interrupt on
the hrst received character or on every
character can be selected. The receiver
automatically deletes all zeroes inserted by the
transmitter during character assembly. It also
calculates and automatically checks the CRC
to validate frame transmission. At the end of
transmiSSIOn, the status of a received frame is
aVailable in the status registers.
The SIO can be convemently used under
DMA control to provide high-speed reception
or transmission. In reception, for example, the
SIO can interrupt the CPU when the first
character of a message IS received. The CPU
then enables the DMA to transfer the message
to memory. The SIO then issues an end-offrame Interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received.

'1'1"'11

-DA-T-A

DATA

II'

I MARKING LINE

ASYNCHRONOUS

::

DATA

SYNC

I

DATA

CRG1

CRC2

DATA

CRel

CRC2

DATA

CRGl

CRC2

CRC1

CRC2

MONOSYNC

SYNC

SYNC

::

DATA
SIGNAL

I

BISYNC

::

+
DATA

EXTERNAL SYNC
FLAG

I

ADDRESS

I

INFO~M~TION

FLAG

SDLC/HDLCIX.25

Figure 9. Some Z-80 SIO Protocols
6 BITS

~

SYN~

SYNC

DATA

DATA

DATA

DATA

~

~----V~---·~-,.
Figure 10.

98

2042-0108, 0109

110 Interface
Capabilities

The SIO offers the chOIce of pollmg, mterrupt (vectored or non-vectored) and blocktransfer modes to transfer data, status and control mformahon to and from the CPU. The
block-transfer mode can also be Implemented
under DMA control.

CPU IS mterrupted by the transmit buffer
becommg empty. (ThIS lmplles that the
transmitter must have had a data character
wntten mto It so It can become empty.) The
receIVer can mterrupt the CPU in one of two
ways:

Polling. Two status registers are updated at
appropnate hmes for each funchon bemg performed (for example, CRC error-status valld at
the end of a message). When the CPU IS
operated m a pollmg fashion, one of the SIO's
two status registers IS used to mdlCate whether
the SIO has some data or needs some data.
Dependmg on the contents of this register, the
CPU Will either wnte data, read data, or Just
go on. Two bits in the register mdlcate that a
data transfer IS needed. In addition, error and
other condihons are mdicated. The second
status register (special receIVe condihons) does
not have to be read in a polling sequence,
untt! a character has been received. All mterrupt modes are disabled when operatmg the
deVice in a polled environment.

• Interrupt on hrst received character

Interrupts. The SIO has an elaborate interrupt
scheme to provide fast mterrupt servICe m
real-time apphcatlOns. A control register and a
status register in Channel B contam the interrupt vector. When programmed to do so, the
SIO can modify three bits of the interrupt vector in the status register so that it points directly to one of eight mterrupt service routmes in
memory, thereby servlCmg condihons m both
channels and ehmmating most of the needs for
a status-analysis routme.
Transmit interrupts, receive mterrupts and
external/status mterrupts are the main sources
of interrupts. Each interrupt source is enabled
under program control, with Channel A havmg a higher prionty than Channel B, and with
receive, transmit and external/status mterrupts
pnoritized m that order within each channel.
When the transmit mterrupt is enabled, the

• Interrupt on all receIVed characters
Interrupt-on-hrst-recelved-character IS
typically used with the block-transfer mode.
Interrupt-on-all-received-characters has the
ophon of modifying the mterrupt vector m the
event of a panty error. Both of these mterrupt
modes will also mterrupt under special receive
condihons on a character or message baSIS
(end-of-frame interrupt m SDLC, for example).
This means that the speclal-rec81ve condition
can cause an mterrupt only if the mterrupt-onfirst-recelved-character or interrupt-on-allreceived-characters mode IS selected. In
interrupt-on-hrst-recelved-character, an interrupt can occur from special-rec81ve conditions
(except panty error) after the hrst-recelvedcharacter interrupt (example: receive-overrun
mterrupt).
The mam function of the external/status
mterrupt is to mom tor the signal transitions of
the Clear To Send (CTS), Data Carner Detect
(DCD) and Synchronizahon (SYNC) pms
(Figures 1 through 6). In addihon, an external/status interrupt is also caused by a CRCsending condihon or by the detechon of a
break sequence (asynchronous mode) or abort
sequence (SDLC mode) m the data stream.
The interrupt caused by the break/abort
sequence allows the SIO to mterrupt when the
break/abort sequence IS detected or termmated. This feature facihtates the proper terminahon of the current message, correct
imtiallzahon of the next message, and the
accurate timmg of the break/abort condlhon in
external logIC.

99

I/O Interface
In a 2-80 CPU envIronment (FIgure 11), SIO
Capabilities interrupt vectormg IS "automahc"; the S10
(Contmued)

SYSTEM

BUSES

passes Its mternally-modlflable 8-blt interrupt
vector to the CPU, whICh adds an addItional 8
bIts from ItS mterrupt-vector (I) register to form
the memory address of the mterrupt-routme
table. ThIs table contains the address of the
begmnmg of the mterrupt routme Itself. The
process entails an mdirect transfer of CPU
control to the mterrupt routme, so that the
next mstruchon executed after an mterrupt
acknowledge by the CPU IS the first instruchon
of the mterrupt routme Itself.

DMA

CPU

INT

lEI
+5V

T

CPU/DMA Block Transfer. The SlO's block-

lEI

transfer mode accommodates both CPU block
transfers and DMA controllers (2-80 DMA or
other desIgns). The block-transfer mode uses
the Wait/Ready output sIgnal, which IS
selected with three hits in an internal control
regIster. The Wait/Ready output sIgnal can be
programmed as a WAIT line m the CPU blocktransfer mode or as a READY line m the DMA
block-transfer mode.
To a DMA controller, the SIO READY output
mdICates that the S10 IS ready to transfer data
to or from memory. To the CPU, the WAIT output mdicates that the S10 is not ready to
transfer data, thereby requestmg the CPU to
extend the I/O cycle.

ZC/T01

CTC
ZCIT02

iN!

lEO

--.!.-

WfRDYA

iiiiFiDYB
SIO

J-

iNT
lEI

ROY

DMA

Figure II. Typical Z-80 Environment

Internal
Structure

The internal structure of the device includes
a 2-80 CPU mterface, internal control and
interrupt logic, and two full-duplex channels.
Each channel contains its own set of control
and status (write and read) registers, and control and status logic that provides the interface
to modems or other external devices.
The registers for each channel are designated as follows;
WRO- WR7 - Write Registers 0 through 7
RRO-RR2 - Read Registers 0 through 2
The regIster group includes five 8-bit control
registers, two sync-character registers and two
status registers. The interrupt vector is written
into an additional 8-bit register (Write Register
2) in Channel B that may be read through
another 8-hlt register (Read Register 2) in
Channel B. The bit assignment and functional
grouping of each regIster is configured to
simplify and organize the programming process. Table 1 lists the funchons assigned to
each read or write register.

100

Read Register FUDctions

RRO
RRI
RR2

Transmit/Receive buffer status, mterrupt
status and external status
SpecIal ReceIve Condihon status
Modified mterrupt vector (Channel B only)
Write Register FUDctions

WRO Register poiriters, CRC initialize, mihahzation commands for the various modes, etc.
WRI TransmIt/ReceIve interrupt and data transfer
mode defmihon.
WR2 Interrupt vector (Channel B only)
WR3 Receive parameters and control
WR4 TransmIt/ReceIve miscellaneous parameters
and modes
WR5 TransmIt parameters and controls
WR6 Sync character or SDLC address field
WR7 Sync character or SDLC flag

2032-0127

Internal
Structure
(Continued)

The logIc for both channels provides formats, synchronization and validahon for data
transferred to and from the channel mterface,
The modem control mputs, Clear To Send
(CTS) and Data Carrier Detect (DCD), are
monitored by the external control and status
logic under program control. All external
control-and-status-Iogic signals are generalpurpose m nature and can be used for funchons other than modem control.

Data Path. The transmit and receive data path
Illustrated for Channel A in Figure 12 is idenhcal for both channels. The receiver has three
8-bit buffer registers in a FIFO arrangement,
in addition to the 8-bit receive shift register.
This scheme creates additional time for the

CPU to service an mterrupt at the beginnmg of
a block of hIgh-speed data. Incommg data is
routed through one of several paths (data or
CRC) dependmg on the selected mode
and-in asynchronous modes-the character
length.
The transmItter has an 8-blt transmit data
buffer regIster that is loaded from the internal
data bus, and a 20-bJt transmIt shift register
that can be loaded from the sync-character
buffers or from the transmit data regIster.
Depending on the operational mode, outgoing
data is routed through one of four mam paths
before It IS transmitted from the Transmit Data
output (TxD).

CPU 110

-ftTxDA
HUNT MODE (BISYNC)

r---------,

Figure 12. Transmit and Receive Data Path (Channel A)

2042·0112

101

Programming

The system program first issues a series of
commands that Initialize the basic mode of
operatIon and then other commands that
qualify conditions within the selected mode.
For example, the asynchronous mode,
character length, clock rate, number of stop
bits, even or odd parity might be set first; then
the interrupt mode; and finally, receiver or
transmitter enable.
Both channels contain registers that must be
programmed via the system program prior to
operation. The channel-select Input (B/A) and
the control/data Input (C/D) are the commandstructure addressing controls, and are normally controlled by the CPU address bus. FIgures
15 and 16 illustrate the timing relationships for
programming the write regIsters and transferring data and status.
Read Registers. The S10 contains three read

registers for Channel B and two read registers
for Channel A (RRO-RR2 in Figure 13) that can
be read to obtain the status information; RR2
contains the internally-modifiable interrupt
vector and is only in the Channel B register
set. The status information includes error conditions, interrupt vector and standard
communications-interface signals.
To read the contents of a selected read
register other than RRO, the system program
must first write the pointer byte to WRO in
exactly the same way as a write register operation. Then, by executing a read instruction,
the contents of the addressed read register can
be read by the CPU.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring. For
example, when the interrupt vector indicates
that a Special Receive Condition interrupt has
occurred, all the appropriate error bits can be
read from a single register (RR1).
Write Registers. The S10 contains eight write

WRO IS a special case in that all of the basic
commands can be written to it with a single
byte. Reset (internal or external) initializes the
pointer bIts Do-D2 to POint to WRO. This
implies that a channel reset must not be combined with the pointing to any register.
READ REGISTER 0

III L§I

I L-R,CHARACTERAVAILABLE
L.::=
tNT PENDING (CH A ONLY)
~~~UFFER EMPTY

}

SYNC/HUNT
eTS
Tx UNOERRUNIEOM

•

BREAK/ABORT

. .

READ REGISTER It

, , , , ,I
101, 0 101010101010
L-ALLSENT

III

1
0
1
0
1
0
1
0

0
1
1
0
0
1
1
0

I FI ELC BITS
I FIELD BITS IN
}
IN PREVIOUS SECOND PREVIOUS

0
0
0
1
1
1
1
0

BYTE

BYTE
3
4

o
o
o
o
o

•

•

6
7

o

•

1

•

2

•

L-.-- PARITY ERR OR
i....---- Rx OVEAAU N ERROR
-CRC/FRAMI NG ERROR

'Residue Data
Rx Bits/Character

END OF FRA ME (SOLe)
tUsed With SpeCial Receive COrtdlllon Mode

READ REGISTER 2"

I~I~I~I~I~I~I~I~I

III L§I
~~~t)
~~~
V4

V.

INTERRUPT
VECTOR

V6

V7
tVariable If "Status Affects
Vector" IS Programmed
("CHANNEL B ONLY)

Figure 13. Read Register. Bit Functions

registers for Channel B and seven write
registers for Channel A (WRO-WR7 in Figure
14) that are programmed separately to configure the functional personality of the channels; WR2 contains the interrupt vector for
both channels and is only in the Channel B
register set. With the exception of WRO, programming the write registers requires two
bytes. The first byte is to WRO and contains
three bits (Do-D2) that point to the selected
register; the second byte is the actual control
word that is written into the register to configure the S10.

102

2042·0114

Programming

WRITE REGISTER 0

(Continued)

10, I 0,10, 10.10, 10, I 0 10

WRITE REGISTER 4

"

I

I I I
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTER
REGISTEA
REGISTER

0
1
2
3
4
5
6
7

SYNC MODES ENABLE
1 STOP BIT/CHARACTER
1'/' STOP BITS/CHARACTER
2 STOP BITS/CHARACTER
8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER
SOLe MODE (01111110 FLAG)
EXTERNAL SYNC MODE

NULL COD E
SEND ABO RT (SOLC)
RESET EXTISTATUS INTERRUPTS
CHANNEL RESET
ENABLE IN T ON NEXT Rx CHARACTER
RESET Tx 1NT PENDING
ERROR RES ET
RETURN FA OM INT (CH·A ONLY)

Xl CLOCK MODE
X16 CLOCK MODE
X32 CLOCK MODE

X64 CLOCK MODE

NULL COCE
RESET Ax CRC CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNDERAUNIEOM LATCH

WRITE REGISTER 5

WRITE REGISTER I

I~I~I~I~I~I~I~I~I

~II

I

L - e x T INT ENABLE
Tx INT ENABLE
STATUS AFFECTS VECTOR
(CH B ONLY)

~ ! ~J)~t ~~[!~:6~::ARtT~TR~R(PARITY

1

1

AFFECTS VECTOR) }
INT ON All Rx CHARACTERS (PARITY DOES NOT AFFECT
VECTOR)

V4

V,

i

~~;RCENABLE

0
1
0
1

Tx
Tx
Tx
Tx

5
7
6
8

a

SEND BREAK

BITS (OR LESS)lCHARACTER
BITS/CHARACTER
BITS/CHARACTER
BITS/CHARACTER

WRITE REGISTER 6

WRITE REGISTER 2 (CHANNEL B ONLY)

I~I~I~I~I~I~I~I~I

~~

o
o
1
1

I

J:~·====SDlCICRC.16
Tx ENABLE

DTR

WAIT/READY ON R/T
WAIT/READY FUNCTION
'----WAIT/READy ENABLE

1[1~'~~~1

•

~

IIIL

I[I1II ~:;:.!mll
SYNC
SYNC
SYNC
SYNC
SYNC

INTERRUPT
VECTOR

V6
V7

BIT
BIT
BIT
BIT
BIT

3
4
5
6
7

..

"Also SOLe Address Field

WRITE REGISTER 7

WRITE REGISTER 3

IIII
R)(
R)(
R)(
R)(

I~SYNC
L - R, ENABLE
CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SOlC)
Ax CRC ENABLE
ENTER HUNT PHASE
AUTO ENABLES

III1II ~!!:!!!tl
SYNC
SYNC
SYNC
SYNC
SYNC

BIT
BIT
BIT
BIT
BIT

11
12
13
14
15

..

5 BITS/CHARACTER
7 BITS/CHARACTER
6 BITS/CHARACTER
8 BITS/CHARACTER

Figure 14. Write Register Bit Functions

2042-0113

103

Timing

The SIO must have the same clock as the
CPU (same phase and frequency relationship,
not necessarily the same driver).

Read Cycle. The timing signals generated by
a 2-80 CPU input instruction to read a data or
status byte from the SIO are illustrated in
Figure 15.
Write Cycle. Figure 16 illustrates the timing
and data signals generated by a 2-80 CPU output instruction to write a data or control byte
into the SIO.
Interrupt-Acknowledge Cycle. After receiving an interrupt-request signal from an SIO
(TNT pulled Low), the 2-80 CPU sends an
interrupt-acknowledge sequence (Ml Low, and
IORQ Low a few cycles later) as in Figure 17.
The SIO contains an internal daisy-chained
interrupt structure for prioritizing nested interrupts for the various functions of its two channels, and this structure can be used within
an external user-defined daisy chain that
prioritizes several peripheral circuits.
The lEI of the highest-priority device is
terminated High. A device that has an interrupt pending or under service forces its lEO
Low. For devices with no interrupt pending or
under service, lEO = lEI.
To insure stable conditions in the daisy
chain, all interrupt status signals are prevented from changing while Ml is Low. When
IORQ' is Low, the highest priority interrupt
requestor (the one with lEI High) places its
interrupt vector on the data bus and sets its
T,

internal interrupt-under-service latch.

Return From Interrupt Cycle. Figure 18
illustrates the return from interrupt cycle.
Normally, the 2-80 CPU issues a RETI (Return
From Interrupt) instruction at the end of an
interrupt service routine. RET! is a 2-byte
opcode (ED-4D) that resets the interruptunder-service latch in the SIO to terminate the
interrupt that has just been processed. This is
accomplished by manipulating the daisy chain
in the following way.
The normal daisy-chain operation can be
used to detect a pending interrupt; however, it
cannot distinguish between an interrupt under
service and a pending unacknowledged interrupt of a higher priority. Whenever "ED" is
decoded, the daisy chain is modified by forcing High the lEO of any interrupt that has not
yet been acknowledged. Thus the daisy chain
identifies the device presently under service as
the only one with an lEI High and an lEO Low.
If the next opcode byte is "4D," the interruptunder-service latch is reset.
The _ripple time of the interrupt daisy chain
(both the High-to-Low and the Low-to-High
transitions) limits the number of devices that
can be placed in the daisy chain. Ripple time
can be improved with carry-look-ahead, or by
extending the interrupt-acknowledge cycle.
For further information about techniques for
increasing the number of daisy-chained
devices, refer to the Z-80 CPU Product
Specification.

T,

CLOCK

CLOCK

Ci,CID, ali

~--------------------J------I

M1----------------~------------DATA - - - - -____________.=:1.

DATA

------------------1 VECTOR >------

Figure 15. Read Cycle
T1

T2

Tw

T3

Figure 17. Interrupt Acknowledge Cycle
T1

CLOCK~

"~

••i

IORQ

__

---------...,..-------!I
...-----1
1\
____ _

lEI _ _ _ _ _ _ _ _ _

CLDCK

~

~

~---------------~----------

M1------------______~----------__

lEI -

DATA _______________ ~________
lEO

Figure 16. Write Cycle

104

-

- - -

- ",----------.....,--------

------.1
-

_ _ _ _..........

r--

~I

Figure 18. Return from Interrupt Cycle
2044-008, 009, 010, Oil

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3Vto +7.0V
Operating Ambient
As Specified in
Temperature ........... Ordering Information
Storage Temperature ........ -65°C to + 150°C

Test
Conditions

The characteristics below apply for the
followmg test conditions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:

Stresses greater than those hsted under Absolute Maximum Rahngs may cause permanent damage to the device.

ThIS IS a stress ratmg only; operation of the devIce at any

condItion above those indIcated In the operational sections
of these speclilCations IS not Imphed. Exposure to absolute
maXImum rahng condItIons for extended penods may affect
deVice rehablhty.

• S* = O°C to + 70°C,
+4.75 V S Vee S +5.25 V
• E* = -40°C to +85°C,
+4.75 V S Vee S +5.25 V
• M* = - 55°C to + 125°C,
+4.5VsVee s +5.5V
·See Ordermg Information sectIon for package
temperature range and product number.

DC
Characteristics

Symbol

Parameter

Min

IL(SY)

Clock Input Low Voltage
Clock Input High Voltage
lriput Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
3-State Output/Data Bus Input Leakage Current
SYNC Pin Leakage Current

Icc

Power Supply Current

VILe
VIHe

VIL

VIH
VOL
V OH

ILl
Iz

Max

-0.3
+0.45
Vee-0.6 +5.5
-0.3
+0.8
+2.0
+5.5
+0.4
+2.4
-10
+ 10
-10
+10
-40
+10
100

Unit

V
V
V
V
V
V
p.A
p.A

p.A

Test Condition

IOL
IOH

= 2.0 mA
= -250 p.A

O
ex>
ex>
400
330
2
400
ex>
ex>
ex>
2
180
180
100
220--2180-00--180-00
400
300
2
9
9
9
3
5
5
5
5
9
5
9
5
9
3
00
00
ex>
400
400
330
2
180-00--180-00 --100-00 - - - 2 00
00
00
180
180
100
2
2
0
0
0
140
140
100
2
13
10
13
10
13
10
3
10

13

10

13

10

13

3

1. Tlmmgs are preliminary and subject to change.
2 Umts In nanoseconds (ns).
3 Units equal to System Clock Penods

119

Ordering
Information

Product
Number

Package/
Temp
Speed

Description

Product
Number

Package/
Temp
Speed

Z8470A

CS

4.0 MHz

Z80A DART
(40-pm)
Same as above

Description

Z8470

CE

2.5 MHz

Z80 DART (40-pm)

Z8470

CM

2.5 MHz

Same as above

Z8470

CMB

2.5 MHz

Same as above

Z8470A

DE

4.0 MHz

Z8470

CS

2.5 MHz

Same as above

Z8470A

DS

4.0 MHz

Same as above

Z8470

DE

2.5 MHz

Same as above

Z8470A

PE

4.0 MHz

Same as above

Z8470

DS

2.5 MHz

Same as above

Z8470A

PS

4.0 MHz

Same as above

Z8470

PE

2.5 MHz

Same as above

Z8470B

CE

6.0 MHz

Z8470

PS

2.5 MHz

Same as above

Z80B DART
(40-pm)

Z8470A

CE

4.0 MHz

Z80A DART
(40-pm)

Z8470B

CS

6.0 MHz

Same as above

Z8470B

DS

6.0 MHz

Same as above

Z8470B

PS

6.0 MHz

Same as above

Z8470A

CM

4.0 MHz

Same as above

Z8470A

CMB

4.0 MHz

Same as above

'NOTES C = CeramlC, D = Cerd,p, P = Plashc, E = -40°C to +85°C, M = -55°C to + 125°C, MB = -55°C to + 125°C wIth
MIL·STD·883 Class B processmg, S = O°C to + 70°C

120

OO·2044·A

Z8000 Family

Zilog Z8000™ Family

~
Zilog

The Art of Staying a Generation Ahead

June 1982

zao Tradition in 16 bits.

Continumg
the FamIly concept so successfully
mtroduced by Its 8-blt 280 CPU, 2110g
devIsed the 28000 FamIly of 16-blt
parts. As you would expect from 2110g,
this Fam1ly provIdes much more than
an extension of 8-bit archItecture: the
28000 Family lets you deSIgn advanced
concepts from the mamframe and
mmicomputer worlds mto mICrocomputer systems.
And because the 28000 FamIly was
built around a unifymg set of protocols
and interconnections, present and
future fam1ly members are enhrely
compatible. Your system can grow as
your applications mature or expand. A
whole range of funchons have been
planned for from the begmning; the
growing famIly now mcludes parts to
prOVIde memory management, DMA
transfer, and extended processmg.

System Flexibility. Even the smallest
28000 systems offer hIgh throughput
and easy programmmg far superior to
any eXlshng mICroprocessor alternahve. In mid-range applicahons,
28000 components offer very powerful
soluhons to the deSIgn problems of
word processmg, mtelhgent termmals,
data commumcahons, instrumentahon,
and process control. In a complex network of mulhple processors, smart
penpheral components, and a
dIstributed memory conhgurahon, the
28000 FamIly provides performance
and versahhty exceedmg that of much
larger-and far more expenSlve-mmlcomputers.

Higher Throughput. Reduced
Cost. The powerful mstruchon set,
hIgh execuhon speed, regular archItecture, and numerous speCIal features of
the 28000 mICroprocessors dramahcally
mcrease system throughput. Intelhgent
28000 penpheral controllers and extended processmg umts unburden the
CPU and boost throughput even more.
SImply put, the 28000 FamIly offers
more for less money. The 28000
microprocessors gIve mId-range
mmIComputer performance at
mIcroprocessor cost. At component
pnces, 28000 penpheral controllers
perform complex system funchons that
preVIOusly reqUIred an enhre PC
board.
The 28000 Fam1ly is deSIgned for
mulhple-processor operation-an
economICal way of greatly mcreasmg
system performance. Many speCIal
features for mulhple 28000 CPUs
faclhtate the deSIgn of mulhpleprocessor systems that share access to
a common memory. The Memory Management Umts can dynamICally
relocate code and protect memory
areas. The Z8034 Z-UPC Umversal
Penpheral Controller, a complete slave
mICrocomputer, and the 28070 Floatmg
Pomt Emulahon Package for hIgh
speed anthmehc, can mampulate data
off-lme. Asynchronous parts of
mulhple-processor systems can be
Jomed by the 28038 2-FIO FIFO Interface Umt.

An Unmatched CPU. The 28000
data
path, more regIsters, more data types,
more addressmg modes, more mstruchans and more addressmg space. It
brmgs blg-machme concepts to the
level of components. Its generalregIster archItecture aVOIds bottlenecks
assocIated WIth dedICated or Imphed
regIsters. SpeCIal features support
parallel processors, operating systems,
comp1lers, and the Implementahon of
VIrtual memory.
The 28000 CPU IS also a very fast
machme. Its throughput is greater than
that of any other 16-blt microprocessor
WIth comparable clock speeds. And the
28000 CPU IS avaIlable WIth speeds
rangmg from a moderate 4 MHz clock
rate that allows you the choice of sbwaccess, low-cost memones to a hlghspeed 10 MHz clock rate for hlghperformance systems. From the four
versIOns of the 28000 mICroprocessors,
you can select the one best SUI ted to
your needs: the 2800 I for large
memory apphcahons, the 28002 for
small memory apphcations, the 28003
for VIrtual memory, the 28004 for
mIcroprocessor IS not Just a WIder

multIprocessors sharIng a common,

small memory.

How to Manage Your Memory
Belter. Trends are mcreasmgly toward
systems WIth mulhple users, complex
programs, secunty reqUIrements and
memones that don't stop growmg.

123

These design problems pose queshons
not sufficiently answered by other
mlCroprocessor famihes.
Exemplifying the Z-Family commitment to advanced architecture, the
Z8010 Memory Management Umt
(MMU) and the Z8015 Paged Virtual
Memory Management Unit (PMMU)
both provide flexiblhty m code segmenter page relocahon and sophistication m memory protection rarely found
in the microprocessor world. These
devices encourage modular software
development-a cnhcal factor as programs reach new levels of complexIty.
You are free from speclfymg where
informahon IS actually located in
physical memory because the MMU
and PMMU make software addresses
totally independent from the actual
physical memory address. While some
mlCroprocessor CPUs do have internal
CPU relocation registers, they are
dedicated and support few segments.
These CPUs also restrict memory protection. Not true for the MMU or
PMMU. VarlOus conhgurahons of these
devIces can randomly relocate all 128,
segments output by the Z8000 CPU m
any of ItS available memory systems.
For even more sophisticated memory
management, the Z8000 microprocessors mclude a new member that
supports virtual memory vIa an
mstruchon abort mechanism. The
Z8003 VIrtual Memory Processing Umt
can Implement either segmented vIrtual
memory that allows demand swappmg
of segments, or a paged vIrtual
memory in whlCh the umt of memory
allocahon IS a page wlthm a segment.

124

But the memory management umts
are more than relocation devlCes. They
offer you a host of memory protection
features that allow the system to protect
its software from unwanted uses and
users. Segments or pages can be
speclfied as read-only to protect them
from being overwnlten, as systemonly to protect the operatmg system
from madvertent user access, as
execute-only, and so on. A wnte warning zone IS especially useful m stack
operations so the operating system can
deal with growing stacks.

Peripheral Problem Solvers. Z8000
penpheral components are not dumb
I/O circuits. They perform intelligent,
complicated tasks on their own. They
unburden the CPU, reduce bus traffic,
and mcrease system throughput. Complex system tasks that previously
required burdensome conglomerahons
of MSI can now be handled off-line by
Z-BUS peripherals wIth little CPU
overhead, Mulhfunchon Z-BUS
penpherals are extensIvely programmable, so each can be preCIsely
tailored to ItS applicahon.
Counting, hmmg, and parallel I/O
problems seem less hresome with the
Z8036 Z-CIO Counter and Parallel I/O
devlCe. It has three 16-bit counter/
hmers, and three 110 ports. It can even
double as a programmable mterruptprlOnty controller, Data commumcations are neatly handled by the Z8030
Z-SCC Senal Commumcation Controller and the Z8033 Z-ASCC Asynchronous Senal Communicahons Controller, dual-channel multi-protocol
components that support bqtween them
all popular commumcahons formats.
DIrect memory access IS amply supported by the Z8016 DTC DMA
Transfer Controller, a fast dual-channel

devlCe that enhances the addressmg
power of the Z8000 CPU in stand-alone
or parallel-processor envIronments.
General purpose control and datamanipulation problems are smoothly
solved by the Z8034 Z-UPC Universal
Peripheral Controller, a complete offlme mlCrocomputer-on-a-chlp WIth
three 110 ports. ThIs processor
executes the same friendly, capable
mstruchon set as our Z8 MlCrocomputer. BIts and pieces of asynchronous
parallel-processing systems are interconnected by the Z8038 Z-FIO FIFO
Input/Output, a surprIsingly fleXIble
device that can interface any major
microprocessor and most penpherals to
the Z-BUS. Its buffer depth can be
expanded WIthout hmlt using the
Z8060 FIFO,
Where high-speed error detechon
and correchon are essenhal, the Z8065
Burst Error Processor (Z-BEP) offers a
chOlce of four selectable mdustrystandard polynomials and three correchans algonthms. It IS effective for data
rates of up to 20M bits per second. If
encryphon or decryphon of data IS
necessary, the Z8068 Data Ciphermg
Processor (Z-DCP) supports three standard clphermg ophons and key panty
check. It can also mput, output, and
encIpher sImultaneously. To perform
hIgh-speed anthmehc now, the Z8070
Floatmg Pomt Emulation Package (WIth
IEEE P754 Standard format) can be
Implemented WIth any Z8000 mlCroprocessor. Later thIS software package
will be replaceable by the Z8070
Floatmg Pomt Anthmehc Processmg
Umt Itself.

Z8001/2
Z8000™ CPU Central
Processing Unit

~
Zilog

Product
Specification

June 1982

Features

• Regular, easy-to-use archItecture
• Instruchon set more powerful than many
minicomputers

• Mulh-programmmg support

• Directly addresses 8M bytes

• ComplIer support

• EIght user-selectable addressmg modes

• Memory management and protechon provIded by Z8010 Memory Management Umt

• Seven data types that range from bIts to
32-bIt long words and byte and word strmgs

General
Description

• Resource-sharmg capabIllhes for mulhprocessmg systems

• System and Normal operatmg modes

• 32-blt operahons, mcluding sIgned mulhply
and dIvIde

• Separate code, data and stack spaces

• Z-BUS compahble

• Sophlshcated mterrupt structure

• 4, 6 and 10 MHz clock rate

The Z8000 is an advanced hIgh-end 16-blt
mIcroprocessor that spans a wIde varIety of applicahons ranging from sImple stand-along
computers to complex parallel-processing
systems. Essenhally a monolithic mmicomputer
central processmg umt, the Z8000 CPU IS
characterIzed by an mstruchon set more
powerful than many mmicomputers; abundant
resources in registers, data types, addressmg
modes and addressmg range; and a regular
architecture that enhances throughouput by
avoidmg crIhcal bottlenecks such as ImplIed or
dedicated registers.
CPU resources mclude sIxteen J6-blt
general-purpose registers, seven data types
that range from bits to 32-bit long words and
byte and word strmgs, and eIght userselectable addressmg modes. The 110 dlStmct
instruchon types can be combmed with the
varIOUS data types and addressmg modes to
form a powerful set of 414 mstruchons.
Moreover, the mstruchon set is regular; most
mstruchons can use any of the five mam addressmg modes and can operate on byte, word
and long-word data types.
The CPU can operate m eIther the system or
normal modes. The distinchon between these
two modes permits prIVIleged operatIOns,
thereby Improvmg operating system orgamzahon and implementahon. Mulhprogrammmg is
supported by the "atomIc" Test and Set m-

struchon; mulhprocessmg by a combmahon of
mstruchon and hardware features; and compilers by multiple stacks, specIal mstruchons
and addressmg modes.

AS
BUS{
TIMING

os
MifECi
READ/WRiTE

AD11

NORMALlSVS'l'E'M

.nru.{

BYTE/WORD

ADDRESS I
DATA BUS

ST,
ST,
ST,
ST,

CPU{
CONTROL

Z8001
Z8002

CPU

T':~~

BUS{
CONTROL

SEGMENT:
NUMBER I

INTERRUPTS{

I
I
I

SN,
MULTI·MICRO {
CONTROL

I

Figure 1. Z8000 CPU Pin Functions

2001·0089

125

The 28000 CPU is offered in two versions:
the 28001 48-pin segmented CPU and the
28002 40-pin non-segmented CPU. The main
difference between the two is in addressing
range. The 28001 can directly address 8 megabytes of memory; the 28002 directly addresses
64 kilobytes. The two operating modes-system
and normal-and the distinction between code,
data and stack spaces within each mode allows
memory extension up to 48 megabytes for the
28001 and 384 kilobytes for the 28002.
To meet the requirements of complex,
memory-intensive applications, a companion

memory-management device is offered for the
28001. The 28010 Memory Management Unit
manages the large address space by providing
features such as segment relocation and
memory protection. The 28001 can be used
with or without the 28010. If used by itself, the
28001 still provides an 8 megabyte direct
addressing range, extendable to 48 megabytes.
The 28001, 28002 and 28010 are fabricated
with high-density, high-performance scaled
n-channel silicon-gate depletion-load technology, and are housed in dual in-line
packages.

Register
The 28000 CPU is a register-oriented
Organization machine that offers sixteen 16-bit generalpurpose registers and a set of special system
registers. All general-purpose registers can be
used as accumulators and all but one as index
registers or memory pOinters.
Register flexibility is created by grouping
and overlapping multiple registers (Figures 2

and 3). For byte operations, the hrst eight
16-bit registers (RO ... R7) are treated as sixteen
8-bit registers (RLO, RHO, ... , RL7, RH7). The
sixteen 16-bit registers are grouped m pairs
(RRO ... RR14) to form 32-bit long-word
registers. Similarly, the register set is grouped
in quadruples (RQO ... RQI2) to form 64-bit
registers.

General
Description
(Continued)

RRO {

RO "
Rl '15

RHO
RHl

01,

RLO

01
ROO

R.'

RH'

RL'

R.'

RH.

RL'

R41

RH4

RL4

R.'

RH.

RR' {

RLO

RRO {
R'I

RH'

RL'

{ Rl0

RH'

RL'

R41

RH4

RL4

R.'

RH'

RL'

Rol

RHO

RLO

R'I

RH'

RL'

R04

RQ8

R121
RR12 {

R13

126

R'I

ROO

R111

RR12 {

Stacks

RL'

RR10 {

R12

R15'

RH'

Rl0'

R11

R15

R'I

I
I

R9'

ROO

RR14 [

o

RRO {

R.

R14'

RLl

Rol15

RR8 {

R14

o

Rll15

RRO {

R8 15

RR10

RLO

RHl

RR4 {

RL'
R04

RH8

RHO

RR. {

RR4 {

Rol

I,

Rol'
RRO {

RLl

R131
SYSTEM STACK POINTER (SEG. NO)

RQ12

RR14 {
SYSTEM STACK POINTER (OFFSET)

NORMAL STACK POINTER (OFFSET)

RQ12

R141

NORMAL STACK POINTER (SEG. NO)

R15'

R15

SYSTEM STACK POINTER
NORMAL STACK POINTER

Figure 2. Z8001 General-Purpose Registers

Figure 3. Z8002 General-Purpose Registers

The 28001 and 28002 can use stacks located
anywhere in memory. Call and Return instructions as well as mterrupts and traps use implied stacks. The distinction between normal
and system stacks separates system information
from the application program information. Two
stack pOinters are avallable: the system stack
pointer and the normal stack pointer. Because
they are part of the general-purpose register

group, the user can manipulate the stack
pointers With any instruchon available for
register operahons.
In the 28001, register pair RR14 is the
Implied stack pOinter. Register Rl4 contains
the 7-bit segment number and Rl5 contams the
16-bit offset. In the 28002, register Rl5 IS the
Implied 16-blt stack pOinter.

2001-0090, 0091

Refresh

Program
Status
Information

The Z8000 CPU contains a counter that can
be used to automatically refresh dynamic
memory. The refresh counter regIster consIsts
of a 9-blt row counter, a 6-bit rate counter and
an enable bit (Figure 4). The 9-blt row counter
can address up to 256 rows and is Incremented
by two each time the rate counter reaches endof-count. The rate counter determines the time
between successIve refreshes. It consists of a
programmable 6-blt modulo-n prescaler

(n = 1 to 64), driven at one-fourth the CPU
clock rate. The refresh perIOd can be programmed by 1 to 64 p.s with a 4 MHz clock. Refresh
can be dIsabled by programming the refresh
enable/disable bIt.

This group of status registers contains the
program counter, flags and control bits. When
an interrupt or trap occurs, the entire group is
saved and a new program status group is
loaded.
Figure 5 illustrates how the program status
groups of the Z8001 and Z8002 differ. In the
non-segmented Z8002, the program status
group consists of two words: the program
counter (PC), and the flag and control word
(FCW). In the segmented Z8001, the program

status group consists of four words: a two-word
program counter, the flag and control word,
and an unused word reserved for future use.
Seven bits of the first PC word designate one
of the 128 memory segments. The second word
supplies the 16-blt offset that deSIgnates a
memory location wIthin the segment.
WIth the exception of the segment enable bIt
In the Z8001 program status group, the flags
and control bIts are the same for both CPUs.

"

"

.ow

RATE

I

1

J

Figure 4. Refresh Counter

,

"

1..1_".J.1_"...I'_"...JI,-"--1...'_".J.I_".I.I_"...J'_"--1...'_"J..'_".J.'_"...11_"_',-"--1...'_".J.'_"...1'_"-11

}~~i~VED

1_'
..

Lls_,o.J.1WM.....J.I_"...JA1'-"_'1..INV_".J.I_".I.'_"...J'_'-L!c-,-I_'.J.I_'...II_'N...J1C-'_".L..I_".J.I_,....,_,-II

}&~;\:~~

L-",--'--...L-L---1...-1.-iI--.JIL-I.'-L-i--.J_LL-L.J.

I, 1

SeGMENT NUMBER

I

!

I

ADDRESS

}~~~1:g~

II

PI!.OGRAM

COUNTER

Z8002 Program Status RegIsters

, 1' )'"00'".

,

8_'"....I_'' ...JI_''_'LINV_".L..I_'.J..1_'...I1_'...J1'-'--1...1_'.J.I_'.I.I_'N...JI_'_"1..1_".J.1_'...I'_'...J1

oLl

1

:=:=:======:=:~'~Ei=M':"~,o="'~,":==:========:,=~I

COUNTER

28001 Program Status RegIsters

r

SEGMENT NUMBER

!

!

I

28002 Program Status Area Pomter

UPPERDFFSET

I

!

UPPER POINTER
I
I
!

t

28001 Program Status Area Pomter

Figure S. Z8000 CPU Special Registers
Interrupt
and Trap
Structure

2045-0282. 0283

The Z8000 provides a very flexible and
powerful interrupt and trap structure. Interrupts are external asynchronous events reqUIrIng CPU attention, and are generally triggered
by peripherals needing service. Traps are synchronous events resulting from the execution
of certain instructions. Both are processes In a
SImilar manner by the CPU.
The CPU supports three types of Interrupts
(non-maskable, vectored and non-vectored)
and four traps (system call, Extended Process
Architecture, privileged instructions and
segmentation trap). The vectored and nonvectored Interrupts are maskable. Of the four
traps, the only external one is the segmentation trap, which IS generated by the Z801O.
The remaining traps occur when instructions
limited to the system mode are used in the normal mode, or as a result of the System Call instruction, or for an EPA instruction. The
descending order of Priority for traps and in-

terrupts IS: Internal traps, non-maskable interrupt, segmentatIOn trap, vectored interrupt
and non-vectored interrupt.
When an interrupt or trap occurs, the current program status IS automatically pushed on
the system stack. The program status consists
of the processor status (PC and FCW) plus a
16-blt identifier. The Identifier contains the
reason or source of the trap or interrupt. For
mternal traps, the idenhfler IS the first word of
the trapped instruchon. For external traps or
interrupts, the identifier is the vector on the
data bus read by the CPU during the
interrupt-acknowledge or trap-acknowledge
cycle.
After saving the current program status, the
new program status IS automatically loaded
from the program status area in system
memory. ThIS area IS deSIgnated by the program status area pomter (PSAP).

127

Data
Types

28000 instructions can operate on bIts, BCD
digits (4 bits), bytes (8 bits), words (16 bits),
long words (32 bits) and byte strmgs and word
strings (up to 64 kilobytes long), and word strings (up to 64 blobytes long). Bits can be set,
reset and tested; digits are used in BCD
arithmetic operations; bytes are used for
characters or small integer values; words are
used for integer values, instructions and nonsegmented addresses; long words are used for

, Segmentation
HIgh-level languages, sophlshcated operatand Memory ing systems, large programs and data bases,
Management and decreasing memory prices are all ac-

celerating the trend toward larger memory reqUIrements in mICrocomputer systems. The
28001 meets this requirement wIth an eight

long integer values and segmented addresses.
All data elements except strings can resIde
either in registers or memory. Strings are
stored m memory only.
The basic data element is the byte. The
number of bytes used when manipulating a
data element is either imphed by the operation
or - for strings and mulhple register operations - explicitly specified in the instruction.
megabyte addressmg space. ThIs large address
space IS directly accessed by the CPU using a
segmented addressmg scheme and can be
managed by the 28010 Memory Management
Unit.

Segmented
Addressing

A segmented addressing space - compared
with linear addressmg - is closer to the way a
programmer uses memory because each procedure and data space resIdes m its own segment. The 8 megabytes of 28001 addressing
space IS divIded into 128 relocatable segments
up to 64 kilobytes each. A 23-bit segmented
address uses a 7-blt segment address to point
to the segment, and a 16-bit offset to address
any location relative to the begmning of the
segment. The two parts of the segmented address may be manipulated separately. The
segmented 2800 I can run any code written for
the non-segmented 28002 m anyone of ItS 128
segments, provided it IS set to the nonsegmented mode.

In hardware, segmented addresses are contamed in a register pair or long-word memory
locahon. The segment number and offset can
be manipulated separately or together by all
the available word and long-word operahons.
When contamed in an mstruction, a
segmented address has two dIfferent representations: long offset and short offset. The long
offset occupies two words, whereas the short
offset requires only one and combmes in one
word the 7-blt segment number WIth an 8-bit
offset (range 0-256). The short offset mode
allows very dense encoding of addresses and
mmlmizes the need for long addresses reqUIred by duect accessmg of this large address space.

Memory
Management

The addresses manipulated by the programmer, used by instruchons and output by the
28001 are called logical addresses. The
Memory Management Unit takes the logICal
addresses and transforms Jhem into the
physical addresses required for acceSSing the
memory (Figure 6). This address transformahon process is called relocation. Segment
relocatIOn makes user software addresses independent of the physIcal memory so the user is
freed from specifying where mformation IS
actually located m the physical memory.
The relocation process is transparent to user
software. A translation table in the Memory
Management Unit associates the 7-bit segment
number WIth the base address of the physical
memory segment. The 16-bit offset is added to
the physical base address to obtain the actual
physical address. The system may dynamically
reload translahon tables as tasks are created,
suspended or changed.
In addItIOn to supportmg dynamic segment
relocation, the Memory Management Unit also
provIdes segment protection and other segment management features. The protection
features prevent illegal uses of segments, such
as writing mto a write-protected zone.
Each Memory Management Unit stores 64
segment entries that consist of the segment

base address, its attributes, size and status.
Segments are variable in size from 256 bytes to
64 kilobytes in increments of 256 bytes. Pairs
of Management Units support the 128 segment
numbers available for each of the six CPU
address spaces. Within an address space,
several Management Units can be used to
create multiple translation tables.

128

LOGICAL ADDRESS

L.....--,-,-_.....

----I

r--------I MEMORY

I MANAGMENT
I UNIT
I
I

BASE

ADDRESS
REGISTER
FILE

I

I
I
I

I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I

I

I
I
I
I

23
24-BIT PHYSICAL ADDRESS

L ________ _

__-1

Figure 6. Logical-Io-Physical Address
Transformation
2045·0284

Extended
Processing
Architecture

The Zilog Extended Processing Architecture
(EPA) provides an extremely flexible and
modular approach to expanding both the hardware and software capabilities of the Z8000
CPU. Features of the EPA include:
• Specialized instructions for external processors or software traps may be added to
CPU instruction set.
• Increases throughput of the system by using
up to four specialized external processors in
parallel with the CPU.
• Permits modular design of Z8000-based
systems.
• Provides easy management of multiple
microprocessor configurations via "single
instruction stream" communication.
• Simple interconnection between extended
processing units and Z8000 CPU requires no
additional external supporting logic.
• Supports debugging of suspect hardware
against proven software.
• Standard feature on all Zilog Z8000 CPUs.
Specific benefits include:
• EPUs can be added as the system grows and
as EPUs with speCialized functions are
developed.
• Control of EPUs is accomplished via a
"single instruction stream" in the Z8000
CPU, eliminating many significant system
software and bus contention management
obstacles that occur in other multiprocessor
(e.g., master-slave) organization schemes.
The processing power of the Zilog Z8000
16-bit microprocessor can be boosted beyond
its intrinsic capability by Extended Processing
Architecture. Simply stated, EPA allows the

Z8000 CPU to accommodate up to four Extended Processing Units (EPUs), which perform
specialized functions in parallel with the CPU's
main instruction execution stream.
The use of extended processors to boost the
main CPU's performance capability has been
proven with large mainframe computers and
minicomputers. In these systems, specialized
functions such as array processing, special
input/output processing, and data communications processing are typically assigned to
extended processor hardware. These extended
processors are complex computers in their own
right.
The Zilog Extended Processing Architecture
combines the best concepts of these proven
performance boosters with the latest in highdensity MOS integrated-circuit design. The
result is an elegant expansion of design
capability-a powerful microprocessor
architecture capable of connecting Single-chip
EPUs that permits very effective parallel
processing and makes for a smoothly integrated instruction stream from the Z8000 programmer's point of view. A typical addition to
the current Z8000 instruction set might be
Floating Point Instructions.
The Extended Processing Units connect
directly to the Z8000 BUS (Z-BUS) and continuously monitor the CPU instruction stream.
When an extended instruction is detected, the
appropriate EPU responds, obtaining or
placing data or status information on the
Z-BUS using the Z8000-generated control
signals and performing its function as directed.
The Z8000 CPU is responsible for instructing
the EPU and delivering operands and data to
it. The EPU recognizes instructions intended
for it and executes them, using data supplied

Figure 7. Typical Extended Processor Configuration

2007-001

129

Extended
Processing
Architecture
(Continued)

with the instruction and/or data within its internal registers. There are four classes of EPU
instructions:

28000 CPU.
This software trap mechanism facilitates the
design of systems for later addition of EPUs:
initially, the extended function is executed as a
trap subroutine; when the EPU is finally
attached, the trap subroutine is eliminated and
the EPA control bit is set. Application software
is unaware of the change.
Extended Processing Architecture also offers
protection against extended instruction overlapping. Each EPU connects to the 28000 CPU
via the STOP line so that if an EPU is
requested to perform a second extended
instruction function before it has completed the
previous one, it can put the CPU into the
Stop/Refresh state until execution of the
previous extended instruction is complete.
EPA and CPU instruction execution are
shown in Figure 8. The CPU begins operation
by fetching an instruction and determining
whether it is a CPU or an EPU command. The
EPU meanwhile monitors the 2-BUS for its own
instructions. If the CPU encounters an EPU
command, it checks to see whether an EPU is
present; if not, the EPU may be simulated by
an EPU instruction trap software routine; if an
EPU is present, the necessary data and/or
address IS placed on the 2-BUS. If the EPU is
free when the instruction and data for it
appear, the extended instruction is executed.
If the EPU is still processing a previous
instruction, it activates the CPU's STOP line to
lock the CPU off at the 2-BUS until execution
is complete. After the instruction is finished,
the EPU deactivates the STOP line and CPU
transactions continue.

• Data transfers between main memory and
EPU registers
• Data transfers between CPU registers and
EPU registers
• EPU internal operations
• Status transfers between the EPUs and the
28000 CPU Flag and Control Word register
(FCW)
Four 28000 addressing modes may be utilized
with transfers between EPU registers and the
CPU and main memory:
• Register
• Indirect Register
• Direct Address
• Indexed
In addition to the hardware-implemented
capabilities of the Extended Processing
Architecture, there is an extended instruction
trap mechanism to permit software simulation
of EPU functions. A control bit in the 28000
FCW register indicates whether actual EPUs
are present or not. If not, when an extended
instruction is detected, the 28000 traps on the
instruction, so that a software "trap handler"
can emulate the desired EPU function-a very
useful development tool. The EPA software
trap routine supports the debugging of suspect
hardware against proven software. This feature
will increase in significance as designers
become familiar with the EPA capability of the

I

I

I

&.

IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

.& DATA OR ADDRESSES ARE PLACED ON THE BUS AND USED BY THE EPU IN THE EXECUTION OF AN INSTRUCTION
Figure S. EPA and ZSOOO CPU Instruction Execution

130

2007-002

Addressing
Modes

The information included in 28000 instructions consists of the function to be performed,
the type and size of data elements to be
manipulated and the location of the data
elements. Locations are designated by register
addresses, memory addresses or I/O
addresses. The addressing mode of a given
instruction defines the address space it references and the method used to compute the
address itself. Addressing modes are explicitly
speCified or implied by the instruction.

Mode

Operand Addressing
In the Instruction

Register

Figure 4 illustrates the eight addressing
modes: Register (R)' Immediate (1M), Indirect
Register (IR), Dire~t Address (DA), Indexed
(X), Relative Address (RA), Base Address (BA)
and Base Indexed (BX). In general, an addressing mode explicitly specifies either
register address space or memory address
space. Program memory address space and
I/O address space are usually implied by the
instruction.

I

REGISTER ADDRESS

In Memory

In a Register

H

Operand Value

N

OPERAND

I

i...

The content of the
register

N

Immediate

I

OPERAND

Indirect
Register

I

REGISTER ADDRESS

Direct
Address

I

ADDRESS

H{~A~D~DR~E~ss!]I------...·~I~o~PE~R~AN~D~

1'1

OPERAND

I

The content of the location
whose address Is In the
register

The content of the location
whose address is In the
instruction

The content of the location
whose address Is the
address in the Instruction,
offset by the content of
the register

Index

Relative
Address

9

In the instruction

PC VALUE

~

[!D~IS~PL~A~C~EM~E~N~TJ~~====~I

OPERAND

I

The content of the location
whose address Is the
content of the program
counter. offset by the
displacement In the
instruction

Base
Address

The content of the location
whose address is the
address in the register.
offset by the displacement
in the instruction

Base
Index

The content of the location
whose address is the
address In the register.
offset by the displacement in the register

Figure 9. AddresSing Modes

2045-0285

131

Input!
Output

A set of I/O instructions performs 8-bit or.
16"bit transfers betwen the CPU and I/O
devices. 1/0 devices are addressed with a
16-bit 1/0 port address. The 1/0 port address
is similar to a memory address; however, 1/0
address space need not be part of the memory
address space. 1/0 port and memory addresses
coexist on the same bus lines and they are
distinguished by the status outputs.

Two types of 1/0 instructions are available:
standard and special. Each has its own address
space. The 1/0 instructions include a comprehensive set of In, Out and Block 1/0 instructions for both bytes and words. Special I/O instructions are used for loading and unloading
the Memory Management Unit. The status information distinguishes between standard and
speCial 1/0 references.

Multi-MicroProcessor
Support

Multi-microprocessor systems are supported
in hardware and software. A pair of CPU pins
is used in conjunction with certain instructions
to coordmate multiple microprocessors. The
Multi-Micro Out pin issues a request for the
resource, while the Multi-Micro In pin is used
to recognize the state of the resource. Thus,
any CPU in a multiple microprocessor system
can exclude all other asynchronous CPUs from
a critical shared resource.

Multi-microprocessor systems are supported
in software by the instructions Multi-Micro Request, Test Multi-Micro In, Set Multi-Micro
Out and Reset Multi-Micro Out. In addition,
the eight megabyte CPU address space is
beneficial in multiple microprocessor systems
that have large memory requirements.

Instruction
Set
Summary

The 28000 provides the following types of
instructions:

• Bit Manipulation

Load
and
Exchange

• Load and Exchange

• Rotate and Shift
• Block Transfer and String Manipulation

• Arithmetic

• Input/Output

• Logical
• Program Control

• CPU Control
Clock Cycles *

Mnemonics

CLB
CLBB

Operands

dB!

Addr.
Modes
R
IR

DA
X
EX
EXB

R, src

R
IR

DA
X
LO
LOB
LOL

R,src

R
1M
1M
IR

DA
X
BA
BX
LO
LOB
LOL

dst,R

LO
LOB

dst, 1M

• NS

132

IR

DA
X
BA
BX
IR

DA
X

= Non-Segmented

SS

Word. Byte
NS

SS

Long Word

SL

NS

SS

Clear

7

8
11
12
6
12
15
16

dB! 12
12

0

14
15

Exchange
R - src
16
16

18
19

3
7
5 (byte only)
7
9
10
12
10
10
13
14
14

5
II

8
II
12
14
14

II
14
15
17
17

11
14
15

Operation

SL

12
12

14
15

15
15

17
18

II
12
13
17
17

Load into Register
R - src

13
13

15
16

15
15

17
18

Load into Memory (Store)
dst -

R

Load Immediate into Memory

= Segmented Short Offset

SL

= Segmented Long Offset

dst -

1M

Load and
Exchange
(Contmued)

Clock Cycles

Mnemonics

Operands

Addr.
Modes

Word. Byte
N5

55

5L

13
13

IS
16

LDA

H, src

DA
X
BA
BX

12
13
IS
IS

LDAR

R,src

RA

IS

Long Word
N5

55

Operation

5L
Load Address
R - source address

Load Address Relative

R - source address
LDK

R,src

1M

5

LDM

H, sra, n

JR
DA
X

II
14
IS

IS
IS

;7 } +3n
18

Load Multiple
R - src (n consecutive words)
(n = I ... 16)

JR
DA
X

II
14
15

IS
IS

;7 } +3n
18

Load Multiple (Store Mulhple)
dst - R (n consecuhve words)
(n = 1 ... 16)

RA

14

LDM

R,src

LDR
LDRD
LDRL

dst,R

RA

14

17

Load Relative (Store Relahve)
dst - R
(range -32768 ... +32767)

POP
POPL

dst,JR

R
IR
DA
X

8
12
16
16

12
19
23
23

Pop
dst -

R
1M
JR
DA
X

9
12
13
14
14

JR, src

ADC
ADCD

H, sra

R

5

ADD
ADDD
ADDL

H, sra

R
1M
JR
DA
X

4

9
10

R
1M
JR
DA
X

4
7
7
9
10

JR
DA
X

II
14
15

CP
CPD
CPL

H, sra

17

16
16

18
19

Load Relative
R - src
(range -32768 ..

23
23

25
26

16
17

20
21
21

+32767)

IR

Automcrement contents of R

21
21

23
24
Add with Carry
R-R+src + carry

12
13

8
14
14
IS
16

10
10

12
13

8
14
14
IS
16

15
15

17
18

10
10

Add
R-R + sra

16
16

18
19
Compare with Register
R - sra

16
16

18
19
Compare with Immediate
dst - 1M

CP
CPD

dst,IM

DAD

dst

R

5

Decimal Adjust

dst,n

R
IR
DA
X

4
II
13
14

Decrement by n
dst-dst-n
(n = I . . 16)

DEC
DECD

Q
a

Push
Autodecrement contents of R
JR - src

12

14
14

N

g
...
iii

LDR
LDRD
LDRL

PUSH
PU5HL

Arithmetic

dst,R,n

Load Constant
R - n (n = 0 ... IS)

14
14

16
17

133

Arithmetic
(Continued)

Clock Cycles

Mnemonics

DIV
DIVL

Operands

Addr,
Modes

INC
INCB

MULT
MULTL

NEG
NEGB

Logical

Operation

SL

R

11

11

Extend Sign
Extend sIgn of low order half of dst
through hIgh order half of dst

dst,n

R
IR
DA
X

4
11
13
14

R

IR
DA
X

70
70
70
71

72

72

72

R
IR
DA
X

7
12
15
16

R

5

R

4
7
7
9
10

R, sre

1M

dst

1M
IR
DA
X
R, src

R

IR
DA
X

4
7
7
9
10

R
IR
DA
X

7
12
15
16

R

IR
DA
X

4
7
7
9
10

1M

dst

R, src

1M

TCC
TCCB

ee,dst

R

5

TEST
TESTB
TESn

dst

R
IR
DA
X

7
8

R, src

R

1M
IR
DA
X

134

SS

dst

R, src

XOR
XORB

Long Word
NS

X

SUB
SUBB
SUBL

OR
ORB

SL

Divide (signed)
Word: Rn+l - Rn,n+l + sre

R,sre

COM
COMB

SS

744 744 744 744 744
745 746 748
746 746 749

R

1M

SBC
SBCB

AND
ANDB

NS

107
107
107 107 107
108 109 III
109 109 112

R,sro

IR
DA

EXTS
EXTSB
EXTSL

Word. Byte

11

12
4
7
7
9
10

14
14

remamder
Rn , n + 1 -

282'
282'
282'
283'
284'

-

284' 286'
284' 287'

Multiply (sIgned)
Word: Rn,n+l - Rn+I' sre
Long Word: Rn n+ 3 -Rn+2, n+3
* Plus seven cycles for each 1 m the
mulhpheand
Negate
dst-O-dst

16
16

18
19

Subtract with Carry
R - R-src-carry

10
10

12
13

8
14
14
15
16

Subtract
R-R-sre

16
16

18
19

AND
R-RANDsre

10
10

12
13
Complement
dst - NOT dst

16
16

18
19
OR
R - R OR src

10
10

12
13
Test Condition Code
Set LSB 11 ee IS true

12
12

14
15

13
13
16
17

TeBt
dst OR 0

17
17

19
20
Exclusive OR
R - R XOR sre

10
10

12
13

remainder

Increment by n
dst-dst+n
(n ~ 1 ... 16)

16
17

74
75

Rn -

Long Word: Rn +2,n+3 - Rn ... n+3 + sre

Program
Control

Cloc:k Cycles
Mnemonics

CALL

CALR

Operands

Adc1r.
Modes

dst

dst

Word. Byte

Long Word
NS

SS

Operation

SL

NS

SS

SL

IR
DA
X

10
12
13

15
20
21

Call Subroutine

18
18

RA

10

15

Call Relative

Autodecrement SP
@SP-PC
PC - dst

Autodecrement SP
@SP-PC
PC - PC + ds! (range -4094 to + 4096)

DJNZ
DBJNZ

R,dst

RA

Decrement and Jump If Non-Zero

II

R - R- I
If R 0: PC - PC + ds! (range -254 to 0)

'*

IRET*

13

Interrupt Return

16

PS-@SP
Automcrement SP

JP

JR

cc,dst

cc,dst

IR
IR
DA
X

10
7
7
8

RA

6

8
8

15
7
10
II

(taken)
(not taken)

I

Jump Conditional
If cc

IS

~

true: PC - dst

ft

~

Jump Conditional Relatl"e
If cc IS true: PC - PC + dst
(range -256 to + 254)

RET

SC

cc

src

1M

10
7

13
7

33

39

(taken)
(not taken)

Return Conditional
If cc

IS

true: PC - @ SP
Automcrement SP

System Call
Autodecrement SP
@SP-oldPS
Push InstructIon

PS - System Call PS

Bit

Manlpulation

BIT
BITB

dst,b

BIT
BITB

dst,R

RES
RESB

dst,b

R
IR
DA
X

4
8
10
II

R

10

Test Bit Static
Z flag - NOT dst bit speClhed by b
II
II

13
14

Test Bit Dynamic
Z flag - NOT dst bit speClhed by
contents of R

RES
RESB

dst,R

SET
SETB

dst,b

R
IR
DA
X

4
II
13
14

R

10

Reset Bit Static
Reset dst bit speClhed by b
14
14

16
17

Reset Bit Dynamic
Reset ds! bit speClheci by contents R

DA
X

4
II
13
14

R

10

R
IR

SET
SETB

dst,R

TSET
TSETB

dst

Set Bit Static
Set dst bit speClhed by b
14
14

16
17

Set Bit Dynamic
Set dst bit speclhed by contents of R

"PnvIleged instructIon Executed

R
IR
DA
X
In

7
II
14
15

Test and Set
15
15

17
18

S flag - MSB of dst
dst - allis

system mode only

135

Rotate
and
Shift

Block
Transfer
and String
Manipulation

Clock Cycles
Mnemonics

Addr.
Modes

Word. Byte
NS

SS

SL

Long Word
NS

SS

Operation

SL

R
R

6forn
7forn

=1
=2

Rotate Left

R
R

6forn
7forn

=1
=2

Rotate Left through Carry

R,src

R

9

RR
RRB

dst,n

R
R

6forn
7forn

=1
=2

Rotate Right

RRC
RHCB

dst,n

R
R

6forn
7forn

=I
=2

Rotate Right through Carry

RRDB

R,src

R

9

SDA
SDAB
SDAL

dst,R

R

SOL
SDLB
SDLL

dst,R

SLA
SLAB
SLAL

dst,n

SLL
SLLB
SLLL

dst,n

SRA
SRAB
SRAL

dst,n

SRL
SRLB
SRLL

dst,n

CPO
CPDB

Rx , src, Ry, cc

CPDR
CPDRB

Rx, sre, Ry, cc

RL
RLB

dst,n

RLC
RLCB

dst,n

RLDB

by n bIts (n

by n bits (n

= 1, 2)
= 1,

2)

Rotate Digit Left

(15 + 3 n)

by n bits (n

by n bits (n

= 1,2)
=

1, 2)

Rotate Digit Right
(15 + 3 n)

Shift Dynamic Arithmetic
ShIft dst left or rIght
by contents of R

R

(15 + 3 n)

(15 + 3 n)

Shift Dynamic Logical
ShIft dst left or rIght
by contents of R

R

(13 + 3 n)

(l3+3n)

Shift Left Arithmetic
by n hIts

R

(13 + 3 n)

(13 + 3 n)

Shift Left Logical
by n bIts

R

(13 + 3 n)

(13 + 3 n)

Shift Right Arithmetic
by n bIts

R

(13 + 3 n)

(13 + 3 n)

Shift Right Logical
by n bIts

IR

20

Compare and Decrement
Rx - src
Autodecrement src address
Ry - Ry - I

IR

(l1+9n)

Compare, Decrement and Repeat
RX - src
Autodecrement src address
Ry - Ry - I
Repeat untIl cc IS true or Ry

CPI
CPIB

RX, src, Ry , cc

CPIR
CPIRB

RX, src, Ry , cc

CPSD
CPSDB

136

Operands

IR

20

=0

Compare and Increment
RX - src
Automcrement src address
Ry - Ry - I

IR

(II + 9 n)

Compare. Increment and Repeat
RX - src
Automcrement src address
Ry - Ry - I
Repeat unlIl cc IS true or Ry

dst, sre, R, cc

IR

25

=0

Compare String and Decrement
dst - src
Autodecrement dst and src addresses
R - R- I

Block Transfer
and String
Manipulation

Clock Cycles
Mnemonics

Operands

Addr.
Modes

(Contmued)
CPSDR
CPSDRB

dst, sre, H, cc

CPSI
CPSIB

dst, src, R, cc

CPSIR
CPSIRB

dst, src, R, cc

IR

Word, Byte
NS

SS

SL

(11 + 14 n)

Long Word
NS

SS

Operation

SL
Compare String, Deer. and Repeat
dst - src
Autodecrement dst and src addresses
R - R- 1
Repeat unhl cc IS true or R = 0

IR

25

Compare String and Increment
dst - src
Automcrement dst and src addresses
R- R- 1

IR

(ll+14n)

Compare String, Incr. and Repeat
dst - src
Automcrement dst and src addresses
R- R- 1
Repeat unhl cc IS true or R = 0

N

00

LDD
LDDB

dst, src, R

LDDR
LDDRB

dst, src, R

LDI
LOIB

dst, src, R

LOIR
LOIRB

dst, src, R

IR

TRDB

dst, src, R

IR

IR

IR

20

(11 + 9 n)

8...

Load and Decrement
dst - src
Autodecrement dst and src addresses
R - R- 1

N

"•
CI

Load, Decrement and Repeat
dst - src
Autodecrement dst and src addresses
R - R- 1
Repeat untIl R = 0

IR

20

Load and Increment
clst - src
Automcrement dst and src addresses
R- R- 1

(11 + 9 n)

25

Load, Increment and Repeat
dst - src
Automcrement dst and src addresses
R - R- 1
Repeat untIl R = 0
Translate and Decrement
dst - src (dst)
Autodecrement dst address
R- R- 1

TRDRB

dst, src, R

IR

(11 + 14n)

Translate, Decrement and Repeat
dst - src (dst)
Autodecrement dst address
R - R-l
Repeat untIl R = 0

TRIB

dst, src, R

IR

25

Translate and Increment
dst - src (dst)
Automcrement dst address
R - R- 1

TRIRB

dst, src, R

IR

TRTDB

src 1, src2, R

IR

(11 + 14 n)

25

Translate, Increment and Repeat
dst - src (dst)
Automcrement dst address
R - R-l
Repeat untIl R = 0

Translate and Test, Decrement
RHl - src 2 (src 1)
Autodecrement src 1 address
R- R- 1

137

Block Transfer
and String
Mnemonics
Manipulation

Clock Cycles
Operands

(Continued)

Input/
Output

Addr.
Modes

Word. Byte
N5

55

5L

(II + 14 n)

Long Word
N5

55

Operation

5L

TRTDRB

srcl,src2,R

IR

TRTIB

src I, src2, R

IR

TRTIRB

src I, src2, R

IR

R,sro

IR
DA

10
12

Input
R - sra

IND*
INDB*

dst, src, R

IR

21

Input and Decrement
dst - src
Autodecrement dst address
R - R- I

INDR*
INDRB*

dst, src, R

IR

INI*
INIB*

dst, sro, R

IR

INIR*
INIRB*

dsl, src, R

IR

OUT*
OUTB"

dst,R

IR
DA

10
12

Output
dsl - R

OUTD*
OUTDB*

dsl, src, R

IR

21

Output and Decrement
dsl - src
Autodecrement sra address
R - R- I

OTDR*
OTDRB*

dst, src, R

IR

OUTI·
OUTIB*

dsl, src, R

IR

IN*
INB*

25

(II + 14n)

(II + IOn)

21

(II + 10 n)

(II + IOn)

21

Translate and Test. Decr. and Repeat
RHI - src 2 (src I)
Autodecrement src I address
R-R I
Repeat until R = 0 or RHI = 0
Translate and Test. Increment
RHI - src 2 (src I)
Automcrement Brc 1 address
R - R- I
Translate and Test. Incr. and Repeat
RHI - src 2 (src I)
Automcrement Brc 1 address
R - R- I
Repeat until R = 0 or RHI = 0

Input. Decrement and Repeat
dsl - src
Aulodecremenl dsl address
R - R- I
Repeal until R = 0
Input and Increment
dsl - src
Automcrement dst address
R - R- I
Input. Increment and Repeat
dsl - src
Automcrement dst address
R - R- I
Repeal until R = 0

Output. Decrement and Repeat
dsl - src
Autodecrement ~c address
R - R- I
Repeal until R = 0
Output and Increment
dst -

sra

Automcrement
R - R- I

OTIR*
OTIRB*

dsl, src, R

IR

(II + 10 n)

138

address

Output. Increment and Repeat
dst - Brc
Automcrement sra address

R - R- I
Repeat until R
* Pnvlleged

Brc

mstruchons Executed m system mode only

=0

Input/Output
(Continued)

Clock Cycl..
Mnemonics

Operands

Addr.
Mod..

SIN"
SINB"

Word, Byte
NS

R,sra

DA

12

SIND"
SINDB"

ds!, src, R

IR

21

SINOR"
SINDRB"

ds!, src, R

IR

SINI"
SINIB"

ds!,src,R

IR

SINIR"
SINlRB"

ds!, src, R

IR

SS

SL

Long Word
NS

SS

Operation

SL

Special Input
R - sre
Special Input and Decrement
dst - src
Au!odecremen! ds! address
R - R- 1

(11 + lOn)

Special Input. Decrement and Repeat
ds! - sre
Au!odeeremen! ds! address
R - R-1
Repea! unhl R : a
Special Input and Increment
ds! - sre
Au!omeremen! ds! address
R - R- 1

21

(II + Ian)

Special Input, Increment and Repeat
ds! - src
Au!omcremen! ds! address
R- R- 1
Repea! unlIl R : a

SOUTo
SOUTB"

ds!, src

DA

12

Special Output
ds! - src

SOUTO"
SOUTOB"

ds!, src, R

IR

21

Special Output and Decrement
ds! - sre
Au!odeeremen! src address
R- R- 1

SOTDR"
SOTDRB"

ds!,src,R

IR

SOun"
SOUTIB"

ds!, src, R

IR

(ll+lOn)

Special Output, Decr. and Repeat
ds! - src
Autodecrement src address
R - R- 1
Repea! unhl R : a
Special Output and Increment
ds! - sre

21

Automcrement src address
R - R- 1

CPU

SOTIR"
SOTIRB"

ds!, src, R

(11 + lOn)

Special Output,lncr. and Repeat
ds! - src
Automcrement src address
R - R- 1
Repeat unlIl R : a

COMFLG

flags

7

Complement Flag
(Any combmalIon of C, Z, S, PlY)

01"

m!

7

Disable Interrupt
(Any combmal1on of NVI, VI)

EI"

m!

7

Enable Interrupt
(Any combma!lOn of NVI, VI)

R

Control

HALT*

(8 + 3 n)

HALT

LDCTL"

CTLR,src

R

7

Load into Control Register
CTLR - Brc

LDCTL*

dst,CTLR

R

7

Load &om Control Register
ds! - CTLR

*Prlvlleged instructions Executed

10

system mode only

139
-------

----

--- ----

I
ia

ft

•
c:I

CPU
Control
(Continued)

Clock Cycles
Mnemonics

LDCTLB

Operands

Addr.
Modes

NS

R

7

FLGR, sra

Word. Byte
55

SL

Long Word
NS

SS

Operation

SL
Load Into Flag Byte Register
FLGR - src

LDCTLB

dst,FLGR

R

Load from Flag Byte Register

7

dst -

LOPS*

IR

src

DA
X

MBIT*

12
16
17

20
20

FLGR

Load Program Status

16
22
23

PS - src

Test Multi-Micro Bit

7

Set S If

MREQ*

R

dst

(12 + 7 n)

Mi lS Low;

5

Multi-Micro Reset

MSET*

5

Multi-Micro Set

NOP

7

No Operation

7

Reset Flag

flag

Mi 1S H1gh.

Multi-Micro Request

MRES*

RESFLG

reset S If

(Any combmahon of C, Z, S, PlY)

SETFLG

Set Flag

7

flag

(Any combmahon of C, Z, S, PlY)
*Pnvlleged mstruchons Executed

Condition
Codes

In

system mode only

Code

Meaning

Flag Settings

Z
NZ
C
NC
PL
MI
NE
EQ
OV
NOV
PE
PO
GE
LT
GT
LE
UGE
ULT
UGT
ULE

Always false
Always true
Zero
Not zero
Carry
No Carry
Plus
Mmus
Not equal
Equal
Overflow
No overflow.
Panty IS even
Panty 1S odd
Greater than or equal (slgned)
Less than (slgned)
Greater than (slgned)
Less than or equal (slgned)
UnsIgned greater than or equal
U nS1gned less than
UnsIgned greater than
UnS1gned less than or equal

Z
I
Z
0
C
I
C = 0
S = 0
S
I
Z = 0
Z = I
PlY = I
PlY = 0
PlY = I
PlY = 0
(S XOR P/V) = 0
(S XOR PlY) = I
[Z OR (S XOR PIY)J
0
[Z OR (S XOR P!V)J
I
C=O
C = I
[(C = 0) AND (Z = O)J = I
(C OR Z) = I

Note that some condihon codes have IdentIcal flag settmgs and bmary £Ields
Z = EQ, NZ = NE, C = ULT, NC = UGE, OV = PE, NOV = PO

Status
Code
Lines

140

ST3-STO
0000
000 I
00 I 0
001 I
0100
0101
o I 10
oI I I

Definition
Internal operation
Memory refresh
1/0 reference
Spec1al 110 reference (e.g., to an MMU)
Segment trap acknowledge
Non-maskable mterrupt acknowledge
Non-vectored mterrupt acknowledge
Vectored mterrupt acknowledge

ST3-STO
1000
100 I
10 I 0
101 I
I 100
I 101
I I 10
IIII

In

CC Field
0000
1000
0110
1110
01 II
IIII
1101
0101
1110
0110
0100
1100
0100
1100
1001
0001
10to
0010
IIII
0111
1011
0011

the instructIon:

Definition
Data memory request
Stack meplOry request
Data memory request (EPU)
Stack memory request (EPU)
Program reference, nth word
Instruction fetch, £Irst word
ExtenSIon processor transfer
Reserved

Pin
Description

ADo-ADls, Address/Data (Inputs/outputs,
active HIgh, 3-state). These multiplexed
address and data lines are used both for I/O
and to address memory.

Nis. Normal/System Mode (output, Low

=

AS. Address Strobe (output, active Low,

System Mode, 3-state). Nis indIcates the CPU
IS In the normal or system mode.

3-state). The rising edge of AS indICates
addresses are valid.

NVI. Non- Vectored Interrupt (Input, active

BUSACK. Bus Acknowledge (output, active

Low). A Low on thIS line requests a nonvectored interrupt.

Low). A Low on thIs line indICates the CPU has
relinqUIshed control of the bus.

RESET. Reset (Input, active Low). A Low on

BUSREQ. Bus Request (Input, active Low).

thIS line resets the CPU.

ThIs line must be driven Low to request the
bus from the CPU.

R/W. Read/Wnte (output, Low = Write,
3-state). R/W indICates that the CPU IS reading
from or writing to memory or I/O.

B/W. Byte/Word (output, Low = Word,
3-state). ThIs SIgnal defines the type of memory
reference on the 16-blt address/data bus.

SEGT. Segment Trap (mput, active Low). The

CLK. System Clock (Input). CLK is a 5V
single-phase time-base input.
OS. Data Strobe (output, active Low, 3-state).
ThIs line times the data in and out of the CPU.

MREQ. Memory Request (output, active Low,
3-state). A Low on thIs line indICates that the
address/data bus holds a memory address.

MI. Mo. MulfJ-MlCro In, MulfJ-MlCro Out
(Input and output, active Low). These two lines
form a resource-request daIsy chain that allows
one CPU In a multi-mICroprocessor system to
access a shared resource.

NMI. Non-Maskable Interrupt (edge triggered,
input, active Low). A hlgh-to-low transition on
NMI requests a non-maskable interrupt. The
ADo

AD.

AD"

SN.

AD10

SN,

AD11

AD,

Memory Management Umt Interrupts the CPU
wIth a Low on thIS line when the MMU detects
a segmentatIOn trap. Input on 28001 only.
HIgh, 3-state). These lines prOVIde the 7-blt
segment number used to address one of 128
segments by the 28010 Memory Management
Umt. Output by the 28001 only.

STo-ST3. Status (outputs, active HIgh, 3-state).
These lines specify the CPU status (see table).
STOP. Stop (input, active Low). ThIS Input can
be used to single-step Instruction execution.

VI. Vectored Interrupt (Input, active Low). A
Low on thIS line requests a vectored Interrupt.

WAIT. Walf (input, active Low). ThIS line
indICates to the CPU that the memory or I/O
device IS not ready for data transfer.

Reserved. Do not connect.

AD12

AD"

AD"

ADo

AD,

AD10

AD.

STOP

SN,

AD11

AD,

iii,

AD.

AD12

AD,

AD 15

AD,

AD13

AD,

AD14

AD,

STOP

AD,

+5V

AD,

1If,

ADo

SN,

AD15
AD14

AD,

OND
CLOCK

+5V

GND

Vi
SEGT

AD,

RESERVED

Vi
liVi

lifo

Bm

NMI

MREQ

RESET

lIS

NIS
RiW

lifo

Nil

ST,

BUSACK

MREli

RIW

ST,

WAIT

ST,

BUSREQ

ST.

SN.

ST,

BUSREQ

SN,

SN,

ST,

ST.

NMI
RESET

Figure 10.

AS

zaool Pin Aaaignmenls

lIS
ST,

I
iii

SNo-SNs. Segment Number (outputs, active

AD13

NVI

2045·0286, 0287

NMI Interrupt has the hIghest prIOrity of the
three types of Interrupts.

CLOCK

AS
RESERVED
BNI

BUSACK

WAif

Figure 11. zaOO2 Pin Aaalgnmenls

141

9

Z8000
CPU

Timing

Memory
Read and

Write

The Z8000 CPU executes instructions by
stepping through sequences of basic machine
cycles, such as memory read or write, I/O
device read or write, interrupt acknowledge,
and internal execution. Each of these basic
cycles requires three to ten clock cycles to
execute. Instructions that require more clock
cycles to execute are broken up into several
machine cycles. Thus no machine cycle is
longer than ten clock cycles and fast response
to a Bus Request is guaranteed.
The instruction opcode is fetched by a
normal memory read operation. A memory
refresh cycle can be inserted just after the
completion of any first instruction fetch (IF))
cycle and can also be inserted while the
following instructions are being executed:
MULT, MULTL, DIV, DIVL, HALT, all Shift

instructions, all Block Move instructions, and
the Multi-Micro Request instruction (MREQ).
The following timing diagrams show the
relative timing relationships of all CPU signals
during each of the basic operations. When a
machine cycle requires additional clock cycles
for CPU internal operation, one to five clock
cycles are added. Memory and I/O read and
write, as well as interrupt acknowledge cycles,
can be extended by activating the WAIT input.
For exact timing information, refer to the composite timing diagram.
Note that the WAIT input is not synchronized
in the Z8000 and that the setup and hold times
for WAIT relative to the clock must be met. If
asynchronous WAIT signals are generated,
they must be synchronized with the CPU clock
before entering the Z8000.

Memory read and instruction fetch cycles
are identical, except for the status information
on the STo-ST3 outputs. During a memory
,

read cycle, a 16-bit address is placed on the
ADo-AD15 outputs early in the first clock
period, as shown in Figure 12. (In the Z8001,

.

CLOCK

.

I

-

.

,

,

~

.

I

1

WAIT
INSERTS WAIT STATE

STAT.!!SE.$
(BIW, N/S,

S1 0 -ST3)

,..SNo-SNs

SEGMENT NUMBER

"'""""

is

MREQ

AD

MEMORY ADDRESS

READ

)---

~

DS

READ

Riw

READ

L

/

AD

MEMORY ADDRESS

WRITE

DATA OUT

DS

WRITE

R/W
WRITE

L

\
Figure 12. Memory Read and Write Timing

142

2045·0288

Memory

Read and
Write
(Continued)

Input/
Output

the 7-bit segment number is output on
SNo-SN6 one clock period earlier than the
16-bit address offset to compensate for the
delay in the memory management circuitry.)
A valid address is indicated by the rising
edge of Address Strobe. Status and mode
information become valid early in the memory
access cycle and remain stable throughout.
The state of the WAIT input is sampled in the
middle of the second clock cycle by the falling
edge of Clock. If WAIT is Low, an additional
clock period is added between T2 and T3.
WAIT is sampled again in the middle of this

wait cycle, and additional wait states can be
inserted. This allows interfacing slow
memories. No control outputs change during
wait states.
Although Z8000 memory is word organized,
memory is addressed as bytes. All instructions
are word-aligned, using even addresses.
Within a 16-bit word, the most significant byte
(Os-DIs) is addressed by the low-order address
(Ao = Low), and the least significant byte
(00-07) is addressed by the high-order
address (Ao = High).

va timing is similar to memory read/write
timing, except that one wait state is automatically inserted between T2 and T3 (Figure 13).

Both the segmented Z8001 and the nonsegmented Z8002 use 16-bit va addresses.

CLOCK

-

T,

T.

TWA

T.

I

I

~

I

~-

WAiT

- D<
-

WTUSES -

(

• STo-Sla)

N/S

Ai

~

INSERT WAIT STATE

LOW

rL.J
HIGH

MREQ

ADINPUT

-

D<

PORT ADDRESS

~

}-------

i'

C

iii

INPUT

AlW

INPUT

ADOUTPUT

"-

- LI
-

D<

PORT ADDRESS

DATA OUT

iii
OUTPUT

R1WOUTPUT

r

"\
Figure 13. Input/Output Timing

2045-0289

143

Interrupt and
Segment
Trap Request
and
Acknowledge

The Z8000 CPU recognizes three interrupt
inputs (non-maskable, vectored and nonvectored) and a segmentation trap input. Any
High-to-Low transihon on the NMI input is
asynchronously edge detected and sets the
internal NMI latch. The VI, NVI and
SEGT inputs as well as the state of the internal
NMI latch are sampled at the begmning of T3
m the last machme cycle of any instruchon.
In response to an mterrupt or trap, the subsequent IFl cycle IS exercised, but ignored.
The mternal state of the CPU is not altered and
the instruction wIll be refetched and executed
after the return from the mterrupt routine. The
program counter is not updated, but and the
system stack pointer IS decremented m
preparahon for pushing starting informahon
onto the system stack.
The next machme cycle IS the mterrupt
LASTMACHINE~

I-1~;~~~tT:'~Y
C'OCK

-

INSTRUCTION_~+-_ _ _ _ _ _ _ _ _ _ _

~~~R~~~

CYCL.E

\fVi. iiVi, SIiUT

"'"
INTERNAL

iiiii

\

~'-\

ACKHOWlEDGE

r -____A_um_._M~IC~~A"_._~_'~____~

m····"

rtJLrU

acknowledge cycle. This cycle has five
automatic waft states, with addlhonal wait
states pOSSIble, as shown in FIgure 14.
After the last walt state, the CPU reads the
informahon on ADo-ADl5 and stores it temporarily, to be saved on the stack later in the
acknowledge sequence. ThIS word idenhhes
the source of the interrupt or trap. For the
non-vectored and non-maskable interrupts, all
16 bits can represent peripheral device status
information. For the vectored interrupt, the
low byte is the jump vector, and the hIgh byte
can be extra user status. For the segmentation
trap, the high byte IS the Memory Management
Unit idenhfier and the low byte IS undefmed.
After the acknowledge cycle, the N/S output
mdicates the automahc change to system
mode.

rv

/ L-I \

,

/

/
t--SAMPlE

IV;;;

Biw

STo-ST3

-J
-""\
-

-

x=:==
. X
AD

- X)----

ACKNOWLEDGE

<

IDENTIFIER

>

iiiiiQ

Figure 14. Interrupt and Segment Trap Request! Acknowledge Timing

Status
Saving
Sequence

The machme cycles followmg the mterrupt
acknowledge or segmentahon trap acknowledge cycle push the old status information on
the system stack (FIgure 12) m the followmg
order: the 16-blt program counter; the 7-blt
segment number (Z8001 only); the flag control

A Low on the BUSREQ input mdlCates to the
Bus Request
Acknowledge CPU that another device IS requeshng the
Timing
Address/Data and Control buses. The asynchronous BUSREQ input IS synchronized at the
begmnmg of any machme cycle (FIgure 15). If
144

word; and fmally the interrupUtrap ldentiher.
Subsequent mach me cycles fetch the new program status from the program status area, and
then branch to the mterrupUtrap service
routme.

BUSREQ IS Low, an mternal synchronous
BUSREQ SIgnal IS generated, whlCh-after complehon of the current machme cycle-causes
the BUSACK output to go Low and all bus outputs to go mto the hIgh-Impedance state. The
2045·0290

BUSACK output goes HIgh one clock period
later, mdicating that the CPU will agam take
control of the bus.

Bus Request/ requesting device-typically a DMA-can then
Acknowledge control the bus.
When BUSREQ IS released, it IS synchron(Continued)
ized wIth the rIsmg clock edge and the

"MQ __~____________~_ _~_ _ _ _~-J

~----------------~
~--

Ai

---- --- ----

- - - - - - t - '~-- ---- ---- ----------------+J>---

I
N

.:::.•~:-----------------h~-- __________ _

Q

BtW, JUW, NII _________________+_'

c:I

Figure 15. Bus Requeatl Acknowledge Timing

Stop

The STOP mput IS sampled by the last falling
clock edge immediately preceedmg any IF)
cycle (Figure 16) and before the second word
of an EPA instruction is fetched. If STOP is
found Low between the IF) cycle, a stream of
memory refresh cycles is inserted after T3,
agam samplIng the STOP input on each falling
clock edge in the middle of the T3 states. During the EPA instruction, both EPA mstruction
words are fetched but any data transfer or

I'

subsequent instruction fetch is postponed until
STOP is sampled High. This refresh operation
does not use the refresh prescaler or Its dlvideby-four clock prescaler; rather, it doublemcrements the refresh counter every three
clock cycles. When STOP is found High agam,
the next refresh cycle IS completed, any
remaming T states of the IF) cycle are then
executed and the CPU continues its operatIon.

-------,,,.------------1
~

~

~

k------REFRESH------l

I

~R

~

~

I

I.------REFRESH--------l

I

~

~

~

I

~

~

CLOCK

SToP

\"-I<--_ _ _\ . . . I. ___---'XX J \\-_________
--C:::::>--

os

v

v

"---v
"------I

\'-----'/

STo-eTa

J'--_____, _.____--IX,,_____________
/

__________x==
x==

Figure 16. Stop Timing
2045-0291. 0292

145

Internal
Operation

clock cycles long (Figure 17). This allows fast
response to Bus Request and Refresh Request,
because bus request or refresh cycles can be
inserted at the end of any internal machine
cycle.

Certain extended instructions, such as
Multiply and Divide, and some special instructions need additional time for the execution of
internal operations. In these cases, the CPU
goes through a sequence of internal operation
machine cycles, each of which is three to eight

CLOCK

STo-ST3

MREQ,

Di,

r--L- ~r--L- r----

-

-

P<
rL-!

ex

INTERNAL OPERATION

>--

UNDEFINED

HIGH

RlW

alii

UNDEFINED

MIS

SAMEASPREVIOUSCVCLE

I
Figure 17. Internal Operation Timing

Memory
Refresh

When the 6-bit prescaler in the refresh
counter has been decremented to zero, a
refresh cycle consisting of three T-states is
started as soon as possible (that is, after the
next IFj cycle or Internal Operation cycle).
The 9-bit refresh counter value is put on the
low-order side of the address bus (ADo-ADa);
ADg-ADj5 are undefined (Figure 18). Since
the memory is word-organized, Ao is always
Low during refresh and the refresh counter is

always incremented by two, thus stepping
through 256 consecutive refresh addresses on
ADj-ADa. Unless disabled, the presettable
prescaler runs continuously and the delay in
starting a refresh cycle is therefore not
cumulative.
While the STOP input is Low, a continuous
stream of memory refresh cycles, each three
T-states long, is executed without using the
refresh prescaler.

CLOCK

iiii'f

--r---~--~---r---

STo-STa

AD

RiW ••,W,

REFRESH ADDRESS

)--------

Niil_-t____-t__

--------

-C

-----t---

SA_M_,,_,_,,_EV_'Ou_'t-Cy_CL_,

Figure 18. Memory Refresh Timing

146

2045-0293. 0294

Halt

A HALT instruction executes an unlimIted
number of 3-cycle Internal operations,
inter-spersed wIth memory refresh cycles
whenever requested. An Interrupt, segmentation trap or reset are the only eXIts from a
HALT instruction.

The CPU samples the VI, NVI, NMI and
SEGT inputs at the beginning of every T3
cycle. If an Input IS found active during two
consecutive samples, the subsequent IF) cycle
IS exercIsed, but ignored, and the normal
Interrupt acknowledge cycle IS started.

Reset

A Low on the RESET input causes the following results within five clock cycles (FIgure 19):

are executed in the system mode. In the 28001,
the first cycle reads the flag and control word
from location 0002, the next reads the 7-blt
program counter segment number from location 0004, the next reads the 16-bit PC offset
from location 0006, and the following IF) cycle
starts the program. In the 28002, the first cycle
reads the flag and control word from location
0002, the next reads the PC from location
0004, and the following IF) cycle starts the
program.

• ADo-AD)5 are 3-stated

• AS, 00, MREQ, STO-ST3'
BUSACK and MO are forced High
• SNo-SN6 are forced Low
• Refresh is dIsabled

• R/W,

B/W and Nis are not affected
When RESET has been High for three clock
periods, two consecutive memory read cycles

\'---------------'>-----

" ______________1
fiEa _ _ _ _ _ _ _ _ _ _ _ _ _ _~1

----------------~I
1

STO-ST3 _ _ _ _ _ _ _ _ _ _ _ _ _ _

RIW

BIlY

--____~I
--------------~I
Figure 19. Reset Timing

2045·0295

147

Composite
AC Timing
Diagram

~

x

~ :slfl

~
.-/i

I

ii, NYI

.-/i

HD-r-®-

~-w-

I

MO

~

This composite timing diagram does not show actual
tlmmg sequences Refer to
this diagram only for the
detailed timing relationships
of IndiVidual edges Use the
preceding Illustrations as an
explanation of the variOus
timing sequences

~
'---

K

~'---

~

c::

STOP

IY

r®- r®-

Timing measurements are
made at the following
voltages
High
Low

Fe

K=
~~~

IY-

WAIT

XC
--@--:J. ~(s4)j

Clock
Output
Input
Float

40V
20V
20V
6V

o 8V
o 8V
o 8V
±05V

~-

r)
67

'l'

--)

"DATA IN

® I-r--

L L----®-f-®-

I-f--t@

:x

~"
22

~

~

~

J

MEMORY WRITE

J

INPUT/OUTPUT

.../

j

jIo---

~

I'--

16

t®

~(

r--
I®- ~ ~1 r>-:D

I - t-~

f--®-v ~ f--- r-®
r® ---J'I-MEMORY READ

~

11

I-----®--

DATA OUT

}1-iJr

1-

SNo-SN.

ADDRESS

-

~

,.. .. _(

-@------

r-®

f-€> t-f-®-

.. _-

~

38

~

.. _-

~

~~
~--.C
~
I-- ~~ ~ H9~
.v~~,~."'-44

INTERRUP~J

ACKNOWLEDGE

REA:~R~:.:

NORMAUSYSTEM,
BYTE/WORO

148

~

:x

rl!D-

-®--l

-

~--

I

2045-0296

Z800IlZ8002
Number

Symbol

Parameter

Min

Max

Z8001A/Z8002A Z800lB/Z8002Bt
Min

Max

Min

Max

I
TcC
Clock Cycle Time
250
2000
165
2000
100
2000
2
TwCh
Clock Width (High)
105
2000
70
2000
40
3
TwCI
Clock Width (Low)
105
2000
70
2000
40
4
TIC
Clock Fall Time
20
10
10
5--TrC----Clock Rise T l m e - - - - - - - - - - - - - - - - 2 0 - - - - - 1 5 - - - - - 1 0 6
TdC(SNv)
Clock t to Segment Number Valid
130
110
70
(50 pF load)
TdC(SNn)
Clock t to Segment Number Not Valid
5
7
10
20
8
TdC(Bz)
Clock t to Bus Float
65
55
40
9
TdC(A)
Clock t to Address Valid
100
75
50
10-- TdC(Az)--- Clock t to Address F l o a t - - - - - - - - - - - - - 6 5 , - - - - - 5 5 - - - - - 4 0 II
TdA(DR)
Address Valid to Read Data ReqUired Valid
475'
305'
180'
12
TsDR(C)
Read Data to Clock j Setup Time
30
20
10
13
TdDS(A)
i5S t to Address Aclive
80'
45'
20'
14
TdC(DW)
Clock t to Write Data Valid
50
100
75
15-- ThDR(DS)-- Read Data to DS t Hold T l m e - - - - - - - - - O - - - - - O - - - - - - O - - - 16
TdDW(DS)
Write Data Valid to DS t Delay
295'
195'
110'
17
TdA(MR)
Address Valid to MREQ j Delay
55
35'
20'
18
TdC(MR)
Clock j to MREQ j Delay
80
70
40
19
TwMRh
MREQ Width (High)
210'
135'
80'
20 - - TdMR(A)--- MREQ j to Address Not A c l i v e - - - - - - - 7 0 ' - - - - - 3 5 ' - - - - - 2 0 ' - - - 21
TdDW(DSW)
Write Data Valid to DS j (Write) Delay
55'
35'
15'
22
TdMR(DR)
MREQ j to Read Data ReqUired Valid
375'
230'
140'
23
TdC(MR)
Clock j MREQ t Delay
80
60
45
24
TdC(ASf)
Clock t to AS j Delay
80
60
40
25-- TdA(AS)--- Address Valid to AS t D e l a y - - - - - - - - 5 5 ' - - - - - 3 5 ' - - - - - 2 0 ' - - - 26
TdC(ASr)
Clock j to AS t Delay
90
80
40
27
TdAS(DR)
AS t to Read Data Required Valid
360'
220'
140'
28
TdDS(AS)
i5S t to AS j Delay
70'
35'
15'
29
TwAS
AS Width (Low)
85'
55'
30'
30 - - TdAS(A)--- AS t to Address Not Aclive D e l a y - - - - - - 7 0 ' - - - - - 4 5 ' - - - - - 2 0 ' - - - 31
TdAz(DSR)
Address Float to i5S (Read) j Delay
0
0
0
32
TdAS(DSR)
AS t to i5S (Read) j Delay
80'
55'
30'
33
TdDSR(DR)
DS (Read) j to Read Data Required Valid
205'
130'
70'
34
TdC(DSr)
Clock j to DS t Delay
70
65
45
35--TdDS(DW)-- DS t to Write Data Not V a l i d - - - - - - - - 7 5 ' - - - - - 4 5 ' - - - - - 2 5 ' - - - 36
TdA(DSR)
Address Valid to i5S (Read) j Delay
180'
110'
65'
60
37
TdC(DSR)
Clock t to DS (Read) j Delay
120
85
110'
38
TwDSR
DS (Read) Width (Low)
275'
185'
39
TdC(DSW)
Clock j to DS (Write) j Delay
95
80
60
40--TwDSW--- DS (Write) Width ( L o w ) - - - - - - - - - - 1 8 5 ' - - - - 1 1 0 ' - - - - - 7 5 ' - - - 41
TdDSI(DR)
i5S (1/0) j to Read Data Required Valid
330'
210'
120'
42
TdC(DSf)
Clock j to DS (110) j Delay
90
120
60
43
TwDS
DS (110) Width (Low)
410'
255'
160'
44
TdAS(DSA)
AS t to DS (Acknowledge) j Delay
1065'
690'
410'
45--TdC(DSA)--Clock t to DS (Acknowledge) j D e l a y - - - - - - - - 1 2 0 - - - - - 8 5 - - - - - 6 5 46
TdDSA(DR)
i5S (Acknowledge) j to Read Data
455'
295'
165'
ReqUired Delay
47
TdC(S)
Clock t to Status Valid Delay
110
85
60
48
TdS(AS)
Status Valid to AS t Delay
50'
30'
10'
49
TsR(C)
RESET to Clock t Setup Time
180
70
50
50--ThR(C)
RESET to Clock t Hold T l m e - - - - - - - - O - - - - - O - - - - - O - - - 51
TwNMI
NMI Width (Low)
100
70
50
52
TsNMI(C)
NMI to Clock t Setup Time
140
70
50
53
TsVI(C)
VI, NVI to Clock t Setup Time
110
50
40
54
ThVI(C)
VI, NVI to Clock t Hold Time
20
20
10
55--TsSGT(C)--SEGT to Clock t Setup Time
70
55
40---56
ThSGT(C)
SEGT to Clock t Hold Time
0
0
0
57
TsMI(C)
MI to Clock t Setup Time
180
140
80
58
ThMI(C)
MI to Clock t Hold Time
0
0
0
59
TdC(MO)
Clock t to MO Delay
120
85
70
60--TsSTP(C)---STOP to Clock j Setup Time
140
100-----50---61
ThSTP(C)
STOP to Clock j Hold Time
0
0
0
62
TsW(C)
WAIT to Clock j Setup Time
50
30
20
63
ThW(C)
WAIT to Clock j Hold Time
10
10
5
64
TsBRQ(C)
BUSREQ to Clock t Setup Time
90
80
60
65-- ThBRQ(C)-- BUSREQ to Clock t Hold Time
10
10
5---66
TdC(BAKr)
Clock t to BUSACK t Delay
100
75
60
67
TdC(BAKf)
Clock t to BUSACK j Delay
100
75
60
68
TwA
Address Valid Width
150'
95'
50'
69
TdDS(S)
DS t to STATUS Not Valid
80'
55'
30'
·Clock-cycle-hme-dependent characterIstIcs See table on followmg page.

t Umts

In

nanoseconds (ns) All hmmgs are prehmmary.

149

Number

Symbol

Z800l/Z8002
Equation

Z800lAlZ8002A
Equation

Z800lB/Z8002B
Equation

2TeC + TwCh - 95 ns
TdA(DR)
2TeC + TwCh - 60 ns
II
2TeC + TwCh - 130 ns
TdDS(A)
TwCl - 20 ns
TWCl - 25 ns
TwCI- 25 ns
13
TdDW(DS)
16
TeC + TwCh - 40
TeC + TwCh - 30 ns
TeC + TwCh - 60 ns
17
TdA(MR)
TwCh - 50 ns
TwCh - 35 ns
TwCh - 20 ns
19--TwMRh--- TeC - 40 n s - - - - - - TeC - 30 n s - - - - - - - - T e C - 20 n s - - - - - 20
TdMR(A)
TdDW(DSW)
21
TdMR(DR)
22
25
TdA(AS)
27--TdAS(DR)--

TwCl - 35 ns
TwCh - 50 ns
2TeC - 130 ns
TwCh - 50 ns
2TeC - 140 ns

TwCl - 35 ns
TwCl - 20 ns
TwCh - 25 ns
TwCh - 35 ns
2TeC - 100 ns
2TeC - 60 ns
TwCh - 35 ns
TwCh - 20 ns
2TeC - 110 ns-------2TeC - 60 n s - - - - - -

28
TdDS(AS)
TwCl - 35 ns
TwCl - 35 ns
TwCl - 25 ns
29
TwAS
TwCh - 20 ns
TwCh - 15 ns
TwCh - 10 ns
30
TdAS(A)
TwCl - 35 ns
TwCl - 25 ns
TwCl - 20 ns
TdAS(DSR)
TwCl - 25 ns
TwCl - 15 ns
TwCl - 10 ns
32
33-- TdDSR(DR)-- TeC + TwCh - 150 n s - - - TeC + TwCh - 105 ns
TeC + TwCh - 70 n s - - 35
TdDS(DW)
TwCl - 30 ns
TwCl - 25 ns
TwCl - 15 ns
36
TdA(DSR)
TeC - 70 ns
TeC - 55 ns
TeC - 35 ns
TwDSR
TeC + TwCh - 30 ns
TeC + TwCh - 50 ns
38
TeC + TwCh - 80 ns
40
TwDSW
TeC - 65 ns
TeC - 55 ns
TeC - 25 ns
41--TdDSI(DR)-- 2TeC - 170 n s - - - - - - 2TeC - 120 n s - - - - - - - 2TeC - 80 n s - - - - - 43
TwDS
TdAS(DSA)
44
TdDSA(DR)
46
TdS(AS)
48
68--TwA
TdDS(s)
69

150

2TeC - 90 ns
2TeC - 75 ns
4TeC + TwCl - 40 ns
4TeC + TwCI - 40 ns
2TeC + TwCh - 150 ns
2TeC + TwCh - 105 ns
TwCh - 55 ns
TwCh - 40 ns
TeC - 90 ns - - - - - - TeC - 70 ns
TwCI- 25 ns
TwCl - 15 ns

2Te8 - 40 ns
4TeC + TwCl - 30 ns
2TeC + TwCh - 75 ns
TwCh - 30 ns
TeC - 50 n s - - - - - TwCl - 10 ns

Absolute
Maximum
Ratings

Test
Conditions

Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operatmg Ambient
Temperature ........ See Ordering Information
Storage Temperature ........ -65 D C to + 150 D C

devIce rehablhty,

All ac parameters assume a total load
capacitance (including parasitic capacitances)
of lOa pF max, except for parameter 6 (50 pF
max). Timing references between two output
signals assume a load difference of 50 pF max.

*See Ordermg Information sectIon for package
temperature range and product number.

8085-0006

condItIon above those mdicated In the operatIonal sechons
of these speclhcahons IS not ImplIed. Exposure to absolute
maXImum ratmg condItIons for extended penods may affect

The characteristics below apply for the
following test condItions, unless otherwise
noted. All voltages are referenced to GND
(0 V). Positive current flows into the referenced pin. Available operating temperature
ranges are:
• S· = ODe to + 70 DC,

+4.75V:5Vee:5 +5.25V
• E* = -40 D C to +85 D C,
+4.75 V:5 Vee :5 +5.25 V
• M* = -55 D C to + 125 D C,
+4.5 V:5 Vee :5 +5.5 V

DC
Characteristics

Stresses greater than those hsted under Absolute MaxImum Ratmgs may cause permanent damage to the devIce.
ThIS IS a stress ratmg only, operatIon of the devICe at any

Min

Max

Unit

VCH

Symbol

Clock Input HIgh Voltage

VCC-O.4

VCC+0.3

V

Driven by External Clock

VCL

Clock Input Low Voltage

-0.3

0.45

V

Dnven by External Clock

VIH

Input HIgh Voltage

2.0

Vec+0.3

V

VIH RESET

Input HIgh Voltage on RESET
pm

2.4

Vee to.3

V

VIL

Input Low Voltage

-0.3

0.8

VOH

Output HIgh Voltage

VOL

Output Low Voltage

0.4

IlL

Input Leakage

±10

pA

IlL SEGT

Input Leakage on SEGT pm

100

pA

IOL

Output Leakage

±10

pA

ICC

Vee Supply Current

300

rnA

Parameter

Condition
Generator

Generator

2.4

-100

V
V
V

IOH = -250 p.A
IOL = +2.0 rnA
0.4 :S VIN :S + 2.4 V

0.4 :S VIN :S + 2.4 V

151

Ordering
Information

Product
Number

Z8001

Package/
Speed
Temp

CE

4.0 MHz

Z8001
Z8001
Z8001
Z8001
Z8001
Z8001
Z8001
2800lA
2800lA
Z800lA
Z800lA
Z800lA
2800lA
28002

CM
CMB
CS
DE
DS
PE
PS
CE
CS
DE
DS
PE
PS
CE

4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
4.0 MHz

28002
28002
Z8002
28002

CM
CMB
CS
DE

4.0
4.0
4.0
4.0

MHz
MHz
MHz
MHz

Description

CPU (segmented,
48-pm)
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
CPU (nonsegmented, 40-pm)
Same as above
Same as above
Same as above
Same as above

Product
Number

Z8002
Z8002
28002
28002A
Z8002A
28002A
Z8002A
28002A
28002A
Z8002A
28002A
28002B
28002B
28002B
28002B
28002B
28002B
Z8002B
Z8002B

Package/
Temp
Speed

DS

4.0 MHz

PE
PS
CE
CM
CMB
CS
DE
DS
PE
PS
CE
CM
CMB
CS
DE
DS
PE
PS

4.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
6.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz
10.0 MHz

Description

CPU (nonsegmented, 40-pm)
Same as above
Same as above
Same as above
Same a~ above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above
Same as above

'NOTES C = Ceramic, D :::: Cerdlp, P = Plashc, E = -40°C to +85°C, M = -55°C to + 125°C, ME :::: -55°C to + 125°C WIth
MIL-STD-883 with Class B processmg, S :::: oDe to + 70 0e

152

00-2045·02

Z8003/4 Z8000™ VMPU
Virtual Memory
Processing Unit

~

Product

Brief

Zilog

June 1982

Features

• Binary, function, and pin compatibility with
the Z8001l2 mlCroprocessors.
• Designed-in compatibility with present and
future Zilog Memory Management Units
(MMUs).

• Status lines indicate the read/write phase of
the Test and Set instruction for use in
multiprocessor systems.
• 23-bit segmented addresses for Z8003.
• 16-bit non-segmented addresses for Z8004.

• Operates with up to a 10 MHz clock.

Description

The Z8003/4 Virtual Memory Processor Unit
(VMPU), a 16-bit MOS microprocessor, offers
integral provisions for operation in a virtual
memory environment, in addition to the
features of the Z8001 CPU. The Z8003 VMPU
generates 23-bit addresses. The address space
is organized into 128 segments, each up to 64K
bytes in length. The Z8004 generates 16-bit addresses. The Z8003/4 VMPU addressing
scheme distinguishes between memory space
for program, data, and stack in each of two
modes, System and Normal.
For use in shared-memory multiprocessor
systems, the Z8003/4 VMPU provides an output

BUS{

TIMING

A011

on the status lines (STo-ST3), indicating the
read/write phase of the Test and Set (TSET)
instruction. This status output can be used
externally for arbitration of bus control.
In a virtual memory environment, the programs and data being operated on need not
reside simultaneously in main memory. Thus,
provision must be made for retrieving parts of
a program or data located in "secondary"
storage (such as a disk). Attempts by the
microprocessor to access instructions or data
not in main memory are called "accesses to
nonresident data." When this is done, the
transaction acceSSing the nonresident data
must be interrupted, the state of the
microprocessor saved, the program or data in
secondary storage moved to main memory, the
state of the microprocessor restored, and the
interrupted instruction restarted.
The Z8003/4 VMPU provides an external
abort pin to permit the interruption of instruc-

ADDRESS I
DATA BUS

""-1
CPU{

CONTROL

Z8003

Z8004
VMPU

BUS{

T=~

CONTROL

SEGMENT:
NUMBER 1

I
I
I

SN,
MULT1OMICRO{
CONTROL

~~~::~; ::;~s I

ABORT

_L~IO~1!!.A!:..

+5V OND

elK

RESET

Figure I. Pin Assignments
2096-001. 002

--.J

Figure 2. Virtual Memory Environment

153

Description
(Contmued)

tion execution before the instruction completes.
When the 2800314 VMPU is used in a
multiprocessor system, there may be dualported memorIes used by the processors. In
this type of system, a resources manager arbitrates simultaneously attempted accesses to
shared resources. When a processor tests to

see if a resource is m use, the read/write portion of the test transaction must not be interrupted or the probability of a colhslOn
increases greatly. The 28003/4 VMPU provides
features that help to avoid collisions during
accesses to shared resources via the enhanced
TSET instruction.

Functional
Description

The 28003/4 VMPU can operate in a vIrtual
memory environment. The virtual memory
capability is provided by an instruction abort
function on pin 33 of the 28003 and on pin 28
of the 28004. When this pin WAIT, and SAT
are activated at the same time, an instruchon
abort sequence begins. This abort sequence
leaves the VMPU in a well-defined state, allowing a software recovery. To make this recovery
smoothly, the software must know which
instruction was aborted and how much of the
mstruction was executed. Figure 3 shows the
timmg sequence for the abort funchon. Figure

4 shows the sequence of hardware and software events that occurs when an instruction is
aborted.
During the read phase of the TSET
instruction on the 28003/4 VMPU, the status
Imes STo-ST3 are all set to Is. On the 2800112
all I s on the status lines is a reserved status
encodmg.
The 28003/4 VMPU is compatible with the
28000 Family of microprocessor and peripheral
devices. Instruction set and bus transaction
protocols of the VMPU can be found in the
Z8000 CPU Techmcal Manual (document
number 00-2010-C). The VMPU enhancements are described in the VMPU Product
Specification.

4 MHz 6 MHz 10 MHz
Ts 50 ns
30 ns 25 ns
Th Ons
Ons
Ons

elK

- - - - I "I ,

T.....--i---'

••••

~

AS

YES

OS

ABORT

Ih-i ~

NO

ABORT THE

Th~I r~---------------+--~

INSTRUCTION

I

TRAP
• SAVE STATUS
• SWAP IN PROGRAM!

DATA ELEMENT
• RESTORE STATUS

VIRTUAL ADDRESS
ABORT

NOTES:

Summary

154

'*

=

ABORT
(II,)

ACKNOWLEDGE
CYCLE

Clock Sample Pomts

NOTE. The abort sequence 15 1mbated when ABORT, SAT, and
WAIT are achvated.

Figure 3. Instruction Abort Timing

Figure 4. Instruction Abort Function Flow

The Zilog VMPU is the first 16-bit
microprocessor that offers integral provision
for operation in a virtual memory environment.
The upward compatibility of the VMPU with

the 2800112 CPU means that applications software developed for a 28001/2 CPU will
execute directly on the VMPU, preserving
investments in software and development tools.

2096·003, 004

Z8010
Z8000™ Z·MMU Memory
Managemenl Unil

~
Zilog

Produci
Specification

June 1982

Features

• Dynamic segment relocation makes software
addresses independent of physical memory
addresses.
• Sophisticated memory-management features
include access validation that protects
memory areas from unauthorized or
unintentional access, and a write-warning
indicator that predicts stack overflow.
• For use with both Z8001 and Z8003 CPU.

General
Description

The Z8010 Memory Management Unit (MMU)
manages the large 8M byte addressing spaces
of the Z8001 CPU. The MMU provides dynamic
segment relocation as well as numerous
memory protection features.
DynamiC segment relocation makes user software addresses independent of the physical
memory addresses, thereby freeing the user
from specifymg where mformation is actually

• 64 variable-sized segments from 256 to
65,536 bytes can be mapped into a total
physical address space of 16M bytes; all 64
segments are randomly accessible.
• Multiple MMUs can support several translation tables for each Z8001l3 address space.
• MMU architecture supports multi-programming systems and virtual memory Implementations.
located in the physical memory. It also proVides a flexible, efficient method for supporting multi-programming systems. The MMU
uses a translation table to transform the 23-bit
logical address output from the Z8001 CPU
into a 24-bit address for the physical memory.
(Only logical memory addresses go to an MMU
for translation; I/O addresses and data, in
general, must by pass this component.)

A"
A"

cs

A"

DMASYNC

A"
A"
A"
A17
A"
A15

PHYSICAL
ADDRESS

A"
A13
A12
A"
AlO
A,

As
SEGMENT
TRAP

RrN_)

DMAISEQMENT

812"'ST,

CHIP SELECT

-4--

STo ...--

+5 V

ST,

A"

ST,

A"
A"

ST,

A20

AD,

A"
Vee

AD,

A"
A17

AD'1
elK

A"
A15

AD'2

A"
A13

AD'4

STATUS

A,

ST,

AD'0

OND
ACt3

AD1s
SNo
SN,
SN,

A,

SN,

RESERVED

SN,

SN,

SN,

GND eLK RESET

Figure 1. Pin Functions
2046·051. 033

sUP

A12

5 T3 ......-.

BUS TIMING {

RJW

RESET

A"
AlO

NIS~

NIS

AS
DS

SEGT

Figure 2. Pin Assignments

155

I•
•
C

General
Description
(Contmued)

Memory segments are variable m SIze from
256 bytes to 64K bytes, m increments of 256
bytes. PaIrs of MMUs support the 128 segment
numbers aVailable for the various Z8001 CPU
address spaces. Wlthm an address space, any
number of MMUs can be used to accommodate
mulhple translahon tables for System and Normal operatmg modes, or to support more
sophlshcated memory-management systems.
MMU memory-protechon features safeguard
memory areas from unauthorized or unintended access by assocIating special access
restrictions with each segment. A segment IS
assIgned a number of attributes when ItS
descriptor IS entered into the MMU. When a
memory reference IS made, these attributes are
checked agamst the status mformahon supplied by the Z8001/3 CPU. If a mIsmatch ocSEGMENT NUMBER

curs, a trap IS generated and the CPU IS interrupted. The CPU can then check the status
regIsters of the MMU to determine the cause.
Segments are protected by modes of permItted use, such as read only, system only,
execute only and CPU-access only. Other segment management features mclude a wrltewarnmg zone useful for stack operahons and
status flags that record read or write accesses
to each segment.
The MMU IS controlled VIa 22 Special 1/0
mstruchons from the Z8000 CPU in System
mode. With these mstructions, system software
can aSSIgn program segments to arbitrary
memory locatIOns, restrict the use of segments
and momtor whether segments have been read
or written.

OFFSET/DATA
~

SNO-SNs

SNo-SNa

___-#:;1-----' hll SNo-SNs

..

....Ell,

tlESCNPTOR
R£ClI$TE~

STO-ST3

SEGi

Sli'P

RIW,N/S

STATUS
SEGMENT SUPPRESS PHYSICAL
INFORMATION
TRAP
ADDRESS
REQUEST

STo-STa

fIiW,NtS

SEG'f

Sli'P

STATUS
SEGMENT SUPPAESS PHYSICAL
INPORMATION
TAAP
ADDRESS
REQUEST

Figure 3. The shaded areas in these block diagrams illustrate the resources used in the two modes of MMU operation. In
the Address Translation Mode shown on the lell. addresses are translated automatically. In the Command Mode shown
on the right. specific registers are accessed using Special 1/0 commands.

156

2046·028

Segmented
Addressing

Memory
Protection

2046-029

A segmented addressmg space~compared
with linear addressmg~ls closer to the way a
programmer uses memory because each procedure and data set can reside m its own
segment.
The 8M byte 28001 addressmg spaces are
divided mto 128 relocatable segments of up to
64K bytes each. A 23-blt segmented address
uses a 7-blt segment address to pomt to the
segment, and a l6-blt offset to address any
byte relative to the beginning of the segment.
The two parts of the segmented address may
be manipulated separately.
The MMU divides the physical memory mto
256-byte blocks. Segments consist of phYSICally
conliguous blocks. Certam segments may be
deSignated so that writes mto the last block
generate a warnmg trap. If such a segment IS
used as a stack, thiS warnmg can be used to
mcrease the segment size and prevent a stack
overflow error.
The addresses manipulated by the programmer, used by mstructions and output by the
28001 are called logIcal addresses. The MMU
takes the logical addresses and transforms
them mto the physical addresses required for
accessing the memory (Figure 4). This address
transformalion process is called relocation.
The relocalion process IS transparent to user
software. A translalion table m the MMU
associates the 7-bit segment number with the
base address of the phYSical memory segment.
The 16-bit logICal address offset is added to the
phYSICal base address to obtain the actual
phYSICal memory location. Because a base
address always has a low byte equal to zero,

only the high-order 16 bits are stored m the
MMU and used in the addllion. Thus the loworder byte of the physical memory location is
the same as the low-order byte of the logICal
address offset. This low-order byte therefore
bypasses the MMU, thus reducmg the number
of pins reqUired.

Each memory segment IS assigned several
attributes that are used to provide memory
access proteclion. A memory request from the
2800113 CPU IS accompanied by status mformali on that mdlcates the attributes of the
memory request. The MMU compares the
memory request attributes with the segment
attributes and generates a Trap Request
whenever It detects an attribute vlOlalion. Trap
Request mforms the 28001/3 CPU and the
system control program of the vIOla lion so that
appropriate aclion can be taken to recover.
The MMU also generates the Suppress signal
SUP in the event of an access vlOlalion. Suppress can be used by a memory system to mhlbit stores mto the memory and thus protect the
contents of the memory from erroneous
changes.
Five attributes can be associated with each
segment. When an attempted access VIOlates
anyone of the attributes associated with a segment, a Trap Request and a Suppress signal
are generated by the MMU. These attributes
are read only, execute only, system access
only, mhlblt CPU accesses and mhlblt DMA
accesses.

Segments are speCified by a base address
and a range of legal offsets to this base
address. On each access to a segment, the offset is checked agamst thiS range to msure that
the access falls within the allowed range. If an
access that hes outside the segment IS attempted, Trap Request and Suppress are generated.
Normally the legal range of offsets withm a
segment is from 0 to 256N + 255 bytes, where
OsNs255. However, a segment may be
specified so that legal offsets range from 256N
to 65,535 bytes, where OsNs255. The later
type of segment is useful for stacks since the
28000 stack manipulation instructions cause
stacks to grow toward lower memory locations.
Thus when a stack grows to the limit of ItS
allocated segment, additional memory can be
allocated on the correct end of the segment.
As an aid in maintaining stacks, the MMU
detects when a write is performed to the lowest
allocated 256 bytes of these segments and
generates a Trap Request. No Suppress signal
is generated so the write is allowed to proceed.
ThiS write warning can then be used to indicate that more memory should be allocated to
the seqment.

23·BIT LOOICAL ADDRESS

o

BIT SN, MUST BE

EQUAL TO FLAG URS

r-----I~SE~G~N~OJ

15

81

OFFSET

-,

,---------rSEGNOI

1

I ~R~

I

1

.. 1

1

1""'"------"""'..,

0

~Rf

.. I
TABLE OF 64
SEGMENT DESCRIPTOR
REGISTERS

• 1
• I

"+1

1

1
1

1

n+641

1

•

n

1

1
1

•

!

1

•

I

1

1

1

1

1

1
1

24·BIT PHYSICAL ADDRESS

Figure 4. Logical-to-Physical Address Translation

157

MMU
The MMU contains three types of registers:
Register
Segment Descnptor, Control and Status. A
Organization set of 64 Segment Descnptor Registers supphes
the Informahon needed to map logical memory
addresses to physical memory locations. The
segment number of a logical address determines which Segment Descriptor RegIster is
used in address translation. Each Descriptor
RegIster also contains the necessary information for checking that the segment locahon
referenced IS within the bounds of the segment
and that the type of reference is permitted. It
also indicates whether the segment has been
read or written.
In addition to the Segment Descriptor
Registers, the 28010 MMU contains' three 8-bit
control regIsters for programming the device
and six 8-bit status registers that record information in the event of an access vIOlation.
Segment Descriptor Registers. Each of the 64
Descriptor Registers contains a l6-bit base
address field, an 8-bit limIt field and an 8-bit
attnbute field (Figure 5). The base address
field IS subdivided into high- and low-order
bytes that are loaded one byte at a time when
the descriptor is Initialized. The limit field contains a value N that indicates N + I blocks of
256 bytes have been allocated to the segment. *
The attribute field contains eIght flags
(Figure 6). Five are related to protecting the
segment against certain types of access, one
indicates the special structure of the segment,
and two encode the types of accesses that have
been made to the segment. A flag is set when
its value is 1. The following brief descriptions
indicate how these flags are used.
Read-Only (RD). When th,s flag IS set, the segment IS read
only and 18 protected agamst any wrIte access.
System-Only (SYS). When th,s flag IS set, the segment can
be accessed only In System mode, and 15 protected agamst
any access In Normal mode.
CPU-InhibIt (CPUI). When th,s flag IS set, the segment IS
not accessIble to the currently executmg process, and IS
protected agamst any memory access by the CPU. The
segment IS, however, accessable under DMA.
Execute-Only (EXC). When th,s flag IS set, the segment
can be accessed only durmg an Instruction fetch or access
by the relatlve addressmg mode cycle, and thus IS protected agamst any access durmg other cycles.
DMA-Inhunt (DMAI). When th,s flag IS set, the segment
can be accessed only by the CPU, and thus IS protected
agamst any access under DMA.
D,rection and Warning (DIRW). When th,s flag IS set, the
segment memory locatIons are consIdered to be orgamzed
in descendmg order and each wrIte to the segment 15
checked for access to the last 256-byte block. Such an
access generates a trap to warn of potential segment
overflow, but no Suppress sIgnal IS generated.
Changed (CHG). When th,s flag IS set, the segment has
been changed (written). Th,s b,t IS set automahcally durmg
any WrIte access to thIS segment If the wnte access does not
cause any vIolation.
Referenced (REF). When th,s flag IS set, the segment has
been referenced (eIther read or written). Th,s b,t IS set
automatically durmg any access to the segment If the
access does not cause a vlOlatron.

BASE ADDRESS
FIELD

LIMIT ATTRIBUTE
FIELD
FIELD

~

15

87

• ::~~ l::t~

07

SoR
SoR 1

07
LO
L1
L2

A.
AI

BAL2

SDR63 BAH63 [ BAL63

L63

A63

SDR2

BAH2

•

A2

I
I
I
I
I
I
I

Figure 5. Segment Descriptor Registers

7

•

I

REF I CHG IDIRWIDMAII EXC ICPUII SYS I RD

I

Figure 6. Attribute Field in Segment Descriptor Register

Control Registers. The three user-accessIble
8-bit control registers in the MMU direct the
functioning of the MMU (Figure 7). The Mode
Register provides a sophisticated method for
selectively enabling MMUs in mulhple-MMU
configurations. The Segment Address Register
(SAR) selects a particular Segment Descriptor
Register to be accessed during a control
operation. The Descriptor Selection Counter
Register pOints to a byte WIthin the Segment
Descriptor Register to be accessed durmg a
control operahon.
7

6

5

4

3,2

'0
7

I

65
0

0

ISEG~ENT pESC~IPTO~ NU~BER I ~~~~~;;

7

I

MODE

0

2 1

I

0

I

DESCRIPTOR

_0-,-,_0-,-,_0-,-,_0-L_O....~C......J ~~~ENC;~~N

L_O-,-_O-,-'

Figure 7. Control Registers

The Mode Register contains a 3-bit Identification field (ID) that distinguishes among
eight enabled MMUs In a multiple-MMU configuration. This field is used during the segment trap acknowledge sequence (refer to the
section on Segment Trap and Acknowledge).
In addition, the Mode Register contains five
flags.
Mulhple Segment Table (MST). Th,s flag mdICates whether
multiple segment tables are present In the hardware conhguratIon. When thIS flag IS set, more than one table IS
present and the Nis line must be used to determme
whether the MMU contams the appropnate table.
Normal Mode Select (NMS). Th,s flag mdICates whether
the MMU IS to translate addresses when the Nis lme IS
HIgh or Low. If the MST flag IS set, the Nis lme must
match the NMS flag for the MMU to translate segment
addresses, otherWIse the MMU Address lmes remam
3-stated.

*In the stack mode, segment SIze IS 64K-256N.

158

2046-030, 031

MMU
Register
Organization
(Contmued)

Upper Range Select (URS). ThIS flag IS used to IndIcate
whether the MMU contams the lower-numbered segment
descriptors or the hIgher-numbered segment descnptors.
The most slgmilcant bIt of the segment number must match
the URS flag for the MMU to translate segment addresses,
otherwIse the MMU Address lInes remam 3-stated
Translate (TRNS). ThIs flag mdlcates whether the MMU IS
to translate logIcal program addresses to physIcal memory
locations or IS to pass the loglCal addresses unchanged to
the memory and wIthout protectIon checkmg In the nontranslatIon mode, the most sIgmficant byte of the output IS
the 7-blt segment number and the most sIgmfIcant bIt IS O.
When thIs flag IS set, the MMU performs address translahan and attrIbute checkmg.
Master Enable (MSEN). ThIs flag enables or dIsables the
MMU from performmg Its address translahon and memory
protectIon functions. When thIS flag IS set, the MMU performs these tasks; when the flag IS clear the Address lmes
of the MMU remaIn 3-stated.

The Segment Address Register (SAR) pomts
to one of the 64 segment deSCriptors. Control
commands to the MMU that access segment
descriptors Implicitly use thIs pomter to select
one of the deSCriptors. ThIS regIster has an
auto-mcrementmg capab!lity so that multiple
deSCriptors can be accessed in a block
read/write fashion.
The Descriptor Selechon Counter RegIster
holds a 2-blt counter that indicates whICh byte
in the deSCriptor is bemg accessed during the
readmg or wrltmg operahon. A value of zero
in thIs counter indIcates the hIgh-order byte of
the base address held is to be accessed, one
mdICates the low-order byte of the base
address, two mdICates the limit held and three
mdICates the attribute field.

Status Registers. Six 8-bit regIsters contain
mformahon useful in recovering from memory
access violahons (Figure 8). The Violation
Type Register describes the conditions that
generated the trap. The Violation Segment
Number and Violation Offset Registers record
the most-sigmficant 15 bits of the logical
address that causes a trap. The Instruction
Segment Number and Offset Registers record
the most-significant 15 bits of the logical
address of the last instruction fetched before
the first accessing vlOlahon. These two
registers can be used in conjunction WIth
external cIrcuitry that records the low-order
offset byte. At the time of the addressmg VIOlation, the Bus Cycle Status Register records the
bus cycle status (status code, read/write mode
and normal/system mode).
The MMU generates a Trap Request for two
general reasons: 81ther it detects an access

2046-032

vlOlahon, such as an attempt to write into a
read-only segment, or It detects a warning
condihon, which IS a write mto the lowest 256
bytes of a segment with the DIRW flag set.
When a vlOlahon or warning condihon is
detected, the MMU generates a Trap Request
and automatically sets the appropriate flags.
The eIght flags m the Violahon Type RegIster
descnbe the cause of a trap.
Read-Only VlOlahon (RDV). Set when the CPU attempts to
access a read-only segment and the R/W Ime IS Low.
System VlOlahon (SYSV). Set..!'hen the CPU accesses a
system-only segment and the N/S lme IS HIgh.
CPU-InhIbIt VlOlahon (CPUIV). Set when the CPU
attempts to access a segment WIth the CPU-InhIbIt flag set.
Execute-Only VlOlahon (EXCV). Set when the CPU
attempts to access an execute-only segment In other than
an mstruchon fetch or load relahve mstruchons cycle.
Segment Length VlOlation (SLV). Set when an offset falls
outslde of the legal range of a segment.
Pnmary Wnte Warnmg (PWW). Set when an access IS
made to the lowest 256 bytes of a segment WIth the D1RW
flag set.
Secondary Wnte Warmng (SWW). Set when the CPU
pushes data mto the last 256 bytes of the system stack and
EXCV, CPUIV, SLY, SYSV, RDV or PWW IS set. Once thIS
flag IS set, subsequent wnte warnmgs for accessmg the
system stack do not generate a Segment Trap request.

Fatal Condlhon (FATL). Set when any other flag In the
V101ahon Type RegIster IS set and eIther a vlOlahon IS
detected or a wnte warnmg condition occurs In Normal
mode. ThIs flag IS not set durmg a stack push In System
mode that results In a warnmg conditIOn. ThIs flag
mdIcates a memory access error has occurred In the trap
processmg routme. Once set, no Trap Request sIgnals are
generated on subsequent vlOlahons. However, Suppress
sIgnals are generated on thIS and subsequent CPU vlolahons unhl the F ATL flag has been reset.

7

0

IFATLISWWlpwwlExcvEpUlvl SLY ISYSVI ROV
7

10

I

7

I
I

0

0

I ~~c::,~ATION

SEGMENT NUMBER
I
I
I

VIOLATION
SEGMENT
NUMBER

UPPER OFFSET

VIOLATION
OFFSET

I ""I,ml

CPU STATUS

BUS
CYCLE
STATUS

7

0

[

SEGMENT NUMBER

UPPER OFFSET
I

I

I

INSTRUCTION
SEGMENT
NUMBER

INSTRUCTION
OFFSET

Figure 8. Status Registers

159

N

I;;

i

Segment
The Z8010 MMU generates a Segment Trap
Trap and
when It detects an access vlOlahon or a
Acknowledge wnte warnmg condlhon. In the case of an
access vlOlahon, the MMU also achvates Suppress, whIch can be used to mhlblt memory
wntes and to flag special data to be returned
on a read access. Segment Trap remams Low
unhl a Trap Acknowledge signal IS receIved. If
a CPU-generated vlOlahon occurs, Suppress IS
asserted for that cycle and all subsequent CPU
mstruchon executIOn cycles unhl the end of
the mstruchon. Intervenmg DMA cycles are
not suppressed, however, unless they generate
a vlOlahon. VlOlahons detected durmg DMA
cycles cause Suppress to be asserted durmg
that cycle only-no Segment Trap Requests are
ever generated durmg DMA cycles.
Segment traps to the Z800113 CPU are handled SImilarly to other types of mterrupts. To
servIce a segment trap, the CPU Issues a segment trap acknowledge cycle. The acknowledge cycle IS always preceded by an mstruchon fetch cycle that IS Ignored (the MMU has
been desIgned so that this dummy cycle is
Ignored). Durmg the acknowledge cycle all
enabled MMUs use the AddresslData lmes to
mdlcate theIr status. An MMU that has
generated a Segment Trap Request outputs a 1
on the AID lme associated WIth the number m
ItS ID field; an MMU that has not generated a
segment trap request outputs a 0 on ItS
assocIated AID lme. AID lmes for whIch no
MMU IS assoCIated remam 3-stated. Durmg a

segment trap acknowledge cycle, an MMU
uses AID lme 8 + i If Its ID held IS I.
Followmg the acknowledge cycle the CPU
automahcally pushes the Program Status onto
the system stack and loads another Program
Status from the Program Status Area. The Segment Trap lme IS reset durmg the segment trap
acknowledge cycle. Suppress IS not generated
durmg the stack push. If the store creates a
wnte warnmg condlhon, a Segment Trap
Request IS generated and IS servICed at the
end of the Program Status swap. The SWW
flag IS also set. ServICmg thIS second Segment
Trap Request also creates a wnte warnmg condlhon, but because the SWW flag IS set, no
Segment Trap Request IS generated. If a vlOlahon rather than a wnte warnmg occurs durmg
the Program Status swap, the FATL flag is set
rather than the SWW flag. Subsequent vlOlahons cause Suppress to be asserted but not
Segment Trap Request. WIthout the SWW and
FATL flags, trap processmg rouhnes that
generate memory VIOlations would repeatedly
be mterrupted and called to process the trap
they created.
The CPU routme to process a trap request
should hrst check the FATL flag to determme
If a fatal system error has occurred. If not, the
SWW flag should be checked to determme If
more memory IS reqUIred for the system stack.
Fmally, the trap Itself should be processed and
the VlOlahon Type RegIster reset.

Virtual
Memory

Several features of the MMU can be used in
conjunction with external CIrcuitry to support
virtual memory for the Z800113. Segment Trap
Request can be used to signal the CPU in the
event that a segment IS not m primary memory.
The CPU-Inhibit Flag can be used to indicate
whether a segment is in the memory or m

secondary storage. The Changed and Altered
Flags in the attribute field for each segment
can aid in implementmg effICIent segment
management pohcles. The Status Registers can
be used m recovering from virtual memory
access faults.

Multiple
MMUs

MMU architecture directly supports two
methods for multiple MMU configurations. The
first approach extends single-MMU capabIlity
for handling 64 segments to a dual-MMU configuration that manages the 128 different
segments the Z8001/3 can address. ThIS
scheme uses the URS flag in the Mode Register
in connection with the high-order bIt of the
segment number (SN6).
The second approach uses several MMUs to
Implement multiple translahon tables. Multiple
tables can be used to reduce the hme reqUIred
to switch tasks by aSSIgning separate tables to
each task. Multiple translation tables for mulh-

task environments can use the Master Enable
Flag to enable the appropriate MMUs through
software. Multiple translation tables may also
be used to extend the physical memory sIze
beyond 16 megabytes by separating system
from normal memory andlor program from
data memory. The MST and NMS flags in the
Mode RegIster can be used m conjunction with
the N/S line to select the MMU that contains
the appropnate table. Special external circuitry that monitors the CPU Status lmes can
manipulate the MMU N/S line to perform thIS
selection.

160

DMA
Operation

MMU
Commands

DIrect memory access operations may occur
between Z8DD] mstructlon cycles and can be
handled through the MMU. The MMU permIts
DMA m eIther the System or Normal mode of
operahon. For each memory access, the segment attributes are checked and If a vlOlahon
IS detected, Suppress IS activated. Unlike a
CPU violahon that automahcally causes Suppress signals to be generated on subsequent
memory accesses unhl the next instruchon,
DMA vlOlahons generate a Suppress only on a
per memory access basis.
The DMA deVIce should note the Suppress
sIgnal and record sufhclent mformahon to
enable the system to recover from the access
vIOlation. No Segment Trap Request IS ever
generated durmg DMA, hence warning
condItions are not sIgnaled. Trap Requests are
not ISsued because the CPU cannot
acknowledge such a request.
The various regIsters m the MMU can be
read and written usmg Z8DD] CPU specIal 1/0
commands. These commands have machme
cycles that cause the Status lmes to mdlcate an
SIO operahon IS in progress. During these
machine cycles the MMU enters command
mode. In thIS mode, the rlsmg edge of the
Address Strobe mdlcates a command is present on the ADs-ADI5. If ChIp Select IS
asserted and If thIS command indICates that
data IS to be written mto one of the MMU
regIsters, the data IS read from ADs-ADI5
while Data Strobe IS Low. If the command mdlcates that data IS to be read from one of the
MMU regIsters, the data IS placed on
ADs-ADI5 whIle Data Strobe is Low.
There are ten commands that read or write
various fields in the Segment DeSCriptor
RegIster. The status of the Read/Write line
indicates whether the command IS a read or a
write.
The auto-mcrementing feature of the Segment Address RegIster (SAR) can be used to
block load segment deSCriptors using the
repeat forms of the SpecIal 1/0 instruchons.
The SAR IS automcremented at the end of the
held. In accessmg the base held, first the
hIgh-order byte is selected and then the loworder byte. The command accessmg the entire
Descriptor RegIster references the fields in the
order of base address, hmit and attribute.

At the start of a DMA cycle, DMASYNC
must go Low for at least two clock cycles,
mdlcatmg to the MMU the begmnmg of a
DMA cycle. A Low DMASYNC mhlbits the
MMU from usmg an mdeterminate segment
number on lmes SNo-SN6. When the DMA
logIcal memory address IS vahd, the
DMASYNC lme must be HIgh before a rising
edge of Clock and the MMU then performs ItS
address translation and access protection funchons. Upon the release of the bus at the termmahon of the DMA cycle the DMASYNC lme
must agam be HIgh. After two clock cycles of
DMASYNC HIgh, the MMU assumes that the
CPU has control of the bus and that subsequent memory references are CPU accesses.
The hrst instruction fetch occurs at least two
cycles after the CPU regams control of the
bus. Durmg CPU cycles, DMASYNC should
always be High.
Opcode (Hex)

as
09
OA
OB
OC
OD

OE
OF
15
16

Instruction
Read/WrIte Base FIeld
Read/WrIte LImIt FIeld
Read/WrIte AttrIbute FIeld
Read/WrIte DeSCrIptor (all helds)
ReadIWrIte Base FIeld; Increment SAR
Read/WrIte LImIt FIeld; Increment SAR
Read/WrIte AttrIbute FIeld; Increment
SAR
Read/WrIte DeSCrIptor; Increment SAR
Set All CPU-InhIbIt AttrIbute Flags
Set All DMA-Inhlblt AttrIbute Flags

Three commands are used to read and write
the control registers.
Opcode (Hex)

00
01
20

Instruction

Read/WrIte Mode RegIster
Read/WrIte Segment Address RegIster
Read/WrIte DeSCrIptor Selector Counter
RegIster

The Status Registers are read-only registers,
although the Violahon Type Register (VTR)
can be reset. Nine mstructions access these
regIsters.
Opcode (Hex)

02
03
04
05
06

Read
Read
Read
Read
Read

Instruction
Violahon Type RegIster
VlOlahon Segment Number RegIster
Vlolahon Offset (HIgh-byte) RegIster
Bus Status RegIster
InstructIOn Segment Number

Reglster

07

11
13
14

Read InstruclIon Offset (HIgh-byte)
RegIster
Reset VlOlahon Type Register
Reset SWW Flag In VTR
Reset FATL Flag In VTR

161

I
!

MMU
Timing

The Z8010 translates addresses and checks
for access vIOlations by stepping through
sequences of basic clock cycles corresponding
to the cycle structure of the Z8001 CPU. The
followmg timmg diagrams show the relative
timing relahonships of MMU sIgnals during the
basic operations of memory read/write and
MMU control commands. For exact timing
mformahon, refer to the composIte timing
diagram.

CLOCK

-

Memory Read and Write. Memory read and
instruction fetch cycles are identical, except
for the status informahon on the STo-ST3
inputs. During a memory read cycle (Figure 9)
the 7-bit segment number is input on SNo-SN6
one clock penod earlier than the address offset; a High on DMASYNC during T3 indicates
that the segment offset data is valid. The most
slgmflcant eight bIts of the address offset are
placed on the ADo-ADI5 inputs early m the

,

,

,

I

I

I

Nis,
STo-ST3

SNo-SNe

DON'T CARE

SEGMENT NUMBER

ADDRESS VALID

MEMORY ADDRESS

RIW

>---

~

L

/
Figure 9. Memory Read Timing

162

2046-034

MMU
Timing
(Continued)

hrst clock penod. Valid address offset data IS
mdlcated by the rismg edge of Address
Strobe. Status and mode mformahon become
vahd early m the memory access cycle and
remam stable throughout. The most slgmhcant
16-blts of the address (physIcal memory locahon) remam vahd unhl the end of T3. Segment
Trap Request and Suppress are asserted m T2 .

Segment Trap Request remams Low until Segment Trap Acknowledge IS receIved. Suppress
IS asserted durmg the current machme cycle
and termmates durmg T3. Suppress IS
repeatedly asserted durmg CPU mstruchon
execuhon cycles unhl the current mstruchon
has termmated.

~T1-~+-T2-~+_T3--i

I

CLOCK~

I

I

I

~I-

NIS.
STo-STa

SNO-SN8

DMASYNC

(

SEGMENT NUMBER

DON'T CARE

.I \

~

/

"

PHYSICAL ADDRESS

AS-AU

/

/

ADa-ADu

OFFSET

DATA OUT

/

\
Figure 10. Memory Write Timing

2046-198

163

MMU
Timing
(Contmued)

MMU Command Cycle. During the command
cycle of the MMU (Figure II), commands are
placed ~e Address/Data llnes durmg T1.
The Status lines indlCate that a SpeClal I/O
mstruction IS m progress, and the Chip Select
line enables the appropnate MMU for that
command. Data to be wntten to a register m
the MMU must be valld on the Address/Data
lines late m T2. Data read from the MMU IS

placed on the Address/Data lines late m the
TWA cycle.
Input/Output and Refresh. Input/Output and
Refresh operations are mdlCated by the status
lmes STo-ST3. During these operations, the
MMU reframs from any address translation or
protection checking. The address lines Aa- A23
remam 3-stated.

I_T,_!---T.-!---TWA-t°l-·-T,---1
1 1 1 1 1 1 1 "'---1-

CLOCKJ

Ci

STo-STa

-

-

ex··

11

LOW

N/S

Ai

-

""----I

MiiEQ

ADa-AD15

INPUT

-

=x

READ COMMAND
VALID

-----

DATA INTO CPU

c

iii

Rlii

ADa-AD1S

OUTPUT

HIGH

-~
-

ex

L
WRITE COMMAND
VALID

DATA OUT OF CPU TO MMU

iii

RlW

-

r\

L
Figure 11. 1/0 Command Timing

164

2046-199

MMU
Timing
(Contmued)

Reset. The MMU can be reset by eJther hard
ware or software mechamsms. A hardware
reset occurs on the fallmg edge of the Reset
sIgnal; a software reset IS performed by a
28000 SpecIal 110 command. A hardware reset
clears the Mode RegIster, ViolatIOn Type
RegISter and Descriptor Selection Counter. If
the Chip Select lme IS Low, the Master Enable
Flag m the Mode RegISter IS set to 1. All other
regIsters are undefmed. After reset, the
ADs-AD15 and As-A23 lmes are 3-stated. The
SUPand SEGT open-dram outputs are not
drl ven. If the Master Enable flag IS not set durmg reset, the MMU does not respond to subsequent addresses on ItS A/D lmes. To enable an
MMU after a hardware reset, an MMU command must be used in conjunction WIth the
ChIp Select lme.
A software reset occurs when the Reset
VIOlation Type RegIster command IS Issued.
ThIS command clears the VIOlation Type
RegIster and returns the MMU to ItS Imtlal
state (as If no VIOlations or warnmgs had
occurred). Note that the hardware and software
resets have different effects.
Segment Trap and Acknowledge. The 28010
MMU generates a segment trap whenever It
detects an access VIOlatIOn or a write mto the
lowest block of a segment WIth the DIRW flag

set. In the case of an access VIOlation, the
MMU also activates Suppress. Th,s Suppress
SIgnal can be used to mhlblt memory writes.
The Segment Trap remams Low until a Trap
Acknowledge sIgnal IS receIved. If a VIOlation
occurs, Suppress IS asserted for that cycle and
all subsequent CPU cycles until the epd of the
mstruchon; mtervenmg DMA cycles are not
suppressed, however, unless they generate a
vlOlahon. VIOlations detected durmg DMA
cycles cause Suppress to be asserted durmg
that cycle only, but no Trap Request IS
generated.
When the MMU Issues a Segment Trap
Request II aWaits a Segment Trap Acknowledge. Subsequent VIOlations occurrmg before
the Trap Acknowledge IS receIved are still
detected and handled appropriately. Durmg
the Segment Trap Acknowledge cycle, the
MMU drives one of ItS Address/Data lmes
HIgh; the particular lme selected IS a funchon
of the Identification field of the mode regIster.
After the Segment Trap has been acknowledged by the 28001/3 CPU, the VlOlahon
Status RegIster should be read vIa the SpeCIal
I/O commands m order to determme the cause
of the trap. The Trap Type RegIster should also
be reset so that subsequent traps will be
recorded correctly.

ACKNOWLEDGE

r----------__

CYCLE---------------.I

~r~T~g

AUTOMATIC WAIT CYCLES

T,

T,

~A~

~

_ _ _ _ _ _ _ _ _ _ _ _~,
~

~

~

~

~

CLOCK

RIW

SEGMENT TAAP ACKNOWLEDGE

ADO-AD15

(

IDENTIFIER

)

'--------'

Figure 12. Segment Trap and Acknowledge Timing

2046·123

165

Pin
Description

between MMU s during different phases of an
mstruction.
Reserved. Do not connect.

As-A23' Address Bus (outputs, active High,
3-state). These address lines are the 16 mostsignificant bits of the physical memory
location.

RESET. Reset (input, active Low). A Low on

ADs-AD15' Address/Data Bus (inputs/outputs,

this line resets the MMU.

active High, 3-state). These multiplexed
address and data lines are used both for commands and for logical addresses intended for
translation.

R/W. Read/Write (input, Low = write). R/W
indicates the 28001/3 CPU or 28016 DMA is
reading from or writing to memory or the
MMU.

AS. Address Strobe (input, active Low). The
rising edge of AS indicates that ADo-AD IS,
STo-ST3, R/W and Nis are valid.
CLK. System Clock (input). CLK is the 5 V
single-phase time-base input used for both the
CPU and MMU.

SEGT. Segment Trap Request (output, active
Low, open dram). The MMU interrupts the
2800113 CPU with a Low on this Ime when the
MMU detects an access violation or write
warning.

SNo-SN6. Segment Number (mputs, active
High). The SNo-SNs lines are used to address
one of 64 segments in the MMU; SN6 is used to
selectively enable the MMU.

CS. Chip Select (input, active Low). This line
selects an MMU for a control command.
DMASYNC. DMA/Segment Number Synchronization Strobe (input, active High). A
Low on this line indICates the segment number
lmes are 3-state; a High indicates the segment
number is valid. It must always be High during
CPU cycles and Low when the SN lines are invalid. If a DMA device does not use the MMU
for address translation, the BUSACK signal
from the CPU may be used as an input to
DMASYNC.

STo-ST3' Status (inputs, active High). These
lines specify the 2800113 CPU status.
ST3- STO

a a a a,
aaa I
aaI a
aa I I
a I aa
aI aI
a I 10

aI

DS. Data Strobe (input, active Low). This line

I I

10 a a
100 I
1010

provides timing for the data transfer between
the MMU and the 28001/3 CPU.

Nis.

I
I
I
I
I

Normal/System Mode (input, Low =
System Mode). Nis indicates the 2800113 CPU
or 28016 DMA is in the Normal or System
Mode. The signal can also be used to switch

aI

I
100
101
I 10
III

Definition

Internal operahon
Memory refresh
I/O reference
SpecIal I/O reference (e.g., to an MMU)
Segment trap acknowledge
Non-maskable mterrupt acknowledge
Non-vectored interrupt acknowledge
Vectored mterrupt acknowledge
Data memory request
Stack memory request

Data memory request (EPU)
Status memory request (EPU)
Instruction space access
Instruchon fetch, hrst word
ExtenslOn processor transfer
Bus Lock, Data Memory Request (ZB003 only)

DOwD,

o,wOn

vt-;;-oo-

AD7

A
ADe-AD1S

~
Z8001
CPU

A,o-A7

~
~

SeGT

AS
OS

RIW
NIS

r--J!IW

~

r---.
rr---.
r---.

r
~

Aa-A23

r

~
5To-5T3

~

+cs

MEMORY
CONTR.OL

SUP

SNo·5N,

'I

-"

1>.

Z8010

MMU

STo-STl

;ul'

~
~
B~

Figure 13. The MMU in a Z8001 System

166

2046-052

Pin
Description

SUP. Suppress (output, achve Low, open
drain). This sIgnal is asserted during the cur-

rent bus cycle when any access violahon
except write warning occurs.

Voltages on all mputs and outputs
wIth respect to GND .......... -0.3 V to + 7.0 V

mum Ratmgs may cause permanent damage to the deVIce.

(Continued)

Absolute
Maximum
Ratings

Standard
Test
Conditions

Stresses greater than those lIsted under Absolute MaXI-

Operatmg AmbIent
Temperature ........ See ordermg mformahon

ThIs IS a stress ratmg only; operatIon of the devlC8 at any
condlhon above those mdlcated In the operahonal sectIons
of these speClfIcatIons IS not lmphed Exposure to absolute

Storage Temperature ........ -65°C to + 150°C

maXlmum ratmg condlhons for extended perIods may affect
deVIce reliabIlIty.

+5V

The charactenshcs below apply for the
followmg standard test condlhons, unless
otherWIse noted. All voltages are referenced to
GND. PosItive current flows mto the referenced pm. Standard condihons are as follows:
•

22K

+4.75 V :5 Vee :5 +5.25 V

• GND

=0V

• O°C :5 TA :5 + 70°C

DC
Characteristics

Parameter

Min

Max

Unit

VeH

Clock Input Hlgh Voltage

Vee- O.4

Vee+ 0.3

V

Driven by External Clock Generator

VeL

Clock Input Low Voltage

-0.3

0.45

V

Driven by External Clock Generator

VIH

Input Hlgh Voltage

2.0

Vee+ 0.3

V

VrL

Input Low Voltage

-0.3

0.8

V

VOH

Output Hlgh Voltage

VOL

Output Low Voltage

0.4

V

IOL = +2.0 rnA

IlL

Input Leakage

±10

I'A

0.4 ,;; VIN ,;; +2.4 V

IOL

Output Leakage

±10

I'A

0.4 ,;; VIN ,;; +2.4 V

ICC

Vee Supply Current

300

rnA

Symbol

Condition

V

2.4

IOH = -2501'A

NOTE The on-chIp back-bIas voltage generator takes approxImately 20 ms to pump the back-bIas voltage to -2 5 V after the power has
been turned on the performance of the 28010 2-MMU IS not guaranteed durmg thIS perIod.

Ordering
Information

Product
Number

Description

Product
Number

Package/
Speed
Temp

Description

28010

CE

4.0 MHz

2-MMU (48-pm)

28010A

CE

6.0 MHz

28010

CM

4.0 MHz

Same as above

28010A

CM

6.0 MHz

Same as above

28010

CMB

4.0 MHz

Same as above

28010A

CMB

6.0 MHz

Same as above

28010

CS

4.0 MHz

Same as above

28010A

CS

6.0 MHz

Same as above

28010

PE

4.0 MHz

Same as above

28010A

PE

6.0 MHz

Same as above

28010

PS

4.0 MHz

Same as above

28010A

PS

6.0 MHz

Same as above

NOTES

8085·0209

Package/
Speed
Temp

2-MMU (48-pin)

C = CeramIC, P = PlastIc, E = _40°C to +85°C, M = -55°C to + 125°e, MB = -55°e to + 125°C WIth
MIL-STD-883 Class B processmg, S = O°C to + 70°C

167

AC Characteristics
No.

Symbol

Parameter

TcC
2
TwCh
3
TwCl
4
TIC
!i-TrC
TdDSA(RDv)
6

Z8010

Z8010

Z8010

4 MHz

6 MHz

10 MHz

Min

Clock Cycle TIme
250
Clock WIdth (HIgh)
105
Clock WIdth (Low)
105
Clock Fall TIme
Clock RIse TIme
DS I (Acknowledge) to Read Data
Valid Delay
7
TdDSA(RDf)
DS t (Acknowledge) to Read Data
Float Delay
TdDSR(RDv)
DS I (Read) to AD Output Driven Delay
8
TdDSR(RDf)
9
DS t (Read) to Read Data Float Delay
10- TdC(WDv)-- CLK t to Write Data Valid Delay
ThC(WDn)
11
CLK I to Write Data Not Valid
30
Hold TIme
12
TwAS
Address Strobe WIdth
60
13
TsOFF(AS)
Offset Valid to AS' t Setup TIme
45
ThAS(OFFn)
14
AS t to Offset Not Valid Hold TIme
60
15- TdAS(C)--- AS I to CLK t Delay
110
16
TdDS(AS)
DS t to AS I Delay
50
TdAS(DS)
17
AS t to i5S I Delay
50
TsSN(C)
SN Data Valid to CLK t Setup TIme
18
100
ThC(SNn)
19
CLK t to SN Data not Valid Hold TIme
0
20- TdDMAS(C)- DMASYNC Valid to CLK t Delay
120
TdSTNR(AS)
21
Stajl,ls (STo-ST 3 , N/S, R/W) Valid to
50
AS t Delay
TdC(DMA)
22
CLK t to DMASYNC j Delay
20
TdST(C)
23
Status (STo-ST3 ) Valid to CLK t Delay
100
TdDS(STn)
24
i5S t to Status Not Valid Delay
0
25 - TdOFF(Av)-- Offset Valid to Address Output
Valid Delay
26
TdST(Ad)
Status Valid to Address Output
Driven Delay
TdDS(Af)
27
DS t to Address Output Float Delay
28
TdAS(Ad)
AS I to Addres Output Driven Delay
TdC(Av)
29
CLK t to Address Output Valid Delay
30 - TdAS(SEGT) AS t to SEGT I Delay
TdC(SEGT}
31
CLK t to SEGT t Delay
TdAS(SUP)
AS t to SUP I Delay
32
TdDS(SUP
33
DS t to SUP t Delay
TsCS(AS)
34
ChIp Select Input Valid to AS t Setup
10
TIDle
35 - ThAS(CSn) - - AS t to ChIp Select Input Not Valld---60
Hold TIme
TdAS(C)
36
AS t to CLK t Delay
0
37
TsCS(RST)
ChIp Select Input Valid to RESET t
150
Setup TIme
ThRST(CSn)
RESET t to ChIp Select Input Not
38
0
Valid Hold TIme
TwRST
39
RESET WIdth (Low)
2TcC
40 - TdC(RDv)-- CLK t to Read Data Vahd Delay
TdDS(C)
41
DS t to CLK t Delay
30
TdC(DS)
42
CLK I to DS t Delay
0
NOTES
1. 50 pF Load
2 2 2K Pull-up
All 6 MHz tImmgs are prehmmary
Umts m nanoseconds (ns)

168

Max

Min

Max

165
70
70

Min

Max

100
40
40

20
20
100

10
15
80

10
10
60

75

60

45

80
60
80

60
45
50

100
75
125

60

Notes*t

20

10

50
35
40
90
30
40
40
0
80
30

30
20
20
50
15
30
20
0
60
10

15
60
0

10
30
0

175

90

60---1-

155

75

45

160
145
255
160
300
150
155

130
70
155
100
200
90
100

100
40
100
60--1,21,2
100
55
1,2
1,2
60

10

10

40

20

0
100

0
60

0

0

2TcC

2TcC
300

460
20
0

190
10
0

CLOCK

TRAP ACKNOWLEDGE

~I
---~C

D_AT_A_ _ _ _ _ _ _

~w __________~\~__________________~;==~

..J!

cs, _ _ _ _ _ _

C
\~________'r__

Figure 13. Write Cycle TimiDg

Interrupt Acknowledge Cycle Timing.
Figure 14 illustrates Interrupt Acknowledge
cycle timing. The address on ADo-AD7 and
the state of CSo and INTACK are latched by
188

the rising edge of AS. However, if INTACK is
Low, the address and CSo are ignored. The
state of the RIW and CS 1 are also ignored for
the duration of the Interrupt Acknowledge
2016·007,008

Timing
(Continued)

intended for the Z-SCC. In this case, the
Z-SCC may be programmed to respond to DS
Low by placing its interrupt vector on
ADo-AD 7. It then sets the appropriate
Interrupt- Under-Service latch internally.

cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
IEIIIEO daisy chains settle. If there is an interrupt pending in the Z-SCC and lEI is High
when DS falls, the Acknowledge cycle was

X

Cio _ _ _..1

(IGNORED)

I

\

X

ADO-AD7 _ _...J

x=::

(IGNORED)

)

;-

CJ(

iJ

}-

VECTOR

I

Figure 14. Interrupt Acknowledge Cycle Timing

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
withrespecttoGND .......... -0.3Vto +7.0V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150 °c

Standard
Test
Conditions

The characteristics below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:

Stresses greater than those hsted under Absolute MaJumum Ratmgs may cause permanent damage to the devlCe.
This IS a stress ratmg only; operahon of the devlCe at any
condlhon above those mdlcated m the operahonal sections
of these speClhcahons IS not Imphed. Exposure to absolute
maximum ratmg condlhons for extended periods may affect
deVice rehablhty.

• +4.75 V :S Vee:s +5.25 V
• GND = 0 V
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.

+5V

21K

+5V

FROM OUTPUT
UNDER TEST

~ 2.2K

r

50P

Figure 15. Standard Test Load

DC
Characteristics

Symbol
VIH
VIL
VOH
VOL
IlL

Im
Icc

>

Figure 16. Open-Drain Test Load

Parameter

Min

Max

Unit

Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

2.0
-0.3
2.4

Vee+ 0.3
0.8

V
V
V
V

0.4
± 10.0
±1O.0
250

~
~
rnA

Condition

IOH=
IOL=
0.4 :S
0.4 :S

-250 ~
+2.0 rnA
VIN :S + 2.4V
VOUT :S +2.4V

Vee = 5 V ± 5% unless otherWise speCIfIed, over speclfIed temperature range.

Capacitance

Symbol

CIN

Parameter

Input Capacitance
Output CapaCitance
CoUT
Bidirectional CapaCitance
CliO
f = 1 MHz, over speCIfied temperature range
2016-009

8085-006. 001

Min

Max

Unit

10
15
20

pF
pF
pF

Test Condition
Unmeasured Pins
Returned to Ground

189

Read and

~

Write
Timing

~
0-l-

~

X
~

X

l(

f--0--

Riw
READ

----cJ- ~
1-w--

-- ®~
I

\-

R/W
WRITE

f--. f-®

WRITE

ADO-AD7
READ

X

H-®

(ii;

ex

'Ii'

X

@-- ~--I@ )(
@~
~

-

®I-

-+

-----®----ADo-AD7

01-

-+

M-®
)(
-+

~
12

@ I-

14

\-

W/REQ
WAIT

r-----w--r
~

W/REQ
REQUEST

DTR/REQ

~

i

REQUEST

21

\4 MHz

No.

Symbol

Parameter

Min

I
TwAS
AS Low WIdth
70
TdDS(AS)
DS t to AS I Delay
2
50
3
TsCSO(AS)
~ to AS t Setup TIme
0
4
ThCSO(AS)
CSo to AS t Hold TIme
60
5-TsCSI(DS) --CS 1 to DS I Setup T I m e - - - - - - - - - - - 100
6
ThCSI(DS)
CS 1 to DS tJiold TIme
55
7
TsIA(AS)
INTACK to AS t Setup Time
0
8
ThIA(AS)
!NTACK to AS t Hold TIme
250
9
TsRWR(DS)
RiW (Read) to DS I Setup Time
100
10-ThRW(DS)--RiW to DS t Hold TIme - - - - - - - - - - 55
II
TsRWW(DS)
R!W (WrIte) to DS j Setup TIme
0
12
TdAS(DS)
AS t to DS j Delay
60
13
TwDSl
DS Low WIdth
390
14
TrC
ValId Access Recovery Tlme
6TcPC
+200
15 - TsA(AS)---Address to AS t Setup Time - - - - - - - - - - 30
16
ThA(AS)
Address to AS t Hold TIme
50
17
TsDW(DS)
WrIte Data to DS j Setup Time
30
18
ThDW(DS)
WrIte Data to DS t Hold TIme
30
19
TdDS(DA)
DS I to Data Acbve Delay
0
20-TdDSr(DR)--DS t to Read Data Not ValId D e l a y - - - - - - - 0
21
TdDSf(DR)
DS I to Read Data ValId Delay
22
TdAS(DR)
AS t to Read Data ValId Delay
NOTES
1. Parameter does not apply to Interrupt Acknowledge
transactions

190

Max

250
520

6 MHz
Min

Max

Notes*t

50
25
0
I
40
I
80 - - - - - - 1 I
40
0
250
80
40
0
40
250
6TcPC
2
+130
10 - - - - - - 1 30
I
20
20
0
0
180
335

2 Parameter applies only between transactions mvolvmg the
*Tlmmgs are prebmmary and subject to change
tUmts m nanoseconds (ns)

sec

y

Interrupt
Acknowledge
Timing

- - - - - -.....
iii

29

ADo-AD, _ _ _ _ _ _ _ _ _ _ _I-_______

++_~

@

,.,

"

=
c
W

Reset
Timing

i

Cycle
Timing

PCLK

4 MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

Max

23
TdDS(DRz)
DS I to Read Data Float Delay
70
45
24
TdA(DR)
Address Required Vahd to Read Data Valid Delay
570
420
25
TdDS(W)
DS I to Wait Valid Delay
240
200
26
TdDSf(REQ)
DS I to W/REQ Not Valid Delay
240
200
27 -TdDSr(REQ)--DS I to DTR/REQ Not Valid D e l a y - - - - - - - - - 5TcPC
5TcPC
+250
+300
500
28
TdAS(INT)
AS I to INT Vahd Delay
500
29
TdAS(DSA)
AS I to DS I (Acknowledge) Delay
250
250
30
TwDSA
OS (Acknowledge) Low Width
250
390
31
TdDSA(DR)
OS I (Acknowledge) to Read Data Valid Delay
180
250
100
32 - TsIEI(DSA) - - lEI to DS I (Acknowledge) Setup TIme - - - - - 120
0
33
ThIEI(DSA)
IEI to DS I (Acknowledge) Hold Time
0
34
TdIEI(IEO)
IEI to lEO Delay
120
100
35
TdAS(IEO)
AS I to lEO Delay
250
250
36
TdDSA(INT)
DS I (Acknowledge) to INT Inactive Delay
500
500
15
37 -TdDS(ASQ)--DS I to AS I Delay for No Reset - - - - - - - 30
38
TdASQ(DS)
AS I to DS I Delay for No Reset
30
30
250
39
TwRES
AS and DS Coincident Low for Reset
250
105
2000
70
1000
40
TwPCl
PCLK Low WIdth
41
TwPCh
PCLK High Width
105
2000
70
1000
42-TcPC
PCLK Cycle T i m e - - - - - - - - - - - - 250 -4000--165-2000
20
15
43
TrPC
PCLK Rise Time
10
20
44
TfPC
PCLK Fall Time
NOTES'
3 Float delay IS dehned as the hme reqUlred. for a ± 0.5 V change
In the output WIth a maxImum de load and minImUm de load.
4 Open-dram output, measured WIth open-dram test load.
5. Parameter IS system dependent. For any Z-SCC In the daISY
cham, TdAS(DSA) must be greater than the sum of TdAS(IEO)
In the daISY cham, TsIEI(DSA)
and TdIEIf(IEO) for each devlce separatmg them

for the hIghest priority deVIce

for the
In

z·see,

Notes*t
3
4

4

5

6
4
7

6. Parameter apphes only to a z·see pulhng iNf Low at the
begmmng of the Interrupt Acknowledge transacbon.
7. Internal CIrCUItry allows for the reset prOVided by the Z8 to be
recogruzed as a reset by the Z-SCC.
.. TImings are prelIminary and subject to change. All tIming references assume 2.0 V for a logIC "1" and 0 B V for a logIC "0".
t UnIts In nanoseconds (ns).

the daISY cham.

2016·011, 012, 013

191

General
Timing

~CLI( ~~=+--r-=~-.M"-____~~t__=====~~"E~:~~

WAIT

~.

______~_,

_ _ _ _ _ _ _ _ _ _ __

.:==:i~~~==_=~'__=
to .x

EUERNAL

~,~

TAANSMIT

TaD

---~~~~~~---

A""

....

~

A

~--

--~@ ~~===--====r-

': ',,-e=L)----,.:'------,==rTRaC

nllc
INPUT

192

\,_~.

_ _ _ __

---~~
'~r.
I

---~

2016-014

No.

2

Min

6 MHz
Min
Max

Parameter

TdPC(REQ)

PCLK

j

to WIREQ Vahd

250

250

TdPC(W)

PCLK

j

to Walt InactIve Delay

350

350

TsRXC(PC)
3
TsRXD(RXCr)
4
5 -ThRXD(RXCr) -

RxC I to PCLK I Setup TIme

50

50

0

0

150

150

RxD to RxC I Setup TIme (XI Mode)
RxD to RxC I Hold TIme (XI Mode)

6

TsRXD(RXCf)

RxD to RxC

j

Setup TIme (XI Mode)

7

ThRXD(RXCf)

RxD to RxC

j

Hold TIme (XI Mode)

8

TsSY(RXC)

SYNC to RxC I Setup TIme

9

ThSY(RXC)

SYNC to RxC I Hold TIme

Notes*t

1,4
I
1-

0

0

1,5

150

1,5

-200

150
-200

3TcPC
+200

3TcPC
+200

I

2,4-

10 -

TsTXC(PC) - - TxC

j

to PCLK I Setup TIme

II

TdTXCf(TXD)

TxC

j

to TxD Delay (XI Mode)

300

300

2

12

TdTXCr(TXD)

hc

I to TxD Delay (XI Mode)

300

2,5

13

TdTXD(TRX)

TxD to TRxC Delay (Send Clock Echo)

300
200

RTxC HIgh WIdth
14
TwRTXh
15 -TwRTXI---RTxC Low WIdth

0

TcRTX

RTxC Cycle TIme

400

17

TcRTXX

Crystal OscIllator PerIod

250

18

TwTRXh

TwTRXl
19
20-TcTRX

250
180

180

TRxC Cycle TIme

400

180
400
200

DCD or CTS Pulse Width

200

TwSY

SYNC Pulse WIdth

200

W

C

N

400
1000

180

TwEXT

=

180
180

TRxC HIgh WIdth

22

N

200

TRxC Low WIdth

21

NOTES

0

180
180

16

I

4 MHz
Max

Symbol

1000

•

fI.I

3

n
n

____

RxC IS RTxC or TRxC, whichever
clu!;k _ _

IS

supplymg the receive

2 TxC IS TRxC or RTxC, whlChever IS supplymg the transmIt
clock _ _
3 Both RTxC and SYNC have 30 pI capacItors to the ground
connected to them

4 Parameter apphes only If the data rate IS one-fourth the PCLK
rate In all...2!..her cases, no phase relationship between RxC and
PCLK or TxC and PCLK IS required

Parameter applies only to FM encodmg/decodmg
* TImmgs are prelimmary and subject to change

t UnIts

In

nanoseconds (ns)

193

System
Timing

AfiC, TAxe
RECEIVE

W/REQ
REQUEST

W/REQ
WAIT

------------------~---------'

SYNC
OUTPUT

iifiC,

TRxe

TRANSMIT

W/REQ
REQUEST

WIREQ
WAIT

__________________

~---------J

DTAlREQ
REQUEST

x.
SYNC
INPUT

](
~

\
~

No.
I

2
3
4

Symbol

Parameter

TdRXC(REQ)
TdRXC(W)

RxC
RxC
RxC
RxC

TdRXC(SY)
TdRXC(INT)

5-TdTXC(REQ)-TxC
6
7
8
9
10

Min

4MHz
Max

t to W/REQ ValId Delay
t to Wait Inachve Delay
t to SYNC Valid Delay
t !NT Valid Delay
j

8
12
8
12
4
7
8
12
+2
+3
to W/REQ ValId D e l a y - - - - - - - - - 5 - - 8

TdTXC(W)
TdTXC(DRQ)
TdTXC(!NT)

TxC j to Wait Inachve Delay
TxC I to DTR/REQ Valid Delay
TxC j to !NT ValId Delay

TdSY(INT)
TdEXT(INT)

SYNC Transition to INT Valid Delay
OCD or CTS Transition to INT Vahd Delay

5
4
4
+2
2
2

8
7
6
+3
3
3

6MHz
Min
Max

Notes"

2,4
8
12
1,2,4
8
12
2,4
4
7
1,2,4
8
12
5
+2
+3
5--8---3,45
4
4
+2
2
2

8

1,3,4

7

3,4
1,3,4
5
1,5
1,5

6
+3
3
3

NOTES
1. Open-dram output, measured wIth open-dram test load.

2. RxC IS RTxC or TRxC, whIchever IS supplymg the receIve
clock.
TxC IS TRxC or RTxC, whlChever'ls supplymg the transmIt
clock.

194

4 UnIts equal to !£pC
5. UnIts equal to AS.
.. TImmgs are prelimmary and subject to change

2016-015

Ordering
Information

Product
Number

Package/
Temp
Speed

Description

Product
Number

Description

28030

CE

4.0 MHz

2-SCC (40-pm)

28030A

CE

6.0 MHz

2-SCC (40-pm)

28030

CM

4.0 MHz

Same as above

28030A

CM

6.0 MHz

Same as above

28030

CMB

4.0 MHz

Same as above

28030A

CMB

6.0 MHz

Same as above

28030

CS

Same as above

28030A

DE

Same as above

28030A

CS
DE

6.0 MHz
6.0 MHz

Same as above

28030

4.0 MHz
4.0 MHz

28030

OS

4.0 MHz

Same as above

28030A

OS

6.0 MHz

Same as above

28030

PE

4.0 MHz

Same as above

28030A

PE

6.0 MHz

Same as above

28030

PS

4.0 MHz

Same as above

28030A

PS

6.0 MHz

Same as above

NOTES' C = Ceramic, D = Cerdlp, P = Plastic; E = _40°C to +85°C, M
wlth Class B processmg, S = O°C to + 70°C

00-2016-A

Package/
Temp
Speed

=

Same as above

_55°C to 125°C, MB = _55°C 10 125°C w.,h MIL-STD-883

195

Z8031 Z8000™ Z-ASCC

Asynchronous Serial
Communications Controller

~
Zilog

Product
Specification

June 1982

Features

General
Description

• Two independent, 0 to 1M bit/second, fullduplex channels, each wIth a separate
crystal oscillator, baud rate generator, and
Digital Phase-Locked Loop for clock
recovery.

• Asynchronous commumcatlons wIth hve to
eIght bIts per character and one, one and
one-half, or two stop blls per charader; programmable clock factor; break detection
and generahon; panty, overrun, and frammg error detection .

• Programmable for NRZ, NRZI, or FM data
encodmg.

• Local Loopback and Auto Echo modes.

The Z8031 Z-ASCC Asynchronous Serial
Commumcations Controller IS a dual-channel
data communications penpheral deSlgned for
use with the Zilog Z-BUS. The Z-ASCC funchons as a senal-to-parallel, parallel-to-serial
converter/controller. The deVIce contains a
vanety of new, sophISticated internal functions
including on-chIp baud rate generators,
DigItal Phase-Locked Loops, and crystal
oscillators that dramatically reduce the need
for external logic.

The Z-ASCC has faclhtles for modem
controls m both channels. In apphcations
where these controls are not needed, the
modem controls can be used for generalpurpose I/O.
The Z-BUS dalsy-cham mterrupt hIerarchy
IS also supported-as IS standard for Z!log
penpheral components.
The Z8031 Z-ASCC IS packaged m a 40-pm
ceramIC DIP and uses a smgle + 5 V power
supply.

TxDA
RxDA...-

I
I

SERIAL
DATA

CHANNEL

CLOCKS

ADDRESSI
DATA BUS

CH·A
CHANNEL
CONTROLS
FOR MODEM,

BUS
TIMING
AND RESET

I

DMA,OR
OTHER

Os
RIW

CONTROL (

INTERRUPT

I

I
I

SERIAL
DATA

CHANNEL
CONTROLS
FOR MODEM,

DMA, OR
Z8031
Z·ASCC

AD,

AD,

AD,

AD,

AD,

iNT

os

lEO

OTHER

As

lEI

R/W

lNTACK
+5V

es,
es,

W/REQA

OND

RIA

RxDA
TRxCA

INTACK

lEO

AD,

RTxCA

CHANNEL
CLOCKS

lEI

AD,
AD,

TxDA
DTRIREQA

W/REQB
RIB
RTxCB
RxDS

TRxeB
TxDB

RTSA

DTRIREQB

eTSA

Rlse

CCCA

crss

PCLK

DCDS

t t t

+5V GND PCLK

Figure 1. Pin Functions

2245-00 I, 002

Figure 2. Pin Assignments

197

Pin
Description

The following sectIon describes the pm
functions of the Z-ASCC. Figures I and 2
detail the respective pin functions and pin
assignments.

ADo-AD7' Address/Data Bus (bidirectional,
active High, 3-state). These multiplexed lines
carry register addresses to the Z-ASCC as well
as data or control mformation to and from
the Z-ASCC.

AS. Address Strobe (input, actIve Low).
Addresses on ADo-AD7 are latched by the rising edge of this signal.

CSo. Chip Select 0 (mput, active Low). This
signal is latched concurrently with the
addresses on ADo-AD7 and must be active for
the mtended bus transaction to occur.

CSl. Chip Select 1 (input, active High). This
second select signal must also be actIve before
the intended bus transaction can occur. CSt
must remain active throughout the transaclion.

CTSA, CTSB. Clear to Send (mputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables their
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The Z-ASCC detects pulses on these inputs
and can interrupt the CPU on both logiC level
transitions.

DCDA, DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accommodate slow
rise-tIme signals. The Z-ASCC detects pulses
on these pins and can interrupt the CPU on
both logIC level transilions.
OS. Data Strobe (mput, active Low). This
signal provides timing for the transfer of data
mto and out of the Z-ASCC. If AS and DS
coincide, this is mterpreted as a reset.

DTR/REQA, DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, active High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if IEI is High and the
CPU is not servicing a Z-ASCC interrupt or
the Z-ASCC is not requesting an interrupt
(Interrupt Acknowledge cycle only). IEO is
198

connected to the next lower prIOrity device's
IEI mput and thus inhibits mterrupts from
lower priority devices.

INT. Interrupt Request (output, open-dram,
actIve Low). This signal IS activated when the
Z-ASCC requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. Durmg this cycle, the
Z-ASCC interrupt daisy cham settles. When
DS becomes active, the Z-ASCC places an
mterrupt vector on the data bus (if lEI IS
High). INTACK is latched by the rismg edge
of AS.
PCLK. Clock (mput). This is the master
Z-ASCC clock used to synchrOnize internal
signals. PCLK is not required to have any
phase relationship With the master system
clock, although the frequency of this clock
must be at least 90% of the CPU clock frequency for a Z8000. PCLK is a TTL level
signal.

RxDA, RxDB. Receive Data (inputs, active
High).' These input signals receIVe serial data
at standard TTL levels.

RIA, RIB. Ring Indicator (inputs, active Low).
These pins can act either as inputs or as part
of the crystal oscillator circuit.
In normal operation (crystal oscillator option
not selected), these pins are inputs similar to
CTS and DCD. In this mode, transitions on
these lines affect the state of the Ring Indicator
status bits in Read Register 0 (Figure 8) but
have no other function.

RTxCA, RTxCB. Receive/Transmlt Clocks
(inputs, active Low). These pms can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock of the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective RI pins as a crystal oscillator. The receive
clock may be I, 16,32, or 64 times the data
rate in Asynchronous modes.

RTSA, RTSB. Request To Send (outputs,
actIve Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 9) IS set, the
RTS signal goes Low. When the RTS bit is
reset and Auto Enable is on, the signal goes
High after the transmitter is empty. With Auto
Enable off, the RTS pin strictly follows the state
of the RTS bit. Both pins can be used as
general-purpose outputs.
R/W. Read/Write (input). This signal specifies
whether the operation to be performed is a
read or a write.

TxDA, TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.

Pin
Description
(Contmued)

Functional
Description

TRxCA. TRxCB. Transmit/Receive Clocks

W/REQA. W/REQB. WOlt/Request (outputs,

(mputs or outputs, achve Low). These pms can
be programmed in several dIfferent modes of
operation. TRxC may supply the receive clock
or the transmIt clock in the mput mode or supply the output of the DIgital Phase-Locked
Loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output
mode.

open-dram when programmed for a Walt funchon, dnven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request hnes
for a DMA controller or as Wait hnes to
synchromze the CPU to the Z-ASCC data rate.
The reset state is Walt.

The funchonal capabhhes of the Z-ASCC
can be descnbed from two dIfferent pomts
of vIew: as a data communicatIOns devIce,
It transmIts and receIves data in a wIde
variety of data commumcations protocols;
as a Z8000 penpheral, It mteracts wIth the
CPU and other penpheral ClrcUlts and IS part
of the system mterrupt structure.

handle data at a rate of I, 1116, 1132, or 1164
of the clock rate supphed to the receIVe and
transmIt clock mputs.

Baud Rate Generator. Each channel in the

Data Communications Capabilities. The
Z-ASCC provides two independent full-duplex
channels programmable for use m any common Asynchronous data communicatIOn protocol. FIgure 3 and the followmg descnpt!On
bnefly detaIl thIs protocol.
Asynchronous Modes. TransmIssIon and
reception can be accomphshed independently
on each channel wIth fIve to eight bits per
character, plus ophonal even or odd panty.
The transmItters can supply one, one-and-ahalf, or two stop bits per character and can
prOVide a break output at any time. The
receiver break-detechon logIc interrupts the
CPU both at the start and at the end of a
receIved break. Recephon IS protected from
spikes by a transient splke-reJechon
mechamsm that checks the SIgnal one-half a
bit time after a Low level is detected on the
receive data mput (RxDA or RxDB m
Figure 1). If the Low does not persIst (as m the
case of a transIent), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together wIth the parhal
character on whICh they occur. Vectored interrupts allow fast servicing of error condlhons
usmg dedicated routmes. Furthermore, a
bUllt-in checking process aVOIds the mterpretation of a framing error as a new start bl1: a
framing error results m the addlhon of one-half
a bit hme to the point at which the search for
the next start bIt begms.
The Z-ASCC does not reqUlre symmetric
transmIt and receIve clock slgnals-a feature
allowing use of the WIde vanety of clock
sources. The transmItter and receiver can

sr

Z-ASCC contams a programmable baud rate
generator. Each generator consists of two 8-bt
hme constant regIsters that form a 16-bit hme
constant, a 16-blt down counter, and a flip-flop
on the output producing a square wave. On
startup, the flIp-flop on the output IS set m a
HIgh state, the value m the time constant
register IS loaded mto the counter, and the
counter starts countmg down. The output of
the baud rate generator toggles upon reachmg
0, the value m the hme constant register is
loaded mto the counter, and the process IS
repeated. The hme constant may be changed
at any hme, but the new value does not take
effect unhl the next load of the counter.
The output of the baud rate generator may
be used as eIther the transmIt clock, the
receIVe clock, or both. It can also drive the
DigItal Phase-Locked Loop (see next sechon).
If the receive clock or transmit clock IS not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pm.
The following formula relates the hme constant to the baud rate (the baud rate is m
bIts/second and the BR clock penod IS m
seconds):
baud rate

=

I
2 (hme constant + 2) x (BR clock perIOd)

Digital Phase-Locked Loop. The Z-ASCC
contains a Digital Phase-Locked Loop (DPLL)
to recover clock mformahon from a data
stream WIth NRZI or FM encoding. The DPLL is
dnven by a clock that IS nominally 32 (NRZI)
or 16 (FM) hmes the data rate. The DPLL uses
thIS clock, along with the data stream, to construct a clock for the data. ThIS clock may then
be used as the Z-ASCC receive clock, the
transmit clock, or both.

PARITY

!r

p

M""~RK""'N""G""''''''NE=---''I "I-O'-T-'....1.,1""':1:1=O.=T=A:1:1....':1.L.1_O_AT_A...Jlul'

i MARKING LINE

ASYNCHRONOUS

Figure 3. Z-ASCC Protocol

199

Iw

-

Functional
Description
(Contmued)

For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
incoming data stream for edges (either 1 to 0
or 0 to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producmg a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the Z-ASCC via the TRxC pm (if
this pin is not bemg used as an input).

Data Encoding The Z-ASCC may be programmed to encode and decode the senal data
in four different ways (Figure 4). In NRZ
encoding, a I is represented by a High level
and a 0 is represented by a Low level. In NRZI
encodmg, a I is represented by no change in
level and a 0 is represented by a change in
level. In FMI (more properly, bi-phase mark)
a transition occurs at the beginning of every
bit cell. A I is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space),
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a I
is represented by no additIOnal transition at
the center of the bit cell. In addition to these
four methods, the Z-ASCC can be used to
decode Manchester (bl-phase level) data by
using the DPLL in the FM mode and programmmg the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is 0 to I,

the bit is a O. If the transItion is I to 0 the
bit IS a 1.

Auto Echo and Local Loopback. The Z-ASCC
is capable of automatically echoing everything
It receives. In Auto Echo mode, RxD IS connected to TxD internally. Auto Echo mode can
be used with NRZI or FM encodmg with no
additional delay, because the data stream IS
not decoded before retransmission. In Auto
Echo mode, the CTS input IS Ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter IS
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The Z-ASCC is also capable of Local Loopback. In this mode TxD is connected to RxD
internally, Just as m Auto Echo mode.
However, in Local Loopback mode, the internal transmit data IS tied to the mternal receive
data and RxD IS Ignored (except to be echoed
out via TxD). The CTS and DCD inputs are
also Ignored as transmit and receive enables.
However, transItions on these mputs can still
cause interrupts. Local Loopback works with
NRZ, NRZI or FM coding of the data stream.
I/O Interface Capabilities. The Z-ASCC
offers the chOICe of Pollmg, Interrupt (vectored
or nonvectored), and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the Z-ASCC are automatically updated whenever any function is performed. The Idea behind polling is for the
CPU to periodically read a status register unlil
the register contents indicate the need for data
to be transferred. Only one register needs to
be read; dependmg on ItS contents, the CPU
either writes data, reads data, or continues.
Two bits m the register indICate the need for
data transfer. An alternative is a poll of the

DATA

NRZ

NRZI

\
\

I
I

\
\

FM1

FMIif

MANCHESTER

Figure 4. Data Encoding Methods

200

2016002

Functional
Description
(Contmued)

Interrupt Pending regIster to determme the
source of an mterrupt. The status for both
channels resIdes m one register.
Interrupts. The Z-ASCC interrupt scheme
conforms to the Z-BUS speclhcahon. When a
Z-ASCC responds to an Interrupt Acknowledge
signal (INTACK) from the CPU, an interrupt
vector may be placed on the A/D bus. This
vector IS written in WR2 and may be read m
RR2A or RR2B (FIgures 8 and 9).
To speed interrupt response hme, the
Z-ASCC can modify three bits m this vector to
indICate status. If the vector IS read m Channel
A, status is never included; If It IS read in
Channel B, status IS always included.
Each of the six sources of mterrupts m the
Z-ASCC (Transmit, Receive, and External/Status interrupts in both channels) has
three bIts associated wIth the mterrupt source:
Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bit is straIghtforward. If the IE bit
IS set for a gIven interrupt source, then that
source can request mterrupts. The excephon is
when the MIE (Master Interrupt Enable) bit in
WR9 is reset and no interrupts may be
requested. The IE bIts are write only.
The other two bits are related to the Z-BUS
interrupt priority chain (Figure 5). The
Z-ASCC may request an mterrupt only when
no higher priority device is requesting one,
e.g., when lEI is HIgh. If the deVIce m question requests an interrupt, it pulls down INT.
The CPU then responds with INTACK, and the
mterruptmg device places the vector on the
AID bus.
In the Z-ASCC, the IP bit signals a need for
interrupt servicing. When an IP bIt is I and
the lEI input is High, the INT output is pulled
Low, requesting an mterrupt. In the Z-ASCC,
if the IE bit IS not set by enabling mterrupts,
then the IP for that source can never be set.
The IP is set two or three AS cycles after the
interrupt condition occurs. Two or three AS
rising edges are required from the hme an
interrupt condition occurs until INT is activated. The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all mterrupt
sources of lower priority in the Z-ASCC and

Z·BUS
PERIPHERAL
lEI ADo-AD7

iNT

external to the Z-ASCC are prevented from
requestmg interrupts. The internal interrupt
sources are mhibited by the state of the internal daISY chain, whIle lower prIOrity deVIces
are mhlbited by the IEO output of the Z-ASCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set durmg an
Interrupt Acknowledge cycle if there are no
higher Priority deVIces requesting interrupts.
There are three types of mterrupts:
TransmIt, ReceJve, and External/Status. Each
mterrupt type IS enabled under program control with Channel A having hIgher priority
than Channel B, and wIth Receiver, TransmIt,
and External/Status mterrupts priorihzed in
that order within each channel. When the
Transmit mterrupt IS enabled, the CPU IS
interrupted when the transmIt buffer becomes
empty. (ThIS implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receIver can interrupt the CPU in one of
three ways:
• Interrupt on First Receive Character or
SpecIal ReceIve CondItion.
• Interrupt on All ReceIve Characters or
Special Receive Condition.
• Interrupt on Special Receive Condihon
Only.
Interrupt on FIrst Character or SpecIal Condlhon and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A SpecIal Receive Condition is receiver
overrun, and, optionally, a parity error. The
Special Receive Condition mterrupt IS different
from an ordinary receive character available
mterrupt only m the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on FIrst Receive Character, an interrupt can occur from Special Receive Conditions any time after the first receive character
interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and RI pins; however, an
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detechon
of a Break.

Z·BUS
PERIPHERAL

INTACK lEO

lEI ADo-AD7

iNT

Z·BUS
PERIPHERAL

INT ACK lEO

lEI ADo-AD1

iNf

INTACK

+5V
+5V

ADo-AD7

\r--------:--:---------.,----------'

INT.-------~_+--------~_+--------~_+~
INTACK~-------~

_________

~

_________

~

Figure S. Z-BUS Interrupt Schedule

2016·003

201

I...w

i

Functional
Description
(Contmued)

CPU/DMA Block Transfer. The Z-ASCC provides a Block Transfer mode to accommodate
CPU block transfer functions and DMA controllers. The Block Transfer mode uses the
WAIT/REQUEST output m conjunction with the
WaiVRequest bits in WRl. The WAIT/
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the

DMA Block Transfer mode.
To a DMA controller, the Z-ASCC REQUEST
output indicates that the Z-ASCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the Z-ASCC is not
ready to transfer data, thereby requestmg that
the CPU extend the I/O cycle. The DTR/
REQUEST lme allows full-duplex operation
under DMA control.

Architecture

The Z-ASCC internal structure mcludes
two full-duplex channels, two baud rate
generators, internal control and interrupt
logic, and a bus interface to the Zilog Z-BUS.
Associated with each channel are a number of
read and write registers for mode control and
status information, as well as logic necessary to
mterface to modems or other external devices
(FIgure 6).
The logIC for both channels provIdes
formats, synchronization, and validation for

data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) regIsters, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the

INTERNAL
CONTROL

lOGIC

_

}

MODEM, DMA, OR
OTHER CONTROLS

ADDRESSI

DATA
CPU

BUS 1/0
CONTROL
}

INTERRUPT

CONTROL
LINES

MODEM, DMA, OR
OTHER CONTROLS

INTERRUPT
CONTROL
LOGIC

} SERIAL DATA

ttt

} CHANNEL CLOCKS

Ai

+5VGND PCLK

WAIT/REQUEST

Figure 6. Block Diagram of Z-ASCC Architecture

202

2245-003

~c;

~>

0 ..

o n

~

af!
5 i
c n
CD
p.S::

~;
CPU 110

BR GENERATOR

8ft GENERATOR

INPUT

RECEIVE

RECEIVE

DATA

ERROR

FIFO

FIFO

OUTPUT

TRANSMIT
CLOCK

R,D

DPLL

DPLL OUTPUT

~

I

BR GENERATOR OUTPUT
DPLL OUTPUT - - - -..
--1-

TRxC-----o-t

AT,C--.,.---I

RECEIVE CLOCK

CLOCK

MUX

TRANSMIT CLOCK
DPLL CLOCK

BR GENERATOR CLOCK

iii
(OSCILLATOR)

tv

a
w

Figure 7. Data Path

33SY-Z I £oaz

Architecture
(Contmued)

baud rate. Fmally, assocIated wIth the interrupt logIC is a wrIte register for the mterrupt
vector accessible through eIther channel, a
write-only Master Interrupt Control regIster
and three read regIsters: one contaming the
vector wIth status mfomatIon (Channel B only),
one containing the vector without status
(Channel A only), and one containing the
Interrupt Pendmg bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WRI5 -

Write Registers 0-5, 8-15.

Read Register Functions

RRO
RRI

TransmlVRecelve buffer status and External status

RR2

Modlhed mterrupt vector (Channel B only)
Unmodlhed mterrupt vector (Channel A only)

SpeCIal ReceIve CondItion status

RR3

Interrupt Pendmg bIts (Channel A only)

RR8

ReceIve buffer

RRIO

MIscellaneous status

RRl2

Lower byte of baud rate generator hme constant

RRl3

Upper byte of baud rate generator lIme constant

RRl5

External/Status mterrupt mformatIon

RRO-RR3, RRIO, RRI2, RRI3, RRl5 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table I lists the functions assIgned to each
read or WrIte regIster. The Z-ASCC contams
only one WR2 and WR9, but they can be
accessed by either channel. All other registers
are paired (one for each channel).
Data Path. The transmit and receive data path
illustrated in FIgure 7 is identIcal for both
channels. The receiver has three 8-bit buffer
registers m an FIFO arrangement, in addition
to the 8-bit reC81ve shift register. This scheme
creates addItional tIme for the CPU to service
an interrupt at the begmnmg of a block of
high speed data. Incoming data IS routed
through one of several paths depending on the
selected mode (the character length determmes the data path).
The transmItter has an 8-blt TransmIt Data
buffer regIster loaded from the internal data
bus and an II-bIt TransmIt ShIft regIster that IS
loaded from the TransmIt Data regIster.
Programming

204

The Z-ASCC contams 11 WrIte regIsters m
each channel that are programmed by the
system separately to confIgure the functIonal
personalIty of the channels. All of the regIsters
m the Z-ASCC are dIrectly addressable. How
the Z-ASCC decodes the address placed on
the address/data bus at the begmning of a
Read or WrIte cycle IS controlled by a command Issued in WROB. In the shIft right mode,
the channel select AlB is taken from ADo and
the state of AD5 is Ignored. In the shIft left

Write Register Functions
WRO

eRe

InitIahze, InItIalIzation commands for the

varIOUs modes, shIft flghVshdt left command

WRI

TransmlVRec81ve mterrupt and data transfer mode
dehmhon

WR2

Interrupt vector (accessed through eIther channel)

WR3

ReceIve parameters and control

WR4

TransmIt/ReceIve miscellaneous parameters and

modes
WR5

TransmIt parameters and controls

WR8

TransmIt buffer

WR9

Master mterrupt control and reset (accessed

WRIO

MIscellaneous transmItter/receIver control bIts

WRll

Clock mode control

WRl2

Lower byte of baud rate generator hme constant

through mther channel)

WRl3

Upper byte of baud rate generator bme constant

WRl4

MIscellaneous control bIts

WRl5

ExternaVStatus mterrupt control

Table I. Read and Write Register Functions

mode, A/B is taken from AD5 and the state of
ADo is Ignored. AD7 and AD6 are always
Ignored as address bIts and the regIster
address itself occupIes AD4 - ADI.
The system program fIrst issues a series of
commands to imllalize the basic mode of
operation. For example, the character length,
clock rate, number of stop bIts, even or odd
parity mIght be set fIrst. Then the Interrupt
mode would be set, and fmally, receIver or
transmitter enable.

Programming Read Registers. The Z-ASCC contams eIght
(Conhnued)
read regIsters (actually mne, countmg the
receIVe buffer [RRS]) m each channel. Four of
these may be read to obtam status mformahon
(RRO, RRl, RRIO, and RR15). Two registers
(RR12 and RR13) may be read to learn the
baud rate generator hme constant. RR2 contams eIther the unmodIfIed mterrupt vector
(Channel A) or the vector modIfied by status
mformahon (Channel B). RR3 contams the

Interrupt Pendmg (lP) bIts (Channel A).
FIgure S shows the formats for each read
register.
The status bIts of RRO and RRI are carefully
grouped to SImplIfy status momtormg; e.g.,
when the mterrupt vector mdicates a Special
ReceIve CondlllOn interrupt, all the appropriate error bIts can be read from a smgle
regIster (RR1).

Read Register 0

Read Register 10

10, 10, 10, 10.1 0,1 0, 10, 1Do I

I~I~I~I~I~I~I~I~I

~ R,CHARACTERAVAILABLE

L
E~~

ZERocaUNT
Tx BUFFER EMPTY

DCD
RING INDICATOR

CTS
1

~j
E
~ ~wo

CLOCKS MISSING

ONE CLOCK MISSING

BREAK

Read Register 1

Read Register 12

I~I~I~I~I~I~I~I~I

E~

LOWER Byre OF
TIME CONSTANT

TC,

Read Register 13

Read Register 2

E~

UPPER BYTE OF
TIME CONSTANT

INTERRUPT VECTOR·

v,

*MODIFIED IN B CHANNEL

Read Register 3

E~~

Read Register 15

L~CHANNELBEXTISTATIP'
CHANNEL B Tx Ip·

CHANNEL B Rx Ip·
CHANNEL A EXT/STAT IP*
CHANNEL A Tx IP*
CHANNEL A Rx fp·

o

o
"ALWAYS 0 IN B CHANNEL

Figure 8. Read Register Bit Functions

205

Programming Write Registers. The Z-ASCC contains 11

(Contmued)

write registers (12 counting WR8, the transmit
buffer) m each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and
Write Register 0

WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the mterrupt vector for both channels, while
WR9 contains the interrupt control bits. Figure
9 shows the format of each write register.

Write Register 3

1
0

0

NULL CODE

o

1

NULL CODE

1

0

SELECT SHIFT LEFT MODP

1

1

:ELECT SHIFT RIGHT MODE*

NULL CODe

o

0

NULL CODe

o

1

Ax 7 BITS/CHARACTER

RESET EXT/STATUS INTERRUPTS

1

0

Rx 6 BITS/CHARACTER

1-+- ,.~~~

NULL CODE

1

1

Rx 8 BITS/CHARACTER

I-'-I-'-~
c2..c2..c2..

ERROR RESET

+~+
~r;-~

ro'1'1

I-'-~I-'­

Rx 5 BITS/CHARACTER

ENABLE INT ON NEXT Rx CHARACTER
RESET Tx 'NT PENDING

Write Register 4

RESET HIGHEST IUS

I

Write Register 1

~
o

L EXT INT ENABLE

~
L

IL

L

PARITY ENABLE
PARITY EVEN/ODD

o
o

0

DO NOT PROGRAM

1

1 STOP BIT/CHARACTER

1

0

1 Yt STOP BITS/CHARACTER

1

1

2 STOP BITS/CHARACTER

Tx INT ENABLE
PARITY IS SPECIAL CONDITION

0

Ax INT DISABLE

o

1

Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION

1

OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION

X16 CLOCK MODE

1

1

X32 CLOCK MODE

X 1 CLOCK MODE

Rx INT ON SPECIAL CONDITION ONLY

X64 CLOCK MODE

L _ _ _ _ _ WAIT/DMA REQUEST ON RECEIVErrRANSMIT
' - - - - - - - - WAIT/DMA REQUEST FUNCTION
' - - - - - - - - - WAITIDMA REQUEST ENABLE

Write Register 5
Write Register 2
I~I~I~I~I~I~I~I~I

E~

INTERRUPT VECTOR

o
o

0

Tx 5 BITS (OR LESS)lCHARACTER

1

Tx 7 BITS/CHARACTER

1

0

Tx 8 BITS/CHARACTER

1

1

Tx 8 BITS/CHARACTER

L _ _ _ _ _ _ _ DTR

Figure 9. Write Register Bit Functions

206

2245-006

Programming Write Register 9
(Contmued)

Write Register 12

'~I~I~I~I~I~I~I~'

L~:~
~~

DLC

o

0

NO RESET

o

1

CHANNEL RESET 8

MIE

LOWER BYTE OF

~ATUS HIGH/STATUS LOW

TIME CONSTANT

1

0

CHANNEL RESET A

1

1

FORCE HARDWARE RESET

Write Register 13
Writer Register 10

UPPER BYTE OF
TIME CONSTANT

o
o

0

1

NAZI

1

0

FM1 (TRANSITION

1

1

FMO (TRANSITION "" 0)

I...

i

HRZ

Write Register 14

= 1)

'~I~I~I~I~I~I~I~'

L
~llli

L BR OENERATOR ENABLE

Write Register 11

BR GENERATOR SOURCE

DfRIREQUEST FUNCTION
AUTO ECHO

LOCAL LOOPBACK

o

0

NULL COMMAND

fRiC OUT _ XTAL OUTPUT

o
o

0

0

0

1

ENTER SEARCH MODE

o

1

0

RESET MISSING CLOCK

0

o
o

1

1

'fAxC OUT =
TRiC OUT".

1

1

DISABLE DPLL

1

1

TiiiC OUT = DPLL OUTPUT

1
1

0
0

0
1

SET SOURCE

1

1

0

SET FM MODE

1

1

1

SET NRZI MODE

~

TRANSMIT CLOCK
BR GENERATOR OUTPUT

TRxC o/i

o
o

0

TRANSMIT CLOCK

= RfiC PIN
= TRxC PIN

1

TRANSMIT CLOCK

1

0

TRANSMIT CLOCK"" BR GENERATOR OUTPUT

1

1

TRANSMIT CLOCK

= DPLL OUTPUT

o
o

0
1

RECEIVE CLOCK

1

0

RECEIVE CLOCK

1

1

RECEIVE CLOCK "" DPLL OUTPUT

RECEIVE CLOCK = RTxC PIN

= fRxC PIN
= BR GENERATOR OUTPUT

' - - - - - - - - - ffi'iC XTAUNO XTAL

= BR GENERATOR

SET SOURCE _ FffiC

Write Register IS
'~I~I~I~I~I~I~I~'

m~

~;EROCOUNTIE

CDCDIE

iii IE
CTSIE
1

' - - - - - - - - BREAK IE

Figure 9. Write Register Bit FUDCIiollS (Conhnued)

2245-006

207

Timing

The Z-ASCC generates internal control
signals from AS and DS that are related to
PCLK. Since PCLK has no phase relationship
with AS and DS, the circuitry generating these
internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the Z-ASCC. The recovery
time required for proper operation is specified
from the rising edge of DS in the first transaction involving the Z-ASCC to the falling edge

of DS in the second transaction involvmg the
Z-ASCC. This time must be at least 6 PCLK
cycles plus 200 ns.

Read Cycle Timing. Figure 10 illustrates
Read cycle timing. The address on ADo-AD 7
and the state of CSo and INTACK are latched
by the rising edge of AS. R/"W must be High to
indicate a Read cycle. CSj must also be High
for the Read cycle to occur. The data bus
drivers in the Z-ASCC are then enabled while
DS is Low.

AS~
~o

_____
\~ _ _ _ _~/_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

\~-------------------( ____--iX
)
X~~=::...J~---'\.
c
- - - - - - - '7
7
c

ADO- AD 7 _ _ _....

R/VI

cs,

ADDRESS

DATA VALID

}---

\. . . ____---Jr--

Figure 10. Read Cycle Timing

Write Cycle Timing. Figure II illustrates
Write cycle timing. The address on ADo-AD7
and the state of CSc and INTACK are latched
by the rising edge of AS. R/"W must be Low to

indicate a Write cycle. CSj must be High for
the Write cycle to occur. DS Low strobes the
data into the Z-ASCC.

I

\~-----------------A'Do-AD7

AlW

cs,

~

ADDRESS

x::x_______

>C

\

C

/

c

DA_T_A_ _ _ _ _ _

---------'

\. . . ____---Jr--

Figure ll. Write Cycle Timing

Interrupt Acknowledge Cycle Timing.
Figure 12 illustrates Interrupt Acknowledge
cycle timing. The address on ADo-AD7 and
the state of CSc and INTACK are latched by
208

the rising edge of AS. However, if INTACK is
Low, the address and CSo are ignored. The
state of the R/"W and CSj are also ignored for
the duration of the Interrupt Acknowledge
2016~007,

008, 005

Timing

(Continued)

cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
IEI/IEO dalsy chains settle. If there is an interrupt pending in the Z-ASCC and lEI is High
when DS falls, the Acknowledge cycle was

X

CSo _____-J

(IGNORED)

X:=:'J---:- - J'

~

\
ADO-AD7 ______

intended for the Z-ASCC. In this case, the
Z-ASCC may be programmed to respond to
DS Low by placing its interrupt vector on
ADo-AD7. It then sets the appropriate
Interrupt- Under-Service latch internally.

J

..i)(C~IIG~N~O:R~ED~)==»-------i/,~'-------~~__V_EC_T_OR____J}----

Figure 12. Interrupt Acknowledge Cycle Timing

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C

Standard
Test
Conditions

The characterishcs below apply for the
follOWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:

Stresses greater than those hsted under Absolute MaXI'
mum Ratings may cause permanent damage to the devlCe.
ThIs IS a stress rahng only; operation of the deVice at any
condItion above those IndlCated In the operahonal sections
01 these speclfIcahons is not lmphed. Exposure to absolute
maxImum ratmg condlhons lor extended penods may affect
devlCe rehabihty.

• +4.75 V :5 Vee :5 +5.25 V
• GND = 0 V
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.

+5V
+5V

2.1K

FROM OUTPUT
UNDER TEST

~
I

Figure 13. Standard Test Load

DC

Symbol

Characteristics

2.2K
soOF

Figure 14. Open-Drain Test Load

Parameter

Min

Max

Unit

Input HIgh Voltage
Input Low Voltage
Output HIgh Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current

2.0
-0.3
2.4

Vec +0.3
0.8

V
V
V
V

0.4
± 10.0
± 10.0
250

p,A
p,A

Condition

IaH=

-250 p,A

1m = +2.0 rnA
0.4 :$ VIN :$ + 2.4V
0.4 :$ VOUT :$ + 2.4V

rnA

Vee:;;; 5 V ± 5% unless otherWise speclbed, over speclfled temperature range

Capacitance

Symbol

Parameter
Input CapacItance
Output CapacItance
Bldlrechonal CapacItance

Min

Max

Unit

10
15
20

pF
pF
pF

Test Condition
Unmeasured Pms
Returned to Ground

f = 1 MHz, over speclhed temperature range
2016~009

8085~006,

001

209

!-

Read and
Write
Timing
Cio

~

.J-I

J(

.~ ~

X

-

~

AIW
READ

A/W

---a4.. W
1-w--

-- ®~
/

\.

WRITE

--

I--- -®

-----@---ADO~ADT

)j

WRITE

®ADo-AD7
READ

----J
®-

-

-

+®-

0-

®

®I+-

H-®

~

14

X

-

f---1-®
)i

~

~

-®+

X

01-

-+

@

l+-

II

~

WIARQ

"

r-w---r

WAIT

WIAIQ

~

REQUEST

DTAIAEQ

~

/

REQUEST

\.
28

No.

Symbol

I
TwAS
TdDS(AS)
2
TsCSO(AS)
3
ThCSO(AS)
4
5-TsCSI(DS)-ThCSI(DS)
6
TsIA(AS)
7
ThIA(AS)
8
TsRWR(DS)
9
10 - ThRW(DS)-TsRWW(DS)
11
TdAS(DS)
12
13
TwDSl
14
TrC
15 16
17
18
19
20 21
22

Parameter
AS Low Width
DS 1 to AS I Delay
C~ to AS 1 Setup Time
CSa to AS 1 Hold Time
CS 1 to DS I Setup Time
CSt to DS l.Jiold Time
INTACK to AS I Setup Time
INTACK to AS I Hold Tlme
R!yt (Read) to DS I Setup Time
RI"'!{ to DS I Hold Time
RIW (Write) to DS I Setup Time
AS I to DS I Delay
DS Low Width
Valid Access Recovery Time

TsA(AS) - - - Address to AS I Setup Time
ThA(AS)
Address to AS I Hold Time
TsDW(DS)
Write Data to DS I Setup Time
ThDW(DS)
Write Data to DS I Hold Time
TdDS(DA)
DS I to Data Active Delay
TdDSr(DR) - - DS I to Read Data Not Valid Delay
TdDSf(DR)
DS I to Read Data Valid Delay
TdAS(DR)
AS I to Read Data Valid Delay

NOTES.
1. Parameter does not apply to Interrupt Acknowledge
transactIons.
2. Parameter applies only between transactIons involVing

210

Min

4 MHz
Max

6MHz
Min
Max
50
25
0
40
80
40
0
250
80
40
0
40
250
6TcPC
+ 130
10
30
20
20
0
0

70
50
0
60
100
55
0
250
100
55
0
60
390
6TcPC
+200
30
50
30
30
0
0
250
520

Notes*t

1
1
1I

2
1-

1

180
335

the Z-ASCC
*Tlmmgs are preliminary and subject to change.

i Umts m nanoseconds (ns).
201G-01O

Interrupt
Acknowledge
Timing
.NTACK

------------~~~--~--~~--------------------------

ADO-AD7----------------------t---------------11~-(~::~t:::::tJ~-----------@--@

••• --JF~__------~~--~,-_+----------~'~------

~J.-----Reset
Timing

Cycle
Timing

4 MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

Max

DS t to Read Data Float Delay
70
45
Address ReqUIred Valid to Read Data Valid Delay
420
570
DS I to Walt Vahd Delay
240
200
DS I to WIREQ Not Valid Delay
240
200
DS t to DTRlREQ Not Valid D e l a y - - - - - - - - 5TcPC
5TcPC
+300
+250
500
28
TdAS(INT}
AS t to INT Valid Delay
500
29
TdAS(DSA}
AS t to DS I (Acknowledge) Delay
250
30
TwDSA
DS (Acknowledge) Low Width
390
31
TdDSA(DR}
DS I (Acknowledge) to Read Data Valid Delay
250
180
32 - TsIEl(DSA} - - lEI to DS I (Acknowledge) Setup Time - - - - - 120
100
33
ThlEI(DSA}
lEI to DS t (Acknowledge) Hold Time
0
0
34
TdIEl(lEO}
lEI to lEO Delay
120
100
35
TdAS(lEO}
AS t to lEO Delay
250
250
36
TdDSA(INT}
DS I (Acknowledge) to INT Inactive Delay
500
500
15
37 - TdDS(ASQ} - - DS t to AS I Delay for No Reset - - - - - - - 30
38
TdASQ(DS}
AS t to DS I Delay for No Reset
30
30
39
TwRES
AS and DS CoinCident Low for Reset
250
250
70
40
TwPCl
PCLK Low Width
105
2000
1000
2000
70
1000
41
TwPCh
PCLK High Width
105
42 -TcPC
PCLK Cycle Time - - - - - - - - - - - - 250- 4000 - - 1 6 5 - 2000
15
43
TrPC
PCLK Rise Time
20
10
44
TfPG:
PCLK Fall Time
20
23
TdDS(DRz}
TdA(DR}
24
25
TdDS(W}
26
TdDSf(REQ}
27-TdDSr(REQ}-

Notes*t
3
4

4
5

6
4
7

NOTES.
3. Float delay IS dehned as the bme required for a ± 0 5 V change
In the output With a maximum de load and mlrumum de load.
4. Open-dram output, measured With open-dram test load.
5. Parameter IS system dependent. For any Z-ASCC In the daiSY

cham, TdAS(DSA) must be greater than the sum of TdAS(lEO)
In the daISY cham, TsIEI(DSA)
for the Z·ASCC, and TdIEIf(lEO) for each deVIce separatmg

for the highest priority deVIce

them

In

6. Parameter applIes only to a Z-ASCC pulhng INT Low at the
begmrung of the Interrupt Acknowledge transactIon.
7 Internal CIrCUItry allows for the reset provIded by the Z8 to be
recognized as a reset by the ZMASCC
.. TImings are prehmmary and subject to change. All timing refer
ences assume 2.0 V for a logIC "I" and 0 8 V for a lOgIC "0".
t U mts m nanoseconds (ns).

M

the daISY chain.

2016·011,012,013

211

General
Timing

PeL!(

W'RlQ--------------------~-----------------+--~~,

REQUEST

Wiiifi
WNT ____________~~--~-----------------------'

iiTiC, TRaC

RECEIVE ________________~ I

IbD

TIblC,RTaC
TRANSMIT

TaD

nbC

--C~:

___.__Ji<'--------J, '-_____

------'-~-------~®~~~--~.~

OUTPUT _______________________...i

--------------------------------------------'---"""7-:-----:::----:-----------------------------

\~r:T3
~c---~\~_ _~-----\~___~r_

em. DCii, iii

.II'\.

/

---'~~

212

2245-007

No.

Symbol

Parameter

Min

I

TdPC(REQ)

PCLK

2

TdPC(W)

3
4

TsRXC(PC)

PCLK j to Walt Inachve Delay
RxC , to PCLK , Setup TIme

TsRXD(RXCr)

RxD to RxC , Setup TIme (Xl Mode)

5-

ThRXD(RXCr) -

6
7
8

j

4 MHz
Max

to W/REQ Vahd

6 MHz
Min
Max

250

250

350

350

Notes*t

1,4

50

50

0

0

RxD to RxC , Hold TIme (XI Mode) - - - - - - 150
RxD to RxC , Setup TIme (Xl Mode)
0

150

TsRXD(RXCf)
ThRXD(RXCf)
TsTXC(PC)

RxD to RxC j Hold TIme (Xl Mode)
TxC , to PCLK , Setup TIme

150

150

1,5

0

0

2,4

9
10 -

TdTXCf(TXD)
TdTXCr(TXD) -

0

11

TdTXD(TRX)

TxC j to TxD Delay (Xl Mode)
300
TxC , to TxD Delay (Xl Mode) - - - - - - - - - - - 300
TxD to TRxC Delay (Send Clock Echo)

12

TwRTXh

RTxC HIgh WIdth

180

13

TwRTXI

RTxC Low WIdth

180

14

TcRTX

2
300
300---2,5180
180

15 -

400
RTxC Cycle TIme
TcRTXX - - - Crystal Osclllator PerlOd - - - - - - - - - - - 250 -

16

TwTRXh

TRxC HIgh WIdth

180

180

17

TwTRXl

TRxC Low WIdth

180

180

18

TcTRX

TRxC Cycle TIme

400

400

19

TwEXT

DCD or CTS or

200

200

ill Pulse WIdth

NOTES
1 RxC IS HIxe or TRxC, whichever IS supplymg the receive
clock
2 Ixe IS TRxC or HIxe, whichever IS supplymg the transmit
clock
3 Both RTxC and Rf have 30 pf capacitors to the ground
connected to them

11,5

400
1000 - - 250 -

N

00

1000 - - - 3 -

-..
0
W
N

•

Ul

C":t
C":t

Parameter apphes only If the data rate IS one-fourth the PCLK
rate In all other cases, no phase relatIonship between RxC and
PCLK or Ixe and PCLK 15 required
5 Parameter apphes only to FM encodmg/decodmg
* Tlmmgs are prehmmary and subject to change
i Umts m nanoseconds (ns)
4

213

System
Timing

RTxC, TRxC
RECEIVE

WIREQ
REQUEST

WIREQ
WAIT

RTxC, TRxC
TRANSMIT

WIREQ
REQUEST

WIREQ
WAIT

OTNREQ------------------------~r-----,
REQUEST

CTS.OC~~:,----tf,.....-

y--

t~-----~0r-----~t------------------4 MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

Max

Notes*

2,4
12
8
12
8
12
8
12
8
1.2,4
1,2,4
12
8
12
8
5
+3
+2
+3
+2
4-TdTXC(REQ)-TxC I toW/REQ Valid D e l a y - - - - - - - - - 5 - - 8 - - - 5 - - 8 - - - 3,41,3,4
5
TdTXC(W)
TxC I to Wait Inactive Delay
5
8
5
8
3,4
6
TdTXC(DRQ)
TxC I to DTRlREQ Valid Delay
4
7
4
7
1,3,4
TdTXC(INT)
TxC I to INT Valid Delay
4
4
6
7
6
+2
+3
5
+2
+3
1,5
3
TdEXT(INT)
DCD, ill or CTS Transition to INT Valid Delay
2
3
2
8
TdRXC(REQ)

2
3

TdRXC(W)
TdRXC(INT)

RxC 1 to W/REQ Valid Delay
RxC 1 to Wail Inactive Delay
RxC 1 INT Valid Delay

NOTES.

1 Open-dram output, measured WIth open-dram test load.
2. RxC IS RTxC or TRxC, whichever IS supplYing the receIve
clock.
3. TxC IS TRxC or RTxC, whIchever IS supplymg the transmlt
clock.

214

4. Umts equal to TcPC.
5. Units equal to AS.
.. Timings are preliminary and subject to change.

2245·008

Ordering
Information

Product
Number

Package/
Speed
Temp

Description

Product
Number

Package/
Speed
Temp

Description

Z8031

CE

4.0 MHz

Z-ASCC (40-pm)

Z8031A

CE

6.0 MHz

Z8031

CM

4.0 MHz

Same as above

Z8031A

CM

6.0 MHz

Same as above

Z8031

CMB

4.0 MHz

Same as above

Z8031A

CMB

6.0 MHz

Same as above

Z8031

CS

4.0 MHz

Same as above

Z8031A

CS

6.0 MHz

Same as above

Z8031

DE

4.0 MHz

Same as above

Z8031A

DE

6.0 MHz

Same as above

Z8031

DS

4.0 MHz

Same as above

Z8031A

DS

6.0 MHz

Same as above

Z8031

PE

4.0 MHz

Same as above

Z8031A

PE

6.0 MHz

Same as above

Z8031

PS

4.0 MHz

Same as above

Z8031A

PS

6.0 MHz

Same as above

Z-ASCC (40-pm)

NOTES C =: CeramIc, D = Cerdlp, P ::::: Plashc, E ::::: -40°C to +85°C, M = -55'C to 125'C. MB = -55'C to + !25'C wIth
MIL-STD-883 wIth Class B processmg, S ::::: O°C tn +70°C

00·2245-01

215

Z8036 Z8000™ Z-CIO

CounterlTimer and
Parallel 1/0 Unit

~
Zilog

Product
Specification

June 1982

Features

General
Description

• Two independent 8-blt, double-buffered,
bidirectional I/O ports plus a 4-bit
special-purpose I/O port. I/O ports
feature programmable polarity,
programmable direction (Bit mode), "pulse
catchers," and programmable opendrain outputs.

• Flexible pattern-recognition logic, programmable as a 16-vector interrupt controller.

• Four handshake modes, including 3-Wire
(like the IEEE-488).

• Three independent 16-bit counter/timers
with up to four external access lines per
counter/timer (count input, output, gate,
and trigger), and three output duty cycles
(pulsed, one-shot, and square-wave),
programmable as retriggerable or
nonretriggerable.

• REQUEST/WAIT signal for high-speed data
transfer.

• Easy to use since all registers are read/write
and directly addressable.

The Z8036 Z-CIO Counter/Timer and
Parallel I/O element is a general-purpose
peripheral circuit, satisfying most
counter/timer and parallel I/O needs
encountered in system designs. This versatile
device contains three I/O ports and three
counter/timers. Many programmable options
tailor its configuration to specific applications.

The use of the device is simplified by making
all internal registers (command, status, and
data) readable and (except for status bits)
writable. In addition, each register is given its
own unique address so that it can be
accessed directly-no special sequential
operations are required. The Z-CIO is directly
Z-Bus compatible.

.-mf~--BUS

AD,

PA,

AD,

PA,

AD,

PA,

AD.

PA.

......... AD,
AD,

PA,

-----

PA,

AD,

PA,

ADo

PAo

~}-.

BUS TIMING { ----. AS
AND RESET

CONTROL {

INTERRUPT {

=:
~

=:

os
R/W

Z8038
Z·CIO

Gso

cs,
INT
INTACK

lEI
lEO

AD.

AD,

AD,

AD,

AD,

AD,

AD,

ADo

os

csa

Riw

CS,

GND

Ali

PBo

PAo

PB,

PA,

PB,

PA,

ps,

PA,

PB.

PA,

PB,

PA,

PB,

PA,

PB,
PClK

lEI

PA,
INTACK

iNT

lEO

+5V

PCo

PC,

PC,

PC,

PCLK+5VGND

Figure 1. Pin Functions

2014-0035, 0036

Figure 2. Pin Assignment.

217

Pin
Description

INT. Interrupt Request (output, open-drain,
achve Low). ThiS signal is pulled Low when
the Z-CIO requests an interrupt.

ADo-AD,. Z-Bus Address/Data lines
(bldlrechonal/3-state). These mulhplexed
Address/Data lmes are used for transfers
between the CPU and Z-CIO.
AS*. Address Strobe (mput, achve Low).
Addresses, INTACK, and CSo are sampled
whde AS is Low.

CSo and CSI. Chip Select 0 (mput, achve
Low) and Chip Select 1 (mput, achve High).
CSo and CSj must be Low and High, respechvely, in order to select a device. CSo is
latched by AS.
DS*. Data Strobe (mput, achve Low). DS provides hming for the transfer of data into or out
of the Z-CIO.
lEI. Interrupt Enable In (mput, achve High).
lEI IS used with lEO to form an mterrupt daisy
chain when there is more than one interruptdriven device. A High lEI mdicates that no
other higher prIOrity device has an interrupt
under servICe or is requestmg an interrupt.
lEO. Interrupt Enable Out (output, active
High). lEO is High only if IEI IS High and the
CPU IS not servicmg an interrupt from the
requeshng Z-CIO or is not requestmg an mterrupt (Interrupt Acknowledge cycle only). lEO
IS connected to the next lower priority device's
lEI mput and thus inhibits mterrupts from
lower priority devices.
* When AS and iSS are detected Low at the same hme (normally
an Iilego.l condlbon), the Z-CIO IS reset

Architecture

The Z8036 Z-CIO Counter/Timer and
Parallel I/O element (Figure 3) consists of a

INTACK. Interrupt Acknowledge (mput, active
Low). This Signal mdicates to the Z-CIO that
an Interrupt Acknowledge cycle is in progress.
INTACK is sampled while AS is Low.
PAo-PA,. Port A I/O lines (bidirectional,
3-state, or open-dram). These 81ght I/O lmes
transfer information between the Z-CIO's Port
A and external devices.

PBO-PB,. Port B I/O lines (bidirechonal,
3-state, or open-drain). These eight I/O lines
transfer mformahon between the Z-CIO's Port
B and external devices. May also be used to
provide external access to Counter/Timers
I and 2.
PCo-PC3. Port C I/O lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to prOVide handshake, WAIT, and
REQUEST lines for Ports A and B or to provide
external access to Counter/Timer 3 or access
to the Z-CIO's Port C.
PCLK. (input, TTL-compatible). This is a
peripheral clock that may be, but IS not
necessarily, the CPU clock. It is used with
hmers and REQUEST/WAIT logic.
R/W. Read/Write (input). R/W indicates that
the CPU is readmg from (High) or writing to
(Low) the Z-CIO.
Z-Bus interface, three I/O ports (two generalpurpose 8-bit ports and one special-purpose

INTERRUPT



CONTROL

LOGIC

INTERNAL BUS

PORT
A
PORT A
110

CONTROL


ADDRESSJ

Z·BUS
INTERFACE

4 .
PORT C

110

INTERNAL

CONTROL

LOGIC

PORT 8

110

Figure 3. Z-CIO Block Diagram

218

2014-001

Architecture

(Continued)

4-bit port), three l6-bit counter/timers, an
interrupt control logic block, and the internal
control logic block. An extensive number of
programmable options allow the user to tailor
the configuration to best suit the specific
application.
The two general-purpose 8-bit I/O ports
(Figure 4) are identical. except that Port B can
be specified to provide external access to
Counter/Timers I and 2. Either port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the direction
of each bit individually programmable. Each
port includes pattern-recognition logic, allowing interrupt generation when a specific pattern is detected. The pattern-recognition logic
can be programmed so the port functions like
a priority-interrupt controller. Ports A and B
can also be linked to form a 16-bit I/O port.
To control these capabilities, both ports contain 12 registers. Three of these registers, the

Input, Output, and Buffer registers, comprise
the data path registers. Two registers, the
Mode Specification and Handshake SpeCification registers, are used to define the mode of
the port and to speCify which handshake, if
any, is to be used. The reference pattern for
the pattern-recognition logic is defined via
three registers: the Pattern Polarity, Pattern
TranSition, and Pattern Mask registers. The
detailed characteristics of each bit path (for
example, the direction of data flow or whether
a path is inverting or noninverting) are programmed using the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The primary control and status bits are
grouped in a single register, the Command
and Status register, so that after the port is initially configured, only this register must be
accessed frequently. To facilitate initialization,
the port logic is designed so that registers
associated with an unrequired capability are
ignored and do not have to be programmed.

N

w
=
~

N

•

S

TO COUNTERfTlMERS 1 AND 2

(PORT B ONLY)
INTERNAL

~

INPUT
BUFFERt
INVERTERS
AND
1',
CATCHER

OUTPUT

DATA
REGISTER

PATTERN
RECOGNITION
LOGIC

PORT
1/0

INPUT
DATA
REGISTER

OUTPUT
BUFFERI
INVERTERS

PORT
CONTROL
LOGIC

TO PORT C

Figure 4. Portl A and B Block Diagram

2014-002

219

Architecture

(Continued)

numerous. Up to four port VO lines can be
dedicated as external access lines for each
counter/timer: counter input, gate input, trigger input, and counter/timer output. Three different counter/timer output duty cycles are
available: pulse, one-shot, or square-wave.
The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable. With these and other options, most
counter/timer applications are covered.
The interrupt control logic provides standard
Z-Bus interrupt capabilities. There are five
registers (Master Interrupt Control register,
three Interrupt Vector registers, and the Current Vector register) associated with the interrupt logic. In addition, the ports' Command
and Status registers and the counter/timers'
Command and Status registers include bits
associated with the interrupt logic. Each of
these registers contains three bits for interrupt
control and status: Interrupt Pending (IP),
Interrupt Under Service (IUS), and Interrupt
Enable (IE).

The function of the special-purpose 4-bit
port, Port C (Figure 5), depends upon the
roles of Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lines can be used as
VO lines or to provide external access for the
third counter/timer.
Since Port C's function is defined primarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed. These registers specify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special VO Control registers.
The three counter/timers (Figure 6) are all
identical. Each is comprised of a l6-bit downcounter, a 16-bit Time Constant register
(which holds the value loaded into the downcounter), a l6-bit Current Counter register
(used to read the contents of the downcounter), and two 8-bit registers for control
and status (the Mode Specification and the
Command and Status registers).
The capabilities of the counter/timer are

nn
I
I
TO PORT TO PORT
A
B

TO COUNTERI
TIMER 3

HANDSHAKE
AND
REQUESTIWAIT
LOGIC

rr

NTERNAL

lL
--i
f-y--

OUTPUT
DATA
REGISTER

INPUT

DATA
REGISTER

~

DATA
MULTIPLEXER

"":...

3

INPUT

-

~

-

BUFFERI
INVERTERS

,.,

AND

CATCHER
~

...

¢¢

PORT

I/O

A-

,

OUTPUT

BUFFERI
INVERTERS

¢=l

PORT

CONTROL
LOGIC

<

~NTERNAL

PORT
CONTROL LINES

"'v
Fig.... 5. Port C Block Diagram

220

2014-003

Architecture
(Continued)

INTERNAL

BUS

/'

~A
~

I~

TIME
CONSTANT

REGISTER
(MSa's)

~

r------v

I ~

CURRENT
COUNT
REGISTER
(MSa's)

~

CURRENT
COUNT
REGISTER

I-I----

16-81T
DOWN
COUNTER

k=l

TIME

CONSTANT
REGISTER
(LSS's)

-----'\

----v

CONTROL

LINES

COUNTERI
TIMER
CONTROl.
LOGIC

(LSS's)

~COUNTER

A

k=l

r------I

A

,

'-..7

3

-ul

TO PORT

Figure 6. Counter/Timer Block Diagram

Functional
Description

The following describes the functions
of the ports, pattern-recognition logic,
counter/timers, and interrupt logic.

1/0 Port Operations. Of the Z-CIO's three
I/O ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port B also
provides access for Counter/Timers I and 2. In
all configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake hnes for Ports A and B when required.
A REQUEST/WAIT line can also be provided
so that Z-CIO transfers can be synchronized
with DMAs or CPUs. Any Port C bIts not used
for handshake or REQUEST/WAIT can be used
as input or output bits (individually data direction programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any combination of bits can be set
and/or cleared while the other bits
remain undisturbed without first reading the
register.

port's Data Direction register specifies the
direction of data flow for each bit. A I
specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverting.
The value returned when reading an input
bit reflects the state of the mput just prior to
the read. A I's catcher can be inserted into the
input data path by programming a 1 to the
corresponding bit position of the port's Special
I/O Control register. When a 1 is detected at
the 1's catcher input, its output is set to a 1
until it is cleared. The l' s catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of Port C return the state
of the pin. Outputs can be speCIfied as opendrain by writing a 1 to the corresponding bIt of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
signiflcant bits are used as a write protect
mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with aI, the state of the corresponding output
bit is not changed.

Bit Port Operations. In bit port operations, the
2014·004

221

Functional
Description
(Continued)

Ports with Handshake Operation. Ports A and
B can be specified as 8-bit input, output, or
bidirectional ports with handshake. The Z-CIO
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When specified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake logic. Port C provides the
handshake lines as shown in Table 1. Any Port
C lines not used for handshake can be used as
simple I/O lines or as access lines for Counterl
Timer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
interrupt for the first byte is serviced. Normally, the Interrupt Pending (IP) bit is set and
an interrupt is generated when data is shifted
into the Input register (input port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. In bidirectional ports, IP is cleared only by command.
When the Interrupt on Two Bytes (ITB) control
bit is set to 1, interrupts are generated only
when two bytes of data are available to be read
or written. This allows a minimum of 16 bits of
information to be transferred on each interrupt. With ITB set, the IP is not automatically
cleared until the second byte of data is read or
written.
When the Single Buffer (SB) bit is set to 1,
the port acts as if it is only single-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a 1 in the Port Link Control (PLC) bit. In this mode, only Port A's
Handshake Specification and Command and
Status registers are used. Port B must be
specified as a bit port. When linked, only Port
Port AlB Configuration
Ports A and B:

BIt Ports

A has pattern-match capability. Port B's
pattern-match capability must be disabled.
Also, when the ports are linked, Port B's Data
register must be read or written before
Port A's.
When a port is specified as a port with handshake, the type of port it is (input, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port C (Table 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special I/O Control register apply only to output bits (3-state or open-drain). Inputs may not
have l's catchers; therefore, those bits in the
Special 1/0 Control register are ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the Z-CIO must
be acknowledged by the external device
before the next action can take place. Figure 7
shows timing for Interlocked Handshake. An
output port does not indicate that new data is
available until the external device indicates it
is ready for the data. Similarly, an input port
does not indicate that it is ready for new data
until the data source indicates that the previous byte of the data is no longer available,
thereby acknowledging the input port's acceptance of the last byte. This allows the Z-CIO to
interface directly to the port of a Z8 microcomputer, a UPC, an FlO, an FIFO, or to another
Z-CIO port with no external logic.
A 4-bit deskew timer can be inserted in the
Data Available (DAY) output for output ports.
As data is transferred to the Buffer register,
the deskew timer is triggered. After the
number of PCLK cycles speCified by the
deskew timer time constant plus one, DAY is

Pes

P~

PCl

PCO

BIt 110

BIt I/O

BIt 110

BIt 110

Port A: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)-

RFD or DAV

ACKIN

REQUESTIWAIT
or BIt 110

BIt 110

Port B: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake)-

REQUEST/WAIT
or BIt 110

BIt 110

RFD or DAV

ACKIN

Port A or B: Input Port (3-Wire
Handshake)

RFD (Output)

DAV (Input)

REQUEST/WAIT
or BIt 110

DAC (Output)

Port A or B: Output Port (3-Wlre
Handshake)

DAV (Output)

DAC (Input)

REQUESTIWAIT
or BIt 110

RFD (Input)

Port A or B: B,d,rechonal Port
(Interlocked or Strobed Handshake)

RFD or DAV

ACKIN

REQUESTIWAIT
or BIt 110

IN/OUT

*Both Ports A and B can be speCIfIed mput or output with Interlocked, Strobed, or Pulsed. Handshake at the same tIme If neIther
uses REQUESTIWAIT.

Table 1. Port C Bit Utilization

222

Functional
Description
(Continued)

allowed to go Low. The deskew timer therefore
guarantees that the output data is valid for a
specIfied mmimum amount of time before DA V
goes Low. Deskew timers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data is "strobed" into or out of
the port by the external logic. The falling edge
of the Acknowledge Input (ACKIN) strobes
data into or out of the port. Figure 7 shows
timing for the Strobed Handshake. In contrast
to the Interlocked Handshake, the signal
indicating the port is ready for another data
transfer operates independently of the ACKIN
input. It is up to the external logic to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wire Handshake is
designed for the situation in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to mdicate If an input port is ready
for new data or if it has accepted the present
data. In the 3-Wire Handshake (Figure 8), the
rising edge of one status line indicates that the
port is ready for data, and the rising edge of
another status line indicates that the data has
been accepted. With the 3-Wire Handshake,
the output lines of many input ports can be
bussed together with open-drain drivers; the

Pulsed Handshake. The Pulsed Handshake
(Figure 9) is designed to interface to
mechanical-type devICes that require data to
be held for long periods of time and need
relatively wide pulses to gate the data into or
out of the device. The logic is the same as the
Interlocked Handshake mode, except that an
internal counter/timer is linked to the handshake logic. If the port is specified in the input
mode, the timer is inserted in the ACKIN path.
The external ACKIN input triggers the timer
and its output is used as the Interlocked Handshake's normal acknowledge input. If the port
is an output port, the timer is placed m the
Data Available (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output is used as the actual DAV output. The
counter/timer maintams all of its normal
capabJlihes. ThIs handshake is not available to
bidirechonal ports.
OUTPUT HANDSHAKE

INPUT HANDSHAKE

DATA::X

output port knows when all the ports have
accepted the data and are ready. ThIs IS the
same handshake as is used on the IEEE-488
bus. Because this handshake reqUIres three
lines, only one port (either A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
mode. Because the port's direction can be
changed under software control, however,
bidirectional IEEE-488-type transfers can be
performed.

VALID

X\._________

DATA

NEXT BYTE

STROBED

HANDSHAKE.........r -

RFD

-

-,.---

INTERLOCKED
DATA MOVED

DATA LATCHED

TO INPUT

IN BUFFER REGISTER

REGISTER

HANDSHAKE
BUFFER REGISTER
"EMPTIED"

NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO

BUFFER REGISTER

Figure 7. Interlocked and Strobed Handshakes

OUTPUT HANDSHAKE

INPUT HANDSHAKE

DATA

=::x

X\._________

VALID

INPUT _ _ _ _ _ _- '

---I'~""\

OUTPUT

DAC
OUTPUT

NEXT BYTE

-------------'I'~--------

RPD

DAV
INPUT

"PO

DATA

DAC

'-----+---' "'~~~::~~r=:::ISTER

+-J

___

INPUT

DAV
OUTPUT

BUFFER REGISTER
"EMPTIED"

NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER

Figure 8. 3-Wlre Handshake
20]4·005, 006

223

!!oil

00

o
w
en

...o~

Functional
Description
(Continued)

REQUEST/WAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST
signal indicates when a port is ready to perform a data transfer via the Z-Bus. It is
intended for use with a DMA-type device. The
WAIT signal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake Specification register provide controls for the REQUEST/WAIT logic. Because
the extra Port C line is used, only one port can
be specified as a port with a handshake and a
REQUEST/WAIT line. The other port must be
a bit port.
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (lTB) control bit. When ITB is a, the
REQUEST line goes active as soon as the
Z-CIO is ready for a data transfer. If ITB is 1,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte is available to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only. In this
case, the REQUEST line indicates the status of
the register not being used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line is High when the Output
register is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.

Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
interrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
allowing the port to recognize patterns in all of
its configurations. The pattern can be
independently specified for each bit as 1, a,
rising edge, falling edge, or any transition.
Individual bits may be masked off. A patternmatch is defined as the simultaneous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit specifications in either of the OR or
OR-Priority Encoded Vector modes.
INPUT PORT

ACKIN'

OUTPUT PORT

Figure 9. Pulsed Handshake

224

The pattern specified in the Pattern Definition register assumes that the data path is programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the opposite of the one
specified. Output bits used in the patternmatch logic are internally sampled before the
invertlnoninvert logic.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as I/O for the counter/timers. The input
to the pattern-recognition logic follows the
value at the pins (through the invertlnonmvert
logic) in all cases except for simple inputs with
l's catchers. In this case, the output of the l's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports specified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state eXIsts. A
transition from a no-match to a match state is
not required.
The pattern-recognition logic of bit ports
operates in two basic modes: Transparent and
Latched. When the Latch on Pattern Match
(LPM) bit is set to a (Transparent mode), the
interrupt indicates that a specified pattern has
occurred, but a read of the Data register does
not necessarily indicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM = 1), the state of all the
port inputs at the time the interrupt was generated is latched m the input register and held
until IP is cleared. In all cases, the PMF indicates the state of the port at the time it is read.
If a match occurs while IP IS already set, an
error condition exists. If the Interrupt On Error
bit (IOE) is a, the match is ignored. However,
if IOE is 1, after the first IP is cleared, it is
automatically set to 1 along with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP IS cleared.
When a pattern-match is present in the
OR-Priority Encoded Vector mode, IP is set to
1. The IP cannot be cleared until a match is no
longer present. If the interrupt vector is
allowed to mclude status, the vector returned
during Interrupt Acknowledge indicates the
highest priority bit matching its speCification at
the time of the Acknowledge cycle. BIt 7 is the
hIghest priority and bIt a is the lowest. The bit
initially causmg the interrupt may not be the
one indicated by the vector If a higher prionty
bIt matches before the Acknowledge. Once the
Acknowledge cycle IS initiated, the vector is
2014-007

Functional
Description
(Continued)

frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt is serviced, the l's
catcher can be used to hold the value.
Because a no-match to match transition is not
required, the source of the interrupt must be
cleared before IP is cleared or else a second
interrupt is generated. No error detection is
performed in this mode and the Interrupt On
Error bit should be set to O.

Function

TRIGGER

r1

---1 U

PC 0

Counter Input

PB 5

PB I

PC I

Trigger Input

PB 6

PB 2

PC 2

Gate Input

PB 7

PB 3

PC 3

11 rI r1 r'J1 r1 r-1 rLJ L..J LJ L..J LJ LJ L..J

ri

~
//

LJ

GATE

1
PULSE OUTPUT

ClTa

PB 0

The flexibility of the counter/timers is
enhanced by the provision of up to four lines
per counter/timer (counter input, gate input,
trigger input, and counter/timer output) for
direct external control and status. Counter/
Timer l's external I/O lines are prOVided by
the four most significant bits of Port B.
Counter/Timer 2's are provided by the four
least significant bits of Port B. Counter/Timer
3' s external I/O lines are provided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a bit-by-bit basis
via the Counter/Timer Mode SpeCification
registers.
When external counter/timer I/O lines are to
be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lines used for counter/timer I/O
have the same characteristics as simple input
lines. They can be speCified as inverting or
noninverting; they can be read and used with
the pattern-recognition logic. They can also
include the l's catcher input.
Counter/Timers 1 and 2 can be linked internally in three different ways. Counter/Timer
l's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilities as when used separately. The
only restriction is that when Counter/Timer 1
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles available for the
timer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the counter/

Counter/Timer Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-bit down counter, a 16-bit Time
Constant register, a 16-bit Current Counter
register, an 8-bit Mode Specification register,
an 8-bit Command and Status register, and the
associated control logiC that links these
registers.
PCLK/2 OR

C/TZ

PB 4

Table 2. Counter/Timer External Acceas

Ports with Handshake Pattern-Recognition
Operation. In this mode, the handshake logic
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logic controls the Pattern
Match Flag (PMF). The data is compared with
the match pattern when it is shifted from the
Buffer register to the Input register (input port)
or when it is shifted from the Output register to
the Buffer register (output port). The patternmatch logic can override the handshake logic
in certain situations. If the port is programmed
to interrupt when two bytes of data are
available to be read or written, but the first
byte matches the speCified pattern, the
pattern-recognition logic sets IP and generates
an interrupt. While PMF is set, IP cannot be
cleared by reading or writing the data
registers. IP must be cleared by command.
The input register is not emptied while IP is
set, nor is the output register filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bit is
set, IP is set only when the data matches the
pattern. This is useful in DMA-type applications when interrupts are required only after a
block of data is transferred.

COUNTER INPUT

C/Tl

Counter/TImer Output

TC

1

TC-'

1

TC-'

1

TC-2

I· •

·1

1 ~~ 1
rI

-----_o----l

L...

ONE SHOT
~-------~~~----~
OUTPUT _ _ _oJ

SQUARE WAVE
OUTPUT
FIRST HALF

SQUARE WAVE
OUTPUT

-------------...,"~)l'------'

--------------~,,~.----.

Figure 10. Counter/Timer Waveforms
2014-008

225

Functional
Description
(Continued)

226

timer waveforms. When the Pulse mode is
specified, the output goes High for one clock
cycle, beginning when the down-counter
leaves the count of 1. In the One-Shot mode,
the output goes High when the counter/timer is
triggered and goes Low when the downcounter reaches O. When the square-wave output duty cycle is specified, the counter/timer
goes through two full sequences for each
cycle. The initial trigger causes the downcounter to be loaded and the normal countdown sequence to begin. If a I count is
detected on the down-counter's clocking edge,
the output goes High and the time constant
value is reloaded. On the clocking edge, when
both the down-counter and the output are I's,
the output is pulled back Low.
The Continuous/Single Cycle (C/SC) bit in
the Mode SpeCification register controls operation of the down-counter when it reaches terminal count. If C/SC is 0 when a terminal
count is reached, the countdown sequence
stops. If the C/SC bit is I each time the countdown counter reaches I, the next cycle causes
the time constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant
register and initiating the countdown sequence
by loading the down-counter with the time
constant value. Tho Time Constant register is
accessed as two 8-bit registers. The registers
are readable as well as writable, and the
access order is irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter is loaded in one of
three ways: by writing a I to the Trigger
Command Bit (TCB) of the Command and
Status register, on the rising edge of the external trigger input, or, for Counter/Timer 2 only,
on the rising edge of Counter/Timer I's internal output if the counters are linked via the
trigger input. The TCB is write-only, and read
always returns O.
Once the down-counter is loaded, the countdown sequence continues toward terminal
count as long as all the counter/timers' hardware and software gate inputs are High. If any
of the gate inputs goes Low (0), the countdown
halts. It resumes when all gate inputs are I
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrigger Enable Bit (REB) in the Mode
SpeCification register. If REB is 0, ret riggers
are ignored and the countdown continues normally. If REB is I, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output

is programmed in the Square-Wave mode,
retrigger causes the sequence to start over
from the initial load of the time constant.
The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the Timer mode (the External Count Enable
[ECEl bit is 0), the down-counter is clocked
internally by a signal that is half the frequency
of the PCLK input to the chip. In the Counter
mode (ECE is 1), the down-counter is
decremented on the rising edge of the counterl
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending OP) bit is set to I,
and if interrupts are enabled (IE = 1), an interrupt is generated. If a terminal count occurs
while IP is already set, an internal error flag is
set. As soon as IP is cleared, it is forced to a I
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag is set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter via the Current Count
register or by testing the Count In Progress
(CIP) status bit in the Command and Status
register. The CIP status bit is set when the
down-counter is loaded; it is reset when the
down-counter reaches O. The Current Count
register is a 16-bit register, accessible as two
8-bit registers, which mirrors the contents of
the down-counter. This register can be read
anytime. However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a I to
the Read Counter Control (RCC) bit in the
counter/timer's Command and Status register.
This freezes the value in the Current Count
register until a read of the least significant
byte is performed.

Interrupt Logic Operation. The interrupts
generated by the Z-CIO follow the Z-Bus
operahon as described more fully in the Zilog
Z-Bus Summary. The Z-CIO has five potential
sources of interrupts: the three counter/timers
and Ports A and B. The priorities of these
sources are fixed in the following order:
Counter/Timer 3, Port A, Counter/Timer 2,
Port B, and Counter/Timer 1. Since the
counter/hmers all have equal capablhties and
Ports A and B have equal capabilities, there is
no adverse impact from the relative pnorihes.
The Z-CIO mterrupt priority, relative to
other components withm the system, is determmed by an interrupt daisy chain. Two pins,
Interrupt Enable In (lEI) and Interrupt Enable
Out (IEO), provide the mput and output
necessary to implement the daisy chain. When
IEI is pulled Low by a higher priority device,

Functional
Description
(Continued)

the Z-CIO cannot request an interrupt of the
CPU. The following discussion assumes that
the IEI line is High.
Each source of interrupt in the Z-CIO contains three bits for the control and status of the
interrupt logic: an Interrupt Pending (IP)
status bit, an Interrupt Under Service (IUS)
status bit, and an Interrupt Enable (IE) control
bit. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (INT) output Low, if the
associated IE is l.
The IUS status bit is set as a result of the
Interrupt Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
time the Interrupt Acknowledge commences. It
can also be set directly by the CPU. Its
primary function is to control the interrupt
daisy chain. When set, it disables lower priority sources in the daisy chain, so that lower
priority interrupt sources do not request servicing while higher priority devices are being
serviced.
The IE bit provides the CPU with a means of
masking off individual sources of interrupts.
When IE is set to 1, an interrupt is generated
normally. When IE is set to 0, the IP bit is set
when an event occurs that would normally
require service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts within the Z-CIO to be
disabled without having to individually set
each IE to 0. If MIE is set to 0, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Chain

(DLC) bit is included to allow the CPU to
modify the system daisy chain. When the DLC
bit is set to 1, the Z-CIO's lEO is forced Low,
independent of the state of the Z-CIO or its IEI
input, and all lower priority devices' interrupts
are disabled.
As part of the Interrupt Acknowledge cycle,
the Z-CIO is capable of responding with an
8-bit interrupt vector that specifies the source
of the interrupt. The Z-CIO contains three vector registers: one for Port A, one for Port B,
and one shared by the three counter/timers.
The vector output is inhibited by setting the No
Vector (NV) control bit to 1. The vector output
can be modified to include status information
to pinpoint more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = 1, reading the base vector register
always includes status, independent of the
state of the VIS bit. In this way, all the information obtained by the vector, including
status, can be obtained with one additional
instruction when VIS is set to 0. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified. Another register, the Current Vector
register, allows use of the Z-CIO in a polled
environment. When read, the data returned is
the same as the interrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector register is read-only.

Programming

Programming the Z-CIO entails loading control registers with bits to implement the desired
operation. Individual enable bits are provided
for the various major blocks so that erroneous
operations do not occur while the part is being
initialized. Before the ports are enabled, IPs
cannot be set, REQUEST and WAIT cannot be
asserted, and all outputs remain high-impedance. The handshake lines are ignored until
Port C is enabled. The counter/timers cannot
be triggered until their enable bits are set.
The Z-CIO is reset by forcing AS and DS
Low simultaneously or by writing a 1 to the
Reset bit. Once reset, the only thing that can
be done is to read and write the Reset bit.
Writes to all other bits are ignored and all
reads return Os. In this state, all control bits
are forced to 0. Only after clearing the Reset

bit (by writing to it) can the other command
bits be programmed.
Register Addressing. The Z-CIO allows two
schemes for register addressing. Both schemes
use only six of the eight bits of the address/
data bus. The scheme used is determined by
the Right Justify Address (RJA) bit in the
Master Interrupt Control register. When RJA
equals 0, address bus bits and 7 are ignored,
and bits 1 through 6 are decoded for the
register address (110 from ADl). When RJA
equals 1, bits through 5 are decoded for the
register address (110 from ADo). In the following register descriptions, only six bits are
shown for addresses and represent address/
data bus bits through 5 or 1 through 6,
depending on the state of the RJA bit.

°

°

°

227

Registers

Master Interrupt Control Register
Address: 000000
(Read/Write)

MASTER
INTERRUPT
ENABLE
(M1E)

~~i

DISABLE LOWER CHAIN (OLe)
NO VECTOR (NV)

Master Configuration Control Register
Address: 000001
(Read/Write)

PORTB~JJ

~RESET

~

PORT A VECTOR INCLUDES
STATUS (PA VIS)

1

L

ENABLE (PSE)

RIGHT JUSTIFIED ADDRESSES
O=SHIFT LEFT (Ao from ADd

[

COUNTERfTlMER 1

=RIGHT JUSTIFY (Ao from ADo)

ENABLE (eT1E)

COUNTERfTlMERS VECTOR
INCLUDES STATUS (CT VIS)

COUNTERfTlMER 2
ENABLE (eT2E)

PORT B VECTOR INCLUDES
STATUS (P8 VIS)

PORT C AND CaUNTERI
TIMER 3 ENABLE
(PCE AND eT3E)

COUNTERITIMER LINK
CONTROLS (LC)

LC1

o
o
1
1

LCD
0
1
0
1

COUNT

CIT l's
CIT l's
CIT l's

INDEPENDENT
GATES CIT 2
TRIGGERS CIT 2
IS CIT 2's

COUNT INPUT
PORT A ENABLE (PAE)
PORT LINK CONTROL (PLC)
O=PORTS A AND B OPERATE INDEPENDENTLY
1 = PORTS A AND B ARE LINKED

Figure ll. Master Control Registers

Port Handshake Specification Registers
Addresses: 100001 Port A
101001 Port B
(Reael/Write)

Port Mode Specification Registers
Addresses: 100000 Port A
101000 Port B
(Read/Write)

PORTTYPE~

SELECTS (PTS)
PTS1 PT80.

o
o
1
1

0

BIT PORT

1
0
1

INPUT PORT
OUTPUT PORT
BIDIRECTIONAL
PORT

INTERRUPT ON TWO
BYTES (ITB)

L

LATCH ON PATTERN MATCH (LPM)
(BIT MODE)
DESKEW TIMER ENABLE (OTE)
(HANDSHAKE MODES)

HANDSHAKE TYPE SPECIFICATION
BITS (HST)

!!~ HSTQ
o
0 INTERLOCKED HANDSHAKE
o 1 STROBED HANDSHAKE

PATTERN MODE SPECIFICATION
BITS (PMS)

1
1

PMS1 PMSO

- - --a1

o
1

SINGLE BUFFERED
MODE (SB)

J

I~I~I~I~I~I~I~I~I

0
1

-c

DESKEW TIME SPECIFICATION
BITS

~~~~~~I~~~ ~~~SC~NSTANT

LSS IS FORceD 1

PULSED HANDSHAKE
THREE·WIRE HANDSHAKE

DISABLE PATTERN MATCH
"AND"MODE
"OR" MODE
"OR·PRIORITY ENCODED

REaUEST/WAIT SPECIFICATION BITS

RWS2

VeCTOR" MODE

RWS1

(AWS)
RWSO FUNCTION
- - REQUEST/WAIT DISABLED
OUTPUT WArT
INPUT WAIT
SPECIAL REQUEST
OUTPUT REQUEST
INPUT REQUEST

' - - - - INTERRUPT ON MATCH ONLY (IMO)

Port Command and Status Registers
Addresses: 001000 Port A
001001 Port B
(Reael/Partial Write)

'E

I~I~I~I~(~I~I~I~I

L

INTERRUPT UNDER
SERVICE (IUS)

L

INTERRUPT ENABLE (IE)
INTERRUPT PENDING (IP)

NULL CODE

SET IUS
CLEAR IUS
SETIP

PATTERN MATCH FLAG (PMF)
(READ ONLy)

INPUT REGISTER FUll (IRF)
(READ ONLY)

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING CODE:

CLEAR IP & IUS

INTERRUPT ON ERROR (IOE)

•••
0

0

OUTPUT REGISTER EMPTY (ORE)
(READ ONLy)

1

010

0

1

1

100

CLEAR IP

1

0

1

SET IE

1

1

0

CLEAR IE

1

1

1

INTERRUPT ERROR (ERR) - - - - - - - '
(READ ONLY)

Figure 12. Port Specification Registers

228

20 14~009, 010

Registers
(Continued)

Data Direction Registers
Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(Read/Write)

Data Path Polarity Registers
Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(Read/WrIte)

' - - - - - DATA DIRECTION (DO)

" - - - - DATA PATH POLARITY (DPP)

0= OUTPUT BIT

0= NON·INVERTING
1 = INVERTING

1 =INPUT BIT

Special 1/0 Control Registers
Addresses: 100100 Port A
101100 Port B
000111 Port C (4 LSBs only)
(Read/Write)

" - - - - SPECIAL INPUT/OUTPUT (SID)

0= NORMAL INPUT OR OUTPUT
1 =OUTPUT WITH OPEN DRAIN OR

N

CO

INPUT WITH 1'5 CATCHER

S
en

Figure 13. Bit Path Definition Registers

~o

Port C Data Register
Address: 001111
(Read/Write)

Port Data Registers
Addresses: 001101 Port A
001110 Port B
(Read/Write)

4 MSBs
O=WR!T1NQ OF CORRESPONDING LSB ENABLED
1 "'WRITING OF CORRESPONDING LSB INHIBITED
(READ RETURNS 1)

Figure 14. Port Data Registers

Pattern Polarity Registers (PP)
Addresses: 100101 Port A
101101 Port B
(Read/Write)
Pattern Transition Registers (PT)
Addresses: 100110 Port A
101110 Port B
(Read/Write)

~ ~

f!"

PAITERN SPECIFICATION

BIT MASKED OFF
ANY TRANSITION

ZERO
ONE
ONE TO-ZERO TRANSITION (\)

ZERo-rO-ONE TRANSITION (I)

Pattern Mask Registers (PM)
Addresses: 100111 Port A
101111 Port B
(Read/Write)
Figure 15. Pattern Definition Registers

2014-011,012,013

229

Registers
(Continued)

CounterlTimer Command and Status Registers
Addresses: 001010 Counter/Timer 1
001011 Counter/Timer 2
001100 Counter/Timer 3
(Read/Partial Write)

,.-"""-~... "~~ I
---.LJ
I

I

INTERRUPT ENABLE (IE}

I

INTERRUPT PENDING (lP)

I

I

NULL CODE

0

0

~~

TRIGGER COMMAND BIT (TeB)
(WRITE ONLY· READ RETURNS 0)

GATE COMMAND BIT (GeB)

READ COUNTER CONTROL (RCC)

IUS, IE, AND IP ARE WRlnEN USING

(READ/SET ONLY-

THE FOLLOWING CODE:

& IUS

0

0

SET IUS

0

1

CLEAR IUS

0

1

SETIP

1

0

CLEAR IP

1

0

CLEAR IP

COUNT IN PROGRESS (CIP)
(READ ONLy)

SET IE

CLEARED BY READING CCR LS&)

0

1

110

CLEAR IE

1

1

1

INTERRUPT ERROR (ERR)
(READ ONLy)

Counter/Timer Mode Specification Registers
Addresses: 011100 Counter/Timer 1
011101 Counter/Timer 2
01111 0 Counter/Timer 3
(Read/Write)

CONTINUOUS SJ!!.
GLE CYCLE (e/SC)

JJ~

EXTERNAL OUTPUT
ENABLE (EOE)
EXTERNAL COUNT
ENABLE (EeE)

EXTERNAL TRIGGER
ENABLE (E1E)

L
[

OUTPUT DUTY CYCLE
SELECTS (DeS)
DCS1DCSO

- 0 ( ) PULSE OUTPUT

o

1

ONE·SHOT OUTPUT

1
1

0
1

SQUARE·WAVE OUTPUT
DO NOT SPECIFY

RETRIGGER ENABLE BIT (REB)
EXTERNAL GATE ENABLE (EGE)

Counter/Timer Current Count Registers
Addresses: 010000 Counter/Timer l's MSB
010001 Counter/Timer I's LSB
010010 Counter/Timer 2's MSB
0100 II Counter/Timer 2' s LSB
010100 Counter/Timer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)

MOST - - - - - - '
SIGNIFICANT
BYTE

L-_ _ _

LEAST
SIGNIFICANT

BYTE

Counter/Timer Time Constant Registers
Addresses: 010110 Counter/Timer l's MSB
010111 Counter/Timer I'. LSB
011000 Counter/Timer 2's MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011011 Counter/Timer 3's LSB
(Read/Write)

MOST - - - - - - '
SIGNIFICANT
BYTE

L-_ _ _

Figure 16. Center/Timer Registers

230

LEAST
SIGNIFICANT

BYTE

Registers

Interrupt Vector Register

(Continued)

Addresses: 000010 Port A
000011 Port B
000100 Counter/Timers
(ReadlWrite)

Current Vector Register

Address: 011111
(Read Only)

' - - - - - INTERRUPT YECTOR lASED
ON HIGHEST PRIORITY
UNMASKED IP.

IF NO INTERRUPT PENDING

L-_ _ _ INTERRUPT VECTOR

ALL 1'. OUTPUT

PORT VECTOR STATUS
PRIORITY ENCODED YECTOR MODE

~

x

~

x

~

x

NUMBER OF HIGHEST PRIORITY BIT
WITH A MATCH

ALL OTHER MODES:

Da D:z

D1

ORE i'iF 'MF
o

0

0

NORMAL
ERROR

COUNTERITIMER STATUS

D2 D1

"0 "0

ctrs

1
0
1

CIT 2

o
1
1

CIT 1
ERROR

Figure 17. Interrupt Vector Registers

Register

Address
Summary

Address'
000000
000001
000010
000011
000100
000101
000110
000111

Address'
001000
001001
001010
001011
001100
001101
001110
001111

Address'
010000
010001
010010
010011
010100
010101
010110
01O1ll
011000
011001
011010
011011
011100
011101
011110
011111

Main Control Registers
Reg.ster Name
Master Interrupt Control
Master Conhgurallon Control
Port A'. Interrupt Vector
Port B' s Interrupt Vector
CounterlT.mer's Interrupt Vector
Port C's Data Path Polaflty
Port C's Data DlfeclIon
Port C's SpecIal I/O Control
Most Often Accessed Registers
ReglSter Name
Port A's Command and Status
Port B's Command and Statu.
Counter/TImer I'. Command and Status
CounterlTlmer 2's Command and Status
Counter/TImer 3'. Command and Status
Port A's Data
Port B's Data
Port C's Data

Address'
100000
100001
100010
100011
100100
100101
100110
loolll

Address'
101000
101001
101010
101011
101100
101101
101110
101111

Port A Specification Registers
Reg.ster Name
Port A's Mode SpeclilCalIon
Port A's Handshake SpeClhcalIon
Port A'. Data Path Polaflty
Port A's Data DlfeclIon
Port A's SpeCIal I/O Control
Port A's Pattern Poiaflty
Port A's Pattern TransllIon
Port A's Pljttern Mask
Port B Specification Registers
Register Name
Port B'. Mode SpeClhcalIon
Port B'. Handshake SpeclilCalIon
Port B's Data Path Polaflty
Port B's Data Dlfeclion
Port B's SpeCIal I/O Control
Port B's Pattern Polaflty
Port B's Pattern TransllIon
Port B's Pattern Mask

Counter/Timer Related Registers
Reg.ster Name
CounterlTlmer I's Current Count-MSBs
Counter/TImer I's Current Count-LSBs
CounterlTlmer 2's Current Count-MSBs
Counter/TImer 2's Current Count-LSBs
CounterlTlmer 3's Current Count-MSBs
CounterlTlmer 3's Current Count-LSB.
CounterlTlmer 1'. TIme Constant-MSBs
CounterlTlmer I's TIme Constant-LSBs
Counter/TImer 2'. TIme Constant-MSBs
CounterlTlmer 2's TIme Constant-LSB.
Counter/TImer 3's TIme Constant-MSBs
Counter/TImer 3's TIme Constant-LSBs
Counter/TImer I's Mode SpeClhcalIon
Counter/TImer 2'. Mode SpeClhcalIon
Counter/TImer 3'. Mode SpeClhcalIon
Current Vector

'When RJA = 0, AO from AD1, when RIA = 1, AO from ADO

2014-015

231

Timing

Read Cycle, The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSo and CSl). Six bits of the least
significant byte of the ,address are latched
within the Z-CIO and used to specify a Z-CIO
register. The data from the register specified is
strobed onto the address/data bus when the
CPU issues a Data Strobe (OS). If the register
indicated by the address does not exist, the
Z-CIO remains high-impedance.

Write Cycle, The CPU places an address on
the address/data bus. The more significant bits
and status information are combined and
decoded by external logic to provide two Chip
Selects (CSo and CSl). Six bits of the least
Significant byte of the address are latched
within the Z-CIO and used to specify a Z-CIO
register. The CPU places the data on the
address/data bus and strobes it into the Z-CIO
register by issuing a Data Strobe (OS).

ca, _ _--J

c=
r--

R/W~
iii
ADo-AD7

READ DATA

ADo-AD7

\

~

Figure 19. Write Cycle TlmlDg

Figure 18. Read Cycle Timing

Interrupt Acknowledge Cycle, When one of
the IP bits in the Z-CIO goes High and interrupts are enabled, the Z-CIO pulls its INT
output line Low, requesting an interrupt. The
CPU responds with an Interrupt Acknowledge
cycle. When INTACK goes Low with IP set, the
Z-CIO pulls its Interrupt Enable Out (lEO)
~

C.

WRITE DATA

Low, disabling all lower priority devices on the
daisy chain. The CPU reads the Z-CIO interrupt vector by issuing a Low OS, thereby
strobing the interrupt vector onto the address/
data bus. The IUS that corresponds to the IP is
also set, which causes lEO to remain Low.

__________________--J/

lEI

1110

ADO-AD.

\'------\'--_.....J1
-J{oGjNo.iro)-----------<
'INTACK

IS

decoded from 28000 status

Figure 20. Interrupt Acknowledge Timing

232

2014-016.017.018

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to +7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C

Standard
Test
Conditions

The characterisllcs below apply for the
followmg standard test condItions, unless
otherWIse noted. All voltages are referenced to
GND. Poslllve current flows mto the referenced pin. Standard condItions are as follows:

Stresses greater than those hsted under Absolute Maxl+
mum Ratmgs may cause permanent damage to the deVIce.
ThIs IS a stress ratmg only; operatIon of the devIce at any
condlhon above those mdlCated In the operatIonal sechons
of these speclhcahons IS not Impbed. Exposure to absolute
maXImum ratmg condItIons for extended perIods may affect
deVIce rehablhty.

• +4.75 V

:5

Vee

:5

+5.25 V

• GND = 0 V
• TA as speclhed m Ordermg Informahon
All ac parameters assume a load capacitance
of 50 pF max.

+5V

+5V
22K

FROM OUTPUT
UNDER TEST

dr

N

~

22K

W

50 PF

Figure 21. Standard Test Load
DC
Characteristics

Symbol

Parameter

'"n•
N

....o

Figure 22. Open-Drain Test Load
Min

Max

Unit

Vee+ 0.3
0.8

V

VIH
VIL

Input HIgh Voltage

2.0

Input Low Voltage

-0.3

VOH

Output HIgh Voltage

VOL

Output Low Voltage

IlL

2.4

Condition

V
V

0.4

V

Input Leakage

0.5
± 10.0

Ji.A

IOL

Output Leakage

± 10.0

Ji.A

Icc

Vee Supply Current

200

rnA

V

IOH = -250 Ji.A
IOL~ +2.0 rnA
IOL ~ +3.2 rnA
0.4 s VIN S +2.4 V
0.4 s VOUT S +2.4 V

Vee:::: 5 V ± 5% unless otherWIse speclbed, over speclhed temperature range

Capacitance

Symbol

Parameter

Min

Max

Unit

C IN
C OUT

Input CapacItance

10

pF

Output CapacItance

15

CliO

Bldlrechonal CapacItance

20

pF
pF

Test Condition
Unmeasured Pms
Returned to Ground

f = 1 MHz, over speclhed temperature range

8085-0209, 0001

233

CPU

Interface
Timing

Ai

NW

-------H~r-~~----------~~-----------

READ _ _ _ _.j.j...J

NW

++__~~+_------+_~-------

WRrrE _ _ _ _

ADo-AD.

CIO

WRITE

CIO
READ

Interrupt
Timing

PATTIIRN.rrPOM
MATCH

INPUTtS)

~

~

_
__
_ _~_ _ _ _ _ _ _ _ _ _ _ _ ___
PATTERN
MATCHES

•

@)-____~.'

ACKIN
NOTE 4

COUNTIR
INPUT _ _ _ _ _.1

"

PCL!(

Ai

Interrupt
Acknowledge
Timing

AOo-AD.

Ai

I.
1m

234

2014-019, 020, 021

No.

Symbol

Min

Parameter

TwAS
AS Low Width
TsA(AS)
Address to AS I Setup Time
ThA(AS)
Address to AS I Hold TIme
3
4 -TsA(DS)---Address to DS ! Setup TIme
TsCSO(AS)
5
CSo to AS I Setup TIme
ThCSO(AS)
CSo to AS I Hold TIme
6
TdAS(DS)
AS I to DS ! Delay
7
8 - TsCSI(DS)-- CS 1 to DS ! Setup TIme
TsRWR(DS)
RlW (Read) to DS ! Setup T,me
9
TsRWW(DS)
R/W (Wnte) to OS ! Setup TIme
10
II
TwDS
DS Low Width
12-TsDW(DSf)--Wnte Data to DS ! Setup Time
TdDS(DRV)
OS (Read) ! to Address Data Bus Driven
13
TdDSf(DR)
DS ! to Read Data Vahd Delay
14
ThDW(DS)
15
Write Data to DS I Hold TIme
16-TdDSr(DR)--DS I to Read Data Not Vahd Delay
TdDS(DRz)
DS I to Read Data Float Delay
17
ThRW(DS)
R!W to DS I Hold TIme
18
ThCSI(DS)
CS 1 to DS I Hold TIme
19
TdDS(AS)
DS I to AS ! Delay
20
Vahd Access Recovery TIme
21
Trc

4 MHz
Max

70
30
50
130
0
60
60
100
100
0
390
30
0

2

30
0

4

2000

1-

N

00
C

20
0

55
55
50
1000

W

~

45
40
40
25
650

4

2

3

4

6
4,6
66

0
250
350

0
250
250
250

390

250
250
5
100---570
70

100
100
600
S

5
180

350
150

N

...
n•
0

I

TsIA(AS)
INTACK to AS I Setup TIme
ThIA(AS)
INTACK to AS I Hold TIme
TsAS(DSA)
AS I to DS (Acknowledge) ! Setup TIme
TdDSA(DR) - - DS (Acknowledge) ! to Read Data Valid Delay
TwDSA
DS (Acknowledge) Low WIdth
31
32
TdAS(lEO)
AS t to lEO! Delay (IN TACK Cycle)
33- TdlEI(lEO)--lEI to lEO Delay
TsIEl(DSA)
34
lEO to OS (Acknowledge) ! Setup TIme
ThIEI(DSA)
lEI to DS (Acknowledge) I Hold TIme
35
TdDSA(INT)
36
DS (Acknowledge) ! to INT I Delay

Float delay IS measured to the hme when the output has
changed 0.5 V from steady state with mmlmum ae load and
maximum de load
ThIS IS the delay from DS t of one CIO access to DS I of
another CIa access
The delay IS from DAV I for 3-Wlre Input Handshake The
delay IS fro.!!LDAC r for 3-Wlre Output Handshake One
additional AS cycle IS reqUlred for ports 10 the S10gle Buffered mode

Notes*t

180

70

27
28
29
30 -

2.

50
10
30
100
0
40
40
80
80
0
250
20
0

250

TdPM(INT)
22
Pattern Match to INT Delay (BIt Port)
TdACK(INT)
ACKIN to INT Delay (Port wIth Handshake)
23
24- TdCl(lNT)-- Counter Input to INT Delay (Counter Mode)
TdPC(INT)
PCLK to INT Delay (Timer Mode)
25
TdAS(INT)
AS to INT Delay
26

NOTES:
1. Parameter does not apply to Interrupt Acknowledge transachons.

2000

6 MHz
Min
Max

5
600

The parameters for the devICes many parhcular daISY

cham must meet the followmg constramt the delay from
AS t to DS l must be greater than the sum of TdAS(lEO)
for the hIghest pnonty peripheral, TsIEI(DSA) for the
lowest prIOrIty peripheral, and TdIEI(lEO) for each
penpheral separatmg them m the cham
6 Umts equal to AS cycle + ns
.. Tlm10gs are prehmmary and subject to change.
t Umts m nanoseconds(ns), except as noted

235

Strobed
Handshake

DATA

,NPUT

ACKIN

MPD

DATA

O"TPUT

iCKiii

DAV

Interlocked
Handshake

DATA

.NPUT

ACKIN

MFD

DATA

OU1'PUT

ACKIN

DAV

3-Wlre
Handshake

DATA

DAV
INPUT

INPUT
MFD
OUTPUT

DAC
OUTPUT

DATA

DAC
INPUT

OUTPUT
MI'D
INPUT

DAV
OUTPUT

236

2014·022, 023, 024

No.

Symbol

Parameter

TsDl(ACK)
ThDl(ACK)

Data Input to ACKIN ( Setup Time
Data Input to ACKIN ( Hold Time - Strobed
Handshake
TdACKf(RFD)
ACKIN ( to RFD ( Delay
3
4 - TwACKI--- ACKIN Low Width - Strobed Handshake
ACKIN High Width - Strobed Handshake
5
TwACKh

Min

4 MHz
Max

6 MHz
Max

Min

0

0

0

0

RFD I to ACKIN ( Delay
TdRFDr(ACK)
0
6
TsDO(DAV)
Data Out to DAV ( Setup TIme
7
25
TdDAVf(ACK) DAV ( to ACKIN ( Delay
8
0
9-ThDO(ACK)-- Data Out to ACKIN ( Hold Time
TdACK(DAV)
ACKIN ( to DAV I Delay
I
10
ThDI(RFD)
Data Input to RFD ( Hold Time - Interlocked
II
0
Handshake
TdRFDf(ACK)
12
RFD ( to ACKIN I Delay - Interlocked Handshake
0
13-TdACKr(RFD)- ACKIN I (DAV I ) to RFD I Delay - Interlocked--O
and 3-Wlre Handshake
TdDAVr(ACK) DAV I to ACKIN I (RFD I ) - Interlocked and
14
0
3-Wire Handshake
TdACK(DAV)
ACKIN I (RFD I )to DAV ( Delay - Interlocked and
15
0
3-Wire Handshake
16-TdDAVIf(DAC)- DAV ( to DAC I Delay - Input 3-WIre Handshake - - 0
ThDl(DAC)
Data Input to DAC I Hold Time - 3-Wlre
17
0
Handshake
18
TdDACOr(DAV) DAC I to DAV t Delay - Input 3-Wire Handshake
0
TdDAVIr(DAC) DAV I to DAC ( Delay - Input 3-Wire Handshake
19
0
20-TdDAVOf(DAC)-DAV ( to DAC I Delay - Output 3-Wire Handshake-O
21
ThDO(DAC)
Data Output to DAC I Hold Time - 3-Wlre
I
Handshake
TdDACIr(DAV) DAC t to DAV t Delay - Output 3-Wire Handshake
22
TdDAVOr(DAC) DAV t to DAC ( Delay - Output 3-Wire Handshake
23
0

0
20
0

2

Notes*t

2I
0

2

0
0

N

=
W
~

0

N

...C"•

0
0
0
0
0
0
2
2
0

NOTES:

1. ThIS hroe can be extended through the use of the deskew
Umts equal to

* Tlmmgs are prehmmary and subject to

change. All hmmg

references assume 2.0 V for a loglc "}" and 0.8 V for a

tImers.

2

AS cycle.

lOgIC

"0".

i Umts m nanoseconds (ns), except as noted.

237

Counter/
Timer
Timing

PCLK

PCLKI2
INTERNAL

_ _ _- - J

COUNTER

INPUT

TRIGGER
INPUT

GATE
INPUT

COUNTER
OUTPUT

4 MHz
No.

Symbol

Parameter

Min

Max

6MHz
Min
Max

I
2

TcPC
TwPCh

PCLK Cycle TIme
PCLK HIgh WIdth

250
105

4000
2000

165
70

4000
2000

3
4

TwPCI

PCLK Low Width

105

2000

70

2000

TIPC
5
TrPC
6-TcCI
7
TClh

PCLK Fall TIme
PCLK Rise Time

10

20
20

Counter Input Cycle TIme
Counter Input HIgh Width

500
230

NoIes*t

15
330
150

8

Counter Input Low WIdth
TwCIl
230
150
Counter Input Fall Time
9
TIC I
20
15
10
TrCI
Counter Input RIse Time
20
15
ll-TsTI(PC)---Trlgger Input to PCLK ! Setup TIme - - - - - - - - - - - - - - - - - - (TImer Mode)
TsTI(CI)
Trigger Input to Counter Input! Setup
12
TIme (Counter Mode)
13
TwTI
Trigger Input Pulse WIdth (HIgh or Low)
14-TsGI(PC)---Gate Input to PCLK ! Setup T l m e - - - - - - - - - - - - - - - - - - - (TImer Mode)
TsGI(CI)
15
Gate Input to Counter Input! Setup
TIme (Counter Mode)
16
ThGI(PC)
Gate Input to PCLK ! Hold TIme (TImer
Mode)
17-ThGI(CI) - - - Gate Input to Counter Input! Hold - - - - - - - - - - - - - - - - - - - Time (Counter Mode)
18
TdPC(CO)
PCLK to Counter Output Delay (TImer
Mode)
TdCI(CO)
19
Counter Input to Counter Output Delay
(Counter Mode)
NOTES
1 PCLK

IS

only used wIth the counter/timers (m Timer mode), the

deskew hmers, and the REQUESTIWAIT logiC If these
hons are not used, the PCLK mput can be held low

func~

These parameters must be met to guarantee that trigger or gate

238

2-2

2-2
2
2--

are valId for the next counter/hmer cycle.
* Tlmmgs are prelIminary and subject to change. All hmmg refer-

ences assume 2 a v for a logic" 1" and 0 8 V for a logIc "0".
t Units In nanoseconds (ns)

2014·025

REQUEST/

WAIT
Timing

4 MHz
No.

2
3
4
5
6

Symbol

Parameter

TdDS(REQ)

DS I to REQ I Delay

TdDS(WAIT)

DS I to WAIT I Delay
PCLK I to REQ I Delay

TclPC(REQ)
TclPC(WAIT)
TdACK(REQ)
TdACK(WAIT)

Min

Max

6 MHz
Min

Max

PCLK I to WAIT I Delay
ACKIN I to REQ I Delay
ACKIN I to WAIT I Delay

NOTES:
I. The Delay IS from DAV j for the 3-W,re Input Handshake The
delay IS from DAC 1 for the 3-W,re Output Handshake.
2. Umts equal to AS cycles + PCL!:: cycles + ns.

Notes"t

1,2
3
3 Umts equal to PCLK cycles + ns.
* Timmgs are prelInunary and subject to change. All tImmg references assume 2.0 V for a logIC "1" and 0.8 V for a logIC "0".

t Umts In nanoseconds (ns),

except as noted.

Reset

Timing

-

r

INTERNAL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

4 MHz
No.

2
3

Symbol

Parameter

Min

TdDSQ(AS)
TdASQ(DS)

Delay from DS I to AS I for No Reset
Delay from AS I to DS I for No Reset

TwRES

Minimum Width of AS and DS both Low for Reset

40
50
250

NOTES
1 Internal circuitry allows for the reset provided by the Z8

held Low whIle .AS pulses) to be sufhclent

2014-026, 027

(00

Max

6 MHz
Min

Max

Notes"t

15
30
170

* TImmgs are prelImmary and subject to change. All hmmg references assume 2.0 V for a 10g1C "1" and 8 V for a 10glC "0".

t Umts In nanoseconds (ns)

a

239

I
i

Miscellaneous
Port
Timing

:r=iL

allY INPUT

------~
1'. CATCHER
INPUT
PATTIIAN
MATCH
INPUT(S)

~~---------------

\~~_________

------~I

________~-J~~~--------:.~

' . k
X=

DATA TO BE - - - - - - ' " "
LATCHED TO
PATTilIIN MATCH _ _ _ _ _ _- '

No.

2
3
4
5
6

------_ _ _ _ _ __

Parameter

Trl
TfI
Twl's

Any Input RIse TIme
Any Input Fall TIme
I's Catcher HIgh WIdth
250
750
Pattern Match Input Vahd (BIt Port)
Data Latched on Pattern Match Setup TIme (BIt Port)
0
Data Latched on Pattern Match Hold TIme (BIt Port) 1000

TwPM
TsPMD
ThPMD

Min

4 MHz
Max

Symbol

6 MHz
Min
Max

Notes*t

100

100
100

100
170
500

o
650

NOTES
1 If the mput

IS

programmed Invertmg, a Low"gomg pulse of the

Ordering
Information

Product
Number

• TImmgs are prehmmary and subJect to change. All hmmg refer-

ences assume 2.0 V for a logIC "1" and

same wIdth wlll be detected

r Umts In nanoseconds (ns)

Package/
Speed
Temp

Description

Product
Number

Package/
Speed
Temp

a8 V for a logIc "0",
Description

CE

4.0 MHz

2-CIO (40-pm)

ZS036A

CE

6.0 MHz

2-CIO (40-pm)

6.0 MHz
6.0 MHz

Same as above
Same as above

28036A
28036A

CM
CMB

6.0 MHz

28036

CM
CMB

6.0 MHz

Same as above
Same as above

28036

CS

4.0 MHz

Same as above

ZS036A

CS

6.0 MHz

Same as above

28036

DE

4.0 MHz

Same as above

28036A

DE

6.0 MHz

Same as above

ZS036

DS

4.0 MHz

Same as above

ZS036A

DS

6.0 MHz

Same as above

28036
28036

PE
PS

4.0 MHz
4.0 MHz

Same as above
Same as above

ZS036A
ZS036A

PE
PS

6.0 MHz
6.0 MHz

Same as above

ZS036
28036

NOTES C = CeramlC, D = Cercilp, P

= Plashc,

E

=

-40°C to +85°C, MB

=

Same as above

-55°C to 125°C wIth MIL-STD-SS3 wIth Class B processmg,

S = O°C to +70°C

240

2014-028

00-2014-A

Z8038 Z8000™
Z-FIO FIFO Input!
Output Interface Unit

~
Zilog

Product
Specification

June 1982

Features

• 128-byte FIFO buffer provides asynchronous
bidirectional CPU/CPU or CPU/peripheral
interface, expandable to any width in byte
increments by use of multiple FIOs.
• Interlocked 2-Wire or 3-Wire Handshake
logic port mode; Z-BUS or non-Z-BUS
interface.
• Pattern-recognition logic stops DMA
transfers and/or interrupts CPU; preset byte
count can initiate variable-length DMA
transfers.

General
Description

The Z8038 FlO provides an asynchronous
128-byte FIFO buffer between two CPUs or
between a CPU and a peripheral device. This
buffer interface expands to a 16-bit or wider
data path and expands in depth to add as
many Z8060 FIFOs (and an additional FlO) as
are needed.
The FlO manages data transfers by assuming
Z-BUS, non-Z-BUS microprocessor (a generalized microprocessor interface), Interlocked

• Seven sources of vectored/nonvectored
interrupt which include pattern-match,
byte count, empty or full buffer status;
a dedicated "mailbox" register with
interrupt capability provides CPU/CPU
communication.
• REQUEST/WAIT lines control high-speed
data transfers.
• All functions are software controlled via
directly addressable read/write registers.

2-Wire Handshake, and 3-Wire Handshake
operating modes. These modes interface
dissimilar CPUs or CPUs and peripherals
running under differing speeds or protocols,
allowing asynchronous data transactions and
improving I/O overhead by as much as two
orders of magnitude. Figures I and 2 show
how the signals controlling these operating
modes are mapped to the FlO pins.

QJ
0,

0,

0,

0,

0,
0,
0,

0,

_M,

0,

_M,
+5 V

0,

GND

M,

GND

Figure 1. Pin Functions

2020-096, 097

0,

M,

Figure 3. flO Block Diagram

241

General
Description
(Continued)

The FlO supports the Z-BUS interrupt protocols, generating seven sources of interrupts
upon any of the following events: a write to a
message register, change in data direction,
pattern match, status match, over/underflow
error, buffer full and buffer empty status. Each
interrupt source can be enabled or disabled,
and can also place an interrupt vector on the
port address/data lines.
The data transfer logic of the FlO has been

specially designed to work with DMA (Direct
Memory Access) devices for high-speed
transfers. It provides for data transfers to or
from memory each machine cycle, while the
DMA device generates memory address and
control signals. The FlO also supports the
variably sized block length, improving system
throughput when multiple variable length
messages are transferred amongst several
sources.

CPU
INTERPACE
OR
110 PORT

CPU
INTERPACE

DATA
BUS

DATA
BUS

PORT 1 SIDE

Functional
Description

PORT 2 SIDE

Operating Modes, Ports I and 2 operate in
any of twelve combinations of operating
modes, listed in Table 2. Port I functions in
either the Z-BUS or non-Z-BUS microprocessor
modes, while Port 2 functions in Z-BUS, nonZ-BUS, Interlocked 2-Wire Handshake, and
3-Wire Handshake modes. Table I describes
the signals and their corresponding pins in
each of these modes.
Control
Signal
Pins

Z-BUS
Low Byte

Z-BUS
High Byte

[K]
[!]
@]

REQIWT
DMASTB
DS

REQIWT
DMASTB

[pJ

R!W

W
W

CS
AS
INTACK
lEO
lEI
INT

@]
[ill
[!]
[!]

55
RIW
CS
AS
Aa
Al
A2
A3

The pin diagrams of the FlO are identical,
except for two pins on the Port I side, which
select that port's operating mode. Port 2's
operating mode is programmed by two bits in
Port I's Control register O. Table 2 describes
the combinations of operating modes; Table 3
describes the control signals mapped to pins
A-J in the five possible operating modes.

Non-Z-BUS

REQIWT
DACK
RD
WR
CE
C/D

INTACK
lEO
lEI
INT

Interlocked
HS Port·

3-Wlre
HS Port·

RFD/DAV
ACKIN
FULL
EMPTY
CLEAR
DATA DIR
INa
OUTI
OE
OUT3

RFD/DAV
DAV/DAC
DAC/RFD

EMPTY
CLEAR
DATA DIR
INa
OUTI
OE
OUT3

'2 side only.
Table 1. Pin Assignments

242

2020·001

Functional
Description
(Continued)

Mode

MI

MO

0
0

0
0
0
0

0

0

BI

BO

Z- BUS Low Byte
Z-BUS Low Byte
Z-BUS Low Byte
Z-BUS Low Byte

Z-BUS Low Byte
Non-Z-BUS
3-Wire Handshake
2-WIre Handshake

0

Z-BUS High
Z-BUS High
Z-BUS High
Z-BUS High

Z-BUS High Byte
Non-Z-BUS
3-Wire Handshake
2-Wire Handshake

0

11

0
0
0
0

Port 2

0
1
0

6
8
9
10

Port 1

0

1
0

Byte
Byte
Byte
Byte

Z-BUS Low Byte
Non-Z-BUS
3-WIre Handshake
2-Wire Handshake

Non-Z-BUS
Non-Z-BUS
Non-Z-BUS
Non-Z-BUS

Table 2. Operating Modes

I

CHANNEL A

CHANNEL B

i

PORT 2

<8>

Z8OO2

PORT 3

<8>

SYSTEM
MEMORY

zao BUS
110
Z8.

}

SYSTEM
MEMORY

Z·BUS

Z80 BUS

Figure 4. CPU to CPU Configuration

2020-002, 003

MEMORY

Figure 5. CPU to 1/0 Configuration

HANDSHAKa
SIGNALS

Pins Common
To Both Sides

Pin
Signals

Pin
Numbers

Signal
Description

MO

21
19

MI and MO program Port I
sIde CPU interface

40

DC power source

GND

20

DC power ground

Pin
Signals

Pin
Names

Pin Numbers
Port
2

ADO-AD7
(Address/Data)

Do-D7

11-18

REQ/WAIT
(Request/Walt)

A

DMASTB
(DIrect Memory
Access Strobe)

B

DS
(Data Strobe)

C

R/W
(Read/Wnte)

D

4

36

Input; achve HIgh SIgnals CPU read from FlO;
achve Low SIgnals CPU wnte to FlO.

CS
(ChIp Select)

E

5

35

Input, achve Low. Enables FlO. Latched on the
rismg edge of AS.

AS
(Address Strobe)

F

6

34

Input, achve Low. Addresses, CS and INTACK
sampled whIle AS Low.

INTACK
(Interrupt
Acknowledge)

G

7

33

Input, achve Low. Acknowled~ an mterrupt.
Latched on the rismg edge of AS.

lEO
(Interrupt
Enable Out)

H

8

32

Output, achve HIgh. Sends interrupt enable to
lower prionty deVICe lEI pm.

lEI
(Interrupt
Enable In)

9

31

INT
(Interrupt)

10

GND

Z-BUS
High Byte
Mode

Pin

MI
+5 Vdc

MO
MI
+5 Vdc

Z-BUS
Low Byte
Mode

Names

Signal
Description

29-22

Mulhplexed bldlrechonal address/data hnes, Z·BUS
compatible.

39

Output, achve Low, REQUEST (ready) Ime for DMA
transfer; WAIT Ime (open-dram) output for synchromzed CPU and FlO data transfers.

2

38

Input, achve Low. Strobes DMA data to and from
the FIFO buffer.

3

37

Input, active Low. PrOVIdes hming for data trans-

fer to or from FlO.

Input, active HIgh. ReceIves mterrupt enable from

hIgher priority deVICe lEO signal.
30

Output, open dram, achve Low. SIgnals FlO mterrupt request to CPU.

Pin
Signal.

Pin
Names

Pin Numbers
Port
2

ADO-AD7
(Address/Data)

DO-D7

11-18

REQIWAI'C
(Request/Wait)

A

DMASTB
(DIrect Memory
Access Strobe)

B

2

38

DS
(Data Strobe)

C

3

37

Input, active Low. PrOVIdes timing for transfer of data
to or from FlO.

RIW
(ReadlWrite)

D

4

36

Input, achve High. Signals CPU read from FlO; achve
Low signals CPU wnte to FlO.

CS
(ChIp Select)

E

5

35

Input, achve LQ!Y.. Enables FlO. Latched on the
rlsmg edge of AS.

AS
(Address Strobe)

F

6

34

Input, active Low. Addresses, CS and INTACK are
sampled while AS IS Low.

Ao

G

7

33

Input, achve High. With Aj, A2, and A3, addresses
FlO internal registers.

Aj
(Address BIt I)

H

8

32

Input, achve HIgh. WIth AO, A2, and A3, addresses
FlO mternal regIsters.

A2
(Address BIt 2)

9

31

Input, active High. WIth AO' AI, and A3, addresses
FlO internal registers.

A3
(Address Bit 3)

10

30

Input, active HIgh. WIth AO, Aj, and A2, addresses
FlO internal regIsters.

29-22
39

(Address Bit 0)

Signal
Description
Mulhplexed bldirechonal address/data hnes, Z-BUS
compahble.
Output, active Low, REQUEST (ready) Ime for DMA
transfer; WAIT Ime (open-drain) output for synchronized CPU and FlO data transfers.
Input, active Low. Strobes DMA data to and from the
FIFO buffer.

Table 3. Signal/Pin Descriptions

244

Non-Z-BUS
Mode

Pin
Signals
DO-D7
(Data)

Pin

Pin Numbers
Pori

Signal
Description

Names

DO-D7

REQ/WT
(Request/Walt)

A

DACK
(DMA Acknowledge)

B

RD

C

11-18

2

29-22

BldlrectlOnal data bus.

39

Output, achve Low, REQUEST (ready) lme for DMA
transfer, WAIT lme (open-dram) output for synchromzed CPU and FlO data transfer.

38

Input, actIve Low

37

Input, actIve Low Signals CPU read from FlO

DMA acknowledge

(Read)
WR
(Wnte)

D

4

36

Input actIve Low Signals CPU wnte to FlO

CE
(ChIp Select)

E

5

35

Input, actIve Low. Used to select FlO.

cii5

F

6

34

Input, achve HIgh Idenhhes control byte on DO-D7;
active Low IdentIfIes data byte on DO-D7'

G

7

33

Input, actIve Low Acknowledges an mterrupt.

(Control/Data)
INTACK
(Interrupt
Acknowledge)
lEO
(Interrupt
Enable Out)

Port 2-1/0
Port Mode

00
0

H

8

32

W

Output, actIve HIgh Sends mterrupt enable to

.

00

lower prIonty devlce lEI pm.

lEI
(Interrupt
Enable In)

9

INT
(Interrupt)

!O

Pin
Signals

N

31

N
"It

....

Input active HIgh. ReceIves mterrupt enable from
hIgher pnonty devlCe lEO Slgnal

30

Output, open dram, active Low

0

SIgnals FlO mterrupt

to CPU
Pin

Signal
Description

Names

Pin
Numbers

DO-D7

29-22

2-Wlre HS'
3-Wlre HS

RFD/DAV
(Ready for Data/Data
AvaIlable)

A

39

2-Wlfe HS
3-Wlfe HS

ACKIN
(Acknowledge Input)

B

DAV/DAC
(Data AvaIlable/Data
Accepted)

B

38

3-Wlfe HS

Input; DAV (acl1ve Low) SIgnals that data IS valid on
bus. DAC (achve HIgh) SIgnals that output data IS
accepted by penpherals

FULL

C

37

2-Wlfe HS

Output open dram, achve HIgh Signals that FlO
buffer IS full.

DAC/RFD
(Data Accepted/Ready
for Data)

C

37

3-Wlfe HS

Dlrection controlled by mternal programmmg. Both
actIve HIgh DAC (an output) SIgnals that FlO has
receIved data from penpheral; RFD (an mput) SIgnals
that the lIsteners are ready for data.

EMPTY

D

36

2,Wlfe HS
3-Wlfe HS

Output, open dram, actIve HIgh Signals that FIFO
buffer IS empty.

CLEAR

E

35

2-Wlfe HS
3-Wlfe HS

Programmable mput or output, active Low. Clears all
data from FIFO buffer

DATA DIR
(Data Dlrecl1on)

F

34

2-Wlfe HS
3-Wlfe HS

Programmable mput or output. ActIve HIgh SIgnals
data mput to Port 2; Low SIgnals data output from
Port 2

INa

G

33

2-Wlfe HS
3-Wlfe HS

Input lme to DO of Control RegIster 3.

OUT)

H

32

2-Wlfe HS
3-Wlfe HS

Output lme from D) of Control RegIster 3

OE
(Output Enable)

31

2-Wlfe HS
3-Wlfe HS

Input, achve Low When Low, enables bus dnvers
When H,gh, floats bus dnvers at hIgh Impedance

OUT3

30

2-Wlfe HS
3-Wlfe HS

Output Ime from D3 of Control regIster 3.

DO-D7
(Data)

Mode
BIdIrectIonal data bus

Output, RFD achve
that FlO

38

2-Wlfe HS

HIgh~nals

penpherals that FlO

IS ready to receIve data DA V actIve Low SIgnals
IS

ready to send data to penpherals.

Input, actIve Low SIgnals FlO that output data

IS

receIved by perIpherals or that mput data IS vahd.

'Handshake
Table 3. Signal/Pin Descriptions (Conhnued)

245

Reset

The FlO can be reset under either hardware
or software control by one of the following
methods:
• By forcing both AS and DS Low simultaneously in Z-BUS mode (normally illegal).
• By forcing RD and WR Low simultaneously
in non-Z-BUS mode.
• By writing a I to the Reset bit in Control
register 0 for software reset.
In the Reset state, all control bits are cleared
to O. Only after clearing the Reset bit (by

CPU

Interfaces

The FlO is designed to work with both
Z-BUS- and non-Z-BUS-type CPUs on both Port
1 and Port 2. The Z-BUS configuration interfaces CPUs with time-multiplexed address and
data information on the same pins. The Z8001,
Z8002, and Z8 are examples of this type of
CPU. The AS (Address Strobe) pin is used to
latch the address and chip select information
sent out by the CPU. The R/W (Read/Write)
pin and the DS (Data Strobe) pin are used
for timing reads and writes from the CPU to

ADO-AD7

writing a 0 to it) can the other command bits
be programmed. This action is true for both
sides of the FlO when programmed as a CPU
interface.
For proper system control, when Port I is
reset, Port 2 is also reset. In addition, all Port
2's outputs are floating and all inputs are
ignored. To initiate the data transfer, Port 2
must be enabled by Port I. The Port 2 CPU
can determine when it is enabled by reading
Control register 0, which reads "floating" data
bus if not enabled and "OIH" if enabled.
the FlO (Figures 6 and 7).
The non-Z-BUS configuration is used for
CPUs where the address and data buses are
separate. Examples of this type of CPU are the
Z80 and 8080. The RD (Read) and WR (Write)
pins are used to time reads and writes from the
CPU to the FlO (Figures 9 and 10). The c/i5
(Control/Data) pin is used to directly access
the FIFO buffer (CiD = 0) and to access the
other registers (C/O = 1). Read and write to all

--< A~~~~:S )>_------~(......:T~O.:CP:u~)>------

IVWJ

\ ...._ _

f

\ ' -_ _---..I

Figure 6. Z-BUS Read Cycle timing

ADo-AD7

IVW

-_-----« A~~~~:S

H,-__~DA~TA~F:RO~M~c::pu~__)l---

c

\

\ . . . _ _--11
Figure 7. Z·BUS Write Cycle Timing

246

2020-004, 005

CPU
Interfaces

(Continued)

registers except the FIFO buffer! are two-step
operations, described as follows (Figure 8).
First, write the address (c/lS = 1) of the register
to be accessed into the Pointer Register (State
0); second, read or write (C/i) = I) to the
register pointed at previously (State 1). Continuous status monitoring can be performed in
State I by continuous Control Read operations
(C/D= I).

AD OR WR

1The FIFO buffer can also be accessed by this two~step operatIon

Figure 8. Register Access in Non-Z-BUS Mode

C/D=:=:x_______________C
Do-Dr

--------------_«:T~O~C:pu~>__
\~

______________J;__

I§

\~------_--'I
Figure 9. Non-Z-BUS Read Cycle Timing

eli)

x

C

X

-----I

)
(
DO-D7-----~~:::~~~::::>------FROM CPU

I

\

\

I

Figure 10. Non-Z-BUS Write Cycle Timing

WAIT
Operation

When data is output by the CPU, the
REOIWT (WAIT) pin is active (Low) only when
the FIFO buffer is full, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not full.

When data is input by the CPU, the
REO/WT pin becomes active (Low) only when
the FIFO buffer is empty, the chip is selected,
and the FIFO buffer is addressed. WAIT goes
inactive when the FIFO buffer is not empty.

Interrupt
Operation

The FlO supports Zilog's prioritized daisy
chain interrupt protocol for both Z-BUS and
non-Z-BUS operating modes (for more details
refer to the Zilog Z-BUS Summary).
Each side of the FlO has seven sources of
interrupt. The priorities of these devices are
fixed in the following order (highest to lowest):
Mailbox Message, Change in Data Direction,
Pattern Match, Status Match, Overflow/

Underflow Error, Buffer Full, and Buffer
Empty. Each interrupt source has three bits
that control how it generates the interrupt.
These bits are Interrupt Pending (IP),
Interrupt Enable (IE), and Interrupt Under
Service (IUS).
In addition, each side of the FlO has an
interrupt vector and four bits controlling the
FlO interrupt logic. These bits are Vector

2020-006. 007. 008

247

Interrupt
Operation

(Continued)

Includes Status (VIS), Master Interrupt Enable
(MIE), Disable Lower Chain (DLC), and No
Vector (NV).
A typical Interrupt Acknowledge cycle for
Z-BUS operation IS shown in FIgure II and for
non-Z-BUS operation in Figure 12. The only
dlfference is that in Z-BUS mode, INTACK is
latched by AS, and in non-Z-BUS mode
INTACK is not latched.
When MIE = I, reading the vector always
includes status, independent of the state of the

ADO-AD7~

VIS bIt. In this way, when VIS = 0, all mformabon can be obtained with one additional
read, thus conserving vector space. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified.
In non-Z-BUS mode, the IPs do not get set
while in State 1. Therefore, to minimize interrupt latency, the FlO should be left in State o.
In Z-BUS mode IPS are set by an AS following
the event.

(

VECTOR

}----

\\-.__-.JrlEI _ _...oJ/

INT _ _ _ _ _ _ _- J
/

Figure 11. Z-BUS Interrupt Acknowledge Cycle

DO-D7

------------~~~)_---

\1...... _ _--11
lEI _ _-...J/

INT _ _ _ _ _ _ _..J/

Figure 12. Non-Z-BUS Interrupt Acknowledge Cycle

CPU to CPU
Operation

248

DNA Operation. The FlO is particularly well

suited to work with a DMA in both Z-BUS and
non-Z-BUS modes. A data transfer between the
FlO and system memory can take place during
every machine cycle on both sides of the FlO
simultaneously.
In Z-BUS mode, the DMASTB pin (DMA
Strobe) is used to read or write into the FIFO
buffer. The RlW (Read/Write) and DS (Data
Strobe) signals are ignored by the FlO;

however, the CS (Chip Select) signal is not
ignored and therefore must be kept invalid.
Figures 13 and 14 show typical timing.
In Non-Z-BUS mode, the DACK pin (DMA
Acknowledge) is used to tell the FlO that its
DMA request is granted. After DACK goes
Low, every read or write to the FlO goes into
the FIFO buffer. Figures 15 and 16 show
typical timing.

2020·009, o!O

CPU to CPU

Operation

AID

aus

==><

F~~~R~:A}---{

DATA FROM FlO TO MEMORY

}-

(Continued)

'\,..__---JI

iii

,\. . ___-JrFigure 13. Z-BUS FlO to Memory Data T._loD

DATA FROM MEMORY TO FlO

}--

i
iii

, ' - -_ _ _

=

i

--J~

''--_---JI
Figure U. Z-BUS Memory to FlO Data Trcmsaction

ADDR.....

:::x. . .__

M_EM_O_R_y_AD_D_R_ESS_O_F_W_RIT_E_ _J

X..__________
J}-

DATA
aus

(DATA FROM FlO TO MEMOAV}---(-.-_ _ _ _ _ _

MEMORY
WRln

110

iiiAii

~~. ------------------------------------------Figure 15. Non-Z-BUS FlO to Memory Transaction

ADDR. . . . .

:::x

MEMORY ADDRESS OF READ

X,,____________
_:..j)-

DAaTuA. _ _ _ _<-::J!DA~T~AF~R~OM;:-"'I»)...--~«(
..._:._:._:._:.-:.-_-_
MEMORY TO FlO

•

•

'\...._-JI
''--_....,1
DR~~

_________________________

Figure 18. Non-loBUS Memory to FlO Data Trcmsactlon

2020-011,012,013,014

249

CPU to CPU
Operation
(Continued)

The FlO provides a special mode to enhance
its DMA transfer capability. When data is
written into the FIFO buffer, the REQ/WT
(REQUEST) pin is active (Low) until the FIFO
buffer is full. It then goes inactive and stays
inactive until the number of bytes in the FIFO
buffer is equal to the value programmed into
the Byte Count Comparison register. Then the
REQUEST signal goes active and the sequence
starts over again (Figure 17).

When data is read from the FlO, the
REQ/WT pin (REQUEST) is inactive until the
number of bytes in the FIFO buffer is equal to
the value programmed in the Byte Count Comparison register. The REQUEST signal then
goes active and stays active until the FIFO buffer is empty. When empty, REQUEST goes
inactive and the sequence starts over again
(Figure 18).

REC

(2)

ACTIVE

INACTIVE

(2)

-====-+---.--...----.0

ACTIVE

--!-----....---"T""--

CD

-.::0"'+__-4..::;0;;....__---1-.. NUMBER OF BYTES IN FIFO
NUMBEFlIN BYTE COUNT COMPARISON REGISTER

NUMBER IN BYTE COUNT COMPARISON REGISTER

NOTES:
I FIFO empty.
2. REQUEST enabled. FlO requests DMA transfer.
3. DMA transfers data mto the FlO.
4. FIFO full. REQUEST mactlve.

NOTES:
I. FIFO empty.
2. CPU/DMA hils FIFO buffer from the Opposlte port.
3. Number of bytes In FIFO buffer IS the same as the number
of bytes programmed In the Byte Count ComparIson regIster.

5. The FIFO emphes from the OppOSite port until the number
of bytes In the FIFO buffer IS the same as the number pro·
grammed m the Byte Count Companson register.

4. REQUEST goes achve.
5. DMA transfers data out of FIFO untillt IS empty.

Figure 17. Byte Count Control: Write to flO

Figure 18. Byte Count Control: Read from FlO

Message Registers. Two CPUs can communicate through a dedicated "mailbox" register
without involving the 128 x 8 bit FIFO buffer
(Figure 19). This mailbox approach is useful
for transferring control parameters between
the interfacing devices on either side of the
FlO without using the FIFO buffer. For
example, when Port l's CPU writes to the
Message Out register, Port 2's message IP is
set. If interrupts are enabled, Port 2's CPU is

PORT 1
MESSAGE OUT
REGISTER

<

interrupted. Port 2's message IP status is
readable from the Port 1 side. When Port 2's
CPU reads the data from its Message In register, the Port 2 IP is cleared. Thus, Port 1's
CPU can read when the message has been
read and can now send another message or
follow whatever protocol that is set up between
the two CPU's. The same transfer can also be
made from Port 2' s CPU to Port l' s CPU.

REGISTER
ADDRESS

?-

>

PORT 1

TO
PORT 2

--

MESSAGE
REGISTER

'---

PORT 2

TO

REGISTER

ADDRESS
"8"

REGISTER
ADDRESS

MESSAGE
REGISTER

"e"

po RT 1
MESSAGE IN
REG ISTER

(2)

FJlL

EMPTY

FULL

EMPTY

(2)

-.::::.+--------+=--r----

INACTIVE

-

PORT 1

"B"

-

A
~

PORT 2
MESSAGE IN
REGISTE R

~

"..

REGISTER
ADDRESS

~

PORT 2
MESSAGE OUT
REGISTER

"C"

NOTE: Usable only for CPU/CPU mterface.

Figure 19. Message Register Operation

250

2020-015.016.017

CPU to CPU
Operation

(Continued)

CLEAR (Empty) FIFO Operation. The CLEAR

Data Direction bit controls the direction of data
transfer in the FIFO buffer. The Data Direction
bit is defined as 0 = output from CPU and
1 = input to CPU. This bit reads correctly
when read by either port's CPU. For example,
if Port l's CPU reads a 0 (CPU output) in its
Data Direction bit, then Port 2's CPU reads a 1
(input to CPU) in its Data Direction bit.
In CPU/CPU mode, under program control,
only one of the ports can control the direction
of data transfer. The Port 1 CPU must program
bit 5 in Control Register 3 to determine which
port controls the data direction (0 = Port 1
control; 1 = Port 2 control). Figure 20 shows
FlO data transfer options.

FIFO bit (active Low) clears the FIFO buffer of
data. Writing a 0 to this bit empties the FIFO
buffer, inactivates the REQUEST line, and
disables the handshake (if programmed). The
CLEAR bit does not affect any control or data
register. To remove the CLEAR state, write a 1
to the CLEAR bit.
In CPU/CPU mode, under program control,
only one of the ports can empty the FIFO by
writing to its Control Register 3, bit 6. The
Port 1 CPU must program bit 7 in Control
Register 3 to determine which port controls the
CLEAR FIFO operation (0 = Port 1 control;
1 = Port 2 control).
Direction of Data Transfer Operation. The

Iw
00

~

(PROGRAM REGISTERS FOR OPERATING MODE,
PORT 2 CONFIGURATION, DATA TRANSFeR CONTROL, ETC)

PORT 1 (CPUI

PORT 2 (CPUI

PORT 2(1101

(DMA OR INTERRUPT·

TRANSFERS DATA BYTE·
AT-A·TIME UNTIL
FifO BUFFER IS

EXCHANGE BYTES
VIA MESSAGE REGISTER

DRIVEN TRANSFERS, AS

FOR PORT 1)

I
I
I

tI

TERMINATES ON ANY

TERMINATES ON ANY

OF THESE CONDITIONS:
*DMA BLOCK LENGTH REGISTER

OF THESE CONDITIONS.
·CPU COMPLETES BUFFER DUMP

=0

-FlO PATTERN MATCH INTERRUPT
·BYTE COUNT DISABLES REQ

·FIO PATTERN MATCH INTERRUPT
·flO BYTE COUNT INTERRUPT
-FlO Full I Empty INTERRUPT

I

I

I

l"

.//)
..... ,

,

full OR Empty

./,#'
./

Y

I
I
I
I
I
I
I
I
I
I

I
EXCHANGE BYTES
VIA MESSAGE REGISTERS

- - - .......

--

....

-----

\

/

Y
t
I
I

I
I
I

I
I
I
I
I

I
I
I
I

CONTINUE OR REPROGRAM PORT REGISTERS WITH NEW BLOCKS OF CONTROL BYTES.

Figure 20. FlO Data Transfer Options

2020·018

251

CPU to I/O
Operation

DATA I N = : ) (

VALID DATA

(Continued)

VALID DATA

X

'---I

I

\

ACKIN

X

X

RFD

Figure 21. Interlocked Handshake Timing (Input) Port 2 Side Only

X

DATA OUT = : ) (....._V_A_Ll_D_DA_T_A_.JXI.._ _ _.J

VALID DATA

X'-_ _ _ __

....~

ACiffij - - - - - " " " " \.... _ _--J/~---

\ ....._ _-'1

'---I

Figure 22. Interlocked Handshake Timing (Output) Port 2 Side Only

DATA I N . = : : x :

~~

c:::::x

VAl.ID DATA

J

\

D~~

\

DAC
OUT

________________J

I

VALID DATA

Iw

X......____

00

\ ...._____

§
o

'---I

I

Figure 23. Input (Acceptor) Timing IEEE-U8 HS Port: Port 2 Side Only

DATA OUT

=::x

DAV
OUT

X

VALID DATA

X

I

\

VALID DATA

X

'----f

DAC
IN

R~:--1

\

I

\

Figure 24. Output (Source) Timing IEEE-488 HS Port: Port 2 Side Only

2020-019, 020, 021, 022

253

Programming

The programming of the FlO is grea,tly
simplified by the effiCient grouping of the
various operation modes in the control
registers. Since all of the control registers are
read/write, the need for maintaining their
image in system memory is eliminated. Also,
the read/write feature of the registers aids in
system debugging.
Each side of the FlO has 16 registers. All 16
registers are used by the Port 1 Side; Control
register 2 is not used on the Port 2 side. All
registers are addressable 0H through FH.
In the Z-BUS Low Byte mode, the FlO allows
two methods for register addressing under control of the Right Justify Address (RJA) bit in
Control register 0. When RJA = 0, address
bus bits 1-4 are used for register addressing
and bits 1, 5, 6, and 7 are ignored (Table 4).
When RJA = 1, bits 0-3 are used for the
register addresses, and bits 4-7 are ignored.

Control Registers. These four registers specify
FlO operation. The Port 2 side control
NonZ·BUS

o,-Dc

{ RJA=O
RJA= I

°

Interrupt Status Registers. These four
registers control and monitor the priority
interrupt functions for the FlO.
Interrupt Vector Register. This register stores
the interrupt service routine address. This vector is placed on Do-D7 when IUS is set by the
Interrupt Acknowledge signal from the CPU.
When bit 4 (Vector Includes Status) is set in
Control Register 0, the reason for the interrupt
is encoded within the vector address in bits 1,
2, and 3. If bit 5 is set in Control register 0, no
vector is output by the FlO during an Interrupt
Acknowledge cycle. However, IUS is set as
usual.

D3

D:i

DI

Do

A3

A2

AI

An

Ao,-ADs
AD,-ADc

ADc
AD3

AD3
AD2

AD2
AD)

ADI
ADo

x

0
0
0

0
0
0
0

0
0

0
I

Z·BUS High
Z·BUS Low

registers operate only if the Port 2 device is a
CPU. The Port 2 CPU can control interface
operations, including data direction, only
when enabled by the setting of bit in the Port
1 side of Control Register 2. A 1 in bit 1 of the
same register enables the handshake logic.

Description
Control Register 0
Control Register 1
Interrupt Status Register 0
Interrupt Status RegIster I
Interrupt Status Register 2
Interrupt Status Register 3
Interrupt Vector RegIster
Byte Count RegIster
Byte Count ComparIson
Register
Control Register 2"
Control RegIster 3
Message Out RegIster
Message In RegIster
Pattern Match Register
Pattern Mask RegIster
Data Buffer RegIster

x
x
x
x
x
x
x

0
0
0
0
0

x
x
x
x

0
0
1

0
1
0

x
x
x
x

x

0

0

0

x

x

0
0
0

0

1
0

x

I

I

x

0
0

0
I

x

0

x

x
x
x
x
x
x

x=Don't Care
·Register IS only on Port I side

Table 4. FlO Register Address Summary

254

0

ADo

x

x

x

Programming Byte Count Compare Register. This register
(Continued)
contains a value compared with the byte count
in the Byte Count register. If the Byte Count
Compare interrupt is enabled, an interrupt will
occur upon compare.
Message Out Register. Either CPU can place
a message in its Message Out register. If the
opposite side Message register interrupt is
enabled, the receiving side CPU will receive
an interrupt request, advising that a message
is present in its Message In register. Bit 5 in
Control Register 1 on the initiating side is set
when a message is written. It is cleared when
the message is read by the receiving CPU.
Message In Register. This register receives a
message placed in the Message Out register by
the opposite side CPU.

Pattern Match Register. This register contains
a bit pattern matched against the byte in the

Data Buffer register. When these patterns
match, a Pattern Match interrupt will be
generated, if previously enabled.

Pattern Mask Register. The Pattern Mask
register may be programmed with a bit pattern
mask that limits comparable bits in the Pattern
Match register to non-masked bits (l = mask).
Data Buffer Register. This register contains
the data to be read from or written to the
FIFO buffer.
Byte Count Register. This is a read-only
register, containing the byte count for the
FIFO buffer. The byte count is derived by subtracting the number of bytes read from the buffer from the number of bytes written into the
buffer. The count is "frozen" for an accurate
reading by setting bit 6 (Freeze Status register)
in Control Register 1. This bit is cleared when
the Byte Count register read is completed.

I
GO

Z·8US

5
1/'0---'''-'\ ~MM.
l \ r - - v LINE

MASTER
CPU

NOTES:
I. Data from master CPU - Z-FIO Port 2.
2. Z-FIO Port I -DCP.
3. DCP -RAM.
4. RAM -Z-SCC.
5. Z-SCC - data comm. Ime loop.

Figure 25. Typical AppllcatlOD' Node CoDtroUer

2020-033

255

Registers

Control Register 0
Address: 0000
(ReadIWrite)

EC

Control Register 2*
Address: 100 1
(ReadIWrite)

'TL..:=
'OG1

10, I0.1 0, I0 I !

I~I~I~I~I~I~I~I~I

I

= RESET

1 "" AT JUST ADDRESS
(81) (Bo)'
(RJA)

~ ~~::: ~g~scpu
3 WIR~ BHUSSI~U

g

1_

}

- INTERLOCKED HS

~ :: PORT 2 SIDE ENABLED
_ PORT 2 SIDE ENABLE

BITS 2-7 NOT U

-THIS R

=~OGRAMS

D'S

FRg;I~6ERRTREADS

ALL

MUST Be

2SIDE

RT 2 MODE

PROG:~~MED

HANDSHAKE
0

_ VECTOR INCLUDE
1 ;:: NO VECTOR ON I : STATUS (VIS)

.:~~~ ~~,LOYEFROM

1 = DISABLE LOWER
1

D:~RAUPT (NV)

= INTERRUPTS EN ABLED
SY (MIE)
CHAIN 10LC)

Control Register 3
Address: 1010
(ReadIWrite)

Control Register I
Address: 0001
(ReadIWrile)
0

1,1

i

II i'~ :~":~~~::;:':;:

10, I0.1 0, I0.1 0

~'ID
~'ID
~'ID
~'I~:

0

l1;,jD

= REQUEST/WAIT ENABLED

10

I

1 "" REQUEST

DIREC~

0"" PORT 1

p:~E COUNT

1 :; START DMA ON
1 ::: STOP DMA ON

UTPUT LINE (PIN 30)"

SI~:OM CPU

: : PORT 2 SIDE

1 '" MESSAGE
ERN MATCH
1 _ M
MAILBOX REGIS
1
ESSAGE MAILBOX REGiSTER UNDER SERVICE-

_ _ _ _ _ _ _-

=

-READ.ONLY BITS

DATA

~: ~:TUpTu~ci~~~IT

"" WAIT

_ FREeZE STATU

PORT 2 SIDE 05T BE PROGRAMMED 0)

_~~~~.ONLY
•

TER FULL·

O=PORT1SIDE

BITS

~~~~:~~: DATA DIRECTION

- CLEAR FIFO BUFFER

1= PORT 2 SIDE

~g~~ROLS

Y WHEN PORT 2 IS AN 110 PORT

NOT USED (MUST BE
S PROGRAMMED
REGISTER COUNT
0)

CLEAR

ROLS

Figure 26_ Control Registers

Interrupt
Add8t atus Register 0
ress: 0010
(ReadIWrite)

1111 l' ',I ',I'e ~~J'.~..""._,"
,

,

MESSAGE INTERRUPT
0)
MESSAGE INTERRUPT :ENDING (IP)
ABLE

MESSAGE INTERRUPT U:
(IE)
FOLLOWIN~R;o%~nEN
USING
DER SERVICE IIUS)

IUS. IE. AND IP
THE
NULL CODE

AND.

CLEAR IP & IUS

o

SET IUS

Figure 27_ Interrupt Status Registers

256

2020-023

Registers
(Continued)

Interrupt Status Register 1
Address: 0011
(ReadlWrite)

DATA DIRECTION CHANGE INTERRUPT

UNDER SERVICE (IUS)

DATA OlRECTION CHANGE INTERRUPT
DATA DIRECTION CHANGE

~:~:~:~~~

iJ ~llli

L 1 = PATTERN MATCH FLAG'

I

I

~

I

:

I

I

PATTERN MATCH INTERRUPT

I

I

I

t

I

I

UNDER SERVICE (IUS)
NOT USED
(MUST BE PROGRAMMED 0)

o
o

0

0

NULL coDe

0

1

CLEAR IP & IUS

o

1

0

SErlUS

o

1

1

CLEAR IUS

1

0

1

0

:

PENDING (IP)
IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND

NULL CODE

0

0

0

CLEAR IP & IUS

0

0

1

SET IUS

0

1

0

CLEAR IUS

0

1

1

SET IP

1

0

0

CLEAR IP

1

0

1

SET IE

1

1

0

CLEAR IE

1

1

1

PATTERN MATCH INTERRUPT PENDING (IP)
PATTERN MATCH INTERRUPT ENABLED (IE)

IUS, IE, AND IP ARE WRITTEN USING

THE FOLlOWING COMMAND:

SETIP
CLEAR IP

11

0

8ETIE

1

1

CLEAR IE

1

I

* READ ONLY BITS

Interrupt Status Register 2
Address: 0100
(ReadlWrite)

BYTE COUNT COMPARE INTERRUPT
UNDER SERVICE (IUS)

jJ I
I

I

BYTE COUNT COMPARE INTERRUPT
ENABL.E (IE)
BYTE COUNT COMPARE INTERRUPT
PENDING (lP)

I
I

L
~llli

L UNDERFLOW ERROR'

I

I

CLEAR IP &: IUS

ERROR INTERRUPT PENDING (ID)
ERROR INTERRUPT ENABLED (IE)

I

I

ERROR INTERRUPT UNDER SERVICE (IUS)

I

I

I

OVERFLOW ERROR*

0

o

0

0

1

o

0

CLEAR IP &: IUS

0

1

'SET IUS

I

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

IUS, IE, AND IP ARE WRITTEN USING
THE FOL.LOWING COMMAND'
NULL CODE

•

0

0

1

••

NULL CODE

0

1

1

o
o

SET IP

1

0

0

1DOSETIP

CLEAR IP

1

seT IE

1

•

CLEAR IE

1

SET IUS
CLEAR IUS

i

1

1

CLEAR IUS

1

1

0

1

CLEAR IP

1

0

11

0

SET IE

1

1

1

1

CLEAR IE

~READ·ONlY

1

BITS

Interrupt Status Register 3
Address: 0101
(ReadlWrite)

FU," INTERRUPT UNDER SERVICE IIU$)
FULL INTERRUPT ENABLE (IE)

~ I
~
I
I

I

llli

~ BUFFER EMPTY'
I

FULL INTERRUPT PENDINIl (IP)
IUS, "IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

I

I

I

I

I

EMPTY INTERRUPT PENDING (IP)
EMPTY INTERRUPT ENABLE (IE)
EMPTY INTERRUPT UNDER SERVICE (IUS)

' - - ' - - ' - - - BUFFER FULV

NULL CODE

IUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING COMMAND:

CLEAR IP &: IUS

0

0

1

SET IUS

0

1

0

o

0

0

NULL CODE

•

1

1

o

0

1

CI,.EAR IP &: IUS

1

0

0

o

1

0

SETIUS

CLEAR IP

1

0

1

o

1

1

CLEAR IUS

SET IE

1

1

0

CLEAR IE

1

1

1

CLEAR IUS
SET IP

100SETIP

0

1

CLEAR IP

11

1

o

SET IE

1

1

CI,.EAR IE

1

-READ·ONLY BITS

Figure 27, Interrupt Status Regllte.. (Continued)

2020-024

257

Registers
(Continued)

Byte Count Register
Address: 0 III
(Read Only)

Interrupt Vector Register
Address: 0110
(ReadlWrite)

I~I~I~I~I~I~I~I~I

1~1~1~1~1~1~1~1~1

1..

I I I I

I I I I I I I I
REFLECTS NUMBER OF BYTES IN BUFFER

Figure 28. Byte Count Register
VECTOR STATUS

NO INTERRUPTS PENDING

o

0

BUFFER EMPTY

0

OVER/UNDERFLOW ERROR

o
o
o

BYTE COUNT MATCH

1

1
0

1

BUFFER FULL

0

1

PATTERN MATCH

1

0

1

DATA DIRECTION CHANGE

1

1

0

MAILBOX MESSAGE

1

1

1

Figure 29. Interrupt Vector Register

Pattern Match Register
Address: 110 1
(ReadlWrite)

Pattern Mask Register
Address: 1110
(ReadlWrite)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

II I I II I I
STORES BYTE COMPARED WITH
BYTE IN DATA BUFFER REGISTER

II I II I I I
IF SET, BITS ()'7 MASK BITS 0·7

IN PATTERN MATCH REGISTER.
MATCH OCCURS WHEN ALL
NON·MASKED BITS AOREE.

Figure 30. Pattern Match Register
Figure 31. Pattern Mask Register

Data Buffer Register
Address: 1111
(ReadlWrite)

Byte Count Comparison Register
Address: 1000
(ReadlWrite)

ID, ID.I D.ID.I D, ID, ID, I~ I
I I " II I I

I~I~I~I~I~I~I~I~I

CONTAINS THE BYTE TRANSFERRED

CONTAINS VALUE COMPARED TO BYTE COUNT

TO OR FROM FIFO BUFFER RAM

REQISTER TO ISSUE INTERRUPTS ON MATCH
(BIT 7 ALWAYS 0.)

Figure 32. Data Buffer Register

Figure 33. Byte Count Comparison Register

Message Out Register
Address: 1011
(ReadlWrite)

Message In Register
Address: 1100
(Read Only)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

"

I I II I I

STORES MESSAGE SENT'TO MESSAQE
IN REGISTER ON OPPOSITE PORT OF FlO

Figure

258

I I I I I I I I

3.. Message Out Rl!glster

"

II I I I I

STORES MESSAGE RECEIVED FROM MESSAGE
OUT REGISTER ON OPPOSITE PORT OF CPU

Figure 3S. Message In Register

2020-025,026,027,028,029,030,031. 032

Absolute
Maximum
Ratings

Voltages on all mputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operahng Ambient
Temperature ................. 0 °C to + 70°C
Storage Temperature ........ -65°C to + 150°C

Standard
Test
Conditions

The charactenstics below apply for the
following standard test condihons, unless
otherwise noted. All voltages are referenced to
GND. Posihve current flows mto the referenced pm. Standard conditions are as follows:

Stresses greater than those lIsted under Absolute MaxI·
mum RatIngs may cause permanent damage to the deVIce.

ThIs IS a stress rahng only; operahon of the devlCe at any
condIhon above those mdIcated In the operahonal sections
of these speclhcahons IS not Imphed. Exposure to absolute
maXImum ratmg canddions for extended perIods may affect
devIce relIabIlIty
~

• +4.75 V

:5

Vee

:5

+5.25 V

• GND = 0 V
• TA as specified m Ordermg Informahon

+5V

dr
+5V

22<

'·'<

FROM OUTPUT
UNDER TEST

N
GO

SOPF

2GO

.
N

Standard Test Load

....

Open-Drain Test Load

C

DC
Characteristics

Symbol

Parameter

Min

Max

Unit

Vcc+ 0.3
0.8

V

VIH

Input High Voltage

2.0

VIL
VOH

Input Low Voltage

-0.3

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

1m

Output Leakage

ILM

Mode Pms Input Leakage
(Pins 19 and 21)

Icc

Vee Supply Current

2.4

-100

Condition

V
V
V

IOH = -250 ",A

0.4
0.5
± 10.0

V
",A

IOL = +3.2 rnA
0.4 :5 VIN :5 + 2.4V

± 10.0

",A

0.4

+ 10.0

",A

O--n----0----y._@_IfI---@----I

-0-1

1ii

\

--®--I

,------i

EMPTY

.®-fULL

Figure 48. 2-Wire Handshake (Port 2 Side Only) Output

DATA

=>t

VALID DATA

-(ij-

.(B).

ACKiN

,

---{2}---1 .(B).I
RFD

EMPTY

FULL

.

@

-®---y1--(3)-\
.

I~'-----

Figure 49. 2-Wire Handshake (Port 2 Side Only) Input

2020-046, 047

269

AC Characteristics
"MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

Max

Notes*t

TsDI(DAV)
Data Input to DAV I Setup Time
50
50
TdDAVIf(RFD) DAV I to RFD I Delay
2
o
500
0
500
TdDAVf(DAC) DAV I to DAC I Delay
o
500
0
500
3
4-ThDI(DAC)--Data In to DAC I Hold T l m e - - - - - - - - - O - - - - - - a
5
TdDACIr(DAV) DAC I to DAV I Delay
0
0
500
0
6
TdDAVIr(DAC) DAV I to DAC I Delay
0
500
500
7
TdDAVIr(RFD) DAV I to RFD I Delay
0
0
500
8-TdRFDI(DAV)-RFD I to DAV I Delay
0------0
9
TsDO(DAC)
Data Out to DAV I
10
TdDAVOf(RFD) DAV I to RFD I Delay
o
0
0
II
TdDAVOf(DAC) DAV I to DAC I Delay
o
12-ThDO(DAC)--Data Out to DAC I Hold Time - - - - - - - - - - - - - - - - - - - - - - - 13
TdDACOr(DAV) DAC I to DAV I Delay
400
400
14
TdDAVOr(DAC) DAV I to DAC I Delay
a
0
15
TdDAVOr(RFD) DAV I to RFD I Delay
0
o
16
TdRFDO(DAV) RFD I to DAV I Delay
800
o 800
0
NOTES* Timmgs are prelimmary and subject to change.
r Umts In nanoseconds (ns)

DATA

(PIN)
38

INPUT

DAY

( PIN)
39

OUTPUT

( PIN)
37

OUTPUT _ _ _ _ _~_~

R,D

Dole

Figure 50. 3·Wlre Handshake Input

DATA

( PIN)
38

ISO

OUTPUT

Figure 51. 3·Wlre Handshake Output

270

2020-049

Ordering
Information

Product
Number

Packagel
Temp
Speed

Description

Product
Number

Packagel
Temp
Speed

Description

CE
CM

4.0 MHz

2-FIO (40-pm)

28038A

CM

6.0 MHz

2-FIO (40-pin)

28038

4.0 MHz

Same as above

28038A

CMB

6.0 MHz

Same as above

28038

CMB

4.0 MHz

Same as above

28038A

CS

6.0 MHz

Same as above

28038
28038

CS
DE

4.0 MHz
4.0 MHz

Same as above
Same as above

28038A
28038A

DE
DS

6.0 MHz
6.0 MHz

Same as above
Same as above

28038

DS

4.0 MHz

Same as above

28038A

Same as above

PE

4.0 MHz

Same as above

28038A

PE
PS

6.0 MHz

28038

6.0 MHz

Same as above

28038

PS

4.0 MHz

Same as above

28038

NOTES. C = Ceramic, D = Cerdlp, P = Pla,lic; E
WIth Class B processmg, S = aoc to + 70°C

= -40°C to

+85°C, M

= 55°C to

+ 125°C, MB

= -55°C to

125°C wilh MIL·STD-883

271

Z8060
Z8000™FIFO Buffer Unit
and Z-FIO Expander

~
Zilog

Product
Specification

June 19S2

Features

• Bidirectional, asynchronous data transfer
capability
• Large 12S-bit-by-S-bit buffer memory
• Two-wire, interlocked handshake protocol
• Wire-ORing of empty and full outputs for
sensing of multiple-unit buffers

General
Description

The ZS060 First-In First-Out (FIFO) Buffer
Unit consists of a 12S-bit-by-S-bit memory,
bidirectional data transfer and handshake
logic. The structure of the FIFO unit is similar
to that of other available buffer units. FIFO is
a general-purpose unit; its handshake logic is
compatible with that of other members of
Zilog's ZS and Z8000 Families.
FIFOs can be cascaded end-to-end without
limit to form a parallel S-bit buffer of any

D:~:{=~ '!' ~~}~~!A

deSired length (in 12S-byte increments). Any
number of single- or multiple-unit FIFO serial
buffers can be connected in parallel to form
buffers of any desired width (in S-bit
increments).
The FIFO buffer units are available as
2S-pin packages. Figures 1 and 2 show the pin
functions and pin assignments, respectively, of
the FIFO device. A block diagram is shown in
Figure 3.

RFDIDAVA
ACKINA
FULL

Z8060

O2 ........

EMPTY

FI~O

0, ........

OEA

......... Do

I

Do .........

DOA

ACKIN

I

ACKIN ___ }

--.... RFOJDAV : RFD/DAV

~

----. ~~~~ 1r~~~

~

DIRAIB

FULL
EMPTY
CLEAR

+5V

CONTROL

+5V
RFD/DAVB

ACKINe
CLEAR
CIR AlB

OEB

0,.

Do.

0,.

0,.

D3A

0,.

D'A
D5A

03.

D6A

05.

D••

0,.

D,.

GND

0,.

GND

Figure I. FIFO Pin Functions

2123-001,002

• Connects any number of FIFOs in parallel
to form buffer of any desired width

. . - . . 0,

_

COMMON {
CONTROL

• Connects any number of FIFOs in series to
form buffer of any desired length

......... 02

-

CONTROL {

• 3-state data outputs

Figure 2. FIFO Pin Assignments

273

General
Description
(Continued)

DATA

DATA

BUS

BUS

•

A

CONTROL
AND

1/ - - - , CONTROL

AND

STATUS

STATUS

Figure 3. Functional Block Diagram

Pin
Descriptions

ACKIN. Acknowledge Input (input, active
Low). This line signals the FIFO that output
data has been received by peripherals or that
input data is valid.
CLEAR. Clear Buffer (input, active Low).
When set to Low, this line causes all data to be
cleared from the FIFO buffer.
Do-~. Data Bus (inputs/outputs, bidirectional). These bidirectional lines are used by
the FIFO to receive and to transmit data.

Functional
Description

FULL. Buffer Status (output, active High,
open-drain). A High on this line indicates that
the FIFO buffer is full.
OEA, OEB. Output Enable A, Output Enable
B (inputs, active Low). When Low, OEA
enables the bus drivers for Port A; when High,
OEA causes the bus drivers to float to a highimpedance level. Input OEB controls the bus
drivers for Port B in the same manner as OEA
controls those for Port A.

DIR AlB. Direction Input AlB (input, two control states). A High on this line signals that
input data is to be received at Port B. A Low
on this line signals that input data is to be
received at Port A.
EMPTY. Buffer Status (output, active High,
open-drain). A High on this line indicates that
the FIFO buffer is empty.

RFD/DAV. Ready-for-DataIData Available
(outputs RFD, active High; DAV active Low).
RFD, when High, signals to the peripherals
involved that the FIFO is ready to receive
data. DAV, when Low, signals to the
peripherals involved that FIFO has data
available to send.

Interlocked 2-Wire Handshake. In interlocked 2-wire handshake operation, the action
of FIFO must be acknowledged by the other
half of the handshake before the next action
can occur. In an Output Handshake mode, the
FIFO indicates that new data is available only
after the external device has indicated that it is
ready for the data. In an Input Handshake
mode, the FIFO does not indicate that it is
ready for new data until the data source indi-

cates that the previous byte of the data is no
longer available, thereby acknowledging the
acceptance of the last byte. This control
feature allows the FIFO, with no external
logic, to directly mterface with the port of any
CPU in the 28 Family-a CIO, a UPC, an FlO,
or another FIFO. The timing for the input and
output handshake operations IS shown in
Figures 4 and 5, respectively.

DATAIN:::X

VALID DATA

X
I

\

ACKIN

X

X
'----I
VALID DATA

RFD

Figure 4. Two·Wire Interlocked Handshake Timing (input)

DATA OUT

:::x

ACKIN

DAV

X

VALID DATA

I

\

\

I

VALID DATA

x::

~

'---I

Figure 5. Two·Wire Interlocked Handshake Timing (output)

274

2123-003,004,005

Functional
Description
(Continued)

Resetting or Clearing the FIFO. The CLEAR
input is used to initialize and clear the FIFO.
A Low level on this input clears all data from
the FIFO, allows the EMPTY output to go High
and forces both outputs RFD/DAVA and
RFD/DAVB High. A High level on CLEAR
allows the data to transfer through the FIFO.
Bidirectional Transfer Control. The FIFO has
bidirectional data transfer capability under
control of the DIR AlB input. When DIR AlB is
set Low, Port A becomes input handshake and
Port B becomes output handshake; data
transfers are then made from Port A to Port B.
Setting DIR AlB High reverses the handshake
assignments and the direction of transfer. This
bidirectional control is illustrated in Table 1.

DIR ilB

0

tion change is to be made, the recommended
procedure is:
(1) Force and hold CLEAR Low.
(2) Set DIR AlB to the level required for the
desired direction.
(3) Force CLEAR High.
Empty and Full Operation. The EMPTY and
FULL output lines can be wire-ORed with the
EMPTY and FULL lines of other FIFOs and
FIOs. This capability enables the user to
determine the empty/full status of a buffer consisting of multiple FIFOs, FIOs, or a combination of both. Table 2 shows the various states of
EMPTY and FULL.
Number 01
Bytes In FIFO

PortA
Handabake

Port B
Handshake

Trcmsfer

Input
Output

Output
Input

Ato B
BtoA

EMPTY

High
Low
Low

0
1-127
128

I

FULL

Low
Low
High

Table 2. Signals EMPTY aDd FULL Operallon Table

Table I. BldlrectloDCII Control Function Table

The FIFO buffer must be empty before the
direction of transfer is changed; otl;1erwise, the
results of the change will be unpredictable. If
FIFO status is unknown' when a transfer direc-

Interconnection Example. Figure 6 illustrates
a simplified block diagram showing the manner in which FIFOs can be interconnected to
extend a FlO buffer .
• 5V

.5V

t------'--.,..-------+----,----

SYSTEM FULL

t-----.,..--+-----~-~-4---- SYSTEM EMPTY

,, _ _ _ , OATA
BUS

PORT 2
of

Z803.
AFDlDAV

Z80.0

Z80.0

.ACKiR,.

ACKiNA

RFDIHAYs

RFDlI5AV,

}.IO ....LS

ACiiiN

RFDIDAVA

Ammil

RFDlDAV,.

OE.

OE.

AC'i("iN.

OE.

OUTPUT CONTROL

....
SVSTEMCI:EliR
SYSTEM DIREcnON

Figure 6. TyplcallDterconneclion (Simpllfled Diagram)

2123·006

275

I

f'unctional
Description
(Continued)

Output Enable Operation. The FIFO provides
a separate Output Enable (OE) signal for each
port of the butler. An OE output is valid only
when its port is in the Output Handshake
mode, The control of this output function is
shown in Table 3. Signal OE operates with
lines DIR AlB. A High on a valid OE line
3-states its port's data bus but does not affect
the handshake operation. A Low level on a
valid OE enables the data bus outputs if its
port is in the Output Handshake mode. Note
that the handshake operation is unaffected by
the Output Enable pin.

Function

o

x

o

x

o

Disable Port A Output
Disable Port B Output

o

NOTE: X

Disable Port A Output
Enable Port B Output

X

Enable Port A Output
Disable Port B Output

X

Disable Port A Output
Disable Port B Output

= Don't care.
Table 3. Output Control Function Table

Absolut.
Maximum
Ratings

Voltages on all inputs and outputs with respect
to GND ................... -0.3 V to +7.0 V
Operating
Ambient Temperature ......... As specified in
Ordering Information
Storage Temperature ........ . _65° to + 150°C

Stresses greater than those lIsted under Absolute Maxlmum
Ratings may cause permanent damage to the devICe Thls IS a
stress ratIng only; operation of the devICe at any condItion above
those mdlcated m the operatIonal sections of these speciflCatlODs IS
not ImplIed Exposure to absolute maXImum ratmg concilhons for
extended penods may affect devICe reliabIlIty.

Standard
Test
Conditions

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard condihons are as follows:

• +4.75 V:$ Vee :$ +5.25 V
• GND = 0 V
• TA as speclfJed m Ordermg InformatIOn. All
ac parameters assume a load capacItance of
50 pF max .

d
.5\1

• 5\1

2.2K

2.2K

FROM OUTPUT
UNDER TEST

SOPF

Figure 7. Standard Test Load

276

I

Figure 8. Open-Drain Test Load

8085-0239. 00 I

DC
Character-

istics

Symbol

Min

Max

Unit

VIH

Input High Voltage

2.0

Vcc+0.3

V

VIH

Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

VOL

Output Low Voltage

2.4

Condltlon

IoH

V
V

IoL = +2.0 rnA
IoL = +3.2 rnA

IlL

Input Leakage

±IO

p.A

0.4

Output Leakage

± 10

p.A

0.4

Icc

Vcc Supply Current

200

rnA

Vcc

Symbol

=

= -250 A

V
0.4
0.5

1m
NOTE.

Capacitance

Parameter

:s VIN ::s +2.4 V
:s Your ::s +2.4 V

+ 5 V ± 5% unless otherwIse specIfIed over specIfIed temperature range

Parameter

Min

Max

Unit

Test Condition

C IN

Input CapaCitance

10

pF

Unmeasured pins

CoUT

Output Capacitance

IS

pF

returned to ground

CliO

Bidlreclional CapaCitance

20

pF

I

Input
tr

Any input rise lime

100

ns

If

Any input fall time

100

ns

NOTE' f

Ordering
Information

=

Produc:t
Number

i

1 MHz over speCIfied temperature range

Pac:kage/
Temp
Speed

Desc:ription

Produc:t
Number

Pac:kagel
Temp
Speed

Description

28060

CE

4.0 MHz

FIFO (28-pin)

28060

DS

4.0 MHz

FIFO (28-pin)

28060

CS

4.0 MHz

Same as above

28060

PE

4.0 MHz

Same as above

28060

DE

4.0 MHz

Same as above

28060

PS

4.0 MHz

Same as above

NOTES. C

= CeramIc, D = Cerdlp, P = Plastic, E = -40'C 10

+SS'C, S

= O'C 10 70'C

277

2-Wire
Interlocked
Handshake
Timing

INPUT TIMING

DATA

RFD

EMPTY

FULL

_-----J~
J
OUTPUT TIMING

ACKNOWLEDGE INPUT TO DATA AVAILABLE TIME (BUBBLE TIME)

\~-------

1:S~-

OUTPUT ENABLE AND CLEAR

Figure 9. Timing Diagrams

278

2123-007

FIFO 2-Wire Handshake Timing. Timing for
2-wire interlocked handshake operation is
shown in Figure 9. The symbol, description
AC
Characteristics

No.

2
3
4

Symbol
TsDI(ACK)
TdACKf(RFD)
TdRFDr(ACK)
TsDO(DAV)

and values for the numbered parameters
(Figure 9) are given in AC Characteristics.

Parameter

Data Input to ACKIN I to Setup Time
ACKIN I to RFD I Delay
RFD I to ACKIN I Delay
Data Out to DAV I Setup Time

MID

Max

UDitS·

ns

o
o

ns
ns

25

ns
5 - TdDAVf(ACK) - - DAV I to ACKIN I Delay - - - - - - - - - - - 0 - - - - - ns6 ThDO(ACK)
Data Out to ACKIN I Hold Time
ns
7 TdACK(DAV)
ACKIN I to DAV I Delay
0
ns
8 ThDI(RFD)
Data Input to RFD I Hold Time
0
ns
9 TdRFDf(ACK)
RFD I to ACKIN I Delay
0
ns
10-TdACKr(RFD)--ACKIN I toRFD I Delay - - - - - - - - - - - 0 - - - - - nsII
TdDAVr(ACK)
pAY I to ACKIN I
0
ns
12 TdACKr(DAV)
ACKIN I to DAV I
o
ns
13
TdACKINf(EMPTY) (Input) ACKIN I to EMPTY I Delay
(Output) ACKIN I to EMPTY I Delay
14 TdACKINf(FULL) (Input) ACKIN I to FULL I Delay
(Output) ACKIN I to FULL I Delay
15 -ACKIN Clock Rate (Input or Output) - - - - - - - - - - - - - - - 1 . 0 - - - - - MHz16
TdACKINf(DAVf) (Bubble Time)
ns
17
TwCLR
Width of Clear to Reset FIFO
700
ns
18 TdOE(DO)
OE I to Data Bus Driven
o
ns
19
TdOE(DRZ)
OE I to Data Bus Float
ns
NOTES.
* All tImmg references assume 2 0 V for a logIC 1 and 0.8 V for a
loglc O. Tlmmgs are prelIminary and subject to change.

OU·2123-U2

279

N

I....

3

Z8065
Z8000™Z·BEP
Barst Error Processor

~
Zilog

Prodact
Specification

June 1982

Features

• Provides three correction algorIthms:

• Detects errors in serial data up to 585,442
bits in length

o

• Implements correction of a detected error
burst of up to 12 bits in length

Full-period clock-around method for conformance to current practices

o Chinese remainder theorem, which
reduces correction time by orders of
magnitude

• Handles effective data rates of up to 20M
bits per second

o ReCiprocal polynomial, which allows cor-

• Provides four industry-standard polynomials
for error detection

rection with 48-bit code

• Designed for use in both microprocessor
and microprogrammed disk-controlled
systems

General
Description

The Z8065 Burst Error Processor (BEP) provides error detection and correction faClilties
for high-performance, high-density disk
systems and any other system in which highspeed serial data transfers occur.
For error detection, the BEP provides a
selection of four standard polynomials,
including the more popular 56-bit and 48-blt

} _. .

DATA {
INPUT

versions, to satIsfy a broad range of applications. During write operations, the BEP
generates check-bit words, which are appended to the record being written onto the disk.
These check-bit words are then used in subsequent reads and, if necessary, in correction
operations.

+5V

o~-

Q,
Q,

a,
a,
a,
a,

CHECK BITS

REP

.,
P,

POLYNOMIAL {
SELECT

P,

}

FUNCTION {
SELECT

LOCATED ERROR
PATTERN

Co

READ ERROR
PATTERN

ERROR

C,

ALIONMENT EXCEPTION

P,
P,

ERROR PATTERN

C,

,

}

POLYNOMIAL {
SHIFT CONTROL

+5V GND

CP

D,

PATTERN MATCH

2019-002

Some of the materIal used herem

IS

D,

GND

D,

MR

Figure I. Pin Functions

2019-001

D,

used by

permISSIon

Figure 2. Pin Assignments

of Advanced MIcro

DeVIces, Ir..c

281

I
;
at

•

General
Description
(Continued)

When a stored record is read, the BEP computes the syndrome for data validation. This
syndrome is then used to determine if an error
burst. is present in the retrieved data stream. If
an error is detected, the BEP can be used to
locate its actual bit pattern. The information
obtained is then made available to the host
system where it is used to correct the data
read. Any oLthe three algorithms can be

selected for this process.
The BEP is fabricated using silicon-gate,
N-MOS technology and is supplied in a 40-pin
dual in-line package (DIP). Figures 1
and 2 illustrate the pin functions and pin
assignments, respectively, of the 28065. 28065
operation requires a + 5 V dc power supply
and a single-phase clock.

Pin
Descriptions

AE. Alignment Exception (output, active

data stream. If the register array contains a
zero syndrome, ER is set Low to indicate that
no error was detected. If the array contains a
non-zero syndrome, ER is set High to indicate
that an error was detected. The output is valid
only after the BEP receives the last check byte
during a norpIal read or a read high-speed
function. The resulting syndrome is contained
by the register array. ER is set Low each time
the BEP is initialized.

High). This output goes High when a misalignment condition occurs during an error-pattern
search operation.
Co-~. Function Select (inputs, active High).
These three lines carry the binary code used to
select the BEP functions. The codes and the
functions initiated by each are listed in
Table 1.

H

~

CI

Co

L
L
L
L
H
H
H

L
L
H
H
L
L
H

L
H
L
H
L
H
L

H

H

H

Function

Compute Check Bits
Write Check Bits
Read Normal
Read High Speed
Load
Reserved
Correct Normal (Full Period
Clock Around)
Correct High Speed (Chinese
Remainder Theorem Method)

= High, L = Low
Table I. Function Select Codes

CPo Clock (input, active High). All BEP
operations are timed by this external clock
input. Any input changes must be made to the
BEP when CP is High. Data is strobed into the
BEP only during the Low-to-High transition of
CP. BEP outputs are valid only after a subsequent Low-to-High transition occurs on CP.

Do-D,. Data In (input, active High). These
eight lines are used to enter data into the BEP.
Do is the least-significant bit (LSB) position of
the input; D7 is the most-signihcant bit (MSB)
position of the input. Data entry occurs on the
Low-to-High transition of the input clock pulse.
Any change on Do-D7 must take place when
the clock pulse (CP) input is High.

EP. Error Pattern (output, active High). During an error correction process, EP is set High
to indicate that the bit pattern of the detected
error has been found. EP is set Low each time
the BEP is initialized. EP IS valid only during
the performance of a correction function; it
must be ignored at all other tImes.

ER. Error (output, active High). ER indicates
that the BEP has detected an error in the input
282

LPO-LP3. Located Error Pattern (outputs,
3-state). These four lines, together with 00-07
provide a 12-bit error pattern that is output
when REP is High. 07 is the MSB of the pattern; LPO is the LSB of the pattern. A High
level on any output line represents a logical 1;
a Low level a logical O. When no error pattern
is available (REP is Low), output lines LPO-LP3
and 00-07 are maintained in a highimpedance state.

MR. Master Reset (input, active Low). This
input controls the initialization of the BEP. Setting MR Low for a minimum period of 800 ns
initialized the BEP. The BEP must be initialized
prior to performing compute check bits, read
normal, read high-speed, and load functions.
PO-P3' Polynomial Shift Control (inputs, active
High). During correction procedures using the
Chinese remainder theorem, each syndrome
obtained by the high-speed read function is
shifted indiVidually. The PO-P3 inputs provide
this capability: Po enables the shifting of the
first syndrome, Pj shifts the second syndrome
and so on. A High on an input allows the corresponding register to shift; a Low causes it to
hold. These inputs are effective only during
the correct high-speed function. Changes on
these inputs occur only when the CP input is
High.

PM2-PMt. Pattern Match (outputs, active
High). These lines are used during a Chinese
remainder theorem error-correction operation
to indicate error-pattern match conditions for
each syndrome involved. When High, an output specihes that the corresponding syndrome
register has achieved a match.
QO-Q7' Data Out (outputs, 3-state). These
eight lines are active only during write check
bit and error correction functions. At all other
times, 00-07 are maintained at a highimpedance level. During the write check bit

Pin
Descriptions
(Continued)

function, check bIts are presented to these
hnes one byte at a tIme. 00 is the LSB and 07
is the MSB of the output. During the errorcorrectIon functIon, REP enables these lines to
carry the detected error bit pattern.
REP. Read Error Pattern (input, 3-state). REP
when High, enables lines LPO-LP3 and 00-07.
This error pattern InformatIon is valid only

after a High is indicated on the EP output durIng correction operations.

So-Sl' Polynomial Select (inputs, active High).
These two pins carry the binary codes required
to select whICh polynomial the BEP will implement. The select codes (logic levels) are given
in Table 2.

Number of
Check Blt8

Polynomial
L L

(X22 + I)(X II +X7 +X6+X+ 1)(XI2+Xll +XlO+X9+XB+X7 +X6+X5+X4+X3+X2+X+ I)
(Xll +X9+X7 +X6+X5+X+ I)

56

L H

(X21 + I)(XII +X2+ I)

32

H L

(X23+1)(XI2+Xll+XB+X7+X3+X+1l

35

H H

(XI3+ I)(X35+X23+XB+X2+ I)

48

H

= HIgh, L = Low
Table 2. Polynomial Selecl Cod..

Architecture

The BEP consIsts of four major circuit
groups: control logic, polynomial divide
matrix, register array, and status logIC. Figure
3 shows a block diagram of the BEP.
Control Logic. The control logIC CIrCUIts provide timIng, reset, polynomial selectIon, and
read error-pattern control inputs for the
remaining BEP circuits.
BaSIC timing is provided to the control logic
by clock Input CPo The control logic generates
and distributes approprIate timIng and control
signals to the remaIning BEP circuits.
Enabling the Master Reset (MR) causes the
control logic to initialize all device circuits.
ThIS operation is usually performed before the
execution of a selected deVIce function.
FunctIOn select and polynomIal select Inputs

are decoded by the control logic. The outputs
of the decoder are then used to generate the
control and timing signals needed to perform
the encoded function or to select the encoded
polynomial.
The Read Error Pattern (REP) and
Polynomial Shift Control sIgnals enable the
control logic to strobe valid error bIt pattern
outputs onto the register array output lines.
During high-speed corrections, the polynomial
shift inputs are used for register array, error
burst-pattern bit-matching operations.
Polynomial Divide Matrix. ThIS matrix connects the regIster array circuits so that each
data byte presented on hnes Do-Dz is SUitably
divided by the user-selected polynomial. The
connectIons to be made are determined by
STATUS LOGIC

1 - - - . ERROR (ER)

ZERO DETECTION
RESET {MRl - - - - - - - - ,
CLOCK (CP) _ _ _,

1 - - - . ALIGNMENT EXCEPTION (AE)

ALIGNMENT MONITOR
ERROR PAnERN DETECTOR

FUNCTION

1---. ERROR PAneRN (EP)

...---\1

PATTERN MATCH (PM4-PM2>

SELECT (C2-CO)

r-....I..-'---,.--..i-:---\
POLYNOMIAL SHIFT
CONTROL (Pa-Po) ~-~.fl

REGISTER
ARRAY

I---,---=--'/

DATA OUT

(0,-00)

POLYNOMIAL
SElECT (51-SO)

POLYNOMIAL

DIVIDE MATRIX

Figure 3. Simplified Block Diagram
2019-003

283

I
i•

Architecture
(Continued)

gating the signals supplied by the control logic
after decoding the select code on inputs So
and Sj.

Register Array. This array consists of 56 flipflop circuits used for: (1) check-bit computation during write operations, (2) syndrome
computation during read operations, and (3)
error pattern extraction during errorcorrection operations.
The bit patterns required for array functions
are provided by the polynomial divide matrix.
The array and matrix circuits, together,
simulate a serial, polynomial, feedback-shift
Condition
Detected

register arrangement in an 8-bit parallel form.
At the end of each write operation, the computed check-bit bytes are available on lines
QO-Q7' On completion of a correction operation, the bit pattern of the detected error is
available on lines LPO-LP3 and QO-Q7' Input
REP determines when a valid error bit pattern
is on the register ou tpu t lines.

Status Logic. These circuits monitor the
register array to detect the conditions listed in
Table 3 and to enable the generation of the
corresponding control signals.

Signal

Result of Polynominal DlVlslOn

ER (error) HIgh when error found; Low when no error.

Ahgnment during H-S and normal correchon

AE (alIgnment error) HIgh when error pattern IS incorrectly alIgned.

LocatIon of an error bIt pattern

EP (error pattern) HIgh when an error-bIt pattern

Pattern matching dUring H-S correchon

PM2, PM3 , PM4 (pattern match). Each sIgnal goes HIgh when ItS
correspondmg regIster matches the proper sechon of a located burst-bIt
pattern.

IS

detected.

Table 3. Status Logic. Detected Condition and Resulting Output

Functional
Description

The BEP detects and corrects data errors
using write, read, and correct operations. The
BEP operates in conjunction with external
logic: either a microprocessor or microprogrammed control circuitry. Master clock
inputs, the selection of polynomials and functions, and the output of check bytes and error
bit patterns are initiated and controlled by
inputs from external circuits. External logic is
also used to collect data, perform calculations,
and carry out the actual modification of stored
data during error-correction operations.
The BEP contains code for four standard
polynomIals (sometimes r€ferred to as Fire
codes). This code forms the basis fo the unit's
error detection and correction functions. The
polynomial to be used is selected by a coded
input from the host system'. Table 2 lists the
polynomial select codes, the equations implemented, and the number of check bits
generated by each polynomial during a write
operation. The same polynomial must be
selected for the write, read, and correction
operations performed for a given data stream.
It IS the responsibility of the host system to
keep track of which polynomial is selected for
use with each data stream.
The BEP also contains the code required to
implement each of seven functions that can be
executed during data stream write, read, and
correction operations. The function to be performed is selected by a coded input from the
host system.' The functions and their required
input code are listed in Table I.
"NOTE In the remamder of thIS speCIficatIon, external CIrCUltry
and software IS referred to as the host system.

284

Write Operation. Before data is written onto a
disk or similar storage device, the BEP must
generate and add check-bit bytes to the data to
be stored. These bytes are required for the
detection and correction of errors that may
occur during write and during subsequent
read operations.
Immediately before a write operation, the
host system must output codes to the BEP to
select the polynomial to be used and to initiate
the compute check-bit function.
The data stream to be written is entered, onthe-fly, into the BEP as it is written onto the
disk. Data is presented to the BEP as a series
of 8-bit bytes in parallel form. Check bits are
generated by dividmg each input byte by the
selected polynomial using the rules of algebra
in polynomial fields. The check bits are stored
as they are generated. Check bits are
generated in sets of 56, 48, 35, or 32 bits,
dependmg on the selected polynomial. When
the last input byte has been processed, the
write check-bit funchon is initiated by the host
system. During a check-bit write, the
generated check bits are organized into 8-bit
bytes (check-bit bytes), whICh are output byte
by byte in 8-bit parallel form on lines QO-Q7'
The host system adds these check-bit bytes to
the end of the newly written file.
The polynomial selected for data write
operations must also be used in subsequent
reads of the written data. Therefore, in selectmg a polynomial for a write operation, the
user should consider the type of read and correction functions desired for future data
retrieval operations. The relationshIps between

Functional
Description
(Continued)

the polynomials and the read and corrections
functions are:
• A read normal function must be followed by
a correct normal function. All four
polynomials can be used with this set of
reael/correction functions.
• A read high-speed function must be followed by the Chinese remamder theorem
correction function. All but the 48-bit
polynomial can be used with this set of
reael/correction functions.

Read Operations. When data is read from a
disk, the BEP checks the retrieved data and
check-bit bytes for read and write errors. If
errors are detected, the host system initiates
correction functions, retrieving from the BEP
the informatIOn needed to locate and correct
the erroneous data. Immediately before starting the read operation, the host system selects
the desired polynomial and either a read normal or a read high-speed function. Data and
associated check-bit bytes are then loaded,
byte-by-byte, into the BEP as they are read
from the disk. A divide operation results in
one or more syndromes (depending on the
polynomial used), whICh are stored in the
register array. The bmary values of these syndromes indicate whether or not an error was
present in the scanned data stream. If an error
was detected, ER is set High.
When an error condition IS indicated and
correction is desired, the host system must
inihate a correct normal, a 48-blt correct normal, or a correct high-speed function. The
function selected depends on which
polynomial and whICh read function were
selected for the imhal read operation. When
executed, the selected correction function supphes the host system with the information
needed to calculate the location of the error
pattern in the data stream and to correct the
erroneous data stream bits.
Read Normal Function. When this function is
selected, the polynomial matrix is configured
to establish the selected polynomial in its
expanded form. The input stream, data and
check bit bytes, are divided byte by byte by
the expanded polynomial. The results form a
syndrome whose bmary value is detected by
the status logIC. If the syndrome is nonzero, ER
goes High, to indicate an error condition; if
the syndrome IS zero, ER remains Low, to
indICate a no-error state.
Read High-Speed Function. This function is
selected when the correct high-speed function
IS used. All but the 48-bit polynomial can be
used with thiS function.
When selected, thiS function configures the

polynomial matrix to simultaneously divide
each byte of the input data/check-bit stream by
all factors of the selected polynomial. The
result of each factor division forms a separate
syndrome. Thus, the number of syndromes
developed depends upon the number of factors
in the selected polynomial. The status logic
monitors all syndromes and uses their combined binary values to determine if an error
condition is present. If all syndromes are zero
after the last byte of the input stream is read, a
no-error state is indicated and ER remains
Low. If any syndrome has a non-zero value, an
error condition is indicated and ER is set High.

48-Bit Polynomial. Only read normal and correct normal functions can be used when this
polynomial is selected. The read normal function for the 48-bit polynomial is performed in
the same manner as for the other polynomials.
The resulting syndrome, however, will be too
long and cannot be used directly in subsequent correct normal functions; instead, the
reciprocal of the syndrome must be established
m the BEP before the correct normal function
is selected. The host system initiates this
operation by selecting the write check-bit
function immediately after the syndrome is
formed and error is indicated. Clock pulses
are then applied to the BEP during the write
bit function to strobe the syndrome onto hnes
00-07 as SIX sequential 8-bit bytes. The host
system must then reverse the order of the syndrome bits (that IS, the original LSB becomes
the new MSB and the original MSB becomes
the new LSB) to form the reciprocal. The host
system then reloads this new syndrome into the
BEP by selecting the load function.
Load Function. This function is used only during read normal and correct normal operations
when the 48-bit polynomial is selected. The
host system selects the load function to prepare
the BEP to receive an externally-formed
reciprocal syndrome and to control the loadmg
of the syndrome bytes into the BEP. The load
function causes the register array to be configured into an 8-blt wide, 7-bit deep shift
register connected to hnes Do-D7. The host
system then presents the six syndrome bytes on
lines Do-D7. Clock pulses are then generated
to strobe the bytes mto the Shift register one at
a hme.
When all six bytes of the syndrome are
loaded, the host system causes the input hnes
to be pulled Low, then generates a seventh
clock pulse. The seventh clock pulse strobes
these Lows mto the Shift register as a zero
dummy fill byte. On completion of the load
operalion, the BEP IS ready for the correct normal function.

285

I
CIt

'tI

•
•
N

Correction
Operations

The detection of an error in a retrieved data
stream causes the following corrective functions to be performed:
1. The error burst containing the erroneous
data bits is located by the BEP.

2. Using data supplied by the BEP, the host
system calculates the exact position of the
error burst in the retrieved data stream.
3. The bit pattern of the error burst is strobed
out of the BEP and used by the host system
to perform bit correction.
Location of an Error Pattern. An error pattern is characterized by the appearance of a
known number of consecutive as in specific
registers of the register array. The exact
number of as and their locations in the register
array is unique to each polynomial. When a
polynomial is selected for read and errordetecVcorrection operations, the pattern
associated with that polynomial is loaded into
the status logic. The status logic uses this pattern to identify an error burst during the error
pattern location operations.
When only one syndrome is developed during the read error-detection function, the
error-bit pattern is located by repeatedly
dividing the syndrome by the polynomial. Division is accomplished by the repeated application of clock pulses (CP), while ignoring the
states of lines Do-D7. This operation results in
a serial bit-by-bit reconstruction of the
retrieved data stream. The generated data bits
are shifted at a rate of one per clock cycle
through the register array. The BEP status
logic performs the actual error bit pattern
detection as the data stream is reconstructed.
The status logic monitors specific registers of
the register array, and it detects a pattern of as
that matches the zero error pattern unique to
the selected polynomial, it sets EP High to indicate that an error burst was found.
When more than one syndrome is developed
during the read error-detection function, each

syndrome is divided by its associated factor
until a match condition is found for each. Each
time a match is found, the status logic enables
one of outputs PM2, PM3 or PMi. When the
total error bit pattern is found, the status logic
outputs associated with the syndromes of a
polynomial (2 or 4) are all enabled. The clock
pulses required for each factor syndrome
divide operation are supplied by lines PO-P3.
A major factor in calculating the exact location of error-burst patterns in the retrieved
data stream is the number of clock pulses used
by the BEP to detect the error-burst pattern.
The host system must record the total number
of clock pulses generated from the start of BEP
pattern-location operations to the enabling of
output EP. If necessary, this total must include
the clock pulses needed for alignment
operations.

Bit Alignment. During syndrome division, the
register array is configured into a matrix
representing an 8-bit, parallel mechanization
of a serial, polynomial division scheme. Under
certain conditions the error pattern bits
developed do not line up automatically. When
the status logic detects such a misalignment,
AE is set High. When AE is High, the BEP
switches internally into One-Bit Shift mode
during which each input clock pulse shifts the
data stream one cell through the register
array. When alignment is achieved, the status
logic sets AE Low and the BEP is switched out
of the One-Bit Shift mode. The number of shift
pulses needed to achieve alignment is an additional factor in calculating the position of the
error-bit pattern.
Uncorrectable Errors. If the total clock cycle
time needed to locate the error burst pattern is
greater than the natural period of the selected
polynomial (Table 4), an uncorrectable error
condition is indicated and the host system must
abort the correction operation.

No. of
Check Bits

Period
(Bits)

Correctable
Burst Error
Length (Bits)

(X22 + 1)(X11 +X7 +X6+X+ 1)(XI2+XII +xIO+ ...
+x+ 1)(X 11 +X9+X7 +X6+X5+X+ I)

56

585,442

II

(X21 + I)(XII +X2+ I)

32

42,987

11

(X23 + 1)(XI2+XII +X8+X7 +X3+X+ I)

35

94.185

12

(XI3+ 1)(X35+X23+X8+X2+ I)

48

13(235 -I)

7

Polynomial

Table 4. Polynomials. Checkbits. Natural Period. and Length of Error Burst

286

Correction
Operations
(Continued)

Correct Normal Function. This function must
be preceded by a read normal function. With
the exception of 4S-bit polynomial operations,
this function performs all operations needed to
construct a serial form of the retrieved data
stream and to locate the detected error burst.
The operations performed are the same as
those described previously for a singlesyndrome situation.
Computing Error Bit Pattern Locations. If no
alignment exception state is indicated (AE is
Low), the locations of the error-bit pattern
within the data stream (except when the 35-bit
polynomial is used) can be calculated by the
formula:
L = NK - SRI
Where:
L = The location (number) of the first bit in
the error burst, counting from the last check
bit in the scanned record.
N = The natural period of the selected polynomial.
K = The smallest integer needed to make this
expression positive.
RI = The total number of clock pulses input
by the BEP from the start of the find operation
until EP goes High.
If an alignment exception state is indicated
(AE is High), the location of the error-bit pattern within the data stream (except when the
35-bit polynomial is used) can be calculated
using the formula:
L = NK - SRI - R2
Where:
L,N,K, and RI are the same as described
above.
R2 = The number of clock pulses input by the
BEP between the time that AE goes High and
EP goes High.
If the 35-bit polynomial is selected, the
quantity 5 must be added in the following manner to the formulas used to calculate the location of the error-bit pattern:
L = NK - SRI + 5
and L = NK - SRI - R2 + 5

Correct Normal Function. 48-Bit Polynomial. The functions performed by the correct normal function when a 4S-bit polynomial
is selected are essentially the same as those
described for the other polynomials. The major
exception is that the location of the first bit in
the error-bit pattern is calculated using the
formula:
L = (SRI + R2) - 4S
Where:
L = The number of bit positions from the last
check bit to the nearest error burst bit.

RI = If alignment is needed, Rl is the number
of clock pulses from the start of the find operation until AE goes High. If no alignment is
needed, Rl is the total number of clock pulses
from the start of the find operation until EP
goes High.
R2 = Variable used only when an alignment is
needed; it represents the number of clock
pulses from the time AE goes High until EP
goes High.

Correct High Speed Function. This function
uses a Chinese remainder theorem to locate a
detected error-burst bit pattern. This theorem
minimizes the number of clock pulses required
for the location process, thus making it appreciably faster than the correct normal method.
The correct high-speed function must be
preceded by the read high-speed function. The
multiple syndromes developed during the read
operation are located in consecutive sets of
flip-flops in the register array. The set of flipflops containing syndromes is treated as an
individual shift register. Each syndrome shift
register is associated with the factor of the
polynomial used to develop the syndrome. For
example, the 56-bit polynomial has four factors
(see Table 2), and when selected for read and
correction operations it causes four corresponding syndromes to be developed, each housed
in an individual shift register in the register
array.

2S7

I
en

i

Correction
Operations
(Continued)

The actual location of an error-bit pattern
can be computed by the host system using the
following elements:
1. The number of clock pulses required (per
factor/syndrome register) to find the error
pattern.
2. The natural period of each factor of the
selected polynomial.
3. A predetermined constant per factor.
The formulas used to calculate error-pattern
locations for high-speed operations are
described in Table 5. Table 6 lists the predetermined constants for each factor of the
polynomials. Table 7 lists the natural period of
each factor of each polynomial.
56-Bit L = (NK) - (AIMI + A2M2 +
A3M3 + A4M4)
32-Bit L = (NK) - (AIMI + A2M2)
35-Blt L = (NK) -(AIMI + A2M2 +5)
Table 5. Correct High-Speed. Error-Burst
Location Formulas

Legend:
L = Beginning (first bit) of detected error
burst counting from the last check bit in the
processed record.

-1

ERROR BURST

~-

K = Smallest integer required to make right
side of equation positive.

N = Natural period of selected polynomial.
MI-~ = Number of clock pulses required to
achieve a match in each factor/syndrome
register.

A detected error-bit pattern can be strobed
from the BEP in l2-bit. parallel form by forcing REP High when EP goes High. The l2-bit
output is then matched bit for bit with the corresponding bits in the stored data. The errorbit pattern is then XORed with the matching
data stream bits to effect the required bit-bybit correction.
Figure 4 illustrates the format for strobing
the error bit pattern (II or 12 bits) out of the
BEP in all but the 48-bit polynomial correction
operation and shows how the pattern must be
oriented to the data stream bits. Figure 5 illustrates the format for strobing the error-bit pattern (7 bits) out of the BEP in the 48-bit
polynomial correction operation and shows
how the pattern must be oriented to the data
stream bits.

Data Stream Correction Function. Each
detected error pattern consists of 12 consecutive bits not all of which represent errors.
If the data and check-bit stream scanned during the preceding read operation was stored in
accessible memory, the error-bit pattern can
be used directly to correct the data stream.
Polynomial

Al

Predetermined Constants
~
.Aa

56 Bit

452,387

2,521,404

32 Bit

311,144

32,760

35 Bit

32,760

720,728

578,864

At

2,647,216

AI-~ =

Predetermined constants for each
factor of the selected polynomial.

288

Table 6. Chinese Remainder Theorem Coefficients

Correction
Operations

Table 7. Natural Periods lor Polynomial. and Polynomial Factors

(Continued)

Polynomial

Period
Factor I

Period
Factor 2

Period
Factor 3

Period
Factor 40

Composite
Perlod (n)

56 Bit
32 Bit
35 Bit

22
21
23

13
2047
4095

89

23

585442
42987
94185

L (COMPUTED ERROR LOCATION)
RECORD

Figure 4. Error Pattern Format lor 56-Bit. 35-Bit. and 32-Bit Polynomials

L (COMPUTED ERROR
LOCATION)

~---------------------------------------RECORD----------------~----------------------~

Figure 5. Error Pattern Format lor 48-Bit Polynomial

2078-003 2078-004

289

Timing

The overall timing requirements for BEP
operations are illustrated in Figures 6 through
13. Individual timing parameters are identified
numerically in each timing diagram and are
described in the AC Characteristics section.

Figure 8. Clock Waveform For All FUDClioDB Except
Correct Normal Or Correct High-Speed

AC
Character-

lstics·

No.

Symbol

Parameter

Clock Pulse (CP) Width (Low)
I
TwCPI
Clock Pulse Cycle Time
TcCP
2
TwCPh
Clock Pulse Width (High)
3
4
TwMRI
MR Pulse Width (Low)
5-TdMR(CP)-- MR I to CP I Time Delay-Recovery
TsDI(CP)
6
DI (Do-~) to CP I Setup Time
ThCP(DI)
CP I to DI (Do-~) Hold Time
7
TsC(CP) or
8
C(Co-C:!) or 5(50-51) to CP I Setup Time
TsS(CP)
ThCP(C) or
9
CP I to C(Co-C:!) or 5(50-51) Hold Time
ThCP(S)
10-TsC(CP) a r - - C(Co-C:!) or 5(50-51) to CP I Setup Time
TsS(CP)
TdC(Q) or
11
C(Co-C2) or S(50-~) to Q(Oo-OJ) Valid Time Delay
TdS(Q)
TdCP(Q)
CP I to Q(Oo-OJ) Invalid Time Delay
12
TdCP(Q)
CP I to Q(Oo-OJ) Valid Time Delay (write)
13
TdC(Q)
14
C(Co-C:!) to Q(Qo-OJ) Time Delay-3-state
l5-TdMR(ER) - - MR I to ER I Time Delay
TdCP(ER)
CP I to ER I Valid Time Delay
16
CP Pulse Width (Low) for Correct Functions
17
TwCPCl
TwCPCh
CP Pulse Width (High) for Correct Functions
18
CP Cycle Time for Correct Functions
19
TcCPC
20- TdC(EP) or-- C(Co-C:!) to EP or to AE Valid Time Delay
TdC(AE)
TdCP(EP) or
21
CP I to EP, to AE or to PM(PM2-P14) Valid Time Delay
TdCP(AE)
TsP(CP)
22
P(PO-P3) to CP I Setup Time
23
TdPo(EP) or
Po I to EP or to AE Time Delay
TdPo(AE)
TsC(CPC) or
24
C(Co-C2) or 5(50-51) to CP I Setup Time for Correct Functions
TsS(CPC)
25 - TdP(PM) - - - PI or P2 or P3 to Corresponding PM Output, Time Delay
TdCP(EP) or
CP I to EP, to AE, or to PM (PM2, PM3, P14) Invalid Time Delay
26
TdCP(AE) or
TdCP(PM)
27
TdPo(EP) or
Po I to EP or to AE Invalid Time Delay
TdPo(AE)
REP Pulse Width (High)
28
TwREPh
TdREP(Q) or
REP I to Q(Oo-OJ) or to LP(LPo-LP3) Time Delay
29
TdREP(LP)
30-TdREP(QT) or- REP I to Q(Oo-OJ) or to LP(LPO-LP3) TIme Delay 3-state
TdREP(LPT)
TdP(PM)
P(P1-P3) I to PM(PM2-P14) Invalid Time Delay
31
C(Co-C2) to EP, or to AE, PM(PM2-P14) Invalid Time Delay
TdC(EP) or
32
TdC(AE) or
TdC(PM)

Min

Max

(DS)

(DS)

180
400
180
800
250
350
0
400
0
180
200
0
200
100
200200
450
450
1000
250400

400
250
400
2500
0
250
150
1000
0

.. All tImmgs are prehmInary and subject to change.

290

,

2078-005

AC
Characteristics
(Continued)

'-------I:

1--:
-

-

-

-

Figure 7. Compute Check Bits or Load Function

I
CII

i•
Notes: 1. REP Input assumed low.
2. QO-Q7 outputs will be high Impedance If CO-C2 Inputs do not specify write check bits function.
Figure 8. Write Check Bits Function

ER

Note: ER output Is a function of the contents In the register array flip-flops.
Figure 9. Read Normal or Read High·Speed Function

2078-006 2078-007

2078-008

291

AC
Characteristics
\--

(Continued)

Figure 10. Clock Waveform for Correct Normal or Correct High-Speed Functions

Note 1: Assumes AE or EP output becomes active without any clocking.
Figure II. Correct Normal Function

CP

Po

~----~-+--------~~

~----------~~~------~~

EP,AE

~---------r------------~-------r--------~~

~----------~--------~~
~~----1\--

Note 2: Assumes EP, AE becomes active without clocking.
Note 3: Assumes corresponding PM output becomes active without clocking.
Figure 12. Correct High-Speed Function

I·@------II
REP_A

\ _

f--@~

@+--j

i-=----------""'}-

QO-Q7/LP..:;O_-L_P....;3:-_________

Figure 13. Read Error Pattern Timing

292

2078~009

2078-010 2078-011

2078-012

Absolute
Maximum
Ratings

Voltages on all mputs and outputs with respect
to GND ................... -0.3 V to +7.0 V
Operatmg
AmbIent
Temperature ........ See Ordering Information
Storage Temperature ......... -65 ° to + 150°C

Standard
Test
Conditions

Stresses greater than those hsted under Absolute MaxImum Ratmgs may cause permanent damage to the devICe.

ThIS IS a stress ratmg only; operatIon of the devIce at any
condItion above those mdicated In the operational sechons
of these specifIcations IS not ImplIed. Exposure to absolute
maXImum ratmg condItions for extended penods may affect

device rehabllity.

The characteristics below apply for the followmg standard test conditions, unless otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pm. Standard conditions are as follows:
•

+5V

2.2K

+4.75 V :$ Vee:$ +5.25 V

• GND = 0 V
• O°C :$ TA :$ + 70°C
Symbol

DC
Characteristics

Electrical
Characteristics

Parameter

Max

Unit

Condition

N

00
VeH

Clock Input HIgh Voltage

Vee - O.4

Vee+ 0.3

V

Dnven by external clock
generator

iCII

VeL

Clock Input Low Voltage

-0.3

0.45

V

Driven by external clock
generator

N

VIH

Input HIgh Voltage

2.0

V

VIL
VOH
VOL

Input Low Voltage
Output High Voltage

Vee+ 0.3
0.8
0.4

V

IoH =
loL=

-0.3
2.4

Output Low Voltage

V
V

Input Leakage

±10

p,A

0.4 :$ VIN :$ +2.4 V

Output Leakage

±JO

0.4 :$ VIN :$ +2.4 V

Icc

Vee Supply Current

300

p.A
rnA

Min

Max

Unit

+.8

V

Vee
0.4

V

Symbol

Parameter

VIL
VIH

Input Low Voltage

-0.5

Input HIgh Voltage

2.0

VOL
VOH

Output Low Voltage
Output High Voltage

2.4

loL

Output Leakage Current

10

IWH

Output Leakage Current

10

C IN

Input Capacitance
I/O CapacItance

15
25

p.A
pF
pF

ILL

Input Leakage Current

±10

p,A

Icc

Vee Power Supply Current

NOTE· TYPIcal values apply at TA

Product
Number

25°e and Vee

Package/
Temp
Speed

~

5.0 V.

l'J

Condition

IOH = 3.2· rnA
IOH = 400 p,A
VOUT
VOUT

= 0.4 V
= Vee

See table above for operating range.

Description

Product
Number

Package/
Temp
Speed

Description

Z8065

CE

2.5 MHz

Burst Error
Processor
(40-pin)

Z8065

PE

2.5 MHz

Burst Error
Processor
(40-pin)

Z8065

DS

2.5 MHz

Same as above

Z8065

PS

2.5 MHz

Same as above

NOTES C = CeramiC, D

00-2078-02 8085-0209

~

V
V
p.A

••
•

-250 A
+2.0 rnA

IlL
IOL

CliO

Ordering
Information

Min

= Cercilp, P =

Plastic; E

= -40°C to

+85°C, S =

aoc to 70°C

293

Z8068
Z8000™Z·DCP Data
Ciphering Processor

~
Zilog

Product
Specification

June 1982
Features

• Encrypts and decrypts data using the
National Bureau of Standards encryption
algorithm.

security and throughput by eliminating frequent reloading of keys.

• Supports three standard ciphering modes:
Electronic Code Book, Chain Block and
Cipher Feedback.

• Three separate programmable ports (master,
slave, and key data) provide hardware
separation of encrypted data, clear data,
and keys.

• Three separate registers for encryption,
decryption, and master keys improve system

• Data rates greater than 1M bytes per second
can be handled.
• Key parity check.

General
Description

The 28068 Data Ciphering Processor (DCP)
is an n-channel, silicon-gate LSI device, which
contains the circuitry to encrypt and decrypt
data using National Bureau of Standards
encryption algorithms. It is designed to be
used in a variety of environments, including
dedicated controllers, communication concentrators, terminals, and peripheral task processors in general processor systems.
The DCP provides a high throughput rate
using Cipher Feedback, Electronic Code
Book, or Cipher Block Chain operating modes.
The provision of separate ports for key input,
clear data, and enciphered data enhances
security.

The host system communicates with the DCP
using commands entered in the master port or
through auxiliary control lines. Once set up,
data can flow through the DCP at high speeds
because input, output and ciphering activities
can be performed concurrently. External DMA
control can easily be used to enhance
throughput in some system configurations.
The Z8068 DCP is designed to interface
directly to Zilog's Z-BUS@ . Device signal/pin
functions are shown in Figure 1; actual pin
number assignments are shown in Figure 2.

MASTER

PORT
(ADDRESSI

)

DATA)
SLAVE PORT {

CONTROL

AUXILIARY {
CONTROL

AUXILIARY
PORT

SLAVE
PORT
(DATA)

)

1

CONTROL I

KEY

PARITY

+5V;

elK

Figure I. Pin Functions
2080·00 I, 002

Figure 2. Pin Assignments

295

Pin
Descriptions

AFLG. Auxiliary Port Flag (output, aclive
Low). This output sIgnal Indicates that the DCP
IS expecting key data to be entered on pinS
AUXo-AUX7. ThIs can occur only when ClK is
Low and a "Load Key Through AUX Port"
command has been entered. AFLG remains
active (Low) during the Input of all eIght bytes
and will go inactive wIth the leading edge of
the eighth strobe (ASTB).

ASTB. Auxiliary Port Strobe (input, aclive
Low). In Multiplexed Control mode (C/K Low),
the rising (tralhng) edge of ASTB strobes the
key data on pins AUXo-AUX7 into the
appropriate Internal key regIster. This input is
ignored unless AFLG and C/K are both Low.
One byte of key data is entered on each ASTB
with the most signihcant byte entered first.

AUXo-AUX7' Auxiliary Port Bus (bIdIrectional,
aclive High). When the DCP is operated In
Multiplexed Control mode (C/K Low), these
eight lines form a key-byte input port, which
can be used to enter the master and session
keys. ThIS port is the only path available for
entering the master key. (Session keys can also
be entered vIa the master port.) AUXo is the
low-order bIt and is considered to be the parity
bit In key bytes. The most significant byte is
entered first.
When the DCP is operated in Direct Control
mode (C/K High), the auxiliary port's keyentry function is disabled and five of the eight
lines become direct controllstatus lines for
interfaCing to high-speed microprogrammed
controllers. In this case, AUXO, AUXj and
AU~ have no function, and the other pins are
defined as follows:

AUX2-BSY. Busy (output, active Low). This
status output gives a hardware indication that
the ciphering algorithm is in operation.
AUX2-BSY is driven by the BSY bit in the
Status register such that when the BSY bit is I
(active), AUX2-BSY is Low.

AUX3-CP, Command Pending (output, active
Low). This status output gives a hardware
indication that the DCP is ready to accept the
Input of key bytes following a Low-to-High
transition on AUX7-K/D. AUX3-CP is driven
by the CP bit in the Status register such that
when the CP bit is I (active), AUX3-CP is
Low.

Auxs-sls. Start/Stop (input, Low = Stop).
When this pin goes Low (Stop), the DCP
follows the normal Stop command sequence.
When this pin goes High, a sequence
equivalent to a Start Encryption or Start
Decryption command is followed. When
AUX5-S/S goes High, the level on AUXt,-E/D
selects either the start encryption or start
decryption operation.
AUXs-E/D. Encrypt/Decrypt (input,
Low = Decrypt). When AUX5-S/S goes High,

296

it inItiates a normal data cIphering operation
whose input speCifies whether the Ciphering
algOrithm is to encrypt (EllS HIgh) or decrypt
(EllS Low).
When AUX7-K/D goes HIgh, iniliating the
entry of key bytes, the level on AUXt,-E/D
specifies whether the bytes are to be written
into the E Key register (E/D HIgh) or the D key
Register (EllS Low).
The AUXt,-E/lS input is not latched internally
and must be held constant whenever one or
more of AUX5-S/S, AUX7-K/lS, AUX2-BSY, or
AUX3-CP are active. Fatlure to maintain the
proper level on A UXt,- EllS during loading or
ciphering operations results in scrambled data
in the internal registers.

AUX7-K/D. Key/Data (Input, Low = Data).
When this signal goes High, the DCP inItiates
a key-data input sequence as if a Load Clear E
or D Key Through Master Port command had
been entered. The level on AUXt,-E/lS determines whether the subsequently entered clearkey bytes are written into the E key register
(E/D High) or the D key register (EllS Low)
AUX7-K/lS and AUX5-S/S are mutually
exclUSIve control lines; when one goes active
(High), the other must remain inaclive (Low)
until the hrst returns to an inactive state. In
addihon, both lines must be inactive (Low)
whenever a trans ilion occurs on C/K (entering
or exiting DIrect Control mode).
C/i{. Control/Key Mode Control. (Input,
Low = Key). ThIS input determines the
operating characteristics of the DCP. A Low
input on C/K puts the DCP into the Multiplexed Control mode, enabling programmed
access to internal registers through the master
port and enabling input of keys through the
auxihary port. A High input on C/K specifies
operahon in Direct Control mode. In this
mode, several of the aUXIliary port pins
become direct control status signals which can
be driven/sensed by high-speed controller
logic, and access to internal registers through
the master port is limited to the Input or Output register.
CLK. Clock (input, TTL compatible). An external timing source is input via the CLK pin.
The Master and Slave Port Chip Select and
Data Strobe signals (MCS, MDS, SCS, SDS)
must change synchronously with this clock
input, as must Master Port Address Strobe
(MAS) in Multiplexed Control mode (C/K
Low), and also AUX7-KllS and AUX5-S/S in
Direct Control mode (C/K High). In addition,
the Auxiliary, Master and Slave Port Flag outputs (AFLG, MFLG, and SFLG) change synchronously with the clock. When using the
DCP with the Z8000 CPU in Multiplexed Control mode, the clock input must agree in frequency and phase with the processor clock;
however, the DCP does not require the high
voltage levels of the processor clock.

Pin
Descriptions
(Contmued)

MAS. Master Port Address Strobe (mput,
active Low). In Multiplexed Control mode
(C/K Low), an achve (Low) signal on this pin
indicates the presence of valid address and
chIp select informahon at the master port. This
information is latched internally on the rising
edge of Master Port Address Strobe (MAS).
When C/K is HIgh (Direct Control mode),
MAS can be HIgh or Low without affectmg
DCP operation, except that, regardless of the
state of C/K, if both Master Port Address
Strobe (MAS) and Data Strobe (MDS) are Low
simultaneously, the DCP Mode regIster will be
reset to ECB mode. The master port is
assigned to clear data, the slave port is
assigned to enable data, and all flags remain
inactive.
MCS. Master Port Chip Select (input, active
High). This signal IS used to select the master
port. In Multiplexed Control mode (C/K Low),
the level on MCS is latched internally on the
rising edge of Master Port Address Strobe
(MAS). This latched level is retained as long
as MAS is High; when MAS IS Low, the latch
becomes inviSIble and the internal signal
follows the MCS mput. In DIrect Control mode
(C/K High), no latching of Master Port Chip
Select occurs; the level on MCS is passed
dIrectly to the internal select circuitry,
regardless of the state of Address Strobe
(MAS).
MOS. Master Port Data Strobe (mput, achve
Low). When MDS is achve and Master Port
Chip Select (MCS) is valid, it indicates that
valid data is present on MPO-MP7 during output. MDS and Master Port Address Strobe
(MAS) are normally mutually exclusive; if both
go Low sImultaneously, the DCP is reset to
ECB mode and all flags remain inactive.
MFLG. Master Port Flag (output, active Low).
This flag is used to indicate the need for a data
transfer into or out of the master port during
normal Ciphering operation. Dependmg upon
the control bits written to the Mode register,
the master port is associated with either the
Input register or the Output register.
If data is to be transferred through the
master port to the Input register, the MFLG
reflects the contents of the Input register; after
any start command is entered, MFLG goes active (Low) whenever the Input register is not
full. MFLG is forced High by any command
other than a start. Conversely, if the master
port is assocIated with the Output register,
MFLG reflects the contents of the Output
register (except in single-port configuration).
MFLG goes active (Low) whenever the Output
register is not empty. In single-port configuration, MFLG reflects the contents of the Input
register, while the Slave Port Flag (SFLG) is
associated with the Output register.

MPO-MP7' Master Port Bus (input/output,
active HIgh). These eIght bidirechonallines
are used to specify internal register addresses
m Mulhplexed Control mode (see C/K) and to
mput and output data. The master port provides software access to the Status, Command
and Mode regIsters as well as the Input and
Output registers. The 3-state master port outputs are enabled only when the master port is
selected by Master Port Chip Select CMCS)
being Low, with Master Port Read/Write
(MR/W) HIgh, and strobed by a Low on the
Master Port Data Strobe (MDS). MPO is the
low-order bit. Data and key information is
entered into this port with most significant byte
input first.
MR/W. Master Port Read/Write (input,
Low = Write). ThIs sIgnal indicates to the
DCP whether the current master port operahon
is a read (MR/W is High) or a write (MRlW is
Low), thereby indicating whether data is to be
transferred from or to an internal register.
MRIW is not latched internally and must be
held stable while Master Port Data Strobe
(MDS) i,s Low.
PAR. Parity (output, active Low). The DCP
checks all key bytes for correct (odd) parity as
they are entered through either the master port
(Multiplexed or Direct Control mode) or the
auxiliary port (Multiplexed Control mode
only). If any key byte contains even parity, the
PAR bit m the Status register is set to I and
PAR goes Low. The least significant bit of key
bytes is the panty.
SCS. Slave Port Chip Select (input, active
Low). This signal is logICally combined with
Slave Port Data Strobe (SDS) to facilitate slave
port data transfers in a bus environment. SCS
is not latched internally and can be permanently tied to Low without impairing slave
port operation.
SDS. Slave Port Data Strobe (input, active
Low). When both SDS and SCS are Low, it
indicates to the DCP either that valid data is
on the SPO-SP7 lines for an input operation, or
that data is to be driven onto the SPO-SP7 lines
for output. The direction of data flow is determined by the control bits in the Mode register.
SFLG. Slave Port Flag (output, active Low).
This output indicates the status of either the
Input register or the Output register, depending on the control bits in the Mode register.
In single-port configuration, SFLG goes active
during normal processing whenever the Output register is not empty. In dual-port configuration, SFLG reflects the content of
whichever register is associated with the slave
port. If the input register is assigned to the
slave port, SFLG goes active whenever the
Input register is not full, once any of the start
commands has been entered; SFLG is forced
297

Pin
Descriptions
(Contmued)

inactive if any other command IS entered. If
the slave port is assIgned to the Output
regIster, SFLG goes active whenever the Output regIster is not empty. In this case, SFLG
goes inachve If any command is aborted.

SPO-SP7' Slave Port Bus (bidirechonal). The
slave port provides a second data input/output
interface to the DCP, allowing overlapped
Functional
Description

The overall desIgn of the DCP, as shown
in Figure 3, is optimized to achIeve hIgh data
throughput. Data bytes can be transferred
through both the master and slave ports, and
key bytes can be written through both the auxiliary and master ports. Three 8-blt buses
(input, output and C bus) carry data and key
bytes between the ports and the internal
registers. Three 56-bIt, write-only key regIsters
are provIded for the Master (M) Key, the
Encryphon (E) Key and the DecryptIOn (D)
Key. Parity checking is provIded on incommg
key bytes. Two 64-bit regIsters are provided
for imhahzmg vectors (lVE and IVD) that are
required for chained (feedback) ciphering
modes. Three 8-bit registers (Mode, Command
and Status) are accessible through the master
port.

Algorithm Processing.
The algonthm processing unit of the DCP (FIgure 3) is designed
to encrypt and decrypt data accordmg to the
National Bureau of Standards' Data Encryphon
Standard (DES), as specified in Federal Information Processing Standards Pubhcahon 46.
The DES specifies a method for encrypting
64-bit blocks of clear data ("plain text") into
corresponding 64-bit blocks of "CIpher text."

mput, output, and ciphering operations. The
3-state slave port outputs are driven only when
Slave Port ChIp Select (SCS) and Slave Port
Data Strobe (SDS) are both Low, SFLG IS 0,
and the mternal port control configuration
allows output to the slave port. SPa is the low
order bIt. The most sIgnificant byte of data
blocks IS entered or retrieved through this port
first.
The DCP offers three clphermg methods,
selected by the CIpher type field of the Mode
regIster: Electromc Code Book (ECB), Cipher
Block Chain (CBC) and CIpher Feedback
(CFB). These methods are implemented in
accordance with Federal Informahon Processing Standards, Pubhcation 46.
Electromc Code Book (ECB) is a straIghtforward implementahon of the DES: 64 bIts of
clear data m, 64 bits of cipher text out, with no
cryptographic dependence between blocks.
CIpher Block Cham (CBC) also operates on
blocks of 64 bits, but It includes a feedback
step which chams consecuhve blocks so that
repetihve data m the plain text (such as ASCII
blanks) does not yield repetitive Cipher text.
CBC also provIdes an error extension
charactenstic which protects against
fraudulent data insertions and deletions.
Cipher Feedback (CFB) is an additive
stream Cipher method in which the DES
algonthm generates a pseudorandom binary
stream, which IS then exclusive-ORed with the
clear data to form the Cipher text. The Cipher
text is then fed back to form a portion of the
next DES input block. The DCP implements
8-bit cipher feedback, with data input, output,

MUXIDIRECT J CLOCK
CONTROL

I ==---f---H-+I

MASTER
PORT
CONTROL

MASTER

KEY
OR

8

--f-'--

DATA MPO-MP7

OUTPUT BUS

PORT

I

i~~

_ _ _ _ _~INP~U~TB=U~S_ _ _~_ _~_ _ _~+-1

8

SPO-SP7
(DATA)

Figure 3. Z8068 Block Diagram

298

2080-003

Operating Modes: Multiplexed Control vs.
Direct Control. The DCP can be operated in
either of two basic interfacing modes, determined by the logic level on the clK: input pin.
In Multiplexed Control mode (C/K: Low), the
DCP is configured internally to allow a master
CPU to address five of the internal control/status/data registers directly, thereby controlling the device via mode and command
values written to these registers. Also, in this
mode, the auxiliary port is enabled for keybyte input.
If the logic level on C/K: is brought High,
the DCP enters Direct Control mode, and the
auxiliary port pins are converted into direct
hardware status or control signals capable of
instructing the DCP to perform a functionally
complete subset of its cipher processing at
very high throughputs. This operating mode is
particularly well suited for ciphering data for
high-speed peripheral devices such as
magnetic disk or tape.

AUXILIARY

PORT

~

A

~

~

-

-

~

Multiple Key Registers. The DCP provides
the necessary registers to implement a
multiple-key or master-key system. In such an
arrangement, a single master key, stored in
the DCP M key register, is used to encrypt session keys for transmissIOn to remote DES
equipment and to decrypt session keys
received from such equipment. The M Key
register may be loaded (with plain text) only
through the auxihary port, using the Load
Clear Master Key command. In addition to the
M Key register, the DCP contains two session
key registers: the E key register, used to encrypt clear text, and the D key register, used
to decrypt cipher text. All three registers are
loaded by writing commands such as Load
Clear E Key, through master port, into the
Command register, and then writing the eight
bytes of key data to the port when the Command Pending bit in the Status register is 1.

-

hgural10n bits are set to master port only
(Figure 4). In this operating configural1on, the
encrypt/decrypt bit (~) controls the processmg of data. Data to be encrypted or decrypted
is written to the master port Input register
address. To facilitate monitoring of the Input
regIster status, the MFLG signal goes Low
when the Input register is not full. Data is read
by the master CPU through the master port
Output register address. Pin SFLG goes Low
when the Output register is not empty. MFLG
is then redefined as a master input flag and
SFLG is redefined as a master output flag.

and feedback paths of one byte wide. This
method is useful for low speed, character-at-atime, serial communications.

-

Functional
Description
(Continued)

IY- 1

_____ _
MASTER KEY)

MASTER
PORT

OCP

N

ENCR;P~MA~~Ng;CRYPT r

i

KEYS, CLEAR TEXT
CIPHER TEXT

Figure 4. Single-Port Configuration. Multiplexed Control

CPU BUS

COMMANDS

ENCRYPT AND DECRYPT
KEYS CLEAR TeXT

Figure 5a. Dual-Port Configuration. Multiplexed Control

Dual Port. Master Port Clear
Configuration. In the dual-port configurations, both the master and slave ports are used
for data entry and removal (Figures 5a and
5b). In the master port clear configuration,
clear text for encryption can be entered only
through the master port, and clear text
resulting from decryption can be read only
through the master port. Cipher text can be
handled only through the slave port. The
actual direction of data flow is controlled
either by the encrypt/decrypt bit (M4) in the
Mode register or by the Start Encryption or
Start Decryption commands. If encryption is
specified, clear data will flow through the
master port to the Input register, and cipher
data will be available at the slave port when it
is ready to be read from the Output register.
For decryption, the process is reversed, with
cipher data written to the Input register

Data Flow. Bits M2 and M3 of the Mode
register control the flow of data into and out of
the DCP through the master and slave ports.
Three basic configurations are provided: one
single-port and two dual-port.
Single-Port Configuration. The simplest configuration occurs when the Mode register conSTATUS
HIGH SPEED
MICROPROGRAMMED

DEVICE

'COMMANDS,

}

AUXILIARY
PORT
DCP

r

HOST

SYSTEM

>

<

MASTER
PORT

COMMANDS

SLAVE
PORT

A

CIPHER TeXT

~

V

PERIPHERAL
DEVICE OR
BUFFER

I

ENCRYPT AND DECRYPT
KEYS CLEAR TeXT

Figure 5b. Dual-Port Configuration. Direct Control
2080-004. 005, 006

299

i

Functional
Description
(Continued)

through the master port. Slave port and clear
text read from the Master port.
In both dual-port configurations, the Master
Port Flag (MFLG) and the Slave Port Flag
(SFLG) are used to indicate the status of the
data register associated with the master port
and slave port, respectively. For example, during encryption in the master port clear configuration, MFLG goes Low (active) when the
Input register is not full; SFLG goes Low
(active) when the Output register is not empty.
If cyphering operation changes direction,
MFLG and SFLG switch their register association (see Table 1).
Mode Register Bits
Encrypt/
Port
Decrypt Configuration
Bit M4 Bit M3 Bit M2
o
0
0
o
0
1
o
1
0
1
0
0
1
0
1
0
1
1

Input
Register
Flag
MFLG
SFLG
MFLG
SFLG
MFLG
MFLG

Output
Register
Flag
SFLG
MFLG
SFLG
MFLG
SFLG
SFLG

Table 1. Association of Master Port Flag (MFLG)
and Slave Port Flag (SFLG)
with Input and Output Registers

Dual Port. Slave Port Clear Configuration.
This configuration is identical to the previously
described dual-port, master port clear configuration except that the direction of Ciphering is reversed. That is, all data flowing in or
out of the master port is cipher text, and all
data at the slave port is clear text.
Master Port Read/Write Timing. The master
port of the DCP is designed to operate directly
with a multiplexed address/data bus such as
the Zilog Z-BUS. Several features of the master
port lpgic are:
• The level on Master Port Chip Select (MCS)
is latched internally on the rising (trailing)
edge of Master Port Address Strobe (MAS).
This action relieves external address decode
circuitry of the responsibility for latching
chip select at address time.
• The levels on MP) and MP2 are also latched
internally on the rising edge of MAS and
are subsequently decoded to enable reading
and writing of the DCP's internal registers
(Mode, Command, Status, Input and Output). This action also eliminates the need for
external address latching and decoding.
• Data transfers through the master port are
controlled by the levels and transitions on
Master Port Data Strobe (MDS) and Master
Port Read/Write (MR/W). The former controls the timing and the latter controls the
transfer direction. Data transfers disturb
neither the chip-select nor address latches,

300

so once the DCP and a particular register
have been selected, any number of reads or
writes of that register can be accomplished
without intervening address cycles. This
feature greatly speeds up the loading of
keys and data, given the necessary transfer
control external to the DCP.

Loading Keys and Initializing Vector (IV)
Registers. Because the key and Initializing
Vector (IV) registers are not directly
addressable through any of the DCP's ports,
keys and vector data must be loaded (and in
the case of vectors, read) via "command data
sequences." Most of the commands recognized
by the DCP are of this type. A load or read
command is written to the Command register
through the master port. The command processor responds by asserting the Command
Pending output. The user then either writes
eight bytes of key or vector data through the
master or auxiliary port, as appropriate to the
specific command, or reads eight bytes of vector data from the master port.
In Direct Control mode, only the E Key and
D Key registers can be loaded; the M Key and
IV registers are inaccessible. Loading the E
and D Key registers is accomplished by placing the proper state on the AUXt,-E/D input
(High for E Key, Low for D Key) and then raising the AUX7-KlD input-indicating that key
loading is required. The command processor
attaches the proper key register to the master
port and asserts the AUX3-CP (Command
Pending) signal (active Low). The eight key
bytes can then be written to the master port. In
the Multiplexed Control mode, all key and
vector registers can be written to and all but
the Master (M) Key register can be loaded with
encrypted, as well as clear, data. If the operation is a Load Encrypt command, the subsequent data written to the master or auxiliary
port (as appropriate) is routed first to the Input
register and decrypted before it is written into
the speCified key or Initializing Vector
register.
Parity Checking of Keys. Key bytes contain
seven bits of key information and one parity
bit. By DES designation, the low-order bit is
the parity bit. The parity-check circuit is
enabled whenever a byte is written to one of
three key registers. The output of the paritycheck circuit is connected to PAR and the
state of this signal is reflected in Status register
bit PAR (S3). Status register bit PAR goes to 1
whenever a byte with even parity (an even
number of Is) is detected. In addilion to the
PAR bit, the Status register has a Latched Parity bit (LPAR, S4) that is set to 1 whenever the
Status register PAR bit goes to 1. Once set, the
LPAR bit is not cleared until a reset occurs or
a new Load Key command is issued.

Functional
Description
(Continued)

When an encrypted key is entered, the
parity-check logic operates only after the
decrypted key is available. The encrypted data
IS not checked for parity. The PAR signal
reflects the state of the decrypted bytes on a
byte-to-byte basis as they are clocked through

the parity-check logic on their way to the key
register. Thus, the time during which PAR
indicates the status of a byte of decrypted key
data may be as short as four clock cycles. The
LP AR bit in the Status register indicates if any
erroneous bytes of key data were entered.

Programming

Initialization. The DCP can be reset in
several ways:

Code

Hex

• By the "Software Reset" command.

Command

• By writing to the Mode register.

12

Load Clear M Key Through AUXIliary Port
Load Clear E Key Through AUXIliary Port
Load Clear D Key Through Auxiliary Port
Load Clear E Key Through Master Port
Load Clear D Key Through Master Port

• By aborting any command.
These sequences initiate the same internal
operations, except that loading the Mode
register or aborting any command does not
subsequently reset the Mode register. Once a
reset process starts, the DCP is unable to
respond to further commands for approximately five clock cycles. If a power-up hardware
reset is used, the leading edge of the reset
signal should not occur until approximately 1
ms after Vee has reached normal operating
voltage. This delay time is needed for internal
signals to stabilize.

Bl
B2
31
32

Load
Load
Load
Load

85
84
A5
A4

Load Clear lVE Through Master Port
Load Clear lVD Through Master Port
Load Encrypted lVE Through Master Port
Load Encrypted lVD Through Master Port

8D
8C
A9
A8

Read
Read
Read
Read

39
41
40
CO

Encrypt With Master Key
Start Encryption
Start Decryption
Start
Stop
Software Reset

90
91
92

• By a hardware reset, which occurs
whenever both MAS and MDS go Low
simultaneously.

11

Registers. The registers in the DCP that can
be addressed directly through the master port
are shown with their addresses in Table 2. A
brief description of these registers and those
not directly accessible follows.

EO
00

X
X
0
0
1
X
X
X

0
0
1
1
1
X
X
X

0
1
0
1
X
X
0
1

0
0
0
0
0
1
0
0

Input Register
Output RegIster
Command Register
Status Register
Mode Register
No Register Accessed
Input Register
Output Register

C/i

AUx.,-K/D

H
H
H
H
H
H
H
L

L
L
L

L
H
X

I
I
I

I
I
I

L
H
X
X
Data

L
L
L
H
Data

H
Data

N

GO
0
~
GO
N

•

•"
C"JI

Clear lVE Through Master Port
Clear lVD Through Master Port
Encrypted lVE Through Master Port
Encrypted lVD Through Master Port

Command Register. Data written to the 8-bit,
write-only Command register through the
master port is interpreted as an instruction. A
detailed description of each command is given
in the Commands section; the commands
and their hexadecimal representations are
summarized in Table 3. A subset of these
commands can be entered implicitly in Direct
Control mode (C/f( High)-even though the
Command register cannot be addressed In that
mode-by transitions on auxiliary lines
AUXs-S/S, AUXti-E/D, and AUX7-K/D. These
implicit commands are summarized in Table 4.

Table 2. Master Port Register Addresses

Pins
AUXa-ElD

E Key Through Auxiliary Port
D Key Through AUXIliary Port
E Key Through Master Port
D Key Through Master Port

Table 3. Command Codes in Multiplexed Control Mode

C/i MP2 MPI MR/W MCS Register Addressed

0
0
0
0
0
X
1
1

Encrypted
Encrypted
Encrypted
Encrypted

AUX5-S/S Command Initiated

Start Decryption
Start Encryption
Stop
Load D Key Clear through master port
Load E Key Clear through master port
End Load Key command
Not allowed
AUX pins become Key-Byte inputs

Table 4. Implicit Command Sequences in Direct Control Mode

301

Programming
(Continued)

302

Status Register. The bit assignments in the
read-only Status register are shown in Figure
6. The PAR, AFLG, SFLG and MFLG bits
indicate the status of the corresponding output
pins, as do the busy and command pending
bits when the DCP is in a Direct Control mode
(C/K High). In each case, the output signal
will be active Low when the corresponding
status bit is a I. The parity bit indicates the
parity of the most recently entered key byte.
The LP AR bit indicates whether any key byte
with even parity has been encountered since
the last Reset or Load Key command.
The Busy bit is 1 whenever the ciphering
algorithm unit is actively encrypting or
decrypting data, either as a response to a command such as Load Encrypted Key (in which
case the Command Pending bit is I) or in the
ciphering of regular text (indicated by the
Start/Stop bit being 1). If the ciphered data
cannot be transferred to the Output register
because that register still contains output from
a previous ciphering cycle, the Busy bit
remains 1 even after the ciphering is complete.
Busy is 0 at all other times, even when ciphering is not possible because data has not been
written to the Input register.
The Command Pending bit is set to 1 by any
command whose execution requires the
transfer of data to or from a nonaddressable
internal register, such as when writing key
bytes to the E key register or reading bytes
from the IVE register. Thus, the Command
Pending bit is set following all commands ex-

cept the three start commands, the Stop command and the Software Reset command. The
Command Pending bit returns to 0 after all
eight bytes have been transferred following
Load Clear, Read Clear, or Read Encrypted
commands; and after data has been transferred, decrypted, and loaded into the desired
register following Load Encrypt commands.
The Start/Stop bit is set to 1 when one of the
start commands is entered and it is reset to 0
whenever a reset occurs or when a new command other than a Start is entered.

Mode Register. Bit assignments in this 5-bit
read/write register are shown in Figure 7. The
Cipher type bits (M! and Mo) indicate to the
DCP which ciphering algorithm is to be used.
On reset, the Cipher Type mode defaults to
Electronic Code Book mode.
Configuration bits (MJ and M2) indicate
which data ports are to be associated with the
Input and Output registers and flags. When
these bits are set to the single-port, masteronly configuration (M3 M2 = 10), the slave
port is disabled and no manipulation of Slave
Port Chip Select (SCS) or Slave Data Strobe
(SDS) can result in data movement through the
slave port; all data transfers are accomplished
through the master port, as preViously
described in the Functional Description. Both
MFLG and SFLG are used in this configuration; MFLG gives the status of the Input
register and SFLG gives the status of the Output register.
When the configuration bits are set to one of
the dual-port configurations (M3 M2 = 00 or
01), both the master and slave ports are
available for input and output. When MJ,
M2 = 01 (the default configuration), the
master port handles clear data while the slave
port handles encrypted data. Configuration

M3, M2 = 00 reverses this assignment. Actual
data direction at any particular moment is controlled by the Encrypt/Decrypt bit.
The Encrypt/Decrypt bit (~) instructs the
DCP algorithm processor to encrypt or decrypt
the data from the Input register using the
ciphering method specified by the Cipher
Type bits. The Encrypt/Decrypt bit also controls data flow within the DCP. For example,
when the configuration bits are 0,1 (dual-port,
master clear, slave encrypted) and the
Encrypt/Decrypt bit is 1 (encrypt), clear data
will flow into the DCP through the master port
and encrypted data will flow out through the
slave port. When the Encrypt/Decrypt bit is set
to 0 (decrypt), data flow is reversed.

E~

MASTER PORT FLAG
o = INACTIVE
1 := ACTIVE
SLAVE PORT FLAG
= INACTIVE
1 := ACTIVE

o

AUXILIARY PORT FLAG
:= INACTIVE
1 = ACTIVE

o

PARITY (PAR)
= ODD PARITY
1 '" EVEN PARITY

o

' - - - - - - lPAR

o

= ALL BYTES HAD
ODD PARITY
1 = ONE OR MORE BYTES
HAD EVEN PARITY

' - - - - - - - BUSY

o

= NOT BUSY
1 = BUSY
' - - - - - - - - COMMAND PENDING
= INACTIVE
1 = ACTIVE

o

' - - - - - - - - - START/STOP
= STOP ENTERED
1 = START ENTERED

o

Figure 6. Status Register Bit Assignments

-, T ' "'"' "

1.1~IM51·1_1·1.IMOI
RESERVED

~

00
01
10
11

ELECTRONIC CODE BOOK (DEFAULT)
'" CIPHER FEEDBACK
CIPHER BLOCK CHAIN
'" RESERVED
=

=

PORT CONFIGURATION
00 = DUAL PORT, MASTER
ENCRYPTED, SLAVE CLEAR
01 = DUAL PORT, MASTER CLEAR,
SLAVE ENCRYPTED (DEFAULT)
10 = SINGLE PORT, MASTER ONLY
11 = RESERVED
' - - - - - - ENCRYPT/DECRYPT
1 '" ENCRYPT
o = DECRYPT

Figure 7. Mode Register Bit Assignments
2080·007, 008

Programming
(Continued)

Commands

Input Register. The 54-bIt, write-only Input
register is organized to appear to the user as
eight bytes of pushdown storage. A status circuit monitors the number of bytes that have
been stored. The register is considered empty
when the data stored in it has been or is being
processed; it is considered full when one byte
of data has been entered in Cipher Feedback
mode or when eight bytes of data have been
entered in Electronic Code Book or Cipher
Block Chain mode. If the user attempts to write
data into the Input register when it is full, the
Input register disregards the attempt; no data
in the register is destroyed.
Output Register. The 54-bit, read-only Output
register is organized to appear to the user as
eight bytes of pop-up storage. A status circuit
detects the number of bytes stored in the Output register. The register is considered empty
when all the data stored in it has been read by
the master CPU and is considered full if it still
contains one or more bytes of output data. If a
user attempts to read data from the Output
register when it is empty, the buffers driving
the output bus remam in a 3-state condition.
M, E, D Key Registers. The following
multibyte key registers cannot be addressed
directly, but are loaded in response to commands written to the Command regIster.
All operations of the DCP result from command inputs, which are entered in Multiplexed
Control mode by writing a command byte to
the Command register. Command inputs are
entered in Direct Control mode by raising and
lowering the logic levels on the AUX7-K/D,
AUXti-E/D, and AUXs-S/S pins. Table 3 shows
all commands that can be given in Multiplexed
Control mode. Table 4 shows a subset of the
implicit commands that can be executed in the
Direct Control mode.

Load Clear M Key Through Auxiliary Port
(908).
Load Clear E Key Through Auxiliary Port
(918).
Load Clear D Key Through Auxiliary Port
(928).
These commands may be used only for
multiplexed operations; they override the data
flow speCifications set in the Mode register and
cause the Master (M) Key, Encrypt (E) Key, or
Decrypt (D) Key register to be loaded with
eight bytes written to the auxiliary port. After
the Load command is written to the Command
register, the Auxiliary Port Flag (AFLG) goes
active (Low) and the corresponding bit in the
Status register (S2) becomes I, indicating that
the device is able to accept key bytes at the
auxiliary port pins. Additionally, the Command Pending bit (S6) becomes I during the
entire loading process.

There are three 54-bit, write-only key
registers in the DCP: the Master (M) Key
register, the Encrypt (E) key register, and the
Decrypt (D) key regIster. The Master key
register can be loaded only with clear data
through the auxiliary port. The Encrypt and
Decrypt Key registers can be loaded in any of
four ways: (I) as clear data through the auxihary port, (2) as clear data through the master
port, (3) as encrypted data through the auxiliary port, or (4) as encrypted data through
the master port. In the last two cases, the
encrypted data is first routed to the Input
register, decrypted using the M Key, and finally written to the target key register from the
Output register.

Initializing Vector Registers (IVE and
IVD). Two 54-bit registers are provided to
store feedback values for cipher feedback and
chained block ciphering methods. One initializing vector register (IVE) is used during
encryption, the other (IVD) is used during
decryption. Both registers can be loaded with
either clear or encrypted data through the
master port (in the latter case, the data is
decrypted before being loaded into the IV
register), and both may be read out either
clear or encrypted through the master port.

Each byte is written to its respective key
register by placmg an active Low SIgnal on the
Auxiliary Port Strobe (ASTB) once data has
been set up on the auxiliary port pins. The
actual write process occurs on the riSing (trailing) edge of ASTB. (See Switching Characteristics section for exact setup, strobe width, and
hold times.)
The Auxiliary Port Flag (AFLG) goes inactive immediately after the eighth strobe goes
active (Low). However, the Command Pending
bit (S6) remains I for several more clock
cycles, unlll the key loading process is completed. All key bytes are checked for correct
(odd) parity as they are entered.

Load Clear E Key Through Master Port
(118).
Load Clear D Key Through Master Port
(128).
These commands are available in both
Multiplexed Control and Direct Control
modes. They override the data flow specifications set in the Mode register and attach the
master port inputs to the Encrypt (E) Key or
Decrypt (D) Key register, as appropriate, until
eight key bytes have been written. In
Multiplexed Control mode, the command is
initiated by writing the Load command to the
Command register. In Direct Control mode,
the command is initiated by raising the
AUX7-K/D control input while the AUXs-S/S

303

I
i

Commands

input is Low. In this latter case, the level on

(Contmued)

AUXtl-E/15 determines which key regIster is
written (HIgh = E regIster).
Once the command has been recogmzed,
the Command Pending bit (S6 in the Status
register) becomes 1. In Direct Control mode,
AUX3-CP goes active (Low), indicating that
key entry may proceed. The host system then
writes exactly eight bytes to the master port (at
the Input register address in Mulhplexed Control mode). When the key register has been
loaded, the Command Pending bIt returns to
O. In Direct Control mode, the AUX3-CP output goes inactive, indicating that the DCP can
accept the next command.
Load Encrypted E Key Through Auxiliary
Port (BIH).
Load Encrypted 0 Key Through Auxiliary
Port (B2H).

These commands are used in Multiplexed
Control mode only. Their execution IS similar
to that of the Load Clear E (D) Key Through
Auxiliary Port command, except that key bytes
are first decrypted using the electronic code
book algorithm and the Master (M) Key
register. The key bytes are then loaded into
the appropriate key register, after having
passed through the parity-check logic.
The Command Pending bit (S6) is I during
the entire decrypt-and-Ioad operation. In addition, the Busy bit (S5) is 1 durmg the actual
decryption process.
Load Encrypted E Key Through Master Port
(3IH).
Load Encrypted 0 Key Through Master Port
(32H).

These commands are used in Multiplexed
Control mode only. Their execution is similar
in effect to that of the Load Clear E (D) Key
Through Master Port command. The commands
differ in that key bytes are initially decrypted
using the electronic code book algorithm and
the Master (M) Key register. Once decrypted,
they are loaded byte-by-byte into the target
key register, after having passed through the
parity-check logic.
The command pending bit (S6) is 1 during
the entire decrypt-and-Ioad operation. In addition, the busy bit (S5) is 1 during the actual
decryption process.
Load Clear IVE Register Through
Master Port (SSH)
Load Clear IVO Register Through
Master Port (S4H)

These commands are used in Multiplexed
Control mode only. Their execution is virtually
identical to that of the Load Clear E (or D) Key
Through Master Port command. The commands
differ in that the data written to the input
register address is routed to either the Encryption Initializing Vector (IVE) or Decryption
Initializing Vector (IVD) register instead of a
key register. No parity checking occurs. The

304

Command Pending bit (S6) is 1 during the
entire loading process.
Load Encrypted IVE Register Through
Master Port (ASH).
Load Encrypted IVO Register Through
Master Port (A4H).

These commands are analogous to the Load
Encrypted E (or D) Key Through Master Port
command. The data flow specifications set m
the Mode regIster are overridden and the eIght
vector bytes are decrypted using the Decryphon (D) Key register and the electromc code
book algorithm. The resulting clear vector
bytes are loaded into the target Initializing
Vector register. No parity checking occurs.
The Busy bit (S5) does not become I during
the decryption process, but the Command
Pending bit (S6) is 1 durmg the entire
decryption-and-Ioad operation.
Read Clear
Master Port
Read Clear
Master Port

IVE Register Through
(SOH).
IVO Register Through
(SCH).

In the Multiplexed Control mode, these commands override the data flow specifications
set in the Mode register and connect the
appropriate Initializing Vector register to the
master port at the Output register address. In
this state, each IV register appears as eight
bytes of FIFO storage. The first byte of data is
available six clocks after loading the Command register. The Command Pending bit in
the Status register remains a 1 until sometime
after the eighth byte is read out. The host
system is responsible for reading exactly eight
bytes.
Read Encrypted IVE Register Through
Master Port (A9H).
Read Encrypted IVO Register Through
Master Port (ASH).

In the Multiplexed Control mode only, these
commands override the speCifications set in
the Mode register and encrypt the contents of
the speCified Initializing Vector register using
the electronic code book algorithm and the
Encrypt (E) key. The resulting Cipher text is
placed in the output register, where it can be
read as eight bytes through the master port.
During the actual encryption process, the Busy
bit (S5) is 1. When the Busy bit becomes 0, the
encrypted vector bytes are ready to be read
out. The Command Pending bit (S6) is 1
during the entire encryption and output process; it becomes 0 when the eighth byte is read
out. The host system is responsible for reading
exactly eight bytes.
Encrypt with Master (M) Key (39H).

In the Multiplexed Control mode, this command overrides the data flow speCifications set
in the Mode register and causes the DCP to
accept eight bytes from the master port, which
are written to the Input register. When eight
bytes have been received, the DCP encrypts

Commands
(Contmued)

the input using the Master (M) Key register.
The encrypted data is loaded into the Output
register, where it can be read out through the
master port. The Command Pending bit (S6)
and the Busy (S5) bit are used as status
indicators in the three phases of this operahon.
The Command Pending bit becomes I as
soon as the Input register can accept data.
When exactly eight bytes have been entered,
the Busy bit becomes and remains I until the
encryption process is complete. When Busy
becomes 0, the encrypted data is available to
be read out. The Command Pending bit
returns to when the eighth byte has been
read.
Start Encryption (41H)
Start Decryption (40H)
Start (COH).
The three start commands begin normal data
ciphering by setting the Status register's
Start/Stop bit (S7) to 1. The Start Encryption
and Start Decryption commands explicitly
specify the ciphering direction by forcing the
Encrypt or Decrypt bit (M4) in the Mode
register to I or 0, respectively. The Start command, however, uses the current state of the
Encrypt/Decrypt bit, as speCified in a previous
Mode register load.
When a start command has been entered,
the port status flag (MFLG or SFLG) associated with the Input register becomes active
(Low), indicating that data may be written to

°

The control and/or data signals and the
Timing
Requirements timing reqUirements for clock/reset, Direct
Control mode, Multiplexed Control mode
(master port), master (slave) port read/write,
and auxiliary port key entry functions are
illustrated in Figures 8 through 12. The ac
switching characteristics of the signals
involved in the above functions are described
m the AC Characteristics. The specific timing
periods descnbed are idenhfied by numerics
(1 through 48), which are referenced in both
the hming diagrams and in the AC
CharacteristlCs.
A two-to-seven character symbol is listed in
AC Characterishcs for each penod described.
The symbol specihes the signaJ(s) involved, the
state of each signa!, and optionally, the port
associated with a signal. Symbols are encoded
as follows:
General Form: Ta Ab (Cb)

os.

Where:
(l) T is a constant.
(2) a represents anyone of the following symbols:

Symbol
c
d
f

Meaning
Clock
Delay
Fall Time

the Input register to begin ciphering.
In Direct Control mode, the Start command
is issued by raising the level on the AUX5-S/S
input (Table 4). The ciphering direction IS
speCified by the level on AUXtJ-E/D. If
AUXtJ-E/D is High when AUX5-S/S goes High,
the command is Start Encryption; if AUXtJ-E/D
is Low, it is Start Decryption.

Stop (EOH).
The Stop command clears the Start/Stop bit
(~) in the Status register. This action causes
the input flag (MFLG or SFLG) to become
ina<;:tive and inhibits the loading of any further
input into the algorithm unit. If <;:iphering is in
progress [Busy bit (S5) is I or AUX2-BSY Is
achvej, it is allowed to finish, and any data in
the Output register remains accessible.
In Direct Control mode, the Stop command
is implied when the signal level on the
AUX5-S/S input goes from High to Low
(Table 4).
Software Reset (00).
This command has the same effect as a hardware reset (MAS and MDS Low): it forces the
DCP back to its default configuration, and all
processing flags go into Inactive mode. The
default configuration includes setting the Mode
register to Electronic Code Book ciphering
mode and establishes a dual-port configuration
with master port clear and slave port
encrypted.
h
r
s
w

Hold Time
Rise Time
Setup Time
Width

(3) A,C represent any of the follOWing signal
names:

Symbol
A
B
C
D*
E
F*
G*
K
M

N
P
Q*
R
S*
W

Signal Name
Address Strobe
BSY, Busy
Clock
Data In or the address
a t the master port.
E/D, Enable/Disable
Flag (MFLG, SFLG, or
(AFLG)
Data Strobe (MDS,
SDS, or ASTB)
KID, Key/Data
CIK, Control/Key
Mode
sis, Start/Stop
PAR, Parity
Data Out (master or
~Iave port)
CP, Clock Pulse
Chip Select (master or
slave port)
MR/W, Master Port
read/write
305

I
i

(4)

Timing
Requirements
(Continued)

b represents anyone of the
following signal state descriptors (symbol).

Symbol
h
I
v
x

z

For example: Dl specifies data
in at Master Port; F2 specifies
Slave Port flag-SFLG.

State Indicated
High
Low
Valid
Invalid
High Impedance

*These signal names may be
modified by the following optional numeric port identifiers:

Identifier Port
1
2

3
Number

AC
Switching
Characteristics

Master Port
Slave Port
AUX (Key) Port

Symbol

Figure 8. Clock and Reset

Parameter

Min

Max

Notes*t

Clock
I
2
3

TwCh
TwCl
TcC

Clock Width (High)
Clock Width (Low)
Clock Cycle Time

105

105
250

Reset
MDS*MAS Low to MDS*MAS High-- TC - - - - - - - - - (Reset Pulse Width)
TdC(Glh)
Clock High to MDS*MAS High
0
50
5
Direct Control Mode
6
TsNl(Mh)
siS Low to C/K High (Setup)
2TC
7 - - TsKl(Mh) - - KID Low to C/K High (Setup) - - - - 2TC
8
TdMh(Nh)
C/K High to sis high
4TC
9
TdMh(Kh)
C/K High to KID High
4TC
4 - - TdGll(Glh) -

10
TsEv(Kh)
ElD Valid to KID High (Setup)
2TC
II--TdKh(RI) - - KID High to CP Low - - - - - - - - - - - - 200
12
ThKl(Ex)
KID Low to E/D Invalid (Hold)
TC

13
TdCl(Nh)
Clock Low to SIS Valid
80
20
14
TsEv(Hn)
Eli'S Valid to SIS High (Setup)
2TC
15--TdNh(Fll)-- SIS High to MFLG (SFLG) Low - - - - - - - - 230
(Port Input Flag)
16
TdCh(Fll)
Clock High to MFLG (SFLG) Low
230
(Port Input Flag)
17
TdCh(BI)
Clock High to BSY Low
300
18--TdCl(Bh)-- Block Low to BSY High - - - - - - - - - - - 220
19
TdCh(Fll)
Clock High to MFLG (SFLG) Low
230
(Port Output Flag)
20
TdNI(Flh)
SIS Low to MFLG (SFLG) High
230
(Port Input Flag)
Multiplexed Control Mode-Master Port
21
TwAl
MAS Width (Low)
80
22
TdWv(Ah)
MRIW Valid to MAS High
40
23
TsSll(Ah)
MCS Low to MAS High (Setup)
0
24 --ThAh(Slh) - - MAS High to MCS High (Hold)---- 60
25
TsDlv(Ah)
Address-In Valid to MAS High
55
(Address Setup Time)
ThAh(Dlx)
MAS High to Address-In Invalid
26
60
(Address Hold Time)
*

306

2

Notes referenced at end of AC CharacterlstIcs table.

2080·009

AC
Switching
Characteristics
(Contmued)

Number

Parameter

Symbol

Master (Slave) Port Read/Write
MCS (SCS) Low to MDS (SDS) Low
MDS (SDS) High to MCS (SCS) High
(Select Hold Time)
MR/W Valid to MDS Low (Setup)
TsWv(Gll)
29
30 - - ThGlh(Hwx)- MDS High to MR/W Invalid (Hold)
MDS (SDS) Low to MDS (SDS) High
TwGll(Glh)
31
Width-Write Data Read
Width-Status Register Read
32 - - TdCl(Glh)-- Clock Low to MDS (SDS) High
MDS (SDS) High to MDS (SDS) Low
TdGlh(HGIl)
33
(Data Strobe Recovery Time)
Write-Data Valid to MDS (SDS) High
TsDlr(Hlh)
34
Setup Time-Key Load
Setup Time-Data Write
Setup Time-Command/Mode
Register Write
ThGlh(Dlx)
MDS (SDS) High to Wnte-Data
35
Invalid (Hold Time-All Writes)
36 - - TdGll(Qlv)-- MDS (SDS) Low to Read-Data Valid
Read Access Time-Status Register
Read Access Time-Data
ThGlh(Qlx)
MDS (SDS) High to Read-Data Invalid
37
(Read Hold Time)
38-- TdGll(Flh)--MDS (SDS) Low to MFLG (SFLG)
High (Last Strobe)
TdGll(Rh)
MDS High to CP High
39
(Last Strobe, Key Load)
ThGl(HNl)
MDS (SDS) High to SIS Low
40
(Hold Time After Last Input Strobe)
TdGl(HPv)
MDS High to PAR Valid (Key Write)
41
27
28

TdSll(Gll)
ThGlh(Slh)

Min

Max

70
0

Notes*t

3

70
0125
155
20
125

70

200
100
100

1M

40

eft

00
C)

00

.,•
1M

155
120
80

5

t2

•

125---4-TC+280
3TC
200

* Notes referenced at end of AC Charactenstics table

eLK

I

elK

SIS

KID

EJi)

MFLG)
SFLQ INPUT PORT

IJ
MFLG ) OUTPUT PORT
SFLG

Figure 9. Control and Status Signals (Direct Control Mode)
2080-010

307

AC
Switching
Characteristics
(Contmued)

Number

Parameter

Symbol

42
43
44

TwG3
TdCI(G3h)
TdG3h(G31)

45

TsD3v(G3h)

46

ThG3h(D3x)

47
48

TdG3h(Pr)
TdG3l(F3h)

Auxiliary Port Key Entry
ASTB Low to ASTB High (WIdth)
Clock Low to ASTB High
ASTB HIgh to Next ASTB Low
(Recovery Time)
Wnte-Data Valid to ASTB High
(Data Setup Time)
ASTB High to Write-Data Invahd
(Data Hold TIme)
ASTB HIgh to PAR Vahd
ASTB Low to AFLG High
(Last Strobe)

NOTES:
All translhon tImes are assumed to be ::5 20 ns
All umts m nanoseconds (ns). All hmmgs are
prehmmary and subject to change.
I. Parameter TaCh(Fll) applles to all mput blocks except the hrst (when sis hrst goes HIgh).
2. When SIS goes machve (Low) m D,rect Control
mode, the flag assocIated WIth the mput port turns off.

Min

Max

160
20
125

70

Notes*t

200
40
200
230

3. D,rect Control mode only.
4. In C,pher Feedback mode, the port flag (MFLG or
SFLG) goes machve followmg the leadmg edge of the
hrst data strobe (MDS or SDS); m all other modes and
operatIons, the flags go mactIve on the eIghth data

strobe.

CLK

JoIAS

MCS

MP(ADI

WRITE

MRIW

Miii

MP(ADI

READ

MAlYI

Miii

Figure 10. Master Port. Multiplexed Control Mode ReadlWrite Timing

308

2080-011

AC
Switching
Characteristics
(Contmued)

eLK

SIS

MA/W

WRITE
DATA

~!~~

~~~~~~

-----------{

Figure II. Master (Slave) Port Read/Write

eLK

44

-~~------------z

____ _

J

Figure 12. Auxiliary Port Key Entry

2080-012,013

309

Ordering
Information

Product Package/
Number Temp.
Z8068
Z8068
Z8068

CE
DE
DS

Speed
4.0 MHz
4.0 MHz
4.0 MHz

Description
DCP (40-pin)
Same as above
Same as above

Product Package/
Number Temp.
Z8068
Z8068

PE
PS

Speed
4.0 MHz
4.0 MHz

Description
DCP (40-pin)
Same as above

NOTES: C ; Ceramic, D ; Cerdip, P ; PlasUc; E ; -40·C to E; +85·C, S ; O·C to 70·C.

310

00-2080-02

Z8070 Floating-Point
Software Emulation
Package

~
Zilog

Produd
Brief

June 1982

Features

• Provides high-quality, floating-point
arithmetic capability.
• Executes the same instruction set and supports the same architecture as 2ilog's 28070
Arithmetic Processing Unit (APU). The same
application software can use this emulation
package or the 28070 APU without
modification.

General
Description

Instruction
Set

The Floating-Point Software Emulator
Package provides floating-point arithmetic
capability for any of 2ilog's 28000 senes CPUs.
Floating-point instructions are coded using the
Extended Processing Architecture opcodes of
the 28000.
When the CPU encounters an EPU instruction and the Floating-Pomt Emulator is used, a
CPU Extended Instruction trap occurs and a
link is made to the emulation package. Conversely, when a 28070 APU is used, no trap
occurs and the instructions are directly executed by the APU.
Floating-point arithmetic operations are performed according to the requirements of the
proposed IEEE Standard P754 Draft 9.0. This
standard provides for:

• Provides routines for the conversion of
binary integer and Binary Coded Decimal
(BCD) to and from floating-point formats.

i

• Conforms to the proposed IEEE Standard
P754 Draft 9.0 for binary floating-point
arithmetic.

:!

1
S'

.,
-i=..

.a
• Single (32-bit), Double (64-bit), and
Extended (80-bit) precision floating-point
number formats

S'

• Addition, subtraction, multiplication, division, square-root, remainder and compare
operations
• Conversions between different floating-point
formats
• Conversions between binary integers and
floating-point numbers
• Non-numbers (NaNs) and infinity arithmetic
• Floating-pomt exceptions and their handling.

The floating-pomt instruction set consists of the
following instructions:

Load And Store Operations

Primary Anthmetic Operations

• BCD integer
• Binary integer (either rounded or truncated)

• Addition
• Subtraction

c

• Floating point

• Multiplication
• Division
• Square root
• Remainder step

311

'

Instruction
Set
(Continued)

Compare and Examine Operations

• Round to floating integer

• Compare
• Compare and raise exception if unordered

• Negate
• Truncate to integer

• Compare and transfer status to the CPU's
Flag and Control Word (FCW)

Control Operation

• Compare, transfer status to FCW, and raise
exception if unordered
• Compare with zero and transfer to FCW

• Floating-point load and store control
• Transfer selected floating-point flags to
FCW

• Compare with zero, transfer to FCW and
raise exception if unordered

• Clear floating-point flags
• Clear floating-point trap enables
• Set floating-point flags
• Set floatmg-point modes
• Set floating-point trap enables

Secondary Arithmetic Operation
• Load absolute value
• Clear
Data Types

The Floatmg-Pomt Emulator Software supports
the following data types:
SIGNIFICAND
Slftgle Precision Binary (32 bits)

.. 8.

I-I

5251
EXPONENT

SIGNIFICAND

Double Precision Binary (64 bits)

....

7978

1-\

EXPONENT

SIGNIFICAND

Double Extended PreciSion Binary (80 bits)

79

1-\

19 BCD DIGITS

Declmallnl.gar (19 BCD dlglta)

.,
8.
Binary Integer (32 and 84 bit two's complement integers)

312

00-2146-01 2146-001

Z8090
Z8000™ Z-UPC Universal
Peripheral Controller

~
Zilog

Product
Specification

June 1982

Features

• Complete slave mICrocomputer, for
distributed processmg Z-BUS use.
• 2K bytes of on-chip ROM.
• 256-byte register hie, accesSIble by both the
master CPU and Z-UPC, usmg a fall-safe
message-passing protocol.
• Three programmable I/O ports, two with
optional 2- Wire Handshake.

• SIX levels of priority mterrupts from eight
sources: SIX external sources and two internal sources.
• Two programmable 8-bit counter/timers
each with a 6-blt prescaler. Counter/Timer
TO is driven by an mternal source, and
Counter/TImer Tl can be driven by internal
or external sources. Both counter/hmers are
mdependent of program execution.

• Z8 architecture and mstruction set.

General
Description

The Z8090 Universal Peripheral Controller
(Z- UPC) is an intelligent peripheral controller
for distributed processing applications (Figure
3). The Z-UPC unburdens the host processor
by assuming tasks traditionally done by the
host (or by added hardware), such as performing arithmetic, translating or formatting data,
and controlling I/O devices. Based on the Z8

_
1

microcomputer architecture and instruction
set, the Z- UPC contains 2K bytes of internal
program ROM, a 256-byte register file, three
8-bit I/O ports, and two counter/timers.
The Z- UPC offers fast execution time; an
effective use of memory; and sophisticated
interrupt, I/O, and bit manipulation. Using a
powerful and extensive instruction set

AD '

.......... ADs

.3,
.3,

......... AD5

ADDRESSI
DATA BUS

.....-. AD4
..-...... AD3

.2,

lEI OR P30

.......... AD2

IN'f OR P3s

........ AD1
......... ADo

TIM~~:

J

- - . . RM
CONTROL

.2,
.2,

AS

AND RESET \ ----+- 55

Z8090

Z-UPC

f --. cs

1

WAIT

.,,"

WAIT
AD,
AD,
AD,
AD,

+SV--.
PCLK--.
GND

----+-

Figure 1. Pin Functions

2017-069,095

AD,
AD,
AD,

.,.

."
."
."
."."
."
."."

Figure 2. Pin Assignments

313

General
Description
(Continued)

combmed with an efficient internal addressing
scheme, the Z-UPC speeds program execution
and efficiently packs program code into the
on-chip ROM.
An important feature of the Z-UPC is an
10ternal register hIe contain1Og I/O port and
control registers accessed both by the Z-UPC
program and by Its assoCIated master CPU.
The architecture results in both byte and programming effiCIency, because Z-UPC 1Ostruchons can operate directly on I/O data without
moving it to and from an accumulator. Such a
structure allows the user to allocate as many
general-purpose registers as the application
reqUIres for data buffers between the CPU and
peripheral devICes. All general-purpose
registers can be used as address pOinters,
index registers, data buffers, or stack space.
The register hIe is logically divided into 16
groups, each consishng of 16 work1Og
registers. A Register Po1Oter IS used in conjunction with short format instruchons,
resulting 10 tight, fast code and easy task
sWitching.
Communication between the master CPU
and the register file takes place via one group
of 19 interface registers addressed directly by
both the master CPU and the Z- UPC, or via a
block transfer mechanism. Access by the
master CPU is controlled by the Z- UPC to
allow independence between the master CPU
and Z-UPC software.
The Z-UPC has 24 pins that can be dedicated to I/O functions. Grouped logically into

ADo-A'"

three 8-line ports, they can be programmed in
many combinations of input or output lines,
with or without handshake, and with push-pull
or open-drain outputs. Ports 1 and 2 are bitprogrammable; Port 3 has four fixed inputs
and four outputs.
To relieve software from coping with realtime counting and timing problems, the Z- UPC
has two 8-bit hardware counter/timers, each
with a fixed divide-by-four, and a 6-bit programmable prescaler. Various counting modes
may be selected.
In addition to the 40-pin standard configuration, the Z- UPC is available in four special
configurations:
• A 64-pin RAM development version with
external interface for up to 4K bytes of RAM
and 36 bytes of internal ROM permitting
down-loading from the master CPU.
• A Protopack RAM version with a socket for
up to 2K bytes of RAM, with 36 bytes of
internal ROM permitting down-loading from
the master CPU.
• A 54-pin ROM development version with
external interface for up to 4K bytes of ROM
and no internal ROM.
• A Protopack ROM version with a socket for
2K bytes of ROM and no internal ROM.
This range of versions and configurations
makes the Z-UPC compatible with most system
peripheral device control considerations.

HOST CPU
INTERFACE

Z·UPC MICROCOMPUTER

INTERFACE

PROGRAM
MEMORY
2K x 8

REGISTERS

-

(PART OF REGISTER
FILE)

A'

Z·BUSTO
MASTER
CPU

Riw

110

lA'

co

WAIT
REGISTER

FILE
268 )( 8

L _ _ _ _ _ ..,

iNT
INTACK
lEI
lEO

(I/O FUNCTION

IS OPTIONAL)

+5V GND peLK

Figure 3. FUDCtloDai Block Diagram

314

2017-087

Pin
Description

ADD-AD.,. Z-Bus Address/Data Lines (bidirectional). These multiplexed address and data
lines are used to transfer information between
the master CPU and the slave Z- UPC.
AS. Address Strobe (input, active Low). The
rising edge of AS initiates the beginning of a
transaction and indicates that the Address,
Status, R/W, and CS signals must be valid.
PCLK. Clock (input). TTL-compatible clock
input, 4 MHz maximum. This signal does not
need to be related to the master CPU clock.
CS. Chip Select (input, active Low). A Low on
this line during the rising edge of AS enables
the Z- UPC to accept address or data information from the bus during a master CPU write
cycle or to transmit data to the bus during a
read cycle.
DS. Data Strobe (input, active Low). DS
provides timing for data movement to the bus
master. A simultaneous Low on AS and DS
resets the Z-UPC. It is held in reset as long as
DS is Low.

Functional
Description

Address Space. On the 40-pin Z-UPC, all
address space is committed to on-chip
memory. There are 2048 bytes of maskprogrammed ROM and 256 bytes of register
file. I/O is memory-mapped to three registers
in the register file. Only the Protopack and
64-pin versions of the Z-UPC can access external program memory. See the section entitled
"Special Configurations" for complete descriptions of the Protopack and 64-pin versions.
Program Memory. Figure 4 is a map of the 2K
on-chip program ROM. Even though the architecture allows addresses from 0 to 4K, behavior of the device above program address 2047
(7FFH) is not defined. The first 12 bytes of program memory are reserved for the Z- UPC
interrupt vectors. For the Protopack and 64-pin
versions, the address space is extended to 4096
bytes. In the RAM versions, addresses OCH
through 2FH are reserved for on-chip ROM.

Pl o-P1 7• P2o-P27. P30-P37' 1/0 Port Lines
(inputs/outputs, TTL-compatible). These 24
lines are divided into three 8-bit I/O ports and
may be configured in the following ways under
program control:
P1o-P17' Port 1 (input/output-as output it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
P2o-P27. Port 2 (input/output-as output, it can
be push-pull or open-drain). Bit-programmable
Parallel I/O.
P30-P37' Port 3 (four inputs, four outputs).
Parallel I/O, handshake control, timer I/O, or
interrupt control.

R/W. Read/Write (input). This status signal
indicates that the master CPU is executing a
Read cycle if High, and a Write cycle if Low.
WAIT. Wait (output, active Low, open-drain).
When the CPU accesses the Z- UPC register
file, this signal requests the master CPU to
wait until the Z- UPC can complete its part of
the transaction.
Register File. This 256-byte file includes three
I/O port registers (l-3H), 234 general-purpose
registers (6-EEH). and 19 control. status
and special I/O registers (OH, 4H, 5H, and
FO-FFH). The functions and mnemonics
assigned to these register address locations are
shown in Figure 5. Of the 256 Z-UPC registers,
19 can be directly accessed by the master
CPU; the others are accessed indirectly via the
block transfer mechanism.

IDENTIFIER
LOCATION
STACK POINTER

SP

FEH

MASTER CPU INTERRUPT CONTROL

MIC

FDH

REGISTER POINTER

RP

FCH

PROGRAM CONTROL FLAGS

FLAGS

FBH

upe INTERRUPT MASK REGISTER

IMR

FAH

upe INTERRUPT REQUEST REGISTER

IRQ

F9H

upe INTERRUPT PRIORITY REGISTER

IPR

FaH

PORT 1 MODE

P1M

F7H

PORT 3 MODE

P3M

PORT 2 MODE

P2M

F5H

To PRESCALER

PREO

F4H

TIMER/COUNTER 0

To

F3H

T1 PRESCALER

PRE1

FOH

2047
LOCATION OF

USER

FIRST BYTE OF

ROM

INSTRUCTION

EXECUTED AFTER 'I'-,
RESET
12 ....

IRQSlOWER BYTE
lAOS UPPER BYTE

7

T,

TIMER MODE

TMR

FOH

MASTER CPU INTEIlRUPT VECTOR REG

MIV

GENERAL-PURPOSE REGISTERS

IAQ4 LOWER BYTE

IRQ4 UPPER BYTE

IRQ3 LOWER BYTE

•

IRQ3 UPPER BYTE

5

IRQ2 LOWER BYTE

5H

DATA INDIRECTION REGISTER

4

IRQ2 UPPER BYTE

4H

LIMIT COUNT REGISTER

LC

3

IRQ1l0WER BYTE

3H

PORT 3

P3

2

IRQ1 UPPER BYTE

2H

P2

1

IRoo LOWER BYTE

0

IRoo UPPER BYTE

'"

PORT 2
PORT 1
DATA TRANSFER CONTROL REGISTER

Figure 4. Program Memory Map
2017-001, 002

TIMER/COUNTER 1

F1H

F2"

EFH

11
10

•a

(Upe Side)

FFH

OH

OH

DlND

P1
DTC

Figure 5. Register File Organization

315

Functional
Description
(Continued)

The 1/0 port and control registers are
included in the register file without differentiation. This allows any Z- UPC instruction to
process 1/0 or control information, thereby
eliminating the need for special 1/0 and control instructions. All general-purpose registers
can function as accumulators, address
pointers, or index registers. In instruction execution, the registers are read when they are
defined as sources and written when defined as
destinations.
Z- UPC instructions may access registers
directly or indIrectly usmg an 8-bit address
mode or a 4-bit address mode and a Register
Pomter. For the 4-bit addressing mode, the file
is divided mto 16 working register groups,
each occupying 16 contiguous locations
(Figure 6). The Register Pointer (RP)
addresses the starting pomt of the active
workmg-register group, and the 4-blt register
deSIgnator supplied by the instruction specifies
the register within the group. Any mstruction
altering the contents of the register file can
also alter the Register POInter. The Z-UPC instruction set also has a special Set Register
Pointer (SRP) mstructlon for initializmg or
altermg the pointer contents.

Stacks. An 8-bit Stack Pointer (SP), register
R255, is used for addressing the stack,
reSIding within the 234 general-purpose
regIsters, address location 6H through EFH.
PUSH and POP instructions can save and
restore any register in the register file on the
stack. During CALL instructions, the Program
Counter is automatically saved on the stack.
Durmg Z-UPC interrupt cycles, the Program
Counter and the Flag register are automatically saved on the stack. The RET and IRET
instructions pop the saved values of the Program Counter and Flag re.gister.
01

THE 4-BIT REGISTER}
POINTER PROVIDES THE
UPPER NIBBLE OF THE

REGISTER FILE ADDRESS
FOR THE 4·81T ADDRESS
MODE.

1 1

o

75H 01110101

0 0 0

FFH
FDH
FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BOH
AFH
AOH
9FH
90H
8FH
80H
7FH
70H
8FH
60H
SFH
SOH
4FH
40H
3FH
30H
2FH
20H
1FH
10H
OFH

Ports. The Z- UPC has 24 hnes dedicated to
input and output. These are grouped into three
ports of eight lines each and can be configured under software control as inputs, outputs, or special control signals. They can be
programmed to provide Parallel 1/0 wIth or
without handshake and timing signals. All outputs can have active pullups and pulldowns,
compatible with TTL loads. In addItion, they
may be configured as open-dram outputs.

Port 1. Individual bits of Port 1 can be configured as input or output by programmmg
Port 1 Mode register (PIM) F8H. This port IS
accessed by the Z- UPC program as general
register IH. It is written by specifymg address
IH as the destmation of any instruction used to
store data m the output register. The port IS
read by specifymg address I H as the source of
an instruction.
Port 1 may be placed under handshake control by programming Port 3 Mode register
(P3M) F7H. This configures Port 3 pins P33
and P34 as handshake control lines DAV land
RDYl for input handshake, or RDYl and DAVl
for output handshake, as determined by the
direction (mput or output) assigned to bit 7 of
Port 1. The Port 3 Mode register also has a bIt
that programs Port 1 for open-dram output.

Port 2. IndivIdual bIts of Port 2 can be configured as inputs or outputs by programmmg
Port 2 Mode register (P2M) F6H. This port is
accessed by the Z- UPC program as general
register 2H, and its functions and methods of
programmmg are the same as those of Port 1.
Port 3 pms P3l and P36 are the handshake
lines DAV2 and RDY2, wIth the dIrection (mput
or output) determined by the state of bit 7 of
the port. The Port 3 Mode regIster also has a
bit used to program Port 2 for open-dram
output.
Line Direction

Function

~~!
31
P36

DAV2IRDY2
DAVI/RDYI
RDYI/DAVI
RDY2/DAV2

P31
30
P33

In
In
In

IRQ3
IRQ2
IRQI

CounteriT Imer { P31
P36

In
Out

P325
Master CPU f 3
P30
P37

Out
In
In
Out

TIN
TOUT
INT
INTACK
lEI
lEO

Out

AS

Handshake

Z·UPC Interrupt
Request'"
THE LOWER NIBBLE
OF THE REGISTER FILE

{ ADDRESS (0101) IS

Signal

In
In
Out
Out

C

r

PROVIDED BY THE
INSTRUCTION

Test Mode

P35

*P30, P31, and P33 can always be used as UPC mterrupt
request mputs, regardless of the conhgurahon
programmed.

0

Figure 6. Register Pointer Mechanism

316

Table I. Port 3 Control Functions

2017·003

Functional
Description
(Continued)

Port 3. This port can be configured as I/O or

• Nonretriggerable trigger input for the
Z-UPC internal clock diVided by four.

control lmes by programming the Port 3 Mode
register. Port 3 is accessed as general register
3H. The directions of the eight data lines are
fixed. Four lines, P30 through P33, are inputs,
and the other four, P34 through P37, are outputs. The control functions performed by Port
3 are hsted m Table l.

• External gate input for the Z- UPC mternal
clock diVided by four.

Interrupts. The Z- UPC allows SIX interrupts
from eight different sources as follows:
• Port 3 lines P30, P32, and P33.

Counter/Timers. The Z- UPC contams two
8-bit programmable counter/timers, each
driven by an mternal 6-bit programmable
prescaler.
The Tl prescaler can be driven by mternal
or external clock sources. The TO prescaler IS
driven by an internal clock source. Both
counter/timers operate independently of the
processor mstruction sequence to reheve the
program from time-critical operations like
event counting or elapsed-time calculation. TO
Prescaler register (PREO) F5H and Tl Prescaler register (PREI) F3H can be programmed
to divide the input frequency of the source
being counted by any number from I to 64. A
Counter register (F2H or F4H) is loaded with a
number from I to 256. The correspondmg
counter IS decremented from thiS number each
time the prescaler reaches end-of-count. When
the count IS complete, the counter Issues a
timer mterrupt request; IRQ4 for TO or IRQs
for Tl. Loading either counter with a number
(n) results in the mterruption of the Z- UPC at
the nth count.
The counters can be started, stopped,
restarted to contmue, or restarted from the Initial value. They can be programmed to stop
upon reachmg end-of-count (Single-Pass
mode) or to automatically reload the initial
value and continue countmg (Modulo-n Continuous mode). The counters and prescalers
can be read at any time without dlsturbmg
their values or changmg their counts. The
clock sources for both timers can be defmed as
anyone of the followmg:

• The master CPU(3).
• The two counter/hmers.
These mterrupts can be masked and globally
enabled or disabled using Interrupt Mask
Register (IMR) FBH. Interrupt Priority Register
(IPR) F9H specIfies the order of their priority.
All Z-UPC interrupts are vectored.
Table 2 hsts the Z-UPC's interrupt sources,
their types, and their vector locations in program ROM. Interrupt Request IRQo IS
dedicated to master CPU communications.
Interrupt Requests IRQI, IRQ2, and IRQ3 are
generated on the fallmg transitions of external
inputs P33, P31, and P30. Interrupt Requests
IRQ4 and IRQs are generated upon the timeout
of the Z-UPC's two counter/timers. When an
interrupt request IS granted, the Z- UPC enters
an interrupt machme cycle. This cycle disables
all subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector locahon reserved for
that mterrupt. This memory locahon and the
next byte contam the address of the mterrupt
servICe routme for that parhcular mterrupt
request.
The Z-UPC also supports polled systems. To
accommodate a polled structure, any or all of
the mterrupt inputs can be masked and the
Interrupt Request register polled to determme
whICh of the mterrupt requests needs service.
Followmg any hardware reset operation, an
EI mstruchon must be executed to enable the
settmg of any mterrupt request bit m the IRQ
register. Interrupts must be disabled prior to
changmg the content of either the IPR (F9H)
or the IMR (FBH). DI IS the only instructIOn
that should be used to globally disable
interrupts.

• Z- UPC mternal clock (4 MHz maximum)
diVided by four.
• External clock mput to Counter/Timer Tl
via P31 (l MHz maximum).
• Retriggerable trigger input for the Z- UPC
mternal clock diVided by four.

Name

IRQo
IRQj
IRQ2
IRQ3
IRQ4
IRQS

Source

EOM, XERR, LERR
DAVj,IRQj
DAV2, IRQ2, TIN
IRQ3, lEI
TO
Tl

Vector
Location

0,1
2,3
4,S
6,7
8,9
10,11

Comments

Internal (RO BIts 0, I, 2)
External (P33) I Edge TrIggered
External (P3j) I Edge Triggered
External (P30) I Edge TrIggered
Internal
Internal

Table 2. Interrupt Types, Sources, and Vector Locations

317

Functional
Description
(Continued)

Master CPU Register File Access. There are
two ways in which the master CPU can access
the Z-UPC register file: direct access and
block access.
Direct Access. Three Z-UPC registers-the
Data Transfer Control (OH), the Master Interrupt Vector (FOH), and the Master Interrupt
Control (FEH)-are mapped directly into the
master CPU address space. The master CPU
accesses these registers via the addresses
shown in Table 3.
The master CPU also has direct access to 16
registers known as the DSC (Data, Status,
Command) registers. The DSC Registers are
numbered 0 through F (DSCO-DSCF). These
registers can be any 16 contiguous register file
registers beginning on a 16-byte boundary.
The base address of the DSC register group is
designated by the IRP (110 Register POinter),
which is bits D4-D7 of the Data Transfer Control register (OH). Figure 7 shows how the
register address is made up of the 4-bit IRP
field, concatenated with the low order 4-bits of
the address from the master CPU.
Block Access. The master CPU may transmit
or receive blocks of data via address xxx10101
(xx10101x shifted). When the master CPU
accesses this address, the Z-UPC register
pointed to by the Data Indirection register is
DTC REGISTER (OH)
IRP
~

ADDRESS FROM CPU

I~I~I~I~I~I~I~I-I

I~·",rn.
I~I~I~I~I~I.I~I~I

read or written. The Data Indirection register
is incremented, and the Limit Count register is
decremented, for example, when the master
CPU issues a read or write to address
xxx 10 10 1 while the Data Indirection register
contains the value 33H. The operation causes
register 33H to be read or written and the Data
Indirection register to be incremented to 34H.
The Limit Count register (04H) is decremented and is used to control the number of
bytes to be transferred by master CPU block
accesses. If the master CPU attempts a read or
write to the Z- UPC after the Limit Count
register reaches 0, the access is not completed, the LERR bit (DI) of the Data Transfer
Control register is set (indicating a limit
error). and t.he LERR error causes an IRQo interrupt request.
The IRP field of the Data Transfer Control
register, the Data Indirection register, and the
Limit Count register are not directly accessible
to the master CPU and therefore must be set
by the Z-UPC. ThiS allows the Z-UPC to protect
itself from master CPU errors and frees the
master CPU from tracking the Z-UPC's internal
data layout.
Z-UPCAddres.
Decimal
Hex

No-Shilt
Identifier Address

xxx II 000

Shift
Address

xx II OOOx

0

OH

DTC

S
@S"

SH
@SW*

DIND
xxxlOlOl

xxlOlOlx

240

FOH

MIV

xxxi 0000

xxlOooOx

2S4

FEH

MIC

xxxII 110

xxllllOx

"n

DSCO

xxxOOOOO

xxooOoox

n+1
n+2

DSCI
DSC2

xxxOOool
xxxOoolO

xxOOOOlx
xxOOOlOx

n+3

DSC3
DSC4

xxxOOOIl

xxOOOllx

n+4

xxxOOlOO

xxOOIOOx

;o+S

DSCS

xxxoolOI

xxOOlOlx

n+6

DSC6

xxxoollO

xxoo II Ox

xxxoolli

xxoollix

n+7

DSC7

n+B

DSCB xxxOlOOO xxOIOOOx

n+9

DSC9

xxxOlOOI

xxOlOOlx

n+ 10

DSCA xxxOlOIO

xxOlOIOx

n+1I

DSCB

xxxOlOl1

xxOlOllx

n+12

xxOlIOOx

n+13

DSCC xxxOlIOO
DSCD xxxOlIOl

n+14

DSCE

xxxOlllO

xxOllIOx

n+IS

DSCF

xxx011l1

xxOllllx

xxOlIOIx

x = don't care
*n IS the value in the IRP x 16
.... Master CPU accesses the reglster address m Register 5

Figure 7. DCS Register Addressing Scheme

318

Table 3. Master CPU/Z-UPC Register Map

2017-004

Special
Configura·

tions

There are two Protopack and two 64-pin
versions of the Z-UPC. These versions are
identical to the 40-pin Z-UPC with the following exceptions:
• Internal ROM is totally omitted from the
64-pin development and ROM Protopack
versions.
• All but 36 bytes of internal ROM are omitted
from the 64-pin RAM and Protopack RAM
versions.
• The memory address and data lines are buffered and brought out to external pins or to
the socket on the Protopack.
• Control lines for the external memory are
also provided.
The 64-pin version of the Z- UPC allows the
user to prototype the system in hardware with
an actual Z- UPC device and to develop the
code intended to be mask-programmed into
the on-chip ROM of the 40-pin Z- UPC for the
production system. The 64-pin or Protopack
RAM/ROM versions of the Z- UPC are extremely versatile parts. Memory space can be
extended to 4K bytes on the 64-pin version by
using external RAM/ROM for all but 36 bytes
of the Z-UPC's memory space. This memory
can then be down-loaded from the master CPU
using a bootstrap program stored in the 36
bytes (C-2F). Figure 8 is a memory map for
the 64-pin RAM version.
FFFH

1'"'"-----------,

64·Pin and Protopack Pin Functions. Forty of
the pins on the 64-pin and Protopack versions
have functions identical to those of the 40-pin
version. The remaining 24 pins have additional
functions described below. (Figures 9 through
II show the 64-pin and Protopack versions' pin
functions and pin assignments.)
Au-All' Program Memory Address Lines (output). These lines are identical in all 64-pin and
RAM versions in the Protopack. They are used
to address 4K bytes of external Z- UPC memory.
Do-D7. Program Data (input). Data is read in
from the external memory on these lines. The
RAM version also writes external memory
-through this bus.
lACK. Interrupt Acknowledge (output, active
High). This signal is active whenever an internal Z- UPC interrupt cycle is in process.

ADDRESS'!
DATA
BUS

BUS {
TIMING
AND RESET
CONTROL {

INTERRUPT {

I!XTERNAL
RAM

PROGRAM MEMORY

EXTERNAL!
DATA

~=r------------------;
BOOTSTRAP ROM

}

INTERNAL
ROM

~~r------------------;
Z·UPC INTERRUPT
VECTORS

EXTERNAL {
CONTROL

PCLK

BXTERNAL
} RAM
+5V

~------------~

Figure I. Z-UPC RAM Version Memory Map

2017·005.006

Figure 9. ZI091/ZI092 Z-UPC Pin Functions

319

Special
Configurations
(Continued)

MAS. Memory Address Strobe (output, active
Low). This address strobe is pulsed once for
each memory fetch to interface with quasistatic RAM.
MDS. Memory Data Strobe (output, active
Low). This signal is Low during an instruction
fetch or memory write.

P3,

MR/W. Memory Read/Write (output RAM
versions only). This signal is High when the
Z- UPC is fetching an instruction and Low when
it is loading external memory.
SYNC. Instruction Sync (output, active Low).
This signal is Low during the clock cycle just
preceding an opcode fetch.

PClK

P2,

61
+5V 1

P2,

40 P3l

PClK 2

39 P36

P2,

RIW

PS1/IEO 3

38 P27

os

P30fiEI 4

37 P2&

P2,

P3s1iNf 5

36 P2s

P321INTACK 6

35 P24

P3,

AD,

057

34 P23

R/W 8

33 P22

Pl,
Z8091
Z8092

51

AS

CS

Z·UPC
Pl,

AD,

,"
0,

MAS

0,

MRIWIIACK

0,

9

32 P21

10

31 P20

GND 11

30 P3s

WAIT 12

29 P34

AD7 13

28 P11

ADs 14

27 P1&

ADs 15

26 P1s

AD4 16

25 P1 ..

AD3 17

24 P1s

AD2 18

23 P12

AD1 19

22 P11

ADo 20

21 P10

*SOCKET FOR 2716 EPROM (2K x 8) OR RAM

1--_ _ _ _•

A,

Figure 10. Z8091/ZS092 Z-UPC Pin Assignments

AddreSSing
Modes

The followmg notation is used to describe the
addressing modes and instruction operations as
shown in the mstruction summary.

RR
IRR

R

Irr

IR
Ir

Symbols

Register or workmg·register address
Working-regIster address only
Indirect~register or indIrect workmg-register
address
IndIrect workmg-reglster address only

Destmahon location or contents
Source locahon or contents
Condlbon code (see hst)
cc
@
IndIrect address prehx
SP
Stack Pomter (control regIster FFH)
PC
Program Counter
nAGS Flag register (control regIster FCH)
RP
RegIster Pomter (control regIster FDH)
1MB
Interrupt Mask regIster (control register FBH)

dst
arc

320

Figure 11. Z8093/Z8094 Protopack Pin Assignments

X
DA
RA
1M

Register paIr or workmg-register paIr address
IndIrect register pair or indIrect workmg-register
paIr address

IndIrect working-regIster palr only
Indexed address
Dlrect address
Relative address
ImmedIate

Assignment of a value IS indicated by the symbol
"-". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destmation location.· The notation "addr(n)" is used
to refer to bit "n" of a given locahon. For example,
dst (7)
refers to bit 7 of the destmahon operand.

2017·007,008

Flags

Control Register FCH contains the following six
flags:
C
Z

S
V
0
H

Condition
Codes

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adJust flag
Half-carry flag

Value

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

*
X

Meaning

Mnemonic

1000
0111
IIII
0110
1110
1101
OlOl
0100
1100
0110
1110
1001
0001
1010
0010
IIII
0111
1011
0011
0000

Affected flags are indicated by:

o

Flags Set

Always true
Carry

C
NC
2

C
C
2
2
S
S

No carry
Zero

N2

Not zero

PL

Plus

MI

Mmus

OV
NOV
EQ
NE
GE

No overflow

Equal
Not equal

GT

LE
UGE

ULT

ULE

=

a

a

Greater than or equal

(S XOR V) =

Less than
Greater than
Less than or equal
UnsIgned greater than or equal

(S XOR V) = I
[2 OR (S XOR V)j = a
[2 OR (S XOR V)j = I
C = a
C = I
(C = a AND 2 = 0)
(C OR 2) = I

UnsIgned less than
UnsIgned greater than

UGT

=

=

I

a
I
a

= I
V = I
V = a
2 = I
2 = a

Overflow

LT

=

=

UnsIgned less than or equal
Never true

Instruction
Formats

ope
dot

CCF, 01, EI, IRET, NOP,
ReF, RET, SCF

ope

INC r

One-Byte Instructions
ope

MODE
dstlsrc

OR

h 11

O!dstlsrc

ope

I

CLR, CPL, OA, DEC,
DECW, INC, INeW. POP,

ope

PUSH, RL, RLe, RR,
RRC, SRA, SWAP

MODE

OR
OR

dot

1 1 1 0
1 1 1 0

ADC, ADD, AND, CP,
LO, OR, sec, SUB,
TeM, TM, XOR

d"

JP, CALL (Indirect)

lOR 11

dot

1 1

01

oPe

dot

MODE

dot

ope

SRP

OR 11 1 1

01

d.,

VALUE

ADe, ADD, AND, CP,
LO, OR, SBC, SUB,
rCM, 1M, XOR

VALUE
MODE

ope

MODE

dot

ope

MODE
dstlsrc

dot

lD, LOE, LOEI,
LDC, LOCI

sreldst

ope
dst/src
sreldst

I

ope

".

AOC, ADO, AND,
CP, OR, SBC, SUB,
rCM, TM, XOR

OR 1110
OR 1110

ope

MODE

".

LD

dot
LD

dstlsrc
ADDRESS

OR !1 1 1

01

LD

ope

JP

DA.
DA,
LD

VALUE

ope

IdstfCCR~ ope

ope

dot

DJNZ, JR

Two-Byte Instructions

CALL

DA.
DA,

Three-Byte Instructions

321

Opcode

Lower Nibble (Hex)

Map

o
o

2

3

4

5

..

6

e"
:a"
:!!

7

:z;
~

'"'"

8

I:)

9

A

6,5

6,5

DEC

DEC

C

D

E

F

RI

IRI

II, [2

6,5

6,5

RLC

RLC

5

6

7

6,5

10,5

10,5

10,5

10,5

II,

Irz

6,5

R"RI

IR"RI

RI,IM

IRI,IM

10,5

10,5

10,5

10,5

RI

IRI

II, [2

II, II2

Rz,Rl

IR"RI

RI,!M

6,5

6,5

6,5

10,5

10,5

10,5

10,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB
IRI,IM

RI

IRI

II, [2

[1, Ir2

H2/HI

IR"RI

RI,!M

6,1

6,5

6,5

10,5

10,5

10,5

10,5

IP

SRP

SBC

SBC

SBC

SBC

SBC

SBC

IRRI

1M

II, [2

Il,IrZ

Rl,Rl

IR"RI

RI,IM

IRI,IM

8,5

8,5

6,5

6,5

10,5

10,5

10,5

10,5

DA

DA

OR

OR

OR

OR

OR

OR
IRI,IM

RI

IRI

II, [2

II, Ir2

R"RI

IR"RI

RI,IM

10,5

10,5

6,5

6,5

10,5

10,5

10,5

10,5

POP

POP

AND

AND

AND

AND

AND

AND
IRI,!M

RI

IRI

II, [2

Il,II2

R"RI

IR"RI

RI,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

RI

IRI

II, [2

ll,Iu

R"RI

IR"RI

RI,IM

IRI,IM

10112,1 12/14,1

6,5

6,5

10,5

10,5

10,5

10,5

PUSH

PUSH

TM

TM

TM

TM

TM

TM

R,

IR,

II, [2

r},Irz

R2,RI

IR"RI

RI,IM

IRt,lM

10,5

10,5

12,0

18,0

LDE

LDEI

11,Irr2

IrI,IH2

DECW DECW
IRI

6,5

6,5

RL

RL

RI

IRI

10,5

10,5

B

C

E

D

6,5

6,5

12/10,5

12110,0

6,5

12/10,0

6,5

LD

LD

DINZ

LD

IP

INC

Il,Rz

Iz,Rl

rI,RA

IR
cc,RA

[I,IM

cc,DA

rI

IRI,IM

8,0

RRI

A

F

I---

ADC ADC ADC ADC ADC ADC

6,5

12,0

18,0

LDE

LDEI
Irz/lIn

I2,

In l

IRI

r--I--I--I---

r--r---

r-6,1

DI

r-6,1

EI

6,5

10,5

10,5

r--

CP

CP

CP

CP

CP

CP

II, [2

Il,IrZ

R"RI

IR"RI

RI,IM

IRI,IM

RET

6,5

INCW INCW

10,5

10,5

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

CLR

XOR

XOR

XOR

XOR

XOR

XOR

RI

IRI

II, [2

[1, IrZ

IR"RI

RI,IM

lRI,IM

6,5

6,5

12,0

18,0

10,5

RRC

RRC

LDC

LD

RI

IRI

Il,Iu2

LDCI
Irl, Irrz

R"RI

14,0

r--16,0

IRET

I--6,5

RCF

Rz

II, X,

6,5

6,5

12,0

18,0

20,0

20,0

10,5

r--

SRA

SRA

LDC

LDCI

CALL·

CALL

LD

RI

IRI

I2, IrIl

h2/hIl

IRRI

DA

SCF

I2,

x,

6,5

6,5

10,5

10,5

10,5

10,5

RR

RR

LD

LD

LD

LD

LD

RI

IRI

Rz,Rl

IR"RI

RI,IM

IRI,IM

8,5

8,5

II,

SWAP SWAP

'-

IRI

"V
2

Irz

6,5

10,5

LD

LD

!rlf [2

R"IRI

,

'-

6,5

HI

6,5

RI

Bytes per
Instruction

4

ADD ADD ADD ADD ADD ADD

6,5

RRI

B

6,5

3

r-6,5

CCF

r--6,0

"V
3

NOP

.I

\.

~--------~~~----------~" ~ ~
2

3

Lower

Opcode
Nibble

Execution
Cycles
Upper
Opcode-A
Nibble
First
Operand

•

Pipeline
Cycles

Mnemonic

Second
Operand

Legend:
R = 8-Blt Address
r = 4-Blt Address
R 1 or r I = Dst Address
R2 or [2 = Src Address

Sequence:
Opcode, FIrst Operand, Second Operand
Note: The blank areas are not defIned.

"2-byte Instruction, fetch cycle appears as a 3-byte mstruchon

322

8085·002

Instruction
Summary

ADC dst,sre
dst- dst + sre + C

(Note I)

ID

* 0 *

LDE dst,sre
dst - sre

ADD dst,sre
dst - dst + sre

(Note I)

00

* 0 •

AND dst,sre
dst - dst AND sre

(Note I)

50

- * * 0

CALL dst
DA
SP-SP-2
IRR
@SP - PC; PC - dst
CCF
C - NOT C

D6
D4

------

OR dst,sre
dst - dst OR sre

(Note I)

40

-**0--

* - - - - -

POP ds!
dst - @SP
SP - SP + I

R
IR

50
51

------

EF

CLR dst
dst - 0

R
IR

BO
BI

COM dst
dst - NOT dst

R
IR

60
61

CP dst,sre
dst - sre

(Note I)

DA dst
dst - DA dst

R
IR

40
41

DEC dst
dst-dst-I

R
IR

DECW dst
dst-dst-I

RR
IR

dst

arc

*

Irc

r
Irr

Irr

82
92

------

LDEI dst,sre
Ir
Irr
dst - sre
r - r + I; rr-rr+1

Irr
Ir

83
93

------

NOP

FF

PUSH Bre
SP - SP-I; @SP-sre

0--

RET
PC - @SP; SP - SP + 2

AF

------

***x--

RL dst

0l6J

R
IR

90
91

00
01

-***--

RLC dst

L{i):06J
' , •

R
IR

10

80
81

-***--

RR dst

~ lc3--1 I~

EO
EI

AD

R
IR

CO
CI

8F

------

SBC dst,sre
dst- dst-sre-C

rA
r=O-F

------

(Note I)

3D

,

SCF
C-I

~~I~

rE
r=O-F
20
21

-***--

R
IR

SUB dst,sre
dst - dst - sre

RR
IR

AO
Al

-***--

IRET
BF
FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR (7) -I

* •• *.*

IP ee,dst

cD
e=O-F
30
eB
e=O-F

DA
IRR

IR ee,dst

RA

If cc IS true,
PC-PC+dst
Range: + 127, -128

LD dst,sre
dst - src

LDC dst,src
dst - src
LDCI dst, src

r
R

1m
R

r
X
r
Ir
R
R
R
IR
IR

X
r
Ir
r
R
IR
1m
1m
R

r
Irr

Irr

Ir

Irr
Ir

dst - src
Irr
r - r + 1; rr - rr + 1

•

1m
(Note I)

SWAPdst ~ R
IR

c.D
0

N
•
CI

.

* * I

DF

I - - -

DO
DI

*

31

------

20

* * I *

'It

* 0

X - -

FO
FI

X

'It

* * 0

..

TCM dst,sre
(NOT dst) AND sre

(Note I)

60

-

TM dst,sre
dst AND sre

(Note I)

70

- .. * 0

------

XOR dst,sre
dst - dst XOR sre

(Note I)

BO

------

Note I

* 0 - -

These instructIons have an identIcal set of addressmg

rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5

------

C2
D2

------

C3
D3

------

modes, whlCh are encoded for breVIty. The hrst opeode
mbble IS found m the mstruehon set table above. The
second mbble IS expressed symboheally by a 0 m th,s
table, and ItS value IS found m the followmg table to the
left of the appheable addressmg mode pair.
For example, to determme the opcode of an ADC
instructIon usmg the addressmg modes r (destmatIon) and

Ir (source) IS 13.

Addr Mode
dst

src

Lower
Opcode Nibble

rn
R

R
R

IR

Ir
R
IR
1M
1M

N

=

11

RRCdst~

SRP sre
RP - sre

If cc IS true
PC - dst

70
71
CF

------

INCW dst
dst - dst +

R
IR

RCF
C-O

- * * 0 - -

9F

INC dst
dst-dst+1

---

dst

SRA dst

EI
IMR (7) - I

Addr Mode

Instruction
and Operation

'

DINZ r,dst
RA
r - r- I
if r
0
PC-PC+dst
Range: + 127, -128

-----

Opcode Flags Allected
Byte
(Hex) CZSVDH

Addr Mode

DI
IMR (7) - 0

8085·003

Opcode Flags Allected
Byte
(Hex) CZSVDH

Instruction
and Operation

m
m

rn

lID

rn
323

..,n

Registers

11.248 PIM
Port 1 Mode Register
Z·UPC reqister address (Hex): F8

8247 PSM
Port S Mode Register
Z-UPC reqister address (Hex): F7

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

LI____ :~E~~: :~_::~~~UT
1 DEFINES liT AS INPUT

III

~:=::::=:
1 PORT 1 PULL·UPS ACTIVE

o PJIj

.. OUTPUT
1 Pas "" iNi'
RESERveD

RU8P2M
Port 2 Mode Register
Z·UPC reqister address (Hex): F6

o Pa .. INPUT
1 Pu ... 6AVi/RDV1

I~I~I~I~I~I~I~I~I

l...._ _ _ _ _ ~ =~

:

b\WR~~

'-______ =:: ::r

11-____ ~~"':~~F~~PUT

~

1 DEFINES BIT AS INPUT

UT

P34 ... OUTPUT
P34 ... RDY1/DAV1

=:: ~~~~~tJT)
P37" OUTPUT

P37 ... lEO

'--------~ ~: :U;XClK

Figure 12. Port Mod. Reglst....

R25llMR
Interrupt Mask Register
Z-UPC reqlster address (Hex): FB

11.250 IRQ
Interrupt Request Register
Z-UPC register address (Hex): FA

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

1

~m~

L IRaD. MASTER CPU COMMUNICATIONS

~~~

L'ENASLESIRQO

L-: 1 ENAIL'S IRQ1

1 ENABLES IRQ2
1 ENABLES IAas

IRQ1

= P331NPUT

IRQ2 ... P31 INPUT

IROS ... P30 INPUT
lAO. ... To

1 ENABLES IRQ4
1 !!HASLES IRQS

IAQS'" T1

RESERVED

RESERVED

1 ENAILQ INTERRUPTS

1I.2491PR
Interrupt Priority Register
Z-UPC reqister address (Hex): F9 (Write Only)
I~I~I~I~I~I~I~I~I

•__ :J \11

INTERRUPT GROUP PRIORITY
RESERVED - 000
C>A>B _ 001
A>B:>C .. 010
A>C>B 011
B>C>A 100
C>B>A 101
B>A>C .. 110
RESI:.RVED ... 111

o ...
~-'..~.-"
IRQ1 > IRQ4
1 "" IRQ4 > IRQ1

IRQO, IRQ2 PRIORITY (GROUP S)
0 = IR02 > IRoo
, ... IRQO>IRQ2

=
=
=

IR03, IRQ5 PRIORITY (GROUP A)
0 = IRQ5 > IR03
1 = IRQ3>IRQ5

Figure 13. lutenupt Coutrol Registers

8254 MIC
Malter CPU Interrupt Control Regllter
Z-UPC reqlster address (Hex): FE

11.240 MIV
Malter CPU Interrupt Vector Register
, Z-UPC reqister address (Hex): FO

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

~~

LD-

1L--_ _ VEerOR DATA (D, = LSB)

1 END OF MESSAGE

o WAIT ENABLE WHEN WRln

1 WAil DISABLE WHEN WRITE

o ENABLE LOWER CHAIN
o DISABLE DATA TRANSFER
1 DISABLE LOWER CHAIN

1 ENASLE DATA TRANSFER
o VECTO" OUTPUT
1 NO veCTOR OU1PU1
, _ _ _ _ _ _ 0 NO MASTER CPU INTERRUPT PENDING.
1 MASfI:R CPU INTERRUPT PENDING,
' -_ _ _ _ _ _ ~ ~~~:~~';.;U:D~~D::R~~~:ICE

'--------~ ::~~:=~~ :~g~=~ ~:::LL:g

,

Figure U. Master CPU luterrupt Reglst....

324

2017 -009, 010, 011

Registers

R252 FLAGS
Flag Register

R253 RP
Register Pointer

Z-UPC register address (Hex): FC

Z-UPC register address (Hex): FD

(Continued)

I~I~I~I~I~I~ID~~I

~m~
1

L

I~I~I~I~I~I~I~I~I

LUSERFLAGF1

REGISTER POINTER

USER FLAG f2

(r4-1'7)

::::::J

HALF-CARRY fLAG
DECIMAL ADJUST FLAG
SIGN FLAG

R255 SP
Stack Pointer

ZERO fLAG

Z-UPC register address (Hex): FF

OVERFLOW FLAG

CARRY FLAG

"

L:DON'TCARE

I~I~I~I~I~I~I~I~I

Figure IS. Z.UPC Control Reglate..

RODTC
Data Transfer Control Register
Z-UPC register address (Hex): 00

R4LC
Limit Count Register
Z-UPC register address (Hex): 04

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

I

LIMIT COUNT VALUE

'-------1:~~~E~255 DECIMAL

(EOM) 0
1 END OF MESSAGE
NO LIMIT ERROR

LIMIT ERROR

(XERR)

NO TRANSFER ERROR
TRANSFER ERROR

(EDX)'

DISABLE DATA TRANSFER
ENABLE DATA TRANSFER

R5DIND
Data indirection Register
Z-UPC register address (Hex): 05

10, I~ ID, ID, I~I~ ID, I~ I
...1-----:~~i;~~N

"'11"'RP:.:.)_ _ _ _ _ _ 1 If0 REGISTER POINTER

ADDRESS

Figure 18. Master CPU-Z.UPC Data Tronaler Reglate..

R241 TMR
Timer Mode Register
Z-UPC register address (Hex): Fl

R243 PREI
Prescaler I Register
Z-UPC register address (Hex): F3

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

=
=

RESERVED
00
To OUT
01
TOUTMODESj
11 OUT = 10
INTERNAL CLOCK OUT. 11

~~

~L

0 ... NO FUNCTION
1
LOAD To

=

0 = DISABLE To COUNT
1 - ENABLE To COUNT

EXTERN1~ ~~g~

INPUT _ 00

:

TRI::~= :==~~ ~~

INON.RETRtGGERABLE)
TRIGGER INPUT - 11
IRETRIGOERABLE)

0
1

=
=

NO FUNCTION
LOAD T1

0
1

=
=

DISABLE T, COUNT
ENABLE T, COUNT

COUNTMODE

o
1

= T,
= T,

SINGLE PASS
MODULO. N

CLOCK SOURCE
o
EXTERNAL TIMING INPUT
(TIN) MODE
T1 INTERNAL

1

=
=

PRESCALER MODULO
(RANGE. 1-54 DECIMAL
01-00 HEX)

R244 TO
Counter/Timer 0 Register
Z-UPC register address (Hex): F4

R242 Tl
Counter/Timer I Register
Z-UPC register address (Hex): F2

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

----l.f~=~~~-~~~~CIMAL

T11NITIAL VALUE
' - - - - - (RANGE 1-256 DECIMAL
01-00 HEX)

LI

01-00 HEX)

R245 PREO
Prescaler 0 Register
Z-UPC register address (Hex): F5
I~I~I~I~I~I~I~I~I

~

Lg~u~:s~.:'.:'c
..PASS
1 = To MODULO • N
RESERVED
PRESCALER MODULO
(RANGE 1-84 DECIMAL
01-00 HEX)

Figure 17. Z.UPC Counter/Timer Regiat...
2017-012, 013, 014

325

Registers

(Continued)

Control Register

0,

De

Ds

D4

D3

D2

Dj

Do

Comments

OOH
Data Transfer Control Register

X

X

X

X

0

0

0

0

Dlsable data transfer
from master CPU

0

0

0

Stops TO and Tl

X

0

0

Single-Pass mode

X

0

0

Single-Pass mode
External clock source

04H
L,mit Count Register

Not Defined

OSH
Data Indlrection Register

Not Defined

FOH
Interrupt Vector Register

Not Defmed

FIH
T,mer Mode

0

0

0

X

X

X

X

X

Not Defmed

F4H
Tl Reglster
FSH
Tl Prescaler

0

Not Defined

F2H
TO Register
F3H
TO Prescaler

0

X

X

X

X

X

Port 2 Imes defmed as
inputs

F6H
Port 2 Mode
F7H
Port 3 Mode

0

0

0

0

X

0

0

Port limes defined as
mputs

FBH
Port I Mode
Not Defined

F9H
Interrupt Priorlty
FAH
Interrupt Request

X

X

0

0

0

0

0

0

Reset Interrupt Request

FBH
Interrupt Mask

0

X

X

X

X

X

X

X

Interrupts disabled

0

0

0

Master CPU interrupt disapled; wait enable when
write; lower cham enabled

FCH
Flag Register

Not Defined

FDH
Register Pointer

Not Defined

FEH
Master CPU Interrupt
Control Reglster
FFH
Stack Pomter

0

0

0

0

0

Not Defmed

NOTE: X means not defmed.

Table 4. Control Register Reset Conditions

326

Port I, 2 ~n dram;
P3S = INT; P30, P31, P32,
P33 defmed as input; P34,
P%, P3-y defined as output.

Absolute
Maximum
Ratings

Standard
Test
Conditions

Voltages on all pins (except VBB)
with respect to GND .......... -0.5 V to +7.0 V
Operating Ambient
Temperature ........ See Ordermg Information
Storage Temperature ........ -65°C to + 150°C

Stresses greater than those listed under Absolute Maximum Rahngs may cause permanent damage to the device.
This IS a stress ratmg only; operahon of the devlCe at any
condition above those mdlCated m the operational sections
of these speci/icahons is not lmphed. Exposure to absolute

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:

• +4.75 V :5 VCC :5 +5.25 V
• VSS = GND = 0 V
• O°C :5 TA :5 +70°C

maXImum rating conditions for extended penods may affect

devlCe reliabihty.

"See Ordermg Information section for package
temperature range and product number.
+5V

+5V
22'

Figure 19. Test Load 2

Figure 18. Test Load I

DC
Characteristics

Symbol

Parameter

1m

Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage

Icc'

Vcc Supply Current

VCH
VCL
VIH
VIL
VOH
VOL
IlL

Min

Max

Unit

2.4
-0.3

Vcc
0.8

2.0
-0.3

Vcc
0.8

V
V
V
V
V
V
p.A
p.A
rnA

2.4
0.4

-10

10

-10

10
180

Condition

Notes

IoH = -250 p.A
IOL = +2.0 rnA

o :S
o :S

VIN :S +5.25 V
VIN :S + 5.25 V

I For AO-All and DO-D7, MDS, SYNC, MAS, and MRiW/IACK on the 54-pm verslOns IOH ~ 100 "A and 10L ~ lOrnA
"For Protopack verSIons ICC = 180 IlA plus the current for the memory

8085-0006, 0312

Ie used

327

Master CPU
Interface
TimIng

_eLK

iii
---~

Ai

AlW
(WRITE)

AIW

-------~~-----..J~+_----+--t"----i-

-::--:-++-__--'

(READ) _ _ _ _ _

ADO-AD7

MASTE:~~~

_ _ _ _ _ _""

,'--I-..::~_~~-..::::..:..:..;,:=--~:_:_------Z

12

Interrupt
Acknowledge
Timing

ADO-AD7

AS

~---------+------'~--~---M
IEI _ _ _~'-_ _ _~_~~_~~_+-

_______

~r'

_____

lEO

328

2017-015,016

No.

Symbol

TrC
2
TwCh
TIC
3
TwCI
4
5-TpC

Min

Clock Rise Time
Clock HIgh Width
Clock Fall TIme
Clock Low WIdth
Clock Period
CS to AS t Setup TIme

20
1855
20
105
1855
250-2000

TsCS(AS)
6
7
ThCS(AS)
CS to AS t Hold Time
TsA(AS)
8
Address to AS t Setup Time
ThA(AS)
9
Address to AS t Hold Hme
IO-TwAS
AS Low Width
TdDS(DR)
11
DS I to Read Data Not Valid
TdDS(DRz)
12
DS I to Read Data Float Delay
TdAS(DS)
13
AS t to DS I Delay
TdDS(AS)
14
DS t to AS I Delay
15-ThDW(DS)--Write Data to OSI Hold Time
TdDS(DR)
16
DS I to Read Data Valid Delay
TdAz(DS)
Address Float to DS Delay
17
18
TwDS
DS Low Width
TsRWR(DS)
RlW (Read) to DS I Setup Time
19
20-TsRWW(DS)-- RlW (Write) to DS I Setup Time
TsDW(DSf)
21
Write Data to DS I Setup Time
TdAS(W)
22
AS I to WAIT I Vahd Delay
ThRW(DS)
23
RlW to DS I Hold Time
TsDR(W)
24
Read Data Valid to WAIT I
25
26
27
28

TsIA(AS)
ThIA(AS)
TdAS(DSA)
TdDSA(DR)

4 MHz
Max

Parameter

INTACK to AS t Setup Time
INTACK to AS I Hold Time
AS I to DS I (lAcknowledge) Delay

DS I (Acknowledge) to Read Data Valid
Delay
29
TwDSA
OS I (Acknowledge) Low Width
30-TdAS(lEO)-- AS t to IEO Delay
31
TdIElf(IEO)
lEI to lEO Delay
TsIEI(DSA)
32
IEI to DS ! (Acknowledge) Setup Time
TdDS(lNT)
33
DS I to INT Delay
ThIEl(OS)
34
lEI to OS t Hold Time

105

0
60
30
50
70
0
60
50
30

6 MHz
Min
Max

70

Notes*t

15
1855

10
70
1855
165-2000
0
40
10
30
50
0

70
2095

40
35
20

45
2095

2

N

1--3

0
390
100
0
30
195

0
250
940

0
250
200
360

475

~

180
250

290
120
150

250
100
120

500
100

•

d
.,.,

160
40
0

500
100

NOTES
I

Parameter does not apply to Interrupt Acknowledge transactlOns

2
3

The maximum value for TdAS(DS) does not apply to Interrupt
Acknowledge transachons
This parameter 18 dependent on the state of U~C at the tIme of
master CPU access

0

N

0
250
80
0
20

60
0

!U>

" Tlmmgs are prehmmary and subject change
t Umts In nanoseconds (ns)
The jlmIng charadenshcs given reference 2 a v as High and

08VasLow.
All output de parameters use test load 1

329

Handshake
Timing

DATA IN

DAY
INPUT

RDY
OUTPUT

POAT

READ

Input Handshake

>f.~~~--~--------------D-.-T-A-O-UT-V-A-LI-D----------------------------

DATADUT _________

DAY
OUTPUT

I

RDY

\

INPUT

\
"

'-~ J

Output Handshake

Reset
Timing

\L --

RAM Version
Program
Memory
Timing

I

I--0--j

0--

~
0+

MRIW

X

ADDRESS VALID

4-

~

(RAM VERSION
ONLY)

-0-1

~ CDI-

MD.
WRITE CASE

)(

DO-D7
WRITE CASE

X

DATA VALID OUT

'i'
~

Miii
READ CASE

-----®----DO-D7
READ CASE

riM
13

iYiiC """"""'\

IRQN

330

®

.

J

-

DATA

VALID

"

IN'"

~~~
"L-J.:-...;;........:....--------------

2017-017,018,019

4 MHz
No.

Symbol

Parameter

Min

Max

6 MHz
Min

1

TsDI(DA)

Data In Setup Time

0

0

2

ThDA(DI)

Data In Hold Time

230

230

3

TwDA

Data AVailable Width

175

4

TdDAL(RY)

20
0

5

TdDAH(RY)

Data Avadable Low To Ready
Delay Time
Data Avadable High To Ready
Delay Time

0
50

20
0

TdDO(DA)

Data Out To Data Avadable
Delay Time

7

TdRY(DA)

Ready To Data Available Delay Time

0

205

Notes*t

1,2

175
175

175

1,2
2,3

150
0

1,2
2,3

50

2

150

6

Max

0

205

2

I

TdRDQ(WR)

Delay from DS t to AS t for No Reset

40

2

TdWRQ(RD)

Delay from AS t to DS

50

35

3

TwRES

Mimmum Width of AS and DS both Low
for Reset

250

250

4

1

Memory Address Strobe Width

60

55

5

2

TwMAS
TdA(MAS)

Address Vahd to Memory Address
Strobe t Delay

30

30

5

CO
0
U)
0

3

TdMR/W(MAS)

Memory Read/Write to Memory Address
Strobe t Delay

30

30

5

d•

4

TdMDS(A)

Memory Data Strobe t to Address
Change Delay

60

60

5-TDMDS(MRlW)-Memory Data Strobe t to Memory
Read/Write Not Vahd Delay

80

75

160

110

6

30

30

5

30

30

5

j

for No Reset

Tw(MDS)

Memory Data Strobe Width (Write Case)

7

TdDO(MDS)

Data Out Valid to Memory Data Strobe

8

TdMDS(DO)

Memory Data Strobe t to Data Out
Change Delay

9

Tw(MDS)

Memory Data Strobe Width (Read Case)
j

j

Delay

230

to Data In Vahd Delay

Memory Address Strobe t to Data In
Valid Delay

230

6

160

130

7-

180

220

7

11

TdMAS(DI)

12

ThMDS(DI)

Memory Data Strobe t to Data In Hold Time

0

0

13

TwSY

Instruchon Sync Out Width

160

100

14

TdSY(MDS)

InstructlOn Sync Out to Memory Data
Strobe Delay

200

160

15

TwI

Interrupt Request via Port 3 Input Width

100

100

three mput clock perIods must be added to the specIhed WIdth.
Data strobe Width varies accordmg to the mstruchon bemg

3. Output Handshake

executed

Internal reset signal
condlhon.

IS

Address strobe and data strobe to data In valid delay hmes
represent memory system access hmes and are gIven for a 4

1/2 to 2 clock delays from external reset

5. Delay hmes are speCIfIed for an Input clock frequency of 4
MHz When operatmg at a lower frequency, the Increase

6

In

mput clock period must be added to the specIfIed delay hme
Data strobe WIdth IS specified for an mput clock frequency of 4
MHz. When operatmq at a lower frequency, the mcrease III

•

n

NOTES·
1 Input Handshake
2. Test Load 1
4

N

N

6

lO-TdMDS(DI)--Memory Data Strobe

35

MHz mput frequency

Tlmmgs are prehmmary and subject to change. All tImmg refer~
ences assume 2 a v for a logiC \\1" and a 8 V for a logiC "0",
t Umts III nanoseconds (ns)
All output ac parameters use test load 2

*

331

Ordering
Information

Product
Number

Package/
Temp
Speed

Description

28090

PS

8.0 MHz

Z8000 Z-UPC
Universal
Peripheral
Controller (40-pin)

Z8090

DE

8.0 MHz

Same as above

Z8090

DS

8.0 MHz

Same as above

Z8090

CS

8.0 MHz

Same as above

28090

PE

8.0 MHz

Same as above

28090

CE

8.0 MHz

Same as above

Z8091

QS

8.0 MHz

Z8000 Z-UPC
(QUIp)
External
ROM-based
Program
Memory (64-pm)

NOTES- C = CeramlC, D == Cercilp, P = Plashc, Q

332

=

Product
Number

Pack"age/
Temp
Speed

Description

Z8092

QS

8.0 MHz

28000 Z-UPC
(QUIp)
External
RAM-based
Program
Memory (64-pm)

Z8093

RS

8.0 MHz

Z8000 Z-UPC
(Protopack)
2716 EPROM
Program Memory
(40-pm)

Z8094

RS

8.0 MHz

Z8000 Z-UPC
(Protopack)
RAM Program
Memory
(40-pin)

QUIP, E = ~40°C to +85°C, S = O°C to +70°C.

00·2017-02

Universal Peripherals

Universal Peripherals

~

Zilog

Two Versions Extend
Range of Applications
June 1982

Zilog's Universal Peripheral
Components Family is more than a
group of simple I/O circuits-they
are intelligent, fully programmable
devices capable of performing
complicated tasks independently.
Their capabihties unburden the
master CPU, reduce bus traffic,
increase system throughput, and
greatly simplify overall system
hardware design requirements.
The peripheral components,
where needed, are produced in
two versions to increase their
range of application. One version,
identified by the number Z80xx, is
capable of interfacing with Zllog's
multiplexed Z-BUS only or with
both the Z-BUS and conventional
multiplexed buses. The second version, identified by the number
Z85xx, is capable of interfacing
with conventional non-multiplexed
buses. Many of these Z85xx
peripherals will function with and
add capability to non-Zilog CPUs.
Contact your local Zilog sales
office, local distributor or
representative for additional information and detailed speCifications.
ThiS section of the data book
includes only product specifications or product briefs on the
Z85xx series of components. For
the speCifications or bnefs on the
Z80xx components refer to the
Z8000 peripherals section.
All of the peripheral components
are extensively programmable to
permit each to be tailored to Its
own application(s). All Z-BUS peripherals share common mterrupt
and bus-request structures; they
can also be operated in either
a priority-mterrupt or polled
environment.

Counting, timing, and parallel
I/O transfer problems are easily
solved using the Z8036/Z8536 CIO
CounterlTimer and 110 Unit. This
component has three 16-bit
counter/timers, three 1/0 ports,
and can double as a programmable
prionty-interrupt controller.
Data communications problems
are neatly handled by the Z80301
Z8530 SCC Serial Communications
Controller. This device is a senal,
dual-channel, multi-protocol controller which supports all popular
communications formats. The SCC
supports virtually all serial data
transfer applications.
Interface problems with the
interconnection of major components within an asynchronous,
parallel processor system can be
solved using the Z8038 Z-FIO FIFO
110 Interface Unit. This generalpurpose interface unit provides
expandable, bidirectional buffering between asynchronous CPU s m
a parallel processmg network, or
between a CPU and penpheral circuits and/or devices. The Z-FIO
can be used with systems having
either multiplexed or nonmultiplexed buses.
General-purpose control and
data manipulation problems are
easily handled by the Z8034/Z8534
UPC Universal Peripheral Con·
troller. The UPC is a complete
microcomputer designed for offline applications. This microcomputer executes the same fnendly,
capable instruction set as Zllog's Z8
microcomputer; it has three 1/0
ports, six levels of priorityinterrupt, and 2K bytes of memory
on chip. The UPC is intended for
applications that require an mtelh-

gent peripheral controller which
can assume many of the tasks normally required of the master CPU.
Two new universal peripherals
have been added to the ever
expanding line of Zilog peripherals. They are the Z8581 Clock
Generator and Controller (CGC)
and the Z8531 ASCC Asynchronous Serial Communications
Controller.
The Z8581 Clock Generator and
Controller (CGC) is a versatile
addition to Zilog's family of universal microprocessor components.
The selective clock-stretching
capabilities and variety of timmg
outputs of this device allow it to
meet the timing design requirements of various microprocessors easily, including those
of LSI and VLSI penpherals.
The outputs of the Z8581 CGC
directly dnve the Z80 and Z8000
microprocessor clock inputs. The
oscillator mput frequency reference sources can be either crystals
or TTL compatible oscillators.
To complement the Z8530lZ8030
SCC Serial Communications Controller Zilog has introduced an
asynchronous version deSignated
the Z8531 ASCC. It features two
independent 0 to 1M bit/second,
full-duplex channels each with a
seperate crystal oscillator, baud
rate generator and digital phaselocked loop for clock recovery.
The Z8581 ASCC has programmable NRZ, NRZI, or FM data
encodmg.
The LSI and VLSI components
now available can meet the deSign
needs of today, while Zilog continues to deSign state-of-the-art
deVices for the needs of tomorrow.
335

Z8530 SCC Serial
Communications
Controller

~
Zilog

Product
Specification

June 1982

Features

• Two independent, 0 to 1M biVsecond, fullduplex channels, each with a separate
crystal oscillator, baud rate generator, and
Digital Phase-Locked Loop for clock
recovery.

• Synchronous mode with internal or external
character synchronization on one or two
synchronous characters and CRC generation and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.

• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.

• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.

• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.

General
Description

The Z8530 SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with conventional non-multiplexed buses.
The SCC functions as a serial-to-parallel,
parallel-to-serial converter/controller. The
SCC can be software-configured to satisfy a

0,

TxDA

} SERIAL
DATA

0,
0,
03

eH-A

0,

CHANNEL
CONTROLS

DTR/REQA

FOR MODEM,
DMA,OR

AISA

wide variety of serial communications applications. The device contains a variety of new,
sophisticated internal functions including
on-chip baud rate generators, Digital PhaseLocked Loops, and crystal oscillators that
dramatically reduce the need for external
logic.

0,

0,

DATA BUS

• Local Loopback and Auto Echo modes.

OTHER

0,
0,

0,

0,

iNT

AD

lEO
lEI

WR
Alii

INTACK

CE

+5V

ceCA

WIREQA

TxDB
RxDS
TRxeB

WIREQB

RTxCA

SYNCe

TRxCA

CHANNEL
DTR/REQB

RISB
Z8530

sec

CTSB

Deoa

--

CONTROLS

FOR MODEM,

DMA,OR
OTHER

CH·S

DIC
GND

SYNCA

AxOA

RTxCB

Do

03
0,

TxOA
DTRIREQA

RISA

RTxCB
RxDS
TAxes

TxDB
DTA/REQB

RISB

elSA
ceCA

CTSB

PCLK

CCDS

t t t

+5V GND PCLK

Figure 1. Pin Functions

2023·00 I, 002

Figure 2. Pin Assignments

337

General
Description
(Continued)

Pin
Description

The SCC handles asynchronous formats,
Synchronous byte-oriented protocols such as
IBM Bisync, and Synchronous bit-oriented protocols such asHDLC and IBM SDLC. This versatile device supports virtually any serial data
transfer application (cassette, diskette, tape
drives, etc.).
The device can generate and check CRC
codes in any Synchronous mode and can be
programmed to check data integrity in various
modes. The SCC also has facilities for

modem contrals in both channels. In applications where these controls are not needed,
the modem controls can be used for
general-purpose 1/0.
The 2-Bus daisy-chain interrupt hierarchy is
also supported-as is standard for 2ilog
peripheral components.
The 28530 SCC is packaged in a 40-pin
ceramic DIP and uses a single + 5 V power
supply.

The follOWing section describes the pin
functions of the SCC. Figures I and 2 detail
the respective pin functions and pin
assignments.

lEO. Interrupt Enable Out (output, active

A/B. Channel A/Channel B Select (input).
This signal selects the channel in which the
read or write operation occurs.
CEo Chip Enable (input, active Low). This
signal selects the SCC for a read or write
operation.

CTSA. CTSB. Clear To Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the inputs enables the
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The SCC detects pulses on these inputs and
can interrupt the CPU on both logic level
transitions.

Die. Data/Control Select (input). This signal
defines the type of information transferred to
or from the SCC. A High means data is
transferred; a Low indicates a command.
DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accomodate slow
rise-time signals. The SCC detects pulses on
these pins and can interrupt the CPU on both
logic level transitions.
DO-~.

Data Bus (bidirectional, 3-state). These
lines carry data and commands to and from
the SCC.
DTR/REQA, DTR/REQB. Data Terminal
Ready/Request (outputs, active Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, acllve High).
lEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requestmg an interrupt.

338

High). lEO is High only if IEI is High and the
CPU is not servicing an SCC interrupt or the
SCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). IEO is connected to
the next lower priority device's IEI input and
thus inhibits interrupts from lower priority
devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
SCC requests an interrupt.

INTACK. Interrupt Acknowledge (input, active
Low). This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the
SCC interrupt daisy chain settles. When RD
becomes active, the SCC places an interrupt
vector on the data bus (if lEI is High).
!NTACK is latched by the rising edge
of PCLK.
PCLK. Clock (input). This is the master SCC
clock used to synchronize internal signals
PCLK is a TTL level signal.
RD. Read (input, active Low). This signal indicates a read operation and when the SCC is
selected, enables the SCC's bus drivers. During the Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the bus
if the SCC is the highest priority device
requesting an interrupt.

RxDA. RxDB. Receive Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.

RTxCA. RTxCB. Receive/Transmit Clocks
(inputs, active Low). These pins can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmit clock, the clock for
the baud rate generator, or the clock for the
Digital Phase-Locked Loop. These pins can
also be programmed for use with the respective SYNC pins as a crystal oscillator. The
receive clock may be I, 16,32, or 64 times the
data rate in Asynchronous modes.
RTSA, RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 11) is set, the
RTS signal goes Low. When the RTS bit is
reset in the Asynchronous mode and Auto

Pin
Description
(Continued)

Functional
Description

Enable is on, the signal goes High after the
transmitter is empty. In Synchronous mode or
in Asynchronous mode with Auto Enable off,
the RTS pin strictly follows the state of the RTS
bit. Both pins can be used as general-purpose
outputs.
SYNCA. SYNCB. Synchronization (inputs or
outputs, active Low). These pins can act either
as inputs, outputs, or part of the crystal
oscillator circuit. In the Asynchronous Receive
mode (crystal oscillator option not selected),
these pins are inputs similar to CTS and DCD.
In this mode, transitions on these lines affect
the state of the Synchronous/Hunt status bits in
Read Register 0 (Figure 10) but have no other
function.
In External Synchronization mode wllh the
crystal oscillator not selected, these lines also
act as inputs. In this mode, SYNC must be
driven Low two receive clock cycles after the
last bit in the synchronous character is
received. Character assembly begins on the
rising edge of the receive clock immediately
preceding the activation of SYNC.
In the Internal Synchronization mode
(Monosync and Bisync) with the crystal
oscillator not selected, these pins act as outputs and are active only during the part of the
receive clock cycle in which synchronous
characters are recognized. The synchronous

condition IS not latched, so these outputs are
active each hme a synchronization pattern is
recognized (regardless of character boundaries). In SDLC mode, these pins act as
outputs and are valId on receipt of a flag.

TxDA. TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.

TRxCA. TRxCB. Transmit/Receive Clocks
(inputs or outputs, achve Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmIt clock in the input mode or supply the output of the Digital Phase-Locked
Loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output
mode.

WR. Write (input, active Low). When the SCC
IS selected, thIS signal indicates a write
operation. The coincidence of RD and WR is
interpreted as a reset.

W/REQA. W/REQB. Wait/Request (outputs,
open-drain when programmed for a Wait function, driven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request lines
for a DMA controller or as Wait lines to synchronize the CPU to the SCC data rate. The
reset state is Wait.

The functional capabilities of the SCC
can be described from two different pOints
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communications protocols; as a
microprocessor peripheral, the SCC offers
valuable features such as vectored interrupts,
polling, and simple handshake capabIlity.

following description briefly detail these
protocols.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with fIve to eIght bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bits per character and Ciin
provide a break output at any time. The
receiver break-detection logic mterrupts the
CPU both at the start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection

Data Communications Capabilities. The
SCC provides two independent full-duplex
channels programmable for use m any common Asynchronous or Synchronous datacommunication protocol. Figure 3 and the

!lOP

PARITY

STt RT

~MA~R~KIN~G~L~IN~E--'I Ir-DA-TA-'I~I~I~I:I=DA=T=A=I=I~I~ILI_D_AT_A~I~I I i MARKING LINE
ASYNCHRONOUS
DATA

SYNC

~:

I

::

BISYNC

DATA

CAel

CAC2

DATA

CRC1

CRC2

DATA

CAGl

CRC2

CRG1

CRC2

MONO$VNC

SYNC

SYNC

DATA
SIGNAL

I

+
DATA

~:

EXTERNAL SYNC
FLAG

IADDRESS I

INFO~M;TION

FLAG

SDLC/HDLC/X.25

Figure 3. Some

2042·108

see Protocols

339

Functional
Description
(Continued)

mechanism that checks the signal one-half a
bit time after a Low level is detected on the
receive data input (RxDA or RxDB in
Figure I). If the Low does not persist (as In the
case of a transient), the character assembly
process does not start.
Framing errors and overrun errors are
detected and buffered together with the partial
character on which they occur. Vectored interrupts allow fast servicing or error conditions
using dedicated routines. Furthermore, a
built-in checking process avoids the interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half
a bit time to the point at which the search for
the next start bit begins.
The SCC does not require symmetric
transmit and receive clock signals-a feature
allowing use of the wide variety of clock
sources. The transmitter and receiver can
handle data at a rate of 1, 1116, 1/32, or 1/64
of the clock rate supplied to the receive and
transmit clock inputs. In Asynchronous modes,
the SYNC pin may be programmed as an input
used for functions such as monitoring a ring
indicator.
Synchronous Modes. The SCC supports both
byte-oriented and bit-oriented synchronous
communication. Synchronous byte-oriented
protocols can be handled in several modes,
allOWing character synchronization with a 6-bit
or 8-bit synchronous character (Monosync),
any 12-bit synchronization pattern (Bisync), or
with an external synchronous signal. Leading
sync characters can be removed without interrupting the CPU.
Five- or 7-bit synchronous characters are
detected with 8- or 16-bit patterns in the SCC
by overlapping the larger pattern across multiple incoming synchronous characters as shown
in Figure 4.
CRC checking for Synchronous byteoriented modes is delayed by one character
time so that the CPU may disable CRC checking on specific characters. This permits the
implementation of protocols such as
IBM Bisync.
Both CRC-16 (X16 + XIS + X2 + I) and
CCITT (X16 + XI2 + XS + 1) error checking
polynomials are supported. Either polynomial
may be selected in all Synchronous modes.
Users may preset the CRC generator and
checker to all Is or all Os. The SCC also provides a feature that automatically transmits
CRC data when no other data is available for
5 BITS
~

SYN~

I

SYNC

I

transmission. This allows for high speed
transmissions under DMA control, with no
need for CPU intervention at the end of a
message. When there is no data or CRC to
send in Synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous
characters, regardless of the programmed
character length.
The SCC supports Synchronous bit-oriented
protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion,
and CRC generation. A special command can
be used to abort a frame in transmission. At
the end of a message, the SCC automatically
transmits the CRC and trailing flag when the
transmitter underruns. The transmitter may
also be programmed to send an idle line consisting of continuous flag characters or a
steady marking condition.
If a transmit underrun occurs in the middle
of a message, an external/status interrupt
warns the CPU of this status change so that an
abort may be issued. The SCC may also be
programmed to send an abort itself in case of
an unclerrun, relieving the CPU of this task.
One to eight bits per character can be sent,
allowing reception of a message with no prior
information about the character structure in
the information field of a frame.
The receiver automatically acquires synchronization on the leading flag of a frame in
SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can
also be programmed). The receiver can be
programmed to search for frames addressed by
a single byte (or four bits within a byk) of a
user-selected address or to a global broadcast
address. In this mode, frames not matching
either the user-selected or broadcast address
are ignored. The number of address bytes can
be extended under software control. For
receiving data, an interrupt on the first
received character, or an interrupt on every
character, or on special condition only (endof-frame) can be selected. The receiver
automatically deletes all Os inserted by the
transmitter during character assembly. CRC is
also calculated and is automatically checked to
validate frame transmission. At the end of
transmission, the status of a received frame is
available in the status registers. In SDLC
mode, the SCC must be programmed to use
the SDLC CRC polynomial, but the generator
and checker may be preset to all Is or all Os.

DATA

DATA

DATA

DATA

'-----.---'

~----~v~--~·~-16

Figure ,. Detecting 5- or 7-Bil SynchroDOus Character.

340

2042-109

Functional
Description
(Continued)

The CRC is inverted before transmission and
the receiver checks against the bit pattern
0001110100001111.
NRZ, NRZI or FM coding may be used in any
Ix mode. The parity options avaIlable in Asynchronous modes are available m Synchronous
modes.
The SCC can be conveniently used under
DMA control to provide hIgh speed reception
or transmission. In reception, for example, the
SCC can interrupt the CPU when the first
character of a message is received. The CPU
then enables the DMA to transfer the message
to memory. The SCC then issues an end-offrame interrupt and the CPU can check the
status of the received message. Thus, the CPU
is freed for other service while the message is
being received. The CPU may also enable the
DMA first and have the SCC interrupt only on
end-of-frame. This procedure allows all data to
be transferred via the DMA.

SOLe Loop Mode. The SCC supports SDLC
Loop mode in addition to normal SDLC. In an
SDLC Loop, there is a primary controller
station that manages the message traffic flow
on the loop and any number of secondary
stations. In SDLC Loop mode, the SCC performs the functions of a secondary station
while an SCC operating in regular SDLC
mode can act as a controller (Figure 5).
A secondary station in p'n SDLC Loop is
always listening to the messages being sent
around the loop, and in fact must pass these
messages to the rest of the loop by retransmitting them with a one-bit-time delay. The
secondary station can place its own message
on the loop only at specific times. The controller signals that secondary stations may
transmit messages by sending a special
character, called an EOP (End Of Poll),
around the loop. The EOP character is the bit
pattern IIIIIIIQ. Because of zero insertion
during messages, this bit pattern is unique and
easily recognized.
When a secondary station has a message to
transmit and recognizes an EOP on the line, it

changes the last binary I of the EOP to a 0
before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop
and terminates the message with an EOP. Any
secondary stations further down the loop with
messages to transmit can then append their
messages to the message of the first secondary
station by the same process. Any secondary
stations without messages to send merely echo
the incoming messages and are prohibited
from placing messages on the loop (except
upon recognizing an EOP).
SDLC Loop mode is a programmable option
in the SCC. NRZ, NRZI, and FM coding may
all be used in SDLC Loop mode.

Baud Rate Generator. Each channel in the
SCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
time constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reaching
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The following formula relates the time constant to the baud rate (the baud rate is in
bIts/second and the BR clock period is in
seconds);
baud rate;

2 (llme conslanl + 2)

X

(BR clock perIOd)

Digital Phase-Locked Loop. The SCC contains a Digital Phase-Locked-Loop (DPLL) to
recover clock information from a data stream
with NRZI or FM encoding. The DPLL is driven
by a clock that is nommally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses this
clock, along wIth the data stream, to construct
a clock for the data. This clock may then be
used as the SCC receive clock, the transmit
clock, or both.
For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
Figure S. An SDLe Loop

2016-001

341

&':
CII
W

o
fI2
n

n

Functional
Description
(Continued)

incoming data stream for edges (either 1 to 0
or 0 to 1). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the SCC via the TRxC pin (if
this pin is not being used as an input).
Data Encoding. The SCC may be programmed to encode and decode the serial data
in four different ways (Figure 6). In NRZ
encoding, a 1 is represented by a High level
and a 0 is represented by a Low level. In NRZI
encoding, a 1 is represented by no change in
level and a 0 is represented by a change in
level. In FMl (more properly, bi-phase mark),
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space),
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a 1
is represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the SCC can be used to decode
Manchester (bi-phase level) data by using the
DPLL in the FM mode and programming the
receiver for NRZ data. Manchester encoding
always produces a transition at the center of
the bit cell. If the transition is 0 to 1, the bit is
a O. If the transition is 1 to 0, the bit is a 1.

Auto Echo and Local Loopback. The SCC is
capable of automatically echoing everything it
receives. This feature is useful mainly in
Asynchronous modes, but works in Synchronous and SDLC modes as well. In Auto
Echo mode, TxD is RxD. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The SCC is also capable of local loopback.
In this mode TxD is RxD, just as in Auto Echo
mode. However, in Local Loopback mode, the
internal transmit data is tied to the internal
receive data and RxD is ignored (except to be
echoed out via TxD). The CTS and DCD
inputs are also ignored as transmit and receive
enables. However, transitions on these inputs
can still cause interrupts. Local Loopback
works in Asynchronous, Synchronous and
SDLC modes with NRZ, NRZI or FM coding of
the data stream.
1/0 Interface Capabilities. The SCC offers
the choice of Polling, Interrupt (vectored or
nonvectored), and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the SCC are automatically
updated whenever any function is performed.
For example, end-of-frame in SDLC mode
sets a bit in one of these status registers. The
idea behind polling is for the CPU to
periodically read a status register until the
register contents indicate the need for data to
be transferred. Only one register needs to be

DATA

NRZ

NRZI

\
\

I
I

\
\

FM1

FMO

MANCHESTER

Figure 8. Data EncDdlng Methocla

342

2016-002

Functional
Description
(Continued)

read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. When an SCC responds to an
Interrupt Acknowledge signal (INTACK) from
the CPU, an interrupt vector may be placed on
the data bus. This vector is written in WR2 and
may be read in RR2A or RR2B (Figures lO
and 11).
To speed interrupt response time, the SCC
can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits
associated with the interrupt source: Interrupt
Pending (IP), Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the IE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
IE bits are write only.
The other two bits are related to the interrupt priority chain (Figure 7). As a
microprocessor peripheral, the SCC may
request an interrupt only when no higher
priority device is requesting one, e.g., when
lEI is High. If the device in question requests
an interrupt, it pulls down INT. The CPU then
responds with INTACK, and the interrupting
device places the vector on the data bus.
In the SCC, the IP bit signals a need for
interrupt servicing. When an IP bit is 1 and
the IEI input is High, the INT output is pulled
Low, requesting an interrupt. In the SCC, if
the IE bit is not set by enabling interrupts,
then the IP for that source can never be set.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the SCC and

PERIPHERAL
lEI 00- 01

iNf

external to the SCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the lEO output of the SCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of three
ways:
• Interrupt on First Receive Character or
Special Receive Condition.
• Interrupt on All Receive Characters or
Special Receive Condition.
• Interrupt on Special Receive Condition
Only.
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is one of
the following: receiver overrun, framing error
in Asynchronous mode, end-of-frame in SDLC
mode and, optionally, a parity error. The
Special Receive Condition interrupt is different
from an ordinary receive character available
interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on First Receive Character, an interrupt can occur from Special Receive Conditions any time after the first receive character
interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins; however, an

PERIPHERAL

INTACK lEO

lEI 00-07

iNT

INTACK lEO

PERIPHERAL
lEI Do-07

iNT

INTACK

+5V
+5V

DO-D7

v---------------------------------------------~

INT.-----------~~+_--------------+-_+--------------~_,~
INTACK~--------------~------

___________ +_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

Figure 7. Interrupt Schedule

2023·003

343

w
=
o
en

§

Functional
Description
(Continued)

External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection
of a Break (Asynchronous mode), Abort (SDLC
mode) or EOP (SDLC Loop mode) sequence in
the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing
the SCC to interrupt when the Abort or EOP
sequence is detected or terminated. This
feature facilitates the proper termination of the
current message, correct initialization of the
next message, and the accurate timing of the
Abort condition in external logic in SDLC
mode. In SDLC Loop mode, this feature allows
secondary stations to recognize the wishes of
the primary station to regain control of the
loop during a poll sequence.

CPU/DMA Block Transfer. The SCC provides
a Block Transfer mode to accommodate CPU
block transfer functions and DMA controllers.
The Block Transfer mode uses the WAIT/
REQUEST output in conjunction with the
Wait/Request bits in WRl. The WAIT/
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the
DMA Block Transfer mode.
To a DMA controller, the SCC REQUEST
output indicates that the SCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the SCC is not
ready to transfer data, thereby requesting that
the CPU extend the I/O cycle. The DTRI
REQUEST line allows full-duplex operation
under DMA control.

Architecture

The SCC internal structure includes two fullduplex channels, two baud rate generators,
internal control and interrupt logic, and a bus
interface to a nonmultiplexed bus. Associated
with each channel are a number of read and
write registers for mode control and status
information, as well as logic necessary to interface to modems or other external devices
(Figure 8).
The logic for both channels provides
formats, synchronization, and validation for
data transferred to and from the channel interface. The modem control inputs are monitored

by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, two synccharacter (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the
baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a

INTERNAL
CONTROL
LOGIC

DATAW

_

}

MODEM, DMA, OR
OTHER CONTROLS

CPU
BUSIIC

-}

CONTROL

INTERRUPT
CONTROL
LINES

MODEM, DMA, OR
OTHER CONTROLS

INTERRUPT
CONTROL
LOGIC
} SERIAL DATA

t tt

. . - - } CHANNEL CLOCKS
SYNC
WAIT/REQUEST

+5 V GND PCLK

Figure 8. Block Diagram of

344

see Architecture

2016·040

~

~>

0 ..
o n

c;

a=.

§

5' i
c--_~-_-.J-r--'f-C---------:...------------------,( ~______

"\

....

4 MHz
No.

Symbol

Parameter

Min

Max

27
TdA(DR)
Address ReqUlred Valid to Read Data Valid Delay
590
28
TwWRI
WR Low Width
390
29
TsDW(WR)
Write Data to WR I Setup Time
0
30
ThDW(WR)
Wnte Data to WR 1 Hold Time
0
31-TdWR(W)--WR I to Wait Valid D e l a y - - - - - - - - - - - - - 240
32
TdRD(W)
RD I to Wait Valid Delay
240
33
TdWRf(REQ)
WR I to W/REQ Not Valid Delay
240
34
TdRDf(REQ)
RD I to W/REQ Not Valid Delay
240
35
TdWRr(REQ)
WR 1 to DTR/REQ Not Valid Delay
5TcPC
+300
36-TdRDr(REQ)- RD 1 to DTRlREQ Not Valid D e l a y - - - - - - - - - 5TcPC
+300
37
TdPC(lNT)
PCLK I to !NT Valid Delay
500
38
TdIAi(RD)
INTACK to RD I (Acknowledge) Delay
250
39
TwRDA
RD (Acknowledge) Width
285
40 - TdRDA(DR) - - RD I (Acknowledge) to Read Data Valid Delay - - - - - - 190
41
TsIEI(RDAl
IEI to RD I (Acknowledge) Setup Time
120
42
ThIEl(RDA)
IEI to RD 1 (Acknowledge) Hold Time
0
43
TdIEl(IEO)
IEI to lEO Delay TIme
.
120
44
TdPC(lEO)
PCLK 1 to IEO Delay
250
45-TdRDA(lNT)-RD I to !NT Inactive D e l a y - - - - - - - - - - - - - 500
46
TdRD(WRQ)
RD 1 to WR I Delay for No Reset
30
47
TdWRQ(RD)
WR 1 to RD I Delay for No Reset
30
48
TwRES
WR and RD Coincident Low for Reset
250
49
Trc
Valid Access Recovery TIme
6TcPC
+200
NOTES:
3 Parameter apphes only between transactions Involvmg the sec.
4. Open~dram output, measured with open-dram test load
5 Parameter IS system dependent. For any sec 10 the daISY
cham, TdIAl(RD) must be greater than the sum of TdPC(IEO)
for the hIghest pnonty deVice In the daISY cham, TsIEI(RDA)
2023-007, 008, 009

6 MHz
Min

Max

Notes*t

420
250
0
0

250
250

200 - - - 4 200
4
200
200
5TcPC
+250
5TcPC
+250
500
4
5
180

100
0
100
250
500 - - - 4 15
30
250
6TcPC
+ 130

3

for the sec, and TdIEIf(lEO) for each deVice separating them
In the daISY cham.
* TImmgs are prellIIunary and subject to change.

r Umts In nanoseconds (ns),

353

General
Timing

PCLK

W/REQ
REQUEST

W/REQ
WAIT _ _ _ _ _ _ _ _~""':"-_+--------------...J

RTxC, TRxe
RECEIVE

---------'r I

RxD

_+------..r'\---------------------

SYfiC
EXTERNAL _ _ _ _ _, ,_ _ _ _-:-_

TRxe,

RTiC

TRANSMIT

TxD

-C''.I--:::-:---;---"

------'-~------.--®-13r-------~-·xr------------------------------­

TRxe _ _ _ _ _ _ _ _ _ _ _ _ __
OUTPUT

\---§3
TRXC----~\_ _ _ _ _ _ _~~~\-----~rCT.,DCD,iii _ _ _ _ _ _ _ _ _ _~

c:l

J

r~~

SYNC
INPUT

- - - - - -

354

21

.Ir - - - - - - - - - - - - - - -

--®----l

2016-014

No.

Symbol

Parameter

Min

I

TdPC(REQ)

PCLK I to W/REQ Valid Delay

2

TdPC(W)

PCLK I to Wail Inactive Delay

3

TsRXC(PC)

RxC t to PCLK t Setup Time (PCLK + 4 case only)

4
5-

TsRXD(RXCr)

RxD to RxC t Setup Time (XI Mode)

ThRXD(RXCr) -

RxD to RxC t Hold Time (Xl Mode)

6

TsRXD(RXCf)

RxD to RxC I Setup Time (XI Mode)

7

ThRXD(RXCf)

RxD to RxC I Hold Time (XI Mode)

8

TsSY(RXC)

9

ThSY(RXC)

4 MHz
Max

6 MHz
Min
Max

250
80

350
TwPCI

250
70

0

0

150

150

1,4
I
1-

0

0

1,5

150

1,5

SYNC to RxC t Setup Time

-200

-200

SYNC to RxC t Hold Time

3TcPC
+200

3TcPC
+200

I
0 -----2,4-

0

II

TdTXCf(TXD)

TxC I to TxD Delay (XI Mode)

300

12

TdTXCr(TXD)

TxC t to TxD Delay (XI Mode)

13
14

TdTXD(TRX)

300
200

230
230
200

15 -

TxD to TRxC Delay (Send Clock Echo)
RTxC High Width
TwRTXh
TwRTXI--- RTxC Low Width

180

180

16

TcRTX

RTxC Cycle Time

400

400

17

TcRTXX

Crystal OSCillator PerIOd

250

18
19

TwTRXh
TwTRXI

TRxC High Width
TRxC Low Width

180

20-TcTRX

TRxC Cycle Time

400

400

21

TwEXT

DCD or CTS Pulse Width

200

200

22

TwSY

SYNC Pulse Width

200

200

RTxC or TRxC, whichever

IS

supplymg the receive

clock
2 TxC IS TRxC or RTxC, whichever

IS

supplYing the transmit

IS

350
TwPCI

150

10- TsTXC(PC)-- TxC I to PCLK t Setup Time

NOTES
1 RxC

Notes*t

clock
3 Both RTxC and SYNC have 30 pF capacitors to ground connected to them

4

=
en
w

180

180

180

2
2,5

1000

250

C

fft

1000

g

3

180
180

Parameter applies only If the data rate IS one-fourth the PCLK
rate In all other cases, no phase relationship between RxC and

PCLK or TxC and PCLK IS required.
Parameter apphes only to FM encodmg/decodmg
• Tlmmgs are preliminary and subject to change,
t Umts In nanoseconds (ns).

355

System
Timing

RTxC, TRxC
RECEIVE

W/REQ
REQUEST

W/REQ

+ ___::-__J

WAIT _ _ _ _ _ _ _ _ _ _ _ _ _

SYNC
OUTPUT

RTxC, TRxC
TRANSMIT

W/REQ
REQUEST

-------0------

+ ______J ~-----------------

W/REQ
WAIT _ _ _ _ _ _ _ _ _ _ _ _ _

DTRlREQ
REQUEST

~

eTS, DCD. AI

SYNC
INPUT

,

~

------------f----"'I

~I.----~®~--~j~---------------4 MHz
No.

Symbol

Parameter

1

TdRXC(REQ)

RxC t to W/REQ Vahd Delay

2

TdRXC(W)

RxC t to Walt lnachve Delay

3

TdRXC(SY)

RxC t to SYNC Vahd Delay

8
9
10

TdTXC(lNT)

TxC I to INT Vahd Delay

TdSY(lNT)

SYNC Translhon to INT Vahd Delay

TdEXT(INT)

DCD or CTS Translhon to INT Valid Delay

NOTES
1 Open-dram output, measured wIth open-dram test load

2 RxC IS RTxC or TRxC, whichever
clock
TxC IS TRxC or RTxC, whIchever
clock.

356

IS

supplymg the receive

IS

supplymg the transmit

Min

Max

8
8
4

12
12
7

6MHz
Min
Max

8
8

Notes"'t

12
12

4

7

10

16

* Tlmmgs dre prelimmary and subject to change

t Umts equal to TePe

2016-015

Ordering
Information

Product
Number

Package/
Temp
Speed

Product
Number

Package/
Speed
Temp

Description

Z8530

CE

4.0 MHz

SCC (40-pm)

Z8530A

CE

6.0 MHz

SCC (40-pm)

Z8530

CM

4.0 MHz

Same as above

Z8530A

CM

6.0 MHz

Same as above

Z8530

CMB

4.0 MHz

Same as above

Z8530A

CMB

6.0 MHz

Same as above

Z8530

CS

4.0 MHz

Same as above

Z8530A

CS

6.0 MHz

Same as above

Z8530

DE

4.0 MHz

Same as above

Z8530A

DE

6.0 MHz

Same as above

Z8530

DS

4.0 MHz

Same as above

Z8530A

DS

6.0 MHz

Same as above

Z8530

PE

4.0 MHz

Same as above

Z8530A

PE

6.0 MHz

Same as above

Z8530

PS

4.0 MHz

Same as above

Z8530A

PS

6.0 MHz

Same as above

NOTES. C

=

= Plashc, E
+70°C

Ceramic, D ;::; Cercilp, P

Wlth Class B processmg, S ;::;

00·2023·02

Description

aoc to

=

-40°C to +85°C, M = -55°C to 125°C, ME ::::: -55°C to 125°C with MIL-STD-883

357

Z8531 ASCC
Asynchronous Serial
Communications Controller

~
Zilog

Product
Specification

June 1982

Features

• Two independent, 0 to 1M bIt/second, fullduplex channels, each with a separate
crystal oscillator, baud rate generator, and
DIgItal Phase-Locked Loop for clock
recovery.

• Asynchronous communications wIth five to
eight bits per character and one, one and
one-half, or two stop bits per character; programmable clock factor; break detection
and generation; panty, overrun, and
frammg error detection .

• Programmable for NRZ, NRZI, or FM data
encoding.

General
Description

• Local Loopback and Auto Echo modes.

The Z8531 ASCC Asynchronous Senal
Communications Controller IS a dual-channel,
multi-protocol data communications peripheral
designed for use with conventional nonmultiplexed buses. The ASCC functions as a
senal-to-parallel, parallel-to-serial converter/controller. The device contams a vanety
of new, sophisticated internal functions includmg on-chIp baud rate generators, Digital
Phase-Locked Loops, and crystal OSCIllators
that dramatically reduce the need for external
logic.

I
I

The ASCC also has facilities for modem controls in both channels. In applications where
these controls are not needed, the modem controls can be used for general-purpose I/O.
The Z-BUS daisy-chain interrupt hierarchy is
also supported-as is standard for Zilog
peripheral components.
The Z8531 ASCC is packaged in a 40-pin
ceramic DIP and uses a single + 5 V power
supply.

SERIAL

0,
0,

DATA

CHANNEL
CLOCKS
CH-A

CHANNEL

BUS
TIMING
AND RESET

CONTROL

INTERRUPT

1

I
I

0,
0,

0,

iNr

liD

lEO

CONTROLS
FORMODEM,
OMA,OR
OTHER

lEI

I

Ole

RxDA

TRxCA

CHANNEL
CONTROLS
FORMODEM,

DMA,OR
OTHER

CH·8

AlB

+5V

RiA

CLOCKS

wCE

RTxCA

} CHANNEL

0,

INTACK
W/AEQA

SERIAL
DATA

0,
0,

TxDA
DTRIREQA
RTSA

eTSA

OND
W/AEQB

Rii
RTxCB
RxDB
TRxeB

TxOS
DTR/REQS

RTsa

DCDA

em

PCLK

DeDB

+5V

Figure I. Pin Functions

2244-001, 002

Figure 2. Pin Assignments

359

Pin
Description

The following section describes the pin
functions of the ASCC. Figures 1 and 2 detail
the respective pin functions and pin
assignments.

AlB.

Channel A/Channel B Select (input).
This signal selects the channel in which the
read or write operation occurs.

CEo Chip Enable (input, active Low). This
signal selects the ASCC for a read or write
operation.

CTSA, CTSB. Clear To Send (inputs, active
Low). If these pins are programmed as Auto
Enables, a Low on the mputs enables the
respective transmitters. If not programmed as
Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs.
The ASCC detects pulses on these inputs and
can interrupt the CPU on both logIC level
transitions.

Die. DataiControl Select (input). This signal
defines the type of information transferred to
or from the ASCC. A High means data is
transferred; a Low indicates a command.

DCDA. DCDB. Data Carrier Detect (inputs,
active Low). These pins function as receiver
enables if they are programmed for Auto
Enables; otherwise they may be used as
general-purpose input pins. Both pins are
Schmitt-trigger buffered to accomodate slow
rise-time Signals. The ASCC detects pulses on
these pins and can interrupt the CPU on both
logic level transitions.

Do-D,. Data Bus (bidirectional, 3-state). These
lines carry data and commands to and from
the ASCC.

DTR/REQA, DTR/REQB. Data Terminal
Ready/Request (outputs, activ~ Low). These
outputs follow the state programmed into the
DTR bit. They can also be used as generalpurpose outputs or as Request lines for a DMA
controller.
lEI. Interrupt Enable In (input, active High).
IEI is used with IEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High IEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). IEO is High only if IEI is High and the
CPU is not servicing an ASCC interrupt or the
ASCC is not requesting an interrupt (Interrupt
Acknowledge cycle only). IEO is connected to
the next lower priority device's lEI input and
thus inhibits interrupts from lower priority
devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is activated when the
ASCC requests an interrupt.

360

INTACK. Interrupt Acknowledge (mput, active
Low). This SIgnal mdicates an active Interrupt
Acknowledge cycle. Durmg thIS cycle, the
ASCC interrupt daISY chain settles. When RD
becomes active, the ASCC places an interrupt
vector on the data bus (if IEI is High).
INTACK is latched by the rising edge
of PCLK.
PCLK. Clock (mput). This is the master ASCC
clock used to synchronize internal signals;
PCLK is a TTL level signal.

RD. Read (mput, achve Low). This signal mdlcates a read operatIon and when the ASCC IS
selected, enables the ASCC's bus drivers.
During the Interrupt Acknowledge cycle, thIS
signal gates the interrupt vector onto the bus
If the ASCC IS the hIghest prlOnty device
requestmg an mterrupt.

RxDA, RxDB. Receive Data (mputs, active
High). These mput signals receIve serIal data
at standard TTL levels.

RIA. RIB. Rmg Indicator (inputs, active Low).
These pins can act eIther as inputs, or part of
the crystal OSCIllator circuit. In normal mode
(crystal OSCIllator option not selected), these
pms are mputs similar to CTS and DCD. In
thIs mode, transitions on these hnes affect the
state of the Rmg IndICator status bIts in Read
RegIster 0 (FIgure 8) but have no other funchon.

RTxCA, RTxCB. Receive/Transmit Clocks
(inputs, active Low). These pms can be programmed in several different modes of operation. In each channel, RTxC may supply the
receive clock, the transmIt clock, the clock for
the baud rate generator, or the clock for the
DIgital Phase-Locked Loop. These pms can
also be programmed for use with the respective RI pins as a crystal OSCIllator. The receive
clock may be 1, 16,32, or 64 times the data
rate m Asynchronous modes.

RTSA, RTSB. Request To Send (outputs,
active Low). When the Request To Send (RTS)
bit in Write Register 5 (Figure 9) IS set, the
RTS signal goes Low. When the RTS bit IS
reset in the Asynchronous mode and Auto
Enable is on, the SIgnal goes High after the
transmitter IS empty. WIth Auto Enable off, the
RTS pin stnctly follows the state of the RTS bIt.
Both pms can be used as general-purpose
outputs.
TxDA. TxDB. Transmit Data (outputs, actIve
High). These output SIgnals transmit senal data
at standard TTL levels.

TRxCA. TRxCB. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or sup-

Pin
Description
(Contmued)

ply the output of the Digital Phase-Locked
Loop, the crystal OSCillator, the baud rate
generator, or the transmit clock in the output
mode.

W/REQA, W/REQB. Wait/Request (outputs,
open-drain when programmed for aWait funchon, driven High or Low when programmed
for a Request function). These dual-purpose
outputs may be programmed as Request Imes
for a DMA controller or as Wait lines to synchronize the CPU to the ASCC data rate. The
reset state is Wait.

WR. Write (input, achve Low). When the
ASCC is selected, this signal indicates a write
operation. The coincidence of RD and WR is
interpreted as a reset.
Functional
Description

handle data at a rate of I, 1116, 1132, or 1164
of the clock rate supplied to the receive and
transmit clock mputs.

The functional capabilities of the ASCC
can be described from two different points
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communications protocols; as a
microprocessor peripheral, the ASCC offers
valuable features such as vectored interrupts,
polling, and simple handshake capability.

Data Communications Capabilities. The
ASCC prOVides two independent full-duplex
channels programmable for use in any common Asynchronous data communication protocol. Figure 3 and the followmg description
bnefly detail this protocol.
Asynchronous Modes. Transmission and
recephon can be accomplished mdependently
on each channel with !lve to eight bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-ahalf, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the start and at the end of a
received break. Recephon is protected from
spikes by a transient spike-rejechon
mechanism that checks the Signal one-half a
bit time after a Low level is detected on the
receive data input (RxDA or RxDB m
Figure I). If the Low does not persist (as m the
case of a transient), the character assembly
process does not start.
Frammg errors and overrun errors are
detected and buffered together with the parhal
character on which they occur. Vectored interrupts allow fast servicmg of error condihons
usmg dedicated routines. Furthermore, a
built-in checkmg process avoids the mterpretahon of a framing error as a new start bit: a
frammg error results in the addition of one-half
a bit hme to the point at whICh the search for
the next start bit begms.
The ASCC does not require symmetric
transmit and receive clock signals-a feature
allowmg use of the wide vanety of clock
sources. The transmitter and receiver can

sr

""MA"'R""K'N""'G"'"'U""NE:--""""I

Baud Rate Generator. Each channel in the
ASCC contains a programmable baud rate
generator. Each generator consists of two 8-bit
lime constant registers that form a 16-bit time
constant, a 16-bit down counter, and a flip-flop
on the output producing a square wave. On
startup, the flip-flop on the output is set in a
High state, the value in the time constant
register is loaded into the counter, and the
counter starts counting down. The output of
the baud rate generator toggles upon reachmg
0, the value in the time constant register is
loaded into the counter, and the process is
repeated. The time constant may be changed
at any time, but the new value does not take
effect until the next load of the counter.
The output of the baud rate generator may
be used as either the transmit clock, the
receive clock, or both. It can also drive the
Digital Phase-Locked Loop (see next section).
If the receive clock or transmit clock is not
programmed to come from the TRxC pin, the
output of the baud rate generator may be
echoed out via the TRxC pin.
The following formula relates the time constant to the baud rate (the baud rate is in
bits/second and the BR clock period is in
seconds):
baud rate =

I
2 (hme constant + 2) x (BR clock perIOd)

Digital Phase-Locked Loop. The ASCC contains a Digital Phase-Locked-Loop (DPLL) to
recover clock information from a data stream
with NRZI or FM encoding. The DPLL is driven
by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses this
clock, along with the data stream, to construct
a clock for the data. This clock may then be
used as the ASCC receive clock, the transmit
clock, or both.

PARITY

!r

-OA-T-A-r1!,1.!.,'-'1Ir--OA-TA.......I-rl-r'-rlI

1""1

DATA

II'

i MARKING LINE

ASYNCHRONOUS

Figure 3.

2042·108

ASee Protocol
361

:;:en

...

w

~

n

Functional
Description
(Contmued)

For NRZI encoding, the DPLL counts the 32x
clock to create nominal bit times. As the 32x
clock is counted, the DPLL is searching the
incoming data stream for edges (either I to 0
or 0 to I). Whenever an edge is detected, the
DPLL makes a count adjustment (during the
next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the DPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The DPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the DPLL can be programmed to come from either the RTxC input
or the output of the baud rate generator. The
DPLL output may be programmed to be
echoed out of the ASCC via the TRxC pin (if
this pin is not being used as an input).

Data Encoding. The ASCC may be programmed to encode and decode the serial data
m four different ways (Figure 4). In NRZ
encoding, a I IS represented by a High level
and a 0 is represented by a Low level. In NRZI
encoding, a I is represented by no change in
level and a 0 is represented by a change in
level. In FMI (more properly, bl-phase mark),
a transition occurs at the beginning of every
bit cell. A I is represented by an additional
transition at the center of the bit cell and a 0 IS
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space),
a transihon occurs at the begmning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a I
is represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the ASCC can be used to
decode Manchester (bi-phase level) data by
using the DPLL m the FM mode and programming the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is 0 to I,

the bit is a O. If the transition is I to 0, the bit
is a I.

Auto Echo and Local Loopback. The ASCC is
capable of automatically echoing everything it
receives. In Auto Echo mode, RxD is connected to TxD internally. Auto Echo mode can
be used with NRZI or FM encoding with no
addihonal delay, because the data stream is
not decoded before retransmissIOn. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disablmg transmitter interrupts
and WAIT/REQUEST on transmit.
The ASCC is also capable of local loopback.
In thiS mode TxD is connected to RxD internally, Just as in Auto Echo mode. However, in
Local Loopback mode, the internal transmit
data is hed to the internal reC81ve data and
RxD is ignored (except to be echoed out via
TxD). The CTS and DCD
inputs are also ignored as transmit and receive
enables. However, transitions on these inputs
can still cause interrupts. Local Loopback
works with NRZ, NRZI or FM coding of the data
stream.

1/0 Interface Capabilities. The ASCC offers
the choice of Polling, Interrupt (vectored or
non vectored) , and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or DMA
control.
Polling. All interrupts are disabled. Three
status registers in the ASCC are automatically
updated whenever any function is performed.
The idea behind polling is for the CPU to
periodically read a status register until the
register contents indicate the need for data to
be transferred. Only one register needs to be
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for

DATA

NRZ

NRZI

\
\

I
/

\
\

FM.

FMO

MANCHESTER

Figure 4. Data Encoding Methods

362

2016-002

Functional
Description
(Contmued)

data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. When an ASCC responds to an
Interrupt Acknowledge signal (INTACK) from
the CPU, an interrupt vector may be placed on
the data bus. This vector is written in WR2 and
may be read in RR2A or RR2B (Figures 8
and 9).
To speed interrupt response time, the ASCC
can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
ASCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits
associated with the interrupt source: Interrupt
Pending (IP). Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the IE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
IE bits are write only.
The other two bits are related to the interrupt priority chain (Figure 5). As a
microprocessor peripheral, the ASCC may
request an interrupt only when no higher
priority device is requesting one, e.g., when
lEI is High. If the device in question requests
an interrupt, it pulls down INT. The CPU then
responds with INTACK, and the interrupting
device places the vector on the data bus.
In the ASCC, the IP bit signals a need for
interrupt servicing. When an IP bit is 1 and
the lEI input is High, the INT output is pulled
Low, requesting an interrupt. In the ASCC, if
the IE bit is not set by enabling interrupts,
then the IP for that source can never be set.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the ASCC and
external to the ASCC are prevented from
requesting interrupts. The internal interrupt

iNf

• Interrupt on First Receive Character or
Special Receive Condition.

INT ACK lEO

• Interrupt on Special Receive Condition
Only.
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is a
receiver overrun, and, optionally, a parity
error. The Special Receive Condition interrupt
is different from an ordinary receive character
available interrupt only in the status placed in
the vector during the Interrupt Acknowledge
cycle. In Interrupt on First Receive Character,
an interrupt can occur from Special Receive
Conditions any time after the first receive
character interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and RI pins; however, an
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
in the baud rate generator, or by the detection
of a Break.

lEI 00-07

iNT

INTACK lEO

PERIPHERAL
lEI 00-07

fN'f

INTACK

+5V
+5V
Do-D7~

______________________________________________

~

INT.---------____~~______________~~--------------~--+_~

~~--------------~----------------~----------------~
Figure 5. Interrupt Schedule

2016-003

I:CII

...III

W

1.:
n

• Interrupt on All Receive Characters or
Special Receive Condition.

PERIPHERAL

PERIPHERAL
lEI 00- 07

sources are inhibited by the state of the internal daisy chain, while lower priority devices
are inhibited by the lEO output of the ASCC
being pulled Low and propagated to subsequent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
interrupt type is enabled under program control with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of three
ways:

363

Functional
Description
(Contmued)

CPU/DMA Block Transfer. The ASCC provides a Block Transfer mode to accommodate
CPU block transfer functions and DMA controllers. The Block Transfer mode uses the
WAITI REQUEST output in conjunction with
the WaiVRequest bits in WRl. The WAITI
REQUEST output can be defined under software control as a WAIT line in the CPU Block
Transfer mode or as a REQUEST line in the

DMA Block Transfer mode.
To a DMA controller, the ASCC REQUEST
output indicates that the ASCC is ready to
transfer data to or from memory. To the CPU,
the WAIT line indicates that the ASCC is not
ready to transfer data, thereby requesting that
the CPU extend the 1/0 cycle. The DTRI
REQUEST line allows full-duplex operation
under DMA control.

Architecture

The ASCC internal structure includes
two full-duplex channels, two baud rate
generators, internal control and interrupt
logic, and a bus interface to a nonmultiplexed
bus. Associated with each channel are a
number of read and write registers for mode
control and status information, as well as logic
necessary to interface to modems or other
external devices (Figure 6).
The logic for both channels provides
formats, synchronization, and validation for

data transferred to and from the channel interface. The modem control inputs are monitored
by the control logic under program control.
All of the modem control signals are generalpurpose in nature and can optionally be used
for functions other than modem control.
The register set for each channel includes
ten control (write) registers, and four status
(read) registers. In addition, each baud rate
generator has two (read/write) registers for
holding the time constant that determines the

INTERNAL
CONTROL
LOGIC

MODEM, DMA, OR

}

OTHER CONTROLS

}

MODEM, DMA, OR
OTHER CONTROLS

DATA
CPU

BUS 110
CONTROL

INTERRUPT
CONTROL
LINES

INTERRUPT
CONTROL
LOGIC

} SERIAL DATA

ttt

~

} CHANNEL CLOCKS

Ri

+SVGND PClK

WAITfREQUEST

Figure 6. Block Diagram of ASCC Architecture

364

2244-003

:::.

~>

'"

air.
5 ;-

0o n..
"

n

CD o..S::

~;
CPU 110

SA GENERATOR

INPUT

8R GENERATOR
OUTPUT

RECEIVE

RECEIVE

DATA

ERROR

FIFO

FIFO

TRANSMIT
CLOCK

OxD

DPLL

I

~
--1-

SA GENERATOR OUTPUT
DPLl OUTPUT - - - -...

TOxC----+J

RECEIVE CLOCK
CLOCK
MUX

RTxC-~--+I

TRANSMIT CLOCK
DPLL CLOCK

8A GENERATOR CLOCK

iii
(OSCILLATOR)

w
(j)
<.n

Figure 7. Data Path

33SV ItS.

Architecture

(Conhnued)

baud rate. Finally, associated with the interrupt logic is a write register for the interrupt
vector accessible through either channel, a
write only Master Interrupt Control register
and three read registers: one containing the
vector with status infomation (Channel B only),
one containing the vector without status
(Channel A only). and one containing the
Interrupt Pending bits (Channel A only).
The registers for each channel are
designated as follows:
WRO-WR15 -

Write Registers 0-5,8-15.

RRO-RR3, RR10, RR12, RR13, RR15 - Read
Registers 0 through 3, 10, 12, 13, 15.
Table 1 lists the functions assigned to each
read or write register. The ASCC contains only one WR2 and WR9, but they can be accessed by either channel. All other registers are
paired (one for each channel).
Data Path. The transmit and receive data path

illustrated in Figure 7 is identical for both
channels. The receiver has three 8-bit buffer
registers in an FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme
creates additional time for the CPU to service
an interrupt at the beginning of a block of
high speed data. Incoming data is routed
through one of several paths depending on the
selected mode (the character length also determines the data path).
The transmitter has an 8-bit Transmit Data
buffer register loaded from the internal data
bus and an ll-bit Transmit Shift register that
can be loaded from the Transmit Data register.
Programming

366

The ASCC contains 11 write registers in
each channel that are programmed by the
system separately to configure the functional
personality of the channels.
In the ASCC, register addressing is direct
for the data regIsters only, which are selected
by a High on the Die pin. In all other cases
(with the exception of WRO and RRO), programming the write registers requires two
write operations and reading the read registers
requires both a write and a read operation.
The first write is to WRO and contains three
bits that point to the selected register. The second write is the actual control word for the

Read Register Functions
RRO

TransmIt/ReceIve buffer status and External status

RRI

SpeClal ReceIve Condlhon status

RR2

Modified interrupt vector (Channel B only)
Unmodified mterrupt vector (Channel A only)

RR3

Interrupt Pendmg bits (Channel A only)

RRB

ReceIve buffer

RRIO

Miscellaneous status

RR12

Lower byte of baud rate generator time constant

RR13

Upper byte of baud rate generator hme constant

RR15

ExternaVStatus mterrupt information

Write Register Functions
WRO

CRC imtialize, mitiahzahon commands for the
vanous modes, RegIster Pomters.

WRI

TransmIt/ReceIve interrupt and data transfer mode
dehmtion

WR2

Interrupt vector (accessed through either channel)

WR3

ReceIve parameters and control

WR4

Transmit/ReceIve mIscellaneous parameters and
modes

WR5

TransmIt parameters and controls

WRB

TransmIt buffer

WR9

Master mterrupt control and reset (accessed
through eIther channel)

WRIO

Miscellaneous transmItter/receIver control bits

WRll

Clock mode control

WR12

Lower byte of baud rate generator time constant

WR13

Upper byte of baud rate generator hme constant

WR14

Miscellaneous control bits

WR15

ExternaVStatus interrupt control

Table 1. Read and Write Register Functions

selected register, and if the second operation
is read, the selected read register is accessed.
All of the registers in the ASCC, including the
data registers, may be accessed in this fashion.
The pointer bits are automatically cleared after
the read or write operation so that WRO (or
RRO) is addressed again.
The system program first issues a series of
commands to initialize the basic mode of
operation. For example, the character length,
clock rate, number of stop bits, even or odd
parity might be set first. Then the interrupt
mode would be set, and finally, receiver or
transmitter enable.

Programming Read Registers. The ASCC contains eight
read registers (actually nine, counting the
(Continued)
receive buffer (RR8) in each channel). Four of
these may be read to obtain status information
(RRO, RRl, RRlO, and RR15). Two registers
(RR12 and RR13) may be read to learn the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector
(Channel A) or the vector modified by status
information (Channel B). RR3 contains the

Interrupt Pending (IP) bits (Channel A).
Figure 8 shows the formats for each read
register.
The status bits of RRO and RRI are carefully
grouped to simplify status monitoring; e.g.,
when the interrupt vector indicates a Special
Receive Condition interrupt, all the appropriate error bits can be read from a single
register (RRI).

Read Register 0

Read Register 10

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

I L R,CHARACTERAVAILABLE

~~~

~ ZERO COUNT

Tx BUFFER EMPTY
DCD

RING INDICATOR

,

CTS

I~j
~ ~WOCLOCKSMISSING

I:en

...w

ONE CLOCK MISSINQ

BREAK

Read Register 1

Read Register 12

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

i

~r~~_
~
~

LOWER BYTE OF
TIME CONSTANT

FRAMING ERROR

o

Read Register 2

Read Register 13

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

INTERRUPT VECTOR·

-MODIFIED IN 8 CHANNEL

Read Register 3

~~

UPPER BYTE OF
TIME CONSTANT

Read Register IS

I~I~I~I~I~I~I~I~I

~~~

L~CHANNELBEXTISTATIP.
,p.
,p.
CHANNEL B Tx

CHANNEL B Rx

CHANNEL A EXT/STAT IP-

CHANNEL A Tx ,PCHANNEL A Rx Ip·

o
o

I~~:--"
~
~CTSIE
,

BREAK IE

-ALWAYS 0 IN B CHANNEL

Figure 8. Read Register Bit Functions

367

Programming Write Registers. The ASCC contains 11 write
(Contmued)
registers (12 counting WR8, the transmit
buffer) in each channel. These write registers
are programmed separately to configure the
functional "personality" of the channels. In
addition, there are two registers (WR2 and

WR9) shared by the two channels that may be
accessed through either of them. WR2 contains
the interrupt vector for both channels, while
WR9 contains the interrupt control bits.
Figure 9 shows the format of each write
register.
Write Register 3

Write Register 0

I~I~I~I~I~I~I~I~I
0

0

0

REGISTER 0

0

0
1

1

REGISTER 1

0

0

REGISTER 2

0

1

1

REGISTER 3

1

0

0

REGISTER 4

1

0

1

REOISTER 5

0

NULL CODE

o

0

NULL CODe

o

1

1
1

0

0

REGISTER 8

1

0

Ax 6 BITS/CHARACTER

0

0

1

REOISTER 9

1

1

Rx 8 BITS/CHARACTER

0

1

0

REGISTER 10

1

REGISTER 11

0

1

1

0

1

0

1

1

0

REGISTER 14

1

1

1

REGISTER 15

REGISTER 12
REGISTER 13

}

0

0

0

NULL CODE

0

0

1

POINT HIOH

0

RESET EXT/STAT INTERRUPTS

1
1

0

1

0

1

1

1

1

Rx 5 BITS/CHARACTER

1
1

Ax 7 BITS/CHARACTER

Write Register 4

I

I~I~I~I~I~I~I~I~I

NULL CODE
ENABLE INT ON NEXT Ax CHARACTER
RESET lxlNT PENDING

0
1

I L PARITV ENABLE
L PARITY EVEN/ODD

o

0

DO NOT PROGRAM

o

1

1 STOP BIT/CHARACTER

1

0

1 Y2 STOP BITS/CHARACTER

1

1

2 STOP BITS/CHARACTER

ERROR RESET
RESET HIGHEST IUS

X 1 CLOCK MODE

·WITH POINT HIGH COMMAND

X16 CLOCK MODE
X32 CLOCK MODE
X64 CLOCK MODE

Write Register 1
I~I~I~I~I~I~I~I~I

~

~L

Write Register 5
EXT INT ENABLE

1~1~1~1~1~1~1~1~1

Tx INT ENABLE
PARITY IS SPECIAL CONDITION

o

0

Rx INT DISABLE

o

1

Rx tNT ON FIRST CHARACTER OR SPECIAL CONDITION

1

OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION

1

1

Rx INT ON SPECIAL CONDITION ONLY

L.._ _ _ _ _ WAIT/DMA REQUEST ON RECEIVEITRANSMIT
' - - - - - - - WAtT/DMA REQUEST FUNCTION

L.._ _ _ _ _ _ _ WAIT/DMA REQUEST ENABLE

o

0

Tx 5 BITS (OR LESS)lCHARACTER

o

1

Tx 7 BITS/CHARACTER

1

0

Tx 6 BITs/CHARACTER

1

1

Tx 8 BITS/CHARACTER

L.._ _ _ _ _ _ _ DTR

Write Register 2
I~I~I~I~I~I~I~I~I

Figure 9. Write Register Bit Functions

368

2244-006

Programming Write Register 9
(Contmued)

Write Register 12

I~I~I~I~I~I~I~I~I

L~:~
lillhl~

DLC

MIE

LOWER BYTE OF
TIME CONSTANT

:ATUS HIGH/STATUS LOW

o

0

NO RESET

o

1

CHANNEL RESET B

1

0

CHANNEL RESET A

1

1

FORCE HARDWARE RESET

Write Register 13
Write Register 10

UPPER BYTE OF
TIME CONSTANT

o
o

0

NRZ

1

NAZI

1

0

FMi (TRANSITION", 1)

1

1

FMO (TRANSITION

!w...

Write Register 14

=0)

10, I~ ID,I D.I D,ID, ID, I~I

~~
L

Write Register 11

L BROENERATOR ENABLE
8A GENERATOR SOURCE
D'm/REQUEST FUNCTION

AUTO ECHO

10,1~1~1~1~10,1~1~1

o

~
0

o

1

1

0

1

1

LOCAL LOOPBACK

~

fRxC OUT XTAL OUTPUT
"fRiC OUT::: TRANSMIT CLOCK
TRxe OUT = 8A GENERATOR OUTPUT
1'Rie OUT = DPlL OUTPUT
TRxCOJi

o

0

TRANSMIT CLOCK '" RTiC PIN

o

1

TRANSMIT CLOCK

1

0

TRANSMIT CLOCK = BA GENERATOR OUTPUT

1

1

TRANSMIT CLOCK ::: DPLL OUTPUT

0

0

0

NULL COMMAND

0

0

1

ENTER SEARCH MODE

0

0

RESET MISSING CLOCK

0

1

1

DISABLE DPLL

1

0

0

SET SOURCE .. SR GENERATOR

1

1

SET SOURCE =

1

0
1

SET FM MODE

1

1

0
1

1

ifi'iC

SET NAZI MODe

= TRxe PIN

o

0

RECEIVE CLOCK

o

1

RECEIVE CLOCK

1

0

RECEIVE CLOCK

= RTxC PIN
= T"Fii"C PIN
= BR GENERATOR OUTPUT

1

1

RECEIVE CLOCK

= DPLL OUTPUT

L-_ _ _ _ _ _ _ RTxC XTAUNO XTAL

Write Register 15
10,1~1~1~1~1~1~1~1

~~:~~.
BREAK IE

Figure 9. Write Register Bit Functions (Conhnued)

2~44

006

369

Timing

The ASCC generates internal control signals
from WR and RD that are related to PCLK.
Since PLCK has no phase relationship with
WR and RD, the circuitry generating these internal control signals must provide time for
metastable conditions to disappear. This gives
rise to a recovery time related to PCLK. The
recovery time applies only between bus transactions involving the ASCC. The recovery
time required for proper operation is specified
from the rising edge of WR or RD in the first

transaction involving the ASCC to the falling
edge of WR or RD in the second transaction
involving the ASCC. This time must be at least
6 PLCK cycles plus 200 ns.
Read Cycle Timing. Figure 10 illustrates read
cycle timing, Addresses on AlB and DIC and
the status on INTACK must remain stable
throughout the cycle. If CE falls after RD
falls,or rises before RD rises, the effective RD
is shortened.

X

V--

Ali, Die _ _.....1 ...... _ _ _ _
ADDRESS
VALID _ _ _- - ' ' ' - _

\"---1

\

\"""-____.....1
DO-D7

----------~(~_ _ _ _..JX

DATA VALID

)

Figure 10. Read Cycle Timing

throughout the cycle. If CE falls after WR falls
or rises before WR rises, the effective WR is
shortened.

Write Cycle Timing. Figure 11 illustrates
write cycle timing. Addresses on AlB and DIC
and the status on INTACK must remain stable

X

V--

AlB, Die _ _-.oJ ......_ _ _ _
ADDRESS VALID
_ _ _ _- - ' ' ' - -

\ ......_ 1

\
\~
Do-D7

____--'I

---------«~----_;;D:.;AT:A:VA~L;,D-----)----Figure ll. Write Cycle Timing

when RD falls, the acknowledge cycle was intended for the ASCC. In this case, the ASCC
may be programmed to respond to RD Low by
placing its interrupt vector on Do-D7 and sets
the appropriate Interrupt- Under-Service latch
internally.

Interrupt Acknowledge Cycle Timing. Figure
12 illustrates interrupt acknowledge cycle timing. Between the time INTACK goes low and
the falling edge of RD, the internal and external IEl/IEO daisy chains settle. If there is an
interrupt pending the ASCC and lEI is High

INTACK~~_ _ _ _~,~'l~_ _ _ _ _ _ _ _ _ _ _ _ _~
1;<

DO-D7

//

\~----.....I
(

Figure 12. Interrupt Acknowledge Cycle Timing

370

2023~003,

004, 005

Absolute
Maximum
Ratings

Standard
Test
Conditions

Voltages on all inputs and outputs
withrespecttoGND .......... -0.3Vto +7.0V
Operating Ambient
Temperature ................. As Specified in
Ordering Information
Storage Temperature ........ -65°C to + 150°C
The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:

Stresses greater than those hsted under Absolute Maximum Rahngs may cause permanent damage to the dEi!'VIC~.
This IS a stress ratmg only; operation of the devlce at any
conditIOn above those mdlcated In the operational sections

of these specihcahons is not Imphed. Exposure to absolute
maXImum rating condItions for extended perIods may affect

deVICe rehabllity.

• +4.75 V :S Vee :S +5.25 V
• GND = 0 V
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
+,v

+,v

FROM OUTPUT

UNDER TEST

~ 2.2K
.

w
...=
en

r'O.F

fi
Figure 13. Standard Test Load

DC
Characteristics

Symbol

Parameter

VIH

Input High Voltage

VIL
VOH
VOL
IlL
IOL

Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage

ICC

Vee Supply Current

Figure 14. Open-Drain Test Load

Min

Max

Unit

2.0

Vee +0.3
0.8

V
V
V
V
p.A
p.A
rnA

-0.3
2.4

0.4
± 10.0
± 10.0
250

Condition

10H = - 250 p.A
1oL= +2.0mA
0.4 s VIN S +2.4V
0.4 s VauI s +2.4V

Vee = 5 V ± 5% unless otherWIse specIfIed, over speCIhed temperature range.

Capacitance

Symbol
C IN
C aUT
CliO

Parameter
Input Capacitance
Output Capacitance
Bldirechonal Capacitance

Min

Max

Unit

10
15
20

pF
pF
pF

Test Condition
Unmeasured Pins
Returned to Ground

f = 1 MHz, over specIfied temperature range

H(JHil (JUG, 001

371

Read and
Write

PCLK

Timing
Alii, DIe

~I\-~ ~J_

~

'-'-'

).

----(i)r---

-

ik4--: Ciii-J-----

~~

I<

r-------0-~

---®----

-----®

\

I--

--j®

~~
---'K---J
--®-----

f®----+

Hv-

)

®- ~

:-®--I\

:=---®

11

-I'

DO-D7
READ

-~

CD-

@25

-::f-®

-®---

21

.t
®
DO-D7
WRITE

~
®-i-

\

WiiiiQ
WAIT
32

WIREQ
REQUEST

DTRIREQ

I<

-f-®

~

~
,.

I--

==4

-®--

J

REQUEST
36

\
"
4MHz
No.

SymbDI

Parameter

Min

Max

6 MHz
Min
Max

Notes*t

I
TwPCI
PCLK Low WIdth
105
2000
70
1000
2
TwPCh
PCLK High WIdth
105
2000
70
1000
3
TlPC
PCLK Fall Time
20
10
4
TrPC
PCLK RIse TIme
20
15
5-TcPC
PCLK Cycle T I m e - - - - - - - - - - - - 2 5 0 - - 4 0 0 0 --165 -2000 - - - - 6
TsA(WR)
Address to WR j Setup TIme
80
80
7
ThA(WR)
Address to WR I Hold TIme
0
0
8
TsA(RD)
Address to RD j Setup TIme
80
80
9
ThA(RD)
Address to RD I Hold Time
0
0
10-TsIA(PC)---INTACK to PCLK I Setup TIme
0
0 -------II
TsIAi(WR)
INTACK to WR j Setup TIme
200
200
12
ThIA(WR)
INTACK to WR I Hold TIme
0
0
13
TsIAI(RD)
INTACK to RD j Setup TIme
200
200
14
ThIA(RD)
INTACK to RD I Hold TIme
0
0
15-ThIA(PC)--INTACK to PCLK I Hold TIme
100
100-------16
TsCE1(WR)
CE Low to WR j Setup TIme
0
0
17
ThCE(WR)
CE to WR I Hold TIme
0
0
18
TsCEh(WR)
CE HIgh to WR j Setup Time
100
70
19
TsCEl(RD)
CE Low to RD j Setup TIme
0
0
I
20
ThCE(RD)
CE to RD I Hold TIme
0
0
I
21-TsCEh(RD)-- CE HIgh to RD j Setup TIme
100
70 - - - - - - - 1 22
TwRDl
RD Low WIdth
390
250
I
23
TdRD(DRA)
RD j to Read Data ActIve Delay
0
0
24
TdRDr(DR)
RD I to Read Data Not ValId Delay
0
0
25
TdRDf(DR)
RD j to Read Data ValId Delay
250
180
26
TdRD(DRz)
RD 1 to Read Data Float Delay
70
45
2
NOTES-

1 Parameter does not apply to Interrupt Acknowledge
trdnSdchons

372

:2 Float deldY
1Tl

18

the output

for a ± 0 5 V change

uehned as the time
wIth d IDdXlmum

d<-

rind

mlnJrrlUm de

dnd "UbWL t to chdnge

lOdd

Interrupt
Acknowledge
Timing

PCLK

DO-D7--------------------~------------~--~

lEI

lED

tJ

en
w

Reset
Timing

Cycle
Timing

--J/r-----------fuf--------\ "--______

CE _ _

liD o.

No.

Symbol

WR

~t;:::.======~\_=__=__=_®r-_-....J~r-::::::;;.f=========::::"

Parameter

Min

4 MHz
Max

27
TdA(DR)
Address ReqUIred Vahd to Read Data Vahd Delay
590
28
TwWRI
WR Low WIdth
390
29
TsDW(WR)
WrIte Data to WR j Setup TIme
0
30
ThDW(WR)
WrIte Data to WR t Hold TIme
0
31 -TdWR(W)---WR j to Walt Vahd Delay - - - - - - - - - - - - - 240
32
TdRD(W)
RD j to Walt Vahd Delay
240
33
TdWRf(REQ)
WR j to W/REQ Not Vahd Delay
240
RD j to W/REQ Not Vahd Delay
34
TdRDf(REQ)
240
5TcPC
35
TdWRr(REQ)
WR t to DTR/REQ Not ValId Delay
+300
36-TdRDr(REQ)--RD t to DTR/REQ Not Vahd D e l a y - - - - - - - - - 5TcPC
+300
37
TdPC(INT)
PCLK j to INT Vahd Delay
500
38
TdIAI(RD)
IN TACK to RD j (Acknowledge) Delay
39
TwRDA
RD (Acknowledge) WIdth
285
40 -TdRDA(DR)--RD j (Acknowledge) to Read Data ValId D e l a y - - - - - -190
41
TsIEI(RDA)
IEI to RD j (Acknowledge) Setup TIme
120
42
ThIEI(RDA)
IEI to RD t (Acknowledge) Hold TIme
0
43
TdIEI(IEO)
IEI to IEO Delay TIme
120
44
TdPC(!EO)
PCLK t to IEO Delay
250
45-TdRDA(INT)--RD j to INT Inacllve D e l a y - - - - - - - - - - - - -500
46
TdRD(WRQ)
RD t to WR j Delay for No Reset
30
47
TdWRQ(RD)
WR t to RD j Delay for No Reset
30
48
TwRES
WR and RD ComcIdent Low for Reset
250
49
Trc
ValId Access Recovery TIme
6TcPC
+200
NOTES
3. Parameter applies only between transactIons Involvmg the

ASCC
Open-dram output, measured with open-dram test load
Parameter IS system dependent For any ASCC In the daiSY
cham, TdIA1(RD) must be greater than the sum of TdPC(lEO)

2023-007, OOB, 009

6 MHz
Min
Max

Notes*t

420
250
0
0
200 - - - 4 200
4
200
200
5TcPC
+250
5TcPC
+250
500
4
5
250
180
100
0
100
250
500 - - - 4 15
30
250
6TcPC
+ 130

3

for the highest pnonty deVice In the daiSY cham, TsIEl(RDA)
for the ASCC, and TdIEIf(lEO) for each deVice separatmg them
In the daiSY cham
* TImings are prelImmary and subject to change
t Umts m nanoseconds (ns)

373

General
Timing

PCLt(

WIREG
REQUeST

W'REQ
WAIT _ _ _ _ _ _ _ _~--_I'---------------"

RTxC, TRxC

t

RECEIVE - - - - - - - -......

RoD

TRxe, RTxC
TRANSMIT

ToD

-Crr--f.--.----'

TRoC-------'--~--------~®~~------~d~-----------------------------------1<

\,-----FI3

OUTPUT _ _ _ _ _ _ _ _ _ _ _ _ _ _

\,--_~r_

TRoC----~\~_____~~----~\~----~r~
I
- - - , L--w-J~

CTS,DCD,iii

374

2244-007

Parameter

"MHz
Max

6 MHz

No.

Symbol

2
3
4
56
7
8
9
10 11
12
13
14
15 16
17
18
19

TdPC(REQ)
PCLK I to W/REQ Valid Delay
250
TdPC(W)
PCLK I to Walt Inactive Delay
350
TsRXC(PC)
RxC t to PCLK t Setup Time
50
50
TsRXD(RXCr)
RxD to RxC t Setup Time (Xl Mode)
0
0
ThRXD(RXCr) - RxD to RxC t Hold Time (XI Mode) - - - - - - - 150
150
TsRXD(RXCf)
RxD to RxC I Setup Time (Xl Mode)
0
0
ThRXD(RXCf)
RxD to RxC I Hold Time (Xl Mode)
150
150
TsTXC(PC)
TxC I to PCLK t Setup Time
0
0
TdTXCf(TXD)
TxC I to TxD Delay (Xl Mode)
300
TdTXCr(TXD) - TxC t to TxD Delay (XI Mode) - - - - - - - - - - - 300
TdTXD(TRX)
TxD to TRxC Delay (Send Clock Echo)
TwRTXh
RTxC High Width
180
180
RTxC Low Width
TwRTX1
180
180
TcRTX
RTxC Cycle Time
400
400
TcRTXX - - - Crystal Oscillator Period - - - - - - - - - - - 250 -1000 - - 250 TwTRXh
TRxC High Width
180
180
TwTRXI
TRxC Low Width
180
180
TcTRX
TRxC Cycle Time
400
400
200
200
TwEXT
DCD or CTS or ill Pulse Width

NOTES.
1 RxC IS RTxC or TRxC, whIchever

IS

supplYing the receive

IS

supplYing the transmit

clock
2 Txe

IS

TRxC or HTxe, whichever

clock
3. Both HTxe and ill have 30 pF capacitors to ground connected to them

Min

Min

Max

Notes*t

250
350
1,4
11,5
1,5
2,4
300
2
300---2,5-

1000

3-

I:en

...
W

III
fIl

g

4 Parameter apphes only If the data rate IS one-fourth the PCLK
rate In all other cases, no phase relationshIp between Rxe and
PCLK or TxC and PCLK IS requIred
5 Parameter appbes only to FM encodmg/decodmg
* Tlmmgs are prehmmary and subject to change.

t Units In nanoseconds (ns)

375

System
Timing

"TxC, TAxe

J

RECEIVE

\

W/REQ
REQUEST

W/AEQ
WAIT

~I-------------------------------------r---------'
1~

I----{"')---~I

t:=)~-

.NT

ATxC, TRxe
TRANSMIT

WIREQ
REQUEST

W/REQ
WAIT

-----t:===~~

DTR/REQ
REQUEST

en, oeD,RI

r

j

CD

4 MHz

No.

Symbol

Parameter

TdRXC(REQ)
RxC t
2
TdRXC(W)
RxC t
3
TdRXC(INT)
RxC t
4-TdTXC(REQ)-TxC!
5
6
7
8

TdTXC(W)
TdTXC(DRQ)
TdTXC(lNT)
TdEXT(lNT)

Min

Max

to W/REQ Vahd Delay
8
12
to Walt Inactive Delay
8
12
to INT Valid Delay
!O
16
to W/REQ Valid D e l a y - - - - - - - - - 5 - - 8

TxC I to Walt Inachve Delay
TxC I to DTR/REQ Vahd Delay

4

TxC I to INT Vahd Delay
tCD or CTS Translhon to INT Valid Delay

6
2

5

8
7
10
6

6 MHz
Min

Max

8
8

12

5

8
7

12
!O
16
5--8
4

6
2

!O

Notes*t
2
1,2
1,2
31,3
3
1,3

6

NOTES
1. Open-dram output, measured with open-dram test load
2 RxC IS RTxC or TRxC, whichever 1& supplymg the receive
clock.
TxC IS TRxC or RTxC, whichever IS sl,.pplymg the transmIt
clock

376

• Tlmmgs are prelimmary and subject to change.

t Umts equal to TePe

2244-008

Ordering
Information

Product
Number

Package/
Temp
Speed

Description

Product
Number

Package/
Temp
Speed

Z8531

CE

4.0 MHz

ASCC (40-pm)

Z8531A

CE

6.0 MHz

ASCC (40-pm)

Z8531

CM

4.0 MHz

Same as above

Z8531A

CM

6.0 MHz

Same as above

Z8531

CMB

4.0 MHz

Same as above

Z8531A

CMB

6.0 MHz

Same as above

Z8531

4.0 MHz

Same as above

Z8531A

CS

6.0 MHz

Same as above

Z8531

CS
DE

4.0 MHz

Same as above

Z8531A

DE

6.0 MHz

Same as above

Z8531

DS

4.0 MHz

Same as above

Z8531A

DS

6.0 MHz

Same as above

Z8531

PE

4.0 MHz

Same as above

Z8531A

PE

6.0 MHz

Same as above

Z8531

PS

4.0 MHz

Same as above

Z8531A

PS

6.0 MHz

Same as above

NOTES C == CeramIc, D = Cerdlp, P :::: Plastic, eM = -55°C to + 125°e, E = -40°C to +85°C, M
MB = -55°C to + 125°C WIth MIL-STD-883 Class B processmg, S :::: DOC to +70"C

(JtI.OIjIj 01

Description

=

·55°C to 125°C,

377

Z8536 CIO
Counler/Timer and
Parallel I/O Unil

~
Zilog

Product
Specification

June 1982

Features

General
Description

• Two independent 8-bit, double-buffered,
bidirectional I/O ports plus a 4-bit
special-purpose I/O port. I/O ports
feature programmable polarity,
programmable direction (Bit mode). "pulse
catchers," and programmable opendrain outputs.

• Flexible pattern-recognition logic, programmable as a 16-vector interrupt controller.

• Four handshake modes, including 3-Wire
(like the IEEE-488).

• Three independent 16-bit counter/timers
with up to four external access lines per
counter/timer (count input, output, gate,
and trigger), and three output duty cycles
(pulsed, one-shot, and square-wave).
programmable as retriggerable or
nonretriggerable.

• REQUESTIWAIT signal for high-speed data
transfer.

• Easy to use since all registers are
read/write.

The Z8536 CIO Counter/Timer and
Parallel I/O element is a general-purpose
peripheral circuit, satisfying most counter/
timer and parallel I/O needs encountered in
system designs. This versatile device contains
three I/O ports and three counter/timers. Many
programmable options tailor its configuration
to specific applications. The use of the device
is Simplified by making all internal registers

(command, status, and data) readable and
(except for status bits) writable. In addition,
each register is given its own unique internal
address, so that any register can be accessed
in two operations. All data registers can be
directly accessed in a single operation. The
CIO is easily interfaced to all popular
microprocessors.

-l
D

_ D e'

_D,

DATA
BUS

........ D4
~ D3

_D,

l

D,

-Do

PAs

-w.

CONTROL,
TIMING,
AND RESET

----+- iffi
----+- A1

PA,

Z8538
CIO

----+- Ao

----+- CE

iN'i
INTERRUPT

{

----+- INTACK
lEI
lEO

PAs
PAs
PA,
INTACK

iNT
+5'

Pc,
Pc,

PCLK +S V GND

Figure 1. Pin Functions

2021-035,036

Figure 2. Pin Assignment.

379

II
VI

=
a

Pin
Description

Ao-Al' Address Lines (input). These two lines
are used to select the register involved in the
CPU transaction: Port A's Data register, Port
B's Data register, Port C's Data register, or a
control register.
CEo Chip Enable (input, active Low). A Low
level on this input enables the CIa to be read
from or written to.
Do-D? Data Bus (bidirectional 3-state). These
eight data lines are used for transfers between
the CPU and the CIa.
lEI. Interrupt Enable In (input, active High).
IEI is used with lEO to form an interrupt daisy
chain when there is more than one interruptdriven device. A High lEI indicates that no
other higher priority device has an interrupt
under service or is requesting an interrupt.
lEO. Interrupt Enable Out (output, active
High). IEO is High only if lEI is High and the
CPU is not servicing an interrupt from the
requesting CIa or is not requesting an interrupt (Interrupt Acknowledge cycle only). lEO
is connected to the next lower priority device's
lEI input and thus inhibits interrupts from
lower priority devices.
INT. Interrupt Request (output, open-drain,
active Low). This signal is pulled Low when
the CIa requests an interrupt.
INTACK. Interrupt Acknowledge (input, active
Low). This input indicates to the CIa that an
Interrupt Acknowledge cycle is in progress.
INTACK must be synchronized to PCLK, and

it must be stable throughout the Interrupt
Acknowledge cycle.
PAo-PA,. Port A I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the CIa's Port A
and external devices.
PBo-PB,. Port B I/O lines (bidirectional,
3-state, or open-drain). These eight I/O lines
transfer information between the CIa's Port B
and external devices. May also be used to
provide external access to Counter/Timers
1 and 2.
PCo-PCa. Port C I/O lines (bidirectional,
3-state, or open-drain). These four I/O lines
are used to provide handshake, WAIT, and
REQUEST lines for Ports A and B or to provide
external access to Counter/Timer 3 or access
to the CIa's Port C.
PCLK. Peripheral Clock (input, TTLcompatible). This is the clock used by the
internal control logic and the counter/timers
in timer mode. It does not have to be the
CPU clock.
RD*. Read (input, active Low). This signal
indicates that a CPU is reading from the CIa.
During an Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the data
bus if the CIa is the highest priority device
requesting an interrupt.
WR*. Write (input, active Low). This signal
indicates a CPU write to the CIa.
'When RD and WR are detected Low at the same 11m. (normally
an llleqal condition). the CIO

Architecture

The CIa Counter/Timer and Parallel I/O
element (Figure 3) consists of a CPU interface,

IS

reset.

three I/O ports (two general-purpose 8-bit
ports and one special-purpose 4-bit port),

INTERRUPT
CONTROL
LOGIC

DATA BUS

CPU

.-------:----1\1

INTERFACE

CONTROL
INPUTS

INTERNAL
CONTROL
LOGIC

Figure S. CIO Bloc:k Diagram

380

2021-001

Architecture
(Continued)

TO COUNTERfTlMERS 1 AND 2
(PORT B ONLy)
INTERNAL

~

2f

INPUT

BUFFERl
INVERTERS
AND
1',
CATCHER

PORT

110

OUTPUT
BUFFERf
INVERTERS

Figure 4. Poris A and B Block Diagram

three 16-bit counter/timers, an interruptcontrol logic block, and the internal-control
logic block, An extensive number of programmable options allow the user to tailor the configuration to best suit the specific application,
The two general-purpose 8-bit I/O ports
(Figure 4) are identical, except that Port B can
be specified to provide external access to
Counter/Timers 1 and 2. Either port can be
programmed to be a handshake-driven,
double-buffered port (input, output, or bidirectional) or a control-type port with the direction
of each bit indiVidually programmable. Each
port includes pattern-recognition logic, allowing interrupt generation when a specific pattern is detected. The pattern-recognition logic
can be programmed so the port functions like
a priority-interrupt controller. Ports A and B
can also be linked to form a 16-bit I/O port.
To control these capabilities, both ports contain 12 registers. Three of these registers, the
Input, Output, and Buffer registers, comprise
the data path registers. Two registers, the
Mode Specification and Handshake Specification registers, are used to define the mode of
the port and to specify which handshake, if
any, is to be used. The reference pattern for
the pattern-recognition logic is defined via

2014·002

three registers: the Pattern Polarity, Pattern
Transition, and Pattern Mask registers. The
detailed characteristics of each bit path (for
example, the direction of data flow or whether
a path is inverting or noninverting) are programmed using the Data Path Polarity, Data
Direction, and Special I/O Control registers.
The primary control and status bits are
grouped in a single register, the Command
and Status register, so that after the port is initially configured, only this register must be accessed frequently, To facilitate initialization,
the port logic is designed so that registers
assoctated with an unrequired capability are
ignored and do not have to be programmed.
The function of the special-purpose 4-bit
port, Port C (Figure 5), depends upon the
roles of Ports A and B. Port C provides the
required handshake lines. Any bits of Port C
not used as handshake lines can be used as
I/O lines or to provide external access for the
third counter/timer.
Since Port C's function is defined primarily
by Ports A and B, only three registers (besides
the Data Input and Output registers) are
needed. These registers specify the details of
each bit path: the Data Path Polarity, Data
Direction, and Special I/O Control registers.

381

Architecture
(Continued)

TOCOUNTERI
TIMER 3

INPUT
BUFFERI
INVERTERS
AND

",

CATCHER

PORT

I/O

OUTPUT
BUFFERI
INVERTERS

C~~~~~L
PORT

~ ~ONTROL

)'-----<:.NTERNAL PORT
\
LINES

Figure 5. Port C Block Diagram

The three counter/timers (Figure 6) are all
identical. Each is comprised of a 16-bit downcounter, a 16-bit Time Constant register
(which holds the value loaded into the downcounter), a IS-bit Current Count register (used
to read the contents of the down-counter), and
two 8-bit registers for control and status (the
Mode Specification and the Command and
Status registers).
The capabilities of the counter/timer are
numerous. Up to four port I/O lines can be
dedicated as external access lines for each
counter/timer: counter input, gate input, trigger input, and counter/timer output. Three different counter/timer output duty cycles are
available: pulse, one-shot, or square-wave.

382

The operation of the counter/timer can be programmed as either retriggerable or nonretriggerable. With these and other options, most
counter/timer applications are covered.
There are five registers (Master Interrupt
Control register, three Interrupt Vector
,registers, and the Current Vector register)
associated with the interrupt logic. In addition,
the ports' Command and Status registers and
the counter/timers' Command and Status
registers include bits associated with the interrupt logic. Each of these registers contains
three bits for interrupt control and status:
Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE).

2014·003

Architecture
(Continued)

INTERNAL
BUS

-r-AI(
A

'f

~

TIME
CONSTANT
REGISTER
(MSaa)

~

~

[---y'

---,I

CURRENT
COUNT
REGISTER
(MSaa)

f--

I--

180811
DOWN
COUNTER

~

TIME
CONSTANT

REGISTER
(LSaa)

f--------t-,

~
...

TIMER

CONTROL
LOGIC

I

-,I

>

COUNT

..1JrOUNTER

Jl
COUNTERI

CURRENT
REGISTER
(LSBI)

en
==

CONTROL

LINES

'I

A

'I

~

3

=
S

-ul

TO PORT

Figure 8. Counter/Timer Block Diagram

Functional
Description

The following describes the functions
of the ports, pattern-recognition logic,
counter/timers, and interrupt logic.

1/0 Port Operations. Of the CIO's three I/O
ports, two (Ports A and B) are generalpurpose, and the third (Port C) is a specialpurpose 4-bit port. Ports A and B can be configured as input, output, or bidirectional ports
with handshake. (Four different handshakes
are available.) They can also be linked to form
a single 16-bit port. If they are not used as
ports with handshake, they provide 16 input or
output bits with the data direction programmable on a bit-by-bit basis. Port B also provides access for Counter/Timers 1 and 2. In all
configurations, Ports A and B can be programmed to recognize specific data patterns
and to generate interrupts when the pattern is
encountered.
The four bits of Port C provide the handshake lines for Ports A and B when required.
A REQUESTIWAIT line can also be provided
so that CIO transfers can be synchronized with
DMAs or CPUs. Any Port C bits not used for
handshake or REQUEST/WAIT can be used as
input or output bits (individually data-direction
programmable) or external access lines for
Counter/Timer 3. Port C does not contain any
pattern-recognition logic. It is, however,
capable of bit-addressable writes. With this
feature, any combination of bits can be set
and/or cleared while the other bits remain
undisturbed without first reading the register.
Bit Port Operations. In bit port operations, the

2014-004

port's Data Direction register specifies the
direction of data flow for each bit. A 1
specifies an input bit, and a 0 specifies an output bit. If bits are used as I/O bits for a
counter/timer, they should be set as input or
output, as required.
The Data Path Polarity register provides the
capability of inverting the data path. A 1
specifies inverting, and a 0 specifies noninverting. All discussions of the port operations assume that the path is noninverting.
The value returned when reading an input
bit reflects the state of the input just prior to
the read. A l's catcher can be inserted into the
input data path by programming a 1 to the
corresponding bit pOSition of the port's Special
I/O Control register. When a 1 is detected at
the l' s catcher input, its output is set to 1 until
it is cleared. The l's catcher is cleared
by writing a 0 to the bit. In all other cases,
attempted writes to input bits are ignored.
When Ports A and B include output bits,
reading the Data register returns the value
being output. Reads of Port C return the state
of the pin. Outputs can be specified as opendrain by writing a I to the corresponding bit of
the port's Special I/O Control register. Port C
has the additional feature of bit-addressable
writes. When writing to Port C, the four most
significant bits are used as a write protect
mask for the least significant bits (0-4, 1-5,
2-6, and 3-7). If the write protect bit is written
with a 1, the state of the corresponding output
bit is not changed.

383

Functional
Description
(Continued)

Ports with Handshake Operation. Ports A and
B can be specified as 8-bit input, output, or
bidirectional ports with handshake. The CIa
provides four different handshakes for its
ports: Interlocked, Strobed, Pulsed, and
3-Wire. When specified as a port with handshake, the transfer of data into and out of the
port and interrupt generation is under control
of the handshake logic. Port C provides the
handshake lines as shown in Table 1. Any Port
C lines not used for handshake can be used as
simple I/O lines or as access lines for
Counter/Timer 3.
When Ports A and B are configured as ports
with handshake, they are double-buffered.
This allows for more relaxed interrupt service
routine response time. A second byte can be
input to or output from the port before the
interrupt for the first byte is serviced. Normally, the Interrupt Pending (lP) bit is set and
an interrupt is generated when data is shifted
into the Input register (input port) or out of the
Output register (output port). For input and
output ports, the IP is automatically cleared
when the data is read or written. In bidirectional ports, IP is cleared only by command.
When the Interrupt on Two Bytes (lTB) control
bit is set to 1, interrupts are generated only
when two bytes of data are available to be read
or written. This allows a minimum of 16 bits of
information to be transferred on each interrupt. With ITB set, the IP is not automatically
cleared until the second byte of data is read
or written.
When the Single Buffer (SB) bit is set to 1,
the port acts as if it is only single-buffered.
This is useful if the handshake line must be
stopped on a byte-by-byte basis.
Ports A and B can be linked to form a 16-bit
port by programming a 1 in the Port Link Control (PLC) bit. In this mode, only Port A's
Handshake Specification and Command and
Status registers are used. Port B must be
specified as a bit port. When linked, only Port
A has pattern-match capability. Port B's
Port AlB Configuration

PC3

pattern-match 'capability must be disabled.
Also, when the ports are linked, Port B's Data
register must be read or written before
Port A's.
When a port is specified as a port with handshake, the type of port it is (input, output, or
bidirectional) determines the direction of data
flow. The data direction for the bidirectional
port is determined by a bit in Port C (Table 1).
In all cases, the contents of the Data Direction
register are ignored. The contents of the
Special I/O Control register apply only to output bits (3-state or open-drain). Inputs may not
have l's catchers; therefore, those bits in the
Special I/O Control register are ignored. Port
C lines used for handshake should be programmed as inputs. The handshake specification overrides Port C's Data Direction register
for bits that must be outputs. The contents of
Port C's Data Path Polarity register still apply.
Interlocked Handshake. In the Interlocked
Handshake mode, the action of the CIa must
be acknowledged by the external device
before the next action can take place. Figure 7
shows timing for Interlocked Handshake. An
output port does not indicate that new data is
available until the external device indicates it
is ready for the data. Similarly, an input port
does not indicate that it is ready for new data
until the data source indicates that the
previous byte of the data is no longer
available, thereby acknowledging the input
port's acceptance of the last byte. This allows
the CIa to interface directly to the port of a Z8
microcomputer, a UPC, an FlO, an FIFO, or
to another CIa port with no external logic.
A 4-bit deskew timer can be inserted in the
Data Available (DAV) output for output ports.
As data is transferred to the Buffer register,
the deskew timer is triggered. After the
number of PCLK cycles specified by the
deskew timer time constant plus one, DAV is
allowed to go Low. The deskew timer therefore
guarantees that the output data is valid for a
specified minimum amount of time before DA V
~

PCl

PCo

BIt I/O
REQUESTIWAIT
or Bit I/O

BIt I/O

ACKIN

REQUEST/WAIT
or Bit I/O

BIt I/O

RFD or DAY

ACKIN

Port A or B: Input Port (3-WIre
Handshake)
Port A or B: Output Port (3-Wlre
Handshake)

RFD (Output)

DAY (Input)

REQUEST /W AIT
or Bit 1/0

DAC (Output)

DAY (Output)

DAC (Input)

RFD (Input)

Port A or B: BIdIrectIonal Port
(Interlocked or Strobed Handshake)

RFD or DAY

ACKIN

REQUEST/WAIT
or BIt 110
REQUEST/WAIT
or BIt I/O

Ports A and B: BIt Ports
Port A: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake) •

BI! I/O
RFD or DAY

Port B: Input or Output Port
(Interlocked, Strobed, or Pulsed
Handshake) •

Bit 110

BIt I/O

IN/OUT

*Both Ports A and B can be speclhed mput or output wIth Interlocked, Strobed, or Pulsed Handshake at the same bme If neIther uses
REQUEST/WAIT.

Table 1. Port C Bit Utilization

384

Functional
Description
(Continued)

goes Low. Deskew timers are available for output ports independent of the type of handshake
employed.
Strobed Handshake. In the Strobed Handshake mode, data is "strobed" into or out of
the port by the external logic. The falling edge
of the Acknowledge Input (ACKIN) strobes
data into or out of the port. Figure 7 shows
timing for the Strobed Handshake. In contrast
to the Interlocked handshake, the signal
indicating the port is ready for another data
transfer operates independently of the ACKIN
input. It is up to the external logic to ensure
that data overflows or underflows do not occur.
3-Wire Handshake. The 3-Wire Handshake is
designed for the situation in which one output
port is communicating with many input ports
simultaneously. It is essentially the same as the
Interlocked Handshake, except that two signals
are used to indicate if an input port is ready
for new data or if it has accepted the present
data. In the 3-Wire Handshake (Figure 8), the
rising edge of one status line indicates that the
port is ready for data, and the rising edge of
another status line indicates that the data has
been accepted. With the 3-Wire Handshake
the output lines of many input ports can be '
bussed together with open-drain drivers; the
output port knows when all the ports have
accepted the data and are ready. This is the
INPUT HANDSHAKE

DATA::X:

same handshake as is used on the IEEE-488
bus. Because this handshake requires three
lines, only one port (either A or B) can be a
3-Wire Handshake port at a time. The 3-Wire
Handshake is not available in the bidirectional
mode. Because the port's direction can be
changed under software control, however,
bidirectional IEEE-488-type transfers can be
performed.
Pulsed Handshake. The Pulsed Handshake
(Figure 9) is designed to interface to
mechanical-type devices that require data to
be held for long periods of time and need
relatively wide pulses to gate the data into or
out of the device. The logic is the same as the
Interlocked Handshake mode, except that an
internal counter/timer is linked to the handshake logic. If the port is specified in the input
mode, the timer is inserted in the ACKIN path.
The external ACKIN input triggers the timer
and its output is used as the Interlocked Handshake's normal acknowledge input. If the port
is an output port, the timer is placed in the
Data Available (DAV) output path. The timer is
triggered when the normal Interlocked Handshake DAV output goes Low and the timer output is used as the actual DAV output. The
counter/timer maintains all of its normal
capabilities. This handshake is not available to
bidirectional ports.
OUTPUT HANDSHAKE

VALID

X'"_________

DATA _____~~"-E-~~.~n~E--------

STROBED

HANDSHAKE-..r -

RFD
DATA LATCHED
IN BUFFER REGISTER

-

-,---

DATA MOVED
TO INPUT
REGISTER

)----

INTERLOCKED
HANDSHAKE

STROBED
HANDSHAKE

BUFFER REGISTER
"EMPTIED"

NEXT Byre
SHIFTED FROM
OUTPUT REGISTER TO
BUfFER REGISTER

Figure 7. Interlocked and Strobed Handshake.

OUTPUT HANDSHAKE

INPUT HANDSHAKE

DATA

=::x

VALID

Dii

DATA _ _ _ _ _ _ _ _-'l[\-:."="X:;..T...:8:;..YT="_ __
RI'D

INPUT

INPUT

RPD ---i'~",
OUTPUT

_ _ _ _ _ _....J

DAC
INPUT

DAC
OUTPUT

X'"_________

_ _ _~....J

DAV
OUTPUT

BUfFER REGISTER

"EMPTIED"

NEXT BYTE
SHIFTED FROM
OUTPUT REGISTER TO
BUFFER REGISTER

Figure 8. 3-Wire Handshake

2014·005, 006

385

Functional
Description
(Continued)

REQUEST/WAIT Line Operation. Port C can
be programmed to provide a status signal output in addition to the normal handshake lines
for either Port A or B when used as a port with
handshake. The additional signal is either a
REQUEST or WAIT signal. The REQUEST
signal indicates when a port is ready to perform a .data transfer via the CPU interface. It is
intended for use with a DMA-type device. The
WAIT signal provides synchronization for
transfers with a CPU. Three bits in the Port
Handshake SpeCification register provide controls for the REQUEST/WAIT logic. Because
the extra Port C line is used, only one port can
be speCified as a port with a handshake and a
REQUEST/WAIT line. The other port must be
a bit port.
Operation of the REQUEST line is modified
by the state of the port's Interrupt on Two
Bytes (ITB) control bit. When ITB is 0, the
REQUEST line goes active as soon as the CIO
is ready for a data transfer. If ITB is I,
REQUEST does not go active until two bytes
can be transferred. REQUEST stays active as
long as a byte is available to be read or
written.
The SPECIAL REQUEST function is reserved
for use with bidirectional ports only. In this
case, the REQUEST line indicates the status of
the register not being used in the data path at
that time. If the IN/OUT line is High, the
REQUEST line is High when the Output
register is empty. If IN/OUT is Low, the
REQUEST line is High when the Input register
is full.
Pattern-Recognition Logic Operation. Both
Ports A and B can be programmed to generate
interrupts when a specific pattern is recognized at the port. The pattern-recognition logic
is independent of the port application, thereby
alloWing the port to recognize patterns in all of
its configurations. The pattern can be independently speCified for each bit as I, 0, rising
edge, falling edge, or any transition. Individual bits may be masked off. A patternmatch is defined as the simultaneous satisfaction of all nonmasked bit specifications in the
AND mode or the satisfaction of any nonmasked bit speCifications in either of the OR or
OR-Priority Encoded Vector modes.
INPUT PORT

ACKIN'

OUTPUT PORT

The pattern speCified in the Pattern Definition register assumes that the data path is programmed to be noninverting. If an input bit in
the data path is programmed to be inverting,
the pattern detected is the oppOSite of the one
speCified. Output bits used in the patternmatch logiC are internally sampled before the
invertlnoninvert logic.
Bit Port Pattern-Recognition Operations. During bit port operations, pattern-recognition
may be performed on all bits, including those
used as I/O for the counter/timers. The input
to the pattern-recognition logic follows the
value at the pins (through the invert/noninvert
logic) in all cases except for simple inputs with
l's catchers. In this case, the output of the I's
catcher is used. When operating in the AND
or OR mode, it is the transition from a nomatch to a match state that causes the interrupt. In the "OR" mode, if a second match
occurs before the first match goes away, it
does not cause an interrupt. Since a match
condition only lasts a short time when edges
are specified, care must be taken to avoid
losing a match condition. Bit ports speCified in
the OR-Priority Encoded Vector mode generate
interrupts as long as any match state exists. A
transition from a no-match to a match state is
not required.
The pattern-recognition logic of bit ports
operates in two basic modes: transparent and
latched. When the Latch on Pattern Match
(LPM) bit is set to (Transparent mode). the
interrupt indicates that a speCified pattern has
occurred, but a read of the Data register does
not necessarily indicate the state of the port at
the time the interrupt was generated. In the
Latched mode (LPM = I), the state of all the
port inputs at the time the interrupt was
generated is latched in the input register and
held until IP is cleared. In all cases, the PMF
indicates the state of the port at the time it is
read.
If a match occurs while IP is already set, an
error condition exists. If the Interrupt On Error
bit (IOE) is 0, the match is ignored. However,
if IOE is I after the first IP is cleared, it is
automatically set to I along with the Interrupt
Error (ERR) flag. Matches occurring while ERR
is set are ignored. ERR is cleared when the
corresponding IP is cleared.
When a pattern-match is present in the ORPriority Encoded Vector mode, IP is set to I.
The IP cannot be cleared until a match is no
longer present. If the interrupt vector is allowed to include status, the vector returned during Interrupt Acknowledge indicates the
highest priority bit matching its specification at
the time of the Acknowledge cycle. Bit 7 is the
highest priority and bit is the lowest. The bit
initially causing the interrupt may not be the
one indicated by the vector if a higher priority
bit matches before the Acknowledge. Once the

°

°

Figure 9. Pulsed Handshake

386

2014-007

Functional
Description
(Continued)

Acknowledge cycle is initiated, the vector is
frozen until the corresponding IP is cleared.
Where inputs that cause interrupts might
change before the interrupt is serviced, the I's
catcher can be used to hold the value.
Because a no-match to match transition is not
required, the source of the interrupt must be
cleared before IP is cleared or else a second
interrupt is generated. No error detection IS
performed in this mode, and the Interrupt On
Error bit should be set to O.
Ports with Handshake Pattern-Recognition
Operation. In this mode, the handshake logic
normally controls the setting of IP and,
therefore, the generation of interrupt requests.
The pattern-match logic controls the PatternMatch Flag (PMF). The data IS compared with
the match pattern when it is shifted from the
Buffer register to the Input register (mput port)
or when it is shifted from the Output register to
the Buffer register (output port). The pattern
match logIC can override the handshake logic
in certain situations. If the port is programmed
to interrupt when two bytes of data are
available to be read or written, but the first
byte matches the specIfied pattern, the
pattern-recognition logic sets IP and generates
an interrupt. While PMF is set, IP cannot be
cleared by reading or writing the data
registers. IP must be cleared by command.
The input register is not emphed while IP is
set, nor is the output register filled until IP is
cleared.
If the Interrupt on Match Only (IMO) bit IS
set, IP is set only when the data matches the
pattern. This is useful in DMA-type applicahon
when interrupts are required only after a block
of data IS transferred.

Counter/Timer Operation. The three
independent 16-bit counter/timers consist of a
presettable 16-bit down counter, a 16-bit Time
Constant register, a 16-bit Current Counter
register, an 8-bit Mode Specification register,
an 8-bit Command and Status register, and the
associated control logic that links these registers.

Function

C/Tl

CIT2

ClTa

Counter/TImer Output

PB 4

PBO

PC

Counter Input

PB 5

PB I

PC I

TrIgger Input

PB 6

PB 2

PC2

Gate Input

PB 7

PB 3

PC 3

a

Table 2. Counter/Timer External Access

The flexibility of the counter/hmers is
enhanced by the provision of up to four lines
per counter/timer (counter input, gate mput,
trigger input, and counter/timer output) for
direct external control and status. Counter/
Timer I's external I/O lines are proVided by
the four most Significant bits of Port B.
Counter/Timer 2's are provided by the four
least significant bits of Port B. Counter/Timer
3' s external I/O lines are provided by the four
bits of Port C. The utilization of these lines
(Table 2) is programmable on a blt-by-bit basis
via the Counter/Timer Mode Specification
registers.
When external counter/timer I/O lines are
to be used, the associated port lines must be
vacant and programmed in the proper data
direction. Lines used for counter/timer I/O
have the same characteristics as simple input
lines. They can be specified as inverting or
noninverting; they can be read and used with
the pattern-recognition logic. They can also
include the I's catcher input.
Counter/Timers I and 2 can be lmked internally in three different ways. Counter/Timer
I's output (inverted) can be used as Counter/
Timer 2's trigger, gate, or counter input.
When linked, the counter/timers have the
same capabilities as when used separately. The
only restriction is that when Counter/Timer I
drives Counter/Timer 2's count input,
Counter/Timer 2 must be programmed with
its external count input disabled.
There are three duty cycles available for the
timer/counter output: pulse, one-shot, and
square-wave. Figure 10 shows the counter/
timer waveforms. When the Pulse mode

r-1 r-1 . , r-1 1""", r-1 r-1 rL.J L.J L.J LJ LJ L.J L.J L.J

r-1

PCLKI2 OR
COUNTER INPUT.....J

TRIGGER

~

GATE

I
PULSE OUTPUT

,c

LJ

'l

I 'c-. I 'c-. I ,c-, 1···1

1 6:1
II

------_/--.-.1

L-

/f

ONE SHOT

OU1'PUT _ _ _...1
SQUARE WAVE
OUTPUT

FIRSTHALF _ _ _ _ _ _ _ _ _ _ _ _ _-IfJI'--_ _......

SQUARE WAYE
OUTPUT

---------------I0~·----~

SECOND HALF

Figure 10. Counter/Timer Waveforms
2014-008

387

Functional
Description
(Continued)

388

is specified, the output goes High for one
clock cycle, beginning when the down-counter
leaves the count of 1. In the One-Shot mode,
the output goes High when the counter/timer is
triggered and goes Low when the downcounter reaches O. When the square-wave output duty cycle is specified, the counter/timer
goes through two full sequences for each
cycle. The initial trigger causes the downcounter to be loaded and the normal countdown sequence to begin. If a 1 count is
detected on the down-counter's clocking edge,
the output goes High and the time constant
value is reloaded. On the clocking edge, when
both the down-counter and the output are l's,
the output is pulled back Low.
The Continuous/Single Cycle (C/SC) bit in
the Mode Specification register controls operation of the down-counter when it reaches terminal count. If C/SC is 0 when a terminal
count IS reached, the countdown sequence
stops. If the C/SC bit is 1 each time the countdown counter reaches 1, the next cycle causes
the time constant value to be reloaded. The
time constant value may be changed by the
CPU, and on reload, the new time constant
value is loaded.
Counter/timer operations require loading the
time constant value in the Time Constant
register and initiating the countdown sequence
by loading the down-counter with the time
constant value. The Time Constant register is
accessed as two 8-bit registers. The registers
are readable as well as writable, and the
access order is irrelevant. A 0 in the Time
Constant register specifies a time constant of
65,536. The down-counter is loaded in one of
three ways: by writing a 1 to the Trigger Command Bit (TCB) of the Command and Status
register, on the rising edge of the external
trigger input, or, for Counter/Timer 2 only, on
the rising edge of Counter/Timer l's internal
output if the counters are linked via the trigger
input. The TCB is write-only, and read always
returns O.
Once the down-counter is loaded, the countdown sequence continues toward terminal
count as long as all the counter/timers' hardware and software gate inputs are High. If any
of the gate inputs goes Low (0). the countdown
halts. It resumes when all gate inputs are 1
again.
The reaction to triggers occurring during a
countdown sequence is determined by the state
of the Retrigger Enable Bit (REB) in the Mode
Specification register. If REB is 0, retriggers
are ignored and the countdown continues normally. If REB is 1, each trigger causes the
down-counter to be reloaded and the countdown sequence starts over again. If the output
is programmed in the Square-Wave mode,
retrigger causes the sequence to start over
from the initial 19ad of the time constant.

The rate at which the down-counter counts is
determined by the mode of the counter/timer.
In the TImer mode (the External Count Enable
[ECE] bit is 0). the down-counter is clocked
internally by a signal that is half the frequency
of the PCLK input to the chip. In the Counter
mode (ECE is 1), the down-counter is decremented on the rising edge of the counter/
timer's counter input.
Each time the counter reaches terminal
count, its Interrupt Pending (IP) bit is set to 1,
and if interrupts are enabled (IE = I). an interrupt is generated. If a terminal count occurs
while IP is already set, an internal error flag is
set. As soon as IP is cleared, it is forced to 1
along with the Interrupt Error (ERR) flag.
Errors that occur after the internal flag is set
are ignored.
The state of the down-counter can be determined in two ways: by reading the contents of
the down-counter via the Current Count
register or by testing the Count In Progress
(ClP) status bit in the Command and Status
register. The CIP status bit is set when the
down-counter is loaded; it is reset when the
down-counter reaches O. The Current Count
register is a 16- bit register, accessible as two
8-bit registers, which mirrors the contents of
the down-counter. This register can be read
anytime. However, reading the register is
asynchronous to the counter's counting, and
the value returned is valid only if the counter
is stopped. The down-counter can be reliably
read "on the fly" by the first writing of a 1 to
the Read Counter Control (RCC) bit in the
counter/timer's Command and Status register.
This freezes the value in the Current Count
register until a read of the least significant
byte is performed.

Interrupt Logic Operation. The CIa has five
potential sources of interrupts: the three
counter/timers and Ports A and B. The
priorities of these sources are fixed in the
following order: Counter/Timer 3, Port A,
Counter/Timer 2, Port B, and Counter/Timer
1. Since the counter/timers all have equal
capabilities and Ports A and B have equal
capabilities, there is no adverse impact from
the relative priorities.
The CIa interrupt priority, relative to other
components within the system, is determined
by an interrupt daisy chain. Two pins, Interrupt Enable In (IEI) and Interrupt Enable Out
(IEO), provide the input and output necessary
to implement the daisy chain. When lEI is
pulled Low by a higher priority deVice, the
CIa cannot request an interrupt of the CPU.
The following discussion assumes that the lEI
line is High.
Each source of interrupt in the CIa contains
three bits for the control and status of the
interrupt logic: an Interrupt Pending (IP)
status bit, an Interrupt Under Service (IUS)

Functional
Description
(Continued)

status bit, and an Interrupt Enable (IE) control
bit. IP is set when an event requiring CPU
intervention occurs. The setting of IP results in
forcing the Interrupt (INT) output Low, if the
associated IE is 1.
The IUS status bit is set as a result of the
Interrupt Acknowledge cycle by the CPU and
is set only if its IP is of highest priority at the
time the Interrupt Acknowledge commences.
It can also be set directly by the CPU. Its
primary function is to control the interrupt
daisy chain. When set, it disables lower priority sources in the daisy chain, so that lower
priority interrupt sources do not request servicing while higher priority devices are being
serviced.
The IE bit provides the CPU with a means of
masking off individual sources of interrupts.
When IE is set to 1, interrupt is generated normally. When IE is set to 0, the IP bit is set
when an event occurs that would normally
require service; however, the INT output is not
forced Low.
The Master Interrupt Enable (MIE) bit allows
all sources of interrupts within the CIO to be
disabled without haVing to individually set
each IE to O. If MIE is set to 0, all IPs are
masked off and no interrupt can be requested
or acknowledged. The Disable Lower Chain
(DLC) bit is included to allow the CPU to
modify the system daisy chain. When the DLC
bit is set to 1, the CIO's IEO is forced Low,
independent of the state of the CIO or its lEI

input, and all lower priority devices' interrupts
are disabled.
As part of the Interrupt Acknowledge cycle,
the CIO is capable of responding with an 8-bit
interru pt vector that specifies the source of the
interrupt. The CIO contains three vector
registers: one for Port A, one for Port B, and
one shared by the three counter/timers. The
vector output is inhibited by setting the No
Vector (NV) control bit to 1. The vector output
can be modified to mclude status information
to pinpoint more precisely the cause of interrupt. Whether the vector includes status or not
is controlled by a Vector Includes Status (VIS)
control bit. Each base vector has its own VIS
bit and is controlled independently. When
MIE = 1, reading the base vector register
always includes status, independent of the
state of the VIS bit. In this way, all the information obtained by the vector, including
status, can be obtained with one additional
instruction when VIS is set to O. When
MIE = 0, reading the vector register returns
the unmodified base vector so that it can be
verified. Another register, the Current Vector
register, allows use of the CIO in a polled environment. When read, the data returned is
the same as the interrupt vector that would be
output in an acknowledge, based on the
highest priority IP set. If no unmasked IPs are
set, the value FFH is returned. The Current
Vector register is read-only.

Programming

The data registers within the CIO are
directly accessed by address lines An and Al
(Table 3). All other internal registers are
accessed by the following two-step sequence,
with the address lines specifying a control
operation. First, write the address of the target
register to an internal 6-bit Pointer Register;
then read from or write to the target register.
The Data registers can also be accessed by
this method.
An internal state machine determines if
accesses with Ao and Al equalling 1 are to the
Pointer Register or to an internal control
register (Figure 11). FollOWing any control
read operation, the state machine is in State 0
(the next control access is to the Pointer
Register). This can be used to force the state
machine into a known state. Control reads in
State 0 return the contents of the last register

pointed to. Therefore, a register can be read
continuously without writing to the Pointer.
While the CIO is in State 1 (next control
access is to the register pointed to), many
internal operations are suspended-no IPs are
set and internal status is frozen. Therefore, to
minimize interrupt latency and to allow continuous status updates, the CIO should not be
left in State 1.
The CIO is reset by forCing RD and WR Low
simultaneously (normally an illegal condition)
or by writing a 1 to the Reset bit. Reset
disables all functions except a read from or
write to the Reset bit; writes to all other bits
are ignored, and all reads return OlH. In this
state, all control bits are forced to 0 and may
be programmed only after clearing the Reset
bit (by writing a 0 to it).

Register

o

0

o

Port C's Data Register
Port E's Data RegIster

o

Port A's Data Register

1

Control RegIsters

Table 3. Register Selection
2021-002

HARDWARE
OR
_
SOFTWARE
RESET

NOTE:

State changes oc€:ur only when
accesses have effect.

Ao = Al =

1. No other

Figure II. State Machine Operation

389

Registers

Master Interrupt Control Register
Address: 000000
(Read/W rite)

MASTER INTERRUPT
ENABLE (MIE)

~J

DISABLE LOWER CHAIN (OLe)
NO VECTOR (Ny)
PORT A VECTOR INCLUDES
STATUS (PA VIS)

Master Configuration Control Register
Address: 000001
(Read/Write)

PORTBJJ~

~~RESET

l

L

ENABLE (PSE)

RIGHT JUSTIFIED ADDRESSES
0= SHIFT LEFT (Ao from AD i )
1'" RIGHT JUSTIFY (At! from ADo)

CaUNTERlTIMER 1
ENABLE (CT1E)

COUNTERITIMERS VECTOR
INCLUDES STATUS (eT VIS)

[

CONTROLS (lC)
Lei

o

ENABLE (CT2E)
PORT C AND CaUNTERI -

LCO

--0

INDEPENDENT
COUNT
CIT l'S
GATES CIT 2
CIT 1's
TRIGGERS CIT 2
IS CIT 2's
CIT 1's
COUNT INPUT
PORT A ENABLE (PAE)

o
1
1

COUNTERITIMER 2

PORT B VECTOR INCLUDES

COUNTERITIMER LINK

1
0
1

TIMER 3 ENABLE

STATUS (PS VIS)

PORT LINK CONTROL (PLe)
O=PORTS A AND B OPERATE INDEPENDENTLY

(PCE AND CT3E)

1

=PORTS A AND B ARE LINKED

Figure 12. Master Control Registers

Port Handshake Specification Registers
Addresses: 100001 Port A
101001 Port B
(Read/Write)

Port Mode Specification Registers
Addresses: 100000 Port A
101000 Port B
(Read/Write)

SELECTS
(PIS)
PORT TYPE
PT81 PTSQ.

~

----0 ----0- BIT PORT
o 1 INPUT PORT

L

HANDSHAKE TYPE SPECIFICATION

DESKEW TIMER ENABLE (DTE)
(HANDSHAKE MODES)

~~
o
o

BITS (HTS)

PATTERN MODE SPECIfiCATION

1

0

OUTPUT PORT

BITS (PMS)

1

1

BIDIRECTIONAL

PMS1 PMSO
0
DISABLE PATTERN MATCH

PORT
INTERRUPT ON TWO
BYTES (ITB)

SINGLE BUFFERED
MODE (SB)

J

1~1~1~1~1~1~1~1~1

LATCH ON PATTERN MATCH (LPM)
(BIT MODE)

o
o

1

"AND"MODE

1

0

"OR" MODE

1

1

"OR·PRIORITY ENCODED

1
1

HTSC?
0
1
0
1

INTERLOCKED HANDSHAKE
STROBED HANDSHAKE
PULSED HANDSHAKE
THREE·WIRE HANDSHAKE

----c

DESKEW TIME SPECifiCATION

BITS

~:~i~:~,~~~ ~:~sCo;NSTANT

LSB IS FORCED 1.

REQUEST/WAIT SPECIFICATION BITS
(RWS)
RWS2 RWS1 RWSO FUNCTION
~.
REQUESTIWAIT DISABLED
1
OUTPUT WAIT
1
INPUT WAIT
1
0
SPECIAL REQUEST
1
1
OUTPUT REQUEST
1
1
INPUT REQUEST

VECTOR" MODE

-

--a-

o

INTERRUPT ON MATCH ONLY (IMO)

o

Port Command and Status Registers
Addresses: 001000 Port A
001001 Port B
(Read/Partial Write)
I~I~I~I~I~I~I~I~I
INTERRUPT UNDER
SERVICE (IUS)
INTERRUPT ENABLE (IE)
INTERRUPT PENDING (IP)

±U ~
I

JUS, IE, AND IP ARE WRITTEN USING
THE FOLLOWING CODE:
NULL CODE
CLEAR IP & IUS

•••
0

0

SET IUS

0

1

CLEAR IUS

0

1

SETIP

L

L

INTERRUPT ON ERROR (IOE)
PATTERN MATCH FLAG (PMF)
(READ ONLy)
INPUT REGISTER FULL (IRF)
(READ ONLy)
OUTPUT REGISTER EMPTY (ORE)
(READ ONLy)

1

100

CLEAR IP

1

0

1

SET IE

1

1

0

CLEAR IE

1

1

1

INTERRUPT ERROR (ERR)
(READ ONLY)

Figure 13. Port Specifications Registers

390

2014-009, 010

Registers

(Continued)

Data Path Polarity Registers

Data Direction Registers

Addresses: 100010 Port A
101010 Port B
000101 Port C (4 LSBs only)
(Read/Write)

Addresses: 100011 Port A
101011 Port B
000110 Port C (4 LSBs only)
(Read/Write)

' - - - - - ~~T~u~~u~C~:~N (DO)

L -_ _ _ DATA PATH POLARITY (OPP)
0"" NON·INVERTING

1 =INPUT BIT

1 = INVERTING

Special 1/0 Control Registers
Addresses: 100100 Port A
10 1100 Port B
000111 Port C (4 LSBs only)
(Read/Write)

' - - - - - SPECIAL INPUT/OUTPUT (SIO)

0"" NORMAL INPUT OR OUTPUT
1 ",OUTPUT WITH OPEN DRAIN OR

INPUT WITH l's CATCHER

Figure 1'. BII Path Deflnlllon Regllte..
Port Data Registers

Port C Data Register

Addresses: 001101 Port A*
0011 10 Port B*
(Read/Write)

Address: 001111*
(Read/Write)

4 MSBs
O=WRITING OF CORRESPONDING LSB ENABLED
1 =WRITING OF CORRESPONDING LSB INHIBITED

.. These registers can be
addressed dIrectly.

(READ RETURNS 1)

Figure 15. Port Data Regiltera
Pattern Polarity Registers (PP)

Addresses: 100101 Port A
101101 Port B
(Read/Write)
Pattern Transition Registers (PT)

Addresses: 100110 Port A
101110 Port B
(Read/Write)

~ ~!!

o
o
1
1
1
1

0
1

X
X

0
1
1

1
0
1

o o

PATTERN SPECIFICATION
BIT MASKED OFF
ANY TRANSITION

ZERO
ONE
ONE TO ZERO TRANSITION (Io)
ZERO-YO-ONE TRANSITION (1')

Pattern Mask Registers (PM)

Addresses: 100111 Port A
101111 Port B
(Read/Write)
Figure 16. Pattern Deflnlllon Registe..

2014-011, 012, 013

391

Registers
(Continued)

CounterlTimer Command and Status Registers
Addresses: 001010 Counter/Timer 1
001011 Counter/Timer 2
001100 Counter/Timer 3
(Read/Partial Write)

INTERRUPT UNDER SERVICE (IUS)

~jJ, I

INTERRUPT ENABLE (IE)

I

I

I

I

NULL CODE

0

0

CLEAR IP & IUS

0

0

1

SET IUS

0

1

0

CLEAR IUS

0

1

1

INTERRUPT PENDING (IP)

~~

COUNT IN PROGRESS (CIP)
(READ ONLy)
TRIGGER COMMAND BIT (TCB)
(WRITE ONLY· READ RETURNS 0)
GATE COMMAND BIT (GCB)

IUS, IE, AND IP ARE WRITTEN USING

READ COUNTER CONTROL (RCe)

THE FOLLOWING CODE.

(READ/SET ONLYCLEARED BY READING eeA LSB)

0

SETIP10D
CLEAR IP

1

0

SET IE

1

1 0

1

CLEAR IE

1

1

1

INTERRUPT ERROR (ERR)
(READ ONLY)

Counter/Timer Mode Specification Registers
Addresses: 011100 Counter/TImer 1
01110 1 Counter/Timer 2
011110 Counter/Timer 3
(Read/Write)

CONTINUOUS Sl!l-

GLE CYCLE (e/SC)

JJ~

EXTERNAL OUTPUT

ENABLE (EOE)
EXTERNAL COUNT
ENABLE (EeE)
EXTERNAL TRIGGER
ENABLE (ETE)

[L

OUTPUT DUTY CYCLE

SELECTS (DeS)

~S1 D~SO PULSE OUTPUT
0
1
1

1
0
1

ONE·SHOT OUTPUT
SQUARE·WAVE OUTPUT
DO NOT SPECIFY

RETRIGGER ENABLE BIT (REB)
EXTERNAL GATE ENABLE (EGE)

CounterlTimer Current Count Registers
Addresses: 010000 Counter/Timer I's MSB
010001 Counter/Timer I's LSB
010010 Counter/Timer 2's MSB
010011 Counter/Timer 2's LSB
010100 Counter/Timer 3's MSB
010101 Counter/Timer 3's LSB
(Read Only)

MOST - - - - - '
SIGNIFICANT
BYTE

' - - - - LEAST

SIGNIFICANT
BYTE

CounterlTimer Time Constant Registers
Addresses: 010110 Counter/Timer l's MSB
010111 Counter/Timer I' s LSB
011000 Counter/Timer 2's MSB
011001 Counter/Timer 2's LSB
011010 Counter/Timer 3's MSB
011011 Counter/Timer 3's LSB
(Read/Write)

MOST-------'
SIGNIFICANT

' - - - - - LEAST
SIGNIFICANT

BYTE

BYTE

Figure 17. Counter/Timer Register.

392

2014-014

Registers
(Continued)

Interrupt Vector Register

Current Vector Register

Addresses: 000010 Port A
000011 Port B
000100 CounterlTimers
(ReacllWrite)

Address: 011111
(Read only)

L-_ _ _

~;~~:~~=if8:~ASED
UNMASKED IP.
IF NO INTERRUPT PENDING
ALL 1'. OUTPUT

L-_ _ _ INTERRUPT VECTOR
PORT VECTOR STATUS

PRIORITY ENCODED VECTOR MODE:

'!> !1J !'l
x

It

It

NUMBER OF HIGHEST PRIORITY BIT

WITH A MATCH
ALL OTHER MODES'
D3 D2 D1

ORE
o

iiF
0

PMF
0

NORMAL
ERROR

COUNTERITIMER STATUS
D2

D1

"'0"0

ctr3

1
0
1

CIT 2

o
1

1

001
ERROR

Figure 18. Interrupt Vector Reglatera

Register

Address
Summary

2014-015

Address
000000
000001
000010
000011
000100
000101
000110
000111

Main Control Registers
Register Name
Master Interrupl Control
Master Conhgurailon Conlrol
Pori A's Interrupl Veclor
Port B's Interrupt Veclor
Counterlrlmer's Interrupt Veclor
Port C's Data Path Polarity
Port C's Dala Dlfecilon
Port C's SpeClal I/O Conlrol

Address
100000
100001
100010
100011
100100
100101
100110
100111

Port A Specification Registers
Regisler Name
Pori A's Mode SpeclfICailon
Pori A's Handshake SpeclhcatlOn
Port A's Data Palh Polanty
Pori A's Data Dlfecilon
Port A's SpeCIal va Control
Port A's Pattern Polanty
Port A's Pattern Translilon
Port A's Pattern Mask

Address
001000
001001
001010
001011
001100
001101
001110
00 III I

Most Often Accessed Registers
Regisler Name
Port A's Command and Status
Port B's Command and Status
Counterlrlmer I's Command and Status
Counter/TImer 2's Command and Status
Counierlrlmer 3's Command and Status
Port A's Data (can be accessed chrectly)
Pori B's Data (can he accessed dlfectly)
Port C's Data (can be accessed dlfectly)

Address
101000
101001
101010
101011
101100
101101
101110
10 III I

Port B Specification Registers
RegIster Name
Port B's Mode SpeclfICailon
Port B's Handshake SpeClhcailon
Port B's Data Path Polanly
Pori B's Data Dlfecilon
Port B's SpecIal va Control
Pori B's Pattern Polanty
Port B's Paltern Translilon
Port B's Pattern Mask

Address
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111

Counter/Timer Related Registers
RegIster Name
Counterlrlmer I's Current Counl-MSBs
Counterlrlmer I's Currenl Count-LSBs
Counter/TImer 2'. Current Count-MSBs
Counierlrlmer 2's Current Count-LSBs
Counterlrlmer 3'. Current Counl-MSB.
Counter/TImer 3's Current Count-LSBs
Counierlrlmer I's TIme Constant-MSB.
Counterlrlmer I's TIme Conslanl-LSBs
Counterlrimer 2's TIme Conslanl-MSBs
Counterlrlmer 2's TIme Constant-LSBs
Counlerlrlmer 3's TIme Constant-MSBs
Counierlrlmer 3'. TIme Con.tant-LSBs
Counterlrlmer I's Mode SpeClhcailon
Counterlrlmer 2's Mode SpeClhcailon
Counterlrlmer 3's Mode Speclhcailon
Current Vector

393

Timing

Bead Cycle. At the beginning of a read cycle,
the CPU places an address on the address bus.
Bits Ao and Aj specify a CIa register; the
remaining address bits and status information
are combined and decoded to generate a Chip
Enable (CE) signal that selects the CIa. When
Read (RD) goes Low, data from the specified
register is gated onto the data bus.
AO-Ai

Ci
iili
.....D.

==x

Write Cycle. At the beginning of a write
cycle, the CPU places an address on the data
bus. Bits Ao and Aj specify a CIa register; the
remaining address bits and status information
are combined and decoded to generate a Chip
Enable (CE) signal that selects the CIa. When
WR goes Low, data placed on the bus by the
CPU is strobed into the specified CIa register.

x=

ADDRESS VALID

~

/
<

READ DATA

==x

Do-D•

Figure 19. R8Dd Cycle Timing

/

I

\

WR

>--

x=

ADDRESS VALID

~

iii

I

\

Ao-A.

<

)--

WRITE DATA

Figure 20. Write Cycle Timing

Interrupt Acknowl~e. The CIa pulls its
Interrupt Request (INT) line Low, requesting
interrupt service from the CPU, if an Interrupt
Pending (lP) bit is set and interrupts are
enabled. The CPU responds with an Interrupt
Acknowledge cycle. When Interrupt Acknowledge (lNTACK) goes true and the IP is set, the

CIa forces Interrupt Enable aut (lEa) Low,
disabling all lower priority devices in the interrupt daisy chain. If the CIa is the highest
priority device requesting service (lEI is
High), it places its interrupt vector on the data
bus and sets the Interrupt Under Service (IUS)
bit when Read (RD) goes Low.

Off ___________~~------JI
,J
iiiTiCK

~.rj;..--------------..Jr

lEI

~F-(- - - - - iiii

/~

Do-~ ------------~h~------~(C~VE~~~R:J)___
Figure 21. Interrupt Acknowledge TIming

394

2021-003. 004, 005

Absolute
Maximum
Ratings

Voltages on all inputs and outputs
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ................. As Specified in
Ordering Information

Stresses greater than those hsted under Absolute MaXImum Ratings may cause permanent damage to the deVIce.

ThIs 16 a stress rahng only; operation of the device at any
condItIon above those mdicated In the operational sectIons
of these speClhcahons 16 not ImplIed. Exposure to absolute
maXImum rating condItions for extended penods may affect

deVIce rehablhty.

Storage Temperature ........ -65°C to + 150 °C
Standard
Test
Conditions

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the referenced pin. Standard conditions are as follows:

• +4.75 V

S

Vee S +5.25 V

• GND = 0 V
• TA as specified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.

+5V

dr
+5V

22.

2.2.

FROM OUTPUT
UNDER TEST

50 PF

Flgur. 22. Standard T••t Load
DC
Characteristics

Symbol

VIH
VIL
VOH
VOL
IlL
IOL
Icc

Parameter

Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage

Figure 23. Open-Drain Test Load
Min

Max

Unit

2.0

Vee +0.3
0.8

V
V
V
V
V

IoH=
IoL=
IoL =

pA

0.4

pA

0.4 s VOUT

-0.3
2.4

0.4
0.5
± 10.0
± 10.0
200

Input Leakage
Output Leakage
Vee Supply Current

Condition

S

-250/LA
+2.0 rnA
+3.2 rnA
VIN S +2.4 V
S

+2.4 V

rnA

Vee = 5 V ± 5% unless otherwlse speclfied, over speclfied temperature range.

Capacitance

Symbol

CIN
COUT
CliO

Parameter

Input Capacitance
Output Capacitance
Bidirectional Capacitance

Min

Max

Unit

Test Condition

10
15
20

pF
pF
pF

Unmeasured Pins
Returned to Ground

f = 1 MHz, over specIfIed temperature range.

8085·0209, 0001

395

CPU
Interface
Timing

PCLK

AO-Ai

D~~~~

-------t--t-(

DO-D7
WRITE _ _ _ _ _ _- '

DATA VALID

;'~

CE---J/
AD or WR

Interrupt
Timing

PATTERN MATCH
INPUT(S)
BllPORT

~r-,-'===--=,-\'--_-_®)-_--J~--~---+I
~

PATIERN MATCHES

'----------------------

•

®r--------~~

ACKIN
NOTE 4

12

COUNTER

INPUT _ _ _ _ _.J

~CLK

"
34

Interrupt
Acknowledge
Timing
iii)

Do-D7

lEI

lEO

~~---

396

2021-006,007,008

No.

2

Min

Symbol

Parameter

TcPC

PCLK Cycle hme
PCLK W,dth (H,gh)

TwPCh

TwPCI
3
4
TrPC
5-TfPC
6

TsIA(PC)

7

ThIA(PC)
TsIA(RD)

INTACK to PCLK 1 Hold T,me
INTACK to RD I Setup T,me

165

4000

70

2000

2000

70

2000

100
0
200

100
0
200

0
200

0
200

11

ThIA(WR)

INTACK to WR 1 Hold T,me

0

0

TsA(RD)
ThA(RD)

Address to RD I Setup T,me

80

Address to RD 1 Hold Time
TsA(WR)
Address to WR I Setup T,me
ThA(WR)--- Address to WR 1 Hold T,me

0
80

80
0

TsCEI(RD)

CE Low to

TsCEh(RD)

CE H1gh to

18
19
20 -

ThCE(RD)
CE to RD 1 Hold T,me
TsCEI(WR)
CE Low to WR I Setup T,me
TsCEh(WR)-- CE H1gh to WR I Setup Time

21

ThCE(WR)

CE to WR 1 Hold T,me

22

TwRDl
TdRD(DRA)

RD Low Width
lID I to Read Data Achve Delay

0
70

390

250
0

0
255
0

180
0

RD 1 to Read Data Float Delay
WR Low Width
Write Data to WR I Setup T,me

390
0

0

29
30

ThDW(WR)
Trc

Write Data to WR 1 Hold T,me
Vahd Access Recovery T,me

0
1000·

0
650

31

TdPM(INT)

Pattern Match to INT Delay (Bit Port)

TdACK(INT)

ACKIN to INT Delay (Port w1th Handshake)

33
34

TdCI(INT)
TdPC(INT)

Counter Input to INT Delay (Counter Mode)
PCLK to INT Delay (T,mer Mode)

35

TsIA(RDA)

36

TwRDA
TdRDA(DR)
TdIA(IEO)

INTACK TO RD I (Acknowledge) Setup Time
RD (Acknowledge Width)

37
38
39 -

70

45

2

2
10

6
4,6

2
3

6
6

350

250

350

250

100

70

41

ThIEI(RDA)

100

70

42

TdRDA(INT)

transactIons.
Float delay 15 measured to the hme when the output has
changed 0 5 V wIth mmlmum ae load and maXImum de load
Tre IS II'S or repe, whIChever IS longer
The delay IS from DAV J for 3-Wlre Input Handshake. The
delay IS from DAC f for 3-Wlre Output Handshake.
The parameters for the devLCes m any partIcular daIsy cham

3

10
2
3

40

NOTES.
l. Parameter does not apply to Interrupt Acknowledge

2

250

RD I (Acknowledge) to Read Data Vahd Delay
INTACK I to IEO I Delay
TdIE(IEO) - - IEI to IEO Delay
TsIEI(RDA)
lEI to RD I (Acknowledge) Setup T,me

250
350

600

5
180
250
5
100---5-

150

lEI to RD 1 (Acknowledge) Hold Time
RD I (Acknowledge) to INT 1 Delay

~

0

TwWRI
TsDW(WR)

32

...

C

0

0
0
100
0

TdRD(DRz)

28

Co)
~

0
70

100

TdRD£(DR)
RD I to Read Data Vahd Delay
TdRDr(DR) - - RD 1 to Read Data Not Valid Delay

!!oil

00
U'I

80
0

0
0

lID I Setup T,me
lID I Setup T,me

16
17

Notes*t

10
15

20
20

12

26
27

5,

4000
2000

ThIA(RD)
INTACK to RD 1 Hold T,me
TsIA(WR) - - INTACK to WR I Setup Time

23
24
25 -

3
4.

105
105

6 MHz
Min
Max

8
9
10 -

13
14
15 -

2.

250

PCLK W,dth (Low)
PCLK R,se T,me
PCLK Fall Time
INTACK to PCLK 1 Setup T,me

4 MHz
Max

5
600

must meet the followng constramt: The delay from INTACK l to
RD I must be greater than the sum of TdlA(lEO} for the hIghest
pnonty perIpheral, TsIEI(RDA) for the lowest pnorIty
perIpheral, and TdIEI(lEO) for each penpheral separahng them
In

the cham

6. Umts equal to TePe + ns.
"'TJrnmgs are prellmmary and subject to change
tUmts In nanoseconds, except as noted.

397

Strobed
Handshake

INPUT

OUTPUT

Interlocked
Handshake
INPUT

DATA

~I

ACKIN

\

_¥------

DATAVALIDij'

~~
~3__

AFD __________ ___

t

,~~~-,-.~I'------------

DATA

OUTPUT

iCKiii

DAV

3-Wire
Handshake

DATA

DAV
INPUT
INPUT

AFD
OUTPUT

DAC
OUTPUT

DATA

DAC
INPUT

OUTPUT

AFD
INPUT

iiiV

OUTPUT

398

2014-022,023,024

4 MHz
No.

2
3
4
56
7
8
9
10 II
12
13
14
15 16
17
18
19
20 21
22
23

Symbol

Parameter

TsDI(ACK)
ThDI(ACK)

Min

Data Input to ACKIN I Setup Time
0
Data Input to ACKIN I Hold TimeStrobed Handshake
TdACKf(RFD)
ACKIN I to RFD I Delay
0
TwACKI
ACKIN Low Width-Strobed Handshake
TwACKh--- ACKIN HIgh Width-Strobed Handshake
TdRFDr(ACK) RFD I to ACKIN I Delay
0
TsDO(DAV)
Data Out to DA V I Setup TIme
25
TdDAVf(ACK) DAV I to ACKIN I Delay
0
ThDO(ACK)
Data Out to ACKIN I Hold TIme
2
TdACK(DAV) - ACKIN I to DAV I Delay
2
THDI(RFD)
Data Input to RFD I Hold Time-Interlocked
Handshake
TdRFDf(ACK)
RFD I to ACKIN I Delay Interlocked Handshake
0
TdACKr(RFD) ACKIN I (DA V I) to RFD I Delay-Interlocked and
3-Wlre Handwshake
0
TdDAVr(ACK) DAV I to ACKIN I (RFD I)-Interlocked and 3-Wire
Handshake
0
TdACK(DAV)- ACKIN I (RFD I) to DAV I Delay-Interlocked and
3-Wire Handshake
0
TdDAVIf(DAC) DAV I to DAC I Delay-Input 3-Wire Handshake
0
ThDI(DAC)
Data Input to DAC I Hold Time-3-Wire Handshake
0
TdDACOr(DAV) DAC I to DAV I Delay-Input 3-Wire Handshake
0
TdDAVIr(DAC) DAV I to DAC I Delay-Input 3-Wlre Handshake
0
TdDAVO£(DAC) DAV I to DAC I Delay-Output 3-Wlre Handshake - 0
ThDO(DAC)
Data Output to DAC I Hold Time-3-Wire
Handshake
2
TdDACIr(DAV) DAC I to DAV I Delay-Output 3-Wire Handshake
2
TdDAVOr(DAC) DAV I to DAC I Delay-Output 3-Wire Handshake
0

Max

6MHz
Min
Max

Notes*t

0

0

0
20
0
2
2

2
2-

N

0

00

en

0

W

0

...

~

n

C

0
0
0
0
0
0
2
2
0

2
2

NOTES:
1. ThIS hme can be extended through the use of deskew hmers.
2 UnIts equal to TePe.

* Tlmmgs are prelimmary and subject to change. All hmmg refer-

enees assume 2,0 V for a logiC "I" and O.S V for a logIC "0"

r Units 10 nanoseconds (ns), except as noted.

399

Counter/
Timer
Timing

PCLK

PCLKI2
(INTERNAL)

_ _ _ _ _..J

COUNTER
INPUT

TAIGQtR
INPUT

GATE
INPUT

COUNT ...
OUTPUT

No.

Symbol

Parameter

Min

500
230
230

I

TcCI

Counter Input Cycle TIme

2

TCIh

Counter Input HIgh WIdth

3

TWCll

Counter Input Low WIdth

4

TlCI

Counter Input Fall TIme

6 MHz

4MHz
Max

Min

20

TsTI(PC)

Tngger Input to PCLK ! Setup TIme (Timer Mode)

7

TsTI(CI)

Tngger Input to Counter Input! Setup TIme
(Counter Mode)

8

TwTI

Tngger Input Pulse Width (High or Low)

9

TsGI(PC)

Gate Input to PCLK ! Setup TIme (Timer Mode)

Notes*t

330
150
150
15
15

5-TrCI - - - - - Counter Input RIse TIme - - - - - - - - - - - - - - - - 20
6

Max

10 -

TsGI(CI) - - - Gate Input to Counter Input! Setup Time - - - - - - - - - - - - - - - - - - - - - - (Counter Mode)

II

ThGI(PC)

Gate Input to PCLK ! Hold TIme (TImer Mode)

12

ThGI(CI)

Gate Input to Counter Input ! Hold Time
(Counter Mode)

13

TdPC(CO)

PCLK to Counter Output Delay (TImer Mode)

14

TdCI(CO)

Counter Input to Counter Output Delay
(Counter Mode)

NOTES.
1. These parameters must be met to guarantee tngger or gate

are valid for the next counter/hmer cycle.

* Tlmmgs are prehmmary and subject to change All hmmg refer-

ences assume 2

a v for a logic" 1" and 0 8 V for a logiC "0"

t Umts In nanoseconds

400

(ns).

2021-009

REQUEST/

WAIT
Timing

No.

Min

Symbol

Parameter

TdRD(REQ)

RD I to REQ I Delay

2

TdRD(WAIT)

RD I to WAIT I Delay

3

TdWR(REQ)

WR I to WAIT I Delay

4

TdWR(WAIT)

WR I to WAIT I Delay

4 MHz
Max

8 MHz
Min
Max

Notes*t

5-TdPC(REQ)--PCLK I to REQ 1 Delay - - - - - - - - - - - - - - - - - - - - - - - - 6

TdPC(WAIT)

7

TdACK(REQ)

PCLK I to WAIT 1 Delay
ACKIN I to REQ 1 Delay

8

TdACK(WAIT)

ACKIN I to WAIT 1 Delay

NOTES,
1. The delay

IS frorun DAY 1 for 3~ WIre Input Handshake. The
delay IS from DAC t for 3-Wlre Output Handshake.
2. Umts equal to TcPC + ns.

Reset
Timing

RUET

Symbol

* TImings are prelimmary and subject to change. All hmmg refer-

ences assume 2.0 V for a logic "I" and 0.8 V for a logIC "0".
In nanoseconds (ns), except as noted

i Umts

:A'--------'~·- @-}
INTERNAl.

No.

1,2
1,2

--------------------~;-

Parameter

Min

TdRD(WR)

Delay from RD 1 to WR I for No Reset

2

TdWR(RD)

Delay from WR 1 to RD I for No Reset

3

TwRES

Minimum Width of RD and WR both Low for Reset

* TImmgs are prehmmary and subject to change. All hmmg references assume 2.0 V for a loglc "I" and 0.8 V for a logIC "0",

2021·010, .011

4 MHz
Max

8 MHz
Min
Max

50
50

50

250

250

Notes*t

50

t Umtes In nanoseconds (ns).

401

Miscellaneous
Port
Timing

ANY INPUT

1 1• CATCHER
INPUT

PATTERN

-----'l0+y=

-~JI-,--:--

------~~\~~--------

--------'""J~

INr:.t~~~ -----x=":"5""':"--'~~~HE~~

DATA TD BE
LATCHED TD
PATTEIIN MATCH - - - - - - - '

......- - - - '-------

4 MHz
Max

No.

Symbol

Parameter

1
2
3
4
5
6

TrI
Tf!
Twl's
TwPM
TsPMD
ThPMD

Any Input Rise Time
Any Input Fall Time
l's Catcher High Width
250
Pattern Match Input Valid (Bit Port)
750
Data Latched on Pattern Match Setup Time (Bit Port)
0
Data Latched on Pattern Match Hold Time (Bll Port) 1000

NOTES'
1 If the

mput

IS

Min

Package/
Temp
Speed

Umts

In

170
500

o
650

nanoseconds (ns).

Description

Product
Number

Z8536

CE

4.0 MHz

CIa (40-pin)

Z8536A

Z8536
Z8536

CM
CMB

4.0 MHz
4.0 MHz

Same as above
Same as above

Z8536A
Z8536A

Z8536

CS

4.0 MHz

Same as above

Z8536

DE

Same as above

Z8536

OS

4.0 MHz
4.0 MHz

Z8536
Z8536

PE
PS

4.0 MHz
4.0 MHz

Package/
Speed
Temp

Description

6.0 MHz

CIa (40-pin)

CMB

6.0 MHz
6.0 MHz

Same as above
Same as above

Z8536A

CS

6.0 MHz

Same as above

Z8536A

DE

Same as above

Same as above

Z8536A

OS

6.0 MHz
6.0 MHz

Same as above
Same as above

Z8536A
Z8536A

PE
PS

NOTES: C = CeramiC, D = Cerd,p, P = Plashc, E
Wlth Class B processmg, S = O°C to + 70°C.

402

100
100

references assume 2.0 V for a ioglC "1" and 0.8 V for a \Og1g "0".

t

Product
Number

100
100

Notes*t

* Tlmmgs are prelimmary and subject to change. All hmmg

programmed Inverting, a Low-gomg pulse of the

same Wldth WIll be detected.

Ordering
Information

6 MHz
Max

Min

= -40'C to

+85'C, M

CE
CM

Same as above

6.0 MHz

Same as above

6.0 MHz

Same as above

= -55'C to 125'C, MB = -55'C to 125'C wllh MIL·STD·883

2014-028

00·2021-02

Z8581 Clock Generator
and Controller

~
Zilog

Product
Brief

June 1982
Features

D PrOVIdes abdlty to stretch HIgh or Low
phase of clock SIgnal under external
control.

• Two mdependent 20 MHz oscillators.
• Clock output dnvers meet the hIgh capacItance clock mput reqUIrements of NMOS
mIcroprocessors.

PrOVIdes an NMOS-compahble clock sIgnal at a programmable percentage of the
source frequency.

n

t'I

0

source frequency.
Reset output
• System
D Reset output is synchromzed WIth System
Clock output.

• System Clock oscdlator

D

...

00

• D PrOVIdes an NMOS clock SIgnal at half

• OscIllator mput frequency reference source
can be eIther crystals or TTL-compahble
oscllla tors.
PrOVIdes a TTL-compahble hmebase sIgnal at source frequency.

U'I

General-Purpose Clock oscdlator

• Outputs dIrectly dnve the Z80 and Z8000
mIcroprocessor clock mputs.

D

N
00

D External mput mlhates system reset.

1:11

0

and LSI penpherals. The clock output dnvers
of the Z8581 also meet the non-TTL voltage
reqUIrements for dnvmg NMOS clock mputs
WIth no addlhonal external dIscrete transIstors.
In general, the Z8581 prOVIdes an elegant,
smgle-chlp soluhon to the deSIgn of system
clocks for mICroprocessor-based products.

General
Description

The Z8581 IS produced m an 18-pm package
(see FIgure I for pm functions and FIgure 2 for
pm assIgnments); It contams two separate

OSCIllators, cycle stretchmg logIC, and reset
synchromzahon and delay logIC.

REF. FREQ. SOURCE
} FOR SYS. CLOCK OSC

XTL1A
XTl1B

~

STRT

REF. FREQ. SOURCE
} FOR GEN. PURPOSE OSC

NO. OF RISING {
EDGES COUNTED

GENERAL PURPOSE CLOCK

+5V

2248·001. 002

sfR"H

RSTI

ASTO

osc

lNH

ZCLK

+5V

aND

AOD1

TCLK

ADD2

XTL2B

CO

XTl2A

C1

STRT

aND

Figure 1. Pin Functions

Z

1:11

:.
toil

The Z8581 Clock Generator and Controller
IS a versahle addition to Zllog's family of
Universal microprocessor components. The
selective clock-stretchmg capablhhes and
variety of timing outputs produced by this
deVICe allow It to easlly meet the hmmg deSIgn
requirements of systems WIth mIcroprocessors

START COUNT

l'.I

D Power up reset penod IS mamtamed for a
mmlmum of 30 ms.

Introduction

SYSTEM CLOCK

a

l'.I

shmline package used; smgle +5V
• dc18-pm
power reqUIred.

TIME BASE

n
Pi:

Figure 2. Pin Assignments

403

General
Desc:ription
(Continued)

The Z8581 oSCIllators are referenced as the
System Clock oscillator and the GeneralPurpose Clock oscillator. Both oscillators are
driven by external crystals or other frequency
sources.

System Cloc:k Osc:illator. The timing outputs
provided by this OSCillator consist of a Time
Base output (OSC), at the frequency of the
reference source, and a stretchable System
Clock output (ZCLK), at a frequency determined by the stretch control Inputs. An onchip TTL driver at OSC and an NMOS driver
at ZCLK eliminate the need for external buffers
or drivers. The NMOS drivers can drive 200
pF loads to Within 0.2 volts of Vee and sink
8 rnA. Output rise and fall times are 10 ns.
ZCLK can be stretched under program or
hardwired control by selectively adding
periods eqUivalent to a full OSC cycle to
either the High or Low portion of a clock
cycle. One, two, or three periods can be
added to double, triple, or quadruple the
duration of the selected ZCLK half-cycle. AddIng periods to ZCLK IS a function of the ADDI
and ADD2 inputs. These active Low Inputs are
sampled prior to the rising edge of Signal
OSC; their sampled status represents the
number of periods to be added to ZCLK.
Two additional control mputs, INH and
STRH, affect the stretch function. Input INH,
when asserted, inhibits the function of ADDI
and ADD2. Input STRH stretches the ZCLK
output for as long as It IS asserted (Low); it
overrides all other stretch control mputs.
Table I summarizes the functions performed
by the stretch control mputs.
STRH

INH

ADD!

ADD2

Periods Added

0
I
I

X

X
X

X
X

0
0
I
I

0
I
0

UnlImited
0
3
2
I
0

0
I
I
I
I

Notes X ::;: Don't Care, 1

=

High,

The clock stretch capability allows systems to
run at the nommal high speed of ZCLK, except
durmg cycles that reqUire more time than
usual to complete a transaction. For example,
extended access time may be reqUired in
accessing certam areas of memory, m accessing I/O deViCes or m other CPU/Peripheral
transactions. Figures 3 and 4 illustrate, respectively, the CirCUit conhguratlon and tlmmg
required to stretch the Z8000 address strobe
(AS) and data strobe (DS) to allow more time
for address functions and to enable the CPU to
operate With memories that have a relatively
long access time.
In addition, the ZCLK stretch control lOgiC
can be hardWired to meet various duty cycle
requirements. For example, a Simple hardWired connection can cause every other ZCLK
cycle to be stretched to produce a ZCLK output With a 33% duty cycle.
The System Clock OSCillator also prOVides a
system reset output (RTSO) that IS synchronized With ZCLK. This output IS controlled by
a system reset mput (RSTI) durmg normal
system reset operations and by delay CIrcUitry
m the System Clock OSCillator durmg power up
operations. Durmg a normal system reset
operation a Low on RSTI causes RSTO to be
asserted (set Low) on the next rlsmg edge of
ZCLK. Output RSTO is held Low for a period
of 16 ZCLK clock cycles (the required reset
time for both the Z80 and Z8000 CPU system
reset functions). Durmg a power up operatIOn,
RSTO IS asserted for a mmimum of 30 ms after

a = Low
Figure

Table I. Stretch Control Functions

404

3.

Configuration for Stretching zaooo
Address (AS) and Data (DS) Strobes

2248·003

General
Description
(Contmued)

power IS turned on (the hme reqUIred for both
the Z80 and Z8000 power up functlOns).
The System Clock oscillator also contams a
2-blt ZCLK counter. ThIs counter, when lmhallzed by the assertlOn of STRT, counts the next
four nsmg edges of the ZCLK output. The current count IS presented on outputs CO and Cl.
ThlS counter and ItS outputs enable the user to
determme the occurrence (nsmg edge) of each
of four clocks after a speclflc event (STRT IS
asserted). ThIS faclhty can, for example, be
used to determme when a delay IS to be

mserted mto a CPU machme cycle when STRT
IS tnggered by mther an Ml (Z80) or an AS
(Z8000) mput sIgnal.

General-Purpose Oscillator. ThIS oscillator
provIdes a hxed frequency General-Purpose
Clock output (TCLK) at half ItS source frequency. ThIS output IS useful for system hming
funchons such as controlhng a baud rate
generator. Output TCLK can also be used as
the frequency reference source for the System
Clock oscillator.

osc

ZCLK

I:

co

...
=

c.
L..._ _ _.....1..-ONE CSC CLOCK PERIOD ADDED

TWO

asc CLOCK PERIODS ADDED

=I

r

Figure 4. Timing Diagram, Stretching Z8000 AS and DS

00·2248-01

2248-004

405

Z8590
UPC Universal
Peripheral Controller

~
Zilog

Product
Specification

June 1982

Features

• Complete slave microcomputer, for
distributed processing use.
• Unmatched power of Z8 architecture and
instruction set.
• Three programmable I/O ports, two with
optional 2-Wire Handshake.
• Six levels of priority interrupts from eight
sources: six from external sources and two
from internal sources.
• Two programmable 8-bit counter/timers

General
Description

The 28590 Universal Peripheral Controller
(UPC) is an intelligent peripheral controller
for distributed processing applications (Figure
3). The UPC unburdens the host processor by
assuming tasks traditionally done by the host
(or by added hardware), such as performing
arithmetic, translating or formatting data, and
controlling I/O devices. Based on the 28

each with a 6-bit prescaler. Counter/Timer
TO is driven by an internal source, and
Counter/Timer Tl can be driven by internal
or external sources. Both counter/timers are
independent of program execution.
• 256-byte register file, accessible by both the
master CPU and UPC, as allocated in the
UPC program.
• 2K bytes of on-chip ROM for efficiency and
versatility.
microcomputer architecture and instruction
set, the UPC contains 2K bytes of internal program ROM, a 256-byte register file, three 8-bit
I/O ports, and two counter/timers.
The UPC offers fast execution time, an
effective use of memory, and sophisticated
interrupt, I/O, and bit manipulation. Using
a powerful and extensive instruction set

+5V ----...
PCLK---.

GND---.

Figure 1.

2017-068.095

Pin Functions

Figure 2.

Pin Assignments

407

General
Description
(Continued)

combined with an efficient internal
addressing scheme, the UPC speeds
program execution and efficiently packs
program code into the on-chip ROM.
An important feature of the UPC is an internal register file containing I/O port and control registers accessed both by the UPC program and indirectly by its associated master
CPU. This architecture results in both byte
and programming efficiency, because UPC
instructions can operate directly on I/O data
without moving it to and from an accumulator.
Such a structure allows the user to allocate as
many general purpose registers as the application requires for data buffers between the CPU
and peripheral devices. All general-purpose
registers can be used as address pOinters,
index registers, data buffers, or stack space.
The register file is logically divided into 16
groups, each consisting of 16 working
reglsters. A Register Pointer is used in conjunction with short format instructions,
resulting in tight, fast code and easy task
switching.
Communication between the master CPU
and the register file takes place via one group
of 19 interface registers addressed directly by
both the master CPU and the UPC, or via a
block transfer mechanism. Access by the
master CPU is controlled by the UPC to allow
independence between the master CPU and
UPC software.
The UPC has 24 pins that can be dedicated
to I/O functions. Grouped logically into three
HOST CPU

8-line ports, they can be programmed in many
combinations of input or output lines, with or
without handshake, and with push-pull or
open-drain outputs. Ports 1 and 2 are bitprogrammable; Port 3 has four fixed inputs
and four outputs.
To relieve software from coping with realtime counting and timing problems, the UPC
has two 8-bit hardware counter/timers, each
with a fixed divide-by-four, and a 6-bit programmable prescaler . Various counting modes
may be selected.
In addition to the 40-pin standard configuration, the UPC is available in four special configurations:
• A 64-pin RAM development version with
external interface for up to 4K bytes of RAM
and 36 bytes of internal ROM permitting
down-loading from the master CPU.
• A Protopack RAM version with a socket for
up to 2K bytes of RAM, with 36 bytes of
internal ROM permitting down-loading from
the master CPU.
• A 64-pin ROM development version with
external interface for up to 4K bytes of ROM
and no internal ROM.
• A Protopack ROM version with a socket for
2K bytes of ROM and no internal ROM.
This range of versions and configurations
makes the UPC compatible with most system
peripheral device control considerations.

UPC MICROCOMPUTER

INTERFACE

PORT
DBQ-DB1

1

INTERFACE
REGISTERS
(PART OF REGISTER
FILE)

I/O

RP

TO
MASTER

IRP

CPU
REGISTER
FIl.E
256 )( 8

L _ _ _ _ _ -,

INT

P3s

lEO

+5 V GND PCLK

Figure 3. Functional Block Diagram

408

2017-087

Pin
Description

AID. Address/Data (input). A Low on this pin
defines information on the data bus as an
address. A High defines the information
as data.
CS. Chip Select (input, active Low). A Low
enables the UPC to accept address or data
information from the master CPU during a
write cycle or to transmit data to the master
CPU during a read cycle. This line is usually
generated from higher bits of the address
lines.
DBo-DB-,. Data Bus (bidirectional). This bus is
used to transfer address and data information
between the master CPU and the UPC.
Plo-PI,. P2Q-P2,. P30-Pa,. I/O Port Lines
(bidirectional, TTL compatible). These 24 lines
are divided into three 8-bit I/O ports and may
be configured in the following ways under program control:
Plo-PI,. Port 1 (inpuVoutput-as output it can
be push-pull or open-drain). Bit-programmable
Parallel 1/0.

be push-pull or open-drain). Bit-programmable
Parallel 1/0.
P30-Pa,. Port 3 (four mputs, four outputs).
Parallel 1/0, handshake control, timer 1/0, or
interrupt control.
PCU:. Clock (input). TTL-compatible clock
input, 4 MHz maximum. This signal does not
need to be related to the master CPU clock.

RD. Read (input, active Low). A Low enables
the master CPU to read mformation from the
UPC. Raising the voltage on this pin above
VDD will force the UPC into test mode.
WAIT. Wait (output, active Low, open-drain).
When the CPU accesses the UPC register file,
this signal requests the master CPU to wait
until the UPC can complete its part of the
transaction.
WR. Write (input, active Low). A Low on this
pin enables the master CPU to write information to the UPC. A simultaneous Low on RD
and WR resets the UPC. It is held in reset as
long as WR is Low.

P2Q-P2,. Port 2 (inpuVoutput-as output, it can

Functional
Description

Address Space. On the 40-pin UPC, all
address space is committed to on-chip
memory. There are 2048 bytes of maskprogrammed ROM and 256 bytes of register
file. I/O is memory-mapped to three registers
in the register file. Only the Protopack and
64-pin versions of the UPC can access external
program memory. See the section entitled
"Special Configurations" for complete descriptions of the Protopack and 64-pin versions.
Program Memory. Figure 4 is a map of the 2K
on-chip program ROM. Even though the architecture allows addresses from 0 to 4K, behavior of the device above program address 2047
(7FFH) is not defined. The first 12 bytes of program memory are reserved for the UPC
interrupt vectors. For the Protopack and 64-pin
versions, the address space is extended to 4096
bytes. In the RAM versions, addresses OCH
1
LOCATION OF
FIRST BYTE OF
INSTRUCTION
EXECUTED AFTER
RESET

USER

ROM

"r--..

,.

12

11

•
•

through 2FH are reserved for on-chip RGM.
Register File. This 256-byte file includes three
1/0 port registers (l-3H), 234 general-purpose
registers (6-EEH), and 19 control, status and
special I/O registers (OH, 4H, 5H, and
FO-FFH). The functions and mnemonics
assigned to these register address locations
are shown' in Figure 5. Of the 256 UPC
registers, 19 can be directly accessed by the
master CPU; the others are accessed indirectly
via the block transfer mechanism.

fFH
fEH
fDH
fCH
fBH
fAH
F9H
faH
f1H
faH
f5H
f4H
f3H
f2H
f1H

"
IHQ6 LOWER BYTE

fOH

IRQS UPPER BYTE

EFH

STACK POINTER
MASTER CPU INTERRUPT CONTROL

SP
MIC

REGISTER POINTER

RP

PROGRAM CONTAOl FLAGS

FLAGS

UPC INTERRUPT MASK REGISTER
UPC INTERRUPT REQUEST REGISTER

IMR
IRQ

UPC INTERRUPT PRIORITY REGISTER

IPR

PORT 1 MODE

P1M

PORT 3 MODE

PaM

PORT 2 MODE

TIMER/COUNTER 1

P2M
PREO
To
PREi
T,

TIMER MODE
MASTER CPU INTERRUPT VECTOR REG

TMR
MI.

To PRESCALER
TIMERICOUNTER 0
T1 PRESCALER

IRQ4 LOWER BYTE
IRQ4 UPPER BYTE

GENERAL-PURPOSE REGISTERS

1

IAQ3 LOWER BYTE

a

IA03 UPPER BYTE

5
4
3

IRQ2 UPPER BYTE

BH

IHOi LOWER BYTE

5H

DATA INDIRECTION REGISTER

2

IHOi UPPeR BYTE

4H

LIMIT COUNT REGISTER

LC

IROG LOWER BYTE

3H

PORT 3

P3

IROO UPPER BYTE

2H
1H

PORT 2
PORT 1
DATA TRANSFER CONTROL REGISTER

P2
Pi

1

•

IRQ2 LOWER BYTE

OH

Figure 4. Program Memory Map
2017·001.002

IDENTIFIER
(UPC Side)

LOCATION

DIND

DTC

Figure 5. aeglater Fila Orgcmlzatlon

409

Functional
Description
(Continued)

The VO port and control registers are
included in the register file without differentiation. This allows any UPC Instruction to
process VO or control information, thereby
eliminating the need for special I/O and control instructions. All general-purpose registers
can function as accumulators, address
pointers, or index registers. In instruction execution, the registers are read when they are
defined as sources and written when defined as
destinations.
UPC instructions may access registers
directly or indirectly using an 8-bit address
mode or a 4-bit address mode and a Register
Pointer. For the 4-bit addressing mode, the file
is diVided into 16 working register groups,
each occupying 16 contiguous locations
(Figure 6). The Register Pointer (RP) addresses
the starting point of the active working-register
group, and the 4-bit register designator supplied by the instruction specifies the register
within the group. Any instruction altering the
contents of the register file can also alter the
Register Pointer. The UPC instruction set has a
special Set Register Pointer (SRP) instruction
for initializing or altering the pointer contents.
Stacks. An 8-bit Stack Pointer (SP), register
R255 , is used for addreSSing the stack,
residing within the 234 general-purpose
registers, address location 6H through EFH.
PUSH and POP instructions can save and
restore any register in the register file on the
stack. During CALL instructions, the Program
Counter is automatically saved on the stack.
During UPC interrupt cycles, the Program
Counter and the Flag register are automatically saved on the stack. The RET and IRET
instructions pop the saved values of the Program Counter and Flag register.

o

1 1 1

o

THE 4-BIT REOISTER }

POINTER PROVIDES THE
UPPER NIBBLE OF THE
REGISTER FILE ADDRESS
FOR THE 4-81T ADDRESS
MODE

75

1 101

0 0 0

FFH
FDH
FOH
EFH
EOH
DFH
DOH
CFH
COH
BFH
BOH
AFH
AOH
IFH
IOH
IFH
80H
7FH
70H
SFH
BOH
5FH
SOH
4FH
40H
3FH
30H
2FH
20H
1FH
10H
OFH

0

Figure 6. Register Pointer Mechanism

410

Ports. The UPC has 24 lines dedicated to
input and output. These are grouped into three
ports of eight lines each and can be configured under software control as inputs, outputs, or special control Signals. They can be
programmed to provide Parallel I/O with or
without handshake and timing signals. All outputs can have active pull ups and pulldowns,
compatible with TTL loads. In addition, they
may be configured as open-drain outputs.

Port 1. Individual bits of Port 1 can be configured as input or output by programming
Port 1 Mode register (PIM) F8H. This port is
accessed by the UPC program as general
register IH. It is written by specifying address
1H as the destination of any instruction used to
store data in the output register. The port is
read by specifying address 1H as the source of
an instruction.
Port 1 may be placed under handshake control by programming Port 3 Mode register
(P3M) F7H. This configures Port 3 pins P33
and P34 as handshake control lines DAV land
RDYl for input handshake, or RDYj and DAVl
for output handshake, as determined by the
direction (input or output) assign~d to bit 7 of
Port 1. The Port 3 Mode register also has a bit
that programs Port 1 for open-drain output.

Port 2. Individual bits of Port 2 can be configured as inputs or outputs by programming
Port 2 Mode register (P2M) F6H. This port is
accessed by the UPC program as general
register 2H, and its functions and methods of
programming are the same as those of Port 1.
Port 3 pins P3j and P3s are the handshake
lines DAV2 and RDY2, with the direction (input
or output) determined by the state of bit 7 of
the port. The Port 3 Mode register also has a
bit used to program Port 2 for open-drain
output.
Function

ADDRESS (0101) IS

P31
P33
P34
P%
P30
P31
P33
P31
P3S
P3S
Pq
P30
P37
P3S

Handshake

(

UPC Interrupt
Request'

{

Counter/Timer

{

Master CPU

(

{ THE LOWER NIBBLE

OF THE REGISTER FILE

Line DlrecIlon

PROVIDED BV THE
INSTRUCTtON.

Test Mode

In
In
Out
Out
In
In
In
In
Out
Out
In
In
Out
Out

Signal

DAViRDY2
DAVIIRDYI
RDYI/DAVI
RDYJlDAV2
IRQ3
IRQ2
IRQI
T7N
TOUT
INT
INTACK
lEI
lEO

AID

·P30. P31' and P33 can always be used as UPe mterrupt
request mputs, regardless of the confIguration
programmed.

Table I. Port 3 Control Functions

2017·003

Functional
Description
(Continued)

Port 3. This port can be configured as I/O or

• Nonretriggerable trigger input for the UPC
internal clock divided by four.

control lines by programming the Port 3 Mode
register. Port 3 is accessed as general register
3H. The directions of the eight data lines are
fixed. Four lines, P30 through P33, are inputs,
and the other four, P34 through P37, are outputs. The control functions performed by Port
3 are listed in Table I.

• External gate input for the UPC internal
clock divided by four.

Interrupts. The UPC allows six interrupts from
eight different sources as follows:
• Port 3 lines P30, P32, and P33.

Counter/Timers. The UPC contains two 8-bit
programmable counter/timers, each driven by
an internal 6-bit programmable prescaler.
The Tl prescaler can be driven by internal
or external clock sources. The TO prescaler is
driven by an internal clock source. Both
counter/timers operate independently of the
processor instruction sequence to relieve the
program from time-critical operations like
event counting or elapsed-time calculation. TO
Prescaler register (PREO) F5H and Tl Prescaler register (PREI) F3H can be programmed
to divide the input frequency of the source
being counted by any number from I to 64. A
counter register (F2H or F4H) is loaded with a
number from I to 256. The corresponding
counter is decremented from this number each
time the prescaler reaches end-of-count. When
the count is complete, the counter issues a
timer interrupt request; IRQ4 for TO or IRQs
for TI. Loading either counter with a number
(n) results in the interruption of the UPC at the
nth count.
The counters can be started, stopped,
restarted to continue, or restarted from the initial value. They can be programmed to stop
upon reaching end-of-count (Single-Pass
mode) or to automatically reload the initial
value and continue counting (Modulo-n Continuous mode). The counters and prescalers
can be read at any time without disturbing
their values or changing their counts. The
clock sources for both timers can be defined as
anyone of the following:

• The master CPU(3).
• The two counter/timers.
These interrupts can be masked and globally
enabled or disabled using Interrupt Mask
Register (IMR) FBH. Interrupt Priority Register
OPR) F9H specifies the order of their priority.
All UPC interrupts are vectored.
Table 2 lists the UPC's interrupt sources,
their types, and their vector locations in program ROM. Interrupt Request IRQ6 is
dedicated to master CPU communications.
Interrupt Requests IRQI, IRQ2, and IRQ3 are
generated on the falling transitions of external
inputs P33, P31, and P30. Interrupt Requests
IRQ4 and IRQs are generated upon the timeout
of the UPC's two counter/timers. When an
interrupt request is granted, the UPC enters an
interrupt machine cycle. This cycle disables all
subsequent interrupts, saves the Program
Counter and Status Flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
The UPC also supports polled systems. To
accommodate a polled structure, any or all of
the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.
Following any hardware reset operation, an
EI instruction must be executed to enable the
setting of any interrupt request bit in the
IRQ register. Interrupts must be disabled prior
to changing the content of either the IPR
(F9H) or the IMR (FBH). Dr is the only instruction that should be used to globally disable
interrupts.

• UPC internal clock (4 MHz maximum)
divided by four.
• External clock input to Counter/Timer Tl
via P31 (l MHz maximum).
• Retriggerable trigger input for the UPC
internal clock divided by four.
Name

Source

Vector
Location

Comments

EOM, XERR, LERR

0,1

IRQ]

DAV] , IRQ]

2,3

External (P33) I Edge TrIggered

IRQ2

DAV2, IRQ2, TIN

4,S

External (P3]) I Edge TrIggered

IRQ3

IRQ3, lEI

6,7

External (P30) I Edge TrIggered

IRQ4

TO

8,9

Internal

IRQs

Tl

10,11

Internal

IRQo

Internal (RO BIts 0, I, 2)

Table 2. Interrupt Types. Sources. and Vector Locations

411

Functional
Description
(Continued)

Master CPU Register File Access. There are
two ways in which the master CPU can access
the UPC register file: direct access and block
access.

Direct Access. Three UPC regIsters-the Data
Transfer Control (OH), the Master Interrupt
Vector (FOH), and the Master Interrupt Control
(FEH)-are mapped dIrectly into the master
CPU address space. The master CPU accesses
these registers via the addresses shown in
Table 3.
The master CPU also has dIrect access to 16
registers known as the DSC (Data, Status,
Command) regIsters. The DSC regIsters are
numbered 0 through F (DSCO-DSCF). These
registers can be any 16 conltguous regIster file
registers beginning on a 16-byte boundary.
The base address of the DSC register group is
designated by the IRP (I/O Register Pomter),
which is bits D4-D7 of the Data Transfer Control register (OH). Figure 7 shows how the
register address is made up of the 4-bit IRP
field, concatenated with the low order 4-bits of
the address from the master CPU.
Block Access. The master CPU may transmIt
or receive blocks of data vIa address xxxlOlOl.
When the master CPU accesses this address,
the UPC register pointed to by the Data
IndIrection register is read or written. The
Data Indireclton regIster is incremented, and
the LimIt Count register is decremented, for
example, when the master CPU Issues a read
or write to address xxxl0101 while the Data
DTC REGISTER (GNI
IRP
~

ADDRESS FROM CPU

I-I~I-I~I-I-I~I~I

I

Indlreclton regIster contains the value 33H.
The operalton causes register 33H to be read
or written and the Data Indireclton register to
be incremented to 34H. This scheme is well
sUIted to Block 1/0 Instructions and allows the
master CPU to effICIently read or wnte a block
of data to or from the UPC.
The LImIt Count register (04H) is
decremented and IS used to control the
number of bytes to be transferred by master
CPU block accesses. If the master CPU
attempts a read or write to the UPC after the
Limit Count register reaches 0, the access IS
not completed, the LERR bit (DI) of the Data
Transfer Control register is set (indICating a
bmit error), and the LERR error causes an
IRQO interrupt request.
The IRP field of the Data Transfer Control
regIster, the Data Indirection register, and the
LimIt Count regIster are not directly accessIble
to the master CPU and therefore must be set
by the UPC. ThIS allows the UPC to protect
itself from master CPU errors and frees the
master CPU from tracking the UPC's mternal
data layout.
UPC Address
Decimal
Hex
0

Identifier

OH

DTC
DIND

Address
xxxi 1000

S

SH

@S"

@SH"

240

FOH

MIV

2S4

FEH

MIC

xxxllllO

'n

DSCO

xxxOOOOO

n+1

DSCI

xxxOOOOI

n+2

DSC2

xxxOOOIO

n+3

DSC3

xxxOOOl1

n+4

DSC4

xxxOOIOO

n+S

DSCS

xxxOO 10 I

n+6

DSC6

xxxOOllO

n+7

DSC7

xxxOOll1

n+B

DSCB

xxxOIOOO

n+9

DSC9

xxxOlOOI

n+ 10

DSCA

xxxOlOIO

n+11

DSCB

xxxO 10 I I

n+ 12

DSCC

xxxOllOO

n+13

DSCD

xxx01101

n+14

DSCE

xxxOlllO

n+IS

DSCF

xxxOllll

xxxlOlOl
xxxlOOOO

x = don't care
*n IS the value In the IRP x 16
**Master CPU accesses the regIster address m Reglster 5.

Table 3. Master CPU/UPC Register Map
Figure 7. DSC Register Addressing Scheme

412

2017-004

Special
Configurations

There are two Protopack and two 54-pin versions of the UPC. These versions are identical to the 40-pin UPC with the following
exceptions:
• Internal ROM is totally omitted from the
54-pin development and ROM Protopack
versions.
• All but 35 bytes of internal ROM are omitted
from the 54-pin RAM and Protopack RAM
versions.
• The memory address and data lines are buffered and brought out to external pins or to
the socket on the Protopack.
• Control lines for the external memory are
also provided.
The 54-pin version of the UPC allows the
user to prototype the system in hardware with
an actual UPC device and to develop the code
intended to be mask programmed into the
on-chip ROM of the 40-pin UPC for the production system. The 54-pin or Protopack RAM
versions of the UPC are extremely versatile
parts. Memory space can be extended to 4K
bytes on the 54-pin version by using external
RAWROM for all but 35 bytes of the UPC's
memory space. This memory can then be
down-loaded from the master CPU using a
bootstrap program stored in the 35 bytes
(C-2F). Figure 8 is a memory map for the
54-pin RAM version.

64-Pin and Protopack Pin Functions. Forty of
the pins on the 54-pin and Protopack versions
have functions identical to those of the 40-pin
version. The remaining 24 pins have additional
functions described below. (Figures 9 through
11 show the 54-pin and Protopack versions' pin
functions and pin assignments.)
Ao-All' Program Memory Address Lines (output). These lines are identical in all 54-pin and
RAM versions in the Protopack. They are used
to address 4K bytes of external UPC memory.
Do-D,. Program Data (input). Data is read in
from the external memory on these lines. The
RAM version also writes external memory
through this bus.
lACK. Interrupt Acknowledge (output, active
High). This signal is active whenever an internal UPC interrupt cycle is in process.

BUS
DATA

!

BUS {
TIMING
AND RESET
CONTROL {

INTERRUPT {
FFFH . . . - - - - - - - - - - . . . ,

EXTERNAL

PROGRAM MEMORY

RAM

EXTERNAL
DATA

1

~~~ I----------~
BOOTSTRAP ROM

}

INTERNAL
ROM

}

EXTERNAL
RAM

EXTERNAL {
CONTROL

~~~----------;
PCLK
Z UPC INTERRUPT

VECTORS

+5V

~------------~

Figure 8. UPC RAM Version Memory Map

21117 005, 006

Figure 9. Z8591/Z8592 UPC Pin Functions

413

Special
Configurations
(Continued)

MAS. Memory Address Strobe (output, active
Low). This address strobe is pulsed once for
each memory fetch to interface with quasistatic RAM.
MOS. Memory Data Strobe (output, active
Low). This signal is Low during an instruction
fetch or memory write.

P2,

MR/W. Memdry Read/Write (output RAM versions only). This signal is High when the UPC
is fetching an instruction and Low when it is
loading external memory.
SYNC. Instruction Sync (output, active Low).
This signal is Low during the clock cycle just
preceding an opcode fetch.

P321INTACK

+SY 1

40 P31

pelK 2

39 P3e

P37/IEO 3

P2,

P3~IEI

os

10
11
P3,

,.
14

15

Z8591
Z8592

DB,

18

DB,

19
P1,

20
21

0,

22

MAS

23
2.

MRiwllACK

25
A,

2.

35 P24

0,

34 P23

8

33 P22

AID 9

32 P21

cs

upc

17
P1,

P3sllNT 5
P32I1NTACK 8

ViR

13
P1,

3B P21

37 P26
36 P25

RD7

DB,

12

4

10

31 P20

GND 11

30 P33

WAIT 12

29 P34

DB7 13

28 P11

DBe 14

27 P16

DBs 15

28 P15

DB4 16

25 P14

DBa 17

24 P13

DB2 18

23 P12

DB1 19

22 P11

DBo 20

21 P10

27
A,

28

0,
*SOCKET FOR 2716 EPROM (2K x 8) OR RAM

2.

A,

30

AlO

31
A,

32

Figure 10. Z8591/Z8592 UPC Pin Assignments

Addressing
Modes

The following notation is used to describe the
addressing modes and instruction operations as
shown in the instruction summary.
R

IR
Ir

Additional
Symbols

414

dBt
Brc

Register or working-register address
Workmg-register address only
Indirect-regIster or indirect working· register
address
Indirect workmg-reg,ster address only

DestinatIon location or contents
Source location or contents
Condihon code (see list)
cc
@
Indirect address prefix
SP
Stack Pointer (control register FFH)
PC
Program Counter
FLAGS Flag regIster (control register FCH)
RP
RegIster Pomter (control regIster FDH)
IMR
Interrupt Mask register (control register FBH)

Figure II. Z8593/Z8594 UPC Protopack Pin Assignments

RR
IRR
Irr
X
DA

RA
1M

RegIster pair or working-register pair address
IndIrect register pair or indirect working-register

pair address
Indirect working· regIster pair only
Indexed address
Direct address
Relative address
Immediate

Assignment of a value is indicated by the symbol
"_". For example,
dst - dst + arc
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.

2017·007,008

Flags

Control Register FCH contains the following six
flags:
C
Z
S

Affected flags are indicated by:

o

Carry flag
Zero flag
Sign flag
Overflow flag
DeClmal-adjust flag
Half-carry flag

V
D
H

Condition
Codes

Value

*
X

Mnemonic

1000
0111
1111
0110
1110
1101
OIDI

IIII

0111
1011
0011
0000

Flaga Set

Meaning
Always true
Carry
No carry
Zero
Not zero
Plus
Minus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal

C
NC
Z
NZ
PL
MI
OV
NOV
EQ
NE
GE
LT
GT
LE
UGE
ULT
UGT
ULE

0100
1100
0110
1110
1001
0001
1010
0010

Cleared to zero
Set to one
Set or cleared according to operation
Unaffected
Undefined

C =I
C =a
Z =I
2 =a
S =a
S =I
V =1
V =a
2 =I
2 =a
(S XOR V) = a
(S XOR V) = I
[2 OR (S XOR V)]
[2 OR (S XOR V)]
C =a
C =1
(C = a AND 2 = 0)
(C OR Z) = I

a
I

Never true

Instruction
Formats

ope

CCF, DI, El, IRET, NOP,
ReF, RET. SCF

dot

ope

INCr

One-Byte Instructions
ope

MODE

dstlsrc

ope

I

dot

OR

11 1 101 dst/src I

OR

11 1 101

eLR, CPL. DA, Dec,
DECW, INC, INew, POP,
PUSH, RL, RLe, RR,
RRC, SRA, SWAP

ope

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TeM, TM, XOR

MODE

OR f 1 1 0
OR f 1 1 0

dot

dOl

JP, CALL (Indirect)

ope

d.,

ope
SRP

MODE

dOl
VALUE

Oft

b 1 101

d.,

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TeM, TM, XOR

VALUE

MODE

ope

MODE

CP, OR, SSC, SUB,

dot

TeM, TM, XOR

ope

MODE
dstisrc

arcldel

ope
dstlsrc
arc/dst

I

ope
dot
VALUE

ope

OR

11

1 1

01

dot

ope

LD, LOE, LOEI,

MODE

LOC, LOCI

dstisrc
ADDRESS

ope
LD

DJNZ, JR

Two-Byte Instructions

2037·013

dOl

LO

LD

JP

OA,
OA,

ope

IdsUCCR~ ope

LO
OR f 1 1 0
OR 1 1 1 0

ADC, ADD, AND,

CALL

OA,
OA,

Three-Byte Instructions

415

Opcode

Lower Nibble (Hex)

Map

o
6,5

o

6,5

DEC

3

5

.
e•
~

:!!

6

7

:z:
til

''""
9

A

C

D
E
F

8

9

A

B

C

10,5

10,5

10,5

6,5

6,5

12/10,5

12110,0

6,5

12/10,0

6,5

LD

LD

DINZ

IR

LD

IP

INC

11,R2

I2,Rl

n,HA

cc/RA

rdM

cc,DA

r,

R2,Rl

IR2,H,

6,5

6,5

6,5

6,5

10,5

10,5

RLC

RLC

ADC

ADC

H"IM
10,5

IH"IM

IHI

11,12

11, Ir2

R2,H,

IH2,H,

6,5

6,5

10,5

10,5

H"IM
10,5

IHdM

6,5

INC

INC

SUB

SUB

SUB

SUB

SUB

SUB

HI

IHI

H,ll

ll,I12

R2,Hl

IH2,H,

6,5

6,5

10,5

10,5

H"IM
10,5

IHI,IM

6,1

JP

SRP
1M

SBC

SBC

SBC

SBC

SBC

11,12

11, Ir2

H2,HI

IR2,Rl

HI,IM

SBC

8,5

8,5

6,5

6,5

10,5

10,5

10,5

IH"IM
10,5

DA

DA

OR

OR

OR

OR

OR

OR

HI

IRI

11,12

11, 1r2

H2,H,

IR2,R,

6,5

6,5

10,5

10,5

H"IM
10,5

IHdM

10,5

POP

POP

AND

AND

AND

AND

AND

AND

HI

IHI

11,12

11.112

H2,HI

IH2,H,

6,5

6,5

6,5

10,5

10,5

H"IM
10,5

IH"IM
10,5

COM

COM

TCM

TCM

TCM

TCM

TCM

TCM

HI

IRI

n , 12

11, 1r2

H2,H,

IR2,R,

10/12,1 12/14,1

6,5

6,5

10,5

10,5

H"IM
10,5

IH"IM
10,5

PUSH

TM

TM

TM

TM

TM

TM

H2

IH2

fl,12

Il,Iu

H2,H,

IH2,H,

H"IM

IHdM

10,5

10,5

IHI

6,5

6,5

r-----r-----

r-----r------

18,0

6,1

LDEI

DI
I--

n,lrrz lrI,Irrz
12,0

18,0

RL

RL

LDE

LDEI

HI

IHI

12,Inl

If2,InJ

10,5

10,5

6,5

6,5

INCW INCW
IHI

6,1
10,5

10,5

10,5

CP

CP

CP

CP

CP

CP

ll,IZ

Il,Ir2

R2,Hl

IH2,HI

HI,IM

IRI,IM

6,5

6,5

6,5

6,5

10,5

10,5

10,5

10,5

CLR

XOR

XOR

XOR

XOR

XOR

XOR

HI

IRI

11,12

11, Ir2

H2,H,

IR2,H,

H"IM

IRdM

6,5

6,5

12,0

18,0

10,5

RRC

RRC

LDC

LDCI

LD

HI
6,5

IHI
6,5

12,0

18,0

SRA

SRA

LDC

LDCI CALL·

HI

IHI

12/hIl

6,5

RR

II,

Iru In,Ir12

~

6,5

RCF

r---

DA

12, x, HI

SCF

6,5

10,5

10,5

10,5

10,5

LD

LD

LD

LD

LD

HI

IRI

II,Iu

R2,HI

IR2,H,

HI,IM

IHI,IM

8,5

8,5

6,5

10,5

LD

LD

Ill,l2

H2,IR,

....

6,5

r--6,5

CCF

r-----6,0

NOP

'V'

.I

....'---------~~,----------,,/ ~ ~
2

3

Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode-A
Nibble
First
Operand

•

Pipeline
Cycles

Mnemonic

* 2-byte mstruchon; fetch cycle appears as a 3-hyte mstruction.

416

Legend:

= 8-BIt Address
= 4-Blt Address
HI or I I = Dst Address

R

r

Second
Operand

°

LD

RR

,/

16,

IRET

10,5

6,5

'V'

~

20,0

IRRI

IRI

°

CALL

1I 2,lrr!

SWAP SWAP

14,

RET

R2

fl, X,

20,0

EI
I--

10,5

CLR

I".

~

10,5

6,5

HHI

I--

10,5

10,5

°
LDE

I-~

10,5

8,0

12,

F

ADC ADC ADC ADC

HI

PUSH

D

10,5

6,5

HI

Byles per
Instruction

10,5

7

II, Irl

HHI

B

6,5

6

DEC ADD ADD ADD ADD ADD ADD

DECW DECW

~

6,5

E

5

Il,ll

IRHI

,

3

IRI

HI

2

2

R2 or

12

= Src Address

Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defmed.

Instruction
Summary

Opcode Flags Affected
Byte
(Hex)
CZSVDH

Instruction
and Operation

Addr Mode

ADC dst,src
dst-dst + src + C

(Note I)

ADD dst,src
dst - dst + src

(Note I)

00

* 0 •

AND dst,src
dst - dst AND src

(Note I)

50

0

clst

Irc

o*

ID

Addr Mode

Instruction

and Operation

src

r
Irr

Irr

82
92

------

LDEI dst,src
Ir
Irr
dst - src
r - r + I; rr-rr+l

Irr
Ir

83
93

------

LDE dst,src
dst - src

NOP

FF

CALL dst
DA
SP-SP-2
IRR
@SP - PC; PC - dst

D6
D4

------

OR dst,src
dst - dst OR src

(Note I)

40

• 0

* - - - - -

IR

50
51

------

EF

POP dst
dst - @SP
SP-SP+I

R

CCF
C - NOTC
CLR dst
dst - 0

R
IR

BO
BI

COM dst
dst - NOT dst

R

IR

60
61

CP dst,src
dst - src

(Note I)

DA dst
dst - DA dst

R

00
01

R

IR

DECW dst
dst-dst-I

AO
40
41

IR

DEC dst
dst-dst-I

RR

80
81

IR

DI

PUSH src
SP - SP - I; @SP- src

R

IR

DJNZ r,dst
RA
r - r- I
Ifr ,. 0
PC-PC + dst
Range: + 127, -128

CF

o- - - - -

AF

------

. .. .. x - -

RET
PC - @SP; SP - SP + 2
RL dst

IR

90
91

- * * *--

RLC

R

10

.

* * * - -

- * * *--

El.I:.DJ
dst LEl=E3J
' , ,

RR dst

1El

R

IR

8F

------

rA
r=O-F

------

SBC dst,src
dst - dst-src-C

'

,

0

9F

INC dst
dst-dst+1

rE
r=O-F
20
21

R

CO
CI

(Note I)

30

R

IR
INCW dst
dst - dst +

RR

AO
AI

IR

- -

IRET
BF
FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR (7) - I
JP cc,dst
If

CC 18

DA

true

PC - dst

IRR

JR cc,dst

RA

If cc is true,

cD
c=O-F
30

------

cB
c=O-F

------

r
R
r
X
r
Ir
R
R
R

IR
IR

1M
R

rC
r8
r9
r=O-F
C7

------

X
r
Ir
r
R

* 0

31

------

20

* * * * I *

FO
FI

X

IR

TCM dst,src
(NOT dst) AND src

(Note I)

60

- * *

TM dst,src
dst AND src

(Note I)

70

-

XOR dst,src
dst - dst XOR src

(Note I)

BO

IR
1M
1M
R

SRP src
RP - src

1m
(Note I)

SWAPdst ~ R

... *

X - -

0

* *0
* 0 - -

Note I

second mbble IS expressed symbolIcally by a 0 In thIs
table, and ItS value IS found In the follOWing table to the
I

D7

Ir (source) IS 13.

E3
F3
E4
E5
E6
E7
F5

Addr Mode

Lower

dst

sre

Opeode Nibble

R

Ir
R

III
Gl
III
W

rn

C2
D2

------

LDCI dst,src
dst - src

Ir
Irr

Irr
Ir

C3
D3

------

+1

.

F or example to determme the opcode of an ADC

Irr

rr-rr

*

left of the applIcable addressmg mode pair.

r
Irr

+ 1;

DO
DI

1El~1~

mstructlOn usmg the addressmg modes r (destmatIon) and

LDC dst,src
dst - src

r-r

- -

These InstructIons have an Identical set of addressmg
modes, which are encoded for brevity The hrst opcode
mbble IS found In the InstructIon set table above. The

PC-PC+dst
Ra"ge: + 127, -128
LD dst,src
dst - src

.

-

SUB dst,src
dst - dst - src

- * * ... - -

* I
I

-----......

..,

d

n

DF

SCF
C-I

- *

C

EO
EI

IR

R

IR

R

1M
1M

IR

aen
UI

II

4:::3J I~

Lril=E3J

RRC dst

SRA dst

EI
IMR (7) - I

70
71

RCF
C-O

- * ... 0

IMR (7) - 0

8085·003

Opcode Flags Affected
Byte
(Hex)
CZSVDH

dst

rn
417

Registers

R24B PIM
Port I Mode Register
UPC register address (Hex): F8

R24TP3M
Port 3 Mode Register
UPC register address (Hex): F7
I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

III ~:=::==::

P10-P17 1/0 DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

1 PORT 1 PULL-UPS ACTIVE

o P35

R246 P2M
Port 2 Mode Register
UPC register address (Hex): F6

= OUTPUT

1 P35 ""

iNT

RESERVED

o P33 :::

INPUT

1 PS3 '" DAV1fRDY1

I~I~I~I~I~I~I~I~I

P34 ::: OUTPUT
P34

= RDY1/DAV1

'------ ~ ~:~ ~ ~:v'!JR~~~ ::: ~~~~~UT)
P20-P27 110 DEFINITION

' -_ _ _ _ _ _ ~ ~~ : :~tUT

'---------

' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

::~ : ~~TPUT

~ =~: :~~~~K

Figure 12. Port Mode Registers

R251IMR
Interrupt Mask Register
UPC register address (Hex): FB

R250 IRQ
Interrupt Request Register
UPC register address (Hex): FA

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

'

E~~
L

~~

I ~ IRao = MASTER CPU COMMUNICATIONS

L

L'ENABLEslRao
1 ENABLES IRQ1
1 ENABLES IRQ2
1 ENABLES IRQ3
1 ENABLES IRQ4

IRQ1

= P331NPUT

IRQ2

=
=

IRaa

P31 INPUT
P30 INPUT

IRQ4 ::: To

= T1

1 ENABLES IAQS

IAQS

RESERVED

RESERVED

1 ENABLES INTERRUPTS

R249IPR
Interrupt Priority Register
UPC register address (Hex): F9 (Write Only)
I~I~I~I~I~I~I~I~I

"~".:J

INTERRUPT GROUP PRIORITY
RESERVED '" 000
C>A>B :: 001
A>B>C :: 010
A>C>B :: 011
B>C>A:: 100
C>B>A"" 101
B>A>C :: 110
RESERVED"" 111

II I 4-,,-.., '"
o ::: IRQ1 > IRQ4
1 '" IRQ4 > IRQ1

OM"' '"

IRao, IRa2 PRIORITY (GROUP B)
0'" IRQ2 > IRao
1'" IRQO>IRQ2
IRa3, IRas PRIORITY (GROUP A)
0"" IRQS > IRa3
1 "" IRQ3>IRQ5

Figure 13. Interrupt Control Registers

R254 MIC
Master CPU Interrupt Control Register
UPC register address (Hex): FE

R240 MIV
Master CPU Interrupt Vector Register
UPC regIster address (Hex): FO

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

LO1 END OF MESSAGE

~~

, - I-

__

VECTOR DATA (Do

= LSB)

o WAIT ENABLE WHEN WRITE
1 WAIT DISABLE WHEN WRITE

o ENABLE LOWER CHAIN
1 DISABLE LOWER CHAIN

o DISABLE DATA TRANSFER
1 ENABLE DATA TRANSFER
o VECTOR OUTPUT
1 NO VECTOR OUTPUT

'------

~ ~~S~~~Tg~UCI~~~~~~~~U::N~~~gING

'--------

~ ~~~~~~~~U:~D~~D::R~~~tCE

L-_ _ _ _ _ _ _

~ :~~~::~~i :~g~~~i ~~::LL:g

Figure 14. Master CPU Interrupt Registers

418

2017-009,010,011

Registers
(Continued)

R253 RP
Register Pointer
UPC register address (Hex): FD

R252 FLAGS
Flag Register
UPC register address (Hex): FC

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

~m~
1

LUSERFLAGF1

L

REGISTER POINTER

=-:J

(r4-rr)

USER Fl.AG F2

c=-

DDN'T CARE

HALF CARRY FLAG
DECIMAL ADJUST FLAG

OVERFLOW FLAG
SIGN FLAG

ZERO flAG

R255 SP
Stack Pointer
UPC register address (Hex): FF

CARRY FLAG

I~I~I~I~I~I~I~I~I

Figure 15. UPC Control Registers
R4LC
Limit Count Register
UPC register address (Hex): 04

RODTC
Data Transfer Control Register
UPC register address (Hex): 00

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

I ~~
~o

LIMIT COUNT VALUE

L-_ _ _ _ _ ~~~~~::X)255 DECIMAL
END OF MESSAGE

NO TRANSFER ERROR
1 TRANSFER ERROR

(LERR)

NO LIMIT ERROR

LIMIT ERROR
(EOX)

DISABLE DATA TRANSFER
ENABLE DATA TRANSFER

R5DIND
Data Indirection Register
UPC register address (Hex): 05
I~I~I~I~I~I~I~I~I

"'(I"RP"I_ _ _ _ _ _ _ 1 I/O REGISTER POINTER

Figura 16. Master CPU·UPC Data Transfer Raglstars
R243 PREI
Prescaler 1 Register
UPC register address (Hex): F3

R241 TMR
Timer Mode Register
UPC register address (Hex): Fl

J

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

RESTEoRuJE~o!'~:
TO OUT "" 01

INTERNAL

CLOCT~ g~i ~ ;~

II

L:

1

EXTER':l~ ~~g~:

~

L ~~U~"~.."a"L~PASS
=

0 = NO
fUNCTION
1'"
LOAD
Yo
0

= DISABLE To COUNT
= ENABLE To COUNT

0 = NO FUNCTION
1 '" LOAD T1

:

INPUT". 00

TRI::~: :==~~ ~~

0

(NON.RETRIGGERABLE)

1

=
=

1

T1 MODULO. N

CLOCK SOURCE
o = EXTERNAL TIMING INPUT
(TIN) MODE
T1 INTERNAL
1

=

PRESCAlER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

DISABLE T1 COUNT
ENABLE T1 COUNT

TRIGGER INPUT .. 11
(RETRIGGERABLE)

R244 TO
Counter/Timer 0 Register
UPC register address (Hex): F4

R242 Tl
CounterlTimer I Register
UPC register address (Hex): F2

1~1~1~1~1~1~I~t~1

I~I~I~I~I~I~I~I~I

LI----7~~~:r~~~-~~~icIMAl

T1 INITIAL VALUE
' - - - - - - (RANGE· 1-256 DECIMAL
01-00 HEX)

01-00 HEX)

R245 PREO
Prescaler 0 Register
UPC register address (Hex): F5
1~1~1~1~I~t~I~I~1

~L

COUNT MODE
o = To SINGLE·PASS
1 = To MODULO· N
RESERVED
PRESCALER MODULO
(RANGE: 1-64 DECIMAL
01-00 HEX)

Figure 17. UPC Counter/Timer Registers
~()I'1

012, 014, 013

419

Registers

(Continued)

Control Register

Do,

Os

Ds

D4

Da

Da

D)

Do

Comments

OOH
Data Transfer Control Reglster

X

X

X

X

0

0

0

0

Disable data transfer
from master CPU

0

0

0

Stops TO and Tl

X

0

0

Smgle-Pass mode

X

0

0

Single-Pass mode
External clock source

04H
Limit Count Register

Not Defined

OSH
Data Indlrection Register

Not Dehned

FOH
Interrupt Vector Register

Not Defined

FIH
Timer Mode

0

0

0

X

X

X

X

X

Not Defined

F4H
Tl Register
F5H
Tl Prescaler

0

Not Defined

F2H
TO Register
F3H
TO Prescaler

0

X

X

X

X

X

Port 2 lines defined as

F6H
Port 2 Mode
F7H
Port 3 Mode

inputs

0

0

0

0

X

0

0

Port I lines dehned as

F8H
Port I Mode

inputs

Not Dehned

F9H
Interrupt Priority
FAH
Interrupt Request

X

X

0

0

0

0

0

0

Reset Interrupt Request

FBH
Interrupt Mask

0

X

X

X

X

X

X

X

Interrupts disabled

0

0

0

Master CPU interrupt dlsabledi walt enable when
write; lower cham enabled

FCH
Flag Register

Not Defined

FDH
Reglster Pointer

Not Defined

FEH
Master CPU Interrupt
Control Register
FFH
Stack Pointer

0

0

0

0

0

Not Defmed

NOTE: X means not defIned.

Table 4. Control Register Reset Conditions

420

Port I, 2 open dram;
P3s = INT; P3Q, P31, P32,
P% defined as input; P34,
P36, P37 defined as output.

Absolute
Maximum
Ratings

Voltages on all pins (except VBB)
with respect to GND .......... -0.5 V to +7.0 V
Operatmg Ambient
Temperature ........ See Ordermg Information
Storage Temperature ........ -65°C to + 150 °C

Standard
Test
Conditions

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:

Stresses greater than those hsted under Absolute MaJ----·~I

~~----~---------------------------------------

2017-017,018

2014-024

2017-019

4 MHz
No.

Symbol

Parameter

Min
0
230

1

TsDI(DA)

Data in Setup Time

2

ThDA(DI)

Data

In

Hold TIme

TwDA
Data Available Width
3
4-TdDAL(RY)--Data Available Low to Ready
Delay TIme
TdDAH(RY)
Data Available HIgh to Ready
5
Delay TIme
6

TdDO(DA)

Data Out to Data AvaIlable Delay Time

7

TdRY(DA)

Ready to Data Available Delay TIme

Symbol

Parameter

Notes*t

Min

175
175
20-175---20-175
0
0

1,2
1,22,3

0
230

150
0

150
0

50

50
205

0

4 MHz
No.

6 MHz
Max

Max

MiD

Max

1,2
2,3
2

0

205

6MBz
MID
Max

2

Notes*t

TdRDQ(WR)

Delay from RD I to WR I for No Reset

40

35

2

TdWRQ(RD)

Delay from WR I to RD I for No Reset

50

35

3

TwRES

Minimum Width of WR and RD both Low for Reset

250

250

Symbol

Parameter

MiD

TwMAS

Memory Address Strobe Width

60

55

5

30

5
5

4 MHz
No.

Max

2

TdA(MAS)

Address Valid to Memory Address Strobe I Delay
Memory ReadlWrlte to Memory Address Strobe I
Delay

30

TdMRIW(MAS)

30

30

4

TdMDS(A)

Memory Data Strobe I to Address Change Delay

60

60

80
160

75
110

30

30

8

TdMDS(DO)

Memory Data Strobe I to Data Out Change Delay

9

Tw(MDS)

Memory Data Strobe WIdth (Read Case)

30

30

230

230

lO-TdMDS(DI)--Memory Data Strobe I to Data In Valid Delay
11

TdMAS(DI)

Memory Address Strobe I to Data In Valid Delay

12

ThMDS(DI)

Memory Data Strobe I to Data In Hold TIme

13
14

TwSY
TdSY(MDS)

15

TwI

160
280

Max

Notes*t

CI

0

6

5
5
6
130 - - - 7 220

7

0

Instruction Sync Out WIdth

0
160

100

Instruction Sync Out to Memory Data Strobe Delay

200

160

Interrupt Request vIa Port 3 Input WIdth

100

100

NOTES

1

Input Handshake

2. Test Load I

three mput clock periods must be added to the specIfIed Width
Data strobe Width varies accordmg to the Instruction bemg ex-

3. Output Handshake

ecuted.

4. Internal reset signal IS V:z to 2 clock delays from external reset
condItion
5 Delay hmes are speclhed for an mput clock frequency of 4
MHz When operating at a lower frequency I the Increase

In

m-

put clock period must be added to the specIfIed delay bme

6

Data strobe Width

IS

speclhed for an mput clock frequency of 4

MHz When operatmg at a lower frequency, the Increase

In

GO
U»

CII

6 MHz
MiD

3

5-TdMDS(MRIW)-Memory Data Strobe I to Memory ReadIWrlte Not
Valid Delay
Tw(MDS)
Memory Data Strobe WIdth (Write Case)
6
TdDO(MDS)
Data Out Valid to Memory Data Strobe I Delay
7

N

4

Address strobe and data strobe to data In vahd delay tImes
represent memory system access tImes and are gIven for a 4
MHz Input frequency
"'All timing references assume 2.0 V for a logiC "1" and 0.8 V for a
logIC "0" All output ac parameters use test load 2 Tlmmgs are
prelIminary and subject to change.
tUruts In nanoseconds (ns).

425

•"

Ordering
Information

Product
Number

Package/
Temp
Speed

Description

Product
Number
Z8592

QS

8.0 MHz

UPC External
RAM-based
Program Memory
(64-pin)

Z8593

RS

8.0 MHz

UPC External
ROM-based
Program Memory
(Protopack)

Z8594

RS

8.0 MHz

UPC External
RAM-based
Program Memory
(Protopack)

Z8590

CE

8.0 MHz

UPC (40-pin)

Z8590

CS

8.0 MHz

Same as above

Z8590

DE

8.0 MHz

Same as above

Z8590

DS

8.0 MHz

Same as above

Z8590

PE

8.0 MHz

Same as above

Z8590

PS
QS

8.0 MHz

Same as above

8.0 MHz

UPC External
ROM-based
Program Memory
(64-pin)

Z8591

Packtlge/
Temp
Speed

Descrlptlon

NOTES C = CeramIc, D = Cerdlp, P = Plasbc, Q = QUIP, R = Protopack, E = -40·C to +85·C, S = O·C to + 70·C.

426

00-2022-02

Z8 FaDliiy

-l: 9..)
Z··10··

Zilog Z8® Family

~
Zilog

The New Standard For
Single-Chip Microcomputers

June 1982
The Z8 Family of microcomputers
offers the most sophisticated processing capability available on a
single chip. As an extension of
earlier generations of microcomputers, the Z8 Family provides
standard on-chip functions,
such as:
• 2K or 4K bytes of ROM
• 144 8- bit registers
• 32 lines of programmable I/O
• Clock oscillator
In addition, the Z8 Family offers
advanced on-chip features,
including:
• Two counter/timers
• Six vectored interrupts
• UART for serial I/O communication
• Stack functions
• Power-down option
• TTL compatibility

The capability of the Z8 Family
of microcomputers is expandable
off-chip to provide an additional
62K bytes of program memory and
62K bytes of data memory for the
2K-byte ROM version. It provides
an additional 60K bytes of program
memory and 60K bytes of data
memory for the 4K-byte ROM version. The interface to external
memory is accomplished through
one, one and one-half, or two of
the 8-bit I/O ports, depending on
the number of address bits
required for the external functions.
The Z-BUS protocol allows easy
interface to external functions
including Zilog's family of
peripheral chips.
With the third-generation Z8
Family, Zilog is pushing the capability of microcomputers beyond
the first and second generation of
computers. The Z8 Family
challenges the "multi-chip
solution" deSign currently
implemented by general-purpose
microprocessors. Designs based on
Z8-Famlly microcomputers offer a
minimum chip-count configuration
that can easily be expanded to
meet requirements for enhancement options and for future
improvements.

Optimized Instruction Set. The
instruction set of the Z8-Family
microcomputers is optimized for
high-code density and reduced
execution time. This feature is supported by a "working register
area" concept that uses short
(4-bit) register addresses. The
general-purpose registers can be
used as accumulators, as address
pointers for indirect addressing, as
index registers, or for implementing an on-chip stack.
The 47 instruction types and six
addreSSing modes-together with
the ability to operate on bits, 4-bit
BCD digits, 8-bit bytes, and 16-bit
words-offer unique programming.
capability and flexibility.
.<

429

Growing Family. The 28 Family
of microcomputers is growing to
meet the needs of more complex
designs. The 4K ROM version of
the 28 microcomputer (the 28610
series) offers all the features of the
28 Family, plus 4K bytes of on-chip
ROM. The increased ROM allows
the designer to take advantage of
the code optimization inherent in
the 28 instruction set when using
between 2K and 4K bytes of program memory.
The ROMless microcomputer
provides an alternative for
designers seeking to take advantage of the on-chip features of the
28601 in applications that require
external program memory. A
28681 microcomputer can be used
to control a system that addresses
up to 128K bytes of off-chip
memory.

The 28671 microcomputer is a
28-based BASIC/debug interpreter
on a chip. The BASIC used in the
28671 is a subset of Dartmouth
BASIC with the added capability of
interaction between the interpreter
and its environment through the
debug facility. The BASIC/debug
interpreter resides in the 2K of onchip ROM, with all the features of
the 28 microcomputer at its
disposal.

Expanded Applications. The 28
Family of microcomputers is finding its way into increasingly
sophisticated designs. In addition
to the low-end capability applications commonly used with microcomputers, the 28 Family of microcomputers can be used effectively
in such applications as:

Z8
MICROCOMPUTER
SERIAL
COMMUNICATIONS

Figure 1. ZS-Based Intelligent Terminal

430

• Computer peripheral controllers
• Smart terminals
• Dumb terminals
• Telephone switching systems
• Arcade games and intelligent
home games
• Process control
• Intelligent instrumentation
• Automotive mechanisms
An example of how a 28 might
be used in the design of an intelligent terminal is shown in Figure I.
The features of such a terminal
depend on its specific requirements, but it is clear that the 28
microcomputers offer unprecedented capability and flexibility to
the microcomputer deSIgner.

Z8® Family of
Microcomputers
Z8601 • Z8602 • Z8603
Product
Specification

~
Zilog

June 1982
28601 Single-Chip Microcomputer with 2K ROM
28602 Development Device with Memory Interface
28603 Prototyping Device with EPROM Interface

Features

General
Description

• Complete microcomputer, 2K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
62K bytes addressable external space each
for program and data memory.

• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit programmable prescaler.
• Register Pointer so that short, fast instructions can access any of nine working
register groups in 1.5 /LS.

• 144-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.

• On-chip oscillator which accepts crystal or
external clock drive.

• Average instruction execution time of
2.2 /LS, maximum of 4.25 /LS.

• Low-power standby option which retains
contents of general-purpose registers.

• Vectored, priority interrupts for I/O,
counter/timers, and UART.

• Single + 5 V power supply-all pins TTLcompatible.

The 28601 microcomputer introduces a new
level of sophistication to Single-chip architecture. Compared to earlier single-chip microcomputers, the 28601 offers faster execution;
more efficient use of memory; more sophisticated interrupt, input/output and bit-manipulation capabilities; and easier system expansion.
Under program control, the 28601 can be
tailored to the needs of its user. It can be con-

figured as a stand-alone microcomputer with
2K bytes of internal ROM, a traditional microprocessor that manages up to l24K bytes of
external memory, or a parallel-processing element in a system with other processors and
peripheral controllers linked by the 2-BUS. In
all configurations, a large number of pins
remain available for I/O.

PORTO
(NIBBLE

P3,
P3,

XTAL1

P2,

P3,

P2,

P3,

P2,

REm

P2,

AIW

AS

P2,
P2,
P2,

P3,

P2,

GND

P3,

os

PROGRAMMABLE)

110 OR

+5V
XTAL2

Aa-A1~

P3,

PORT 1
(BYTE
PROGRAMMABLE)
110 OR ADo-AD?

PORT 3
(FOUR INPUT;

FOUR OUTPUn
SERIAL AND
PARALLEL 110

AND CONTROL

Figure 1.

2037 -00 1, 002

Pin Functions

po,
po,
po,
po,
po,
po,
po,
po,

Figure 2.

P3,
P1,
P1,
P1,
P1,
P1,
P1,
P1,
P1,

Pin AsSignments

431

Architecture

28601 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O capabilities. The 28601 fulfills this with
32 pins dedicated to input and output. These
Imes are grouped into four ports of eight lines
each and are configurable under software control to provide timing, status signals, serial or
parallel I/O with or without handshake, and an
address/data bus for interfacing external
memory.
Because the multiplexed address/data bus is
merged with the I/O-oriented ports, the Z8601
can assume many different memory and I/O
configurations. These configurations range
from a self-contained microcomputer to a

OUTPUT

Vee

microprocessor that can address 124K bytes of
external memory.
Three basic address spaces are available to
support this wide range of configurations: program memory (internal and external), data
memory (external) and the register file (internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
four I/O port registers, and 16 control and
status registers.
To unburden the program from coping with
real-time problems such as serial data communication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware support for the UART is minimized
because one of the on-chip timers supplies the
bit rate.

XTAL.

GND

As Os RiW

REseT

!!

I/O

(BIT PROGRAMMABLE)

ADDRESS OR ItO
(NIBBLE PROGRAMMABLE)

ADDRESS/DATA OR 1/0

(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

Pin
Description

AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along with
Ports 0 and I, Data Strobe and Read/Write.

OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

POO-P07. Plo-PI7. P2o-P27' P30-P37. I/O Port
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports

432

that can be configured under program control
for I/O or external memory interface.

RESET. Reset (input, active Low). RESET initializes the Z8601. When RESET is deactivated,
program execution begins from internal program location OOOCH.

R/W. Read/Write (output). R/W is Low when
the 28601 is writing to external program or
data memory.
XTALL XTAL2. Crystal 1, Crystal 2 (time-base
input and output). These pins connect a seriesresonant crystal (8 MHz maximum) or an external smgle-phase clock (8 MHz maximum) to
the on-chip clock oscillator and buffer.

2037·003

Address
Spaces

Program Memory. The 16-bit program
counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Figure 4). The first 2048 bytes
consist of on-chip mask-programmed ROM. At
addresses 2048 and greater, the 28601
executes external program memory fetches.
The first 12 bytes of program memory are
reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond
to the six available interrupts.
Data Memory. The 28601 can address 62K
bytes of external data memory beginning at

locations 2048 (Figure 5). External data
memory may be included with or separated
from the external program memory space.
DM, an optional 1/0 function that can be
programmed to appear on pin P34, is used to
distinguish between data and program
memory space.

Register File. The 144-byte register file
includes four I/O port registers (RO-R3). 124
general-purpose regIsters (R4-R127) and 16
control and status registers (R240-R255). These
registers are assigned the address locations
shown in Figure 6.
28601 instructions can access registers

65535.-----------,

5535
EXTERNAL
ROM OR RAM

I...

2048
2047
ON·CHIP
ROM

Locet.onof
Ilrslbyleoi
InstructIon

executed

allerrese!

';-, ~-----------11

IAQS

10

IRQS

•
Inl9rrupl
Vector

(Lower Byte)

Interrupt
Vector
(Upper Byte)

MEMORY

B

IRQ4

S

IRQ4

7

IR03

6

IA03

5

IRQ2

41-'

IRQ2

3

IRQi

2

IRQi

1

IROO

0

IROO

~~:~ 1 - - - - - - - - - - - 1
NOT ADDRESSABLE

Figure 4. Program Memory Map

LOCATION

IDENTIFIERS

255

STACK POINTER (BITS 7-0)

SPL

254

STACK POINTER (BITS 15-8)

SPH

252

REGISTER POINTER

253

PROGRAM CONTROL FLAGS

FLAGS

INTERRUPT MASK REGISTER

IMR

250

INTERRUPT REQUEST REGISTER

IRQ

24.

INTERRUPT PRIORITY REGISTER

IPR

24S

PORTS 0-1 MODe

P01M

247

PORT 3 MODE

P3M

246

PORT 2 MODE

244

TIMER/COUNTER 0

243

11 PRESCALER

242

TIMER/COUNTER 1

241

TIMER MODE

TMR

240

SERIAL I/O

510

TO PRESCALER

Figure 5. Data Memory Map

1-1-':=3==::;::====:,255
_(

RP

251

245

i!w

EXTERNAL
DATA

~"---------I

253

~------------------~2~

The upper nibble 01 Ihe registerille addreaa
provided by the reglalerpolnlerapectftes
the ecllve working register group

12

P2M
PREO

TO
PRE1

T1

NOT
IMPLEMENTED

I

127

SPECIFIED WORKING·
REGISTER GROUP

The lower
nibble 01

-

Ihereglaler
lIIeaddr,ss
provided by

Iheinstrucllon
pOints to the

apecllted
register

(

GENERAL PURPOSE
REGISTERS

1
PORT 3

P3

PORT 2

P2

PORT 1

Pl

PORT 0

PO

Figure 6. The Register File

~(J

11004, 005, 006, 007

f----'/OPORTS-----

a

Figure 7. The Register Pointer

433

Address
Spaces
(Continued)

directly or indirectly with an 8-bit address
field. The Z8601 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-bit mode, the
register file is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.

Stacks. EitheI' the internal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
is used for the external stack, which can reside
anywhere in data memory between locations
2048 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within
the 124 general-purpose registers (R4-RI27).

Serial
Input/
Output

Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second.
The Z8601 automatically adds a start bit and
two stop bits to transmitted data (Figure 8).
Odd parity is also available as an option. Eight
data bits are always transmitted, regardless of

parity selection. If parity is enabled, the eighth
bit is the odd parity bit. An interrupt request
(lRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.

Transmitted Data

Received Data

(No Parity)

(No Parity)
1~1~1~1~1~1~1~1~1~lsij

T

I

LSTART BIT
' - - - - - - E I G H 7 DATA BITS

LSTART BIT
' - - - - - - E I G H T DATA BITS

L.- - - - - - - - O N E STOP BIT

TWO STOP BITS

Transmitted Data

Received Data

(With Parity)

(With Parity)

1~1~lpl~I~I~I~I~I~I~I~1

1~lpl~I~I~I~I~I~I~I~1

T

L

ODD PARITY

I

TWO STOP BITS

' - - - - - - - - - - O N E STOP BIT

_ _
LSTARTBIT

I,

' - - - - - S E V E N DATA BITS

_LSTARTBIT
' - - - - - S E V E N DATA BITS

PARITY ERROR FLAG

Figure 8. Serial Data Formats

Counter/
Timers

434

The Z8601 contains two 8-bit programmable
counter/timers (To and TIl. each driven by its
own 6-bit programmable prescaler. The Tl
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each pres caler drives its counter,
which decrements the value (1 to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQ5 (TI)-is
generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (single-

pass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for Tl is user-definable and
can be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (1 MHz maximuml.
a trigger input that can be retriggerable or
non-retriggerable, or as a gate input for the
internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of T I. Port 3 line P36 also
serves as a hmer output (Tour) through which
To, TI or the internal clock can be output.

2037·009

1/0 Ports

The Z8601 has 32 lines dedicated to input
and output. These lines are grouped into four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to

provide address outputs, timing, status signals,
serial I/O, and parallel I/O with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.

Port 1 can be programmed as a byte I/O
port or as an address/data port for interfacing
external memory. When used as an I/O port,
Port I may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY 1
and DAV1 (Ready and Data Available).
Memory locations greater than 2048 are
referenced through Port 1. To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If
more than 256 external locations are required,
Port 0 must output the additional lines.
Port 1 can be placed in the high-im~dance
state along with Port 0, AS, DS and R/W, allow-

ing the Z860 I to share common resources in
multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33
as a Bus Acknowledge input and P34 as a Bus
Request output.

Port 0 can be programmed as a nibble I/O
port, or as an address port for interfacing
external memory. When used as an I/O port,
Port 0 may be placed under handshake control. In this configuration, Port 3 lines P32 and
P3s are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the I/O direction of the upper
nibble P04-P07.
For external memory references, Port 0 can
provide address bits As-All (lower nibble) or
As-A1S (lower and upper nibble) depending
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as

I/O while the lower nibble is used for addressing. When Port 0 nibbles are defined as
address bits, they can be set to the highimpedance state along with Port I and the control signals AS, DS and R/W.

Port 2 bits can be programmed independently as input or output. The port is
always available for I/O operations. In addition, Port 2 can be configured to provide
open-drain outputs.
Like Ports 0 and I, Port 2 may also be
placed under handshake control. In this con, figuration, Port 3 lines P31 and P36 are used as
the handshake controls lines DAV2 and RDY2.
The handshake signal assignment for Port 3
lines P31 and P36 is dictated by the direction
(i~put or output) assigned to bit 7 of Port 2.
Port a lines can be configured as I/O or controllines. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37). For serial I/O, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, I and 2
(DAVand RDY); four external interrupt
request signals (IRQo-IRQ3); timer input and
output signals (TIN and Tour) and Data
Memory Select (DM).
2037-008

.....T.

(110 OR ADo-AD,)

I...

Figure Sa. Port I

Figure 9b. Port 0

PORTJ:(1I0)

}

~:~~KRED;~NTROLS
(P~

AND p:lt)

Figure 9<:. Port 2 ,

.....T.

(110 OR CONTROL)

435

~

D

Interrupts

The Z8601 allows SIX different interrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter/
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or mdivldually enables or disables the six
interrupt requests. When more than one interrupt is pending, priorities are resolved by a
programmable priority encoder that is controlled by the Interrupt PriorIty register.
All Z8601 interrupts are vectored. When an
interrupt request is granted, an interrupt
machine cycle is entered. This disables all

subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector location reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
Polled interrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determine
which of the interrupt requests needs service.

Clock

The on-chIp oscillator has a high-gain,
series-resonant amplifier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2, using the recommended
capacitors (Cj = 15 pF) from each pin to

ground. The specifications for the crystal are
as follows:

The low-power standby mode allows power
to be removed without losing the contents of
the 124 general-purpose registers. This mode
is available to the user as a bonding option
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply input. This
necessItates the use of an external clock
generator (input = XTALl) rather than a
crystal source.
The removal of power, whether intended or
due to power failure, must be preceded by a
software routine that stores the appropriate
status into the register file. Figure 10 shows

the recommended circuit for a battery back-up
supply system.

Power Down
Standby
Option

• AT cut, series resonant
• Fundamental type, 8 MHz maximum
• Series resistance, Rs s 100 n

+5V

0-----.....--1

VDD

TRICKLE

CHARGE(r_"Wv---f1r

Z8801

l
Figure 10. Recommended Driver Circuit
for Power Down Operation

This 64-pin development version of the
Z8602
Development 40-pin mask-programmed Z8601 (Figure Il)
allows the user to prototype the system in hardDevice
ware with an actual device and to develop the
code that is eventually mask-programmed into
the on-chip ROM of the Z8601.
The Z8602 is identical to the Z8601 with the
following exceptions:
• The internal ROM has been removed.
• The ROM address lines and data lines are
buffered and brought out to external pins.
• Control lines for the new memory have
been added.

Pin Description. The functions of the Z8602
I/O lines, AS, DS, RlW, XTALl, XTAL2 and
RESET are identical to those of their Z8601
counterparts. The functions of the remaining
24 pins are as follows:

Ao-Au. Program Memory Address (outputs).
Ao-All access the first 2K bytes of program
memory. All is a reserved pin.

P1,
P1,

Z8G02

P1,

D,

"

'3

"
"
Figure 11. Z8602 Pin Assignments for Quip Package
(Reverse Assignments for 64·Pin OIL)

436

2037·010,011

Z8602

Do-D7. Program Data (inputs). Program data
Development from the first 2K bytes of program memory is
Device
input through pins Do-D7.
(Continued)

lACK. Interrupt Acknowledge (output, active
High). lACK is driven High in response to an
interrupt during the interrupt mach me cycle.

MDS. Program Memory Data Strobe (output,
active Low). MDS is Low durmg an instruction
fetch cycle when the first 2K bytes of program
memory are being accessed.

Z8603
Protopack
Emulator

The 28603 MPE (Protopack) is used for
prototype development and preproduction of
mask-programmed applications. The Protopack
is a ROMless version of the standard 28601,
housed in a pin-compatible 40-pin package
(Figure 12).
To provide pin compatibility and interchangeability with the standard maskprogrammed device, the Protopack carries
(piggy-backs) a 24-pin socket for a direct
interface to program memory (Figure I). The
24-pin socket is equipped with 11 ROM

SCLK. System Clock (output). SCLK is the
internal clock output through a buffer. The
clock rate is equal to one-half the crystal
frequency.
SYNC. Instruction Sync (output, active Low).
This strobe output is forced Low during the
internal clock period preceding an opcode
fetch.

address lines, 8 ROM data Imes and necessary
controllmes for interface to 2716 EPROM for
the first 2K bytes of program memory.
Pin compatibility allows the user to design
the pc board for a final 40-pin maskprogrammed 28601, and, at the same time,
allows the use of the Protopack to build the
prototype and pilot production units. When the
final program IS established, the user can then
switch over to the 40-pm mask-programmed
28601 for large volume produchon. The Protopack is also useful in small volume applications where masked ROM setup time, mask
charges, etc., are prohibitive and program
flexibility is deSired.
Compared to the conventional EPROM
versions of the single-chip microcomputers,
the Protopack approach offers two main
advantages:
• Ease of developing various programs durmg
the prototyping stage. For instance, in
applications where the same hardware
configuration is used with more than one
program, the 28603 Protopack allows
economical program storage in separate
EPROMs (or PROMs), whereas the use of
separate EPROM-based single-chip
microcomputers is more costly .

Figure 12. The Z8603 Microcomputer Protopack Emulator

Instruction
Set
Notation

Addressing Modes. The following notation is used
to describe the addressing modes and mstruction
operations as shown in the mstruction summary.
IRR
In

X

DA
RA
1M

R

Indirect register paIr or mdlrect working-register
pair address
Indirect workmg-reglster pair only
Indexed address
Dlrect address
Relative address
Immedlate
Register or workmg-reglster address

Working-register address only

IR

Indirect-register or indired workmg-register

Ir

address
Indirect workmg-reglster address only
Register pair or workmg reglster pair address

RR

2037·012

• Elimination of long lead time in procuring
EPROM-based microcomputers.
Symbols. The followmg symbols are used m
describing the instruchon set.
dst
src
cc

DestinatIon location or contents
Source locatIon or contents
Condlhon code (see hst)
@
Indlrect address prehx
SP
Stack pomter (control reglsters 254-255)
PC
Program counter
FLAGS Flag reglster (control reglster 252)
RP
Reglster pomter (control reglster 253)
IMR
Interrupt mask reglster (control reglster 251)

ASSIgnment of a value is indicated by the symbol
"_". For example,
dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" IS used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.
437

I-...
N

W

~

Instruction
Set
Notatlon
(Continued)

Flags. Control Register R252 contains the following
SIX

c

z

S
V

D
H

Condition
Codes

flags:

Affected flags are indicated by:

o

Carry flag
Zero flag
SIgn flag
Overflow flag
DeCImal-adJust flag
Half-carry flag
Value

*
x

Mnemonic

1000
0111
1111
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
0111
1011
0011
0000

Cleared to zero
Set to one
Set or cleared according to operahon
Unaffected
Undefmed

Meaning

Flags Set

Always true
Carry

C
NC
2
N2
PL
MI
OV
NOV
EQ
NE
GE
LT
G'T
LE
UGE
ULT
UGT
ULE

1
C
C =a
2 =1
2 =a
a
S
S =1
V =1
V =a
2 =1
2 =a
(S XOR V) = a
(S XOR V) = 1
[2 OR (S XOR V)]
[2 OR (S XOR V)]
C=O
C = I
(C = a AND 2 = 0)
(COR 2) = I

No carry

Zero
Not zero
Plus
Mmus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
UnsIgned less than
Unsigned greater than
Unsigned less than or equal

a
1

Never true

Instruction
Formats

CCF, DI, EI, (RET, NOP,
ReF, RET, SCF

oPC
dot

OPC

INCr

One-Byte Instructions
ope

MODE

CLR, CPL, DA, DEC,

dstfsrc

OR

I

h 1 1 01 dstlsrc I

OPC
f---'d""S"'1
--lOR 11

1 1

01

MODE

OPC

~~i:"~~~R~~~:R,POP,

ADe, ADD, AND, CP,

OR t i l 0
OR 1 1 1 0

dot

RRC, SRA, SWAP

LO, OR, SSC, SUB,
TeM, TM, XOR

dsl

JP, CALL (Indirect)

dst

MODE

OPC
dst

OPC

ADe, ADD, AND, CP,

OR

11

1 1

01

dot

VALUE

SRP

LO, OR,

sac, SUB,

TeM, TM, XOR

VALUE

MODE

ope

MODE

OPC
OR t i l 0
OR t i l 0

dsl

,n:

LD

dst

TeM, TM, XOR

MODe
dsUsrc

ope
sreldst

dstfsrc

OPC

~~"~~~ds~l~jOR ~11~1~1~ol~~J
dst

ADe, ADD. AND,
CP, OR, S8C, SUB,

dst

I

OPC

LO, LOE, LOEI,
LOC, LDCI

OPC

LD

ADDRESS

LD

OPC

JP

DAu
DA,
LD

VALUE

Idst/CCR~ OPC

MODE
dst/src

DJNZ, JR

OPC
DAu
DA,

Two-Byte Instructions

CALL

Three-Byte instructions
Figure 13. Instruction Formats

438

2037-013

Instruction
and Operation

Addr Mode

ADC dst,sre
dst-dst+sre+C

(Note 1)

ADD dst,sre
dst - dst + sre

(Note 1)

00

AND dst,sre
dst - dst AND sre

(Note 1)

50

Instruction
Summary

dot

orc

Opcode Flags Affected
Byte
(Hex)
C Z S V 0 H
10

·0·

- * * 0

Instruction
and Operation

LOE dst,sre
dst - sre

Addr Mode

Opcode Flags Affected
Byte
(Hex)
C Z S V 0 H

dst

.rc

r

Irr

82

Irr
Ir

83
93

Irr

LOEI dst,sre
Ir
dst - sre
Irr
r-r+ 1; rr-rr+ 1

92

NOP

FF

CALL dst
DA
SP-SP-2
IRR
@SP - PC; PC - dst

D6
D4

OR dst,sre
dst - dst OR sre

(Note I)

40

CCF
C - NOT C

EF

POP dst
dst - @SP
SP - SP +

R
IR

50
51

BO

PUSH sre
SP-SP-l; @SP-sre

CLR dst
dst - 0

R
IR

Bl

COM dst
dst - NOT dst

R
IR

60
61

CP dst,sre
dst - sre

(Note 1)

DA dst
dst - DA dst

R
IR

40
41

DEC dst
dst-dst-l

R
IR

00
01

DECW dst
dst-dst-l

RR
IR

AD

* * * X

80
81

DI
IMR (7) - 0
DJNZ r,dst

- * * 0 - -

8F
RA

r - r - 1
if r
0

*

9F

INC dst
dst-dst+l

R
IR

rE
r=O-F
20
21

RR
IR

AO
Al

IRET
BF
FLAGS - @ SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR(7) - I
JP ee,dst
If CC IS

PC - dst
If

cc

IS

DA

cD
e=O-F

true

JR ee,dst

IRR

30

RA

eB
e=O-F

true f

PC-PC + dst
Range: + 127, -128
LD dst,sre
dst - sre

AF

RL dst

90
91

RLCdstl~ ~I R
~IR

10
II

RR dst

,,""",1~1

R

EO
EI

RRC dst

lciJ=cil
R
, , • IR

Co

1m
R

'"!.Ol~IR

LriJ @

~

SRP sre
RP - sre

- * * * - -

1m

SUB dst,sre
dst - dst - sre

(Note I)

SWAP dst ~ R

~IR

• I •

DO
DI

* * * 0

31

20

." * 1 *

FO
FI

x**x--

TM dst, sre
dst AND sre

(Note I)

70

XOR dst,sre
dst - dst XOR sre

(Note I)

BO

• 0 - -

Note 1
These Instructions have an Idenhcal set of addressmg

modes, whIch are encoded for brevIty. The hrst opeode
mbble IS found m the mstruebon set table above. The
second mbble IS expressed symboheally by a 0 m thIS
table, and ItS value IS found m the followmg table to the
left of the appheable addressmg mode paIr.
For example, to determme the opeode of an ADC
Instruction usmg the addressmg modes r (destmatIon) and
Ir (source) IS 13.

r

Ir
R
R
R
IR
IR

r

F3

R
IR
1m
1m
R

E4

Addr Mode

E5
E6

dst

LOCI dst,sre
Ir
dst - sre
Irr
r - r + 1; rr - rr + 1

I
1-- -

60

Ir

Irr

N

W

DF

(Note I)

r

r
Irr

i-....

3D

TCM dst,sre
(NOT dst) AND sre

X

X

o- - - - -

CI

(Note I)

rC
r8
r9
r=O-F
C7
D7
E3

r
R
r

LDC dst,sre
dst .:. sre

RET
PC - @SP; SP - SP + 2

SRA dst

EI
IMR(7) - 1

INCW dst
dst - dst +

CF

SCF
C-I

PC-PC + dst
Range: + 127, -128

70
71

RCF
C-O

SBC dst,sre
dst- dst-sre-C

rA
r=O-F

R
IR

o

src

Lower
Opcode Nibble

E7
F5

C2
D2

R

Irr

C3

R

Ir

D3

R
IR

Ir
R
IR
1M
1M

439

Registers

R240 SIO
Serial I/O Register

R244 TO
Counter/Timer 0 Register

(FOH ; Read/Write)

(F4H; Read/Write)

' - - - - - SERlAL DATA (Do

=

NOT To",
USEDMODES
00

~~ g~~ ~ ~~
INTERNAL CLOCK OUT

= 11

= LSB)

R241 TMR
Timer Mode Register

R245 PREO
Prescaler 0 Register

(FI H; Read/Write)

(F5H; Wrlte Only)

j

~

~~o

FUNCTION
1 =
= NO
LOAD
To

0
1

T MODES
EXTERNAL CLOCK INPaT = 00
GATE INPUT:: 01

0
1
0

(NON.R~~~~g~:~~:~~) ;; 10
TRIGGER INPUT = 11

1

=
=
=
=
=
=

DISABLE To COUNT
ENABLE To COUNT

~L

COUNTMODE
=
o
1

To SINGLE PASS

= To MODULO·N

RESERVED

NO FUNCTION
LOAD T j
DISABLE T, COUNT

PRESCALER MODULO
(RANGE 1-64 DECIMAL
01-00 HEX)

ENABLE 1, COUNT

(RETRIGGERABLE)

R242 TI
Counter Timer I Register

R246 P2M
Port 2 Mode Register
(F~; Write

(F2H ; Read/Write)

T, INITIAL VALUE (WHEN WRITTEN)

Only)

P2 o-P27 I/O DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

'-----(RANGE 1-256 DECIMAL 01-00 HEX)
T, CURRENT VALUE (WHEN READ)

R243 PREI
Prescaler I Register

R247 P3M
Port 3 Mode Register

(F3H; Write Only)

(F7H; Write Only)

~L

COUNTMODE
o = 1, SINGLE·PASS
1 = T, MODULO·N

CLOCK SOURCE

1 = 1, INTERNAL

o=

1, EXTERNAL TIMING INPUT

LO1 PORT
2 PULL UPS OPEN DRAIN
PORT 2 PULL UPS ACTIVE

[9~

(TIN) MODe

RESERVED

o P32

00

'" INPUT
P35 = OUTPUT
1 P32 = DAVO/RDYO P35 = RDYO/DAVO
P33

~ ~}P33

PRESCALER MODULO

= INPUT

P34

= OUTPUT

= INPUT
P34 = OM
1 1 P33 = DAV1/RDY1 P34 = RDY1/DAV1

(RANGE 1-64 DECIMAL
01-00 HEX)

o P31

= INPUT (TIN) P36 = OUTPUT (TOUT)
1 P31 '" DAV2IRDY2 P36 = RDY2/DAV2

L _ _ _ _ _ _ _ ~ ~~ ~ ~N~~!L

IN

~~~ ~ ~~~:;..~TOUT

'---------~ ~:=tj~ g~F

Figure 14. Control Registers

440

2037-014

R248 POIM
Port 0 aDd 1 Mode Register
(F8H; Write Only)

Registers
(Continued)

.0.-.0,

.-J

OUTPUT =MODE:]
00
INPUT = 01
A,z-A,s
1X

8252 FLAGS

Flag Register
(FCH ; ReadIWrite)

~~ll§
'

~--r
L ',,-PO,

LUSERFLAG F'
LUSER FLAG F2

MODE
00 II: OUTPUT
01 - INPUT
1X = A,-A"

=
EXTERNAL MEMORY TIMING
NORMAL = 0

STACK SELECTION
0 .. EXTERNAL
1 = INTERNAL

EXTENDED ... 1

HALF CARRY FLAG

DECIMAL ADJUST FLAG
OVERFLOW FLAG

SIGN FLAG

P180P~7 :~~EOUTPUT

ZERO FLAG

01 - BYTE INPUT
10
ADo-A~

=

CARRY FLAG

11 • HIGH·IMPEDANCE ADo-AD,.
is. DB. Riii. Ai-Au. A1Z-A1&
IF SELECTED

R2491PR
IDterrupt PrlO1'ity Register
(F%; Write Only)

R253 RP
Register Pointer
(F~; ReadIWrite)

I...

s

I~I~I~I~I~I~I~I~I

_:J

1ROa, IAQ5 PRIOAITY (GROUP A)
O=IRQ&>IR03
1=IR03>IRQ5

I I III ~.""--.~
RESERVED = 000
C > A > 8 = 001
A>B>C=010

A>C>B=011
cB>C>A=100
:> B > A = 101
B > A > C = 110
RESERVED::: 111

IRQO, IRQ2 PRIORITY (GROUP 8)
o = IRQ2 > IROO

1 = IROO:> IRQ2

LDON'YCARE
REGISTER
POINTER

I

IRQ1, IRQ4 PRIORITY (GROUP C)

o = IR01 > IRQ4
1 = IRQ4 :> IRQ1

R250IRQ
Interrupt Request Regiater
(FAH; ReadIWrite)

R2M SPH

Stack PoiDter
(FEH ; ReadIWrite)

I~I~I~I~I~I~I~I~I
RESERVED

T

c=

IROO
IRQ1

IR02
IR03
IRQ4
IAQ5

... IN.UT (Do = IROO)
PIa INPUT
P3t INPUT
P30 INPUT, SERIAL INPUT
To. SERIAL OUTPUT
T,

R25S SPL
Stack Pointer
(FFH ; ReadIWrite)

82511MR

Interrupt Mask Register
(F~; ReadIWrite)

____c=
___ (0,' ENABLES
= IROO) IROO-IOO&
11L.
RESERVED
' - - - - - - - - 1 ENABLES INTERRUPTS

Figure U. Control Registers

441

Z8601
Opcode

Lower Nibble (Hex)

Map

o
o

2

3

4

5

8

-=
IS
~

:!I

II:
~

8:

7

1:1

9
A

B

C

D

E

F

8

7

8

9

A

B

10,5

10,5

10,5

10,5

6,5

6,5

12/10,5

12/10,0

6,5

12/10,0

6,5

LD

LD

DJNZ

JR

LD

INC

Il,Rz

U,RI

Il1RA

JP
cc,DA

6,5

6,5

6,5

DEC
IR,

ADD

ADD

11,12

11,112

6,5

6,5

6,5

6,5

10,5

10,5

RlC
H,

RlC
IH,

ADC

ADC

ADC

ADC

Il,l2

11,112

Hz,Rl

6,5

6,5

6,5

6,5

10,5

INC
H,

INC
IR,

SUB

SUB
11,112

8,0

6,1

rl,Ia
6,5

SUB
H.,H,

6,5

10,5

10,5

IP
IRB,

SRP

SBC

SBC

SBC

1M

11,12

Il,lrz

SBC
H"H,

8,5

8,5

6,5

6,5

10,5

DA
H,

DA
IR,

OR

OR

n,lZ

r1,II2

OR
H"H,

10,5

10,5

6,5

6,5

10,5

pop

POP

AND

AND

Il,la

11,112

AND
H"H,

H,

JR,

6,5

6,9

6,5

COM
H,

COM
IH,

TCM

TCM

11,IZ

rl,lr2

ADD ADD ADD ADD
H.,H, IRz,R. H"IM IH"IM

10,5.

cc,HA

I'l,IM

10,5

" -

ADC ADC
IH.,H, H"IM IH"IM
10,5

10,5

-

10,5

SUB SUB SUB
IR.,H, H"IM IH"IM
10,5

-

10,5

SBC SBC
IRz,R. H"IM IH"IM
10,5

10,5

-

10,5

OR
OR
OR
IR"H, H"IM IR"IM
10,5

10,5

-

10,5

AND AND AND
IR"H, H"IM IH"IM
10,5

10,5

-

10,5

TCM TCM TCM TCM
H"H, IH"H, H"IM IR"IM

10/12,1 12/14,1

6,5

6,5

10,5

PUSH PUSH
H,
IR,

TM

TM

TN

11,12

rl,lI2

12,0

18,0

10,5

10,5

C

H.,H,

10,5

10,5

!---

10,5

TM
TN
TN
IH.,H, H"IM IH"IM

r-6,1

DECW DECW LDE LDEI
RB,
IR,
rl,IrI2 Irl,Iru
6,5

6,5

RL
H,

RL
IR,

10,5

10,5

DI

r--

12,0

18,0

LDE

LDEI

6,5

6,5

10,5

10,5

CP

CP

Il,Ia

II, lIZ

CP
H"H,

IRa,Hl

6,1

EI

~2,bl1 Irz,Irn

INCW INCW
RB,
IH,
6,5

6,5

6,5

6,5

10,5

CLR
H,

CLR
IH,

XOR

XOR

Il,Ia

XOR
H"H,

6,5

6,5

12,0

rl,lrz
18,0

RRC
H,

RRC
IR,

LDC

LDCI

II,

6,5

6,5

12,0

SRA
IR,

LDC

6,5

6,5

6,5

RR
H,

RR
IR,

LD

8,5

8,5

12,IIll

______

18,0

~#

14,0

CP
CP
H"IM IH"IM

10,5

10,5

RET
!---

10,9

16,0

lOR XOR XOR
IH"H, H"IM IR"IM

IRET
!--6,5

LD
II,

20,0

10,5

10,5

20,0

10,5

CALL
DA

LD

10,5

12,

RCF

z, Hz

r-6,5

SCF
!---

x, 81

10,5

6,5
CCF

LD
LD
LD
LD
H"H, IR"H, H"IM IH"IM

r--

10,5

6,0

LD
H"IR,

111,12

______

r--

10,5

10,5

LD

~~~

CP

LDCI CALL*
Ju,lrr! IHH,

Illlrz
6,5

SWAP SWAP
H,
IH,
~,

10,5

Ina Irl,Irra

SRA
H,

F

E

5

6,5

6,9

D

4

3

DEC
H,

10,5

8

2

~,

______

NOP

~~~

______

~~

~,

________

~~~

________

~J

~

~

Bytasper

Instrucllon

3

2

2

3

Lower

Opc:ode
Nibble
Execution

~

Pipeline

CYClea~CYcl"
Upper

Opc:ode _
Nibble

A

First
Operand

10,5

CP
H"H,

Mnemonic

Second
0percmcI

Legend:
H = 8-B,i Address
r
4·BII Addre..
HI or rl = Dst Ad.dreas
H. or r, = Src Address

=

Sequence:
Opcode, First Operand, Second Operand
Note: The blank areas are not defined.

·2-byte Instruction; fetch cycle appears as a. 3-byte Instruction

442

8085-002

Absolute
Maximum
Ratings

Voltages on all pms
with respect to GND .......... -0.3 V to + 7.0 V
Operatmg AmbIent
Temperature ........ See Ordering Information
Storage Temperature ........ -65°C to + 150 °C

Standard
Test
Conditions

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:

Stresses greater than those hsted under Absolute MaxImum Rahngs may cause permanent damage to the devIce.
ThIS IS a stress rahng only I operation of the deVICe at any

condItIon above those mdlcated m the operahonal sections
of these specIficatIons IS not Imphed. Exposure to absolute
maXlmum ratmg conditIons for extended penods may affect
devIce reliabIlIty,

o +4.75 V

:$

Vee

:$

+5.25 V

o GND = a V
o O°C :$ TA :$ +70°C*
*See Ordermg Information sectIon for package
temperature range and product number.

+5V

+5V

+5V

21K

+5V

18K

15k
14LS04

1.Sk
74LS04

I

CL

= 15pF MAX

" - - - - -........_ _ XTAl1

1

CL = 15pF MAX

Figure 15. Test Load I

DC
Characteristics

Parameter

Min

Max

Unit

VeH

Clock Input High Voltage

3.8

Vee

V

Driven by External Clock Generator

VeL

Clock Input Low Voltage

-0.3

0.8

V

Driven by External Clock Generator

VIH

Input High Voltage

2.0

Vee

V

VIL

Input Low Voltage

-0.3

0.8

V

VRH

Reset Input High Voltage

3.8

Vee

V

VRL

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

VOL

Output Low Voltage

IlL

Input Leakage

IOL

Output Leakage

IJR

Symbol

Condition

V

IoH

= -250 p.A

0.4

V

IoL

= +2.0 rnA

-10

10

p.A

0 Vs VIN s +5.25 V

-10

10

p.A

0 Vs VIN s +5.25 V

Reset Input Current

-50

p.A

Vee

Ice

Vee Supply Current

180

rnA

IMM

VMM Supply Current

10

rnA

VMM

Backup Supply Voltage

I. For AO~All.

808,·0313.0312

Figure 17. External Clock Interface Circuit

Figure 16. Test Load 2

2.4

3

MDS. SYNC, SeLK and lACK on the Z8602

Vee
versIOn,

V

=

+5.25 V, VRL

Notes

=0V

Power Down Mode
Power Down

IOH = ~100 p.A and IOL = 1.0 rnA.

443

I-...
I!
w

R

External 1/0
or Memory
Read and
Write Timing

Number

Symbol

TdA(AS)
2

TdAS(A)
TdAS(DI)

3
4
TwAS
5 - - TdA(DS) 6a
TwDS
6b
TwDS
TdDS(DI)
7

Parameter

Min

Address Vahd to Address Strobe Delay
Address Strobe to Address Float Delay

50
70

II

TdDS(AS)
TdR(AS)

12 - - TdDS(R) TdDO(DS)
13
TdDS(DO)
14
15
16

TdW(AS)
TdDS(W)

Unit

Notes

1,2
1,2

360

ns
ns
ns

ns
ns
ns

1,3
1,3
1,4

ns
ns

1,2

Address Strobe to Data In Valid Delay
Address Strobe Width
80
Address Float to Data Strobe Delay - - - 0
Data Strobe Width Read
250
Data Strobe Width Write
160
Data Strobe to Data In Valid Delay

8 - - ThDS(Dl)- Data In Hold Time
TdDS(A)
Data Strobe to Address Change Delay
9
10

Max

200

0
80

1,4
1,2
ns
ns---I---

Data Strobe to Address Strobe Delay
70
50
Read Valid to Address Strobe Delay
Data Strobe to Read Change Delay - - - 60
Data Out Valid to Data Strobe Delay
50

1,2
ns
1,2
ns
ns--1,2--

Data Strobe to Data Out Change Delay
Write Valid to Address Strobe Delay

80
50

ns
ns

1,2
1,2
1,2

Data Strobe to Write Change Delay

60

ns

1,2

ns

NOTES:
4. Address Strobe and Data Strobe to Data In ValId delay hmes
represent memory system aq;ess hmes and are given for an 8
MHz crystal mput frequency For lower frequencies, the change
In four clock periods must be added to TdAS(DI) and the
change In three clock penods added to TdDS(DI)

1 Test Load 1.
2. Delay hmes gIven are for an 8 MHz crystal mput
frequency. For lower frequenCles, the change

In

clock

penod must be added to the delay hme.
3. Data Strobe WIdth IS given for an 8 MHz crystal mput
frequency For lower frequencies the change In three
clock perIods must be added to obtam the minImum
width. The Data Strobe Width vanes accordmg to the

5. All hmlng references assume 2.0 V for a lOgIC "I" and
08 V for a lOgIC "0,"

InstructIon bemg executed.

PORT~
DM

PORT 1

A8-A" OR A8-A15

00-07

our

00-07 IN

~--~~------~CD~-------'I

444

2037-016

Additional
Timing
Table

Symbol

Number

Parameter

1

TpC

Input Clock Period

2

TrC, TIC

Input Clock R,se and
Fall Times

Min

Max

Unit

125

1000
25

ns

Notes

ns
3

TwC
Input Clock Wldth
37
ns
3
3
4 - - TdSC(AS)- System Clock Out to Address - - - - - - - - - - - n s - - - l - - Strobe Delay T,me
TdSY(DS)

Instruction Sync Out to Data
Strobe Delay Time

200

ns

1,2

6

TwSY

Instruchon Sync Out Width

1, 2

TwI

Interrupt Request via
Port 3 Input W,dth

160
100

ns

7

ns

5

NOTESTest ConditIons use Test Load 1 for SCLK when output
through the Port 3 pms and Test Load 2 on the SCLK
and SYNC direct outputs on Z8602.

3 From external clock generator
4. All hmmg references assume 2
o 8 V for a logiC "0 "

a v for a logiC \\ 1" and

I-

2. Times glVen assume an 8 MHz crystalmput frequency.
For lower frequencies, the change In two clock penods
must be added

~

w

I

CLOCK

SCLK

\\....___1

\

AS

I

I·

Ds

SYNC

IRQ"

2037-017

\~-I

DATAIN

~ SAMPLED

READ CYCLE

r
~_______.-'lr-~-Y-~<""'''
l.--~0~~~S________________________
k(

445

Handshake
Timing

Number

Symbol

Parameter

Min

Max

Unit

I

TsDI(DA)

Data In Setup TIme

0

ns

2

ThDA(DI)

Data In Hold Time

230

ns

3

TwDA

Data Available Width

175

4a
4b

TdDAL(RY) Data AvaIlable Low to Ready
Delay Time

20
0

5a
5b

TdDAH(RY) Data Available High to Ready
Delay Time

6

TdDO(DA)

Data Out to Data Available
Delay Time

7

TdRY(DA)

Ready to Data AvaIlable Delay TIme

ns

Notes

1,2

175

1,2
ns
ns--1,3--

150
0

ns
ns

50

ns

0

205

ns

Min

Max

Unit

460

ns

1,2
1,3

NOTES:
1. Test Load 1

2. Input Handshake
3. Output Handshake

DATA IN

DiV
INPUT

RDY
OUTPUT

Input Handshake

DATA OUT

DATA OUT VALID

DAY
OUTPUT

RDY
INPUT

Output Handshake

Z8602. Z8603
Memory Port
Timing

Number

2

Symbol

Parameter

TdA(DI)

Address Valid to Data In
Valid Delay Time

ThDI(A)

Data in Hold Time

0

Notes

ns

NOTES:
1. Test Load 2
2. Delay tunes are specIfled for an mput clock frequency of 8 MHz.
3. All hming references assume 2.0 V for a logic" 1" and 0.8 V for a logIC "0".

AO-A,.

~

"b(

ADDRESS VALID

_~~r.'~'=~0=2j~------IT~1~
Do-D7

446

DON'T CARE

~

DATA IN VALID

~

2037·018, 019

Ordering
Information

28601

CE

28601
28601

8.0 MHz

28MCU
(2K XROM,
64-pin)

Same as above

28602

QS

8.0 MHz

Same as above

Same as above

28603

RS

8.0 MHz

28MCU
(2K XROM,
Prototype Device,
40-pin)

CS

8.0 MHz

Same as above

DE

8.0 MHz

28601

PE

8.0 MHz

Same as above

28601

PS

8.0 MHz

Same as above

CeramIc, D

=

Cerdlp, P

=

,

Description

QE

28MCU
(2K ROM, 40-pin)

8.0 MHz

Package/
Temp
Speed

28602

8.0 MHz

DS

=

Product
Number

Description

28601

NOTES: ~

00-2037-02

Package/
Temp
Speed

Product
Number

PlastIc, Q

=

QUlP, R

=

Protopack; E

=

-40'C to +85'C, S = O'C to +70'C.

447

Z8® Family of
Microcomputers
Z8611 • Z8612 • Z8613
Product
Specification

~
zilog

June 1982
28611 Single·Chip Microcomputer with 4K ROM
28612 Development Device with Memory Interface
Z8613 Prototypmg Device with EPROM Interface

Features

General
Description

• Complete microcomputer, 4K bytes of ROM,
128 bytes of RAM, 32 I/O lines, and up to
6DK bytes addressable external space each
for program and data memory.

i......

@
w

• l44-byte register file, including 124
general-purpose registers, four I/O port
registers, and 16 status and control
registers.

• On-chip oscillator which accepts crystal or
external clock drive.

• Average instruction execution time of
2.2 p.s, maximum of 4.25 p.s.

• Low-power standby option which retains
contents of general-purpose registers.

• Vectored, priority interrupts for I/O,
counter/timers, and UART.

• Single + 5 V power supply-all pins TTL
compatible.

The Z8611 microcomputer introduces a new
level of sophistication to single-chip architecture. Compared to earlier Single-chip microcomputers, the Z86ll offers faster execution;
more efficient use of memory; more sophisticated interrupt, inpuVoutput and bit-manipulation capabilities; and easier system expansion.
Under program control, the Z8611 can be
tailored to the needs of its user. It can be con-

figured as a stand-alone microcomputer with
4K bytes of internal ROM, a traditional microprocessor that manages up to l2DK bytes of
external memory, or a parallel-processing element in a system with other processors and
peripheral controllers linked by the Z-BUS. In
all configurations, a large number of pins
remain available for I/O.

PORT 1

(BYTE
PROGRAMMABLE)
110 OR ADo-AD7

Figure 1. Z8611 MCU PID FunclloDS

2038·001, 002

• Full-duplex UART and two programmable
8-bit counter/timers, each with a 6-bit
programmable prescaler.
• Register Pointer so that short, fast instructions can access any of nine workingregister groups in 1.5 p.s.

+5V

pa,

XTAl2

P3,

XTAL1

P2,

P",

P2,

P3,

P2,

REm
R/iN
DS
AS

P2,
P2,
P2,
P2,

P3,

P"

GND

po,

P3,

P3,

po,
po,
po,
po,
po,
po,
po,
po,

Pl,
Pl,
Pl,
Pl,
Pl,
Pl,
Pl,
Pl,

Figure 2. Z8611 MCU PID Aas1gDlDeDIs

449

I

Architecture

28611 architecture is characterized by a
flexible I/O scheme, an efficient register and
address space structure and a number of
ancillary features that are helpful in many
applications.
Microcomputer applications demand powerful I/O capabilities. The 28611 fulfills this with
32 pins dedICated to Input and output. These
lines are grouped into four ports of eight lines
each and are configurable under software control to provide timing, status signals, serial or
parallel I/O With or without handshake, and an
address/data bus for interfacing external
memory.
Because the multiplexed address/data bus is
merged with the I/O-oriented ports, the 28611
can assume many different memory and I/O
configurations. These configurations range
from a self-contained microcomputer to a

OUTPUT

Vee

microprocessor that can address 120K bytes of
external memory (Figure 3).
Three baSIC address spaces are available to
support this wide range of configurations: program memory (internal and external), data
memory (external) and the register file (internal). The 144-byte random-access register file
is composed of 124 general-purpose registers,
four I/O port registers, and 16 control and
status registers.
To unburden the program from coping with
real-time problems such as serial data commUnication and counting/timing, an asynchronous receiver/transmitter (UART) and two
counter/timers with a large number of userselectable modes are offered on-chip. Hardware support for the UART IS minimized
because one of the on-chip timers supplies the
bit rate.

XTAL

GND

As Os

RM REseT

!!

110

ADDRESS OR 110

ADDRESS/DATA OR 1/0

(BIT PROGRAMMABLE)

(NIBBLE PROGRAMMABLE)

(BYTE PROGRAMMABLE)

Figure 3. Functional Block Diagram

Pin
Description

AS. Address Strobe (output, active Low).
Address Strobe is pulsed once at the beginning of each machine cycle. Addresses output
via Port 1 for all external program or data
memory transfers are valid at the trailing edge
of AS. Under program control, AS can be
placed in the high-impedance state along with
Ports 0 and 1, Data Strobe and Read/Write.
OS. Data Strobe (output, active Low). Data
Strobe is activated once for each external
memory transfer.

POo-Po,. Plo-PI7. P20-P27. P30-P3o,. I/O Port
Lines (input/outputs, TTL-compatible). These
32 lines are divided into four 8-bit I/O ports

450

that can be configured under program control
for I/O or external memory interface.

RESET. Reset (input, active Low). RESET initializes the 28611. When RESET is deactivated,
program execution begins from internal program location OOOCH.
R/W. Read/Write (output). RlW is Low when
the 28611 is writing to external program or
data memory.
XTALI. XTAL2. Crystall, Crystal 2 (time-base
input and output). These pins connect a seriesresonant crystal (8 MHz maximum) or an external single-phase clock (8 MHz maximum) to
the on-chip clock oscillator and buffer.

2038-003

Address
Spaces

Program Memory. The 16-bit program

counter addresses 64K bytes of program
memory space. Program memory can be
located in two areas: one internal and the
other external (Flgure 4). The first 4096 bytes
conslst of on-chlp mask-programmed ROM. At
addresses 4096 and greater, the Z8611
executes external program memory fetches.
The hrst 12 bytes of program memory are
reserved for the mterrupt vectors. These locations contain six 16-bit vectors that correspond
to the SlX avallable mterrupts.
Data Memory. The Z8611 can address 60K

bytes of external data memory beginning at
5535

locahons 4096 (Figure 5). External data
memory may be included wlth or separated
from the external program memory space.
DM, an optional I/O function that can be
programmed to appear on pin P34, is used
to distinguish between data and program
memory space.
Register File. The 144-byte register file
includes four I/O port registers (RO-R3), 124
general-purpose reglsters (R4-RI27) and 16
control and status reglsters (R240-R255). These
registers are asslgned the address locahons
shown in Figure 6.
Z8611 instructions can access registers
65535 .....- - - - - - - - - . ,

EXTERNAL
ROM OR RAM

4096
4095
ON·CHIP

ROM

Loeatlonol
flrslbyle01
Instruction

executed
aftarreset

;,

Interrupt
Vector
jLowerByleI

Interrupt

11

IRQ5

10

IRQS

9

IR04

•
•
7

IR03

'1"
41-'

IR02

,

IRQ1

1

IROO

0

IROO

3

Vector
(Upper Byte)

~------------

EXTERNAL
DATA
MEMORY

IRQ4

IRC3

IRQ2

:~:: 1 - - - - - - - - - - ;

IRQ1

NOT ADDRESSABLE

Figure 4. Program Memory Map

L.OCATION

m
m

STACK POINTER (IITS ' ..0
STACK POINTER (IITS 111..1)
REOISTER POINTER

2S2
.a1

INTERRUPT MASK FlEGISTER

.ao

INTERRUPT REQUEST FlEOISTEFI

2••

•••
24a
247

...'45

PROQRAM CONTROL. FLAGS

INTERRUPT PRIORITY REGISTER
PORTS 0-1 MODE

POAT 3 MODE
PORT 2 MODE
TO PREaCALER

24'
243

TIMER/COUNTER 0

'42

TIMER/COUNTER 1

241

TIMER MODE

240

SERIAL. 110

T1 PRESCAL.ER

IDI!NTIFIIA8
SPC

SPH
RP
FL.AQS
IMR
IRa

IPR
P01M
P3M
P.M
PREO

TO
PRE1
T1

TMR
SIO

Figure 5. Data Memory Map

I __ ~I3::::;::====1

~----------------~.~
Tlilllupp'rnlbbl,ollh,r,glstlllrflieaddress
provldilldby IheI'IIIglstlllrpointer splllcifles
thlll achvill working I'IIIglster group

12

I
I
1
1

NOT

IMPL.EMENTED

I

127

255

11--'--'-"'-'-"---"'-'--1 253

SPECIFIED WORKINO·
REGISTER GROUP

The lower
nlbbleo!
thllll'lllgisllllr
mliladdl'lllss
provided by
hillinsiruction
pOints to IhIiI
specilled
register

... ,

GENERAL.-PURPOSE
REGISTERS

15
PORT 3

P3

PORT 2

P'

PORT 1

P1

PORTO

PO

Figure 6. The Register File

21rJS 004. 005 '2037-006, 007

----"OPORr.----- 3
Figure 7. The Register Pointer

451

Address
Spaces
(Continued)

directly or indirectly with an 8-bit address
field. The 28611 also allows short 4-bit register
addressing using the Register Pointer (one of
the control registers). In the 4-blt mode, the
register hie is divided into nine workingregister groups, each occupying 16 contiguous
locations (Figure 7). The Register Pointer
addresses the starting location of the active
working-register group.

Stacks. Either the mternal register file or the
external data memory can be used for the
stack. A 16-bit Stack Pointer (R254 and R255)
IS used for the external stack, which can reside
anywhere in data memory between locations
4096 and 65535. An 8-bit Stack Pointer (R255)
is used for the internal stack that resides within
the 124 general-purpose registers (R4-RI27).

Serial
Input/
Output

Port 3 lines P30 and P37 can be programmed
as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The
bit rate is controlled by Counter/Timer 0, with
a maximum rate of 62.5K bits/second.
The 28611 automatically adds a start bit and
two stop bits to transmitted data (Figure 8).
Odd parity is also available as an option. Eight
data bits are always transmitted, regardless of

parity selection. If parity IS enabled, the eighth
bit is the odd parity bit. An interrupt request
(IRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight
data bits and at least one stop bit. If parity is
on, bit 7 of the received data is replaced by a
parity error flag. Received characters generate
the IRQ3 interrupt request.

Transmitted Data
(No Parity)

Received Data
(No Parity)
Ispl~I~I~I~I~I~I~I~IMI
LSTARTBIT

LSTARTBIT

' - - - - - - E I G H T D~TA BITS

' - - - - - - E I G H T DATA BITS

TWO STOP BITS

L - - - - - - - - - O N E S T O P BIT

Transmitted Data
(With Parity)

Received Data
(With Parity)

~pl~1 pl~I~I~I~I~I~I~IMI

TL

II

LSTART BIT
' - -_ _ _ SEVEN DATA BITS
L -_ _ _ _ _ _ _ PARITV ERROR FLAG

_LsTARTBIT
'------SEVEN DATA BITS
ODD PARITY
TWO STOP BITS

- - - - - - - - O N E S T O P 81T

L.

Figure 8. Serial Data Formats

Counter/
Timers

452

The 28611 contains two 8-bit programmable
counter/timers (To and TI), each driven by its
own 6-bit programmable prescaler. The TI
prescaler can be driven by internal or external
clock sources; however, the To prescaler is
driven by the internal clock only.
The 6-bit prescalers can divide the input frequency of the clock source by any number
from 1 to 64. Each prescaler drives its counter,
which decrements the value (l to 256) that has
been loaded into the counter. When the
counter reaches the end of count, a timer
interrupt request-IRQ4 (To) or IRQ5 (TI)is generated.
The counters can be started, stopped,
restarted to continue, or restarted from the
initial value. The counters can also be programmed to stop upon reaching zero (single-

pass mode) or to automatically reload the
initial value and continue counting (modulo-n
continuous mode). The counters, but not the
prescalers, can be read any time without
disturbing their value or count mode.
The clock source for TI is user-definable and
can be the internal microprocessor clock
(4 MHz maximum) divided by four, or an
external signal input via Port 3. The Timer
Mode register configures the external timer
input as an external clock (I MHz maximum),
a trigger input that can be retriggerable or
non-retriggerable, or as a gate input for the
internal clock. The counter/timers can be programmably cascaded by connecting the To output to the input of TI. Port 3 line P3s also
serves as a timer output (Tour) through which
To, TI or the internal clock can be output.

2047·009

-

110 Ports

------------

The 28611 has 32 Imes dedicated to input
and output. These Imes are grouped mto four
ports of eight lines each and are configurable
as input, output or address/data. Under software control, the ports can be programmed to

provide address outputs, liming, status Signals,
serial I/O, and parallel I/O with or without
handshake. All ports have active pull-ups and
pull-downs compatible with TTL loads.

Port 1 can be programmed as a byte I/O
port or as an address/data port for interfacing
external memory. When used as an I/O port,
Port 1 may be placed under handshake control. In this configuration, Port 3 lines P33 and
P34 are used as the handshake controls RDY 1
and DAV1 (Ready and Data Available).
Memory locations greater than 4096 are
referenced through Port 1. To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If
more than 256 external locations are required,
Port 0 must output the additional lines.
Port 1 can be placed in the high-impedance
state along with Port 0, AS, DS and RlW,

allowmg the 28611 to share common resources
in multiprocessor and DMA applications. Data
transfers can be controlled by assigning P33 as
a Bus Acknowledge input, and P34 as a Bus
Request output.

Port 0 can be programmed as a nibble I/O
port, or as an address port for mterfacing
external memory. When used as an I/O port,
Port 0 may be placed under handshake control. In this configuration, Port 3 lines P32 and
P3s are used as the handshake controls DAVo
and RDYo. Handshake signal assignment is
dictated by the VO direction of the upper
nibble P04-P(}z,
For external memory references, Port 0 can
provide address bits As-All (lower nibble) or
As-A1S (lower and upper nibble) dependmg
on the required address space. If the address
range requires 12 bits or less, the upper nibble
of Port 0 can be programmed independently as

I/O while the lower nibble is used for addressing. When Port 0 nibbles are defined as
address bits, they can be set to the highimpedance state along with Port 1 and the control signals AS, DS and R/W.

Port 2 bits can be programmed independently as input or output. This port is
always available for VO operations. In addition, Port 2 can be configured to prOVide
open-drain outputs.
Like Ports 0 and 1, Port 2 may also be
placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as
the handshake controls lines DAV2 and RDY2.
The handshake signal assignment for Port 3
lines P31 and P36 is dictated by the direclion
(input or output) assigned to bit 7 of Port 2.
Port 3 lines can be configured as VO or controllmes. In either case, the direction of the
eight lines is fixed as four input (P30-P33) and
four output (P34-P37). For serial VO, lines P30
and P37 are programmed as serial in and serial
out respectively.
Port 3 can also provide the following control
functions: handshake for Ports 0, 1 and 2
(DAVand RDY); four external interrupt
request signals (IRQO-IRQ3); timer input and
output signals (TIN and TOUT) and Data
Memory Select (DM).
203"·008

---

PORT'

(1/0 OR ADo-AD7)

HANDSHAKE CONTROLS
} DAV1 AND ADY1
(• .,AND .3,)

i......

Figure 9a. Pori 1

j

PORT 0

(I/O OR A.-A1s)

Figure 9b. Pori 0

PORT 1(1/0)

}

HANPSHAKE CONTROLS

IlAV2 AND RDY2

(P~

AND P3e)

Figure 9c. Pori 2

Figure 9cl. Pori 3

453

~

D

Interrupts

The 28611 allows six different mterrupts from
eight sources: the four Port 3 lines P30-P33,
Serial In, Serial Out, and the two counter/
timers. These interrupts are both maskable and
prioritized. The Interrupt Mask register globally or mdlvldually enables or disables the SIX
interrupt requests. When more than one interrupt is pending, priorities are resolved by a
programmable pnority encoder that is controlled by the Interrupt Priority register.
All 28611 interrupts are vectored. When an
interrupt request IS granted, an interrupt
machine cycle is entered. This disables all

subsequent interrupts, saves the Program
Counter and status flags, and branches to the
program memory vector locahon reserved for
that interrupt. This memory location and the
next byte contain the 16-bit address of the
interrupt service routine for that particular
interrupt request.
Polled mterrupt systems are also supported.
To accommodate a polled structure, any or all
of the interrupt inputs can be masked and the
Interrupt Request register polled to determme
which of the interrupt requests needs serVlCe.

Clock

The on-chip oscillator has a high-gam,
series-resonant amphfier for connection to a
crystal or to any suitable external clock source
(XTALl = Input, XTAL2 = Output).
The crystal source is connected across
XTALl and XTAL2., using the recommended
capacitors (Cl = 15 pF)'from each pin to

ground. The speCifications for the crystal are
as follows:

Power Down
Standby
Option

The low-power standby mode allows power
to be removed without losmg the contents of
the 124 general-purpose registers. This mode
IS avallab1e to the user as a bondmg ophon
whereby pin 2 (normally XTAL2) is replaced
by the VMM (standby) power supply mput. This
necessitates the use of an external clock
generator (mput = XTALl) rather than a
crystal source.
The removal of power, whether mtended or
due to power fallure, must be preceded by a
software routme that stores the appropnate
status into the register file. Figure 10 shows

Z8612
This 64-pin development version of the
Development 40-pm mask-programmed 28611 (Figure 11)
allows the user to prototype the system 10 hardDevice
ware with an actual device and to develop the
code that IS eventually mask-programmed mto
the on-chip ROM of the 28611.
The 28612 is identical to the 28611 with the
following exceptions:
• The internal ROM has been removed.
• The ROM address hnes and data lines are
buffered and brought out to external pins.
• Control lines for the new memory have
been added.

• AT cut, senes resonant
• Fundamental type, 8 MHz maximum
• Series resistance, R" s 100 n

the recommended ClrcUlt for a battery back-up
supply system.
+5V

0----__.---/

VDD

TRICKLE

CHARGErr_'WI~-tC

Z8811

J
Figure 10. Recommended Driv.. Circuit
lor Power Down Operation

P2,
P2,
P3,

Pl,

Z8812

Pl,

Pin Description. The functions of the 28612
I/O lines, AS, DS, R/W, XTALl, XTAL2 and
RESET are identical to those of their 28611
counterparts. The functions of the remainmg
24 pins are as follows:

Ao-All. Program Memory Address (outputs).
Ao-All access the first 4K bytes of program
memory.

Pl,
D,
D,

24

". ..
" ..
"

25
27

"

2.

As
As

30
31

"

32

Figure II. Z8612 Pin Assignments

454

2038-010,011

Z86l2
Development
Device
(Continued)

Z86l3
Protopack
Emulator

00-0,. Program Data (mputs). Program data
from the first 4K bytes of program memory is
input through pins 00-07.
lACK. Interrupt Acknowledge (output, active
High). rACK is driven High 10 response to an
interrupt during the interrupt machine cycle.
MOS. Program Memory Data Strobe (output,
active Low). MOS is Low during an instruction
fetch cycle when the hrst 4K bytes of program
memory are being accessed.
The Z8613 MPE (Protopack) IS used for
prototype development and preproduction of
mask-programmed applications. The Protopack
IS a ROMless version of the standard Z8611 ,
housed in a pm-compatible 40-pin package
(Figure 12).
To provide pin compatibility and mterchangeability with the standard maskprogrammed deVice, the Protopack carries
(piggy-backs) a 24-pin socket for a direct
interface to program memory (Figure I). The
24-pin socket is equipped with 12 ROM

SCLIC. SysteII'J Clock (output). SCLK is the
internal clock output through a buffer. The
clock rate is equal to one-half the crystal
frequency.
SYNC. Instruction Sync (output, active Low).
This strobe output IS forced Low during the
internal clock period preceding an opcode
fetch.

address lines, 8 ROM data lines and necessary
control hnes for interface to 2732 EPROM for
the hrst 4K bytes of program memory.
Pin compatibility allows the user to
design the pc board for a final 40-pin maskprogrammed Z8611, and, at the same time,
allows the use of the Protopack to bUild the
prototype and pilot production units. When the
final program IS established, the user can then
switch over to the 40-pm mask-programmed
Z8611 for large volume production. The Protopack IS also useful in small volume applications where masked ROM setup hme, mask
charges, etc., are prohibihve and program
flexibility is desired.
Compared to the conventional EPROM
versions of the single-chip microcomputers,
the Protopack approach offers two main
advantages:
• Ease of developing various programs during
the prototyping stage: For instance, in
applications where the same hardware
configuration is used with more than one
program, the Z8613 Protopack allows
economical program storage in separate
EPROMs (or PROMs). whereas the use of
separate EPROM-based smgle-chip
microcomputers is more costly.

Figure 12. The Z8813 Microcomputer Protopack Emulator

Instruction
Set
Notatlon

Adclr_ing Mod... The follOWing notation IS used
to describe the addressing modes and instruchon
operations as shown in the Instruction summary.
IRR
Irr
X
DA
RA
1M

R
1ft
Ir

RR

2038·012

Indirect register pair or indirect workmg-reglster
pair address
Indirect workmg-reglster pair only
Indexed address
Direct address
Relative address
Immediate
Register or workmg-reglster address
Workmg-reglster address only
Indirect-register or mdlrect workmg-register
address
Indirect workmg-register address only
Register pair or workmg register pair address

• Elimination of long lead time in procuring
EPROM-based microcomputers.
Symbols. The follOWing symbols are used in
describing the instruction set.
clat
arc
cc
@

SP
PC
FLAGS

RP
IMR

Destmahon location or contents
Source locahon or contents
Condllion code (see list)
Indirect address prefIX
Stack pomter (control registers 254-255)
Program counter
Flag register (control register 252)
Register pomter (control register 253)
Interrupt mask register (control register 251)

Assignment of a value is indicated by the symbol
"-". For example,

dst - dst + src
indicates that the source data is added to the
destination data and the result is stored in the
destination location. The notation "addr(n)" is used
to refer to bit "n" of a given location. For example,
dst (7)
refers to bit 7 of the destination operand.

455

I......

i!w

I

Instruction
Set
Notation
(Continued)

Flags. Control Register R252 contains the followmg
six flags:
C
Z

S
V
D
H

Condition
Codes

*
X

Always true
Carry
No carry
Zero

C

NC
Z
NZ
PL

OllO
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010

Not zero

OV
NOV
EQ

NE
GE

LT

GT
LE
UGE

III I

C
C
Z
Z

ULT
UGT
ULE

= 1
= a
= 1
= a

S = a
S =1

Plus
Mmus
Overflow
No overflow
Equal
Not equal
Greater than or equal
Less than
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal

MI

all 1
1011
0011
0000

Flags Set

Meaning

Mnemonic

1000
0111
III 1

Cleared to zero
Set to one
Set or cleared accordmg to operatIon
Unaffected
Undefined

1

Carry flag
Zero flag
Sign flag
Overflow flag
Decimal-adJust flag
Half-carry flag
Value

Affected flags are indicated by:

o

=

V
1
V =

a

Z = 1
Z = a
(S XOR V) = a
(SXOR V) = 1
[ZOR (SXOR V)) = a
[Z OR (S XOR V)) = 1

C = a
C = 1
(C = a AND Z = 0)
(C ORZ) = 1

Never true

Instruction
Formats

ope
ds.

CCF, DI, EI.IRET, NOP,
ReF. RET, seF

ope

INCr

One-Byte IlIIIlructlollll

I MODe I

ope

dsUsrc

eLA, CPt.. DA, DEC,
OR

h 1 1 0 I dsUsrc I

ope

OR 1 1 1 0
OR 1 1 1 0

ds'

RRC, SRA, SWAP

I

ope
I---'.::.s'::'.--lOR 11 1 1 01 dst

MODE

or.

~~~:" ~~~R~~~-:R.POPI
ope

MODE

SRP

MODE

.S.

MODE

MODE

ope

ADC, ADD, AND,
CP, OR, SBC. SUB,
TeM, TM, XOR
LD, LDE, LDEI,
LDC, LDCI

dstisrc sreld,'
dstlsrc
ope
sreld_,
dst

lope

OR

11

1 1

01

LD

b 1 1 01

dot

ope

.n:
d••

OR 1 1 1 0
OR 1 1 1 0

.n:

ADe. ADD, AND, CP,
LD, OR, SBC, SUB,
TeM. TM, XOR

LO

.ot

OPC
MODE
datlsrc
ADDRESS

LD

ffi

JP

D....
DA,

LD

VALUE

Id8t1CC~ OPC

OR

VALUE

VALUE

ope

ADC, ADD, AND, CP,
LD, OR, SBC, SUB,
TeM, TM. XOR

JP, CALL (Indirect)

ds.

ope

ds.

ope
DJNZ,JR

CALL

DA.
DA,

Two-Byte IlIIIlructlollll

Figure 13. IlIIIlructlon Formats

456

2037-013

-----

--~---

Instruction
Summary

Instruction
aDd Operation
ADC dsl,sre

Addr Mode
clst

arc

(Nole 1)

Opcode Flags Affected
Byte
(Hex)
CZSVDH

10

o•

dsl-dsl+sre+C
ADD dsl,sre
dsl - dsl + src
AND dsl,sre
dsl - dsl AND sre

LDE dsl,sre

dsl - sre
(Nole 1)
(Nole 1)

00

• * 0 •

LDEI dsl,sre

dsl - sre

• 0 - -

DA
SP-SP-2
IRR
@SP - PC; PC - dsl

D6
D4

------

OR dsl,sre

CCF

EF

* - - - - -

POPdsl
dsl- @SP
SP - SP + 1

R

IR

BO
Bl

------

dsl - 0
COM dsl

dsl- NOT dsl

R
IR

60
61

• 0 - -

CP dsl,sre

(Nole 1)

AD

R

dst - DA dsl

IR

40
41

• X- -

DEC dsl

R
IR

00
01

RR
IR

80
81

dsl-dsl-l

RA

r - r- 1
Ifr .. 0
PC-PC+dsl
Range: + 127, -128

R
IR
INCW dst

RR

dsl - dsl +

IR

IRET

FF

------

(Nole 1)

40

- • * 0 - -

R
IR

50
51

------

70
71

------

CF

o- - - - -

AF

------

R
IR

RCF

C - 0

RLCdsl ~ R
' , • IR

10
11

-***--

RR dsl

i.m '-E::3-I I~

EO
El

------

rA
r=O-F

------

RL dsl

91

ca:::a
R
' , • IR

SBC dsl,sre
dsl- dsl-sre-C

(Nole 1)

------

lriJ @

R
IR

SRP sre

1m

'!

•• 1

30

.

DF

1 - - - - -

DO
Dl

* * • 0

31

- * * *- -

AO
Al

-*.*--

BF

* * • * • *

DA

If cc IS lrue
PC - dsl

IRR

JR cc,dsl

RA

true,

------

r
R

1m
R

r
X
r
Ir
R
R
R
IR
IR

X
r
Ir
r
R
IR
1m
1m
R

r
Irr

Irr

Ir
Irr
dst - sre
r - r + I; rr - rr + I

Irr
Ir

TCM dsl,sre
(NOT dBI) AND sre

(Nole 1)

60

-·*0--

TM dsl, sre
dst AND Bre

(Nole I)

70

-*·0--

(Nole I)

BO

·0 - -

cS
c=O-F

------

Note I

C2
D2

------

C3
D3

------

.

X

XOR dsl,src
dsl- dBI XOR src

------

•• I

20
FO
FI

------

rC
r8
r9
r=O-F
C7
D7
E3
F3
E4
E5
E6
E7
F5

(Nole I)

SWAPdsl~
R
• • IR

cD
c=O-F
30

PC-PC+dsl
Range: + 127, -128
LD dsl,sre

SUB dsl,sre
dsl - dst - src

* *X- -

These mslrucllons have an Idenllcal sel of addressing
modes, whICh are encoded for brevIty. The hrsl opcode
nibble is found m Ihe inslrucllon set lable above. The
second mbble IS expressed symbohcally by a 0 m thlB
lable, and lis value IS found 10 the followmg table to the
left of the apphcable addressmg mode pair.
For example, 10 delermme the opcode of an ADC
mslrucllon usmg the addressmg modes r (deslmallon) anH
Ir (source) IS 13.
AddrMode
dat

arc

R
R
R
IR

Ir
R
IR
1M
1M

I......
W

CO
Cl

SCF

rE
r=O-F
20
21

FLAGS - @SP; SP - SP + I
PC - @SP; SP - SP + 2; IMR(7) -1

LOCI dsl,sre

------

RP - src

dsl-dsl+1

LDC dsl,sre
dsl - src

83
93

PUSH Bre
SP-SP-l; @SP - sre

SRA dsl

INC dsl

dsl - sre

Irr
Ir

- * * * --

8F

9F

IS

Ir
Irr

90

IMR(7) - I

co

------

C-I

EI

If

82
92

NOP

RRC dsl

IMR (7) - 0

JP cc,dsl

Irr

~I~

DI

DJNZ r,dsl

r
Irr

PC - @SP; SP - SP + 2

DA dsl

DECW dsl

arc

RET

dsl- sre

dsl-dsl-l

Opcode Flags Affected
Byte
(Hex)
CZSVDH

clst

dsl- dslOR sre

C - NOT C
CLR dsl

Addr Mode

r-r + 1; rr-rr + 1

50

CAU dsl

8085·003

Instruction
and Operation

Lower
Opcode Nibble

rn
@l

Iil

rn

[§J

III
457

I

Registers

R240 SIO
Serial I/O Register
(FOH ; Read/Write)

R244 TO
Counter/Timer 0 Register
(F4H ; Read/Write)

' - - - - - S E R I A l DATA (Do'" lSB)

To INITIAL VALUE (WHEN WRITTEN)
'-----(RANGE: 1-256 DECIMAL 01-00 HEX)

To CURRENT VALUE (WHEN READ)

NOT To"MOOES
USED"" 00

~~ g~+

: ~J

INTERNAL CLOCK OUT", 11

R241 TMR
Timer Mode Register
(FlH; Read/Write)

R245 PREO
Prescaler 0 Register
(F5H ; Write Only)

I~I~I~I~I~I~I~I~I

l~t~I~I~I~I~I~I~1

j

~

US~O

= NO
FUNCTION
1 ::
LOAD
To

0 :: DISABLE To COUNT

1 = ENABLE To COUNT

=

T MODES
EXTERNAL CLOCK INPI~T '" 00
GATE INPUT = 01
(NON

~L

PRESCAlER MODULO
(RANGE 1-64 DECIMAL
01-00 HEX)

1 :: ENABLE T, COUNT

TRIGGER INPUT = 11
(RETRIGGERABLE)

R242 Tl
Counter Timer 1 Register
(F2H; Read/Write)

1 = To MODULO-N

RESERVED

0
NO FUNCTION
1 '" LOAD T,
0 -= DISABLE Tl COUNT

R~~~~8~:~~:~~) = 10

COUNTMODE
o = To SINGLE·PASS

R246 P2M
Port 2 Mode Register
(F6H ; Write Only)

P2 0-P2 7 I/O DEFINITION
' - - - - - 0 DEFINES BIT AS OUTPUT
1 DEFINES BIT AS INPUT

T, INITIAL VALUE (WHEN WRITTEN)
L----(RANGE 1-256 DECIMAL 01-00 HEX)
T1 CURRENT VALUE (WHEN READ)

R243 PREI
Prescaler 1 Register
(F3H; Write Only)

R247 P3M
Port 3 Mode Register
(F7H; Write Only)

I~I~I~I~I~I~I~I~I

I~I~I~I~I~I~I~I~I

~L

COUNTMOOE
o '"

T, SINGLE·PASS
1 = T, MODULO·N

CLOCK SOURCE
1 == T, INTERNAL
= T, EXTERNAL TIMING INPUT
(TIN) MODE

o

[gE

LO

PORT 2 PULL·UPS OPEN DRAIN
1 PORT 2 PULL·UPS ACTIVE
RESERVED

o P32 = INPUT
P35 = OUTPUT
1 P32 = DAVOIRDYO P35 = RDYOIDAVO

00 P33 = INPUT

~ ~} P33

P34 = OUTPUT

P34 = 15M
1 1 P33 = DAV1/RDY1 P34 = RDY11DAV1

PRESCALER MODULO
(RANGE 1-64 DECIMAL
01-00 HEX)

= INPUT

o P31 = INPUT (fIN) P36 = OUTPUT (TOUT)
1 P31 = DAV2IRDY2 P36 = RDY2IDAV2
'--------

'-________

~ ~~ ~ ~N~~rL IN ~~~ ~ ~~J~~TOUT
~ ~~~:~~ g~F

Figure 14. Control Registers

458

2037-014

Registers

8252 FLAGS

R248 POIM
Port 0 and I Mode Register
(F8H; Write Only)

(Continued)

Flag Register
(FCH; Read/Write)

10,10,10,10.10,10,10,10,1
~

PD,-PO, MODE:]

OUTPUT:: 00

INPUT", 01
A12-A15 ", 1X
EXTERNAL MEMORY TIMING
NORMAL = 0
EXTENDED = 1

~

~
L P",-PO,MODE
00 = OUTPUT
=

01

ll!~~
1

1X = As-Au
STACK SELECTION
= EXTERNAL
1
INTERNAL

o

LUSERFLAG.,

LUSER FLAG F2

INPUT

=

HALF CARRY FLAG
DECIMAL ADJUST FLAG
OVERFLOW FLAG
SIGN FLAG

P1 o-P1 7 MODE
00 '" BYTE OUTPUT
01
BYTE INPUT

ZERO FLAG

=

10'" ADo-AD7

11

c:

CARRY FLAG

HIGH·IMPEDANCE ADo-AD7.

AS, OS, RM, Aa-Al1, A12-A15

IF SELECTED

R2S3 RP
Register Pointer
(FDH; Read/Write)

R2491PR
Interrupt Priority Register
(F9H; Write Only)

E
......

I~I~I~I~I~I~I~I~I

I I II [.-.......-

"~,.~

C > A > B '" 001
A > 8 > C = 010
A> C > B = 011

~

LOON'TCARE

RESERVED "" 000

IRQ3, IROS PRIORITY (GROUP A)
o =: IRQS > IRQ3
1 = IRC3 > IRQS

REGISTER
POINTER

D

B> C > A = 100

C > B > A = 101
B > A > C = 110
RESERVED"" 111

IROO, IRQ2 PRIORITY (GROUP 8)
0", IRQ2 > IROO
1 =: tRoo > IRQ2
IRQ1, IR04 PRIORITY (GROUP C)
o = IR01 > IRQ4
1
IRQ4 > IR01

=

R2S0 IRQ
Interrupt Request Register
(FAH; Read/Write)

R2S4 SPH
Stack Pointer
(FEH ; Read/Write)
I~I~I~I~I~I~I~I~I

1~1~1~1~1~1~I~t~1
RESERVED:::r-

c=

IROO
IRQ1
IRQ2
IR03
lRQ4
IRDS

P32 INPUT (00 '" IROO)
P331NPUT
P3l INPUT
P30 INPUT, SERIAL INPUT
To, SERIAL OUTPUT

T,

R2SIIMR
Interrupt Mask Register
(FBH; Read/Write)

R2SS SPL
Stack Pointer
(FFH; Read/Write)

I~I~I~I~I~I~I~I~I

l~t~t~I~I~I~t~I~1

II

c=

1 ENABLES IRQO-IRQ5
IRQO)
(00

=

'-------RESERVED

LI_ _ _ _

~~~~~s~~~~~~R

LOWER

' - - - - - - - - - 1 ENABLES INTERRUPTS

Figure 14. Control Registers

459

Opcode

Lower Nibble (Hex)

Map

o

o

2

3

4

5

6

-=
!!l.

:a
i
Ii;
'"'"
::>

6,5
DEC
R.
6,5
RLC
R.
6,5
INC
R.
8,0
JP
IRR.
8,5
OA
R.
10,5
POP
R.
6,5
COM
R.

2

3

6,5
ADD

ADC

6,5
ADD
n,1r2
6,5
ADC

II, [2

II,Iu

6,5
SUB

6,5
SUB

II, f2

l1,It2

6,5
SBC

6,5
SBC

II, f2

Il,lrz

6,5
OR

6,5
OR

II, f2

Il,Ir2

6,5
AND

6,5
AND

Il,12

Il,Ir2

6,5
TCM

6,5
TCM

11,Ia

Il,IrZ

6,5
TM

6,5
TM

Il,12

ll,It2

12,0
LOE

18,0
LOEI

Il,Irr2

Irl,lrl2

12,0
LOE

18,0
LOEI

6,5
DEC
IR.
6,5
RLC
IR.
6,5
INC
IR.
6,1
SRP
1M
8,5
OA
IR.
10,5
POP
IR.
6,5
COM
IR.

II, f2

6,5

10/12,1 12/14,1

7

8

9

A

B

C

0

E
F

Bytes per
Instruction

PUSH PUSH
IR2
R2
10,5
10,5
OECW OECW
RR.
IR.
6,5
RL
R.

6,5
RL
JR.

l2,

10,5
10,5
INCW INCW
RR.
JR.
6,5
6,5
CLR
CLR
R.
IR.
6,5
RRC
R.
6,5
SRA
R.
6,5

6,5
RRC
IR.
6,5
SRA
IR.
6,5
RR
RR
IR.
R.
8,5
8,5
SWAP SWAP
IR.
R.

"-

5

6

7

8

9

A

B

C

10,5
ADD
R.,IM

10,5
ADD
IR., 1M
10,5
ADC
IR.,IM

6,5
LO
n,Rz

6,5
LO

12/10,5

12110,0
IR

6,5
LO

cc,RA

n,lM

10,5
SBC
R2,R.
10,5
OR
R2,R.

10,5
ADD
IR2,R.
10,5
ADC
IR2,R.
10,5
SUB
IR2,R.
10,5
SBC
IR2,R.
10,5
OR
IR2,R.

10,5
AND
R2,R.
10,5
TCM
R2,R.
10,5
TM
R2,R.

10,5
AND
IR2,R.
10,5
TCM
IR2,R.
10,5
TM
JR2,R.

10,5
ADD
R2,R.
10,5
ADC
R2,R.
10,5
SUB
R2,R.

10,5
ADC
R.,lM
10,5
SUB
R.,IM
10,5
SBC
R.,IM

l2,R1

OINZ
",RA

o
12/10,0

IP
cc,DA

E
6,5
INC

"

10,5
OR
R.,lM
10,5
AND
R.,IM

10,5
AND
IR.,IM

10,5
TCM
R.,lM
10,5
TM
R.,IM

10,5
TCM
IR.,IM
10,5
TM
IR.,IM

-

r-6,1
01

r-6,1

EI

Irn Ir2,Irr!

6,5
CP

6,5
CP

II, f2

Il,Ir2

6,5
XOR

6,5
XOR

n,rz

n,Irz

10,5
CP
R2,R.

10,5
CP
IR2,R.

10,5
CP
R.,IM

10,5
CP
IR.,IM

10,5
XOR
R2,R.

10,5
XOR
IR2,R.

10,5
XOR
R.,IM

10,5
XOR
IR.,IM
10,5
LO

12,0
18,0
LOC
LOCI
II, Irra hI. !rIZ
12,0
18,0
20,0
LOC
LOCI CALL*
l2, lUI Irz. hI 1
IRR.
6,5
10,5
10,5
LO
LO
LO
II, Irz
R2,Rl IR2,R.
6,5
10,5
LO
LO
hI, [2
R2,IR.

V'

.,

2

""

n,

20,0
CALL
DA
10,5
LO
R.,IM

V'
3

X,

r-14,0
RET

r----16,0
IRET

r----6,5
RCF

Hz

r--

10,5
LO

6,5
SCF

12, x, HI

r--

10,5
LO
IR.,IM

6,5
CCF

r----6,0
NOP

~

"-'---------~~~---------'# ~ ~
2

3

Lower
Opcode
Nibble
Execution
Cycles
Upper
Opcode-A
Nibble

•

Pipeline
Cycles

Mnemonic

Legend:
R = 8-B.I Address
r = 4-B.I Address
Rl or fl
Rl or I.

=
=

Dst Address
Src Address

Sequence:
First
Operand

Second
Operand

*2-byte Instruction; fetch cycle appears as a 3-byte instruction

460

-

10,5
SUB
IR.,IM
10,5
SBC
IR., 1M
10,5
OR
IR., 1M

F

Opcode, F.rst Operand, Second Operand
Note: The blank areas are not defmed.

Absolute
Maximum
Ratings

Voltages on all pins
with respect to GND .......... -0.3 V to + 7.0 V
Operating Ambient
Temperature ........ See Ordering Information

Stresses greater than those hsted under Absolute MaxImum Rahngs may cause permanent damage to the devIce.
ThIs IS a stress rdhng only; operation of the deVIce at any

condItIon above those mdicated In the operatIonal sectIons
of these speCIfIcatIons IS not ImplIed. Exposure to absolute
maXImum ratIng condItIons for extended perIods may affect

Storage Temperature ........ -65°C to + 150°C

Standard
Test
Conditions

deVIce rehablllty,

D +4.75 V!> Vee!> +5.25 V

The characteristics below apply for the
following standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the reference
pin. Standard conditions are as follows:

D

GND

D

aoc

=0V

!> TA !> +70°C'

* See Ordering Informahon section for package

temperature range and product number.
+5V

+SV

21K

+SV

+SV

18K

15k
74LS04

15k
74l.S04

I

CL "" 15pF MAX

' - - - - - - . - - XTAl1

1

Cl "" 15pF MAX

Figure 15. Test Load 1

DC
Characteristics

Symbol

Figure 17. External Clock Interlace Circuit

Parameter

Min

Max

Unit

VeH

Clock Input High Voltage

3.8

Vcc

V

Driven by External Clock Generator

VeL

Clock Input Low Voltage

-0.3

0.8

V

Dnven by External Clock Generator

VIH

Input High Voltage

2.0

Vec

V

VIL

Input Low Voltage

-0.3

0.8

V

VRH

Reset Input High Voltage

3.8

Vcc

V

VRL

Reset Input Low Voltage

-0.3

0.8

V

VOH

Output High Voltage

VOL.

Output Low Voltage

IlL

Input Leakage

IOL

Output Leakage

IIR

2.4

Condition

V

IoH = -250 p.A

0.4

V

IoL= +2.0 rnA

-10

10

p.A

-10

10

p.A

o V,;;
o V,;;

Reset Input Current

-50

p.A

Vee = +5.25 V, VRL = 0 V

Icc

Vec Supply Current

180

rnA

IMM

VMM Supply Current

10

rnA

VMM
1

80BS

Figure 16. Test Load 2

For

0313. 0312 2037·015

Backup Supply Voltage
AO-A]j. MDS, SYNC, SCLK and lACK

Vcc

V

Z8612 verSIOn, 10H

~

3
on the

VIN

,;;

+5.25 V

VIN

,;;

+5.25 V

Notes

Power Down Mode
Power Down
-100

p.A and

IOL

~

1.0 rnA.

461

I........

§

B

Externall/0
or Memory
Read and
Write Timing

Number

Symbol

Parameter

Min

Max

TdA(AS)
Address Valid to Address Strobe Delay
I
50
TdAS(A)
2
Address Strobe to Address Float Delay
70
TdAS(DI)
Address Strobe to Data In Valid Delay
3
4
TwAS
Address Strobe Width
80
5 - - TdA(DS)-Address Float to Data Strobe Delay - - - 0
Data Strobe Width Read
250
6a
TwDS
6b
TwDS
Data Strobe Width Write
160
TdDS(DI)
Data Strobe to Data In Valid Delay
7
ThDS(DI)
8
Data In Hold Time
0
80
9 - - TdDS(A) - Data Strobe to Address Change Delay TdDS(AS)
10
Data Strobe to Address Strobe Delay
70
TdR(AS)
II
Read Valid to Address Strobe Delay
50
TdDS(R)
12
Data Strobe to Read Change Delay
60
TdDO(DS) Data Out Valid to Data Strobe Delay
13
50
14 - - TdDS(DO) - Data Strobe to Data Out Change Delay TdW(AS)
15
Write Valid t6 Address Strobe Delay
TdDS(W)
16
Data Strobe to Write Change Delay

Unit

Notest

360

ns
1,2
1,2
ns
1,4
ns
1,2
ns
ns--- 1 - -

200

ns
1,3
1,3
ns
1,4
ns
ns
ns---1,2-ns

1,2

1,2
ns
1,2
ns
1,2
ns
ns---1,2--

80
50
60

ns
ns

1,2
1,2

NOTES:

t All umts In nanoseconds (ns).

4. Address Strobe and Data Strobe to Data In Valid delay hmes
represent memory system access hmes and are given for an 8
MHz crystal mput frequency. For lower frequenCIes; the change
In four clock perIods must be added to TdAS(DI) and the
change In three clock perIods added to TdDS(DI).

1. Test Load 1.
2. Delay hmes gIven are for an 8 MHz crystal mput
frequency. For lower frequencies, the change In clock
perIod must be added to the delay bme.
3. Data Strobe Width IS gIven for an 8 MHz crystal mput
frequency. For lower frequencIes the change In three
clock periods must be added to obtam the IDlnlIDUm
Width. The Data Strobe Width varies accordmg to the
mstructIon bemg executed.

PORT~

DM

PORT 1

~
~

5. All hmmg references assume 2.0 V for a logiC "I" and
o 8 V for a lOgIC "0,"

As-Au OR Aa-A15

I-

0

~

Ao-A,

Ii
1------0---+

0--

1

~

\

.

0

c=
c=

~
.,
}

OUT

01-

1-

'\

-----

'\

DAY
INPUT

-- 01-

1

RDY
OUTPUT

K.

1~I

1
t

PORT

READ

Input Handshake

DATA OUT

DiY
OUTPUT

RDY
INPUT

Output Handshake

Z8612. Z8613
Memory Port
Timing

Number

2

Symbol

Parameter

TdA(DI)

Address Vahd to Data In
Vahd Delay Time

ThDI(A)

Data in Hold TIme

Min

a

Max

Unit

460

ns

Notes

ns

NOTES.

1 Test Load 2
2 Delay hmes are speCIfIed for an mput clock frequency of 8 MHz
3. All hmmg references assume 2 0 V for a lOgIC" I" and 0.8 V for a lOgIC "0"

ADDRESS VALID

CD
DO-D7

464

DON'T CARE

DATA IN VALID

2037-018.019

Ordering
Information

Product
Number

Packagel
Temp
Speed

Description

Z8611

CE

8.0 MHz

Z8MCU
(4K ROM, 40-pin)
Same as above

Product
Number

Packagel
Temp
Speed

Z8612

OE

8.0 MHz

Description
Z8MCU
(4K XROM,
64-pin)

Z8611

CS

8.0 MHz

Z8611

DE

8.0 MHz

Same as above

Z8612

OS

8.0 MHz

Same as above

Z8611

OS

8.0 MHz

Same as above

Z8613

RS

8.0 MHz

Z8MCU
(4K XROM,
Prototype Device,
40-pin)

Z8611

PE

8.0 MHz

Same as above

Z8611

PS

8.0 MHz

Same as above

NOTES: C

= Ceramic, D = Cerdlp, P = Plastic.

Q

= QUIP. R = Protopack;

E

= -40°C to

+85°C. S

= O°C to

+70°C.

I......

3

I

00·2038·02

465

Z8® Family
Z8671 Microcomputer
BASIC/Debug Interpreter

~
Zilog

Product
Brief

June 1982

Features

Description

• The Z8671 MCU IS a complete mICrocomputer preprogrammed with a BASIC/
Debug interpreter. Interachon between the
mterpreter and its user IS proVided through
an on-board UART.

• The BASIC/Debug mterpreter can call
machine language subrouhnes to increase
execution speed.
• The Z8671's auto start-up capability allows a
program to be executed on power-up or
Reset without operator intervention.

• BASIC/Debug can directly address the
Z8671's internal registers and all external
memory. It provides quick exammahon and
modihcation of any external memory location or I/O port.

• Smgle + 5 V power supply-all pms TTLcompatible.

The Z8671 Single-Chip MICrocomputer
(MCU) is one of a line of preprogrammed
chlps-m thiS case with a BASIC/Debug interpreter in ROM-offered by Zilog. As a member
of the Z8 Family of microcomputers, it offers
the same abundance of resources as the other
Z8 microcomputers.
Because the BASIC/Debug interpreter is
already part of the chip circuit, programming
is made much easier. The Z8671 MCU thus
offers a combination of software and hardware
that is Ideal for most mdustrial control apph-

cations. The Z8671 MCU allows fast hardware
tests, and blt-by-bit exammation and modlhcahon of any memory locahon, I/O port, or
register. It also allows bit manipulation and
logical operations. A self-contained line editor
supports interactive debugging, further
speeding up program development.
The BASIC/Debug interpreter, a subset of
Dartmouth BASIC, operates with two kinds of
memory: on-chip registers and external ROM
or RAM. The BASIC/Debug interpreter is
located in the 2K bytes of on-chip ROM.

+5V
XTAL2

PORTO
(NIBBLE
PROGRAMMABLE)
I/O or Aa-A15

PORT 3
(FOUR INPUT,
FOUR OUTPUT)

PORT 1

SERIAL AND
PARALLEL 1/0

1/0 OR ADo-AD?

AND CONTROL

Figure 1. Pin Functions
2150·001, 002

P3,
P3,

XTAL1

P2,

P3,

P2,

P"

P2,

REm
R/iN

P2,
P2,

os

P2,

AS

P2,

P3,

P2,

OND

P3,

P3,

P3,

po,
po,
po,
po,
po,
po,
po,
po,

AD,
AD,
AD,
AD,
AD,
AD,
AD,
ADo

Figure 2. Pin Assignments

467

Description
(Continued)

Additional features of the Z8671 MCU
include the ability to call machine language
subroutines to increase execution speed and
the ability to have a program be executed
on power-up or Reset, without operator
intervention.
Maximum memory management capabilities
include 62K bytes of external program memory

and 62K bytes' of data memory with program
storage beginning at location 800 hex. This
provides up to 124K bytes of useable memory
space. Very few 8-bit microcomputers can
directly access this amount of memory.
Each Z8671 Microcomputer has 24 I/O lines,
a 144-byte register file, an on-board UART,
and two counter/timers.

Language
Capabilities

The following listing represents all the
expressions, operators, functions, and
statements that can be used with the
BASIC/Debug interpreter.

USR (a,b,c)

expressIOns a,b.

Expressions:
Variable Names A-Z
Signed decimal numbers m the range -32768
to +32767

Statements:
GO@

Branches to an assembly
language routme. ThIS statement
IS SImIlar to USR except no
value IS returned by the
assembly language routme.

GOSUB

Calls a subroutme at Ime
number.

less than

GOTO

Branches to a Ime number.

not equal

IF/THEN

Used for conditIonal operatIons
and branches.

INPUT

Inputs expressIOns separated by
commas.

IN

Same as INPUT except values
remammg m the mput buffer
are used first, then new data IS
requested.

LET

ASSIgns the value of an expression to a vanable or memory
locatIon.

Hexadecimal numbers (preceded by "%") in
the range 0 to 65535

Operators:
Relational Operators:
equal

<=
<
<>
>
>=

less than or equal

grea ter than
greater than or equal

ArithmetIc Operators:
+

addition
subtraction

*

multiphcation

/

divIsIOn

\

unsIgned divISIon

Memory Operators:
@

LIST

Lists the current program.

Any byte may be referenced by
placing the byte sIgnal character "@"
in front of the address. For example,
LET X = @ % 1000 assIgns the
value at address %1000 to X.
LET @ (C* 100) = A assigns the value
of A to the byte at address (C* 100).

NEW

Estabhshes a new start-ofprogram address.

PRINT

LISts ItS arguments, whIch may
be text messages or numencal
values, on the output termmal.

REM

Used to msert comments.

Sixteen-bit words may be
referenced with an address preceded
by the word signal character "1". For
example, PRINT 118 WIll print the
sixteen-bIt value pomted to by the contents of the word at location 8.

RETURN

Returns control to Ime followmg
GOSUB statement.

RUN

ImtIates sequenhal execuhon of
all mstructIons m current program.

STOP

Gracefully ends program
execuhon.

Functions:
AND (a,b)

468

Calls an assembly language
routine at address a. The expreSSIOns b,c may be used to
pass arguments to the routme.
The assembly language rout me
must return a value.

Performs a logIcal AND of the

00-2150-01

Z8® Family
Z8681 Microcomputer

~
Zilog

Product
Brief

June 1982

Features

• "ROMless" version of the Z8601 single-chip
microcomputer, capable of addressing up to
128K bytes of external memory space.

• Up to 24 programmable I/O lines .

General
Description

The Z8681 MeU is the "ROM less" version of
the Z8601 single-chip microcomputer and
offers all the outstanding features of the Z8
Family architecture. Usmg the Z868 1, it is
possible to design a powerful microprocessor
system incorporating a minimum number of
support devices.
Port 1 is configured to function as a multiplexed Address/Data bus (ADo-AD7), while
Port 0 is software configurable to output
address bits As-AIS' This provides for program

memory and data memory space of up to 64K
bytes each.
Located on-chip are 144 bytes of RAM,
organized as a register file of 124 generalpurpose registers, 16 control and status
registers, and three I/O port registers. (Port 1
cannot be utilized as an I/O register.) This file
is divided into groups of working registers in
such a way that short format instructions may
be used to qUickly access a register within a
certain group.

Functional
Description

Register File. The internal register orgamzation of the Z8681 centers around a 144-byte
random-access register file composed of 124
general-purpose registers, 16 control registers,
and the three I/O port registers. Any generalpurpose register can be an accumulator,
address pointer, mdex register, or part of the
internal stack. The register hIe is dIvided into
nine groups of 16 working regIsters. A register
pointer uses short-format instructions to

quickly access anyone of the nine groups,
resulting in fast and easy task-switching.

PORT 0
(NIBBLE
PROGRAMMABLE)
Ae-A'5

PORT 2
(BIT PRO·
GRAMMABLE)
1'0

PORT 3
(FOUR INPUT,
FOUR OUTPUT)

PORT 1
(BYTE
PROGRAMMABLE)
110 OR ADo-ADI

SERIAL AND
PARALLEL 110

AND CONTROL

Figure 1. Pin Functions
2114011111. 1102

I...

• 40-pin package, single + 5 V supply, all
pins TTL compatible.

I/O Ports. The I/O ports (Ports 0, 2, and 3)
are software conhgurable as mput, output, or
additional address lines. These ports can also
prOVIde timing, status SIgnals, and serial or
parallel I/O (WIth or without handshake).
I/O port space is mapped into the register
file, creating an efficient and convenient
means of movmg data.
+sv

P3.

XTAL2

P3,

XTAL1

P2,

P3,

P2.

P3"

P2,

~

P2.

RfW

P2,

os

P2,

AS

P2,

P3,

P2,

GND

P3,

P3,

P3.

po,
po,
po,
po,
po.
po,
po.
po,

P',

p'.
P',

p'.
P',
P1,
P1,
P1,

Figure 2. Pin Assignments

469

I

Functional
Description
(Continued)

Instruction
Set for the

Z8681

Z8681
Applications

Interrupts. The Z8681 can respond to six
separate interrupts from eight sources. The
interrupts are maskable and prioritized by software control, thus allowing greater design
flexibility.
Using vectored interrupts, control is automatically passed to the appropriate service
routine. The interrupts are organized as four
external lines and four internal status signals.
The internal interrupts control the serial port
handshake and the two counter/timers.
UART. The Z8681 also offers the serial I/O
capability of interfacing to asynchronous data
communications. The on-chip counter (TO) is

Counter/Timers. Also on-chip are two 8-bit
programmable counter/timers (TO and Ill.
each driven by its own 6-bit programmable
prescaler. Both counter/timers can operate
independently of the processor instruction
sequence, thereby unburdening the program
from such time-critical operations as eventcounting or elapsed-time calculations. The
counters can be started, stopped, continued,
or restarted from the initial value by program
control.

The basic instruction set for the Z8681 consists of 47 instruction types and utilizes seven
addressing modes. The instructions can
operate on several types of data elements,
including individual bits, 4-bit BCD
characters, bytes, or words.
All 124 general-purpose registers can be

used as accumulators, address pointers, index
registers, or as internal stack, resulting in fast
data manipulation for real-time applications.
The internal pipelining of instructions
dramatically increases throughput by allowing
instruction fetches during the previous instruction execution cycles.

The Z8681 is a Z-BUS-compatible device and
can be interfaced to various Z-BUS peripherals
such as the Z-CIO, Z-SCC, or FlO. Due to the
flexibility of Port 0 and the data memory select

feature, the Z8681 can also support a great
variety of memory configurations. Figures 3
and 4 illustrate two design approaches using
the Z8681.

used to supply- the baud rate for the serial data
transfer. The UART is capable of transferring
data at a rate of up to 62.5K b/s.

Z·BUS

,(.

(

PORT 2

<8>
~

15110
LINES

(

A

•
Z8881

PORT 3

<3>
~

PORT 3

.,

t.

~

<4>

y

.,
.,

A

ADo~AD1

<8>
~

Aa-A15

t.

•

64K
DATA
MEMORY

64K
PROGRAM
MEMORY

<8>

OM

Figure 3. Z8681 Interlacing to External Memory

470

2040-003

Z8681

Z·BUS
Z·BUS COMPATIBLE
PERIPHERAL CHIP

Applications
(Continued)

Z·UPC
Z·CIO
FlO

z·sec
CRT

DMA

Z8881

64K
DATA
MEMORY

a

64K

r:"'"

PROGRAM
MEMORY

II

a
SERIAL IN
SERIAL OUT

Figure 4. Z868 I Interfacing to Memory·Mapped 1/0
Ordering
Information

Product
Number

Description

28681

CE

8.0 MHz

28MCU
(ROMless, 40-pm)

28681

CS

8.0 MHz

28681

DE

8.0 MHz

NOTES' C

2040·004 00·2040·A

Package/
Temp
Speed

:=

CeramlC, D

=

Product
Number

Package/
Speed
Temp

Description

28681

DS

8.0 MHz

Same as above

28681

PE

8.0 MHz

Same as above

Same as above

28681

PS

8.0 MHz

Same as above

Cercilp, P = Plastic, E

=

-40°C to +85°C, S =

aoe to

28MCU
(ROMless, 40-pin)

+70°C.

471

Additional Information

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

Z·BUS®
Componenl Inlerconnecl

~
Zilog

Summary

June 1982

Features

General
Description

• Mulhplexed address/data bus shared by
memory and I/O transfers.

• Direct addressmg of registers within a
penpheral facllitates I/O programmmg.

• 16 or more memory address bits; 16-bit I/O
addresses; 8 or 16 data bits.

• Bus signals allow asynchronous CPU and
penpheral clocks.

• Supports polling and vectored or nonvectored interrupts.

• Daisy-chain bus-request structure supports
dlstnbuted control of the bus.

• Daisy-chain mterrupt structure services
interrupts without a separate pnority
controller.

• Shared resources can be managed by a
general-purpose, distributed resourcerequest mechanism.

The Z-BUS is a high-speed parallel shared
bus that links components of the Z8000 Family.
It provides family members with a common
communication interface that supports the
following kinds of interactions:

------PRIMARy SIQNALS------

<

• Data Transfer. Data can be moved between
bus controllers (such as a CPU) and memories or peripherals.
• Interrupts. Interrupts can be generated by
peripherals and serviced by CPUs over
the bus.

AD,-AD"

STATUS

BUS
MASTER

--As:----...
--05---.
- - R/IN------..
--s{Yi ------.

PERIPHERAL
AND MEMORY

~WAIT--

• Resource Control. Distributed management
of shared resources (including the bus itself)
is supported by a daisy-chain priority
mechanism.
The heart of the Z-BUS is a set of multiplexed address/data lines and the signals that
control these lines. Multiplexing data and
addresses onto the same lines makes more efficient use of pins and facilitates expansion of
the number of data and address bits. Multiplexing also allows straightforward addressing
of a peripheral's internal registers, which
greatly simplifies I/O programming.
A daisy-chained priority mechanism resolves
interrupt and resource requests, thus allowing
distributed control of the bus and eliminating
the need for separate priority controllers. The
resource-control daisy chain allows wide
physical separation of components.
The Z-BUS is asynchronous in the sense that
peripherals do not need to be synchromzed
with the CPU clock. All timing information is
prOVided by Z-BUS signals.
20310045

4 - - - - - RESET---+-

- - - - - B U S REQUEST S I Q N A L S - - - - '--BUSREQ----'

CPU

--BUSACK ----+-

REQUESTER

.-----.. BAi----.

L - - BAO - 4 - - - -----INTERRUPT SIQNALS-----

......--iNf--

PERIPHERAL

~IEI---'

L--'EO-4-------RESOURCE REQUEST SIQNALS-----MMRQ-----....

Z·BU$

....--MMST--

COMPONENT

...--MMAI----,

MULTI·MICRO
REQUEST
NETWORK

---+- MMAO-----J

Figure I. Z-BUS Signals

475

Z-BUS

CPUs. A Z-BUS system contains one CPU, and
this CPU has default control of the bus and
typically initiates most bus transactions.
Besides generating bus transactions, it handles
interrupt and bus-control requests. The 28001
Segmented CPU and Z8002 Non-Segmented
CPU are Z-BUS CPUs.
Peripherals. A Z-BUS peripheral is a component capable of responding to I/O transactions and generating interrupt requests. The
Z8036 Counter Input/Output Circuit (Z-CIO),

Z8038 FIFO Input/Output, Interface Unit
(Z-FlO), the Z8030 Serial Communication
Controller (Z-SCC), the Z8090 Universal
Peripheral Controller (Z-UPC), and the
Z8052 CRT Controller (Z-CRT) are all
Z-BUS peripherals.
Requesters. A Z-BUS requester is any component capable of requesting control of the
bus and initiating transactions on the bus. A
Z-BUS requester is usually also a peripheral.
The Z8016 DMA Transfer Controller (Z-DTC) is
a Z-BUS requester and a peripheral.
Memories. A Z-BUS memory is one that interfaces directly to the Z-BUS and is capable of
fetching and storing data in response to Z-BUS
memory transactions. The Z6132 Quasi-Static
RAM is a Z-BUS memory.

Other
Components

The Z8 Microcomputer-in its microprocessor configuration-conforms to Z-BUS
timing (which allows it to use Z-BUS
peripherals and memories), but is missing a
wait input and certain status outputs.
The za010 Memory Management Unit
(Z-MMU) is a Z8000 CPU support component
that interfaces with part of the Z-BUS on the
CPU side and provides demultiplexed

addresses on the memory side.
The za060 First-In-First-Out Buffer (Z-FIFO)
is not a Z-BUS component; rather, it is used to
expand the buffer depth of the Z-FIO or to
interface the I/O ports of the Z-UPC, Z-CIO,
or Z-FIO to user equipment.
Z-80 Family components, while not
Z-BUS compatible, are easily interfaced to
Z-BUS CPUs.

Operation

Two kinds of operations can occur on the
Z-BUS: transactions and requests. At any given
time, one device (either the CPU or a bus
requester) has control of the Z-BUS and is
known as the bus master. A transaction is
initiated by a bus master and is responded to
by some other device on the bus. Four kinds of
transactions ~ccur in Z-BUS systems:

at a time, and it must be mitiated by the bus
master. A request, however, may be initiated by a component that does not have control of the bus. There are three kinds of
requests:

Components

A Z-BUS component is one that uses Z-BUS
signals and protocols, and meets the specified
ac and dc characteristics. Most components in
the 28000 Family are Z-BUS components. The
four categories of Z-BUS components are as
follows:

• Memory. Transfers 8 or 16 bits of data to or
from a memory loc;:ation.
• I/O. Transfers 8 or 16 bits of data to or from
a peripheral.
• Interrupt Acknowledge. Acknowledges
an interrupt and transfers an identification/status vector from the interrupting
peripheral.
• Null. Does not transfer data. Typically used
for refreshing memory.
Only one transaction can proceed on the bus

476

• Interrupt. Requests the attention of the
Z-BUS CPU.
• Bus. Requests control of the Z-BUS to initia te transactions.
• Resource. Requests control of a particular
resource.
When a request is made, it is answered
according to its type: for interrupt requests an
interrupt-acknowledge transaction is initiated;
for bus and resource requests an acknowledge
signal is sent. In all cases a daisy-chain priority mechanism prOVides arbitration between
simultaneous requests.

Signal
Lines

The Z-BUS consists of a set of common signal
Imes that interconnect bus components (Figure
1). The signals on these Imes can be grouped
mto four catagones, depending on how they
are used m transachons and requests.

Primary Signals. These signals provide
hmmg, control, and data transfer for Z-BUS
transachons.

ADo-AD1S. Address/Data (active High). These
mulhplexed data and address Imes carry 110
addresses, memory addresses, and data during
Z-BUS transactions. A Z-BUS may have 8 or 16
bits of data dependmg on the type of CPU. In
the case of an 8-blt Z-BUS, data is transferred
on ADo-AD7.
Extended Address. (active High). These
Imes extend ADo-ADI5 to support memory
addresses greater than 16 bits. The number of
Imes and the type of address mformahon
carned IS dependent on the CPU.
Status. (active High). These Imes deSignate
the kmd of transachon occurrmg on the bus
and certam addlhonal mformatlOn about the
transachon (such as program or data memory
access or System versus Normal Mode).
AS. Address Strobe (active Low). The nsing
edge of AS mdlcates the begmnmg of a transachon and that the Address, Status, R/W, and
B/W signals are valid.
DS. Data Strobe (active Low). DS provides
hmmg for data movement to or from the bus
master.
R/W. Read/Write (Low = write). This signal
determmes the duechon of data transfer for
memory or I/O transachons.

B/W. Byte/Word (Low = word). This signal
mdicates whether a byte or word of data is to
be transmitted on a 16-blt bus. This signal IS
not present on an 8-bit bus.
WAIT. (active Low). A Low on this Ime mdicates that the responding deVice needs more
time to complete a transaction.
RESET. (active Low). A Low on this Ime resets
the CPU and bus users. Penpherals may be
reset by
RESET or by holding AS and DS Low
simultaneously.
CS. Chip Select (active Low). Each peripheral
or memory component has a CS Ime that is
decoded from the address and status Imes. A
Low on this line mdICates that the penpheral
or memory component IS bemg addressed by a
transachon. The Chip Select mformahon is
latched on the nsmg edge of AS.
Bus Request Signals. These signals make
bus requests and establish which component
should obtam control of the bus.

BUSREQ. Bus Request (active Low). This line
IS dnven by all bus requesters. A Low mdlcates that a bus requester has or IS trymg to
obtam control of the bus.
BUSACK. Bus Acknowledge (active Low). A
Low on this Ime mdlcates that the Z-BUS CPU
has relmqUlshed control of the bus m response
to a bus request.
BAI, BAa. Bus Acknowledge In, Bus
Acknowledge Out (active Low). These signals
form the bus-request dmsy cham.

477

Z·BUS
Connections

Signal

CPU

Requester

Peripheral

Memory

ADo-AD1S

Bidirectional2
3-state

B,directional2
3-state

BldlrectionaJl
3-state

Bldirecnonal2
3-state

Extended
AddressB

Output
3-state

Output
3-state

0

Input

Status

Output
3-state

Output
3-state

InputJO

0

RM

Output
3-state

Output
3-state

Input

Input

BM9

Output

Output

Input:3

Input--

Input

Input

OutputS
Open Drain

Outputs
Open Drain

AS

Output
3-state

Output
3-state

Input

Input

DS

Output
3-state

Output
3-state

Input

Input
Input

WAIT

CS4

0

0

Input

RESET

Input

Inputl3

Inputs

BUSREQ

Input

Bidirectional
Open Drain

0

0

BUSACK

0

Output

0

0

BAfl

0

Input

0

0

BA07

0

Output

0

0--

Input

0

Output
Open Drain

0

INTACK6

0

0

Inputll

0

IEI7

0

0

Input

0

IE07

0

Output

0

MMRQ12

0
Outllut
Open Drain

MMST12

Input

INT

478

0--

MMA17,12

Input

MMA07,12

Output

I.
2.
3.
4.

Only ADo-AD],ljnless peripheral IS 16-Blt.
For an S-blt bus, only ADo-ADz are b,dlrecllonal.
Only for a 16-bit peripheral.
Derived Signal, one for each peripheral or memory; decoded
from status and address hnes.
5. Opllonal-perlpherals are typically reset by AS and iSS being
Low simultaneously, however, they can have a reset input.
6. Derived Signal; decoded from status lines.
7. Dalsy·cham hnes.

S. Opllonal slgnal(s).
9. For 16-blt data bus only.
10. OptIonal-usually only Input on peripherals that are also
requesters.
11. May be onntted If peripheral Inputs status hnes.
12. Ophonal Signal; any component may aUach to the resource
request hnes.
13. Ophonal Signal; a bus requestor may also be reset by AS and
iSS gOing Low and BAI being High Simultaneously.
o No ConnectIon

Table 1. Z·BUS Component Connections to
Signal Lines. This table shows how the
various Z-BUS components attach to each
signal line. When a device is both a bus

requester and a peripheral, the attributes in
both columns of the table should be combined
(e.g., input combined with output and 3-state
becomes bidirectIOnal and 3-state.)

Signal
Lines
(Continued)

Interrupt Signals. These signals are used for
interrupt requests and for determining which
interrupting component is to respond to an
acknowledge. To support more than one type
of interrupt, the lines carrying these signals
can be replicated. (The Z8000 CPU supports
three types of interrupts: non-maskable, vectored, and non-vectored.)
INT. Interrupt (active Low). This signal can
be driven by any peripheral capable of generating an interrupt. A Low on INT indicates that
an interrupt request is being made.

Resource Request Signals. These signals are
used for resource requests. To manage more
than one resource, the lines carrying these
signals can be replicated. (The Z8000 supports
one set of resource request lines.)
MMRQ. Multi-Micro Request (active
Low). This line is driven by any device that
can use the shared resource. A Low indicates
that a request for the resource has been made
or granted.

MMST. Multi-Micro Status (active Low). This

INTACK. Interrupt Acknowledge (active
Low). This signal is decoded from the status

pin allows a device to observe the value of the
MMRQ line. An input pin other than MMRQ
facilitates the use of line drivers for MMRQ.

lines. A Low indicates an interrupt acknowledge transaction is in progress. This signal
is latched by the peripheral on the rising
edge of AS.

MMAI, MMAO. Multi-Micro Acknowledge In,
Multi-Micro Acknowledge Out (active
Low). These lines form the resource-request
daisy chain.

lEI, lEO. Interrupt Enable In, Interrupt Enable
Out (active High). These signals form the
interrupt daisy chain.

Transactions

All transactions start with Address Strobe
being driven Low and then raised High by the
bus master (Figure 2). The Status lines are
valid on the rising edge of Address Strobe and
indicate the type of transactions being initiated. If the transaction requires an address,
it must also be valid on the rising edge
of Address Strobe.
For all transactions except null transactions
(which do nothing beyond this point), data is
then transferred to or from the bus master. The
bus master uses Data Strobe to time the movement of data. For a read (R/W = High), the

)0()(

bus master makes ADo-ADI5 inactive before
driving Data Strobe Low so that the
addressed memory or peripheral can put its
data on the bus. The bus master samples this
data just before raising Data Strobe High. For
a write (R/W = Low), the bus master puts the
data to be written on ADo-ADI5 before forcing
Data Strobe Low.
For an 8-bit Z-BUS, data is transferred on
ADo-AD7' Address bits may remain on
ADs-ADI5 while DS is Low.

)OK

~

CLOCK

~

I

BUS MASTER
SAMPLES WAIT

BUS MASTER

SAMPLES

I

INPUT DATA

STo-STa
AIW,BIW

\

X

ADDRESS FAOM
BUS MASTER

DATA TO
BUS MASTER

\
ADO-AD15

X

--<

\
OAT A FROM BUS MASTER

Figure 2. Typical Transactlon Timing

203J·OJ8J

479

i

Memory
Transactions

For a memory transaction, the Status lines
distinguish among various address spaces,
such as program and data or system and normal, as well as indicating the type of transaction. The memory address is put on
ADo-AD15 and on the extended address lines.
For a Z-BUS with 16-bit data, the .memory is
organized as two banks of eight bits each
(Figure 3). One bank contains all the upper

bytes of all thE! addressable l6-bit words. The
other bank contains all the lower bytes. When
a single byte is written (R/W = Low,
B/W = High), only the bank indicated by
address bit AD is enabled for writing.
For a Z-BUS with 8-bit data, the memory is
organized as one bank which contains all
bytes. This bank always inputs and outputs its
data on ADo-AD7.
1S.BIT Z·SUS DATA PATH

D
D. '"

D,

EXTENDED
ADDRESS

LOWER
BANK

--!:==±=L/----------' ENABLE
Figure 3. Byte/Word Memory Organization

1/0
Transactions

Null
Transactions

480

1/0 transactions are similar to memory
transactions with two important differences.
The first is that 1/0 transactions take an extra
clock cycle to allow for slow peripheral operation. The second is that byte data (indicated
by B/W High on a l6-bit bus) is always trans-

mitted on ADo-AD7, regardless of the 1/0
address. (ADs-ADJ5 contain arbitrary data in
this case.) For an I/O transaction, the address
indicates a peripheral and a particular register
or function within that peripheral.

The two kinds of null transactions are distinguished by the Status lines: internal operation and memory refresh. Both transactions
look like a memory read transaction except
that Data Strobe remains High and no data is
transferred.
For an internal operation transaction, the
Address lines contain arbitrary data when
Address Strobe goes High. This transaction is
initiated to maintain a minimum transaction
rate when a bus master is doing a long internal

operation (to support memories which generate
refresh cycles from Address Strobe).
For a memory refresh transaction, the
Address lines contain a refresh address when
Address Strobe goes High. This transaction is
used to refresh a row of a dynamic memory.
Any memory or I/O transaction can be suppressed (effectively turning it into a null transaction) by keeping Data Strobe High throughout the transaction.

2031·0182

Interrupts

A complete Interrupt cycle consists of an
Interrupt request followed by an Interruptacknowledge transachon. The request, which
consists of INT pulled Low by a peripheral,
notifies the CPU that an Interrupt IS pending.
The interrupt-acknowledge transactIOn, which
is Inihated by the CPU as a result of the
request, performs two funchons: it selects the
peripheral whose Interrupt is to be acknowledged, and it obtains a vector that Identifies
the selected device and cause of Interrupt.
A peripheral can have one or more sources
of interrupt. Each Interrupt source has three
bits that control how It generates Interrupts.
These bits are an Interrupt Pending bit (IP),

and Interrupt Enable bit (IE), and an Interrupt
Under Service bit (IUS).
A peripheral may also have one or more
vectors for identifying the source of an interrupt during an interrupt-acknowledge transaction. Each interrupt source IS associated with
one interrupt vector and each Interrupt vector
can have one or more interrupt sources assocIated with it. Each vector has a Vector Includes
Status bit (VIS) controlling its use.
Finally, each peripheral has three bits for
controlling interrupt behavior for the whole
device. These are a Master Interrupt Enable
bit (MIE), a Disable Lower Chain bit (DLC),
and a No Vector bit (NV).

INTERRUPT

INTERRUPT
VECTOR

VECTOR

II ,~

d·· .~
b=2.I

~r-----J
~~A=Do~-A=D~'________-7,r______~

'EI

HIGHE~~

PRIORI~~
Z-BUS

Z-BUS
PERIPHERAL

PERIPHERAL

+C:fTT't ti

lEO

'NTACK

ADo-AD1

LOWEST

PRIORITY

lEI ADo-AD1 AS

os

tNT

INTACK

Z-BUS
PERIPHERAL
tEt ADo-AD7 AS

lEO

" rrI

~-~llr

AS
Z-BUS

CPU

os
iNf
WAIT

STATUS

AOs-A016

-

===;(

DSOO fNTACR

lEO

t

+f

)

ITATUS
DECODER

rl

~ FROM 1.·.,T PERIPHERAL.
Figure 4. Interrupt Connections

7031 0189

481

Interrupts
(Continued)

482

Penpherals are connected together vIa an
interrupt daisy chain formed with their lEI and
IEO pms (Figure 4). The interrupt sources
wIthin a device are simIlarly connected into
this cham with the overall effect bemg a daisy
chain connecting the mterrupt sources. The
daISY cham has two funchons: durmg an
interrupt-acknowledge transachon, It determmes whIch mterrupt source IS being
acknowledged; at all other hmes it determmes
whICh mterrupt sources can mihate an interrupt request.
FIgure 5 IS a state dIagram for mterrupt
processmg for an mterrupt source (assuming
Its IE bit IS 1). An mterrupt source with an
interrupt pendmg (IP = I) makes an interrupt
request (by pullmg INT Low) If, and only If, It
IS enabled (IE = I, MIE = 1), It does not have
an mterrupt under service (IUS = 0), no
hIgher pnorlty mterrupt is bemg servICed
(IEI = HIgh), and no mterrupt-acknowledge
transachon IS m progress (as mdlcated by
INTACK at the last rlsmg edge of AS). IEO IS
not pulled down by the mterrupt source at thIs
hme; lEO contmues to follow IEI unhl an
mterrupt-acknowledge transachon occurs.
Some hme after INT has been pulled Low,
the CPU mlhates an mterrupt-acknowledge
transachon (mdICated by INTACK Low).
Between the rlsmg edge of AS and the fallmg
edge of DS, the lEI/lEO daISY cham sellles.
Any mterrupt source WIth an mterrupt pendmg
(IP = 1, IE = 1, MIE = 1) or under serVIce
(IUS = I) holds ItS IEO line Low; all other
mterrupt sources make IEO follow IEI. When
DS falls, only the hIghest Priority interrupt
source WIth a pendmg mterrupt (IP = 1) has
Its lEI mput HIgh, ItS IE bIt set to I, and ItS
IUS bIt set to O. ThIS is the mterrupt source
being acknowledged, and at thIS pomt It sets

ItS IUS bit to 1, and, if the peripheral's NV bit
is 0, idenhfies itself by placing the vector on
ADo-AD7. If the NV bIt IS I, then the peripheral's ADo - AD7 pins remain floating, thus
allowmg external cIrcuitry to supply the vector. (All interrupts, includmg the Z8000's nonvectored mterrupt, need a vector for idenhfying the source of an interrupt.) If the vector's
VIS bIt is 1, the vector will also contain status
informahon further Idenhfying the source of
the mterrupt. If the VIS bit IS 0, the vector
held in the peripheral will be output WIthout
modification.
WhIle an mterrupt source has an mterrupt
under serVIce (IUS = 1), it prevents all lower
Priority mterrupt sources from requestmg
mterrupts by forCing IEO Low. When interrupt
servlcmg IS complete, the CPU must reset the
IUS bIt and, m most cases, the IP bit (by
means of an I/O transachon).
A peripheral's Master Interrupt Enable bIt
(MIE) and DIsable Lower Cham bIt (DLC) can
modify the behaVIOr of the peripheral's interrupt sources m the following way: if the MIE
bIt IS 0, the effect IS as If every Interrupt
Enable bIt (IE) m the peripheral were 0; thus
all mterrupts from the peripheral are disabled.
If the DLC bIt is 1, the effect IS to force the
peripheral's lEO output Low, thus dlsablmg all
lower prlonty deVICes from Imhatmg interrupt
requests.
Pollmg can be done by dlsablmg mterrupts
(usmg MIE and DLC) and by readmg peripherals to detect pending mterrupts. Each
Z-BUS peripheral has a smgle dIrectly
addressable regIster that can be read to determme If there IS an mterrupt pendmg m the
device and, If so, what mterrupt source
It IS from.

Interrupts

ANY

ANY

(Continued)
IP

IUS

IE

ITE:EJ

STATEo.D.
HIGH

iNT
IP

IUS

IE

~

STATE'll

,~
<

I

B

IP

IUS

IE

~=
c]1 n
H

HIGH

LOW

LOW

IP

IUS

IE

IP

C£EEI
STATE

aIL

ANY

IP

IUS

IE

CIEEl

•.a

IE

~
<

STATE 4

ANY

LOW

I
G

IP

>

IUS

IE

C!::E:EJ

STA E.

ANY

ANY

ANY

IP

IUS

lEO

CiJ:TI!J

STATE 5

C¢

.

LOW

iNf

lEI

IUS

IE

I§[illJ

c¢

c4

STATE 7

LOW

IP

IUS

IE

~

STATE

c4

8

Figure 5. State Diagram lor an Interrupt Source
Transition Legend

State Legend

lii'The peripheral detects an mterrupt condlhon and sets
~Interrupt Pendmg.

No mterrupts are pendmg or under service for this

perIpheral.

Iii' All hIgher priority peripherals fimsh mterrupt serVIce,

An interrupt

~ thus allowing lEI to go High.

I'(;\. An mterrupt-acknowledge transachon starts, and the

pending, and an mterrupt request has

An mterrupt IS pendmg, but no mterrupt request has
been made because a higher Priority perIpheral has an
mterrupt under serVIce, and this has forced lEI Low.

L::;I' 1EIIIEO daisy cham settles.
@)The interrupt-acknowledge transachon termmates with
the perIpheral selected. Interrupt Under ServICe (IUS)
is set to I, and Interrupt Pendmg (IP) mayor may not
be reset.

An Interrupt-acknowledge sequence IS in progress, and
no hIgher priority perIpheral has a pending mterrupt.

Iii'The mterrupt-acknowledge transaclIon terminates wIth a
t=:.I' higher priority deVIce having been selected.

An interrupt-acknowledge sequence IS In progress, but
higher pnonty penpheral has a pendmg interrupt,
forcmg lEI Low.

IF' The Interrupt Pending bIt m the perIpheral IS reset by

The perIpheral has an Interrupt under service. ServlCe

d

L!:/ an 1/0 operahon.

~ A new mterrupt condition is detected by the peripheral,

~ causmg IP to be set again.

'H' Interrupt servIce is termInated for the peripheral by
~ resetting IUS.

IV IE IS reset to zero, causmg mterrupts to be dIsabled.

IE> IE IS set to one, re-enablmg mterrupts.

1. ThIS dlagram assumes MIE = 1. The effect of MIE = 0 IS the
same as that of settmg IE = O.
2. The DLC bIt does not affect the states of mdividual mterrupt
sources. Its only effect IS on the lEO output of a whole perIpheral.

483

IS

been made by pulling INT Low.

o
[2]
I]]

may be temporarIly suspended (mdlcated by lEI gomg
Low) If a hIgher Priority deVICe generates an mterrupt.
This IS the same as State 5 except that an Interrupt is
also pending In the peripheral.
Interrupts are dIsabled from thIS source because IE

= O.

Interrupts are dIsabled from this source and lower
PrIOrIty sources because IE = 0 and IUS = I.

3. Transltion I to state 6 or 7 can occur from any state except 3 or
4 (whIch only occur durmg mterrupt acknowledge),

4. Translhon J from state 6 or 7 can be to any state except 3 or 4,
dependmg on the value of lEI. lP, and IUS.
2031-0185

Interrupts
(Contmued)

STATE 1

BAIrn
_1
HIGH

,HIGH

BUS REQUESTERS

STATE 2

BAIrn
_2
HIGH

HIGH

STATE 3

u:::~
~
~

BUSREO

_

LOW

LOW

BAIrn
_2
HIGH

HIGH

STATE 4

&Ai
,

BAO

LOW

LOW

STATE 5

:::[fub
~
~

BUSREQ

_

HIGH

HIGH

BAI~
,

U

LOW

STATE 6

8USREQ[fub
~
~U

BUSACK

HIGH

•

LOW

rn

BAI
_8

2

HIGH

LOW

LOW

STATE 7

Figure 6. Bus Request Mechanism States

HIgh, !l may request the bus when Its BAr mput
flses; otherwIse if It wants the bus, It must Walt for
BUSREQ to me.

Bus Requester Legend

'i"Reguester does not want bus and IS not pullmg
L.!./BUSREQ Low.
I2'Requester mayor may not want bus; It IS pullmg
~BUSREQ Low m eIther case.
I3'Requester IS not pullmg BUSREQ Low; it It wants
~control of the bus, It must walt for BUSREQ and
BAr to flse before requestmg the bus.
r:4'Requester is eIther usmg the bus or propagahng
L:!/the Low on ItS BAr input. It will stop driving
BUSREQ when ItS BAO output goes Low. If It
wants to use the bus, but did not want to at the
hme BUSREQ and BAr were last HIgh or BUSREQ
went from Low to HIgh, then It must walt for
BUSREQ and BAr to me before requestmg and
usmg the bus.
I5'Requester IS not pullmg BUSREQ Low. If It wants
~to use the bus, It must wait for ItS BAr to become
HIgh before requesting the bus.
I6'Requester IS propagatmg the High on its BAr
C::/mput. If It wants the bus It WIll pull BUSREQ Low.
'?"Requester is propagatmg the HIgh on ItS BAr
L:../mput.
I8'Requester IS not pulling BUSREQ Low. If it wanted
~he bus at the hme BUSREQ went from Low to

484

Bus State Legend

ill The CPU owns the bus and no one IS requeshng It.

m

A bus requester has requested the bus by pullmg
BUSREQ Low, but the CPU has nor responded.

II] A Low from

the CPU's BUSACK IS propagatmg
down the BAr/BAO daIsy cham. Bus requesters are
using the bus.

8J The Low from BUSACK has propagated to the end
of the daisy cham causmg all bus requesters to
release BUSREQ, which floats High. The CPU has
not yet acknowledged return of the bus.

[§]

The CPU acknowledges the HIgh on BUSREQ with
a High on BUSACK, which has propagated down
the BAIIBAO daisy chain.

[§] Some devICe whose BAi mput IS High requests the
bus by pulling BUSREQ Low. The CPU has not yet
responded with a Low on BUSACK.

ill The CPU has responded to a Low on BUSREQ with
a Low on BUSACK. The prevIOus High state on
BUSACK is shll propagatmg down the BAIIBAO
daIsy cham.

Interrupts

(Contmued)

Transition Legend

A A bus requester requests the bus by pullmg dow"
on BUSREQ.

D The CPU responds to BUSREQ HIgh by dnvmg
BUSACK HIgh.

B The CPU reponds to BUSREQ by pullmg down
BUSACK.

E The HIgh from BUSREQ propagates to the end of
the BAI/BAO dalsy cham.

BtJsAcK

C The Low from
propagates to the end of
the BAI/BAO daisy cham, causmg all the bus reo
questers to let BUSREQ nse.

Bus
Requests

Figure 7 shows how the bus request lines
connect bus requesters and the CPU on a
Z-BUS. Figure 8 shows the states of the bus
request mechanism as the Z-BUS is acquired,
used, and released.
To generate transactions on the bus, a bus
requester must gain control of the bus by
makmg a bus request. This is done by pulling
down BUSREQ . A bus request can be made in
either of two cases:
• BUSREQ is initially High and BAI is High,
indicating that the bus is controlled by the
CPU and no other requester is requesting
the bus.
• BAI is High and the requester had wanted
to request the bus at the time of the last
Low-to-High transition of BUSREQ . This
insures that a module will not be locked out
indefmitely by a higher priority bus
requester.
After BUSREQ is pulled Low, the Z-BUS
CPU relinquishes the bus and indicates this
condition by making BUSACK Low. The Low
on BUSACK is propagated through the
BAI/BAO daisy chain (Figure 7). BAI follows
BAO for components not requesting the bus,
and any component requesting the bus holds
its BAO High, thereby locking out all lower
priority requesters. A bus requester gains con-

Z-BUSCPU

BUS
REQUESTORS

trol of the bus when its BAI input goes Low.
When it IS ready to relmquish the bus, it stops
pulling BUSREQ Low and allows BAO to
follow BAI. This permits lower priority devICes
that made simultaneous requests to gain control of the bus. When all simultaneously
requesting devices have relinquished the bus,
and the Low on BAIIBAO has propagated to
the lowest priority requester, BUSREQ goes
High, returning control of the bus to the CPU.
The CPU responds to the High on
BUSREQ by drivmg BUSACK High. The High
on BUSACK is propagated down the BAIIBAO
daisy chain, thus allowing bus requesters to
make new bus requests. Because high prionty
bus requesters can pull BUSREQ Low before
low priority devICes have a High on BAI, a
way IS needed for low prIOrity devICes to
request the bus when BUSREQ is Low. That IS
provided by the rule that a requester may
request the bus if BAI is High and it had
wanted the bus at the hme the last Low-to-Hlgh
transItion on BUSREQ .
As soon as BUSREQ is pulled Low by any
requester, each of the other requesters on the
bus drives BUSREQ Low and continues to do
so until it dnves ItS BAO output Low. This provides a handshake between the CPU and the
bus requesters by ensuring that BUSREQ wlil
not go HIgh until the CPU's acknowledgement
of BUSACK has reached every requester. Bus
requesters can therefore run asynchronously to
the CPU. This rule also allows the bidirechonal
BUSREQ lme to be buffered usmg the logIC
shown in Figure 8. ThiS logic IS similar to the
logic inside a bus requester that keeps
BUSREQ Low when it has mlhally been
pulled Low by a different requester.

+5V

+ 5 V -'lMr~--+

COMMON BUSREQ

Figure 8. Bus Request Line Buffering

Figure 7. Bus Request Connections

485

Resource
Requests

Resource requests are used to obtain control
of a resource that is shared between several
users. The resource can be a common bus, a
common memory or any other resource. The
requestor can be any component capable of
implementing the request protocol.
Unlike the Z-BUS itself, no component has
control of a general resource by default; every
device must acquire the resource before using
it. All devices sharing the general resource
drive the MMRQ line (Figure 9). When Low,
the MMRQ line indicates that the resource is
being acquired or used by some device. The
MMST pin allows each device to observe the
state of the MMRQ line.
When MMRQ is High, a device may initiate
a resource request by pulling MMRQ Low
(Figure 10). The resulting Low on MMRQ is
propagated through the MMAIIMMAO daisy
chain. If a device is not requesting the
resource, its MMAO output follows its MMAI
input. Any device making a resource
request forces its MMAO output High to deny
use of the resource to lower priority devices.
A device gains control of the resource if its
MMAI input is Low (and its MMAO output is
High) after a sufficient delay to let the daisy
chain settle. If the device does not obtain the
resource after this short delay, it must stop
pulling MMRQ Low and make another request
at some later time when MMRQ is again High.
When a device that has gained control of a
resource is finished, it releases the resource by
allowing MMRQ to go High.

The four unidirectional lines of the resource
request chain allow the use of line drivers,
thus facilitating connection of components
separated by some distance. In the case of the
Z8000 CPU, the four resource request lines
may be mapped into the CPU MI and MO pins
using the logic shown in Figure 11. With this
configuration, the Multi-Micro Request Instruction (MREQ) performs a resource request.

+5V

'MMAI
MMST
MMRQ
MMAO

Figure 10. Resource Request Protocol

MiiAi
MiiSf

1. For any resource requested, this walt time must be less than the
minImum walt hme plus resource usage tIme of all other
requesters.

MiiRQ
MMAO

~~----------------~

MMAI
MMST
MMRQ

MMRQ

Mf---«

MMAO

~I_~>_------- MMRQ

~'-----------------4

Figure 9. Resource Request Connections

486

Figure 11. Bus Request Logic lor Z8000

Test
Conditions

The timmg characteristics gIven m this
document reference 2.0 Vas High and 0.8 V
as Low. The following test load circuit IS
assumed. The effect of larger capacitive
loadmgs can be calculated by delaying output
sIgnal translhons by 10 ns for each addlhonal
50 pF of load up to a maximum 200 pF.

+5V DC

22'

+5V DC

FROM OUTPUT

T

22.

UNDERTESTl

l

SOPF

Open-Drain Test Load

DC
Characteristics

The following table states the dc characteristics for the input and output pins of Z-BUS

components. All voltages are relative to
ground.

Symbol

Parameter

Min

Max

Unit

VIL
VIH
VIHRESEI

Input Low Voltage
Input High Voltage
Input High Voltage on RESET pin

-0.3
2.0
2.4

V
V
V

VOL
VOH
IlL

Output Low Voltage
Output Hlgh Voltage
Input Leakage Current
3-State Output Leakage Current in Float

0.8
Vee+ 0.3
Vee to
0.3
0.4
+10
+10

J.lA
J.lA

1m
Capacitance

The following table gives maximum pin
capacitance for Z-BUS components. Capacitance is specified at a frequency of 1 MHz
over the temperature range of the component.
Unused pins are returned to ground.

2.4
-10
-10
Symbol
C IN
Caul
CliO

Timing
Diagrams

80B5 004, 005

Standard Test Load

The following diagrams and tables give the
timing for each kind of transaction (except null
transactions). Timings are given separately for
bus masters and for peripherals and memories
and are intended to give the minimum timing
requirements which a Z-BUS component must
meet. An individual component will have more
detailed and sometimes more stringent timing
specifications. The differences between bus
master timing and peripheral and memory timing allow for buffer and decoding circuit

V
V

Test Condition

IOL = 2.0mA
IOH = 250J.lA
VIN = 0.4 to 2.4 V
VOUI = 0.4 to 2.4 V

Parameter
Input Capacitance
Output Capacitance
Bidirectional Capacitance

Max (pF)

10
15
15

delays and for signal skew. The timing given
for memories is a constraint on bus-compatible
memories (like the Z6132 Quasi-Static RAM)
and is not intended to constrain memory subsystems constructed from conventional components.
Besides these timings, there is a requirement
that at least 128 transactions be initiated in any
2 ms period. This accommodates memories that
generate refresh cycles from Address Strobe.

487

.•
d

Ut

Bus Master
Timing

EXTENDED
ADDRESS

------1h.
------1J't---+t----+---J "-+-----+---f---+-----I

AOo-A015

os
(WAITE)

Parameters 1-25 are common to all transachons.

1/0 Transaction
Timing

CLOCK

WAIT
SAMPLED

I

o

0\ WAIT
CYCLES

S'!!t-ST.!L
B/W,RIW

r·

AOo-AD15

'.'1"' .....~~ }

ADDRESS FROM

DATA TO BUS

I

AOo-AD15

Interrupt
Acknowledge
Timing

~~'"..~"

CLOCK
WAIT
SAMPLED

STATUS

4Do-AD15

Ai

.

DS
52

WAIT

488

2031·0240, 0187, 0191

No.

Symbol

Parameter

Min

4MHz
Max

6 MHz
Min
Max

Notes*t

All Transactions
1
TpC
Clock Penod
250
2000
165
2000
2
TwCh
Clock Hlgh Wldth
105
70
3
TwCl
Clock Low Wldth
105
70
4
TIC
Clock Fall Tlffie
20
10
5-TrC
Clock Rlse Tlffie - - - - - - - - - - - - - - - - - 2 0 - - - - - - 1 5 - - - - 6
TdC(S)
Clock 1 to Status Vahd Delay
110
85
7
TdC(ASr)
Clock 1 to AS 1 Delay
90
80
8
TdC(ASf)
Clock 1 to AS 1 Delay
80
60
9
TdS(AS)
Status Vahd to AS 1 Delay
50
30
lO-TwAS
AS Low Wldth - - - - - - - - - - - - - - 8 0 - - - - - - 5 5 - - - - - - - - 11
TdDS(S)
DS 1 to Status Not Vahd Delay
75
55
12
TdAS(DS)
AS 1 to DS 1 Delay
80
2095
55
3
13
TsDR(C)
Read Data ~Clock 1 Setup Tlffie
30
20
14
TdC(DS)
Clock 1 to DS 1 Delay
70
65
15-TdDS(AS)--DS 1 to AS 1 D e l a y - - - - - - - - - - - - 7 0
35-------16
TdC(Az)
Clock 1 to Address Float Delay
65
55
17
TdC(A)
Clock 1 to Address Vahd Delay
100
75
18
TdA(AS)
Address Vahd to AS 1 Delay
50
35
19
TdAS(A)
AS 1 to Address Not Vahd Delay
70
45
20-TwA
Address Vahd W l d t h - - - - - - - - - - - - 150 - - - - - - 8 5 - - - - - - - - 21
ThDR(DS)
Read Data to i5S 1 Hold Tlffie
0
0
22
TdDS(A)
DS t to Address Acllve Delay
80
45
23
TdDS(DW)
DS t to Wnte Data Not Vahd Delay
50
45
24
TsW(C)
WAIT to Clock 1 Setup Tlffie
50
30
2,4
25-ThW(C)---WAIT to Clock 1 Hold Tlffie
10
10------2,4_
_ _ Memory Transactions
26
TdAS(W)
AS t to WAIT ReqUlred Vahd
90
45
27
TdC(DSR)
Clock 1 to DS (Read) 1 Delay
120
85
28
TdDSR(DR)
DS (Read) 1 to Read Data ReqUlred Vahd
200
130
29
TwDSR
DS (Read) Low Wldth
250
185
30-TdA(DS) ---Address Vahd to DS 1 Delay---------180 - - - - - - 1 1 0 - - - - - - - - 31
TdAz(DSR)
Address Float to DS (Read) 1 Delay
0
0
32
TdAS(DR)
AS t to Read Data ReqUlred Vahd
360
220
33
TdA(DR)
Address Vahd to Read Data ReqUlred Vahd
410
305
34
TdC(DSW)
Clock 1 to DS (Wnte) 1 Delay
95
80
35-TwDSW---DS (Wnte) Low W l d t h - - - - - - - - - - - 1 6 0 - - - - - - 1 1 0 - - - - - - - - 36
TdDW(DSWI)
Wrlte Data Vahd to DS (Wrlte) 1 Delay
50
35
37
TdDW(DSWr)
Wnte Data Vahd to DS (Wnte) t Delay
230
195
I/O Transactions
38
TdAS(DR)
AS t to Read Data Required Vahd
385
610
39
TdA(DR)
Address Vahd to Read Data ReqUlred Vahd
470
660
40-TdAz(DSl)--Address Float to DS (I/O) 1 - - - - - - - - - - 0 - - - - - - 0 - - - - - - - - 41
TdC(DSI)
Clock 1 to DS (VO) 1
120
90
42
TdDSI(DR)
DS (I/O) 1 to Read Data ReqUlred Vahd
210
330
43
TwDSI
DS (I/O) Low Wldth
400
255
44
TdA(DSI)
Address Vahd to DS (I/O) 1 Delay
180
110
45-TdDW(DSIf)--Wnte Data to DS (I/O) 1 D e l a y - - - - - - - - 5 0 - - - - - - 3 5 - - - - - - - 46
TdDW(DSlr)
Wnte Data to DS (VO) 1 Delay
480
320
47
TdAS(W)
AS to WAIT Required Vahd
340
210
_
Interrupt-Acknowledge Transactions
48
TdAS(DSA)
AS t to DS (Acknowledge) 1 Delay
690
960
49
TdC(DSA)
Clock t to DS (Acknowledge) 1 Delay
120
85
50-TdDSA(DR)--DS (Acknowledge) 1 to Read Data ReqUlred Vahd - - - - - 4 5 5 - - - - - - 2 9 5 - - - - - 51
TwDSA
DS (Acknowledge) Low Wldth
315
485
52
TdAS(W)
AS t to Walt ReqUlred Vahd
840
540
53
TdDSA(W)
DS (Acknowledge) 1 to Walt ReqUlred Vahd
185
120
NOTES
1 T ImlDg for extended addresses IS CPU dependent, however,
extended addresses must ,be valid at least as soon as addresses

are valid on ADO-AD15 and must remam valid at least as
long as addresses are valid on ADO-AD15
2 The exact clock cycle that walt IS sampled on depends on the
type of transaction, however, walt always has the glVen setup
and hold tImes to the clock
The maXlmum value for TdAS(DS) does not apply to InterruptAcknowledge Transactions.

4 The setup and hold hmes for WAlI to the clock must be meL
If WAIT IS generated asychronously to the clock, It must be
synchromzed before mput to a bus master.
* Tlmmgs are prehmmary and subject to change

t U mts

In nanoseconds (ns)
Except where otherwIse stated, maXImum nse and fall hmes for
mputs are 200 ns

489

i

Memory and
Peripheral
Timing

STO-ST3,

1t=========----------i=="0=~~==
-------:~JJ=====:,------------_=:j================

EXTENDED
alW,NW _ _ _ _- '
ADDRESS

os
(READ)

os

-~-=---=---~

(WRITE)

"Do-AD15 _ _ _ _ _ _ _ _ _ _ _ _~

DATA FROM BUS MASTER

Parameters 1-12 are comm on to all transachons.

110 Transaction
Timing
aiii

===-------------==x~____

--~X~=_~_===~__1~---------___{0 ' ________~.I
l~___________

®

1_ _ _ _ _"

ADo-AD15

--®-

_ _2'+:::::::::;:®=_"i'~----®
Alii
(WRITE)

(R~!: ------_~J~~~~~
. . .l;:-:-:-:-:-:-:-:-:-~ -:®:l=:;;:=;;;-__===~ \.______
(==r====~~____~D~A~TA~F:R~OM::BU:S~M~AS~T_ER

ADo-AD15

Interrupt
Acknowledge
Timing
ADo-AD"

490

_ _ _ _....

_ _ _ _ __

=:~J:~=--~)('l"--===j=====

C8014-0183

C8014-0188 C8014-0192

4 MHz
No.

Symbol

Parameter

Min

All Transactions
1
TsCS(AS)
CS to AS t Setup T,me
ThCS(AS)
2
CS to AS t Hold T,me
TsS(AS)
3
Status to AS t Setup T,me
4
ThS(DS)
Status to DS t Hold Time
5-TsA(AS) - - - Address to AS t Setup T,me
ThA(AS)
6
Address to AS t Hold T,me
7
TwAS
AS Low Wldth
8
TdDS(DR)
DS t to Read Data Not Vahd Delay
TdDS(DRz)
9
DS t to Read Data Float Delay
lO-TdAS(DS)--AS t to DS I Delay
TdDS(AS)
11
DS t to AS I Delay
12
ThDW(DS)
Wnte Data to DS t Hold T,me
Memory Transactions
TdA(DR)
13
Address ReqUlred Vahd to Read Data Vahd Delay
14
TdAS(DR)
AS t to Read Valid Delay
15-TdAz(DSR) - - Address Float to DS (Read) I Delay
TdDSR(DR)
16
DS (Read) I to Read Data Vahd Delay
17
TwDSR
DS (Read) Low Wldth
TdA(DS)
18
Address to DS I Setup
19
TwDSW
DS (Write) Low Width
TsDW(DSWf)
20
Wnte Data to DS (Write) I Setup T,me
21-TsDW(DSWr) -Wnte Data to DS (Write) t Setup T,me
I/O Transactions
TdA(DR)
22
Address ReqUlred Vahd to Read Data Vahd Delay
TdAS(DR)
23
AS t to Read Data Vahd Delay
TdDSI(DR)
24
DS (I/O) I to Reai.Jlata Vahd Delay
TdAz(DSl)
25
Address Float to DS (110) I Delay
26-TdA(DSl)---Address to DS (1/0) I Setup
27
TwDSI
DS (1/0) Low Width
28
TsRWR(DSI)
RI'fl (Read) to DS (1/0) I Setup Time
29
TsRWW(DSl)
R/W (Write) toJ2.S (110) I Setup Time
TsDW(DSIf)
Wnte Data to DS (1/0) I Setup T,me
30
31
TsDW(DSIr)
Wnte Data to DS (110) t Setup T,me
32-TdAS(W)---AS t to WAlT Valid Delay

TsIA(AS)
33
34
ThIA(AS)
TdAS(DSA)
35
TdDSA(DR)
36
37-TwDSA
TdAS(IEO)
38
TdIEIf(IEO)
39
40
TsIEI(DSA)

Max

0
60
20
55
30
50
70
0

6MHz
Min
Max

0
40
0
40
10
30
50

1
1
2
11
0

70
45
60-2095 - - 40
50
25
30
20
320
270
0

Notes*t

5-

255
170
0

110
240
160
150
30
210

•51III

80
180
100
105
20
180

570
520
250

0
160
390
100
0
30
460
195
Interrupt-Acknowledge Transactions
INTACK to AS t Setup Time
0
INTACK to AS t Hold Time
250
AS t to DS (Acknowledge) I Delay
940
DS (Acknowledge) I to Read Delay Valid Delay
365
DS (Acknowledge) Low Width
475
AS I to lEO I Delay
lEI to IEO Delay
IEI to DS ("Acknowledge) I Setup Time

420
335
180
0
100
250
100
0
20
305
160
0
250
675
245
310
3,4
4
4

NOTES.
1 Parameter does not apply to Interrupt Acknowledge Transactions.

2. Does not cover R/W for I/O Transachons.
3. ApplIes only to a penpheral whlch 18 pullIng INT Low at the
begmnmg of the Interrupt Acknowledge Transaction.
4 These parameters afe devlCe dependent. The parameters for the
devlces many parhcular daiSY cham must meet the followmg
constramt for any two perIpherals m the daiSY cham,
TdAS(DSA) must be greater than the sum of TdAS(IEO) for the

all ;<031·02

hlgher pnonty peripheral, and TdIEIf(lEO) for each penpheral
separatmg them m the daiSY cham.

S The maximum value for TdAS(DS) does not apply to Interrupt
Acknowledge TransactIons.
" TImmgs are prelimmary and subject to change,
t Umts In nanoseconds (ns)
Except where otherWlse stated, maXImum nse and fall hmes for
mputs are 200 ns,

491

ZBI
Z·BUS Backplane
Interconnect System

~
Zilog

Product
Description

June 1982

Features

The bus structure for the 80' s
• Compatible
the Z-BUS Component
• InterconnectwIth
system
DeSIgned for the powerful Zllog Fam1ly of
• MICroprocessors
D

Z8 CPU

D

Z80 CPU

D

Z8000 CPU

D

Future mIcroprocessors

m apphcahon
• FleXlblhty
8-, 16- or 32-blt operahons
D
D

• Deslgned-m rehability
D Byte-onented panty and panty error lme
D

HIgh rehablhty pm and socket connectors

D

Dlstnbuted ground lmes

D

HIgh-current power dlstnbuhon

D Termmated bus lmes

r----'
I

EXTENDED

I
PROCESSORS

za
zao

I

I

G

ISING LEI

Z8000

Unsegmented, segmented, or memory
mapped systems

growth
• Future
Allows 32-bll operahons
D

D

5-blt status held
EXPANSION
MEMORY

PERIPHERAL
CONTROLLERS

I/O

ACCESSORIES

Description

The Z-BUS Backplane Interconnect (ZBI)
system IS a hIgh performance, apphcahononented system bus designed to utihze the full
capabllihes of all Z1Iog mICroprocessors-the
Z8, Z80 and Z8000.
ThIrty-two address/data lines coupled wIth
twenty-eIght control lmes provide the
resources needed for growth paths to future,
more complex 32-bit mIcroprocessors.
A member of the Z-BUS famIly of mlcrocom-

puter bus structures, the ZBI bus IS compahble
wIth the Z-BUS Component Interconnect (ZCI)
system used for communications at the chIp
level between Zilog processors and theIr
peripheral support modules.
ReliabIlity has been designed into the ZBI
structure: panty lines have been included;
ground lines are dIstributed between signals to
reduce nOIse; and all bus lines are termmated.

Functional
Description

Mechanical Configuration. The ZBI bus is
deflned for three SIzes of modular boards. The
smgle size modulEs measure 6.3" x 3.9" (160
mm x 100 mm). The double size boards are
6.3" x 9.2" (160 mm x 233.4 mm), and the
double extended size measure 11.0" x 9.2"
(280 mm x 233.4 mm). All ZBI boards are
consIstent wIth the standard European form
factor.
The smgle size boards have a single bus
connector wh1le the double boards have two
connectors.
The connector has a matrix of 96 pms on

.100" (2.54 mm) centers whIch are ahgned in 3
rows of 32 pins each. A molded plastic housmg
surrounds the pin array, providing mechanical
ngidlty and protecting the pms from
mechanical damage.
The backplanes use a sirmlar style of matmg
connector. These connectors are highly
reliable because connection surfaces are completely enclosed and shIelded from dirt and
dust when the connectors are mated. Another
advantage of this connector is its hIgh density
whICh permIts the deSign of compact boards.
In addition, the connectors are self-aligning

11l1l3001

493

Functional
Description
(Continued)

and keyed to prevent improper insertion.
All of the signals on the double boards are
assigned to one connector so that smgle
boards can be used in the same backplane

SINGLE

110 SIGNALS

I

6300

with double boards. The second connector on
the double boards is unspecified and available
for use by the designer.

.,

E IFI

DOUBLE

I~ S- -{]!I Q: S§i!IGil iliAgLSo- " " " Ql

11023
280

EXTENDED

-=

1/0 SIGNALS

11----2~,'::0----

Figure 2. The ZBI backplane accepts two sizes of boards: both are compatible with
European standards. The dimensions are in inches (upper) and millimeters (lower).

Signal
Description

The ZBI consists of 96 lines: 32 bidirectional
address/data lines with four parity lines, nine
interrupt lines, 28 control lines, 21 powersupply lines for ± 12 V, ±5 V and ground and
two reserve lines. The pin layout was defined
to provide the most convenient connection
from the board and the backplane, with Signals
collected into logical groups for placement on
the connector.
Address and Data. The address/data group is
laid out to enable the lines to enter the board
in order on both two-layer and four-layer
boards. Low-order lines are placed next to the
power pins for easier routing through buffers.
The high-order address/data pins are positioned near the control pms to faCilitate
decoding of the state of the bus. Address and
data information is transmitted over 32 bidirectional lines with separate address and data
strobe lines arbitrating the information flow.
The use of shared address/data lines enables a
compact connection while still allowing 32-bit
word sizes.
Word size is controlled by two lines that
indicate the data width of the current operation on the bus, making possible 8-bit, 16-bit
and 32-bit word transfers in the same system.
Data is aligned in the lower byte (ADo-AD7) of
the data field for 8-bit transfers, and the lower
word (ADo-ADlS) for 16-bit transfers.
The ZBI includes four parity lines and an
error-indication line to detect errors in
memory devices and transmissions on the bus.
One parity bit IS provided for each byte of the
32-bit address/data field, enabling paritychecking at both the byte and word levels.
Control Signals. The ZBI bus has 28 lines that
are used for bus control and status, grouped
into the following categories:
•

494

Clockmg. Two Imes prOVIde a master clock and a bus
clock. The master clock supphes a constant frequency

and IS used as a master hmmg reference; the bus clock
IS derived from the master.

• Extended processor archItectures. Two hnes enable the
CPU to mteract wIth an Extended Processor Umt.
• Resource sharmg. Three hnes enable processors to
lock other processors off the bus. ThIS IS a software
ImplementatIon, and all processors must be aware of
these SIgnals for the lockout to be effechve.
• D,rect memory access. Three hnes prOVIde the control
SIgnals reqUired for data to be transmItted m burst
mode across the bus. When d DMA device wants to
transmIt mformatIon, It Issues a request that causes the
processor to get off the bus. Once off the bus, the pro·
cessor Issues an acknowledge SIgnal mdICatmg that the
bus IS free. The DMA deVICe then begms transferrmg
data to the speClhed address. When the transfer IS com·
plete, the processor regaInS use of the bus.

• MUl/t'processor. Four hnes enable mulhple processors
to share a common bus. (Arbllrahon logIC to prevent
contenhon errors must be mcluded on each module.)
• Dota/Address Strobe. Two hnes mdICate whether
address or data mformahon IS on the address/data hnes.
• Status. Five hnes deSIgnate the kmd of Iransachon
occurrmg on the bus.
•

Word-SIze select. Two hnes determme the word sIze of
the transachon on the bus.

Interrupts. The ZBI bus has three independent
interrupt groups. Each group has an interrupt
request line and an interrupt enable input and
output daisy chain. A different priority level is
assigned to each of the three interrupt groups
and position-dependent priority is assigned to
each device within the groups.
The treatment of the interrupt signal is
processor-dependent and can be maskable,
non-maskable, vectored, or non-vectored
depending upon the configuration of the
system CPU.
Bus Conditioning. All bus lines are terminated in resistor pairs to provide the highest
integrity and best noise immunity for the
system. This forces all undnven lines to
approximately +3 V.
1003·002

Signal
Definition

NAMEIlNAME2: a doubly named lme,
HIgh/Low logIc levels

Table I defines the sIgnals necessary to the
ZBI structure.
All sIgnals, wIth the excephon of the data
and address lmes, are negahve true sIgnals,
where logical I = < 0.5 V and logIcal
= > + 2.4 V. Any excephon to thIs standard is noted m the table. Nammg conventIOns
are as follows:

OC: Open collector

NAME: a single lme, negative-true logIC level

HC: HIgh-current driver lme, not 3-state

NAME: a single lme, poslhve-true logIc level

DC: Dalsy-chamed sIgnal-OUT on one board
connects to IN of the next board

o

NAME< 0.3>: 4 lmes, poslhve-true logIC level

The abbrevJahons used to describe sIgnal
types are:
BD: Bldlrechonal data lmes
TS: 3-state, undlrectlOnal lmes

Signal
Number
Signal
Type
Name
of Lines
Function
Address and Data Group---------------------------------------------------------------------------AD
32
BD
Address and Data Lines. Address and data mformahon IS tune-muillplexed onto
these Imes. The hmes they are vahd are defmed by address strobe (AS) and data
strobe (DS). Addlllonal mformahon can be denved from the BCLK sIgnal for synchronous operahon.
Parity Group
P

BD

Parity-Check Bits. For bus transfer mtegnty, one panty bIt ;c, provIded for each
byte of the 32-blt address/data bus Even panty ensures that a read from a noneXIstent resource will generate a panty fault.

PE

OC

Parity Error. IndICates to the Bus Master that a panty error m a data transfer on
the bus has been caught by the panty check logIC.

Interrupt Group
INTI

OC

INT2

OC

INT3

OC

Levell Interrupts. HIghest pnonty mterrupt m the system. If a nOCl-maskable
mterrupt IS present, It must be here.
Level 2 Interrupt. Second hIghest pnonty mterrupt m the syste;YD. If a ye;ctored
mterrupt IS present, It must be; here.
Level 3 Interrupt. Lowest pnonty mterrupt m the system. If a non-vectored mterrupt IS present, It must be here.

IEll
IEO]
IEI2
IE02
IEI3
IE03

DC
DC
DC
DC
DC
DC

Level
Level
Level
Level
Level
Level

Control Group
PWRBAD

OC

Power Bad. An early warmng sIgnal that the de power for the system wrll soon
dIsappear. ThIS sIgnal IS generated by the power supply to gIve the processor
enough lime to store the machme state (If appropnate storage IS available) before
power drops below cnhcal levels.

Clocking
MCLK

HC

BCLK

HC

Master Clock. System master clock-l6 to 32 MHz. Frequency IS a 4 X mulhple of
the deSIred bus clock frequency.
Bus Clock. Bus transachon clock, denved from Master Clock and used by all synchronous elements m the system.

4

I
I
2
2
3
3

Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt

Enable
Enable
Enable
Enable
Enable
Enable

In
Out
In
Out
In
Out

Extended Processing Architecture - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Normal/System. Indlcates the 1110de oi [hr:;" C?0" controE1Ily
bl..~"--:;C;~llCl --138r
N/S
]
TS
mode or System mode (able to execute pnvlleged mstruchons)
OC

Stop Line. Stop the processor m control of the bus for synchromzahon of actlvllles
WIth the CPU.

Address/Data Strobes --------------------------------------------------------------------Address Strobe. IndICates that the AD Imes con tam a vahd address. The ~\S lwe IS
AS
I
TS
pulsed low by a board controlhng the transactIon for
or oata memory
access. Addresses are vahd at the trarlmg (nsmg) edge
TS

Dala Strobe. Data IS placed on or accepted from the AD bus lmes when DS IS low.
Table I. Signal D"finHions

495

N

...
till

Signal
Name
Status
ST<0:4>

Number
of Lines

Signal
Type

5

TS
54
0
0
0
0

~ord

B/W

53
0
0
0
0

Function
Status Lines. These lmes desIgnate the type of transacbon occurrmg on the bus.

52
0
0
0
0

51
0
0
1
1

So
0
1
0
1

0 0 1
0 0 1
0 0 1
0 0 1
0 1 0

0
0
1
1
0

0
1
0
1
0

0

0

0

Transaction
Internal Operabon
Memory Refresh
I/O Reference
SpecIal 1/0
Reference
Segment Trap Ack
Int! Interrupt Ack
Int2 Interrupt Ack
Int3 Interrupt Ack
Data Memory
Request
Stack Memory
Request

0

0

0

0

0
0
0

0

0 0
0 1
1 0

0 1 1 1 1
1 X X X X

Data Mem < > EPU
transfer
Stack Mem < > EPU
transfer
Prog Ref - nth cycle
Prog Ref - 1st cycle
EPU < > CPU
transfer
Reserved
Reserved

Size Select-----------------------------------------------------------------------------------TS
Byte/~ord Select. Used m conJuncbon wIth W/LW to dehne data access WIdth.

W/LW

TS

~ord/Long ~ord

Select. Used m conJuncbon wIth B/W to dehne the data access
WIdth. (A logICal 1 IS a hIgh voltage level.)

B/W
1

o
1

o

~ IL ~
1
1
0
0

Access ~idth
Byte (8·blt)--Data on AD <0:7>
Word (l6-blt)--Data on AD < 0: 15>
Double Word (32-blt)--Data on AD < 0:31 >
Reserved

Resource Sharing
MMREQ

OC

Multimicro Request. Th,s IS a software request to another processor for software
synchromzabon.

MMAI

DC

Multimicro Acknowledge In. Forms the logICal cham among processors to perform software arbltrabon, m conJunchon wIth the MMAOslgnal. The effect of th,s
lme IS dependent on the software present on the processor board.

MMAO

DC

Multimicro Acknowledge Out. Completes the logICal cham to the next processor's
MMAI pm.

Direct Memory Access
BAI
1

DC

Bus Acknowledge In From Priority Chain. Th,s sIgnal and BAOform the bus
pnonty cham.

BAO

DC

Bus Acknowledge Out to Priority Chain. Completes the GlrcUlt to the next devICe
m the bus pnorlty cham.

BUSREQ

OC

Bus Request. Used to request access to the bus. A request to a processor to relmqUlsh the bus at the end of the current mstruction cycle. Th,s sIgnal IS used with
the BAI and BAO sIgnals to control bus sharmg by DMA devICes not able to
become bus masters.

Multiprocessor
CAl
CAO
CPUREQ

CAVAIL

Control-----------------------------------------------------------------------------DC
CPU Acknowledge In.
1
DC
CPU Acknowledge Out.
DC
CPU Request. A request to the processor currently in control of the bus to relinqUlsh control at the end of the current mstrucbon cycle. ThlS sIgnal IS used wIth
CAl, CAO, and CAVAIL to control sharmg of the bus by devICes able to become
bus masters.
TS
CPU Available. Used m conJunchon wIth CAl and CAO to transfer bus control
from one bus master to another.

Miscellaneous Control Lines ------------------------------------------------------------------------------RESET
1
OC
Reset. Connected to the master reset sWItch and power-up reset GlrcUlI.
WAIT

OC

R/W

TS

~ait.

Causes a processor or peripheral to walt for the response to a request for
data. Such a Walt could be caused by slow memory or by refresh contenbon
problems.

Read/~rite.

If th,s line IS hIgh, the current opera bon IS a read; If low, a wnte.

Table J. Signal Definitions (contmued)

496

00·1003-01

Advanced Architectural
Features of the
Z8000 CPU

~

Tutorial
Information

Zilog

June 1982

Introduction

The Zllog Z8000 CPU mICroprocessor is a
major advance in microcomputer architecture.
It offers many mimcomputer and mainframe
features for the first time in a microprocessor
chip. This tutorial describes the Z8000 CPU
with emphasis placed on those features that set
it apart from its microprocessor predecessors.
For a detailed description of all Z8000 CPU
features, consult the Zilog pubhcations listed
in the bibliography at the end of this tutorial.
The features to be discussed are grouped
into four areas: CPU organization, handling of
interrupts and traps, use of memory, and new

Instruchons and data capabilities.
Before dISCUSSing these features in more
detail, a word about nomenclature is In order.
The term Z8000 refers to the concept and
architecture of a famIly of parts. Zilog has
adopted the typical conductor industry 4-digii
deslgnahon for Z8000 Family parts, while also
keeping the traditional 3-leUer acronym that
proved so popular for the Z-80 Family. Thus,
the 48-pin version of the Z8000 CPU is called
the Z8001 CPU; the 40-pin version is known as
the Z8002 CPU.

CPU
The Z8000 CPU is organized around a
Organization general-purpose register hIe (Figure 1). The
register file is a group of registers, anyone
of which can be used as an accumulator,
index register, memory pOinter, stack pointer,
etc. The only exception is Register 0, as
explained later.
Flexibility is the major advantage of a
general-purpose register organization over an
organization that dedICates parhcular registers
to each function. Computation-oriented
routines can use general registers as
accumulators for intermediate results whereas
data manipulation routines can use these
registers for memory pOinters.
Dedicated registers, however, have a disadvantage: when more registers of a given type
are needed than are supplied by the machine,
the performance degrades by the extra instructions to swap registers and memory locations.
For example, a processor WIth two index
registers suffers when three are needed
because a temporary variable in memory (or in
another regIster) must be used for the third

index. When the thIrd index is needed, it must
be swapped Into an index register. In contrast,
on a general-regIster machine three of the
registers could be dedICated for index use. In
addition, since the need for index registers
may vary over the course of a program, a
general-register architecture, such as the
Z8000, can be adapted to the changing needs
of the computation with respect to the number
of accumulators, memory pointers and index
registers. Thus flexibility results in increased
performance and ease of use.
In addItion, the registers of the Z8000 are
organized to process 8-bit bytes, 16-bit words,
32-bit long words and 64-bit quadruple words.
This readily accommodates applications that
process data of variable sizes as well as different tasks that require different data sizes.
Although all regIsters can-in general-be
used for any purpose, certain instructions such
as Subrouhne Call and String Translation
make use of speClhc registers in the general
register file, and this must be taken into
account when these instructions are used.

497

o~$J

.!0>eD

co

~ '3::s
~.

~ N"

CD Q

&g::s

~[

ST
ST:
ST

CPUfSVSTEM

ST,

IA

STATUS
INFORMATION

NOAMAUSYsTEM

INSTRUCTION
REGISTER

'If

~

AS

OS

TIMING
CONTROL

MREQ

BUS
CONTROL

BUSACK

INSTRUCTION
DECODER

1'If

~l
A
I

''If
Mi

~

Mo

NMi

~

~

Vi
Wi

I
M~~~'~~g~o IA-Y
K

SEGT

EXTERNAL
~

INTERRUPTI
TRAP
CONTROL

~

CLOCK

~

WAIT

~

CPU
STATE

STOP

~

CONTROL

RESET

~

~

INSTRUCTION
ENCODER

I---tr-----v
~

h'-

ll~
~

~J

..!J,.

AND

UNIT

H
IV

~

L;

REGISTER
CONTROL

l}

11
REGISTER

FILE

I~
~
~

rY

-V

ADDRESS
DATA

REGISTER

k=>

ADDRESSI

DATA BUS
ADo-AD15

SEGMENT NUMBER

REGISTER

I---r--r-

CPU
CONTROL

i

~ SEGMENT

1

UNIT

ADDRESS
SNo-SN7

l

±J
CPU
CONTROL
REGISTER

INTERNAL DATA BUS

1J.
INSTRUCTION
LOOKAHEAD

l-

I..-

~

IS
Figure 1. CPU Organization

I

ARITHMETIC

I---A

~

BUSREQ

Y

IV

A

BUS

FLAGS

LOGIC

ALU
CONTROL

READ/WRITE
WORDfBYTE

~

PROGRAM COUNTER OFFseT
REFRESH COUNTER
REFRESH TIMER

AND
INCREMENTER BY 2

f--

c::

CPU

The Z8000 CPU also contams a number of
Organization special-purpose registers m addihon to the
(Continued)
general-purpose ones. These mclude the Program Counter, Program Status registers and
RO

17

Ri

1'5

RRO \

oi1

01
01

the Refresh Counter. These registers are
accessIble through software and provIde some
of the interestmg features of Z8000 CPU
archItecture.
RO

17

Rt

1'5

RRO \
ROO

R21

R21
Ral
R41

RH'
RH3

RR' \ R31

RR< \

Rsl
Rsl

RH5

RR. \ Rsl

R" \

R71

R" \

R" (

1

01

oi 7

R41

Rei

RR' \
01

R81's
Rgi

RTI

01

Rel's

RR. (

R91
R08

RR10

\ ,,°1

RRt2

\ "'I

R11

I

RR10

( R"

I

R11

I

\ "'I

RR12

R131

N

00

R131

R1S'

R"

NORMAL STACK POINTER \SEG NO)
RR14

1"'1

SYSTEM STACK POINTER (OFFSen

Register
All general-purpose registers can be used as
Organization accumulators, and all but one as index
registers or memory pointers. The one register
that cannot be used as an mdex register is
Register O. Specifying Register 0 IS used as an
escape mechanism to change the address mode
from IR to 1M, from X to DA, or-with Load
instructions-from BA to RA. ThIS has been
done so that the two addreSSing mode bits in
the instruction can specify more than four
addressing modes for the same opcode.
The Z8000 CPU regIster file can be
addressed in several groupings: as sixteen
byte registers (occupying the upper half of the
file only), as sixteen word registers, as eIght
long-word registers, as four quadruple-word
registers, or as a mIxture of these. Instruchons
eIther explicitly or implicitly specify the type
of register. Table I illustrates the correspondence between the 4-bit source and
destmahon register fields in the instruction
(Figure 4) and the location of the registers m
the register file (Figures 2 and 3).

R1S'

SYSTEM STACK POINTER

N

NORMAL STACK POINTER

R"

NORMAL STACK POINTER (OFFSET)

Figure 2. Z8001 General Purpose Registers

8...

Ra12

SYSTEM STACK POINTER (SEG NO)

R"R"

RR14

1

~

•...

Figure 3. Z8002 General Purpose Registers

Register

Designator

Byte

0000

RHO

Word

Long
Word

c:I

Quadruple
Word

0

I»

RO

a a a 1

RHl

Rl

a a 1a

RH2

R2

a a I I

RH3

R3

a lOa

RH4

R4

a 1a 1

RH5

R5

OllO

RH6

R6

all 1

RH7

R7

lOa a

RLO

R8

lOa 1

RLl

R9

lO 1 a

RL2

RlO

1 all

RL3

Rll

I lOa

RL4

RI2

11a 1

RL5

R13

1 1 10

RL6

R14

llll

RL7

R15

RRO

RQO

RR2

RR4

RQ4

RR6

RR8

RQ8

RRlO

RRI2

RQl2

RRl4

Table I

2048·0207, 0208

...
a

499

Register
Note that the byte regIster-addressing
Organization sequence (most significant bIt dIstinguishes
(Continued)
between the two bytes in a word regIster) IS
different from the memory addressing
sequence (least slgmficant bIt distingUIshes
between the two bytes in a word). Long-word
(32-bit) and quadruple-word (64-bit) regIsters
are addressed by the binary number of their
starting word registers (most sIgnifICant word).
For example, RR6 IS addressed by a binary 6
and occupies word registers 6 and 7.

B~~~~ IM~DE

I

LO=~~O~~ IM~DE I
MODE
REGISTER
IMMEDIATE
DIRECT

INDIRECT

OPCODe

I

I

SOURCE
I
I
I

IBiWI

OPCODE
I
I
I

SOURCE
I
I
I

I D~STI~ATI?N I
I D~STI~ATI?N I

I 0I

1

~

} FOR SOURCE = 0

~

}FORSOURCE+O 0 0 0

0

0

0

Figure ,. Instruction Format

The zaooo CPU can run in one of two
System!
Normal Mode modes: System or Normal. In System Mode,
of Operation all of the Instructions can be executed and all
of the CPU regIsters can be accessed. ThIs
mode IS intended for use by programs that perform operating system type functions. In Normal Mode, some instructions, such as I/O
mstructions, are not all allowed, and the control registers of the CPU are inaccessIble. In
general, this mode of operation is intended for
use by applicahon programs. This separahon
of CPU resources promotes the integnty of the
system since programs operating in Normal
Mode cannot access those aspects of the CPU
which deal with time-dependent or system
interface events.
Normal Mode programs that have errors can
always reproduce those errors for debugging purposes by simply re-executing the programs with theIr onginal data. Programs using
facilities available only in System Mode may
have errors due to timmg consIderations (e.g.,

based on the frequency of disk requests and
dIsk arm position) that are harder to debug
because these errors are not easily reproduced. Thus a preferred method of program
development would be to partition the task into
that porhon which can be performed without
recourse to resources accessible only in
System Mode (which will usually be the bulk of
the task) and that portion requiring System
Mode resources. The classic example of this
partihomng comes from current minicomputer
and mainframe systems: the operating system
runs in System Mode and the indIvidual users
write their programs to run In Normal Mode.
To further support the System/Normal Mode
dichotomy, there are two copies of the stack
pointer-one for the System Mode and another
for Normal. Although the stacks are separated,
it is possIble to access the normal stack
registers while in the System Mode by using
the LDCTL Instruction.

Status Lines

with l28K bytes if additional logic is used,
say, to select the lower 64K bytes for program
references and the upper 64K bytes for data
references.

500 I

The Z8000 CPU outputs status information
over its four status lines (STo-ST3) and the
System/Normal line (SIN). This Information can
be used to extend the addreSSing range or to
protect accesses to certain portions of memory.
The types of status information and their codes
are listed in Table 2.
Status conditions are mutually exclusive and
can, therefore, be encoded without penalty.
Most status defimtions are self-explanatory.
One code is reserved for future enhancements
of the Z8000 Family.
Extension of the addressing range is accomplished in a zaooo system by allocating
physical memory to specific usage (program
vs. data space, for example) and uSing external circuitry to mom tor the status lines and
select the appropriate memory space for each
address. For example, the direct addressing
range of the Z8002 CPU is limIted to 64K
bytes; however, a system can be conflgured

Definition

8T3-8TO

0000
000 I
00 I 0
001 I
0100
0101
o I 10

oI

I I

1000
100 I
10 I 0
101 I
I 100
I 101
I I 10
IIII

Internal operabon
Memory refresh
1/0 reference
SpeClal VO reference
Segment trap acknowledge
Non-maskable Interrupt acknowledge
Non-vectored Interrupt acknowledge
Vectored mterrupt acknowledge
Data memory request
Stack memory request
Data memory request (EPU)
Stack memory request (EPU)
Instruchon space access
Instrucbon fetch, hrst word
ExtenslOn processor transfer

Reserved
Table 2

2048·0202

Status Lines
(Contmued)

Protection of memory by access types IS
accomplished sImIlarly. The memory is dIvIded
mto blocks of locahons and assocIated with
each block is a set of legal status sIgnals. For
each access to the memory, the external cIrcuIt
checks whether the CPU status IS appropriate
for the memory reference. The Z8010 Memory
Management Umt IS an example of an external
memory-protechon cIrcuIt, and it is discussed
later m thIs tutorial.
The hrst word m an mstruchon fetch has Its

own dedIcated status code, namely 1101. This
allows the synchronizahon of external circUIts
to the CPU. Durmg all subsequent fetch cycles
within the same mstruchon (remember, the
longest instruchon reqUIres a total of four word
fetches), the status IS changed from 1101 to
1100. Load Relahve and Store Relative also
have a status of 1100 with the data reference,
so informahon can be moved from program
space to data space.

Refresh

The Idea of mcorporating the Refresh
Counter m the CPU was pioneered by the
Z-80 CPU, whICh performs a refresh access m
a normally unused time slot after each opcode
fetch. The Z8000 IS more straIghtforward (each
refresh has ItS own memory-access time slot of
three clock cycles), and IS more versahle (the
refresh rate is programmable and capable of
being disabled altogether).
The Refresh RegIster contams a g-blt Row
Counter, a 6-bit Rate Counter and an Enable
BIt (Figure 5). The row sechon IS output on
ADo-ADs during a refresh cycle. The Z8000
CPU uses word-orgamzed memory, wherein Ao
is only employed to dlstmguish between the
lower and upper bytes WIthin a word during
readmg or wrihng bytes. Ao therefore plays no
role m refresh-It IS always O. The Row
Counter is-at least conceptually-always
mcremented by two whenever the rate counter
passes through zero. The Row Counter cycles
through 256 addresses on Imes AD1-ADs,
which satisfies older and current 64- and
128-row addressmg schemes, and can also be
used WIth 256-row refresh schemes for
64K RAMs.
The Rate Counter determines the time
between succesSIve refreshes. It consists of a
programmable 6-bit modulo-n prescaler

(n = 1 to 64), driven at one-fourth the CPU
clock rate. The refresh period can be programmed from 1 to 64 p.s with a 4 MHz clock.
A value of zero m the counter held indicates
the maximum hme between refreshes; a value
of n mdicates that refresh IS to be performed
every 4n clock cycles. Refresh can be dIsabled
by programming the Refresh Enable Bit to
be zero.
A memory refresh occurs as soon as possible
after the mdICated hme has elapsed. Generally, thIS means after the T3 clock cycle of an
instruchon If an instruction execution has commenced. When the CPU does not have control
of the bus (during the bus- request/busacknowledge sequence, for example), it cannot
issue refresh commands. Instead, it has mternal cirCUItry to record "missed" refreshes;
when the CPU regains control of the bus it
immedIately Issues the "missed" refresh cycles.
The Z8001 and Z8002 CPU can record up to
two "mIssed" refresh cycles.

Most instruchons conclude WIth two or three
clock cycles being devoted to internal CPU
operahons. For such mstructlOns, the subsequent instruchon-fetch machine cycle is
overlapped with the concluding operations,
thereby improving performance by two or
three clock cycles per mstruction.
Examples of instructions for which the subsequent mstruchon IS fetched while they complete are Arithmetic and Shift instructions.

Some mstructions for which the overlap is
logically Impossible are the Jump instructions
(because the following instruchon location has
not been determined until the mstruction completes). Some mstruchons for which overlap is
physically impossible are the Memory Load
mstructions (because the memory is busy with
the current mstruchon and cannot service the
fetch of the succeedmg instruction).

Instruction
Prefetch
(Pipelining)

2048·0203

10 ,

16

RATE
,

, I

ROW
!

!

Figure 5. Refresh Counter

501

Extended
Instruction
Facility

502

The 28000 architecture has a mechanism for
extending the basIc instruction set through the
use of external devices. Special opcodes have
been set aside to implement this feature. When
the CPU encounters mstructions with these
opcodes in its instruction stream, it will perform any indicated address calculation and
data transfer, but otherwise treat the "extended
instruction" as being executed by the external
device. Fields have been set aside in these
extended instructions which can be interpreted
by external devices (called Extended Processing Units-EPUs) as opcodes. Thus by using
appropriate EPUs, the instruction set of the
28000 can be extended to include specialized
instructions.
In general, an EPU is dedicated to performing complex and time consuming tasks in
order to unburden the CPU. Typical tasks
suitable for specialized EPUs include floatingpomt arithmetic, data base search and
maintenance operations, network interfaces,
graphics support operations-a complete list
would include most areas of computing. EPUs
are generally designed to perform their tasks
on data resident in their internal registers.
Moving information mto and out of the EPU's
internal registers, as well as instructing the
EPU as to what operations are to be performed, is the responsibility of the CPU.
For the 28000 CPU, control of the EPUs
takes the following form. The 28000 CPU
fetches instructions, calculates the
addresses of operands residing in memory,
and controls the movement of data to and
from memory. An EPU monitors this activity on
the CPU's AD lines. If the instructions fetched
by the CPU are extended instructions, all
EPUs and the CPU latch the mstruction (there
may be several different EPUs controlled by
one CPU). If the instruction is to be executed
by a particular EPU, both the CPU and the
indicated EPU will be involved in execuhng
the instruction.
If the extended instruction mdicates a
transfer of data between the EPU's internal
registers and the main memory, the CPU will
calculate the memory address and generate
the appropriate timing signals (AS, DS,
MREQ, etc.), but the data transfer itself is
between the memory and the EPU (over the

AD lines). If a transfer of data between the
CPU and EPU is indicated, the sender places
the data on the AD lines and the receiver
reads the AD lines during the next clock
period.
If the extended instruction indicates an
mternal operation to be performed by the EPU,
the EPU begms execution of that task and the
CPU is free to continue on to the next mstruction. Processing then proceeds simultaneously
on both the CPU and the EPU until a second
extended instruction is encountered that is
destined for the same EPU (if more than one
EPU is in the system, all can be operating
simultaneously and independently). If an
extended instruction specifies an EPU still
executing a previous extended instruction, the
EPU can suspend instruction fetching by the
28000 CPU until it is ready to accept the next
extended instruction: the mechanism for this is
the STOP line, whICh suspends CPU activity
durmg the instruchon fetch cycle.
There are four types of extended instructions
m the 28000 CPU mstruction repertoire: EPU
mternal operations; data transfers between
memory and EPU; data transfers between EPU
and CPU; and data transfer between EPU flag
registers and CPU flag and control word. The
last type is useful when the program must
branch based on conditions determined by the
EPU. Six opcodes are dedicated to extended
instructIOns: OE, OF, 4E, 4F, 8E and 8F (in
hexadecimal). The action taken by the CPU
upon encountermg these instructions is dependent upon an EPU control bit in the CPU's
FCW. When this bit IS set, it mdicates that the
system configuration mcludes EPUs; therefore,
the mstruction is executed. If this bit is clear,
the CPU traps (extended instruction trap), so
that a trap handler in software can emulate the
desired operation.
In conclusion, the major features of this
capability are, that multiple EPUs can be
operating in parallel with the CPU, that the
live mam CPU addressing modes (Register,
Immediate, Indirect Register, Direct Address,
Indexed) are available m accessing data for
the EPU; that each EPU can have more than
256 different instructions; and that data types
manipulated by extended instructions can be
up to 16 words long.

Program
Status
Information

The Program Status Information consists of
the Flag And Control Word (FCW) and the
Program Counter (PC). The 28000 CPU uses
one byte In FCW to store flags and another
byte to store control bits.

Arithmetic Flags. Flags occupy the low byte
in the FCW and are loaded, read, set and
reset by the special instruction LDCTLB,
RESFLG and SETFLG. The flags are:
C
Carry
Z
2ero
S
Sign (l = negative; two's complement
notation is used for all arithmetic on
data elements)
PIV Even Parity or Overflow (the same bit is
shared)
D
Decimal Adjust (differentiates between
addition and subtraction)
H
Half Carry (from the low-order nibble)

Control Bits. The control bits occupy the
upper byte in the FCW. They are loaded and
read by the LDCTL instruction, which is
privileged in that it can be executed only in
the System Mode. The control bits are:
NVIE Non-Vectored Interrupt Enable
VIE Vectored Interrupt Enable
SIN System or Normal Mode
SEG Segmented Mode Enable (28001 only)
The SEG bit is always 0 in the 28002 even if
the programmer attempts to set it. In the
28001, a 1 in this bit indicates segmented
operation. A 0 In the 28001 SEG bit forces
non-segmented operation and the CPU interprets all code as non-segmented. Thus, the
28001 can execute modules of user code
developed for the non-segmented 28002.

Interrupt
and Trap
Structure

The 28000 provides a powerful interrupt and
trap structure. Interrupts are external asynchronous events requiring CPU attention, and
are generally triggered by peripherals needing
service. Traps are synchronous events
resulting from the execution of certain instructions. Both are processed in a similar manner
by the CPU.
The CPU supports three types of interrupts

(non-maskable, vectored and non-vectored),
three internal traps (system call, unimplemented instruction, privileged instruction) and
a segmentation trap. The vectored and nonvectored interrupts are maskable.
The descending order of priority for traps
and interrupts is: internal traps, non-maskable
interrupts, segmentation trap, vectored interrupts and non-vectored interrupts.

Effects of
Interrupts
on Program
Status

The Flag and Control Word and the Program Counter are collectively called the Program Status lnformation-a useful grouping
because both the FCW and PC are affected by
interrupts and traps. When an interrupt or trap
occurs, the CPU automatically switches to the
System Mode and saves the Program Status
plus an identifier word on the system stack.
The identifier supplies the reason for the interrupt. (The 28002 pushes three words on the
stack; the 28001 pushes four words.)
After the pre-interrupt or "old" Program
Status has been stored, the "new" Program
Status is automatically loaded into the FCW
and PC. This new Program Status Information
is obtained from a specified location in
memory, called the Program Status Area.
The Z8000 CPU allows the location of the
Program Status Area anywhere in the addressable memory space, although it must be
aligned to a 256-byte boundary. Because the
Status Line code is 1100 (program reference)
when the new Program Status is loaded, the
Program Status must be located in program
memory space if the memory uses this attribute
(for example, when using the 28010 Memory
Management Unit or when separate memory
modules are used for program and for data).

The Program Status Area Pointer (PSAP)
specifies the beginning of the Program Status
Area. In the 28002, the PSAP is stored in one'
word, the lower byte of which is zero. The
Z8001, however, stores its PSAP in two words.
The first contains the segment number and the
second contains the offset, the lower byte of
which is again zero. The PSAP is loaded and
read by the LDCTL instruction.
In the 28002, the first 14 words (28 bytes) of
the Program StatUs Area contain the Program
Status Information for the following interrupt
conditions:

Location
(In Bytes)

Condition

0-3

Not used (reserved for future use)

4-7

Unimplemented instruction has
been fetched, causing a trap

8-11

Privileged instruction has been
fetched in Normal Mode, causing a
trap

12-15

System Call instruction

16-19

Not used

20-23

Non-maskable interrupt

24-27

Non-vectored interrupt

503

Effects of
Interrupts
on Program
Status
(Continued)

Bytes 28-29 contain the FCW that is common to all vectored interrupts. Subsequent
locations contain the vector Jump table (new
PC for vectored mterrupts). These locations
are addressed in the following way: the 8-bit
vector that the interrupting device has put on
the lower byte of the Address/Data bus
(ADo-AD7) is doubled and added to
PSAP + 30. Thus,
Vector 0 addresses PSAP + 30,
Vector I addresses PSAP + 32, and
Vector 255 addresses PSAP + 540.
In the segmented 2800 I, the first 28 words of
the Program Status Area (56 bytes) contain the
Program Status Information (reserved word,
FCW, segment number, offset), for the following interrupt conditions:

Location
(In bytes)

Bytes 56-59 'Contain the reserved word and
FCW common to all vectored interrupts.
Subsequent locations contain the vector jump
table (the new segment number and offset for
all vectored interrupts). These locations are
addressed in the following way: the 8-bit vector that the interrupting device has put on the
lower byte of the Address/Data bus (ADo-AD7)
is doubled and added to PSAP + 60. Thus,
Vector 0 addresses PSAP + 60,
Vector 2 addresses PSAP + 64, and
Vector 254 addresses PSAP + 568.
Care must be exercised in allocating vector
locations to mterrupting devices; always use
even vectors. Thus there are effectively only
128 entries m the vector jump table. (Figure 6
illustrates the Program Status Area.)
~~o:~o

Condition

o Z8001 OFFSET
(IN BYTES)

RESERVED
UNIMPLEMENTED

INSTRUCTION

0-7
8-15
16-23

24-31
32-39

40-47
48-55

504

Not used (reserved for future use)
Unimplemented instruchon has
been fetched causing a trap
Privileged mstruction has been
fetched m Normal Mode causing
a trap
System Call instruction
Segmentation trap (memory vlolahon detected by the 28010 Memory
Management Unit)
Non-maskable mterrupt
Non-vectored mterrupt

PRIVILEGED
INSTRUCTION

"

SYSTEM CALL
INSTRUCTION

.."
24

SEGMENT TRAP
(UNUSED FOR Z8OO2)
NON MASKABLE
INTERRUPT

NON VECTORED
INTERRUPT
VECTORED INT

30

-NEWPC-

"

NEW PC

..

..

34

OJ
72

VECTORED

INTERRUPT
JUMP TABLE

NEW PC

Figure 6. Program Status Area

2()48.0204

Z8000 CPU
Memory
Features

Address
Notation

2048·0205

The way a processor addresses and manages
its memory is an Important aspect in both the
evaluation of the processor and the design of a
computer system that uses the processor. Z8000
architecture provides a consistent memory
address notation in combining bytes into words
and words into long words. All three data
types are supported for operands m the Z8000
instruction set. I/O data can be either byte- or
word-oriented.
The Z8001 CPU provides a segmented
addressing space with 23-bit addressmg. The
Z8010 Memory Management Unit can mcrease
the address range of this processor. To support
a memory management system, the Z8001 processor generates Processor Status Information.

These signals are also generated by the Z8002
CPU and-as menhoned ear her-can be used
to increase the address range of this processor
beyond its nominal 64K byte limit. It IS not
necessary to use a Z8010 Memory Management
Umt with a Z8001. The segment number (upper
six bIts of the address) can be used directly by
the memory system as part of the absolute
address.
These issues are discussed in more detail in
the following sechons, along with a deSCription of the method used to encode certain
segmented addresses mto one word. A brief
comment on the use of 16K Dynamic RAMs
with the Z8001 concludes this group of sections
that deal with Z8000 CPU memory features.

In the Z8000 CPU, memory and IIO
addresses are always byte addresses. Words or
long words are addressed by the address of
their most Significant byte (FIgure 7). Words
always start on even addresses (Ao = 0), so
both bytes of a word can be accessed simultaneously. Long words also start on even
addresses.
Withm a word, the upper (or more significant) byte is addressed by the lower (and
always even) address. SImilarly, within a long
word, the upper (more significant) word is
addressed by the lower address. Note that this
format differs from the PDP-II but is identical
to the IBM convention.
There IS good reason for chOOSing this format. Because the Z8000 CPU can operate on
32-blt long words and also on byte and word
strings, it IS important to maintain a continuity
of order when words are concatenated mto
long words and strings. Making ascending
addresses proceed from the highest byte of the
first word to the lowest byte of the last word
maintams thIS continuity, and allows compar-

mg and sorhng of byte and word strmgs.
BIt labeling withm a byte does not follow this
order. The least slgmficant bIt in a byte, word
or long word is called Bit 0 and occurs in the
byte WIth the highest memory address. This is
consistent WIth the convention where bIt n
corresponds to pOSition 2 n m the convenhonal
binary notahon. This ordering of bit numbers
is also followed in the registers.
LONG WOAD
ADDRESSES

"T -[

·,,(TI
1000

CONTENTS OF BYTE
CONTENTS OF WORD
CONTENTS OF LONG WOAD
CONTENTS OF lONG WOAD

0010 [

0100 [

0110

[

1000 [

A.

0001

5B

0010

e2

0011

35

0100

.2

0101

AB

0110

2B

0111

FF

1000

A2

Q

a

i

!.

~

0000

iii

:So

WORD
BYTE
ADDRESSES ADDRESSES MEMORY

0000 [

I

1001
0100 = "02"
0100 "" "02AB"
0100 "" "02AB2BFF"
0010
"C23502AB"

=

Figure 7. Memory Addressing

505

Memory
and I/O
Addressing

Llke most 16-blt mlcroprocessors, the 28000
CPU uses a 16-blt parallel data bus between
the CPU and memory or 110. The CPU is
capable of readmg or writing a 16-bit word
wlth every access. Words are always addressed
with even addresses (Ao = 0). All instructions
are words or mulhple words.
The Z8000 CPU can, however, also read and
wnte 8-blt bytes, so memory and I/O addresses
are always expressed m bytes. The Byte/Word
(B/W) output mdlcates whether a byte or word
is addressed (Hlgh = byte). Ao distingUlshes
between the upper and lower byte m memory
or I/O. The most slgmhcant byte of the word is
addressed when Ao lS Low (Figure 8).
For word operahons m both the read and
wnte modes, B/W = Low, Ao is simply

ignored and A)-A)5 address the memory or
I/O. For byte operations in the read mode,
B/W = High, Ao is again ignored, and a
whole word (both bytes) is read, but the CPU
internally selects the appropriate byte. For
byte operations in the write mode, the CPU
outputs identical information on both the Low
(ADo-AD7) and the High (ADa-AD)s) bytes of
the Address/Data bus. External TTL logic must
be used to enable writing in one memory byte
and disable writing in the other byte, as
defined by Ao. The replication of byte information for writes is for the current implementation
and may change for subsequent Z8000 CPUs;
therefore system designs should not depend
upon this feature.

is.BIT BUS DATA PATH

D

D.

WORD
ADDRESS

LOWER
BANK

--t==~=L'/----------' ENABLE

Figure 8. Byte/Word Selection

Segmentation

506

In orgamzmg memory, segmentation is a
powerful and useful technique because lt forms
a natural way of dlvldmg an address space into
dlfferent funchonal areas. A program typically
parhhons its avaJlable memory into disjomted
areas for parhcular uses. Examples of this are
slormg the .procedure instructions, holding its
global vanables, or servmg as a buffer area
for processmg large, dlsk-resident data bases.
The reqUlrements for these dJ!ferent areas may
differ, and the areas themselves may be
needed only part of the time.
Segmentation reflects this use of memory by
ollowmg a user to employ a dJ!ferent segment
for each dllferent area. A memory management system can then be employed to provide
system support, such as swapping segments
from disk to pnmary memory as requested (as
m overlays), or m momtoring memory accesses
and allowmg only certam types of accesses to

a particular segment. Thus, dealing with
segments is a convenient way of specifying
portions of a large address space.
When segmentation is combined with an
address translation mechanism to provide
relocation capability, the advantages of
segmentation are enhanced. Now segments can
be of variable user-specifiable sizes and
located anywhere in memory.
The Z8001 generates 23-bit logical
addresses, consisting of a 7-bit segment
number and a l6-bit offset. Thus each of its six
memory address spaces consists of 128 segments, and each segment can be up to 64K
bytes. Different routines of a program can
reside in different segments, and different data
sets can reside in different segments. The
28010 Memory Management Unit translates
these logical addresses into physical-memory
locations.

2048·0206

Long Offset
and Short
Offset
Addressing

When a segmented address is stored m
memory or in a register, it occupIes two
16-bit words as previously deSCribed for the
PC and PSAP. This is a consequence of the
large addressing range. When a segmented
address is part of an instruction in the Direct
Address and Indexed Address Modes, there
are two representations: Long and Short Offset
addressing.
In the general unrestricted case of Long Offset, the segmented address occupies two
words, as described before. The most SIgnificant bit in the segment word is a 1 in thIS case.
The Short Offset Mode squeezes the segment
number and offset into one word, saving pro-

gram sIze and execuhon hme. Smce 23 bIts
obviously don't ht mto a 16-blt word, the 8
most slgnlhcant bIts of the offset are omItted
and Implied to be zero. The most slgnihcant
bit of the address word IS made 0 to mdICate
Short Offset Mode. Short Offset addresses are
thus limIted to the hrst 256 bytes at the begmning of each segment. ThIs may appear to be a
severe restnchon, but It IS very useful,
especIally m the Index Mode, where the mdex
register can always supply the full 16-blt range
of the offset. Short Offset saves one mstruchon
word and speeds up execuhon by two clock
cycles m Direct Address Mode and three clock
cycles m Indexed Mode.

Using the
Z8010 Memory Management Unit

The Z8001 CPU can be combined with
another 48-pin LSI device-the Z8010 MMUfor sophisticated memory management. The
MMU provides address translation from the
logical addresses generated by the Z8001 CPU
to the physical addresses used by the memory.
An address translation table, containmg starting addresses and size mformation for each of
the 64 segments, is stored in the MMU. The
translation table can be written and read by
the CPU using Special 1/0 instructions. The
MMU thus provides address relocation under
software control, making software addresses
(i.e., logical addresses) independent of the
physical memory addresses.
But the MMU provides much more than
address relocation; it also monitors and protects memory access. The MMU provides a
Trap input to the CPU and-if necessary-an
inhibit signal (SUP) to the memory write logic
when specific memory-access violations occur.
The MMU provides the follOWing types of
memory protection:

Multiple MMUs must be used when more
than 64 segments are needed. Thus, to support
the full complement of 128 segment numbers
prOVIded for each Z8001 CPU address space,
two MMUs are reqUIred. The MMU has been
designed for mulhple-chlp conhgurations, both
to support 128-segment translahon tables and
to support multiple translahon table systems.
Note that the memory management features
do not mterfere with the abIlity to directly
address the enhre memory space. Once programmed, the MMU (or MMUs) translates and
mOnitors any memory address generated by
the CPU.
The MMU contams status bIts that descnbe
the hIstory of each segment. One bit for each
segment indicates whether the segment has
been accessed; another bIt indIcates whether
the segment has been wntten. ThIS IS Important
for certam memory management schemes. For
example, the MMU indICates whICh segments
have been updated and, therefore, must be
saved on dIsk before the memory can be used
by another program.
When translatmg logIcal addresses to physIcal memory addresses, the MMU must do the
follOWing: access ItS internal 64 x 32-bit RAM,
usmg the segment number as the address, then
add the 16 bIts of RAM output to the most
slgnlhcant address byte (ADs-AD15) and fmally place the result on ItS Address outputs. The
least SIgnificant byte (ADo-AD7) bypasses the
MMU.
.
The mternal RAM access hme IS approxImately 150 ns. Throughput delay IS aVOIded by
making the segment number avallable early:
SNo-SN7 are output one clock penod earlier
than the address mformatlOn on ADo-AD7.
In summary, the Z8000 CPU supports
sophlshcated memory management through
such archItectural features as the Status Lines,
the R/W and SIN lmes, Segment Trap mput
lme, and early output of segment numbers.

• Accesses outside the segment's alloted
memory can be prevented.
• Any segment can be declared mvalid or
non-accessable to the CPU.
• Segments can be declared Read Only.
• By designating a segment as System Only,
access can be prohibited during the Normal
Mode.
• Declaring a segment Execute Only means It
can be accessed only durmg mstruction
access cycles. Data or stack use is prohibited.
• Any segment can be excluded from DMA
access.
• Segments can have a DIrection And Write
Warnmg attnbute, which generates a trap
when a write access IS made in the last 256
bytes of its size. ThIS mechanism can be
used to prevent stack overflow.

50 i

N

CO

g...

N

..,
=
'".I
~

i==...

I»

Using 16K
Dynamic
RAMs with
the Z8DDI

Z8000 systems usually implement most of
their memory with 16K x I-bit dynamic RAMs
that have time-multiplexed addresses (Zilog
also manufactures this device-the Z6116).
In Z8001-based systems with MMUs, CPU
Address/Data lines AD1-AD7 supply row
addresses, MMU address outputs As-AI4 supply column addresses, and MMU outputs
A15-A23 are decoded to generate Chip Select
signals that gate either RAS or CAS or both.
Gating RAS reduces power consumption
because all non-selected memories remain
in the standby mode. But this technique

requires that HAS must wait for the availability
of the most significant address bits from the
MMU. During refresh, the RAS decoder must
be changed to achvate all memories
simultaneously.
Gating CAS does not achieve lower power
consumption; however, this technique allows
the use of slower memories because RAS can
be activated as soon as the CPU address outputs are stable, without waiting for the MMU
delay. Also, there is no need to change the
CAS decoder during refresh.

Data Types
and
Instructions

The Z8000 architecture directly supports
bits, digits, bytes, and 16- or 32-bit integers as
primitive operands in its instruction set. In
addition, the rich set of addressing modes supports higher-level data constructs such as
arrays, lists and records. The Z8000 also intro-

duces a number of powerful instructions that
extend the capabilities of microprocessors. The
remaining sections of this paper describe
Z8000 data types, addressing modes, and a
selection of novel instructions.

Data Types

Operands are I, 4, 8, 16, 32, or 64 bits, as
speCified by the instruction. In addition,
strings of 8- or 16-bit data can be manipulated
by single instructions. Of parhcular interest
are the increased precisions of the arithmetic
instructions. Add and Subtract instructions can

operate on 8-, 16-, or 32-bit operands; Multiply instructions can operate on 16- or 32-bit
multiplicands; and Divide instructions can
operate on 32- or 64-bit dividends. The Shift
instructions can operate on 8-, 16-, and 32-bit
registers.

Addressing
Modes

The rich variety of addressing modes offered
by Z8000 architecture includes: Register,
Immediate, Indirect Register, Direct Address,
Index, Relative Address, Base Address, and
Base Index. Three are of particular interest
with respect to high-level data structures:
Indirect Register, Base Address, and Base
Index. These modes can be used for lists,
records, and arrays, respectively.

is useful, for example, in accessing fields
within a record whose format is fixed at compile time.

Indirect Register. In this addressing mode,
the contents of the register are used as a
memory address. This mode is needed
whenever special address arithmetic must be
performed to reference data. Essentially, the
address is calculated in a register and then
used to fetch the data. For example, this mode
is useful when manipulating a linked list,
where each entry contains a memory pointer to
the memory location of the next entry. Essentially, the pointer is loaded into a register and
used to access the next item on the list. When
the list item is large or has a complex structure, the Base Address or Base Index Modes
can be used to access various components of
the item.
Base Address. In this addressing mode, the
memory address contained in the register (the
base) is modified by a displacement in the
instruction (known at compile time). This mode

.'

508

Base Index. The memory address in this
addressing mode is contained in a register (the
base) and is modified by the contents of
another register (the index). This mode can be
useful in accessing the components of an
array, because the index of the component is
usually calculated during execution time-as a
function of the index of a DO-Loop, for
example.
Index vs. Base Address. In the Z8002 and in
the Z8001 running non-segmented, these two
addreSSing modes are functionally equivalent,
because the base address and displacement
are both 16-bit values.
When the Z8001 runs segmented, there is a
difference: in the Index mode, the base
address (including the segment number) IS
contained in the instruction, In either Short
Offset or Long Offset notation. The 16-bit displacement stored in a register IS then added to
the offset in the base address to calculate the
effective address. In the Base Address Mode,
on the other hand, the 16-bit displacement is
speCIfied in the Instruchon and is added to the
offset of the base address that is stored in a
long-word register.

The Instruction Set

The Z8000 offers an abundant instruchon set
that represents a major advance over its
predecessors. The Load and Exchange Instructions have been expanded to support operating
system functions and conversion of existing
microprocessor programs. The usual Arithmehc instructions can now deal with higherprecision operands, and hardware Multiply
and Divide instructions have been added. The
Bit Manipulation instruchons can access a
calculated bit position within a byte or word,
as well as specify the position statically In the
instruction.
The Rotate and Shift instructions are considerably more flexible than those in previous
microprocessors. The String instructions are
useful in translating between different
character codes. Special I/O Instructions are
included to manage peripheral devices, such
as the Memory Management Unit, that do not
respond to regular I/O commands. Multipleprocessor configurahons are supported by
special Instructions.
The following instructions exemplify the
innovative nature of the Z8000 instruction set.
A complete list of Z8000 instructions can be
found in the reference materials listed at the
end of this tutorial.

Multiply (MULT) provides signed (two's complement) multiplicahon of two words, generating a long-word result; or of two long-words
generahng a quadruple word result. No byte
mulhply exists because It IS rarely used and,
after sign extension, can be performed by a
word multiply.
Divide (DIV) provides signed (two's complement) diVision of a long word by another word,
generating a word quotient and a remainder
word; or of one quadruple-word by a longword, generating a long-word quotient and
long-word remainder.
Both Mulhply and Divide use a conforming
register assignment. That is, a multiply followed by a diVide on the same registers IS
essenhally a no-op. The register designation
used in the operation description must be even
for word operations and must be a multiple of
four for long-word operations.

Logical Instructions.
Test Condition Code (TCC) performs the same
test as a Jump instruchon, but affects the least
Slgmficant bit of a specified register instead of
changing the PC.

Program Control Instructions.
Load and Exchange Instructions.
Exchange Byte (EX) is prachcal for converting
Z-80, 8080, 6800 and other microprocessor
programs into Z8000 code, because the Z8000
uses the opposite assignment of odd/even
addresses In 16-bit words.
Load Multiple (LDM) saves n registers and is
useful for switching tasks.
Load Relative (LDR) loads fixed values from
program space into data space.
Arithmetic Instructions.
Add With Carry and Subtract With Carry
(ADC, SBC) are conventionally used in 8-bit
mICroprocessors for multiprecision arithmetic
operations. These instructions are rarely used
with the Z8000 CPU because it has 16- and
32-bit arithmetic instructions.
Decrement By N and Increment By N (DEC,
INC) are intended for address and pointer
manipulation, but can also be used for QUick
Add/Subtract Immediate with 4-bit nibbles.
The flag setting is different from Add/Subtract
instructions-as is conventional-in that the
Carry ,and Decimal adjust flags are unaffected
by the Increment and Decrement instructions
to support multiple precision arithmetic.
Decimal Adjust (DAB) automatically generates
the proper 2-digit BCD result after a byte Add
or Subtract operation, and eliminates the need
for special deCimal arithmetic instructions.

Call Relative (CALR) is a shorter, faster version of Call, but with a limited range.
Decrement And Jump If Non-Zero (DJNZ) is a
one-word basic looping instruchon.
Jump Relative (JR) is a shorter, faster versIOn
of Jump, but with a limited range.

Bit Manipulation Instructions.
Test Bit, Reset Bit, Set Bit (BIT, RES, SET) are
available in two forms: stahc and dynamiC. For
the static form, any bit (the position is defined
In the immediate word of the instruchon)
located in any byte or word in any register or
in memory can be set, reset or tested (inverted
and routed mto the Z flag).
For the dynamic form, any bit (the position
is defmed by the content of a register that is,
in turn, spec!fied In the instruction) located in
any byte or word in any register, but not in
memory, can be set, reset or tested.
Test And Set (TSET) IS a read/modify/write
mstruchon normally used to create operating
system locks. The most slgmflcant bit of a byte
or word in a register or In memory IS routed
into the S flag bit and the whole byte or word
IS then set to all Is, Durmg this Instruction, the
processor does not relinquish the bus.
Test Multi-Micro Bit and Multi-Micro
Request/Set/Reset (MBIT, MREQ, MSET,
MRES) are used to synchronize the access by
mulhple mICroprocessors to a shared resource,

509

The Instruction Set
(Continued)

such as a common memory, bus, or I/O
device.
Note that the instruction MREQ (MultiMicroprocessor Request) has nothing whatsoever in common with the MREQ (Memory
Request) output from the Z8000 CPU.

Rotate and Shift Instructions.
The Z8000 CPU has a complete set of shift
instructions that shift any combination of bytes
or words, right or left, arithmetically or logically, by any meaningful number of positions as
specified either in the instruction (static) or in
a register (dynamic).
The CPU also has a smaller repertoire of
rotate instructions that rotates bytes or words,
either right or left, through carry or not, and
by one bit or by two bits.
The instructions Rotate Digit Left and Rotate
Digit Right (RLDB, RRDB) rotate 4-bit BCD
digits right or left, and are used in BCD arithmetic operations.
Block Transfer and String Manipulation
Instructions.
Translate And Decrement/Increment (TRDB,
TRIB) is used for code conversion, such as
ASCII to EBCDIC. These instructions translate
a byte string in memory by substituting one
string by its table-lookup equivalent. TRDB
and TRIB execute one operation and decrement the contents of the length register; thus
they are useful as part of loop performing
several actions on each character.
Translate, Decrement/Increment and Repeat
(TRDRB, TRIRB) are the same as TRDB and
Biliography

510

Selected Publications on the Z8000 Family
Z8001lZ8002 CPU Product Specification
(00-2045)
Z8000 CPU Instruction Set (03-8020-01)

TRIB, except they repeat automatically until
the contents of the length register become
zero. They are therefore useful in straightforward translation applications.
Translate And Test, Decrement/Increment
(TRTDB, TRTIB) tests a character according to
the contents of the translation table.
Translate And Test, Decrement/Increment And
Repeat (TRTDRB, TRTIRB) scans a string of
characters. The first character is tested and,
depending on the contents of the translation
table, the process stops or skips to the next
character. Stopped characters can be used for
further processing.

110 and Special 110 Instructions.
The Z8000 CPU has two complete sets of I/O
instructions: Standard I/O and Special I/O.
The only difference is the status information on
the STo-ST3 outputs. Standard I/O instructions
are used to communicate with Z-Bus compatible peripherals. Special I/O instructions are
typically used for communicating with the
Memory Management Unit.
Both types of instructions transfer 8 or 16
bits and use a type of 16-bit addressing
analogous to the Z8002 memory-addressing
scheme: For word operations, Ao is always
zero; in byte-input operations, Ao is used
internally by the CPU to select the appropriate
byte; in byte-output operations, the byte is
duplicated III the hIgh and low bytes of the
address/data bus, and external logic uses Ao
to enable the appropriate output device.

Z8000 PLZIASM Assembly Language
Programming Manual (03-3055-01)
Z8010 Z-MMU Product Specification (00-2046)

00-2048-A

An Introduction to the
Z8010 MMU Memory
Management Unit

~

Tutorial
Information

Zilog

June 1982

Introduction

The declining cost of memory, coupled with
the increasing power of mIcroprocessors, has
accelerated the trend in mICrocomputer
systems to the use of high-level languages,
sophisticated operating systems, complex programs and large data bases. The 28001 mIcroprocessor supports these advances by offering
multiple 8M byte address spaces as well as a
rich and powerful instruction set. The 28010
Memory Management Umt (MMU) supports the
28001 processor in the efficient and fleXIble
use of Its large address space.
Support for managing a large memory can
take many forms:
• Providmg a logical structure to the memory
space that is largely independent of the
actual physical locahon of the data
• Protecting the user from madvertent
mIstakes such as attemptmg to execute data

Motivations
for Memory
Management

The pnmary memory of a computer IS one of
ItS major resources. As such, the management
of thIS resource becomes a major concern as
demands on It mcrease. These demands can
anse from dIfferent sources, three of whIch are
of mterest m the present context. The hrst
stems from multIple users (or mulhple tasks
wlthm a dedIcated apphcahon) contending for
a hmlted amount of phYSIcal memory. The
second comes from the deSIre to mcrease the
mtegnty of the system by hmltmg access to
vanous porhons of the memory. The fmal
source anses from Issues surroundmg the
development of large, complex programs or
systems. Each of these three sources mvolves a
mulhfaceted group of related Issues.
When mulhple tasks conshtute a given
system (for example, mulhple users of a system
or mulhple sub-tasks of a dedIcated apphcahon), the posslblhty eXIsts that not all tasks
may be m pnmary memory at the same hme.
(A task IS the actIOn of executmg a program on
ItS data; a task may be as SImple as a smgle

• Preventing one user from unauthorized
access to memory resources or data

I:

• Protechng the operatmg system from unexpected access by the users.
The 28010 provides all these features plus
addihonal features that permit a variety of
system hardware conhgurations and system
designs.
ThIS paper exammes the various uses of
memory management m computer systems and
how memory management techniques generally meet these requirements. The major
features of the 28010 MMU Illustrate how
memory management funchons can be supported by hardware. A few examples demonstrate how thIS LSI cIrcuit can be used to
configure several different memory management systems.
procedure or as complex as a set of related
routmes.) If the populahon of memory-resident
tasks can vary over hme, a useful feature of a
system would be the ablhty for a task to re8ide
anywhere m memory, and perhaps in several
different locations durmg its hfetime. Such
tasks are called relocatable, and a system in
whICh all tasks are relocatable generally offers
greater flexibdlty in respondmg to changing
system envIronments than a system m which
each task must reside in a hxed location.
A second Issue that arises m multi-task
envIronments IS that of sharmg. Separate tasks
may execute the same program on different
data, and may therefore share common code.
For example, several users compIling FORTRAN programs may WIsh to share the compIler rather than each user havmg a separate
copy m memory. Alternahvely, several tasks
may WIsh to execute different programs using
the same data as mput, and It may be pOSSIble
for these tasks to access the same copy of the

511

c
c

~

II
II
CI

~

i...

!!.

Motivations
for Memory
Management

(Contmued)

The Fundamentals of
Memory
Management

512

input. For example, a user may wish to print a
PASCAL program while it is being compiled;
the print process and the compiler process
could access the same copy of the text hIe.
A third issue in multi-task systems is protecting one task from unwanted interactions with
another. The classic example of unwanted
interaction is one user's unauthorized reading
of another user's data. Prohibiting all such
interactions confhcts with the goal of sharing
and so this issue is usually one of selectively
prohibiting certain types of interachons. The
issue of protecting memory resources from
unauthorized access is usually included m the
larger set of issues relating to system integrity.
System integrity takes many forms m addihon to protecting a task's data from unwanted
access. Another aspect is preventmg user tasks
from performmg operating system functions
and thereby interruptmg the orderly dispatch
of these tas~s. For example, most large systems
prevent a user task from dIrectly imhating I/O
operations because thIs can disrupt the correct
funchoning of the system.
Another aspect of separating users from
system functIOns relates to separatmg system
1/0 transfers from user tasks, especially with
respect to error conditions. For example, an
error during a direct memory access, say to a
nonexistant memory locatIOn, should not cause
an error in the program that IS currently
executing.
A final example of increasmg the system
integrity is protecting a user task from itself.
Obvious errors, such as trymg to execute data
or overflowing an area set aside for a stack,
can be detected whIle a program is executing
and handled appropriately, provIded the
system is gIven sufhclent mformahon.
The nohon of protecting an executmg task
from performing certain types of actIOns known
to be erroneou~ introduces a third general
motivation for memory management, namely
support for the design and correct implementation of large, complex programs and systems.

Protecting a task from itself obvIOusly helps in
debugging a large program, but there are
other system features that can aid in developing complex systems. Modern methodology for
developing large systems dICtates partitioning
a task into a number of small, simple, selfcontained sub-tasks with well defined interfaces. Each sub-task generally interacts with
only a few other sub-tasks and this communication IS carefully controlled. This methodology
promotes a systems design that can be readily
modified, but it also tends to promote the creahon of a large number of nearly mdependent
sub-tasks and many data structures accessIble
to only one or a few of these sub-tasks.
Because modern systems are mcreasingly
driven to support many interacting tasks,
possibly written and compIled separately, they
must also enforce some commumcation protocol wIthout sacrificing efficient operation.
Modern memory management systems can
offer effective tools for implementing large
systems designed using this methodology.
In summary, the major goals of memory
management systems are to:

Memory management has two funchons:
the allocation and the protection of memory.
DynamIC relocation of tasks dUring their
execution IS accomplished by an address
translation mechamsm. The restriction of
memory access is accomplished by memory
attribute checking. Both operations occur WIth
each memory request during the execuhon of a
program and both are transparent to the user.
Address translation simply means treating
the memory addresses generated by the program as logical addresses to be mterpreted or
translated mto actual phYSICal memory locahons before dispatchmg the memory access
requests to the memory umt. Memory attribute
checkmg means that each area of memory has
associated WIth it information as to who can

access it and what types of access can be made
by each task. Each memory reference IS
checked to msure that the task has the right to
access that locahon m the gIven fashion (for
example, to read the contents of the locahon or
to write data to that locahon).
Instead of a linear address space, more
elaborate memory management systems have a
hIerarchical structure m which the memory
consIsts of a collection of memory areas, called
segments. Access to thIS structured memory
requires the specihcation of a segment and an
offset wlthm that segment. Thus, mstead of
speclfymg memory locahon 1050 m a Imear
address space, a task speclhces memory location 5 m segment number 23, for example.

• Provide flexible and efficient allocation of
memory resources during the execution of
tasks
• Support multiple, independent tasks that
can share access to common resources
• Provide protechon from unauthorized or
unintenhonal access to data or other
memory resources
• Detect obviously incorrect use of memory by
an executing task
• Separate users from system functions.
Most of today's memory management systems
support these functions to some degree. The
extent of this support is largely a question of
resources to be devoted to these funchons and
the understood demands of the intended
apphcations for these systems.

The Fundamentals of
Memory
Management

(Continued)

Generally, segments can be of variable size,
within limits, and a user can specify the size of
each segment to be used. Thus one user may
have two segments of two thousand and ten
thousand words for his FORTRAN program and
data, respectively, while another user might
have three segments of three thousand, six
thousand and two thousand words for her
PASCAL program, data, and run-lime stack. If
the first user called his data segment number
5, then the first word m his data set would be
accessed by the logical address (5,0) mdicatmg segment 5, offset O. The memory management system translates this symbolic name
mto the correct physical memory address.
Figure I gives a conceptual realizalion of
these two users' logical program spaces. The
first user, User A, has his program segment
called "Segment 6" and his data segment
called "Segment 5." The second user, User B,
has her program segment called "Segment 5,"
her data segment called "Segment 12" and her
stack segment called "Segment 2." Nolice that
both users have named one of their segments
"Segment 5," but they refer to different entities. This causes no problem since the system
keeps the two memory areas separate. The
sltualion is analogous to both users having an
integer variable called "I" in their programs:
The system realizes that these are two separate
variables stored in different memory localions.
User A's data segment, "Segment 5," IS ten
thousand words. If he references word 10,050

of Segment 5 he gets an error message from
the system mdicaling that he has exceeded the
allocalion limit for Segment 5. Note that he
does not access word 50 of Segment 6. That is,
segments are logically distinct and unordered.
A reference to one segment cannot inadvertently result in access to another segment.
Thus, in this example, User A is prevented
from accidentally (or deliberately) accessing
hiS program as though It were part of his data
segment.
Figure 2 illustrates one way that these
segments could be arranged in the physICal
memory. The dotted lines mdicate the
memory-mapping function from the logiCal
address space of the user to the physical memory locations allocated to him.
The figure also indicates the access attributes associated with each user's segments.
For example, program segments are "execute only" and data segments are "reac:l!
write." Thus a user is prevented from executmg a data segment or writmg into a
code segment.
LOGICAL ADDRESS SPACE

PHYSICAL
MEMORY

EXECUTE
ONLY

--,,

,,
"-

,

,
,

USER A

,

I
I

"

/
/

,,

,

USERS

SEG 5
PROGRAM

SEG 12
DATA
SEG 2
STACK

Figure I. Two User's Logical Address Space
20490075, 0076

Figure 2. Mapping Logical Segments to Physical Memory

513

The FundaFigure 3 illustrates what happens when
mentals of
both users have access to the same data
set m primary memory, say the results of a
Memory
Management questionnaire that both intend to analyze.

(Continued)

Each user has a logical name associated
with that data set to specify the segment in
which the data set is to reside. Note that the
two users have chosen to put the data set in
different segments of their personal address
spaces. The system-mapping function translates these different segment names to the
same physical memory locations. Thus User
A's access to address (2, 17) references the
same physical memory location as User B's
access to address (7, 17). In the figure, note
that two of B's segments have been moved in
physical memory to create a space large
enough to hold the questionnaire data.
Another topic in memory management that is
supported by Z8001-Z801O architecture but
reqUIres additional support hardware is
demand swappmg, or segmented virtual
memory, which means that the logICal memory

Figure 3. Two Use" SharlDg a CommOD SegmeDI

514

area may not actually reside in physical
memory until a task actually tries to access it.
At the time an access is made to a segment
missing from physical memory, the mstruction
execution IS held m abeyance until the logical
memory can be brought mto the physical
memory and then the instruction is allowed to
proceed with the memory access. The address
translation IS performed, access protection is
checked and the instruction proceeds as If the
logical memory area had been in the physical
memory at the beginnmg of the instruction.
The instructions in the Z8001 must run to completion before the CPU can perform any
action, such as respondmg to a misSing segment trap. But with the conjunction of hardware and software to simulate the above functions, a segmented virtual memory scheme can
be implemented.
A final topic in memory management IS
pagmg, which IS another method for partitioning a user address space and mapping it onto
the physical memory. Pagmg IS most effective
when demand swapping can be supported.
Essentially, paging diVides the logical memory
mto fixed-size blocks, called pages. Like
segments, the individual pages can be located
anywhere in the phYSICal memory and a
translation mechanism maps logical addresses
to physical memory locations. There are two
differences between paging and segmentmg a
logical memory. First, pages are of fixed size
whereas segments are of various sizes. Second,
under pagmg, the logical memory is still
linear, that is, a task accesses memory using a
single number, rather than a pair as in
segmentation. The major advantage of paging
is in treating memory as blocks of fixed sizes,
whICh Simplifies allocating memory to users
and deciding where to place the logical pages
in phYllical memory. The major disadvantage
of pagmg is in asslgnmg different protection
attributes to different areas in a user address
space because a paged memory appears
homogeneous to the user and the operating
system. Paging can be combined with segmentation to produce a memory management
system with the advantages of both paging and
segmentation. The implementation of paging
for the ZSOOI requires additional support hardware and may be implemented independent of
the ZSOlO.
Before proceeding to the mechanism of
memory management, it is instructive to review
how a segmented address translation
mechanism with protection attributes achieves
the five major goals of memory management
outlined in the previous section. The first goal
permits dynamic allocation of memory during
the execution of tasks; that is, a task could be
located anywhere in memory and even moved
about when its execution is suspended. The
address translation mechanism proVides this
flexibility because the task deals exclusively
2046-0077

The Fundamentals of
Memory
Management

(Continued)

with logical addresses and hence is independent of the addresses of the physical memory
locations It accesses. Movmg the task to different physical memory locations requires that
the address mapping function be changed to
reflect the change in memory location, but the
task's code need not be modified. Of course,
this flexibility does incur the price of managing the various system tables required to
implement memory management.
The second goal supports sharing of common memory areas by different tasks. This is
accomplished by mapping different logical
areas in different tasks to the same physical
memory locations.
The third provides protection agamst certain
types of memory accesses. This is accomplished by associating accessing attributes with
each logical segment and checking the type of
access to see if each access IS permitted.
The fourth goal detects obvious execution
errors related to memory accessing. This can
be accomplished by checking each access to a
segment to see whether the address falls within
the allocated physical memory for that segment. It could also include affixmg a
reael/wrlte attribute to data to prevent a task
from trying to execute a data segment, and
affixing an execute-only attribute to code
segments to prevent a task from trying to read
or write data to this segment. Additionally, if a
segment is used for a stack, the system could
issue a warning to a task when the stack
approaches the allocated limit of the segment.
The task could then request more memory for
the stack before the stack overflows and
creates a fatal error.
The final goal listed for memory manage-

The MeehanEssenlially there are four Issues in impleies of Memory menting a memory management system: how
Management addresses are specified, how these addresses

are translated, what attributes are checked for
each access, and how the protection mechanism is implemented. Some of the major alternatives in each of these issues are briefly
discussed here, primarily from the point of
view of a segmented memory.
Two approaches have traditionally been
taken for specifying addresses in a segmented
memory. For Simplicity, only addresses in
instructIOns are discussed. The first way
puts all the addressing information in the
instruction itself. That is, each memory address
in an instruction contains both the segment
name and the offset within the segment. The
alternative sets aside speCial registers that contain some of this information, for example the
segment name or the address in physical memory where the segment reSides.
The advantage of the latter approach lies m
the fact that fewer bits are needed m an
instruction to specify addresses. Thus programs may be shorter. Also, because there is

ment systems separates user functions from
system functions. For processors that distinguish between System mode and User mode
of operation, this goal can be accomplished by associating a system-only attribute
with system segments so users cannot directly
access system tables and tasks.
As a final point, it should be noted how
segmentation can be used to support the
development and execution of large, complex
programs and systems. The concept of segmentation corresponds to the concept of partitioning a large system into procedures and data
structures where each procedure and data
structure can be associated With a separate
segment. A task can then mvoke a procedure
or sub-task or access a data structure by referring to its logical segment name. Access to
these objects can be individually restricted by
usmg the protection-checking mechanism of
the memory management system.
As a specific example of how segmentalion
could be used in the design of a large system,
consider a multi-user interactive BASIC system
with a large data base shared by all users.
Such a system could be designed with
segments 0 through 15 reserved for system
use, segments 16 through 31 reserved for the
BASIC interpreter and its internal tables,
segments 32 through 63 allocated to user tasks
and segments 64 through 127 reserved for portions of the data base when they are in primary
memory being accessed by users. For this
system, segments 0 through 31 would probably
always be in memory; the other segments
would be assigned as needed and the memory
they require allocated dynamically.

reduced traffiC between the memory and the
processor for fetching shorter instructions, a
program may execute faster.
On the other hand, these speCial registers
must be manipulated to access more segments
than there are registers, and this manipulation
adds to the number of instructions, the program size and the execution time. In praclice,
these can destroy the advantages described
above. If the special registers contain physical
memory locations, then these must be protected from user access to maintain the integrity of the system, and changing segments
requires system calls whICh can be time consuming If too few registers are supplied. The
Z8001 architecture speCifies the complete
logICal address in the instruction.
Address translation is performed by adding
the logICal segment offset to the memory location where the segment begins. Thus, when an
address of the form (a, b) IS presented to the
translation mechanism, the segment name "au
IS used to determine where segment "au
reSides in memory. Assume that it resides in
locations 10000 to 25000. Then the actual
515

The Meehan-

memory location of (a, b) is memory location
ies of Memory 10000 + b. The major option in implementing
Management this type of address translation is in determin(Continued)
ing the segment location In physical memory.
When special registers have been set aside to
contain the starting location of the segment
instead of putting all address information in
the instruction, the addressing mechanism is
similar to using the segment register as an
index register or a base register.
When logICal addresses are either completely specified in the instruction or when the
special register contains the symbolic segment
name, a table must be used to translate the
logical segment name Into a physICal memory
location. The table may have an associative
capability, that is, the segment name is
presented to the table and the device returns
the physical memory location where the segment begins. Alternatively, the table could
have one entry for every possible segment
name. The Z8010 implementation of the
address translation table sets aside a specific
table entry for each logical segment name.
A number of attrIbutes can be assoCIated
with a segment and checked during each
access. One of these is the allocated length of
the segment, and each access is checked to
see if it falls within the bounds of the segment.
The Z8010 provides hmit checking.
Another type of attrIbute deals with ownership or class of ownership: tasks are grouped
into classes and only those in certain classes
are permitted access. The simplest example is
the system versus user classification, where
tasks are either one or the other and this determines whether or not any type of access can
be made to the segment. The Z80 10 has this
feature-users are prevented from accessing
system segments.
Other types of attributes that can be
associated with a segment involve modes of
accessing, for ~xample read only, read/write
or execute only. For these attrIbutes, the processor must indICate the type of access to be
made, be it code fetch, read from memory,
write to memory, etc. The Z8001 indicates
when It IS fetching code, reading or wrJting
data, or performing stack operations, and thus
the Z8010 can offer protection for these opera-

tions. The other Issue with respect to attributes
is whether they are permissive or prohibitive.
That is, whether the attribute is in the form of
"write to this segment is permitted" or of the
form "write to this segment is prohibited." The
Z8010 adopts the approach of specifying attributes that prohibit certain types of accessing.
The final issue in the mechanics of memory
management systems is the implementation of
the protection attributes. These may be
associated either with the logical address
space or with the physical memory itself. The
IBM 360 series, for example, places the
memory protection information with the
physical memory itself. Thus the processor
generates a memory address and the memory
module checks to see If the access is permitted. The main difficulty with this approach is
in the lack of flexibility, because protection is
associated with fixed memory partitions. Also,
sharing memory IS cumbersome because each
user IS given a protection key to match the
memory key; thus both users must have the
same access key or a umversal access key.
Associating access attributes with the logical
segment permits a versatile memory management scheme because different users can
access the same segment and have different
access attributes associated with their accessIng. The Z8010 Implements access attributes
using the segment mapping information.
Other information associated with each segment does not pertain to the protection
mechamsm but can be of use to the memory
management system. This information generally relates to the history of the segment; for
example, whether a segment has been
modified while resident in primary memory. If
It has not been modified and the system
requires the memory for another segment, the
memory can be freed immediately; otherwise,
the updated version of the segment must be
stored in secondary memory and the primary
memory IS not available until the segment has
been saved. Although not strictly necessary,
such information can improve the performance
of the memory management system. The Z8010
collects information on segment usage, and
this Information can be used to enhance performance of systems that use this device.

The Z8001 CPU generates segmented
addresses consisting of a 7-bit segment number
Management and a 16-bit segment offset address. In addiUnit
tion, the CPU generates status signals indicating its current mode of operation (such as
Instruction Fetch, Data Memory Reference,
Stack Memory Reference, and Internal Operation), whether it IS performing a Read or a
Write Memory Reference and whether it is In
Normal (User) or System Mode. The Z8010
Memory Management Unit uses this information to perform its memory management functions. This section describes the Z8010 MMU in

some detail, beginning with the translation
procedure and continuing with a description of
the internal registers of the ChiP' The section
concludes with a description of the system
commands that alter the contents of these
registers.
The Z8010 MMU has three functional states.
The first is the memory management state:
when a logical address IS presented to the unit,
the MMU checks the access to insure its validIty and translates the logICal address to a
physICal memory location. The second state is
a command state: when a special IIO instruc-

The Z8010

Memory

516

The Z8010
Memory
Management
Unit

(Continued)

tIon is Issued to the MMU, such as readmg or
writmg one of Its mternal registers, the MMU
responds to the command as appropnate. The
third state IS a qUiescent state: when the CPU
issues an I/O mstructIon or a refresh cycle, the
MMU address lines remam 3-stated.
The mputs to the MMU are the Address/Data
Imes (A/D Imes), Segment Number Imes, Bus
Status and Timing Lmes, and special control
Imes for chip selectIon and DMA. The outputs
from the MMU are Address Imes, a Segment
Trap line and a Suppress Ime (Figure 4). During address translatIon and access protection,
logical addresses are presented to the MMU on
the Segment Number and Address/Data Imes;
the MMU puts the translated physical memory
locatIon on its Address Imes and, If appropnate, activates the Segment Trap and/or Suppress lines.
Segment Trap IS a special type of synchronous mterrupt for the Z8001 CPU; Suppress aborts the memory access. In the command state, the MMU receIVes commands on
the A/D Imes; data to be read from or wntten
into the MMU IS also placed on the A/D Imes.
The MMU selects whICh of the three states It
Will be m according to the status information
on the Bus Status Imes dunng the mltlal clock
cycle of an mstructIon or DMA cycle. The
MMU performs address translation durmg a
memory reference for either a regular mstructIon or a DMA request. Only I/O instructIOns
(eIther regular or speCial), memory refresh and
reserved bus status states cause the MMU to
cease performmg memory address translatIons
and enter another state.
The MMU uses the segment number to
access an mternal table of segment descnptor
registers, each register contaming the startmg
memory location of the segment (called the
base address), the segment's hmlt (used to
determine the range of legal address offsets)
and the types of accesses permitted to that
segment.
Physical memory for segments IS allocated m
blocks of 256 bytes. The eight least slgmficant
bl ts of the base address are all zero and are
not stored m the Segment Descriptor Register.
Also, smce the eight low-order bits of the segment base are always zero, the eight low-order
bits of the segment offset need not participate
6

I

_AD"
........... AOt4

.......... AD13

ADDRESSI
DATA BUS

{

.......... A012
AD11
ACto

.......... ADg
.......... ADs

PHYSICAL

ADDRESS

%8010

MMU

SEGMENT
TRAP
DMA/SEGMENT

BUSTIMINQ {

SUPPRESS
~

DMASYNC

_AS
_
-os

CHIP SELECT ----.

cs

+5 V

GND eLK RESET DECOUPLE

Figure 4. Z8010 MMU Pin Functions

m the additIon of the base address to the offset. Rather, they can be Juxtaposed to the
result of addmg the high-order byte of the offset to the most slgmficant 16 bits of the base
address.
ThiS process IS Illustrated m Figure 5. Note
that the low-order eight bits of the offset are
not used by the MMU. Figure 6 goes through
an example of mappmg the logical address
(5, 1528) to a phYSical memory locatIOn when
segment 5 begms at locatIon 231100.
Figure 6a Illustrates the full addlhon to be
performed durmg address translation. The segment number 5 selects Segment Descnptor
Register 5 m the MMU. The base address held
m thiS register contams 2311 which corresponds to a base address of 231100. The offset,
1528, IS then added to 231100 to produce the
phYSICal memory location 232628. Figure 6b
represents the same logical procedure, but
Illustrates the actual operation of the MMU.
Agam segment number 5 IS used to select the
base address. However, only the high-order
byte of the offset IS added to the contents of the

15

SEGMENT NUMBER

0

O_F.J..~S_ET_ _ _ _ _ _ ____'llOGICAL ADDRESS

L.1_ _ _ _ _ _ _ _

~123_______________ I

..,8 7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

•

BASE ADDRESS

~

STARTING ADDRESS

~.l.~.L~J.~.J..~.L~.L~.L~J ?:~~~~~~T

+
23

0

1L.. . .________________.l.-_ _ _ _ _ _ _---'1

PHYSICAL MEMORY LOCATION

Figure 5. Generation of the Physical Memory Location from a Logical Address
2046·0051

2049-0079

517

MMU base-address held: 15 IS added to 2311
to produce the most slgmflcant 16 bits of the
physIcal memory locahon. The low-order byte
of the physIcal locatIOn is the same as the loworder byte of the offset.
The results of the two processes Illustrated m
figures 6a and 6b are the same, but m 6a a
24-blt addlhon IS Imphed whereas m 6b only a
16-blt addlhon IS needed. Also, the low-order
eIght bIts of the offset are not needed by the
MMU and thIS reduces the number of pins
required by the MMU package.
The MMU checks memory references for two
types of trap condlhons. The first type IS an
access vlOlahon. This occurs when a memory
reference IS performed m a mode that is not
allowed by the read-only, execute-only, CPUmhlblt or system-only attnbute of a segment. A
memory reference outsIde the allocated
memory for the segment also conshtutes an
access vlOlahon.
The second type IS a wnte warnmg. ThIS
occurs when a write IS made to the last 256
bytes of a special type of segment (indIcated
by a special attribute flag called the DIrection
And Warmng Flag). These segments are
tYPIcally used for stacks and are therefore
logIcally organized so that successive wntes
(or stack pushes) access lower-numbered
memory locahons. By generatmg a segment
trap request when a write IS performed mto the
lowest-numbered 256 bytes of the memory
allocated for these segments, the MMU IS
slgnalmg that a stack IS m danger of overflowmg. The operatmg system m servICmg thIS
trap can mcrease the memory allocated for the
segment and aVOId a fatal stack overflow
condlhon.
The MMU generates two control SIgnals that
can be used by the system to perform memory
management funchons. Segment Trap Request
IS generated upon the hrst detected occur-

rance of a violation or write warning. Once
asserted, thIS signal remains set until a trap
acknowledge signal is receIved. Only when the
Fatal Flag, a special MMU control flag, is set
will a detected violahon not cause a segment
trap request. This flag is set only when a
second VIOlation IS detected while a prevIOus
trap IS bemg processed and thus indicates that
the system software IS in error.
The other control signal generated by the
MMU IS Suppress. Once a violahon has been
detected, this signal IS asserted on that and
every succeeding memory reference for the
remamder of the mstruction. In particular, I/O
and Special I/O mstructions are checked for
memory access Violations, and once a memory
access violation is detected, subsequent
memory accesses cause Suppress signals to be
generated. I/O addresses, of course, bypass
the MMU and are neither translated nor
checked. Intervenmg DMA cycles and memory
refresh cycles are excephons to thIS rule. Durmg such cycles Suppress IS not asserted unless
a vlolahon is detected during that cycle. Only
DMA can generate a violation; refresh can
never cause a VIOlation. Suppress can be used
by the memory system to mhiblt writes, thus
protectmg the memory from illegal alterations.

MMU
Internal
Registers

There are three groups of regIsters m the
MMU: Segment DeSCriptor RegIsters, Control
RegIsters and Status RegIsters. The Segment
Descnptor RegIsters con tam all the mformahon
relatmg to the address translahon and access
protechon of a parhcular segment. The Con-

trol RegIsters con tam information used to control the vanous funchons of the MMU, mcludmg how to mterpret various signals generated
by the CPU. The Status RegIsters contain all
the mformahon the MMU generates when it
detects an access VIOlation.

Segment
Descriptor
Registers

Because there are 64 Segment Descnptor
RegIsters m the MMU, two MMUs are reqUlred
10 handle all 12S segments that the ZSOOI can
mampulate dIrectly. An MMU IS programmed
to handle e!ther segments 0 through 63 or
segments 64 through 127; the parhcular set of
64 segments m an MMU can be changed usmg
speCIal operatmg system commands. Each Segment Descriptor contams three fields, a 16-blt
Base FIeld, an S-bl! LImIt Field and an S-blt
Attribute Fjeld (FIgure 7). The segment
number of a logIcal address determmes whIch

segment descnptors are used in address
translahon.
The Base Field specifies the starting location
in memory of the segment.
The Llmit Field specihes the segment size in
blocks of 256 bytes. The address offset is compared against the segment hmit and a size
vlOlahon occurs If the offset falls outside the
segment boundanes. A wnte warning occurs If
the destmahon IS m the last block of a segment
bemg used as a stack.

The Z8010

Memory
Management
Unit
(Contmued)

518

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0

5 , 2 , •

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6

0

15

87

0

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a) FULl. ADDITION

23

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b) ADDITION OF HIGH ORDER
BYTES ONLY

Figure 6. Two Methods of Address Translation

2049-0080

Segment
Descriptor
Registers

BASE ADDRESS

LIMIT

(Continued)

BASE FIELD

LIMIT FIELD

v
ATTRIBUTE !'IBLD

Figure 7. A Segment Descriptor

The Attribute Field contains eight flags. Five
flags protect the segment against certain types
of access, one indicates a special orientation of
the segment, and two indicate the types of
accesses that have been made to the segment.
The following brief description explains how
these flags are used.
The Read-Only Flag (RD) indicates that the
only accesses to this segment are reads. Writes
are prohibited when this flag is set. Thus this
flag is a write-inhibit flag; in particular, code
can be executed from a read-only segment.
This flag is useful in protecting data from
being written by unauthorized users. For
example, if one user wants to give another
access to a document that he has created, but
does not want this user to be able to modify it,
the system can set the Read-Only Flag when it
copies the file into the user's address space. If
the data is already in memory (in a read-only
mode). then this same memory area can be
made accessible to that user without another
copy of the document being required.
The System-Only Flag (SYS) indicates that
only accesses made in System Mode are to be
permitted. When this flag is set, accesses in
the Normal Mode are prohibited. This attribute
is useful in protecting system tables and tasks
from being accessed by users. For example,
system I/O routines can be left in the memory
with this flag set and a user is unable to call
them directly. This feature is useful if a system
is designed so that users are given certain segment names and other segment names are
reserved for system use. This flag prevents
users from accessing system segments, even
though they can generate the logical
addresses.
The CPU-Inhibit Flag (CPUl) indicates that
the segment is not to be referenced by the
CPU. When this flag is set, CPU access to this
segment is prohibited, but DMA channels can
access the segment. This flag is useful in
preventing a program from accessing a segment whose data resides on secondary storage
and has not been brought into primary
memory. For example, a user may request the
operating system to read a file from disk into
segment number 19; if the operating system
returns control to the user before the file has
been read, this flag should be set in Segment
Descriptor Register 19.
The Execute-Only Flag (EXC) indicates that
the segment is to be referenced only during
the instruction fetch cycle of the processor.
When this flag is set, access to the segment
during any other cycle of an instruction, for
example during the memory request cycle, is
2049·0081

prohibited. This flag is useful in preventing a
program from making a copy of a proprietary
program. For example, if this flag is set for a
segment containing code that a user can
access, that code is protected from being read
and hence from being copied.
The DMA-Inhibit Flag (DMAI) indicates that
the segment is not to be referenced by a DMA
Channel. When this flag is set, only the CPU
has access to the segment. This flag is useful
in preventing a DMA device from modifying a
segment being used by an executing task. For
example, segments with valid data should have
this flag set to protect them from modification
by a DMA device.
The Direction And Warning Flag (DIRW)
indicates that memory accesses are to be
monitored and certain accesses are to be
signaled, although allowed to proceed. When
this flag is set, any write to the lowest 256
bytes of the segment generates a write warning. This flag is useful for segments that are
used as stacks since the Z8001 has special
stack instructions to manipulate stacks that
grow toward lower memory locations. Thus a
write warning for a stack indicates that the
stack may soon overflow its allotted memory
space and that more physical memory should
be obtained. For example, if a segment serves
as a run-time stack for a block-structured programming language such as PASCAL, memor}
can be allocated to this segment only as a program requires during its execution. The alternative in a fixed allocation environment is to
allocate as much memory for the stack as the
system expects the program to need, whether
or not it is actually used by the program.
The Changed Flag (CHG) indicates that a
write has occurred to this segment. This flag is
set automatically whenever a program or DMA
device writes into the segment. This flag is
useful in indicating which segments have been
modified in the case where the segment must
be written to a secondary storage device.
Segments that have not been updated need not
be copied back to disk if a copy already exists.
For example, when a user task is suspended in
a multiple-user environment and his task is to
be swapped out of memory temporarily to
make room for another task, only those
segments that have been changed need to be
updated on the disk.
The Referenced Flag (REF) indicates that a
memory access has been made to a segment.
This flag is set automaticaly whenever a program or DMA device accesses the segment.
This flag is useful in indicating which segments
are active in the case that a segment must be
519

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Segment
Descriptor
Registers
(Continued)

selected to be swapped out of primary memory
to make room for another task. For example,
seldom-used operating-system tasks that usually reside in primary memory may be swapped

out to make room for users with large memory
requirements. ThIs flag is a way of ascertaining
whICh segments contain seldom used tasks.

Control
Registers

Three user-accessible 8-bit registers in the
MMU control the functioning of the MMU
(Figure 8). The Mode Register provides a
sophisticated method for selectively enabling
MMUs in a multiple-MMU configuration. The
Segment Address Register (SAR) selects a particular segment descriptor to be accessed by a
system routine whenit is changing the
organization of primary memory. The Descriptor Selection Counter RegIster selects the particular byte in the Segment Descriptor RegIster
that is accessed.
Two flags in the Mode Register govern the
functioning of the MMU. The Master Enable
Flag (MSEN) indicates whether the device will
perform address translation. When thIs flag is
set, addresses translated by the MMU are
placed on its Address lines; when this flag is
clear, the Address Imes are 3-stated. Thus,
once thIs flag is reset, no memory request can
pass through the MMU. In a single-MMU configuration, MSEN set to zero requires that the
CPU must have access to a special memory,
since It will not be able to fetch an instruction
from the primary memory. ThIS flag can be set
during hardware reset (this is discussed later).
The second flag m the mode register that
governs the functioning of the MMU is the
Translate Flag (TRNS). This flag indicates
whether the MMU is to translate the addresses
presented to it. When the flag is set, the MMU
translates logical addresses to physical memory
locations and checks to see if a violation wIll
occur on that access. When the flag is clear,
addresses presented to the MMU are passed to
the output Address lines without change, and
no protection checking IS done.
When multiple-MMUs are used m a memorymanagement system, some mechanism must be
present to select those devices that are to be
achve during the memory translation process.
More specifically, If two MMUs are employed
so that all 128 segments can be used at random
by an executing process, then some way must
exist for each of the MMUs to know which 64
Segment Descnptors are located in its Segment
Descriptor Registers. The Upper Range Select
Flag (URS) indICates whIch set of 64 deSCriptors IS stored m the MMU. When the flag IS
set, the MMU contams descriptors 64 through

127; when the flag is reset, the MMU contains
descriptors 0 through 63.
When multiple-MMU deVICes keep separate
tables for system descriptors and user descriptors, the Multiple Segment Table Flag (MST)
and the Normal Mode Select Flag (NMS) in the
Mode Register dIstinguish which MMUs contain system descriptors and which contain user
descriptors. When the MST flag is set, mulhple
tables are present in the configuration, and
each MMU IS dedicated to one of the tables. In
thIS case the MMU translates addresses only
when the Nis SIgnal matches the NMS flag.
Thus, if there are two tables m the memory
management system (one for the system and
one for users), the NMS flag IS set m those
MMUs containing the users' segment deSCriptors, and is not set in the remammg MMUs. All
MMUs m the system have the MST flag set to
indicate more than one table in the system.
The final pIece of control informahon m the
Mode RegIster is a 3-blt Identification Field
(ID) that indicates a logICal name for the
MMU. When a segment trap is acknowledged
by the CPU, the MMU uses thIS field to select
one of the AID lines; each enabled MMU
should select a different line. If an MMU
requested a segment trap, it outputs a 1 on ItS
assigned AID Ime; otherwIse It outputs a O.
Smce the ID field IS three bIts, up to eight
MMUs can be umquely Idenhfied. One
instructIOn might result m mulhple violahons
in different MMUs, so that the segment trap
software might have to deal WIth several MMUs
to process the trap.
The other two control registers in the MMU
are the Segment Address Register (SAR),
which pomts to one of the 64 segment descriptors, and the Descriptor Selection Counter
Register. Commands to read or write a segment descriptor use the SAR pointer to select
which deSCriptor IS to be accessed. ThIS
register has an auto-incremenhng capabihty
for accessing consecuhve descnptors in succession without having to reload the SAR. Thus
if descriptors 0 through 4 are to be modified,
the SAR is mitiahzed to 0 and then automcremented to point to descriptors, 1, 2, 3
and 4 m successIon.
The Segment DeSCriptor Number is a 6-bit
field that con tams the address of the descriptor
within the MMU. If the MMU holds segments
64 through 127 (that is, if the URS flag IS set),
the segment named 64 IS accessed when the
SAR number field is O. This is a result of the
6-blt limit of the descriptor number held. The
held indicates the 6 least-significant bits of the
logical segment descriptor number.

7

32

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0

SEGMENT DESCRIPTOR NUMBER
,

,

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21

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I

SEGMENT
ADDRESS

0

I ~~~E;;~~N

DESCRIPTOR

L-....L---I_-'---'_",--l.._DSl...1C--'

Figure 8. MMU Control Registers

520

2046·0031

Control
Registers
(Continued)

Segment Descriptors consist of four bytes;
the Descriptor Selection Counter indicates
which byte is being accessed during a command (commands to the MMU can read or
write only one byte at a time). A counter value
of 0 indicates the high-order byte of the base
address is being accessed, I indicates the loworder byte of the base address, 2 indicates the
hmlt field, and 3 indlCates the attribute field.

This counter is used by MMU commands that
access multiple bytes within a descriptor. In
general, the counter is handled automatically
by the MMU commands. Only when a command could be mterrupted-and mtervenmg
MMU commands issued-should this register
be saved and later restored by the interrupting
program.

Status
Registers

Six 8-blt registers contam information useful
in recovering from memory trap condlhons
(Figure 9). The Violation Type Register
descnbes the conditions that generated the
segment trap. The Violation Segment Number
and Offset Registers contain the segment
number and upper byte of the segment address
offset for the logical address that caused
the segment trap. The Instruchon Segment
Number and Offset Registers contam the segment number and uper byte of the segment
address offset for the last mstruchon before the
segment trap was Issued. The Bus Cycle Status
Register records the status of the bus at the
time the trap condlhon was detected.
Only violahons caused by CPU access have
trap information stored in the status registers;
DMA violations cause Suppress to be asserted,
but the Status Registers are not altered. Thus If
a DMA vlOlation occurs between a CPU vlOlahon and entry to the trap service routine, the
service routine shll has the CPU trap information available to process the trap. It is the
responsibility of the DMA device to save
enough informahon m the event of a violation
so that a software DMA violahon service
routine can process the violahon correctly.
Eight flags m the Violation Type Register
descnbe the cause of the segment trap. Four
flags correspond to access protechon modes m
the segment descnptor attribute mode. A readonly vlOlahon sets the RDV flag, a system-only
violahon sets the SYSV flag, a CPU access to a
CPU-Inhibit segment sets the CPUIV flag, an
execute-only vlOlahon sets the EXCV flag.
Three flags correspond to addressmg vlOlation or warnmgs. The Segment Length VlOlation Flag (SL V) is set whenever the offset of the
10glCal address falls outside the memory space
allocated to the segment. The Pnmary Write
Warning Flag (PWW) IS set whenever a wnte
occurs m the last 256 bytes of a segment whose
Direction And Warning Flag is set (that is, for
segments bemg used as stacks where the top of
the stack is withm 256 bytes of the allocated
memory space of the segment). The Secondary
Wnte Warnmg Flag (SWW) IS similar to the
PWW flag, only It IS set when the CPU IS m
system mode, a stack push IS being performed
to a segment With a Dlrechon And Warning
Flag set, and some other addreSSing vlOlahon
or warnmg has occurred (the EXCV, CPUIV,
SLY, SYSV, RDV or PWW flags have been
set). When the SWW flag IS set It mdicates

that the system stack is in danger of overflowing its allotted memory. Once the SWW flag is
set, further write warnmgs are suppressed.
This prevents the system from repeatedly
being interrupted for the same warning while
It is in the process of eliminating the cause
of the warning.
The final violation-type register flag to be
discussed is the Fatal Condition Flag (FATL).
This flag is set when any other flag in the
vlOlation type register is set and either a vlOlation is detected or a write-warning condlhon
occurs m normal mode. This flag is not set
during a stack push m system mode that
results m a warnmg condlhon. This flag
indicates that a memory access error has
occurred in the trap processing routine. Once
this flag has been set, no Trap Request signals
are generated on subsequent violations.
However, Suppress SIgnals are generated on
this and subsequent CPU vlOlations until the
FATL flag has been reset.
The Bus Cycle Status Register contains information pertainmg to the status of the bus when
a trap condihon is detected. This includes
CPU Status (STo-ST3), plus flags indicating
whether a read or a write was being performed
and whether or not the Nis line was asserted.
The VlOlation Segment Number and Offset
ReglSters record the first logical address to
cause a trap. Only the high-order byte of the
offset is saved, however, so that external support circuitry IS needed to save the low-order
eight bits of the logical address offset. If the
trap occurred during the instruction fetch
cycle, this information is the logical address of
the instruction; otherwise it indicates the

20~6

0032

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7

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0

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SEGMENT NUMBER

_L...---'_...J.'_..L'_J..'_"--'----'_ NUMBER

1...

I

UPPER OFFSET

'---'----'_-'--..L_.l..-....L._'-..J.

BUS
CYCLE
STATUS

CPU STATUS

,

I I
0

INSTRUCTION
SEGMENT

SEGMENT NUMBER

7

I

VIOLATION
OFFSET

0

~PPER OFFSET

I

_'-....1...---,,_..1.'_J..'_"----'----'.

1...

INSTRUCTION
OFFSET

Figure 9. MMU Violation Information Registers

52l

Status
Registers
(Continued)

logical address of a data item which was to be
accessed.
The Instruction Segment Number and Offset
Registers record the logical address of the last
instruction fetch that occurred before the trap.
Only the high-order byte of the offset is saved,
however, so external support circuitry is needed to save the low-order eight bits of the offset.
If an instruction fetch caused the trap, these

registers indicate the logical address of the
previous instruction. Such information is useful
if the preceding instruction was a branch
instruction to an invalid address since-in this
case-these registers indicate which branch
instruction led to the erroneous situation. If a
data reference caused the segment trap, then
these registers indicate the logical address of
the instruction that specified the illegal access.

Stack
Segments

Segments are specified by a base address
and a range of legal offsets to this base
address. On each access to a segment, the offset is checked against this range to insure that
the access falls within the allowed range. If an
access outside the segment is attempted, a
Trap Request and a Suppress Signal are
generated.
Normally the legal range of offsets within a
segment is from 0 to 256N + 255 bytes, where
0:5 N:5 255. (N is the value in the limit held of
the segment descriptor.) However, a segment
may be specified so that legal offsets range
from 256N to 65,535 bytes, where 0:5N:5255.
The latter type of segment is useful for stacks
because the 28001 stack-manipulation instruclions cause stacks to grow toward lower
memory locations. Thus, when a stack grows to

the limit of its allocated segment, additional
memory can be allocated on the correct end of
the segment. As an aid in maintaining stacks,
the MMU detects when a write is performed to
the lowest allocated 256 bytes of these
segments and generates a Trap Request. No
Suppress signal is generated so the write is
allowed to proceed. This write warning can
then be used to indicate that more memory
should be allocated to the segment.
The DIRW flag indicates that a segment is to
be treated in this special way by the MMU.
When the DIRW flag is set, the range of
allowed offsets is from 256N to 65,535 bytes
and writes into the range 256N to 256N + 255
generate Segment Trap but not Suppress,
indicating a write warning.

Segment
The 28010 MMU generates a Segment Trap
Trap and
whenever it detects an access violation or a
Acknowledge write warning condition. In the case of an
access violation, the MMU also activates Suppress. Suppress can be used to inhibit memory
writes and to request that special data be
returned on a read access. Segment Trap
remains Low until a Trap Acknowledge signal
is received. If a violalion occurs, Suppress is
asserted for that cycle and all subsequent CPU
memory references until the end of the instruction. Intervening DMA cycles are not suppressed, however, unless they generate a
violation. Violations detected during DMA
cycles cause Suppress to be asserted during
that cycle only; no segment trap requests are
ever generated during DMA cycles. This is
because the CPU would not be able to respond
to these traps until the conclusion of the DMA
cycle.
Segment traps to the 28001 CPU are handled
similarly to other types of interrupts. To service a segment trap, the CPU enters a segment
trap acknowledge cycle. The acknowledge
cycle is always preceded by an instruction
fetch cycle that is aborted. The MMU has been
designed so that this dummy instruction fetch
cycle is ignored. During the acknowledge
cycle, all enabled MMUs use the Address/Data
lines to indicate their status. An MMU that has
generated a Segment Trap request outputs a 1

on the AID line associated with the number in
its ID field. An MMU that has not generated a
segment trap request outputs a 0 on its
assoCiated A/D line. A/D lines for which no
MMU is associated remain 3-stated. During a
segment trap acknowledge cycle, an MMU
uses AID line 8 + i if the content of its ID
field is i.
Following the acknowledge cycle, the CPU
automatically pushes the program status words
and program counter onto the system stack,
and loads a new program status word and program counter from the program status area.
The Segment Trap line is reset during the segment trap acknowledge cycle, and no Suppress
signal is generated during the stack push. If
the store creates a write warning condition, a
segment trap request is generated and is servICed at the end of the context swap; the SWW
flag is also set. ServICing this second Segment
Trap request also creates a write warning condilion, but-because the SWW flag IS set-no
Segment Trap request is generated. If a violation rather than a wnte warning condihon
occurs during the context swap, the FATL flag
is set rather than the SWW flag. In this case,
subsequent violations cause the Suppress to be
asserted but not Trap Request. Without the
SWW and FATL flags, trap processing routines
that generate memory violations would
repeatedly be interrupted and called to pro-

522

cess the violations they create.
Segment
The CPU routine to process a trap request
Trap and
Acknowledge should first check the FATL flag to determine
(Continued)
if a fatal system error has occurred. If not, the
Commands
to the MMU

When a memory management system must
read or change information in the MMU to
respond to a segment trap or to re-organize the
physical memory, it can issue control commands to the MMU. These commands fall into
two generic categories: reset commands and
read/write commands. Reset commands are
simply orders to the MMU to set or clear
specified fields. For these commands, the
28001 Special IIO output command can be
used with the destination field set to be the
MMU command code corresponding to the
desired action.
Read and write commands are slightly more
complicated because they consIst of both commands and data. Such commands to the MMU
are issued using the 28001 Special I/O instructions. These instructions have a source and a
destination field. For an input instruction, the
source field contains an MMU command code
and the destination field indicates where in
primary memory the data is placed. For an
output instruction, the destmation field contains an MMU command and the source field
indicates where the data to be written into the
MMU resides in memory.
The high-order byte of the command contains the opcode for that command; the loworder byte of the command can be used to
specify the particular MMU to be accessed.
The MMU does not receive information on
ADo-AD?, so external circuitry must decode
information on these lines during the Special
IIO commands and then select a particular
MMU. The encoding of the low-order byte is
dependent upon the system implementation.
ThIs paper always uses the convention that
bIt i specifies MMU number I.
The reset commands to the MMU are: Reset
Violation Type Register, Reset SWW Flag In
Violation Type Register, and Reset Fatal Flag
In Violation Type Register. Resetting the Violation Type Register is similar to a hardware
reset in that it clears this register and returns
the internal control of the MMU to an initial
state (as if no vIOlation had occurred smce
system initialization). Resetting the SWW flag
or the FATL flag in the Violation Type Register
clears these flags.
Two other commands are similar to reset
commands m that they have no data associated
with them. These are Set All CPU-InhibIt Flags
in the segment attribute fields and Set All
DMA-Inhlbit Flags in the segment attribute
fields, both of which cause all segment

SWW flag should be checked to determine if
more memory is required for the system stack.
Finally, the trap itself should be processed and
the violation type register reset.
descriptors in the MMU to have the CPU! or
DMAI flags set, respectively. These two set
commands can be useful in initializing address
translation tables or when swapping between
tasks. For example, when swapping between
tasks the Set All CPU! Flags command
automatically makes the previous task's
segments inaccessible to the next task, unless
the system explicitly mitializes the segment
attribute field in these segments.
As an example of using the Special Output
instruction SOUT to control an MMU, consider
resetting the fatal flag of MMU # I. The MMU
command opcode for this is "%14" (% denotes
hexadecimal). The assembler syntax for the
SOUT instruction is "SOUT destination field,
source field" so that the instruction to reset the
fatal flag of MMU #1 IS "SOUT %1402, RO."
Specifying register 0 in this instruction is an
arbItrary choice-the content of this register is
placed on the AID lines during the data phase
of the SOUT instruction, but it is ignored by
the MMU. The low-order byte of the command
(the destination field of the instruction) encodes which MMU is to reset its fatal flag. The
convention followed in this paper is that MMU
i is specified by setting bit i in the low order
byte of the command. (BIt I set is hex "%02.")
The rest of the MMU commands consist of
both operation and data. The following internal
registers can be read or written: the Mode
RegIster, the Segment Address RegIster, the
DeSCriptor Registers and the Descriptor Selection Counter RegIster. A Descriptor RegIster
can be read or written as a whole, or selected
subfields can be accessed. In addition, by
using the auto-increment feature of the Segment Address Register, successive Descriptor
RegIsters can be accessed, or a selected field
withm successIve DeSCriptor RegIsters can be
accessed. For example, one Special IIO command in block mode could read a number of
segment attribute fields. This is useful in determing whICh segments have been modified.
As an example of using the Special Output
instruction SOUT to write data into an MMU,
consider writmg the contents of Register 6 into
the Mode RegIster of MMU #2. The opcode for
thIS command is "%00" and so the command is
"SOUT %0004, R6." Here the high-order byte
of the destmatlon field contains the opcode
and the low-order byte has bit 2 set (hexadeclmal4 if 0100 in bl!;lary) indicatmg
MMU #2.

523

i...
o

~

3
3
d

...
;::I.

e.

Certain MMU internal registers can only be
read-there is no corresponding write instruction. ThIs is because these registers contam
information relating to a detected violation and
thus it is not necessary to be able to write into
these registers. These registers are the Violation Type Register, the Violation Segment
Number Register, the Violation Offset Register,

the Instructiorr Segment Number Register, the
Instruction Offset Register and the Violation
Bus Status RegIster. Although the VlOlation
Type Register cannot be written, it should be
noted that it can be cleared and that two of its
flags can be individually cleared: the SWW
flag and the FA TL flag.

Direct
Memory
Access

DMA operations may occur between 28001
machine cycles and can be handled through
the MMU. The MMU permits DMA in either
the System or Normal Mode of operation. For
each memory access, segment attributes are
checked and-if a violation is detected-a
Suppress signal is generated. Unlike a CPU
Violation, which automatically causes Suppress
signals to be generated on subsequent memory
accesses until the next instruction, DMA violations generate a Suppress only on a permemory-access basis. The DMA devIce should
note the Suppress signal and record sufficient
information to enable the system to recover
from the access violation. No Segment Trap
Request IS ever generated durmg DMA (hence
warning conditions are not signaled). There
are no trap requests because the CPU would
not acknowledge the request until the end of
the DMA cycle.

At the start of a DMA cycle, the DMASYNC
line must go Low, indicating to the MMU the
beginmng of a DMA cycle. A Low DMASYNC
inhibits the MMU from using an indeterminate
segment number on lines SNo-SN6. When the
DMA logical memory address is valid,
DMASYNC must be High on one rising edge of
Clock and the MMU then performs its addresstranslation and access-protection functions.
Upon the release of the bus at the termination
of the DMA cycle, DMASYNC must qgain be
High. After two clock cycles of DMASYNC
High, the MMU assumes that the CPU has control of the bus and that subsequent memory
references are CPU accesses. The first instruction fetch occurs at least two clock cycles after
the CPU regains bus control. During CPU
cycles, DMASYNC should always be High.

Hardware
and
Software
Reset

The MMU can be reset by either hardware
or software mechanisms but note that they
have different effects. A hardware reset occurs
on the falling edge of the Reset input; a software reset is performed by an MMU command.
A hardware reset clears the Mode Register,
Violation Type Register and Descriptor Selection Counter. If the Chip Select line is Low
whlie Reset is Low the Master Enable Flag in
the Mode Register is set to I. All other
registers are undefined. After reset, the AID
and A lines are 3-stated. The SUP and SEGT

open-dram outputs are not driven. If the
Master Enable Flag is not set during reset,
the MMU does not respond to subsequent
addresses on its AID lines. To enable an MMU
after a hardware reset, an MMU command
must be used in conjunction with ChIp Select.
A software reset occurs when the Reset
Violation Type Register command is issued.
ThIS command clears the Violation Type
Register and returns the MMU to its mitlal
state as if no violations or warnings had
occurred.

Commands
to the MMU

(Continued)

Multiple-MMU 28010 MMU architecture supports system
Configurconfigurations that use more than one
ations
MMU. Multiple MMU devices can be used

either to manage 128 CPU segments rather
than the 64 supported by one MMU, or to
manage multiple translation tables.
The 28001 CPU generates logical addresses that can specify up to 128 different segment names. Because the MMU contains
only 64 Segment Descriptor Registers, two
MMUs are needed to perform address translation for 128 logical segments. Systems
designed with only one MMU device still
have the power and flexibility offered by
memory management, although tasks in
such a system are restricted to mampu-

524

lating only 64 logical segment names. These
names must either be 0 through 63 or 64
through 127. If the MMU in a smgle-MMU
configuration is set to translate segment names
in one range and the CPU generates a logical
segment name m the other range, the MMU
does not perform address translation and no
phYSICal memory location is output. In thIS
case, no request IS made to memory. Therefore, a single-MMU configuration should have
additional external logIC to detect erroneous segment names and generate a Segment
Trap and Suppress signal.
The Upper Range Select flag (URS) IS
used in multiple MMU configurations to
indicate which group of logical segment names

Multiple-MMU are to be translated by an MMU. When this
Configurflag is set, the Segment Descriptor Registers m
the MMU are used in translatmg logical
ations
(Continued)
addresses in the range 64 through 127. When
the flag IS clear, the range is 0 through 63.
Thus the URS flag corresponds to the most
significant bit (bit 6) in the logICal segment
names that the MMU translates. Because this
flag IS under program control, the range of
logical segment names can be changed durmg
execuhon in System Mode.
MMU architecture also supports multiple
segment translation tables. This feature is
useful when separate tables are maintained for
different tasks. Each task has its own table and
switchmg between tasks reqUires enablmg the
appropriate MMU devices. In contrast, systems
with only one translahon table must either
restrict the logICal segment names that an
mdividual task can use, or change the
DeSCriptor Register entries whenever tasks are
swapped. Two flags m the Mode Register,
together with the N/S signal, are used in mulhpie table conflgurahons.
The Mulhple Segment Table (MST) flag
mdlCates whether the configurahon IS being
used to support mulhple tables. When this flag
IS set, the MMU Will compare the N/S Ime
agamst the Normal Mode Select Flag (NMS)
before generating a phYSical memory location
on ItS Address lines. When the line and the
flag match (both asserted or both de-asserted),
the MMU IS enabled and an address translahon
IS performed (assummg the URS flag matches
the most significant bit in the logical segment

Examples

This sectIOn describes two Z8001-Z8010 configurations: one contams two MMUs and one
address translahon table; the other con tams
seven MMUs and four address translation
tables. These examples are given m sufficient detail to illustrate some of the major
Ideas in constructing memory-management
systems around the Z8010 MMU. High-level
block diagrams Illustrate some of the major
features of typical hardware configurahons
and short programs illustrate software techniques for using the MMU.
The first example system is the two-MMU
configurahon Illustrated in Figure 10. The two
MMUs are called MMU #1 and #2, and they
are selected during a command cycle by AD)
and AD2 bemg Low, respechvely. Since a
Special 1/0 mstruction IS bemg used bit 0 must
always be zero. Thus, when a low-order byte of
a command IS "%02," MMU #1 responds;
when It IS "%04," MMU #2 responds; and
when it IS "%06," both MMUs respond. (Note
that AD, is mverted before attachment to the
CS pm.)
The AID) Ime, which controls MMU #1
through the Chip Select mput, IS first com-

name). If the N/S Ime fails to match the state
of the NMS flag, no translated address is
generated by the MMU. The MST flag and the
NMS flag are under program control and can
be changed m System Mode.
The Simplest mulhple translation table configurahon has one table for Normal Mode
access and one for System Mode access. In
such a configurahon, the Mulhple Table Flag
IS set m all MMUs and the N/S line of each
MMU receives its input from the NiS output of
the Z8001 CPU. MMUs containing descriptors
of system segments have the NMS flag clear,
and those contammg descriptors to be used in
Normal Mode have the flag set. When the
Z800 I IS in System Mode, the N/S line is Low
and it matches the NMS flag in those MMUs
whose Descriptor Registers contain system segment mformation. Therefore, these MMUs are
used m address translaflOn for system
references.
When the Z8001 is m Normal Mode, the N/S
Ime is High and It matches the NMS flag in
those MMUs whose DeSCriptor Registers contam user segment mformahon. Consequently,
these MMUs are used m address translation for
user segments. In this conhgurahon, system
segments are separated from user segments.
When the Z8001 changes from Normal to
System Mode of operatIOn, the appropriate
translahon table is au tomah cally selected. A
more elaborate example of a conhgurahon With
mulhple translation tables IS given in the next
section.

bined With the Reset line. This allows the
Master Enable Flag to be set upon system
mlhalizahon, so the logICal addresses generated by the CPU are passed to the physical
memory. ThiS IS done because-upon resetthe mode register IS otherWise cleared, the
Translate Flag IS clear and addresses pass
through the MMUs untranslated. The bootstrap
program can therefore reside in absolute
memory locahons in the physical memory. If
the Reset line IS not an mput to the Chip
Select line, the Master Enable Flag would not
be set during system imhalization and the CPU
would not be able to address memory through
the MMUs.
Note that there IS a direct path from the
CPU and DMA to the system bus. ThiS path
IS used durmg 1/0 and memory refresh
because the MMUs are quiescent during these
cycles. It IS also used for data on memory
reads and writes. Also, note that the Suppress
Ime goes both to the memory, where It can be
used to protect the memory from erroneous

525

Examples
(Continued)

To write thiS'descriptor into the MMU, a
copy of the descriptor should be created in
primary memory and a Special I/O block
transfer instruction used. The SOTIRB instruction can be used for this.
This instruction has the assembler syntax
"SOTIRB destination, source, count register"
where both the destination and source are
registers. The destination register contains the
command to the MMU, the memory location
pointed to by the source register contains the
first byte of the data to be transferred, and the
Count Register contains the number of bytes to
be transferred.
The opcode to load the Descriptor Register
is "%OB". Segment Descriptor Register 65 is
Segment Descriptor Register 1 of MMU #2, so
the MMU command is "%OB04".
To specify which Segment Descriptor
Register to write, it is necessary to load the
Segment Address Register of MMU #2 with 1.
The MMU opcode to do this is "%01" and so
the command is "%0104." The segment
number (in this case 65) is a parameter to the
example routine, passed in register O. The

writes, and back to the DMA device to save
information upon the event of a DMA access
error.
Of further interest in the example, address
latches are used to buffer addresses between
the 28001 and a demultiplexed bus. This is
required to demultiplex the address and data
onto the bus. The address latch for ADS-ADJS
may not be needed if the 1/0 device does not
use separate address and data lines.
A detailed example indicates how such a
system could be used. First, consider setting
Segment Descriptor Register 65 to point to a
read-only segment of 768 bytes starting at
memory location % 115200. The segment is to
be accessed in Normal Mode. The Descriptor
Register should be %115202 01. The first two
bytes, %1152, indicate the starting location of
the segment (note that the low-order byte of
the memory address is all zeros and is not
stored in the Descriptor Register). The third
byte, %02, indicates that three blocks of 256
bytes have been allocated to this segment. The
fourth byte, %01, indicates that only the readonly segment flag has been set.

t:l
V'

1 X....

16

,.

RESET
BUSACK

ADo-AD15

7

SNo-SN6

4

STo-STa

4

CNTL

•

ADs-AD1S

•

ADo-AD7

•

ADa-AD15

ZBUS

L
-;:z BAa-BS15

24

V'

Z8001

CPU

-

SEGT
BUSREQ

,.

BRQ

BAi

7

DMA

r-

V'

t:Z. BAa-BA16

ADo-AD15
SNo-SN6

Z8016

EOP

t:Z BAo-BA7

4

5To-51 3

4

CNTL

MMU SYNC

V'

7

SNO-SN&

4

STa-STa

4

CNTL

Z8010

MMU

SUP

>- cs

RESET

-;z BA1S-BA23
V'

AD1~

>---- > %9328. This causes a segment trap both because of the write to a readonly segment and because the access exceeds
the segment limit. At the end of the instruction
that has the illegal memory access, the CPU
acknowledges the trap. During the trap
acknowledge cycle, MMU #2 asserts ADIO
(assuming its ID field is "010") and this information is placed on the system stack for the

!Test to see if Descriptor Register is in MMU III!
lor MMU 1121
ISet SAR in MMU 112!
IPrepare to write descriptor!

trap-handling routine.
The trap-handling routine reads the violation
information registers from the MMU. The violation type register contains "%05" indicating
both a length violation and a read-only violation. The Violation Bus Status Normal Register
contains "%28". The first nibble indicates a
write in Normal Mode was in progress and the
second nibble indicates a memory data access
cycle was in progress. The violation segment
register contains "%41" indicating segment I
of MMU 112 caused the violation (which is segment number 65), and the violation offset
register contains "%93" indicating the highorder byte of the logical address offset. The
operating system can then issue an error
message to the user indicating a read-only
violation to segment 65. Using the program
counter that was stacked when the segment
trap was acknowledged, the system can also
indicate the next instruction that was to be
executed. Note that in this system the loworder byte of the violation offset is lost. This
condition is corrected in the next example
system.

527

Examples
(Continued)

-;:z

t-

...

DMASVNC
18

CPU

r-I- smr
BUSAEQ

18

ADo-ADts

7

SNo..sNe

•

STo-sTa

4

eNTL

•

ADa-AD1s

•

ADo-ADr

l

RESET

I
11

Z801'

D.A

MMU SYNC

c- I"---

7

SNa-SN,

•

STo-STa

4

CNTL

Z80

DMA
MMU SYNC

-I"---

'LATCH

YOFF

J

t:l BAa-8A1&

....

DMASYNC

ADa-ADu

7

SNo-SN,

-

IiEl!ET

a"

....

18}

•
•
•

EO'

BUSAEQ

~BAo-BA7
AD,-ADr

ADo--ADts

r- BAli

Lo.

-;:z BAa-BA,s
....

MMU
SELECT

iAl
jUSREQ

•

DECODE

•
'-

118

Z.BU

~

BUBACK
Z8001

1 .x.

o\Oo-A0..5

_.An

28010

..

hi BAIl-BAn

11

• •U

"

STo-STa
eMTl

::f)-

eo

iiiP
SEGT

~

r-

REBET

18

ADo-AOts

7

SNo-SN,

•

ADa-AD1&

STo-STs

7

SNo-SN,

eNTl

4

STo-STa

4

eNTL

•
•

EliP

DMASYNC

Z8010
• •U

I.

18

ff-r-r-

...,

-

;;up

os
REBET

DMASYNC

•

ADt-AD1'

7

8No-SN,

•

STo-ST.

•

..

Z8010
• •U

CNTL

iUii

es

18

ff-r- tt-

SEaT

REBET

Figure 11. lS-MMU Configuration

Figure 11 gives a high-level diagram of the
second system to be discussed. This configuration contains 16 MMUs, and the AID lines
select the appropriate MMU when in Command mode. The major innovation in this
example, aside from the additional MMUs, is
the latch that retains the least significant byte
of an address offset when a violation is
dptected, Thi~ latch i~ enabled when a ~eg­
ment trap is generated by an MMU and holds
the low-order byte of the address that
generates an access·violahon.
in addition, external decoding logic for
selecting one MMU Chip Select line is indicated. Seven MMUs is the limit in one configuration without additIonal decoding logic
for selecting one MMU Chip Select line. (The
reason why ADO cannot be used to control an
eighth MMU is due to the Special 1/0 input

528

convention of the CPU. When the CPU inputs
a byte of information and ADo is asserted, the
data is taken from ADo-AD7' which are not
driven by the MMU.)
Switching Tables in a 16-MMU System.
The 16-MMU configuration can support a
memory management system designed with two
MMUs permanently allocated to the operating
::;ystt:HIl CluJ the uthef:.) allucated in pairs to dif-

ferent user tasks. Thus, seven user tasks can
have translation tables resident in the 14-user
MMUs, and switching between active tasks
requires the appropriate MMUs to be enabled
and disabled. This selection process can be
effected by manipulating the Master Enable
(MSEN) flags in the mode registers of the
appropriate MMUs.

2049-0085

Examples
(Contmued)

The routine performs the selective enabling
of MMUs required by a task swap. ThIs routine
disables all user MMUs (thus disabling the currently enabled user MMUs). then enables the
appropriate pair. (The system pair is always
enabled.) The code selecting the new task is
passed in register RI; it contains %n, if task n
is to be dispatched.
Two peculiarities of this example are worth
noting. First, each user ID number corresponds to seven MMUs (for example, all
upper-range user MMUs). The Segment Trap
processing routine has to take this into
account. Second, the Chip Select code IS
assumed to be as follows:
CLR
SOUT
SLA
LO

RO
%00F8,RO
RI,#1
Rl, TABLE(Rl)

LOA
SOUTIB

RR2,DATA
@RI,@RR2,RO

INC
SOUTIB
END:
DATA:
TABLE:

Rl, #8
@Rl,@RR2,RO

ADO-AD-,

System:

02

User I:
User 2:

User 6:

ID=O,
ID= I,
ID=2,
ID=3,
ID=2,
ID=3,
ID=2,
ID=3,

URS=O
URS= I
URS=O
URS=I
URS=O
URS=I
URS=O
URS=I

08
!O
18
20
28
30

68
70

#15, ID=2, URS=O
#16, ID=3, URS= I

04

User 0:

MMU Selected

#1
#2
#3,
#4,
#5,
#6,
#7,
#8,

It is also assumed that %F8 will select all
user MMUs.

!Clear RO!
!Disable all user MMUs by clearing their mode registers!
!Multiply Rl by 2-the number of bytes in a memory word!
!Get the command word (opcode always %00) for user n,
URS=O!
!Get the new mode register bit pattern (%DA)!
!Send %DA to lower-range MMU and increment RR2 to
DATA +1!
!Command word for URS = 1!
!Send %FB to upper range MMU!

BYTES(%DA, %FB) !Mode register bit patterns!
WORDS (%8,%18,%28,%38,%48,%58,%68)
Program to Switch Tables

MMU
Command
Summary

Opcode
00
01
02
03
04
05
06
07
08
09
OA
OB

(JO J.lJ4:J

A

Operation
Read/Write Mode Register
Read/Write Segment Address
Register
Read Violation Type Register
Read Violation Segment
Number
Read Violation Offset (hIgh
byte)
Read Bus Cycle Status Register
Read Instruction Segment
Number
Read Instrucbon Offset (hIgh
byte)
Read/Write Base Field In
Descriptor
Read/Write LimIt Field In
Descnptor
Read/Wnte Attribute FIeld In
Descriptor
Read/Write Descriptor (all
fields)

Opcode
OC
OD
OE
OF
10
11
12
13
14
15
16
17-IF
20

21-3F

Operation
Read/Write Base Field And
Increment SAR
Read/Write LImIt Field And
Increment SAR
Read/Write Attribute Field
And Increment SAR
Read/Wnte Descriptor And
Increment SAR
Reserved
Reset Violabon Type Register
Reserved
Reset SWW Flag In VTR
Reset FATL Flag In VTR
Set All CPU-InhibIt Flags
Set All DMA-Inhiblt Flags
Reserved
Read/Write Descriptor Selector
Counter RegISter
Reserved

529

8igh-Reliability
Microcircuits

~
Zilog

Military Specification
Standards

June 1982
General
Description

2ilog offers high-reliability versions of the
entire family of 280 and 28000 logic circuits,
processed in accordance with the requirements
of MIL-STD-833 level B (Test Methods and Procedures for Microelectronics). The 280 and
28000 Families are currently in the process of
qualifying for inclusion in the MIL-M-3851O
Qualified Products List.
General Considerations. 2ilog high-reliability
microcircuits are designed to meet the full
military temperature range of -55°C to
+ 125°C and are packaged in hermetic dualin-line packages. These packages can reliably
withstand the thermal shock requirements of

Test

Condition

MIL-STD-833, method 1011, Condition C
(-65°C to + 150°C). For industrial users, 2ilog
offers an extended operating temperature
range of -40°C to +85°C. All of 2ilog's highreliability microcircuits receive 5005 processing in accordance with the requirements of
MIL-STD-833 level B or C (as speCified). Table
1 lists the screening tests performed on the two
levels. An X indicates that the test is performed 100% of the time and a Z indicates that
the test can be done upon request. Table 2
lists the Zilog products available with the 100%
testing process shown with X's in Table 1.

MIL-STD-883
Method Condition

Class

B

C

SEM Inspechon

2018

Z

Z

Precap Visual

2010

B

X

X

X

X

1008

C

X

X

Seal and Lot J.D.
Stab1hzahon Bake

48 hrs.

@

150°C

Temperature Cyclmg

10 cycles

1010

C

X

X

Centrlfuge

Yl Plane

2001

E

X

X

Fme Leak

1014

A

X

X

Gross Leak

1014

C

X

X

X

X

Electncal Test
Burn-In
Fmal Electncal
Radiograph1c Inspechon
External V1sual

Per Zllog Data Sheets
168 hr.
240 hr.

1015
1015

160 hrs.
240 hrs.

X
X

25°C, -55°C,
and + 125°C
As required

X
Z
X
X

2012

Z

Z

2009

X

X

NOTES: S = Sample testmg only, X = 100% testmg, Z = Opbonal (tested 1f requested).

Table 1. Total Lot Screening

531

I
...

~

General
Description
(Continued)

Speed

Mil Temp
Range

Extended
Temp Range

zao CPU

2.5 MHz

Yes

Yes

280A CPU

4.0 MHz

Yes

Yes

280 PIa

2.5 MHz

Yes

Yes

280A PIa

4.0 MHz

Yes

Yes

zao SIO

2.5 MHz

Yes

Yes

zaOA SIO

4.0 MHz

Yes

Yes

zaODMA

2.5 MHz

Yes

Yes

Product·

zaOA DMA

4.0 MHz

Yes

Yes

zao CTC

2.5 MHz

Yes

Yes

280A CTC

4.0 MHz

Yes

Yes

28001 CPU

4.0 MHz

Yes

Yes

28002 CPU

4.0 MHz

Yes

Yes

"NOTE See Ordermg Information for package and temperature desIgnators.
For Qualified Product LIstings avaIlabilIty call the Mlhtary
Assurance Program OffIce

Table 2. High-Reliability Products Available

Manufacturing and
Process
Controls

Zilog high-reliability microcircuits are
processed and assembled in accordance with
the Zilog Product Assurance Program Plan,
which conforms to the requirements of
Appendix A of MIL-M-38510. The following
are some of the items contained in the plan:
• A clear, concise procedure for converting a
customer specification to a Zilog internal
specification, assuring the customer that
parts received meet or exceed specified
requirements. The converted document controlled by Zilog document contro!'
• A formalized training and testing program
for all operator and inspection personnel to
ensure that each operation is performed
correctly.
• An inspection system that includes a complete Incoming Inspection Laboratory, a
Chemical Analysis Laboratory, and a
Failure Analysis Laboratory to assure that

532

all materials, utilities, and work-in-progress
meet Zilog requirements.
• Rigid requirements for the cleanliness of
work areas and the maintenance of a Class
100 environment at all stations where
critical operations are performed.
• A document control system to control
changes in design, materials, and processes.
• A system for maintaining documents and
records in active files for three years and in
archive files for ten years.
• An instrument maintenance and calibration
system complying to the requirements of
MIL-STD-45662 (Calibration System
Requirements) .
• A quality audit system in accordance
with MIL-Q-9858 (Quality Program
Requirements).

00·2027·02

Package Dimensions

Z···.·1.-l'09

Package Dimensions

~

Zilog

June 1982
Package

Summary

This table summarizes the microprocessor
components available from Zilog by number of
pins and package type. FollOWing the table are
detailed drawings for each package type. For
Pins

Package

Component

18

Ceramic. Cerdlp, Plashc

28

CeramiC, Cerdlp, Plashc

ZS430 ZSO CTC

28

Leadless Carner, Ceramic

ZS430 ZSO CTC

40

CeramlC, Cerdlp, Plashc

ZS002 28000 CPU
28030 28000 2-SCC
ZS036 ZSOOO 2-CIO
ZS038 ZSOOO 2-FlO
ZS090 ZSOOO 2- UPC
ZS400 ZSO CPU
ZS410 280 DMA
ZS420 ZSO PIO
ZS440 ZSO SIO/O
ZS441 ZSO SIOIl
28442 ZSO SI0/2
28449 280 SI0/9
ZS470 ZSO DART
28530 SCC
ZS536 CIO
28538 FlO
ZS590 UPC

ZS581 Clock Generator and Controller

ZS601 28
ZS611 ZS
2867128
ZS681 28

further information on specific components,
see the Ordering Information section of each
product speCification.

III

t

.,...

'I
Pins

Package

Component

40

Protopack

ZS093
28094
ZS593
ZS594
ZS603
ZS613

44

Leadless Carner CeramIC

28002 28000 CPU
ZS030 ZSOOO 2-SCC
ZS036 ZSOOO 2-CIO
ZS038 28000 2-FlO
ZS400 ZSO CPU
28410 280 DMA
ZS420 280 PIO
28444280 SIO·
ZS530 SCC
ZS536 CIO

48

CeramIC PlastIc

ZSOO I ZSOOO CPU
ZSOIO ZSOOO 2-MMU

52t

Leadless Carner Ceramic

I

I

I

ZSOOO 2- UPC
28000 2- UPC
UPC
UPC
ZS MCU
ZS MCU

ZSO 10 ZSOOO 2-MMU
ZSOO I ZSOOO CPU

MCU
MCU
MCU
MCU

"NOTE As a result of Size of package, all three S10 versIOns are
mcluded In one verSlOn, the Z8444

•

t 52-pm Leadless Carner Diagram unavailable at hme of
publication.

535

!

I-III

Package

10

18

Dimensions
(Contmued)
LEAD NO.1
INDENT
0.185

18-Pin Ceramic Package

'~~t:::~:::j

r~' rl~
!-~~~_~ ~ rj l ~Jl~~'l .J
0.125 ±.015
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q

0.100
.010
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:!:

0.056
.003
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±

11_060 MAX
BOTH ENDS

0.018
.003
TYP

±

18-Pin Cerdip Package

18-Pin Plastic Package

NOTE. Package demmslOns are

536

gIven III

mehes. To convert to mlhmeters, multIply by 25.4.

Package
Dimensions

15

28

I

tr:====~
L,r-O~=-=-=~~:;:;::;;::;;:;:::;::;;:;;;..=-==-=,..I
~~S: :;

PIN 1
IDENTIFICATION

14

f
r
t

28-Pln Ceramic Package

.~=t--~2~8LLLL~~-U-LLLLi~~LLLLLL~1~5-.
0.550

l~~~
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0230

'I

0.056

rul.~

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M

I--liOTH ENDS-+l

0.040

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1--=.010
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,,~.

-+11--=.003
TYP

±.020

28-Pln Cerdlp Package
28

15

0.082
RAD
14

----------------~~~·--------------I

~T
J~.tt-

0.100
TYP

0.018
0.050
± .003 TYP TYP

t

M~

•

jMIN

MIN

28-Pin Plastic Package

537

Package

40

21

Dimensions
(Continued)

tfDI"o

r-=======~

PIN 1
IDENTIFICATION

~~~~~~~~~~~~~
20

1---0•530 ---1
I
MAX
I

f

0

l--0.600
REF

.m. '~

±.OO2TYP

----I

~~~

I'

'I

0.040

~~I~

m~

0.125
MIN

!

0.050
L±.015 BOTH ENDS

J

~

0.100
L±.010TYP

0.018
JL±.003TYP

0.060
0.020

'O-Pin Ceramic Package

'~l··

40

21

0.550

l~~n-rrrr-rrrr""'-'-'--'-'-r-rrr-'
20

'I

~~

,

~L~
I

.1.1
MIN

J ~ .,.-

0.040
±.020

BOTH ENDS

-.I

~

!'.
- N~

-.11.-......
-:?$~

40-Pin Cerdip Package

NOTE. Package demmslOns are given m Inches. To convert to mlllmeters, mulhply by 25.4.

538

Package

40

Dimensions

T

(Continued)

0.555

I =n=r=n=;: :;: =;=r=;:= ;=;:;=;=;=;: :;: : ;: :;: : ~: :;: ;: : ;: : r;: ; =d
20

r-----j
1~0.8OO~1

t'~-------------------~~'--------------------~'I

0.820

~~
I

}\

0.650

0.150
MAX

J<=------------++-------j1E~

I

I

r----O.610~

40-Pln Plastic Package

ITrDDDDDDDDDDDD
°

.._l_~o_) D D

MAX MAX

DO 0

/ftC1Tli

P
IDENTI

00000 0

1

-.

I

___ ll

40

F

DO

20

2.020 MAX

FO.05O ±.02O

'I

1.220 MAX

O.~
M X

J~~~
J
r-°'s:'AXSO'----j

~0.1oo±.010TYP

TYP

1+-------------------1~~

l.04O+.oorTYP

MIN

-.002

4O-Pin Prolopack Package

539

r~

Package
Dimensions
(Continued)

PIN 1
IDENTIFICATION

48

25

~~ r:=========~
)'0
24

t - - - 0.530-----+1
I
MAX
I

~'

D

!

o.010

,..010
TYP

l--0.600~
REF

~?i

['

0.040

~!r~

Wi

0.125
MIN

0.060
0.020

,l

I
, I,

L '"

0.050
.025

BOTH ENDS

--I L '"

0.100
.010 TYP

j

48-Pln Ceramic Package

0.082
RADIUS

48-Pin Plastic Package

NOTE Package demmslons are gIven m Inches To convert to mlllmeters, multIply by 25 4.

540

'[

L

0.018
± .003 TYP

Package
Dimensions
(Contmued)

-g::~:~g:-

I~~ ~I ~I-~~~/-.H"':':'-in1, - ~
~

" ii

"

I ~.02{
II
x

METALIZATION
ONE CORNER ONLY

0.036 - .
MIN.

128
45'
_ _ 0.025 TYP.

28-Pin Leadless Package

-g::~~.-

1_1_

0.528
0.492
0.475
0.469

SQ·-I
SQ.
SQ·-I
SQ.

I

.~,.a~~

0.013
0.011
0.020 x 45° REF.

FOF
II

1*

0.077
0.054

~

I

JL

0.056_1

0.040 x 45°
TYP. 3 REF.

0.040

44-Pin Leadless Package

541

Board Producls

The Problem Solvers for
Microcomputer Systems
The Z80 MCB famIly of bus~
compatIble mIcrocomputer boards
features powerful performance and
apphcatIon flexIbIlIty at a low total
systems cost. For every apphcatIon,
from a smgle~board solutIon to a hlgh~
performance board set, the MCB famIly
provIdes the right combmatlOn to easIly
solve most mICrocomputer system
problems.

The Competitive Edge. The hme It
takes from product conception to
market mtroductIon may mean the dlf~
ference between success or faIlure.
Success IS assured WIth the Z80 MCB
famlly. The boards are compatIble, can
be mtegrated mto a system qUIckly, are
easy to learn and use, allow the conve~
ment addItIOn of last mmute features,
and are avallable off~the~shelf.

Performance, The powerful archltec~
ture of the Z80 Central Processmg Umt
(CPU) IS at the heart of the MCB
famIly. The dual~reglster set of the Z80
CPU allows hlgh~speed mterrupt pro~
cessmg, context sWltchmg and other
forms of foreground/background pro~
grammmg. Each regIster set mcludes
an 8~blt storage regISter whICh can also
be used as three l6~blt memory
address or general~purpose regIsters.
Two mdex regIsters provIde greater
memory addressmg capablllly. A 16~blt
external stack pomter permIts
unhmlted subroutme nestmg and tem~
porary data storage. In addItIon, the
CPU features vectored mterrupts and
supports dynamIc memories requmng
periodIC refresh.

Proven Design. The MCB famIly has
been used m hundreds of apphcatIons
throughout the world, demonstratmg
rehablhty and performance day after
day. All 2110g mICrocomputer boards
undergo extensIve burn~m WIth both
pre and post burn~m testing to ensure
constant performance and rehablhty.

IS-Bit Power. With the mtroductIon of
the 28000 Dual-Processor Upgrade
Package, the ophon of upgradmg
Z80-based systems to 16 bits IS
avaIlable. The Z8000 CPU-based board
proVIdes complete software development tools and 256K bytes of
RAM-and stIll allows existmg 280 programs to run.

Family Members. The 280 mICrocom~
puter board famIly mcludes powerful
CPU and memory boards as well as a
variety of versahle, hlgh~performance
1/0 expansIOn boards. The 280
Microcomputer Board (MCB) IS a com~
plete smgle~board mICrocomputer WIth
ItS own self~contamed memory plus
serial and parallel I/O ports. The 280
Memory and DIsk Controller (MDC)
adds up to 48K bytes of system memory
and mterface for up to eIght floppy
dIsk drives. The 280 Serial Interface
Board (SIB) proVIdes four hlgh~
performance serial mterface channels
to solve a variety of data commumca~
tIons problems. Analog mterface IS
SImplified with the 280 Analog Input
Board (AlB) or the Analog Input/Out~
put (AIO) board-each provIdes up to
32 mput channels and 12~blt resoluhon.
Flexible, parallel 1/0 IS provided by
the 280 Input/Output Board (lOB) with
64 I/O lmes and a liberal amount of

Make vs Buy. The make vs buy deCIsIon Impacts both strategIC and
economic Issues mcludmg new product
introductIOn schedules, product
reliablllty, text hxture deSign, resource
allocatIon, spare parts mventory, held
maintenance and many others. These
Issues all mvolve hIdden costs and
potentIal product development delays.
When all costs are consIdered, It is
often more economical to purchase,
rather than manufacture, mIcrocomputer boards.
Purchasing mIcrocomputer boards
for mltIal prodUction quanhhes and
later switching to m-house manufacture
of these boards provIdes an effectIve
compromIse solution. Zllog supports
this approach by hcensmg the
manufacture of ItS mIcrocomputer
boards. The high front-end manufacturing costs can thereby be postponed
unhl the success of the product is canhrmed by market acceptance.

Economy. Because each Z80 mlcro~
computer board proVIdes a large
number of funchons wlthm a con~
vement and compact SIze, Imple~
menhng an MCB famlly soluhon
reqUIres fewer boards and less space
than comparable alternahves. Fewer
boards mean lower power consump~
tIon, lower cost power supply, less heat
generatIon and, therefore, lower cool~
ing costs and greater economy m con~
nector and other mechamcal costs.
Feature for feature, the MCB famIly
adds up-a superior solutIon WIth
unbeatable economy.

\'WIre-wrap" area to gIve the user a
head start on specIal mterface solutIons. Memory expansIOn IS easlly
handled by the 280 RAM Memory
Board (RMB). It contains both RAM (up
to 64K bytes) and fixed memory socket
area, whlle the 280 PROM Memory
Board (PMB) allows up to 32K bytes of
non-volahle memory.

545

Z80®MCB
Z80 Microcomputer Board

~
Zilog

Product
Description

June 1982

• Complete. Powerlul Single-Board
Solution
• 16K or 4K Bytes RAM
• Industry Standard Serial Interlace
• Convenient. Flexible Parallel I/O
• Low-Power 5 V Operation
• Many User Options
• Programmable baud rates
• Relocatable address paging
• Variable I/O port assignments

OVERVIEW

The zao Microcomputer Board
(MCB) is a complete single-board
microcomputer adaptable to a wide
range of applications. As either a
stand-alone board or as the heart of a
system of bus-compatible boards, the
MCB provides the essential system
functions. Built f~om Zilog's widelyused zao Central Processing Unit
(CPU) and other Z80 peripheral components, this board provides serial and
parallel I/O, 4K or 16K bytes of
dynamic RAM and provision for up to
4K bytes of EIPIROM all on a compact
7.7 x 7.5 in. circuit board.
All address, data and control lines
are fully buffered to standard TTL
levels for easy expansion with other
boards in the zao MCB family. The
MCB employs an on-board dc-dc converter to allow operation from a single
+ 5 V power supply; the converter circuit generates the + 12 V and - 5 V
necessary for the dynamic RAM array
and - 10 V for serial communication
interface.

FUNCTIONAL DESCRIPTION
Central Processing Unit. The MCB is
controlled by the Z80 CPU WIth 158
instructions including 16-blt arithmetIc,
block moves and block 1/0, bIt
manipulation and versahle addreSSIng
modes. This powerful set of Instructions
provIdes programmIng ease and, for
convement portability, contains all
8080 instructions as a proper subset.
The CPU has an operating frequency
of 2.457 MHz derived from a 19.6608

MHz system clock and IS able to execute InstructIons as fast as 1.6 I'S.
The CPU has a powerful and versatile vectored Interrupt capabilIty
which allows identifIcation of up to 128
umque Interrupt service subroutInes
WIthout additional hardware. See the
Z80 CPU Product SpeciiIcation for
addItional Information.

547

Memory-RAM Array. The MCB
includes a dynamic Ramdom Access
Memory (RAM) array of eIther 4K or
16K bytes. A umque refresh regIster in
the CPU sends a new refresh address
to the memory array after each op code
fetch; therefore, automatic refresh IS
transparent and no wait states are
imposed. This manner of memory
refresh removes all the disadvantages
of dynamIc memory while still retaimng
economy and speed performance.
The addressable memory space may
be located at any 4K byte boundary by
changing the positIon of two jumpers
on the board. Systems requiring additional fIxed memory, such as the
Z8()® PROM Memory Board (PMB) can
thereby obtain a large block of continuous address space startIng at zero.
This same memory paging scheme
generates a RAM SELECT SIgnal
routed to the array by a pair of connectors. Thus, external hardware may be
used to dIsable the memory for bank
selection. Figure 1 shows the memory
addressing for the MCB/4 and
MCBIl6.
(HEX
ADDRESS)

8000

,

/

/><,

4000

-

,
.-><,

2000

RAM
1000
ElPIROM

MeB 4

RAM

,

/

--><,

,

>< ....

EIPIROM

MeB 16

Figure I. Memory Addressing
for MCB/4 and MCBI1S

Memory-E/P/ROM Array. The MCB
includes four 24-pin sockets that can
accommodate up to 4K bytes of nonvolatile memory. The type of memory
device to bE! used-Erasable Programmable Read Only Memory (EPROM),
Programmable Read Only Memory
(PROM) or Read Only Memory
(ROM)-can be selected by changing
the jumper wires. Although the MCB
dc-dc converter generates the voltages
required by P/ROM arrays, it cannot
deliver suffiCIent current from these
outputs to drive EPROM devices. When
2708 or 2704 EPROMs are used, external supplies must provide the required
voltages. This option is easily
implemented by selecting the
appropriate jumpers on the board.
Table 1 lists devices that can be used
in these sockets. The standard board
configuration is for the 2708.

548

Non-Volatile
Memory
MOS
E/PROM

BIpolar
P/ROM

Device
Number
2704
2708
2716

8704
8708
2316

6341
6381
82S181
82S191

Table I. Non-Volatile Memory Devices

As wIth the RAM array, addressing IS
designed to allow the user to relocate
the E/P/ROM array to any 4K byte
boundary WIthin the address range of
the CPU. A ROM SELECT output
signal and corresponding input contacts on the edge connector allow the
user to Implement shadow EIP/ROM or
select an alternate PROM set.
Counter-Timer. The Z80 CTC contaInS
four independent 8-blt counter channels whIch can be programmed by
system software for a broad range of
countIng and tIming applications. One
of the four channels is used as a baudrate generator for serial interface; the
addItional channels can be used to
satIsfy other system reqUIrements.
Each of the four channels may be
decremented either from an external
input in the counter mode or from a
prescaled version of the system clock.
Upon reaching zero, a pulse is
available from three of the channels
and Interrupts may be generated by all
four channels if they are programmed
to do so. The device will supply an
Interrupt vector indicatIng which channel is causing the Interrupt. The four
Independent input lines are each
avaIlable on a separate position of the
edge connector. The input signal may
serve as a posItive or negative trigger
for the timer mode or as the actual
event to be counted. Each output may
be used as the Input or trigger to a
subsequent channel in order to achieve
long time delays.
If an external deVICe must cause an
interrupt to IndIcate a status change,
one channel of the CTC can be used as
a vectored interrupt generator by programming In a time constant of I and
driving the input trigger with a transition signal from the external device.
Thus, when no other parallel data need
to be transferred, interrupts can occur
without using the PIO strobe line.
The output of channel I serves as the
transmIt and receive clock for the
USART, prOVIding a convenient way to

Implement software programmable
baud rates. This signal is routed to the
edge connector of the board and IS
returned on a separate contact. Consequently, channel I of the CTC may be
used as eIther the USART clock or In
the user's applIcation, depending on
edge connector wiring. See the Z80
CTC Product Specification for details.

1/0 Capability. The MCB provides
both parallel and senal I/O via a
Counter-Timer CirCUIt (CTC), Parallel
Input/Output (PIO) deVIce and a
Universal Synchronous/Asynchronous
Receiver/Transmitter (USART). These
devices occupy eleven locations of
port-assIgned I/O space as shown In
Table 2. Jumper options allow relocatIon of the I/O devices WIthin the portassigned address space.
MeB I/O PORT ASSIGNMENTS
FUNCTION

PORT

CTC Channel 0

D4

CTC Channel I

D5

CTC Channel 2

D6

CTC Channel 3

D7

PIO Port A Data

D8

PIO Port B Data

D9

PIO Port A Control

DA

PIO Port B Control

DB

SWItch RegIster

DD

USART Data

DE

USART Status/Control

DF

Table 2. MCB Port Assignments

Serial J/O. A serial data commumcation channel provides support for
eIther asynchronous or synchronous
data transfer with either half- or fullduplex signalIng. Driver and receiver
devices are included to provide RS232C compatible interface to passive
20 rnA equipment simply by relocating
two jumpers and attaching the serial
line to the appropnate locations on the
edge connector.
Although the 8251 USART IS deSIgned for polled operations, It is possible
to utilize the mode 2 interrupt structure
of the CPU by coupling the transmitter
ready and receiver ready lines from
the USART to the input lines of the
parallel I/O device. The baud-rate
clock is derived from the 19.6608 MHz
crystal oscillator and channel I of the
CTC device. This allows baud-rate
selection under program control as
shown in Table 3.

1030·001

BAUD
RATE

TIME
CONSTANT

50
75
lID
150
200
300
600
1200
2400
4800
9600
19200
38400

96

As an alternahve to the on-board
clock, user-selected Jumpers allow
mdependent transmit and receive
cloch from external sources to be
applied directly to the USART. A
single external clock operatmg at tWice
the desired frequency may be applied
to the on-board wave-shapmg fhp-flop,
thus providmg a clean, reliable clock
signa!.

64
44
32
24
16

8
4
2
I

~}

Parallel 110. The zao PIO contams two
mdependent 8-bit parallel I/O ports. It
can be configured by the CPU to
operate m any of four major
modes-input, output, bidirectional or
contro!' Data direction charactenshcs

Counter
Mode

Table 3_ Programmable Baud Rat_
lor Serial 110

r--

can be programmed mdlvldually or m
byte configuration. Each byte has two
mdependent handshake hnes for completely asynchronous data transfers
with any general-purpose interface. To
allow maximum flexlblhty for the user,
the 16 PIO data hnes and four handshake lines are totally uncommitted.
Also, four 16-pm IC sockets may be
wired to accept any necessary logiC
deVice or terminator package. See the
Z80 PIO Product SpeCification for
details.

CTCI/O

I

I

4K OR 18K BYTE
RAM SPACE

o TO 4K BYTE
ROM, PROM, EPROM
SPACE

,.,

BUFFERED

ADDRESS BUS

I
I

SYSTEM
BUS

lID
PORT
DECODe

I

zeG eTC

SERIAL

DATA

CLOCK

zaD CPU

Dl.
SWITCH

USART

BUFFERED STATUS + CONTROL 12

I

25MHZO
OSC

BUFFERED DATA BUS

PARALLEL 1/0

i-

I•

zaG PIO

20

SERIAL 1/0 (R8.232C OR 20MA CURRENT LOOP BUFFERED)

'----

Z8D'" MCB Block Diagram

1010002

549

SPECIFICATIONS
Processor
Zllog ZSO CPU
Operating Frequency
2.5 MHz
RAM Array
MCB/4
4K x 1 RAMs, tAC = 250 ns
MCB/16 16K x 1 RAMs, tAC = 250 ns
E/P/ROM Sockets
Four 24-Pm Sockets

Serial 1/0 Channels

1 Channel
Loop

~

RS232C or 20 rnA Current

Connectors

122-Pm Edge (l00 mIl spacmg)
Power

Serial Modes
Synchronous or Asynchronous

Data Rales
50 to 38.4K Baud
Parallel 110 Lines
16 Lmes wIth 4 Handshake Lmes

ElP/ROM Types
E/PROM 2704, 2708 or EqUIvalent
P/ROM 6341,6381,82S181,82S191 or
EquIvalent

+ 5 V ± 5% @ 2 A (max)
(wIth 3 PROMs)
Environmental
Temperature

HumIdIty

Physical
HeIght
WIdth

o to 50'C
a to 900/0 noncondensmg
7.5" (l91 mm)
7.7" (l96 mm)

ORDERING INFORMATION
Part No.
05-6009-01

Description
MCB/4

280 Microcomputer
Board wlth 4K bytes
RAM

550

Part No.
05-6009-02

Description
MCBIl6
280 MlCrocomputer
Board wlth 16K bytes
RAM

Part No.
05-6009-19

Description
MCBIl6
280 Microcomputer
Board with 16K bytes
RAM for use wlth
RIO™operatmg system
software

OO-J030-A

Z80®RMB
Z80 RAM Memory Board

~
Zilog

Product
Description

June 1982

I
;;
•

• Automatic Refresh by CPU for
Simple. Fast System Operation
• Low-Cost. High-Performance
Dynamic Memory
• BK Bytes of EIPIROM Sockets
Available for Flexible Memory
Arrangement
• User-Selected Address Boundaries
• On-Board dc-dc Converter Allows
Low-Power Operation
• Compatible with All MCB Family
Microcomputer Boards

OVERVIEW

The zao RMB RAM Memory Board
provides system memory expansion for
the MCB family of microcomputer
boards. Containing both RAM as well
as sockets for ElF/ROM memory, the
RMB board provides a flexible means
of implementing additional system
memory. Each board contains a dc-de
converter that generates +12 V and
-5 V bias voltages, thereby allowing
operation from a single +5 V system
power supply.

FUNCTIONAL DESCRIPTION
Address Map. The RMB memory
address selection is completely compatible with the MCB microcomputer
board. Figure 1 shows the memory
map for the RMB/l6 and RMB/4B.

Location of the memory array may be
altered by the user. The RAM chlpselect logIC allows each 4K segment to
have a starting address at any of 16
boundries WIthin the 64K of
addressable memory space. Chip
selection IS accomplished by using a
PROM decoder to select the Row
Address Strobe (RAS) sIgnal to the
appropriate bank of devICes. ThIS
method of bank selechon mmlmlzes
overall system power since only the

selected bank diSSIpates active power.
The address select PROM is socketed
so that it may be easily replaced by the
user for address reassignment.

PROM Sockets. The RMB contains
eight 24-pin sockets that may be used
for a variety of E/P/ROM devices.
Through selection of appropriate
jumpers the socket area can be configured to accept the devICe types
shown in Table l.

551

... ....,..
...
...
......
_....
FFFF

cooo.

characteristics of the MCB CPU allow
memory to be refreshed automatically
and in a transparent mode. Following
each op-code fetch, a new refresh
address is available on the system

IFFFH

Ao

-.. =x
A

address bus while the op-code is being
decoded within the CPU. The CPU
does not require wait states; therefore,
there is no degradation of system performance (See Figure 2).

MEMORY ACCESS ADDRESS

x"---__>C
REFRESH ADDRESS

_....11\'-----.11

liIiili _ _....., .....

'0••00.

,\...._----11r - - -

•

IiJIiIi - - - - - - - - - . . . . .

• • AMBMEMORY

o

·MCBI16 MEMORY

Figure Z. Automatic Refresh Generation

Figure 1. RNB Memory Map

r-Non-Volatile
Memory

Device
Number

ADDRESS
OUTPUT
ENABLE"'
.AM

MOS
ElPROM

2704
2708
2716

LAD::~UX I

8704
8708
2316

TO 14K BYTE
DYNAMIC RAM
MEMORY SPACE

CAS

~E

ANAL
DATA BUS

6341
6381
825181
825191

BIpolar
PIROM

o

I AAS

DECODER
PAOE

ADDRESS BUS

16

SYSTEM

BUS

DATA BUS

Chip selection is accomphshed by
means of a PROM decoder, supplied
socketed and unprogrammed so that
the user has complete flexibility in its
application. When using EPROM
devices the -5 V and + 12 V
requirements must be supplied from a
source external to the board.
Relresh. Although dynamic RAMs are
used, the RMB does not require any
additional CIrcuitry for refresh. Unique

~

•

CONTROL BUS

Table 1. Non-Volatile Memory Device.

BUFFER
CONTROL

J

DATA
BUS

10lOUT

BUFFER

L

•

ROM

DATA BUS

1
J

PAGE

OUTPUT ENA.LE

DECODER

J

lAND
CHIP SELECT

SELECT

I
I

'----

OTO 16K BYTE
ROM, PROM, EPROM
MEMORY SPACE

'--

Z8O'" RMB Block Diagram

SPECIFICATIONS
Memory Capacity
Dynamic RAM
EIPIROM

MemorySI.e
Standard Conhgurations
16K or 48K RAM

ORDERING INFORMATION
Part No.
Description
05-6003-02
Z80 RMB/16
16K RAM Memory
Board
05-0104-00
Z80 RMB/32
32K RAM Memory
Board

552

EnvlroDJDental

Connectors
64K
16K

122-Pin Edge (100 mil spacmg)

Power
+5 V ±5% @ 1.6 A (max)

DC-DC Converter Output
+12 V @ 320 mA (max)
-5 V @ 50 mA (max)

Part No.

Description

05-6003-04

280 RAMl48
48K RAM Memory
Board

05-6003-05

Z80 RMB/64
64K RAM Memory
Board

Temperature
HumidIty

o to 50·C
o to 90% noncondensmg

Physical
HeIght
WIdth

7.5" (191 mm)
7.7" (196 mm)

1031-001,002 00-1031-02

Z80® AIO/ AlB
Z80 Analog Input/Output
and Analog Input Boards

~

Zilog

Product
Description

June 1982

• 12-Bit Resolution and High
Accuracy
• 16 Single-Ended or 32 Differential
Inputs for Application Flexibility
• Fast 45 ms Channel Conversion
• On-Board dc-dc Converter for Convenient Low-Power Operation
• Polled or Vectored Interrupt Control for Programming Convenience
• Multiple Voltage Ranges for Easy
Interface

OVERVIEW
The Z80 Analog Input Board (AlB)
provIdes 16 differenhal input channels
that may be configured as 32 smgleended channels. Through a combination of user-selectable input voltage
ranges and a programmable gain
amphher, input sIgnals rangmg from
mIllivolts to as hIgh as 10 V can be
converted to a 12-blt word. In order to
ensure accuracy and compatibihty with
the other MCB family boards, a 5 V
dc-de converter is included as a
standard feature.
The Z80 Analog Input/Output (Ala)
Board has input features identical to
the AlB except that there are also two
12-bit D/A output channels, each wIth
a wide range of user-selectable output
voltages.

FUNCTIONAL DESCRIPTION
Input Ranges. The AIB and Ala contain an input mulhplexer, an amphfier
whose gam may be altered from I to
1000, and an analog-to-digital converter module. FIve basIC mput ranges
are shown m Table 1. The bIpolar
inputs are converted into a 12-blt value
in twos complement format; the
Unipolar inputs are converted mto a
12-blt straIght bmary value.

0.0

to
to
-2.500 to
-5.000 to
-10.000 to

aa

+ 4.9988
+99975
+ 2.4988
+ 4.9975
+ 9.9951

V
V
V
V
V

Table 1. Input and Output
Voltage Ranges

553

AmpWler GaIn. Amplifier gain is set
to I but can be changed by a resistor
substitution according to the following
formula:
20 kll
R == Gain-I
Increasing the gain of the amplifier
effectively allows the input voltage
range to be scaled by the reciprocal of
the gain factor. For example, by
increasing the amplifier gain to 1000,
an input voltage range of ±2.5 V
becomes ±2.5 mV. As the gain is
Increased the settling time of the
amplifier will also increase.
Because the Ala and AlB use a fixed
timing sequence between channel
selection and the start of data conversion, the system delay time must be
lengthened, via a resistor change, to
allow for the greater settling time of the
amplifier at higher gain (see Table 2).
Amplllier
Gain

Delay Time

,..

Resistance

1
10
100
1000

20
30
40
100

13.3
14.3
19.0
47.5

kO

equivalent single-ended input circuit is
shown in Figure 1. The multiplexer
must be allowed to settle to ± .01 %
(approximately nine time constants) to
Insure accuracy. For high source
impedance, it may be necessary to
increase the system delay time beyond
that shown in Table 2. For the differential input configuration, the multiplexer
time constant is one half of that in
Figure 1.
System Interface. The Ala and AlB
occupy 10 locations within the MCB
CPU's 110 address space as shown in
Table 3. Input status, control and data
are interfaced through a PIa while the
data for the two output channels is written to a set of 12-bit output registers.
The location of the port assignments
may be moved anywhere within valid
110 space of the CPU, with the restriction that both the PIa and output
registers must reside within the same
20H block of 110 addresses. These
address changes are jumper-selectable.
Data may be obtained in either a
polled or fully vectored Interrupt
mode. The mode is selected entirely by
software control.

Table 2. Recommended Syetem Delay
Time va Amplifier Gain

Input Modes. The standard 16-channel
differential input configuration is
recommended in areas of commonmode noise and for low-level inputs.
For input signals of 1.0 V or more, a
32-channel single-ended configuration
can be jumper selected.

Output RcmgeI. The Ala board Is
configured with two Independent 12-bit
dlgltal-to-analog convertor output
channels. Output voltage range is
selectable by the appropriate jumper
configuration. The available full scale
output ranges are shown In Table 1.
Output quantities are represented as
twos complement numbers for bipolar
ranges and as straight binary numbers
for the unipolar configuration.

Port

PlO Port A Data
PlO Port B Data
PlO Port A Control
P 10 Port B Control
Address Register
(Channel Select)
Status Register
DACI Output (Lo Byte)
DACI Output (HI Byte)
DAC2 Output (Lo Byte)
DAC2 Output (Hi Byte)

80
81
82
83
88
89
8C
8D
8E
8F

AIO
Only

Table 3. AlOIAIB Port AaalgDments

ADDRESS BUS 16

CONTROL LINES

SYSTEM
BUS

Equivalent Input Circuit. Source output impedance has an effect on the settling time of the multiplexer. The
formula for the time constant and the
DATA-BUS

SOURCE

MULnPLEXER

RESISTANCE

ON RESISTANCE

(~

'.

8

RoN
18k

C,

Co

•...F

",F

MULTIPLEXER TIME CONSTANT

= (Rg

+RgN)

Co

Z80 AlOIAlB Block Diagram

Figure I. Input Equivalent Circuit

554

1033-01

1033-02

SPECIFICATIONS
Input Characteristics
Number of Channels
32 Smg Ie-ended! 16 Dlfferenhal
ADC Gain Ranges
0-5 V, 0-10 V, ±2.5V, ±5 V,
±IO V
Amphfier Gain Ranges
I to 1000

Max Input Voltage
±26 V
Input Impedance
100 Mil, IOpF OFF Channel
100 Mil ON Channel
Bias Current

20 nA
Dlfferenhal BIas Current
10 nA
Resolution
12 BIts
Throughput TIme
Gain = I
45 I's Channel
Gam = 100
1001's Channel
Accuracy

Gain = I
Gain = 1000

±0.025% FSR
±0.100% FSR

Lmearlty
±112 LSB
Differential Lmearlty
±112 LSB
QuantIzmg Error

±112 LSB
Temperature StabilIty
Gam = I
± 30ppm of FSR/oC
Gam= 1000 ±SOppm of FSR/oC
DynamIC Accuracy

Sample and Hold Aperature
30 ms
Aperature TIme Variation
±5 ms
DIfferential AmplIfIer CMR
74 db (dc to I kHz)
Crosstalk
SO db down @ I kHz for OFF
and ON Channel

Output Characteristics
Number of Channels
2
Output Voltage Ranges
0-5 V, 0-10 V, ±2.5V, ±5 V,
±IO V

Output Current
SmA
Output Impedance
I
Resoluhon
12 bIts
Output SettlIng TIme
10 I's (max)
Accuracy

Output Accuracy
± 0.0125% FSR
Temperature CoeffICIent
± 30ppm of FSR/oC
Connector.
122-Pm Edge (100 mIl spacmg)

Power
+5V ±S% @ 1.6 A (max)
Environmental
Temperature

HumIdity

Physical
HeIght
Width

o to 50°C
o to 90% noncondensmg

ORDERING INFORMATION
Part No.
05-6075-01

Description
Z80 Ala

05-6075-02

Analog Input/Output Board
280 AlB
Analog Input Board

00 IOJJA

I

I

7.5" (191 mm)
7.7" (196 mm)

555

Z80®IOB
Z80 Input/Output Board

~
Zilog

Product
Description

June 1982

• Large User Interface Area for
Application Flexibility
• 64 Data and 16 Handshake Lines
for Easy Interface
• Fully Vectored Interrupt Operation
Allows Convenient Program
Design
• Port Assignment May Be Altered
to Allow Several lOBs in a Single
System
• Uses Z80A PIO Devices for Full
Compatibility with Other
Members of MCB Family

OVERVIEW
The Z80A Input/Output Board (lOB)
provldes system expanSlOn to external
dlgltal I/O devlCes. It lS fully compahble wlth other boards in the MCB
famlly and provides elght parallel I/O
ports to augment the two contamed on
the Z80 MlCrocomputer Board (MCB).
Deslgned for user flexlblllty, the lOB
contams four Z80A Parallel Input/Output (PIO) devlCes, a large pre-dnlled
user mterface area, dalsy-cham mterrupt pnonty 10glC and user-selectable
port address assignment.

FUNCTIONAL DESCRIPTION
The lOB can tams four PIO controllers whlch provlde 64 programmable I/O hnes. These lmes may be
conhgured elther as mdlvldual data
lmes wlth mdependent data dlrechon
or as groups of elght lmes for byteonented data transfer. The lOB glves
the user a headstart on speclal mter-

face reqUlrements by provlding a large
pre-dnlled, pre-etched mterface area.
The hole array lS spaced on .3" and
.6" centers in a flexible arrangement
that accommodates 16-pm, 24-pin or
40-pm lCs.

Parallel Input/Output. Each Z80A
PIO deVlce lS a programmable, dualport Clrcult that provldes a TTLcompahble mterface between
penpheral devlCes and the Z80 CPU.
The PIO mterfaces to penpherals Vla

two mdependent general-purpose I/O
ports deslgnated Port A and Port B.
Each port has elght data bltS and two
handshake slgnals, READY and
STROBE, whlch control data transfer.
The READY output mdlCates to the
penpheral that the port lS ready for a
data transfer; STROBE lS an mput from
the penpheral that mdicates that the
data transfer has occurred. In addlhon,
the elght output lmes from Port B can
dnve Darhngton translstors (l.5 rnA at
1.5 V).

557

Operating Modes. Each group of eight
lines is capable of being programmed
in one of four modes of operation-byte
output, byte input, byte input/output
and bit input/output.
Input Operation. The PIO device
allows fully vectored interrupt operation with a unique vector for each port.
The interrupt ability of each port may
be enabled or disabled independently
of the other ports. Interrupt priority is
established by a hardware daisy-chain
arrangement. Each group of lines has a
fixed position within the priority structure; individual lines within each port
are assigned equal pnority. (See the
Z80 PIO Product SpeCification for
details.)

PORTA
CONTROL 8US 6
PORT AlB CONTROL

PORTB

1--_ _ _ _-lZ80(~ PIG 1-----1
UNIVERSAL

SYSTEM

DATA BUS

PlO

8

INTERFACE
AREA

SUS

,.

Z80APIO

ADDRESS BUS 8

I-:'N:::'='R:-!N"'AL-:C:::ON:::'=RO::CL:::BUC:S'----!

Port Assignments. By jumper placement, the four PIOs can be placed in
any of eight 32-byte address ranges
allowing the system to be easily configured and expanded.

Z80~) PIO 1-----1

Z80A® lOB Block Diagram

SPECIFICATIONS
I/O Lines
64 Programmable
Operational Modes
Input, Output, Bldlrechonal, BIt Control
Handshake
8 Ready and 8 Strobe Lmes
Interrupt Vectors
8
I/O Port Locations
16 User·selectable wlthm l·of·8 Blocks

Output Voltage
HIGH 2.4 V (min) @ 2S0 rnA Output
Current

LOW

0.4 V (max) @ 2.0 rnA Smk
Current

Connectors
122-Pm Edge (l00 mIl spacmg)
Power

+S V ±S% @ O.S A (max)
(wIthout user ICs)

Darlington Drive Current
Port B of Each PIO
3.8 rnA (max) @ I.S V

Environmental

Input Voltage
HIGH 2.0 V (mm)
LOW 0.8 V (max)

Physical
HeIght
WIdth

Temperature

HumIdIty

o to SO°C
o to 90% noncondensmg
7.S" (l91 mm)
7.7" (l96 mm)

ORDERING INFORMATION
Part

No.

05-6006-03

558

Description

ZSO lOB
Input/Output Board

1034-001

00-1034A

Z80®SIB
Z80 Serial Interface Board

~
Zilog

Product
Description

June 1982

• Industry Standard RS-232C
Interface
• Polled or Fully Vectored Interrupt
Control for Maximum Program
Flexibility
• Single +5 V Operation
• Fully Compatible with Zilog's
MCZ-I Series Microcomputers and
PDS BOOOTM Product Development
System
• Error Detection for Reliable
Message Handling
• Four Powerful. Flexible Data
Channels

OVERVIEW
The 280 Serial Interface Board (SIB)
IS a mulhple channel serial commumcahons interface with a variety of
powerful, convement features. Four
independent channels, provided by
8251 USART devices, allow synchronous or asychronous data transfer
wIth either half or full duplex sIgnal
handlmg. All four channels have
drivers and receivers for RS-232C
system mterface and one will also
accommodate a 20 rnA current-loop
interface. A dc-dc converter
generates all necessary voltages from a
single +5 V supply. An on-board
crystal oscillator provIdes commumcahon timing independent of the system
clock.

FUNCTIONAL DESCRIPTION
The four SIB channels are capable of
mdependent operahon m either asynchronous or synchronous protocols.
The system program may imhate and
control eIther mode by selectmg the
appropriate command words. Both the

transmItter and receIver sechons are
double-buffered for maximum performance and convenience. All data
transfer status signals, such as TxRDY
and RxRDY, are available in a readable status register or as external
sIgnals so that eIther polled operahon

559

or full interrupt control may be
selected by the user under software
control. In addihon to the normal data
transmission, each channel can
generate break Signals and be individually reset under software control.
Asynchronous Mode. In the asynchronous mode, the system program
controls the number of data bits (5, 6,
7, or 8). the number of stop bits (I,
I y" or 2,) and the sense of parity protection (even or odd) if enabled. Each
channel has a programmable baud rate
factor of I, 16, or 64 controlling the
relationship between the transmitted or
received data rates and the frequency
of the baud rate reference clock. See
Figure 1 for a description of the asynchronous mode control word. Error
detection signals are available for each
channel and may be read from the
channel status register; these signals
include panty error (PE), framing error
(FE). and receiver overrun error (OE).
Figure 2 describes the channel status
register.
Synchronous Mode. In the synchronous receive mode, character synchronization may be obtained from an
external device or internally from the
received data stream. The nature of the
SYNC connection for each channel is
programmed as either an input when
the channel is expecting an external
sync signal or as an output to identify
that sync has been achieved. In addlhon, each channel may be programmed to operate with either smgle
or double synchronizing characters.

Baud
Rate
50
75
110
134.5
150
200
300
600
1200
2400
4800
9600
19200
38400
*CTC

Timing. The transmitter and receiver
clocks for each USART channel can be
derived from either the on-board

--1
7

6

I I I

5

4

3

2

..

0

IntClrrupt Control. Each channel may
be selected to operate in either a
polled mode or a fully vectored interrupt mode. The interrupt capability for
each channel may be enabled or
disabled by the programmer to allow
mixing both modes. Each channel may
be programmed to have a umque interrupt vector for the receiver ready and
the transmitter ready signals, allowmg
mdependent mterrupt service
subrouhnes for each direction of data
transfer. Interrupt priorities are assigned by the hardware on a dalsychain basis. The four receiver ready
signals are given prionty over the four
transmitter ready signals. The channel
priority for each group ranges from
channel 0 having highest priority to
channel 3 the lowest.
Hardware Interface. Each of the four
channels has drivers and receivers to
allow full mdustry standard RS-232C
mterface parameters to external eqUipment. All voltages necessary for this

crystal oscillator, thereby enabling
operations to be independent of the
main system clock frequency, or provided externally by the appropriate
jumper selection.
For internal clock signal generation,
input signals to two Counter/Timer Circuits (CTC) can be jumper-selected to
be either 112 or 1132 of the crystal frequency. The outputs of the CTCs are
further divided by flip-flops to provide
a 50% duty cycle to the USARTs. By
programming each channel of the third
on-board CTC with the proper time
constant, baud rates of 50 to 38.4K are
possible. Table 1 shows time constants
for vanous data rates when the USART
has been programmed for a baud rate
faster than 16.

In

Time Constant
Decimal
Hex
96
64
44
36
32
24
16
8
4
2
4'
2'
I'

60
40
2C
24
24
18
10
8
4
2

ADDRESS RANGE

J4 JUMPERS

00 to IF
20 3F
40 SF
60
7F
80 9F
AO
BF
CO
DF
EO
FF

5-16, 1-7,3-6
5-15, 1-7,3-6
5-16,2-7,3-6
5-15,2-7,3-6
5-16, 1-7,4-6
5-15, 1-7,4-6
5-16,2-7,4-6
5-15,2-7,4-6

4'
2'
I'

counter mode

Table 1. Baud Rate vs Time Constant
for 16 X Baud Rate Factor

7

BIT NO.

6

Table 2. Port Address Range

5

4

3

2

..

0

BIT NO

I I I I I CONTROL CODE

T

~:;:O~-:::"."
10
11

BAUD RATE FACTOR
ASYNC MODE, l6X
BAUD RATE FACTOR
ASYNC MODE, 64X

k-t-f-f-f-f-f-t-SYNDET

TxRDY
RxRDY

BAUD RATE FACTOR

00
01
10

5 BITS PER CHARACTER
6 BITS PER CHARACTER
7 BITS PER CHARACTER

11

8 BITS PER CHARACTER

CONDITION OF NAMED SIGNALS

'----TxEN
PE

'-----

~~~I~~~~RAO:ARITY ERROR
IS DETECTED

'------ ~ ~ ;~~:~~ ~~f:ci
1-_ _ _ _ _ _ ~ ~ ~~~NP~:~Tiy

'---------

00

INVALID

11

2 STOP BITS

~~ ~ ~T~:O~11ITS

Figure 1. Channel Mode Control Word

560

OE

THESE BITS

ARE RESET
BY BIT 4 (ER)
OFTHE
COMMAND
INSTRUCTION

'------

~~f~W:NE::~~S NOT BEEN READ
BEFORE RB IS FILLED WITH THE
NEXT CHARACTER

FE
FRAMING ERROR (ASYNCHRONOUS
'-------

S~~~E~Ni 'VALID STOP BIT IS NOT
DETECTED AT THE END OF
EVERY CHARACTER

Figure 2. Channel Status Register

1036-00 I, 002

mterface are provided by the dc-de
converter operatmg from a smgle +5 V
mput. Channel 3 IS supplied with an
active 20 rnA current loop mterface
which the user may disable m favor of
the RS-232C mterface by selecting the
appropriate jumper. In addlhon to the
separate transmit and receive data
signals, standard modem control
signals such as DSR (data set ready),
DTR (data termmal ready), CTS (clear

to send), and RTS (request to send) are
provided for each channel. The sense
of each channel's mterface IS Jumperselectable so that the board may
behave as either a terminal devICe or a
modem device.
Port Selection. The SIB utilizes port
assigned I/O and occupies locahons
within the I/O port assignment space.
By selecbon of appropriate Jumpers

thE! user may place the SIB into any
one of eight port address ranges, each
offering 32 available port addresses.
Table 2 shows the possible address
ranges for the SIB. Each of the four
USARTs and the three CTCs may be
placed at a unique location within the
selected range. The user selects the appropriate jumper configuration for the
location.

r---1-____________________________________________________~~le~O;N~T;,RO~l~4--------------;
J + EXT
~E-XT-e-l-K----------------------------------------------~I Bii~R ~

ADDRESS BUS

I
I

16/

DATA BUS

BUFFER

CONTROL

I

ADDRESS
I/O
DECODER

J

....-..L..----L.._..L..--,

~ EXTl II elK* JI
eLK

I

zeD eTC

SEL

I/O SELECT

1j.--------t-------------------------+--1
TxRDY

SYSTEM
BUS

8/

,_ TxRDY

DATA
BusJ
BUFFER
~

INTERNAL
DATA BUS

1
RS 232C OR 20mA 110

~xRDY

1/0 SELECT

1

USAAT

RS·232C 110

zeD eTC

zeD eTC

RxRDY

DATA BUS

t

4_'-

USART

USAAT

--

USART

J

RS·232C 1/0

RS--232C 110

Z8D SIB Block Diagram

1036 Oil]

561

SPECIFICATIONS
Number of Channel.
4

Synchronization Method
External or Internal Character Match

Power

Mode
Full or Half Duplex

Interface
Channels 0-3
RS232C
Channel 3
Current Loop Available

Environmental
Temperature
Humidity

o to SO°C
oto 90% noncondensmg

Physical
Height
WIdth

7.S" (191 mm)
7.7" (196 mm)

Baud Rates
SO to 38.4K Baud
Baud Rate Reference Clock
19.6608 MHz

Connectors
122-Pm Edge (100 mil spacmg)

+S V ±S% @ I.S A (max)

ORDERING INFORMATION
Part No.

05-6007-01

562

Description
280 SIB
Serial Interface Board

OO-1036-A

Z80®pPB

PROM Programmer Board

~
Zilog

Product
Description

June 1982

• Flexibility to Program a Wide
Range of E/PROMs
• Complete Programming Circuitry Generates All Required
Programming Voltages
• Zero Force Insertion Sockets for
Reliability and Ease of Use

OVERVIEW
The 280 PROM Programmer Board
(PPB) lS designed to be used in conjunction with the Z80 Mlcrocomputer
Board (MCB) to program a vanety of
MaS EIPROM or bipolar PROM
devices. The PPB is available in two
configurahons, PPB and PPBIl6, each
capable of programmmg a specific
type of E/PROM. All necessary programmmg voltages are generated on
the boards making them completely
compatible with the MCB family,
MCzrM microcomputers or ZDS
development systems.

FUNCTIONAL DESCRIPTION
The PPB uses 280 PIa devices to
interface between the E/PROM sockets
and the system microprocessor. Single·
byte data transfers in both directions

permlt either readmg or programmmg
of the selected E/PROM socket. Add,tiona I parallel I/O lines control the
mode of operation and provide chip
select to the desired socket.
Zero force insertion sockets are used
in the programming locahons to provide convemence, reliabllity and long
hfe. The programmer board extends
beyond the card cage for easy access
to programming sockets mounted near
the board edge. Each board contains
one 16-pin and two 24-pin sockets.

Device
MOS E/PROMs
2704
2708
Blpolar PROMs
7610
7611
7620
7621
7640
7641

Organization

512 x 8
1024 x 8
256
256
512
512
1024
1024

X 4
x 4
x 8
x 8
x 8
x 8

Table I. PPB E/PROM Devices

563

PROM Types. The PPB is designed to

r-

program 2704 and 2708 EIPROM
devices and Harris-type bipolar
devices. (See Table 1 for device selection.) The PPB/!6 allows programming
of 5 V 2716-type EIPROM devices and
Signetic-type bipolar devices (see
Table 2).

ADDRESS BUS

I

I/O
ADDRESS
DeCODe

MOS
EPROM
SOCKET

t
PROGICS (2)

'--+
DATA BUS
SYSTEM

BUS

CONTROL
BUS

Device

•

Organization

•

f

I

VPPSNcc;:e (2)

zaG PIG

INTERNAL DATA BUS

PROGRAM

•

I
PROG
PULSE
DRIVER

•

ADDRESS BUS
BC

M05 E/PROMs
2716
Bipolar PROMs
825126
825129
825130
825131
825140
825141
825180
825181
8252708

2048 x 8
256
256
512
512
512
512
1024
1024
1024

X

X
X
X

X
X
X

J
I

1

x4
X

4
4
4
8
8
8
8
8

I

BIPOLAR PROM
SOCKETS

---

PROG
DATA
DRIVERS

I

J

ZaG@ PPB/16 Block Diagram

rTable 2. PPB/16 E/PROM Devices

I/O
ADDRESS
DeCODe

ADDRESS BUS 8

MOS
EPROM
SOCKET

Software. Both programmer boards
are supported by the Z-PROG utility
which is part of Zilog's RIOTM
operating system. Z-PROG is an easy
to use interactive program that allows
EIPROMs to be read, programmed
from disk file and duplicated, and
allows the user to select the appropriate socket by specifying the
ElPROM type and the word length.
Z-PROG also provides address boundary selection for partial E/PROM
programming.

PROG/CS (2)

t-

t

I

VPPS/VCCB (2)

I
PROG
PULSE

DRIVER

DATA BUS 8

zaG PIO

SYSTEM
BUS

CONTROL
BUS

•

I

INTERNAL DATA BUS

BC

-

'-----

PROGRAM
ADDRESS BUS

J
I

zaD PIG
BIPOLAR PROM
SOCKETS

PROG.
DATA

DRIVERS

I

I

'--

zaG@ PPB Block Diagram

SPECIFICATIONS
E/PROM Sockets
One 16-Pin Zero Force InsertlOn
Two 24-Pin Zero Force Inserhon
E/PROM Types
24-Pm M05
2704 (512 x 8) PPB
2708 (1024 X 8) PPB
2716 (2048 x 8) PPBIl6
24-Pm BIpolar
7640 (1024 X 8) PPB
7641 (1024 x 8) PPB
825140 (512 X 8) PPB/16
825141 (512 x 8) PPBIl6
825180 (1024 x 8) PPBIl6

825181 (1024 x 8) PPBIl6
8252708 (1024 x 8) PPB/16
16-Pin Bipolar
7610 (256 x 4) PPB
7611 (256 X 4) PPB
7620 (512 x 8) PPB
7621 (512 x 8) PPB
825126 (256 x 4) PPBIl6
825129 (256 x 4) PPBIl6
825130 (512 X 4) PPBIl6
825131 (512 x 4) PPBIl6
Control Interface
TTL Interface WIth MCZ Senes Data,
Address and Control SIgnals

Connectors
122-Pm Edge (100 mIl spacmg)

Power
+5 V ±5% @
2.5 A dunng Programming
1.5 A during Read
Environmental
Temperature

HumidIty
Physical:
HeIght
WIdth

o to 50°C
o to 900/0 noncondensmg
9.0 In. (229 mm)
7.7 m. (196 mm)

ORDERING INFORMATION
Part No.
05-6005-01
05-6079

564

Description
Z80 PPB
PROM Programmmg Board
280 PPBIl6
PROM Programming Board
1045-001

1045·002

00-1045-A

Z80®pMB
Z80 PROM Memory Board

~

Zilog

Product
Description

June 1982
N

I

• Flexible Application
• Allows several types of EIPIROMs

•iI

• Variable address selechon

• Includes Z8D PIO and CTC Devices
for 1/0 Expansion
• Allows Expansion Up to 32K Bytes
of Non-volatile Memory
• Fully Buffered for Compatibility
with All MCB Family Boards

OVERVIEW
The Z80 PROM Memory Board
(PMB)' desIgned for memory expansIOn
m systems whIch reqUIre a large
amount of fixed memory, proVIdes up
to 32K bytes of fixed program or data
storage. Completely compahble WIth
the Z80 MCB, the PMB IS mterchangeable WIth other memory boards
wlthm the MCB family.

FUNCTIONAL DESCRIPTION
Memory Array. The PMB contams 16
24-pm sockets to accommodate a variety of E/P/ROM devICes as shown m
Table 1. Flexlblhty m the selechon of
the devICe type is provIded in the form
of Jumpers that may be installed on a
16-pm component carrier. ChIp selechon logIC allows each socket wlthm the
array to be configured to have a
umque address startmg on lK byte
boundaries. In addlhon, each socket
may be programmed to have eIther a
lK byte or 2K byte granularity dependmg upon the memory devICe chosen.

Chip selechon is accomplished by a
pair of socketed 32 X 8 PROMs.
Parallel 1/0. An on-board Z80 PIO
devICe provIdes addlhonal system 1/0
via 16 status or data Imes whICh may
be conhgured indIVIdually or In two
groups of eIght. (See Z80 PIO Product
SpecIiJCailOn for addlhonal deta!ls.)
There are two sets of Ready-Strobe
handshake Imes for each group of 1/0
Imes. Drivers for both ports are proVIded for use m the output mode; termmatJon resIstor sockets are ava!lable
for use m the mput mode.

Non-Volatile
Memory
MOS
E/PROM

BIpolar
PIROM

Device

Number
2704
2708
2716

8704
8708
2316

6341
6381
82S181
82S191

Table 1. Non-Volatile Memory Devices

565

Counter/Timer. An on-board Z80
CounterlTimer Circuit provides
expanded timing capability. The zao
CTC includes four independent 8-bit
counter/timers and can be programmed by system software for event counting, interrupt and interval timing, and
general clock rate generation (See ZaD
CTC Product Specification for specific
details.)

r-CONTROL BUS

~ru=~~:u1

I ~~: lADDRESS BUS.

,

CTC 110

SYSTEM
BUS

Port Aaalgmnents. The chip select
logic allows each of the two I/O
devices (CTC and PIO) to be located
within anyone of eight port assignment
blocks each containing 20H bytes for
I/O locations. Each device must occupy
four consecutive locations within the
chosen block. The configuration
desired by the user is easily achieved
by selecting appropriate jumpers that
reside on component carriers.

DATA BUS

ADDRESS
DECODE

I

I t

•

OTO 32K BYTE

ROM. PROM, EPROM
MEMORY SPACE

INTERNAL CONTROL IUS

Z80CTC

.1

DATA BUS

.,

aUFFER

•

PORT A

PORT AlB CONTROL

J.... INIOUT

INTEFINAL DATA BUS

,

.1

~

PORTA

TRI-8TATE

CONTROl
Z'D~O

BUFFERS

•

PORT B

PORT 8

-

-

ZlII'" PMB Block Dlogram

SPECIFICATIONS
Memory Capacity

32K (Populated with 2K DeVIces)

ElP/ROM Socket Array
Number 16 (24-pln)

ElP/ROM Device Type.
2708, 2716, 6381

Parallel I/O
Number of Llnes-16 (Programmable)
Operating Modes-Input, Output,
Bidirectional, Bit Control
Handshake Llnes--Ready, Strobe
Interrupt Vectors--2 (User Programmable)

Counter, Timer

Channela
4 (8 Bita Each)
Interrupt Vectors
4 (User Programmable)
Connector

122-Pln Edge (100 mil spacing)
Power
+SV ±S%
@ 0.60 A (max)
@ 2.28 A (max)
@ 3.40 A (max)
@ 0.84 A (max)

-S V ±S%
@ 0.96 A (max) 2708
+12V±S%
@ 1.28 A (max) 2708
DC-DC Converter Output
+12 V @ 320 mA (max)
-S V @ 50 rnA (max)
Environmental

without Memory
2716
6381
2708

Temperature 0 to 50°C
Humidity
0 to 90% noncondensmg

PhY8Ica1
Height 7.S" (191 mm)
Width 7.7" (196 mm)

ORDERING INFORMATION

Part No.
05-6023-01

Deec:rlptlon

zao PMB

PROM Memory Board

566

1032·001

OO·1032·A

Z80®MDC
Z80 Memory and Disk
Controller Board
Product
Description

June 1982

• CRC Error Checking for Reliable
Data Transfer
• Control Signals Allow Expansion
Up to Eight Full Size. Single Density Floppy Disk Drives
• Memory Array Allows Complete.
Compact System Integration
• Reliable and Proven Frequency
Modulation Recording Technique
• CPU-Controlled Access Allows
Complete Software Flexibility
• Low-Power Operation from a
Single +5 V Supply

OVERVIEW
The Z80 Memory Disk and Controller
(MDC) board IS a floppy dIsk controller
capable of handlmg up to eIght floppy
dIsk drives and provIding sockets for
16K to 48K bytes of addlhonal mam
system memory. A member of the MCB
famIly. the MDC IS completely com·
patible wIth the other mICrocomputer
boards in the sertes.
The MDC IS most effechvely used
with the MCBII6 MIcrocomputer
Board. Together these two boards comprise a complete mICrocomputer system
that includes 64K bytes of RAM. 4K
bytes of PROM, parallel interface,
serial interface, and control of up to
eight floppy dIsk drtves-on a 115 sq.
m. ClrcUlt board whIch operates from a
single +5 V power supply.

FUNCTIONAL DESCRIPTION
Memory Array. The memory array IS
Implemented usmg 16K X I-bIt
dynamIc RAM devICes to provIde 16K
bytes to 48K bytes of mam system
memory. Although dynamIc RAMs are
used m the memory array, addlhonal
refresh clrcUltry is not reqUlred due to
the umque memory refresh charactertShc of the MCB CPU. Followmg each

op-code fetch, a new refresh address is
avaIlable on the system address bus
whtle the op-code is bemg decoded
wlthm the processor.
An on-board dc-dc converter
generates the -5 and + 12 V sIgnals
for the dynamIc memory devICes,
enablmg the MDC board to be
operated from a single +5 V power
supply.

567

Memory address selection is completely compatible wIth the MCBIl6.
ThIs two-board combinatlon provIdes
64K bytes of continuous memory wIthin
the address space of the MCB CPU.
For maximum flexIbility, the RAM chIp
select logic is designed to allow the
memory to be addressed in 4K byte
blocks that may be located anywhere
within the address range of the CPU.
ChIp selechon is accomplished usmg a
PROM decoder to select the Row
Address Strobe (RAS) signal to the
appropriate bank of devices. This
address select PROM is socketed so
that it may easily be replaced by the
user for address reassIgnment.
Disk Control. The disk control signals,
formatting information and data
transfer are provided by the CPU
under program control. A PIO device
is used as the interface element to
transfer disk control and status mformation between the CPU and the control
circuitry on the dIsk drive umts. DIsk
status signals mclude READY, TRACK
0, SECTOR MARKER, WRITE PROTECT, and CRC ERROR. The control
SIgnals are DIRECTION, STEP, four
DISK SELECT lines, READ, WRITE,
imd ENABLE CRC.

-

The MDC includes a CRC used during read and write operations. This circuli generates a 16-blt word whICh IS
appended to the end of the data stream
during write operations. During read
operations a 16-bit word is again computed and then compared with the
value preViously written on the disk. A
CRC error condition causes an error
flag to be read into the CPU through
the PIO interface.
Data is recorded onto the floppy
diskette in a serial format. Parallelto-serial and serial-to-parallel data
conversion is performed by on-board
circuitry. During the frequency

FORWARD/BACKWARD
LINKAGE FOR FILE
MAINTENANCE

16 BYTES

, ,

1 BYTE

SECTOR ADDRESS-

100 A4A3A2A1Ao

1 BYTE

18

1

o TO 48K BYTE
DYNAMIC RAM MEMORY

DATA
SEPARATOR

I

I
I

DISK CONTROL

DISK STATUS

J

PARALLEL
TO SERIAL

REGISTER

I
I

DATA

~

BUS

2 BYTES

8

CPU CONTROL BUS

SYSTEM

4 BYTES

TRACK ADDRESSo AsAsA4A3AZA1AO

SPACE

DISK READ DATA

128 BYTES

Figure I. Sector Data Format

BUFFERED DATA

BUFFERED ADDRESS

modulation recording mode, each data
bit recorded on the diskette has an
associated clock bit recorded.
Formatting of serial data into the
disk is accomplished under program
control by the MCB CPU. Optional
PROM-based firmware to control up to
two Shugart 80lR Floppy Disk Drives
is available from Zilog. This firmwave
assumes that 32 data sectors (records)
are utilized per track and 77 tracks
are uhlized per disk. The firmwave
provides all control functions for the
disk and performs all data transfer. The
sector data format IS illustrated m
Figure 1.

CIRe
GEN/CHK

DATA
ENCODER

I

zao PIO

DISK WRITE DATA

WAIT LINE
WAIT CONTROL

~

r-

Z8D MOe Block Diagram

568

1035-001,002

SPECIFICATIONS
Disk Drive Capability
8 Smgle-Slded Drives

Memory Capacity
48K Bytes

Power
+S V ±S% @ 1.6 A max.

Disk Drive Characteristics
Sector Type
Hard
Recordmg
Smgle DensIty
Sectors per Track
32
Tracks per DIsk
77
CapacIty
308K Bytes Data

Memory Configurations
16K, 32K, or 48K Bytes DynamIC RAM.
Each 4K page may have ItS startmg
address assIgned to any of 16 possIble
values.

Environmental

Data Transfer Mode
Programmed I/O

Connectors
122-Pm Edge (l00 mIl spacmg)

Temperature

HumIdity

Physical
Height
WIdth

o to SO°C
o to 90% noncondensmg
7.S" (l91 mm)
7.7" (l96 mm)

ORDERING INFORMATION
Part No.

Description

Part No.

Description

Part No.

Description

05-6011-04

Z80 MDC/!6
16K Memory and Disk
Controller

05-6209-00

Z80 MDC/32
32K Memory and DIsk
Controller

05-6011-02

Z80 MDC/48
48K Memory and Disk
Controller
N

•=
g

569

Z8000™ Dual-Processor
System Upgrade Package

~

Product
Description

Zilog

June 1982

Features

• Upgrades an MC2™ or PDS system to a
16-bit system wIth 256K bytes of memory.

I

• Provides complete 28000-based software
development tools that execute at 6MHz:
screen edItor, translator, compiler!
assembler, debugger.

II

;I

• All software supplied in source code
form to allow customization for
applications.
• Existing 280 programs continue
to run.

Overview

The 28000 Dual-Processor System Upgrade
Package provIdes 16-bit processing power,
256K bytes of random access memory, and
software development tools for 2ilog's
280-based MC2 and PDS systems. The package
consists of a 28000 Microprocessor Board
(MPB/256), a screen edItor, 280 to 28000
translator, and a 28000 assembler and
debugger.

The 28000 MPB plugs directly into the
backplane of the 280 system and works with
the 280 and RIO. When the 28000 is runmng,
the 280 acts as a perlpheral processor that
manages the resources of the host system.
When the 28000 is not activated, the system is
controlled by the 280 and there is no functional change due to the additional
28000 MPB.

Functional
Description

Hardware. The 28000 MPB contains a 6MHz
28001 CPU and 256K bytes of RAM. The board
uses a FIFO for Inter-CPU block transfers. The
FIFO is Implemented using control logIC and a
lKx8 static RAM chip and can be accessed
sequentially by eIther the 280 or the 28000.
Software resolves any contention for
ownershIp.
The MPB can be plugged dIrectly Into the
top slot of an MC2-1/05 WIth no modlhcatlon to
the system. Or, It can be used In any vacant
slot of an MC2-l/20 or PDS 8000 system, and
may reqUIre minor modifICation to the
backplane.

Software. The software tools provIded WIth the
28000 Dual-Processor System Upgrade
Package Include a screen edItor, Y (a multllevel language compIler), a symbolic debugger, a 280 to 28000 translator, and the
Interface software between the 280 and 28000.
The screen edItor takes advantage of the
6MHz 28000 and 256K RAM to provIde an
easy-to-use, efhclent means of entering and
modIfYing programs. The screen provIdes a
"Window" over the current copy of the hIe In
memory. The cursor may be moved anywhere
In the Window to indICate the posItion where
characters are to be added, deleted or

571

Functional
Description
(Continued)

572

replaced. In addition, commands are available
to find and change strings of text and to
delete, move or copy blocks of text. The
screen editor is designed to be used with an
Infoton 200 or a Visual 200 terminal. It can,
however, be modified to work with almost
any CRT.
The compiler, Y, is a multi-level language.
It includes Z8000 assembly language with Zilog
mnemonics, Pascal-like control structures, data
types, arithmetic expressions with automatic or
specified allocation of registers, procedure
calls with parameter passing, and a descriptive
compiler language. The different levels may,
for the most part, be freely mixed. The Y compiler features direct, one-pass code generation

into memory, immediate execution of
statements, conditional compilation, userdefined language extensIOns and symbolic
debugging.
The debugger can operate in two modes:
Debug and Command. With the symbolic
debugger in Debug mode, any instruction
typed is executed immediately, with registers
preserved from one line to the next. In addition, there is a specIal set of debug commands.
The set includes commands to display and
change memory and/or registers, set and
remove breakpoints (up to eight), locate
strings in memory, display stack history and
execute a speCific number of instructions.

Development Products

Zilog

Comprehensive Developmenl
EnvlroDlDeDls for
All Illog Microprocessors
Innovative Design. Zilog's development system products feature ideal
environments for software development
for the za, zao, and zaooo microprocessors. The modularized design
approach of the Zilog development
systems allows the user a choice of
hardware and software modules to meet
current needs, while providing the
necessary upgradability for future
reqUlrements.
Proven Components. The PDS 8000
Family and ZDS-l Family of develop·
ment systems provide development
support for the za, zao, and Z8000
mICroprocessors. The PDS 8000 systems
are software development stations,
while the ZDS-l systems contain inte·
grated Z80 emulators, which permit full
hardware and software debugging of
the zao target system. Each of these
systems offers variable configuration
choices and extra card slots for additional peripherals. Ample prOVISIOns
have been made for the expansion of
memory, disk-storage, PROM program·
mlng, and external Interface. And each
system is supplied with Zilog's fieldproven RIO operating system and the
necessary utilities.
The Z-LAB concept partitions software and hardware development tools
Into speCially tailored devices. Software and hardware checkout are
handled by separate but compatible
products. You can develop software on
both Zilog and non-Zllog hosts uSing
available compilers and crbsscompilers. In either case, compatible
hardware emulation systems are
available at several levels of compleXity. Standard RS-232 links provide
for uploading and downloading of programs between hosts and emulators.
System 8000 Z-LAB, a hlghperformance, multIUser, multitasking
software development host combines
the Zilog System 8000 and the Z-LAB
concept. The 6 MHz zaOOO-based

System 8000 hardware incorporates a
high-performance Winchester disk, as
well as intelligent disk and tape controllers to further improve performance. ZEUS, the UNIX*-based
operating system, IS speCifically
deSigned for software development and
text processing. Numerous development tools are available, including the
programming languages PLZIASM,
PLZ/SYS, C, FORTRAN 77, and
Pascal; various libraries; and a symbolic debugger. Because ZEUS treats
emulators as System 8000 peripherals,
System 8000 Z-LAB can combine with
EMS 8000, Z-SCAN 8000, ZDS 1140, or
with non-Zllog emulators to provide
total product development support for
multiple microprocessors.
The newest addition to Zilog's
development products, EMS 8000, is a
sophisticated emulation management
system that aids in the development of
zaooo implementahons. By providing
logiC state analYSIS, high-speed emulahons (up to 6 MHz), complex triggering, a large real-hme trace buffer, and
large mappable memory, emulation
and debugging are made both easier
and faster.
Yet another aid to zaooo emulation IS
Z-SCAN 8000. An in-Circuit emulator,
Z-SCAN IS also zaOOO-based. It can be
configured as a stand-alone unit, as
well as linked to System 8000 or to any
other mainframe host. Or it can be
used as a peripheral to Zilog's PDS
8000 or ZDS/I systems.
The za and zaooo Development
Modules are complete Single-board
mICrocomputers that permit the development of code for the Z8 or zaOOO.
They faCilitate prototyping With large
wire-wrap areas and are totally transparent to the CRTs and host CPU
systems.

Software. To faCilitate program development, Zilog offers the complementary
PLZ application languages, PLZlSYS
and PLZlASM. Similar constructs

Within the PLZ languages permit the
user to combine high-level, machineindependent modules together with
machine-dependent modules.
PLZ/SYS IS a procedure-Oriented
language With a style that blends
elements of other well known
languages such as Pascal, ALGOL,
PLII and C.
PLZlASM is a structured assembly
language that provides all the
capabilihes needed to manage the
mIcroprocessor resources such as
registers, memory accesses, and I/O
operahons.
This modular programming techmque enables the programmer to concentrate on program design rather than
on development system software.
The zaooo Cross-Software Package,
running on UNIX, enables mulh-user
access for enhanced software development. The package consists of a complete set of software tools for developing zaooo programs on DEC's PDP
11144, 11145, and lInD systems. The C
language, including compiler and code
ophmlzer, protects the user's software
investment by permitting program
transportablhty.
The ZRTS Kernel, a small execuhve
program, saves software development
time by prOViding the core of a realhme mulhtasking operating system In
PROMable form. Using ZCL, a hlghlevel configuration language, the
designer can define the target system
and produce a memory-effiCient, costeffechve end product.
Even more software products include
the RIO Electric Blackboard, a multiwindow full-screen text editor, and software development packages With uhhty
programs that aid and simplify software
development for the za MCU and for
zaooo programs on the zaooo Development Module.
"'UNIX

IS

a trademark of Bell LaboratOrIes

575

System 8000™ I-LABTM

~

Product
Description

Zilog

Apnl19S2

Features

• A 6 MHz ZSOOlA CPU and three zaOlOA
Memory Management Units (MMUs). This
combination provides high performance and
a potential SM bytes of address space,
enabling the System SOOO Z-LAB (Figure 1)
to support advanced software tools.
• ZEUS, Zilog's enhanced UNIX· operating
system. It supports S or 16 users in a software development environment that
improves programmer productivity.

system reliability, and a large physical
memory size improves system performance
by minimizing the amount of swapping
done.
• System SOOO Z-LAB and ZEUS are designed
to be upgraded for use with 32-bit
microprocessors. This assures compatibility
with the next generation of microprocessors.

• Comprehensive text processing software and
a screen-oriented text editor. Both automate
tedious tasks involved in developing software and documentation.
• Universal software development host. It supports all of Zilog's microprocessors directly
and can support other microprocessors with
the addition of cross software packages.
• A selection of high-level languages for the
ZSOOO: C, Pascal, Fortran 77, and PLZlSYS.
The implementor can choose the language
appropriate for the application.
• In-circuit emulators are peripherals. This
enables the System SOOO Z-LAB to support
multiple emulators for different
microprocessors concurrently and allows
existing emulators to be used.
• Presently 1M byte of error-correcting
memory. Error-correcting memory increases
* UNIX 18

a trademark of Bell LaboratorIes 2110g IS hcensed by

Western ElectrIC Company, Inc.

General
Description

System SOOO Z-LAB is a high-performance
zaOOO-based system that combmes the Zilog
System SOOO and the Z-LAB concept. The
Z-LAB concept for microprocessor product
development separates hardware and software

Figure I. System 8000 Z·LAB

development tools into specially tailored
devices; mcreases the effectiveness of each
development tool; and assures that each
development tool works alone, With the other,
and With those made by other companies.

577

t•
i

I
E

General
Description
(Continued)

_~c~~
I

I

I

______ r----~~L~ILOG

L

~TOR

---------~
~~

Figure 2. Example of System 8000 Configuration

System 8000 Z-LAB can be combined with
EMS 8000, Z-SCAN 8000, ZDS 1/40, and nonZilog microprocessor emulators to provide
complete product development support for
multJple microprocessors (FIgure 2). This IS
possible because emulators are treated as
peripherals to System 8000 by the ZEUS
operating system.

Software. ZEUS is a general-purpose, multiuser, multitasking operating system designed
speCifically for software development and text
processing. The structure of the ZEUS programming environment is shown in Figure 3.
The major operating system features are:
• Hierarchical file system
• Compatible file, device, and interprocess
input/output
• Separate code and data address spaces
• Multiple processes per user
• User configurability
The system utilities include the command interpreter and file maintenance, status inquiry,
and system accounting programs. The command interpreter is selected on a per-user
basis, enabling the system to be tailored to the
needs of different users. Data communications
utilities are also included for handling
peripheral emulators and for networking over
a serial link to other local or remote ZEUS- or
UNIX-based computer systems.
OPERATING
SYSTEM

DEVELOPMENT
TOOLS

Figure 3. The ZEUS Programming Environment

578

The ZEUS development tools consist of programming languages, libraries, a symbolic
debugger, and more than 150 other utilities to
aid software development. Z8000 programming
languages include C, PLZ/SYS, and the
PLZIASM assembler. There are optional Z8000
Pascal and Fortran 77 compilers, an optional
PLZIASM assembler for the Z8, a Z80 C
compiler, and a Z80 assembler.
To increase editing speed, Zilog includes a
screen-oriented text editor in ZEUS. This editor
uses a data base of CRT terminal control information, allowing it to be used with almost any
cursor-addressable CRT termmal. This data
base can be easily updated by the user to add
new terminals.

Hardware. The System 8000 hardware was
designed to support the ZEUS software. The
memory management architecture of System
8000 allows ZEUS to support, without changes,
programs that run under the UNIX operating
system. The memory architecture also makes it
possible for user programs to have an address
space of up to 8M bytes; future versions of
ZEUS will take advantage of this large address
space.
System 8000 hardware is designed for performance, reliability, and future growth. Performance is based on the 6 MHz Z8001A CPU
and high-performance Winchester disks. The
1M byte of error correcting memory that can
be put in a system minimize the amount of
swapping done, also contributing to the
system's performance. Intelligent disk and tape
controllers also aid performance by removing
devICe handling chores from the CPU. Hardware reliabihty comes from the exclusive use
of error correcting memories and Winchester
disks. The Z-BUS Backplane Interconnect
(ZBITM) and the modular system packaging
allow for system growth. The ZBI makes it
2143-001,002

General
Description
(Contmued)

possIble to add memory and controllers to the
system. The modular packaging permits the
economical addItion of peripherals to the
system while allowing It to keep the same
appearance.

32-Bit Future. System 8000 was designed to be
upgraded to the next generation of mICroprocessors. The ZBI is a 32-bit bus, the
Software

The ZEUS operating system is an enhancement of the seventh edihon of the UNIX
operating system and wIll also incorporate
UNIX System III features. ZEUS IS a
transported operatmg system; it was not rewritten. This transporahon was possible because
the operating system was written m C, a highlevel systems Implementahon language. Any
program that runs under the UNIX operatmg
system and IS written m C, Fortran 77, or
Pascal can also be transported to run on
System 8000.
ZEUS IS more than an operating system. It
includes an extensIve set of programs that
comprise the system uhlities and development
tools of the ZEUS programming envIronment
(Figure 3). The system uhlities listed in Table 1
are commands that provide user access, command processing, hIe management
capab!lities, status information, and communication wIth other devices or systems. Certain system utilihes are used for mamtenance
and can be run only by a local system
admmistrator.
The development tools listed in Table 2 are
commands that provide control of runnmg programs, programmmg support, languages, text
processing, and text formattmg.
The ZEUS operatmg system occupies
approxImately 80K bytes of memory. This
memory is completely separate from the user
address space. User programs can have the
same maximum address space found in large,
l6-blt minicomputers: l28K bytes of memory,
consishng of 64K bytes of code and 64K bytes
of data. A future release of ZEUS will expand
the user address space up to 8M bytes.
The remainder of this section describes the
two most frequently used parts of ZEUS: the
hIe system and the command language.
The File System. The file system is probably
the most important feature of ZEUS. It supports
three types of files: ordinary files, directories,
and special files.
Ordinary Files. Ordinary files contain
whatever information the user stores in them.
No distmguished file types are provIded by the
system. A file of text SImply contains a string
of characters; lines are terminated by the
newline character. Binary programs are
sequences of words as they appear in memory.
Any programs that requIre a particular file
structure, such as a loader, must depend upon
cooperating programs to control the structure.

memory can handle 32-bit data transfers, and
the peripheral controllers work with 16- and
32-bit CPUs. In addition, ZEUS will continue
to be the operating system. This is possible
because the UNIX operating system, of which
ZEUS is an enhancement, has already been
transported to several 32-blt computers.

Ordinary files can be up to one billion bytes
long; there is no predetermined file size limit.

Directories. Directories structure the file
system by providing a mapping between names
of files and the files themselves. Each user
starts with a single directory for his or her own
files. The user can then create subdirectories
of files that can be conveniently treated
together. Directories are like ordinary files,
except they contain information about other
hIes. Anyone with access permission can read
a directory just like any other file.
The directory structure is that of a rooted
tree. A file name may be specified to the
system in the form of a path name; this is a
sequence of directory names separated by
slashes (I) and ending in a hIe name. FIle
names are sequences of no more than 14
characters. If a path name begins with a slash,
the search begins at the root directory. Thus,
the path name
Iproject/user/fn
tells the system to search the root directory for
project, then to search project for the directory user, and finally to find the file In in the
directory user. The file In may be an ordinary
file, a directory, or a special file.
When a path name does not start with a
slash, the user's current directory is searched.
Therefore, the command user/In specifies the
file named In in the subdirectory user of the
current directory. Inputting just In tells the
system to search for the file m the current
directory.
It is possible for a nondirectory file to
appear in several directories and even with
different names. This is called linking, and all
links to a file have equal status. This differs
from other systems because files exist independently of any directory entry, although a file
disappears when the last link to it is removed.

Special Files. Special files provide access to
physical deVICes as though they were ordmary
files. These files are, of course, protected from
indiscriminate access. There are three benefits
of treating 1/0 devices this way: file and
device 1/0 are as similar as possible; programs
expecting a file name as a parameter can be
passed a device name as well because file and
device names have the same syntax; and
special files can be protected by the same
mechanism as ordinary files.
579

Software
(Contmued)

Protection. The access control scheme of ZEUS
is simple and effective. Each user is assigned
an Identification number. When a file IS
created, It is marked with the identification
number of its creator or owner. Read, write,
and execute permission for the owner, for
members of the same group, and for all other
users can be set when the file is created or by
command at a later time.
In the standard UNIX operating system,
there is nothing to prevent two users from
simultaneously modifymg a file, resulting in
one user invalidating the other's changes. The
ZEUS operating system augments the three
standard UNIX file opening modes (Read,
Write, or both Read and Write) with a
mechanism for locking portions of a file. Both
Read-Only and Exclusive Use locks are
provided.

Command Language. Most users use the
command interpreter called the shell to communicate with the System 8000. The shell is
usually the first program run when a user logs
on. It is possible to specify other command
interpreters or, in fact, any program to be run
when a user logs on. Consequently, some
users could be in the editor as soon as they log
on, while programmers on the same system
would be in the shell.
The simplest form of command line is a command name followed by a list of arguments to
the command, all separated by spaces:
cmd arg 1 arg2 ... argn
Given this command line, the shell searches
for a file with the name cmd, where cmd may
be a full path name. If cmd is found and is
executable, it is loaded into memory and run.
The arguments entered on the command line
are accessible to the command. When the
command is finished, control is returned to the
shell, which prompts the user for the next command. If cmd is not a full path name, the shell
automatically starts searching for cmd using a
user-specified or default search path.
Standard I/O. Programs executed by the shell
start off with three open files. File 0 is initially
open for reading. Programs that need to read
from the user's terminal can read from this file;
it is the standard input device. File 1 is open
for writing and represents the standard output
file. This file is initially the user's terminal.
File 2 is the standard error file, also initially
assigned to the terminal.
The user can order the shell to change the
standard assignments of these files from the
terminal. If one of the arguments to a command is prefixed by ">", file descriptor 1 will
refer to the file named after the " >" for the
duration of the command. For example,

580

Is
ordinarily lists the names of the files in the
current directory on the terminal. The
command
Is > catalog
creates a file called catalog and puts the
listing there. On the input side,
mail fred
enters the mail program, which normally
accepts input from the terminal and in this
case sends it to the user fred. The command
mail fred < message
causes mail to take its input from the file
message instead of from the terminal.
The "<" and ">" symbols tell the shell to
redirect the I/O to the specified files. The command simply uses file descriptors 0 and 1
where appropriate and needs no special
coding to handle the redirection.
File descriptor 2 is for diagnostic messages
normally associated with the terminal output.
When an output redirection using ">" takes
place, file 2 is still attached to the terminal, so
commands produce diagnostic messages to
the user.
Pipes and Filters. The output of one command
can be directed to the input of another with an
extension of the standard I/O concept. When a
sequence of commands separated by vertical
bars W is entered, the shell executes all the
commands Simultaneously and connects the
standard output of each command to be
delivered to the standard input of the next
command in the sequence. Thus, the command
line
sort data5

I pr I 1pr

sorts the file called data5 in the current directory and passes the sorted output to pr, which
adds an identifying header line and page
breaks. Likewise, the output from pr is passed
to lpr, which prints the formatted listing on
the line printer. This procedure could have
been carried out much more clumsily by using
I/O redirection and two temporary files.
The vertical bar represents a "pipe" that
connects the output of one program to the
input of another. Programs that read standard
input, process the data, and write to standard
output are called filters. Many of the ZEUS
utilities can be used as filters to perform functions such as pattern searching, sorting, text
formatting, encryption, and decryption.

Command Separators and Multitasking. The
shell allows multiple commands to be entered
on a single command line simply by separating
them with a semicolon. A related feature

Software

(Continued)

allows the user to start multiple tasks from a
terminal. When a command is followed by an
ampersand (&), the shell does not walt for the
command to finish before promptmg again;
instead, it is ready to accept a new command
immediately. For example,
cc prog > out &
starts the C compiler compiling prog, with
compilation messages sent to out; the shell
returns to the user immediately, no matter how
long the compilmg process takes. The identification number of the process running a
command is printed when the shell does not
wait for the completion of a command. This
number can be used to termmate a command
or check for its completion. The "&" can be
used several times on a command line. Thus,
the command line
cc prog

> out & 1s > fnames &

both compiles prog and lists the files in the
current directory. Output files other than the
terminal were speCified above; had this not
been done, the output of the various commands would have been intermingled.

Command Files. The shell itself is a command
and can be called recursively. Suppose the
folloWing commands were entered at the
terminal:
Hardware

System 8000 is a modular, free-standing unit
bUllt for multi-station software development in
an office or laboratory environment. It can be
stacked up to SIX modules high. When the side
panels are removed from an individual
module, it can be mounted in a standard
19-mch rack.
The modular design of System 8000 makes it
easy to service. Each module is self-contained
and can be unstacked without the use of any
(l)
~

SYSTEM

~

Zilog

Processor Module:
Z8001A CPU
Eight serial ports

Pnnter Interface

oc:JI

1-

~

Winchester disk controller
Cartridge tape controller
256 KB of EGG memory

Perlpherel Module:
24 MB Winchester disk
Cartridge tape drive

SYSTEM

~

cc -0 testprog prog
testprog > testout
diff testout valid > result
This sequence of commands compiles prog,
giving the binary program the name testprog;
runs testprog, sending the output to the file
testout; executes diff, a file comparison program, to compare testout with the expected
valid output; and places any differences in the
file result. To do the program testing
automatically, the above commands can be
entered in a file. If the file were called validation, then the command
sh < validation
would cause the shell to execute a new copy of
itself, taking the input from validation. If
validation is made an executable file, it
becomes a new command and can be invoked
simply by entering its name in the command
line.
The shell has more advanced capabilities,
including the ability to substitute parameters
and to construct argument lists from a
specified subset of the file names in a directory. It also provides general conditional and
looping constructs. In fact, the shell is its own
programming language.

tools. To aid servicmg, all module mterconnect
cables are located on the outSIde rear panel of
each module.
The System 8000 is available in two basic
configurations, referred to as Model 20 and
Model 30 (see Figures 4 and 5). Both models
can be expanded to the same maximum configuration. The components of the systems are
housed in two types of modules, a processor
module and a peripheral module.

(j)
jg

SYSTEM

o !!!!..-

Zilog

[lJ

r'

!!!!..-

Processor Module:
Z6001A CPU
Eight serial ports
Printer Interface
Winchester disk controller
Cartridge tape controller
512 KB of EGG memory

Peripheral Module:
24 MB Winchester disk
Cartridge tape drive

SYSTEM

Double Storage
Compartment

~

Peripheral Module:
24 MB Winchester disk

Miscellaneous
storage space

Storage Compartment:
Miscellaneous
storage space

Figure 4. System 8000 Z-LAB Model 20
2143·003, 004

Figure 5. System 8000 Z-LAB Model 30

581

J

I

i
E

Hardware
(Continued)

582

Processor Module. The processor module
holds all of the printed CirCUIt boards of
System 8000, the card cage and backplane,
power supplies for the module itself, and the
key lock switch that enables the system reset
and start switches.
The card cage and backplane hold 10
printed circuit boards. The minimal System
8000 is made up of five boards: CPU, ECC
memory controller, one 256K byte memory
array, a Winchester disk controller, and a
cartridge tape controller. The ZBI bus allows
optional memory and controllers to be added
to the system simply by plugging them into
available slots. The ZBI provides increased
flexibihty by supporting 8-, 16-, and 32-bit
data transfers. This assures that future 32-bit
microprocessors can be used In the system.
The CPU board is based on Zilog's 6 MHz
Z8001A. It also includes three Z8010A MMUs,
which allow the hardware to support user programs of up to 8M bytes. Eight RS-232C serial
ports with modem control and programmable
baud rates are standard on the CPU board.
Each serial port contains the control logic
necessary for connection to a modem. The
baud rate on each sefla1 port can be set by
software to standard rates from 110 baud to
19,200 baud (default is 9,600 baud). Also standard is a printer interface that supports the
Centronics parallel interface; It can be
jumpered to support the Dataproducts interface. An 8K byte monitor in ROM holds the
power-up diagnostics and bootstrap. To allow
the use of lower-cost RAMs on the memory
array board and to eliminate walt states, the
system clock runs at 5.5 MHz.
The ECC memory controller provides singlebit error correction and double-bit error detection on a 32-bit basIs and logs correctable
errors. It controls the refresh needed for the
dynamic RAMs on up to 16 memory array
cards. It also performs 8-, 16-, and 32-bit data
transfers to the ZBI, which allows the memory
to be used With future 32-bit microprocessors.
The memory array card currently provides
256K bytes of dynamic RAM and holds the
extra memory necessary for the ECC bits. If
the remaining three slots in the backplane are
used for memory, a System 8000 can have up
to 1M byte of memory. Larger memory configurations are planned for future release.
The Winchester disk controller is an intelligent disk controller based on Zilog's 280B
microprocessor. It supports up to four 8-inch
Winchester disk drives and holds enough
memory to buffer one disk track. This provides
for high-performance, multisector reads and
writes. The controller transfers data to and
from the System 8000 memory under DMA
control, which minimizes CPU overhead and

increases the system's performance.
The cartridge tape controller is also a Z80Bbased intelhgent controller. It supports up to
four standard (not streamer) cartridge tape
drives. DMA data transfers are performed by
this controller, too.
The system can be upgraded to support a
total of 16 users. The upgrade includes an
external panel for the additional ports, cables,
and serial controller board. The board has
eight serial ports that are RS-232C compatible
and a printer interface, identical to those on
the CPU board.

Peripheral Module. The peripheral module
holds a Winchester disk drive, a cartridge tape
drive, and the necessary power supply. The
Winchester disk drive is a high-performance,
8-inch drive with an average access time of
48 ms. The peripheral module can house one
drive; more drives can be added by connecting more peripheral modules to the system.
The standard disk holds 24M bytes when unformatted and 22M bytes when formatted.
A cartridge tape drive can be housed in the
same peripheral module as a Winchester disk.
One standard cartridge tape drive (not
streamer) is provided with System 8000, allowing selective file backup and recovery. All
software for the system is provided on a cartridge tape. The standard cartridge holds 17M
bytes when unformatted and approximately
14M bytes when formatted.
System Diagnostics. To help verify system
integrity, two distinct diagnostic routines are
standard with System 8000.
Power-on diagnostics reside in the bootstrap
ROM and are initialized when the system is
powered on or the RESET and START buttons
are pushed. They provide a limited measure of
hardware integrity. The following tests are performed: 28000 instruction test, MMU test,
memory test, ECC controller test, Winchester
disk controller test, and cartridge tape controller test. If no errors are detected, the
system acknowledges that the test is over and
boots the operating system. If an error is
found, an explicit error message is displayed
on the console.
Stand-alone diagnostics are executed by the
diagnostics monitor and provide a thorough
testing of all standard and optional hardware.
The diagnostic monitor lets the user select
various options, construct a list of tests to be
executed with options, or execute a test
directly. Results and optional decisions are
handled via the console. The tests provided
are CPU test (which covers communications,
the MMU, on-board RAM and ROM, and interrupt handling), stand-alone memory test, Winchester disk test, and cartridge tape test.

-

Table 1.
System
Utilities

-- - - - - - - - - - -

User Access
login

Allows a user to sign on to the
system.
o Verifies password and
acknowledges user's individual
and group (project) identity
o Adapts to terminal characteristics
o Establishes working directory
o Announces presence of mail
(from mail)
o Publishes message of the day
o Executes user-specified profile
o Starts command interpreter or
other initial program

newgrp

Changes working group (project).
Verifies password to protect against
unauthorized changes to projects.

passwd
gpasswd

Sets or changes the password for a
user or a group. Passwords are kept
encrypted for security.

su

Substitu te user. Verifies password to
ensure that present user can temporarily operate under a different
user name.

Command Processing
csh

sh

Processes commands and command
line arguments. Provides all the
general capabilities of the shell sh,
as well as the following features:
o Has a C-like syntax for expressions and conditionals. This
feature gives the C shell
its name.
o Supports aliases for commands.
o Supports history substitutions
involving previous commands.
o Supports more sophisticated
argument processing involving
head or tail of a path name and
root or suffix of a file name.
o Can pass a shell script to the
shell sh for processing.
Processes commands and command
line arguments, and is the standard
seventh edition UNIX shell. Provides
the following features:
o Initiates tasks, either
waiting for completion or

o
o
o

o

o
o

letting them run asynchronously as directed
by the user.
Supports 1/0 redirection.
Connects processes with pipes.
Supports environment variables
for each user that specify the
home directory, prompt, mail
file, and search path for
executable commands.
Can read, interpret, and execute
a command file called a
shell script, substituting
arguments as directed.
For command sequencing contro!, recognizes "if. .. then ... " ,
case switches, while loops, for
loops over lists, break, and exit.
Supports execution of a shell
script at log-in.
Constructs argument lists from
file name patterns used as
arguments.

File Management
ar

Builds, adds to, or retrieves from an
archive (library).

comm

Identifies the common lines in two
files.

cat

Concatenates one or more files onto
standard output. Particularly useful
for simple printing. Works on any
file, regardless of content.

cp

Copies one file to another, or a set
of files to a directory. W or ks on any
file regardless of content.

dd

cd

Changes working directory. Built
mto the shells sh and csh.

Copies one file to another with control over other details such as the
block size for files on tape.

chkdiff
chkin
chkout
chkwhat

Zilog source control (ZSC) commands. Report differences in versions of a source file, check files in
or out, and report on file status.

diff

Reports the changes, additions, and
deletions necessary to make two files
identical.

dog

chmod

Changes read, write, or execute
permissions on one or more files.
Executable only by the file owner.

Displays a file so that the user can
examine the information one full
screen at a time.

find

cmp

Compares two files and reports
whether they are identical. Very
useful for comparing executable
binary files.

Searches the directory hierarchy for
every file that meets specified
criteria. Search criteria include:
o Name matches a given pattern
o Creahon date in a given range

583

fIJI

1
CD

II
00

C
C
C

N
•
t'I

•=-

Table 1.
System
Utilities
(Continued)

File Management (Continued)
fmd
D Date of last use in given range
(cont)
D Given permissions
D Given special file
characteristics
D A boolean combination of the
above
Can start searching from any directory. Performs a specified command
on each file found.

Makes a new directory.

more

DIsplays a file so that a user can
examine the information m full or
partial screenfuls, moving forward
or backward.

mv

Moves a file or files. Used for
renaming a single file or moving a
number of files to a different
directory.

pr

Prints files with date, page number,
and file name on every page. Can
produce column output and parallel
column merge of several files.
Removes a file. Only the name is
removed if any other names are
links to the file. Can delete entire
directory hierarchies interactively or
automatically.

head

DIsplays a specified number of lines
from the beginning of a file.

In

Links another name (establishes an
alias) to an existing file.

Ipr
Ipr2

Spools files to the line printer
or the second line printer.

rm

Is

Lists the names of one, several, or
all files in one or more directories.
Can display names in a single column, multiple columns, or commaseparated Itst. Names can be sorted
alphabetically, in ascending or
descending sequence, or by
modification date. Can dIsplay size,
owner, group, date last modified,
and permissions to read, write or
execute.

rmdir

Removes a directory.

tail

Retrieves a specified number of
lines from the end of a file.

tar

Creates a tape archive and retrieves
from it.

touch

Changes the modification date of a
file without changing the file.

pstat

Prints detailed status from internal
system tables.

pwd

Prints the name of the user's working directory.

setenv

Sets environment variables for the
shell. Changes terminal type for
screen editor vi. Built into the shell
csh.

stty

Reports or changes the terminal
characteristics.

tty

Prints the name of the user's
terminal.

who

Prints who is on the system, with
port assignments and time of log-in.

whoami

Prints the current user name.

Status Information
date
Prints current date and time.
daytime

Gives day and time display.

du

Prints a summary of the total space
occupied by all files in a directory
and all subdirectories.

file

Attempts to determine what kind of
information is in a file by looking at
the file system index and by reading
the file itself.

printenv

Prints shell environment variables,
such as the terminal type known to
vi.

ps

Reports on active processes for one
or all users. Tells what commands
are being executed.

Communication
cu
Provides dial-out capability to
another machine. Intended for use
with the VENTEL 212 + modem,
which can automatically originate
phone calls.
getfile

LOAD

584

mkdir

8000 emulator, or Z8000 target hardware. Uses the Tektronix hex communication protocol.
local

Provides upload of files from a local
MCZ-l, ZDS or System 8000 to a
remote System 8000.

Reverses the effect of remote by
returning the user to the local
system.

putfile

Provides download of Z8000 code
from System 8000 to Z8000 Development Module, Z-SCAN 8000 or EMS

Provides download of files from a
remote System 8000 to a local
MCZ-l, ZDS or System 8000.

remote

Establishes communication by direct
link to another System 8000.

Table 1.
System
Utilities
(Continued)

Communication (Continued)
SEND
Provides upload of 28000 code from
Z8000 DM, Z-SCAN 8000, EMS
8000, or target hardware to System
8000.
SYS
Enables code downloaded with
LOAD to access files on the System
8000.
System Maintenance
ac
Prmts a cumulative connect time
report by user or by day for all or
for selected users.
Imhates collection of system accounaccton
tlng mformation for SQ.
adduser Adds a new user name to the
system.
chown
Changes owner of one or more hies,
chgrp
group (proJect) to whICh files
chog
belong, both the owner and group,
chmog
or the access privIleges as well as
owner and group.
clri
Clears one or more i-nodes.
dcheck
Checks the integrity of the directory
structure.
Reports the amount of free space on
df
hie system devices.
down
Brmgs the system down smoothly,
after broadcastmg to all users at mtervals.
Dumps the file system on the
dump
speCified device either selecti'l'ely,
by date, or in total.
fsck
Performs hie system consistency
check and makes repairs, If
necesary.
icheck
Checks the integrity of the i-nodes
on the file system by reportmg
assIgnment of blocks either to files
or to the free list.
mkfs
Makes a new file system on a
device.

Table 2.
Development Tools

uucp
uux
uulog

Enables communication between
ZEUS and another ZEUS system, or
between ZEUS and another UNIX
system.

mknod

Makes a new hie system entry for a
speCial file that IS a deVICe.

mount

Attaches a deVIce contammg a hIe
system to the tree of dIrectOries.

ncheck

For icheck or dcheck problems,
dIsplays correspondence of i-node
numbers and file names.

quot

Prmts a summary of hie space usage
by user.

rc

Brmgs the system up automatically
after performmg a hie system consistency check and settmg the
date/time information.

restor

Restores a dumped file system, or
retrieves parts selectively.

rmuser

Removes a user name from the
system.

sa

Prints an accounting report of command usage, mcluding the number
of hmes each command was used,
total system time, total user time,
and elapsed real time, with optional
averages and percentages.

sync

WrItes out super blocks to preserve
file system changes.

sysgen

Defines a new system configuration.

umount

Removes a device containing a hie
system from the tree of dIrectOries.
Protects agamst removmg a busy
device.

wall

Writes a broadcast message to all
users.

Running Programs
at
Schedules a command to be run at
an arbitrary time.
basename Prints name after removal of
preceding path information.

kill

Terminates named processes.

nice

Runs a command at low (or high)
priority. BUIlt into the shell csh.

sleep

echo
ech02

Prmts remainder of the command
lme. Useful for prompts or
diagnostics in shell programs and in
make hies. Built mto the shell csh.

Suspends execution for a specihed
time.

tee

Passes data between processes and
diverts a copy into one or more
files.

expr

Performs integer arithmetic and
pattern-matchmg string computation
for calculating command arguments.

test

SupplJes returned status codes as
values for shell scripts.

gets

Gets string from the termmal. Used
in shell SCripts.

true
false

Supplies truth values for shell
scripts.

t•

•

I

I

..•~

585
---~------

-

Table 2.
Development
Tools
(Continued)

Running Programs (Continued)
upkeep
Maintains a record of dIrectory contents and can report modIficatIOns of
contents.
Programming Support
apropos Locates and prints descriphve inforgetNAME mahon from manual entries for
whahs
utihtles.

walt

Mall can be disposed of, saved in a
file, or forwarded.
make

Controls the creation of large programs. Uses a control file specifymg
source file dependencies to make
new versions; uses time last changed
to deduce mimmum amount of work
necessary. Has built-in knowledge of
file extensIOns for source, assembIer, and object files.

mesg

Inhibits receipt of messages from
other users.

nm

Prmts the symbol table of an object
or executable program. Provides
control over types of names and the
order of names that are printed.

prof

Constructs a profile of hme spent
per routine from stahstics gathered
by time-sampling the execution of a
new program.

prom

TransmIts executable code to a
PROM programmer. Intended for
use with the Data 1/0 Model 19 with
translation option.

sIze

Reports the memory requirements of
one or more executable files,
includmg code, data, and stack
sections.

str
strprmt

Collects software trouble reports and
produces listing sent to Zilog.

strip

Removes the relocation and symbol
table mformahon from an executable
hie to save storage space.

time

Runs a command and reports timmg
information on it. Built into the shell
csh.

write
talk

Creates a direct terminal connection
to another user, transmitting entire
lines or characters.

where is

Locates binary code and manual entry for a uhlity.

xget
xsend
enroll

Receives or sends secret mail or
estabhshes password for secret mail.

as

The Z8000 PLYASM assembler for
nonsegmented or segmented Z8000
code.

bc

A C-like interactive interface to the
desk calculator de. It includes
arrays and recursive functions.

calendar Automahc reminder servICe selects
events due same day and next day,
according to the user's calendar.
code

Prints characters and associated
hexadeCImal values.

error

DIsperses compiler error messages
through program hstmg.

hd
od

Dumps any file in hexadeCImal
or octal. Output options include
display in decimal or ASCII.

Id
sId

The Z8000 Imker for nonsegmented
or segmented code. It combines
relocatable object files and mserts
required routmes from speCified
libraries.

learn

Runs computer-aided instruction
(CAl) scripts so that users can learn
about ZEUS whIle using it.

(library The basic run-time library. These
routmes) routmes can be used freely by all
software. They include:
D Buffered, character-bycharacter I/O
D Formatted mput and output
conversion
D Storage allocahon
D Time conversions
D Number conversions
D Password encryption
D QUicksort
D Random number generator
D Mathematical function library,
mcludmg trigonometric
functions and inverses,
exponential, logarithm, square
root, and bessel functions.
man

mall

Prints a specified sechon of the
ZEUS reference manual at the
terminal.
Malls a message to one or more
user, or reads mail sent to the user.

Languages
Interactive Z8000 debugging tool.
adb
Provides breakpoint debugging with
the debugger as a separate process,
as well as supporting symbolic
reference to global variables, a
stack trace for C programs,
patchmg, and postmortem dumping.
586

Waits for termination of asynchronously running processes. Built
Into the shells sh and csh.

Table 2.
Development
Tools
(Contmued)

Languages (Continued)
cb
A beauhfier for C programs; it does
proper indentahon and placement of
braces.
cc
scc

Compiles programs written in the C
language. cc generates nonsegmented Z8000 code, and sec
generates segmented Z8000 code.
The ZEUS operatmg system and the
C compiler itself are written in C.
The major features of Care:
o General-purpose language
designed for structured
programming.
o Data types include character,
integer, float, and double,
pointers to all types, functions
returning those types, arrays of
all types, structures and unions
of all types.
o Operahons mtended to gIve
machine-mdependent control.
o Macro-preprocessor for
parameterized code and inclusion
of standard files.
o All procedures can be recursive,
with parameters passed by value.
o Machine-independent pointer
mampulation.
o Object code uses full addressmg
capability of the Z8000.
o Run-time library gives access to
all system facilities.
o Definable data types.
o Block-structured language.

ctags

Maintains tags file for use in editing
large C or Fortran programs.

cxref

Produces cross-reference lising of
routines in a C program.

dc

Interactive programmable desk
calculator. Has named storage locahons, stack for holding integers or
programs, unlimited precision
decimal arithmetic, and reverse
Polish operators.

f77

Compiles programs written in the
Fortran 77 language and produces
either nonsegmented or segmented
Z8000 code. (Fortran is an option on
System 8000.)

Text Processing
awk
A pattern scanning program and
processing language. Searches
input for patterns and performs
appropriate actions.
crypt

Encrypts and decrypts files for
security.

ed

Interactive, line-oriented context
editor providing random access to
all lines in a file. It lets the user:

lex

Generates lexical analyzers.
ArbItrary C funchons can be called
upon Isolation of each lexical token.
It supports full regular expreSSIOns,
plus left and right context
dependence. Resulting lexical
analyzers interface cleanly with
yoec parsers.

lint

Verifies C programs and reports any
machine-dependent constructs. It
does full cross-module checking of
separately compiled programs.

m4

A general-purpose macroprocessor
that is stream-oriented and
recognizes macros anywhere in the
text. Its syntax fits with the functional syntax of most higher-level
languages. It can evaluate integer
arithmehc expressions.

pascal

Compiles programs written in the
Pascal language and produces
nonsegmented Z8000 code. (Pascal
is an option on System 8000.)

plz

Compiles programs written in Zilog's
PLZ/SYS language and produces
nonsegmented or segmented Z8000
code.

rmcobol Generates an intermediate code and
runcobol then interpretively executes programs written in the COBOL
language. (COBOL is an option on
System 8000.)
yacc

An LR(l)-based compiler writing
system. During execution of
resulting parsers, arbitrary C functions can be called to do code
generation or semantic actions. Syntax specifications are m BNF and it
takes precedence relations. It
accepts formally ambiguous grammars with non-BNF resolution rules.

z8as

Assembles code for the Zilog Z8
microcomputer. (Z8 assembler is an
option on System 8000.)

z80as
z80cc

Assembles code for the Zilog Z80
microprocessor, or compiles C programs to produce Z80 code. (Both
are options on System 8000.)

o

o
o

Find lines by number or pattern.
Patterns may include specified
characters, don't care characters,
choices among characters,
repetitions of these constructs,
beginning of line and end of line.
Add, delete, change, copy, move
or join lines.
Permute or split contents of a line.
587

i

B

I
•t

Table 2.
Development
Tools
(Continued)

Text Processing (Contmued)
D Replace one or all instances of a
ed
(Cont)
pattern with a line.
D Combine or split files.
D Escape to the shell during
editing.
ex
edit

Line-oriented editors that are
supersets of ed and contain many of
the commands found in vi.

grep
egrep
fgrep

Prints all lines in a file that satisfy a
pattern, including line numbers if
requested.

look

Searches for words in a sorted file
that begin with a specified prefix.

sed

Stream-oriented version of ed. Performs a sequence of editing operations on an input stream of
unrestricted length.

sort

Sorts or merges ASCII files line by
line. Sorts alphabetically or by
numeric key. Multiple keys are
located by delimiters or by pOSition.
Sorts in ascending or descending
order.

spell
spellin
spell out

Looks for spelling errors by comparing each word in a document
against a 25,OOO-word dictionary
that includes proper names. It
handles common prefixes and suffixes. It also can collect words to

add to the systems' spelling
dictionary.
uniq

Collapses successive duplicate lines
of a file to a single line.

vi
view

Visual CRT-oriented text editor.
Works with almost any addressablecursor CRT terminal. Features of vi
include:
D Cursor movement on character,
word, line, sentence, paragraph,
section, or page basis.
D Cut and paste.
D Optional automatic indentation
for entry of programs in a block
structured language.
D Full-screen display of current text
in file.
D User-specified margin for
automatic return when typing
text.
D Escape to the shell while editing.
D A line-oriented mode compatible
with ed.
D A user modifiable data base of
CRT terminal control information.
D For important files, a read-only
version named view.

wc

Counts the lines, words, and
characters in a file.

Text Formatting
checkeq Checks vahdity of eqn constructs.
col

Arrange files WIth reverse line feeds
for one-pass printmg.

deroff

Removes all nro!!, fro!!' eqn, and fbI
commands from input.

eqn

A mathematical typesetting
preprocessor for frolf. Translates
formulas that are eaSIly read mto
detailed typesetting instructions.

expand

Expands tabs to spaces for printing.

(man
macros)

A standardized document layout
package that does formatting for entnes in the ZEUS Programmer's
Manual. For use with nrolf or frolf.

(ms
macros)

588

A standardized manuscript layout
package for use with nrolf and frolf.
It includes macros that do:
D Page numbers and draft dates.

D Automahcally numbered
subheads.
D Footnotes.
D Single- or double-column output.
D Paragraphing, display, and
indentation.
neqn

A version of eqn for nrolf; it accepts
the same input language.

nroff
trof!

Advanced text formatting. nrolf
drives ASCII terminals or printers of
all types, and frolf drives a Graphic
Systems phototypesetter or
equivalent.

tabs

Sets the tabs on a variety of terminals for prinhng.

tbl

A preprocessor for nrolf and frolf
that translates simple descriptions of
table layouts and contents into
detailed typesetting instructions.

System
Characteristics

Oil

;!I~J

02

Model 20/30 Physical - - - - - - - - Height
84 cm (33 m.)
Width
48 cm (19 m.)
Depth
61 cm (24 m.)
Weight (Model 20)
60 kg (132 pounds)
approximate
Weight (Model 30)
70 kg (154 pounds)
approximate
Model 20/30 Electrical--------Domestic
Voltage
117 ac± 10%
Phase
smgle
Frequency
60 Hz
Current (sustamed)
3.5 A maximum
Current (surge)
4.5 A maximum
International
Voltage
220 ac± 10%
Phase
smgle
Frequency
50 Hz
Current (sustamed)
1.9 A maximum
Current (surge)
2.5 A maximum

Model 20/30 Environmental------Operatmg Temperature
10° C
(50° F) min.
40° C
(104° F) max.
Relahve Humidity
80%
(Noncondensing)
Disk Performance - - - - - - - - - - - Rotahon Speed
3,600 RPM
Power ON to Ready
60 seconds
Time
Average Posihonmg
43 ms
Time
Number of Surfaces
3
Tracks per Surface
600
Sectors per Track
24
Bytes per Sector
512
Data Transfer Rate
801 K bytes/ s
Tape Drive Performance - - - - - - - - Speed Read/Write
30 ips (90 ips)
(rewmd/search)
Tracks
4
Recording DenSity
6400 BPI

589

EMS 8000
Emulator Subsystem

~
Zilog

Product
Brief

June 1982

Features

• Modular architecture can be easily
expanded to support emulation of future
Zilog microprocessors.
• A unique "snapshot" feature permits partitioning of a large real-time trace module
into many small trace memories.

mappable memory can be accessed by the
target system.
• A pulse output feature permits use of a
high-end logiC analyzer.
• Network debugging is supported.

• Three parallel trigger comparators are
provided.

• Full access is permitted to the target microprocessor's registers, memory and I/O
space.

• Logic-state analysis is provided for target
CPU address, data, status, control and
external probe bits.

• A "transparent" mode allows the same
terminal to be used for host and EMS user
interface.

• Up to 126K bytes of high-speed, static

Description

EMS 8000 is a high-end, emulation management system. The EMS 8000, together with
Zilog's UNIX * - based System 8000™ Z- LABTM ,
provides the developer of Z8000
microprocessor-based products with a complete set of tools for speeding up the product
development cycle.
The emulator provides the lmk between the
applicatIOn software developed on a host

system and the target system. It also aids in the
integration of the software into the target
system. Emulator to target system hookup is
simple and immediate. A CPU pod/cable
assembly directly replaces the target CPU. The
emulator preserves the full capability of the
target microprocessor. The emulator can start
or stop program execution or it can perform

591

Description
(Contmued)

smgle-step execuhon. IndIvIdual regISters or
memory can be exammed and modIfied upon
demand. Newly developed programs may be
loaded mto the development (target) hardware
and executed in a real-hme envIronment.

EMS 8000 Network. Up to 8 emulator systems
can be conhgured mto a network that permIts
emulahon of up to 8 dlstmct Z8000 mIcroprocessors to begin and end simultaneously.
ThIS type of emulatIOn capabIlity enables
message passmg m a communlcahons system
to be mOnitored from source to destmahon.
IndIvIdual emulator systems can be defmed
as bemg either m or out of a "break group."
Those systems out of a "break group" can
Hardware
Description

A fully conhgured EMS 8000 emulatIOn system (see FIgure I) contams the following Units:
• The EMS 8000 Unit Itself.
• A CPU Pod/Cable Assembly. The CPU Pod
contams the processor chIp to be emulated
plus required interface cIrcUItry. Pods are
available for the Z8001 and Z8002.

funchon as mdependent emulators wIth all the
capablhhes of EMS 8000 and the full use of the
host resources, whlle those m the break group
are debugging mulhple processor systems.

Mappable Memory. The emulator permIts the
user to access up to 126K bytes of mappable
memory. This memory may be subshtuted
anywhere m the target mICroprocessor's
memory space and can be mapped wIth 2K
byte resoluhon. Mapped memory can be
declared as unprotected, write-protected, data
memory only, or nonexIstent. Mappmg is also
provided for systems usmg separate code/datal
stack memory spaces for both System and Normal modes.
• The EMS 8000 reqUIres a host computer and
a user CRT termmal. All EMS 8000 software
is downloaded to the target system at the
begmnlng of the debuggmg sessIOn. Apphcation software developed on the host
computer can also be downloaded to the
target system vIa the EMS 8000.

EMS

8000

•

LOGIC ANALYZER

Figure I. Hardware Configuration

Software

The EMS 8000 mterfaces with Zilog computer
systems. ThIS capability allows the user access
to all of the powerful development tools and
cross-software of either the ZEUS or RIO
operating system. The EMS 8000 software provides a friendly, self-prompting interface for
the user.

Interface With UNIX-Based Host System.
When the System 8000 Z-LAB is the host computer, the EMS 8000 can make use of ZEUS,
*UNIX

592

IS

ZlIog's enhanced UNIX' operating system. ThIS
system provides a sophishcated hierarchIal file
structure, C, PLZ/SYS, a Z8000 assembler, a
compiler-writing system, and a general purpose macroprocessor.

EMS 8000 Monitor Software. EMS 8000
monitor software is downloaded from the host
during powerup; therefore, it can be easily
modIfied and upgraded to improve both its
effectiveness and its applicablhty.

a trademark of Bell LaboratOrIes.

00·2147·02

Z8000™ Emulator
Z-SCAN 8000

~

Zilog

Product
Description

June 1982

• Provides Real Time Emulation up
to 4 MHz 01 the Z8001 and Z8002
CPUs.
• Two RS-232C Serial Ports Make It
a Peripheral Usable with Most
Standard CRTs and Soltware
Hosts.

OVERVIEW
The Z-SCAN 8000 Emulator is an mClrcUlt emulator that has been designed
as a penpheral umt for Zilog's Z8001
and Z8002 16-blt mlCroprocessors.
InterfaCing vIa two RS-232C Senal
ports to host and CRT termmal,
Z-SCAN 8000 can work wIth Zllog's
famlly of development hosts.
Because 11 employs a standard senal
mterface, Z-SCAN 8000 can also be
used wIth VIrtually any software host
system that runs a cross assembler or
cross complier capable of generatmg
Z8000 code. Communicahon between
the host system and Z-SCAN 8000 IS
wIth a standard senal format requmng

• Transparent Operation Permits
Direct Communication Between
CRT and Host without Physical
Disconnect.

• Shadow Monitor Removes All
Restrictions on Target System
Memory Space. Making It Fully
Available To the User.

• Highly Interactive. ScreenOriented User Interlace Makes
Z-SCAN Easy To Use.

• High-Speed Mappable Memory
(no wait states) Is Available to
Simulate Target System
RAM/ROM.

only a SImple upload and download
uhhty to operate. For PROM-based
target systems, Z-SCAN can operate
stand-alone wIth a CRT termmal
because the mom tor and debug software is EPROM-resIdent.
In keepmg with Zllog's deSIgn
phIlosophy of separatmg a development system mto two ldenhhable umts
(the software host and an emulation
penpheral), Z-SCAN 8000 hts mto
three scenanos, makmg It a hIghly versahle umt:
• As a penpheral to Zllog's POS 8000
and ZOS-l Senes of development
systems, Z-SCAN 8000 completes

the development support package
for the Z8001 and Z8002 mIcroprocessors aVailable from Zilog.
• As a penpheral to any development
host wIth the capabllity of compIling
or assemblmg Z8000 code, Z-SCAN
8000 allows a low-cost emulahon
capabihty whlCh precludes substantial remvestment in a software host
system.
• As a stand-alone in-CIrcuit emulator
that can operate wIth most CRT
termmals, Z-SCAN 8000 provides
SImple testing and debugging
capabllity for PROM-based target
systems.

593

SYSTEM FEATURES
User Interface. Z-SCAN 8000 incorporates the use of a two-dimensional
screen-oriented user interface which
makes it easy to use. Because it is
general-purpose in nature, the user
interface does not require a customized
CRT terminal to operate. The only
requirements are that the CRT terminal
have screen erase, Ime erase, and cursor addressing capability.
The objective of the user interface is
to provide a screen format with a
menu-like approach, which directs the
user through the operation of the emulator. The user is aware at all times of
where he/she is in the debug process
because Z-SCAN 8000 provides the
CRT information about system parameters, system resources, current
execution, and error messages. When
the system is turned on, a bootstrap
routine produces a display informmg
the user of the unit's configuration and
requesting the user to define set-up
parameters. A menu of display choices
shows the user the different capabilities
of the system:
• The Memory/I/O command display
shows the various memory and I/O
manipulation commands which
access the target system.
• The Resources display presents the
user with the full complement of
arguments applicable to emulation
of the target system.
• The Execution display shows all the
commands and parameters necessary to cause emulation to take
place.
At all times, execution of specific
Monitor commands is possible, and
information on other relevant system
parameters and resources is always displayed. This highly interactive user
interface makes it possible to use
Z-SCAN 8000 without frequent
reference to the operating manual.

Shadow Memory. Z-SCAN 8000 is a
single, CPU-based system that can be
configured to emulate either the Z800 I
or Z8002 by simply exchanging the
CPU, monitor EPROM, and the
emulator cable.
Although the system uses a single
CPU for both monitor and emulation
functions, no restrictions are placed on
the target system memory size. This IS
because the entire monitor resides in
shadow memory and, therefore, does
not appear in the target system memory
space. This feature also provides the
benefit of makmg future system expansIOn possible without any hardware
redesign.

594

ADDRESS/DATA
BUS
COMPARE
VALUE

SEGMENT
BUS

ADDRESS/DATA
COMPARATORS

DON'T

COMPARE

SEGMENT
COMPARATORS

DON'T
CARE

CARE

STATUS
BUS

VALUE

INSTRUCTION
FETCH
DETECT

COUNTER

COMPARE
VALUE

STATUS
COMPARATORS

DON'T

CARE

MATCH

COUNTER

Figure 1. Hardware Trigger Implementation

Hardware Trigger. Z-SCAN 8000
offers the capability of setting breakpoints in three different fields or in a
combination of these fields. These are
the Address/Data Field, the Segment
Field, and the Control/Status Field. A
Pass Counter can be set up to a maximum of 255 counts to allow mulhple
pass triggermg. In addition, Z-SCAN
8000 may also be set to break on
instruction fetches only (single-step
execution), or, by using a Pass
Counter, may be set up to a maximum
of 247 counts to allow tnggermg on
multiple instruction fetches (multi-step
execution) .
With these two capabillhes, a breakpoint argument can be set up whICh IS
on ORed condition allowmg for either
a break-on-field (or combination of
fields) argument or for "n" instruction
fetches, whichever occurs lirst. ThiS
ORed situation is convenient when
traCing through a program in search of
a speCific occurrence. A pulse output,
providing a trigger pulse on breakpoint match condition is available on
the rear panel to trigger auxiliary test
instrumentation.
Mappable Memory. Z-SCAN 8000
offers a 4K work block of high-speed
static RAM. This block is available to
the user to simulate a target system

memory block which would typically
be ROM. No Wait states are required
at 4 MHz. This block is mappable
anywhere in the Z8001 and 28002
address space and can be speCified to
be Normal Code, Normal Data, Normal
Stack, System Code, System Data,
System Stack, or Space Independent.
Mapping must be done on 4K word
boundaries only, and the entire block
can be write protected against illegal
writes to cause system emulation either
to break on such occurrences or continue emulation. An error message
appears on the CRT display informing
the user of an illegal write.

Software Trace. Z-SCAN 8000 offers a
software trace feature which provides
insight into target system activity and
CPU resources. In the Trace Mode, the
system displays the address of the
instruction being executed and the
contents of the CPU registers (both
general-purpose and control) consecutively, covering one full screen
format.
For example, displaying the CPU
registers associated with every instruction executed just prior to executing a
Break is tremendously useful to the
user during debug of target system
activity.

1041-001

SPECIFICATIONS
CPU
Z800 I or Z8002 per conhguratIon
Clock Rate
500 kHz-4.0 MHz (external)
1/0
Two RS-232C Serial Ports for CRT and
host

Baud Rate
AutomatICally selected from 50 to 19.2K
Breakpoint
Address, Data, Segment and Address,
Control, Address and Control, Data and
Control, Segment and Address and
Control, Instruchon Fetch, OR combmatIon of Instruchon Fetch and any FIeld

Mappable Memory
4096 x 16 StatIc RAM (no Walt states at
4 MHz whIle operatmg off User clock)

Front Panel
Target/Monllor, Reset, and NMI toggle

Inputs
One standard LS-TTL load plus 30 pF

Power
110/220 Vac, 50/60 Hz sWItch selectable,
60 VA maxImum

sWItches

maXImum

Outputs
Capable of drlVlng one standard LS-TTL
load plus 30 pF preload

Dimensions
4 m. (10.2 cm) (H) x 14Y, m. (36.8 em)
(W) x 18 m. (45.7 cm) (D)

Rear Panel Output
BNC connector for pulse output, standard
LS-TTL

Emulator Cable
12 mches

argument

AC CHARACTERISTICS

Number
Symbol

zaOO1l2
Parameter

Mln(ns)

Max(ns)

Z-SCAN
Min(ns)
Max(ns)

I TcC
Clock Cycle TIme
250
2000
250
2000
2 TwCh
Clock Width (High)
105
2000
105
2000
3 TwCI
Clock Width (Low)
105
105
2000
2000
20
4 TIC
Clock Fall Time
20
5- TrC
Clock Rise T i m e - - - - - - - - - - - - - - - - - - - 20 - - - - - - - - 2 0 6 TdC(SNv)
Clock I to Segment Number Valid (50 pF load)
175
130
7 TdC(SNn)
Clock I to Segment Number Not Valid
20
35
8 TdC(Bz)
Clock I to Bus Float
165
65
9 TdC(A)
Clock I to Address Valid
163
100
10- TdC(Az)---Clock I to Address Float - - - - - - - - - - - - - - - - 65 - - - - - - - 1 5 4 II
TdA(Dl)
Address Valid to Data In Required Valid
455
383
12 TsDI(C)
Data In to Clock I Setup Time
50
76
13 TdDS(A)
DS I to Address Active
80
-4
14
TdC(DO)
Clock I to Data Out Valid
163
100
15-ThDI(DS)---Data In to DS r Hold T i m e - - - - - - - - - - 0
-20-----16 TdDO(DS)
Data Out Valid to DS r Delay
295
269
17 TdA(MR)
Address Valid to MREQ I Delay
29
55
18 TdC(MR)
Clock I to MREQ I Delay
143
80
19a TwMRh
MREQ Width (High)
193
210
19b-TwMRh
MREQ Width (High) During Monitor O p e r a t i o n - - - - - - - - - - - - - 1 8 4 - - - - - 20 TdMR(A)
MREQ I to Address Not Active
70
53
21
TdDO(DSW)
Data Out Valid to DS I (Write) Delay
59
55
22 TdMR(DI)
MREQ I to Data In Required Valid
287
350
23 TdC(MR)
Clock I MREQ r Delay
134
80
24-TdC(ASf)---Clock r to AS I D e l a y - - - - - - - - - - - - - - - - 80 - - - - - - - 1 3 4 25 TdA(AS)
Address Valid to AS r Delay
55
29
26 TdC(ASr)
Clock I to AS r Delay
144
90
27 TdAS(Dl)
AS I to Data In Required Valid
340
277
DS r to AS I Delay
28 TdDS(Ml)
70
53
29-TwAS
AS Width ( L o w ) - - - - - - - - - - - - - 70 - - - - - - - - - - - - 5 3 - - - - - - - 30 TdAS(A)
AS r to Address Not Active Delay
60
43
31
TdAz(DSR)
Address Float to DS (Read) I Delay
0
4
-41
- - - - - - - - - - - - - - - - - - - C O N T I N U E D ON NEXT P A G E - - - - - - - - - - - - - - - -- - -

595

AC CHARACTERISTICS
Number
Symbol

ZBOO1l2
Parameter

Min (ns)

32 TdAS(DSR)
AS t to DS (Read) I Delay
70
33 TdDSR(DI)
DS (Read) I to Data In Required Valid
185
34 TdC(DSr)
Clock I to- DS t Delay
35 TdDS(DO)
DS t to Data Out and STATUS Not Valid
75
36-TdA(DSR) - - Address Valid to DS (Read) I Delay
180
37 TdC(DSR)
Clock t to 155 (Read) I Delay
38 TwDSR
DS (Read) Width (Low)
275
39 TdC(DSW)
Clock I to DS (Write) I Delay
40 TwDSW
DS (Write) Width (Low)
185
41-TdDSI(DI)-- DS (Input) I to Data In F\equired Valid
320
42 TdC(DSf)
Clock I to DS (110) I Delay
43 TwDS
DS (110) Width (Low)
410
44 TdAS(DSA)
AS t to DS (Acknowledge) I Delay
1065
45 TdC(DSA)
Clock t to DS (Acknowledge) I Delay
46-TdDSA(DI)-- DS (Acknowledge) I to Data In Required Delay---435
47 TdC(S)
Clock t to Status Valid Delay
48 TdS(AS)
Status Valid to AS t Delay
60
49 TsR(C)
RESET to Clock t Setup Time
180
50 ThR(C)
RESET to Clock t Hold Time
0
51-TwNMI
NMI WIdth (Low)
100
52 TsNMI(C)
NMI~Clock t Setup TIme
140
53 TsVI(C)
VI, NVI to Clock t Setup Time
110
54 ThVI(C)
VI, NVI to Clock t Hold Time
0
55 TsSGT(C)
SEGT to Clock t Setup Time
70
56-ThSGT(C)-- SEGT to Clock t Hold Time
0
57 TsMI(C)
MI to Clock t Setup Time
180
MI to Clock t Hold Time
58 ThMI(C)
0
59 TdC(MO)
Clock t to MO Delay
60 TsSTP(C)
STOP to Clock I Setup Time
140
61-ThSTP(C)--STOPto Clock I Hold Time
0
62 TsWT(C)
WAIT to Clock I Setup Time
50
63 ThWT(C)
WAIT to Clock I Hold Time
10
64 TsBRQ(C)
BUSREQ to Clock t Setup Time
90
65 ThBRQ(C)
BUSREQ to Clock t Hold Time
10
66-TdC(BAKr)--Clock t to BUSACK t Delay
67 TdC(BAKf)
Clock t to BUSACK I Delay

Max (ns)

53
122
70

258
168
266
393
1048
381
162

110
45
208
15
116
154
118
22
78
22
188
22

165

120
148
22
78
25
98
32
100
100

Prerequisites

05-0100-00

Z-SCAN 8000/1 Emulator
(Supports Z8001 Emulahon and Control)

ZDS-l Series Development Systems

Z8000 SDP

PDS 8000 Series Development
Systems

Z8000 SDP

Z8002 FIeld Support KIt
(Converts Z-SCAN
800011 mto Z-SCAN

174

120

Systems recommended:

05-0102-00

174

120

Description

Z8001 FIeld Support KIt
(Converts Z-SCAN
800012 mto Z-SCAN
800011)

149

95

Description

05-0101-00

174

120

Part No.

Z-SCAN 8000/2 Emulator
(Supports Z8002 Emulahon and Control)

65
58
154

ORDERING INFORMATION

05-0100-01

Z-SCAN
Min(ns)
Max(ns)

145-145

8000/2)

05-0103-01

596

Z-SCAN 8000 Emulator
Includes Z8001 and
Z8002 CPU s, emulator
cables and serial mterface cables.

00-1041-02

Z8000™

Development Module

~
Zilog

Product
Description

June 1982

• Z8001lZ8002 CPU Evaluation and
Debug Support
• 16K Words Dynamic RAM
{Expandable to 32K for User Code
Execution and Debug
• 32 Programmable I/O Lines
• EPROM Monitor and Debugger
• Transparent Operation Allows
Software Development without
Disconnection from CRT and Hos!
System
• RS-232C Standard Serial Interfaces
Compatible with Most CRT Terminals and Development Hosts
• Wire-wrap Area for Prototyping

OVERVIEW
The 28000 Development Module IS a
complete, smgle-board mICrocomputer
that IS used as a tool for the evaluahon
and debug of 28000-based microprocessor systems. The Development
Module IS used m the first stages of the
deSIgn and development process, not
only as a tool for evaluatmg 28000
mIcroprocessor capab!llhes, but also as
an envIronment m whlCh code can be
executed and debugged.

Evaluation. The Development Module
prOVIdes a ready-made environment In

whlCh the user can execute software
umque to hIS 28000-based apphcahon,

evaluate the CPU's performance, and
then reach a reahshc declSlon about ItS
sUltablhty for a speCIfic apphcahon.

Software Debug. In addlhon to use as
an evaluahon tool, the 28000 Development Module can be used to debug
and modIfy user code. For the software
desIgner, the Development Module is a
real 28000 envIronment m whIch he
can execute code and carry out fairly
extensIve debuggmg. For the hardware
deSIgner, the Development Module IS
an example of 28000 hardware design
whlCh prOVIdes speCial hooks and wlrewrap fac!lihes to strap on addlhonal
logIC.

597

FUNCTIONAL DESCRIPTION

zaooo code developed on a software
host may be downloaded senally to the
Development Module RAM area via a
serial port, and executed and debugged under EPROM monitor controL
Once the system is connected, no further disconnection is necessary as the
module has two serial ports (one connected to a host and the other connected to a CRT terminal). A simple
software command makes the development process transparent in the serial
path, thereby allowing direct communication between the host and terminaL
The senal RS-232C mterfaces allow virtually any software development host
and CRT terminal to be used. For
PROM-based code testing, the development module is self-contained and
can operate stand-alone with a CRT
terminal, since the host is only
required for storage of user code
on disk.
A vanety of jumper areas and
switches permit the selection of clock
rates ranging from 2.5 to 3.9 MHz; the
use of 2708, 2716, or 2732 EPROMs;
the use of 4K or 16K RAMS; serial
interface to modem, terminal, or teletype; I/O port addressing; and baudrate selection from 110 to 19200 baud.

Hardware. The 28000 Development
Module is available in two versions:
one supports the segmented 28001
microprocessor; the other supports the
non-segmented 28002 microprocessor.
Z8001 Development Module. The
28001 Development Module consists of
a zaOOl CPU, 16K words of dynamic
RAM (expandable to 32K words). 4K
words of EPROM monitor (userexpandable to 8K words). a 280A SIO
providing dual serial ports, a zaOA
CTC peripheral chip providing four
counter/timer channels, two 280A PIO
devices providing 32 programmable
I/O Imes, and wire-wrap area for prototyping hardware.
Z8002 Development Module. The
28002 Development Module consists of
a 28002 CPU, 16K words of dynamic
RAM (expandable to 24K words). 2K
words of EPROM monitor (userexpandable to 8K words). a zaOA SIO
device providing dual serial ports, a
280A CTC peripheral device providing
four counter/timer channels, two zaOA
PIO devices providing 32 programmable I/O lines, and wire-wrap area
for prototyping.

598

COMMAND
INTERPRETER

DEBUGGER

Figure 1. Monitor Block Diagram

Software. The monitor software
(Figure 1) contained in EPROM (4K
words for the zaOOI and 2K words for
the 28002) provides debugging commands, I/O control and host interface.
It consists of a terminal handler, command interpreter, debugger and
upload/download handler.

ensures command validity and passes
to other software modules in the
monitor.

Terminal Handler. A Terminal Handler
prOVides interface to the console
deVice to facilitate output to a display
or printing mechanism and input from
a standard ASCII keyboard.

Upload/Download Handler. The
Upload/Download Handler provides an
interface between the serial connection
and the host computer, the command
interpreter and the memory resources
of the 28002 Development Module. It
formats and interprets asynchronous
data streams to and from the host and
provides error checking and recovery
for the serial interface (see Figure 2).

Debugger. The Debugger provides a
basic set of debug commands to allow
the user to start and stop program execution, display and alter CPU
registers, flags or memory, and trap
instruction sequences.

Memory Organization. Tables 1 and 2
show the memory maps for the two versions of the Development Module. The
organization of ROM and RAM in both
the segmented and nonsegmented
modes is indicated.

Command Interpreter. The Command
Interpreter scans console inputs,

/

ADDRESS

I I I

BYTE CHECK
COUNT

SUM

I

I

CHECK C
SUM
R

DATA

I I I I

I I I I

I

Figure 2. Serial Data Format

1047-001. 002

Segment I

Segment 0
Address (Hex)

Memory

Address (Hex)

0000

Momtor
EPROM

0000

OFFF
1000

3FFF
4000

BFFF
COOO
FFFF

User EPROM
(User Installed)
Standard
RAM
ExpanslOn RAM
(User Installed)

Memory

Address (Hex)

Memory

Momtor

lFFF

0000

EPROM

3FFF

ExpansIon RAM
(U ser Installed)

2000

User EPROM
(U ser Installed)

4000

Unused

3FFFF
4000

MomtorRAM
(Scratch pad Area)

49FF
4AOO
BFFF
COOO
FFFF

Table I. Z8002 Development Module Memory Map

FFFF

Standard RAM
ExpanslOn RAM
(U ser Installed)

Table 2. Z8001 Development Module Memory Map

MONITOR COMMAND SUMMARY
The following notation is used in the
command description:
< > Enclose descriptive names for the
quantities to be entered, and are
not actually entered as part of the
command.
[]
Denote optional entries in the command syntax.
Denotes "OR", ego WIB denotes that
eIther W or B may be used but not
simultaneously.
Prompt sign for the nonsegmented
zao02 monitor.
Prompt sign for the segmented
28001 monitor.
The following commands apply when
the 28001 monitor is used. All commands listed remain the same except
those that permit reference to segmented addresses as follows:
<


 =
[ < segment number>] < offset
address>
 =
"<" < hex number in
7-bit range>">"
BREAK < address>
[]

COMPARE



 

DISPLAY < address>
[LIWIB]

FILL < address I >

 

Sets and clears a breakpoint at a
given memory address. The option
 allows specification of the
number of occurrences, where n is
from I to 128. The default is one.
Compares two blocks of memory
data beginning with the addresses
specified for  bytes, where n
is from I to 128. Errors are
reported on the console device.
Displays and modifies memory for
 number of words or bytes.
The optlonal entry allows data to
be handled as bytes, words, or
long words. The default is words.
Stores the  from memory
address I to and including
address 2.

GO

Begins program execution at the
address contained in the current
PC; execution is resumed where it
was last interrupted. All registers
are restored prior to execution.

IOPORT < address>
[WIB]

Allows direct communicatlons from
the console to a selected I/O port.
A word (W) or a byte (B) may be
read from the selected port and a
word or byte may be sent to the
selected port; default is byte.
Unconditional branch to the specified address. All registers are
restored prior to execution.
Moves contents of a memory block
from source address < address I >
to destination address

 for  bytes.
Executes the next < n > machine
instructions.  may be from
I to 128. If n is omitted, I is
assumed.
Punches a copy of memory from
address I to address 2 on paper
tape on the console device. Automatically turns on punch and a
null leader is created.
Upload/Download section
describes the tape format used.
Places serial channels Into transparent mode. The zaooo Development Module must be connected to
both the Zilog host and the console
device, and the Development
Module acts as a message
switcher.

JUMP < address>

MOVE < address I >

 

NEXT[]

PUNCH < address I>



QUIT

REGISTER
[ < register name> ]

TAPE

Allows examination and modification of zaooo registers. 8-bit, 16-bit
or 32-bit quantities may be
selected by the appropriate
register-naming conventions.
Loads memory from pa,per tape via
the console device. The
Upload/Download section
describes the tape format used.

599

I

SPECIFICATIONS
Microprocessor

Input/Output

Z8001 or 28002 CPU
Clock Rate: 2.5 MHZ or 3.9 MHz

Memory
ROM: 2K or 4K Words (Expandable
to 8K Words)
RAM: 16K Words (Expandable
to 32K Words)

Parallel: 32 Lmes (Two Z80A-PIOs)
SerIal: Dual RS-232C or RS-232C and
Current Loop (Z80A-SIO)
Note
The user has access to all bus signals to allow
custom system expansion mto the wire-wrap area

off-board
Interrupts

Maskable Vectored (256), Maskable
Non-vectored, Non-maskable,
SegmentatlOn Trap

Power
+5 V, 3 A
+12 V, 1 A
-12 V, 0.2 A

Physical
HeIght
WIdth
Depth
WeIght

1.75 m. (4.5 em) InclusIve of
Standoffs
14.0 m. (35.6 em)
11.0 m. (27.9 em)
Approx. 30 oz. (850 gm)

ORDERING INFORMATION
Part No.

Description

05-6168-01
05-6101-01
05-6171-01

ZSOOI Development Module
Z8002 Development Module
Z8001 Conversion KIt (converts Z8002 Development Module into
Z8001 Development Module)

Systems recommended for use with the above:
Description

Prerequisite

ZDS-I Serles Development Systems

Z8000 Software Development Package

PDS 8000 Serles Development
Systems

Z8000 Software Development Package

600

OO-1047-A

Z8000™

Cross-Software
Package Version II

~
Zilog

Product
Brief

June 1982

Features

• Runs on the UNIX' Operatmg System. ThIs
enables mulh-user access for more efficient
software development and provides tools to
aId documentahon production.

Description

• ProvIdes C run-hme support envIronment
for the Z8000 Development Module. ThIs
keeps product development on schedule by
reducmg dependency on prototype
hardware .

• Includes C, a hIgh-level, machinemdependent, systems ImplementatIOn
language, that generates efficient Z8000
code. C improves programmer produchvlty,
shortens product hme-to-market, and protects software mvestment.

• C compiler produces Z8000 cross-assembler
source code. Assembly language hstmg of
C programs slmphhes debuggmg many
target envIronment.

In today's complex mICroprocessor-based
products, software development costs typICally
exceed those of hardware development. The
Z8000 Cross-Software Package, runnmg on the
UNIX operating system, reduces software
development costs by Improving programmer
productIvIty and enablmg software to be
developed before prototype hardware IS ready.
This allows hme for thorough product teshng
wh1le still meetmg development schedules. The

result IS a hIgher quahty product dehvered on
schedule.
The Z8000 Cross-Software Package (CSP) IS
a complete set of software tools for developmg
Z8000 programs. The package works on DIgItal
Equipment Corporahon's PDP-I 1144, 11145,
and 11170 systems wIth the Seventh Edlhon of
the UNIX operating system. Programmers and
related support personnel at a UNIX mstallation can eas1ly transfer theIr knowledge of the

." IIiU rill "~~, )if '"' '

"" /-------

CRgdl
~

~~/

~ WI I~~ =-.~-:~ ~=~: =:=~,~~
/

PDP11
UNIX,V7
Z8000 C$P

Z8000

OEVElOPMENO
MODULE

CRT I

~

\

Z8000

OEVELOPMENT
MODULE

g-J)I CeT
l__ _

=~~

Typical
lOon 00:; *UNIX

IS

a trademark of Bell Laboratones

zaooo Cross-Software Package Installation
601

Description
(Contmued)

UNIX environment to the 28000 development
project. The result IS that programmers
become productive.more qUickly. And, there
is a greater likelihood of the project flnlshmg
on schedule.
The C language, like other high-level,
machme-independent, systems Implementation
languages, Improves programmer productivity
and protects the software investment made m a
product by assurmg program transportability.
In addition, C produces 28000 code whICh IS
efficient both m terms of execution time and
memory space used. The result IS a lower cost,
higher performance product.
The development environment supported by
the 28000 CSP allows for multiple user software development on vanous 28000 target
systems (see figure below). The pass-through
mode of the 28000 Development Module
enables any termmal connected to the' host
system to be a hardware and software evaluation station. In this mode, the termmal and the
host system communicate directly as if the
28000 Development Module were not present.
Thus, each termmal on a host system can text
edit and compile programs and then download
them mto a development module for testing.
The pass-through mode of the development
module offers a more effective means of
debuggmg than software emulation because
programs can be debugged in real-time on actual hardware, without requmng any host
system resources. Zilog emulation products,
such as Z-SCAN 8000 and EMS 8000, Will continue to use the pass-through mode to communicate to the host system. Thus, a single host
system with 2ilog's development modules,
emulation products, and the 28000 CSP can
support total product development.

Product Description. The major pieces of software m the 28000 CSP are the C compiler, C
Ordering
Information

602

Prerequisites
• License for the Seventh Edition of the UNIX
operating system.
• One of the following computers from Digital
Equipment Corporation:
PDP 11144

optimizer, 28000 cross-assembler, 28000 crosslinker, upload/download program for the 28000
Development Module, and C run-time support
environment for the 28000 Development
Module.
The Z8000 C compiler IS the portable PDP-ll
C compiler from the Seventh Edition of the
UNIX system modified to generate 28000 code.
This means that eXisting PDP-II C programs
can be compiled by the Z8000 C compiler and,
If the programs are machine-mdependent, they
Will run on a 28000 target system. The C compiler generates both segmented and nonsegmented code.
The C optimizer speed optimizes the code
produced by the compiler and outputs 28000
cross-assembler source code. ThiS process
Yields an assembly language listing of the
optimized code.
The Z8000 cross-assembler accepts Zllog's
standard mnemonics and uses the pseudooperations familiar to UNIX assembly language
programmers. It supports programs with combined or separate code and data spaces. The
28000 cross-lmker links cross-assembler and C
program modules together.
The upload/download program transfers programs and data between the Z8000 target
system and the UNIX host usmg Tektronix hex
format. The C run-time support environment
provides the necessary faCilities to run
sophisticated C programs on the Z8000
Development Module. Because It includes
routines for terminal and UNIX file access,
Significant software development can take
place using C and the 28000 Development
Module.
The 28000 Cross-Software Package combines
with the UNIX operating system to prOVide a
complete development environment for 28000
software.
PDP 11145
PDP 11170
License Requirement
• A special license is reqUired for 28000
Cross-Software Package

00-1006-02

Z8000™ Software
Development Package

~
Zilog

Product
Description

June 1982
• Structured assembly language
with high-level constructs_
• Relocatable and absolute object
code format_
• Free format statements allow
indentation and spacing for
readability.
• External symbol references.
• Global symbol definitions.
OVERVIEW
The Z8000 Software Development
Package consists of fIve uhllty programs whICh aId and slmphfy the
development of Z8000 programs.
PLZlASM from Zllog's PLZ family bring
all the advantages of modular programmmg to the Z8000 software developer
and ensure transportabihty to future
processors. The Z8000 LINKER, IMAGER, LOAD/SEND and ZPROG
sImplify the testmg and produchon
stages of new software. Each program
facIlitates a single step towards completmg a segmented or nonsegmented
program; together they guarantee a
smooth, logICal, and manageable software development process.
ORDERING INFORMATION
Prerequisites:
PDS 8000 SerIes
ZDS 1140
MCZ-l SerIes
RIO
Part No.

Description

07-0085-01

28000 Software Develop·
ment Package
Ob)8ct CartrIdge DIsk
for Use WIth PDS
8000/20A

00 ]011 A

FEATURES
Assembler. The Z8000 PLZlASM
Assembler assembles easy-to-read,
free-format PLZlASM source programs
dIrectly to machme code. PLZlASM
allows an effICIent mIX of powerful
assembly language mnemomcs WIth
hIgh-level control structures, such as
IF . . . THEN . . . ELSE . . . FI and
DO ... OD loops. The PLZlASM programmer may map instructions and
informahon into the Z8000's program
and data memory space, and orgamze
the data space with such data declarahans as RECORDS and ARRAYS. The
PLZ/ASM Assembler supports both
segmented and nonsegmented pro·
grams and is fully supported by the
RIOIM operating system.
ZLINK. 2LINK lmks assembled modules

mto a smgle relocatable module and
resolves any external references among
separa tel y assembled modules. It can

also reorder and combme named sechons found m the mput assembly
language modules. ZLINK accepts a

symbohc speclfIcahon of the program
entry pomt m the command lme and,
on request, produces a detalled lmk
map whICh gIves the locahons of global
references and relocated modules and
sechons. Errors m the hnking process
are reported m the ophonal lmk map
and at the system console.
Imager. The IMAGER accepts mull!pie lmked obJect fIles from ZLINK and
translates them mto absolute code. IMAGER can then ellher store the absolute code m a dIsk hie or leave It m
system memory. IMAGER supports
segmented and non-segmentmg code.
Named sectlOns found m the mput obJect modules may be reordered and
loaded anywhere m system memory.
Program Transfer. LOAD/SEND
downloads an absolute program hie
mto the 28000 Development Module for
debuggmg, then sends It back to the
dIsk for back-up and storage.
Prom Programming. Z-PROG stores
the perfected load module m PROM.

Part No.

Description

Part No.

Description

07-3306-01

28000 Software Development Package
ObJect CartrIdge DIsk
for Use with PDS
8000/20

07-3309-01

28000 Software Development System
ObJect DIskette for Use
WIth PDS 8000/5

07-3310-01

07-3306-02

Z8000 Software Development Package
Ob)8ct DIskette for Hard
DIsk Systems WIth
Ophonal Floppy DrIves

28000 Software Development System
ObJect DIskette for Use
WIth ZDS-l SerIes

603

I

e

zaOOO™

PLZ/SYS

.~

Product
Brief

Zilog

June 1982

Features

• High-level procedure-oriented language
permits effiCIent writing of machineindependent modules and programs.
• Structured format for fast and easy-tocompile programs.
• Produces efficient code for economical
memory usage and processing time.

Description

Z8000 PLZ is a family of different programmmg languages designed to satisfy a wide
range of mICrocomputer software development
requirements. The two members of the PLZ
family, PLZ/SYS and PLZlASM, produce object
code~compatible modules and share common
control structures and data definition facilities.
Thus, selective portions of programs can be
written in the most appropriate language for
the specific application and still maintain a
consistent structure between modules.
PLZlSYS IS a high-level, procedure-Oriented
language that is syntactically Similar to Pascal.
It prOVides a medIUm for wrltmg structured,
machme-mdependent programs With a
mmlmum of programmmg effort.
PLZ/ ASM, on the other hand, IS a structured
assembly language that permits aCC3SS to the
low-level capabilities of the processor by mixmg assembly language and high-level control
structures.

Compiler. The Z8000 PLZlSYS Compiler
translates source code modules into an
intermediate stage called Z-code. The Z-code
modules can then be executed mterpretively or
processed by the code generator to produce a
machme-code object module.
The compiler provides support for both the
segmented and non-segmented Z8000 processors.
Code Generator. The Z8000 PLZCG Code
Generator accepts a hIe of mtermedlate Z-code
generated by PLZ/SYS and produces the cor-

• Simplihes software production and
maintenance.
• Allows direct or interpretive execution of
program modules.
• Supports both segmented and nonsegmented
Z8000 processors.

responding Z8000 machine code as a relocatable object module. This hIe can be linked
With other modules to form a complete
executable load module.

Interpreter. The intermediate Z-code modules
produced by the Z8000 PLZlSYS Compiler can
be executed interpretively by ZINTERP. Linking ZINTERP With the other modules generated
by the compiler produces an executable load
module.
Linker. The Lmker, ZLINK, links Z-code,
ZINTERP andlor machme code modules mto a
smgle relocatable load module, allowmg the
user to control the overall size and speed of
the program.
Although mterpretlve Z-code runs more
slowly than machme code, the space savmgs
over machme code IS usually substantial for
larger programs where the 3K bytes of
ZINTERP IS a small percentage of the entire
program. By balancmg the number of Z-code
and machme code modules, the user can maxImize the efhclency of a particular program.
ZLINK resolves any external references
between separately assembled modules, so that
the load module produced is relocatable. It
also allows the reordermg and combmmg of
named sectIOns between modules and supports
incrementallinkmg.
Operating Environment. Z8000 PLZlSYS is
supported on all Zilog development systems
that have at least 64K bytes of memory.

6ut;

ZRTS™8000
Zilog Real·Time Software
for the Z8000 Microprocessor

~
Zilog

Product
Description
Preliminary

June 1982
The ZRTS package consists of a
small real-hme; multi-taskmg executive
program, the Kernel, and a System
Configurator. The Kernel provides
sychronizahon and control of mulhple
events occurrmg in a real-time environment. All major real-time functions are available-task synchronization, mterrupt-driven priOrity scheduling, intertask communicatIon, real-time
response, and dynamiC memory allocation. The System Conhgurator is a
language processor that allows the
target operatmg system to be defmed
m high-level terms usmg the ZRTS
Conhguration Language (ZCL) .

• Easy-To-Use System Generator
• Real-time Multi-tasking Software
Components
• Synchronization of multiple tasks
• Interrupt-driven priority schedulmg
• Real-tIme response
• Dynamic memory allocatIon

• Modular and Flexible Design
• Efhcient memory utilization
• 4K byte PROMable kernel
• Support for 28001 and Z8002
16-bit microprocessors
• Configurable via linkable
modules

• Versatile Base for Z8000™ System
Designs
• Segmented/non-segmented tasks
• System/normal mode tasks
• Uses standard Zilog calling convenhons

• High-level configuration
language
• Supports a wide variety of hardware configurations
• EaSily changed control
parameters allow system
ophmization
• Eliminates the requirement for
inhmate knowledge of system internal structure

OVERVIEW
Zilog's Real Time Software (ZRTS)
prOVides of a set of modular software
components that allows qUick and easy
implementation of customized
operahng systems for all members of
the Z8000 16-blt mICroprocessor family.
In effect, ZRTS extends the instruction
set of the Z8000, adding easy-to-use
commands that give the Z8000 the
capability for managmg real-hme,
multI·taskmg applicahons.

These functions greatly Simplify the
tasks of the designer, allowing
development efforts to be concentrated
on the application, instead of on realhme coordination, task management
problems, and complicated system
generations. ZRTS provides a modular
and fleXible development tool that
serves as a versatile base for Z8000
system deSigns. The Kernel reqUires
only 4K bytes of either PROM or RAM
memory, thus allowmg conhgurations
for a wide vanety of target systems,
while producing a memory-efhcient,
cost-effectIve end product.

607

TABLE 1.

FUNCTIONAL DESCRIPTION

The Concepts. ZRTS IS both easy-tolearn and easy-to-use. Only a few simple concepts need to be understood
before designing begins.
Tasks. Tasks are the components comprising a real-hme application. Each
task is an independent program that
shares the processor with the other
tasks in the system. Tasks provide a
mechanism that allows a complicated
application to be subdivided into
several independent, understandable,
and manageable units.
Semaphores. Semaphores provide a
low overhead facility for allowing one
task to signal another. Semaphores can
be used for md,cating the availability
of a shared resource, hmmg pulses or
event notification.
Exchanges and Messages. Exchanges
and Messages provide the mechanism
for one task to send data to another. A
Message is a buffer of data, while an
Exchange serves as a mailbox at which
tasks can wait for Messages and to
whICh Messages are sent and held.
The ZRTS Kernel. The Kernel IS the
baSIC buildmg block of ZRTS and performs the management funchons for
tasks, semaphores, the real-hme clock,
memory and mterrupts. The Kernel
also provides for task-to-task commUnicahons via Exchanges and
Messages. All requests for Kernel
operahons are made via system call
instructions With parameters m
registers, according to the standard
Zilog callmg convenhons.
Task Management. One of the mam
activihes of the Kernel is to arbitrate
the compelition that results when
several tasks each want to use the processor. Each task has a unique task
descnptor that is managed by the
Kernel. The data contained m the
descnptor mclude the task name,
priority, state and other pertment
status informahon. ZRTS supports any
number of tasks, limited only by the
memory available to accommodate the
task descriptors and stacks.
The Kernel mamtains a queue of all
achve tasks on the system. Each task IS
scheduled for processor time based on
ItS priority. The highest-priority task
that's ready to run gams control of the
CPU; other tasks are queued. Tasks
can be prionhzed up to 32767 levels,
with round-robm scheduling among
tasks With the same prionty.
Tasks can run either segmented or
non-segmented code, in either normal
or system mode. The numerous operahons that may be performed on tasks
are listed m Table 1.

608

TASK MANAGEMENT
T_Census

PrOVides the status of tasks

In

the

system

T_Create

Creates a task dynamICally

T--.Destroy

Removes a dynamICally created task

L-Lock

Allows a task to take exclUSive control
of the CPU

T-Reschedule

Changes the pnorlty of a task

T-Resume

Aclivates a suspended task

T---.Suspend

Suspends another task.

T_Unlock

Releases exclUSive control of the CPU
for other tasks.
Suspends task execulion

SEMAPHORE MANAGEMENT
SeIlL-Clear

Clears semaphore queue and
remlhahzes a semaphore

SeIlL-Create

Creates a semaphore dynamIcally.

Sem--.Destroy

Removes a dynamlCally created

semaphore.

SeIlL-Slgnal

SIgnals a semaphore, Increments the
counter.

Tests a semaphore for a SIgnal.
Causes a task to walt unhl a semaphore
IS SIgnaled, decrements the counter

CLOCK MANAGEMENT
Clk--.Delay--.Absolute
Clk--.Delay--1nterval

Places a task on the clock queue

waltmg for ab~olute hme

Places a task on the clock queue
walhng for passage of an mterval of
time.

CILSet

Sets the real-lime clock

CILT,me

Reads the clock

MEMORY MANAGEMENT
MeI'IL-CenSllS

PrOVides status of the memory
resource.

Alloc

DynamIcally allocates memory.

Release

Releases allocated memory

INTER-TASK COMMUNICATION
M-AcqUlre

Gets a message from an exchange pool
and aSSIgns a destinatIon or a reply
exchange to It.

1L-Asslgn

ASSIgns a new source and destmatIon
to an eXistIng message.

1L-Create

Creates a message dynamICally

M-Destroy

Removes a dynamICally created
message

1L-Get--.Descnptor

Gets message's descnptor mformatIon

1L-Read

Reads the message data.

~ecelve

ReceIves a message from an exchange.

~ecelve_Walt

Walts to receIve a message from an
exchange.

1L-Release

Returns a message to the exchange

pool.
1L-Reply

Sends a message back to deshnatIon
exchange

1L-Send

Sends a message to an exchange.

1L-Wnte

Changes message data.

LCreate

DynamICally creates an exchange With
a pool of messages.

JL...Destroy

Removes a dynamically created
exchange.

Semaphore Management. The Kernel
provIdes semaphore management for
synchromzmg interacting tasks. A
tYPIcal use of semaphores IS to provIde
mutual exclusion of a shared resource.
When a resource IS to be used by only
one task at a time, a semaphore wIth a
counter of I controls the resource.
Every task reqUlrmg the resource must
first Walt on that semaphore. Since the
counter is I, only one task wlll acqUIre
the resource. The others will be
queued on the semaphore and
suspended until the semaphore is
sIgnaled that the resource is once
again available. At that time, the first
task on the semaphore queue wlll be
made ready to run and can use the
resource. After all tasks have acqUIred
the resource and signaled the complehan of theIr use, the semaphore returns
to its anginal state wIth a counter of I.
Counters greater than one are useful
when there are a number of similar
resources, (i.e., three tape dnves, four
I/O buffers, etc.).
In ZRTS, a semaphore can count up
to 32676 signals. The commands proVIded by the Kernel to manage
semaphores are hsted in Table 1.
Clock Management. ZRTS operates
wIth a real-time clock that generates
interrupts at a hardware-dependent
rate. It is used for timed walts,
hmeouts, and round-robm scheduling.
Allhmes are given m numb';r of ticks.
The clock may be mampulated by the
set of commands provIded by the
Kernel that are listed in Table 1.
Memory Management. Storage for
ZRTS data structures is allocated either
stahcally at system generahon time, or
dynamically at run time. Dynamic
allocahon occurs via a system call that
speCIfies the attnbutes of the structure
to be created and returns a name that
can be used to refer to the structure.
Memory IS allocated in 256-byte
mcrements, and can be released using
a system call.
The storage allocator can also be
called directly to obtain blocks of
memory up to 64K bytes long, whICh
can be used by the task for any purpose.
Interrupt Management. Interrupthandlmg routmes are prOVIded for
system calls, non-vectored interrupts
and a hardware clock. The user must
provide mterrupt rouhnes for whatever
other vectored mterrupts are mcluded
in the target system.
ZRTS can swllch control to a task
waltmg for an external event wlthm
500-microseconds after the occurrence
of the event. ThIS IS based on the worst
case WIth a 4MHz Z8000. A more typIcal response hme would be

TABLE 2.

CONSTANTS

Speclhes system constants.

EXCHANGES

Defmes the charactenshcs of apphcahan exchanges.

FILES

IndICates addllional hIes to be mcluded
m the conhgurahon lmk.

HARDWARE

Descnbes the target hardware conhgurahon-Z8001, Z8002, or Development Module.

INITIALIZATION

Specdles routmes that are to execute
pnor to beginnmg execuhon of the hrst
task.

INTERRUPT

AssocIa.tes an Interrupt routIne WIth an

mterrupt vector or trap and system
call-handlers. PrOVIdes the facllihes to
speCIfy a NVI mterrupt-handler that
WIll be called from the system NVIhandler rouhne.
MEMORY

Speclhes the memory conhgurahon
and Idenhhes where sections are to be
plac.ed (l.e.,CODE,DATA, ... ).

SECTIONS

Allows modules to be placed m a
specdIC sechon, overndmg the standard assIgnment convenhons.

SEMAPHORES

Dehnes the charactenshcs of apphcahan semaphores.

SWITCHES

Allows flags that control the system
generahon operahon to be set.

TASKS

Defmes the charactenshcs of apphcahon tasks.

250-microseconds. QUIcker service of
interrupts IS possible through the use
of user-written routines.

Messages can be obtamed qUICkly.
ZRTS prOVIdes several commands for
inter-task commumcations. These are
listed m TobIe 1.

Inter-task Communication. The
Kernel provides the capabIlity for tasks
to exchange mformahon. ThIS communlcatIon process occurs when one
task sends a Message to an Exchange
and another task receIves the Message.
A Message contams a length mdlcator, a buffer with a variable amount
of data, and a code that identihes the
Message type. The Exchange IS a
system data structure that consIsts of a
queue for Messages sent but not yet
receIved, a semaphore on whICh a task
can Walt for a Message, and an
ophonal "pool" hst from whICh

ZRTS Configuration Language (ZCL).
Smce ZRTS's modular deSIgn leads to
so many dIfferent conhgurahons, a
SImple faclhty for generatmg the target
operahng system IS a cnhcal part of
the ZRTS package. The ZRTS Conhgurahon Language (ZCL) provides an
easy-to-use means for generatmg the
target system. Usmg ZCL, the deSIgner
can speCIfy hardware mformahon, software parameters, lmkage mformahon,
and system data structures m hlghlevel terms.

(JULE
Z8000

USER
APPLICATION

DEVELOPMENT

Development Environment

609

ZCL unburdens the user of the
necessIty to learn the details of the
ZRTS internal structures. System data
structures can be generated simply by
spec!lying the approprlate parameters.
The ZCL syntax is free-format with
comments allowed to make the conhguration commands more readable
and mamtamable.
ZCL input IS comprlsed of a number
of descrlptive sechons, each contammg
the deta1ls of the target operating
system. The funchons of these sections
are described m Table 2. A sample
system generahon using ZCL is Illustrated m Figure 1.
Development Envjronment. Apphcahon modules for ZRTS can be
developed on any Zilog Z80 or
Z8000-based development system and
then down-loaded mto a Zllog Development Module or a customIzed target
system.
Subroutine hbrarles are provIded for
makmg ZRTS systems calls from programs Wrltten m PLZlSYS, PLZlASM
and C. Register usage m the system
calls is compatible with the Z1Iog
standard.
When using a Development Module,
the Debugger can be used with the
ZRTS modules for testmg purposes.
After the application IS debugged, the
system can be eas1ly reconhgured for
the final target hardware.

SWITCHES:
APPLICATloIN
HARDWARE;
Z8002
INTERRUPTS:
CONSTANTS:

MINIMUM_SYSTEM_STACK_SIZE

=

512,

FILES:
REAL_TIME _CLOCK:
MEMORY:

CODE =

[%8000 .. %8FFF] ;

DATA = [%900D •• %9FFF];
FREE_MEMORY = [%FQOO •• %FFFF];
SECTIONS:

INITIALIZATION:
TASKS:

prior ty
pc ioc ty
prlor ty

10]
20]

prior ty
[entry'" ALARM,
= ONE_SECOND_GENERATOR, prlor ty

20 ]
30]

input handler task '"
tim d"Isplay t'ask
=
egg-timer task

[entry = TIME DISPLAY,
[entry"" EGG TIMER,

alarm task
one second task

[entry

[E'ntry '" INPUT HANDLER,

20]

SEMAPHORES:
ONE SECOND SEMAPHORE;

TIME_DISPLAY_ENABLE_SEMAPHORE;
EXCHANGES:

INPUT_HANDLER_ ETE _EXCHANGE '"
EGG TIMER ENABLE EXCHANGE
INPUT_ HANDLER_ A_EXCHANGE

[number of messages

=

message sIze
=
[number of messages =
[number-of-messages =
message sIze
[number_af_messages '"
:0

ALARM_EXCHANGE

1,

8) i
0Ji
1,
8) i
OJ i

Figure I. ZeL Sample Input.

ORDERING INFORMATION
Description

Prerequisites

ZRTS/8001 Z1Iog Real Time Software for the Z8001
ZRTS/8002 Zilog Real TIme Software for the Z8002

Zllog Development System
MCZll, PDS, ZDS SerIes or System 8000 (Requires Software LICense)

610

00·)097-02

PDS 8000™
Development Systems

~
Zilog

Product
Brief

June 1982

Features

Description

• Supports entire family of Zilog
mICroprocessors-Z8, Z80, and Z8000 .

• Extends system capability with an intelligent
CRT console.

• Speeds program development with highlevel, structured assembler.

• Optional screen-oriented text editor.

System Hardware. The PDS 8000 Series consists of several models of single-user systems
for the design, development, and debugging of
Zilog microprocessor-based systems. The PDS
8000 is a Z80-based microcomputer system with
64K bytes of RAM, a disk controller, parallel
printer interface, and an intelligent CRT
console. Dual, floppy-dIsk drive with 600K
bytes of hard-sectored storage capacity is standard with the PDS 8000.
The floppy disk drive is interfaced to the
microcomputer via the Z80 Memory Disk Controller (MDC), which provides the Z80
microcomputer with all the data formatting
required for reading and writing onto the floppy disks from RAM storage. Disk read/write
accuracy IS ensured by 16-blt CRC-code circuitry. The MDC also provides 48K bytes of
dynamic RAM memory for programs or data
storage.

RIO Operating System. The PDS 8000 utilizes
Zllog's field-proven RIO Operating System for
the creation, editing, assembly, and debugging of software. RIO, with relocatable
modules and I/O management, is a generalpurpose computing system with architecture
designed to facilitate the development process.
RIO provides straIghtforward linking to vanous
system routines and enables expansion of
system features to meet the particular needs of
individual user. RIO is composed of the following elements whICh aid in the development
process:

System Software. The PDS 8000 System provides all the necessary software to handle
software development tasks, from inputting
source code to printing listings and creating
EPROM's.

I•

I

Operating System Executive. The RIO Execu-

tive maps requests of operations on logical
umts to specIfic devIce-handling programs.
Commands may be issued to the operating
system from the system console or by an
executmg program. Any number of userdefined commands may be added to the
system. Command sequences may be recorded
in files and executed as a group. The Executive manages the allocation of memory blocks.

611

Description
(Continued)

Relocating Macro Assembler. The Relocating
280 Macro Assembler offers relocatable or
absolute object code format with external symbol references and global symbol definitions,
macros and conditional assembly. The
Assembler pages the symbol table, permitting
assembly of arbitranly large programs in standard memory. It also includes a directive permitting additional files to be merged with the
source at assembly time.
Linker. The Linker assigns absolute addresses
to program modules, resolves external
references, permIts overlays, and produces a
load memory map with a global address table.
Text Editor. A line-oriented text editor pages
work space so that files of any size can be
edited and also provides automatic hie backup
and access to other disk files durmg editmg.
String matching allows for locatmg and modifying lines within a file. Also aVaIlable is an
optional multi-window, screen-oriented text
editor.
PROM Monitor. The PROM Monitor bootstrap
loads for easy system entry, supports a full
machine-language debug package, and
mcludes low-level devICe handlers for system
console and disk.
Processor-Oriented Support. To enhance the
development capability of the PDS 8000 Series

of systems, 2ilog also provides specific software packages and development tools to aid
the microprocessor system designer. To support the 28 MCU, an assembler and development module are available.

Z8000 Support. For 28000- based system
deSigns, the 28000 Software Development
Package (SDP) provides the necessary tools to
aid in software development. Utilizing PL2,
2ilog's high-level language, the 28000 SDP
includes a Cross Assembler, Linker, and
PROM programming utility.
For a tried and tested environment to run
28000 code, the 28000 Development Module IS
available. Providing support for either the
28001 or 28002, the Development Module is a
smgle-board computer With RAM, JlO and
monitor/debug firmware. The 28000
Development Module IS a convement tool to
evaluate 28000 CPU performance, as well as a
hrst-Ievel software debug tool for use early in
the design process.
For real-hme emulation of either the 28001
or 28002, the 2-SCAN 8000 Emulator is
avaIlable. Operable both stand-alone and with
a host system, 2-SCAN 8000 makes possible
software and hardware mtegration with realtime breakpoint, momtor/debug software, mappable memory, and an interachve user
interface.

,----1

: GiJ :
CRT
CONSOLE

I

FLOPPY DISK

I

L_S~R~E_~

Z80 MCB

B

OPTIONS:
•

SERIAL 110 EXPANSION

•

PARALLEL 110 EXPANSION

•

PROMIEPROM
PROGRAMMERS

Figure I. PDS 8000 Development System

612

IOJ.() 1101

ORDERING INFORMATION
Floppy Disk-Based
Description
Part No.
05-6102-01

06-6102-02

PDS 8000105 Development System (60 Hz). Includes 280 MICrocomputer, 64K bytes
dynamIc RAM, 3K
momtor, prmter mterface, edltmg-type vIdeo
termmal w/line-drawmg
capabIlIty, dual floppy
dIsk and RIO Operatmg
System. (l15 VAC)
PDS 8000105 Development System (50 Hz).
Same as 05-6102-01 except 230 VAC.

Floppy Disk-Based (ContInued)

Floppy Disk-Based (ContInued)

Part No.
05-6102-04

Part No.
05-6104-01

05-6102-03

Description
PDS 8000105-1 Development System (60 Hz). Includes 280 MIcrocomputer, 64K bytes
dynamIc RAM, 3K
momtor, prmter mterface, senal mterface,
dual floppy dIsk and
RIO Operatmg System.
(l15 VAC)
PDS 8000105-1 Development System (50 Hz).
Same as 05-6102-04 except 230 VAC.

05-6104-02

07-3001-01

Description
PDS 8000/15 Development System (60 Hz). Includes 280 MICrocomputer, 64K bytes
dynamIC RAM, 3K
momtor, prmter mterface, edItIng-type VIdeo
ternmal w/lme-drawmg
capabIlIty, dual floppy
dIsk, 28000 Development
Module, 28000 SDP Software Development
Package, and RIO
Operatmg System.
(l15 VAC)
PDS 8000/15 Development System (50 Hz).
Same as 05-6104-01 except 230 VAC.
PDS 8000/RIO

613

ZDS· 1140
Develop.ent System

~

Zilog

Product
Description

June 1982

• Full Development Support for the
Z80@ and Z80A Microprocessors
• 64K Bytes of Memory to Support
Large Programs

• In-Circuit Emulation up to 4 MHz

• 600K Bytes Floppy Disk Storage

• Memory Mapping Allows Borrowing of System Memory Before Prototype Memory Is Built

• ZAP Package Provides Interactive.
Symbolic Debugging With
Disassembly

OVERVIEW
The ZDS-l/40 Development System
provides total development support for
zao and ZaOA CPU-based system
designs. This support begins with a
complete zaO-based mICrocomputer
system that includes 64K bytes of RAM.
dual single· sIded, single densIty floppy
disk drIves and system software to

assist in every phase of software
development.
Included with the powerful
microcomputer is an in-circUlt emulahon subsystem whICh connects to the
user's prototype to momtor the execution of the software, control the
behavlOr of the microprocessor m the

prototype, and mimmize the problems
encountered in integrating software
with hardware. Interachve debug software-the ZAP package, provided with
the emulahon system-allows debuggmg of the prototype, full disassembly
of memory data and trace informahon,
the use of symbohc references, and the
capability of placing all debug commands on disk for execution.

Software Development. The software
development host is a zaO-based
general-purpose mIcrocomputer with
3K bytes of EPROM, 64K bytes of

dynamic RAM, a floppy disk controller,
serial RS-232C console interface, and
two Single-sIded, single density floppy
disk drives.

FUNCTIONAL DESCRIPTION
The ZDS-1/40 Development System m
effect consists of two functional parts: a
software development host and an incircuit emulation subsystem.

615

Included with the microcomputer
system is Zilog's RIOTM Operating
System and System Utilities. This set of
tools provides the user with the full
capability of carrying out the various
development tasks from the inputting
and assembly of source code to the
printing of listings and the creation of
EPROMs. The RIO operating system is
designed to provide the user with the
capability of tailoring commands and
mitialization routines to suit the needs
of the specific application. The main
features of RIO include a PROM-based
monitor, OS executive, ZDOS II file
manager, text editor, 280 relocating
macro assembler and linker.

PROM-Based Monitor. 3K bytes of
nonvolatile storage provide system
primitives for communication with
floppy disk and console devices, and
contain the bootstrap rouhne for the
system.
OS Executive. The executive is the
focus of system activity and thus
handles VO requests, dynamically
allocates system storage areas to active
programs on an "as needed" basis and
invokes programs in response to
operator commands.
ZDOS II File Manager. The file
manager organizes, stores and
retrieves data from the floppy disk
units. A directory provides an index for
the data, which is accessed using a
"hierarchical linked list." All space on
the disk is dynamlCally allocated on an
"as needed" basis to prevent gaps in
the storage space. Logical record
lengths from 128 to 4096 bytes per
record may be used. Also, all hIes may
be assigned one or more attributes for
protection and privacy.
Text Editor. A line-oriented text editor
can handle files or programs larger
than the available memory space. All
operations withm a file are based on
character string matching to allow
quick and easy search and modificahon
of text. The capability to access other
files during an edit session saves the
repetitive entry of commonly used
routines and enables the user to build
libraries of commonly used code. Automatic backup of an existing file
prevents accidental destruction of
valuable data.
Z80 Relocating Macro Assembler. The
relocating macro assembler provIdes a
quick way to create 280 code in a
modular fashion. Its deSIgn supports
absolute or relocatable object code formats, global definihons, external
references, macros and condihonal
assembly. Ophonally, a cross-reference
andlor symbol table is hmlted only by

616

available storage on the disk. All
dIagnostic messages are routed to the
system console with perhnent line
number, error and the statement itself
so that there is no waihng for a listing
to locate erroneous statements.

Z80 Lmker. The Z80 Linker provides a
means to lmk various program modules
together and resolve communiqation
between global modules, described by
external references. The result is the
generation of a smgle, executable program with absolute addresses. The use
of the linker allows indIvIdual modules
to be bUIlt and debugged, then merged
WIth others without performing a complete assembly.
System UtIlities. All of the software
used to drive or control the various
accessory boards available IS mcluded
with the system. There is no need to
write software to commumcate with
prmters or PROM programmers
because it is already completed. The
source code for the utilities IS included
so that the user can supplement or
custom-tailor the software.
In-Circuit Emulation. The in-Circuit
emulation subsystem enables the software developed on the microcomputer
to be debugged before the hardware
prototype is completed and even while
the prototype is nonexistent. Resourcelending capabilities enable the software
to be tested in the prototype hardware
before it is completed. After the hardware is complete, the emulation subsystem allows total integration and
testmg to occur in a real-time environment. The subsystem consIsts of a trigger or breakpomt module, a monitor
module, a user pod controller, a user
pod, and a Z80A emulator CPU.
Hardware trIgger capability enables
searching for a specific condition while
the software is executmg in real hme,
and executing breaks when detected.
The detection can also be used to generate a sync pulse to trigger other
instruments, such as OSCIlloscopes or

logic analyzers used m the debug
process.

Monitoring Functions. The emulation
subsystem provides a means of
monitoring the interaction of the
microprocessor with the target design.
A special high-speed trace memory
records the microprocessor's bus achvity, while running the software in real
time. The contents of the memory may
then be dumped on the console after
emulation has been halted for subsequent debug. The output of the trace
memory can be displayed in three
available formats. The user may qualify
the mputs to the trace memory to select
the specific type of bus cycle to be
recorded, such as a memory write or
an VO operahon.

Resource Sharing Functions. The
ZDS-1/40 system allows the user to borrow memory resources so that testing
can begin even before the hardware is
complete.
The system provides a memory mapping mechanism, whereby the user can
describe the addressable memory
space of the microprocessor. This
memory space is divided into blocks,
each containing 1024 bytes of contiguous memory addresses. These
blocks may be described to exist in the
user's prototype, in the development
system memory, or not to exist at all.
All commands executed to examine or
modify memory are quahhed by the
mapping mechanism.
The mapping mechanism also allows
hardware write protection of any block.
Any attempted write to a writeprotected block will be reported as a
write violation and will terminate program execution without causmg overwrites to the block. The nonexistent
memory feature enables the user to
declare blocks of memory nonexIstent.
Any attempt to access these blocks will
immediately terminate program execution with a nonexi'stent memory vlOlahon message.
Emulahon occurs by removing the
Z80 or Z80A microprocessor from the
prototype and replacing it with the
280A Emulator CPU of the development system. ThIS emulator is connected to and controlled by the emulation subsystem. Monitoring and
resource lending capabIlities provided
by the emulation subsystem also
simplify the development process.
Emulation Functions. The emulahon
subsystem provides several functions
extremely useful to software and hardware designers: I) control of the microprocessor in the hardware prototype; 2)
the ability to monitor the bus signals of
the microprocessor and record them;
and 3) the ability to lend development
system resources to the user's hardware
prototype.
Control Function. The cable connection between the user's prototype and
the development system allows start!
stop control of the 280A CPU Emulator.
This feature enables the user to execute
the software in a normal run mode,
single-step the software, or execute
multiple instruchons. When the
emulator is idling or not running the
user's software, 11 generates the
necessary refresh timing sIgnals to
keep dynamic memory in the prototype
ahve. Control of the microprocessor
also allows the user to examine or
modify CPU regIsters, memory or I/O
deVices.

------------ -

----------

--~~~~-

SPECIFICATIONS
SWHOST
CPU

zao CPU and zaOA Emulator CPU

Memory

64K bytes (3K EPROM, lK stabc RAM,
60K dynamic RAM)
WordSi.e
8 bits (I byte)
Clock Rate

IN-CIRCUIT EMULATOR

POWER

Clock Rate
Trigger
Real-bme trace
module
Emulahon cable
(mcludmg pod)

System

4 MHz
Break on address
256 x 36 bits Wide,
high-speed stahc RAM
6 ft.

(1.82 m)

PHYSICAL

System

2.5 MHz crystal-controlled
InterruptI
Three modes Includmg vectored,

nonvectored and nonmaskable
Option Card Slota

Five (5)

Height

Width

Depth

Weight

10.0 m.
19.0 m.
16.0m. 35.01bs.
(25.4 cm) (48.3 cm) (40.6 cm) (15.9 kg)
D,sk Umt
Height

Width

Depth

Weight

10.0 m.
35.01bs.
19.0 m.
16.0 m.
(25.4 cm) (48.3 cm) (40.6 cm) (15.9 kg)

Frequency

Voltage

Current

50 Hz
50 Hz
60 Hz
D'Sk Umt

110 Vac
220 Vac
110 Vac

1.5 A
0.7 A
1.5 A

Frequency

Voltage

Current

50 Hz
50 Hz
60Hz

110 Vac
220 Vac
Ii0Vac

1.5 A
0.7 A
1.5 A

ENVIRONMENTAL
Operating
Storage
Temperature
Temperature

0° to 40°C

0° to 85°C

Relati..e
Humidity

20 to 80%
noncondensmg

Floppy Disk Storage

CapaClty
Type

300,000 bytes/dnve
Smgle-slded, smgle
density, hard-sectored
MaXimum Capacity
600,000 bytes
(dual dnves)
Transfer Rate
260K bls
Average Latency
83 ms
Track-to-Track Seek 10 ms
Average Access Time 250 ms
PhyslCal Sectors
32 sectors/track,
77 tracks

....

i

ORDERING INFORMATION
Part No.

Description

05-6013-05
07-3002-01

ZDS-1I40 Development System (60 Hz)
ZDS-1I40 RIO Developw.ent System (50 Hz)

Z1LOG ANALY"ZER PACKAGE (ZAP)
EMULATION SOFTWARE
Product Overview. The Z,log Analyzer
Program IS a sophisticated software
module used to operate the emulation
hardware of the ZDS-l/40 Development
System. ZAP prOVides full control over
the emulation hardware for qUick and
easy debugging of Z80- and zaOAbased deSigns. This module allows the
user to mspect the microprocessor and
to interact With the prototype system.
The registers, user or system memory,
and I/O ports may be mterrogated and
controlled. Control of program execution, interrupt, and Direct Memory
Access (DMA) achvlty is also prOVided.
These features, combmed With full symbolic debugging and disaaembly capability, prOVide powerful debugging
tools for the zao mICroprocessor.

Functional Description. The Zilog
Analyzer Program is a disk-resident
program used to control the zaO/zaOA
emulation hardware of the ZDS-l/40
Development System. It prOVides an
interface between a command source
and the emulahon hardware. Commands may therefore be supplied from
the disk file system (command hie),
system console deVICe or a control program. This provides flexibility m hardware debugging as well as teshng
applications.
ZAP prOVides a complete spectrum of
commands and data formats to enable
prototype hardware and software to be
qUickly mtegrated and debugged. A
simple command syntax, using abbreviated command words, provides Visibility into the zao's registers, user
memory, system memory, user 1/0
ports, and CPU status. Microprocessor
registers may be displayed and altered
mdlvldually, or the complete register
set may be displayed. Commands for
accessing user or system memory
include FILL, SET, DISPLAY, and
ALTER. A block compare command IS
also prOVided for companson of a
given strmg with memory. All memory
data may be disassembled to reflect the
actual source code mnemonics and
symbolic references If the symbol table
for the code IS available.

Emulator Start/Stop ControJ. The use
of ZAP and the ZDS-l/40 emulation
hardware allows the user to control the
start up and shut down of the zaOA
Emulator CPU. Emulation is mitiated
by the GO command and continues
until one of the follOWing condlhons
occurs:
• One of eight different software
breakpoints IS encountered
• Hardware breakpoint compare
• Operator mtervention (manual
break)
• Bad clock detection (m target
system)
• Non-existent memory access
• Write-protect violahon

617

The user may select single step or
multi-step execution of the program
under test. This enables the registers to
be exammed after each step operation.
In multi-step mode a group of instructions may be executed m real time.
Any group of up to 255 mstructlons
may be multi-stepped before stoppmg
the emulator.
Memory Mapping. The memory mappmg capabihtles of the ZDS-1I40
Development System are easily manipulated by ZAP. Blocks of memory, each
contaming 1024 contiguous bytes, may
be assigned to eXist m the user's
system, in the development system at
the normal address, m the development
system with a translated address, or not
to eXist at all. In addition, these blocks
of memory may be hardware wrlteprotected to assist m the debuggmg
task and prevent accidental destruction
of data.

D,sassembly Capab,ilty. User memory,
system memory, and the trace memory
of the development system may be displayed m the hexadeCimal or disassembled format. In disassembled format,

618

the instructions are displayed in both
hexadecimal machine code and assembly language mnemomcs.

Symbolic Debuggmg Capablilty. Symbol tables for each program module
may be loaded mdivldually, or the
entire symbol table for the program
may be loaded. The user may dehne
local symbols to assist in the debugging process.
Symbols are loaded mto development system memory and are automatically hardware write-protected to
prevent aCCidental destruction. A maxImum of 29K bytes of system memory
may be used for the symbol table: thiS
equals approximately 3000 symbols.
Since development system memory
may be shared with the user's prototype system, the maximum symbol
table size IS a function of the number of
blocks allocated for use m the user's
prototype hardware.
The use of symbols m place of
numeric values in the ZAP command
syntax, teamed with disassembly,
enables the user to have an electromc
hsting of the program under test. ThiS
allows the user to concentrate on the
debugging task mstead of havmg to
struggle with the development system
software.
Command Flle Capability. The Zilog
Analyzer Program IS structured to
accept command mput from several
sources: console, hie, or program. This
capability is important m the debugging process, the traimng process, and
even the manufacturing test process.
In the debuggmg process, commonly
used commands for estabhshmg the
memory map, enablmg mterrupts, and

loading program modules may be
placed m a disk file and executed. This
allows a series of necessary operations
to be performed with a mlmmum
number of keystrokes. It also msures
that the system will be initialized the
same way, no matter how many mdivIduals are using the system.
The same techmque may be used for
trammg new users of the ZAP command structures. TutOrial hies can be
created to execute the various system
commands and Illustrate the results. An
example of this is ZAP TUTOR, a software trammg package mcluded with
ZAP to acquaint the user with the commands and their use.
In a manufacturmg test operation,
the user may create software whICh formats command parameters for ZAP and
pass these usmg a CALL to ZAP. The
ZAP software Will perform the
requested operation and return the
results to the callmg program. ThiS
enables the user to diagnose deSigns
usmg the emulation hardware controlled by apphcatlons software.

OO-1040-A

Z80®pLZ

~
Zilog

Product
Description

June 1982

• High-Level Procedure-Oriented
Language Permits Efficient
Writing of Machine-Independent
Modules and Programs.
• Structured Format for Fast and
Easy-to-Compile Programs.
• Produces Efficient Code for
Economical Memory Usage and
Processing Time.
• Simplifies Software Production
and Maintenance.
• Allows Direct or Interpretive
Execution of Program Modules.

FEATURES
Compiler. The Z80 PLZlSYS Compiler
translates source code modules into an
intermediate stage called Z-code. The
Z-code modules may then be executed
Interpretively or processed by the code
generator to produce a machine-code
object module.
Code Generator. The Z80 PLZCG
Code Generator accepts a hIe of intermediate Z-code generated by PLZlSYS
and produces the corresponding Z80
machine code as a relocatable object
module. This file may be linked with
other modules to form the complete executable load module.
Interpreter. The Intermediate Z-code
modules produced by the Z80 PLZlSYS

OVERVIEW
Z80 PLZ is a family of different programming languages designed to
sahsfy a wide range of mICrocomputer
software development reqUlrements.
The two members of the PLZ fam!ly,
PLZlSYS and PLZlASM, produce object
code-compatible modules and share
common control structures and data
definition facilities. Thus, selective portions of programs may be written in the
most appropriate language for the
specific application and still maintain a
consistent structure between modules.

PLZlSYS is a hIgh-level, procedureoriented language that is syntactically
SImIlar to PASCAL. It provides a
medium for wnting structured,
machine-independent programs with a
minImum of programming effort.
PLZIASM, on the other hand, is a
structured assembly language that permits access to the low-level capabilities
of the processor by mixing assembly
language and high-level control
structures.

Compiler can be executed interpretively by ZINTERP. Linking ZINTERP
with the other modules generated by
the compiler produces an executable
load module.

Although interpretive Z-code runs
more slowly than machine code, the
space savings over machine code is
usually substantial for larger programs
where the 3K bytes of ZINTERP is a
small percentage of the entire program. By balancing the number of
Z-code and machine code modules, the
user can maximize the efficiency of a
parhcular program.
PLINK resolves any external references between separately assembled
modules, so that the load module produced is relocatable. It also allows the
reordering and combining of named
sections between modules and supports
incremental linking.

PLZ/ASM Translator. The PLZ FILTER
translates a PLZIASM source module
into a file of the corresponding Z80
Assembler source. This gIves the
Assembler the beneht of logical data
structure, program flow control, and
modular program deSign, in addition to
its eXIsting features.
PLZ Linker. The PLZ Linker, PLINK,
links Z-code, ZINTERP and/or machine
code modules into Ii Single relocatable
load module, allOWing the user to control the overall size and speed of the
program.

ORDERING INFORMATION
Part No.

Description

07-3301-01

Z80 PLZ
Object Diskette for use
with PDS 8000/05 and
PDS 8000/15

07-3302-01

Z80 PLZ
Object DIskette for use
with ZDS-I Senes

07-3303-01

Z80 PLZ
Object Cartridge Disk
for use with PDS 8000/20
and PDS 8000/30

619

PLZISYS

FILTER

PLZCQ

ASM

PLINK

Figure I. Z8D PLZ Language Modules.

620

OO-1043-A

RIO Electric
Blackboard™'

~
Zilog

Product
Brief

February 1982

Features

• Full-screen text editor
• Simple, easy-to-remember commands

• Multiple windows on screen:

o Same file may be shared by two or more
windows

• Edits any size file
• Provides automatic file backup
• Easily reconfigured for any CRT

Description

The RIO Electric Blackboard is a
sophisticated multi-window, full-screen text
editor. The Electric Blackboard allows the user
to divide the CRT screen into horizontal and
vertical "windows." Because all editing is done
directly to the text on the screen, the results
are seen immediately.
Multiple Windows. A window acts as an in-

o
o

Screen can be divided horizontally and
vertically
Text may be moved between windows

dependent text editor - with its own tab settings, page sizes, cursor position (and so
forth). The Electric Blackboard allows the
screen to be divided into horizontal and vertical windows. Windows can be as narrow as
one column and as thin as one line. As many
as ten windows can be displayed on the screen
at the same time.

Both horizontal and
vertical windows

Cut text from one
window and paste
it into another

View and edit many
files simultaneously
Figure 1. Three windows looking at three Iiles: A program. a spec and a trouble report.
• Eleclnc Blackboard IS the trademark of Santa Cruz Software ServIces.

621

Description
(Continued)

The same file may be shared by two or more
windows. This is useful when two physically
separate but logically connected pieces of text
in the same file are to be edited or viewed
simultaneously. Text can be moved or copied
within or between windows allowing text and
figures to be easily rearranged.

Find and Replace Strings. The next or
previous occurrence of characters can be
found or replaced with another string. Strings
can also be repeatedly found and selectively
replaced.

Simple, Easy-to-Remember Commands. The
Electric Blackboard supports a command mode
with English-list mnemonics. See Table I for
available commands.

Saves Keystrokes. At any time during an
editing session the user can record the exact
keystrokes that are being typed. Later the
recorded keystrokes can be executed. Once
keystrokes have been recorded they can also
Function
Single Key Commands
Delete previous character
Move cursor to next Ime
Termmate execution
Move cursor
Move cursor to home posihon
Move cursor to next tab stop
Escape Key Commands
Cursor Control
Insert Character
Delete Character
Replace Character
Insert Lines
Delete Lmes
Replace Lmes
Set Margin
Reset Margin
Marking Text
Insert Mark Begin
Insert Mark End
Delete Marks
Erasmg Text
Erase Workspace
Erase Marked Text
Erase Box
Inserting and Deleting Windows
Insert Window
Insert Window Horizontally
Insert Wmdow Verhcally

Command
RUB Key
RETURN Key
BREAK Key
tl--Keys
HOME Key
TAB Key

IC
DC
RC
IL
DL
RL
SM
RM
1MB
IME
DM
EW
EM
EB
IW
IH
IV

be saved as a file on disk for later use-thus
libraries of prerecorded procedures can be
built.

Edits Large Files. The length of a text file is
limited only by the amount of space on the
disk. The Electric Blackboard automatically
manages memory for large files. As a window
is moved through a file, those parts of the file
that are needed are read in from the disk.

Automatic File Backup. Each time a file is
saved, the previous version of the file is saved
as a back-up file. In addition, the original disk
image of the file being edited is not modified
until the file is saved.

Easily Reconfigured for a Wide Range of
CRTs. The Infoton 200, ADM 3, and ADM 31
CRTs are supported by Zilog. However, a different CRT may be used with the Electric
Blackboard simply by making the appropriate
changes to the configuration package.

Function
Escape Key Commands (continued)
Moving Text
Move Marked Text
Move Box
Move Workspace
Copy Marked Text
Copy Box of Text
Copy Workspace
Loading, Savmg and Sharing FlIes
Load File
Save File
Use File
Use Option
UseWmdow
Finding and Replacing Strings
Find Next
Find Previous
Replace Next
Replace PreviOUS
Replace Repeat Next
Replace Repeat PrevIous
Managing Keystrokes
Load Keystrokes
Save Keystrokes
Delete Keystroke workspace
eXecute Keystroke workspace
eXecute File

Command

MM
MB
MW
CM
CB
CW

LF
SF
UF
UO
UW
FN
FP
RN
RP
RRN
RRP
LK
SK
DK
XK
XF

Table 1. Electric Blackboard Commands

622

00·2227·01

Z8® Development
Module

~
zilog

Product
Description

June 1982
• Two ZS-02 Devices Ofter Complete
Configuration Choice for Any
Application.

• 2048 Byte. Static RAM for ConveDient Execution and Debug of
User Code.
• On-board 2716 Socket to Test User
Code in EPROM Without Additional Hardware.

• AI Many

(III 2048 Hardware Breakpoints on Addre.. Compare Cover
the Entire Internal ROM Space.

• Versatile MoDitor Software for
Debugging. Regilter and Memory
Manipulation, and File Upload
and Download.
• 'TraDlparent' Operation Allows
Software Development Without
DiscoDD8Cllng from CRT aDd Host.
Industry-Standard Interface Compatible with Most CRT Terminals
and Development Hosts.
• Wire-Wrap Area for Prototyping.
OVERVIEW
The Z8 Development Module is a
Single-board mICrocomputer system
speCIfically deSIgned to aSSIst In the
development and evaluation 01 hardware and software designs based on the
Z8 microcomputer. It allows system
prototyping in hardware WIth the Z8-02
prototyping device, thereby developing
code that WIll eventually be mask programmed into the Z8 on-chip ROM.
Two Z8-02 devices on the Z8 Development Module provide llexIbIhty: one
serves as a controller whIle the other IS
totally user-delinable. All user ports on
the second Z8-02 are unconhgured and
available to suit any apphcahon.
To simulate the final mask-programmed verSIon on whICh user code

resides, 2048 bytes 01 h,gh-speed stahc
RAM are available lor executing and
debuggIng code. An on-board EPROM
socket allows the user to substItute
EPROM lor static RAM. This enables
the user to test PROM after soltware
development and debug WIthout buildIng special hardware.
The EPROM-resIdent mom tor software oilers debugging leatures,
regIster and memory mampulahon, as
well as a convement means to upload
and download soltware between the
host and user RAM space.
The Development Module connects
to the CRT terminal and host system
via two on-board standard RS·232C
serIal ports and IS phYSIcally located

between the CRT and host. A SImple
command makes the Development
Module transparent In the serial path to
allow software development WIthout
disconnecting Irom the CRT and host.
The Development Module can
operate stand-alone lor SImple debugging operatIons or It can Interlace
dIrectly to a host development system
such as the ZIlog ZDS-I or PDS 8000™
SerIes lor soltware development and
hIe storage.
Twenty square Inches 01 wire-wrap
area WIth convemently located 5 V and
ground points are prOVIded near the
user Z8-02 lor prototYPlng.

623

FUNCTIONAL DESCRIPTION
Hardware. Two Z8 mICrocomputer
umts designated the Monitor MCU and
User MCU are at the heart of the za
Development Module. The Momtor
MCU controls operalion of the User
MCU and the monitor/debug software.
The monitor/debugger resides m 4K
bytes of EPROM. Hardware breakpoint
logic provides a maximum of 2048
breakpomts. Smgle steppmg and software trace capabllilies are also
available.
The User MCU is a za-02 controlled
by the Momtor MCU via internal
address/data and control lines brought
out to external pms. This effectively

leaves all ports on the User MCU
unconfigured and available to the user.
The 2K bytes of stalic RAM on the
'mternal' bus are for user code that
may be executed by the User MCU.
Execution is m real time at full processor speed. Both MCUs utilize
7.4 MHz crystal oscillators, the outputs
of which are divided mternally to proVide 3.7 MHz clocks.
In addllion to wire-wrap area, a
40-pin header (3M type 3495-1002) for
the User Z8 can connect to a ribbon
cable With a 40-pin plug that may plug
into a target system. Bus driver logiC
may be added on the wire-wrap area

for baSIC emulation capability. Two
switches, 'Mode' and 'Reset', provide a
means to re-enter the Momtor and
reinitialize the system, respeclively.
Baud rate from 110 to 19200 may be
selected With an on-board 4-element
DIP sWitch.
Software. The momtor/debug pro- .
gram, residing in 4096 bytes of
EPROM, mcludes debug, input/output,
control and host interface commands.
The commands are grouped into four
major functional blocks: monitor,
debug, manipulalion and hie
commands.

Z8 Development Module conveniently connects to both the CRT and PDS 8000 Development System.

Monitor Commands. This group of commands controls
execution of the User MCU, monitors user interrupts and
transfers controls from the momtor to the host system.
GO 


HALT
QUIT
INTERRUPTS [EID}

624

Causes User MCU to execute program disallowing further debug
until a BREAK or HALT command
is encountered.
Halts program execuhon of the
User MCU.
Returns control to the host system
and enters the 'transparent' mode.
Enables or disables all user
generated interrupts. Note: All
user interrupts are automatically
disabled when a breakpoint is
encountered. It IS necessary to
reenable such interrupts by thiS
command.

Debug Commands. This group of commands allows the user
to debug code by tracing through code and setting breakpoints and Jumps to specified locations within the 'internal'
ROM space.
BREAK 

Sets a breakpoint at the speCified
address.
Clears the breakpoint at the
KILL [< ADDRESS> }
specified address.
Allows the User MCU to jump to a
JUMP < ADDRESS>
specified address anywhere within
the mternal ROM space, by changing the value of the program
counter.
Causes execution of n instructions
NEXT [}
of the User MCU and then halts
the User MCU.
Causes single step execution of the
TRACE
User MCU. Every instruction
executed is output to the console.

~

It--i
I\r-

MONITOR
EPROM

...
....

-Jl

I·CODE
REGISTERS

TRACE
STOP/GO

;::..

7-

~

MONITOR DATA BUS

I
MONITOR
MCU

1"

MONITOR
EPROM

....,

BREAK
POINT

.....

fr

PROGRAM

COUNTER

ir

y

1"
RAM

DATA
MUX

W
I

V

OATA

BUS

USER
MCU

,I

ir

~
MONITOR AODR BUS

AD DR
MUX

V

~
BUS

I~
I~
BUS

A

~

~

r

RS232C
PORTS

:UJ1
TO CRT

TO HOST

Z8 Development Module Block Diagram

Manipulation Commands. The manipulation commands
d1splay and alter reg1sters and memory. Thls group may be
subd1vided mto two categones: register mampulahon and
memory mampulation.
Register Manipulation
Allows examination and modificaREGISTER [< REG
tion of the User MCU reg1sters.
NUMBER>] [< NEW
REG VALUE>]]
WORKING REGISTERS Displays contents of the 16 working
registers of the User MCU.

PHILL < STARTING
REGISTER> ]

Stores the sequence of DATA
BYTES mto User MCU registers
beginning at the STARTING
REGISTER and is copied as many
times as necessary for the
NUMBER OF REGISTERS
speCified.

Memory Manipulation

DISPLAY [< STARTING Allows display and modification of
user memory contents for n
ADDRESS> [  II
number of bytes.
Allows a sequence of data bytes
SET 

begmning at the ADDRESS speci
[]
fied to be written into user
memory.
Stores the sequence of DATA
FILL < STARTING
BYTES mto user memory beginADDRESS>
mng at the starting ADDRESS and

[]
is copied as many hmes as
necessary for the LENGTH
specified.

IUO/OOI

MOVE < SOURCE
ADDRESS>
< DESTINATION
ADDRESS> [< n> ]
COMPARE



[]

Moves contents of a user memory
block from a source address to a
destinahon address for a length
of n bytes.
Compares two blocks of user
memory data, one beginmng at
ADDRESS 1 and the other at
ADDRESS 2 for n bytes.

File Commands. The File group enables the user to upload
and download programs to and from the host system.

LOAD
< FILE NAME>

Downloads a hie to user memory
starting at the low address of the
hie and contmumg unhl the enhre
file 1S transferred.
UPLOAD
Creates a RIO hie 1mage of user
memory, begmmng at ADDRESS



I, creating default length records,
< NUMBER OF BYTES> and imagmg memory for the
[< ENTRY ADDRESS>] specified number of bytes.
Note: The following notation is used in the command descriphon.
< > Enclose descnphve names for the
quantities to be entered, and are not
actually entered as part of the
command.
[]
Denote ophonal entries in the command syntax.
Denotes \\or.

II

625

SPECIFICATIONS
Central Processor
Momtor MCU Z8-02 (64-pm package)
User MeU. Z8-02 (64-pm package)
Clock Rate 3.7 MHz
Memory
Momtor: 4K bytes of EPROM
User: 2K bytes of stahc RAM
User' WIred socket for EPROM to
substItute for statIc RAM

Input/Output
Two RS-232C ports to CRT term mal and
host system

Power
+5V,I.4A
Physical

Baud Rate
SWItch selectable from 110 to 19200 baud

Area

Breakpoint
2048 max, valId for Address Compare,

HeIght

applIcable to user 'mternal' memory only

Control
Mode and Reset

WIre Wrap

WIdth
Depth

20 sq. In 0.036" dla.
plated-through holes
on 3/32 In. centers
1.75 In. (4.76 cm),
Includmg standoffs
14.5 In. (35.6 cm)
11.0 In. (29.9 cm)

sWItches

ORDERING INFORMATION
Part No.
05-6158-01

Description
28 Development Module.
Includes one serial mterface nbbon cable and
reference manual.

Systems recommended lor use with above:
Description

Prerequisites

2DS-1 Senes Development Systems

28 Software Development Package

PDS-8000 Senes Development
Systems

28 Software Development Package

626

00·1007 A

Z8® Software
Development Package

~
Zilog

Product
Description

June 1982
• Structured Assembly Language
with High-Level Constructs.
• Relocatable and Absolute Object
Code Format.
• Free Format Statements Allow
Indentation and Spacing for
Readability.
• External Symbol References.
• Global Symbol Definitions.

OVERVIEW
The Z8 Software Development
Package consists of five uhhty programs which aid and SImplify software
development for Z8-based systems. Z8
PLZlASM, part of Zllog's PLZ family,
brmgs all the advantages of modular
programming to Z8 software development. The programmmg task can be
broken mto eaSIly managed modules,
glvmg more work assIgnment ophons to
the engmeering manager and a clearcut structure to the mdlvldual programmer. The Z8 linker completes the task
by combmmg the modules and resolving any external references.

FEATURES
Assembler. The Z8 PLZlASM
Assembler translates easy-to-read, freeformat PLZlASM source programs to
object code. Because the user may
specdy that eIther absolute or
relocatable object code be produced,
he may choose a memory location for
the program or leave that responsIbilIty
to the Lmker. The Z8 PLZlASM
Assembler produces a hshng hie contammg both the source and assembled
code.
Z8 PLZlASM allows an efhclent mix
of powerful assembly language
mnemOlllCS wIth hIgh-level control
structures such as IF ... THEN ..
ELSE ... FI and DO ... OD loops.
The PLZlASM programmer may map
mstruchons and mformahon mto the
Z8's regIster, program and data
memory spaces, and orgalllze the data
space WIth such data declarahons as
RECORDS and ARRAYS. The
PLZIASM Assembler supports external
symbol references and global symbol
dehlllhons and IS fully supported by
the RIOTM operating system.
ZLINK. ZLINK Imks assembled modules
mto a smgle relocatable module and
resolves any external references among

separately assembled modules. It can
also reorder and combine named sechans found m the mput assembly
language modules. ZLINK accepts a
symbolic specdICation of
the program entry point m the command Ime and, on request, produces a
detaIled hnk map whICh gIves the locahans of global references and relocated
modules and sechons. Errors in the
Imkmg process are reported m the
ophonal link map and at the system
console.

Imager. IMAGER accepts mulhple
Imked-obJect hies from the hnker and
translates them into absolute code.
IMAGER can then eIther store the
absolute code in a dIsk hie or leave It
in system memory. Named sechons
found m the mput obJect modules may
be reordered and loaded anywhere m
system memory.
Program Transfer. LOAD/SEND
downloads an absolute program hie
mto the Z8 Development Module for
debuggmg, then sends It back to the
dIsk for back-up and storage.
Prom Programming_ Z-PROG stores
the perfected load module in PROM.

ORDERING INFORMATION
Prerequisites:
PDS 8000 Senes
ZDS 1140 or 1125
MCZ-l Senes
RIO

OO·1042·A

Part No.

Description

07-0086-01

Z8 Software Development Package
ObJect Cartndge DIsk
for Use WIth PDS
8000/20A

07-3361-01

Z8 Software Development Package
Object DIskette for Use
WIth PDS 8000/5 and
PDS 8000115

Part No.
07-3362-01

Description
Z8 Software Development Package
ObJect DIskette for Use
WIth ZDS-I Senes

07-3363-01

Z8 Software Development Package
ObJect Cartndge DIsk
for Use WIth PDS
8000/20 and PDS
8000/30

627

11101 Tecbalcal TralniDI
Time and money are precious oommodities in the 1980's. At
Zilog, our wide range of innovative oomponents and systems
helps you get the edge on your competitors by reducing both
system design time and costs. Zilog's Training and Education
Department oan help you by saving on those oostly hours
spent getting up to speed.
Zilog offers sophisticated microcomputer products in every
form-mioroprocessor components, OEM Boards, development
systems, powerful general purpose systems; and to give you
the knowledge necessary to take full advantage of these products, we offer thorough training and programs geared to the
needs of the individuals.
Zilog offers you the path through the state of the art training
oourses via an informal, hands-on, interactive approach that
takes you where you need to be, up to speed, in the qUickest,
most efficient way. Each course enhances your ability to use
individual Zilog produots effectively. You will get all the information you want and need.
The Zilog Training and Eduoation Department is offering an
exoeptionally wide range of courses in 1982. This catalog
describes your path through the state of the art technical training in detail.

631

Location

ZlIo, Trainin, and Education
General Information
The Zilog Training Center is located at:
1315 Dell Avenue
BUilding C
Campbell, CA. 95008
Telephone: (408) 370-8000
Ask for the Training and Education Department.

Registration

Enrollment in any of the classes listed in the catalog may be
accomplished by contacting the Training and Education
Department at the above location.
After the Training and Education Department has received
your purchase order or advance payment, written confirmation
of your registration will be provided, along with local hotel information and dIrections to the Training Center.
The Traming and Education Department requests you register
well m advance of the course date, as Zilog classes are well attended and enrollment is limited. If the purchase order or payment has not been received at least two weeks before the start
of the' class, your reservations will not be guaranteed. Payment, in the form of a confirming purchase order, check or
money order, must be received by the Training Department
prior to being admItted into the class. This must be accomplished before the start of class on the first day.

Discount

The Trainmg and Education Department offers a 10% discount
to compames with three or more employees attending a
regularly scheduled class.
The Training and Education Department also offers a 10% discount to companies with an employee attending three or more
consecutive regularly scheduled classes.

On-Site Classes

All classes described in this catalog can, by special arrangement, be presented at your facility. This on-site class is the
same course provided m our regularly scheduled classes.
The price for an on-site class IS $8000.00. It includes:
Training for up to 15 employees. There will be an addItional
charge of $100.00 for each additional employee.
Trammg materials.
One instructor.
Equipment for hands-on traming.
These courses can also be tailored to meet your needs. These
tailored on-site classes mclude the Items hsted for the standard
on-sIte class. However, the price of a tailored course will depend on each company's requirements and objechves.
For further mformatlOn regardmg on-site traimng, contact the
Trammg and Educahon Department at the above location.

032

Training Material

Instructional aids include student notebooks, appropriate Zilog
manuals, course notes and worksheets. The trainmg matenal IS
designed to aid in the retention of the material presented as
well as provide a practical reference after the formal traming
is completed.

Payment

Payment for any regularly scheduled class, or an on-site class
may be made by confirmed company purchase order, check or
money order made payable to Zilog, Inc.
Please indicate on the purchase order, and/or the enrollment
form the name(s) of the individual(s) and the class(es) the
documents pertain to.

Cancellation

Zilog reserves the right to cancel any class. If a class is
cancelled, all persons registered for that class will be notified
as soon as possible.
Cancellation of enrollment received less than two weeks prior
to the scheduled start of the class, will be subject to a
cancellation fee equal to one-third of the tuition.

If a registered student fails to appear for a scheduled class, a
cancellation fee equal to the full tuition will be charged.
A cancellation fee of one-third the cost of the on-site class will
be charged if an on-site class is cancelled, by the customer,
within 10 days prior to the scheduled start of the class.

Price

Zilog reserves the right to change pnces at any time without
notice. Confirmed registrations will be honored at the origmal
price. Registrations confirmed by the receipt of a purchase
order within 30 days of a price change WIll be honored at the
original pnce.

MICROPROCESSORS:
AGEHERA.
__ SYSTEMS

~~~~

________________________

~~

INTRODUCTION

SOPTWAAE

Your path through the State of the Art Technical Training for the '80s.

633

Microprocessors:
A General
Introduction

Length: Three days
This course introduces the world of microprocessors.
Tuition: $525
In it you wIll learn basIc mICroprocessor fundamentals and capabihties as well as the basics of microcomputerbased design. Some of the topics covered
mclude:
v What is a microprocessor?
v Some fundamental concepts about microprocessors
v Microprocessor organization
v Instruction execution
v Central processing units, memories, support chips
v Overview of ZJ!og products
A background in dIgItal logic, bmary and hex number systems
is suggested as course prerequisite.

Z8 Component
Family

The Z8 is Zilog's powerful single-chip, 8-bit mICrocomputer.
Length: Three days
This seminar is designed for hardware and software develop- Tuition: $525
ment personnel who are familiar with mIcrocomputer system
desIgn and who are interested in learning Z8 architecture,
capabilities, and supporting systems. Some of the topics
covered are:
v Z8 architecture and hmmg
v Z8 assembly language programming
v Interfacing memory and peripheral devIces
v Z8 software development tools
v Z8 Development Module and other supporting products
Designers interested in using the Z8090 UPC Universal
Peripheral Controller should also attend this seminar, smce
the architecture of the UPC is very SImIlar to that of the Z8.
A general mICrocomputer course or equivalent expenence is
suggested as a course prerequisite.

634

".,

Z8D Component

Family

............ ,

This basic course on 280 components is designed for hardware and software development personnel with a modest
background in mlCroprocessors and assembly language programmmg. This course should be taken by anyone
interested in effectively using the 280 family of products.
Some topics covered are:
".. 280 architecture and timing
".. 280 assembly language programming
".. 280 interrupt processing (interfacing non-2ilog
peripherals)
".. 280 PIa Parallel I/O Controller
".. 280 CTC Counter/Timer Controller
".. 280 DMA Direct Memory Access Controller
This course offers a "hands-on" approach to learning by doing. As each chIp is covered, students measure their progress
by programming a single-board computer in the laboratory.

Length: Four days
Tuition: $695

A general microcomputer course or equivalent experience is
suggested as a course prerequisite.

Z8DDD Component

Family

2ilog's basic course on the 28000 family of components is
Length: Four days
for hardware and software development personnel who are
Tuition: $695
familiar with microprocessor system design. Anyone interested
in effectively using the 28000 family of products should
take this course. Some of the tOPICS covered include:
".. 28000 architecture and timing
".. 28000 assembly language programming
".. 28010 MMU Memory Management Unit
".. 2-Bus peripheral interfacing
".. 28000 peripheral devices (CIa, FlO, SCC, and UPC)
".. 28000 software development tools
".. 28000 Development Module and other support products
A general microcomputer course or equivalent experience is
suggested as a course prerequisite.

635

..

ZDS-1I40
Development
System

This seminar describes 280 emulation using the 2DS-1I40
Length: One day
development system. Description of the 2DS-1I40 emphaTuition: $175
sizes those aspects of the development system that affect the
emulation process. Some of the topics covered include:
",. 2DS-1I40 hardware design
",. 280 system design hints to aid the emulation process
",. The 2ilog Analyzer Program (2AP)
",. The RIO Hardware Emulation Driver (RHED)
This course is recommended for designers of 280 systems
where the emulation process IS used as a development tool, as
well as for engineers who are directly involved in 280
emulation.
A 280 component class or equivalent 280 assembly language
experience is suggested as a course prerequisite.

EMS 8000
Emulation System

636

This seminar details the use of the EMS 8000 emulator during
development and debugging of 28000-based systems. The
emulator commands and their operation are fully described.
The EMS 8000 emulation system is a very powerful development tool for both the hardware and software engineer. Some
of the tOPICS covered include:
",. EMS 8000 hardware design
",. Use of triggers as breakpoints or trace qualifiers
",. Mapping EMS memory to the target system
",. Performance measurements for benchmarking
applications
",. Link EMS systems for multiprocessor emulations
",. Building user-definable macros of EMS commands
This course is recommended for all engineers interested in
uSing the EMS 8000 Emulation System to analyze and debug
28000-based systems. The 28000 Components family course or
eqUivalent experience IS recommended as a prerequisite.

~

MCZl/ZDS

The needs of both the new Zilog system user and the experienced desIgner are met in this Z80-based systems course.
The full range of MCZ-l and ZDS microcomputer systems is
described. EmphaSIS IS placed on RIO, the Zilog operating
system. Some topics covered are:
v' MCZ-I/ZDS hardware
v' Z80 assembler, linker, debugger, editor
v' Advanced debugging techniques (symbolic
debugging ZBUG and NBUG)
v' Elements of RIO-the MCZ-l/ZDS operating system
v' RIO structure-making system calls
v' RIO floppy disk driver-ZDOS
v' Device drivers-printers, consoles
This course provides a "hands-on" approach to learning by
doing. As each portion of the operating system is covered in
lecture, students can measure their progress by writing their
own programs in class.

Length: Four days
Tuition: $695

A Z80 component class or equivalent Z80 assembly language
experience is suggested as a course prerequisite.

MCZ-2 Systems

This Z80A-based systems course introduces the systems user
Length: Four days
to MCZ-2 local network microcomputer systems architecture
Tuition: $695
and operation. The full range of MCZ-2 systems is described,
with emphasis placed on RIOICP, Zilog's multi-tasking
operating system. Some topics covered are:
v' RIOICP (Concurrent Processing) multitasking operating
system
v' MCZ-2 System Kernel-dispatcher for multitasking
environment
v' RIO floppy disk driver-FFS
v' COBOL calls to the operating system.
v' Z-Net philosophy and local networking concepts
A Z80 component class or equivalent Z80 assembly language
experience is suggested as a course prerequisite.

637

ZEUS/System 8000
Users

The ZEUS/System 8000 operating system user course covers
features of the powerful multiuser multitasking ZEUS
Operating System. (Zilog's enhancement of UNIX· Version
VII). It is designed for persons with little or no knowledge
about ZEUS. Some topics covered are:
".. Hierarchical file system
".. C shell command language and procedures
".. ZEUS source code control system
".. ZEUS screen editor
".. Text and document processmg
".. Software development using ZEUS

Length: Five days
Tuition: $875

This course provides the student wIth lab exercises to supplement the lecture session. Some previous programming or
systems experience is recommended but is not a prerequisite
for this course.

ZEUS/System 8000
System Administrator

638

The ZEUS/System 8000 systems administrator course is
designed for persons responsible for maintaining the
ZEUS Operating System. Some of the topics covered are:
".. Role of the systems administrator
".. System organization
".. System startup
".. File system checking and repair
".. Adding users to the system
".. Commands available to the administrator
A working knowledge of the ZEUS Operating System, or
equivalent, IS suggested as a course prerequisite.

Length: Two days
Tuition: $350

zaD

Assembly
Language

ThIS seminar IS for programmers needmg to learn the Z80 low
level assembly programmmg language. The course mcludes
class presentation and hands-on programming labs that allow
the students to write theIr own assembly language programs.
Some of the tOPICS covered are:
V' Language structure and syntax
V' Z80 mstruction set
V' Z80 CPU flag and register utihzation
V' Macros
V' Subroutines
V' System calls to the RIO operatmg system
It is suggested that attendees to this seminar have some
prevIOus programmmg experience.

PLZlSYS
Programming

The PLZ programming seminar is for programmers who
need language tools that permit methodical and wellorganized programs. PLZ, Zilog's Pascal-like language,
includes the PLZ/SYS (high level, user-oriented) and
PLZlASM (a structured assembly language) elements.
Some topics covered in this seminar are:
V' Program structure
V' Data types-simple and structured
V' Recursive programming
V' Pointers and linked lists
V' System I/O calls
V' Comparison of programming languages
V' Protocols for communicating with other languages
V' The PLZ symbolic Debugging Tool (PDT)

C Programming

The C programming course is for programmers interested Length: Four days
in learning C, a high-level systems programming language. Tuition: $695
The course includes class presentation and hands-on programming labs that allow students to write their own C programs on an System 8000 system. Some topics covered are:
V' Program structure
V' Data types, data structures, and painters
V' Program flow control
V' Program development on the System 8000 system
V' System calls to the ZEUS Operating System
Some high-level language programming experience is suggested as a course prerequisite.

Length: Four days
Tuition: $695

639

I Center
Sales & Tec
~lfog. Inco ~orated
,i315 O~!l Avenue
~amQt?ell, CA 95008
Ph~ (408) 370-8120
TW 910-338-7621
S1l es & Ter:hnical Cente
zitog. Incorporat~
'm023 SkyZ
ircle
SuiteJ
Irvire. CA 714
Phone: (;'141549-2891
TWX: 910-595-2803
Sales & Technical Center
Zilog. Incorporated
15643 Sherman Way
SUite 430
Van Nuys. CA 91406
hone: (213) 989-7485
WX: 910-495-1765
les & Technical Center
log. Incorporated
~50 112th Ave "'E.
uite 0161
WA98004
. (206) 454-5597

Midwest

East

Sales & Technical Center
Zilog. Incorporated
890 East Higgins Road
Suite 147
Schaumburg.ll
95
Phone: (312,.
-8080
TlNX: 910-291-1064

Sales & Technical Center
Zilog. Incorporated
Corporate Place
~~ South Bedford SI.
Eurlington. MA01803
Phone: (617) 273-4222
TWX: 710-332-1726

Sales & Technieal Center
Zilog. Incorporated
28349 Chagrin Blvd.
Sui1e 109
Woodmere. OH 441
Pfione: (216) 831-7
FAX: 216-831-2957

Technical Center
j!:ilog. Incorporated
110 Gibraltar Road
Horsham. PA 19044
Phone: (215) 441-8282
TWX: 510-665-7077

South
Sales & Technical Center
Zilog. Incorporated
48511 Keller"springs Road.
S ite211
Oa. s. TX 75248
Ph~ : (214)931-9090
TWX: ' 0-860-5850
lilog , If?, orporated
7113 B (net Rd
StJite2fll7
Austin. TX 78757
Phone; (512) 453-3216

France

Sales & Technical Center
Zilog.lncorporatea
240 Cedar Knolls Rd.
Cedar Knolls. NJ 07927
Phone: (201) 540-1671
If!chnical Center
Zilog. Incorporated
3300 Buckeye Rd.
Suite 401
Atlanta. GA 30341
Phone: (404) 451-8425
Sales & Technical Center
Zilog.lncorporated
1442 U.S Hwy 19 South
Suite 135
Clearwater. FL33516
Phone: (813) 535-5571

Zilog.lncorporat
Tour Europe
Cedex 7
92080 Paris La Defe
France
Phone: (1) 778-14-3
TWX: 611445F

ZilogGmbH
Zugspitzstrasse 2a
0-8011 Vaterstetten
Munich. West Germ
Phone: 08106 4035
Telex: 529110 Zilog d.

Japan
Zilog. Japan K.K.
Konparu Bldg. 5F
2-8. Akasaka 4-Chom
Minato-Ku. Tokyo 107
Japan
Phone: (03) 587-0528
Telex: ESSOEAST ~22

Zilog
1315 Dell Drive
Campbell. Calif. 95008
Phone: (408) 370-8000
TWX: 910-338-7621
00-2034-02
Printed in U.S.A.
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