1983_TI_High_Speed_CMOS_Logic_Data_Book 1983 TI High Speed CMOS Logic Data Book

User Manual: 1983_TI_High_Speed_CMOS_Logic_Data_Book

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SCLD001

lIigh--speed
CMOS
ic
DataBooK
1983

Silicon-gate
COITlpleITlentary MOS

..If
TEXAS
INsrRUMENTS

GENERAL INFORMATION . .
RATINGS AND CHARACTERISTICS . .
DESCRIPTIVE INFORMATION . .
EXPLANATION OF LOGIC SYMBOLS . .
ORDERING INSTRUCTIONS AND MECHANICAL DATA . .
ICSOCKETS . .

TI Sales Offices

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Laurent. Ville" Sr. LaUTf'nr Quehec. 9460 Trans C.lnaJa Hw}'"
St. Lau«nt. Que~c. CanaJa H4SIR7. (5141134·1611.
A

COLORADO: Denver. 972 5 E. Hampden Sr .• Suire 101.
Dcnver. COBOZlI. (l03) 695·Z800.

GEORGIA: Atlanta. 3100 North.." bpv.. BuilJing 9.
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.
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Rochester. IZIO jeffe""n RJ .• Rochester. NY 146Zl. (716)
424·5400.

TI Distributors
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NORTH CAROLINA: Arrow (919) 876·1I 3Z. (919)
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OHIO: Cincinnati. Graham (Ill) 772-1661; Hall·Mark (Ill)
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47l·Z907; Kierulff (2161 587·6558; Columbus. Hall·Mark (6141
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771·7217; Hall·Mark (71l) 781·6100; Harrison Equipm.nt
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UTAH: Diplomat (801 J 486·4134; Kierulff(80I) 973.6913;
Wyl. (SOl) 974·9951.

WISCONSIN: Arrow (414) 764·6600; Hall·Mark (414)
761·1000; Kierulff(414) 784·8160.

OHIO: Beachwood. Z3408 Commerce Park RJ .• lleachw...J.
OH 44122. (ZI6) 464·6100; Dayton. Kmgsl.y BIJg .• 4124
LinJen Av•.• Dayton. OH 4143Z. (511) ZI8·1877.

OREGON: Beaverton. 6700 SW IOlth St .. SUlle 110.
Beave"on. OR 97005. (50l) 641·6758.

NEW JERSEY: Arrow (ZOI) 575·5300. (609) Zl5·1900;
D'ph'ma, (201) 785·1810; G.neral Rad.o (6091964·8560;
Hall·M"k (ZOI) 571-4411. (609) 424·0880;)ACO (ZOI)
778·472Z; Kirrulff(ZOI) 575·6750; Marshall (ZOI) 140·1900;
Milgray (6091981·1010.

WASHINGTON: Arrow (Z06) 641·4800; Kierulff (Z06)
575-4420; Wyl. (Z06) 451·8100.

NORTH CAROLINA: Charlotte. 8 W.. ,Jlawn Green.
W",Jlawn RJ .. Charlotte. NC Z8Z10. (7041127·0910;
Raleigh. 1000 Highw.. ,Js BlvJ .• Suire 118. Raleigh.
NC 276Z5. (919) 876·Z725.

OKLAHOMA: Tulsa. 1105 E. Sk.lly Dr.. Suite 110. Tulsa.
OK 74105. (918) 749.9547.

NEW HAMPSHIRE: Am'w (601) 1068·6968.

TEXAS
INSTRUMENTS

CANADA: Calgary. Future (403) Z59·6408; Varah (403)
BO·lll5; Hamilton. Varah (416) 561·9111; Montreal. CESL.'O
(514) 735·5511; Future (5\4) 694·7710; Ottawa.CESCO (61l)
ZZ6·6905; future (611) 8Z0·831 3; Quebec City. CESL.'O (418)
687·4ZlI; Toronto. CESCO (416) 661·0ZZ0; Future (416)
661·5163; Vancouver. Future (604) 418·5545; Varah (6041
873·111l; Winnipeg. Varah (Z04) 6JJ·6190.
BA

High--Speed CMOS Logic
Data Book

TEXAS

INSTRUMENTS

SCLD001
0283-288PP-100M

Printed in U.S.A.

IMPORTANT NOTICE

Texas Instruments reserves the right to make changes at any time in
order to improve design and to supply the best product possible.
Texas Instruments assumes no responsibility for infringement of patents
or rights of others based on Texas Instruments applications assistance
or product specifications, since TI does not possess full access to data
concerning the use or applications of customer's products. TI also
assumes no responsibility for customer product designs.
ISBN 0-89S12-114-X
Library of Congress No. 82-074480

Copyright © 1983 Texas Instruments Incorporated

HIGH-SPEED CMOS LOGIC DATA BOOK
1983
Texas Instruments is pleased to announce the SN74HC family of high-speed CMOS
logic circuits. This versatile new family promises to be the product family of choice for
many new logic systems, offering a unique combination of high-speed, low-power
dissipation, high noise immunity, wide fanout capability, extended supply voltage
range, and high reliability.
This data book describes the initial product line scheduled for introduction during
1983. Included are pinout and package information, logic symbols, maximum ratings
and dc electrical characteristics. At the time of this edition, JEDEC recommendations
for ac performance have not been finalized, consequently the timing requirements
and switching characteristics for each device have been left blank. However, as each
new family member is released, TI will publish the corresponding ac parameters,
which may be obtained from your nearest TI field sales office or your local authorized
TI distributor. Later editions of this data book will contain complete ac specifications.

v

TI Worldwide
Sales Offices
ALABAMA: Huntsvme. 500 Wynn Drive. Suite 514.
Hunuville. AL 35B05. (205) 837-7S30.
ARIZONA: Phoenix. P.O. Box 3SI6O. 8102 N. 23rd Ave .•
Suitrt. SK12RT. EnglanJ.
061 4428448.
RA

NORlll CAROLINA: Charlotte. 8 Woodlawn Green.
Woodlawn Rd" Charlotte. NC28Z10. (704) 527·0930,
Raleigh. 3000 Highwoods Blvd .• Suite 118. Raleigh.
NC 27625. (919) 876·2725.
OHIO: Beaehwood. 23408 Commerce Park Rd .• Beachwood.
OH 44122. (216) 461·6100, Dayton. Kingslev Bldg .• 1121
linden Ave .• Davton. OH 45432. (513) Z58·J877.

lepanto Bldg .• 8747 Paseo de Roxas, Makatl, Merro Manila.

TEXAS
INSTRUMENTS

II
GENERAL INFORMATION
Alphanumeric Index .. . • • . • . . . • . . . . . . . . . • . • • . . . . • . . . • . . . . . • . . . . . • • • . • • . • .• 1-2
Glossary. . . . . • . . . . . • • . . . . • . . . • . . • . . • . • . . . • . . . . . . . . . . . . • • . . . . • • • . • . . . . . . .• 1-4
FunctionallndexiSelection Guide .......................................... 1-7
Explanation of Function Tables ........................................... , 1-12
Parameter Measurement Information ..................................... 1-14

1-1

ALPHANUMERIC INDEX
TYPE
NUMBERS

II

'HCoo
'HC02
'HC04
'HC08
'HC10
'HC11
'HC14
'HC20
'HC21
'HC27
'HC30
'HC32
'HC36
'HC42
'HC51
'HC73
'HC74
'HC75
'HC76
'Hcn
'HC78
'HC85
'HC86
'HC107
'HC109
'HC112
'HC113
'HC114
'HC123
'HC132
'HC133
'HC137
'HC138
'HC139
'HC147
'HC151
'HC152
'HC153
'HC154
'HC157
'HC158
'HC160
'HC161
'HC162
'HC163
'HC164
'HC165
'HC166

RATINGS AND
CHARACTERISTICS·
TABLE
PAGE

V

V

II
1/
II
1/
II
IV

IV
IV
IV
IV
1/1
III
III
IV
III
III
IV
IV
IV
IV
IV
IV
IV

2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-6
2-3
2-4
2-4
2-4
2-4
2-4
2-4
2-6
2-3
2-4
2-4
2-4
2-4
2-4
2-6
2-3
2-3
2-6
2-6
2-6
2-6
2-5
2-5
2-5
2-6
2-5
2-5
2-6
2-6
2-6
2-6
2-6
2-6
2-6

DESCRIPTIVE
INFORMATIONt
PAGE
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-17
3-18
3-20
3-22
3-24
3-26
3-28
3-30
3-32
3-34
3-36
3-38
3-40
3-42
3-44
3-46
3-47
3-48
3-50
3-52
3-54
3-56
3-58
3-60
3-62
3-64
3-64
3-66
3-66
3-66
3-66
3-72
3-74
3-77

TYPE
NUMBERS
'HC173
'HC174
'HC175
'HC189
'HC190
'HC191
'HC192
'HC193
'HC194
'HC195
'HC221
'HC240
'HC241
'HC242
'HC243
'HC244
'HC245
'HC251
'HC253
'HC257
'HC258
'HC259
'HC266
'HC273
'HC280
'HC299
'HC323
'HC352
'HC353
'HC354
'HC356
'HC365
'HC366
'HC367
'HC368
'HC373
'HC374
'HC377
'HC378
'HC379
'HC386
'HC390
'HC393
'HC423
'HC490
'HC533
'HC534
'HC563

RATINGS AND
CHARACTERISTICS·
TABLE
PAGE
III
IV
1/
III
IV
IV
IV
IV
IV
IV
IV
III
III
/1/
III
/1/
III
III
III
III
III
IV
IV
IV
III
III
III
III
III
III
III
III
III
III
III
III
IV
IV

IV
IV
IV
IV
III
1/1
III

·See these pages for absolute maximum ratings. recommended operating conditions. and electrical characteristics.
tSee these pages for description. pin assignments. timing requirements. and switching characteristics.

1-2

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

2-5
2-6
2-4
2-5
2-6
2-6
2-6
2-6
2-6
2-6
2-6
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-6
2-3
2-6
2-6
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-6
2-6
2-4
2-3
2-6
2-6
2-6
2-6
2-5
2-5
2-5

DESCRIPTIVE
INFORMATION
PAGE
3-80
3-82
3-82
3-84
3-87
3-87
3-91
3-91
3-95
3-98
3-100
3-102
3-102
3-104
3-104
3-106
3-108
3-110
3-112
3-114
3-114
3-116
3-118
3-119
3-121
3-123
3-126
3-129
3-131
3-133
3-136
3-139
3-139
3-139
3-139
3-141
3-143
3-145
3-145
3-145
3-148
3-149
3-149
3-152
3-154
3-156
3-158
3-160

ALPHANUMERIC INDEX
TYPE
NUMBERS
'HC564
'HC573
'HC574
'HC590
'HC592
'HC593
'HC594
'HC595
'HC597
'HC598
'HC620
'HC623
'HC640
'HC643
'HC645
'HC646

RATINGS AND
CHARACTERISTICS·
TABLE
PAGE
III
III
III
III
IV
III
III
III
IV

111
111
III
III

111
III

111

2-5
2-5
2-5
2-5
2-6
2-5
2-5
2-5
2-6
2-5
2-5
2-5
2-5
2-5
2-5
2-5

DESCRIPTIVE
INFORMATIONt
PAGE
3-162
3-164
3-166
3-168
3-170
3-170
3-173
3-175
3-177
3-177
3-180
3-180
3-183
3-183
3-183
3-186

TYPE
NUMBERS
'HC648
'HC651
'HC652
'HC688
'HC4002
'HC4017
'HC4020
'HC4040
'HC4060
'HC4075
'HC4078
'HC4511
'HC4514
'HC4515
'HC4538
'HC4724

RATINGS AND
CHARACTERISTICS·
TABLE
PAGE
III
III
III
IV
I
IV
IV
IV
IV
I
IV
IV
IV
IV
IV

2-5
2-5
2-5
2-6
2-3
-2-6
2-6
2-6
2-6
2-3
2-3
2-6
2-6
2-6
2-6
2-6

DESCRIPTIVE
INFORMATIONt
PAGE
3-186
3-190
3·190
3-194
3-196
3-197
3-199
3-201
3~203

3-205
3-206
3-207
3-209
3-209
3-212
3-214

II

·See these pages for absolute maximum ratings. recommended operating conditions. and electrical characteristics.
tSee these pages for description. pin assignments. timing requirements. and switching characteristics.

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1-3

GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEOEC Counc-il of the
Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (IEC)
for international use.
OPERATING CONDITIONS AND CHARACTERISTICS (IN SEQUENCE BY LETTER SYMBOLS)

•

Cpd

Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (See individual circuit pages):
Po = Cpd VCC 2 f + ICC VCC.

f max

Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence while
maintaining stable transitions of logic level at the output with input conditions established that should cause
changes of output logic level in accordance with the specification.

ICC

Supply current
The current into· the VCC supply terminal of an integrated circuit.

IIH

High-level input current
The current into· an input when a high-level voltage is applied to that input.

IlL

Low-level input current
The current into· an input when a low-level voltage is applied to that input.

10H

High-level output current
The current into· an output with input conditions applied that, according to the product specification, will
establish a high level at the output.

10L

Low-level output current
The current into· an output with input conditions applied that, according to the product specification, will
establish a low level at the output.

lOS

Short-circuit output current
The current into· an output when that output is short-circuited to ground (or other specified potential) with
input conditions applied to establish the output logic level farthest from ground potential (or other
specified potential).

10Z

Off-state (high-impedance-state) output current (of a three-state output)
The current flowing into· an output having three-state capability with input conditions established that,
according to the production specification, will establish the high-impedance state at the output.

V,H

High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent the
binary variables.
NOTE: A minimum is specified that is the least-positive va lue of high-level input voltage for which operation
of the logic element within specification limits is guaranteed.

• Current out of a terminal is given as a negative value.

1-4

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GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
VIL

Low-level input voltage
An input voltage level within the less positive(more negative) of the two ranges of values used to represent the
binary variables.
NOTE:
A minimum is specified that is the most-positive value of low-level input voltage for which operation
of the logic element within specification limits is guaranteed.

VOH

High-level output voltage
The voltage at an output terminal with input conditions applied that. according to product specification, will
establish a high level at the output.

VOL

Low-level output voltage
The voltage at an output terminal with input conditions applied that. according to product specification. will
establish a low level at the output:
Positive-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according to
specification as the input voltage rises from a level below the negative-going threshold voltage, VT-.
Negative-going threshold level
The voltage level at a transition-operated input that causes operation of the logic element according to
specification as the input voltage falls from a level above the positive-going threshold voltage, VT+.

ta

Access time
The time interval between the application of a specified input pulse and the availability of valid signals at an
output.

tdis

Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms. with the
three-state output changing from either of the defined active levels (high or low) to a high-impedance (off)
state. (tdis = tPHZ or tpLZ).

ten

Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms. with the
three-state output changing from a high-impedance (off) state to either of the defined active levels (high or
low). (ten = tpZH or tpzLl.

th

Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal.
NOTES: 1.
The hold time is the actual time interval between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is guaranteed.
2.

•

The hold time may have a negative value in which case the minimum limit defines the longest
interval (between the release of the signal and the active transition)forwhich correct operation
of the digital circuit is guaranteed.

tpd

Propagation delay time
The time between the specified reference points on the input and output voltage waveforms with the output
changing from one defined level (high or low) to the other defined level. (tpd = tPHL or tPLH).

tPHL

Propagation delay time, high-to-Iow level output
The time between the specified reference points on the input and output voltage waveforms with the output
changing from the defined high level to the defined low level.

tPHZ

Disable time (of a three-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms with
the three-state output changing from the defined high level to a high-impedance (off) state.

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1·5

I

GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS

•

tpLH

Propagation delay time. low-to-high-Ievel output
The time between the specified reference points on the input and output voltage waveforms with the output
changing from the defined low level to the defined high level.
.

tpLZ

Disable time (of a three-state output) from low level
The time interval between the specified reference points on the input and output voltage waveforms with the
three-state output changing from the defined low level to a high-impedance (off) state.

tpZH

Enable time (of a three-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state to the defined high level.

tpZL

Enable time (of a three-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state to the defined low level.

tsr

Sense recovery time
The time interval needed to switch a memory from a write mode toa read mode and toobtain valid data signals
at the output.

tsu

Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is guaranteed.
2.

tw

1-6

The setup time may have a negative value in which case the minimum limit defines the longest
interval (between the active transition and the application of the other signal)forwhich correct
operation of the digital circuit is guaranteed.

Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse waveform.

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FUNCTIONAL INDEX/SELECTION GUIDE
FUNCTIONS

PAGE

ANDINAND Gates and Inverters ••....•••••.•....•••...••........•......••..•...•..•.•.....•.•......•..•••.•.. 1-8
OR/NOR/EXCLUSIVE-OR and A-O-I Gates •.•.•••..•.....•...•.•...•.......•...•••.•.....•..•.....•.•..•...... 1-8
Schmitt-trigger NAND Gates and Inverters •.••.•..••.••.•.•.•.••....••.•.•.......................••........••• 1-8
Bus Drivers and Transceivers with 3-State Outputs •.•..•••.••......•......•.............•...••...........•.... 1-8
Dual J-K Flip-flops •••.••••..••.•....••..••....••.•............••.......•..........•....••............•...•.• 1-9
D-Type Flip:flops .••.•.•• , •••...•..•.•..••.••.•.••..•••..•....•.......••......••..•....••........•.•......•.. 1-9
Latches and Registers •..•••.•......•...•••••.....•.•.•...•••.......•.•........ ~ . . . . • • • • . . . . . . . • . . . . . . . . • . • .. 1-9
Monostable Multivibrators ••••••...•.•....•••.•...•.••...•.•..•......••.....•..•.•..............••........•.. 1-9
Shift Registers •••.•••••••••••••••••••••••••..•............................................................. 1-10
Asynchronous Counters ..•••••.••..•.•......•••....•.•.......••.•......•...............•••.......••......•. 1-10
Synchronous Counters .••••.••......••...•••.•.•...••.•.....•••......•.•.......•......••..................• 1-10

..

Comparators, Parity Generators/Checkers, and Priority Encoders .............................................•. 1-10
Data Selectors/M ultiplexers ....••..•.•..••.•...•.•••..••.••.•.....•....••...•.....•.•......•..•.......•..•. 1-11
Decoders/Demultiplexers ••.... ; •.••......•••.•...•......••.•.••..•..•......•.••.....•........•...........•. 1-11
Display Decoders/Drivers .••.••....••.•..••....•••.....••......••.......••...........•..••..•......•.......• 1-11
Random-Access 'Memories (RAM's) .•......•••.•.•....••.......•.•.....••..........•.....•.......•••.......•. 1-11

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1-7

FUNCTIONAL INDEX/SELECTION GUIDE
AND, NAND GATES AND INVERTERS

OR, NOR, EXCLUSIVE-OR, AND
AND-OR-INVERT GATES

(for Maximum Ratings and Electrical Characteristics See Table I,
Page 2-3)

(for Maximum Ratings and Electrical Characteristics See Table I,
DESCRIPTION

a

Hex Inverters
Quad 2-lnput NAND Gates
Quad 2-lnput AND Gates
Triple 3-lnput NAND Gates
Triple 3-lnput AND Gates
Dual 4-lnput NAND Gates
Dual4-lnput AND Gates
8-lnput NAND Gate
13-lnput NAND Gate

DEVICE
TYPE
'HC04
'HCOO
'HC08
'HC10
'HC11
'HC20
'HC21
'HC30
'HC133

DESCRIPTIVE
INFORMATION
3-4
3-2
3-5
3-6
3-7
3-9
3-10
3-12
3-47

SCHMITT-TRIGGER GATES AND INVERTERS
(for Maximum Ratings and Electrical Characteristics See Table I,
Page 2-3)
DESCRIPTION
Hex Inverters
Quad 2-lnput NAND Gates

DEVICE
TYPE
'HC14
'HC132

Page 2-3)
DEVICE
DESCRIPTION
TYPE
'HC02
Quad 2-lnput NOR Gates
'HC36
Quad 2-lnput OR Gates
'HC32
Quad 2-lnput EXCLUSIVE'HC266
NOR Gates
Quad 2-lnput EXCLUSIVE-OR
'HC86
Gates
'HC386
Dual 2-Wide 2-lnput A-O-I
'HC51
Gates
Triple 3-lnput NOR Gates
'HC27
Triple 3-lnput OR Gates
'HC4075
Dual 4-lnput NOR Gates
'HC4002
8-lnput NOR Gate
'HC4078

DESCRIPTIVE
INFORMATION
3-3
3-14
3-13
3-118
3-32
3-148
3-17
3-11
3-205
3-196
3-206

DESCRIPTIVE
INFORMATION
3-8
3-46

BUS DRIVERS .AND TRANSCEIVERS WITH 3-STATE OUTPUTS
DESCRIPTION
Quad Bus Transceivers

Hex Bus Drivers/Receivers

Octal Bus Drivers/Receivers

Octal Bus Transceivers

(for Maximum Ratings and Electrical Characteristics See Table III, Page 2-5)
DEVICE
OUTPUT DATA
CONTROL INPUTS
TYPE
Inverting
Independent Enables
'HC242
True
True
Inverting
True
Inverting
Inverting
True
Inverting
True
Inverting
True and Inverting
True

Octal Bus Transceivers
with Registers

1-8

for A and B Buses
Common Enables
Symmetrical Enables
Symmetrical Enables
Complementary Enables
Symmetrical Enables
Independ.ent Enables
for A and B Buses
Enable and
Direction Control

True

Enable and

Inverting
Inverting
True

Direction Control
Independent Enables
for A and B Buses

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'HC243
'HC365
'HC366
'HC367
'HC368
'HC240
'HC241
'HC244
'HC620
'HC623
'HC640
'HC643
'HC645
'HC245
'HC646
'HC648
'HC651
'HC652

DESCRIPTIVE
INFORMATION
3-104

3-139

3-102
3-106
3-180

3-183
3-108
3-186
3-190

FUNCTIONAL INDEX/SELECTION GUIDE
D-TYPE FLIP-FLOPS
DESCRIPTION
Dual D-type Flip-flops with
Preset and Clear
Quad D-Type Flip-flops with
Common Clocks
Hex D-Type Flip-flops with
Common Clocks

OUTPUT
CONFIGUATION
Complementary
Complementary
Qonly
Qonly

Octal D-type Flip-flops
with Common Clocks

3-State, Q only

OTHER
FEATURES
Independent
Clocks
Common Clear
Output Enable
Common Clear
Output Enable
Common Clear
Output Enable

DEVICE
TYPE

Output Control

3-State, Q only

Output Control

RATINGS AND
CHARACTERISTICS

TABLE

PAGE

II

2-4

DESCRIPTIVE
INFORMATION
3-20

'HC74
'HC175

3-82
3-145
3-82

'HC379
'HC174
'HC378
'HC273

IV

2-6

III

2-5

'HC377

3-145
3-119
3-145
3-143

'HC374
'HC574
'HC534

3-166
3-158
3-162

'HC564

DUAL J-K FLIP-FLOPS

II

(for Maximum Ratings and Electrical Characteristics See Table II,
Page 2-4)

Dual J-K Flip-flops with Preset

DEVICE
TYPE
'HC73
'HC107
'HC113

Dual J-K Flip-flops with

'HC78

3-28

'HC114

3-42

'HC76

3-24

'HC112

3-38

'HC109

3-36

DESCRIPTION
Dual J-K Flip-flops with Clear

DESCRIPTIVE
INFORMATION
3-18
3-34
3-40

Preset, Common Clock, and
Common Clear
Dual J-K Flip-flops with Preset
and Clear
Dual J-K Flip-flops with Preset
and Clear

LATCHES AND REGISTERS

DESCRIPTION
Quad D-type Latches
Quad D-type Registers

DEVICE
TYPE

OUTPUTS
Complementary
Qonly
Q only, 3-state

'HC75
'HC77

II

2-4

'HC173
'HC373

Q only, 3-state

'HC573

Octal D-Type Latches

'HC533
'HC563

Q only, 3-state
8-8it Addressable Latches

RATINGS AND
CHARACTER ISTICS
TABLE
PAGE

'HC4724
'HC259

Oonly

DESCRIPTIVE
INFORMATION
3-22
3-26
3-80
3-141

III

2-5

IV

2-6

3-164
3-156
3-160
3-214
3-116

MONOSTABLE MULTIVIBRATORS
(for Maximum Ratings and Electrical Characteristics See Table IV, Page 2-4)
DEVICE
FEATURES
DESCRIPTION
TYPE
Dual Monostable Multivibrators

I

with Direct Clear, Postive
and Negative Inputs, and
complementary Outputs

Retriggerable

I Will not trigger from clear

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DESCRIPTIVE
INFORMATION

'HC221

3-100

'HC123

3-44
3-152
3-212

'HC423
'HC4538

1-9

FUNCTIONAL INDEX/SELECTION GUIDE
SHIFT REGISTERS

J-K/Parallel

Parallel

DEVICE
TYPE
'HC195

Serial/Parallel

Parallel

'HC194

DESCRIPTION

INPUTS

4-Bit Shih Register with Clear
4-Bit Bidirectional Shih
Registers with Clear

Serial/Parallel, Clock
Inhibit, Shih/Load
2 Serial, Clear
Serial/Parallel, Clear;
Clock Inhibit, Shih/Load
Serial/Parallel

8-Bit Shift Registers

a

OUTPUTS

8-Bit Shift Registers with
Input Registers
8-Bit Bidirectional Shift
Registers with Storage and
Multiplexed 3-State I/O
8-Bit Shift Registers with
Output Registers

RATINGS AND
CHARACTERISTIC
TABLE
PAGE

DESCRIPTIVE
INFORMATION
3-98
3-95

2 Serial

'HC165

Parallel

'HC164

3-72

Serial

'HC166

3-77

IV

2-6

3-74

Serial

'HC597

3-177

Serial/Parallel

3-state Parallel
(Multiplexed I/O)

'HC598

3-177

Serial/Parallel

3-state Parallel

'HC299
'HC323

Serial

Parallel
3-State Parallel

'HC594
'HC595

III

2-5

3-123
3-126
3-173
3-175

SYNCHRONOUS COUNTERS
DESCRIPTION

Async Clear
Sync Clear
Clock Inhibit
Async Clear

Decade
Decade Up/Down
Divide-by- 10
Johnson Counter
4-Bit Binary
4-Bit Binary Up/Down
8-Bit Binary with
Input Registers
8-Bit Binary with
Output Registers

FEATURES

TYPE

Sync Load
Async Load

Async Clear

'HC4017
'HC161
'HC163
'HC191
'HC193
'HC592

Sync Clear

Sync Clear

Async Load

Multiplexed
3-state I/O

'HC593

3-state Outputs

'HC590

ASYNCHRONOUS (RIPPLE CLOCK) COUNTERS
(for Maximum Ratings and Electrical Characteristics See Table IV,
Page 2-6)
DESCRIPTION

FEATURES

DEVICE DESCRIPTIVE
INFORMATION
TYPE

12-Bit Binary
'HC4040
Counters
'HC4020
14-Bit Binary
Counters
On-chip Oscillator 'HC4060
Dual Decade Bi-quinaryor BCD 'HC390
Counters
Set-to-9 Input
'HC490
Dual 4-Bit Bi'HC393
nary Counters

1-10

'HC160
'HC162
'HC190
'HC192

Async Clear
Sync Clear
Clock Inhibit
Async Clear

Sync Load

3-201
3-199
3-203
3-149
3-154

RATINGS AND
CHARACTERISTICS
TABLE
PAGE

DESCRIPTIVE.
INFORMATION
3-66
3-66
3-87
3-91
3-197

IV

2-6

III

2-5

3-66
3-66
3-87
3-91
3-170
3-170
3-168

COMPARATORS, PARITY GENERATORS/
CHECKERS, AND PRIORITY ENCODERS
(for Maximum Ratings and Electrical Characteristics See Table IV,
Page 2-6)
DEVICE
DESCRIPTIVE
DESCRIPTION
INFORMATION
TYPE
3-30
4-Bit Magnitude Comparators
'HC85
8-Bit Magnitude Comparators
'HC688
3-194
9-Bit Odd/Even Parity
Generator/Checker
10-Line Decimal to 4-Line
BCD Priority Encoder

3-149

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'HC280

3-121

'HC147

3-54

FUNCTIONAL INDEX/SELECTION GUIDE
DATA SELECTORS/MULTIPLEXERS
DESCRIPTION

8-Line-to-1-Line

DuaI4-line-to-1-Line

Quad 2-Line-to-1-Line

(for Maximum Ratings and Electrical Characteristics See Table III Page 2-5)
DEVICE
INPUTS
OUTPUTS
TYPE
Inverting
'HC152
Complementary
'HC151
Enable
Complementary, 3-state
'HC251
Transparent
Complementary
'HC354
Latches, Enable
3-state
Registers, Enable
'HC356
True, 3-state
'HC253
Independent
Inverting, 3-state
'HC353
Enables
True
'HC153
Inverting
'HC352
True
'HC157
Inverting
'HC158
Common Enable
True, 3-state
'HC257
Inverting, 3-state
'HC258

DESCRIPTIVE
INFORMATION
3-58
3-56
3-110
3-133
3-136
3-112
3-131
3-60
3-129
3-64
3-64
3-114
3-114

..

DECODERS/DEMULTIPLEXERS
(for Maximum Ratings and Electrical Characteristics See Table IV,
Page 2-6)
DEVICE DESCRIPTIVE
DESCRIPTION
FEATURES
TYPE INFORMATION
2 Enables
'HC154
3-62
4-Line-to-16-Line Input latches, 'HC4514
3-209
Output Enable 'HC4515
3-209
4-Line-to-10-Line,
'HC42
3-15
BCD-to-Decimal
3 Enables
'HC138
3-50
3-Line-to-8-Line
Dual 2-Lineto-4-Line

3 Enables, Ad'HC137
dress Latches
Independent
'HC139
Enables

3-48
3-52

DISPLAY DECODERS/DRIVERS
DESCRIPTION
BCD-to-7-Segment Decoders/Drivers
with Input Latches

DEVICE
TYPE

RATINGS AND
CHARACTERISTICS
PAGE
TABLE

I

'HC4511

IV

3-207

2-6

I

DESCRIPTIVE
INFORMATION

RANDOM ACCESS MEMORIES

DESCRIPTION

54-Bit

ORGANIZATION

FEATURES

DEVICE
TYPE

16x4

3-state Outputs

'HC189

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RATINGS AND
CHARACTERISTICS
TABLE
PAGE

I

III

I

2-5

DESCRIPTIVE
INFORMATION
3-84

1-11

EXPLANATION OF FUNCTION TABLES

The following symbols are now being used in function tables on TI data sheets:
H

high level (steady state)

L

low level (steady state)
transition from low to high level
transition from high to low level

..

X

irrelevant (any input, including transitions)

Z

off (high-impedance) state of a 3-state output

a .. h

the level of steady-state inputs at inputs A through H respectively
level of a before the indicated steady-state input conditions were established

00

complement of

an

level of a before the most recent active transition indicated by

JL =
LJ =
TOGGLE

00 or level of Q before the indicated steady-state input conditions were established
t or 1

one high-level pulse
one low-level pulse
each output changes to the complement of its previous level on each active transition indicated by

t or 1.

If. in the input columns. a row contains only the symbols H. L. and/or X. this means the indicated output is valid whenever
the input configuration is achieved and regardless of the sequence in which it is achieved. The output persists so long as the
input configuration is maintained.
If. in the input columns. a row contains. H. L. and/or X together with f and/or 1. this means the output is valid whenever the
input configuration is achieved but the transition(s) must occur following the achievement of the steady-state levels. If the
it persists so long as the steady-state input levels and the levels that terminate
output is shown as a level (H. L. 00. or
indicated transitions are maintained. Unless otherwise indicated. input transitions in the opposite direction to those shown
have no effect at the output. (If the output is shown as a pulse.
or
the pulse follows the indicated input
transition and persists for an interval dependent on the circuit.)

60).

IL

1-12

LJ.

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EXPLANATION OF FUNCTION TABLES
Among the most complex function tables in this book are those of the shift registers. These embody most of the symbols used
in any of the function tables. plus more. Below is the function table of a 4-bit bidirectional universal shift register. e.g .• type
SN74HC194.

FUNCTION TABLE
INPUTS
CLEAR

MODE

~

L
H

X
X

H
H

CLOCK

X
X

X

H

H

L

H

H
H

L
H

H

H

H

L

1
!
!
!
I

H

L

L

X

L

L

OUTPUTS

SERIAL
LEFT RIGHT

PARALLEL
A

B

C

D

X
X

X

X

X
X
c
X
X
X
X
X

X
X

L

X
X
a
X
X

X
X
X

X
X

X
X

H

H
L

X

X

X

X
X

X

b

X
X
X
X
X

QA

QB

QC

L

L

L

L

OAO

OCO

ODO

QD

d

a

OBO
b

X

H

OAn OBn

OCn

X

L

OAn OSn

OCn

X
X
X

OBn

QCn QDn

H

OBn

OCn ODn

GAn

OSn

c

OCn

d

L

ODO

..
I

The first line of the table represents a synchronous clearing of the register and says that if clear is low. all four outputs will be
reset low regardless of the other inputs. In the following lines. clear is inactive (high) and so has no effect.
The second line shows that so long as the clock input remains low(while clear is high). no other input has any effect and the
outputs maintain the levels they assumed before the steady-state combination of clear high and clock low was established.
Since on other lines of the table only the rising transition of the clock is shown to be active. the second line implicitly shows
that no further change in the outputs will occur while the clock remains high or on the high-to-Iow transition of the clock.
The third line of the table represents synchronous parallel loading of the register and says that if 51 and 50 are both high
then. without regardto the serial input. the data entered atAwili be at output OA, data entered at Bwill be at OS. and so forth.
following a low-to-high clock transition.
The fourth and fifth lines represent the loading of high- and low-level data. respectively. from the shift-right serial input and
the shifting of previously entered data one bit; data previously at OA is now at OS. the previous levels of Os and Oc are now at
Oc and OD respectively. and the data previously at OD is no longer in the register. This entry of serial data and shift takes
place on the low-to-high transition of the clock when 51 is low and 50 is high and the levels at inputs A through D have no
effect.
The sixth and seventh lines represent the loading of high- and low-level data. respectively. from the shift-left serial input and
the shifting of previously entered data one bit; data previously at Os is now at 0A. the previous levels of Oc and OD are nowat
Os and OC. respectively. and the data previously at OA is no longer in the register. This entry of serial data and shift takes
place on the low-to-high transition of the clock when 51 is high and SO is low and the levels at inputs A through D have no
effect.
The last line shows that as long as both mode inputs are low. no other input has any effect and. as in the second line. the
outputs maintain the levels they assumed before the steady-state combination of clear high and both mode inputs low was
established.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFice BOX 225012 • DALLAS. TeXAS 75265

1-13

PARAMETER MEASUREMENT INFORMATION

TOTEM POLE OUTPUTS

3-STATE OUTPUTS

L

FROM OUTPUT
UNDER TEST

..

~

TVCC
S1

TEST
POINT

j)
TEST
POINT
RL
FROM OUTPUT _ _--4-._-""'""'rv--e
UNDER TEST

ICL

l· .

CLI
\

PARAMETER
t PLH or\ Standard outputs

/ tPHL \ High-current outputs §

\

co

\

co

\ CLt*

I

\
\

\

50pF
150pF

I

tCl includes probe and test fixture capacitance.

LOAD CIRCUIT

tThese values apply only when alternative values (Rl =2 kn. Cl = t 5 pF) are
not specified in the column heading in switching characteristics.
§High-current outputs are indicated by the t> in the logic symbol.

PARAMETER
tpZH
tpZL
tpHZ
tpLZ
tpLH or tpHL

RLf

CLTf

1 kO

5 pF

1 kO

50pF

co

75 pF

S,
OPEN
CLOSED
OPEN
CLOSED
CLOSED

S2
CLOSED
OPEN
CLOSED
OPEN
OPEN

tCl includes probe and test fixture capacitance.
fThese values apply only when alternative values (Rl = 667n. Cl = 45 pFI
are not spacified in the column heading in switching characteristics.

TIMING~VCC
INPUT -----4'_5~~
OV
!-"tlu.r-- th -,

HIGH-LEVEL
PULSE

DATA
INPUT

LOW-LEVEL
PULSE

____

~I""---VCC
50%
50%
OV

VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES·

~----VCC

---IT

~O%

VOLTAGE WAVEFORMS
PULSE WIDTHS·

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DAllAS. TEXAS 75285

0 V

--....r-::",--'..v~---OV

• In the examples above. the phase relationships between inputs and outputs have been chosen arbitrarily.
All input pulses are supplied by generators having the following characteristics: PRR ::; 1 MHz. zoul'" 50n. tr = 6 ns. tf = 6 ns.

1-14

~

i--tw---l

VCC

PARAMETER MEASUREMENT INFORMATION

INPUT ~r6-0-%------------"-\1\.::---------- :C:
l-4--tPHL~

!4--tPLH--+j

frS-O%-------+-!-----"-\\~~,,---VOH

j

IN-PHASE
OUTPUT

I

1

I+-- tPHL--+j

!+--tPLH-----I

--------~

f

I

I

\L

OUT-Of-PHASE
OUTPUT

VOL

I

,60%

VOH

~~___

VOL

VOLTAGE WAVEfORMS
PROPAGATION DELAY TIMES·

•

Vee
OUTPUT CONTROL
(Low-level enabling) \

WAVEfORM 1
(See Note 1)

WAVEfORM 2
(Sea Note 11

/60%
: ""_ _ _ _ _ _ _ _ _ _ _ _....J.:..j _ _ _ _ _ _ _ _ _ _ _ _ _ _ 0 V

1

r+-- tpZL ---+t

I

1 1 - - - Vee

1

i.

\60%

t+-- tpLZ ----1
I

:

I

1

t+--tPZH~

:

I
,.
60%
_ _ _ _ _ _ _--J.

I
I
I

y,::

- vee

- - - - - - VOL

t

- - - - - - VOH

90 %

J'--- - - - - -0 v

~tPHZ-..l

VOLTAGE WAVEfORMS
ENABLE AND DISABLE TIMES. THREE-STATE OUTPUTS·

Note: 1. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output wilh internal conditions such that the output is high except when disabled by the output control.
• In the examples above. the phase relationships between inputs and outputs have been chosen arbitrarily.
All input pulses are supplied by generators having the following characteristics: PRR S 1 MHz. Zout ... 50

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265

n. tr = 6 ns. tf = 6 ns.

1-15

THIS PAGE
INTENTIONALLY LEFT BLANK

1-16

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

..

Ratings and

I

Characteristics

2-1

ATTENTION
These devices contain circuits to protect the inputs and outputs against damage due to
high static voltages or electrostatic fields; however, it is advised that precautions be
taken to avoid application of any voltage higher than maximum-rated voltages to these
high-impedance circuits.
Unused inputs must always be connected to an appropriate logic voltage level,
preferably either Vee or ground.

Copyright ©1982 by Texas Instruments Incorporated

2-2

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

HIGH-SPEED
CMOS LOGIC

TABLE I
SPECIFICATIONS FOR SSI CIRCUITS
02684. DECEM8ER 1982

absolute maximum ratings over operating free-air temperature ranget
Supply voltage range. VCC ....................................•.................•................ -0.5 to 7 V
Input diode current. ',K(V, < -0.5 V or V, > VCC + 0.5 V) ............................................... ±20 mA
Output diode current. 'OK(VO < -0.5 V or Vo > VCC + 0.5 V) ....•..................................... ±20 mA
Continuous output current (-0.5 V < Vo < VCC + 0.5 V) .....................•••......••••.....•.•..... ±25 mA
Continuous current through VCC or GND pins ............................................•........... ±50 mA
Lead temperature 1.6 mm (1/16 in) from case: J package for 60 seconds •.....•................ , ......... 300°C
N package for 10 seconds ................................. 2600C
Storage temperature range ...•......•................•..................................... -65°C to 150°C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

recommended operating conditions
MIN
2
3.15
3.50
3.85
0
0
0
-0.5
-0.5

Vee Supply voltage
Vee=4.5 V
Vee=5 V
Vee = 5.5 V
Vec=4.5 V

VIH High-level input voltage

VIL Low-level input voltage

Vee=5 V
Vee = 5.5 V

VI Input voltage
Vo Output voltage
IOH High-level output current
IOL Low-level output current
Input transition (rise and fall) times
tt
(except Schmitt-trigger inputs)
TA

Operating free-air temperature

SN64HC'
NOM
5

MAX
6

0.9
1.0

1.1
Vee+ 0 .5
Vee+ 0 .5
-4

MIN
2
3.15
3.50
3.85
0
0
0
-0.5
-0.5

SN74HC'
NOM
5

MAX
6

UNIT
V
V

0.9
1.0
1.1
Vcc+ 0 .5'
Vee+ 0 .5

-4

...

V
V
V
mA
mA

3.4

4

0

500

0

500

ns

-55

125

-40

85

°e

electrical characteristics, Vee =5 V ± 10%,
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

VOH

TEST CONDITIONS

MIN

VI = VIH or VIL. Vee = 4.5 V.
IOH= -4mA

3.86

VI " VIH or VIL.
IOH= -200SJA

Vee -0.2

Vee

VI " VIH or VIL.
IOH= -20SJA

Vee -0.1

Vee

VI" VIH or VIL
VOL
VT+ -VT-~
II
lee
ej

TA = 25°C
TYp:I:

IIOL = 3.4 mA
POL =4 mA

VI = VIH or VIL.
IOL =20SJA

0
0.4

MAX

3

SN74HC'
MIN
MAX

3.56

3.70

Vee -0.2

Vee-0 .2

Vee- 0 .1
0.4

0.1

0.1

V

0.4

0.4
±O.l
2
10

UNIT

Vee -0.1

0.27
0.32

1

VI" Vee orO V
VI" Vee orO V.IO" 0

SN54HC'
MIN
MAX

V

0.4
±1
40
10

V

0.1

±1
20
10

SJA
SJA
pF

tAli tYPIcal values are at VCC = 5 V.
"-his parameter applies only to Schmitt-trigger inputs.

switching characteristics
See individual circuit pages.
Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

2-3

TABLE II
SPECIFICATIONS FOR DUAL AND
QUAD FLIP-FLOPS AND LATCHES

HIGH-SPEED
CMOS LOGIC

02684. DECEM8ER 1982

absolute maximum ratings over operating free-air temperature ranget
Supply voltage range. VCC .....•..............................•...............•.................. -0.5 to 7 V
Input diode current. IIKeVI < -0.5 V or VI > VCC + 0.5 V) ......•........................•....•.......... ±20 mA
Output diode current. IOK.cvO < -0.5 V or Vo > VCC + 0.5 V) ., .............•..•.....•................. ±20 mA
Continuous output current (-0.5 V < Vo < VCC + 0.5 V) .•..........................•.....•............ ±25 mA
Continuous current through VCC or GND pins ..•....•...................•............................ ±50 mA
Lead temperature 1.6 mm (1/16 in) from case: J package for 60 seconds .......•......................... 300°C
N package for 10 seconds ..•...•.....•.•............•..... 260°C
Storage temperature range ....................... '......•.....•..•..........•.....•......... -65°C to 150°C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

recommended operating conditions
SN54HC'

II

MIN

2
3.15
3.50
3.85
0
0
0
-0.5
-0.5

Vee Supply voltage
VIH High-level input voltage

VIL Low-level input voltage

Vee = 4.5 V
Vee = 5 V
Vee=5.5V
Vee = 4.5 V
Vee= 5 V
Vee = 5.5 V

VI Input voltage
Vo Output voltage
10H High-level output current
10L Low-level output current
Input transition (rise and fall) times
tt
TA Operating free-air temperature

NOM
5

MAX
6

0.9
1.0
1.1
Vee+ 0 .5
Vee + 0.5
-4
3.4
500
125

0
-55

MIN
2
3.15
3.50
3.85
0
0
0
-0.5
-0.5

SN74HC'
NOM
5

MAX
6

UNIT
V
V

0.9
1.0
1.1
Vee +0.5
Vee+ 0 .5
-4
4
500
85

0
-40

V
V
V
mA
mA
ns
°e

=

electrical characteristics, Vee 5 V ± 10%,
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

TEST CONDITIONS
VI = VIH or VIL. Vee = 4.5 V.
IOH=-4mA

VOH

TA = 25°C
TYpt

MIN
3.86

VI = VIH or VIL.
10H= -2oopA

Vee -0.2

Vee

VI = VIH or VIL.
10H= -20pA

Vee -0.1

Vee

II
ICC

POL=4 mA
VI = VIH or VIL.
10L = 20pA
VI = Vee orO V
VI = Vee or 0 V. 10 = 0

c.t

SN54HC'
MIN
MAX

SN74HC'
MIN
MAX

3.56

3.70

Vee -0.2

Vee -0.2

Vee- O.1

UNIT

V

Vee -0.1

0.27
0.32

0.4

0

0.1

0.1

0.1

±1
80
10

±1
40

3

±0.1
4
10

VI = VIH or VIL POL = 3.4 mA .
VOL

MAX

0.4

10

V

pA
pA
pF

tAli typical values are at VCC = 5 V.

switching characteristics
See individual circuit pages.
Copyright ©1982 by Texas Instruments Incorporal

2-4

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TABLE III
SPECIFICATIONS FOR CIRCUITS
WITH HIGH-CURRENT OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DEeEM8ER 1982

absolute maximum ratings over operating free-air temperature ranget
Supply voltage range, VCC ..•.•..............................•........•.....................•.... -0.5 to 7 V
Input diode current, IIK(VI < -0.5 V or VI > VCC + 0.5 V) .................•.....................•....... ±20 mA
Output diode current, IOK(VO < -0.5 V or Vo > VCC + 0.5 V) ..........................•....•.......... ±20 mA
Continuous output current (-0.5 V < Vo < VCC + 0.5 V) ...................................•........... ±25 mA
Continuous current through VCC or GND pins ..........................................•.......•..... ±50 mA
Lead temperature 1,6 mm (1/16 in) from case: J package for 60 seconds ...........•......•... '," .......• 300 o C
N package for 10 seconds ................................• 260 0 C
Storage temperature range ................................................................. -65°C to 150°C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

recommended operating conditions
SN74HC'

SN64HC'
MIN

NOM

MAX

MIN

NOM

MAX

2

5

6

2

5

6

Vee Supply voltage
V,H High·level input voltage

VIL Low·level input voltage
VI

Vee=4.5 V

3.15

3.15

Vee =5 V

3.50

3.50

Vee =5.5 V
Vee =4.5 V

3.85
0

0.9

3.85
0

=5 V
=5.5 V

0

1.0

0

1.0

0
-0.5

1.1

0
-0.5

1.1

Vee
Vee

Input voltage
High·current outputs

IOH High·level output current

Vee + 0.5
-6

11

Standard outputs
High·current outputs"

IOL Low·level output current
tt
TA

Vee + 0.5

-0.5

Vo Output voltage

Standard outputs
0
-55

0.9

Vee+ 0 .5
Vee + 0.5
-6

-0.5

-3.4

-4

5.1

6
4

Operating Iree·air temperature

500

0
-40

125

V
V

3.4

Input transition (rise and lall) times

UNIT

..

V
V
V
mA
mA

500

ns

85

°e

,High-current outputs are indicated by the t> in the logic symbol. AlI3-state outputs are high-current outputs.

=

electrical characteristics, Vee 5 V ± 10%,
over recommended operating free-air temperature range (unless otherwise noted)
TA
PARAMETER

TEST CONDITIONS
VI =VIH or VIL. Vee
IOH =-4mA

VOH

MIN

=4.5 V.

VI =VIH or VIL.
10H =-200pA
VI =VIH or VIL.
10H =-20 pA
VI =VIH or VIL
10L =max rec.

VOL

10Z§
II
ICC
ej

I
I

=25°C
TYpt

3.86
Vee -0.2

Vee

Vee -0.1

Vee

(except transceiver 1/0 pins)

MAX

0

3

MIN

3.56

3.70

Vee -0.2

Vee-0 .2

MAX

UNIT

V

Vee-0 .1

Vee -0.1
0.4

0.4

0.32

74He'

=VIH or VIL.
10L =20pA
Vo =Vee orO V. VI =VIH orVIL
VI =Vee orO V
VI =Vee or 0 V. 10 =0
VI

MIN

0.27

54He'

SN74HC'

SN64HC'
MAX

V

0.1

0.1

0.1

±0.5
±0.1

±5
±1

±5
±1

pA
pA

8
10

160

80
10

pA

10

pF

tAli typical values are at Vee = 5 V.
§This parameter. 10Z. the high impedance-state output current. applies only lor three-state outputs and transceiver 1/0 pins.

switching characteristics
See individual circuit pages.
Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265

2-5

HIGH-SPEED
CMOS LOGIC

TABLE IV
SPECIFICATIONS FOR MSI CIRCUITS
02684. DECEM8ER 1982

absolute maximum ratings over operating free-air temperature ranget
Supply voltage range. VCC ............•.....•...•.....•....•..•....•..........•.•••.............. -0.5 to 7 V
Input diode current. IIK(VI < -0.5 V or VI> VCC + 0.5 VI .•••..•.•..•..•..................•........•..•• ±20 mA
Output diode current. IOK(VO < -0.5 V or Vo > VCC + 0.5 VI ...•..........•.....................••...• ±20 mA
Continuous output current (-0.5 V < Vo < VCC + 0.5 VI •....•......•.. : •..•.....••.•.•..•.....•.•.•... ±25 mA
Continuous current through Vec or GND pins •...•••.•••...••....•................•...••.•..•....•..• ±50 mA
Lead temperature 1.6 mm (1/16 in)from case: J package for 60 seconds ................................. 300°C
N package for 10 seconds ...........••..•••.....•.•.••••.. 260°C
Storage temperature range ..........•..•..•.........•..•..•.•.•• , ..•...........••..•....... -65°C to 150°C
tStresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

..

recommended operating conditions

MIN
2
3.15
3.50
3.85
0
0
0
-0.5
-0.5

Vee Supply voltage
Vee=4.5V
Vee = 5 V
Vee = 5.5 V
Vee=4.5V
Vee = 5 V
Vee = 5.5 V

VIH High-level input voltage

VIL Low-level input voltage
VI
Vo
IOH
IOL

Input voltage

Output voltage
High-level output current
Low-level output current
Input transition (rise and fall) times
tt
(except Schmitt-trigger inputs)
TA Operating free-air temperature

SN54HC'
NOM
5

MAX
6

0.9
1.0
1.1
Vee + 0.5
Vee + 0.5
-4

MIN
2
3.15
3.50
3.85
0
0
0
-0.5
-0.5

SN74HC'
NOM
5

MAX
6

UNIT
V
V

0.9
1.0
1.1
Vee+ 0 .5
Vee +0.5
-4

3.4

4

V
V
V
mA
mA

0

500

0

500

ns

-55

125

-40

85

°e

=

electrical characteristics. Vee 5 V ± 10%,
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER

VOH

TEST CONDITIONS

MIN

VI = VIH or VIL. Vee = 4.5 V.
IOH=-4mA

3.86

VI = VIH or VIL.
IOH = -200IlA
VI = VIH or VIL.
IOH= -201lA
VI = VIH or VIL

VOL

ICC
ei

Vee- O.2

Vee

Vee -0.1

Vee

IIOL = 3.4 mA
IIOL=4mA

VI = VIH or VIL.
IOL = 20llA

0
0.4

VT+-VT-lI
II

TA=25°C
TYP:\:

SN74HC'
MIN
MAX

3.56

3.70

Vee- 0 .2

Vee -0.2

Vee- 0 .1
0.4

0.1

0.1

3

V

0.4

0.4
±0.1
8
10

UNIT

Vee -0.1

0.27
0.32

1

VI=VeeOrOV.lo=O
VI=Vee OrOV

tAli typical values are at VCC = 5 V.

SN54HC'
MAX
MIN

MAX

0.4
±1
160
10

V

0.1

±1
80
10

V
IlA
IlA
pF

,,-his parameter applies only to Schmitt-trigger inputs.

switching characteristics
See individual circuit pages.
Copyright ©1982 by Texas Instruments Incorporated

2-6

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

Descriptive
Information

III

3-1

HIGH-SPEED
CMOS lOGIC

~UADRUPLE

TYPES SN54HCOO, SN74HCOO
2-INPUT POSITIVE-NAND GATES
02684. DECEMBER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
• Dependable Texas Instruments Quality
and Reliability

SN54HCOO ... J PACKAGE
SN74HCOO ... J OR N PACKAGE
(TOP VIEW)

description
VCC

These devices contain four independent 2-input
NAND gates. They perform the boolean functions
y =A'B or Y =A + B in positive logic.

18
1Y
28
2Y

The SN54HCOO is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HCOO is characterized for operation from -40°C to 85°C.

GND

FUNCTION TABLE (each gate)

..

INPUTS

SN54HCOO ... FH OR FK PACKAGE
SN74HCOO ... FH OR FN PACKAGE
(TOP VIEW)

OUTPUT
V

A

B

H

H

L

L

X

H

X

L

H

lB
2A
2B
3A
3B
4A
4B

U

aJ«U

>

3 2

2019

Z

UaJ
qo

1Y

logic symbol
lA

48
4A
4Y
38
3A
3Y

NC
(11

NC

2A

&

(2)

NC

(4)

28

14
9 1011 1213

(5)
(9)

(10)
NC -

(12)

No internal connection

(13)

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics.
See Table I, page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC= 5 V,
CL=15pF.
PARAMETER

tpLH

FROM

TO

(INPUT)

(OUTPUT)

Aor 8

Y

RL = 2 kO.

VCC = 4.5 V to 5.5 V,
CL = 50 pF
UNIT

SN54HCOO SN74HCOO
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
ns

tpHL
Power dissipation capacitance per gate

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-2

This document contains information on a
product under development. Texas Instruments reserves the right to change or dis·
continue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC02, SN74HC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02684. DECEMBER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC02 ... J PACKAGE
SN74HC02 ... J OR N PACKAGE
(TOP VIEW)

• Dependable Texas Instruments Quality
and Reliability

VCC
4Y

48
description

4A

3Y
38
3A

These devices contain four independent 2-input
NOR gates. They perform the boolean functions
y = A + B or Y = A'S in positive logic.
The SN54HC02 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC02 is characterized for operation from -40°C to 85°C.

SN54HC02 ... FH OR FK PACKAGE
SN74HC02 ... FH OR FN PACKAGE
(TOP VIEW)
U

-uu>-

z>(O

6Y

2A
NC

NC
5A
NC

2Y
NC
3A

5Y

logic symbol
lA
2A

NC -

3A

No internal connection

4A
5A
6A

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I, page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

A

Y

tpLH
tPHL

VCC==5V.
VCC =4.5 V to 5.5 V.
CL=15pF.
CL = 50 pF
RL = 2 kO
SN54HC04 SN74HC04
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

Power dissipation capacitance per inverter

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-4

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC08, SN74HC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES

HIGH-SPEED
CMOS lOGIC

02684. DECEMBER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC08 ... J PACKAGE
SN74HC08 ... J OR N PACKAGE
(TOP VIEW)

description
These devices contain four independent 2-input
AND gates. Tl'ey_perform the boolean functions
Y = A·B or Y = A + B in positive logic.
The SN54HC08 is characte.rized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC08 is characterized for operation from -40 o to 85°C.

e

SN54HC08 ... FH OR FK PACKAGE
SN74HC08 ... FH OR FN PACKAGE
(TOP VIEW)
CD

2A

3A
3B
4A
4B

U

U
U CD

4A

B

Y

lY

H

H

H

NC

NC

L

X

L

2A

4Y

X

L

L

NC

Ne

28

38

(1)

..

OUTPUT

A

logic symbol

2B

<{

~~z><:t

(each gate)

INPUTS

lA

48
4A
4Y
38
3A
3Y

GND

FUNCTION TABLE

lB

Vee

1A
18
1Y
2A
28
2Y

• Dependable Texas Instruments Quality
and Reliability

&

(2)

(3) lY

(4)

NC -

(6) 2Y

(5)

No internal connection

(9)

(8) 3Y

(10)
(12)

(11) 4Y

(13)

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL

FROM
(INPUT)

TO
(OUTPUT)

AorB

y

VCC= 5 V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
CL = 50 pF
RL = 2 kn.
SN54HC08 SN74HC08
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

Power dissipation capacitance per gate

No load. TA

=25°C

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1·14.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-5

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC10, SN74HC10
TRIPLE 3-INPUT POSITIVE-NAND GATES
02684. DECEMBER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
• Dependable Texas Instruments Quality
and Reliability

SN54HC10 ... J PACKAGE
SN74HC10 ... J OR N PACKAGE
(TOP VIEW)

VCC
lC

description

1Y
3C
3B
3A

These devices contain three independent 3-input
NAND gates. They perform the boolean functions
Y = A·B·C or Y = A+ B+ C in positive logic.

-..._ _......r- 3Y

The.SN54HC10 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC1O is characterized for operation from -40°C to 85°C.

SN54HC10 ... FH OR FK PACKAGE
SN74HC10 ... FH OR FN PACKAGE
(TOP VIEW)

FUNCTION TABLE (each gate)

..

INPUTS

OUTPUT
y

A

B

H

H

C
H

L

X

X

H

X

L

X

X

X

L

H
H

u

CDctUUU
Z> ...

L

3 2

logic symbol
lA
lB
lC
2A
2B
2C
3A
3B
3C

(11

2019

2A
NC
28

&

lY

NC
3C

NC

NC

2C

38

(21
(131

>-ou>-ct
NZZMM

(31

t:l

(41

NC -

No internal connection

(51
(9)

(101
(111

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tpLH
tpHL

A.B.orC

Y

VCC=5V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
CL =50 pF
RL = 2 kn.
SN54HC10 SN74HC10
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

Power dissipation capacitance per gate

pF typ

NOTE t: For load circuit and voltage waveforms. see page 1 ·14.
PRODUCT PREVIEW

3-6

•

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change o.r dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED

POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265

TYPES SN54HCll, SN74HCll
TRIPLE 3-INPUT POSITIVE-AND GATES

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC11 ... J PACKAGE
SN74HC11 ... J OR N PACKAGE
(TOP VIEW)

1A
18
2A
28
2C
2Y

description
These devices contain three independent 3-input
AND gates. They perform the boolean functions
Y =A'B'C or Y =A + 8 + C in positive logic.
The SN54HC11 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC11 is characterized for operation from -40°C to 85°C.

VCC
1C
1Y

3C
38
3A
'"""""L_ _---I-

3Y

SN54HC11 ... FH OR FK PACKAGE
SN74HC11 ... FH OR FN PACKAGE
(TOP VIEW)

FUNCTION TABLE (each gate)

A

B

C

OUTPUT
y

H

H

H

H
L

INPUTS

L

X

X

X

L

X

L

X

X

L

L

logic symbol
lA
lB
lC
2A
2B
2C
3A
3B
3C

..

1Y

NC
3C
NC
38

>-ou>- co

V

L
H

2A

6Y
NC

NC
2Y

5A
NC
5Y

NC

logic symbol

3A

1A

c u >>M

2A

Z

Z

<{
"N

..

1 2019

NC
NC

4

2C

5

NC

lC

6

NC

7

NC
NC

10

8

28
9

1B

-«
2

Y

logic symbol
1A

2Y

10 11 1213

>-OU>-«
(1)

ZZNN
c..?

&

(2)

NC -

1Y

No internal connection

1C
10
2A
2B
2Y

2C
20

(13)

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL

FROM
(INPUT)

TO
(OUTPUT)

A. B. C. or 0

Y

VCC=5 V.
CL=15pF.
RL = 2 kO.

VCC = 4.5 V to 5.5 V.
CL = 50 pF
UNIT

SN54HC20 SN74HC20
.TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
ns

Power dissipation capacitance per gate

No load. TA

= 25°C

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
rhis document contains information on a
lroduct under development. Texas Instrunents reserves the right to change or dis:ontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-9

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC21, SN74HC21
DUAL 4-INPUT POSITIVE-AND GATES
02684. DECEMBER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC21 ... JPACKAGE
SN74HC21 ... J OR N PACKAGE
(TOP VIEW)

1A
18
NC
1C
1D

• Dependable Texas Instruments Quality
and Reliability
description
These devices contain two independent 4-input AND
gates. They perform the boolean functions Y = A·a·C·D
or Y = A + 8 + C + D in positive logic.
The SN54HC21 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC21 is characterized for operation from -40°C to 85°C.

VCC
2D
2C
NC
28
2A
2Y

SN54HC21 ... FH OR FK PACKAGE
SN74HC21 ... FH OR FN PACKAGE
(TOP VIEW) .
U
CllN

OUTPUT

INPUTS

..

A
H

B
H

C
H

0
H
X

1 2019

y

NC
NC
1C
NC

H

L

X

X

X

L

X

X

X

X

L

X

L
L
L

X

X

X

L

L

2C
5

Nr.

6

NC
NC

7

1D

28

8
9 10 11 1213

logic symbol
lA

>-OU>-.,....

logic symbol
lA

GND

OUTPUT

INPUTS
A

VCC
1C
1Y
3C
38
3A
3Y

1A
18
2A
28
2C
2Y

2A

1Y

NC

NC

28

3C

NC

NC

2C

38

~1

2A~
2B

(4)

2C

(5)

3A

(9)

3B

(10)

3C

(11)

NC -

No internal connection

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tPLH
tPHL

A. B,orC

Y

Vce= 5 V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
CL = 50 pF
RL = 2 kn.
SN54HC27 SN74HC27
TA = 25°C
TA = 25°e
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

Power dissipation capacitance per gate

pF typ

NOTE1: For load circuit and voltage waveforms. see page 1 -14.
Copyright &)1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product witho'ut notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265

3-11

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC30, SN74HC30
8-INPUT POSITIVE-NAND GATES
02684, DECEM8ER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC30 ... J PACKAGE
SN74HC30 . , , J OR N PACKAGE
(TOP VIEW)

• Dependable Texas Instruments Quality
and Reliability

A

VCC
NC

B

C
D

description

H

G
NC
NC

E
F

These devices contain a single B-input NAND gate
and perform the following boolean functions in
positive logic:

y

GND

Y =A·B·C·D·E·F·G·H
or

SN54HC30 ... FH OR FK PACKAGE
SN74HC30 ... FH OR FN PACKAGE
(TOP VIEW)

Y=A+B+C+D+E+F+G+H
The SN54HC30 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC30 is characterized for operation from -40°C to 85°C.

a

u

u

UU

cnZ

3 2

2019

C
NC
D
NC

4

H

5
6

E

8

NC
G
NC
NC

logic symbol

9 1011 1213
(11

A

&

ou >- u
Z
ZZ

(2)

~

(3)

NC -

(4)

0

(8)

No internal connection

y

(51

FUNCTION TABLE

(61

G
H

(11)

INPUTS A THRU H

(12)

Pin numbers shown are for J and N packages.

OUTPUT

Y

All inputs H

l

One or more inputs l

H

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I, page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH

FROM
(INPUT)

TO
(OUTPUT)

Athru H

y

VCC=5V,
Cl = 15 pF,
RL = 2 kCl,

VCC = 4.5 V to 5.5 V,
Cl = 50 pF
UNIT

SN54HC30 SN74HC30
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
ns

tPHL
Power dissipation capacitance per gate

No load. TA

= 25°C

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-12

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
02684. DECEM8ER 1982

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•

SN54HC32 ... J PACKAGE
SN74HC32 ... J OR N PACKAGE
(TOPVIEW) .

1A
1B
1Y
2A
28
2Y

Dependable Texas Instruments Quality
and Reliability

description
These devices contain four independent 2-input OR
gates. They perform the boolean functions Y = A + B
or Y = A'S in positive logic.
The SN54HC32 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC32 is characterized for operation from -40°C to 85°C.

SN54HC32 ... FH OR FK PACKAGE
SN74HC32 ... FH OR FN PACKAGE
(TOP VIEW)
(,)

co«(') (')co

lB

..

Z><:t

OUTPUT
Y
H
H
L

3 2

2019

4A

lY

NC

NC

2A

4Y

NC

NC

28

38

I

9 1011 1213

logic symbol
lA

4B
4A
4Y
38
3A
3Y

GND

FUNCTION TABLE
(each gatel
INPUTS
A
B
H
X
X
H
L
L

VCC

(1)

;;'1

(2)

(3) lY

NC -

2A

No internal connection

(6) 2Y

28
Ia) 3Y
3B
4A
4B

(11) 4V

(13)

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC=5V.
CL=15pF.

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tPLH
tPHL

AorS

Y

VCC = 4.5 V to 5.5 V.
CL = 50 pF
RL = 2 kCl.
SN54HC32 SN74HC32
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

Power dissipation capacitance per gate

No load. TA = 25°C

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1-14.
PRODUCT PREVIEW
This document contains information on a
product under development, Texas Instruments reserves the right to change or discontinue this product without no¥il:e.

Copyright (&i1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-13

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC36, SN74HC36
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC36 .. _J PACKAGE
SN74HC36 . __ J OR N PACKAGE
(TOP VIEW)
VCC
4B
4A
4Y

1B
1Y

description

The SN54HC36 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC36 is characterized for operation from -40°C to 85°C.

3B
3A
3Y

2B
2Y
GND

These devices contain four independent 2-input
NOR gates. They perform the boolean functions
y =A + B or Y =A-S in positive logic.

SN54HC36 .. _FH OR FK PACKAGE
SN74HC36 . __ FH OR FN PACKAGE
(TOP VIEW)

m<
.... uz >em
..,.

logic symbol

•

4A
NC
4Y
NC
3B

1A
1B

2A
2B

3A
3B
4A

NC -

No internal connection

4B

Pin numbers shown are for J and N packages.

FUNCTION TABLE (each gata)
INPUTS
A
H
X
l

B
X
H
l

OUTPUT
V
L

l
H

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I, page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tplH
tpHl

FROM
(INPUT)

TO
(OUTPUT)

AorB

Y

Cpd

VCC=5V,
Cl = 16 pF,
Rl = 2 kn

VCC = 4.5 V to 5.5 V,
Cl = 60 pF
UNIT

. TA = 26°C
SN54HC36 SN74HC36
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
ns

Power dissipation capacitance per gate

No load. TA

=25°C

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1.14.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-14

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC42, SN74HC42
4-UNE TO 10-UNE DECODERS (1-of-1 0)

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

• Full Decoding of Input Logic

SN54HC42 ... J PACKAGE
SN74HC42 ... J OR N PACKAGE
(TOPVIEWI

• All Outputs Are Off for Invalid
BCD Conditions

0
1
2
3
4
5
6

• Also for Application as 3-Line to 8-Line Decoders
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and' Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability
description

VCC
A

B
C

D
9

8

GND

These monolithic decimal decoders consist of eight
inverters and ten four-input NAND gates. The inverters are connected in pairs to make BCD input
data available for decoding by the NAND gates. Full
decoding of valid input logic ensures that all inputs
remain off for all invalid input conditions.

7

SN54HC42 ... FH OR FK PACKAGE
SN74HC42 ... FH OR FN PACKAGE
(TOPVIEWI

The SN54HC42 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC42 is characterized for operation from -40°C to 85°C.

2

B

3

C
NC

NC
4
5

FUNCTION TABLE
NO.

0

0
1

L

2

L
L

3
4
5
6

7
8
9

0

:::i

~
~

L

L

.L
L
L
H
H
H
H
H
H
H
H

INPUTS
C B
L L
L L
L H
L H
H L
H L
H H
H H
L L
L L
L H
L H
H L
H L
H H
H H

0

1

L
H

H

H

H

A
L
H
L
H
L
H
L
H
L

H

H

H

H

H

H

H

H

H

L
H
L
H
L
H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

OUTPUTS
3 4 5 6
H H H H
H H H H
H H H H
L H H H
H L H H
H H L H
H H H L
H H H H
H H H H
H H H H
H !"i H H
H H H H
H H H H
H H H H
H H H H
H H H H

D

..

9

7
H
H
H
H

8

9

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L
H

H

H

L

H

H

H

L

H

H

H

A

(15)

H

H

H

B

(14)

H

H

H

C

(13)

H

H

H

(12)

H

H

H

o

H

H

H

to

I

0 u r-- co
z z

(!)

NC -

No internal connection

logic symbol
BCOIDEC

Pin numbers shown are tor J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.

PRODUCT PREVIEW

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-15

TYPES SN54HC42, SN74HC42
4-L1NE TO 10-L1NE DECODERS (1-of-1 0)
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpHL
tPLH

FROM
(INPUT)

TO
(OUTPUT)

A.B.Cor 0

o thru 9

VCC=5V.
CL = 15 pF.

VCC=4.5 Vto5.5 V.
CL = 50 pF

RL =2 kn.
SN54HC42 SN74HC42
TA = 25°C
. TA=25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

ns

Power dissipation capacitance

No load, TA = 25°C

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

...

3-16

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pFtvp

TYPES SN54HC51, SN74HC51
AND-DR-INVERT GATES

HIGH-SPEED
CMOS LOGIC

02684. DECEM8ER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC51 •.. J PACKAGE
SN74HC61 .•• J OR N PACKAGE
(TOP VIEW)

description
The 'HC51 provides 2-wide, 2-input, and 2-wlde, 3input AND-OR-INVERT gates. The device performs
the following boolean functions:

2Y =(2A'2B') + (2C'2D)

INPUTS
H

X

28
NC

18

2C

1F

NC
20

NC
1E

1F

H
H
X
X
X
X
H
H
Any other combination

X

L

H

L
H

X

2C

X
X
H
Any other combination

II

>cu ~e

NZZ
t!)

NC - No internal connection

logic symbol
IB

INPUTS
2B
H

NC

1V

IA

H

1E
10

OUTPUT
1E

2A

1F

20
2Y

« u uuu
>.-

FUNCTION TABLES

10

18

2C

N.-Z

The SN54HC51 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC51 is characterized for operation from -40°C to 85°C.

1C

28

SN54HC51 ..• FH OR FK PACKAGE
SN74HC51 ..• FH OR FN PACKAGE
(TOP VIEW)

=

1B

VCC
1C

GNO --....._ _-r-1Y

1Y (1 A'1 B·1 C) + (10'1 E·1 F)

1A

1A
2A

OUTPUT

111

&

;'1

1121

IC

20
X

2V
L

IE

H

L
H

2A

10

IF

2B
&

2C
20

151

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 V.
CL = 15 pF.
RL = 2 kO.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC51 SN74HC51
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH

Any

tPHL

Y

ns

Power diSSipation capacitance per AOI gate
NOTE 1: For load circuit and voltage waveforms. see page 1·14.

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instru·
menta reserves the right to change or discontinue this product without notice.

pF typ

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265

3-17

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC73, SN74HC73
DUAL J-K FLIP-FLOPS WITH CLEAR
02684. DECEM8ER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC73 ... J PACKAGE
SN74HC73 ... J OR N PACKAGE
(TOPVIEWI

1ClK
lClR
1K

Vec

description

..

2ClK
2ClR
2J

These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the clear
input resets the outputs regardless of the levels of
the other inputs. When clear is inactive (high). data
at the J and K inputs meeting the setup time
requirements are transferred to the outputs on the
negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold time interval. data at the J and K inputs may
be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high .

lJ
10
10
GND

2K
20
2Q

For chip carrier information.
contact the factory.

The SN54HC73 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC73 is characterized for operation from -40°C to 85°C.

logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
OUTPUTS

INPUTS
CLR

CLK

J

K

Q

L

X

Q
H

I
I

00

00

H

X
l
l

L

H
H

X
l

H

H

I

l

H

L

L
H

H

I

H

H

H

H

X

X

TOGGLE

00

00
Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table II. page 2-4.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-18

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC73, SN74HC73
DUAL J-K FLIP-FLOPS WITH CLEAR
timing requirements (supplement to recommended operating conditions)
SN54HC73
MIN
fclock

Clock frequency

tw

Pulse duration

Setup time before ClKI

tsu

NOM

SN74HC73
MAX

MIN

NOM

UNIT

MAX

MHz
ClK high or low

ns

ClR low
High-level data
low-level data

ns

ClR in;lctive
Hold time. data after ClKI

th

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 V.
CL= 15 pF.
RL = 2

VCC = 4.5 V to 5.5 V.
CL = 50 pF

kn.

UNIT

SN54HC73 SN74HC73
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
f max
tplH
tpHL
tPlH
tpHL

MHz
ClK
ClR

aorO

ns

a

II

ns

a

Power dissipation capacitance per flip-flop

No load. TA = 25°C

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

3-19

TYPES SN54HC74. SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR AND PRESET

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments auality and Reliability

SN54HC74 ... J PACKAGE
SN74HC74 ... J OR N PACKAGE
(TOPVIEWj
1CLR

VCC
2CLR

10
1CLK

description
These devices contain two independent Ootype positive-edgetriggered flip-flops. A low level at the Preset or Clear inputs sets
or resets the outputs regardless of the levels of the other inputs.
When Preset and Clear are inactive (high) data at the 0 input
meeting the setup time requirements are transferred to the
outputs on the the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to
the rise time of the clock pulse. Following the hold tim~ interval,
data at the 0 input may be changed without affecting the levels
at the outputs.

20

1 PRE

2CLK

10

2PRE

10

20

GNO

20

SN54HC74 ... FH OR FK PACKAGE
SN74HC74 ... FH OR FN PACKAGE
(TOPVIEWj

0: u 10:
~ 1~ ~ ~~
1CLK

II

The SN54HC74 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC74
is characterized for operation from -40°C to 85°C.

20

NC

NC

1PRE

2CLK

NC

NC

10

2PRE

10

FUNCTION TABLE
INPUTS

-

OUTPUTS

X
X
X

H

,

0
X
X
X

L

r

H.
L

H

H

L

H

H

L

X

00

00

PRESET CLEAR
L

H

H

L

L

L

H
H
H

CLOCK

Q

NC -

Cl U
Z Z
t:)

10 0
N

N

No internal connection

Q

H

L

L

H

Ht

Ht

logic symbol

lQ

lClK
10
lClR

tThis configuration is nonstable; that is. it will not persist when
Preset or Clear returns to its inactive (high) level.

2m
2ClK
20

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-4.
PRODUCT PREVIEW
This document contains information on a

3-20

:::~~c:e~~~:sdt~Vee~~:;;~:t~~:~:: ~rs~~~:
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225Ot2 • DALLAS. TeXAS 75265

TYPES SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR AND PRESET
timing requirements (supplement to recommended operating conditions)
SN54HC74
MIN
fclock

NOM

SN74HC74
MAX

MIN

NOM

MAX

UNIT
MHz

Clock frequency
PRE or ClR low

tw

tsu

Pulse duration

ClK high

Setup time

ClK low
Data

ns

before ClKI

PRE or ClR inactive

ns

Hold time. data after ClKI

th

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 V.
Cl = 15 pF.
Rl = 2 kn.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

T A = 25°C
SN54HC74 SN74HC74
T A = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

f max

MHz
PRE or CLR

CorO

ns

ClK

cora

ns

Power dissipation capacitance per flip-flop

..

pF typ

NOTE 1: For load circuit and voltage wavefor.ms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-21

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC75, SN74HC75
4-BIT BISTABLE LATCHES
02684. DECEMBER 1982

SN54HC75 •.. J PACKAGE
SN74HC75 ... J OR N PACKAGE
(TOP VIEW)

• Complementary Q and Q Outputs
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability
description

10
10
20
3C,4C

Vec

These latches are ideally suited for use as temporary
storage for binary information between processing
units and input/output or indicator units. Information present at a data (0) input is transferred to the
output when the enable (C) is high and the a output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was present at the data input at the
time the transition occurred) is retained at the
output until the enable is permitted to go high.

3D
40
40

a

10.
20
20
1C,2C
GNO

30
30
40

a

..

The SN54HC75 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC75 is characterized for operation from -40°C to 85°C.

For chip carrier information,
contact the factory

FUNCTION TABLE
(Each Latch)
INPUTS
OUTPUTS

0
L
H

C
H
H

Q

Q

L
H

H
L

X

L

00

00

logic symbol

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-4.

PRODUCT PREVIEW
This document contains information on a

3-22 ~~~~c:e~~~:sdtehv:~~;;;~~t~~:~:: ~:~~:
continue this product without notice.

Copyright ©1.982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TexAS 75265

TYPES SN54HC75, SN74HC75
~-BIT BISTABLE LATCHES
timing requirements (supplement to recommended operating conditions)
SN74HC75

SN54HC75
MIN

NOM

MAX

MIN

NOM

MAX

UNIT

tw

Pulse duration, C high

ns

tsu
th

Setup time, data before CI

ns

Hold time, data after CI

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 v.
CL = 15 pF.
RL = 2 kO.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC75 SN74HC75
TA = 25°C
TA = 25°C
MIN ·TYP MAX MIN TYP MAX MIN MAX MIN MAX
tPLH
tpHL

D

Q

ns

tpLH
tpHL

D

Q

ns

C

Q

ns

C

Q

ns

tpLH
tpHL
tPLH
tpHL

Power dissipation capacitance per latch

No load, TA = 25°C

..

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 225Ot2 • DALLAS, TEXAS 75265

3-23

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC76, SN74HC76
DUAL J-K FLIP-FLOPS WITH CLEAR AND PRESET
02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC76 .•. J PACKAGE
SN74HC76 •.. J OR N PACKAGE
(TOP VIEW)

lCLK
lPAE
lCLA
lJ
VCC
2CLK
2PAE
2CLA

description

..

These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the Preset or
Clear input sets or resets the outputs regardless of
the levels of the other inputs. When Preset and
Clear are inactive (high). data at the J and K inputs
meeting the setup time requirements are transferred
to the outputs on the negative-going edge of the
clock pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the clock
pulse. Following the hold time interval. data at the J
and K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
also perform as toggle flip-flops by tying J and K
high.

lK
10
10
GND

2K
20
2Q
2J

For chip carrier information.
contact the factory.

logic symbol

The SN54HC76 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC76 is characterized for operation from -40°C to 85°C.

1PRE

1J

10

1CLK -'-~::::o..t:>
1K
1CLR
1PRE

2J

FUNCTION TABLE

20

2CLK--'-"--1..;;:::".j' ......

(EACH FLIP-FLOP)

2K
INPUTS
PRE

ClR

L
H

H

L

L
H

ClK
X

I

L
H

H

X

X

H
H

H

H

H

H

H
H

H

J
X
X
X

K
X
X
X
L
L
H
H

X
X
I
I
I

L

OUTPUTS

L
H

Q

Q

H

L
H

L
H*

00
H
L

2CLR

Pin numbers shown are for J and N packages.

H*
-

00
L
H

TOGGLE

00

00

'This configuration is nonstable; that is. it will not persist when
either Preset or Clear returns to its inactive (high) level.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table II. page 2-4.
PRODUCT PREVIEW
This document contains information on a
3-24 product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC76, SN74HC76
DUAL J-K FLIP-FLOPS WITH CLEAR AND PRESET
timing requirements (supplement to recommended operating conditions)
MIN
fclock

Setup time
before ClKI
Hold time. data after ClKI

tsu
th

MIN

SN74HC76
NOM
MAX

UNIT

Clock frequency
Pulse duration

tw

SN54HC76
NOM
MAX

MHz
PRE or ClR low
ClK high
ClK low
Data
PRE or ClR inactive

ns

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC= 5 V.
VCC = 4.5 V to 5.5 V.
CL = 15 pF.
CL = 50 pF
RL = 2 kCl
SN54HC76 SN74HC76
TA=25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

tplH
tpHl

PRE or ClR

cora

ns

tPlH
tpHl

ClK

cora

ns

PARAMETER

UNIT

f max

MHz

Power dissipation capacitance per flip-flop

II

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-25

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC77, SN74HC77
4-BIT BISTABLE LATCHES
02684. DECEM8ER 1982

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

SN54HC77 ... J PACKAGE
SN74HC77 ... J OR N PACKAGE
(TOP VIEW)

• Dependable Texas Instruments Quality and Reliability
10
20
3C,4C
VCC

description
These latches are ideaily suited for use as temporary
storage for binary information between processing
units and input/output or indicator units. Informa~
tion present at a data (0) input is transferred to the Q
output when the enable (C) is high and the Q output
will follow the data input as long as the enable
remains high. When the enable goes low, the information (that was present at the data input at the
time the transition occurred) is retained at the Q
output until the enable is permitted to go high.

D

3D

40
NC

NC - No internal connection

F.or chip carrier information,
contact the factory.

The SN54HC77 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC77 is characterized for operation from -40°C to 85°C.

FUNCTION TABLE
(Each Latch)
INPUTS
D
C
L
H
H
H
X
L

10
20
1C,2C
GNO
NC
30
40

logic symbol

OUTPUT
Q

L
H

00

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-4.

PRODUCT PREVIEW

3.26

This document contains information on 8
product under development. TexIS Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC77, SN74HC77
4-B11 BISTABLE LATCHES
timing requirements (supplement to recommended operating conditions)
SN54HC77
MIN

NOM

SN74HC77
MAX

MIN

NOM

MAX

UNIT

tw

Pulse duration, C high

tsu
th

Setup time, data before CI

ns

Hold time, data after CI

ns

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted) .

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5 V,
CL = 15 pF,
RL = 2 kCl,

VCC = 4.5 V to 5.5 V.
CL =50 pF

UNIT

SN54HC77 SN74HC77
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tPLH

0

Q

ns

C

Q

ns

tPHL
tPLH
tpHL

Power dissipation capacitance per latch
NOTE 1: For load circuit and voltage waveforms, see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFice BOX 225012 • DALLAS, TeXAS 75265

pFtyp

..

3-27

. TYPES SN54HC78, SN74HC78
DUAL J-K FLIP-FLOPS WITH PRESET,
COMMON CLEAR, AND COMMON CLOCK

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC78 ... J PACKAGE
SN74HC78 ... J OR N PACKAGE
(TOP VIEW)

CLK
1PRE
1J
VCC
CLR
2PRE
2K

description

..

These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the Preset or
Clear input sets or resets the outputs regardless of
the levels of the other inputs. Whe!l Preset and
Clear are inactive (high). data at the J and K inputs
meeting the setup time requirements are transferred
to the outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock
pulse. Following the hold time interval. data at the J
and K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
also perform as toggle flip-flops by tying J and K
high.

20
20
2J
GND

1'0
10
lK

For chip carrier information.
contact the factory.

The SN54HC78 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC78 is characterized for operation from -40°C to 85°C.

logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
PRE
L
H
L
H
H
H
H
H

ClR
H
l
L
H
H
H
H
H

ClK

J

K

X
X
X

X
X
X

X
X
X

I

L
H

I
I
I
H

OUTPUTS
Q
Q
H
L
L
H
H*

H*

00

00

L
H

L
L
H
H

X

X

00

1PRE

10

1K

L
L
H
TOGGLE

H

2PRE

20

2J

00

"This configuration is nonstable; that is. it will not persist when
either Preset or Clear returns to its inactive (high) level.

10

1J

20

2K
Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table II. page 2-4.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-28

This document contains information on a
product under development. Texas Instruments resarves the right to change or dis·
continue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 7S26S

TYPES SN54HC78, SN74HC78
DUAL J-K FLIP-FLOPS WITH PRESET,
COMMON CLEAR, AND COMMON CLOCK
timing requirements (supplement to recommended operating conditions)
SN74HC78

SN54HC78
MIN
fclock

NOM

MAX

MIN

NOM

UNIT

MAX

Clock frequency

MHz
PRE or ClR low

tw

tsu

Pulse duration

ClK high

Setup time

ClK low
Data
PRE or ClR inactive

before ClKI

ns

ns

Hold time. data after ClKI

th

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

VCC=5V,
Cl = 15 pF,

VCC = 4.5 V to 5.5 V,

FROM
(INPUT)

TO
(OUTPUT)

PRE or CLR

CorO

ns

ClK

CorO

ns

CL = 50 pF
RL = 2 kO,
SN54HC78 SN74HC78
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

f max
tPlH
tpHl
tplH
tpHl

MHz

Power dissipation capacitance per flip-flop

pF typ

NOTE1: For load circuit and voltage waveforms. see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-29

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC85, SN74HC85
4-81T MAGNITUDE COMPARATORS
02684, DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic and
Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HCB5 .. , J PACKAGE
SN74HCB5 ... J OR N PACKAGE
(TOPVIEWI
03

02

P>O

description

..

VCC
P3

{P
0, P < 0, and p:: 0 outputs of a stage handling lesssignificant bits are connected to the corresponding P> 0,
P < 0, and P 0 inputs of the next state handling moresignificant bits. The stage handling the least-significant
bits must have a high-level voltage applied to the P = 0
input. The cascading path of the 'HC85 is implemented
with only a two-gate-level delay to reduce overall comparison times for long words.

OUTPUTS

P2
P1

{P>O
P=O

01

PO
NC

{P>O
OUTPUTS P=O

The SN54HC85 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74HC85 is characterized for operation from -40°C to
85°C.

4
5
6
7
8

02
P2
NC
P1
01
9 1011 1213

50

0

U

0

1=~t§ZO

~

:::>

o

NC - No internal connection

FUNCTION TABLE

P3,03
P3 = 03

COMPARING
INPUTS
P2,02
Pl,Ol

PO, 00

P>O

Po
00
01
Q2

Q3

(9)
(11)

(14)
(1)

CASCADING

OUTPUTS

INPUTS

L
L

P>O
L
L

P

:}

P>O

PO

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-30

This document contains information on a
product under development. Texas Instruments relerves the right to change or discontinue this product without notice.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265

TYPES SN54HC85, SN74HC85
4-81T MAGNITUDE COMPARATORS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

F.ROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
CL=15pF.
RL = 2 kO.

Vcc = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC85 SN74HC85
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tPHL
tPLH
tpHL
tpLH
tpHL
tpLH
tpHL

Any Por 0

PO
P=O

ns

PO
P=O

ns

PO

ns

P=O

P=Q

ns

P>QorP=O

P B = AB + AS in positive logic.

VCC

4B
4A
4Y
38
3A
3Y

GND

A common application is as a true/complement element. If one
of the inputs is low. the other input will be reproduced in true
form at the output. If one of the inputs is high. the signal on the
other input will be reproduced inverted at the output.

..

SN54HC86 ... FH OR FK PACKAGE
SN74HC86 •.. FH OR FN PACKAGE
(TOP VIEW)

The SN54HC86 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC86
is characterized for operation from -40°C to 85°C.

U
co <{U UCO
...-Z

>'<:1'

2 1 2019

logic symbol
lA

(1)

-I

131

18

FUNCTION TABLE
leach gate)
1Y

INPUTS

2A

2V

28
3A
38
4A

4B

A

B

OUTPUT

lY

4

4A

NC

5

NC

2A

6

4Y

NC

7

NC

28

8

Y

L

L

L

L

H

H

H

L

H

H

H

L

3B
9 10 11 1213

>-OU>-<{

NZZMC")
l!)

NC -

No internal connection

Pin numbers shown are for J and N packages.

exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

EXCLUSIVE-OR

Thes~ are five equivalent Exclusive-OR symbols valid for an 'HeS6 gate in positive logic; negation may be shown at any two ports.

LOGIC IDENTITY ELEMENT

EVEN-PARITY

ODD-PARITY ELEMENT

~.
The output is active (low) if

The output is active (low) if

The output is active (high) if

all inputs stand at the same

an even number of inputs

an odd number of inputs (i.e .•

(i.e., 0 or 2) are active.

only 1 of the 2) are active.

logic level (i.e., A

=B).

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I. page 2-3.
PRODUCT PREVIEW

3-32

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC86, SN74HC86
nUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 V.
Cl = 15 pF.
Rl = 2 kn.

VCC = 4.5 V to 5.5 V.
Cl = 50 pF

UNIT

SN54HC86 SN74HC86
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tplH

Aor B

tpHL

(other input low)

tpLH

AorB
(other input high)

tPLH

y

ns

y

ns

Power dissipation capacitance per gate

pFtyp

NOTE 1: For load circuit and voltage waveforms. see pages 1-14.

..

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-33

TYPES SN54HC1 07, SN74HC107
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR

HIGH-SPEED
CMOS LOGIC

02684, DECEM8ER 1982

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC107 , , , J PACKAGE
SN74HC107 ... J OR N PACKAGE
(TOP VIEW}

lJ
10
10
1K
20
20
GND

description

..

These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the CLR
input resets the outputs regardless of the levels of
the other inputs. When CLR is inactive (high). data at
the J and K inputs meeting the setup time requirements are transferred to the outputs on the negativegoing edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold time
interval. data at the J and K inputs may be changed
without affecting the levels at the outputs. These
versatile flip-flops can perform as toggle flip-flops by
tying J and K high.

VCC
lClR
lClK
2K
2ClR
2ClK
2J

SN54HC107 ... FH OR FK PACKAGE
SN74HC107 ... FH OR FN PACKAGE
(TOP VIEW}
10 ~ u
z

3 2

10
NC
lK
NC
20

The SN54HC107 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC1 07 is characte'rized for operation from -40°C to 85°C.

lClK
NC
2K
NC
2ClR
9
N

L
H
H
H
H
H

J

I

X
l

I

H

J

l

J

H
X

H

K
X
L
L
H
H
X

Z
l!)

U
Z

-,

N

~

...J

U

N

NC - No internal connection

FUNCTION TABLE
INPUTS
CLOCK
X

2019

4
5
6
7
8
10 0

CLEAR

tlld

> _

OUTPUTS
Q
0
L
H

00

logic symbol

00

H

L
L
H
TOGGLE

00

00

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table II, page 2-4.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-34 ;~!~~:tC~::~td~~::~~n~~~:~~~:~~o~n:t~u~
ments reserves the right to change or dis·
continue this product without notice':

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC107, SN74HC1 07
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR
timing requirements

(supplem~nt

to recommended operating conditions)
MIN

fclock

MIN

SN74HC107
NOM
MAX

Clock frequency

tw

Pulse duration

tsu

Setup time
before ClKI
Hold time. data after ClKI

th

SN54HC107
NOM
MAX

UNIT
MHz

ClR low
elK high
ClK low
Data
ClR inactive

ns
ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted) .

PARAMETER

f max
tPlH
tPHl
tplH
tpHl

VCC=5V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
CL = 50 pF
RL =2 kO.
SN54HC107 SN74HC107
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

a:R

aorO

ns

ClK

aorO

ns

UNIT

MHz

Power dissipation capacitance per flip-flop

No load. TA = 25°C

..

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-35

TYPES SN54HC109, SN74HC109
DUAL J-K POSITIVE-EDGE-TRIGGERED
. FLIP-FLOPS WITH CLEAR AND PRESET

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
.

•

Dependable Texas Instruments Quality
and Reliability

SN54HC109 ... J PACKAGE
SN74HC109 ... J OR N PACKAGE
(TOPVIEWj

1CLR
lJ
1K
1CLK

description

II

These devices contain two independent J.j( positiveedge-triggered flip-flops. A low level at the Preset or
Clear inputs sets or resets the outputs regardless of
the levels of the other inputs. When Preset and
Clear are inactive (high), data at the J and K inputs
meeting the setup time requirements are transferred to the outputs on the positive-going edge of
the clock pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data at
the J and j( inputs may be changed without affecting
the levels at the outputs. These versatile flip-flops
can perform as toggle flip-flops by grounding Kand
tying J high. They also can perform as D-type flipflops if J and Kare tied together.

VCC
2CLR
2J
2K
2CLK
2i5R"f
2Q
2Q

GND

SN54HC109 ... FH OR FK PACKAGE
SN74HC109 ... FH OR FN PACKAGE
(TOPVIEWj

0::
uul5
-,du
IU
\
~Z>N

1K
1CLK
NC

The SN54HC109 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC109 is characterized for operation from -40°C to 85°C.

2J

2K
NC
2CLK

1Q

2PRE
10 0

U 10 0

.-ZZNN
t!)

FUNCTION TABLE
(EACH FLIp· FLOP)

NC -

INPUTS

OUTPUTS

CLOCK

J

K

0

L

H

X

X

X

H

0
L

H

L

X

X

X

L

H

L

L

X

X

X

H"

H"

H

H

t

L

L

L

H

H

H

t

H

L

H

H

t

L

H

TOGGLE
00
00

H

H

t

H

H

H

L

H

H

L

X

X

Qo

00

PRESET

CLEAR

No Internal connection

logic symbol

"This configuration is nonstable; that is. it will not persist when Preset
or Clear return to their inactive (high) level.
Pin numbers shown are for J and N packages

maximum ratings. recommended operating conditions. and electrical characteristics.
See Table II. page 2-4.

Copyright 91982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-36

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC109, SN74HC109
DUAL J-K POSITIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH CLEAR AND PRESET
timing requirements (supplement to recommended operating conditions)
SN54HC109
MIN
fclock

NOM

SN74HC109
MAX

MIN

NOM

UNIT

MAX

Clock frequency

MHz
PRE or ClR low

Pulse duration

tw

ClK high

ns

ClK low
tsu

Setup time
before ClKI

th

Hold time. data after ClKI

Data
PRE or ClR inactive

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC= 5 V.
CL=15pF.
PARAMETER

f max
tPlH
tpHl
tPlH
tpHl

FROM
(INPUT)

TO
(OUTPUT)

VCC = 4.5 V to 5.5 V.
CL = 50 pF

RL = 2 kCl.
SN54HC109 SN74HC109
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz
PRE or ClR

QorO

ns

ClK

QorO

ns

Power dissipation capacitance per flip·flop

..

pF typ

NOTE': For load circuit and voltage waveforms. see page '·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-37

TYPES SN54HC112, SN74HC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 19B2

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

SN54HC112 ... J PACKAGE
SN74HC112 ... J OR N PACKAGE
(TOPVIEWI

• Dependable Texas Instruments Quality
and Reliability

.1ClK
lK
lJ
1 PRE
10
lQ

description

..

These devices contain two independent J-K negativeedge-triggered flip-flops. A low level at the Preset or Clear
inputs sets or resets the outputs regardless of the levels of the
other inputs. When Preset and Clear are inactive (high), data at
theJ and K inputs meeting the setup time requirements are transferred
to the outputs on the negative-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold
time interval, data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
The SN54HC112 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HCl12
is characterized for operation from -40°C to 85°C.

VCC
lClR
2ClR
2ClK
2K
2J
2PRE
20

20
GND

SN54HC112 ... FH OR FK PACKAGE
SN74HC112 ... FH OR FN PACKAGE
(TOPVIEWI

::£

:J
u
2

UIS

uu
z>.-

U

1 2019

2CLR
2ClK
NC
2K
2J

1J
1PRE
NC
10

10

NC -

No internal connection

FUNCTION TABLE
INPUTS

OUTPUTS

logic symbol

Q

PRE

ClR

ClK

J

K

Q

X
X

H

L

L

H

1J

X

X
X
X

H"

H"

1CLK

l

H

H

L

L

L

X
X
X

H

H

~

L

L

00

00

H

H

~

H

L

H

L

1UR

H

H

~

L

H

L

H

2PRE

H

H
H

i

H

H

TOGGLE

H

X

X

H

00

00

"This configuration is nonstable; that is. it will not persist when either
Preset or Clear returns to its inactive (high) level.

1 P'R'E

1K

2J
2CLK
2K

2CLR

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions. and electrical characteristics
See Table II, page 2-4.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-38

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC112, SN74HC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
timing requirements (supplement to recommended operating conditions)
MIN
fclock

MIN

SN74HC112
MAX
NOM

Pulse duration

tsu

Setup time
before ClKI
Hold time. data after ClKI

UNIT
MHz

Clock frequency

tw

th

SN54HC112
NOM
MAX

PRE or ClR low
ClK high
ClK low
Data
PRE or ClR inactive

ns
ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
CL = 15 pF.
RL = 2 kn.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC112 SN74HC112
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

..
I

f max

MHz

tplH
tpHl

PRE or ClR

QorO

ns

tPlH
tpHl

ClK

QorO

ns

Cpd

Power dissipation capacitance per flip·flop

No load. TA = 25°C

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-39

TYPES SN54HC113, SN74HC113
DUAL J-K NEGATIVE-EDGE-TRIGGERED
FLIP-FLOPS WITH PRESET

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

SN54HC113 ... J PACKAGE
SN74HC113 ... J OR N PACKAGE
(TOP VIEW)

Dependable Texas Instruments Quality and Reliability
1CLK
1K
1J
1PRE
10

description
These devices contain two independent J-K negative-edgetriggered flip-flops. A low level at the Preset input sets the
outputs regardless of the levels of the other inputs. When Preset
(PRE) is inactive (high), data at the J and K inputs meeting the
setup time requirements are transferred to the outputs on the
negative-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data at the J and K
inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops
by tying J and K high.

II

The SN54HC113 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC113
is characterized for operation from -40°C to 85°C.

VCC
2CLK
2K
2J
2PRE
20
20

10
GND

SN54HC113 ... FH OR FK PACKAGE
SN74HC113 ... FH OR FN PACKAGE
.
(TOPVIEWI

2K
NC
2J
NC
2PRE

1J

NC
1 PRE
NC
10
10 Cl U 10 0

.... Z Z N N

t.:l
NC - No internal connection

logic symbol

FUNCTION TABLE
INPUTS
PRE

eLK

L

OUTPUTS
J

K

0

0

X

X

H

L

L

L

00

00

H

L

H

L

L

H

H

,
,
,

L

H

H

+

H

H

TOGGLE

H

H

X

X

00

H
H

X

1m
lJ
lCLK
lK

2r;Rr
2J
2CLK
2K

00

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-4.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-40

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265

TYPES SN54HCl13, SN74HCl13
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS WITH PRESET
timing requirements (supplement to recommended operating conditions)
SN74HC113

SN54HC113
MIN
fclock

NOM

MAX

MIN

NOM

MAX

UNIT
MHz

Clock frequency
PRE low

tw

Pulse duration
Setup time

ClK high
ClK low
Data

tsu

before ClK I

PRE inactive

th

Hold time. data after ClK I

ns

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

VCC=5V.
Cl = 15 pF.

VCC = 4.5 V to 5.5

v.

Cl = 60 pF

FROM
(INPUT)

TO
(OUTPUT)

PRE

QorO

ns

ClK

QorO

ns

UNIT
Rl=2kn.
SN54HC113 SN74HC113
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

f max
tpLH
tpHl
tpLH
tPHl

Power diSSipation capacitance per flip-flop

III

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-41

TYPES SN54HC114, SN74HC114
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

HIGH-SPEED
CMOS LOGIC

02684, DECEMBER 1982

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC114 .•• J PACKAGE
SN74HC114 ... J OR N PACKAGE
(TOP VIEW)

description

..

These devices contain two independent J-K negative-edgetriggered flip-flops. A low level at the Preset or Clear inputs sets
or resets the outputs regardless of the levels of the other inputs.
When Preset and Clear are inactive (high), data at the J and K
inputs meeting the setup time requirements are transferred to
the outputs on the negative-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to
the rise time of the clock pulse. Following the hold time interval,
data at the J and K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can perform as
toggle flip-flops by tying J and K high.

VCC
ClK
2K
2J
2 PRE
20

ClR
1K
1J
1PAE
10
1Q
GND

20

SN54HC114 ... FH OR FK PACKAGE
SN74HC114 ... FH OR FN PACKAGE
(TOP VIEW)

Jd uz>u
~~
3

The SN54HC114 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC114
is characterized for operation from -40°C to 85°C.

1J
NC

2

1 2019

2K
NC
2J
NC
2PRE

5

6
7

10

B
9 1011 12 13

10 Cl U 10 0

...-ZZNN
CJ

NC -

FUNCTION TABLE

PRE
l
H

ClR
H
L

L
H

L
H

H
H
H

H
H
H
H

H

INPUTS
ClK

logic symbol
OUTPUTS

J
X
X
X

K

a

a

X
X
X

H
L

L

H*

H*

L
L
H
H

00

00

l

L
H
L
H

H

X

X

Qo

X
X
X
l
l
l

No internal connection

H

L
H
H
L
TOGGLE

ill
CLK

1m

10

lJ

III

lK

2m

20

2J

25

2K

00

*This configuration is nonstable; that is, it will not persist when
either Preset or Clear returns to its inactive (high) level.

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table II, page 2-4.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-42

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice. •

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC114, SN74HC114
DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
timing requirements (supplement to recommended operating conditions)
SN54HC114
MIN
fclock

SN74HC114

MAX

NOM

MIN

NOM

UNIT

MAX

Clock frequency

MHz
PRE or ClR

Pulse duration

tw

ClK high

ns

ClK low
Setup time

Data

tsu

before ClK I

PRE or ClR inactive

th

Hold time. data after ClK I

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM

TO

(INPUT)

(OUTPUT)

=
=
Rl =2 kn.
TA =25°C

VCC 5 V.
Cl 15 pF.

=4.5 V to 5.5 V.
=50 pF

VCC
Cl

UNIT

=

SN54HC114SN74HC114
TA 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

f max
tplH

MHz
PRE or GlR

QorQ

ns'

ClK

QorO

ns

tPHl
tPlH
tpHl

Power dissipation capacitance per flip-flop

II

pF typ

NOTE 1: For load circuit and voltage waveforms"see page 1-14.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-43

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC123, SN74HC123
RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
02684. DECEMBER 1982

• D-C Triggered by Active-High or
Active-Low Inputs
.

SN54HC123 ... J PACKAGE
SN74HC123 ... J OR N PACKAGE

• Retriggerable for Very Long Output
Pulses. Up to 100% Duty Cycle

1A
18
1ClR
1Q
20
2C ext

• Overriding Clear Terminates Output Pulse
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

2ClR
2B
2A

2Rext/Cext
GND

description

II

VCC
1Rext/Cext
1Cext
10
2(l

These d-c triggered multivibrators feature output
pulse duration control by three methods. The basic
pulse duration is programmed by selection of external resistance and capacitance values. Once triggered, the basic pulse duration may be extended by
retriggering the gated low-level-active (A) or highlevel-active (B) inputs. or be reduced by use of the
overriding clear. Figure 1 illustrates pulse control by
retriggering and early clear.

SN54HC123 ... FH or FK PACKAGE
SN74HC123 ... FH or FN PACKAGE

~
CD
U

co ~

U
Z

U

)
CD

ua::

>

~

3 2

1ClR
10
NC
20
2C ext

The SN54HC123 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC123 is characterized for operation from -40°C to 85°C.

4

1Cext
10
NC
2(l

5
6
7

8

2ClR

9 1011 1213
~o

CDZ

U

u

Z

<
co
N N

l!)

)
CD

a::

N

FUNCTION TABLE
INPUTS
A
CLEAR
X
L
H
X
X
X

H
H
I

l
I
l

8
X
X
L

logic syml)ol

OUTPUTS
0
0
H
l

It
It

t

n

H
H

Il..
11.

lA
18

Ht
Ht

1CLR
1Cex t

U
1S
U

1 Rext/Cext
2A

2B
tThe second and third lines each indicate the logic
levels the outputs will take on after the completion
of any pulse already started.

2CLR
2Cext

2R ex t/Cex!
Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.
Note: The minimum recommended supply voltage for this device is 3 V.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a

3-44 ~~~~c:8~:~:sdt8hV8e~~:~~~t~~:~:: ~rS~~:

TEXAS INSTRUMENTS
tNCORPORATED

continue this product without notice.
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC123, SN74HC123
RETRIGGERABlE MONOSTABlE MUlTIVIBRATORS

RETRIGGER PULSE
BINPUT

~~----~C=J
,

OUTPUTQ

I

I+--tw + tPHL ~

L________ L

J

I+-tw---·~I OUTPUTWITHOUTRETRIGGER
OUTPUT PULSE CONTROL USING RETRIGGER PULSE

BINPUT~~___________________________

CLEAR
OUTPUT Q

0

J

OUTPUT WITHOUT CLEAR

I. .-_-_-_-_-_-_""'I..!:________

..

OUTPUT PULSE CONTROL USING CLEAR INPUT

FIGURE 1 - TYPICAL INPUT/OUTPUT PULSES

timing requirements (supplement to recommended operating conditions)
SN54HC123
MIN

NOM

SN74HC123
MAX

MIN

NOM

UNIT
MAX

tw

Pulse duration. A low. B high. or CLR low

ns

Rext

External timing resistance

kO

External timing capacitance

pF
pF

Cext

Wiring capacitance at Rext/Cext terminal

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tPLHt
tPHLt
tPHLt
tPLHt
twQ(minlt
twQt
Cpd

FROM
(INPUT)

A
B
A
B
CLR
Aor B
AorB

TO
(OUTPUT)

VCC= 5 V.
CL = 15 pF.

VCC = 4.5 V to 5.5 V.

CL = 50 pF
RL = 2 kO.
SN54HC123 SN74HC123
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

Q

ns

Q

ns

Q
Q

ns

Q

ns

Q

/.Is

Power dissipation capacitance per monostable

No load. TA = 25°C

pFtyp

tC ext = O. Rext = 5kO
;twQ = duration of pulse at output Q. Cext = 400 pF. Rext = 10kO.
NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-45

TYPES SN54HC132, SN74HC132
SCHMITT-TRIGGER POSITIVE-NAND GATES
WITH TOTEM-POLE OUTPUTS

HIGH-SPEED
CMOS LOGIC

D26B4. DECEMBER 19B2

• Operation from Very Slow Transitions

SN54HC132 ... J PACKAGE
SN74HC132 ... J OR N PACKAGE
(TOP VIEW)

• Temperature-Compensated Threshold Levels
• High Noise Immunity

Vee

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

4B
4A

4Y

• Dependable Texas Instruments Quality and Reliability

3B
3A

description

""'"'--_ _~_3Y

Each circuit functions as a NAND gate. but because of the
Schmitt action. it has different input threshold levels for positiv.eand negative-going signals.

SN54HC132 ... FH OR FK PACKAGE
SN74HC132 ... FH OR FN PACKAGE
(TOP VIEW)

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitterfree output signals.

•

al

<

U

Z

3 2

The SN54HC132 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC132
is characterized for operation from -40°C to 85°C .

u

U al
o:t

>

2019

lY

Ne
2B

logic symbol
lA
lB
2A
26
3A
36
4A
46

(1)

>

&D

N

0
Z

U

Z

> <

(') (')

t!l

(2)
(4)

NC - No internal connection

(5)
(9)

(10)
(12)
(13)
positive logic: Y = As

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tpLH
tpHL

AorB

Y

VCC=5V.
VCC = 4.5 V to 5.5 V.
CL= 15 pF.
CL = 50 pF
RL = 2 kn.
SN54HC132 ~N74HC132
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

Power dissipation capacitance per gate

No load. TA = 25°e

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

PRODUCT PREVIEW

3-46

This document contains information on a
product under development. Texas Instruments reserveS the right to change or discontinue this product without notice.

Copyright ©19B2 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC133, SN74HC133
13-INPUT POSITIVE-NAND GATES
02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC133 ... J PACKAGE
SN74HC133 ... J OR N PACKAGE
(TOP VIEW)

A
B
C
D

description

M
L
K
J

E

These devices contain a single 13-input NAND gate.
They perform the boolean functions in positive logic:
Y = A·B·C·D·E·F·G·H·I·J·K·L·M

VCC

F
G
GND

or

Y=A+8+C+O+E+F+G+H+I+J+K+L+M

The SN54HC133 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC133 is characterized for operation from -40°C to 85°C.

logic symbol

H
Y

SN54HC133 ... FH OR FK PACKAGE
SN74HC133 ... FH OR FN PACKAGE
(TOP VIEW)

C
&

NC

(2J

..
I

NC
J

E

(31

C

L
K

D

(11

A

F

(4)

0

I

(51
~ClU>-I

(61

ZZ

(7J

(91

G

H

~

y

(101

NC -

No internal connection

(111

FUNCTION TABLE
INPUTS A THRU M
M

(15)

OUTPUT
y

All inputs H

L

One or more inputs L

H

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tpLH

Any

y

VCC=5V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
CL = 50 pF
RL = 2 kO.
SN54HC133 SN74HC133
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

ns

tpHL
Power Dissipation capacitance per gate

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-47

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC137, SN74HC137
3-LlNE TO a-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
02684. DECEMBER 1982

•

SN54HC137 ... J PACKAGE
SN74HC137 ... J OR N PACKAGE

Combines Decoder and 3-Bit Address Latch

•

Incorporates 2 Output Enables to Simplify Cascading

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

(TOPVIEWI

A
B

C
GL
(32
Gl
Y7

description

..

The 'HC137 is a three-line to eight-line decoder/demultiplexer with latches on the three address inputs. When the
latch-enable input (GL) is low. the 'HC137 acts as a
decoder/demultiplexer. When GL goes from low to high.
the address present at the select inputs (A. B. and C) is
stored in the latches. Further address changes are ignored
as long as Gi remains high. The output enable controls.
Gl and G2. control the outputs independently of the select
or latch-enable inputs. All of the outputs are forced high if
Gl is low or 132 is high. The 'HC137 is ideally suited for
implementing glitch-free decoders in strobed (storedaddress) applications in bus-oriented systems .

VCC
YO
Yl
Y2
Y3
Y4
Y5
Y6

GND

SN54HC137 ... FH OR FK PACKAGE
SN74HC137 ... FH OR FN PACKAGE

(TOPVIEWI

U

U

uo

co~z>>-

The SN54HC137 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC137 is characterized for operation from -40°C to
85°C.

C

Yl
Y2

GL
NC

NC

(32
Gl

Y3
Y4
r--OUCOLO

>-zz>->C)

NC - No internal connection

logic symbols (alternatives)

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6.

PRODUCT PREVIEW

3-48

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC137, SN74HC137
3-LlNE TO 8-LlNE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
FUNCTION TABLE
INPUTS
ENABLE

OUTPUTS

SELECT

GL G1 G2 C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
H H H
H X X X H H H H H
X
X
H

X

L

X

X X

X

H

H

H

H

H

H

H

L

H

L

L L

L

L

H

H

H

H

H

H

H

L

H

L

L L H

H

L

H

H

H

H

H

H

L

H

L

L H L

H

H

L

H

H

H

H

H

L

H

L

L H H

H

H

H

L

H

H

H

H

L

H

L

H L

L

H

H

H

H

L

H

H

H

L

H

L

H L

H

H

H

H

H

H

L

H

H

L

H

L

H H L

H

H

H

H

H

H

L

H

L

H

L

H H H

H

H

H

H

H

H

H

L

H

H

L

X X

Output corresponding to stored
X

address. L; all others. H

timing requirements (supplement to recommended operating conditions)
SN54HC137
MIN
fclock
tw
tsu
th

NOM

MAX

MIN

SN74HC137
MAX
NOM

UNIT

Clock frequency

MHz

Pulse duration. GL low

ns

Setup time. A. B. and C before GLt

ns

Hold timt3. A. B. and C after GLt

ns

..

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC::5 V.
CL::15pF.
RL:: 2 kO.

=

VCC 4.5 V to 5.5 V.
CL:: 50·pF

UNIT

SN54HC137 SN74HC137
TA:: 25°C
TA:: 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
MHz

f max
tPLH
tpHL
tpLH

A.B.C

y

ns

(32

y

ns

G1

y

ns

CIT

y

ns

tpHL
tpLH
tpHL
tPLH
tpHL

Power dissipation capacitance

No load. TA:: 25°C

pF Iyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

3-49

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC138, SN74HC138
3-LlNE TO 8-LlNE DECODERS/DEMULTIPLEXERS
02684. DECEM8ER 1982

SN54HC138 ... J PACKAGE
SN74HC138 ... J OR N PACKAGE
(TOPVIEWI

•

Designed Specifically for High-Speed Memory
Decoders and Data Transmission Systems

•

Incorporates 3 Enable Inputs to Simplify Cascading
and/ or Data Reception

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

A
8
C
G2A
G28
Gl
Y7
GND

description

..

The 'HC138 circuit is designed to be used in high-performance
memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory
systems this decoder can be used to minimize the effects of
system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory are usually less than the typical
access time of the memory. This means that the effective
system delay introduced by the decoder is negligible.

VCC
YO
Yl
Y2
Y3
Y4
Y5
Y6

SN54HC138 ... FH OR FK PACKAGE
SN74HC138 ... FH OR FN PACKAGE
(TOPVIEWI
U

U
Uo

CD«Z>>The conditions at the binary select inputs and the three enable
inputs select one of eight input lines. Two active-low and one
active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data
input for demultiplexing applications.

C
G2A

Yl
Y2
NC
Y3
Y4

NC

G2B
Gl

The SN54HC138 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC138
is characterized for operation from -40°C to 85°C.
NC -

No internal connection

logic symbols (alternatives)

BIN/OCT
A (1)
8 (2)

c

(3)

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-50

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
tNCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC138, SN74HC138
3-LlNE TO 8-LlNE DECODERS/DEMULTIPLEXERS,
FUNCTION TABLE
ENABLE

SELECT

INPUTS

INPUTS

OUTPUTS

G1

G2*

C

B

A

VO

V1

V2

V3

V4

V5

V6

X

H

X

X

X

H

H

H

H

H

H

H

H

L

X

X

X

X

H

H

H

H

H

H

H

H

V7

H

L

L

L

L

L

H

H

H

H

H

H

H

H

L

L

L

H

H

L

H

H

H

H

H

H

H

L

L

H

L

H

H

L

H

H

H

H

H

H

L

L

H

H

H

H

H

L

H

H

H

H

H

L

H

L

L

H

H

H

H

L

H

H

H

H

L

H

L

H

H

H

H

H

H

L

H

H

H

L

H

H

L

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

L

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC=5V.
PARAMETER

VCC = 4.5 V to 5.5 V.

CL=15pF.

CL = 50 pF

FROM

TO

(INPUT)

(OUTPUT)

A.B.C

AnyV

ns

Enable

AnyV

ns

TA = 25°C

MIN TVP MAX MIN TVP MAX
tPLH

UNIT

RL=2kO.
TA = 25°C

II

SN54HC138 SN74HC138
MIN

MAX

MIN

MAX

tPHL
tpLH
tpHL

~~C~pd~__- J_ _ _ _ _ _ _ _ _P_ow_e_r_d_IS_S~IP_at_lo_n_c~ap~a_c_lta_n_ce________- L_ _ _ _N_o_lo_a_d_.T~A~=_2_5_o_C____~____~p_F_t~yp____~
NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-51

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC139, SN74HC139
DUAL 2-UNE TO 4-UNE DECODERS/DEMULTIPLEXERS
02684. DECEM8ER 1982

• Designed Specifically for High-Speed Memory
Decoders and Data Transmission Systems

SN54HC139 ... J PACKAGE
SN74HC139 ... J OR N PACKAGE
(TOP VIEW)

• Incorporates 2 Enable Inputs to Simplify Cascading
and/or'Data Reception

1<3
1A
18
lYO
lYl
1Y2
1Y3

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
Dependable Texas Instruments Quality and Reliability
description
The 'HC139 circuit is designed to be used in high-performance
memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory
systems, this decoder can be used to minimize the effects of
system decoding. When employed with high-speed memories
utilizing a fast-enable circuit. the delay times of this decoder and
the enable time of the memory are usually less than the typical
access time of the memory. This means that the effective
system delay introduced by the decoder is negligible.

II

The 'HC139 is comprised of two individual two-line to four-line
decoders in a single package. The active-low enable input can
be used as a data line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of
which represents only one normalized load to its driving circuit.
The SN54HC139 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC139
is characterized for operation from -40°C to 85°C.

logic symbols (alternatives)

VCC

2<3
2A
28
2YO
2Y1
2Y2
2Y3

GND

SN54HC139 ... FH OR FK PACKAGE
SN74HC139 ... FH OR FN PACKAGE
(TOP VIEW)

« 1<.9

U

u

UI<.9

Z>N

18
lYO

2A
28

NC

NC

2YO
2Y1

lYl
lY2

NC -

No internal connection

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-52

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012. DALLAS. TEXAS 75265

TYPES SN54HC139. SN74HC139
DUAL 2-lINE TO 4-lINE DECODERS/DEMUlTIPlEXERS
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE SELECT

G

B A

H

X

X

H

H

H

L

L

L

L

H

H

L

L

H

H

L

H

L

H

L

H

L

L

H

H

H

H
H

H
H
H
H

H

L

YO Y1 Y2 Y3

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC= 5 V.
PARAMETER

tPLH
tPLH

VCC = 4.5 V to 5.5 V.
CL = 50 pF

TO

(INPUT)

(OUTPUT)

Aor B

Y

ns

G

y

ns

tPHL
tPHL

CL=15pF.

FROM

UNIT

RL = 2 kCt
SN54HC139 SN74HC139
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dIssIpatIon capacllance per decoder

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-53

HIGH-SPEED
CMOS lOGIC

TYPES SN54HC147, SN74HC147
1O-lINE-TO-4-lINE PRIORITY ENCODERS
02684. DECEMBER 1982

• Encodes 1 O-Line Decimal to 4-Line BCD

SN54HC147 . .. J PACKAGE
SN74HC147 . .. J OR N PACKAGE
(TOPVIEWI

• Applica~ions Include:
Keyboard Encoding
Range Selection

4
5
6

VCC
NC

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

8

• Dependable Texas Instruments Quality and
Reliability

8

0
3
2
1
9

GND

A

7

C

description
SN54HC147 '" FH OR FK PACKAGE
SN74HC147 ... FH OR FN PACKAGE
(TOP VIEW)

These encoders feature priority decoding of the
inputs to ensure that only the highest-order data
line is encoded. The 'HC147 encodes nine data lines
to four-line (8-4-2-1 ) BCD. The implied decimal zero
condition requires no input condition as zero is
encoded when all nine data lines are at a high logic.
level. The data inputs and outputs are active at the
low logic level.

..

.Ltl

U
'It Z

tl ZU

>

6

o

7

3

NC

The SN54HC147 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC147 is characterized for operation from -40°C to 85°C.

NC

8
C

2

alOU«m

z z

l!1

NC - No internal connection

logic symbol
FUNCTION TABLE
INPUTS
6
4
5

1
H
X
X
X
X

2
H
X
X
X
X

X

X

X

X
X
X

X
X

X
L

L

H.
H

L

H

H
H

3
H
X
X
X
X

H
X
X
X
X

H
X
X
X
X

H
X
X
X

X

L

L

H
H
H

H
H
H
H

H

H

H

L

7
H
X
X
L
H
H
H
H
H
H

8
H
X
L
H
H
H
H
H
H
H

9
H
L
H
H
H
H
H
H
H
H

HPRI/BCD

OUTPUTS
D
A
C
B

H
L
L

H
H
H
H
H
H
H

H
H
H

H
H
H

L
L
L

L

L

L

H

H
H

H

L

H
H
H

H
L

H

L

L

L

L
H

H
L

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-54

This document contains information on a
product under development. Texas Instruments reserves the right to change or dis·
continue this produ'ct without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TeXAS 75265

TYPES SN54HC147, SN74HC147
1O-UNE-TO-4-UNE PRIORITY ENCODERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

VCC=5V.
CL=15pF.

TO

RL = 2

(OUTPUT)

kn.

Vcc = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC147 SN74HC147
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tpHL
tPLH
tpHL

Any
Any

Any

ns

(in phase with input)
Any

ns

(out of phase with input)
Power dissipation capacitance

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1·14.

•

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-55

I

I

HIGH-SPEED
CMOS lOGIC

TYPES SN54HC151, SN74HC151
DATA SElECTORS/MUlTIPlEXERS
02684. DECEM8ER 1982

SN54HC151 ... J PACKAGE
SN74HC151 ... J OR N PACKAGE
(TOPVIEWI

• 3-Line to 1-Line Multiplexers
Can Perform As:
Boolean Function Generators
Parallel-to-Serial Converters
Data Source Selectors
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

03
02
01

• Dependable Texas Instruments Quality and Reliability

y

VCC

04
05
06
07
A

description

B

These monolithic data selectors/multiplexers provide full binary
decoding to select one of eight data sources. The strobe input
(G) must be at a low logic level to enable the inputs. A high level
at the strobe terminal forces the W output high and the Y output
low.

..

GNO

C

SN54HC151 ... FH OR FK PACKAGE
SN74HC151 ... FH OR FN PACKAGE
(TOPVIEWI

The SN54HC151 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC151
is characterized for operation from -40°C to 85°C.

N C'1 U

U
U'o
3

2

1 2019

D1

05
06

00
NC
y

FUNCTION TABLE
INPUTS
SELECT
C

B

OUTPUTS
STROBE

A

G

y

w

X

X

X

H

L

H

L

L

L

L

L

L

H

L

Do'
D1

L

H

L

L

L

H

H

L

DO
01
02
03
04
05
06
07

H

L

L

L

H

L

H

L

H

H

L

L

H

H

H

L

'B2
D3
04

NC

07

W

A
g 10 11 1213

/l? 0

U U CD

ZZ

l?
NC -

No internal connection

logic symbol

i55
06
07

MUX[>

H ~ high level, L ~ low level. X ~ irrelevant
00,01 .. , 07 ~ the level of the 0 respective input

G

EN

A

:)G~

B
C

DO

(5)

01
02
03
04
05
06
07

(6)

y

w

(1)
(15)

(14)
113)

(12)

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

PRODUCT PREVIEW

3-56

This document contains information on a
product under development. Texas Instruments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPO'RATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC151, SN74HC151
DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tPHL

I
NOTE

VCC=5V.
Vcc = 4.5 V to 5.5 V.
CL=15pF.
See Note 1
RL =2 kn.
SN54HC151 SN74HC151
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

A. B.orC

Y

ns

A. B.orC

W

ns

Any 0

Y

ns

Any 0

W

ns

G

y

ns

G

w

ns

Cod
Power diSSipation capacitance
t: For load circuit and voltage waveforms, see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pF typ

UNIT

..

3-57

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC152, SN74HC152
8-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
02684. DECEMBER 1982

•

SN54HC152 ... J PACKAGE
SN74HC152 ... J OR N PACKAGE
(TOP VIEW)

Selects One-of-Eight Data Sources

•

Performs Parallel-to-Serial Conversion

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

description
These monolithic data selectors/multiplexers contain full on-chip binary decoding to select the desired
one-of-eight data sources.

04
03
02
01

VCC

DO

A

05
06
07

W

B

GNO

C

SN54HC152 ... FH OR FK PACKAGE
SN74HC152 ... FH OR FN PACKAGE
(TOP VIEW)

The SN54HC152 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC152 is characterized for operation from -40°C to 85°C,

3 2 1 2019
02

•

06

NC

NC

01

07

NC

NC

DO

14
9 1011 1213

A

:S:0UUal
Z Z
<.!)

NC -

logic symbol

FUNCTION TABLE
SELECT
INPUTS
B A

OUTPUT

C

W

L

L

DO

L

L

H

L

H

L

L

No internal connection

A

B

L

H

H

L

L

51
52
D3
54

H

L

H

55

03

H

c

(10)
(9)
(8)

MUX [>

:}G~

00
01

(6)

02

H

H

L

56

04

H

H

H

57

05
06
07

W

(12)
(11)

Pin numbers shown are for J and N packages.

maximum ratings. recomme':1ded operating conditions. and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW

3-58

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright '£'1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 2250t2 • DALLAS. TEXAS 75265

TYPES SN54HC152, SN74HC152
8-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL
tPLH
tpHL

VCC=5V.
CL=15pF.

Vcc = 4.5 V to 5.5 V.
See Note 1

FROM
(INPUT)

TO
(OUTPUT)

A. B. orC

W

ns

AnyD

W

ns

RL = 2 kn.
SN54HC152 SN74HC152
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dissipation capacitance

No load. TA = 25°C

UNIT

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1-14.

II

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-59

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC153, SN74HC153
DUAL 4-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
02684, DECEMBER 1982

• Permits Multiplexing from N Lines to 1 Line

SN54HC153 ... J PACKAGE
SN74HC153 ... J OR N PACKAGE
(TOP VIEW)

• Performs Parallel-to-Serial Conversion
• Strobe (Enable) Line Provided for Cascading (N
lines to n lines)

1<3

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic
DIPs

lC3
lC2
lCl
lCO
lY
GND

• Dependable Texas Instruments Quality and
Reliability
description
Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data
selection to the AND-OR gates. Separate strobe inputs (<3)
are provided for each of the two four-line sections.

..

A

2C3
2C2
2Cl
2CO
2Y

SN54HC153 ... FH OR FK PACKAGE
SN74HC153 ... FH OR FN PACKAGE
(TOP VIEW)

The SN54HC153 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC153 is characterized for operation from -40°C to
85°C.

U

aJ

3

lC3
lC2
NC
lCl
lCO

FUNCTION TABLE
SELECT

VCC
2<3

B

1<.::> U UI<.::>
Z>N
2

1 2019

A
5

2C3

6

NC

7

2C2
2Cl

8

STROBE

OUTPUT

9 10 11 1213

C2

C3

G

Y

X

X

X

H

L

>- 0 U>-O
Z ZNU
N
<.::>

X

X

X

L

L

X

X

X

L

H

X

L

X

X

L

L

H

X

H

X

X

L

H

L

X

X

L

X

L

L

DATA INPUTS

INPUTS
B

A

CO

X

X

X

L

L

L

L

L

H

L

H

L
H

C1

NC - No internal connection

logic symbol

H

L

X

X

H

X

L

H

A

H

H

X

X

X

L

L

L

B

H

H

X

X

X

H

L

H

Select inputs A and B are common to both sections.
(71

2CO

(91

2Cl

1Y

2Y

2C2
2C3 (131

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW

3-60

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS, TEXAS 75265

TYPES SN54HC153, SN74HC153
DUAL 4-lINE TO 1-lINE DATA SElECTORS/MUlTIPlEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
Vcc = 4.5 V to 5.5 V.
See Note 1

(OUTPUT)

Aor B

y

ns

tPLH
tpHL

Data
(Any C)

y

ns

tpLH
tpHL

G

y

ns

PARAMETER

tpLH
tpHL

TO

VCC=5V.
CL=15pF.

FROM
(INPUT)

RL = 2 kO.

UNIT

SN54HC153 SN74HC153
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dissipation capacitance per multiplexer

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-61

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC154, SN74HC154
4-UNE-TO-16-UNE DECODE.RS/DEMULTIPLEXERS
02684, OECEM8ER 1982

• Decodes 4 Binary-Coded Inputs into One of
16 Mutually Exclusive Outputs

SN54HC154 ... JT PACKAGE
SN74HC154 ... JT OR NT PACKAGE
(TOPVIEWI

• Performs the Demultiplexing Function by
Distributing Data From One Input line to
Any One of 16 Outputs

0

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

2
3
4
5

• Dependable Texas Instruments Quality
and Reliability

6
7

A

B

e
0

<32
<31
15
14
13
12

8
9
10

description

..

Vee

Each of these monolithic. 4-line-to-16-line decoders
decodes four binary-coded inputs into one of sixteen
mutually exclusive outputs when both the strobe
inputs. G1 and G2. are low. The demultiplexing
function is performed by using the 4 input lines to
address the output line. passing data from one of the
strobe inputs with the other strobe input low. When
either strobe input is high. all outputs are high.
These demultiplexers are ideally suited for implementing high-performance memory decoders.

11

GND

SN54HC154 ... FH OR FK PACKAGE
SN74HC154 ... FH OR FN PACKAGE
(TOPVIEWI

3
4
5

The SN54HC154 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC154 is characterized for operation from -40°C to 85°C.

C

o

G2

NC

NC

6
7
8

<31
15
14

logic symbols (alternatives)
NC -

No internal connection
OMUX

4
5

A

(23)

6

B

(22)

C

(21)

o

(20)

9
10
11

10

12

12
13

13

11

14

14

15

15

Pin numbers shown are for JT and NT packages.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-62

This document contains information on a
product under development. Texas Instruments reserves the right to chanee or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC154, SN74HC154
4-UNE-TO-16-LlNE DECODERS/DEMUlTIPlEXERS
FUNCTION TABLE
OUTPUTS
0
C

61

62

L
L
L
L
L
L
L
L

L
L
L
L
L
L
L

L

L
L

H

L
L
L
L
L
L

L

L
L
L
L
L
L
L
L

L
L
L
L

OUTPUTS
B

A

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

L
L

L

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H
H

151

H

L

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

L

L

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H
H

L

H

L

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

L
L

H
H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

L

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H
L

H

H

H

H

H

L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

L
L
L
L
L

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

L

H

X
X
X

X
X
X

X
X
X

X
X
X

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

H

L

H

H

H = high level. L = low level. X = irrelevant

..
I

I

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV. page 2-6.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL
tpLH
tpHL
Cpd

VCC =5 V.
CL=15pF.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

FROM

TO

(INPUT)

(OUTPUT)

A. B. C. or D

Any

ns

<31orG2

Any

ns

RL = 2 kO.
SN54HC154 SN74HC154
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dissipation capacitance

No load. TA = 25 c C

UNIT

pF typ

NOTE 1: For load CircUit and voltage waveforms. see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-63

TYPES SN54HC157, SN54HC158, SN74HC157, SN"14HC158
QUADRUPLE 2-LlNE TO 1-LlNE
DATA SELECTORS/MULTIPLEXERS

HIGH-SPEED
CMOS LOGIC

DECEMBER 1982

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC157, SN54HC158 ... J PACKAGE
SN74HC157, SN74HC158 ... J OR N PACKAGE
ITOPVIEW)

• Dependable Texas Instruments Quality and
Reliability

AlB
1A
1B
1Y
2A
28
2Y
GND

description
These monolithic data selectors/multiplexers contain inverters and drivers to supply full data selection to the four
output gates. A separate strobe input (G) is provided. A
4-bit word is selected from one of two sources and is
routed to the four outputs. The 'HC157 presents true data
whereas the 'HC158 presents inverted data.
The SN54HC157 and SN54HC158 are characterized for
operation over the full military temperature range of
-55°C to 125°C. The SN74HC157 and SN74HC158 are
characterized for operation from -40°C to 85°C .

•

FUNCTION TABLE
INPUTS

A

B

H

X

X

X

L

H

L

L

L

X

L

H

L

L

H

X

H

L

L

H

X

L

L

H

L

H

X

H

H

L

'HC157

4A
4B
NC
4Y
3A

18
1Y
NC
2A
28

OUTPUTV

SELECT
A/B

4A
4B
4Y
3A
3B
3Y

SN54HC157, SN54HC158 ... FH OR FK PACKAGE
SN74HC157, SN74HC158 ... FH OR FN PACKAGE
ITOPVIEW)

DATA

G

STROBE

VCC

G

'HC158

NC -

No internal connection

logic symbols
'HC157

1A

'HC158

1Y

18

lB

2A

2A

2Y

28

28

3A

3A

38

3Y

1Y
2Y

3Y

4Y

4Y

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW

3.64

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 •

OA~~AS.

TEXAS 15265

TYPES SN54HC157, SN54HC158, SN74HC157, SN74HC158
QUADRUPLE 2-LlNE TO 1-LlNE
DATA SELECTORS/MULTIPLEXERS
'HC157 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

FROM
(INPUT)

VCC::5 V.
CL=15pF.

TO
(OUTPUT)

RL = 2 kC'l.

vcc = 4.5 V to 5.5 V.
See Note 1

UNIT

SN54HC157 SN74HC157
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

AorB

y

ns

AlB

y

ns

G

y

ns

Power dissipation capacitance per multiplexer

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

'HC158 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

FROM
(INPUT)

VCC= 5 V.
CL = 15 pF.
RL = 2 kC'l.

TO
(OUTPUT)

VCC = 4.5 V to 5.5 V.
See Note 1

. .

UNIT

SN54HC158 SN74HC158
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tPLH
tpHL

AorB

Y

ns

tpLH
tpHL

AlB

y

ns

G

y

ns

tpLH
tpHL

Power dissipation capacitance per multiplexer

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS

INSTRUMENTS

INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-65

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC160 THRU SN54HC163,
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
02684, DECEMBER 1982

•

Internal Look-Ahead for Fast Counting

SN54HC'... J PACKAGE
SN74HC', . , J or N PACKAGE
(TOPVIEWI

•

Carry Output for n-Bit Cascading

•

Synchronous Counting

•

Synchronously Programmable

•

Package Options Include Both Plastic and Ceramic Chip
Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

ClR
ClK
B
C

VCC
RCO
OA
OB
Oc

0

00

A

ENT
lOAD

ENP
GNO
description

..

These synchronous, presettable counters feature an internal
carry look-ahead for application in high-speed counting designs.
The 'HC160 and 'HC162 are decade counters, and the 'HC161
and 'HC163 are 4-bit binary counters. Synchronous operation is
provided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This
mode of operation eliminates the output counting spikes that
are normally associated with synchronous (ripple clock) counters.
A buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may
be preset to either level. As presetting is synchronous, setting
up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock
pulse regardless of the levels of the enable inputs.

SN54HC' ... FH or FK PACKAGE
SN74HC' ... FH or FN PACKAGE
(TOPVIEWI

~15 u
u u z

>tl8
a::

3 2

2019

4

B

5

NC

6

C

Oc

o

00
9 1011 1213

0 10OW
« z

U
Z Z Z

11.

t-

w(!l

..J

NC -

no internal connection

The clear function for the 'HC160 and 'HC161 is asynchronous and a low level at the clear input sets all four of the
flip-flop outputs low regardless of the levels of the clock, load, or enable inputs.
The clear function for the 'HC162 and 'HC163 is synchronous and a low level at the clear input sets all four of the
flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one
external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000
(LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both
count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the ripple carry output.
The ripple carry output (RCO) thus enabled will produce a high-level pulse while the count is maximum (9 or 15 with
QA high). This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions
at the ENP or ENT are allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the
counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable
setup and hold times.
The SN54HC160 through SN54HC163 are characterized for operation over the full military temperature range of
-55°C to 125°C. The SN74HC160 through SN74HC163 are characterized for operation from -40°C to 85°C.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-66

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

TEXAS INSTRUMENTS
I NCOR PORATED
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265

TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
logic symbols

HC1.60 DECADE COUNTER
WITH DIRECT CLEAR

'HC161 BINARY COUNTER
WITH DIRECT CLEAR

CTRDIV10

CTRDIV16

RCa
ENT

ENP
ClK - - - 0

D

RCa

ClK

141
181

(14)

oA

A

(121

oB

B

(111

Oc
aD

C

(121 °B
(111 Oc

D

OD

A

B
C (51
(61

(151

ENT
ENP

'HC162 DECADE COUNTER
WITH SYNCHRONOUS CLEAR

(131 °A

..

'HC163 BINARY COUNTER
WITH SYNCHRONOUS CLEAR

RCa

ENT
ENP

ENT
ENP

ClK

ClK

A

A

B

B

C

C

D

D

RCa

Pin numbers shown are for J and N packages.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3·67

TYPES SN54HC160, SN54HC162,
SN74HC160,SN74HC162
SYNCHRONOUS 4-81T DECADE COUNTERS
'160 and '162 output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (SN54HC160 and SN74HC160 are asynchronous; SN54HC162 and
SN74HC162 are synchronous)
2. Preset to BCD seven
3. Count to eight. nine, zero, one, two, and three
4. Inhibit

u

c=

•

L=

DATA
INPUTS

c=

---J1
I__

o _ _---i-_ _ _ _
ClK
ENP

ENT
I

I

OA

-,

-.

I

,

I_I

I
,

OB

I

I

I

,

;i~
I
I
,'-----------'

Oc

-; --l~~________________________________
I

,

I

-; i

I

I

'

00

-:
I

I
I

I

I

I

I

OUTPUTS

RCa

I~------~

____________~______________________

____~I--~I--~I~--+I----Jr---l~------~-----------------:
:7
;8
9
0
2
3,

I

I

:

...

i · > - - - - - C O U N T - - - - - - I...
• ---INHIBIT----

SYNC PRESET

ASYNC CLEAR
CLEAR

3·68

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC161, SN54HC163, SN74HC161, SN74HC163
SYNCHRONOUS 4-BIT BINARY COUNTERS

'161 and '163 output sequence
Illustrated below is the following sequence:
1. Clear outputs to zero (SN54HC161 and SN74HC161 are asynchronous; SN54HC163
and SN74HC163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen, zero, one, and two
4. Inhibit

ClR~
I

I

U

I

LOAD
A

I

I--

8
DATA
INPUTS

,--

..

I

c..J

'--

D~

1L_

I

ClK
ENP

ENT

I

OA

--, --,
---!

_I

- --, --,

08 _ _I

I

OUTPUTS

OD- - , - .

--1--,

I

I

I~

I

I

I
r---I

RCO----~'--~--~I----------~I
:
:
:12
13
14
15

I

1 11-·

SYNC

I~--~--~----------------------2

0

- - - C O U N T - - - _ ·....
I·o-----INHIBIT--_

PRESET

CLEAR

ASYNC
CLEAR

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-69

TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
maximum ratings. recommended operating conditions. and electrcical characteristics
See Table IV, page 2-6.

timing requirements (supplement to recommended operating conditions)
SN54HC160

SN74HC160

THRU
SN54HC163

THRU
SN74HC163

MIN
fclock
tw

NOM

MAX

MIN

NOM

UNIT

MAX

Clock frequency
Pulse duration

MHz
ClK high or low
'HC160, 'HC161

I 'HC160, 'HC162
I'HC161, 'HC163
ClR low

ns

A,B,C,D

tsu

Setup time
before ClKI

I'HC160, 'HC161

ENP,ENT
'HC160, 'HC161

I'HC162, 'HC163
ClR inactive

ns

I ClR 'ow
'HC162, 'HC163 I ClR high (inactive)
th

II

Hold time, all synchronous inputs after ClKI

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V,
Cl=15pF,
Rl = 2 kO,

VCC:: 4.5 V to 5.5 V,
CL:: 50 pF

TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX

UNIT

SN54HC'

SN74HC'

MIN MAX

MIN MAX

f max
tplH
tpHl
tplH
tpHl
tplH

MHz
ClK

RCO

ns

ClK

AnyO

ns

ENT

RCO

ns

tpHl

ClR

AnyO

ns

tPHl

ClR

tpHl

RCO

ns

Power dissipation capacitance

No load. TA = 25°C

NOTE 1: For load circuit and voltage waveforms. see page 1·14.

3-70

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

pF typ

TYPES SN54HC160 THRU SN54HC163
SN74HC160 THRU SN74HC163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
TYPICAL APPLICATION DATA
N-BIT SYNCHRONOUS COUNTERS
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter. The
'HC160 and 'HC162 wi" count in BCD, and the 'HC161 and 'HC163 wi" count in binary. Virtually any count mode
(modulo-N, N1-to-N2, N1-to-maximum) can be used with this fast look-ahead circuit.
LSB
CLR " " CT=O CTR
LOAD
Ml
ENT
G3
3CT MAX
ENP
G4
CLK
., C5/2.3,4+

CLEAR (L)

r--.

COUNT (H) AND
DISABLE (L)

RCO

roo-

r

LOAD III

COUNT (H) AND
DISABLE (L )-~

CLOCK - - - I

A - 1,50

(1)

I--QA

B-

(2)

I--QB

C-

(3)

t--Qc

0-

(4)

I--Qo

CLR ,.....

CT=O CTR

LOAD ,.....

Ml

ENT

G3

ENP
CLK

MAX

3CT

~

G4
,

C5/2,3,4+

r

A - 1,50

(1)

B-

(2)

I--QB

C-

(3)

I--Oc

0-

(4)

r--Oo

CLRr--.
LOAO~

ENT
ENP
CLK

CT=O

..

I--QA

CTR

Ml
G3

3CT

MAX

-RCO

r---

G4

.,

C5/2,3,4+

,..

A - 1,50

(1)

B-

(2)

r---OB

C-

(3)

r---Oc

0-

(4)

r--Qo

r---QA

CLR.J'""-.. CT=O CTR
LOAD ,.....
ENT
ENP
CLK

Ml
G3

3CT

MAX

RCO

r---

G4

t;"'

C5/2,3,4+

r

A - 1,50

(I)

r--OA

B-

(2)

I - - OB

C-

(3)

I - - Qc

0-

(4)

t - - 00

--------------~v~-------------­
TO MORE SIGNIFICANT STAGES
TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-71

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
02684. DECEMBER 1982

• AND-Gated (Enable/Disable) Serial Inputs

SN54HC164 ... J PACKAGE
SN74HC164 ... J OR N PACKAGE
(TOPVIEWI

• Fully Buffered Clock and Serial Inputs
• Direct Clear

A
S
OA
Os
Oc
OD
GND

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
• Dependable Texas Instruments Quality
and Reliability

VCC
OH
OG
OF
OE
ClR
ClK

description
These 8-bit shift registers feature AND-gated serial
inputs and an asynchronous clear. The gated serial
inputs (A and B) permit complete control over incoming data as a low at either input inhibits entry of
the ~ew data and resets the first flip-flop to the low
level at the next clock pulse. A high-level input
enables the other input. which will then determine
the state of the first flip-flop. Data at the serial
inputs may be changed while the clock is high or
low. provided the minimum setup time requirements
are met. Clocking occurs on the low-to-high-Ievel
transition of the clock input.

..

SN54HC164 ... FH OR FK PACKAGE
SN74HC164 ... FH OR FN PACKAGE
(TOPVIEWI

u

u

U J:

mO

3 2 1 2019

OA
NC
Os
NC
Oc

The SN54HC164 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC164 is characterized for operation from -40°C to 85°C.
NC -

6
7
8

No internal connection

logic symbol

FUNCTION TABLE
OUTPUTS

INPUTS
CLEAR

CLOCK

A

B

L

X

X

X

H

L

X

X

H

t

H

H

t

L

H

t

X

OA
L

0B··· 0H
L
L
aBO

OHO

H

OAO
H

OAn

°Gn

X

L

QAn

L

L

QAn

°Gn
QGn

Ci:R
ClK
A

H - high level Isteady statel. L ~ low level (steady state)
X ::. irrelevant (any input, including transitions)

t

= transition from low to high level

0AO. 0SO. 0HO

0

the level of 0A. OS. or 0H. respectively. before the

indicated steady-state input conditions were established.
0An' 0Gn = the level of 0A or 0G before the most-recent t transition
of the clock; indicates a one-bit shift.

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV. page 2-6.

PRODUCT PREVIEW

3· 72

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DAllAS. TEXAS 75265

TYPES SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
typical clear. shift. and clear sequences

u

CLEAR-U
I
I

SERIAL {
INPUTS

L-Jl~

A

________~--------_

S _ _:-,_ _ _ _---J
I

I

. CLOCK

I

---,
---,
---,

I

~~------~---------­
~------~-------­
QC __
_____________
~~--~-------QD==-~l~________~_____
~~--------QA ___ ...1.1_ _ _ _ _ _ _ _ _---'

QS ___ ...II_ _ _ _ _ _ _ _ _ _ ___J
~I

~

_...I

---,

OUTPUTS

Ln_________

QE ___ ~I~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___J

---,

I
I

QF ___ ~I~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___J

I

---,

QG ___

~I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___J
I

---,

n'

QH ___ ...II_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

~

_ _ _ _ _ _ __

..

I

CLEAR

CLEAR

timing requirements (supplement to recommended operating conditions)
SN74HC164

SN64HC164
MIN
fclock

MAX

MIN

NOM

UNIT
MAX
MHz

Clock frequency
CLR low
CLK high

Pulse duration

tw

NOM

ns

CLK low
Setup time
tsu

Data
ClR inactive

before CLKI

ns

Hold time. data after ClKI

th

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

f max
tpHl
tPlH
tpHl
Cpd

VCC: 6 V.
CL: 16 pF.

VCC: 4.6 V to 6.6 V.

FROM
(INPUT)

TO
(OUTPUT)

ClR

Any 0

os

ClK

AnyO

os

CL: 50 pF
RL: 2 kn.
SN54HC164 iSN74HC164
TA: 25°C
TA: 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz

Power dissipation capacitance

No load. TA: 25°C

pF typ

NOTE 1: For load CirCUit and voltage waveforms. see page 1·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-73

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC165, SN74HC165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
02684. DECEM8ER 1982

SN54HC165 ... J PACKAGE
SN74HC165 ... J OR N PACKAGE

• Complementary Outputs
• Direct Overriding Load (Data) Inputs

(TOP VIEW)

• Gated Clock Inputs

SH/LD
ClK
E

• Parallel-to-Serial Data Conversion
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic and
Ceramic DIPs

F

G
H
OH
GND

• Dependable Texas Instruments Quality and
Reliability
description

SN54HC165 ... FH OR FK PACKAGE
SN74HC165 ... FH OR FN PACKAGE

The 'HC165 is an B-bit serial shift register that,
when clocked, shifts the data toward serial output
QH. Parallel-in access to each stage is provided by
eight individual direct data inputs that are enabled
by a low level at the SH/LD input. The 'HC165 also
features a clock inhibit function and a complementary serial output QH.

II

Clocking is accomplished by a low-to-high transition
of the ClK input while SH/Lo is held high and ClK
INH is held low. The functions of the ClK and ClK
INH (clock inhibit) inputs are interchangeable. Since
a low ClK input and a low-to-high transition of ClK
INH will also accomplish clocking, ClK INH should
be changed to the high level only while the ClK
input is high. Parallel loading is inhibited when
SH/W is held high. The parallel inputs to the
register are enabled while SH/LD is low independently of the levels of ClK, ClK INH, or SER inputs.

VCC
ClK INH
D
C
B
A
SER
QH

(TOPVIEWI
I
~

~I~

U~

..JIU U..J

ucnz >u
3

1 2019

2

E

D
C
NC
B
A

NC
G
H

IO U

10

t§ z

Ie:::

0 ~

NC - No internal connection

logic symbol
SRGB

The SN54HC165 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC165 is characterized for operation from -40°C to 85°C.

SH/LD (1)

FUNCTION TABLE

SER
A

INPUTS

SHim CLK
l

X

H

H

H
H

X

H

ClK

B

FUNCTION

C

INH

X
X

PARAllEL lOAD

D

NO CHANGE

E

NO CHANGE

F

l

H
t

SHIFT

G

t

l

SHIFT

SHIFT - content of each internal register
shifts toward serial output QH. Data at serial
input is shifted into first register.

H

(4)
(5)
(6)

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.
Copyright

PRODUCT PREVIEW

3-74

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

~'1982

by Texas Instruments Incorporated

TYPES SN54HC165, SN74HC165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
typical shift. load. and inhibit sequences
ClK

Jl..J"1.S1S1..J"LS-LJ"1..J"LI1..J"lJUL

ClKINH
SER ____________~-------------------------------SH,COf-j

A~____~_______________________________
B

I

l

C~~__~_______________________________

OIL
I

DATA

E~~____~________________________________
I

l

I

G~----~----------

__________________

H~_ _ _ _~_____________________________

I

I

l--

L

II

L

INHIBIT

--1-------

SERIAL SHIFT - - - - - - - - - -

lOAD

timing requirements (supplement to recommended operating conditions)

MIN
fclock

SN54HC165
NOM
MAX

Clock frequency

tw

Pulse duration

tsu

Setup time

th

Hold time. SER after elK!

MIN

SN74HC165
NOM
MAX

UNIT
MHz

SHILD low
elK high
elK low
SHILD high before elKI
SER before elK!
elK INH before elK!
Data before SHILD!

ns

ns

ns

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-75

TYPES SN54HC165, SN74HC165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5 V.
CL=15pF.
RL = 2 kO

Vcc = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC165 SN74HC165
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
MHz

f max

tpLH
tpHL
tpLH
tpHL
tplH
tpHL
tPlH

•

3-76

tPHl
tplH
tpHL
tplH
tpHl
Cpd

QH
SH/lli

ns
'OH
QH

ClK

ns

OH
QH
H

ns
OH
Power dissipation capacitance

No load. TA = 25°C

NOTE 1: For load circuit and voltage waveforms. see page 1 ·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

pF typ

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC166, SN74HC166
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
02684. OECEM8ER 1982

• Synchronous Load

SN54HC166 ... J PACKAGE
SN74HC166 ... J OR N PACKAGE
(TOP VIEW)

• Direct Overriding Clear
• Parallel to Serial Conversion
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

B

C
D
CLK
INH
CLK
GND

description
The' HC166 parallel-in or serial-in. serial-out registers feature
gated clock inputs and an overriding clear input. The parallel-in
or serial-in modes are established by the shift/load input. When
high. this input enables the serial data input and couples the
eight flip-flops for serial shifting with each clock pulse. When
low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel
loading, serial data flow is inhibited. Clocking is accomplished
on the low-to-high-Ievel edge of the clock pulse through a twoinput positive NOR gate permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either of the clock
inputs high inhibits clocking; holding either low enables the
other clock input. This, of course, allows the system clock to be
free-running and the register can be stopped on command with
the clock input. The clock-inhibit input should be changed to the
high level only when the clock input is high. A direct clear input
overrides all other inputs. includi,ng the clock, and sets all flipflops to zero.
The SN54HC166 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC166
is characterized for operation from -40°C to 85°C.

VCC
SH/LD
H
QH
G

SER
A

E
CLR

SN54HC166 ... FH OR FK PACKAGE
SN74HC166 ... FH OR FN PACKAGE
(TOP VIEW)

ffi

u

ul~

U J:

4:u>Z>U>

3 2 1 2019

B
C
NC

II

H

QH
NC
G

D
CLK INH

14
9 10111213

NC -

No internal connection

logic symbol

FUNCTION TABLE
INPUTS
CLEAR

SHIFTI

CLOCK

INTERNAL

CLOCK SERIAL

PARALLEL

LOAD

INHIBIT

L

X

X

X

X

A ... H
X

H

X

L

L

X

X

H

L

L

t

X

OUTPUTS

CLR
OUTPUT

. SH/LD

°H

°A
L

°B
L
GBO
b

GHO

a. .. h

GAO
a

L

ClK INH
CLK

h

H

H

L

t

H

X

H

GAn

GGn

H

H

L

t

L

X

L

GAn

GGn

H

X

H

t

X

X

GAO

GBO

GHO

SER
A
B
C

0
E
F
G
H

('41

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV. page 2-6.

PRODUCT PREVIEW

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265

~1982

by Texas Instruments Incorporated

3-77

TYPES SN54HC166, SN74HC166
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
typical clear, shift, load, inhibit, and shift sequences
CLOCK

CLOCK

INHIBIT-'~__7-________________________~__----~r-----l~---------------------------I

I

CLEAR

--UI
I

SERIAL INPUT

I

I

~______________________~______~____~--~------------------------I

I

U

SHIFT/LOAD

I

A ________________________________~--~~~----~~--------------------------L,
I

--7-~------------------------~~--~~~----~~--------------------------­
,

PARALLEL
INPUTS

D__~~------------------------~------~L~,--------~---------------------------~~------------------------~----~~~----~~--------------------------L:

..

G __

OUTPUrQH

~~------------------------~---J~~----~~-------------------------

H::J
__~I~~----------------------------~
____________________________
_J

t-----SERIAL SHIFT----CLEAR

-f J.-INHIBIT~ I---- SERIAL S H I F T - - - - LOAD

timing requirements (supplement to recommended operating conditions)
SN54HC166
MIN
fclock

NOM

MAX

MIN

SN74HC166
NOM
MAX

UNIT
MHz

Clock frequency
CLR low

tw

Pulse duration

Setup time
tsu

before CLK!

SH/LD low
CLK high
CLK low
SH/LD high before CLKI

ns

SER before CLK!
CLK INH before CLK!
Data before SH/LD!

ns

CLR inactive
th

3-18

ns

Hold time, SER after CLK!

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC166, SN74HC166
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

VCC=5V.
Cl=15pF.
Rl = 2 kCl,

Vcc = 4.5 V to 5.5 V.

FROM
(INPUT)

TO
(OUTPUT)

ClR

QH

ns

ClK

QH

ns

SH/i])

QH

ns

H

QH

ns

Cl = 50 pF

UNIT

SN54HC166 SN74HC166
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
MHz

f max
tPHl
tplH
tpHl
tplH
tpHL
tpLH
tPHl

Power dissipation capacitance

No load. TA = 25°C

pF typ

NOTE t: For load circuit and voltage waveforms. see page 1 -14.

II

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

3-79

TYPES SN54HC173, SN74HC173
4-81T D-TYPE REGISTERS WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

High-Current 3-State Outputs Interface Directly with
System Bus or Can Drive up to 15 LSTTL Loads

•

Gated Output-Control Lines for Enabling or
Disabling the Outputs

•

Fully Independent Clock Virtually Eliminates
Restrictions for Operating in One of Two Modes

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

SN54HC173 ... J PACKAGE
SN74HC173 ... J OR N PACKAGE
ITOPVIEW)
M

N

•

CLK
GNO

Dependable Texas Instruments Quality and Reliability

description

•

10
20
3Q
40

The 'HC173 four-bit registers include Ootype flip-flops featuring
totem-pole three-state outputs capable of driving highly capacitive
or relatively low-impendance loads. The high-impedance third
state and increased drive provide these flip-flops with the capability
of being connected directly to and driving the lines in a busorganized system without need for interface or pull-up components.

VCC
CLR
10
20
3D

40

G2
G1

SN54HC173 ... FH OR FK PACKAGE
SN74HC173 ... FH OR FN PACKAGE
(TOP VIEW}

Gated enable inputs are provided on these devices for controlling
the entry of data into the flip-flops. When both data-enable inputs
are low, data at the 0 inputs are loaded into their respective flipflops on the next positive transition of the clock input. Gate output
control inputs are also provided. When both are low, the normal
logic states (high or low levelsl of the four outputs are available for
driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output control input. The outputs then present a high impedance
and neither load nor drive the bus line. Detailed operation is given
in the function table.

10
20

10
20

NC

30

NC
3D

40

40

NC - No internal connection

The SN54HC173 is characterized for operation over the full military
temperature range of -55°C to 125°C. The SN74HC173 is characterized for operation from -40°C to 85°C.

logic symbol

FUNCTION TABLE

CLEAR

CLOCK

H
L
L
L
L
L

X

INPUTS
DATA ENABLE
Gl
G2

L
I
I
I

I

X
X
H

X
L
L

X
X
X
H
L
L

DATA
D

OUTPUT
0

X
X
X
X

Clo
Clo
Clo

L
H

L
H

L

When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however sequential
operation of the flip-flops is not affected.

10
20

30
40

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.
Copyright m 982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-80

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC173, SN74HC173
4-81T O-TYPE REGISTERS WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN54HC173
MIN
fclock

MIN

NOM

UNIT

MAX
MHz

ClK high or low

ns

ClR low

Setup time before ClK!

tsu

SN74HC173
MAX

Input clock frequency
Pulse duration

tw

NOM

G1 and G2 low
Data

ns

ClR inactive
Hold time after ClK!

th

G1 and G210w
Data

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC =5 V.
Cl = 45 pF,

VCC = 4.5 V to 5.5 V.

FROM
(INPUT)

TO
(OUTPUT)

ClR

Any

ns

ClK

Any

ns

tpZH
tpZl

MorN

Any

ns

tpHZ
tpLZ

MorN

Any

ns

PARAMETER

f max
tpHl
tplH
tpHl

See Note 1

Rl = 6670,
SN54HC173 SN74HC173
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz

Power dissipation capacitance

II

pF typ

NOTE 1: For load circuit and voltage waveforms. see.page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-81

,HIGH-SPEED
CMOS LOGIC

TYPES SN54HC174, SN54HC175, SN74HC174, SN74HC175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
02684, DECEMBER 1982

•

'HC174 Contains Six Flip-Flops with Single-Rail
Outputs

•

'HC175 Contains Four Flip-Flops with Double-Rail
Outputs

•

Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC174", J PACKAGE
SN74HC174, , ,J OR N PACKAGE
ITOPVIEW)
VCC

60

-......_ _.-r- CLK

SN54HC174, , , FH OR FK PACKAGE
SN74HC174 , , , FH OR FN PACKAGE
(TOP VIEW)

5 u 80
01
.. uZ>co

description

..

3 2

These monolithic, positive-edge-triggered D-type flip-flops
have a direct clear input and the 'HC175 features complementary ou'tputs from each flip-flop.

10
20

Information at the 0 inputs meeting the setup time requirements is transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related to the
transition time of the positive-going edge of the clock
pulse. When the clock input is at either the high or low
level, the 0 input signal has no effect at the output.

2019
60
50

4
5
6

NC

7

50
40

8

9 10111213
OOu~O

t'laZd~

SN54HC176 .. , J PACKAGE
SN74HC175. , ,J OR N PACKAGE
(TOP VIEW)

The SN54HC174 and SN54HC175 are characterized for
operation over the full military temperature range of
-55°C to 125°C, The SN74HC174 and SN74HC175 are
characterized for operation from -40°C to 85°C.

CLR

10

10
10
20
2Q

20
GNO-......_ _...rFUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
CLR CLK
0
L
H
H
H

OUTPUTS

a

at

f

H
L

L
H
L

H
L
H

L

X

00

00

x

X

f

SN54HC175 " ,FH OR FK PACKAGE
SN74HC176 , . , FH OR FN PACKAGE
(TOP VIEW)

e::

u

.. U Z

>

I

O..J U UO
~

40
40
NC
3D

t'HC175 only

3Q
oou~o

NaZdt'l

NC -

3-82

This document contains information on a
product under development, Texas Instruments reserves the right to change or discontinue this product without notice.

No internal connection

Copyright'£'1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC174, SN54HC175, SN74HC174, .SN74HC175
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
logic symbols
'HC174

'HC175
ClK
(2) 10
(5)
20

20
3D (6)

(7)

(11)

(10)

50 (13)

(12)

60 (14)

(I!.')

40

10

10

30

10
20

20

40

20

50

30

3D

60

30
40

40

Pin numbers shown are for J and N packages.

40

maximum ratings. recommended operating conditions. and electrical characteristics
'HC174 See Table IV, page 2-6.
'HC175 See Table II, page 2-4.

timing requirements (supplement to recommended operating conditions)
SN74HC174

SN54HC174
SN54HC175
MIN
fclock

NOM

SN74HC175
MAX

MIN

NOM

MAX

UNIT

II

MHz

Clock frequency
ClR low
Pulse duration

tw

ClK high

ns

ClK low
tsu

Setup time
before ClKI

Data
ClR inactive

th

Hold time, data after ClKI

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC=5V,
CL=15pF,
PARAMETER

f max
tplH
tpHl
tPlH
tpHl

FROM
(INPUT)

TO
(OUTPUT)

VCC = 4.5 V to 5.5 V,
CL = 50 pF

RL = 2 kO,
SN54HC174 SN74HC174
TA = 25°C
SN54HC175 ~N74HC175
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz
ClR
ClK

Any Q ("HC175)

ns

AnyQ
AnyQ
(or Q, 'HC175)

ns

Power dissipation capacitance per flip·flop

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1 ·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DAllAS. TEXAS 75265

3-83

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC189, SN74HC189
64-BIT RANDOM-ACCESS MEMORIES
02684. DECEMBER 1982

•

Organized as 16 Words of Four Bits Each

•

High-Current 3-State Inverting Outputs Can Drive
up to 15 LSTTL Loads

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC189 ... J PACKAGE
SN74HC189 ... J OR N PACKAGE
(TOP VIEW)
AD

•

R/iiil

A2

01
01

A3
04
Q4

Dependable Texas Instruments Quality
and Reliability

02

description
Information to be stored in the memory is written
into the selected address location when the chipselect (S) and the write-enable (R/W) inputs are low.
While the write-enable input is low, the memory
outputs are off (Hi-Z). When a number of outputs are
bus-connected, this off state neither loads nor drives
the data bus; however, it permits the bus line to be
driven by other active outputs or a passive pull-up.

II

VCC
Al

S

'02

03

GNO

03

SN54HC189 ... FH OR FK PACKAGE
SN74HC189 ... FH OR FN PACKAGE
(TOP VIEW)

Rjiiil

4

.01

Q1

5
6
7

02

8

Information stored in the memory(see function table
for input/output phase relationship) is available at
the outputs when the write-enable input is high and
the chip-select input is low. When the chip-select
input is high, the outputs will be off.

NC

A2
A3
NC
04
04

NClUMM
Cl

10 z z 10

The SN54HC189 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC189 is characterized for operation from -40°C to 85°C.

l.!l

NC -

No internal connection

logic symbol

RAM16X4
AO
A1

FUNCTION TABLE

A2

(1)
(15)
(14)

]A~

A3

INPUTS
FUNCTION
Write
Read
Inhibit

CHIP

S

SELECT

WRITE
ENABLE

L

L

L
H

H

X

OUTPUTS

R/iii

Z

01

Complement

02

of Data

03

Entered

04

Z
Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions. and electrical characteristics
See Table III, page 2-5.

Copyright -91982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-84 !~~~~:tC~~~~td~~~:~~n~~~!~~~:~~o~n~t~u~
ments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC189, SN74HC189
64-BIT RANDOM-ACCESS MEMORIES
timing requirements (supplement to recommended operating conditions)

MIN
tw

SN54HC189
MAX
NOM

SN74HC189
MIN

NOM

UNIT

MAX

Pulse duration. R/W low

ns

Address before R/WI
tsu

ns

Data before R/WI

Setup time

Chip-select before R/WI
Address after R/WI
th

Data after R/WI

Hold time

ns

Chip-select after R/WI

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V,
VCC = 4.5 V to 5.5 V.
CL=45pF.
See Note 1
RL = 6670.
SN54HC189 SN74HC189
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX

UNIT

ta/ad)

A

Any

ns

tatS)
tsr

S

Any

ns

S

Any

R/W

Any

tdis

ns
ns

Power dissipation capacitance

•

pF typ

NOTE 1: For load circuit and voltage waveforms, see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-85

•

3-86

THIS PAGE
INTENTIONALLY LEFT BLANK

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC190, SN54HC191, SN74HC190, SN74HC191
SYNCHRONOUS 4-BIT UP IDOWN DECADE
AND BINARY COUNTERS
02684. DECEMBER 1982

• Single Down/Up Count Control Line
• Look-Ahead Circuitry Enhances Speed of Cascaded
Counters

SN54HC190, SN54HC191 ... J PACKAGE
SN74HC190, SN74HC191 ... J OR N PACKAGE

(TOP VIEW)
B
OB
OA
CTEN

• Fully Synchronous in Count Modes
• Asynchronously Presettable with· Load Control
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

DIU

Oc
OD
GND

• Dependable Texas Instruments Quality and Reliability
description

VCC
A
ClK
RCO
MAXIMIN
lOAD
C
D

SN54HC190, SN54HC191 ... FH OR FK PACKAGE

The 'HC190 and 'HC191 are synchronous, reversible up/down SN74HC190, SN74HC191 ... FH OR FN PACKAGE
counters. The 'HC190 is a 4-bit decade counter and the 'HC191
(TOP VIEW)
u
is a 4-bit binary counter. Synchronous counting operation is
co
U U
OcoZ>~ 0 t!)

FUNCTION TABLE

NC
NC
B1
NC
B2

INPUTS
GAB

GBA

'HC242

'HC243

L

L

A to B

A to B

H

H

B to A

B to A

H

L

Isolation

Isolation

L

H

Latch A and B

Latch A and B

(A=B)

(A=B)

NC -

No internal connection

logic symbol
'HC242

'HC243

GBA

GAB
Al

Bl

A2

62

A3

63

A4

B4

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions. and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW

3-104

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • CALLAS, TexAS 75265

TYPES SN54HC242, SN54HC243, SN74HC242, SN74HC243
QUADRUPLE BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
'HC242 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
VCC=6V.
CL =45 pF.
RL =6670.

VCC=4.6 V to6.6 V.

FROM
(INPUT)

TO
(OUTPUT)

AorB

BorA

ns

GAB

B

ns

GAB

B

ns

tpZH
tpZL

GBA

A

ns

tPHZ
tpLZ

GBA

A

ns

PARAMETER

tpLH
tPHL
tpZH
tpZL
tpHZ
tpLZ

Cpd

I

See Note 1

UNIT

SN64HC242 ~N74HC242
TA:: 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

..

pF typ

Power dissipation capacitance per transceiver

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

'HC243 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

tPLH
tPHL
tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ
Cpd

VCC=5 V.
CL=46 pF.

VCc:: 4.6 V to 6.6 V.

FROM
(INPUT)

TO
(OUTPUT)

AorB

BorA

ns

GAB

B

ns

GAB

B

ns

GBA

A

ns

GBA

A

ns

See Note 1

UNIT
RL=667Cl.
SN64HC243 SN74HC243 .
TA:: 26°C
TA:: 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dissipation capacitance per transceiver

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012

~

DALLAS. TEXAS 75265

3-105

TYPES SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEMBER 1982

• 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers

SN54HC244 ... J PACKAGE
SN74HC244 ... J OR N PACKAGE
(TOP VIEW)

• High-Current Outputs Can Drive up to 15 LSTTL Loads
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability
description
These octal buffers and line drivers are designed specifically to
improve both the performance and density of the three-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Taken together with the 'HC240 and
'HC241, these devices provide the choice of selected combinations of inverting outputs, symmetrical G (active-low input
control) inputs, and complementary G and Ginputs.

..

The SN54HC244 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC244
is characterized for operation from -40°C to 85°C .

1(;
lAl
lA3

VCC
lVl
2A4
lV2
2A3
lV3
2A2
lV4
2Al

2<3

SN54HC244 ..• FH OR FK PACKAGE
SN74HC244 •.. FH OR FN PACKAGE
(TOP VIEW)

lYl
2A4
lY2
2A3
lV3

lA2
2V3
lA3
2Y2
lA4

logic symbol

lA2

1G"
lAl
2V4
lA2
2V3
lA3
2V2
lA4
2Vl
GND

(18) lVl
(16)

(14)

lA4

lY2
lV3
lY4

2(;
2Al

2Vl

2A2

2Y2

2A3

2Y3

2A4

2Y4

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrica! characteristics
See Table III, page 2-5.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-106

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC244, SN74HC244
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC=6V.

Vcc = 4.6 V to 6.6 V.
CL= 46 pF.
See Note 1
RL = 6670.
SN64HC244 SN74HC244
TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tpLH
tpHL

A

Y

ns

G

y

ns

G

y

ns

tPZH
tpZL
tpLZ
tpHZ

Power dissipation capacitance per buffer

UNIT

pF 1yp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

II

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-107

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
02684. DECEMBER 1982

•

High-Current 3-5tate Outputs Drive Bus Lines
Directly or Up to 15 L5TTL Loads

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC246 •.. J PACKAGE
SN74HC246 ... J OR N PACKAGE
(TOPVIEWI

Dependable Texas Instruments Quality and Reliability

desc~iption

These octal bus transceivers are designed for synchronous twoway communication between data buses. The control function
implementation minimizes external timing requirements.
The devices allow data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic level at
the direction control (DIR) input. The enable input (G) can be
used to disable the device so that the buses are effectively
isolated.

II

DIR

Vee

A1
A2
A3
A4
A5
A6
A7
A8

G
B1
B2
B3
B4
B5

B6
B7
B8

GND

SN54HC246 ... FH OR FK PACKAGE
SN74HC246 ... FH OR FN PACKAGE
(TOP VIEW)

~

a:: U

<0

~I(!)

3

The SN54HC245 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC245
is characterized for operation from -40°C to 85°C.

A3

4

A4

A5

5
6

A6
A7

8

B1
B2
B3
B4

7

B5

9

logic symbol

FUNCTION TABLE
CONTROL
INPUTS
DIR
G
L
L
H
L
H
X

OPERATION
B data to A bus
A data to B bus
Isolation

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III, page 2-5.

PRODUCT PREVIEW

3-108

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAsINSTRUMEN~S
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC245, SN74HC245
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

Vcc= 5 V,
CL=45 pF,
RL = 6670,

VCC = 4.5 V to 5.5 V,
See Note 1

UNIT

SN54HC245 SN74HC245
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tPHL
tpZH
tpZL
tpHZ
tpLZ

AorB

BorA

ns

G

AorB

ns

G

AorB

ns

Power dissipation capacitance per transceiver

No load, TA = 25°C

pFtyp

NOTE 1: For load circuit and voltage waveforms, see page 1-14.

II
I

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS, TEXAS 15265

3-109

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
02684, DECEMBER 1982

• 3-State Version of 'HC151
• High-Current 3-State Outputs Interface Directly
with System Bus or Can Drive up to 15 LSTTL Loads'

SN64HC261 •.. J PACKAGE
SN74HC261 , , . J OR N PACKAGE
(TOP VIEW)

• Performs Parallel-to-Serial Conversion
• Complementary Outputs Provide True and Inverted
Data
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

03
02
01

16

DO

13

Y

12

Vce
04
05
06
07

11

A

10

B
C

15
14

W

G

• Dependable Texas Instruments Quality and Reliability

GNO

9

description
These data selectors/multiplexers contain full binary decoding
to select one-of-eight data sources and feature strobe-controlled
complementary three-state outputs.

•

SN64HC261 . , • FH OR FK PACKAGE
SN74HC261 ... FH OR FN PACKAGE
(TOP VIEW)

The three-state outputs can interface with and drive data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high-impedance state). the low-impedance
of the single enabled output will drive the bus line to a high or
low logic level. Both outputs are controlled by the strobe (G). The
outputs are disabled when G is high.

N

c")

U

U
Uv

ooz>o
01

05
06
NC
07

DO
NC

The SN54HC251 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC251
is characterized for operation from -40°C to 85°e.

Y
W
It!) 0

U U CD

zz

t!)

NC - No internal connection

FUNCTION TABLE
INPUTS

OUTPUTS

STROBE

SELECT

w

Z

Z

G

Do
i51

A

C

B

A

G

X

X

X

H

L
L

L

L

L

DO

L

H

L

L

H

L
H

L

L
H

L

L
H

L

01
02
03
04
05
06
07

L

H

H

L

H

L

H

H

H

H

L
L
L

logic symbol

V

MUXI>

B

c

52
03
54
Os
06
07

00
01

EN

:)G~
0

"il
"il

02

5)
(6)

Y

W

03
04
05

DO, 01 ... 07 = the level of the respective 0 input

06
07

6

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III. page 2-5.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-110

This document contains information on a
product under development. TeKas Instruments reserves the right to change or discontinue this product without notice.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC251, SN74HC251
DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
Vcc= 6 V,
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CL=46 pF,
RL = 6670,

VCC = 4.5 V to 6.5 V,
See Note 1

UNIT

SN54HC251 SN74HC251
TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tPHL
tplH
tPHL
tpLH
tPHL
tPLH
tPHL
tpZH
tpZL
tpZH
tpZL
tPHZ
tpLZ
tpHZ
tpLZ

A, BorC

y

ns

A. BorC

W

ns

Any 0

y

ns

Any 0

W

ns

G

y

ns

G

W

ns

G

y

ns

G

w

ns

Power dissipation capacitance

pF typ

II
!

Cpd

NOTE 1: For load circuit and voltage waveforms. see page 1·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-111

TYPES SN54HC253, SN74HC253
DUAL 4-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEM8ER 1982

SN54HC253 ..• J PACKAGE
SN74HC253 • , . J OR N PACKAGE
(TOP VIEW)

• 3-State Versions of 'HC153
• High-Current Outputs Drive up to 15 LSTTL Loads
• Permits Multiplexing from N Lines to 1 Line

VCC
2<3
A
2C3
2C2
2C1
2CO
2Y

• Performs Parallel-to-Serial Conversion
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

1C3
1C2
1C1
1CO
1Y
GND

• Dependable Texas Instruments Quality and Reliability
description
Each of these data selectors/multiplexers contains inverters
and drivers to supply full binary decoding data selection to the
AND-OR gates. Separate output control inputs are provided for
each of the two four-line sections.

•

The three-state outputs can interface with and drive data lines
of bus-organized systems, With all but one of the common
outputs disabled (at a high-impedance state) the low-impedance
of the single enabled output will drive the bus line to a high or
low logic level. Each output has its own strobe (<3). The output is
disabled when its strobe is high.

SN54HC253 •.. FH OR FK PACKAGE
SN74HC253 ... FH OR FN PACKAGE
(TOP VIEW)

CO
3

It:) U

U

Ult:)

Z>N

2 1 20 19

A
2C3
NC
2C2
2C1

The SN54HC253 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC253
is characterized for operation from -40°C to 85°C.

>-OU>-O

.... ZZNU
t:)

N

FUNCTION TABLE
SELECT
INPUTS
A
B

X

X

L
L
L
L

L
L

H
H

L
L
H
H

H
H

H
H

DATA INPUTS
CO

Cl

C2

X

X

X

L

X
X

X
X
X
X

H
X
X

X
X

X
X

L

H
X
X
X
X

L
H
X
X

OUTPUT
OUTPUT
CONTROL
V
C3
G

X
X
X
X
X
X
X
L
H

H

Z

L
L
L
L
L
L
L
L

L

NC -

No internal connection

logic symbol

H
L

H
L
H
L
H

16
lCO

"V

lCl

(7)

1Y

lC2
lC3

Address inputs A and B are common to both sections.

2~

2CO
2Cl
2C2 (12)
2C3 (13)

(9)

2Y

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW

3-112

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC253, SN74HC253
DUAL 4-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC=5V.
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CL= 45 pF.
RL = 6670.

Vcc = 4.5 V to 5.5 V.
See Note 1

UNIT

SN54HC253 SN74HC253
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
tPLH
tpHL
tPLH
tPHL
tpZH
tpZL
tPHZ
tpLZ
Cpd

AorB

AnyY

ns

Data (Any C)

Y

ns

G

.y

ns

G

Y

ns

Power dissipation capacitance per multiplexer

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

·11

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-113

TYPES SN54HC257, SN54HC258, SN74HC257, SN74HC258
QUAD 2-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEMBER 1982

•

High-Current 3-State Outputs Interface Directly with
System Bus or Can Drive up to 15 LSTTL Loads

•

Provides Bus Interface from Multiple Sources in HighPerformance Systems

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC257, SN54HC258 .. , J PACKAGE
SN74HC257, SN74HC258 , , ,J OR N PACKAGE
(TOPVIEWI

VCC

·cr

4A
4B
4Y
3A
3B
3Y

2Y
GND

description

..

These devices are designed to multiplex signals from four-bit
data sources to four-output data lines in bus-organized systems,
The 3-state outputs will not load the data lines when the output
control pin (G) is at a high-logic level..

SN54HC257, SN54HC258." FH OR FK PACKAGE
SN74HC257, SN74HC258. "FH OR FN PACKAGE
(TOP VIEW)

~ ~

The SN54HC257 and SN54HC258 are characterized for operation over the full military temperature range of -55°C to 125°C,
The SN74HC257 and SN74HC258 are characterized for operation from -40°C to 85°C.

~I~

U

~

z >1t::J

1B
1Y

NC

FUNCTION TABLE

2A
INPUTS
. OUTPUT
CONTROL

OUTPUT Y
DATA

SelECT

'HC257

2B

'HC258

AlB

A

B

X
L

X
L

L

L

H

X
X
X

H

L

L

H

L

L

H

L

H

X
X

H

H

L

G
H

L

Z

Z

L

H

NC -

No internal connection

logic symbols
'HC258

'HC257

AlB

1A

AlB

1Y

1A

1B

1B

2A

2A

2B

2Y

3B
4B

2Y

2B

3A
4A

1Y

3Y
4Y

3A
3B
4A
48

3Y
4Y

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW

3-114

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC257, SN54HC258, SN74HC257, SN74HC258
QUADRUPLE 2-UNE TO 1-UNE
DATA SELECTORS/MULTIPLEXER WITH 3-STATE OUTPUTS
'HC257 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
VCC= 5 V.
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

CL= 45 pF.
RL = 667n.

VCC = 4.5 V to 5.5 V.
See Note 1

UNIT

TA = 25°C
TA = 25°C . SN54HC257 SN74HC257
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
IPLH
IPHL
IPLH
IpHL
IPZH
IPZL
IPHZ
IpLZ

AorB

AnyV

ns

AlB

AnyV

ns

G

AnyV

ns

G

AnyV

ns

Power dissipation capacitance per multiplexer

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

'HC258 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

..

VCC=5V.

PARAMETER

tPlH
IPHl
IPLH
IPHL
tpZH
tPZL
tPHZ
tPLZ

vcc = 4.5 V to 5.5 V.
CL=45 pF.
See Note 1
RL=667 n.
SN54HC258 SN74HC258
TA=25°C
TA= 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

Aor B

AnyV

ns

AlB

AnyV

ns

G

AnyV

ns

G

AnyV

ns

Power disSipation capacitance per multiplexer

UNIT

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-115

TYPES SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES

HIGH-SPEED
CMOS LOGIC

02"684, DECEMBER 1982

•

a-Bit Parallel-Out Storage Register Performs Serial-toParallel Conversion with Storage

•

Asynchronous Parallel Clear

•

Active-High Decoder

•

Enable Input Simplifies Expansion

•

Expandable for N-Bit Applications

•

Four Distinct Functional Modes

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC259 .. , J PACKAG!:
SN74HC259 ... J OR N PACKAGE

(TOPVIEWI

SO
S1
S2
00
01
02
03

G
D
07
06
05
04

GND

SN54HC259 ... FH OR FK PACKAGE
SN74HC259 . , . FH OR FN PACKAGE

description

II

VCC
CLR

(TOPVIEWI

These 8-bit addressable latches are designed for general purpose
storage applications in digital systems, Specific uses include working registers, serial-holding registers, and active-high decoders or
demultiplexers, They are multifunctional devices capable of storing
single-line data in eight addressable latches, and being a 1-of-8
decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the
clear (ClA) and enable (G) inputs as enumerated in the function
table. In the addressable-latch mode, data at the data-in terminal is
written into the addressed latch. The addressed latch will follow
the data input with all unaddressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous states and are unaffected by the data or address inputs.
To eliminate the possibility of entering erroneous data in the
latches, enable Gshould be held high (inactive) while the address
lines are changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the 0 input with all
other outputs low. In the clear mode, all outputs are low and
unaffected by the address and data inputs.

o

~15

U

(J)Z>U

G

S2
00
NC
01
02

D
NC
07
06
9 10 11 12 13
(")QU' 'co
2D
20
30
3D
4D

The SN54HC273 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC273 is characterized for operation from -40°C to 85°C.

8D
7D
70
60
6D

logic symbol
FUNCTION TABLE
(EACH FLIP-FLOP)
ClK

INPUTS

OUTPUT

CLEAR CLOCK 0

Q

10

(2)

L

X

X

L

20

H

!

H

H

3D

H

!

L

L

40

H

L

X

00

50
60
70
80

(5)
(6)

(9)
(12)
(14)

(151

(17)

(16)

(18)

(191

10
20
30
40
50
60
70
80

Pin numbers shown are for all packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV. page 2-6.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS

INSTRUMENTS

INCORPORATED
POST OFFICE BOX 225012 • DAllAS. TEXAS 75265

3-119

TYPES SN54HC273, SN74HC273
OCTAL O-TYPE FLIP-FLOPS WITH CLEAR
timing requirements (supplement to recommended operating conditions)
MIN
fclock

Setup time
tsu

SN74HC273
MIN

NOM

UNIT
MAX

Clock frequency
Pulse duration

tw

SN54HC273
NOM
MAX

MHz
ClR low
ClK high
ClK low
Data

ns

ns

before ClKI
ClR inactive state
Hold time. data after ClKI

th

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

III

VCC= 5 V.
VCC = 4.5 V to 5.5 V.
Cl= 15 pF.
CL = 50 pF
RL=2kn.
SN54HC273 SN74HC273
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

ClR

Any 0

ns

ClK

AnyO

ns

f max
tpHL
tpLH
tpHl

MHz

Power dissipation capacitance per flip-flop

No load. TA = 25°C

NOTE 1: For load circuit and voltage wayeforms. see page 1-14.

3-120

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pF typ

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC280, SN74HC280
9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
02684, DECEMBER 19B2

•

Generates Either Odd or Even Parity for Nine
Data Lines

•

Cascadable for n-Bits

•

Can Be Used to Upgrade Existing Systems
Using MSIParity Circuits

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC280 , .. J PACKAGE
SN74HC280 ... J OR N PACKAGE
(TOPVIEWI
G
H
NC

Vee
F
E
D
C
B
A

:rEVEN
:rODD
GND

Dependable Texas Instruments Quality
and Reliability

SI'1I54HC280 ... FH OR FK PACKAGE
SN74HC280 ... FH OR FN PACKAGE
(TOP VIEW)

description
These universal. monolithic. nine-bit parity generators! checkers feature odd and even outputs to facilitate operation of either odd or even parity application.
The word-length capability is easily expanded by
cascading.

..

E

NC
NC

The SN54HC280 is characterized for operation over
the full military temperature range of -55°C to
125°C. The'SN74HC280 is characterized for operation from -40°C to 85°C.

NC
D

NC

NC
:r EVEN

C
00

oz
O~

1-1

NC -

No internal connection

logic symbol

A
B

c

FUNCTION TABLE

0

NUMBER OF INPUTS A
THRU I THAT ARE HIGH

E

OUTPUTS
:rEVEN
:rOOD

0,2.4.6,8
1.3,5,7.9

H
L

G

L
H

H

(8)

2k

(9)

(10)
(11)

(5)

(13)
/1)

~

EVEN

(12)
(6)

~

000

(2)
(4)

Pin numbers shown are for J and N packages,

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV. page 2-6.

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-121

TYPES SN54HC280, SN74HC280
9-81T ODD/EVEN PARITY GENERATORS/CHECKERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

VCC=5V.
CL = 15 pF.
RL = 2 kO.

TO
(OUTPUT)

Vcc = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC280 SN74HC280
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
tPLH
tpHL

Data

I Even

ns

tPLH
tpHL

Data

I Odd

ns

Power dissipation capacitance

No load. TA = 25°C

NOTE 1: For load circuit and voltage waveforms. see page 1-14 .

..

3-122

TEXAS

INSTRUMENTS

INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

pFtyp

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC299, SN74HC299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
02684, DECEMBER 1982

•

Multiplexed 1/0 Ports Provide Improved Bit
Density

•

Four Modes of Operation: Hold (Store). Shift
Right. Shift Left. and Load Data

•

50
G1
G2

High-Current 3-State Outputs Drive Bus Lines
Directly or up to 15 LSTTL Loads

•

Can Be Cascaded for N-Bit Word Lengths

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC299 ... J PACKAGE
SN74HC299 •.. J OR N PACKAGE
(TOP VIEW)
VCC
51
5l

G/OG

A/OA

°H'
H/OH
F/OF
0/0 0

°A'
ClR
GND

S/OS
ClK
5R

E/OE

C/OC

Dependable Texas Instruments Quality
and Reliability

SN54HC299 ... FH OR FK PACKAGE
SN74HC299 ... FH OR FN PACKAGE
(TOP VIEW)

description

u

These eight-bit universal registers feature multiplexed
liD ports to achieve full eight-bit data handling in a single
20-pin package. 'HC299 applications are as stacked or
push-down registers, buffer storage, and accumulator
registers.

'" - 0(/)
l(!ll(!l

•

3 2 1 2019

G/OG

Two function-select inputs and two output control inputs
can be used to choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by taking
both function-select lines, SO and 51, high. This places
the three-state outputs in a high-impedance state, which
permits data that is applied on the liD ports to be clocked
into the register. Reading out of this register can be
accomplished while the outputs are enabled in any mode.
A direct overriding input is provided to clear the register
whether the outputs are enabled or off. Taking either of
the output controls, <31 or G2, high disables the outputs
but this has no effect on shifting or storage of data.

>u(/)
5l

E/OE

Ow

C/OC
A/OA

H/OH
F/OF

OA'

0/0 0

logic symbol

The SN54HC299 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC299 is characterized for operation from -40°C to
85°C.

(81

0A'

(171

Ow

Pin numbers shown are for J and N packages.

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DAL.L.AS. TeXAS 75265

3-123

TYPES SN54HC299,SN74HC299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
FUNCTION TABLE
INPUTS/OUTPUTS

INPUTS
MOOE

FUNCTION OUTPUT
CLEAR

SELECT CONTROL
Sl

Clear

Hold
Shilt Right

L
L
L •
H

H
H

X
L
H

SQ
L

ill t

X

L
L

CLOCK

~2t
L

SERIAL

OUTPUTS

AlQA 8/Q8C/QCO/QOE/QE F/QF G/QGH/QH

QA'

QH'

SL SR
X
X

X
X

X
X

X
X

X
X

X
X

L
L

L
L

L
X

H
L

X
L

L
X
L

X

L

L

L

X

X

L
L

H
H

L

I

X

H

L

L
L

I

X

L

L

OAn

H

L

L

L

I

H

X

OSn

OCn

L

L
L

X

X

L
X

OAO
OAO
H

OBO

OCO

OSO

OCO
OSn

OAn

L
L

L

L

L

L
X

L
X

L
L

L

X

X

L
X

L

L
L

000
000

OEO

OFO

OGO

OHO

OAO

OHO

OEO

OFO

OGO

OHO

OCn

OOn

OEn

OFn

°Gn
°Gn
H

OAO
H

OHO
.OGn

L
OSn aCn OOn OEn OFn
OGn
H
aO n OEn OFn °Gn OHn
°Sn
I
H
L
L
X OSn aCn OOn aEn OFn aGn aHn
L
H
L
L
L
aS n
I
X
h
d
Load
H
H
H
X
X
X
b
c
e
I
g
h
a
a
tWhen one or both output controls are high the eight input/output terminals are disabled to the high·impedance state; however, sequential
Shilt Left

H
H

operation or clearing 01 the register is not affected.

..

a ... h = the level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip·flop outputs are isolated from the
input/output terminals.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

timing requirements (supplement to recommended operating conditions)
SN64HC299
MIN
fclock

NOM

MAX

Clock frequency

MIN

SN74HC299
NOM
MAX

UNIT
MHz

ClK high
tw

Pulse duration

ClK low

ns

ClR low

tsu

Setup time before ClKI

Select
High-level data

ns

low-level data
CLR inactive-state

th

3-124

Hold time after ClKI

Select

ns

Data

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFice BOX 225012 • DALLAS, TexAS 75265

TYPES SN54HC299, SN74HC299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

Vcc= 6 V.
CL = Note 2,
RL = Note 2,

VCC = 4.6 V to 6.6 V.
See Note 1

UNIT

TA = 26°C

SN64HC299 SN74HC299
TA=26°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
MHz

f max

tplH
tpHl
tPHL
tplH
tpHl
tpHl
tpZH
tpZL
tPHZ
tpLZ
tPZH
tpZL
tpHZ
tplZ
Cpd

ns

ClK

0A' orOH'

ClR

°A'orOH'

ns

ClK

OA thru OH

ns

ClR

OA thru OH

ns

Gl,G2

OA thru OH

ns

G1,(32

OA thru OH

ns

50,51

OA thru OH

ns

50,51

OA thru OH

ns

Power dissipation capacitance

'

..

pF typ

NOTES: 1. For load circuit and voltage waveforms, see page 1 -14.
2, CL = 15 pF, RL = 2 kCl for outputs 0A' or 0H';
CL = 45 pF, RL = 667 Cl for outputs 0A thru 0H.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TeXAS 75265

3-125

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC323, SN74HC323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
02684. DECEMBER 1982

• Multiplexed I/O Ports Provide Improved Bit
Density

SN54HC323 •.. J PACKAGE
SN74HC323 ... J OR N PACKAGE

(TOPVIEWI

• Four Modes of Operation: Hold (Store), Shift
Right, Shift Left, and Load Data
• High-Current 3-State Outputs Drive Bus
Lines Directly or up to 15 LSTTL Loads

°H'
H/OH
F/OF
0100
BlaB

G/OG
E/OE
C/OC
AlOA

• Can Be Cascaded for N-Bit Word Lengths
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

°A'

CLR

CLK
5R

GND

• Dependable Texas Instruments Quality
and Reliability

SN54HC323 ... FH OR FK PACKAGE
SN74HC323 .•. FH OR FN PACKAGE

description

..

VCC
51
5L

50
G1
G2

(TOPVIEWI

These eight-bit universal registers feature multiplexed
liD ports to achieve full eight birdata handling in a single
20-pin package. 'HC323 applications are as stacked or
push-down registers, buffer storage, and accumulator
registers.

G/OG
E/OE
C/OC

Two function-select inputs and two output control inputs
can be used to choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by taking
both function-select lines SO and S1, high. This places the
three-state outputs in a high-impedance state, which
permits data that is applied on the liD ports to be clocked
into the register. Reading out of this register can be
accomplished while the outputs are enabled in any mode.
The clear function is synchronous, and a low level at the
clear input clears the register on the next low-to-high
transition of the clock.

5L
°H'
H/OH'

AlOA

F/OF
0/0 0

°A'

logic symbol

The SN54HC323 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC323 is characterized for operation from -40°C to
85°C.

SL 18)

2,40

Pin numbers shown are fo"r-J-an-d-N-p-aC-ka-g-es....

PRODUCT PREVIEW

3-126

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TexAS 75265

TYPES SN54HC323, SN74HC323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
FUNCTION TABLE
INPUTS
MODE

CLEAR

-'aU

INPUTS/OUTPUTS

FUNCTION OUTPUT

---- f - - -

SERIAL

SELECT CONTROL

CLOCK
A/OA B/OBC/OCO/OO E/OE F/OF G/OG H/OH °A'
G1t G2t
SL SR
-I
L
L
L
X
X X
L
L
L
L
L
L
L
L
L
L
Clear
I
L
L
X
L
L
X X
L
L
L
L
L
L
L
L.
L
H
H
X
X
I
X X
X
X
X
X
X
L
X
X
X
L
L
H
L
X X OAO OBO OCO ODO OEO OFO °GO OHO OAO
X
L
L
L
aHO
Hold
H
X
X
L
L
X X OAO OBO OCO ODO OEO OFO OGO OHQ_
L
~- aHO
H
H
I
H
H
L
L
X
H
L
OAn °Bn °Cn ODn OEn OFn OGn
aGn
Shift Right
I
H
L
H
L
L
X L
L
L _ OGn
OAn °Bn OCn ODn OEn OFn OGn
--:::H
H
I
H
H
L
L
H
X OBn OCn °Dn OEn OFn OGn OHn
L
GS n
Shift Left
I
H
H
L
L
L
X OBn OCn ODn OEn OFn OGn OHn
L
L
h -- ~
Load
H
H
H
X
X
I
f
X X
a
b
c
d
g
a
e
tWhen one or both output controlS are high the eight input/output terminals are disabled to the high-Impedance stale; howeve~. se quentlal
operation or clearing of the register is not affected.
S1

SO

-----~--------~.--

a . . h = the level 0' the sleady-stale Inpul al Inputs A through H. respeClively These data are loaded mto the 'lip-flops while the flip-flop outputs are Isolated from the
input! output terminals.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

timing requirements (supplement to recommended operating conditions)
SN54HC323
MIN
fclock

Clock frequency

tw

Pulse duration

tsu

Setup time before ClKI

NOM

..

SN74HC323
MAX

MIN

NOM

MAX

UNIT
MHz

ClK high

ns

ClK low
SOorS1
Data

ns

ClR
SOorS1
th

Hold time after ClKI

ns

Data
ClR

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-127

TYPES SN54HC323, SN74HC323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=6V.
Vec = 4,5 V to 6,6 V.
CL = Nota 2.
Sae Note 1
RL = Nota 2.
SN54HC323 SN74HC323
TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz

f max
tPlH
tPHl
tPlH
tpHL
tpZH
tpZL
tPHZ
tplZ
tpZH
tpZL

•

tPHZ
tPLZ

ClK

°A'or.OH'

ns

ClK

0A thru OH

ns

<31,<32

0Athru OH

ns

<31,G2

0Athru OH

ns

SOorS1

OA thru OH

ns

SOorS1

0Athru OH

ns

Power dissipation capacitance per register

Cpd

NOTES: 1. For load circuit and voltage waveforms. see page 1-14.
2. CL 45 pF and RL 6670 for outputs 0A thru 0H;
CL = 15 pF and RL = 2k!l for outputs 0A' end 0H"

=

3-128

=

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pF typ

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC352, SN74HC352
DUAL 4-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
02684, DECEMBER 1982

• Inverting Versions of 'HC153

SN64HC362 . , . J PACKAGE
SN74HC362 ... J OR N PACKAGE
(TOP VIEW)

• Permits Multiplexing from N Lines to 1 Line
• Performs Parallel-to-Serial Conversion

lG
8
lC3
lC2
lCl
lCO
lY
GND

• Strobe (Enable) Line Provided for Cascading (N Lines to
n Lines)
• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

VCC
213
A
2C3
2C2
2Cl
2CO
2Y

description
Each of these data selectors/multiplexers contains inverters
and drivers to supply fully complementary binary decoding data
selection to the AND-DR-invert gates. Separate strobe inputs
(G) are provided for each of the two four-line sections.
The SN54HC352 is characterized for operation over the full
military temperature range of -55°C to 125°C, The SN74HC352
is characterized for operation from -40°C to 85°C.

SN64HC362 •.. FH OR FK PACKAGE
SN74HC352 ... FH OR FN PACKAGE
(TOP VIEW)
It:) U

U

Ult:)

oo.-Z>"'I

A
2C3
NC
2C2
2Cl

lC3
lC2
NC
lCl

leO

NC -

No internal connection

FUNCTION TABLE
SELECT
DATA INPUTS

INPUTS

STROBE

OUTPUT

V

B

A

CO

Cl

C2

C3

G

X

X

X

X

X

X

H

H

L

L

L

X

X

X

L

H

L

L

H

X

X

X

L

L

L

H

X

L

X

X

L

H

L

H

X

H

X

X

L

L

H

L

X

X

L

X

L

H

H

L

X

X

H

X

L

L

H

H

X

X

X

L

L

H

H

H

X

X

X

'H

L

L

logic symbol

Select inputs A and B are common to both sect'ons.

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or dis·
continua this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • OALLAS, TEXAS 75265

3-129

TYPES SN54HC352, SN74HC352
DUAL 4-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tPHL
tpLH
tpHL
tPLH
tpHL

Vcc= 5 V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
See Note 1
RL = 2 kn.
SN54HC352 SN74HC352
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

Aor B

Y

ns

Data (Any C)

Y

ns

G

y

ns

Power diSSipation capacitance per data selector
NOTE 1: For load circuit and voltage waveforms. see page 1 -14 .

..

3-130

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TexAS 75265

pF typ

UNIT

TYPES SN54HC353, SN74HC353
DUAL 4-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

SN54HC353 ... J PACKAGE
SN74HC353 ... J OR N PACKAGE
(TOPVIEWI

•

Inverting Versions of 'HC253

•

Permits Multiplexing from N Lines to 1 Line

•

Performs Parallel-to-Serial Conversion

•

High-Current Outputs Can Drive up to 15 LSTTL Loads

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

1(3

description
Each of these data selectors/multiplexers contains inverters
and drivers to supply full binary decoding data selection to the
AND-OR-invert gates. Separate strobe inputs (<3) are provided
for each of the two four-line sections.

VCC
2<3
A
2C3
2C2
2C1
2CO
2Y

B
1C3
1C2
1C1
1CO
1Y
GND

SN54HC353 ... FH OR FK PACKAGE
SN74HC353 ... FH OR FN PACKAGE
(TOPVIEWI
al

The three-state outputs can interface with and drive data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high-impedance state) the low-impedance
of the single enable output will drive the bus line to a high or low
logic level. Each output has its own strobe (<3). The output is
disabled when its strobe is high.

It!)

u
Z

~It!)

>

('oj

..

A
2C3

1C3
1C2

NC

NC

1C1

2C2

1CO

2C1

The SN54HC353 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC353
is characterized for operation from -40°C to 85°C.
NC -

logic symbol

FUNCTION TABLE
SELECT
INPUTS
B A

OUTPUT
OUTPUT
CONTROL
G
Y

DATA INPUTS
CO

C1

C2

C3

X

X

X

L
L
L
L
H
H
H
H

L
L

L
H

H
H
L
L
H
H

X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X

No internal connection

B

X

X
X
X

H

Z

L
L

H

L

X

L
L

X

L

L
H

L
L

fa

L
H
L
H
L
H
L

lCO
lCl

1V

lC2

2Y

Select inputs A and B are common to both sections.
Pin numbers shown are for J and N packages.

maximum

ratings~

recommended operating conditions, and electrical characteristics

See Table III, page 2-5.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instrument. reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

3-131

TYPES SN54HC353,SN74HC353
DUAL 4-UNE TO 1-UNE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=6V,
CL =45 pF,
RL = 6670,

Vcc = 4.6 V to 5.5 V,
See Note'

UNIT

SN54HC353 SN74HC353
TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpHL

..

3-132

Cpd

AorB

y

ns

Data (Any C)

y

ns

G

y

ns

G

y

ns

Power dissipation capacitance

NOTE1: For load circuit and voltage waveforms. see page 1-14 .

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 2250t2 • DALLAS. TEXAS 75265

pF typ

TYPES SN54HC354, SN74HC354
a-LINE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Transparent Latches on Data Select Inputs

•

Transparent Data Registers

•

High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads

SN54HC354 ... J PACKAGE
SN74HC354 ... J OR N PACKAGE
(TOPVIEWj

•

Complementary Outputs

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

Vee

07
06
05
04
03
02
01

y
W

G3
G2
G1

SO

oe

51
52

GNO

Sc

DO

description
These monolithic data selectors/multiplexers contain full on-chip binary decoding to select one of
eight data sources. The data-select is stored in
transparent latches that are enabled by a low level
on pin 11, SC. A similar enable for data is obtained
by a low level on pin 9, DC.

SN54HC354 ... FH OR FK PACKAGE
SN74HC354 ... FH OR FN PACKAGE

The SN54HC354 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC354 is characterized for operation from -40°C to 85°C.

logic symbol

(TOPVIEWj

III

0

co ......
0 o

U
U

> >-

•

3 2
04
03
02
01

4
5
6
7

G1

DO

8

SO

G3
G2

9 1011 1213

Ig

MUX

~ I~

N

_

IJ)IJ)

t!)

G1
G2
G3

SC
SO

51
52
DC

00
01
02
03
04
05
06
07
Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-133

TYPES SN54HC354, SN74HC354
8-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3-STATE OUTPUTS
FUNCTION TABLE

SELECyt
S2
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H

..

H
H

S1
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

SO
X
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

INPUTS
DATA
CONTROL
DC
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

OUTPUT
ENABLES
G1
G2
G3
H
X
X
X
H
X
X
X
L
H
L
L
H
L
L
H
L
L
L
H
L
L
L
H
L
L
H
H
L
L
H
L
L
H
L
L
L
L
H
L
l
H
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L

OUTPUTS
W
Z
Z
Z

Y

Z
Z
Z

00

DO

Don
01

DOn
01

151 n
'02

01n
02

D2n
03
03 n

04

02n
03
03 n
04

D4 n

D4 n

05

05

OSn
06
156 n
07
D7 n

OSn
06
06 n
07
07 n

H = high level (steady state)
L = low level (steady state)
X =irrelevant (any input. including transitions)
Z = high-impedance state (off state)
I = transition from low to high level
DO ... 07 = the level of stead-state inputs at inputs DO through
07. respectively
DOn ... 07 n = the levlH-of steady state inputs at inputs DO through
07. respectively. before the most recent low-to-high
tra nsition of data control
tThis column shows the input address setup with SC low.

timing requirements (supplement to recommended operating conditions)
MIN
tsu
th

3-134

Setup time (with respect
to I at pin 9)
Hold time (with respect
to I at pin 9)

SN64HC364
NOM
MAX

High-level or
low-level data
High-level or
low-level data

MIN

SN74HC364
NOM
MAX

UNIT
ns
ns

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC354, SN74HC354
8-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/
TRANSPARENT REGISTERS WITH 3-STATE OUTPUTS
switching characteristics over recommended 'operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

tpLH
tpHL
tpLH
tpHL

00·07

tPLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tPLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tPHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ

TO
(OUTPUT)

VCC= 5 V.
VCC = 4.5 V to 5.5 V.
CL = 45 pF.
See Note 1
RL = 6670.
SN54HC354 SN74HC354
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX

UNIT

Y
ns

W

Y

OC

ns
W

Y
50.51.52

ns

W

Y

SC

ns

W

y
G1.G2

•

ns

W

y
G3

ns
W

Power dissipation capacitance

pF typ

NOTE t: For load circuit and voltage waveforms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012. DALLAS,TEXAS 75265

3-135

TYPES SN54HC356, SN74HC356
8-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/
EDGE-TRIGGERED REGISTERS WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Transparent Latches on Data Select Inputs

•

Edge-Triggered Data Registers

•

High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads

•

Complementary Outputs

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic and
Ceramic DIPs

•

SN54HC356 ... J PACKAGE
SN74HC356 ... J OR N pACKAGE
(TOPVIEWI
07
06
05
04
03
02
01

DO

Dependable Texas Instruments Quality
and Reliability

eLK
GNO

Vee
y
W
G3
(32

Gl
50
51
52
5e

description

..

These m~nolithic data selectors/multiplexers contain full
on-chip binary decoding to select one of eight data sources.
The data-select address is stored in transparent latches
that are enabled by a low level on"pin 11. SC. The edgetriggered data registers are clocked by a low-to-high
transition on pin 9. ClK. Both true and complementary
outputs are available.
The SN54HC356 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC356 is characterized for operation from -40°C to
85°C.

SN54HC356 ... FH OR FK PACKAGE
SN74HC356 ... FH OR FN PACKAGE
(TOPVIEWI
U
It)cor- U
000>>-

W

03
02
01

5
6
7

Gl

DO

8

50

G3
(32

logic symbol

MUX

Gl
(;2
G3

SC
so
51
S2
ClK

00
01

02
03
04
05
06
07
Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III. page 2-5.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-136

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC356. SN74HC356
8-LlNE TO 1-LlNE DATA SELECTORS/MULTIPLEXERS/
EDGE-TRIGGERED REGISTERS WITH 3-STATE OUTPUTS
FUNCTION TABLE
INPUTS

52

51

X

OUTPUT

CLOCK

SELECTt

ENABLES
G3
G1
G2

X

SO
X

X

H

X

X

X
.X

X
X

X
X

X
X

X
X

H
X

X
L

L

L

L

I

L

L

L

L

H or L

L

L

H
H

L

L

L
H

L

L

L
H
H

H

H or L
I

H

L
L
L

L
L

OUTPUTS

W

Y

Z
Z
Z

Z
Z
Z

Do

DO

Don
01

DOn
01

01n
02

01n
02

L
L

H

L'
L
L

L
L

H
H

I

L

L

H

02n
03

02n
03

I

H or L

H

L

H

H
H

H or L

L

L

H

03 n

H

L

L

!

L

L

04

03 n
04

H

L

H or L

L

L

04 n

04 n

H
H

L
L
H

L
H
H

H
H

!
H or L

L
L

H
H

05
05 n

!
H or L

L

L
L
L

05
05 n
06

H
H

H

L

H

H

L
H

H

H

H

H

06

L

H

L

H

06 n
07

06 n

!

L
L

H or L

L

L

H

07 n

07 n

•

07

tThis column shows the input address setup with SC low.

timing requirements (supplement to' recommended operating conditions)
SN54HC356
MIN
fclock

NOM

SN74HC356
MAX

Clock frequency

tsu

Setup time before CLK!

th

Hold time after CLK!

MIN

NOM

MAX

UNIT
MHz

High-level or

ns

low-level data
High-level or

ns

low-level data

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-137

TYPES SN54HC356, SN74HC356
8-L1NE TO 1-L1NE DATA SELECTORS/MULTIPLEXERS/
EDGE-TRIGGERED REGISTERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
CL =45 pF.

Vcc = 4.5 V to 5.5 V.
See Note 1

RL=6670.
SN54HC356SN74HC356
TA = 25°C
TA = 25°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX

UNIT

f max

MHz

tpLH
tpHL

y

00-07

ns

tPLH
tpHL
tpLH
tpHL
tpLH

W
Y
CLK

ns

W

tpHL
tPLH
tpHL

..

tPLH
tpHL
tpLH
tpHL
tpLH

Y
ns

50.51.52

W
Y
5C

ns

W

tpHL
tpZH
tpZl
tpHZ
tpLZ
tpZH

y
ns

Gl.G2

tPZL
tpHZ

W

tPLZ
tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZl
tpHZ

y
ns

G3

W

tPLZ
Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms, see page 1-14.

3-138

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pF typ

TYPES SN54HC365 THRU SN54HC368,
SN74HC365 THRU SN54HC368
HEX BUS DRIVERS WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEM8ER 1982

•

High-Current 3-State Outputs Drive Bus Lines. Buffer
Memory Address Registers. or up to 15 LSTTL Loads

•

Choice of True or Inverting Outputs

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC365, SN54HC366 ... J PACKAGE
SN74HC365, SN74HC366 ... J OR N PACKAGE
(TOP VIEW)

<31 [
Al
Yl
A2
Y2

Dependable Texas Instruments Quality
and Reliability
'HC365, 'HC367
'HC366, 'HC368

1 U16

VCC
<32

2

15

3

14

A6

4

13

Y6

5

12

A5

A3

6

11

Y5

Y3
GND

7

10

A4

8

9

Y4

True Outputs
Inverting Outputs
SN54HC367, SN54HC368 ... FH OR FK PACKAGE
SN74HC367, SN74HC368 ... FH OR FN PACKAGE
(TOP VIEW)
u

description

'I""'""

'I""'""

~1l'J

These Hex buffers and line drivers are designed
specifically to improve both the performance and
density of three-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters.
The designer has a choice of selected combinations
of inverting and noninverting outputs, symmetrical
G (active-low control) inputs.

3

Yl
A2
NC
Y2
A3

2

U

UN

Z >1l'J

1 20 19

A6
Y6
NC
A5
Y5

4
5
6

7
8

II

9 1011 1213

The SN54' family is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74' family is characterized for operation from -40°C to 85°C.

C'lClU-zz>-~

l'J

SN54HC367, SN54HC368 ... J PACKAGE
SN74HC367, SN74HC368 ... J OR N PACKAGE
(TOP VIEW)

1<3
lAl
lYl
lA2
lY2
lA3
lY3

VCC
2<3
2A2
2Y2
2Al
2Yl
lA4
lY4

SN54HC365, SN54HC366 ... FH OR FK PACKAGE
SN74HC368, SN74HC366 ... FH OR FN PACKAGE
(TOP VIEW)
~
u
~1l'J

U UIl'J

~~Z>N

3

lYl
lA2
NC
lY2
lA3

4
5
7
8

2

1 20 19

2A2
2Y2
NC
2Al
2Yl

maximum ratings. recommended operating conditions.
and electrical characteristics
NC - No inlernal connection

See Table III, page 2-5.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-139

TYPES SN54HC365 THRU SN54HC368, SN74HC365 THRU SN54HC368
HEX BUS DRIVERS WITH 3-STATE OUTPUTS
logic symbols

'HC365

'HC366

Y1

Y1

Y2

Y2

Y3

Y3

Y4

Y4

Y5

Y5

Y6

Y6

'HC367

'HC368

10

16

1A1

1Y1

1Y1
1Y2

1A2

1Y3

1Y2
1Y3

1Y4

1Y4

2A1

2Y1

2Y1

2A2

2Y2

2Y2

1A3
1A4

iG

Pin numbers shown are for J and N packages.

II

'HC365, 'HC367 switching characteristics over recommended operating free-air temperature range
(unless otherwise noted)

PARAMETER

tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ

VCC=6V,

vcc = 4.5 V to 5.5 V,

CL = 45 pF,

Saa Nota 1

FROM
(INPUT)

TO
(OUTPUT)

A

Y

ns

G

y

ns

G

y

ns

RL = 667'l
SN54HC366 SN74HC366
TA = 25°C
SN54HC367 SN74HC367
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

pFtyp

Power diSSipation capacitance per dnver

'HC366, 'HC368 switching characteristics over recommended operating free-air temperature range
(unless otherwise noted)

PARAMETER

tpLH
tpHL
tpZH
tpZL
tpHZ
tPLZ
Cod

VCC = 4.5 V to 5.5 V,

VCC= 5 V,
CL = 45 pF,

Saa Nota 1

FROM
(INPUT)

TO
(OUTPUT)

A

y

ns

G

y

ns

G

y

ns

RL = 6670,
SN54HC366 SN74HC366
TA = 25°C
SN54HC368 SN74HC368
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dissipation capacitance per driver

No load, TA = 25°C

NOTE 1: For load CIrCUIt and voltage waveforms. see page 1-14.

3-140

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS:TEXAS 75265

pF typ

UNIT

TYPES SN54HC373, SN74HC373
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. OECEM8ER 1982

•

8 High-Current Latches in a Single Package

•

High-Current3-State True Outputs Can Drive
up to 15 LSTTL Loads

•

Full Parallel Access for Loading

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC373 ... J PACKAGE
SN74HC373 ... J OR N PACKAGE
(TOP VIEW)

DC

description
These a-bit latches feature three-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. They are particularly suitable for implementing buffer
registers, 1/0 ports, bidirectional bus drivers, and working
registers.
The eight latches of the 'HC373 are transparent Ootype latches.
While the enable (C) is high the Q outputs will follow the data (D)
inputs. When the enable is taken low, the Q outputs will be
latched at the levels that were set up at the 0 inputs.

SN54HC373 ... FH OR FK PACKAGE
SN74HC373 ... FH OR FN PACKAGE
(TOP VIEW)

An output-control input (OC) can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or
a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The highimpedance third state and increased drive provide the capability
to drive the bus lines in a bus-organized system without need
for interface or pull-up components.

20
20
30
3D
4D

5

6
7

8
9 10 11 1213

dOUdO
'00
3

An output-control input can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a highimpedance state, In the high-impedance state the outputs
neither load nor drive the bus lines significantly. The highimpedance third state and increased drive provide the capability
to drive the bus lines in a bus-organized system without need
for interface or pull-up components.

20
20
30
3D
40

2

8D
7D
70
60
6D

5

7

8
9 10 11 1213

'

description
Each of these monolithic circuits contains eight flipflops and additional gating to implement two individual four-bit counters in a single package. The
'HC390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement
cycle lengths equal to any whole and/ or cumulative
multiples of 2 and/or 5 up to divide-by-100. When
connected as a bi-quinary counter, the separate
divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The
'HC393 comprises two indepenqent four-bit binary
counters each having a clear and a clock input. N-bit
binary counters can be implemented with each
package providing the capability of divide-by-256.
The 'HC390 and 'HC393 have parallel outputs from
each counter stage so that any submultiple of the
input count frequency is available for system-timing
signals.
The SN54HC390 and SN54HC393 are characterized
for operation over the full military temperature range
of -55°C to 125°C. The SN74HC390 and
SN74HC393 are characterized for operation from
-40°C to 85°C.

N

lOA
lCKB

2CLR

NC

20A
NC

laB
lac

20a

II

2CKB

c cue u

ozzoo
NN

..-(!)

SN54HC393 ... J PACKAGE
SN74HC393 ... J OR N PACKAGE
(TOP VIEW)

lCLK
lCLR
lOA
laB
lac
lao

VCC
2CLK
2CLR
20A
20B
20c
20 0

GNO

SN54HC393 ... FH OR FK PACKAGE
SN74HC393 ... FH OR FN PACKAGE
(TOP VIEW)

5:J

u:J

3 2

2019

u
uuz~~

2CLR

lOA

NC

NC

20A

laB

NC

NC

20B

lac
9 1011 1213

c cue u

o..- (!)
z
NC -

N

N

No internal connection

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

ZOO

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS, TEXAS 15265

3-149

TYPES SN54HC390, SN54HC393, SN74HC390, SN74HC393
DUAL 4-B11 DECADE AND BINARY COUNTERS
logic symbols

'HC390

'HC393
CTROIV1S
1ClR
(3)

cr{

CT=O

1CLK

10A

(5)

(2)

(3)

10A
(4)
(5)

(S)

10B
10C
10 0

10B

(S)

(11)

10C

(7)

20A
2ClR

10 0

(10)

20B

(9)

20C

2CLK

DO~CT

r

(13)
(11)

20 0

20A
20B

(10)
20C
(9)

2

•

(8)

20 0

Pin numbers shown are for J and N packages.

FUNCTION TABLES
'HC390
BCD COUNT SEQUENCE
(EACH COUNTER)
(See Note A)
OUTPUT
COUNT
QD
QC
QB
QA
L
L
L
L
0
H
1
L
L
L
L
L
L
H
2

3
4·
5
6
7

8
9

L
L
L
L
L
H
H

L
H
H
H
H
L
L

'HC390
BI-QUINARY (5-2)
(EACH COUNTER)
(See Note B)
COUNT
0
1

H

3

L
L
H
H
L
L

L
H
L
H
L
H

4

COUNT

OUTPUT
QA
L
L

QD
L
L

L
L
L
H
H
H
H
H

L
L
H
L
L
L
L
H

2

H

'HC393
COUNT SEQUENCE
(EACH COUNTER)

5
6
7
8
9

QC
L
L
H
H
L
L
L
H
H
L

QB
L
H
L
H
L
L
H

0
1
2

L
H
L

8

NOTES: A. Output QA is connected to input CKB for BCD count.
B. Output QO is connected to input CKA for bi-quinary count.

3
4
5

6
7

OUTPUT
QD
L
L
L
L
L
L
L
L
H

·9
10
11
12
13
14
15

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6_

3-150

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

H

QB
L
L
H
H
L
L
H

H

H

H
H

L
L
L
L

H

H

H

H

H

H

L
L
H
H
L
L
H

H

H

H

H

QC
L
L
L
L
H
H

QA
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

TYPES SN54HC390, SN54HC393, SN74HC390, SN74HC393
DUAL 4-BIT DECADE AND BINARY COUNTERS
timing requirements (supplement to recommended operating conditions)
SN54HC390

SN74HC390

SN54HC393
MIN
fclock

Clock frequency

tw

Pulse duration

NOM

MAX

MIN

SN74HC393
NOM
MAX

UNIT

CKA or ClK

MHz

CKB
CKA or ClK high or low
CKB high or "low

ns

ClR high
Setup time, clear inactive

tsu

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
Cl= 15 pF.
Rl = 2 kO.

VCC = 4,5 V to 5,5 V.
Cl = 50 pF

TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX

SN54HC'
MIN MAX

UNIT
SN74HC'
MIN MAX

CKA or ClK

OA

CKB

OB

tPlH
tpHl

CKA or ClK

OA

ns

tPlH
tpHl

CKA or ClK

Oc of 'HC390
QO of 'HC393

ns

tplH
tpHl

CKB

OB

ns

CKB

Oc

ns

f max

tplH
tpHl

MHz

tplH
tpHl

CKB

00

ns

tpHl

ClR

Any

ns

Power dissipation capacitance per counter

II

pF typ

NOTE 1 For load circuit and voltage waveforms, see page 1-14"

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-151

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC423, SN74HC423
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
02684. DECEMBER 1982

•

Retriggerable for Very Long Output Pulses,
Up to 100% Duty Cycle

•

Overriding Clear Terminates Output Pulse

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC423 ... J PACKAGE
SN74HC423 ... J OR N PACKAGE
(TOP VIEW)
1A
1CLR
1Q
20

Dependable Texas Instruments Quality
and Reliability

2 Cext

28

2R ext /C ext
GND

description

..

VCC
1 Rext/Cext
1Cext
10
2Q
2CLR

18

These dc-triggered multivibrators feature outpLltpulse-duration control by two methods. The basic
pulse duration is programmed by selection of external resistance and capacitance values. Once triggered. the basic pulse duration may be extended by
retriggering the gated low-level-active (A) or highlevel-active (8) inputs. or be reduced by use of the
overriding clear. Figure 1 illustrates pulse control by
retriggering and early clear .

2A

SN54HC423 ... FH OR FK PACKAGE
SN74HC423 ... FH OR FN PACKAGE
(TOP VIEW)

3 2

The 8 input is a Schmitt trigger enabling jitter-free
triggering from input signals with slow transition
rates.

2019

1CLR

10
NC
20

The SN54HC423 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC423 is characterized for operation from -40°C to 85°C.

1Cext
10
NC

20

2C ex t

2CLR

FUNCTION TABLE
NC -

INPUTS
CLEAR
L

A
X

X
X

X

H

L

H

H

I

OUTPUTS
B
X
X
L
I
H

Q

Q

L

H

L*

H*

L*

n

.n.

No internal connection

logic symbol

lA
lB

H*

lS
lS

lQ

lCLR

iO

lCext

*These are the logic levels the outputs
will take on after the completion of any
pulse already started.

1 Rext/Cext

2A
28
2CLR

Pin numbers shown are for J and N packages.

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-152

This document contains information on a
product under development. Texas Instruments reserve. the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC423, SN74HC423
DUAL RETRIGGERABlE MONOSTABlE MUlTIVIBRATORS

BINPUT

OUTPUTQ

Jl
J
I"

RETRIGGER PULSE

P

I

~tw+tPLH-'
I

I

I

·~OUTPUTWITHOUTRETRIGGER

tw

OUTPUT PULSE CONTROL USING RETRIGGER PULSE

~~____________________________________

BINPUT

o

CLEAR

OUTPUT WITHOUT CLEAR

Jr----:I-_-__-_-__-_-_. .:. _____________________

OUTPUT Q

..

OUTPUT PULSE CONTROL USING CLEAR INPUT
FIGURE 1-TYPICAL INPUT/OUTPUT PULSES

maximum ratings, recommended operating conditions. and electrical characteristics
See Table IV. page 2-6.
Note: The minimum recommended supply voltage for this device is 3 V.

timing requirements (supplement to recommended operating conditions)
SN54HC423
MIN
tw
Cext
Rext

NOM

SN74HC423
MAX

MIN

NOM

MAX

UNIT

Pulse duration. A low. B high. or CLR low

ns

External timing capacitance
External timing resistance

J1F
kO

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO

TIMING

OUTPUT) COMPONENTS
Cext

tPLH
tpHL
tpHL
tpLH
.two/min)
twa

A

B
A
B
CLR
A or B

Q

VCC=5V.
CL = 15 pF.
RL=2kO.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC423 SN74HC423
TA = 25°C
TA = 25°C
Rext MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

0

5 kO

ns

Q

0

5 kO

ns

a
a

0

5 kO

ns

0

5 kO

ns

lnF

10 kO

-

a

J1S

Power dissipation capacitance per multivibrator

pFtyp

NOTE1: For load circuit and voltage waveforms. see page 1·14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-153

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC490, SN74HC490
DUAL 4-811 DECADE COUNTERS
02684, DECEMBER 1982

•

Individual Clock. Direct Clear, and Set-to-9 Inputs
for Each Decade Counter

•

Dual Counters Can Significantly Improve System
Densities as Package Count Can Be Reduced by 50%

SN54HC490 , .. J PACKAGE
SN74HC490 ... J OR N PACKAGE
(TOP VIEW)

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Additionto Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

lCLK
lCLR
lOA
lSET9

20A
2SET9

laB
lac
lao
GNO

description

..

VCC
2CLK
2CLR

Each of these monolithic circuits contains eight master-slave
flip-flops and additional gating to implement two individual4-bit
decade counters in a single package, Each decade counter has
individual clock, clear, and set-to-9 inputs, BCD count sequences of any length up to divide-by-1 00 may be implemented
with a single 'HC490. The counters have parallel outputs from
each counter stage so that submultiples of the input count
frequency are available for system timing signals.

20B
20c
20 0

SN54HC490 ... FH OR FK PACKAGE
SN74HC490 ... FH OR FN PACKAGE
(TOP VIEW)
II: ~
..J..J

U

~

U

U
Z

3 2

The SN54HC490 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC490
is characterized for operation from -40°C to 85°C.

u..J

U U

>

N

2019
2eLR
20A
NC
2SET9
20B

910111213
00 U

0

U

ozzoo
.... (!)
NN
NC -

No internal connection

logic symbol
CTROIV10

BCD COUNT SEQUENCE
(EACH COUNTER)
CLEAR/SET-TO-9
FUNCTION TABLE
(EACH COUNTER)
INPUTS
OUTPUTS
CLEAR SET-TO-9 QA QB QC
H
L
L
L
L
L
H
H
L
L
L
L
COUNT

COUNT
0

QO
L
H

1
2
3
4

5
6
7

8
9

lClR (2)

CT=O

lSET9 (4)

CT=9

OUTPUT

cr{

(3)
(5)
(6)
(7)

00 Oc QB QA
L
L
L
L
L
L
L

L
L
L
L
H
H
H

L
L
H
H
L
L
H

L
H
L
H
L
H
L

L
H
H

H
L
L

H
L
L

H
L
H

(13)
2ClR

(11)

2SET9

(10)

2ClK

(9)

lOA
lOB
10C
10 0

20A
20B
20C
20 0

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.
PRODUCT PREVIEW

3-154

Thil document contains information on a
product under development. Tax.. Instruments relerves the right to change or discontinue this product without notic:lt.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DAllAS. TEXAS 75265

TYPES SN54HC490, SN74HC490
DUAL 4-81T DECADE COUNTERS
timing requirements (supplement to recommended operating conditions)
SN54HC490
MIN

NOM

SN74HC490
MAX

MIN

NOM

MAX

UNIT
MHz

fclock
tw

Clock frequency
Pulse duration (any input)

tsu

Setup time. clear or set-to-9 inactive

ns
ns

switchino. characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5 V.
CL=15pF.
RL = 2 kn.

vcc = 4.5 V to 5.5 V.
CL = 50 pF

UNIT

SN54HC490 SN74HC490
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
f max
tpLH
. tpHL
tpLH
tpHL
tpLH
tpHL

MHz
CLK

OA

ns

CLK

as. 00

ns

CLK

Oc

ns

tpHL

CLR

Any

tpLH
tpHL

Set-to-9

OA.OO
QS.OC

ns
\

Power dissipation capacitance per counter

..

ns
pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS]NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-155

TYPES SN54HC533, SN74HC533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

B Latches In a Single Package

•

High-Current 3-State Inverting Outputs Can Drive
up to 15 LSTTL Loads

•

Full Parallel Access for Loading

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality and
Reliability

SN54HC533 ... J PACKAGE
SN74HC533 ... J OR N PACKAGE
(TOP VIEW)

OC
10
1D
2D
20
30
3D
4D
40
GND

description

..

These 8-bit latches feature three-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. They are particularly suitable for implementing buffer
registers, liD ports, bidirectional bus drivers, and working
registers.

SN54HC533 ... FH OR FK PACKAGE
SN74HC533 ... FH OR FN PACKAGE
(TOP VIEW)

OIOIU

2D
20
30
3D
4D

An output-control (DC) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or
a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The highimpedance third state and increased drive provide the capability
to drive the bus lines in a bus-organized system without need
for interface or pull-up components.

The SN54HC533 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC533
is characterized for operation from -40°C to 85°C.
FUNC~ION

~IO

....... 0>00

The eight latches of the 'HC533 are transparent D-type latches.
While the enable (C) is high, the 5 outputs will follow the
complements of the D inputs. When the enable is taken low, the
Q outputs will be latched at the inverses of the levels that were
set up at the D inputs. The 'HC533 is functionally equivalent to
the 'HC373 except for having inverted outputs.

The output control does not affect the internal operation of the
latches. Old data can be retained or new data can be entered
while the outputs are off.

VCC
80
8D
7D
7Q
60
6D
5D
50
C

8D
7D

75
60
6D

logic,symbol

10
20 (4)
30 (7)

TABLE (EACH LATCH)

40 (8)
INPUTS

OUTPUT

50 (13)
60 (14)

OC

ENABLE C

D

Q

L

H

H

L

L

H

L

H

L

L

X

00

H

X

X

Z

70 (17)
80 (18)
Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

PRODUCT PREVIEW

3-156

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC533, SN74HC533
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN74HC533

SN54HC533
MIN
fclock
tw
tsu
th

NOM

MAX

MIN

NOM

UNIT

MAX

MHz

Clock frequency

ns

Pulse duration. enable C high
Setup time. data before enable CI

ns

Hold time. data after enable CI

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
CL=45 pF.
RL = 6670.

VCC = 4.5 V to 5.5 V.
See Note 1

UNIT

SN54HC533 SN74HC533
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
MHz

f max
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
Cpd

D

-a

ns

C

Any

ns

OC

Any

ns

OC

Any

ns

Power dissipation capacitance per latch

No load. TA = 25°C

..

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

D latch signal conventions
It is TI practice to name the outputs and other inputs of a D-type latch and to draw its logic symbol based on the
assumption of true data (D) inputs. Then outputs that produce data in phase with the data inputs are called Q and
those producing complementary data are called O. An input that causes a Q output to go high or a 0 output to go low
is called Preset; an input that causes a 0 output to go high or a Q output to go low is called Clear. Bars are used over
these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input 15. In that case all the other inputs and
outputs should be renamed as shown below. Also shown are corresponding changes in the graphical symbol.
Arbitrary pin numbers are shown in parentheses.

Notice that Q and 0: exchange names. which causes Preset and Clear to do likewise. Also notice that the polarity
indicators (~) on PRE and CLR remain since these inputs are still active-low. but that the presence or absence of
the polarity indicator changes at D. Q. and O. Of course pin 5 (0) is still in phase with the data inputD', but now both
are considered active-low.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 2250t2 • DALLAS. TEXAS 75265

3-157

TYPES SN54HC534, SN74HC534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS lOGIC

DECEMBER 19B2

• High-Current 3-State Inverting Outputs Can Drive
up to 15 LSTTL Loads

SN54HC534 ..• J PACKAGE
SN74HC534 ... J OR N PACKAGE
(TOPVIEWI

• Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

oc

• Dependable Texas Instruments Quality and Reliability

10
10
20
20
35
3D
40

description
These a-bit flip-flops feature three-state outputs designed specifically for driving highly capacitive or relatively low impedance
loads. They are particularly attractive for implementing buffer
registers, 1/0 ports, bidirectional bus drivers, and working
registers.
The eight flip-flops of the 'HC534 are edge-trigger!d Ootype flipflops. On the positive transition of the clock, the Q outputs will
be set to the complement of the logic states that were set up at
the 0 inputs. The 'HC534 is functionally equivalent to the
'HC374 except for having inverted outputs.

•

GNO

SN54HC534 ... FH OR FK PACKAGE
SN74HC534 ... FH OR FN PACKAGE
(TOPVIEWI
U

An output-control input can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly. The highimpedance third state and increased drive provide the capability
to drive the bus lines in a bus-organized system without need
for interface or pull-up components.

91~lg ~Ig
3

2

1 20 19

20
20
30
3D
40

The output control does not affect the internal operation of the
flip-flops. Old data can be retained or new data can be entered
while the outputs are off.
The SN54HC534 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC534
is characterized for operation from -40°C to 85°C.

70
70
60
60
50
50
ClK

80
70
7Q
60
60

logic symbol

FUNCTION TABLE (EACH FLIP-FLOP)
INPUTS

OUTPUT

ClK

D

l

t
t

H

l

l

H

l
l

l

H

X

X
X

10

Q

OC

20
3D

00

40

Z

50

(3)

(4)
(7)
(8)

10
20
30
40

(13)

60 (14)
(17)

70
80 (18)

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.
Copyrighl ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW

3-158

This document contains inforr;nation on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC534, SN74HC534
OCTAL D-TVPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN74HC534

SN54HC534
MIN

NOM

MAX

MIN

NOM

MAX

UNIT
MHz

fclock

Clock frequency

tw

Pulse duration

tsu
th

Setup time. data before ClKI
Hold time. data after ClKI

I ClK high
I ClK low

ns
ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
Cl = 45 pF.
Rl = 667!l.

VCC = 4.5 V to 5.5 V.
See Note 1

UNIT

SN54HC534 SN74HC534
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
f max
tplH
tpHl
tpZH
tpZl
tpHZ
tpLZ

MHz
ClK

Any

ns

OC

Any

ns

6C

Any

ns
pF typ

Power dissipation capacitance per fllp·flop

..

NOTE 1: For load circuitand voltage waveforms. see page 1·14.

o flip-flop signal conventions
It is TI practice to name the outputs and other inputs of a O-type flip-flop and to draw its logic symbol based on the
assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs are called a and
those producing complementary data are called O. An input that causes a a output to go high or a Q output to go low
is called Preset; an input that causes a Q output to go high or a output to go low is called Clear. Bars are used over
these pin names (PRE and CLR) if they are active-low.

a

In some applications it may be advantageous to redesignate the data input O. In that case all the other inputs and
outputs should be renamed as shown below. Also shown are corresponding changes in the graphical symbol.
Arbitrary pin numbers are shown in parentheses.

Notice that a and Q exchange names. which causes Preset and Clear to do likewise. Also notice that the polarity
indicators ( ~ ) on PRE and CLR remain since these inputs are still active-low, but that the presence or absence of
the polarity indicator changes at 0, a. and O. Of course pin 5 (0) is still in phase with the data input 0, but now both
are considered active-low.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-159

TYPES SN54HC563, SN74HC563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEMBER 1982

•

High-Current 3-State Outputs Drive Bus-Lines Directly.
or up to 15 LSTTL Loads

•

Bus-Structured Pinout

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC563 , , , J PACKAGE
SN74HC563 ... J OR N PACKAGE
(TOP VIEW)

OC
1D
2D
3D
4D
5D
6D
7D
8D
GND

description
These 8-bit latches feature three-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. They are particularly suitable for implementing buffer
registers. I/O ports. bidirectional bus drivers. and working
registers.

..

The eight latches are transparent D-type latches. While the
enable (C) is high the 5 outputs will follow the complements of
data (D) inputs. When the enable is taken low the outputs will be
latched at the inverses of the levels that were set up at the D
inputs.

SN54HC563 ... FH OR FK PACKAGE
SN74HC563 ... FH OR FN PACKAGE
(TOP VIEW)

~

An output-control input can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state t"e outputs
neither load nor drive the bus lines significantly. The highimpedance state and increased high-logic level provide the
capability to drive the bus lines in a bus-organized system
without need for interface or pull-up components.

3

30
40
50
60
70

lEach Latch)
OUTPUT

ENABLE

2

U

5'1~

1 20 19

20
30
40
50
60

4

5

6
7

B

0

o

co Z

t!)

UIOIO

cor--

logic symbol

oc
c

FUNCTION TABLE

INPUTS

91g

9 10 11 1213

The output control (Oc) does not affect the internal operation of
the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54HC563 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC563
is characterized for operation from -40°C to 85°C.

VCC
10
20
30
40
50
60
70
80
C

10

Q

OC

c

0

L

H

H

L

H

L

H

40

L

L

X

H

X

X

00
Z

50
60

20
L

3D

70

60
70

80

80

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III. page 2-5.
PRODUCT PREVIEW

3-160

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC563, SN74HC563
OCTAL 0-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
MIN

SN54HC563
NOM
MAX

MIN

SN74HC563
NOM
MAX

UNIT

Pulse duration. enable C high
Setup time. data before enable CI
Hold time. data after enable CI

tyJ
tsu·
th

ns
ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ

VCC= 5 V.
VCC = 4.5 V to 5.5 V.
CL=45pF.
See Note'
RL = 6670.
SN54HC563 SN74HC563
TA = 25°C
TA = 25°C
MIN·TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

0

Q

ns

C

Any

ns

6C

Any

ns

OC

Any

ns

Power dissipation capacitance per latch

UNIT

..

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

o latch signal conventions
It is TI practice to name the outputs and other inputs of a O-type latch and to draw its logic symbol based on the
assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs are called Q and
those producing complementary data are called Q. An input that causes a Q output to go high or a Q output to go low
is called Preset; an input that causes a Q output to go high or a Q output to go low is called Clear. Bars are used over
'
these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other inputs and
outputs should be renamed as shown below. Also shown are corresponding changes in the graphical symbol.
Arbitrary pin numbers are shown in parentheses.

(6)'0

Notice that Q and 5 exchange names. which causes Preset and Clear to do likewise. Also notice that the polarity
indicators (t:::::::..) on PRE and CLR remain since these inputs are still active-low. but that the presence or absence of
the polarity indicator changes at O. Q. and O. Of course pin 5 (0) is still in phase with the data input 5. but now both
are considered active-low.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-161

TYPES SN54HC564, SN74HC564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEMBER 1982

•

High-Current 3-State Inverting Outputs Drive Bus-Lines
Directly or up to 15 LSTTL Loads

•

Bus-Structured Pinout

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC564 ... J PACKAGE
SN74HC664 ... J OR N PACKAGE
(TOP VIEW)

OC
10
20
30
40
50
60
70
80
GND

description
These 8-bit registers feature inverting three-state outputs designed specifically for bus driving. They are particularly suitable
for implementing buffer registers, 1/0 ports, bidirectional bus
drivers, and working registers.
The eight-bit edge-triggered Ootype flip-flops enter data on the
low-to-high transition of the clock.

SN64HC664 ... FH OR FK PACKAGE
SN74HC564 ... FH OR FN PACKAGE
(TOP VIEW)

The output control does not affect the internal operation of the
flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.

a

VCC
10'
20'
30
40
55
60
70
85
ClK

U

° 0IUO>Uld...
N ...

The SNS4HCS64 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HCS64
is characterized for operation from -40°C to 85°C.

30
40
50

60

FUNCTION TABLE
(EACH FLIP-FLOP)
OC
l
l
l
H

INPUTS
ClK
D
t
H
t
l

L
X

logic symbol

OUTPUT

X
X

a

5C

(1)

EN

l

ClK _(_11"";")--IJlC1

H

00
Z

10
20----t
30

t-------t

40
50
60
70
80~~~--------~

Pin numbers shown are "for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

PRODUCT PREVIEW

3-162

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC564, SN74HC564
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN74HC564

SN54HC564
MIN

NOM

MAX

MIN

NOM

UNIT

MAX

MHz

fclock

Clock frequency

tw

Pulse duration
ClK low
Setup time, data before ClKI
Hold time, data after ClKI

I ClK high

ns

I

tsu
th

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5 v,
Cl=45pF,
Rl = 6670.

VCC = 4.5 V to 5.5 V.
See Note 1

UNIT

SN54HC564SN74HC564
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
MHz

f max
tplH
tpHl
tpZH
tpZl
tpHZ
tplZ

ClK

Any

ns

OC

Any

ns

OC

Any

ns

..

pF typ

Power diSSipation capacitance per flip-flop
NOTE 1: Fnr Inad circuit and vnltaoe wavefnrms. see naoe 1 -14.

D flip-flop signal conventions
It is TI practice to name the outputs and other inputs of a D-type flip-flop and to draw its logic symbol based on the
assumption of true data (D) inputs. Then outputs that produce data in phase with the data inputs are called Q and
those producing complementary data are called O. An input that causes a Q output to go high or a 0 output to go low
is called Preset; an input that causes a 0 output to go high or a Q output to go low is called Clear. Bars are used over
·these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input 5. In that case all the other inputs and
outputs should be renamed as shown below. Also shown are corresponding changes in the graphical symbol.
Arbitrary pin numbers are shown in parentheses.

(51

Q

a

Notice that Q and
exchange names, which causes Preset and Clear to do likewise. Also notice that the polarity
indicators (t:::::::,.,) onPREand CLR remain since these inputs are still active-low, but that the presence or absence of
the polarity indicator changes at 0, Q, and O. Of course pin 5 (a) is still in phase with the data input 5, but now both
are considered active-low.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-163

TYPES SN54HC573, SN74HC573
OCTAL D-TVPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

High-Current 3-State Outputs Drive Bus-Lines Directly
or up to 15 LSTTL Loads

•

Bus-Structured Pinout

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC673 ... J PACKAGE
SN74HC673 ... J OR N PACKAGE
(TOPVIEWI

oc

Vee
10
20
30
40
50
60
70
80

3D
4D

description
These 8-bit latches feature three-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. They are particularly suitable for implementing buffer
registers. I/O ports. bidirectional bus drivers. and working
registers.
The eight latches are transparent O-type latches. While the
enable (C) is high the outputs (0) will respond to the data (0)
inputs. When the enable is taken low the outputs will be latched
to retain the data that was set up.

II'

8D
GND

9

e

SN54HC573 .•. FH OR FK PACKAGE
SN74HC573 ... FH OR FN PACKAGE
(TOPVIEWI

~
3

9125
2

u

~9

1 20 19

20
30
40
50
60

An output-control input can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state the outputs
neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to
drive the bus lines in a bus-organized system without need for
interface or pull-up components.

9 1011 1213

OOUOO

CO2
t:J

cor--

The output control (OC) does not affect the internal operation of
the latches. Old data can be retained or new data can be entered
while the outputs are at high impedance.
The SN54HC573 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC573
is characterized for operation from -40°C to 85°C.

logic symbol
FUNCTION TABLE
(EACH LATCH)
INPUTS
ENABLE

DC

OUTPUT

10

Q

20

L

C
H

L

H

L

L

L

L

X

H

X

X

00
Z

(41
3D
(51
40
(61
50
(71
60
(SI
70
(91
SO

D

H

10
(31

H

1191

10
(lSI 20
(17) 30

(161 40
(151 50
(141

so

1131 70
(121
SO

Pin numbers shown are for J and N packages,

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III. page 2-5.
PRODUCT PREVIEW

3-164

This document contains information on a
product under development. Texas Instrumants reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS

INSTRUMENTS

INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC573, SN74HC573
OCTAL 0-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN54HC573
MIN

NOM

SN74HC573
MAX

MIN

NOM

UNIT

MAX

tw

Pulse duration. C high

ns

tsu
th

Setup time. data before enable CI

ns

Hold time. data after enable CI

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 V.
CL=45pF.
RL = 6670.

VCC = 4.5 V to 5.5 V.
See Note 1

UNIT

SN54HC573 SN74HC573
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
tpLH
tpHL
tpLH
tPHL
tpZH
tpZL
tpHZ
tPLZ

0

Q

ns

C

Any

ns

OC

Any

ns

DC

Any

ns

Power dissipation capacitance per latch

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

•

o latch signal conventions
It is TI practice to name the outputs and other inputs of a Ootype latch and to draw its logic symbol based on the
assumption of true data (0) inputs. Then outputs that produce data in phase with the data inputs are called Q and
those producing complementary data are called Q. An input that causes a Q output to go high or a 0 output to go low
is called Preset; an input that causes a 0 output to go high or a Q output to go low is called Clear. Bars are used over
these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other inputs and
outputs should be renamed as shown below. Also shown are corresponding changes in the graphical symbol.
Arbitrary pin numbers are shown in parentheses.

(5)a

(6)'0

Notice that Q and 0 exchange names. which causes Preset and Clear to do likewise. Also notice that the polarity
indicators (c:::::,.,) on PRE and CLR remain since these inputs are still active-low. but that the presence or absence of
the polarity indicator changes at D. Q. and O. Of course pin 5 (0) is still in phase with the data input D. but now both
are considered active-low.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-165

TYPES SN54HC574, SN74HC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEMBER 1982

•

High-Current 3-State Noninverting Outputs
Drive Bus-Lines Directly or up to 15 LSTTL Loads

•

Bus-Structured Pinout

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC574 . , . J PACKAGE
SN74HC574 ... J OR N PACKAGE
(TOP VIEW)

oc

Vee
10
20
30
40
50
60
70

10
20
3D
40
50
60
70

description

80

These 8-bit registers feature three-state outputs designed
specifically for bus driving. They are particularly suitable
for implementing buffer registers, liD ports, bidirectional
bus drivers, and working registers.

SN54HC574 ... FH OR FK PACKAGE
SN74HC574 ... FH OR FN PACKAGE
(TOP VIEW)

The eight edge-triggered Ootype flip-flops enter data on
the low-to-high transition of the clock.

III

80
elK

GNO

The output-control does not affect the internal operation
of the flip-flops. Old data can be retained or new data can
be entered while the outputs are in the high-impedance
state.

3D
40

The SN54HC574 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC574 is characterized for operation from -40°C to
85°C.

20
30
40
50
60

4

5

50
60
70

7
8

9 1011 1213
ClCI~dd

OOt§dcol'
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OC
l
l
l

ClK
I
I

H

OUTPUT

logic symbol

Q

l

0
H
l
X

00

X

X

Z

H

oc

l

ClK

10

·10

"V

(4)
3D
(5)
40
50
60
70
80

(19) 10
(18) 20

20

(6)

(17) 30
(16) 40
(15) 50

(7)

(14) 60

(8)

(13) 70

(9)

(12) 80

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

PRODUCT PREVIEW

3-166

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DAllAS. TEXAS 75265

TYPES SN54HC574, SN74HC574
OCTAL D-TVPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN54HC574
MIN
fclock

Clock frequency

tw

Pulse duration

tsu
th

Setup time, data before ClKI
Hold time, data after ClK!

NOM

SN74HC574

MAX

MIN

NOM

MAX

UNIT
MHz

I
I

ClK high

ns

ClK low

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5 V,
Cl = 45 pF,
RL = 6670,

VCC = 4,5 V to 5.5 V,
See Note 1

UNIT

SN54HC574 SN74HC574
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
f max
tplH
tpHl
tpZH
tpZl
tpHZ
tplZ

MHz
ClK

Any

ns

OC

Any

ns

OC

Any

ns

Power dissipation capacitance per fllp·flop

..

pf typ

Note: 1. For load circuit and voltage waveforms, see page 1·14.

o flip-flop signal conventions
It is TI practice to name the outputs and other inputs of a D-type flip-flop and to draw its logic symbol based on the
assumption of true data (D) inputs. Then outputs that produce data in phase with the data inputs are called Q and
those producing complementary data are calledO. An input that causes a Q output to go high or a 0 output to go low
is called Preset; an input that causes a Q output to go high or a Q output to go low is called Clear. Bars are used over
these pin names (PRE and CLR) if they are active-low.
In some applications it may be advantageous to redesignate the data input D. In that case all the other inputs and
outputs should be renamed as shown below. Also shown are corresponding changes in the graphical symbol.
Arbitrary pin numbers are shown in parentheses.

Notice that Q and 0 exchange names, which causes Preset and Clear to do likewise. Also notice that the polarity
indicators ( ~ ) on PRE and CLR remain since these inputs are still active-low, but that the presence or absence of
the polarity indicator changes at B, Q, and O. Of course pin 5 (0) is still in phase with the data input 5, but now both
are considered active-low.

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-167

HIGH-SPEED
TYPES SN54HC590, SN74HC59.0
CMOS LOGIC 8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS
02684. DECEMBER 1982

•

8-Bit Counter with Register

•

High-Current 3-State Parallel Register Outputs
Can Drive up to 15 LSTTL Loads

•

Counter Has Direct Clear

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC590 ... J PACKAGE
SN74HC590 ..• J OR N PACKAGE
(TOP VIEW)

Os
Oc

VCC

00

G

OA
RCK
CCKEN
CCK
CCLR
RCO

OE
OF
OG
OH
GNO

Dependable Texas Instruments Quality
and Reliability

description

..

These devices each contain an a-bit binary counter
that feeds an a-bit storage register. The storage
register has parallel outputs. Separate clocks are
provided for both the binary counter and storage
register. The binary counter features a direct clear
input CCLR and a count enable input CCKEN. For
cascading a ripple carry output RCO is provided.
Expansion is easily accomplished by tying RCO of
the first stage to CCKEN of the second stage. etc.

For chip carrier information.
contact the factory

Both the counter and register clocks are positiveedge triggered. If the user wishes to connect both
clocks together. the counter state will always be one
count ahead of the register. Internal circuitry prevents clocking from the clock enable.
The SN54HC590 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN74HC590 is characterized for operation from -40°C to 85°C.

logic symbol

CTR8
(CTa 255) Z4

(15) OA
(1) OB
(2)

Oc
00
OE
OF

OG
OH
Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III. page 2-5.

PRODUCT PREVIEW

3-168

This document contains information on a
product under development. Texas Instru·
. ments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC590, SN74HC590
8-BIT BINARY COUNTERS WITH 3-STATE OUTPUT REGISTERS
timing requirements (supplement to recommended operating conditions)
MIN
fclock
tw

tsu

SN54HC590
NOM
MAX

MIN

SN74HC590
NOM
MAX

Clock frequency, CCK or RCK
CCK or RCK high or low
Pulse duration
CCLR low
CCKEN low before CCKI
Setup time
CCLR high (inactive) before CCKt
CCKt before RCKtt

UNIT
MHz
ns

ns

tThis setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in which case the register state will be one
clock pulse behind the counter.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

f max

CCK or RCK

tpLH
tpHL
tpLH
tPLH
tpHL
tpZH
tpZL
tpHZ
tpLZ

TO
(OUTPUT)

VCC= 5 V.
VCC = 4.5 V to 5.5 V.
CL = Note 2.
CL = 50 pF
RL = Note 2.
SN54HC590 SN74HC590
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz

CCKt

RCO

ns

CCLRI

RCO

ns

RCKt

Q

ns

GI

Q

ns

Gt

Q

ns

Power diSSipation capacitance

II

pFtyp

NOTES: 1. For load circuit and voltage waveforms, see page 1-14.
2. Cl =15 pF and RL = 2 kO for RCO output;
Cl = 45 pF and RL = 6670 for a outputs.

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-169

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC592, SN54HC593, SN74HC592, SN74HC593
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
02684. DECEM8ER 1982

• Parallel Register Inputs (,HC592)
• Parallel 3-State I/O: Register Inputs/Counter'
Outputs ('HC593)

SN54HC592 ... J PACKAGE
SN74HC592 ... J OR N PACKAGE
(TOP VIEW)
B

• Counter Has Direct Overriding Load and Clear

15
14

CLOAO

13

RCK

12

CCKEN

F

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
• Dependable Texas Instruments Quality
and Reliability

G

6

H
GNO

7
B

11
CCK
10 . CCLR
RCO

SN54HC592 .. , FH OR FK PACKAGE
SN74HC592 ... FH OR FN PACKAGE
(TOP VIEW)
U

U

description
The 'HC592 consists of a parallel input, 8-bit storage
register feeding an 8-bit binary counter. Both the
register and the counter have individual positive
edge-triggered clocks. In addition, the counter has
direct load and clear functions. Expansion is easily
accomplished by connecting RCO of the first stage to
the count enable of the second stage, etc.

CD Z

U

U

> «
CLOAO
RCK

NC

NC
CCKEN
CCK

J: 0z
c.:l

NC -

The 'HC593 has all the features of the 'HC592 plus
3-51ate I/O, which provides parallel counter outputs.
The SN54HC592 and SN54HC593 are characterized
for operation over the full military temperature range
of -55°C to 125°C. The SN74HC592 and
SN74HC593 are characterized for operation from
-40°C to 85°C.

VCC
A

2
3

E

• High-Current Outputs Can Drive up to
15 LSTTL Loads ('HC593)

II

1 U16

C

0

ulola:
z u..J
a: ~

No internal connection

SN54HC593 ... J PACKAGE
SN74HC593 ... J OR N PACKAGE
(TOP VIEW)
AlOA
BlOB

20
19

G

C/OC

lB

0/0 0

4
5
6

E/OE
FIOF
G/OG
H/OH

17
16
15

RCK
CCKEN

14

CCKEN

13

CLOAO

9
10

GNO

vCC·

G
RCKEN

CCK

12

CCLR

11

RCO

SN54HC593 ... FH OR FK PACKAGE
SN74HC593 ... FH OR FN PACKAGE
(TOP VIEW)

3

0/0

2

1 2019

0

G

E/OE

RCKEN

FIOF

6

RCK

G/OG

7

CCKEN

H/OH

B

CCKEN

09tj~g~
01° Ia: ""
1u
PRODUCT PREVIEW

3·170

This document contains information on a
product under development. Texas Instru·
ments reserves the right to change or dis·
continue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC592, SN54HC593, SN74HC592, SN74HC593
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
logic symbols

'HC692

'HC693

CTRB
CCLR
~

CCK
CLOAO
RCK
A

10

(1)

B

20

(2)

C

(3)

0

(4)

E

(5)

F

(6)

G

H

/7l

II
Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
'HC592: See Table IV,page 2-6.
'HC593: See Table III, page 2-5.

timing requirements (supplement to recommended operating conditions)

MIN
fclock
tw

SN54HC'
NOM
MAX

SN74HC'
NOM
MAX

UNIT
MHz

Clock frequency, CCK or RCK
CCK or RCK high or low
Pulse duration

MIN

CCLR low

ns

CLOAD low

tsu

Setup time (see Note)

CCKEN low before CCK
CCLR high (inactive) before CCKI
RCKI before CCKI

ns

Data A thru H before RCKI
th

Hold time

ns

NOTE: The RCKI to CCKI setup time ensures the counter will see stable data from the register outputs.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 15265

3-171

TYPES SN54HC592,SN54HC593,SN74HC592,SN74HC593
8-BIT BINARY COUNTERS WITH INPUT REGISTERS
'HC592 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

FROM
(INPUT)

TO

VCC=5V.
CL = 15 pF.

(OUTPUT)

RL=2 kO.

CL = 50 pF

UNIT

SN54HC592 SN74HC592
TA = 25°C
TA =25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

f max

CCK or RCK

tPLH
tpHL

CCKI

RCO

ns

tpLH
tpHL

CLOADI

RCO

ns

tpLH

CCLRI

RCO

ns

tpLH
tpHL

RCKI

RCO

ns

MHz

Power dissipation capacitance

..

VCC = 4.5 V to 5.5 V.

No load. TA = 25°C

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1 -14 .

'HC593 switching characteristics over recommended operating free-air temperature range (unles's
otherwise noted)

PARAMETER

'max
tpLH
tpHL
tpLH
tpHL
tpHL
tpZH
tpZL
tpZH
tpZL
tpHZ
tpLZ
tpHZ
tPLZ
tpLH
tPHL
tpLH
tpHL
tPLH
tpLH
tpHL

FROM
(INPUT)

TO
(OUTPUT)

VCC=6V.
CL = 46 pF.

vcc = 4.5 V to 5.5 V.

See Note 1
RL = 6670.
SN54HC593 SN74HC693
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

CCK or RCK

MHz

CCKI

Q

ns

CLOADI

Q

ns

CCLRI

Q

ns

GI

Q

ns

GI

Q

ns

GI

Q

ns

Gt

Q

ns

CCKI

RCO

ns

RCO'

ns

CCLRI

RCO

ns

RCKI

RCO

ns

CLOADI

Power dissipation capacitance

No load. TA = 25°C

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

3-172

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 226012 • OALLAS. TEXAS 75265

pF typ

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
SN54HC594 ... J PACKAGE
SN74HC594 ... J OR N PACKAGE
(TOP VIEW)

• a-Bit Serial-In, Parallel-Out Shift Registers
With Storage
• Independent Direct-Overriding Clears On Shift
And Storage Registers
• Independent Clocks for Both Shift and Storage
Registers

OB
Oc

VCC

00

SER
RCLR
RCK
SRCK
SRCLR
OH'

°A

OE
OF
OG
OH

• High-Current Outputs Can Drive up to 15
LSTTL Loads

GND

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC594 ... FH OR FK PACKAGE
SN74HC594 ... FH OR FN PACKAGE
(TOP VIEW)

• Dependable Texas Instruments Quality
and Reliability

u ceu ~<

ddz>d

description
These devices each contain an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit Ootype storage register.
Separate clocks and direct-overriding clears are provided
on both the shift and storage registers. A serial output
(OH') is provided for cascading purposes.

..

SER
RCLR
NC

RCK
SRCK

Both the shift register and storage register clocks are
positive-edge triggered. If the user wishes to connect both
clocks together, the shift register will always be one clock
pulse ahead of the storage register.

:x: cZ
t:l
d

NC -

The parallel outputs (OA thru 0H) have high-current
capability; output OH'is a standard output.

:x:\a:d
a:
Ul

u
Z d

No internal connection

logic symbol
The SN54HC594 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC594 is characterized for operation from -40°C to
85°C.
SRCK
SER

(15)
(1)

(14)

(2)

a
A

as

(3) Oc
(4) 00

(5) °E
(6) OF

(7) °G
20

OH
(9) 0H"

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-173

TYPES SN54HC594, SN74HC594
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS
timing requirements (supplement to recommended operating conditions)
MIN

SN54HC594
NOM
MAX

MIN

SN74HC594
NOM
MAX

UNIT

f clock Clock frequency, RCK or SRCK
RCK or SRCK high or low
Pulse duration
tw
SRCLR low
SRCLR high (inactive) before SRCK!
RCLR high (inactive) before RCK!
Setup time
tsu
SER data before SRCK!
SRCK! before RCK! (see note)
Hold time
SER after SRCK!
th

MHz
ns

ns

ns

NOTE: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the
storage register state will be one clock pulse behind the shift register.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

..

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V,
CL=16pF,
RL=2kO,

VCC = 4.5 V to 6.5 V,
See Note 1

UNIT

SN54HC594 SN74HC594
TA = 25°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
f max
tpLH
tpHL
tpLH
tpHL
tpHL

RCK orSRCK

MHz

SRCK

QH'

ns

RCK

QA thru QH

ns

SRCLR
RCLR

QH'
QAthru QH

ns

Power dissipation capacitance

No load, TA = 25°C

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

3-174

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012. DALLAS. TEXAS 75265

pF typ

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC595, SN74HC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
02684, DECEM8ER 1982

•

B-Bit Serial-In. Parallel-Out Shift
Registers with Storage

•

High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads

•

Shift Register Has Direct Clear

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC595 ... J PACKAGE
SN74HC595 ... J OR N PACKAGE
(TOP VIEW)
QB

VCC
OA
SER

Oc

00
OE
OF

G

OG

SRCK
SRCLR

RCK

OH
GND

Dependable Texas Instruments Quality
and Reliability

description
These devices each contain an 8-bit serial-in. parallel-out shift
register that feeds an 8-bit D-type storage register, The storage
register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The
shift register has a direct-overriding clear. serial input, and
serial output pins for cascading.

OH'

SN54HC595 ... FH OR FK PACKAGE
SN74HC595 .. , FH OR FN PACKAGE
(TOP VIEW)

..

Both the shift register and storage register clocks are positiveedge triggered. If the user wishes to connect both clocks
together. the shift register state will always be one clock pulse
ahead of the storage register,
The SN54HC595 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC595
is characterized for operation from -40°C to 85°C.

J: C U J:: 15
OZZOu
(!)
a:
III

NC -

No internal connection

logic symbol

QA
QS
QC
QO
QE

~
20 [> 3'V
Pin numbers

sh~wn

are for J and N packages.

(7)

(9)

QF
QG
QH
QW

maximum ratings. recommended operating conditions. and electrical characteristics
See Table III. page 2-5.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
Thil document contains information on a
product under development. Texas Instrumentl relervel the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TexAS 75265

3-175

TYPES SN54HC595. SN74HC595
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
timing requirements (supplement to recommended operating conditions)
MIN
fclock
tw

tsu
th

SN54HC595
NOM
MAX

MIN

SN74HC595
NOM
MAX

UNIT

Clock frequency,RCK or SRCK
RCK or SRCK high or low
Pulse duration
SRCLR low
SRCLR high (inactive) before SRCKI
Setup time
' SER data before SRCKI
SRCKI before RCKlt
Hold time
SER data after SRCKI

MHz
ns

ns
ns

tThis setup time ensures the register will see stable data from the shift-register outputs, The clocks may be connected together in which case the storage
register state will be one clock pulse behind the shift register.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

II

PARAMETER

FROM
(INPUT)

f max

RCK or SRCK

tPLH
tpHL
tpHL
tpLH
tpHL
fpZH
tpZL
tPHZ
tpLZ

SRCK

TO
(OUTPUT)

VCC= 6 V.
VCC =4.6 Vto6.6 V.
Cl = Note 2.
See Note 1
Rl = Note 2.
SN64HC696 SN74HC696
TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

MHZ
°H'

ns

SRCLR

OH'

ns

RCK

OA thru OH

ns

G

OAthruOH

ns

G

OA thru OH

ns

Power dissipation capacitance
NOTES: t. For load circuit and voltage waveforms. see page 1-14.
2. CL = 15 pF and RL = 2 kO for OH' output;
. CL =45 pF and RL =6670 for OA thru OH outputs.

3-176

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

pFtyp

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC597, SN54HC598, SN74HC597 , SN74HC598
8-BIT SHIFT REGISTERS WITH INPUT LATCHES
02684, DECEMBER 1982

•

8-Bit Parallel Storage Register Inputs (,HC597)

•

Parallel 3-State 1/0, Storage Register Inputs,
Shift Register Outputs (,HC598)

•

High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads (,HC598)

•

SN54HC597 , .. J PACKAGE
SN74HC597 ... J OR N PACKAGE
(TOP VIEW)

0
F

Shift Register Has Direct Overriding Load
and Clear

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

16
15
14
13
12
11
10
9

C

G
H
GND

VCC
A
SER'
SRLOAD
RCK
SRCK

SRCER
OH'

SN54HC597 •.. FH OR FK PACKAGE
SN74HC597 ... FH OR FN PACKAGE
(TOP VIEW)
u

u

 «

3 2 1 2019

description
The 'HC597 consists of an 8-bit storage latch feeding a
parallel-in, serial-out 8-bit shift register. Both the storage
register and 'shift register have positive-edge triggered
clocks. The shift register also has direct load (from storage)
and clear inputs.

•

The 'HC598 has all the features of the 'HC597 plus 3-state
110 ports that provide parallel shift register outputs.
The 'HC598 also has multiplexed serial data inputs.
The SN54HC597 and SN54HC598 are characterized for
operation over the full military temperature range of
-55°C to 125°C. The SN74HC597 and SN74HC598 are
characterized for operation from -40°C to 85°C.

SN54HC59B ... JPACKAGE
SN74HC598 .. , J OR N PACKAGE
(TOP VIEW)
AlOA
BlOB

C/OC
0/0 0
EIOE
FIOF

G/OG
HlOH
SRLOAD

10

GND

20
19
18
17
16
15
14
13
12

G

11

OH'

VCC

os
SERO
SERI
RCK
SRCKEN
SRCK
SRCLR

SN54HC598 ... FH OR FK PACKAGE
SN74HC598 ... FH OR FN PACKAGE
(TOP VIEW)
U

 Ie!)

These devices allow data transmission from A bus to the B bus
or from the B bus to the A bus depending upon the logic levels at
the enable inputs (GBA and GAB).
A3
A4
A5
A6
A7

The enable inputs can be used to disable the device so that the
buses are effectively isolated.
The dual-enable configuration gives these devices the capability
to store data by simultaneous enabling of GBA and GAB. Each
output reinforces its input in this transceiver configuration.
Thus, when both control inputs are enabled and all other data
sources to the two sets of bus lines are at high impedance, both
sets of bus lines (16 in all) will remain at their last states. The
8-bit codes appearing on the two sets of buses will be identical
for the 'HC623 or complementary for the 'HC620.
The
tion
The
tion

B1
B2
B3
B4
B5

SN54HC620 and SN54HC623 are characterized for operaover the full military temperature range of -55°C to 125°C.
SN74HC620 and SN74HC623 are characterized for operafrom -40°C to 85°C.

FUNCTION TABLE
ENABLE INPUTS
GBA
GAB
L
L

H
H

H

L

H

L

OPERATION
'HC620
B data to A bus
A data to B bus
Isolation
B data to A bus,

A data

to B bus

'HC623
B data to A bus
A data to B bus
Isolation
B data to A bus,
A data to B bus

PRODUCT PREVIEW

3-180

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC620, SN54HC623, SN74HC620,. SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
logic symbols
'HC620

'HC623

..

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

'HC620 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

tPLH
tPHL
tPLH
tPHL
tpZH
tpZL
tPHZ
tpLZ
tpZH
tpZL
tPHZ
tpLZ

VCC=6V,
CL = 46 pF,

VCC = 4.6 V to 6.6 V,

FROM
(INPUT)

TO
(OUTPUT)

A

B

ns

B

A

ns

GBA

A

ns

GBA

A

ns

GAB

B

ns

GAB

B

ns

See Note 1

RL = 6670,
SN54HC620 SN74HC620
TA = 26°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

Power dissipation capacitance per transceiver

No load. TA =25°C

UNIT

pF typ

----------------------------NOTE 1: For load circuit and voltage waveforms. see page 1 -14 .

....

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-181

TVPESSN54HC620,SN54HC623,SN74HC620,SN74HC623
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
'HC623 switching characteristics over recommended operating free-air temperature. range (unless
otherwise noted)

PARAMETER

TO
(OUTPUT)

tpLH
tpHL

A

B

ns

B

A

ns

GBA

A

ns

GBA

A

ns

GAB

B

ns

GAB

B

ns

tPLH
tpHL
tpZH
tpZL
tpHZ

..

VCC=6V.
vcc = 4.6 V to 6.6 V.
CL = 46 pF.
See Note'
RL = 667Cl.
SN64HC623 SN74HC623
TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

tPLZ
tpZH
tpZL
tpHZ
tpLZ

Power dissipation capacitance per transceiver
NOTE 1: For load circuit and voltage waveforms. see page 1 ·14.

3-182

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 15265

pF typ

UNIT

TYPES SN54HC640, SN54HC643, SN54HC645,
SN74HC640,SN74HC643,SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

02684, DECEM8ER 1982

•

Bus Transceivers in High-Density 20-Pin
DIPs and also Plastic and Ceramic Chip Carriers

•

Choice of True or Inverting Logic

•

High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads

•

Dependable Texas Instruments Quality
and Reliability
DEVICE

lOGIC

'HC640
'HC643

Inverting
True and Inverting

'HC645

True

SN54HC' , , . J PACKAGE
SN74HC' ... J OR N PACKAGE
(TOP VIEW)

DIR

Vee

A1
A2
A3
A4
A5
A6
A7
A8

G
81
82
83
84
85
86
87
88

GND

description
These octal bus transceivers are designed for asynchronous two-way communication between data
buses. The devices transmit data from the A bus to
the 8 bus or from the 8 bus to the A bus depending
upon the level at the direction control (DIR) input.
The enable input {G) can be used to disable the
device so the buses are effectively isolated.

SN54HC' ... FH OR FK PACKAGE
SN74HC' , .. FH OR FN PACKAGE
(TOP VIEW)

a:
N...- _
<1:<1: o

II

U
U

>

It:)

TheSN54HC64~SN54HC643andSN54He645are

characterized for operation over the full military
temperature range of -55°e to 125°e. The
SN74He640, SN74HC643, and SN74HC645 arecharacterized for operation from -40°C to 85°C.

81
82
83
84
85

A5
A6
A7
roo rol'CO

<1:2 eDeDeD
t:)

FUNCTION TABLE

OPERATION

CONTROL
INPUTS

'HC640

'HC645

'HC643
B data to A bus
A data'to B bus
Isolation

G

DIR

L

L

B data to A bus

l

H

A data to B bus

B data to A bus
A data to B bus

H

X

Isolation

Isolation

PRODUCT PREVIEW
This document contains information on e
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated'

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

3-183

TYPES SN54HC640, SN54HC643, SN54HC645
SN74HC640,SN74HC643,SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
logic symbols

'HC640

DIR

..

'HC646

'HC643

OIR

A1

B1

A2

B2

DIR

A1

B1

A2

B2

A1

B1

A2

B2

B3

B3

B3

B4

B4

B4

A5

B5

A5

B5

A5

B5

A6

B6

A6

B6

A6

B6

A7

B7

A7

B7

A7

B7

A8

B8

A8

B8

A8

B8

Pin numbers shown are for J and N packages

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

'HC640 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 6 V,
CL=46pF,
RL = 6670,

VCC = 4.6 V to 6.6 V,
See Note 1

UNIT

SN64HC640 SN74HC640
TA = 26°C
TA = 26°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
tpLH
tpHL
tpZH
tPZL
tpHZ
tPLZ

AorB

BorA

I1S

G

AorB

ns

G

AorB

ns

Power disSipation capacitance per transceiver
NOTE 1: For load circuit and voltage waveforms. see page 1-14.

3-184

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pF typ

TYPES SN54HC640, SN54HC643, SN54HC645
SN74HC640,SN74HC643,SN74HC645
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
'HC643 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

FROM

TO

(INPUT)

(OUTPUT)

VCC=6V.
CL = 46 pF.
RL = 6670.

vcc = 4.6 V to 6.6 V.
See Note 1

UNIT

SN64HC643 SN74HC643
TA = 26°C
TA = 26°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ

A

B

ns

B

A

ns

G

A

ns

G

A

ns

G

B

ns

G

B

ns
pF typ

Power dissipation capacitance per transceiver
NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

..

'HC645 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
VCC=6V.
CL =46 pF.

vcc = 4.6 V to 6.6 V.

'

FROM
(INPUT)

TO
(OUTPUT)

AorB

BorA

ns

tpZH
tpZL

G

AorB

ns

tpHZ

G

AorB

ns

PARAMETER

tpLH
tpHL

tpLZ

See Note 1

RL = 6670.
SN64HC646 SN74HC646
TA = 26°C
TA = 26°C
MIN TVP MAX MIN TVP MAX MIN MAX MIN MAX

Power diSSipation capacitance per transceiver

No load. TA = 25°C

UNIT

pF lyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 2250t2 • DALLAS, TEXAS 75265

3-185

TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

HIGH-SPEED
CMOS LOGIC

DECEMBER 19B2

SN54HC' ... JT PACKAGE
SN74HC' ... JT OR NT PACKAGE
(TOP VIEW)

• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data

CAB
SAB

• Choice of True or Inverting Data Paths
• High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads

DIR

A1
A2
A3
A4
A5
A6
A7
A8

• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability
description

..

VCC
CBA
SBA

These devices consist of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers on the low-to-high transition of the
appropriate clock pin (CAB or CBA). The examples below demonstrate the four fundamental bus-management functions that
can be performed with the 'HC646 or 'HC648 .

G
B1
B2
B3
B4
B5
B6
B7
B8

GND

SN64HC' ... FH OR FK PACKAGE
SN74HC' ... FH OR FN PACKAGE
(TOP VIEW)

Enable (G) and direction (DIR) pins are provided to control the
transceiver functions. In the transceiver mode, data present at
the high-impedance port may be stored in either register or in
both. The select controls (SAB and SBA) can multiplex stored
and real-time (transparent mode) data. The direction control
determines which bus will receive data when enable G is active
(low). In the isolation mode (enable G high), A data may be
. stored in one register and/or B data may be stored in the other
register.

A1

G

A2

B1
B2
NC
B3

A3
NC
A4
A5

B4

A6

B5

When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B, may be driven at a time.

NC -

No internal connection

The SN54' family is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74' family
is characterized for operation from -40°C to 85°C.

1211

0"

(3)

111

1231
CIA

121

1221

1211

G

(3)

.

1'1
CAB

~
123)
CIA

121
SAB

1221
S8A

REAL-TIME TRANSFER REAL-TIME TRANSFER
BUS B TO BUS A
BUS A TO BUS B

1211

(3)

G

(1)

(23)

12)
SAB

(22)
saA

STORAGE FROM
A, B, OR A AND B

1211

G

(3)

"I

..

(23)

,21

(22)

e8A

SAB

saA

TRANSFER STORED DATA
TO A OR B

Pin numbers shown are for JT and NT packages.
PRODUCT PREVIEW
This document contains information on a

3-186 ~:~t~c:e~:~:sdt~Vee~~:;;~~t~~:~=: ~rS~~:

Copyright ©1.982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED

continue this product without notice.
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
.OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
FUNCTION TABLE

DIR
X
X
X
X
L
L

G

X
X
H
H
L
L
L
L

H

H

INPUTS
CAB CBA SAB
I
X
X
X
I
X
I
X
I
H or L H or L
X
X
X
X
X
X
X
X
X
L
X
H
X

SBA
X
X
X
X
L
H

X
X

DATA IIOt
A1 THRU A8 B1 THRU B8
Input
Not specified
Not specified
Input
Input

Input

Output

Input

Input

Output

OPERATION OR FUNCTION
'HC646
'HC648
Store A. B unspecified
Store A. B unspecified
Store B. A unspecified
Store B. A unspecified
Store A and B Data
Store A and B Data
Isolation. hold storage
Isolation. hold storage
Real-Time B Data to A Bus
Real-Time B Data to A Bus
Stored B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to Bus

tThe data output functions may be enabled or disabled by various signals at the G and OIR inputs. Data input functions are always enabled. i.e .. data at the bus
pins will be stored on every low-to-high transition on the clock inputs.

logic symbols
'HC646

G

'HC648

G

(21)

OIR (3)

(21)

G3

OIR (3)

[BA)

[BA)

II

[AB)
CBA (23)
SBA (22)
(1)

CAB

SAB

(2)
(4)

CBA (23)
SBA (22)
CAB (1)
(2)
SAB

C6

C6

(20)
;;;'1

B1

A1

(4)

(20)
;;;'1

B1

A1

;;;'1
(5)

'1

(19)

(5)
B2

A2
(6)

(18)

(7)

(171

(8)

(16)

(9)

(15)

(10)

(14)

(11)

(13)

B3

A3

B4

A4
AS

B5

A6

B6
B7

A7
AS

BS

'1

(19)

A2

B2
(6)

(18)

(7)

(17)

(8)

(16)

(9)

. (15)

(10)

(14)

(11)

(13)

A3

B3

A4

B4

AS

B5

A6

B6
B7

A7
AS

B8

Pin numbers shown are for JT and NT packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table III, page 2-5.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-187

TYPES SN54HC646, SN54HC648, SN74HC646, SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS'
WITH 3-STATE OUTPUTS
timing requirements (supplement to recommended operating conditions)
SN74HC'

SN54HC'
MIN
fclock
tw

Clock frequency

tsu
th

Setup time

NOM

MAX

MIN

NOM

MAX

UNIT
MHz
ns
ns

Clock pulse duration

I A before CAB! or 8 before CBA!
I A after CAB! or B after CBA!

Hold time

ns

'HC646 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

..

f max
tpLH
tpHL
tpLH
tpHL

CBAor CAB

Aor B

ns

Aor B

8 orA

ns

Aor B

ns

G

AorB

ns

DIR

AorB

ns

See Note 1

RL = 667Cl,
SN54HC646 SN74HC646
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz

tpLH

SBAorSAB
(with A or 8 high)t

tpLH
tpHL

SBAorSAB

tpHZ
tpLZ

vcc = 4.5 V to 5.5 V,

TO
(OUTPUT)

tpHL

tpZH
tpZL

VCC=5V,
CL =45 pF,

FROM
(INPUT)

(with A or 8 low)t

tpZH
tpZL
tpHZ
tpLZ

Power dissipation capacitance per transceiver
NOTE 1: For load circuit and voltage waveforms. see page 1-14.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.

3-188

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 15265

pF typ

TVPESSN54HC646,SN54HC648,SN74HC646,SN74HC648
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
'HC648 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
VCC= 5 V.
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

. CL=45pF.
RL = 667Cl.

VCC = 4.5 V to 5.5 V •
See Note 1

UNIT

SN54HC648 SN74HC648
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
f max
tpLH

MHz
CBAor CAB

Aor B

ns

AorB

BorA

ns

AorB

ns

G

Aor B

ns

. DIR

AorB

ns

tpHL
tpLH
tpHL
tpLH
tpHL

SBAor SAB
(with A or B highlt

tpLH

SBAorSAB

tpHL

(with A or B lowlt

tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ
Power dissipation capacitance per transceiver

..

pFtyp

NOTE 1: For load circuit and voltage waveforms, see page 1-14.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-189

HIGti-SPEED
CMOS LOGIC

TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH J-STATE OUTPUTS
02684, DECEM8ER 1982

•

Bus Transceivers/ Registers

•

Independent Registers and Enables for A
and B Buses

•

High-Current 3-State Outputs Can Drive
up to 15 LSTTL Loads

•

Multiplexed Real-Time and Stored Data

•

Choice of True and Inverting Data Paths

•

Included Among the Package Options Are
Compact 24-Pin 300-mil-wide DIPs and
Both 28-Pin Plastic and Ceramic Chip Carriers

•

Dependable Texas Instruments Quality and
Reliability

SN54HC651, SN54HC652 , .. JT PACKAGE
SN74HC651, SN54HC652 ... JT OR NT PACKAGE
(TOP'VIEW)

CAB
SAB
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND

These devices consist of bus transceiver circuits, 0type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal· storage registers,
Enable GAB and GBA are provided to control the
transceiver functions. SAB and SBA control pins are
provided to select whether real-time or stored data
is transferred. A low input level selects real-time
data, and a high selects stored data. The following
examples demonstrate the four fundamental busmanagement functions that can be performed with
the 'HC651 and 'HC652.

GBA
Bl
B2
Ne
B3
B4
B5

NC -

I

No internal connection

~

~

13) 121) 11) 123) (2) 122)
GAB GBA CAB CBA SAB SBA

13) 121) 11) 123) 12) 122)
GAB GBA CAB CBA SAB SBA
X
H
X
X
X

X

X

X

L

H

H

X

X

L

X

REAL-TIME TRANSFER
BUS BTO BUS A

REAL-TIME TRANSFER
BUS ATO BUS B

X
.X

13) (21)
(1)
(23)
(2)
GAB GBA CAB CBA SAB
H
L
HorL HorL
H

122)
SBA
H

TRANSFER
STORED DATA
TOAAND/OR B

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product. without notice.

X
X

STORAGE FROM
AAND/OR B

Pin numbers shown are for JT and NT packages.

3-190

~

'-.-'
(3) 121) 11) 123) 12) 122)
GAB GBA CAB CBA SAB SBA

L

eBA
SBA
GBA
Bl
B2
B3
B4
B5
B6
B7
B8

SN54HC651, SN74HC652 ... FH OR FK PACKAGE
SN74HC661, SN74CH652 ... FH OR FN PACKAGE
(TOP VIEW)

description

L

Vee

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
Data on the A or B data bus, or both, can be stored in the internal 0 flip-flops by low-to-high transitions at the
appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without using the internal Ootype flip-flops by simultaneously
enabling GAB and GBA. In this configuration each output reinforces its input. Thus, when all other data sources to
the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.
The SN54HC651 and SN54HC652 are characterized for operation over the full military temperature range of -55°C
to 125°C. The SN74HC651 and SN74HC652 are characterized for operation from -40°C to 85°C.

FUNCTION TABLE
DATA 1/0·

INPUTS
GAB GBA CAB
L
L

H

X
H
L
L
L
L
H
H

H
H
X

H

H

CBA SAB SBA
H or L H or L X
X
I
I
X
X
I
H orL X
X

OPERATION OR FUNCTION

B1 THRU B8

A1 THRU A8

'HC6S1

'HC662
Isolation

Isolation
Store A and B Data

Input

Input

Input

Store A in both registers
Hold A, Store B

Store A. Hold B
Store A in both registers
Hold A, Store B

Store A and B Data

Store A, Hold B

Output

Input

Store B in both registers

Store B in both registers

Output

Input

Real-Time B Data to A Bus
Stored B Data to A Bus

Real-Time B Data to A Bus
Stored B Data to A Bus

Input

Output

Real-Time A Data to B Bus

H

X
X
X
L
H
X
X

Input
Not specified

I
X
H or L
X
X
H or L

X
X
X
X
X
L
H

Not specified
Output
Input

Real-Time A Data to B Bus
Stored A Data to B Bus

L

H or L H or L

H

H

Output

Output

L
L
L
H

I
H or L

I
I

I
X
X
X

Stored A Data to B Bus
Stored A Data to B Bus and
Stored BData to A Bus

..

Stored A Data to B Bus and
Stored B Data toA Bus

"The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled. i.e .• data at
the bus pins will be stored on every low-to-high transition on the clock inputs.

logic symbols
'HC651

. 'HC652

B1

A2

B1

B2

A2

AJ

AJ

A4

A4

A5

B5

A5

B5

A6

B6

A6

B6

A7

B7

A7

B7

AS

BS

AS

BS

Pin numbers shown are for JT and NT packages.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225Ot2 • DALLAS. TEXAS 75265

3-191

TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
maximum ratings, recommended operating conditions, and electrical characteristics
See Table III. page 2-5.

timing requirements (supplement to recommended operating conditions)
SN54HC651

SN74HC651

SN54HC652
MIN
NOM
MAX

tsu
tw

..

NOM

UNIT
MAX

CBA or CAB high

Pulse duration

tw

SN74HC652
MIN

ns

CBA or CAB low

Set up time

SBAorSAB

before CAB or CBAI

Aor B

Hold time
after CAB or CBAI

SBAorSAB
Aor B

ns
ns

'HC651 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
VCC= 5 V.
CL = 45 pF.

VCC = 4.5 V to 5.5 V.
See Note 1

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tpLH
tpHL

CBA or CAB

AorB

ns

tpLH

RL = 6670.
SN54HC651 SN74HC651
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

AorB

BorA

ns

tpHL

SBAor SABt
(with A or B high)

AorB

ns

tPLH
tpHL

SBA or SABt
(with A or Blow)

AorB

ns

GBA

A

ns

GBA

A

ns

GAB

B

ns

GAB

B

ns

tpHL
tpLH

tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ

Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1 -14.
tThese parameters are measured with the internal output state of the storage register opposite to the that of the bus input.

3-192

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

pF typ

TYPES SN54HC651, SN54HC652, SN74HC651, SN74HC652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
'HC652 switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER

tpLH
tpHL
tPLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpHZ
tpLZ
tpZH
tpZL
tpHZ
tpLZ

VCC=5V.
vcc = 4.5 V to 5.5 V.
CL=45pF.
See Note 1
RL = 6670.
SN64HC652 SN74HC652
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

CBAor CAB

Aor B

ns

Aor B

BorA

ns

AorB

ns

Aor B

ns

GBA

A

ns

GBA

A

ns

GAB

B

ns

GAB

B

ns

SBAor SABt
(with A or B high)
SBAor SABt
(with A or Blow)

Power diSSipation capacitance

UNIT

II

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.
tThese parameters are measured with the internal output state of the storage register opposite to that of the bus input.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-193

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC688, SN74HC688
8-BIT IDENTITY COMPARATORS
02684. DECEM8ER 1982

•

Compares Two Eight-Bit Words

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC688 ... J PACKAGE
SN74HC688 ... J OR N PACKAGE
(TOP VIEW)

description
These identity comparators perform comparisons of two eightbit binary or BCD words. An enable input (G) may be used to
force the output to the high level.
The SN54HC6BB is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC6BB
is characterized for operation from -40°C to B5°C.

p=o

07
P7
06
P6
05
P5
04
P4

GND

SN54HC688 ... FH OR FK PACKAGE
SN74HC688 ... FH OR FN PACKAGE
(TOP VIEW)

logic symbol

..

Vee

G
PO
00
P1
01
P2
02
P3
03

COMP

G

EN

PO (2)

o

P1 (4)

P1
01
P2
02
P3

P2 (6)
P3 (8)
P

P4 (11/
P5 (13)

Q7

P7
06
P6
05

P6 (15)
P7 (17)

00 (3)

7

o

01 (5)
Q2

(7)

(9)

03
04 (12)

o

05 (14)

FUNCTION TABLE

06 (16)

07 (18)

INPUTS
DATA
ENABLE
P,O
G
P= 0
L

7

Pin numbers shown are for J and N packages,

OUTPUT
P=O

p>o

L

L
H

p- z z >- ><.:l

The SN54HC4017 is characterized for operation over the
full military temperature range df -55°C to 125°C. The
SN74HC4017 is characterized for operation from -40°C to
85°C.

NC -

No internal connection

logic symbol

CTR DIV 10/
DEC
0

_ _ (13)
CLKEN
(14)
CLK

&

2
3

.IT

4
5
6

ClR (15)

CT=O

7

a
9

(3)
(2)
(4)
(7)
(10)
(1 )
(5)
(6)
(9)
(11 )

VO
V1
V2
V3
V4
V5
V6
V7

va
V9
CO

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-B.
PRODUCT PREVIEW·
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-197

TYPES SN54HC4017, SN74HC4017
DECADE COUNTERS/DIVIDERS
typical clear. count. and inhibit sequences

CLOCK
ENABLE

Yl:J

I

Y2;

______~r_lL______________________~l--~~

Y3:]

________~r_lL________________

Y4:J
OUTPUTS
Y5:J

-+:__
I

~~r

------------~r-l~----------------~Ir_~-----

______________~r_l~______________~lr_~----I

Y6:J
Y7:J
YB:J

...

------------------~r-l~----------+:--r_----

--------------------~r-l~--------_ri--~----

________________________~r-lL-_____+:--~----

yg-' ________________________~r_l~'__~:~----_I

I

CARRY-,
OUTPUT
CLEAR

I~I -

,-I+-_________~C-OU-N-T-=--=--=--=--=--=--=--=-IN~H-IB-IT~

.

COUNT

timing requirements (supplement to recommended operating conditions)
SN54HC4017
MAX
NOM

MIN
fclock

Clock frequency

tw

Pulse duration

tsu

Setup time. before ClKI

SN74HC4017
NOM
MAX

MIN

UNIT
MHz

ClK high or low

ns

ClR high
ClKEN low

ns

ClR inactive

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted) .

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5V.
Cl=15pF.
RL = 2 kO.

VCC=4.5Vto5.5V.
CL= 50 pF

UNIT

SN74HC'
SN54HC'
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX
MHz

f max
tplH
tpHl
tPlH
tpHl
tPlH
tpHl
tplH

ClR

AnyY

ns

ClK

co

ns

ClK

AnyY

ns

ClR

CO

ns

Power dissipation capacitance
NOTE1: For load circuit and voltage waveforms. see page 1-14.

3-198

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

pF typ

TYPES SN54HC4020, SN74HC4020
ASYNCHRONOUS 14-BIT BINARY COUNTERS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC4020 ... JPACKAGE
SN74HC4020 ... J OR N PACKAGE
(TOPVIEWI

description
These devices are 14-stage binary ripple-carry counters that advance on the negative-going edge of the
clock pulse. The counters are reset to zero (all
outputs low) independently of the clock· when CLR
goes high.

Ol
OM
ON
OF
OE
OG

VCC
OK
OJ
OH

00

ClK

01
ClR

GNO ........._ _....J_OA
SN54HC4020 ... FH OR FK PACKAGE
SN74HC4020 ... FH OR FN PACKAGE
(TOPVIEWI

The SN54HC4020 is characterized for operation
over the full military temperature range of -55°C to
125°C. The SN74HC4020 is characterized for operation from -40°C to 85°C.

..

logic symbol
RCTR14
OA
00
CLR (111

CT=O

9 1011 1213

OE
OF
OG

.J:1+

NC - No internal connection

°H

CT

01
OJ
OK
OL

OM
ON
Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6.

timing requirements (supplement to recommended operating conditions)
SN54HC4020
MIN
NOM
MAX

tw

Pulse duration
ClR high
Setup time. ClR inactive before ClKI

I ClK high or low

I

ns
ns

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

UNIT
MHz

fclock

Clock frequency

tsu

SN74HC4020
MIN
MAX
NOM

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-199

TYPES SN54HC4020, SN74HC4020
ASYNCHRONOUS 14-BIT BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

f max
tplH

tPHL
tPlH
tPHL
tpHL

VCC=6 v.
Vec = 4.6 V to 6.6 V.
CL = 15 pF.
CL = 60 pF
RL=2kn.
SN64HC'
SN74HC'
TA= 26°e
TA = 26°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

ClK

OA

ns

an

On+1

ns

ClR

Any

MHz

ns

Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms, see page 1 -14 .

•

3-200

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

pFtyp

TYPES SN54HC4040, SN74HC4040
ASYNCHRONOUS 12-BIT BINARY COUNTERS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality
and Reliability

SN54HC4040 ... J PACKAGE
SN74HC4040 ... J OR N PACKAGE
.
(TOP VIEW)
Ol
OF
OE

description
This device is an asynchronous 12-stage binary counter
~. with the outputs of all stages available externally. A high
level at ClR asynchronously clears the counter and resets
all outputs low. The count is advanced on a high-to-Iow
transition at ClK. Applications include time delay circuits.
counter controls. and frequency-dividing circuits.

OG

. VCC
OK
OJ
OH

00

0,
ClR
ClK

Oc
Os
GNO

OA

SN54HC4040 ... FH OR FK PACKAGE
SN74HC4040 ... FH OR FN PACKAGE
(TOP VIEW)

The SN54HC4040 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC4040is characterized for operation from -4;0°C to
85°C.

u..

...J

U

t3

U

<{~

~

OOz>o

..

logic symbol
RCTR12

ale

O~ZOd
CLR

(111

NC -

No internal connection

CT=O

..D"+
CT

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV. page 2-6.

timing requirements (supplement to recommended operating conditions)
SN74HC4040

SN54HC4040
MIN

NOM

MAX

NOM

MAX

UNIT
MHz

fclock

Clock frequency

tw

Pulse duration

tsu

Setup time. ClR inactive before ClKI

I ClK high or low
I ClR high

ns
ns

Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

MIN

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-201

TYPES SN54HC4040, SN74HC4040
ASYNCHRONOUS 12-B11 BINARY COUNTERS
switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

VCC= 5 V.
VCC = 4.5 V to 5.5 V.
CL = 15 pF.
CL = 50 pF
RL=2kn.
SN54HC'
SN74HC'
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

FROM
(INPUT)

TO
(OUTPUT)

ClK

OA

ns

an

On+1

ns

CLR

Any

.. MHz

f max
tpLH
tPHl
tplH
tpHL
tpHL

ns

Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14 .

..

3-202

UNIT

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

pF typ

TYPES SN54HC4060, SN74HC4060
ASYNCHRONOUS 14-STAGE BINARY COUNTERS
AND OSCILLATORS

HIGH-SPEED
CMOS LOGIC

02684. DECEM8ER 1982

•

Allows Design of Either RC or Crystal
Oscillator Circuits

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC4060 ... J PACKAGE
SN74HC4060 ... J OR N PACKAGE
(TOP VIEW)

QL
QM
QN
QF
QE
QG
QD
GND

Dependable Texas Instruments Quality
and Reliability

description
The 'HC4060 consists of an oscillator section and 14
ripple-carry binary counter stages. The oscillator
configuration allows design of either RC or crystal
oscillator circuits. A negative transition on the clock
input increments the counter. A high level at CLR
disables the oscillator (CKO goes high and CKO goes
low) and resets the counter to zero (all Q outputs
low).
The SN54HC4060 is characterized for operation
over the full military temperature range of -55°C to
125°C. The SN74HC4060 is characterized for operation from -40°C to 85°C.

VCC
QJ
QH
QI
CLR
CKI
CKO
CKO

SN54HC4060 ... FH OR FK PACKAGE
SN74HC4060 ... FH OR FN PACKAGE
(TOP VIEW)

~

...J

d d

QN
QF
NC
QE
QG

U

Z

~

>

..,

d

4

QH
QI
NC
CLR
CKI

5
6

7.
8

logic symbol
U
d0 0
Z Z
(!)

NC -

II

010
~

U

~

U

No internal connection

RCTR14

00

OE
OF
OG
OH
01

OJ
OL
OM
ON
CKO

CKI (11)

Z1

(9)

CKO

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV, page 2-6.
PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-203

TYPES SN54HC4060, SN74HC4060
ASYNCHRONOUS 14-STAGE BINARY COUNTERS AND OSCILLATORS
timing requirements (supplement to recommended operating conditions)
SN54HC4060
MIN

NOM

MAX

SN74HC4060
MIN
NOM
MAX

UNIT

I CKI high or low
I CLR high

tw

Pulse duration

tsu

Setup time. CLR inactive before CKII

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

Vec= 5 v.
CL = 15 pF,

VCC = 4.5 V to 5:5 V.
CL = 50 pF
RL=2kO,
SN54HC'
SN74HC'
TA = 25°e
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

MHz

f max
tpLH
tpHL

II

CKI

OD

ns
ns

tpLH
tpHL

On

On+)

tpHL

CLR

AnyO

ns

Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

3-204

TEXAS INSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • OALLAS. TeXAS 75265

pF typ

HIGH~SPEED

TYPES SN54HC4075, SN74HC4075
TRIPLE 3-INPUT OR GATES

CMOS LOGIC

02684. DECEM8ER 1982

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC4075 ... J PACKAGE
SN74HC4075 ... J OR N PACKAGE
(TOP VIEW)
1A

These devices contain three independent 3-input OR gates and
perform the boolean functions Y = A + B + C or Y = A'B'C in
positive logic.

38

2A
28
2C

3A
3Y

2Y

1Y

GND

1C

description

The SN54HC4075 is characterized for operation over the full
military temperature range of -55°C to 125°C. The
SN74HC4075 is characterized for operation from -40°C to
85°C.

VCC
3C

18

SN54HC4075 ... FH OR FK PACKAGE
SN74HC4075 ... FH OR FN PACKAGE
(TOP VIEW)

logic symbol

2019

3 2
2A

1A
18
1C
2A
28
2C

(1 )

2':1
(9)

(2)

3A

NC
2C

NC
3Y

(3)

9 10 11 1213

(4)

(6)

2Y

>('oj

(5)

0

Z

U

Z

U

~

>~

(!)

NC - No internal connection

3A

(10)

38
3C

1Y

(8)

3B
NC

NC
28

3Y

FUNCTION TABLE

(13)

INPUTS
Pin numbers sh.own are for J and N packages.

OUTPUT

A

8

C

H

X
X

X
H

X
X

X

H

L

L

L

Y
H
H
H
L

maximum ratings, recommended operating conditions, and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC=5 V.
CL = 15 pF.
RL=2kO.

VCC = 4.5 V to 6.6 V.
CL = 60 pF

TA = 26°C
TA = 26°C
MIN TYP MAX MIN TYP MAX
tpLH
tpHL

A. 8. or C

SN64HC'
MIN MAX

UNIT
SN74HC'
MIN MAX

Y

ns

Power dissipation capacitance per gate

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instrument. reserves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-205

.HIGH-SPEED
CMOS LOGIC

TYPES SN54HC4078, SN74HC4078
8-INPUT NOR GATE
02684. DECEMBER 1982

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

SN54HC4078 ... J'PACKAGE
SN74HC4078 ... J OR N PACKAGE
(TOP VIEW) ,

NC

VCC
y

A
B

These devices contain a single 8-input NOR gate and
perform the following boolean functions in positive logic:
Y = A + 8 + C + 0 + E + F + G + H or

The SN54HC4078 is characterized for operation over the
full military temperature range of -55°C to 125°C. The
SN74HC4078 is characterized for operation from -40°C to
85°C.

NC

3 2

OUTPUT
V

All inputs L
One or more inputs H

F
E

u u u
u
< z z >

FUNCTION TABLE

II

G

SN54HC4078 ... FH OR FK PACKAGE
SN74HC4078 ... FH OR FN PACKAGE
(TOP VIEW)

y=A·B·C·D·E·F·G·H

INPUTS A
THRU H

H

C
D
NC
GND

description

>

2019

B

H

NC
C
NC

G

NC
NC

D

H
L

9

uouuw
z z z z

logic symbol

(!)

(2)
A

B
C

0

2':1

NC -

No internal connection

(3)
(4)
(5)

(13)

V

(9)

E
F
G

H

(10)
(11\

(12)

Pin numbers shown are for J and N packages.

maximum ratings. recommended operating conditions. and electrical characteristics
See Table I. page 2-3.

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH

FROM
(INPUT)

TO
(OUTPUT)

Athru H

y

VCC=5V.
CL=15pF.

,.

VCC = 4.5 V to 5.5 V.
CL = 50 pF
RL=2 kn.
SN54HC'
SN74HC'
TA = 25°C
TA =26°C
MIN TVP'MAX MIN TVP MAX MIN MAX MIN MAX

ns

tpHL
Cpd

UNIT

Power dissipation capacitance

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

PRODUCT PREVIEW

3-206

This document contains information on a _
product under development. Texas Instruments reserves the right to change or discontinua this product witho(it notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265.

TYPES SN54HC4511. SN74HC4511
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
WITH LATCHED INPUTS

HIGH-SPEED
CMOS LOGIC

02684. DECEMBER 1982

SN54HC4511 ... J PACKAGE
SN74HC4511 ... J OR N PACKAGE
(TOP VIEW)

•

Latch Storage of Code

•

Blanking Input

•

Lamp Test Provision

•

Readout Blanking on All Illegal Input Combinations

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

Vee

B

e

a

LE

b

0
d

Dependable Texas Instrume.nts Quality and Reliability

description
The 'HC4511 provides the functions of a 4-bit storage latch, a
BCD-to-seven-segment decoder, and an output driver. Lamptest
(IT), blanking (Bi), and latch enable (LE) inputs are used to test the
display, to turn off or pulse-modulate the brightness of the
display, and to store a BCD code, respectively.

GND

e

SN54HC4511 ... FH OR FK PACKAGE
SN74HC4511 ... FH OR FN PACKAGE
(TOP VIEW)
U

e

u

> _

III Z

3 2

The SN54HC4511 is characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC4511
is characterized for operation from -40°C to 85°C.

..

2019
9

Bi
Ne
LE

NC
b

o
FUNCTION TABLE

<{

c

Z

INPUTS
LE
L

BI
H

H

L

H
H
H
H
H
H

L
L

H
H
H
H
H
H
H
H

L

H

L
L

H
H
H
H
H

H
H
H
H
H
H

L
L
L
L
L

L
L
L

LT

a

b

L

H

H

L

L

H
H
H
H
H

H

H

L

L

H

H

L

L

L

H

H

H

H

L
H

L

L

L
L
L

L
L

H

L

H

L

H

L

L

H
X
X

H
H
X
X

H
X
X

X

X

X

0
1

H

H

L

H

2

H
H

H

L
L

L

L

H
H

4

L

H

L

H

H
H

H

H

L

L

H
H

H
H
H

L

H

H

H

H

L

L

L
L

L
L

L
L

L

L

L

L

L

L

L

L

L

L

L

L

L

H

H

L

L

L

L

L

L

H

L

L
L

L
L.

H

H

H
H

H

L

L

L

H

L

L

H

H

H

L

H

H

H
H

L
L

H
H

L
L

H

H

H
H

X
L

L
H

H
X
X

H

H

H

X

L

L

A

H

L

DISPLAY

L

B
L

H

H

e
H

9
L

C
L

L
X
X

c
H
H

f
H
L

D
L

L

d

U

CIl

'0

Z

(!)

OUTPUTS

L

H
H

H

H

H

H

NC -

No internal connection

logic symbol
BCOn-SEG
[T4)

3

5
6

IT
Bi

L

7

8
9

LE

H

H
H

L
L

L
L

Blank
Blank

B

2

C

4

L
L

L

Blank

0

L

Blank

L

L

Blank

L

L
L

L

L

Blank

H

H

H

H

8

L

L

L

H
L

L

Blank

I>

A
el0,11
flO,11
910,11

Pin numbers shown are for J and N packages.

All outputs remain in state
existing before LEI

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6.
Copyright ©1982 by Texas Instruments Incorporated

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments resarves the right to change or discontinue this product without notice.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-207

TYPES SN54HC45", SN74HC45,11
BCD~ TO~SEVEN~SEGMENT DECODERS/DRIVERS
WITH LATCHED INPUTS
SEGMENT IDENTIFICATION

FONT TABLE T4RESULTANT DISPLAYS USING 'HC4511

2

3

4

5

6

7

8

9

timing requirements (supplement to recommended operating conditions)
SN54HC4511
MIN
NOM
MAX

UNIT

Pulse duration, LE low
Setup time, data before LEI
Hold time. data after LEI

tw

..

SN74HC4511
MIN
NOM
MAX

tsu
th

ns
ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)
VCC=5V,
VCC = 4.5 V to 5.5 V,
CL = 15 pF,
CL = 50 pF
RL=2kn.
SN54HC'
SN74HC'
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

tpLH
tpHL

Athru D

a thru 9

ns

Bi

a thru 9

ns

LT

a thru 9

ns

LE

a thru 9

ns

tPLH
tpHL
tpLH
tpHL
tPLH
tpHL

-

Power dissipation capacitance
NOTE 1: For load circuit and voltage waveforms. see page 1-14.

3-208

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

UNIT

pF typ

TYPES SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515
HIGH-SPEED
4-UNE TO 16-UNE DECODERS/DEMULTIPLEXERS
CMOS LOGIC
WITH ADDRESS LATCHES
02684. DECEMBER 1982

•

Two Output Options:
'HC4514 Has Active-High Outputs
'HC4515 Has Active-Low Outputs

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

SN54HC' ... JT PACKAGE
SN74HC' ..• JT OR NT PACKAGE
(TOPVIEWI

lE
A
B
Y7

•

Dependable Texas Instruments Quality
and Reliability
Y4
Y3
Y1
Y2
YO
GND

description
These devices present two output options of a 4-to16 line decoder with latched inputs. The 'HC4514
presents a high level at the selected output. The
'HC4515 presents a low level at the selected output.
These devices consist of four storage latches with
common latch enable (LEI and inhibit (G) inputs.
When a low signal is applied to the LE input, the
input data is stored, decoded, and presented to the
output. When LE is high, all sixteen 'HC4514 outputs
are at a low logic level, or all 'HC4515 outputs are a
high logic level.
The SN54HC4514 and the SN54HC4515 are characterized for operation over the full military temperature ra nge of -55°C to 125°C. The SN74HC4514
and SN54HC4515 are characterized for operation
from -40°C to 85°C.

VCC
G
0
C
Y10
Y11
Y8
Y9
Y14

Y15
Y12
Y13

SN54HC' ... FH OR FN PACKAGE
SN74HC' .•. FH OR FN PACKAGE
(TOPVIEWI

•

C

Y7
Y6
Y5

Y10
Y11

NC

NC

Y4
Y3
Y1

Y8
Y9
Y14
NOOUMNI.O

»z
z(,!)
»->

FUNCTION TABLE

LE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
l

G
l
l
L
L
L
l
L
L
L
L
L
L
l
l
l
l
H
L

INPUTS
D C B
l
l
L
l
l
L
L H
l
L
L
H
H
L
L
H l
l
H H
l
L
H H
H
L
L
H
L
L
H
L
H
l
H
H
H L
H
H H L
H
H H
H H H
X
X
X
X
X
X

A
l
H
L
H
l
H
L
H
l
H
l
H
L
H

OUTPUT
SELECTED
0
1
2

OUTPUTS
'HC4614
'HC4515

NC -

No internal connection

3
4

5
6
7
8
9
10
11
12
13
14
15

Selected

Selected

=H
All others =l

Output= l

Output

All others =H

l
H
X
All =L
All =H
X All outputs remain in state existing before LEI

PRODUCT PREVIEW
This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas·lnstruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TexAS 75265

3-209

TYPESSN54HC4514,SN54HC4515,SN74HC4514,SN74HC4515
4-LlNE TO 16-LlNE DECODERS/DEMULTIPLEXERS
.
WITH ADDRESS LATCHES
'HC4514 logic symbols (alternatives)

XIV

OMUX

YO

0

Yl
Y2

LE

(11

Y3

C20

V4
V6

B
4
B

A

(11

(21

Yl

(31

Y4
Y5

200

jG*

YB
V9
Yll

YO

Y3

C20

V6
Y7
VB
9

Vl0

G

..

LE

V7

C
0

(91

Y2

V5

A

(111

V9
Yl0

G

11

Y11

V12

12

Y12

13

V13

13

Y13

14

V141

14

Y14

15

Y15

15

Y15

11

Pin numbers shown are for JT and NT packages.

'HC4515 logic symbols (alternatives)

XIV

OMUX

YO

YO

Yl

Yl

Y2

LE

(1)

Y3

C20

Y4

(1)

Y3

C20

Y4

Y5

A

Y5
200

Y6

B

Y7

C

YB

0

G

Y2

LE

Y9

jG*

Yl0
11

Yl1

G

Y7
YB
Y9
10

Yl0

11

Yll

12

Y12

12

V12

13

Y13

13

Y13

14

Y14)

14

Y14

15

Y15

15

Y15

Pin numbers shown are for JT and NT packages.

3-210

Y6

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFiCe BOX 225012 • DALLAS. TexAS 75265

TYPES SN54HC4514, SN54HC4515, SN74HC4514, SN74HC4515
4-UNE TO 16-UNE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
maximum ratings. recommended operating conditions. and electrical characteristics
See Table IV. page 2-6.

timing requirements (supplement to recommended operating conditions)
MIN

SN54HC'
NOM
MAX

MIN

SN74HC'
MAX
NOM

UNIT

tw

Pulse duration.LE high

ns

tsu
th

Setup time before LEI
Hold time after LEI

ns

ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
Cpd'

FROM
(INPUT)

TO
(OUTPUT)

VCC= 6 V.
CL = 16 pF.

VCC = 4.5 V to 5.5 V.
CL = 50 pF

RL=2 kO.
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX

SN54HC'
MIN MAX

UNIT
.SN74HC·
MIN

MAX

Athru 0

Any

ns

LE

Any

ns

G

Any

ns

Power diSSipation capacitance

II

pFtyp

NOTE 1: For load circuit and voltage waveforms. see page 1 -14.

TEXAS (NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

3-211

TYPES SN54HC4538, SN74HC4538
DUAL PRECISION RETRIGGERABLE/RESETTABLE
MONOSTABLE MULTIVIBRATORS

HIGH-SPEED
CMOS LOGIC

02684, DECEM8ER 1982

•

Positive- and Negative-Edge Triggered
Inputs with Hysteresis

•

Complementary Outputs Available

•

Independent Clear Inputs

•

Wide Range of Output Pulse Durations

•

Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

•

SN54HC4538 , , , J PACKAGE
SN74HC4538 ... J OR N PACKAGE
(TOP VIEW)
VCC
2C ext

1A

2CLR
2A

2Rext/Cext

18
10

2B

10

20

in

GND

Dependable Texas Instruments Quality
and Reliability

SN54HC4538 ... FH OR FK PACKAGE
SN74HC4538 .. , FH OR FN PACKAGE
(TOPVIEWI

description

II

1Cex t
1 Rext/Cext
1CLR

The 'HC4538 can be triggered by either the positiveor the negative edge of an input pulse. This device
will produce an accurate output pulse over a wide
range of pulse durations. The output pulse duration
and accuracy are determined by the external timing
components Cext and Rext. Trigger and clear propagation delays are independent of Rext and Cext.

3 2

1 2019

1CLR

2Rext/Cext

1A

A clear input is provided for immediate termination
of the output pulse or to prevent output pulses when
power is turned on.

2CLR

NC

NC

1B

2A
2B

10

14
9 10111213

The SN54HC4538 is characterized for operation
over the full military temperature range of -55°C to
125°C. The SN74HC4538 is characterized for operation from -40°C to 85°C.

10 0
~

Z

10 0

U
Z

N

N

(!)

NC -

No internal connection

logic symbol

FUNCTION TABLE

CLEAR

A

L

X
H
X
L
I

X
X
H
H

2:1

OUTPUTS

INPUTS
B
X
X
L
I
H

Q

Q

18

L

H

lCLR

L
L

H
H
1.[

1 Rext/Cext

1..[

2A

Sl
Sl

.n.

lA

lCex t

..n.
(10)

2Q

28
2ClR
2C ex t
2Rext/ Cext

(9)
--=....;..~*--I

(14)

ex
RX/CX

Pin numbers shown are for J and N packages.

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV, page 2-6.
Note: The minimum recommended supply voltage for this device is 3 V.

PRODUCT PREVIEW -

3-212

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS (NSTRUMENTS
INCORPORATED

POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TYPES SN54HC4538. SN74HC4538
DUAL PRECISION RETRIGGERABLE/RESETTABLE
MONOSTABLE MULTIVIBRATORS
timing requirements (supplement to recommended operating conditions)
SN54HC4538
MIN
NOM
MAX
tw
Rext

Pulse duration. A high or Blow
External timing resistance

Cext

External timing capacitance

SN74HC4538
MIN
MAX
NOM

UNIT
MHz

kn
JJf

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

A
B
A

tPLHt
tPHLt

B

tPHLt
tPLHt
two(min)t
twot

-

CLR

AorB
AorB

TO
(OUTPUT)

'VCC=5V.
VCC = 4.5 V to 5.5 V.
CL=15pF.
Cl =50 pF
RL = 2 kn.
SN54HC'
SN74HC'
TA = 25°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

0

ns

0

ns

0
0
0
0

ns
p.s

ns

Power diSSipation capacitance per monostable

=

UNIT

No load. TA = 25°C

pFtyp

..

=

tCext 0, Rext 5kO
ttwQ =duration of pulse at output Q,
NOTE 1: For load circuit and voltage waveforms, see page 1 -14.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

3-213

HIGH-SPEED
CMOS LOGIC

TYPES SN54HC4724, SN74HC4724
8-BIT ADDRESSABLE LATCHES
02684. DECEMBER 19B2

•

a-Bit Parallel-Out Storage Register Performs Serial-toParallel Conversion with Storage

•

Asynchronous Parallel Clear

•

Active-High Decoder

•

Enable Input Simplifies Expansion

•

Expandable for N-Bit Applications

•

Four Distinct Functional Modes

•

Package Options Include Both Plastic and Ceramic
Chip Carriers in Addition to Plastic and Ceramic DIPs

•

Dependable Texas Instruments Quality and Reliability

Vcc

50
51
52
00
01
02
03

description

II

SN54HC4724 ... J PACKAGE
SN74HC4724 ... J OR N PACKAGE
(TOP VIEW)

CLR

G
0
Q7

06
05
04

GND

SN54HC4724 ... FH OR FK PACKAGE
SN74HC4724 ... FH OR FN PACKAGE
(TOP VIEW)

These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific uses
include working registers, serial-holding registers, and activehigh decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable
latches, and being a 1-of-8 decoder or demultiplexer with
active-high outputs.

3 2

2019

52
00

G

NC

NC

o

01

Four distinct modes of operation are selectable by controlling
02
the clear (ClR) and enable {IT) inputs as enumerated in the
function table. In the addressable-latch mode, data at the datain terminal is written into the addressed latch. The addressed
latch will follow the data input with all unaddressed latches
remaining in their previous states. In the memory mode, all
NC latches remain in their previous states and are unaffected by the
logic symbol
data or address inputs. To eliminate the possibility of entering
erroneous data in the latches, enable IT should be held high
(inactive) while the address lines are changing. In the 1-of-8
decoding or demultiplexing mode, the addressed output will
follow the level of the D input with all other outputs low. In the
clear mode, all outputs are low and unaffected by the address
and data inputs.

Q7

06

No internal connection

(4)

The SN54HC4724 i.s characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74HC4724
is characterized for operation from -40°C to 85°C.

QO

10,oR
11.10

(5)

10JR
8,20

(8)
02

10,2R
11,30

(7)
03

10.3R
9.40

(8)

04

10,4R
9,50

(10)
05

lo;5R
9.80

(11)

08

lo;iR
9,70

01

(12)

1o;iR

07

Pin numbers shown are for J and N packages.

PRODUCT PREVIEW

3-214

This document contains information on a
product under development. Texas Instruments reserves the right to change or discontinue this product without notice.

Copyright ©1982 by Texas Instruments Incorporated

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TYPES SN54HC4724, SN74HC4724
8-BIT ADDRESSABLE LATCHES
FUNCTION TABLE

INPUTS
CLR
G
L
L
L
H
H

H
L
H

OUTPUT OF
ADDRESSED
LATCH
D
aiO
D
L

LATCH SELECTION TABLE

EACH
OTHER
OUTPUT

FUNCTION
Addressable Latch
Memory
a-Line Demultiplexer
Clear

aiO
aiO
L
L

0= the level at the data input.
0iQ = the level of 0i (i = 0.1. '....7. as appropriate) before the indicated
steady-state input conditions were established'.

SELECT INPUTS
S2
S1
SO
L
L
L
H
L
L
L
L
H
H
H
H

H
H
L

L
H
L
H
L
H

L
H
H

LATCH
ADDRESSED

0
1
2

3
4
5
6
7

maximum ratings, recommended operating conditions, and electrical characteristics
See Table IV. page 2-6.

timing requirements (supplement to recommended operating conditions)
SN54HC4724
MIN
NOM
MAX

SN74HC4724
MAX
NOM

UNIT

MIN

I G)ow
I CLR high

tw

Pulse duration

tsu
th

Setup time before GI
Hold time after GI

ns

..

ns
ns

switching characteristics over recommended operating free-air temperature range (unless otherwise
noted)

PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

VCC= 5 V.
V.ce = 4.6 V to 5.5 V.
CL=16pF.
CL = 50 pF
RL = 2 kn.
SN54HC08 SN74HC08
TA = 26°C
TA = 25°C
MIN TYP MAX MIN TYP MAX MIN MAX MIN MAX

UNIT

CLR

Any

ns

Data

Any

ns

tplH
tpHL

Address

Any

ns

tPLH
tpHL

G

Any

ns

tpHL
tpLH
tpHL

Power diSSipation capacitance

pF typ

NOTE 1: For load circuit and voltage waveforms. see page 1-14.

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..

3-216

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Expla nation of
Logic Symbols

II

4-1

TABLE OF CONTENTS

Title
1.
2.
3.

4.

II

5.
6.

7.
8.
9.
10.

Page

INTRODUCTION ........................................................ 4-3
SYMBOL COMPOSITION .................................................. 4-3
QUALIFYING SYMBOLS
................................................. 4-5
3.1
General Qualifying Symbols
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
3.2
Qualifying Symbols for Inputs and Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
3.3
Symbols Inside the Outline ........................................... 4-9
DEPENDENCY NOTATION ................................................ 4-10
4.1
General Explanation
................................................ 4-10
4.2
G,AND .......................................................... 4-10
4.3
Conventions for the Application of Dependency Notation in General ........... 4-12
4.4
V,OR
........................................................... 4-13
4.5
N, Negate (Exclusive OR)
............................................ 4-13
4.6
Z, Interconnection
................................................. 4-14
4.7
C, Control ........................................................ 4-15
4.8
S, Set and R, Reset ................................................. 4-15
4.9
EN, Enable
.' ...................................................... 4-16
4.10
M, Mode
......................................................... 4-17
4.11
A, Address ........................................................ 4-19
BISTA8LE ELEMENTS
....... , ....... , ................................... 4-22
CODERS ............................................................... 4-23
USE OF A CODER TO PRODUCE AFFECTING INPUTS ......................... 4-24
USE OF BINARY GROUPING TO PRODUCE AFFECTING INPUTS ................ 4-25
SEQUENCE OF INPUT LABELS ............................................ 4-25
SEQUENCE OF OUTPUT LABELS .......................................... 4-26

LIST OF TABLES

Table
I.
II.
III.
IV.

Title

Page

General Qualifying Symbols
................................................ 4-6
Qualifying Symbols for Inputs and Outputs
.................................... 4-7
Symbols Inside the Outline ................................................. 4-8
Summary of Dependency Notation ........................................... .4-21

If you have questions on this Explanation

IEEE Standards may be purchased from:

of Logic Symbols, please contact:
Institute of Electrical and Electronics Engineers,
F .A. Mann MS 49

345 East 47th Street

Texas Instruments Incorporated

New York, N.Y. 10017

P.O. Box 225012
Dallas, Texas 75265

International Electrotechnical Commission (lEC)

Telephone (214) 995·2867

publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018

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EXPLANATION OF LOGIC SYMBOLS

by F. A. Mann
INTRODUCTION
The International Electrotechnical Commission (IEC) has been developing a very powerful symbolic
language that can show the relationship of each input of a digital logic circuit to each output without
showing explicitly the internal logic. At the heart of the system is dependency notation, which will be
explained in Section 4.
The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard Y32.14-1973.
Lacking at that time a complete development of dependency notation, it offered little more than a
substitution of rectangular shapes for the familiar distinctive shapes for representing the basic functions
of AND, OR, negation, etc. This is,no longer the case.
Internationally, Working Group 2 of IEC Technical Committee TC-3 is preparing a new document
(Publication 617-12) that will consolidate the original work started in the mid 1960's and published
in 1972 (Publication 117-15) and the amendments arid supplements that have followed. Similarly
for the USA, IEEE Committee SCC 11.9 is revising the publication IEEE Std 91/ANSI Y32.14.
Texas Instruments is participating in the work of both organizations and this Data Book introduces
new logic symbols in anticipation of the new standards. When changes are made as'the standards
develop, future editions will take those changes into account.

•

The following explanation of the new symbolic language is necessarily brief and greatly condensed
from what the standards publications will finally contain. This is not intended to be sufficient for
those people who will be developing symbols for new devices. It is primarily intended to make possible
the understanding of the symbols used in this book; comparing the symbols with functional block
diagrams and/or function tables will further help that u~derstanding.
2

SYMBOL COMPOSITION
A symbol comprises an outline or a combination of outlines together with one or more qualifying
symbols. The shape of the symbols is not significant. As shown in Figure 1, general qualifying symbols
are used to tell exactly what logical operation is performed by the elements. Table I shows the general
qualifying symbols used in this data book. Input lines are placed on the left and output lines are
placed on the right. When an exception is made to that convention, the direction of signal flow is
indicated by an arrow as shown in Figure 11.
All outputs of a single, unsubdivided element always have identical internal logic states determined by
the function of the element except when otherw'ise indicated by an associated qualifying symbol
or label inside the element.

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EXPLANATION OF LOGIC SYMBOLS
OUTLINE

GENERAL QUALIFYING
SYMBOL

I **

**1

INPUT
LINES

**

OUTPUT
LINES

**

*Possible positions for qualifying symbols relating to inputs and outputs
FIGURE 1 - SYMBOL COMPOSITION

The outlines of elements may be abutted or embedded in which case the following conventions apply.
There is no logic connection between the elements when the line common to their outlines is in the
direction of signal flow. There is at least one logic connection between the elements when the
line common to their outlines is perpendicular to the direction of signal flow. The number of
logic connections between elements will be clarified by the use of qualifying symbols and this is

II

discussed further under that topic. If no indications are shown on either side of the common line, it
is assumed there is only one connection.
When a circuit has one or more inputs that are common to more than one element of the circuit, the
common-control block may be used. This is the only distinctively shaped outline used in the I EC
system. Figure 2 shows that unless otherwise qualified by dependency notation,

an input to the

common-control block is an input to each of the elements below the common-control block.
COMMON~ONTROLBLOCK

FIGURE 2 - ILLUSTRATION OF COMMON· CONTROL BLOCK

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EXPLANATION OF LOGIC SYMBOLS
A common output depending on all elements of the array can be shown as the output of a commonoutput element. Its distinctive visual feature is the double line at its top. In addition the commonoutput element may have other inputs as shown in Figure 3. The function of the common-output
element must be shown by use of a general qualifying symbol.

COMMON-OUTPUT
ELEMENT

(must, like other elements,
have a qualifying symbol to
denote its logic function).

FIGURE 3 -ILLUSTRATION OF COMMON-OUTPUT ELEMENT

3

QUALIFYING SYMBOLS

II

3.1 General Qualifying Symbols
Table I shows the general qualifying symbols used in this data book. These characters are placed near
the top center or the geometric center of a symbol or symbol element to define the basic function
of the device represented by the symbol or of the element.
3.2 Qualifying Symbols for Inputs and Outputs
Qualifying symbols for inputs and outputs are ,shown in Table II and will be familiar to most users
with the possible exception of the logic polarity and analog signal indicators. The older logic negation
indicator means' that the external 0 state, produces the internal 1 state. The internal 1 state means the
active state. Logic negation may be used in pure logic diagrams; in order to tie the external 1 and 0
logic states to the levels H (high) and L (low), a statement of whether positive logic (1

= H, 0 = L)

or

negative logic (1 = L, 0 =' H) is being used is required or must be assumed. Logic polarity indicators
eliminate the need for calling out the logic convention and are used in this data book in the symbology
for actual devices. The presence of the triangular polarity indicator indicates that the L logic level will
produce the internal 1 state (the active state) or that, in the case of an output, the internal 1 state will
produce the external L level. Note how the active direction of transition for a dynamic input is
indicated in positive logic, negative logic, and with .polarity indication.

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EXPLANATION OF LOGIC SYMBOLS
TABLE 1- GENERAL QUALIFYING SYMBOLS

&

AND gate or function.

'HCOO

.. 1

OR gate or function. The symbol was chosen to indicate that at least
one active input is needed to activate the output.

'HC02

=1

Exclusive OR. One and only one input must be active to activate the output.

'HC86

Logic identity. All inputs must stand at same state.

'HC86

2k

An even number of inputs must be active.

'HC280.

2k+1

An odd number of inputs must be active.

'HC86

The one input must be active.

'HC04

A buffer or element with more than usual output capability (symbol
is oriented in the direction of signal flow).

'HC240

IT

Schmitt trigger; element with hysteresis.

'HC132

X/V

Coder, code converter (DEC/BCD, BIN/OUT, BINI7·SEG, etc.).

'HC42

MUX

Multiplexer/data selector.

'HC151

OMUX or OX

Demultiplexer.

'HC138

t> or ~

II

Postponed output (of a pulse-triggered flip-flop). The output changes when input
initiating change (e.g., a C input) returns to its initial external state or level. See § 5_

---1 EN

J, K, R, S, T

---1D
---1- m --1- m
~+m

-1-m

+

t

Output with more than usual output capability (symbol is oriented in the direction
of signal flow).
Enable input
When at its internal 1-state, all outputs are enabled.
When at its internal O-state, open-collector and open-emitter outputs are off,
three-state outputs are at normally defined internal logic states and at external
high-impedance state, and all other outputs (e.g., totem-poles) are at the
internaIO-state.
Usual meanings associated with flip-flops (e.g., R
Data input to a storage element equivalent to:

= reset, T = toggle)

~~

Shift right (left) inputs, m = 1,2,3 etc. If m = 1, it is usually not shown_
Counting up (down) inputs, m = 1,2,3 etc_ If m = 1, it is usually not shown_

D:}

Binary grouping. m is highest power of 2.

-1CT= 15'

The contents-setting input, when active, causes the content of a register to take
on the indicated value.

CT=9~

The content output is active if the content of the register is as indicated.
Input line grouping .... indicates two or more terminals used to implement a single
logic input.
e.g., The paired expander inputs of SN7450.

"1"~

4-8

~=:1JE

Fixed-state output always stands at its internal 1 state. For ex~mple, see SN74185.

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EXPLANATION OF LOGIC SYMBOLS
The application of internal inputs and outputs requires an understanding of dependency notation,
which is explained in Section 4.
In an array of elements, if the same general qualifying symbol and the same qualifying symbols
as~ociated

with inputs and outputs would appear inside each of the elements of the array, these

qualifying symbols are usually shown only in the first element. This is done to reduce clutter and to
save time in recognition. Similarly, large identical elements that are subdivided into smaller elements
may each be represented by an unsubdivided outline. The SN54HC242 symbol illustrates this principle.
3.3 Symbols Inside the Outline
Table III shows some symbols used inside the outline. Note particularly that open-collector, openemitter, and three-state outputs have distinctive symbols. Also note that an EN input affects all of the
outputs of the circuit and has no effect on inputs. When an enable input affects only certain outputs
and/or affects one or more inputs, a form of dependency notation will indicate this (s~e4-9). The
effects of the EN input on the various types of outputs are shown.
It is particularly important to note that a D input is always the data input of a storage element. At
its internal 1 state, the D input sets'the storage element to its 1 state, and at its internal 0 state it resets
the storage element to its 0 state.

II

The binary grouping symbol will be explained more fully in Section 8. Binary-weighted inputs are
arranged in order and the binary weights of the least-significant and the most-significant Iines are
indicated by numbers. In this data book weights of input and output lines will be represented by
powers of two usually only when the binary grouping symbol is used, otherwise, decimal numbers will
be used. The grouped inputs generate an internal number on which a mathematical function can be
performed or that can be an identifying number for dependency notation. See Figure 28. A frequent
use is in addresses for memories.
Reversed in direction, the binary grouping symbol can be used with outputs. The concept is analogous
to that for the inputs and the weighted outputs will indicate the internal number assumed to be
developed within the circuit..
Other symbols are used inside the outlines in this data book in accordance with the IEC/IEEE
standards but are not shown here. Generally these are associated with arithmetic operations and are
self-explanatory.
When nonstandardized information is shown inside an outline, it is usually enclosed in square brackets
[like these] .

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EXPLANATION OF LOGIC SYMBOLS
4

DEPENDENCY NOTATION

4.1

General Explanation
Dependency notation is the powerful tool that sets the I EC symbols apart from previous systems and
makes compact, meaningful, symbols possible. It provides the means of denoting the relationship
between inputs, outputs, or inputs and outputs without actually showing all the elements and interconnections involved. The information provided by dependency notation supplements that provided
by the qualifying symbols for an element's function.
In the convention for the dependency notation, use will be made of the .terms "affecting" and
"affected". In cases where it is not evident which inputs must be considered as being the affecting
or the affected ones (e.g., if they stand in an AND relationship), the choice may be made in any
convenient way.
So far, ten types of dependency have been defined and all of these are used in this data book. They are

..

listed below in the order in which they are presented and are summarized in Table IV following
4.1 ~ .
Section

Dependency Type or Other Subject

4.2

G, AND

4.3

General rules for dependency notation

4.4

V, OR

4.5

N, Negate, (Exclusive OR)

4.6

Z, Interconnection

4.7

C, Control

4.8

S, Set and R, Reset

4.9

EN, Enable

4.10

M, Mode

4.11

A, Address

4.2 G (AND) Dependency
A common relationship between two signals is to have them ANDed together. This has traditionally
been shown by explicitly drawing .an AND gate with the signals connected to the inputs of the gate.
The 1972 IEC publication and the 1973 IEEE/ANSI standard showed several ways to show this AND
relationship using dependency notation. While nine other forms of dependency have since been
defined, the ways to invoke AND dependency are now reduced to one.

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EXPLANATION OF LOGIC SYMBOLS
In Figure 4 input b is ANDed with input a and the complement of b is ANDed with c. The letter G has
been chosen to indicate AND relationships and is placed at input b, inside the symbol. A number
considered appropriate by the symbol designer (1 has been used here) is placed after the letter G and
also at each affected input. Note the bar over the 1 at input

c.

:~--­

c~
FIGURE 4 - G DEPENDENCY BETWEEN INPUTS

In Figure 5, output b affects input a with an AND relationship. The lower example shows that it is
the internal logic state of b, unaffe~ted by the negation si'gn, that is ANDed. Figure 6 shows input a to
be ANDed with a dynamic input b.

cctJ]
II
FIGURE 5 - G DEPENDENCY BETWEEN OUTPUTS AND INPUTS

a-iG'-b--t'

=

FIGURE 6 - G DEPENDENCY WITH A DYNAMIC INPUT

The rules for G dependency can be summarized thus:
When a Gm input or output (m is a number) stands at its internal 1 state, all inputs and outputs.
affected by Gm stand at their normally defined internal logic states. When the Gm input or output
stands at its

a state, all inputs and outputs affected by Gm stand at their internal a states.

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EXPLANATION OF LOGIC SYMBOLS
4.3 Conventions for the Application of Dependency Notation in General
The rules for applying dependency relationships in general follow the same pattern as was illustrated
for G dependency.
Application of dependency notation is accomplished by:
1)

labeling the input (or output) affecting other inputs or outputs with the letter symbol
indicating the relationship involved (e.g., G for AND) followed by an identifying number,

2)

appropriately chosen; and
labeling each input or output affected by that affecting input (or output) with that same
number.

If it is the complement of the internal logic state of the affecting input or output that does the affecting,
then a bar is placed over the identifying numbers at the affected inputs or outputs. See Figure 4.
If two affecting inputs or outputs have the same letter and same identifying number, they stand in an

•

OR relationship to each other. See Figure 7 .

a~G-1b

c

G1
1

a~~1
b
&
c

FIGURE 7 - OR'ED AFFECTING INPUTS

If the affected input or output requires a label to denote its function (e.g., "0"), this label will be
prefixed by the identifying number of the affecting input. See Figure 12.

If an input or output is affected by more than one affecting input, the identifying numbers of each of
the affecting inputs will appear in the label of the affected one, separated by commas. The normal
reading order of these numbers is the same as the sequence of the affecting relationships. See Figure
12.
If the labels denoting the functions of affected inputs or outputs must be numbers, (e.g., outputs
of a coder), the identifying numbers to be associated with both affecting inputs and affected inputs or
outputs will be replaced by another character selected to avoid ambiguity, e.g., Greek letters. See
Figure 8.

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EXPLANATION OF LOGIC SYMBOLS

={

--.

a

=[

a
b

oc
Goc

c

b

(i

c

--

1

~1
1

FIGURE 8 - SUBSTITUTION FOR NUMBERS

4.4 V (OR) Dependency
The symbol denoting OR dependency is the letter V. See Figure 9.

.lbv-.

·f~t· ... ~. -

=t: - =ro: -~:
FIGURE 9 - V (OR) DEPENDENCY

When a Vm input or output stands at its internal 1 state, all inputs and outputs affected by Vm stand
at their internal 1 states. When the Vm input or output stands at its internal 0 state, all inputs and
outputs affected by Vm stand at their normally defined internal logic states.

•

4.5 N (Negate) (X-OR) Dependency
The symbol denoting negate dependency is the letter N. See Figu're

10.

Each input or output affected

by an Nm input or output stands in an exclusive-OR relationship with the Nm input or output.

If a = 0, then c = b
If a = 1, then c =b
FIGURE 10 - N (NEGATE) (X·OR) DEPENDENCY

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EXPLANATION OF LOGIC SYMBOLS
When an Nm input or output stands at its internal 1 state, the internal logic state of each input and each
output affected by Nm is the complement of what it would otherwise be. When an Nm input or
output stands at its internal 0 state, all inputs and outputs affected by Nm stand at their normally
defined internal logic states.
4.6 Z (I nterconnection) Dependency
The symbol denoting interconnection dependency is the letter Z.
Interconnection dependency is used to indicate the existence of internal logic connections between
inputs, outputs, internal inputs, and/or internal outputs.
The internal logic state of an input or output affected by a Zm input or output will be the same as the
internal logic state of the Zm input or output, unless modified by additional dependency notation.
See Figure 11.

..

a-f~-tb

-

E=~a

-

E=~a

-

ba~1}-c

-

1Zl

'W'
W·
W·

where

---B- =-{>-

where

~=-~t

D G5
1 G6
2 G7
J G8

I
I

..

FIGURE 28 - USE OF THE BINARY GROUPING SYMBOL

9

SEQUENCE OF INPUT LABELS
If an input having a single functional effect is affected by other inputs, the qualifying symbol (if there
is any) for that functional effect is preceded by the labels corresponding to the affecting inputs.
The left-to-right order of these preceding labels is the order in which the effects or modifications
must be applied. The affected input has no functional effect on the element if the logic state of any
one of the affecting inputs, considered separately, would cause the affected input to have no effect,
regardless of the logic states of other affecting inputs.
If an input has several different functional effects or has several different sets of affecting inputs,
depending on the mode of action, the input may be shown as often as required. However, there are
cases in which this method of presentation is not advantageous. In those cases the input may be shown
once with the different sets of labels separated by solidi. See Figure 29. No meaning is attached to the
order of these sets of labels. If one of the functional effects of an input is that of an unlabelled input
of the element, a solidus will precede the first set of labels shown.

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EXPLANATION OF LOGIC SYMBOLS
If all inputs of a combinational element are
disabled (caused to have no effect on the

a~l--b

G2

function of the element), the internal logic

c

1~/~,~~

states of the outputs of the element are not
specified by the symbol. If all inputs of a
sequential element are disabled, the content
of this element is not changed and the outputs remain at their existing internal logic
states.
Labels

may

be

factored

using algebraic

FIGURE 29 - INPUT LABELS

techniques .

•

FIGURE 30 - FACTORING INPUT LABELS

10

SEQUENCE OF OUTPUT LABELS
If an output has a number of different labels, regardless of whether they are identifying numbers of
affecting inputs or outputs or not, these labels are shown in the following order:
1)

2)

if the postponed output symbol has to be shown, this comes first, if necessary preceded by
the indications of the inputs to which it must be applied;
followed by the labels indicating modifications of the internal logic state of the output,
such that the left-to-right order of these labe.ls corresponds with the order in which their
effects must be applied;

3)

4-26

followed by the label indicating the effect of the output on inputs and other outputs of the
element.

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EXPLANATION OF LOGIC SYMBOLS
Symbols

for

open-circuit

or

three-state

outputs, where applicable, are placed just
inside the outside boundary of the symbol
adjacent to the output line. See Figure 31.
If an output needs several different sets of
labels that represent alternative functions

FIGURE 31 - PLACEMENT OF 3-STATE SYMBOLS

(e.g., depending on the mode of action), these sets may be shown on different output lines that must
be connected outside the outline. However, there are cases in which this method of presentation is not
advantageous. In those cases the output may be shown once with the different sets of labels separated
by solidi. See Figure 32.
Two adjacent identifying numbers of affecting inputs in a set of labels that are not already separated
by a nonnumeric character should be separated by a comma.
If a set of labels of an output not containing a

8i;1--fC;:~b

solidus contains the identifying number of an

1CT=15

affecting Mm input standing at its internal 0

-------

state, this set of labels has no effect on that

af~-T~;=;n~i=~tb = af~--1cT:tb

output.
Labels

may

be

factored

using

algebraic

---------

-

1CT=15

------

II

FIGURE 32 - OUTPUT LABelS

techniques.

FIGURE 33 - FACTORING OUTPUT LABELS
If you have questions on this Explanation
of Logic Symbols, please contact:

IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street
New York, N.Y. 10017

F .A. Mann MS 49
Texas Instruments Incorporated
P.O. Box 225012
Dallas, Texas 75265
Telephone (214) 995-2867

International Electrotechnical Commission (lEe)
publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, N.Y. 10018

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THIS PAGE

II

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Ordering Instructions
and
Mechanical Data
I

II

5-1

ORDERING INSTRUCTIONS

Electrical characteristics presented in this data book. unless otherwise noted. apply for circuit type(s) listed in the page
heading regardless of package. The availability of a circuit function in 8 particular package is denoted by an
alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical outline
drawings shown in this section.
Factory orders for circuits described in this catalog should include a four-part type number as explained in the following
example.
EXAMPLE

~~

________________

SN

64HC02

J

-00

--J~

MUST CONTAIN TWO TO FOUR LETTERS
SN
SNJ

Standard Prefix
MIL-STD-883B Processed
JEDEC Screening Standard 101

2.

Unique Circuit Description

MUST CONTAIN SIX TO NINE CHARACTERS
Examples:

54HCOO
74HC74
74HC4002
3. Package
MUST CONTAIN ONE OR TWO LETTERS
J. JT. N. NT (Oual-in-line packages)t
FH. FK. or FN (Chip carriers)
(From pin-connection diagram on individual data sheetl

4. Instructions (Oesh No.1
MUST CONTAIN TWO NUMBERS
-

00 No special instructions
10 Solder-dipped leads IN and NT packages only)

T These circuits In dual·in·line packages are shipped in one of the Cllrrlers shown belOW. Unless a specific method of shipment is specified by the customer
Iwith possible additional costsl. circuits wiU be shipped In the most practical cllrner. Please contact your TI.ales representative for the method that Will best
SUit your particular needs

Dual-in-line (J. JT. N. NT)
-

5-2

Slide Magazines
A-Channel Plastic Tubing
Barnes Carrier IN only)
Sectioned Cardboard Box
Individual Plastic Box

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265

MECHANICAL DATA
FH and FK ceramic chip carrier packages
Both versions of these hermetically sealed chip carrier packages have ceramic bases. The FH package has a single·layer
base with a ceramic lid and glass seal. The F K package has a three·layer base with a metal lid and braze seal.
The packages are intended for surface mounting on solder lands on 1,27 (O.050·inch) centers. Terminals require no
additional cleaning or processing when used in soldered assembly.
FH and FK packages are identical to the FC and FD packages, respectively. The new designations are used to indicate
devices whose terminal assignments conform to a forthcoming JEDEC Standard.

FH AND FK CERAMIC CHIP CARRIER PACKAGES
(28-terminal package shown)

CERAMIC CHIP CARRIERS
~----------A----------~
~--------B--------~

JEOEC

NO. OF

OUTLINE
DESIGNATION'

TERMINALS

MIN

MAX

MIN

MAX

MS004CB

20

B.69
10.342)

9.09
10.358)

7.BO
10.3071

9.09
10.358)

2B

11.23
10.442)

11.63
10.458)

10.31

11.63

10.406)

10.458)

16.26

16.76

10.640)

10.660)

12.58
10.495)

10.560)

18.78

19.32

12.58

14.22

10.739)

10.761)

10.495)

10.560)

23.83

24.43

10.938)

10.962)

12.6
10.495)

10.862)

28.83
11.135)

29.59
11.165)

12.6
10.495)

27.0
11.065)

MS004CC
MS004CD

. 44

MS004CE
MS004CF
MS004CG

52
68
84

14.22

21.8

* All dimensions and notes for the specified JEDEC outline apply.

FK
(FD)

FH
(FC)

~I
1---+

2,54 (0.100)
1,63 (0.064)

~I

2,03 (O.OBO)

f--+~

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS, TEXAS 75265

5'-3

MECHANICAL DATA
FN plastic chip carrier package
Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound. The compound withstands soldering temperatures with no deformation, and
circuit performance characteristics remain stable when the devices are operated in high-humidity conditions. The
packages are intended for surface mounting on solder lands on 1 ,27-mm (O.050-inch) centers. Leads require no additional cleaning or processing when used in soldered assembly.

FN PLASTIC CHIP CARRIER PACKAGE

128·t.rmin.1 package shown)

NO.OF
TERMINALS
20
28

44
52
68

B

A
MIN
9,35
(0.368)
11,89
(0.468)
16,97
(0.668)
19,51
(0.768)
24,59
(0.968)

MAX
10,03
(0.395)
12,57
(0.495)
17,65
(0.695)
20.19
(0.795)
25,27
(0.995\

MIN
8,89
(0.350)
11,43
(0.450)
16,51
(0.650)
19,05
(0.750)
24.13
(0.950)

C
MAX
9,04
(0.356)
11,58
(0.456)
16,66
(0.656)
19,20
(0.756)
24,28
(0.956)

MIN
8,08
(0.318)
10,62
(0.418)
15,70
(0.618)
18,24
(0.718\
23,32
(0.918)

18
MAX·
8,38
(0.330)
10,92
(0.430)
16,00
(0.630)
18,54
(0.730\
23,62
(0.930)

17

[ 19

wwuunm

[ 20
( 21
( 22

8~

( 23

7 )

•

4,78 (0.188)
4,06 (0.160\
1,14 (0.045\
0,63 (0.025)
2,41 (0.095\ MIN
1,27 (0.050) X 45·
NOM

26

27

28

o

/
':-(0'045)~45.+

~

~------

NOM

B------~

A -------+1

L

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

5-4

A

6~

( 24
25

B

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE 80X 225012 • DALLAS, TEXAS 75265

1,35 (0.053)
1,19 (0.047)

MECHANICAL DATA
J ceramic packages (including JT packages)
Each ofthese hermetically sealed dual-in-line packages consists of a ceramic base, ceramic cap, and a lead
frame. Hermetic sealing is accomplished with glass. Once the leads are compressed and inserted sufficient
tension is provided to secure the package in the board during soldering. Tin-plated ("bright-dipped") leads
require no additional cleaning or processing when used in soldered assembly.
NOTE:

For the 14·, 16-. and 20-pin packages, the letter J is used by itself since these packages are available only in the 7.62 (0.300) row spacing.

14-PIN J CERAMIC

r;;

19.94 (0 7851
19,18 (0.7551

@@ @®

Fall,WithinJEDECTO·116and

@00

"'M.~'~-::·"="'~i:::: ::: I
7,87 (0.3101

114----1-1-

--I

(o.i~r(O.2901

0) CD

7,11
6,22 (0.2451

CD 0 CD 00
1,78 (0.070) MAX 14 PLACES

'"

'" ";""] ~~;~~~~~;~~;~~;~~~ S~.k~~T

ffi 8
(o.05OI NOM

5,08 (0.2001
MAX

.

- SEATING PLANE

105'

9ir

14PLACES -1\4"
0,356 ro:;;;41

058(00231
0:38 (0:0151 14 PLACES

3,30 (0.1301

0203 (0 0081
14 PLACES

MIN

2,54 (0.1001

~~i.~CO:~1

..

0,76 (0.0301 MIN
14 PLACES

.
~

PIN SPAC(': ~~s,:

~.1001 T.P.

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
16-PIN J CERAMIC
'9940.786~

19,1810.755)

I

~@@@®®@(!)

1:':·:~~
II"-1.rf~=
as

/h; ~r..

18 PLACES

'··='"'~i::::::J

~ SEATING PLANE - -.....- - , . - 1 ~

~\-~:: :~:~:
18 PLACES

.~

\;:;;:;g;:;;:;;:;;:;~~ SE';.~~T
1.--+l--+f--fftO,78 10.0301 MIN

jl.!...
~~\:~~~118
-II~

PLACES

.,3810 .• 1"

~:~ :~:~: 4 PLACES

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
NOTE: a, Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

TEXAS INSTRUMENTS
INCORPORATED
POST OFF)CE BOX 225012 • DALLAS, TEXAS 75265

5-5

MECHANICAL DATA
J ceramic dual-in-line packages (continued)
2G-PIN J CERAMIC
24.76(0.9751
I4lel-----23.62(0.9301

!l~!l

.~". "'~{!~~~~~~~J

7.87(03101
7.37 (0 290)
7.62 10.300\

~

1

1,27(0050) NOM

l1!\
~

---~·I

MAX

--SEATING PLANE

.W

20 PLACES

t, •
5.08(0200)

MIN
~~~

f

0.35610.014)
""'\\'-0,20310.008)
20 PLACES

0.30510.012) MIIiIJ
4 PLACES

I

~

I~I

PIN SPACING 2.5410.100) T. P.
ISeeNot•• )

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

24-PIN JT CERAMIC

1 - 0 - - - - 3 1 . 8 (1.2S0) M A X - - - - - . \

III
.....___'t.+-_

~:~~ :~:~~:

I"'---.Hi-- ~:~~ \~:~~~

1.27 (O.OSO) NOM

0000®00®®@@@
0.51 (0.020)
MIN

S.08~".""''''''''''p!II''.'''''''.''

GLASS
SEALANT

~~;OO} ~

SEATING PLANE - - - r.......----r-+~

~0.76 (0.030)

MIN

24 PLACES

--11- ~:~: :~:~~~: 24 PLACES

-.1\..- 0,356 (0.014)

~ \"

0.203 (0.008)
24 PLACES

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
NOTE: a. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.

5-6

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

MECHANICAL DATA
N plastic packages (including NT package)
Each of these dual-in-line packages consists of a circuit mounted on a lead frame and encapsulated within an
electrically conductive plastic compound. The compound will withstand soldering temperature with no deformation
and circuit performance characteristics remain stable when operated in high-humidity conditions. Once the leads are
compressed and inserted. sufficient tension is provided to secure the package in the board during soldering. Leads
require no additional cleaning or processing when used in soldered assembly.
NOTE:

For the 14-. 16-.20-. and 28-pin packages. the letter N is used by itself since these packages are available in only one row-spacing width -7.62
(0.300) for the 14-. 16-. 18-. and 20-pin packages and 15.24 (0.600) for the 28-pin package.

1i.E]11i.(:':~:~~~o;
"1

(0.250 ~ 0 0101

-+l

2.0 (0 0801 NOM

!S1

--,

--';;,25 (00101

•

-

~

14 PLACES

1-"1,78 (0 0701 MAX 14 PLACES

0'51(0.0201~1
508 (0.2001 MAX MIN

-L

NOM

'

:5l
--L..

•

SEATING PLANE - - .

0,84 (0.0331 MIN

1

J'~ 0,28' 0,08
(0.011 • 0.0031
14 PLACES

3,17 (0.1251 MIN

~

(0~~~:~:~~01

(Seo No'es bind cl

.,
.

4 PLACES

14 PLACES
045H 0078

I- (0:018.0:003)
14 PLACES

(SeoNo'lSblndc)

PIN SPACING 2,54 (0.100) T. P.
(SMNote a '

Falls Within JEDEC TO·116 and EIA MO-OO1AA Dimensions

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.

r

l6-PIN N PLASTIC

I----~ '-'"~:;:."
-106;~:~:~~01

., t

II

00000000
--t 1--1.1810.0101 MAX 16 PLACES

2.010.0801 NOM

. ....L.

t

0.51iO020i~11
MIN

5.08 10 .•001 MAX

~

---1

,:,:~:::-£
~ : :: : : :1

Ijr--r.:cl:l=.=
~O.25 (0.0101 NOM
L

198 101801 MAX

~@@)@)@@@)~

~I-SEATING PLANE

-*--

~

~P!LACES -.,r-IO.Ol1,O.ooll
_11- 0.28tO.08

l.1110.1251MIN

1SPLACES

O'S:2~~~!~IE~IN
_1~0457tDD76

-e.(

U~

"""1""""10:018,0:0031

1,65(0.065)

ISee NOlnband cl

16 PLACES

lSee Notnband cl

0,38 10.015)
4 PLACES

PIN SPACING 2,54 (0.1001 T. P.
(See Not•• '

-1
Parts may be supplied in accordance with the
altemate side view at the option of TI plants
located in Europe. In this case, the overall
length of the package is 22.1 (0.870) max.

t

ALTERNATE SIDE VIEW
t-"-1,78 10.0701 MAX 16 PLACES

0.51~~~20Imm

5.0810.2,1 MAX

L

~

l.111 0 .,25
.IMIN

O'~61~~!~IE~IN

L~

~1e-0.'51'0.016
(0.018tO.003)

2,41 (00951

1,02 (0.0401
4 PLACES

PIN SPACING

2,~

16 PLACES
(0.1001 T. P. (See NotHbandCI

(See Note_,

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES,
NOTES:

a. Each pin centerline is located within 0,25 (0,010) of its true longitudinal position.
b. This dimension does not apply for solder-dipped leads.
c. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane.

TEXAS INSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

5-7

MECHANICAL DATA
N plastic dual-in-line packages (continued)

I-

20·PIN N PACKAGE

-1

24.77(0.9751
23.2210.9141

W<®®®@@)@@@@

~~:·~=i:::::::J

000000000@

'PLACES
ALTERNATE SIDE VIEW
~

t-"-,.78 (0.0701 MAX 20 PLACES

to"'10'0201~'

p.,tlmaybelUp~jedjn

~eordanc:.wilhthe

,It.rnate sifH view It
theoptionofTlpientl

'7~ f3,94(0.1551
3,1710.125)

toc.tedinEuro~.

1,91 (0.0751

1.0210.00t01
'PLACES

J
-L

: : ; O , 8 4 10.033IMIN
.

~

20 PLACES

---,~O.45'tO,O'.
--,
'------'O.018t: 0.003)
20 PLACES

PINSPACING2.5410.100)T.P.

IS.. Not•• '

ALL D)MENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

24·PIN NT PLASTIC
1 + - - - - - - - 3 1 , 8 (1.250) MAX

~,:;::=::=ivvvvVVVVVVI

ftEtft

7,62±O,25
(0,300 t 0.010)
7,1 (0.280) MAX

-,

--*. --r..
JL

000000000®®®

0,36 (0,015)
2,0 (0.080) NOM

MIN

0,25 (0.010) NOM

0,28 • 0,08
~, (0,011 ± 0.003)
24 PLACES

-------t

.

.....! 1+-~24PLACES
. I I 0,83 (0.033)

rl ill~

'.M"~J

T J~---:::"''''''''JM''
L H-,

3,17 (0.125) MIN

f

24 PLACES

-.j I-- 0,457 ± 0,076

-

(0.018 ± 0.003)
24 PLACES

2,16 (0.085) MAX
4 PLACES

PIN SPACING 2,54 (0.100) T.P.
(See Note 0)

ALL DIMENSIONS ARE IN MI LLiMETERS AND PARENTHETICALLY IN INCHES.
NOTES:

a. Each pin centarllne is loc8tad within 0,25 (0.010) of its true longitudinal position.
b, This dimension does not apply for solder·dipped leads.
c. When solder·dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane,

5-8

TEXAS)NSTRUMENTS
INCORPORATED
POST OFFICE BOX 225012 • OALLAS. TEXAS 75265

Ie Sockets

6-1

ICSOCKETS
Texas Instruments lines of off·the·shelf interconnection products are designed specifically to meet the performance needs of
volume commercial applications. They provide both the economy of a standard product line and performance features
developed after many year's experience with custom designs. Foremost among these is our abilitY to selectively bond a
wrought gold stripe at the contact point. No waste. Reduced cost. Reliable contacts.
Wrought Gold Contact
Plate a contact with gold and you get a better contact. More reliable, longer lasting. Increase the gold, you improve the
contact. But gold is precious, so improved performance has to be costly - right? Wrong. Because now you can get the gold
only where it is needed - at the point of contact.
How? With selective metallurgical bonding; a gold stripe inlay. Not porous plating, but durable wrought gold bonded to the
contact by the same technology used to produce clad coins and thermostat metals.
Texas Instruments, Attleboro, Massachusetts, is the world's largest producer of these multimetal systems. We also know our
way around electronics. The result? A full line of reliable, low cost, interconnection systems featuring an extra measure of
gold where it's needed. Premium performance at no premium in price.
IC Sockets
Texas Instruments family of IC sockets includes every tYpe and size in common use today, and as wide a choice of contact
materials as you'll find anywhere. Choose from open or closed entry wire·wrapped t sockets, standard or low profile solder
tail sockets, cable plugs, and component platforms. Sizes from 8 to 40 pins.

Additional information including pricing and delivery quotations may be obtained from your nearest TI Distributor, TI
Representative, or:

II

Texas Instruments Incorporated
Connector'Systems Department
MS 14·3
Attleboro, Massachusetts 02703
Telephone: (617) 699·3800
TELEX: ABORA927708
tReglstered trademark of Gardner·Denv'"

6·2

LOW PROFILE SOCKETS
SOLDER TAIL
C-93 SERIES GOLD-CLAD CONTACTS

•
•
•
•

Universal mounting and packaging
Anti-wicking wafer
Stand-off tabs on base for solder flush
Redundant contact points for low contact resistance,
high reliability and repetitive insertion

•

Closed entry construction

MATERIAL:
A. Body-glass filled nylon (GFN)
B. Contact-copper nickel alloy
C. Finish-see part number schedule

IDENTIFICATION NOTCH

cD':';Nn
TOLERANCE ~
NON-CUMULATIVE

~_100
TYP.

PART NUMBER
SCHEDULE

NOTES:
A. Sockets meet requirements of Texas Instruments
test specification TS-0005 and test report
TR-0003
0
B. Operating temperature _65 C to ± 1500 C
C. Contacts have redundant spring elements
D. Accommodates standard.IC leads up to .024"
square, rectangular, or .024" diameter
E. Contact is designed and oriented in the plastic
body to generate maximum possible contact
pressure
F. Socket is designed to achieve maximum density
on boards
G. Sockets may be mounted end to end on .100"
centers continuous line or on .400" centers
row to row
H. Socket is designed to prevent IC leads from
contacting P.C. board
I. Closed entry feature provided to facilitate
automatic IC insertion and protects the IC
leads against damage

rl=W~

~~

.JOMAX

.150 MAX

.007

f-- X --l

..
BLACK BODY
Pins
8

C9308-02

14

C9314-02

16

C9316-02

18

C9318-02

20

C9320-02

22

C9322-02

24

C9324-02

28

C9328-02

40

C9340-02

CONTACT FINISH
50 microinch minimum gold strip
inlay

:m

IC LEAD GUARD

8 Pin

14 Pin

16 Pin

18 Pin

20 Pin

22 Pin

24 Pin

28 Pin

Dimension X ±.005

.300

.300

.300

.300

.300

.400

.600

.600

40 Pin
.600

Dimension V ±.OlO

.400

.700

.800

.900

1.000

1.100

1.200

1.400

2.000

Dimension W (max)

.400

.400

.400

.400

.400

.500

.700

.700

.700

6-3

STANDARD PROFILE SOCKET
SOLDER TAIL
C-82 SERIES PLATED CONTACTS •

C·92 SERIES GOLD CLAD CONTACTS

WIRE WRAP
C-81 SERIES PLATED CONTACTS •

C·91 SERIES GOLD CLAD CONTACTS

•
•
•
•

Designed for low cost, reliable, high density production packaging
Universal mounting and packaging capabilities
8 to 40 pin lead configurations
Contacts accommodate .015" through .024" rectangular or round
du.l·in·line leads
• Wire wrap posts held to true position of .015" providing a true
position of .020" on boards for efficient automatic wire wrapping

WIREWRAP

SOLDER TAIL

IDENTIFICATION
FOR PIN ND.

'.=-7

[E1t;[ !
'I

. 1§1'1m-1§1 D-§·A
TCll·_·[1(JOI·NON·CUMUlATIVE ITYP I

I

- -,- _I- -

1~®®.8

'T"
w

--i- --1.'00
-1-" . _
I.

Y

SOlDER
STANDOFFS

T I ~-I III
II"LV
El
a [ J.-x wI ®
@J.
,
1§J.1§1-1§1- ._.=--1II. - IlQ]-C

1§1.1§1-1§1 I§J.I§J-I§J-

Ol

0

,

r-1§J.1§1.1§J

II

11'11

I'

I

II

NON.cL~~ri~t-

'TYP

11'11

-=rf

COVER: TYPICAL LOCKING

..

rm

F~~~ l:'~=Tj::f1
rn
_~ti
N.. f--=
~I-'" .~

MATERIAL:
A. Body-glass filled
nylon (GFN)
B. Contact·phosphor
bronze per 00·B·750
(C-811 copper nickel
alloy (C·91)
C. Finish-see part
number schedule

Dimension V ±0.10
Dimension W (max)
Dimension X ±.005
Dimension Y iO.10
Dimension Z i.005

6-4

1- -l

IDENTIFICATION
FOR PIN ND '~_

NOTES:
A. Sockets meet requirements of Texas
Instruments test specification TS·OOO3
and test report TR-0001
B. Contacts are replaceable
C. Contacts have redundant spring elements
D. Cover is removeable
E. Contact is designed and oriented in the
plastic body to generate maximum
possible contact pressure
F. Operating temperature -65°C to +150°C

BPin
.465
.400
.300
NA
.280.

14Pin
.765
.400
.300
.400
.280

16 Pin
.865
.400
.300
.400
.280

I-x-I

G. Sockets are designed to achieve maximum
density on boards and may be mounted
.400" row to row centers
H. Closed entry cover is provided to facilitate
automatic insertion and protect IC leads
against damage
I. Accommodates standard Ie leads up to
.024" square, rectangular or .024" dia.
J. Contact retention - 7 Ibs. min.
K. Sockets are capable of being automati·
cally or semiautomatically wire wrapped

18 Pin

20 Pin

24 Pin

2BPin

36 Pin

.965
.400
.300
.400
.280

1.065
.400
.300
.400
.280

1.280
.700
.600
.500
.280

1.480
.700
.600
.500
.280

1.845
.700
.600
.800
.325

40 Pin
2.045
.700
.600
1.000
.325

WIRE WRAP

SOLDER TAIL
OPEN ENTRY

PART

II

NUMBER
SCHEDULE

Contact
Finish
Series

C-81
200-400
microinch
min tin
per
MIL·T·l0727

Series

C-91
50 microinch
min
gold stripe
inlay

Pins

Black
Body

CLOSED ENTRY

•

OPEN ENTRY
PART
NUMBER
SCHEDULE

Black

Contact

Cover

Finish

8

C810854

C810804

14

C811454

C811404

16

C811654

C811604

18

C811854

C811804

20

C812054

C812004

24

C812454

C812404

28

C812854

C812804

36

C813604

40

C814004

8

C910850

C910800

14

C911450

C911400

16

C911650

C911600

18

C911850

C911800

20

C912050

C912000

24

C912450

C912400

28

C912850

C912800

CLOSED ENTRY

Series

C-82
30 microinch
min gold per
MIL·G-45204
over
50 microinch _
min nickel per
QQ·N·290

Pins

'" "
Black

Black

Body

Cover

C820850

C820800

14

C821450

C821400

16

C821650

C821600

18

C821850

C821800

24

C822450

C822400

28

C822850

8

40
Series

C-82
50 microinch
min gold per
MI L·G-45204
over
100 microinch
min nickel per
QQ·N·290

C824000

8

C820852

C820802

14

C821452

C821402

16

C821652

C821602

18

C821852

C821802

24

C822452

C822402

28

C822852

C822802
C823602

36
40

36

C913600

Series

40

C914000

C-82
200-400
microinch
min tin per
MIL·T·l0727

C824002

8

C820854

C820804

14

C821454

C821404

16

C821654

C821604

18

C821854

C821804

24

C822454

C822404

28

C822854

C822804
C823604

36

C824004

40
Series

C-92
1OO·microi nch
min
gold stripe
inlay

C822800
C823600

36

8

C920850

C920800

14

C921450

C921400

16

C921650

C921600
C921800

18

C921850

24

C922450

C922400

28

C922850

C922800

36

C923600

40

C924000

III

6-5

SINGLE BEAM SOCKETS
LOW PROFILE/HIGH RETENTION
CB7 SERIES BERYLLIUM COPPER CONTACTS
The C87 socket utilizes a beryllium copper ~ontact spring

. CBB SERIES PHOSPHOR BRONZE CONTACTS

with a 200JJ inch minimum tin alloy finish in the contact
area. This contact system has been recognized as the standard
high performance combination. The system maintains the
highest withdrawal and normal forces, along with the ability
to retain these properties after cycling.

The C88 socket utilizes a specially processed high-strength
copper alloy spring with a 200", inch minimum tin alloy finish in the contact area. This uniquely engineered contact
system has been designed to achieve the performance characteristics that normally require a beryllium copper spring.
The device, available at a significantly lower cost than the
beryllium copper version, offers the advantage of a substantial cost reduction without sacrificing critical performance
requirements.

PART NUMBER SCHEDULE

PIN NO.1 IDENTIFICATION

COLORWH'ff

~~1J
II
MATERIAL:
A. Body - Glass reinforced polyester
UL rating 94V-0.
·B. Contacts - C87 Series, beryllium
copper - C88 Series, phosphor
bronze.
C. Contact finish - tin plate: 200j,t
micro inch min. thick in contact
area.

14 Pin
16 Pin
8 Pin
(7,62)
(7,62)
(7,62)
Dimension A
.300
.300
.300
(17,78)
(20,32)
Dimension B (10,16)
.700
.800
.400
(9,40)
(9,40)
Dimension C
(9,401
.370
.370
.370
·Also available: C98-Gold Inlay, C89-Copper

6-6

NOTES:
A. Operating temperature: _40°C to +105°C
B. Contact rating: 1 amp
C. Contact capacitance: 2 picofarads max.
D. Contact resistance: 20 milliohms max.
E. Dielectric withstanding voltage: 1000 V.A.C. min.
F. Insulation resistance: 100,000 megohms min.
G. Insertion force - 16 position "blunt IC" (.010
lead): .5#/lead nominal
H. Withdrawal force (.008 test blade)
C87 Series
Initial: 155 gm nominal
After probing with a .014 blade: 98 gm nominal
After probing with a .025 blade: 87 gm nominal
C88 Series
Initial: 112 gm nominal
After probing 2 times with .014 blade: 82 gm
nominal
After probing 2 times with .025 blade: 29 gm
nominal
I. Normal force (.010 deflection): 250 gm min.
J. Polarization identification: a white circle at the #1
position.
K. Full test reports, #TR S01015 for CS7 Series and
#TR 810112 for C88 Series, are available from
y·our local sales office.

18 Pin
(7,62)
.300
122,86)
.900
(9,40)
.370
Alloy

20 Pin
(7,62)
.300
(25,40)
1.000
(9,40)
.370

22 Pin
(10,16)
.400
(27,90)
1.100
(11,941
.470

24 Pin
(15,24)
.600
(30,48)
1.200
(17,02)
.670

28 Pin
(15,24)
.600
(35,36)
1.400
(17,02)
.670

40 Pin
(15,24)
.600
(50,80)

2.000
(17,02)
.670

tllII
Pins C87 SERIES C88SERIES'
S

C8708·01

CS808·01

14

CS714·01

C8814-01

16

C8716-01

C8816-01

18

CS718-01

C8818·01

20

C8720·01

C8820-01

22

C8722-01

C8822-01

24

C8724-01

C8824-01

28

C8728·01

C8828·01

40

C8740-01

C8840·01

SCREW MACHINE SOCKETS
LOW PROFILE
CJ1 SERIES WIRE WRAP. C72 SERIES SOLDER TAIL

• Gold contacts with gold sleeve or tin sleeve

PART NUMBER SCHEDULE

rA-l
T
t
COO
~
~
0000000000

o

0000000000

~~~~

8
14
16
18
20

B. Contact - Beryllium copper QQ-C-530, finish gold over nickel per mil·G-45204

22
24

C. Sleeve - Brass QQ-B-626, finish - gold over nickel
per mil·G-45204 or tin over nickel per mil-T-l0721

28
40

C7140-03

C724()'09

C7206-59*
C7208-59
C7214-59
C7216-59
C7218-59
C722()'59

28

C7106-53·
C7108·53
C7114-53
C7116·53
C7118·53
C7120·53
C7122-53
C7124·53
C7128·53

40
64

C7140·53
C7164-53*

C724().59

MATERIAL:

A. Body - Thermoplastic, meeting UL specification
94-V-O

A. Open body construction and high standoffs provide improved cleaning and heat dissipation

6
8
14
16
18
20

B. Accept standard I.C. leads .010± .003 x .018±
.003 or .010 to .022 dia.
C. Accept I.C. lead lengths from ,090 to .155

T U.120
T

Dimension
Dimension
Dimension
Dimension

'0

OIA.---.,.jU

C72SERIES

A max.
B :t.005
C max.
D :t.OOS

6 Pin
.300 .400
.200 .300
.400 .400
.300 .300

T

D. Operating temperatures:
Gold sleeve _65° C to 125° C
Tin sleeve -40°C to 100°C

22
24

E. Performance - meets req. of T.I. test spec. T.S.

0008 as shown in test report T.R. 1021.

11--0.012.3.
...

.700
.600
.400
.300

.800
.700
.400
.300

.900 1.000
.800
.900 1.000 1.100
.400 .400 .500 .700
.300 .300 .400 .600

C7222-09
C7224-09
C7228-09

..

64

NOTES:

--I--...-----......,.....,~
1
.170 IH L
.053----""H

C7208-09
C7214-09
C7216-09
C7218-09
C722()'09

C7114-03
C7116-03
C7118·03
C7120-03
C7122-03
C7124-03
C7128-03

C7222-59
C7224-59
C7228·59
'C7264-59*

Note: Contacts for one- and twolevel wire wrapping are also available. Contact the factory for details .
3.100
.600

.600

.600

1.000
.900

·Minimum order requirements on
these parts. Alternate insulator
materials may be used.

6-7

SPECIAL saCKETS
SLIM PACKAGE
C8424-03 • C9324-03

.300 row to row spacing on the low profile edgegrip

42PosmON

QUAD PACKAGE

C4742-11

C4W64-11 SERIES 64 STAGGERED PINS

mm

-·;l

--

17.78

(.700)

-- J

MATERIAL:
A. Body: 94V-O
glass filled
polyester
B. Contact: Copper alloy
C. Finish: Tin
plating: 120"
min.

~~~l
25.2

~E:~~~~mr

NOTES:
A. Operating temperature:
_40°C to
+100°C

[L
O m-=··l
0J
iiI=:

17.78

(.700)

:.= ...

111111=::=

15~]

3.81

I I

I

I~j
I !.-(.7oo)-.I 1-'

~22.86--l ('~'108)

530

1.9(0)

~~~~....J ~(.208)

II

MIN.

SHRINK PACKAGE
C4S SERIES 28 AND 40 POSITIONS

~__ ll~ __E]
I-

~~

1. 778
--l 14- (.070)

8

-I

~J

MATERIALS:
A. Body: 94V-O glass filled polyester
B. Contacts: Copper alloy
C. Finish: Tin plating 125" min.

WDJ

NOTES:
A. Operating temperature: _40°C to +100°C
4.5
(.177)

4.5
(.177)

~~
LA-J

~=i

~A----..If

3.0

3.0
(.118)

(.118)

MIN.

MIN.

6-8

NOTES:
Operating Temperature: _40°C
to +200°C
6.5
(.256)

(.600)

l

MATERIAL:
A. Body: Ryton
R-8
B. Contact: Copper alloy
C. Finish: Tin
plating 200"
min.

Part No.

Pos.

C4S28-02

28

C4540-02

40

A

B

C

13.0
10.16
25.0
(.400) (.984) (.512)
15.24
35.7
18.0
(.600) (1.406) (.709)

8

I'

~O

--.l

I+-:.d/~

"I

O~

..

TEXAS
INSTRUMENTS

SCLDOC



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:07:25 18:08:15-08:00
Modify Date                     : 2017:07:25 18:34:57-07:00
Metadata Date                   : 2017:07:25 18:34:57-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:73d44857-2a7e-6342-931f-4fb73293f12b
Instance ID                     : uuid:b7ca2c08-6a52-f442-b9c7-ad93c863c7c0
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 291