1985_U71_Hitachi_8 Bit_Single Chip_Microcomputer_Data_Book 1985 U71 Hitachi 8 Bit Single Chip Microcomputer Data Book

User Manual: 1985_U71_Hitachi_8-Bit_Single-Chip_Microcomputer_Data_Book

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8-BIT SINGLE-CHIP
MICROCOMPUTER DATABOOK

.HITACHI

When using this manual, the reader should keep the following in mind:
1. This manual may, wholly or partially, be subject to change without notice.
2. All pjghts reserved: No one is permitted to reproduce or duplicate, in any
form, the whole or part of this manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4. This manual neither ensures the enforcement of any industrial properties
or other rights, nor sanctions the enforcement right thereof.

INDEX
• GENERAL INFORMATION

•
•
•
•
•

Quick Reference Guide .... . . . . . . . . . . . . . . . . • . • . . . . . . . . . . . . • . . • • • • . . . . . . . . . . . . . . . . . • . . • . . .. 7
Introduction of Packages . . . . . . . . . . . . . . . . • . • . . • • . • • • • . . . . . . . . • . . . . . . . . . . . . . . • • . . . . . . • . . . . .. 17
Quality Assurance .•...•..•.••••.•.•••••••.•...••.•..••••••...•.•.•.••••.•••••••..•..•••....•.••..••••.••••. 25
Reliability Test Data. • • • • . • • . • . • . • . • . • • • • • • • • • • . • . • • . . . . • • • • •. . • . • . . • • . . • • • • • • • • . . • • • • • • • . . • • • • • • . • • • . . • • • • . 31
. Design Procedure and Support Tools for 8-bit Single-chip Microcomputers .•. : . . . . . . • • . . . . . . . . . . . . . . . . . •. 36

• DATA SHEETS

H06801S0
H06801SS
H0680lVO
HD680lVS
HD6803
HD6803·1 .
H0680SS1
H0680SS6
H0680SUl
H0680SVl
HD680ST2
H0680SWI
H06301Vl
HD63AOIVl
HD63BOIVI
HD6301XO
H063AOIXO
H063BOIXO
HD630IYO
HD63AOIYO
HD63BOIYO
HD6303R
H063A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
HD6303Y
HD63A03Y
HD63B03Y
HD6305UO
HD63A05UO
HD63B05UO
HD6305VO
HD63A05VO
HD63B05VO
HD630SXO
HD63A05XO
HD63BOSXO
HD6305Xl
HD63AOSXl
HD63B05Xl
HD6305X2
HD63A05X2
HD63B05X2

Microcomputer Unit (NMOS) . . . . . • . . . . . . . . • . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .•
Microcomputer Unit (NMOS) . . . . . . . . . . • . . . . . . . . . . . • . . . . . . . . • . . . . . . . . . . . . . . . . . . ..
Microcomputer Unit (NMOS) . . . . . . . . • . . . . . . . . . . . . . . • . . • . . • . . • . • . . . . . . . . . . . . . . . •.
Microcomputer Unit (NMOS) . . . • . • . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . • . . . . . . . . . . . . . ..
Micro Processing Unit (NMOS) ...•........•....•.•..•............................
Micro Processing·Unit (NMOS) ......••.•..•......•......••....•..........•.......
Microcomputer Unit (NMOS) ..•.......•..........••........•....•..•............
Microcomputer Unit (NMOS) .......•....................•......•....•..........•
Microcomputer Unit (NMOS) .......•.......................•..•....•....•.....•.
Microcomputer Unit (NMOS) .........•....•...•..•....••.....•................. ,
Microcomputer Unit (NMOS) ..•......•........•..•.................•............
Microcomputer Unit (NMOS) ........•............•.••.•.....•..•...•.•....•.....
Microcomputer Unit (CMOS) .........•....•...•..............••...........•.....
Microcomputer Unit (CMOS) ....•...•....••..........................•..........
Microcomputer Unit (CMOS) ..•....•.••.......•..•........•...........•..•......
Microcomputer Unit (CMOS) .......•........ : ..•.......•......•....•........•...
Microcomputer Unit (CMOS) •......•...........•.........•..•....•....•....•....
Microcomputer Unit (CMOS) ..•.....•.•...•.......•.........•....•......•.•.•...
Microcomputer Unit (CMOS) ..•.................................................
Microcomputer Unit (CMOS) ....•........••.••...•....•.•...........•...........
Microcomputer Unit (CMOS) ....•...•..•..•....................•...•••.....•.•..
Micro Processing Unit (CMOS) ..•....•..••......................•...•............
Micro Processing Unit (CMOS) ...•..•....................................••......
Micro Processing Unit (CMOS) ..•..................•......•.•.............•......
Micro ProceSSing Unit (CMOS) .......•..•..........•........•....................
Micro Processing Unit (CMOS) .............•..•..................................
Micro Processing Unit (CMOS) ...•..................•...•...............•........
Micro Processing Unit (CMOS) ..........................••...••.•.......••.......
Micro ProceSSing Unit (CMOS) ....•.•....•...•..••...•.......•••....•............
Micro Processing Unit (CMOS) •...•.........•.......•..••.................•.....•
Microcomputer Unit (CMOS) .........•...•..•..•........•.....•...........•.....
Microcomputer Unit (CMOS) ...•.•...•...•.•.•.•....•.•........................•
Microcomputer Unit (CMOS) •..................................•....•..•....•...
Microcomputer Unit (CMOS) .. . . . . . . . . . . . • . . . . . . . . . . • . . . . . . . . . . • . . . . • . . . . . . .. ..
Microcomputer Unit (CMOS) •...........••...•........•...•..••.................
Microcomputer Unit (CMOS) •.•.••.....•....•.••.......•....•.•...••.•..........
Microcomputer Unit (CMOS) ...........•..........................•..•.•........
Microcomputer Unit (CMOS) ......•..•....................•.•............•......
Microcomputer Unit (CMOS) ....................•.......•.•.....................
Microcomputer Unit (CMOS) .•...........•......................................
Microcomputer Unit (CMOS) ...•.............•.....•..........•.....•.•..•......
Microcomputer Unit (CMOS) .....•...•.......•......•...........................
Microcomputer Unit (CMOS) .•.....•.......•....•.....••••....••....••.........•
Microcomputer Unit (CMOS) ..•.•••..........•.........•....•...•..•........•...
Microcomputer Unit (CMOS) •..........•.•.•.•.•...•...•.•....•...•.............

_HITACHI

41
41
75
75
109
109
136
156
176
197
218
219
247
247
247
284
284
284
321
321
321
323
323
323
353
353
353
388
388
388
391
391
391
393
393
393
395
395
395
422
422
422
422
422
422

HD630SYO
HD63AOSYO
HD63BOSYO
HD630SYI
HD63AOSYI
HD63BOSYI
HD630SY2
HD63AOSY2
HD63BOSY2
HD63LOSFI
HD63LOSEO
HD68POIV07
HD68P01V07-1
HD68POIMO
HD68POIMO-1
HD68POSV07
HD68POSWO
HD63POIMI
HD63PAOIMI
HD63PBOIMI
HD63POSYO
HD63PAOSYO
HD63PBOSYO
HD63701XO
•

Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . . . . . . . . . . 451
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . 451
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Evaluation Chip for HD63LOSFI (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 540
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,' . . . . . . . . . . . . . . . . . . . . . 579
Microcomputer Unit (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Microcomputer Unit (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

INTRODUCTION OF RELATED DEVICES
• 8/16-buMulti-chip Microcomputers, • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• 4-bit Single-chip Microcomputer HMCS400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . '.' . . . . . . . . . . . . . . . . . . . . .
• 4-bit Single-chip Microcomputer HMCS40 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LCD Driver Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• IC Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• Gate Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• LSI for Speech Synthesizer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• CODEC/Filter Combo LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

•

675
677
678
680
682
685
687
690

HITACHI SALES OFFICE LOCATIONS ..•..............•..•...........•......••..•...••...............•. 692

_HITACHI

GENERAL
INFORMATION
•
•
•
•
•

Quick Reference Guide
Introduction of Packages
Quality Assurance
Reliability Test Data
Design Procedure and Support Tools
for 8-bit Single-chip Microcomputers

QUICK REFERENCE GUIDE
• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6801 SERIES
HD6801S0
HD6801S5

HD6801VO
HD6801V5

Bus Timing (MHz)

1.0/1.25

1.0/1.25

Supply Voltage (V)

5.0

5.0

5.0

0-+70

0-+70

0-+70

DP·40

DP·40

DP·40

2

4

-

128

128

128

Type No.

LSI
Characteristics

Operating Temperature * (C)
Package t
Memory

ROM (k byte)
RAM (byte)

I/O Port

Interrupt
Functions

HD6803
HD6803-1
1.0/1.25

29

29

13

External

2

2

2

Soft

1

1

1

Timer

3

3

3

1

1

Serial

• Free running counter
• Output compare register
• Input capture register

Timer
SCI

1
16·bit xl
16·bit xl
16·bit xl

Full double step·stop type
• Address/data non· multiple mode
(256 bytes)
• Address/data multiple mode
(65k bytesf

External Memory Expansion
Clock Pulse Generator

• Address/data
multiple mode
(65k bytes)

Built·in (External clock useable)

Built·in RAM Holding

Yes (64 bytes)

EPROM on the Package Type"

HD68P01V07
HD68P01V07·1

Compatibility

MC6801
MC6801-1

HD68P(J1V07
HD68P01V07·1

-

MC6803
MC6803·1

• Wide Temperature Range 1-40 - +BSoC) version is available .
•• H D6BPO 1 MO u..abla.
t DP; Plastic DIP

•

HITACHI

7

QUICK REFERENCE G U I D E - - . . . , - - - - - - - - - - - - - - - - - - - - - - - - - - -

• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6805 SERIES
HD6805S1

HD6805S6*

1.0

1.0

1.0

5.25

5.25

5.25

0-+70

0-+70

0-+70

DP·28

DP·28

DP·40

ROM (k byte)

1.1

1.8

2

RAM (byte)

64

64

96

Type No.
Clock Frequency (MHz)
LSI
Characteristics

Supply Voltage (V)
Operating Temperature *** ( °C)
Package t
Memory

I/O Port
I/O Port

-

20

Functions

-

20

-

Output Port

Interrupt

20

20

Input Port

HD6805Ul

24
32

8

-

Nesting

6

6

6

External

1

1

1

Soft

1

1

1

Timer

1

1

1

Serial

-

-

-

• 8-bit timer with 7·bit prescaler
• Event counter

Timer

-

SCI

Low·voltage Automatic Reset (LVI)
External Memory Expansion

-

• Resistor
• Crystal

Clock Pulse Generator

Self-check Mode

-

Yes

Yes

Yes

Available

Available

Available

-

-

-

-

-

HD68P05V07

MC6805P2

MC6805P6

-

Other Features

EPROM on the Package Type
Compati bi Iity
* Preliminary

** Under development

*** Wide Temperature Range (-40""'" +8SoC) verSion is available.
t DP; Plastic DIP

8

~HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE

HD6805Vl

HD6805T2**

HD6805Wl*

1.0

1.0

1.0

5.25

5.25

5.25

0-+70

0-+70

0-+70

DP·40

DP·28

DP·40

4

2.5

4

96

64

96

24
32

8

19

-

19

23

6

29

-

-

-

6

6

12

1

1

2

1

1

1

1

1

4

-

-

• 8·bit timer
with 7-bit
prescaler
• Event counter
·8-bit
comperator

-

-

-

• Crystal
Yes

Yes

Yes

Available

Available

Available

-

PLL logic
for RF
synthesizer

HD68P05V07

-

-

MC6805T2

• 8-bit x
4-channel
internal
AID converter
• 8 bytes of
standby RAM
HD68P05WO'

-

_HITACHI

9

QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER HD6301 SERIES
HD6301Vl

Type No.

HD63A01Vl
HD63B01Vl
1.0 (HD6301Vl)

Bus Timing (MHz)
LSI
Characteristics

1.5 (HD63A01Vl)
2.0 (HD63B01Vl)

Supply Voltage (V)

5.0

Operating Temperature-tC)
Package t
Memory

DP-40, FP-54, CG·40

ROM (k byte)

4

128

192

-

29

53

8
21

External

2

Soft

2

2

Timer

3

4

Serial

3

1
1
16·bit xl
16-bitx 1
( Free running counter X l ) ( Free running counter Xl)
Output compare register x 1
Output compare register x2
Input capture register xl
Input capture register xl
8-bit xl
(8.bit up counter X l )
Time constant register x 1
Asynchronous/Synchronous
Asynchronous

Timer

SCI

65k bytes

65k bytes

- Error detection
-Low power consumption
modes (sleep and standby)

-Error detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt

External Memory Expansion
Other Features

HD63P01Ml
HD63PA01Ml *
HD63PB01Ml'

EPROM on the Package Type

* Preliminary
** Under development * .. '" Wide Temperature Range (-40 -- +85°C) version is available.
t DP; Plastic D!I!, FP; Plastic Flat Package, CG; Glass-sealed Ceramic Leadless Chip Carrier

10

24

29

Input Port
Output Port

Functions

DP-64S, FP·80

4

I/O Port

Interrupt

5.0
0-+70

0-+70

RAM (byte)
I/O Port

HD6301XO
HD63A01XO
HD63B01XO
1.0 (HD6301XO)
1.5 (HD63A01XO)
2.0 (HD63B01XO)

•

HITACHI

HD63701 XO'*
(EPROM on-chip)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE

HD6301Y0"
HD63A01YO"
HD63B01YO"

HD6303R
HD63A03R
HD63B03R

HD6303X
HD63A03X
HD63B03X

HD6303Y"
HD63A03Y"
HD63B03Y"

1.0 (HD6301YO)
1.5 (HD63A01YO)
2.0 (HD63B01YO)

1.0 (HD6303R)
1.5 (HD63A03R)
2.0 (HD63B03R)

1.0 (HD6303X)
1.5 (HD63A03X)
2.0 (HD63B03X)

1.0 (HD6303Y)
1.5 (HD63A03Y)
2.0 (H D63B03Y)

5.0

5.0

5.0

0-+70

0-+70

0-+70

0-+70

DP·64S, FP·64

DP·40, FP·54, CG·40

DP·64S, FP·ao

DP·64S, FP·64

5.0

16

-

-

-

256

12a

192

256

4a
53

-

,

16

13

-

13

24

a

-

5

24

24

r---'---

-

-

-

3

2

3

3

2

2

2

2

4

3

4

4

1

1

1

1

---.

16·bit xl
16·bit xl
16·bit x 1
16·bit xl
(Free running counter xl
) (Free running counter Xl) (Free running counter xl
) (Free running counter X l )
Output compare register x 2
Output compare register x 2
Output compare register x 1
Output compare register x 2
I nput capture register x 1
Input capture register x 1
Input capture register x 1
Input capture register x 1
a·bit xl
a·bit xl
a·bit xl
( a·bit up counter X l )
( a·bit up counter X l ) (a.bit up counter X l )
Time constant register x 1
Time constant register x 1
Time constant register x 1
Asynchronous/Synchronous

Asynchronous

Asynchronous/Synchronous

65k bytes

65k bytes

65k.bytes

65k bytes

-Error detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt

-Error detection
-Low power consumption
modes (sleep and standby)

-Error detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt

-Error detection
-Low power consumption
modes (sleep and standby)
-Slow memory interface
-Halt

•

HITACHI

Asynchronous/Synchronous

11

QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• CMOS 8·BIT SINGLE·CHIP MICROCOMPUTER HD6305 SERIES

Type No.

Clock Frequency (MHz)
LSI
Characteristics

HD6305UO"
HD63A05UO"
HD63B05UO"

HD6305VO"
HD63A05VO"
HD63B05VO"

HD6305XO'
HD63A05)c0'
HD63B05XO'

1.0 (HD6305UO)
1.5 (HD63A05UO)
2.0 (HD63B05UO)

1.0 (HD6305VO)
1.5 (HD63A05VO)
2.0 (HD63B05VO)

1.0 (HD6305XO)
1.5 (HD63A05XO)
2.0 (HD63B05XO)

Supply Voltage (V)
Operating Temperature ••• tC)
Package t
Memory

5.0

5.0

5.0

0-+70

0-+70

0-+70

DP·40

DP·64S, FP-64

DP-40
ROM (k byte)
RAM (byte)

2

4

4

12B

192

128

I/O Port
I/O Port

J

Input Port

31

Output Port

31

31

-

-

31

32
55

7
16

-

External

2

2

Soft

1

1

1

Timer

2

2

2

Serial

1

1

1

-

-

-

EPROM on the Package Type

-

-

Evaluation Chip

-

-

Interrupt

2

Functions
Timer
SCI
External Memory Expansion

Other Features

* Preliminary ** Under development *** Wide Temperature Range (-46 - +85 Q C) version is available.
t DP; Plastic DIP, FP; Plastic Flat Package

12

•

HITACHI

HD63P05YO"
H D63PA05YO"
HD63PB05YO"

-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE

HD6305Xl
HD63A05Xl
HD63B05Xl

HD6305X2
HD63A05X2
HD63B05X2

HD6305YO'
HD63A05YO'
HD63B05YO*

HD6305Yl*
HD63A05Yl*
HD63B05Yl'

HD6305Y2*
HD63A05Y2*
HD63B05Y2*

1.0 (HD6305Xl)
1.5 (HD63A05X1 )
2'.0 (H D63B05X 1)

1.0 (HD6305X2)
1.5 (HD63A05X2)
2.0 (HD63B05X2)

1.0 (HD6305YO)
1.5 (HD63A05YO)
2.0 (HD63B05YO)

1.0 (HD6305Yl)
1.5 (HD63A05Y1)
2.0 (HD63B05Y1)

1.0 (HD6305Y2)
1.5 (HD63A05Y2)
2.0 (HD63B05Y2)

HD63L05Fl

0.1

5.0

5.0

5.0

5.0

5.0

3.0

0-+70

0-+70

0-+70

0-+70

0-+70

-20 - +75

DP·64S, Fp·64

Dp·64S, FP·64

DP·64S, Fp·64

DP·64S, Fp·64

DP·64S, Fp·64

DP·64S, Fp·80

4

-

8

8

-

4

128

128

256

256

256

96

24

24
31

7

31

7

-

32
7

55

-

24
7

31

24
7

31

-

16

20

-

20

-

(19)

2

2

2

2

2

1

1

1

1

1

1

2

2

2

2

2

1

1

1

1

1

1

• 8·bit )( 1 (with 7 ·bit prescaler)
• 15·bit)( 1 (combined with SCI)

-

-

-

-

.8·bit )( 1 (with
7·bit prescaler)

Synchronous
16k bytes
12k bytes
• Low power consumption modes
(Wait, stop and standby)

1

-

8 k bytes

16k bytes

• a·bit AID converter
• LCD driver
(6 )( 7 segment)
• Low power con·
sumption modes
(Standby and halt)

HD63P05YO"
HD63PA05YO"
HD63PB05YO'*

-

-

•

HITACHI

-

HD63L05EO

13

QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• NMOS 8-BIT SINGLE-CHIP MICROCOMPUTER EPROM ON PACKAGE TYPE
Type No.
LSI
Characteristics

HD68P01V07 IHD68P01V07-1 'I HD68P01MO

1Supply Voltage

IOperating Temperature*

'It

H D68P01 MO-1'

HD68P05V07

HD68P05WO'

(V)

5.0

5.0

5.0

(oC)

0-+70

0-+70

0-+70

1Package t
Equivalent Device

Mountable EPROM

DC-40P
HD6801V0

HD6801V5

HN482732A-30

HN482732A-30

HN482764-3

HN482764-3

DC-40P

DC-40P

HD6805U1
HD6805V1

HD6805W1

HN482732A-30

-

H N482732A-30
HN482764-3"

* Preliminary
** Wide Temperature Range (-40""'- +8SoC) version is available.
t DC; Ceramic DIP (EPROM on the package type)

• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER EPROM ON PACKAGE TYPE
Type No,

HD63P01M1

(V)
Supply Voltage
LSI
Characteristics Operating Temperature * * * (0 C)

Mountable EPROM

..
**
***
t

14

HD6301Vl

0-+70

0-+70

DC-40P

DP-64SP

HD63A01Vl

HD63B01V1

HD6305XO
HD6305YO

HD63A05XO
HD63A05YO

HN482732A·30

HN482732A·25

HN482764-3

HN482764·3

HN482764

HN482732A·30
HN482164·3

HN482732A·30
HN482764·J

HN27C64·30

HN27C64·30

HN27C64·25

HN27C64·30

HN27C64·30

HN482732A·30

HD63PB05YO'*

5.0

5.0

Package t
Equivalent Device

1HD63PA01M1 'IHD63PB01Ml* HD63P05YO*' HD63PA05YO"

Prel irninary
Under Development
Wide Temperature Range (-40""" +85°C) version is available.
DC; Ceramic DIP (EPROM on the package type)

~HITACHI

HD63B05XO
HD63B05YO
HN482732A·25
HN482764

HN27C64·25

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - QUICK REFERENCE GUIDE

• CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER EPROM ON-CHIP TYPE
HD63701XO'

Type No.

1.0

Bus Timing (MHz)
LSI
Characteristics

Supply Voltage

(V)

5.0

Operating Temperature (C)

0-+70

Package t

DC·64S
4 (EPROM)

ROM (k byte)
Memory
RAM (byte)

192
24

I/O Port
I/O Port

Input Port

53

B
21

Output Port

Functions

External

3

Soft

2

Timer

4

Serial

1

Interrupt

(

Timer

-

16·bit xl
Free running counter x 1
Output compare register x 2
Input capture register x 1
B·bit xl
( B·bit up counter
Time constant register x 1

)

Xl)

Asy nch ronous/Sy nch ronou s

SCI
External Memory Expansion

65k bytes
•
•
•
•

Other Features

Error detection
Low power consumption modes (sleep and standby)
Slow memory interface
Halt

Equ ivalent Device

HD6301XO

Reference Page

720

* U ndar development
t DC; Ceramic DIP (Shrink type)

•

HITACHI

15

INTRODUCTION OF PACKAGES
Hita~hi microcomputer devices are offered in a variety of
packages, to meet various user requirements.

1. Package Classification
When selecting suitable packaging, please refer to the
Package Classifications given in Fig. I for pin insertion, surface
mount, and multi-function types, in plastic and ceramic.

Standard Outline

Plastic DIP
Ceramic DIP

Pin Insertion Type
Shrink Outline

Shrink Type Plastic DIP
Shrink Type Ceramic DIP

Package Classification

SOP IPlastic)
FPP (Plastic)

Surface Mounting Type

PLCC (Plastic)
LCC
(Glass Sealed Caramic)

Multi·function Type

DIP; DUAL IN LINE PACKAGE
S·DIP; SHRINK DUAL IN LINE PACKAGE
PGA; PIN GRID ARRAY
FLAT·DIP; FLAT DUAL IN LINE PACKAGE
FLAT·QUIP; FLAT QUAD IN LINE PACKAGE
CC: CHIP CARRIER
SOP; SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC; PLASTIC LEADED CHIP CARRIER
LCC; LEADLESS CHIP CARRIER

Fig. 1

Package Classification according to Material and Printed Circuit Board Mounting Type

$

HITACHI

17

INTRODUCTION OF P A C K A G E S - - - - - - - - - - - - - - - - - - - - - - by code as follows, and illustrated in the data sheet for each
device.
When ordering, please write the package code next to the
type number.

2. Type No. and Package Coda Indication

The Hitachi Type No. for single-chip microcomputer devices
is followed by package material and outline specifications, as
shown below. The package type used for each device is identified
Type No. Indication

HDx X

X

xP

(Note) H DXX.fXXXX stands for Type No.
of EPROM on the package type

Package Classification
No Indication : Ceramic DIP
P ; Plastic DIP
F ; FPP
CG; LCC

microcomputer device.

Package Code Indication

DP-64S
D ;DIP
C ;CC

P
G

F ; FLAT

Additional Outline
S; Shrink type
P; EPROM on the package type

C

18

_HITACHI

------------------------------------------------INTRODUCTIONOFPACKAGES
3. Package Dimensional Outline

Hitachi single-chip microcomputer devices employ the packages shown in Table I according to PCB mounting method.

Table 1 Package List
Mounting method

Package classification
Standard outline (DIPI

Pin insertion type

Package material

Package code

Plastic

DP-28
DP-40

Plastic

DP-64S

Shrink outline (S-DIPI
Ceramic

Surface mounting type

Flat package (FPPI

Plastic

FP-54
FP-64
FP-80

Chip carrier (LCCI

Glass sealed ceramic

CG-40

Ceramic

DC-40P
OC-64SP

EPROM on the package type

Multi-function type

OC-64S

Plastic DIP
• DP-28
.....

28

I
I

14

15

(Unit: mm)

• DP-40

(Unit: mm)

•

HITACHI

19

INTRODUCTION OF PACKAGES

I Shrink Type Plastic DIP
• DP·64S

iF=1l
.J~Ji~-'~
(Unit:mm)

I Shrink Type Ceramic DIP
• DC-64S

I----

.11,1 _ _

(Unit:mm)

20

eHITACHI

- - - - - - - - - - - - - - - - - - · - - - - - - I N T R O D U C T I O N OF PACKAGES

Flat Package
•

FP-54

(Unit:mm)

•

FP-64

(Unit:mm)

• FP-80

(Unit: mm)

eHITACHI

21

INTRODUCTION OF PACKAGES - - - - - - - - - - - - - - - - - - - - - - -

I Lead'es. CII'p C.rri.r I
•

CG-40
12.19

•
"ii'!.'

CO.14

J

,;

~

9
(Unlt:mml

I

EPROM on-PICIIIge ",.

• DC·40P

I

I

Im

010-011

II!D

q'

..

-" -G1OnHn

1114

'(Unlt:mml

22

•

HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - INTRODUCTION OF PACKAGES
.DC-64SP

1--o

23

____ ......

e---

1--

I

1.--,," .,
(Unit:mm)

4. Mounting Method

Package lead pins are surface treated with solder coating or
plating to facilitate PCB mounting. The lead pins are connected
to the package by eutectic solder. Common connecting method
of leads and precautions are explained as follows:
4.1 Mounting Methods of Pin Insertion Type Package

Insert lead pins into the PCB through-holes (usually about
q,O.8mm). Soak leads in a wave solder tub.
Lead pins held by the through-holes enable handling of the
package through the sqldering process, and facilitate automated
soldering. When soldering leads in the wave solder tub, do not
get solder on the package.
4.2 Mounting Mathod of Surfaca Mount Type Package

Apply the specified quantity of solder paste to the pattern on
any printed board by the screen printing method, to temporarily
fix the package to the board. The solder paste melts when heated
in a reflowing furnace, and package leads and the pattern of the
printed board are fixed by the surface tension of the melted
solder and self alignment.
The size of the pattern where leads are attached should be 1.1
to 1.3 times the leads' width, depending on paste material or
furnace adjustment.
The temperature of the reflowing furnace is dependent on
packaging material and type. Fig. 2 lists the adjustment of the
reflowing furnace for FPP. Pre-heat the furnace to 150°C. Surface temperature of the resin should be kept at 235° C maximum
for \0 minutes or less.

Time----'

Fig.2 Reflowing Furnace Adjustment
for FPP
Employ adequate heating or temperature control equipment
to prevent damage to the plastic package epoxy-resin material.
When using an infrared heater, avoid long exposure at temperatures higher than the glass transition point of epoxy-resin (about
1500 C), which may cause package damage and loss of reliability
characteristics. Equalize the temperature inside and outside of
packages by reducing the heat of the upper surface of the
packages.
FPP leads may easily bend in shipment or during handling,
and impact soldering onto the printed board. Heat the bent leads
again with a soldering iron to reshape them.
Use a rosin flux when soldering. Do not use chloric flux
because the chlorine in the flux has a tendency to remain on the
leads and reduce reliability. Use alcohol, chlorothene or freon to
wash away rosin flux from packages. These solvents should not
remain on the packages for an excessive length oftime, because
the package markings may disappear.

@HITACHI

23

INTRODUCTION OF PACKAGES
6. Package Marking
The Hitachi trademark and product type No. are printed on
packages, as shown in the following examples. Customer
marking can be added to single-chip devices upon request.

(a)

(b)

.~@~
(C'B DB80[]]SOB
~ 0 0 D~B~lSl
(d)

24

(e)

•

HITACHI

Meaning of .ach mark

(a)

Hitachi Trademark

(b)

Lot Code

(e)

TYpe No.

(d)
(e)

,ROM Code
.Iapan Mark,

QUALITY ASSURANCE
1. VIEWS ON QUALITY AND RELIABILITY
Basic views on quality at Hitachi are to meet the
individual uers' required quality level and maintain a
general quality level equal to or above that of the
general market. The quality required by the user may
be specified by contract. or may be indefinite. In either
case, efforts are made to assure reliable performance
in actual operating circumstances. Quality control
during the manufacturing process, and quality awareness from design through production lead to product
quality and customer satisfaction. Our quality assurance technique consists basically of the following
steps:
(1) Build in reliability at the design stage of new
product development.
(2) Build in quality at all steps in the manufacturing
process.
(3) Execute stringent inspection and reliability confirmation of final products.
(4) Enhance quality levels through field data feed
back.
(5) Cooperate with research laboratories for higher
quality and reliability.
With the views and methods mentioned above,
utmost efforts are made to meet users' requirements.

design, device deSign, layout deSign, etc. Therefore, as long as standardized processing and
materials are used the reliability risk is extremely
small even in the case of new development
devices, with the exception of special requirements imposed by functional needs.
(2) Device DeSign
It is important for the device design to consider
total balance of process, structure, circuit, and
layout deSign, especially in the case where new
processes and/or new materials are employed.
Rigorous technical studies are conducted prior to
device development.
(3) Reliability Evaluation by Functional Test
Functional Testing is a useful method for design
and prcicess reliability evaluation of IC's and LSI
devices which have complicated functions.
The objectives of Functional Test are:
• Determining the fundamental failure mode.
• Analysis of relation between failure mode and
manufacturing process.
• Analysis of failure mechanism.
• Establishment of QC points in manufacturing
process.

2. RELIABILITY DESIGN OF
SEMICONDUCTOR DEVICES
2.1 Reliability Targets
The reliability target is an important factor in sales,
manufacturing, performance, and price. It is not adequate to set a reliability target based on a single set of
common test conditions. The reliability target is set
based on many factors:
(1) End use of semiconductor device.
(2) End use of equipment in which device is used.
(3) Device manufacturing process.
(4) End user manufacturing techniques.
(5) Quality control and screening test methods.
(6) Reliability target of system.
2.2 Reliability Design
The following steps are taken to meet the reliability
targets:
(1) Design Standardization
As for design rules, critical items pertaining to
quality and reliability are always studied at circuit

•

2.3 Design Review
Design Review is an organized method to confirm that
a design satisfies the performance required and
meets design specifications. In addition, design review
helps to insure quality and reliability of the finished
products. At Hitachi, design review is performed from
the planning stage to production for new products,
and also for design changes on existing products.
Items discussed and considered at design review are:
(1) Description of the products based on design
documents.
(2) From the standpoint of each participant, deSign
~ documents are studied, and for points needing
clarificatio~, further investigation will be carried
out.
\
(3) Specify quaiity control and test methods based on
design documents and drawings.
(4) Check process and ability of manufacturing lineto
achieve design goal.
(5) Preparation for production.
(6) Planning and execution of sub-programs for
design changes proposed by individual specialists,

HITACHI

25

QUALITY ASSURANCE - - - - - - - - - - - - - - - - - - - - - -

for test, experiments, and calculations to confirm
the design changes.
(7) Analysis of past failures with similar devices, discussion of methods to prevent them, and pia nning
and execution oftest programs to confirm success.

design, as described in section 2. Our views on quality
approval are:
(1) A third party executes approval objectively from

the standpoint of the customer.
(2) Full consideration is given to past failures and

3. QUALITY ASSURANCE SYSTEM

information from the field.
(3) No design change or process change without QA

3.1 Activity of Quality Assurance

approval.

General views of overall quality assurance in Hitachi
are as follows:
(1) Problems in each individual process should be
solved in ~he process. Therefore, at the finished
product stage the potential failure factors have
been removed.
(2) Feedback of information is used to insure a satisfactory level of ability process.

3.2 Quality Approval
To insure quality and reliability, quality approval is
carried out at the preproduction stage of device

(4) Parts, materials, and processes are closely

monitored.
(5) Control points are established in mass production

after studying the process abilities and variables.

3.3 Quality and Reliability Control at Mass
Production
Quality control is accomplished through division of
functions jn manufacturing, quality assurance, and
other related departments. The total function flow is
shown in Fig. 2. The main points are described below.

Contents

Step

Purpose

Design Review

I~__-I

Characteristics of Material and 1+____--1 Confirmation of
Parts
Characteristics and
Reliability of Materials
Appearance
L,;a:;;n;.;:d:...;P:...:a:;.rt.::s~_ _ _ _.....I
Dimension
Heat Resistance
Mechanical
Electrical
Others

rr:C~h~a~rac~t~er~is~t~ics~A~p~p~ro~v~a~1~--------fjE~I~ect~ri~ca~I::------I-------1 Confirmation of Target

u.;

Quality Approval (1

Characteristics
Function
Voltage
Current
Temperature
Others
Appe~rance, Dimension

Spec. Mainly about
Electrical Characteristics

Reliability Test
Life Test
Thermal Stress
Moisture Resistance
Mechan ical Stress
Others

Confirmation of Quality
and Reliability in Design

Reliability Test
Process Check same as
Quality Approval (1)

Confirmation of Quality
and Rl!liability in Mass
Production

Figure 1 Flow Chart of Quality Approval,

26

$

HITACHI

QUALITY ASSURANCE

Quality Control

Process

Products
I
I

Method

Inspection on Material and
Parts for Semiconductor
Devices

Lot Sampling,
Confirmation of
Quality Level

Manufacturing Equipment,
Environment, Sub-material,
Worker Control

Confirmation of
Quality Level

Inner Process
Quality Control

Lot Sampling,
Confirmation of
Quality Level

100% Inspection on
Appearance and Electrical
Characteristics

Testing,
Inspection

Sampling Inspection on
Appearance and Electrical
Characteristics

Lot Sampling

Reliability Test

Confirmation of
Quality Level, Lot
Sampling

I

I
I
Ia..

___ _

I'" - - - - - - - - - - - - - - - ,

Feedback of
Information

: Quality Information
I
I
Claim
:
Field Experience
:
I
General Quality
Information
L ______________
___ I
~

Figure 2 Flow Chart of auality Control in Manufacturing Process

•

HITACHI

27

QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - - -

3.3.1 Quality Control of Parts and Materials
As semiconductor devices tend towards higher performance and higher reliability. the importance of
quality control of parts and materials becomes paramount. Items such as crystals. lead frames. fine wire
for wire bonding. packages. and materials needed in
manufacturing processes such as masks and chemicals. are all subject to rigorous inspection and control.
Incoming inspection is performed based on the purchase specification and drawing. The sampling is executed based mainly on MIL-STD-l05D.
The other activities of quality assurance are as
follows:
(1) Olotside vendor technical information meeting.
(2) Approval and guidance of outside vendors.
(3) Chemical analysis and test.
The typical check points of parts and materials are
shown in Table 1 .
Tobie 1 Qualitv Control Chock Point. of Material.nd Parts

(Example'
Material,
Parts

Important
Control Items

Point for Check

Appearance

Damage and Contamination on Surface

Wafer

Mask

Fine
Wire for
Wire

Bonding

Dimension

Flatness

Sheet Resistance

Resistance

Defect Density
Crystal Axis

Defect Numbers

Appearance

Defect Numbers, Scratch

Dimension
Resistoration
Gradation

Dimension Level

Appearance

Contamination. Scratch,
Bend, Twist

(2) Quality Control of Manufacturing Facilities and
Measuring Equipment
Manufacturing equipment is improving as higher
performance devices are needed. At Hitachi. the
automation of manufacturing equipment is encouraged. Maintenance Systems maintain operation of high performance equipment. There are
daily inspections which are performed based on
related specifications. Inspection points are listed
in the specification and are checked one by one to
prevent any omission. As for adjustment and
maintenance of measuring equipment. specifications are checked one by one to maintain and
improve quality.

Dimension

Purity

Purity level

Elongation Ratio
Appearance
Dimension

Contamination, Scratch

Mechanical Strength

Dimension Level

Accuracy

Plating
Mounting
Characteristics

Ceramic
Package

Plastic

28

Bondabilitv. Solderability
Heat Resistance

Appearance
Dimension
Leak Resistance
Plating
MountiAg
Characteristics
Electrical
Characteristics
MeChanical
Strength

Contamination, Scratch
Dimension level
Airtightness
Bondability, Solderability
Heat Resistance

Composition

Characteristics of
Plastic Material

Electrical
Characteristics
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics

(1) Quality Control of Semi-final Products and Final
Products
Potential failure factors of semiconductor devices
are removed in the manufacturing process. To
achieve this. check points are set-up in each process and products which have potential failure
factors are not moved to the next process step.
Manufacturing lines are rigidly selected and tight
inner process quality controls are executed-rigid
checks in each process and each lot. 100% inspection to remove failure factors caused by manufacturing variables and high temperature aging and
temperature cycling. Elements of inner process
quality control are as follows:
• Condition control of equipment and workers
environment and random sampling of semifinal products.
• Suggestion system for improvement of work.
• Education of workers.
• Maintenance and improvement of yield.
• Determining quality problems. and implement·
ing countermeasures.
• Transfer of quality information.

Uniformity of Gradation

Processing
Frame

3.3.2 Inner Process Quality Control
Inner Process Quality Control performs very important
functions in quality assurance of semiconductor
devices. The manufacturing Inner Process Quality
Control is shown in Fig. 3.

Mechanical Strength

(3) Quality Control of Manufacturing Circumstances
and Sub-Materials
The quality and reliability of semiconductor devices
are highly affected by the manufacturing process.
Therefore. controls of manufacturing circum-

Molding Performance
Mounting Characteristics

•

HITACHI

QUALITY ASSURANCE
stances such as temperature, humidity and dust,

attention to buildings, facilities, air conditioning

and the control of submaterials,like gas, and pure

systems, delivered materials, clothes, work envir-

water used in a manufacturing process, are inten-

onment, and periodic inspection of floating dust

sively executed.

concentration.

Dust control is essential to realize higher integra-

3.3.3 Final Product Inspection and Reliability

tion and higher reliability of devices. At Hitachi,

Assurance

maintenance and improvement of cleanliness at

(1) Final Product Inspection

manufacturing sites is accomplished through

Process

Lot inspection is done by the quality assurance

Control Point

Purpose of Control

Purchase of Material

wafer~

Wafer

, Surface Oxidation
Inspection on Surface
Oxidation
Photo Resist

Charactdristics, Appearance

Oxidation
Appearance, Thickness of
Oxide Film

Scratch, Removal of Crystal
Defect Wafer
Assurance of Resistance
Pinhole, Scratch

Photo
Resist

Inspection on Photo Resist
<) pac Level Check
Diffusion

Diffusion

Dimension, Appearance

Dimension Level

Diffusion Depth, Sheet

Check of Photo Resist
Diffusion Status

Resistance

Inspection on Diffusion
<) pac Level Check

Gate Width
Characteristics of Oxide Film
Breakt:own Voltage

Evaporation

Evapora·

Thickness of Vapor Film,

tion

Scratch, Contamination

Wafer

Thickness, VTH Characteris·

Control of Basic Parameters
(VTH, etd Cleanness of surface,
Prior Check of V,H
Breakdown Voltage Check
Assurance of Standard
Thickness

Inspection on Evaporation
<) PQC Level Check
Wafer Inspection

tics

Prevention of Crack,
Quality Assurance of Scribe

Inspection on Chip
Electrical Characteristics
Chip Scribe
I nspection on Ch ip
Appearance
<) PQC Lot Judgement

Chip

Electrical Characteristics

Assembling

Assembling

Appearance after Ch ip
Bonding
Appearance after Wire
Bonding
Pull Strength, Compression
Width, Shear Strength
Appearance after Assembling

Quality Check of Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short

Sealing

Sealing
Marking

Appearance after Sealing
Outline, Dimension
Marking Strength

Guarantee of Appearance
and Dimension

PQC Level Check
Final Electrical Inspection
<) Failure Analysis

Appearance of Chip

Frame

<)

PQC Level Check

I nspection after
Assembling
<) PQC Lot Judgement
Package

<)

Analysis of Failures, Failure
Mode, Mechanism

Feedback of Analysis Infor·
matian

Appearance Inspection
Sampling Inspection on
Products
Receiving
Shipment
Figure

3

Example of Inner Process Quality Control

eHITACHI

29

QUALITY ASSURANCE - - - - - - - - - - - - - - - - - - - - department for products which were judged good
in 100% test ... the final process in manufacturing. Though 100% yield is expected, sampling
inspection is executed to prevent mixture of bad
product by mistake. The inspection is executed not
only to confirm that the products have met the
users' requirements but also to consider potential

quality factors. Lot inspection is executed based
on MIL-STD-1050.
(2) Reliability Assurance Tests
To assure the reliability of semiconductor devices,
reliability tests and tests on individual manufacturing lots that are required by the user, are periodically performed.

j

Customer

Claim
(Failures, Information)
Sales Dept.
Sales Engineering Dept.

r - - - - - - - - - - - - t--------- -------------,

I
I
I

I
I
I
I
I

L

I

I
I

L

Countermeasure
Execution of
Countermeasure

DeSign Dept.

Manufacturing Dept.

I

I
I
I
I
I
I

Failure Analysis

Quality Assurance Dept.

Report

I----

Report

Follow-up and Confirmation
of Countermeasure Execution

____________ -l

--------

Sales Engineering Dept.
Reply

Customer
Figure 4 Process Flow Chart of Field Failure

30

I
I
I
I

~

Quality Assurance Dept.

-------------

I

I

•

HITACHI

RELIABILITY TEST DATA
1. INTRODUCTION

Microcomputers provide high reliability and quality to meet
the demands of increased functions, enlarging scale, and widening application. Hitachi has improved the quality level of
microcomputer products by evaluating reliability, building
quality into the manufacturing process, strengthening inspection
techniques, and analyzing field data.
The following reliability and quality assurance data for
Hitachi 8-bit single-chip microcomputers indicates results from
test and failure analysis.

(1)

2. PACKAGE AND CHIP STRUCTURE
2.1 Packaging
Production output and application of plastic packaging continues to increase, expanding to automobile measuring and control systems, and computer terminal equipment operating under
severe conditions. To meet this demand, Hitachi has significantly
improved moisture resistance and operational stability in the
plastic manufacturing process.
Plastic and side-brazed ceramic package structures are shown
in Figure I and Table I.

Plastic DIP

121 Plastic Flat Package

Bonding wire

Figure 1 Package Structure

Table 1 Package Material and Properties

Item
Package

Plastic DIP

Plastic Flat Package

Epoxy

Epoxy
Solder plating Alloy 42

Lead

Solder dipping Alloy 42

Die bond

Au·Si or Ag paste

Au·Si or Ag paste

Wire bond

Thermo compression

Thermo compression

Wire

Au

Au

•

HITACHI

31

RELIABILITY TEST D A T A - - - - - - - - - - - - - - - - - - - - - - - - - - 2.2 Chip Structure
The HMCS6800 family is produced in NMOS Ej D technology or low power CMOS technology. Si-gate process is used

in both types to achieve high reliability and density. Chip structure and basic circuitry are shown in Figure 2.

Si·Gate N-channel E/O

Drain

Source

FET1

Drain

Si·Gate CMOS

Si0 2

Source

Drain

Source
FET2

FET2

P..,hannel
EMOS

N·channel
OMOS

N-channel
EMOS

N-channel
EMOS

Figure 2 Chip Structure and Basic Circuit

3. QUALITY QUALIFICATION AND EVALUATION
3.1 Rellabllltv Te.t Method,
Reliability test methods shown in Table 2 are used to qualify and evaluate new products and processes.
Table 2 Reliability Test Methods
Test Items

32

Test Condition

MIL·STD·883B Method No.

Operating Life Test

125°C,1000hr

1005,2

High Temp, Storage
Low Temp, Storage
Steady State Humidity
Steady State Humidity Biased

Tstg max, 1000hr
Tstg min, 1000hr
65°C 95%RH, 1oo0hr
85°C 85%RH, 1000hr

1008,1

Temperature Cvcling
Temperature Cycling
Thermal Shock
Soldering Heat
Mechanical Shock
Vibration Fatigue
Variable Frequency
Constant Acceleration
Lead Integrity

_55°C -150°C, 10 cycles
_20°C - 125°C:200 cycles
OOC - 100°C, 100 cycles
260°C, 10 sec
1500G 0.5 msec, 3 times/X, Y, Z
60Hz 20G, 32hrs/X, Y, Z
2D-2oo0Hz20G,4min/X, Y, Z
20000G,1 min/X, Y, Z
225gr, 90° 3 times

1010,4

•

1011,3
2002,2
2005,1
2007,1
2001,2
2004,3

HITACHI

~---~-

~~---

- - - - - - - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y TEST DATA
3.2 R.liability T.st R.sults
Reliability Test Results of 8-bit single-chip microcomputer
devices are shown in Table 3 to Table 7.

Table 3 Dynamic Life Test
Sample Size

Device

Component Hour

191
HD6801P
HD6605P
114
.........................................................................................

Failure

191000
0
114000
0
, .....................................................................................

HD6301P
HD63L05FP
HD6305XP

92
40
56

92000
40000
56000

0
0
0

HD68POl
HD68P05

22
22

22000
22000

o
o

Table 4 High Temperature. High Humidity Test (Moisture Resistance Test)
(1) 85°C 85%RH Bias Test
Device

,Vee Bias

168 hrs

500 hrs

HD6601P
HD6B05P
HD6301P
Total

5.5V
5.5V
5.5V

0/22
0/22
0/176
0/220

0/22
0/22
0/131

1000 hrs
0/22
0/22
0/131

0/175

0/175

(2) High Temperature High Humidity Storage Life Test
Device

Condition

HD6B01P
HD6805P
HD6301P
HD6301P
HD63L05FP
HD63L05FP
HD6305XP

65°C 95%RH
65°C 95%RH
65°C 95%RH
85°C 95%RH
65°C 95%RH
85°C 95%RH
65°C 95%RH

168 hrs
0/45
0/45
0/603
0/234
0/160
0/160
0/373

500 hrs
0/45
0/45
0/603
1*/234
0/160
1*/160
0/373

1000 hrs
0/45
0/45
0/603
0/233
0/160
0/159
0/373

* Aluminium corrosion
(3) Pressure Cooker Test
(121°C,2atm)
Device
HD6801P
HD6B05P
HD6301P
HD6305XP
HD63L05FP

40 hrs

60 hrs

100 hrs

200 hrs

0/13
0/44
0/135
0/83

0/13
0/44
0/135
0/83
0/80

0/13
0/44
0/135
0/83
1*/80

0/13
0/44
0/135
0/83
2**/79

O/SO

* Current leakage
** Current leakage and aluminium corrosion

•

HITACHI

33

RELIABILITY TEST DATA - - - - - - - - - - - - - - - - - - - - - - - - - (41 MIL·STD·883B Moisture Resistance Test
(_65°C - _10°C, 90%ijH or morel
Device

20 cycles

40 cycles

0/50
0/32
0/75
0/22

0/50
0/32
0/75 .
0/22

10 cycles

100 cycles

200 cycles

0/102
0/442
0/258
0/80
~~::·

0/102
0/45
0/258
0/80
...........................................
0/44
0/19

0/102
0/45
0/258
0/80
...........................................
0/44
0/19

10 cycles
, 0/50
0/32
0/75
0/22

HD6801P
HD6805P
HD6301P
HD63L05FP

Table 5 Temperature Cycling Test
(-SSoC - 150°CI
Device
HD6801P
HD6805P
HD6301P
HD6305XP
············t·g:::~!····

. ·. ····· . ··r···· . · . · · . ..................

Table 6 High Temperature, Low Temperature Storage Life Test

Device
HD6801P

Temperature
150°C
_55°C

168 hrs
0/22
0/22

500 hrs
0/22
0/22

1000 hrs
0/22
0/22

0/22

0/22

0/22

.......................................... ················'·50·C·················· ··················iii44· .. ··········· ·············· ....oi;j;j··············· ··········· .. ···0/44 .. ·........ ·· ..
HD6805P
-55°C
0/22
0/22
0/22
.......................................... ·.... ·.. ·· .... ··;·50°C· .. ····...... ·.. ·· ·· .... ·· .... ·.. ·.. oi'22' .... ·..·.. ·.. ·.... ·.. ·.. ·......Oi22 .... ·.. ·..··· .. ·..·.. ·· .. ·· .. ·..0122 .. ·.. ··· .. ··· ..
HD6.301P
0/22
0/22
..................................
,., .. ". ,.. ,... ,.... ,' _55°C
." .. ,.. ',., ...... '0/22
0/22' .. ·.. ",·,·,· ., ....... ,',.', .. 'oi:i:i
.. '.... ·" .. ,,· .. ,..... ,....... 0·i22""'
.. ·, ......
",'50~C''''''''''''''''''

HD63L05FP

-55 C

Table 7 Mechanical and Environmental Test
Test Item
Thermal Shock
Soldering Heat
Salt Water Spray
Solderability
Drop Test
Mechanical Shock
Vibration Fatigue
Vibration Variable Freq.
Lead Integrity

34

Plastic DIP

Condition
0°C-l00°C
10 cycles
260° C, 10 sec.
35°C, NaCI 5%
24 hrs
230°C, 5 sec.
Rosin flux
75cm, maple board
3 times
1500G, 0.5ms
3 times/X, Y, Z
60 Hz, 20G
32hrs/X, Y, Z
100-2000Hz
20G, 4 times/X, Y, Z
225g, 90°
Bonding 3 times

•

Flat Plastic Package

Sample Size

Failure

110

0

100

0

Sample Size

Failure

164

0

2,)

0

110

0

20

0

159

0

34

0

110

0

20

0

110

0

20

0

110

0

20

0

110

0

20

0

110

0

20

0

HITACHI

- - - - - - - - - - - - - - - - - - - - - - - - - - - RE LlASI LlTY TEST DATA
4.

PRECAUTIONS

4.3 Handling for Measurement

4.1 Storage

To prevent deterioration of electrical characteristics, solderability, appearance or structure, Hitachi recommends semiconductor devices be stored as follows:
(I) Store in ambient temperatures of 5 to 300 C, with a relative
humidity of 40 to 60%.
(2) Store in a clean, dust- and active gas-free environment.
(3) Store in conductive containers to prevent static electricity.
(4) Store without any physical load.
(5) When storing devices for an extended period, store in an
unfabricated form, to minimize corrosion of pre-formed
lead wires.
(6) Unsealed chips should be stored in a cool, dry, dark and
dust-free environment. Assembly should be performed
within 5 days of unpacking. Devices can be stored for up to
20 days in dry nitrogen gas with a dew point at -300 C or less.
(7) Prevent condensation during storage due to rapid temperature changes.

Avoid static electricity, noise and voltage surge when measuring or mounting devices. Precaution should be taken against
current leakage through terminals and housings of curve tracers,
synchroscopes, pulse generators, and DC power sources.
When testing devices, prevent voltage surges from the tester,
attached clamping circuit, and any excessive voltage possible
through accidental contact.
In inspecting a printed circuit board, power should not be
applied if any solder bridges or foreign matter is present.
4.4 Soldering

Semiconductor devices should not be exposed to high
temperatures for excessive periods. Soldering must be performed
consistent with temperature conditions of 2600 C for 10 seconds,
3500 C for 3 seconds, and at a distance of I to 1.5mm from the end
of the device package.
A soldering iron with secondary voltage supplied through a
grounded transformer is recommended to protect against
leakage current. Use of alkali or acid flux, which may corrode the
leads, is not recommended.

4.2 Transportation

General precautions for electronic components are applicable in transporting semiconductors, units incorporating semiconductors, and other similar systems. In addition, Hitachi
recommends the following:
(I) When transporting semiconductor devices or printed circuit
boards, minimize mechanical vibration and shock. Use containers or jigs which will not induce static electricity as a
result of vibration. Use of an electrically conductive container or aluminum foil is recommended.
(2) To prevent device deterioration from clothing-induced static
electricity, workers should be properly grounded while handling devices. Use of a I M ohm resistor is recommended to
prevent electric shock.
(3) When transporting printed curcuit boards containing semiconductor devices, suitable preventive measures against
static electricity must be taken. Voltage build-up can be
avoided by shorting the card-edge terminals. When a belt
conveyor is used, apply some surface treatment to prevent
build-up of electrical charge.
(4) Minimize mechanical vibration and shock when transporting semiconductor devices or printed circuit boards .

•

4.5 Removing Residual Flux

Detergent or ultrasonic removal of residual flux from circuit
boards is necessary to ensure system reliability. Selection of
detergent type and cleaning conditions are important factors.
When chloric detergent is used for plastic packaged devices,
care must be taken against package corrosion. Extended
cleaning periods and excessive temperature conditions can cause
the chip coating to swell due to solvent permeation. Hitachi
recommends use of Lotus and Dyfron solvents. Trichloroethylene solvent is not suitable.
The following conditions are advisable for ultrasonic
cleaning:
•
Frequency: 28 to 29 k Hz (to avoid device resonation)
•
Ultrasonic output: 15W/f
•
Keep devices from making direct contact with power
generator
•
Cleaning time: Less than 30 seconds.

HITACHI

35

DESIGN PROCEDURE AND SUPPORT TOOLS FOR
8-BIT SINGLE-CHIP MICROCOMPUTERS
The cross assmebler and hardware simulator using various
types of computers are prepared by Hitachi as supporting systems to develop user's programs.
User's programs are mask programmed into the ROM and

delivered as the LSI by the company.
Fig. I shows the typical program design procedure and Table
I shows the system development support tools for the 8-bit
single-chip microcomputer family used in these processes.

-----'l

Rl "2.2kn

Test Point

r

30PF

®

152074

or Equl ....

C

(a) CMOS Load

R

(bl TTL Load

Figure 9 Bus Timing Test Loads

l."'."'"""'.

-I

.. .

.,

evele

., I .. I .. 1

"0

I

I

011

I

.,2

Inlernal
A~r"$Bus~_~~_~~

_

_''__~~_~

OpCode OpCodeAddr

NiMlorIAo~-------,\~~

SPlnl

___J\_ _~_ _~_
sPtn.1)

SPCn·21

5Pln·31

_J~_

SP{n-41

_''__~~_J\

SPln·51

SP(n·61

SPI~·71

Addr

_ _ ~_

Vector
MSB Addr

_J~_

Vector

_ ' ' ____

NewPC

lSI Add, Addreu

__________________________________________________________

~11_tPcs

.._--v--...r -........r--__,,.--...,...----v---'V"--...r - - v - -........,...-......r---..,.·-......r--_....,....--v--

Inlernal...,. •

Data Bus ~--~--lIo-.-c-....
-'\.O-.-C-od-.~PC-O---PCJ7"P-C8---PC-'J.'-xo---X-7I\..X-8--X-,-S"-A-C-C-AJ\-.-C-c.-''-C-C-R~...',-,.-'....
-.,~-V-"'-'0-'~v-oc-'-O,..A-F,-,,-,-..J,.\.o-Data
InternalR/W

*IR02 .... Internal

MSB

LSB

I"""uP! Routin_

InterruPt\~-----------------------JI
Figure 10 Interrupt Sequence

E

~\\\\\\\\\\\\\\\ ~\\\\\\\\\\\\\\\\ ~ ~~
-s.OSV

11-------------11

'I

~ ------~ll·

1

n

~~~
, \,•.-------.-:_-_-_-_-_-_-_-_-_.R________
C
-4! ----+~;_tPCS

~
'~OB:::-':...._P2 clock frequency or
external clock x8 input
• wake-up feature - enabled or disabled
• Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Serial Communications Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 22. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
Transmit/Receive Control and Status (TRCS) Register
The TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0-4 may be written. The
register is initialized to $20 on RES. The bits in the TRCS
register are defined as follows:

Transmit/Receive Control and Status Register

76543210

IROREI ORFE ITORE I RIE I RE I TIE I TE I
58

eHITACHI

wu

I AOOR : $0011

-----------------------------------------------------HD6801S0,HD6801S5
Bit 7

Rate and Mode Control Register

alt 0

I eel Ieeo 1551 Isso ISla

I

Transmit/ReceIVe Control and Status Register

Port 2
R.
B,t
3

11

T.
Bit
4

12

Figure 22 Serial I/O Registers
writing a new byte into the transmit data register,
TDRE is initialized to I by
Bit 6 ORFE Over-Run-Praming Error - set by hardware when
an overrun or framing error occurs (receive only).
An overrun is defined as a new byte received with
last byte still in Data Register/Buffer. A ~raming
error has occurred when the byte boundaries in bit
stream are not synchronized to bit counter. The
ORFE bit is cleared by reading the status register,
then reading the Receive Data Register, or by
RES.
Bit 7 RORF Receiver Data Register Full - Set by hardware
when a transfer from the input shift register to the
receiver data register is made. The RDRF bit is
cleared by reading the status register, then reading
the Receive Data Register, or by RES.

Bit 0 WU

"Wake-up" on Next Message - set by HD6801S
software and cleared by hardware on receipt of
ten consecutive I's or reset of RE flag. It should
be noted that RE flag should 'be set in advance of
CPU set of WU flag.
Bit I TE
Transmit Enable - set by HD680lS to produce
preamble of nine consecutive I's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set-up of transmit data
rate and mode.
Bit 2 TIE
Transmit Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 5 (TDRE) is
set; when clear, the TDRE value is masked from
the bus.
Bit 3 RE
Receiver Enable - when set, gates Port 2 bit 3 to
input of receiver regardless of DDR value for this
bit; when clear, serial I/O has no effect on Port 2
bit 3.
Bit 4 RIE
Receiver Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.
Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared by reading the status register, then

m.

Rate and Mode Control Register
The Rate and Mode Control register controls the follOWing
serial I/O variables:
• Baud rate
• format
• clocking source, and
• Port 2 bit 2 configuration
The register consists of 4 bits aU of which are write-only and
cleared on RES. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining two bits control the
format and clock select logic. The register definition is as
follows:

Rate and Mode Control Register

7

6

6

4

X

X

X

X

3

2

I I ceo I
CC1

_HITACHI

0
SS1

SSO

ADDR : $0010

59

HD6801S0.HD6801S5-----------------------------------------------------Bit 0 SSO
Bit I SS1

Speed Select - These bits select the Baud rate for
the internal clock. The four rates which may be
selected are a function of the CPU 2 clock
frequency. Table 5 lists the available Baud rates.

Bit 2 CCO Clock Control and Format Select - this 2-bit field
Bit 3 CC1 controls the format and clock select logic. Table 6
defines the bit field.

Table 5 SCI Bit Times and Rates
XTAL

2.4576 MHz

4.0 MHz

E

614.4 kHz

1.0 MHz

E+ 16
E+ 128
E+ 1024

26Ils/38.400 Baud

16 Ils/62.500 Baud

208Ils/4.800 Baud

128Ils/7812.5 Baud

104.2 Ils/9.600 Baud

1.67 ms/600 Baud
6.67 ms/150 Baud

1.024 ms/976.6 Baud
4.096 ms/244.1 Baud

833.3Ils/1.200 Baud

551 : SSO
0
0
1
1

0
1
0
1

E+4096

4.9152 MHz'
1.2288 MHz
13Ils/76.800 Baud

3.33 ms/300 Baud

• HD680'S5 Only

Table 6 SCI Format and Clock Source Control
CC1: CCO
0
0
1
1
•

0
1
0
1

Port 2 Bit 2

Port 2 Bit 3

Port 2 Bit 4

-

-

-

NRZ
NRZ
NRZ

Internal
Internal
External

Not Used
Output'
Input

...,

"
.,
"
.,

Format

Clock Source

Clock output is available regardless of values for bits RE and TE.

Bit 3 is used for serial input if RE ~ "'" in TRCS; bit 4 is used for serial output if TE

InternallY Generated Clock
If the user wishes for the serial I/O to furnish a clock, the
following requirements are applicable:
• the values of RE and TE are immaterial.
• CCI, CCO must be set to 10
• the maximum clock rate will be E + 16.
• the clock will be at Ix the bit rate and will have a rising
edge at mid-bit.
Externally Generated Clock
If the user wishes to provide an external clock for the serial
I/O, the following requirements are applicable:
• the CCI, CCO, field in the Rate and Mode Control Register
must be set to II,
• the external clock must be set to 8 times (x 8) the desired
baud rate and
• the maximum external clock frequency is 1.0 MHz.
• Serial Operations
The serial I/O hardware should be initialized by the
H0680lS software prior to operation. This sequence will
normally consist of;
• writing the desired operation control bits to the Rate and
Mode Control Register and
• writing the desired operational control bits in the Transmit/
Receive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.

60

•

"

"
= ", .. in TRCS.

Transm it Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit when
set, gates the output of the serial transmit shift register to Port 2
Bit 4 and takes unconditional control over the Data Direction
Register value for Port 2, Bit 4.
Following a RES the user should configure both the Rate
and Mode Control Register and the Transmit/Receive Control
and Status Register for desired operation. Setting the TE bit
during this procedure initiates the serial output by first
transmitting a nine-bit preamble of I's. Following the preamble,
internal synchronization is established and the transmitter
section is ready for operation.
At this point one of two situation exist:
I) if the Transmit Data Register is empty (TDRE = I), a
continuous string of ones will be sent indicating an idle
line, or,
2) if data has been loaded into the Transmit Data Register
(TDRE = 0), the word is transferred to the output shift
register and transmission of the data word will begin.
During the transfer itself, the 0 start bit is first transmitted.
Then the 8 data bits (beginning with bit 0) followed by the stop
bit, are transmitted. When the Transmitter Data Register has
been emptied, the hardware sets the TDRE flag bit.
If the H0680 I S fails to respond to the flag within the proper
time, (TDRE is still set when the next normal transfer from th~
parallel data register to the serial output register should occur)
then a I will be sent (instead of a 0) at "Start" bit time,
followed by more I's until more data is supplied to the data
register. No O's will be sent while TDRE remains a I.

HITACHI

------------------------------------------------------HD6801S0,HD6801S5
Receive Operation
The receive operation is enabled by the RE bit which gates in
the serial input through Port 2 Bit 3. The receiver section
operation is conditioned by the contents of the Transmit/
Receive Control and Status Register and the Rate and Mode
Control Register.
The receiver bit interval is divided into 8 sub·intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a I (stop bit) a framing
error is assumed, and bit ORFE is set. If the tenth bit as a I, the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set.·If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an over·run has occurred. When the
HD6801S responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register, RDRF
(or ORFE) will be cleared.
• RAM CONTROL REGISTER
This register, which is addressed at $0014, gives status
information about the standby RAM. A 0 in the RAM enable
bit (RAM E) will disable the standby RAM, thereby protecting
it at power down if Vcc Standby is held greater than VSBB
volts, as explained previously in the signal description for Vee
Standby.

- Condition code register manipulation instructions - Table 10
- Instructions Execution times in machine cycles - Table
II

- Summary of cycle by cycle operation - Table 12
• Op codes Map - Table I3
• CPU Programming Model
The programming model for the HD680 I S is shown in Figure
23. The double (D) accumulator is physically the same as the
Accumulator A concatenated with the Accumulator B so that
any operation using accumulator D will destroy information in
A and B.

8·Blt Accumulators A and 8
Or 16·8.t Double Accumulator 0

1,5

0

1 Index

115

SP

0

1 Stack POinter (SP)

115

PC

0

1

s;W~

IRAMEI

X

I

X

I

X

(XI

Program Counter (PC)

Condition Code Register (CCR)

RAM Control Register
$00141

Regl~ter

X

Carry/Borrow from MSB
Overflow
Zero
Nept'v,
Interrupt
Half Carry (From Bit 3)

X

Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAME The RAM Enable control bit allows the user the
ability to disable the standby RAM. This bit is set
to a logic "I" by RES which enables the standby
RAM and can be written to one or zero uner program control. When the RAM is disabled, data is
read from external memory.
Big 7 STBV The Standby Power bit is cleared when the standPWR by voltage is removed. This bit is a read/write status flag that the user can read which indicates that
the standby RAM voltage has been applied, and
the data in the standby RAM is valid.
• GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6801S is upward object code compatible with the
H06800 as it implements the full HMCS6800 instruction set.
The execution times of key instructions have been reduced to
increase throughout. In addition, new instructions have been
added; these include 16-bit operations and a hardware multiply.
Included in the instruction set section are the following:
• CPU Programming Model (Figure 23)
• Addressing modes
• Accumulator and memory instructions - Table 7
• New instructions
• Index register and stack manipulations instructions - Table

Figure 23 CPU Programming Model.
• CPU Addressing Modes
The H06801S eight-bit microcomputer unit has seven
address modes that can be used by a programmer, with the
addressing mode a function of both the type of instruction and
the coding within the instruction. A summary of the addressing
modes for a particular instruction can be found in Table 11
·along with the associated instruction execution time that is
given in machine cycles. With a clock frequency of 4 MHz, these
times would be microseconds.
Accumulator (ACCX) AddreSSing
In accumulator only addressing, either accumulator A or
accumulator B is specified. These are one-byte instructions.
Immediate Addressing
In immediate addressing, the operand is contained in the
second byte of the instruction except LDS and LOX which have
the operand in the second and third bytes of the instruction.
The CPU addresses this location when it fetches the immediate
instruction for execution. These are two or three-byte instructions.

8
• Jump and branch instructions - Table 9

•

HITACHI

61

HD6801S0,HD6801S5 - - - - - - - - - - - - - - - - - - - - - - - - - Table 7 Accumulator & Memory Instructions
Condition Code

Addressing Modes
Operations

Mnemonic

IMMED.
OP

Add

ADDA

8B

ADDB

CB

Add Double

ADDD

C3

Add Accumulators

ABA

Add With Carry

ADCA
ADCB

C9

ANDA

84

ANDB

C4

Bit Test

BITA

85

BIT B

C5

Compare

CLR

OP

-

#

OP

-

#

2 B9
09 3 2 E9 4 2 F9
94 3 2 A4 4 2 B4
04 3 2 E4 4 2 F4
2 2 95 3 2 AS 4 2 B5
2 2 05 3 2 E5 4 2 F5
6F 6 2 7F

2
2
2
2

2
2
2
2

99

3 2

A9

4

A:B+M:M+l .... A:B

2 1 A+B .... A
A+M+C .... A
B+M+C .... B
A·M .... A
B·M .... B

3

4

3

4

3

4

3

4

3

A·M

4

3

B·M

6

3
2

1 00 .... B

81

CMPB

Cl

2

2 91
2 2 01

4

2

Bl

4 3

A-M

4

2

Fl

4 3

B-M

•

A-B

63

6

2

73

6

•
•

11

2

1

M .... M

3
43

2

1

A .... A

COMB

53

2

1

B .... B

60

IIIEG
NEGA
NEGB

Decrement

DEC

6A

6

2

2

6

70

6

7A 6

OO-M .... M

3
40

2

50

2

19

2

M-l .... M
4A

2

DECB

5A

2

8B

2 2 98

EORB

C8

2 2

3 2

08 3

2

INC

4

3

A(j;) M .... A

E8

4

2

F8

4

3

B (j;) M.... B

6C

6

2 7C

6

3

2 2 96

LDAB

C6

2

Load Double
Accumulator

LDD

CC 3 3

Multiply Unsignad

MUL

OR, Inclusive

ORAA

8A

ORAB

CA 2 2

3

2 A6 4

2

B6

4

3

E6

2

F6

4

3

EC 5 2

FC

5 3

2 06 3 2
DC 4

2

4

3 2

DA 3

2

AA 4

2

BA 4

3

EA 4

2

FA 4

3

M .... B

A+M .... A
B + M .... B
3

1 A .... Mop, SP - 1 .... SP

PSHB

37

3

Pull Data

PULA

32

4

33

4

1 B .... Msp, SP - 1 .... SP
1 SP + 1 .... SP, Mop .... A
1 SP + 1 .... SP. Mop .... B

Rotate Left

ROL
ROLA

49

2

1

ROLB

59

2

1

Rotate Right

ROR

66

6

6

2 79

2

76

6 3

6

3

RORA

46

RORB

56

..
The Condition Code Register nates are listed after Table 10.

:l~"""
B

C

b7

~-H-1 ~l?'

2

B

b7

f
f
f

•
•

f
f
f
f
f

f
f
f
f
f
R 5
R 5
R 5
: f
f f

f

f

•
•

R
R
R

R R
R R
R R

f
f

f
f

f

f

f

f R S
f R S

f

R

* CD@)S
*f CD@)
f CD@)
f

f

HITACHI

®

f @ •

@ •

f
f
f

:
f

• •
• • •
•• f
• • f
• • •
• • •
•• •
• • •
• • f
•• f
• • f
• • f
• • f
• • f

1101
bo

1 1 1 1 1 I~
bO

f @ •
f @ •
f @.
f R
f R

•

f R

•
•

• • ®
f R •
f

R

•

• • •

•••
•• •
•• •
f
f
f
f
f
f

@ f
@ f
@ f
@ f
@ f
@

(Continued)

•

•
•

f
f
f
f
f

• *
• f
•
•

f
R

f

f

M + 1 .... B. M .... A

36

69

•

• •
••
• •

PSHA

PULB

•
•
•
•
•
•
•
•
•
•

·• ·•

1 A+l .... A
2 1 B + 1 .... B
M .... A

2

3D 10 1 AxB .... A:B
2 2 9A

•
•
•
•
•
•
•
•

f

• • ** *f @ •
• • f f R •
• • *f R •

M+1-M
5C

INCB
86

1 A -1 .... A
1 B-1 .... B

AS 4 2 B8

4C

LDAA

1 00 - A .... A
1 OO-B .... B
Converts binary add of Bcb
1 characters.into BCD format

3

DECA
EORA

•
•

2 Al
3 ,2 El

3

COMA

DAA

••
•
•
•
•

1 0

*
* *f f
• ** * : :*
• f f f f

•
• •

OO .... M
5F

CMPA

f
f
f

3 2

I N Z V C

•
•
• •
f
f

B+M .... B

4

INCA

62

A+B .... A

2 2 9B 3 2 AB 4 2 BB 4 3
2 DB 3 2 EB 4 2 FB 4· 3
4 3 03 5 2 (;3 6 2 F3 6 3

2

5 4
H

#

CLRB

Decimal Adjust. A

Push Data

-

1 00 .... A

COM

Load
Accumulator

OP

2

CElA

Increment

#

4F

Complement. 1 's

Exclusive OR

-

Arithmetic Operation

CLRA

Compare
Accumulators

Complement. 2's
(Negate)

OP

Boolean/

IMPLIED

lB
89

AND

Clear

-

#

Register

EXTEND

INDEX

DIRECT

f

------------------------------------------------------HD6801S0,HD6801S5
Table 7 Accumulator & Memory Instructions (Continued)
Condition Code

Addressing Modes

Operations

Mnemonic

IMMED.
OP

Shift Left
Arithmetic

Double Shift
Left. Arithmetic
Shift Right
Arithmetic

-

#

DIRECT
OP -

#

ASL

INDEX

EXTEND
OP

OP -

#

68

2 78

6

-

#

Double Shift
Right Logical

IMPLIED
OP

-

Ml [Hllllillt--o
--

ASLA

48

ASL8

58

2 1
2 1

ASLD

05

3 1 ~

A
B

C

b7

6

2 77

6

3
47

ASRA

57

LSR

64

6

2 74

6

2 1
2 1

3
44

LSRB

54

2 1
2 1

LSRD

04

3 1

LSRA

3 2 A7 4 2 B7
3 2 E7 4 2 F7

Store
Accumulator

STAA

97

STAB

07

Store Double
Accumu lator

STD

DO 4

Subtract

SUBA

BO

2

ED 5

-

B

b7

~l0"'i
0->1
A.7

4

3

A_M

4

3

B_M

-

ACC AI ACCB
AO

87

B-M-+B
A:B-M:M+l->A:B

SUBB

CO

Double Subtract

SUBD

83

Subtract
Accumulators

SBA

Subtract
With Carrv

SBCA

82

2 2 92

3 2

A2

4

2

B2

4

3

A-M-C-A

SBCB

C2

2 2

3

E2

4

2

F2

4

3

B -M-C"'B

Transfer
Accumulators

TAB
TBA

Test Zaro or
Minus

TST
TSTA
TSTB

10

2

1

A - B-+ A

2 1 A-+B
17 2 1 B_A
M-OO
60 6 2 70 6 3
40 2 1 A -00
50 2 1 B - 00
16

Tho ConditIon Code Re~l.ter nota. ara listed eftar Teble 10.

Direct Addreasing
In direct addressing, the address of the operand is contained
thE! second byte of the instruction. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine
i.e., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations, it should be a random access memory. These are two-byte
instructions.
Extended Addressing
In extended addressing, the address contained in the second
byte of the instruction is used as the higher eight-bits of the
address of the operand. The third byte of the instruction is used
as the lower eight-bits of the address for the operand. This is an
absolute address in memory. These are three-byte instructions.
Indexed Addressing
In indexed addressing, the address contained in the second
byte of the instruction is added to the index register's lowest

tt.\

•

80

A-M_A

3 2 AO 4 2 BO 4 3
2 2 DO 3 2 EO 4 2 FO 4 3
4 3 93 5 2 A3 6 2 B3 6 3

2

~

·•
•

• •

• •
• •
• •
• •
••
• •
• •
• •

•
•
•
•
•
•
•
•
•

Register
3 2 1 0

I N Z V

bO

A-+ M
B _ M+l

2 FD 5 3

2 2 90

02

BQ

1 111111J""'9

b7

•
•
•
•
•

•
•
l/ili 1 ~ • •
• •
1+-0

AQ 81

~) I:?I

B

bO

ACe AI Ace B

A7

67

ASR

5 4
H

#

6 3

ASR8
Shift Right
Logical

Booleanl
Arithmetic Operation

•
•

•

•
•
•
•
•
•

C

t t @t
t t @t
t t 6 t
t t @ t
t
t
t
t
t
t

@t
@t
@t
§) t
@t
t @t

R

t @t

t
t
t
t
t

t t
t t

R

t

R

t

R

•

•
•

t
t
t
t

t t t
t t t
t t t
t t t
t t t t
t t t t
t t R •
t t R •
t t R R
t t R R
t t R R

eight bits in the CPU. The carry is then added to the higher
order eight bits of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addressing
In the implied addressing mode the instruction gives the
address (i.e., stack pointer, index register, etc.). These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
eight bits plus two. The carry or borrow is then added to the
high eight bits. This allows the uSer to address data within a
range of -126 to +129 bytes of the present instruction. These
are two-byte instructions.

HITACHI

63

HD6801S0,HD6801S5-------------------------• New Instructions
In addition to the existinJ!, 6800 Instruction Set, the following new instructions are
incorporated in the H06801S Microcomputer.
ABX

Adds the 8-bit unsigned accumulator B to the 16-bit X-Register taking into account
the rossible carry out of the low order t-" Ie of the X-Register.
ADDD Add~ the double precision ACCD* to t.. double precision value M: M+ I and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double precision memory location into the double
accumulator A:B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator B to obtain a
16-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address contained
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack' beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents 9f double accumulator A:B in memory. The contents of ACCD
remain unchanged.
S!JBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX

Internal processing modified to permit its use with any conditional branch instruction .

• ACCD is the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A-accumulator is the most significant byte.

Table 8 Index Register and Stack Manipulation Instructions
Addressing Modes
Pointer Operations

Mnemonic

IMMED.
OP BC 4

Compare Indu Reg

CPX

Decrement Index Reg

DEX

Decrement Stack Pntr

DES

Increment Index Reg

INX

Increment Stack Pntr

INS

Load I ndex Reg

LOX

CE
BE

DIRECT
# OP
#
3 9C 5 2

-

DE 4

2
3 3 9E 4 2
OF 4 2
9F 4 2
3 3

Booleanl
Arithmetic Operation

EXTND
IMPLIED
# OP
# OP
#
AC 6 2 BC 6 3
X-M: M+1
09 3 1 X-1-X
34 3 1 SP-1-SP
INDEX

OP

-

-

5 2 FE 5
AE 5 2 BE 5
EF 5 2 FF 5
AF 5 2 BF 5
EE

-

08

3

1 X+ 1- X

31

3

1 SP+1-SP
M- X H • (M+1)- XL

3
3

M- SP H • (M+1)-SP L

3

XH - M. XL - (M + 1)

Load Stack Pntr

LOS

Store I ndex Reg

STX

Store Stack Pntr

STS

I ndex Reg - Stack Pntr

TXS

36

3

SPH - M. SPL - (M+1)
1 X-1-SP

Stack Pntr - Index Reg

TSX

30

3

1 SP+1-X

3

Add

ABX

3A

Push Data

PSHX

3C

3 1 B+X- X
4 1 XL .... M.... SP -1 - SP

Pull Data

PULX

3B

5 1 SP + 1 - SP. M... - XH

XH'-' Mop. SP - 1 - SP
SP+1-SP.M....... XL
The Condition Code Register notes are listed after Table 10•

64

•

HITACHI

Condition Code
Register

5 4 3 2 t 0
I N Z V C

H

• •

t t

t t

• •• t
• •••
• • • t
••••

••

•
•

•
•

• 0 t
• (j) t
• 7 t
• 7 t

• • •
•• •
•• •
• • •
•• •

•
•
•
•
•

• •
• •

• •
•
R •
R •
R •
••
••
• •
• •
• •
R

------------------------------------------------------HD6B01S0,HD6B01S5
Table 9 Jump and Branch Instructions
Condition Code

Addressing Modes
Operations

Branch Always
Branch Never

Branch If Carry Claar
Branch If Carry Set
Branch If = Zero
Branch If .. Zero
Branch If > Zero

Mnemonic

BRA
BRN

RELATIVE
OP
20

BCC

21
24

BCS
BEO

25
27

BGE

2C
2E

Branch If Higher

BGT
BHI

Branch If .. Zer6
Branch If lower Or
Same

-

#
3 2
3 2
3 2

INDEX
DIRECT
OP
# OP
#

-

-

Register

EXTND
OP

-

Branch Test

IMPLIED
# OP

-

#
None

C=O

3 2

C=1

3 2
3 2

Z=1

3 2

Z + (N <±l VI

~

0

3 2

~

1

N<±lV~O

BlE

3 2

C+Z=O
Z + (N <±l VI

BlS

23

3 2

C+ Z

BlT
BMI

20
2B

3 2
3 2

N <±l V~ 1
N~ 1

Branch If Not Equal
Zero

BNE

26

3 2

Z~O

Branch If Overflow
Clear

BVC

28

3 2

VeO

Branch If Overflow Set

8VS

29

3 2

V~

Branch If Plus

BPl

2A

N=O

Branch To Subroutine

80

Jump

BSR
JMP

3 2
6 2

Jump To Subroutine

JSR

No OparMlon

NOP

01

Branch If Minus

·• •• ·• •• •• ••
• ·· • • •
• • • • • •
·• •• •• ·• •• ••
• · • • ··
• • • • • •
• • • • • •
• • • • • ·
• • • • • •

None

22
2F

Branch If < Zero

5 4 3 2 1 0
H I N Z V C

6E
90

5 2

~

1

• • •
• • •
• •- •
• • •
• • •
• • •

1

3 2 7E 3 3
2 BD 6 3

AD 6

2 1

Rlturn From Interrupt

RTI

3B 10 1

Return From
Subroutine

RTS

39

Softwere Interrupt

SWI

3F 12 1

Welt for Interrupt

WAI

3E

5

Advances Prog. Cntr.
Only

I

9 I

• • •
• • •
•• •

•••
• ••
• • •
• •• •••
• •• • ••
• •• •••
-- @:i• •• •••
• S• •••
• ®. • • •

Table10 Condition Code Register Manipulation Instructions
!Addre.. ingModes
Operations

Mnemonic

OP
el"r Clrry
CI"r Intlrrupt Malk
.CI"r Overflow

-

IMPLIED

ClC
Cli

OC
OE
OA

Sat Carry

ClV
SEC

Sat Intlrrupt Malk

SEI

Sat Overflow
Accumulator A .... CCR

SEV
TAP

OF
OB

CCR .... Accumu lator A

TPA

00

06
07

2
2
2
2
2
2
2
2

Condition Code Register
Boolean Operation

#
1
1

O .... C
0 .... 1

1

0 .... V

1

1 ... C

I
I
1
I

1 ... 1
1 .... V
A .... CCR
CCR"'A

5

4

3

H

I

N

2
Z

1

0

V

C

• • • • • R
• R • • • •
• • • • R •

• • • • • S
• S • • • •
• • • • S •
---~ g ) - • • • • • •

Condition Code Raglstar Notas: (Bit set It tast Is true and claared otherwlsa)

 PC

lIIMI
:SVVI

I TAO;
ICF
OCF
TOF
SCI

FFFC FFFO
~':FA FFFB
F F F8 F F F9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFFI

I

Non-Maskable Interrupt
Softvvere Interrupt
Ma.kable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt CTORE + RDRF + ORFE)

::I:

o

en

00

o

~

::I:

A

oen

00

o
....

~

Figure 24 Interrupt Flowchart

(/)

U1

HD6801S0,HD6801S5---------------------------------------------------Vee

Vee

Enable

Enable

KiM!
Port 3
8 Transfer

lmes
Port 1

Port'

B I/O

81/0 Lmes

Lines

Port 4
8110 Unes

Port 2
L..._....._ _..J~I""".., 51,0 LInts
SCI

Port 4

Port 2

SilO Lines .,..-.,.I_--r--.J'I'-'" 8110 Lines
SCI
Vss

Vss

Figure 25 HD6BOl S MCU Single-Chip Dual Processor Configuration

HD6801 5

MCU

Address

Bus

Data
Bus

Figure 26 HD6BOl S MCU Expanded Non-Multiplexed Mode

Addr.ss Bus

Data Bus

Figure 27 HD6BOl S MCU Expanded Multiplexed Mode

74

•

HITACHI

HD6801VO,HD6801V5

Me U (Microcomputer
The HD6801V MCU is an 8-bit microcomputer system which
is compatible with the HD6801S except the ROM size. The
HD6801V MCU is object code compatible with the HD6800
with improved execution times of key instructions plus several
new 16-bit and 8-bit instructions including an 8x8 unsigned
multiply with H)-bit result. The HD680lV MCU can operate as
a single chip microcomputer or be expanded to 65k words. The
HD6801V MCU is TIL compatible and requires one +5.0 volt
power supply. The HD6801V MCU has 4k bytes of ROM and
128 bytes of RAM on chip. Serial Communications interface
(SCI). and parallel I/O as well as a three function 16-bit timer.
Features and Block diagram of the HD6801V include the
following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•

FEATURES
Expanded HMCS6800 Instruction Set
8 x 8 Multiply
On-Chip Serial Communications Interface (SCI)
Object Code Compatible With The HD6800 MPU
16-Bit Timer
Single Chip Or Expandable To 65k Words
4k Bytes Of ROM
128 Bytes Of RAM (64 Bytes Retainable On Power
Down)
29 Parallel I/O lines And 2 Handshake Control lines
Internal Clock/Divided-By-Four Circuitry
TTL Compatible Inputs And Outputs
Interrupt Capability
Compatible with MC6801 (except ROM size)

Unit)
HD6801VOP
HD6801V5P

(DP·40)

• PIN ARRANGEMENT
0

sc,
sc,
P"
Pn
P"
P"
P"
P"

HD6801V

P"
P"
P"n

P"
P"
p ..

• BLOCK DIAGRAM

P"
p ..
P"

(Top View)

•

TYPE OF PRODUCTS

MCU

§

Bus Timing

HD6801VO

1 MHz

HD6801V5

1.25 MHz

PIO

~:;

PI!

~::
I---~::

_HITACHI

75

HD6801VO,HD6801V5----------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage

Vee
Vin

Input Voltage
Operating Temperature
Storage Temperature
• With

re~pect to

[NOTE]

.

Symbol

Value
-0.3-+7.0

•

Unit
V
V
°c
°c

-0.3 - +7.0
0 -+70
- 55-+150

Topr
TBIg

Vss (SYSTEM GND)

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating

conditions. If these conditions are exceaded, it could affect reliability of LSI.

•

ELECTRICAL CHARACTERISTICS

• DC CHARACTERISTICS (Vee "'S.OV±S%, Vss

z

Item

OV, Ta" 0- +70°C, unless otherwise noted.)
Symbol

RES
Other Inputs·

VIH

Input "Low" Voltage

EXTAL
Other Inputs·

VIL

Input Load Current

P40 - P47
SCI
EXTAL

Illnl

NMI, IRQ" RES

Ili"1

Input "High" Voltage

"

Input Leakage Current
Three State (Offset)
Leakage Current
Output "High" Voltage

P IO
Pao

-

P 17 , Poo - P37
Pa4

IITSd

P30 - P 37
P40 - P47 , E, SCI, SCa
Other Outputs
All Outputs

Output "Low" Voltage
Darlington Drive Current PIO
Power Dissipation

-

V OH
VOL
-loH

P 17

Test Condition

Input Capacitance
Vee Standby

Powerdown
Operating

VSBB
VSB

Standby Current

Powerdown

ISBB

-

P47 , SC,

Cin

-

-

VI" = 0- 2.4V
Vi" = 0- Vee
VI" = 0 - 5.25V
VI" = 0.5 - 2.4V

-

I LOAD = -205 !LA
I LOAD =-145 !LA
I LOAD =-100 !LA
I LOAD = 1.6 mA

2.4
2.4

Vou;
Vi"

= 1.5V

f

=OV, Ta =25°C,

= 1.0 MHz

eHITACHI

-

1.0

-

-

-

2.4

-

4.75

VSBB =4.0 V

-

-

4.0

·Except Mode Programming Levels.

76

typ

-0.3

Po

P30 - P37 , P40
Other Inputs

min
4.0
2.0
-0.3

-

-

max
Vee

Unit
V

Vee
0.6
0.8
0.5
0.8
1.2
2.5
10
100

0.5
10.0
1200
12.5
10.0
5.25
5.25
8.0

V

mA
!LA
!LA
V
V
mA
mW
pF
V
mA

------------------------------------------------------HD6801VO,HD6801V5
• AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V±5%, Vss

=OV, Ta'" 0 -

+70°C, unless otherwise noted.)

Symbol

Item

Test Condition

min

HD6B01VO
max
tvp

min

HD6B01V5
typ
max

Unit

10

O.B

/J.s

150

-

10

-

-

ns

5

-

50

5

-

50

ns

tAS!

5

-

50

5

-

50

ns

Address Strobe Delay Time

tASO

60

-

30

-

-

ns

Enable Rise Time

tE,

5

50

5

-

50

ns

Enable Fall Time

tEl

5

50

5

ns

PWEH

450

340

-

ns

Enable Pulse Width "Low" Time

PWec

450

-

ns

Address Strobe to Enable Delay Time

tASEO

60

-

-

ns

Address Delay Time

tAD

Fig. 1

-

260

ns

tADL

Fig. 2

-

-

260

Address Delay Time for Latch

-

260

ns

Data Set-up Write Time

tosw

225

-

ns

tOSR

BO

80

tHR

10

10

-

Write

tHw

20

-

20

-

Address Set-up Time for Latch

tASL

60

tAHL

20

-

20

Address Hold Time

tAH

20

-

50

Address Hold Time for Latch

-

20

-

-

ns

Read

-

115

Data Set-up Read Time

-

-

50

Enable Pulse Width "High" Time

-

1

Cycle Time

tcyc

Address Strobe Pulse Width "High"

PW ASH

Address Strobe Rise Time

tASr

Address Strobe Fall Time

Data Hold Time

Peripheral Read
Access Time

I
I

I
I

Non-Multiplexed Bus

(tACCN)

Multiplexed Bus

(tACCM)

200

-

Oscillator stabilization Time

tRC

Fig. 10

100

Processor Control Set-up Time

tpcs

Fig. 11

200

270

(610)
(600)

350
30

-

-

100

-

200

ns
ns
ns
ns

(410)

ns

(410)

-

ms
ns

PERIPHERAL PORT TIMING (Vee = 5_0V ±5%, Vss = OV, Ta'" 0 - +70°C, unless otherwise noted.)
Item
Peripheral Data Setup Time
Port 1, 2,3,4
Peripheral Data Hold Time
Port 1, 2, 3, 4
Delay Time, Enable Positive Transition
to 053 Negative Transition
Delay Time, Enable Positive Transition
to 053 Positive Transition
Delay Time, Enable Negative
Transition to Peripheral Data Port 1, 2·,3,4
Valid
Delay Time, Enable Negative
*
Port 2**, 4
Transition to Peripheral
CMOS Data Valid
Input Strobe Pulse Width
Input Data Hold Time
port 3
Input Data Sat-up Time
Port 3
·Except P"

Symbol

Test Condition

min

typ

max

Unit

tposu
tpOH

Fig. 3
Fig. 3

200
200

-

ns
ns

tOSOl

Fig. 5

-

-

350

ns

toso2

Fig. 5

-

-

350

ns

tpwo

Fig. 4

-

-

400

ns

teMo s

Fig.4

-

2.0

liS

tPWIS

Fig. 6

200

tlH
tiS

Fig. 6
Fig. 6

50
20

-

-

ns
ns
ns

··10kn pull up register required for Port 2

•

HITACHI

77

HD6801VO,HD6801V5-----------------------------------------------------TIMER, SCI TIMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
Item

Symbol

Timer Input Pulse Width
Delay Time, Enable Positive Transition to
Timer Out
SCI Input Clock Cycle
SCI Input Clock Pulse Width

=OV. Ta =0 -

Mode Programming
Hold Time

.1 m

max

-

600

-

-

tcyc

0.6

tScYc

max
1.7

Unit

-

V
tcye
tcye

1

0.4

min

typ

VMPL

-

-

VMPH
PW RSTL

4.0
3.0

-

Test Condition

Fig. 8

-

2.0

tMPs
Rise Time 21#s
Rise Time < 1115

0

tMPH

100

tcyo

2.2Y

Address Strobe
(ASI

V
--

-PWASH-

O.6Y

--

-tAS,

2.4
Enable
(El

y'

1--

IASO

\

I----

/

I\~
I-- tASt

1---

ASE< 1--,
PWeH

V

PWeL

O.SY

--

I----IAO~

\

--

I--tE'

.-tEt

~

(SC~

~

(Port41

Address Valid

'/

O.6Y

IASL---

~

+IAHL

!----106W-

,

2.2Y

MCU Write

Address

Do .... O,.A.-A,

Valid
O.6Y

(PorI 31

2.2Y

(PorI 31

\

,

!--IOSR-

I\ddress

Data Valid

I

\

O.BY

Figure 1 Expanded Multiplexed Bus Timing

•

I-

I-IHR

2.0Y

(tACCMl

78

10-1_

Data Valid

2.2Y
Valid
O.6Y

-

O.6Y

-IAOL-----

MCU Read
0.-0,. A.-A,

.-IAH

2.2Y

R/W, Ar-A.

Unit
ns
ns

+70°C. unless otherwise noted.)

Symbol

RES "Low" Pulse Width
Mode Programming Set-up Time

typ

-

Fig. 7

tScYC
tpwsCK

Item
Mode Programming Input "Low" Voltage
Mode Programming Input "High" Voltage

min
2tcyc+2OO

tTOD

MODE PROGRAMMING (Vee - 5.0V ±5%. Vss

I RES

Test Condition

tpWT

HITACHI

1/

V

ns

-----------------------------------------------------HD6801VO,HD6801V5
I.

Enable

tcyc

2~

IE)

r-

\

O.5V

-

I---'ADAc,:..A~Po •• 4)

2.2V

RNI ISC')
lOS ISC,)

O.6V

PWEH

/

PWEL

r-

-

1--,.,

\ rI-- 'EI

1-

r-'AH

-

r-'''''

Address Valid

-'DSW~

2.2V

MCUWr ite

Data Valid

OD-O,
0.6V

IPo •• 3)
I·ACCN)

2.0V

MCU Read

.r--'OSR- --

~'HR

Data Vahd

0 0 -0,

O.BV

IPort3)

Figure 2 Expanded Non-Multiplexed Bus Timing

rMCUWrite
rMCURead

EnabIB(E)~
0.5V

EnabIB(E)

'.. -'.,
-'24
PH

'40 -

tCMOS1JtpwD

2.0V
O.BV

•

All Data
Port Outputl _ _ _ _ _ _ _- J

'41

Inputs

'10Inputs·
-'n

- - - - 0.1 Vee

~::~

Data Valid

(Note)

1. 10 kfl Pullup .esisto. required for Port 2 to reach 0.7 Vee

i: ~:r~ 1~~:~e;:!Ued

·Port 3 Non-Latched Operation (LATCH ENABLE = 0)

Figure 3 Data Set-up and Hold Times
(MCU Read)

above

Vee

Figure 4 Port Data Delay Timing
(MCUWrite)

rMCU access of Port 3*
Enable(E)

~nu------~,--~----~,-~-----

aus

Pso -'n

OS3 - - - - - - - -....

Inputs

• Access matches Output Strobe Select (OSS = 0, a read;

OSS = I, a wri.e)

Figure 5 Port 3 Output Strobe Timing
(Single Chip Mode)

Figure 6 Port 3 Latch Timing
(Single Chip Mode)

•

HITACHI

79

HD6801VO,HD6801V5-----------------------------------------------------

Enable

(E)

Tnner

----...J'--F=::..,.-J '-___

Count..

P"

Output

Figure 8 Mode Programming Timing
Figure 7 Timer Output Timing

Teot Po,nt

.1

0-----

m
Vee

AL02.2kO

Test POint

30pF

t5207'

®

or Equlv.

C

(a) CMOS Load

A

(b) TTL Load

Figure 9 Bus Timing Test Loads

LI~,tnI1""c'lon_1

. I .. I·,! .. ! .. I·,·!·"I·,,!

..

Cycle

In'l,n.1

Add"I' BIII-"-......'Io..-""'O....."""'=' ' 'O."''c.....
o.oo''-''••'''n..I.A.......'n"'.'.,I,~••""'n...'.., ""....'-n.'".I,..,S..
PI-n.....,"'......."~......,A......."""V...,,..o,.J'\..V.......O'.J'\.,,N_
....PC~-Addr

Addr

MSI Add,

LSI Addr Addrl"

i'RO l
MMlaIIRO~----~\\1-

_________________________________________________

~~"CS

'1'1'1'1'1,1 A/W - - - - - - - - - - - - - , . \...__________________________J

• 'iRCr, ..• Internal

Interrupt

Figure 10 Interrupt Sequence

E

~\\\\\\\\\\\\\\~ M%\\\\\\\\\\\\

L.f"l.f4 ~HflIl.1l-.J

+':;";.V_ _ _-IIII'-_ _ _ _ _ _ _ _ _ _-Ill

~

~

- L !-...,.

Vee 11o-_"'_'V________ .""

-d 1-."",

illS __________11 ..._________________....., ~ •.dV

·'~~
•.•:::v:.----------

J;,~':=: M\\\\§\\\\\\\\\\\\1 ,§§\\\\S\§\\\SM§\\\\§S«:: ~
pc:x:Jc
PC8-PC15PCO"'PC7 flnl
Instruction

Figure 11 Resat Timing

80

•

HITACHI

-----------------------------------------------------HD6801VO,HD6801V5
•

SIGNAL DESCRIPTIONS

•

Vee andVss

•

XT AL and EXT AL

•

These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts t5%.

These connections are for a parallel resonant fundamental
crystal, AT cut. Divide by 4 circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at I MHz. The divide by 4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non-time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. EXTAL may
be driven by an external TTL compatible clock source with a
50% (tlO%) duty cycle. It will divide by 4 any frequency less
than or equal to 5 MHz. XT AL must be grounded if an external
clock is used. The following are the recommended crystal parameters:
Nominal Crystal Parameter

~

4MHz

5 MHz

Co

7 pF max.

4.7 pF max.

Rs

son max.

30n

Item

XTAl~--~------,

C L1 =CL2 =22pF ± 20%
(3.2 - 5MHz)

CJ

(Note1 These are representative
AT cut parallel resonance
crystal parameters.

EXT Al 1----...- ,

tL2

Jr

CL1

Figure 12 Crystal Interface
•

Vee Standby

This pin will supply +S volts ±S% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
VSBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
I) Write "0" into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
Vee Standby

•

iPowerLine
Jr

Figure 13 Battery Backup for Vee Standby

•

Enable (E)

This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL load and 90 pF.
•

typo

Reset (RES)

This input is used to reset and start the CPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low" must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the MCU does the following:
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits 2, I, and 0 are latched into programmed
control bits PC2, PCI and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cleared before the
CPU can recognize maskable interrupts.

Non-Maskable Interrupt (NMII

A low-going edge on this input requests that a non-maskableinterrupt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
hasnoefrectonNMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these locations causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kn external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQl and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.
•

Interrupt Request II RO l

)

This level sensitiv~ input requests that an interrupt sequence
be generated within the machine. The processor will wait until it
completes the current instruction that it being executed before
it recognizes the request. At that time, if the interrupt mask bit
in the Condition Code Register is not set, the'm~chine will begin
an interrupt sequence. The Index Register, Progr.am Counter,
Accumulators, and Condition Code Register are stored on the
stack. Next the CPU will respond to the interrupt request by
setting the interrupt mask bit "High" so that no further maskable interrupts may occur. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address which is
located in memory locations $FFF8 and $FFF9. An address
loaded at these locations causes the CPU to branch to an interrupt routine in memory.
The IRQ. requires a 3.3 kn external resister to Vee which
should be used for wire-OR and optimum control of int~ts.
Internal Interrupts will use an internal interrupt line (IRQ2)'
This interrupt will operate the same as IRQ. except that it will
use the vector address of $FFFO through $FFF7. IRQ. will
have priority over IRQ2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table I) .

HITACHI

81

HD6801VO,HD6801V5--------------------------------------------------Table 1 Interrupt Vector Location
Vector
Highest
Priority

Lowest
Priority

MSB

LSB

FFFE

FFFF

FFFC

FFFD

FFFA

FFFB

• PORTS
There are four I/O ports on the HD6S0 IV MCU; three 8-bit
ports and one S·bit port. There are two control lines associated
with one of the 8-bit ports. Each port has an associated write
only Data Direction Register which allows each I/O line to be
progranuned to act as an input or an output *. A "I" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
four ports: Port 1, Port 2, Port 3, and Port 4. Their addresses
and the addresses of their Data Direction registers are given in
Table 2.

Interrupt
RES
NMI
Software Interrupt (SWII

FFF8

FFF9

IRQ, (or 153)

FFF6

FFF7

ICF (Input Capture)

FFF4

FFF5

OCF (Output Compare)

FFF2

FFF3

TOF (Timer Overflow)

FFFO

FFFl

SCI (RORF + ORFE + TORE)

*

The only exception is bit 1 of Port 2, which can either be data
input or Timer output.

Table 2 Port and Data Direction Register Addresses

The following pins are available in the Single Chip Mode, and
are associated with Port 3 only.
• Input Strobe (lS3) (SCI)
The function of the IS3 signal depends on the I/O Port 3
Control/Status Register. If IS3 Enable bit is set, an interrupt
will occur by the fall of the IS3 signal. If the latch enable bit is
set, the data in the I/O Port 3 will be latched at the I/O Port 3
Data Register. The timing condition of the IS3 signal that is
necessary to be latched the input data normally is shown in
Figure 6.
• Output Strobe (0S3) (SC2 )
This signal is used by the processor to strobe an external
device, indicating valid data is on the I/O pins. The timing for
the Output Strobe is shown in Figure 5 I/O Port 3 Control/
Status Register is discussed in the following section.

The following pins are available in the Expanded Modes.
• Read/Write (R/W) (SC2)
This TTL compatible output signals the peripherals and
memory· devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signa1is
Read ("High"). This output is capable of driving one TTL load
and 90pF.
• I/O Strobe (K)S) (SCI)
In the expanded non·multiplexed mode of operation, lOS
internally decodes Ag through AI5 as zero's and A8 as a one.
This allows external access of the 256 locations from $0100 to
$0 I FF. The timing diagrams are shown as figure 2.
• Addr... Strobe (AS) (SC,)
In the expanded multiplexed mode of operation address
strobe is output on this pin. This signal is used to latch the S
LSB.'s of address which are multiplexed with data on Port 3. An
S-blt latch is utilized in conjunction with Address Strobe as
shown. in figure 19. Expanded Multiplexed Mode. Add;ess
Strobe signals the latch when it is time to latch the address lines
so the lines can become data bus lines during the E pulse. The
timing for this singal is shown in Figure I of Bus Timing. This
signal Is also used to disable the address from the multiplexed
bus allowing a deselect time, tASD before the data is enabled to
the bus.

Port Address

Register Address

I/O Port 1

$0002

$0000

I/O Port 2

$0003

$0001

I/O Port 3

$0006

$0004

I/O Port 4

$0007

$0005

• I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three·state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "1" and less than 0.8 V for a logic "0". As out·
puts these lines are TTL compatible and may also be used as
a source of up to I mA at 1.5 V to directly drive a Darlington
base. After Reset, the I/O lines are configured as inputs. In all
three modes, Port 1 is always parallel I/O.

• I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "1" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pins 10, 9, and 8 of the chip) are used
to program the mode of operation during reset. The values of
these pins at reset are latched into the three MSB's (bits 7, 6,
and 5) of Port 2 which are read only. This is explained in the
Mode Selection Section.
In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the
Timer. Bit I is the only pin restricted to data input or Timer
output.
• I/O Port 3
This is an S·bit port that can be configured as I/O, a data bus,
or an address bus multiplexed with the data bus - depending on
the mode of operation hardware progranuned by the user at
reset. As a data bus, Port 3 is bi·directional. As an input for
peripherals, it must be supplied regular TTL levels, that is,
greater than 2.0 V for a logic "I" and less than 0.8 V for a logic

"0" .

82

•

Data Direction

Ports

HITACHI

-----------------------------------------------------HD6801VO,HD6801V5
Its TTL compatible three-state output buffers are capable of
driving one TTL load and 90 pF_ln the Expanded Modes, after
reset, the data direction register is inhibited and data flow
depends on the state of the R/W line_ The input strobe (IS3)
and the output strobe (OS3) used for handshaking are explained
later_
In the three modes, Port 3 assumes the following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register_ There are two control
lines associated with this port in this mode, an input strobe and
an output strobe, that can be used for handshaking_ They are
controlled by the I/O Port 3 Control/Status Registp.r explained
at the end of this section. Three options of Port 3 operations
are sumarized as follows: (I) Port 3 input data can be latched
using IS3 (SC,) as a control signal, (2) OS3 can be generated by
either an CPU read or write to Port 3's Data Register, and (3)
and IRQ, interrupt can be enabled by an IS3 negative edge.
Port 3 latch and strobe timing is shown in Fig. 5 and Fig. 6.
Expanded Non-Multiplexed Mode: In this mode, Port 3
becomes the data bus (Do -0 7 ).
Expanded Multiplexed Mode: In this mode, Port 3 becomes
both the data bus (Do -0 7 ) and lower bits of the address bus
(Ao-A7). An address strobe output is true when the address is
on the port.

load and 90 pF. After reset, the lines are configured as inputs.
To use the pins as addresses, therefore, they should be
programmed as outputs. In the three modes, Port 4 assumes the
following characteristics:
Single Chip Mode: Parallel Inputs/Outputs as programmed by
its associated Data Direction Register.
Expanded Non-Multiplexed Mode: In this mode, Port 4 is
configured as the lower order address lines (Ao - A7 ) by writing
one's to the data direction register. When all eight address lines
are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
Expanded MUltiplexed Mode: In this mode, Port 4 is
configured as/ the higher order address lines (As -AI 5) by writing one's to the data direction register. When all eight address
lines are not needed, the remaining lines, starting with the most
significant bit, may be used as I/O (inputs only).
•

OPERATION MODES

The mode of operation that HD680 I V will operate in after
Reset is determined by hardware that the user must wire on pins
10,9, and 8 of the chip. These pins are the three LSB's (I/O 2,
I/O 1, and I/O 0 respectively) of Port 2. They are latched into
programmed control bits Pe2, Pel, and PeO when reset goes
high. I/O Port 2 Register is shown below.
PORT 2 DATA REGISTER

76543210
I/O PORT 3 COt.!TROL/STATUS REGISTER

153

$OOOF

Bit 0;
Bit I;
Bit 2;
Bit 3;

Bit 4;

Bit 5;
Bit 6;
Bit 7;

•

FLAG

6

5

4

3

2

153

X

a55

LATCH

x

o
X

X

IRQ,

ENABLE

$0003 r--PC-2~I-p-C-,TI-p-C-o~I-I-IO--4~Irl-IO--3~,I-I-la--2~1~I/O--l-lrl-la--0-'

ENABLE

Not used.
Not used.
Not used.
LATCH ENABLE. This controls the input latch for I/O
Port 3. If this bit is set "High" the input data will be
latched with the falling edge of the Input Strobe, IS3.
This bit is cleared by reset, and the latch is "reoOpened"
with CPU read Port 3.
ass. (Output Strobe Select) This bit will select if the
Output Strobe should be generated at OS3 (SC 2 ) by a
write to I/O Port 3 or a read ofl/O Port 3. When this bit
is cleared the strobe is generated by a read Port 3. When
this bit is set the strobe is generated by a write Port 3.
Not used.
IS3 IRQI ENABLE. When set, interrupt will be enabled
whenever IS3 FLAG is set; when clear, interrupt is
inhibited. This bit is cleared by RES.
IS3 FLAG. This is a read only status bit that is set by
the falling edge of the input strobe, IS3 (SC,). It is
cleared by a read of the Control/Status Register followed by a read or write of I/O Port 3. Reset will clear
this bit.

I/O Port 4

This is an 8-bit port that can be configured as I/O or as
address lines depending on the mode of operation. In order to
be read properly, the voltage on the input lines must be greater
than 2.0 V for a logic "I" and less than 0.8 V for a logic "0".
As outputs, each line is TTL compatible and can drive I TTL

An example of external hardware that could be used for
Mode Selection is shown in Fig 14. The HDI4053B provides
the isolation between the peripheral device and MCU dming
Reset, which is necessary if data conflict can occur between
peripheral device and Mode generation circuit.
As bits 5, 6 and 7 of Port 2 are read only, the mode cannot
be changed through software. The mode selections are shown in
Table 3.
The HD6801V is capable of operating in three basic modes;
(I) Single Chip Mode, (2) Expanded Multiplexed Mode (compatible with HMCS6800 peripheral family) (3) Expanded NonMultiplexed Mode.
•

Single Chip Mode

In the Single Chip Mode the Ports are configured for I/O.
This is shown in Figure 16 the single Chip Mode. In this
mode, Port 3 will have two associated, control lines, an input
strobe and an output strobe for handshaking data.
•

Expanded Non-Multiplexed Mode

In this mode the HD680IV will directly address HMCS6800
peripherals with no external logic. In this mode Port 3 becomes
the data bus. Port 4 becomes the Ao-A 7 address bus or partial
address and I/O (inputs only). Port 2 can be parallel I/O, serial
I/O, Timer, or any combination of them. Port I is parallel I/O
only. In this mode the HD6801V is expandable to 256 locations. The eig\1t address lines associated with Port 4 may be
substituted for I/O (inputs only) if a fewer number of address
lines will satisfy the application (See Figure 17).

eHITACHI

83

HD6801VO,HD6801V5-----------------------------------------------------Vee
(

•

R

RI RI RI
6

TT T

A B C
X.

p,.
P"

XI
YI

P"

ZI
C

I

???
~

Mode
Control
Switch

H06801V
8

X

Y.

...-- z.

RES

9

Y

10

Z

p,. (PCO)
P" (PC1)
P" (PC2)

HOI4053B

Inh

.~

[NOTES]

1) Mode 7 as shown
2) RC .. Reset time constant
3) RI =10kfl

Figure 14 Recommended Circuit for Mode Selection
Truth Table
Control Input

Inh
A
B

Binary to 1-of-2
Decoder with
Inhibit

C

Inhibit

xoo---------------~~~~-+--­
X,o-----------------~~~-+--J

yoo------------------R~+-~-.

y,o-------------------~~-+~
Zoo---------------------~~~
Z,o-----------------------~~J

x
y
Z

Select

On Switch

C B A H014053B

0

0 0 0

Z. Yo X,

0

0 0 1

Z. Yo XI

0

0 1 0

Zo YI Xo

0

0

1 1

Zo VI XI

0

1 0 0

ZI Yo Xo

0

1 0 1

ZI Yo 'XI

0

1 1 0

ZI YI Xo

0

1 1 1

ZI YI XI

1

X X X

-

Figure 15 HD14053B Multiplexers/Demultiplexers

Vec

Vee
2

7

40

Port 1

Port 3

8110 Line.

81/0 Line.

Port 4
8110 Line.

Port 2
5 I/O Line.
SCI

Vss

Port 1

Port 3

8 P.re"el 110

8 Data Lines

Port 2
5 P.r."el I/O
SCI

Port 4
To 8 Address

Timer

Timer

Vss

Figure 16 HD6801V MCU Single-Chip Mode
84

Enable

=

Enable

Lines or To
8110 Line.
(Input. On IV)

Figure 17 HD6801V MCU Expanded Non-Multiplexed Mode
•

HITACHI

------------------------------------------------------HD6801VO,HD6801V5
•

Expanded Multiplexed Mode

Vee

In this mode Port 4 becomes higher order address lines with
an alternative of substituting some of the address lines for I/O
(inputs only). Port 3 is the data bus multiplexed with the lower
order address lines differentiated by an output called Address
Strobe. Port 2 is 5 lines of Parallel I/O, SCI, Timer, or any
combination of them. Port I is 8 Parallel I/O lines. In this mode
it is expandable to 65k words. (See Figure 18).
•

Enable

Lower order Address Bus Latches

Since the data bus is multipfexed with the lower order
address bus in Port 3, latches are required to latch those address
bits. The 74LS373 Transparent octal D-type latch can be used
with the HD680 I V to latch the least significant address byte.
Figure 19 shows how to connect the latch to the HD6801V.
The output control to the 74LS373 may be connected to
ground.

Port 1

8 Lines

8 I/O Lines

Multiplexed

Data/Address
Port 2
51/0 Lines
SCI

Port 4
To 8 Address
lines or To
8 I/O Lines
(Inputs Only)

Timer

Vss

Figure 18 HD6801V MCU Expanded Multiplexed Mode

GND
AS

I

G OC
0,

Port 3
Address/Data

[

l""'~'

Q,

74LS373

0,

Q,

........

Function Table
Output
Control

A. -A,

L
L
L

1,,,. '.-',

H

G

0

Output
Q

H
H

H

H

L
X
X

L
Q,
Z

Enable

L
X

Figure 19 Latch Connection
•

Mode and Port Summary MCU Signal Description

This section gives a description of the MCU signals for the various modes. SCI and SC2 are signals which vary with the mode
that the chip is in.
MODE
SINGLE CHIP

PORT 1
Eight Lines

PORT 2
Five Lines

I/O

PORT 3
Eight Lines

PORT4
Eight Lines

SCI

SC2

I/O

I/O

I/O

IS3 (I)

OS3(0)

ADDRESS BUS'
(As-A Is )

AS(O)

R!W(O)

ADDRESS BUS'
(Ao-A 7 )

10S(0)

R/W(O)

EXPANDED MUX

I/O

I/O

ADDRESS BUS
(An-A 7 )
DATA BUS
(Do-D 7 )

EXPANDED NON-MUX

I/O

I/O

DATA BUS
(0 0 -0 7 )

*These lines can be substituted for I/O (Input Onlv) starting with the most significant address line.
I = Input
~= Input Strobe
SC = Strobe Control
o = Output
OS3 = Output Strobe
AS = Address Strobe
lOS = I/O Select
R/W = Read/Write

•

HITACHI

85

HD6801VO,HD6801V5--------------------------------------------------___
Table 3 Mode Selection Summary
Mode

P"
(PC2)

(~t'1)

(~c'b)

7
6
5
4

H
H
H
H

H
H
L
L

H
L
H

3
2

L
L

H
H

1

L
L

L

L
H

L

L

0

L
H

LEGEND:
I -Interna'
E - External
MUX - Multiplexed
NMUX - Non.Multlplexed
L - logic "0"
H - L.ogic "1"

Interrupt
Vectors

I

I

I

I

I

I

I
1(2)

I
1(1)

I
I
I

NMUX(61

E
E

E

E

MUX

Multiplexed/No RAM & ROM

E

MUX

I

I
I

I

I

E
1(3)

MUX
MUX

Multiplexed/RAM
Multiplexed/RAM & ROM
Multiplexed Test

MUX(61
I

• INTERRUPT FLOWCHART

The Interrupt flowchart is depicted in Figure 24 and is com·
man to every interrupt excluding reset.

Table 4 Internal Register Area
Ragistar
Port 1 Data Direction Raglstar-'-

Addra•• '

00

Port 1 Data Ragister
Port 2 Data Register

01
02
03

Port 3 Data Direction Register·"''''
Port 4 Data Direction Register***

05**

Port 2 Data Direction Register*"'*

04-

Port 3 Data Register
Port 4 Data Register

06-

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compere Register (High Byte)

08

Output Compere Register (Low Byte)
Input Capture Register (High Bytel
Input Capture Ragister (Low Byte)
Port 3 Control and Stetus Register

OC
00
OE
OF"

Rate and Mode Control Register
Transmit/Recaive Control and Status Register
Receive Data Regi.tar
Transmit Data Registar

10
11
12
13

07**

09
OA
OB

14
lEi·1F

• External addre•• In ModaLl!. " 2. 3. 6. 6; cannot be
acceDed In Mode Ii (No. lOS)
•• External addre.... In Mod.. O. '. 2. 3
••• , -Output. 0-1 nput·

86

Mode
Single Chip
Multiplexed/Partial Decode
Non·Multiplexed/Partial Decode
Single Chip Test

[NOTES]
1) Internal RAM is addressed at $XX80
2) Internal ROM is disabled
3) RES vector is e.ternal for 2 cycles after RES goas "High"
4) Addresses .ssociated with Port. 3 and 4 are considered axtarnal in Modes 0,
1,2,and3
5) Add".... a.sociat.d with Port 3 are considered external In Mode. Ii and 6
6) Port 4 default I, u.ar data input; addr... output is optional by writing to Port 4
Data Oiractlon Raglater

The MCU can provide up to 6Sk byte address space depend·
ing on the operating mode. A memory map for each operating
mode Is shown In Figure 20. The first 32 locations of each map
are reserved for the MCV's Internal register area, as shoWI) In
Table 4. With exceptions as indicated.

Reserved

Operating

RAM

• MEMORY MAPS

RAM Control Ragistar

Bus
Mode

ROM

•

HITACHI

-----------------------------------------------------HD6801VO,HD6801V5

HD6801V
Mode

o

HD6801V
Mode

Multiplexed Test mode

1

Multiplexed/RAM & ROM

$0000(1)

$0000(1)
Internal Registers

Internal Registers

$001F
External Memory Space

$0080

~~~~~j

External Memory Space

$0080
Internal RAM

Internal RAM

External Memory Space
External Memory Space

$FOOO 17J;=m::>~~1

Internal ROM
$FFEF

Internal ROM

VhYhVhV~lj'A

$FFFO
$FFFF(2)u.::===.... •

Internal Interrupt Vectors(2

[NOTES]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and internal at all other
times.

External Interrupt Vectors

$FFFF .....- - -...

[NOTES]
1) Excludes the following addresses which may
be used externally: $04, $05. $06, $07 and
$OF.
2) Internal ROM addresses $FFFO to $FFFF are
not usable,

3) After 2 CPU cycles, there must be no over·
lapping of internal and external memory

spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal
ROM using an external Reset vector.

Figure 20 HD6801V Memory Maps

•

HITACHI

87

HD6801VO,HD6801V5---------------------------------------------------

HD6801V
Mode

2

HD6801V3
Mode

Multiplexed/RAM

Multiplexed/No RAM or ROM

$0000(1)

$0000(1)
) Internal Registers

Internel Registers

SOOlF

$OOlF
External Memory Space
$0080
Internel RAM

SOOFF

External Memory Spaca
External Memory Space

$FFFO 1-----1
SFFFF ....._ _ _.. ' External Interrupt Vectors
[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and

$FFFO 1-----1
$FFFF "-_ _.......

[NOTE]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and

$OF.

$OF.

Figure 20 HD6801V Memory Maps (Continued)

88

External Interrupt Vectors

•

HITACHI

-----------------------------------------------------HD6801VO,HD6801V5

HD6801V

HD6801V4
Mode

Mode

Single Chip Test

5

Non-Multiplexed/Partial Decode
$0000(1)

$0000
Internal Registers

} Interna' Registers

$00IF

$OOIF

$0080
Internal RAM
$OOFF
$0100
External Memory Space

$01 FF '---r--.l'

$FOOO

Internal ROM
Internal RAM
Internal Interrupt Vectors

[NOTES]
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without
having to assert RESET by writing a "'" into

the PCO bit of Port 2 Data Register.
3) Addresses As to AI5 are treated as "don't
cares" to decode internal RAM.

4) Internal RAM will appear at $XX80to $XXFF.

$FFFF

Internal Interrupt Vectors

[NOTES]
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF.
INo lOS)
2) This mode may be entered without going
through RES by using Mode 4 and subsequently writing a "1" into the PCO bit of
Port 2 Data Register.
3) Address lines A,-A, will not contain addresses until the Data Direction Register for Port 4

has been written with "1 's" in the appropriate
bits. These address lines will assert "l's" until
made outputs by writing the Data Direction

Register.

Figure 20 HD6801V Memory Maps (Continued)

•

HITACHI

89

HD6801VO,HD6801V5---------------------------------------------------

HD6801V7
Mode

HD6801V6
Mode
Multiplexed/Partial Decode
$0000(1)

$00IF

$0000

Internal Registers

$OOIF

} Intarnal Registers

External Memory Spece
$0080

$0080

Internal RAM

Internal RAM

$ooFF

$OOFF

Extarnal Mamory Space

$FOOO

$FOOO

$FFFF

Intarnal ROM

Internal ROM

Internal Interrupt Vectors

Inllrnal Interrupt Vectora

$FFFF

[NOTES)
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address linas A, -Au will not contain
addresses until the Data Direction Register for
Port 4 has been written with "1'1" in the
appropriate bits. These address linas will
assart "1 's" until made outputs by writing the
Data Direction Register.

Figure 20 HD6801 V Memory Maps (Continued)

90

• HITACHI

-----------------------------------------------------HD6801VO,HD6801V5
the output level register value will appear on the pin for Port 2
Bit 1. The values in the Output Compare Register and Output
level bit may then be changed to control the output level on the
next compare value. The Output Compare Register is set to
$FFFF during RES. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made.

• PROGRAMMABLE TIMER

The HD680lV contains an on-chip 16-bit programmable
timer which may be used to perform measurements on an input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
o
an 8-bit control and status register,
a 16·bit free running counter,
o
a 16-bit output compare register, and
a 16-bit input capture register
A block diagram of the timer registers is.shown in Figure 21.
• Free Running Counter ($OOO9:000A)
The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable). The counter value may be read by the CPU software at
any time. The counter is cleared to zero on RES and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the patt, but may be of value in some
applications.

•

• With Port 2 Bit 0 configured as an output and set to "1". the
external input will still be seen by the edge detect unit.

• Timer Control and Status Register (TCSR) ($0008)

The Timer Control and Status Register consists of an 8-bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read-only
timer status information and indicate that:
• a proper transition has taken place on the input pin with a
subsequent transfer of the current counter value to the
input capture register.
• a match has been found between the value in the free
running counter and the output compare register, and
• when $0000 is in the free running counter.
Each of the flags may be enabled onto the HD680lV internal
bus (IRQ2) with an individual Enable bit in the TCSR If the

• Output Compare Register ($OOOB:OOOC)

The Output Compare Register is a 16-bit read/write register
which is used to control an output waveform. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "I" (Output),

lAO,

Input Capture Register ($OOOD:OOOE)

The Input Capture Register is a 16-bit read-only register used
to store the current value of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR The Data
Direction Register bit for Port 2 Bit 0, should* be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.

HD6801V Internal 8us

...-_I::::;OE

Timer b~7:t:;:±;~::;::::;::::;::"'1..J:!l r

c:.~~O'IJrCFlO~C~F~TO~F~~rr=t!;!~1

Status
Aegister
$08

81t1

ODR

Port 2

Output Input

Figu re 21

Level

Edge

Bit 1
Port2

8itO
Port2

Block Diagram of Programmable Timer

eHITACHI

91

HD6801VO,HD6801V5----------------------------------------------~--Timer Control and Status Register
7

5

6

IICF I OCF

4

3

2

1

0

TOF I EICI I EOCI I ETOIIIEDG I OLVq $0008

I-bit in the HD6801V Condition Code Register has been cleared,
a priority vectored interrupt will occur corresponding to the flag
bites) set. A description for each bit follows:
Bit 0 OLVL Output Level - This value is clocked to the output
level register on a successful output compare. If
the OOR for Port 2 bit I is set, the value will
appear on the output pin.
Bit I IEDG Input Edge - This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The OOR for Port 2 Bit
o must be. clear for this function to operate. IEOG
= 0 Transfer takes place on a negative edge
("High"-to-"Low" transition).
IEOG = I Transfer takes place on a positive edge
("Low"-to-"High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for a
TOF interrupt; when clear the interrupt is inhibited.
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IRQ 2 to appear on the internal bus
for an output compare interrupt; when clear the
interrupt is inhibited.
Bit 4 EICI Enable Input Capture Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for
art input capture interrupt; when clear the interrupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains $FFFF. It is cleared by
a read of the TCSR (with TOE set) followed by an
CPU read of the Counter ($09).
Bit 6 OCF Output Compare Flag - This read-only bit is set
when a match is found between the output
compare register and the free running coullter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register ($OB or SOC).
Bit 7 ICF
Input Capture Flag - This read-only status bit is
set by a proper transition on the input; it is cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($00).

• SERIAL COMMUNICATIONS INTERFACE
The HD6~01V contains a full-duplex asynchronous serial
communications interface (SCI) on chip. The controller
comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same
data rate. Both transmitter and receiver communicate with the

CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the followin~ paragraphs.
• Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MCU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
''wakes-up'') for the next message. The "wake-up" is automatically triggered by a string of ten consecutive I's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.
• Programmable Options
The following features of the H0680 1V serial I/O section are
programmable:
• format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate - one of 4 per given CPU "'2 clock frequency or
external clock x8 input
• wake-up feature - enabled or disabled
• Interrupt requests _. enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Serial Communications Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 22. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addition to the four registers, the serial I/O section utilizes
bit 3 (serial input) and bit 4 (serial output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected .
Transmit/Receive Control and Status (TRCS) Register
The TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0-4 may be written. The
register is initialized to $20 on RES. The bits in the TRCS
register are defined as follows:

Transmit/Receive Control and Status Register

765432

0

LIR_D_R_FILo_R_F_E"\'I_T_D_R_E...II_R_1E.....II"--R_E--JIL-T_I_E-LI_T_E-...I_W_u-J1 ADDR : $0011

92

•

HITACHI

-----------------------------------------------------HD6B01VO,HD6801V5
Bit 7

Rate and Mode Control Register

I

Bit 0

I ee, Iceo Iss, Isso Is,o

Transmit/Receive Control and Status Register

Port 2
Ax

Bot
3

"

Clock

10

Bit
2

:rx

Bit

12

4

Figure 22 Serial 1/0 Registers

TDRE is initialized to I by RES.
Bit 6 ORFE Over-Run-Framing Error - set by hardware when
an overrun or framing error occurs (receive only).
An overrun is defined as a new byte received with
last byte still in Data Register/Buffer. A framing
error has occurred when the byte boundaries in bit
stream are not synchronized to bit counter. IfWU
flag is set, the ORFE bit will not be set. The
ORFE bit is cleared by reading the status register,
then reading the Receive Data Register, or by
RES.
Bit 7 RDR F Receiver Data Register Full - set by hardware
when a transfer from the input shift register to the
receiver data register is made. If WU flag is set,
the RDRF bit will not be set. The RDRF bit is
cleared by reading the status register, then reading
the Receive Data Register, or by RES.

Bit 0 WU

"Wake-up" on Next Message - SIlt by HD6801V
software and cleared by hardware on receipt of
ten consecutive I's or reset of RE flag_ It should
be noted that RE flag should be set in advance of
CPU set ofWU flag.
Bit 1 TE
Transmit Enable - set by HD680lV to produce
pream ble of nine consecutive l's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the DDR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit 4.
TE set should be after at least one bit time of data
transmit rate from the set-up of transmit data
rate and mode.
Transmit Interrupt Enable - when set, will permit
Bit 2 TIE
an IRQ, interrupt to occur when bit 5 (TDRE) is
set; when clear, the TDRE value is masked from
the bus.
Bit 3 RE
Receiver Enable - when set, gates Port 2 bit 3 to
input of receiver regardless of DDR value for this
bit; when clear, serial I/O has no effect on Port 2
bit 3.
Receiver Interrupt Enable - when set, will permit
Bit 4 RIE
an IRQ, interrupt to occur when bit 7 (RDRF) or
bit 6 (ORFE) is set; when clear, the interrupt is
masked.
Bit 5 TORE Transmit Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TDRE bit
is cleared, by reading the status register, then
writing a new byte into the transmit data register,

Rate and Mode Control Register

The Rate and Mode Control register controls the following
serial I/O variables:
• Baud rate
• format
• clocking source, and
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are write-only and
cleared on RES. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining two bits control the
format and clock select logic. The register definition is as
follows:

RBte and Mode Control Register
7

6

5

x

x

x

4

x

3

2

o

eeo

550

I I I
eel

_HITACHI

551

AD DR : $0010

93

HD6801VO.HD6801V5--------------------------------------------------Speed Select - These bits select the Baud rate for
the internal clock. The four rates which may be
selected are a function of the CPU  Zero
Branch If Higher
Branch If" Zero
Branch If Lower Or
Seme
Branch If < Zero
Branch If Minus
Branch If Not Equal
Zero

Mnemonic

Branch Test

BRA
BRN
BCC
BCS
BEQ
BGE
BGT
BHI
BlE

IMPLIED
RELATIVE DIRECT
INDEX EXTNO
OP
#
# OP
# OP - # OP
# OP
20 3 2
21 3 2
24 3 2
25 3 2
27 3 2
2C 3 2
2E 3 2
22 3 2
2F 3 2

BlS

23

BlT
BMI

20 3 2
2B 3 2

BNE

26

3 2

Z=O

-

-

-

-

None

None

C=O
C-l
Z=1
N<±JVzO
Z + (N <±J VI - 0
C+Z=O
Z + (N <±J VI = 1
C+Z=1

3 2

N<±JV=1
N -1

Branch If Overflow
Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutlna
Jump
Jump To Subroutine

BVC

2B

3 2

V-O

BVS
BPl
BSR
JMP
JSR

29 3 2
2A 3 2
BO 6 2

V=1
N=O

No Operation

NOP

01

Return From Interrupt

RT!

3B 10 1

Return From

RTS

39

SWI
WAI

3F 12 1
3E 9 1

Subroutine
Software Interrupt
Wait for Interrupt

6E 3 2 7E 3 3
90 5 2 AD 6 2 BO 6 3

5

1

•
•
•
•
•

•
•
•
•
•
• •
• •
•.
• •
• •
• •
• •
••
• •
••
••

•
•
•
•

•
•
•
•
• •

Advances Prog. Cntr.
Only

•
•
•
•
•

•
•

•
•
•
• • • •
• • • •
• • • •
• • • •

•• ••
• • • •
• • • •

•
•
•
•
• • •

--

2

Condition Code
Register
5 4 3 2 1 0
H I N Z V C

• • •
• • •

•
•
•
•• ••
• • ••
•• • •

•
•
•
•

•
•

•
•

• •
••

-@-

•• •• ••
• S •• ••
• ®. • • •

1

Table10 Condition Code Register Manipulation Instructions
AddressingModes
Operations
Claar Carry
Clear Interrupt Mask
Claar Overflow
Set carry
Set Interrupt Mask
Set Overflow
Accumulator A - CCR
CCR - Accumulator A

Mnemonic

ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA

IMPLIED
OP
#
1
OC
2
OE
2
1
OA
2
1
00
2
1
OF
1
2
1
OB
2
2
1
06
07
2
1

-

Boolean Operation
O .... C
0-1
O-V
l-C
I-I
I-V
A- CCR
CCR- A

Condition Code Register
5
4
3
2
1
0
H
I
N Z
V
C
R
R
R
S
S
S

• • •
•
•
• • •
• • •
•
•
• • •

• •

• • •
•
•
• •
• • •
•
•

--@l---

·1·1·1·1·1·

Condition Code Register Notes: (Bit set it test is true and cleared otherwisel
 (Bit NI
Test: Result less than zero? (Bit 15 = 11
@ (Alii
load Condition Code Register from Stack. (See Special Operationsl
@ (Bit 1\
Set when interrupt occurs. If previously set, a Non·Maskable Interrupt i. required to exit the wait state.
@ (Alii
Set according to the contents of Accumulator A.
® (Bit CI Set equal to result of Bit 7 (AccBI

eHITACHI

99

HD6801VO,HD6801V5----Table 11

Instruction Execution Times in Machine Cycle
Im-

ABA
ABX
AOC
ADD

AODO
AND
ASl
ASlD
ASR

BCC
BCS

BEQ
BGE
BGT
BHI
BIT
BlE
BLS

BlT
BMI
BNE
BPl
BRA

BRN
BSR

BVC
BVS

2

•

•
•
•

•
•
•

.,•
•
•
•
•

•
•
•

•
•
•

CBA
ClC
Cli

•

ClR

2

ClV

CMP
COM
CPX
OAA

•

•
•
2

•
•

DEC

2

DES
OEX

•
•
•
2
•

EOR

INC
INS

100

•

•
•
•
•
•
2
•

•
•

•
•

•
•

•
•

2
2
4

4
4

4
4

2

3
3
5
3

•

•

6
4
6

6
4
6

•
6
•

•

•
•
•

•
•

6

•
•
•

•

•
•
•
•
•
•

2

3

4

4

•
•

•
•

•
•

•
•

•
•
•

•
•

•
•
•
•

•

•
•
•
•

•
•
•

•
•
2
•
4
•
•
•
•
2
•
•

•

•
•

•
•

•
•
•
•
•
•

•
•

•
•

•
•
•

•
•

•

•

•
•
•

•

•
•
•

•
•
•

6

6

•
3
•

•

•

4

4

6

6

5

6

6

•

•
6
•
•

•

4
6

4

•

•

•
•
•
•

•
•

•
3

•

•

•
•
•

•

6

•

•
6

plied

Relative

2
3

•
•

•
•
•
•

•

•
•
•
•

•
•

3

•

•
•

3
3
3
3
3
3

•
•
•
•
•
•
•

•
3

•

3
3
3
3
3
3
3
6
3
3

•
•

•

•
•
•
•

•

2
2
2

•

•

•

•

•
•

2

•
•
•

•
•
•
•
•
•
•
•

2

•
3
3

•
•

ACCX

INX
JMP
JSR
lOA
lOO
lOS
lOX
lSR
lSRO
MUl

NEG
NOP

•

•
2

•

•
2

•

ORA

•

PSH

3

PSHX

•

PUl
PUlX
ROl

4

ROR

2

Rli
RTS
SBA

•

SBC
SEC

SEI
SEV

STA
STO
STS
STX
SUB

SUBO
SWI
TAB
TAP
TBA
TPA

TST
TSX
TXS

WAI

•

3

•
•
•
•
•
•

HITACHI

•
2

~'7a':-

•

•
•
2
3
3
3

•
•
•
•

•
2
•
•
•
•
•

•
•

Direct

•
•
5
3
4

4
4

•
•
•

•
•
3

•
•

•
•

•

•
•
•
•

te~~~ d~~~

•

•

3
6
4
5
5
5

3

6

6
4

5
5
5
6

6
6

•

•

10
5
2

•

•

•

•
•

•
•

3

4

4

•

•
•

•

•

•
•

4
5

4

•

•

4

2
4

3
5

•

•

•
•

•
•

•
•
•
•
•
2

•
•
•

•

•
•

•
•
•
•
•
•

3
4
4

•
•
•

•
•
•

•
•

•
•
•
•

6
6

4

2

•

•
•

•

•

•

•

•
•
•

•
•
•
•
•

•
•
•
•

6

•

•
•

•

Relative

•
•

•
•

•
•

3

•
•
6
•
4
•
•
•

•
•
•

Implied

•

•

•
5

5
5
4
6

5

•
•
•

•

•
•
6

•
•
•

5
4

6

•
•
•
•
6
•
•
•

3
10

•
2

•

•
4
•
5

•
•

2
2
2

•

•
•
•
•
•
12
2
2
2
2

•
3
3

9

•
•
•

•
•
•
•
•

•
•

•
•

•
•
•
•
•
•
•

•
•
•

•
•
•

•
•
•

•
•

--------·-----HD6801VO,HD6801V5
• Summary of Cycle by Cycle Operation
Table 12 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write line
(RjW) during each cycle for each instruction.
This information is useful in comparing actual with expected
results during debug of both software and hardware as the

control program is executed. The information is categorized in
groups according to addressing mode and number of cycles per
instruction. (In general, instructions with the same addressing
mode and number of cycles execute in the same manner; exceptions are indicated in the table).

Table 12 Cycle by Cycle Operation
Address Mode &
Instructions

Data Bus

Address Bus

IMMEDIATE
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Operand Data

LOS
I,DX
LDD

3

1
2

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F

1
1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

Op Code Address
Op Code Address + 1
Destination Address

1
1
0

Op Code
Desti nati on Address
Data from Accumulator

Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1

1

0
0

Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1

1
1
1
0
0

Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

3
1
2

3
4

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

3

1
2

3

STA

3

LOS
LOX
LDD

4

STS
STX
STD

4

CPX
SUBD
ADDD

5

JSR

5

1
2

3
1
2

3
4
1
2

3
4
1
2

3
4
5
1
2

3
4
5

1

(Continued)

•

HITACHI

101

HD6801VO HD6801V5----Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

INDEXED
JMP

1
1
1

Op Code
Offset
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset

1
1
1
11

Op Code
Offset
Low Byte of Restart Vector
Operand Data

1
2
3
4

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
0

Op Code
Offset
Low Byte of Restart Vector
Operand Data

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
0
0

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

6

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

1
1
1
1
1
0

Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus F F F F

1
1
1
1
1
1·

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byt~)

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

4

1
2
3
4

STA

4

LOS
LOX
LDD

STS
STX
STD

ADC
ADD
AND
BIT
CMP

ASL
ASR
CLR
COM
DEC
INC

EOR
LOA
ORA
SBC
SUB

LSR
NEG
ROL
ROR
TST*

6

CPX
SUBD
ADDD

6

JSR

6

1
2
3
4
5

6
1
2
3
4
5

6

• In the TST Instruction, RtW line of the sixth cycle il "'" level, and AB=F FFF, DB-Low Byte of Reset Vector.

102

•

HITACHI

(Continued)

---------------------------HD6801VO,HD6801V5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

EXTENDED

3

JMP

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

4

3
4
4

STA

1
2

1
2

3
4
LOS
LDX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

CPX
SUBD
ADDD

6

1
2

3
4

5
6

6

1
2

3
4

5
6
JSR

6

1
2

3
4

5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data

Op Code
Op Code
Op Code
Operand

1
1
1
0

Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
0
0

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

Op Code Address
Op Code Add,ess + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand

1
1
1
1
1
0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus F F F F

1
1
1
1
1
1

Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

Address
Address + 1
Address + 2
Destination Address

• In the TST instruction, R/W line ofthe sixth cycle is "1" level, and AB = FFFF, DB = Low Byte of Reset Vector.

eHITACHI

(Continued)

103

HD6801VO,HD6801V5------------------------------------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
IMPLIED
ABA DAA
ASL DEC
ASR INC
CBA LSR
CLC NEG
CLI NOP
CLR ROL
CLV ROR
COM SBA

ABX

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

2

1

2

3

1

2
3
ASLD
LSRD

3

DES
INS

3

INX
DEX

3

PSHA
PSHB

3

TSX

3

TXS

3

1

2
3
1

2
3
1

2
3
1

2
3
1
2

3
1

2
3
--~

PULA
PULB

1
2
4

4

PULX

----- - 5

Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Previous Re!li~~r_Conten!S__
Op Code Address
Op Code Address + 1
Address Bus---FFFF
----Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Address Bus ...FFFF
-.-.----

1
1
1

Op Code
Irrelevant Data
Low Byte of Restart Vector

5

1

5

Stack Pointer + 2

1

1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1
0
0

1

1

2
3

9

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code
1
Op Code of Next Instruction
1
Irrelevant Data
1
Op Code
1
Op Code of Next Instruction
1
.1_ ~ow Byte of Restart Vector
Op Code
1
Op Code of Next Instruction
1
Accumulator Data
0
Op Code
1
Op Code of Next Instruction
1
Irrelevant Data
1
Op Code
1
Op Code of Next Instruction
1
Low Byte of Restart Vector
1
Op Code
1
Op Code of Next Instruction
1
Irrelevant Data
1
1
1
1

4

4

5

WAI"'

Op Code
Op Code of Next Instruction

1
1
0
0

2
3
4
RTS

1
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
--_.- --- ------ Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1

2
3
----- -

Op Code Address
Op Code Address + 1

~~-

4

3
PSHX

Data Bus

Address Bus

2
3
4

1
1
1
1
1
1

1
1

1

Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
(Continued)

104

eHITACHI

-------------------------------------------------------HD6801VO,HD6801V5
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
WAI**

Cycles

Cycle
#
5
6
7

8
9

MUL

10

SWI

10

12

Stack
Stack
Stack
Stack
Stack

Pointer
Pointer
Pointer
Pointer
Pointer

-

2
3
4
5
6

RIW
Line
0
0
0
0
0

Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

5

Stack Pointer + 2

1

6

Stack Pointer + 3

1

7

Stack Pointer + 4

1

8

Stack Pointer + 5

1

9

Stack Pointer + 6

1

10

Stack Pointer + 7

1

9
10
11

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)

1
1
0
0
0
0
0
0
0
1
1

12

Vector Address F F FB (Hex)

1

1
2
3
4
5
6
7

8

RTI

Address Bus

9
10
1
2
3
4

1
2
3
4
5
6
7

8

Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code
Irrelevant Data
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (H igh Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
Op Code
Irrelevant Data
Return Address (Low· Order Byte)
Return Address (H igh Order Byte)
Index·Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)

·*While the MCU is in the "Wait" state, its bus state will appear as a series of MCU reads of an address which is seven locations less than the

original contents of the Stack Pointer. Contrary to the HD6800, non. of the ports are driven to the high impadance state by a WAI instruction.

(Continued)

•

HITACHI

105

HD6801VO,HD6801V5 - - - - - ,
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction

Data Bus

Address Bus

RELATIVE
BCC
BCS
BEQ
BGE
BGT
BRN

BHT
BlE
BlS
BlT
BMT

3

BNE
BPl
BRA
BVC
BVS

1
2

3

BSR

1
2

6

3
4

5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

OpCode
Branch Offset
low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

Op Code
Branch Offset
low Byte of Restart Vector
Op Code of Next Instruction
Return Address (low Order Byte)
Return Address (High Order Byte)

• Summary of Undefined Instruction Operations
The HD6801 V has 36 undefmed instructions. When these are
carried out, the contents of Register and Memory in MCV
change at random.

When the op codes (4E, SE) are used to execute, the MCV
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the

LSI.

Table 13 Op codes Map
HD6B01V
OP
CODE

~

1010
1011
1100

0
1
2
3
4
5
6
1
S
9
A
B
C

1101

0

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

[NOTES)

0001
1
SBA
CBA

0010
0011
2
3
BRA
TSX
NOP
BRN
INS
~ BHI PULA (+11
BlS PUlB (+11
LSRD (+11 ~ BCC
DES
ASlD (+11 ~ BCS
TXS
TAP
TAB BNE
PSHA
TPA
TBA BEQ
PSHB
INX (+11
BVC PUlX (+21
DEX(+I) DAA BVS RTS (+21
ClV
ABX
~ BPl
RTI (+11
SEV
ABA BMI
Cle
BGE PSHX (+11

--

Cli
SEI
1/2

---/"

/'
~
1/2

ACCAorSP
ACCB or X
ACC ACC IND EXT
A
B
IMM DIR liND EXT IMM I DIR liND I EXT
0100 0101 0110 0111 1000 1'00'1'0'0 1'011 1100 1"0'1"'01""
4
5
1
6
B I 9 I A I B
C I 0 I ElF
NEG
SUB
CMP
SBC
COM
SUBD (+21
I • : ADDD (+21
AND
lSR
BIT
lOA
ROR
ASR
STA
STA
~I
ASl
EOR
ROl
ADC
ORA
DEC
ADD
CPX (+21
lDD (+11
INC

I

-------- -0000
0

SEC

1110
E
1111
F
BYTE/CYCLE

MICROCOMPUTER INSTRUCTIONS

BlT
BGT
SlE
2/3

------

----

MUl (+11
WAI (+6)
SWI (+91
1/3

-- ..
1/2

TST

I

·

/L

·
r!~1

·

.

JSR (+21

,

.

• (+111

STD(+1I

JMP (-31
lOS (+11
lOX (+11
• (+Ii1
• (+111
STS (+11
STX (+11
ClR
1/2 2/6 3/6 2/2 2/3 2/4 3/4 2/2 2/3 2/4 3/4

I

I

I

I

1I Undefined Op codes are marked with ~.
21 (
I indicate that the number in perenthesis must be added to the cycle count for that instruction ..
3) The instructions shown below are all 3 bytes and are marked with """.

Immediate addressing mode of SUBD, CPX, lOS, ADDD, lDD and lOX instructions, and undefined op codes
(SF, CD, CFI.
41 The Op codes (4E, 5EI are 1 byte/~ cycles instructions, and are marked with """ .

106

•

HITACHI

;

I

I

0
2
3
4
5
6
1
S
9
A
B
C
0
E
F

•
J:

~

()

-J:
'SCI

=

TIE-TORE + RIE-(RORF + ORFE)

Vector -+ PC

lIIl\iII

SWI

fRO,
ICF
OCF
TOF
SCI

FFFC FFFO
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFFl

Non-Maskable Interrupt
Software Interrupt

Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt

SCI Interrupt (TORE + RORF + ORFE)

J:

o

(l)
Q)

o

~

<

o

J:

A

o

(l)
Q)

o

~

~

Figure 24 Interrupt Flowchart

<
U1

HD6801VO,HD6801V5---------------------------------------------------Vee

Vee

Enable

--IRQ,
Port 3
8 Transfer
Lines
Port 1

Port 1

81/0
lines

81/0 Lines

-"I__-.-__J.,-..,.

POrt 4
81/0 Lines ....

Port 2
51/0 Lines
SCI
16 B,tTllner

Port 4
B I/O Lmes

Port 2
51/0 Lines
SCI

Voo

Voo

Figure 25

HD6801V MCU Single-Chip Dual Processor Configuration

HD6801V
MCU

Address
Bus

Data
Bus

Figure 26 HD6801V MCU Expanded Non-Multiplexed Mode

Address Bus

Data Bus

Figure 27 HD6801 V MCU Expanded Multiplexed Mode

108

•

HITACHI

H06803, H06803-1---MPU (Micro Processing Unit)
The HD6803 MPU is an 8-bit microcomputer system which
is compatible with the HMCS6800 family of parts. The HD6803
MPU is object code compatible with the HD6800 with improved
execution times of key instructions plus several new 16-bit and
8 bit instruction including an 8 x 8 unsigned multiply with
16-bit result. The HD6803 MPU can be expanded to 65k words.
The HD6803 MPU is TTL compatible and requires one +0.5
volt power supply. The HD6803 MPU has 128 bytes of RAM,
Serial Communications Interface (S.C.1.), and parallel I/O as
well as a three function 16·bit timer. Features and Block
Diagram of the HD6803 include the following:
•
•

FEATURES
Expanded HMCS6800 Instruction Set

•
•
•

8 x 8 Multiply
On-Chip Serial Communications Interface (S.C. I.)
Object Code Compatible with The HD6800 MPU

•
•
•
•

1'6-Bit Timer
Expandable to 65k Words
Multiplexed Address and Data
128 Bytes of RAM (64 Bytes Retainable On Power
Down)

•
•
•
•
•

13 Parallel 110 Lines
Internal Clock/Divided-By-Four
TTL Compatible Inputs and Outputs
Interrupt Capability
Compatible with MC6803 and MC6803·1

•

BLOCK DIAGRAM

HD6803P
HD6803P-1

I
L
_
10'.'01

•

PIN ARRANGEMENT
Vss

o

XTAL

AS

RM
Do/Ao
O,/A,
02 /A 2
O~/A:l

Vce
P JII

D4 /A 4

P"
P"
P"
P"
P"
P"
P"
P"

Os/A,

HD6803

,

Ds/Ah

O,/A,

p ..

P"
P"
Standby

(Top View)

p"
p"
p"
p"
p"

A.
A.

!----p"

~

A"

A"
A"
A"
A..
A..

Vee

p"

p"

•

TYPE OF PRODUCTS

p"
P..
P ..
p ..

HD6803

1.0MHz

p"

HD6803-1

1.25MHz

Type No.

Bus Timing

Standby

~HITACHI

109

H D 6 B 0 3 , H D 6 B 0 3 - 1 - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ __
•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit
V
V
°c
°c

Input Voltage

Vee "
V ln "

Operating Temperature

Topr

-0.3- +7.0
-0.3-+7.0
0 -+70

Storage Temperature

Till!

- 55-+150

Supply Voltage

• With respect to VSS (SYSTEM GNDI
[NOTE] Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these condition. are exceedad. it could affect rellabilitv of LSI.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee =5.0V±5%, Vss = OV, Ta" o--+I70°C, unless otherwise noted.1
Item
Input "High" Voltage

Symbol

m
Other Inputs"

Test Condition

V 1H

min

typ

max

4.0

-

Vee

2.0

-

Vee
0.8
0.8

Input "Low" Voltage

All Inputs"

V 1L

Input Load Current

EXTAL

IIlnl

Vln=O-V ee

-

Input Leakage Current

NMI,IRQI

II'nl

Vln = 0 - 5.25V

Three State (Offset)

PIO - PI7

Leakage Current

P20 - P24
Do/Ao - D7/A7

il TS ;!

V in = 0.5 - 2.4V

-

-

As -

V OH

I LOAD = -205 IJ.A
I LOAD = -1451J.A

2.4

Output "High" Voltage

2.4

-

I LOAD = -100 IJ.A

2.4

-

I LOAD = 1.6 mA
V ou , = 1.5V

-

-

RES

~IS, E, R/W, AS

-0.3

Other Outputs
Output "Low" Voltage

All Outputs

Darlington Drive Current PIO - P17
Power Dissipation
I nput Capacitance
Vee Standby
Standby Current

AD/Do - A7/D7
Other Inputs
Powerdown

VOL
-loH

-

Po
V in = OV, Ta = 25°C,

Cin

f=1.0MHz

-

-

10
100

1200
12.5
10.0

-

5.25

4.75

5.25

Powerdown

ISBB

-

HITACHI

IJ.A

IJ.A

V
V

4.0

$

mA

-- - - - -

mA
mW

V SB

-

V

10.0

V SBB
VSBB = 4.0V

V

0.5

Operating

... Except Mode Programming Levels.

110

1.0

2.5

Unit

8.0

pF
V
mA

---------------------------------------------------------H06803,H06803-1
• AC CHARACTERISTICS
BUS TIMING (Vee'" 5.0V ± 5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)

Item

Test
Condition

Symbol

HD6803
min

max

-

Cycle Time

t cvc

Address Strobe Pulse Width "High"

PW ASH

Address Strobe Rise Time

tAs,

5

-

Address Strobe Fall Time

tASt

5

-

Address Strobe Delay Time

tASD

60

Enable Rise Time

tE,

5

-

Enable Fall Time

tEf
PW EH

5
450

Enable Pulse Width "High" Time

1

Enable Pulse Width "Low" Time

PW EL

Address Strobe to Enable Delay Time

tASED

200

450
Fig. 1

60

-

Address Delay Time

tAD

Address Delay Time for Latch

tADL

-

Data Set-up Write Time

tDsw

225

Data Set-up Read Time

tDSR

80

Read

tHR

10

Write

tHW

20

Address Set-up Time for Latch

tASL

60

Address Hold Time for Latch

tAHL

20

Address Hold Time

tAH

20

Peripheral Read Access Time (Multiplexed Bus)

(tACCM)

Oscillator stabilization Time

tRC

Fig. 7

100

Processor Control Set:up Time

tpcs

Fig.8

200

Data Hold Time

I

I

-

HD6803-1

typ

Unit

min

typ

max

0.8
150

-

-

ns

50

5

-

50

ns

50

5

50

ns

-

ns

50

ns

10

10

f.ls

50

5

-

-

50

5

-

50

ns

-

-

340

-

-

ns

-

-

-

260
270

(600)

-

30

350

30

115
70
10
20
50
20
20

100
200

-

260

ns

260

ns

-

ns

-

-

ns
ns

-

ns
ns
ns
ns
ns

(420)

ns

-

ms

-

ns

PERIPHERAL PORT TIMING (Vee = 5.0V ± 5%, Vss" OV, Ta· 0 - +70°C, unless otherwise noted.)
Symbol

Test Condition

min

typ

max

Peripheral Data Setup Time

Item
Port 1, 2

tpDSU

Fig.2

200

-

-

ns

Peripheral Data Hold Time

Port 1,2

tpDH

Fig.2

200

-

ns

Delay Time, Enable Negative
Transition to Peripheral Data
Valid

Port 1,2*

tpWD

Fig. 3

-

400

ns

-

Unit

* Except P21

•

HITACHI

111

H06803,H06803-1--------------------------TIMER, SCI TIMING (Vee = 5.0V ±5%, Vss • OV, Ta = 0 - +70oC, unless otherwise noted.1
Item

Symbol

Timer Input Pulse Width

tpw~

Delay Time, Enable Positive Transition to
Timer Out

tTOD

SCI Input Clock Cycle

Test Condition
~

Fig. 4

tScve
tPWSCK

SCI Input Clock Pulse Width

typ

max

-

-

ns

-

-

600

ns

1

-

0.6

!eve
tScve

min
2tcye+ 2OO

0.4

-

Unit

MODE PROGRAMMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0 - +70°C, unless otherwise noted.)
min

typ

max

Unit

Mode Programming Input "Low" Voltage

V MPL

-

1.7

V

Mode Programming Input "High" Voltage

V MPH

4.0
3.0
2.0

-

-

V

-

-

tcyc

-

-

tcyc

-

-

ns

Fig. 8

PW RSTL

RES "Low" Pulse Width
Mode Programming Set·up Time

tMPS

Im

Mode Programming
Hold Time

Test Condition

Symbol

Item

Rise Time ~ lllS
Rise Time < llls

I RES

0
100

tMPH

-

10\'<

2.2Y

Address Strobe

V

-PWASH-

CASI
oey

2.4 y '

-

- l+-

CEI

-

-lAS,

I+-IASI

I-

'ASO

\

Enable

~r
ASEO

o.sy

-

-tAO-

'\

MPUWrtte

Do/A.. - D,/A,
IPurt 3)

-

-

-

-tE,

I

Oey

J
)

O,,/A. -07lA,
tPort 3)

\

/

,
J

Address Vahd

i

I=.

·'AHL

-tosw-

22Y

22Y

Address
Valid

Oey

-

Data Vahd

/

Oey

-'OSR-_

22Y
Address
Vahd

1/

Oey

,

HITACHI

1-'_
If

""HR

2.0Y
0.1. V.lld

O.8Y

Figure 1 Expanded Multiplexed Bus Timing

•

r-'AH

If

C,ACCMI

112

-tEl

-

-'AOL-

MPU Read

1\

2.2V

'ASL-

I

PWEH

V

PWEL

J

r--.

I

----------------H06803,H06803-1

r

r-MPU Read

MPUW",.

Enable (E)
Enable (E)

O.5V

o
P,. - PI'

-:2:-:::.0~V..Jt;-----:i~~--­

p,. -

.;O:::.:::8.:.V.;r~-----_r~::.::..:....-----_

P"

Figure 2

5V\--'PWDxl

i--::2~2:::V-:----

All Oat:
POri Qu'puts _ _ _ _ _ _ _ _ _ _

51 6V

Oa'a Valid

• Not applicable to P 21

Data Set-up and Hold Times
(MPU Read)

Figure 3 Port Data Delay Timing
(MPU Write)

Enable (E)

Tlm.r

Coun,., _ _ _ _ _...1 ,-_+;;';;;;";';""...,J ' -_ _ __

P"

Output

Figure 5 Mode Programming Timing
Figure 4

Timer Output Timing

Vee

Tesl POint

0-..,...,.-+....
C

152074 ®
or Equ,v

A

C=90pFforDu/Au-D7/A7. A~-Al·" E. AS,
'" 30 pF for p. o
P20 -Pu

-p".

Riw

A: 12kSl fO'D'/~'-DdA,.:. A,-A,-" E. AS. R/W
-24knforP,o p."P 10 P u
TTL Load

Figure 6 Bus Timing Test Load

•

HITACHI

113

HD6803,HD6803-1------------------------------------------------------___

Enable

~E)

Internal

_.J,__

Address BusJ\._-I"'-_-""..._.J'-_.J'~_.JI.......

J'I._ _" _ _.......'\..._

_J"__.J~_...n

_ _J'l._~"__...J"__ _

In t e r n a l " ' " ' \ . r - - - V - - V - - V - - - V - - " , " " r - - " - - - V - - V - - Y - - - Y - - - " ' ' ' - - V - - V - - , r - - , , ' ' - BUS..J'o--~--"-o-p-Cod
.......
' "O-P-C-O-d.~P-C-O--P-C7"P"'C8--P-C..J'5"-X-O_-X-7J\.X-S---X'-5"-A-C-C-AJ'.......
AC-C-S...n-CC-A-J"I-"-"'-""-n-'"-V-.-,,-o,~-V-,,-'O-'J'l.F-;"-'-,n-st".

0-'-

Data

f

\\..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J

Internal A/W
• IRQ: ; Internal Interrupt

Eriabl,(EJ

Data

MSB

LSD

Interrupt Routine

Figure 7 Interrupt Sequence

~~\\\\\\\\\\\\,\ ~W\~'\'\~

Lf1..f4 ~ [1..f1...flJ

~5.~2S:.:.V---_tt )-l"".- - - - - - - - - - - ; \ ,~

~

II

~~'PCS

Vee :;}1<-_4._7S_V_ _ _ _ _ _ _ _ _ 'AC

~ f.-'PCS
t -.:;.:;O",.SV;...-_ _ _ __
,-

,<.OV

~ -------_tt~l-----------~,

Ad~te'";' §\\\\\\\\\\\\\\\\\\\~t~
%\s\\\\\SS\S~~
~
~
~E
felSUS

'n,,,n,' AI'll

~

\\\\\\\\\\\\\\\\\\\\\'ilI\SS\SS\\\\\\\S\\\SS\\\\\\\SY

:::::x:=r---

6:,~'~~: &\\\\\\\\\\\\\\\\\%1 Jtz\\\\\S\\\S\\\\\\\\\\\\\\~ I--...A_...J\_-.J"--____
"-_"-~"-I
pCS ..... pelS PCO..... PC7 First

pc:::x:=x::

Instruction

~NotValid

Figure 8 Reset Timing

Nominal Crystal Parameter

• SIGNAL DESCRIPTIONS

• Vee and Vss
These two pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
•

XTAL and EXTAL

~all
Item
~>
RS

These connections are for a parallel resonant fundamental
crystal, AT cut. Devided by 4 circuitry is included with the
internal clock. so a 4 MHz crystal may be used to run the
system at I MHz. The devide by 4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non·time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. EXTAL may
be driven by an external TTL compatible source with a 50%
(±\O%) duty cycle. It will devided by 4 any frequency less than
or equal to 5 MHz. XTAL must be grounded if an external
clock is used. The following are the recommended crystal
parameters:

114

4MH z

@HITACHI

5MH z

I.

_~~_-L7p~,:,:~x.

4.7pF max.
30n typo

XTAL~--~-----.

CJ
EXTAL

1--....-,

tL2

e L1 = C L2 = 22pF

± 20%

(3.2 - 5 MHz)
iNOTE) AT cut parallel
resonance parameters

Jr

CL1

Figure 9 Crystal Interface

- - - - - - - - - - - - - - - - - - - - - - - - - - - H06803,H06803-1
•

Vee Standby
This pin will supply +5 volts ±5% to the standby RAM on the
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
VSBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
I) Write "0" into the RAM enable bit, RAM E. RAM E is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.

Vee Standby i P o w e r L i n e

Figure 10 Battery Backup for Vee Standby
• Reset (RES)
This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. During operation, RES, when
brought "Low", must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the CPU does the follow·
ing;
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits. 2, I, and 0 are latched into programmed
control bits PC2, PCI and PeO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set, must be cieared before the
CPU can recognize maskable interrupts.
• Enable (E)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide by 4 result of the
crystal frequency. It will drive one TTL load and 90 p F.
• Non·Maskable Interrupt (NMII
A low-going edge on this input requests that a non-maskable·
interr\lpt sequence be generated within the processor. As with
interrupt Request signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these loca·
tions causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 k51 external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs IRQI and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
E following the completion of an instruction.

$

•

Interrupt Request URQI)
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait until it
completes the current instruction that it being executed before
it recognizes the request. At that time, if the interrupt mask bit
in the Condition Code Register is not set, the-mllchine will begin
an interrupt sequence. The Index Register, Program Counter,
Accumulators, and Condition Code Register are stored on the
stack. Next the CPU will respond to the interrupt request by
setting the interrupt mask bit "High" so that no further maskable interrupts may occur. At the end of the cycle, a 16-bit
address will be loaded that points to a vectoring address which is
located in memory locations $FFF8 and $FFF9. An address
loaded at these locations causes the CPU to branch to an interrupt routine in memory.
The IRQI requires a 3.3 k51 external resister to Vee which
should be used for wire-OR and optimum control of int~ts.
Internal Interrupts will use an internal interrupt line (IRQ,).
This interrupt will operate the same as IRQ I except that it will
use the vector address of $FFFO through $FFF7. IRQI will
have priority over IRQ2 if both occur at the same time. The
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table I).

Table 1 Interrupt Vector Location
Vector
Highest
Priority

Lowest
Priority

Interrupt

MSB

LSB

FFFE

FFFF

FFFC

FFFO

FFFA

FFFB

FFF8

FFF9

IRQ I

FFF6

FFF7

ICF (Input Capture)

FFF4

FFF5

OCF (Output Compare)

FFF2

FFF3

TOF (Timer Overflow)

FFFO

FFFl

SC I (RORF + ORFE + TORE)

RES
NMI
Software Interrupt (SWIl

• ReadlWrite (R/W)
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output is capable of driving one TTL load
and 90 pF.
• Address Strobe (AS)
In the expanded multiplexed mode of operation address
strobe is output on this pin. This signal is used to latch the 8
LSB's of address which are mUltiplexed with data on Port 3. An
8-bit latch is utilized in conjunction with Address Strobe, as
shown. in figure II. Expanded Multiplexed Mode. Address
Strobe signals the latch when it is time to latch the address lines
so the lines can become data bus lines during the E pulse. The
timing for this singal is shown in Figure I of Bus Timing. This
signal is also used to disable the address from the multiplexed
bus allowing a deselect time, t ASD before the data is enabled to
the bus.
• PORTS
There are two I/O ports on the H06803 MPU; one 8-bit
port and one 5·bit port. Each port has an associated write

HITACHI

115

H06803.H06803-1----------------------------------------_______________
only Data Direction Register which allows each I/O line to be
programmed to act as an input or an output·. A "I" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
two ports: Port I, Port 2. Their addresses and the addresses of
their Data Direction registers are given in Table 2.
• The only exception is bit 1 of Port 2, which can either be data
input or Timer output.

Table 2 Port and Data Direction Register Addresses
Data Direction

Ports

Port Address

Register Addres.

I/O Port 1

$0002
$0003

$0000
$0001

I/O Port 2

state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "I" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup resistors but will drive TIL inputs
directly. For driving CMOS inputs, external pullup resistors are
required. After Reset, the 1/0 lines are configured as inputs.
Three pins on Port 2 (pin 8, 9 and 10 of the chip) are requested
to set following values (Table 3) during reset. The values of
above three pins during reset are latched into the three MSBs
(Bit 5,6 and 7) of Port 2 which are read only.
Port 2 can be configured as 1/0 and provides access to the
Serial Communications Interface and the Timer. Bit I is the
only pin restricted to data input or Timer output.
Table 3 The Values of three pins

I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logic "I" and less than 0.8 V for a logic "0". As outputs,
these lines are TTL compatible and may also be used as a source
of up to I rnA at 1.5 V to directly drive a Darlington base. After
Reset, the 1/0 lines are configured as inputs.

Pin Number

Value

8
9
10

H

•

•

I/O Port 2
This port has five lines tha t may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance

GND
AS

G OC

a,

74 LS373

D.

• BUS

• Data/Address Lines (Do/Ao - D,/A,)
Since the data bus is multiplexed with the lower order
address bus in DatalAddress, latches are required to latch those
address bits. The 74LS373 Transparent Octal D-type latch can
be used with the HD6803 to latch the least significant address
byte. Figure II shows how to connect the latch to the HD6803 .
The output control to the 74LS373 may be connected to
ground.
• Address Lines (As - Au)
Each line is TTL compatible and can drive one TTL load and
90 pF. After reset, these pins become output for upper order
address lines (As to Au)

1A~,_"

Function Table

.. -A,

a.

1..

·'0._0,

Figure 11 Latch Connection

116

L

L; Logical ''0''
H; Logical .., ..

• INTERRUPT FLOWCHART
The Interrupt flowchart is depicted in Figure 16 and is common to every interrupt excluding reset.

I

D,

[NOTES]

L

_HITACHI

OutPUt
Control
L
L
L
H

Enable

Output

G

D

a

H
H

H
L

L

x
x

H
L

x

a.
Z

----------------------------HD6803,HD6803-1
•

MEMORY MAP

•

The MPU can provide up to 65k byte address space. A
memory map is shown in Figure 12. The first 32 locations are
reserved for the MPU's internal register area, as shown in Table
4 with exceptions as indicated.
Table 4 Internal Register Area
Address

Register
Port 1 Data Direction Register * *
Port 1 Data Register
Port 2 Data Register

00
01
02
03

Not
Not
Not
Not

04·
05·
06·
07·

Port 2 Data Direction Register··

Used
Used
Used
Used

OA
OB
OC

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Not Used

OE
OF·
10
11
12
13

Rate and Mode Control Register
Receive Data Register

Transmit Data Register

14
15-1F

RAM Control Register

Reserved
• External Address
** 1; Output. 0; Input

Multiplexed/RAM
$0000

Internal Registers

Output Compare Register ($OOOB:OOOC)

The Output Compare Register is a 16-bit read/write register
which is used to control an output wavefonn_ The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the T(,SR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit 1 contains a'''I'' (Output),
the output level register value will appear on the pin for Port 2
Bit I. The values in the Output Compare Register and Output
Level bit may then be changed to control the output level on
the next compare value. The Output Compare Register is set to
$FFFF during RES_ The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16-bit value is in the register
before a compare is made_
•

$OOIF

Free Running Counter ($O009:000A)

The key element in the programmable timer is a 16-bit free
running counter which is driven to increasing values by E (Enable)_ The counter value may be read by the CPU software at
any time_ The counter is cleared to zero on RES and may be
considered a read-only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications_
•

00

Transmit/Receive Control and Status Register

The HD6803 contains an on-chip 16-bit programmable timer
which may be used to perform measurements on an input
waveform while independently generating an output waveform.
Pulse widths for both input and output signals may vary from a
few microseconds to many seconds. The timer hardware consists
of
an 8-bit control and status register,
a 16-bit free running counter,
a 16-bit output compare register. and
a 16-bit input capture register
A block diagram of the timer registers is shown in Figure 13.
•

08
09

Timer Control and Status Register

Counter (High Byte)
Counter I Low Byte)
Output Compare Register (High Byte)

PROGRAMMABLE TIMER

Input Capture Register ($OOOD:OOOE)

The Input Capture Register is a 16-bit read-only register used
to store the current value of the free running counter wren the
proper transition of an external input signal occurs_ The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEDG) in the TCSR The Data
Direction Register bit for Port 2 Bit 0, should * be clear (zero)
in order to gate in the external input signal to ilie edge detect
unit in the timer_
* With Port 2 Bit 0 configured as an output and set to "I", the

External Memory Space

$0080
Internal RAM

$ooFF

external input will still be seen by the edge detect unit.

External Memory Space

$FFFO .....----1
$FFFF ....._ _ _.. '

External Interrupt Vectors

INOTE]
Excludes the following addresses which may
be used externally: $04, $05. $06. $07. and
$OF.

Figure 12 HD6803 Memory Map

•

HITACHI

117

H 0 6 8 0 3 . H 0 6 8 0 3 - 1 - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ __

HD6803 Internal Bus

Output Input
Level Edge
B.t 1 81t 0

Port 2

Port 2

Figure 13 Block Diagram of Programmable Timer
Timer Control and Status Register

76543210
I,CF

I I I I I
OCF

TOF

EICI

• Timer Control and Status Register (TCSRI ($00081
The Timer Control and Status Register consists of an 8·bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read·only
timer status information and indicate that:
• a proper transition has taken place on the input pin with a
subsequent transfer of the current counter value to the
input capture register.
.3' match has been found between the value in the free
running counter and the output compare register, and
when $0000 is in the free running counter.
Each of the flags may be enabled onto the HD6803 internal
bus (iRQ;') with an individual Enable bit in the TCSR. If the
I·bit in the HD6803 Condition Code re~ister has been cleared, a
priority vectored interrupt will occur corresponding to the flag
bit(s) set. A description for each bit follows:
Bit 0 Ol VL Output Level'- This value is clocked to the output
level register on a successful output compare. If
the DDR for Port 2 bit I is set. the value will
appear on the output pin.
Bit I IEDG Input Edge -- This bit controls which transition of
an input will trigger a transfer of the counter to
the input capture register. The DOR for Port 2 Bit
must be clear for this function to operate. IEDG
= 0 Transfer takes place on a negative edge
r·High"·to·"Low" transition).
IEOG = I Transfer takes place on a positive edge

o

118

EOCI

ETO,I'EDG

I

OLVLI $0008

("Low"·to."High" transition).
Bit 2 ETOI Enable Timer Overflow Interrupt - When set, this
bit enables IRQ 2 to occur on the internal bus for a
TOF interrupt; when clear the interrupt is in·
hibited .
Bit 3 EOCI Enable Output Compare Interrupt - When set,
this bit enables IRQ 2 to appear on the internal 'bus
for an output compare interrupt; when clear the
interrupt is inhibited.
Bit 4 EICI Enable input Capture Interrupt - When set, this
bit enables IRQ2 to occur on the internal bus for
an input capture interrupt; when clear the inter·
rupt is inhibited.
Bit 5 TOF Timer Overflow Flag - This read-only bit is set
when the counter contains SFFFF. It is cleared by
a rea4 of the TCSR (with TOE set) followed by an
CPU read of the Counter (S09).
Bit 6 OCF Output Compare Flag - This read·only bit is set
when a match is found between the output
compare register and the free running counter. It is
cleared by a read of the TCSR (with OCF set)
followed by an CPU write to the output compare
register (SOB or SOC).
Bit 7 ICF
Input Capture Flag - This read·only status bit is
set by a proper transition on the input; it is cleared
by a read of the TCSR (with ICF set) followed by
an CPU read of the Input Capture Register ($00).

_HITACHI

---------------------------------------------------------HD6803,HD6803-1
• SERIAL COMMUNICATIONS INTERFACE
The H06803 contains a full-duplex asynchronous serial
communications interface (SCI) on chip. The controller
comprises a transmitter and a receiver which operate independently or each other but in the same data format and at the same
data rate. Both transmitter and receiver communicate with the
CPU via the data bus and with the outside world via pins 2, 3,
and 4 of Port 2. The hardware, software, and registers are explained in the following paragraphs.

Bit 7

1

Rate and Mode Control RegIster

1 Icco I I
CCI

551

BIt 0

550

IslO

Transmit/ReceIVe ContrOl and Status Register

IRDAFIORFEITDA~ AlE

I I I I I
RE

TIE

TE

WU

S11

Port 2

•

Wake-Up Feature
In a typical multi-processor application, the software
protocol will usually contain a destination address in the initial
byte(s) of the message. In order to permit non-selected MPU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further interrupt processing may be
optionally inhibited until the beginning of the next message.
When the next message appears, the hardware re-enables (or
''wakes-up'') for the next message. The "wake-up" is automatically triggered by a string of ten consecutive I's which
indicates an idle transmit line. The software protocol must
provide for the short idle period between any two consecutive
messages.

Programmable Options
The following features of the H06803 serial 1/0 section are
programmable:
- format - standard mark/space (NRZ)
• Clock - external or internal
• baud rate - one of 4 per given CPU q>2 clock frequency or
external clock x8 input
• wake-up feature - enabled or disabled
• Interrupt requests - enabled or masked individually for
transmitter and receiver data registers
• clock output - internal clock enabled or disabled to Port
2 (Bit 2)
• Port 2 (bits 3 and 4) - dedicated or not dedicated to serial
I/O individually for transmitter and receiver.
• Serial Communications Hardware
The serial communications hardware is controlled by 4
registers as shown in Figure 14. The registers include:
• an 8-bit control and status register
• a 4-bit rate and mode control register (write only)
• an 8-bit read only receive data register and
• an 8-bit write only transmit data register.
In addition to the four registers, the serial [/0 section utilizes
bit 3 (seria[ input) and bit 4 (seria[ output) of Port 2. Bit 2 of
Port 2 is utilized if the internal-clock-out or external-clock-in
options are selected.

Rx

11

B"
3

Clock

B"

2

10

...-"'--------~

Tx

B"
4

12

•

Transmit/Receive Control and Status (TRCS) Register
TIle TRCS register consists of an 8-bit register of which all 8
bits may be read while only bits 0-4 may be written. The
register IS initialized to $20 on RES. The bits in the TReS
register are defined as follows:

Figure 14 Serial I/O Registers
BitOWU

Bit I TE

Bit 2 TIE

Bit 3 RE

Bit 4 RIE

"Wake-up" on Next Message - set by 1106803
software and cleared by hardware on receipt of
ten consecutive I's or reset of RE nag. I t should
be noted that RE nag should be set in advance of
CPU set of WU flag.
Transmit Enable - set by H06803 to produce
pream ble of nine consecutive I's and to enable
gating of transmitter output to Port 2, bit 4
regardless of the OOR value corresponding to this
bit; when clear, serial I/O has no effect on Port 2
bit4.
TE set should be after at least one bit time of data
transmit rate from thc set-up of transmit data
rate and mudc.
Transmit Interrupt Enable - when set, will permit
an IRQ2 interrupt to occur when bit 5 (TORE) is
set; when clear, the TORE value is masked from
the bus.
Receiver Enable - when set, gates Port 2 bit 3 to
input of receiver regardless of OOR value for this
hit; when clear, serial I/O has no effect on Port 2
bit 3.
Receiver Interrupt Enable - when set, will permit
an IRQ2 interrupt to' occur when bit 7 (RORF) or
bit 6 (OR FE) is set; when clear, the interrupt is
mru.ked.

Transmit/Receive Control and Status Register
76543210

~HITACHI

119

HD6803,HD6803-1--------------------------Bit 5 TORE Transmit,Data Register Empty - set by hardware
when a transfer is made from the transmit data
register to the output shift register. The TORE bit
is cleared by reading the status register, then

writing a new byte into the transmit data register,
TORE is initialized to 1 by RES.
Bit 6 ORFE Over-Run-Framing Error - set by hardware when
an overrun or framing error occurs (receive only).

Rate and Mode Control Register

x

I

6

5

4

X

X

x

3

2

CC1

CCO

I I I

o
SS1

SSO

ADDA : S0010

An overrun is defined as a new byte received with
last byte still in Oat Register/Buffer. A framing
error has occured when the byte boundaries in bit
stream are not synchronized to bit counter. If
WV-tlag is set, the ORFE bit will not be set. The
ORFE bit is cleard by reading the status register,
then reading the Receive Data Register, or by
RES.
Bit 7 RORF Receiver Data Register Full-set by hardware when
a transfer from the input shift register to the
receiver data register is made.lfWV-tlag is set, the
RDRF bit will not be set. The RDRF bit is cleared
by reading the status register, then reading the
Receive Data Register, or by RES.
Rate and Mode Control Register (RMCR)
The Rate and Mode Control register controls the following
serial I/O variables:
• Baud ratc

• format
• clocking source, and
• Port 2 bit 2 configuration
The register consists of 4 bits all of which are wri te-only and
cleared on RES. The 4 bits in the register may be considered as
a pair of 2-bit fields. The two low order bits control the bit rate
for internal clocking and the remaining tWQ bits control the
format and clock select logic. The register definition is as
follows:
.
Bit 0 SSO Speed Select - These bits select the Baud rate for
Bit I SS1 the internal clock. The four rates which may be
selected are a function of the CPU 9
.,

\-SRD

Store Double

Ace

AD R1

A - 00

·• ••
• •
·• ••

• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•

·

·

3 2

1 0

I N Z V

• •

bO

ACe AI

Mj

3

LSRA

I

j

A D--llllllill-o
B

5 4
H

_

Douhle Shift
RighI logicol
Accumulator

124

-

Arithmetic Operation

A7

ASRB
Shift RighI

IMPLIED

= OP
78

Booleanl

I
I
I

C

I @I
I ('[, I
I 6 I

I

Ir-w I

I

I

6

I
I

I

®

I
I

§l

I
I

®

I

I
I
I

I
I

6

@ I

R I

®

I
I

R

I
I

I
I

I

•

R

•

I

I R

•

I
I
I

I
I
I

I
I
I

I
I
I

I

I

I

I

I
I
I
I
I
I
I

I I I
I I I
I R
I R
I R R
I R R
I R R

•
•

8-bits in the "'CPU. The carry is then added to the higher
order 8-bits of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
I mplied Addressing
In the implied addressing mode the instruction gives the
address (i.e., stack pointer, index register, etc.). These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
!l-bits plus two. The carry or borrow is then added to the high
8-bits. This allows the user to address data within a range of
-126 to +129 bytes of the present instruction. These are twobyte instructions.

HITACHI

----------------------------H06803.H06803-t
• New Instructions
In addition to the existing 6800 Instruction Set, the following new instructions are
incorporated in the HD6803 Microcomputer.
ABX

Adds the 8·bit unsigned accumulator B to the 16·bit X·Register taking into account
the possible carry out of the low order byte of the X·Register.
AD DO Adds the double precision ACCD* to the double precision value M:M+I and places
the results in ACCD.
ASLD Shifts all bits of ACCD one place to the left. Bit 0 is loaded witlr zero. The C bit is
loaded from the most significant bit of ACCD.
LDD
Loads the contents of double precision memory location mto the double
accumulator A: B. The condition codes are set according to the data.
LSRD Shifts all bits of ACCD one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCD.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits in accumulator H to obtain a
16·bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register is pushed onto the stack at the address conta11led
in the stack pointer. The stack pointer is decremented by 2.
PULX The index register is pulled from the stack beginning at the current address
contained in the stack pointer +1. The stack pointer is incremented by 2 in total.
STD
Stores the contents of double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBD Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result in ACCD.
BRN
Never branches. If effect, this instruction can be considered a two byte NOP (No
operation) requiring three cycles for execution.
CPX
Internal processing modified to permit its use with any conditional branch in·
struction.
*ACCD·i. the 16 bit register (A:B) formed by concatenating the A and B accumulators. The A·accumu·
lator is the most sillnificant byte.

Table 8 Index Register and Stack Manipulation Instructions
AddreSSing Modes
Pointer Operations

Mnemonic

IMMED.
OP

Compare Ind•• Reg

----_.-

CPX

8C

-4 3,.

-.

DIRECT
OP
9C

--,-------

INDEX
OP

-

5 2 AC 6

"2

EXTND
OP

IMPLIED
DP

-" - "

BC 6 3

DEX
-- - - -Decrement
--- f----Stack Pntr
DES

----

Increment Index Reg

INX

Increment Stack Pntr

INS

Load Index Reg

LOX

CE

Loed Stack Pntr

LOS
STX

liE

Store I nde. Reg

-

DE 4

2
3 3 9E 4 2
OF 4 2
9F 4 2
3

3

EE

5 2 FE
AE 5 2 BE
EF 5 2 FF
AF 5 2 BF

5

3

5

3

5

3

5

3

X-M:M+l

08

3 1 X-l-X
3 1 SP-l-SP
3 1 X + 1- X

31

3

09
34

Decrement Index Reg

Booleanl
ArithmetiC OperatIon

1 SP+l-SP
M-XH,IM+ll-XL
M- SP H . (M+ll-SPL

-+-- -c- 30

3
3

XH - M. XL - 1M + 11
SPH-'v'I.SP L -IM+ll
1 X-l-SP
1 SP+l-X

3A

3

1 B + X- X

Push Data

ABX
PSHX

3C

4

1

Pull Dala

PULX

38

5

XH - MoP' SP - 1 - SP
1 SP + 1 - SP, MIl> - XH
SP + 1- SP,M oP - XL

Store StIck Pntr
Index Reg - Stack Pntr
StIck Pntr'~ Index Reg
Add

STS
TXS
TSX

----

35

XL - MoP' SP - 1 - SP

Condition Code
Reg.ster

2J~_E

5 4 3
H I N Z.V C

• .' I ,
••• I
••••
• •• I
••••
• ) I
• • (1) I
• .(2)1
• .'Y.!.'
• •• •
••• •
•• ••
• •• •
•• ••

·

I

,

•
•
•
•

•
•
•
•
R'.
R •
R •
-

•
.--;-

R

• •
• •
••
••

The Condition Code Register nOle, are listed Ifter Table 10.

_HITACHI

125

H 0 6 8 0 3 . H 0 6 8 0 3 - 1 - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ __
Table 9 Jump and Branch Instructions
Condition Code

Addressing Modes
Mnemonic

Operations

Branch Always
Branch Never
Branch If Carry Clear

Branch If Carry Set

= Zero

Branch If

Branch If ... Zero
Zero
---->._._--

Branch If

--

Branch If Higher

Branch If '" Zero

---'_._----Branch If Lower Or
Same

INDEX
RELATIVE DIRECT
OP
# OP
# OP
#
BRA
20 3 2
BRN
21 3 2
BCC
24 3 2
BCS
25 3 2
BEQ
27 3 2
BGE
2C 3 2
2E 3 2
BGT
BHI
122 3 2
--Eii-E-- 21' 3 2
- - - - f-- - - - - BlS
23 3 2

< Zero

-

20
Branch If Minus
2B
--- ---- --Branch If Not Equal
BNE
26
Zero
- - - - - - f-Branch If Overflow
BVe;
28
Clear
-Branch If Overflow Set
BVS
29
--------Branch If Plus
BPl
2A
---------Branch To Subroutine
BSR
80
Jump
JMP
Jump To Subroutine
JSR
Branch If

-

-

-

-

• • • •
• • • •
• • • •
• •• •
• • • •
• • • •
• • •
• • • •
• • • •
• • • •

None
None

CoO
C=1
Z=1
N (i) V=O
Z + (N (i) V) = 0

·

IC+Z=O
Z + (N (i) V) = 1
C+Z-l

3 2
3 2

N (i) V= 1

3 2

ZoO

,3 2

V=O

3 2

V= 1
N=O

BLT
BMI

Register
5 4 3 2 1 0
H I N Z V C

Branch Test

IMPLIED
EXTND
# OP
OP
#

••

N =1

--------~~

---~----

No Operation

--L

Return From Interrupti

-------

~---

Return From

--

Subroutine
Software Interrupt
Wait for Interrupt

3 2
6 2
90 5

6E 3 2
2 AD 6 2

7E 3 3
BD 6 3

NOP

01

2 1

Advances Prog. Cntr.
Only

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

••
• •

·• • •

• • •
• • •
•• •
• • •
• • •
• • •
• • •
•• •
•• •

•• •
•
•
•
•
•

•
•
•
•
•

•
•
•
•
•
•••
•••
• • •

RTI

3B 10 1

-@-

RTS

39

5 1

•• • • • •

SWI
WAI

3F 12 1
3E 9 1

•
•

5
9

• • • •
• • • •

Tablel0 Condition Code Register Manipulation Instructions
IAddressingModes
Operations

IMPLIED
OP
#

Mnemonic

Clear Carry

CLC

Clear Interrupt Mask

Cli
CLV

Clear Overflow

OC
OE

Condition Code Register
Boolean Operation

2
2

5
H

O-C
0-1

--c-0-A-t---::-2 -+-1-t------,0------------V

4

3
N

2
Z

V

0
C
R

• • • • •
•• R• •• • R
• .

--=0~l?--+-'2~t__'_i--+r-----=--=--=-=-'1--::.---=c'--=-=-=-~--~------- "; • • •
S
-:c
---_ _ ~E_I_____+-,0_F-1f-2-1f-l-+_
1- I
________~ ~~
•
•
SE V
OB
2
1- V
•
•
•
•
S
•
-A-c-cu-m-u-Iaro~-A~-C-C-R---+-- T~A~P_ _ _-+~06~+-'2~+-'~_ _ _ _~A~-~~C~C~R~_ _ _ _ _--_+_~~~----T--~~I0r-=~=~~r---C-C-R--:A~~-m-ul-a;;'~A- ---;;PA
07
2
CCR - A
• I • I.
• • •
----S-E-C------

Set Carry

_Se_t_l_nt!,,:u'p~~!'.."--~
Set Overflow

__

Condition Code Register Notes: (Bit set it test is true and cleared otherwise)

1 (Bit V)
(Bit C)

126

Test: Resull = 1000oo00?
Test: Result ~ 00000000?

(Bit C)
{Sit VI

Test: Decimal value of most significant BCD Character greater than nine? (Not cleared if previously set)
Test: Operand = 10000000 prior to execution?

(Bil V)

Test: Operand

(Bit VI

Test: Set equal to result of N (±) C after shift has occurred.

(Bit N)

Test: Result less than zero? (Bil 15 = 1)

(All)
(Bit I)
(All)

Load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state.
Set according to the contents of Accumulator A.

(Bit C)

Set equal 10 result of Bit 7 (AccB)

= 01111111

prior to execution'

•

HITACHI

----------------------------HD6803,HD6803-1
Table 11

Instruction Execution Times in Machine Cycle

In·
1m·
Ex·
ACCX I:;::;;:. Direct tended
dexed plied

ABA
ABX
ADC
ADO
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
ClI

CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

•
•
•
•

•
•
2

•
2

•
•
•
•
•
•
•
•
•
•

•
•
•

•
•
•
•
•
•
•
2

•
•
2

•
•
2

•
•
•
2

•

•
•

•
•

•

2

3

4
4

2
4

2

•

•

•
•
•
•
•
•

5
3

•
•
•
•
•
•

•

•
•
•

2

•
•
•

•
•
•
•
•
•
•

•
•
•
•
•

•

•

2

•

3

6
4
6

4
4
6
4
6

•

•

6

6

•
•
•

•
•
•

•
•

•

3

4

4

•
•
•
•
•
•
•

•
•
•

•

•
•
•
•

•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•

•
•
•
•
•
•
•
•

6

6

•

•

4
6
6

4

6
6

2

3

•

•

4

5

•

•
•
•

•

•

6

6

•

•
•

•
•

2

3

4

4

•
•

•

6

'.

•
•
•

•

•

6

Re·

•
•
•
•
•
•
•
•
•

•
•
•

•
3

•
•
•
•
•

3
3

3
3
3

•
•
•
•
•
•
•
•
•
•

3

•
3
3
3
3
3

3
3
6

•
•

3
3

2
2
2

•
•
•
•
•
•
•

2

•
•

•
•

•
3
3

•
•

•
•

INX
JMP
JSR
LOA
LDD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RT!
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

•

3

•

1m·
plied

ACCX

lative

HITACHI

•

•
•
•
•
•
•
2

•
•
2

•
•
•
4

•
2
2

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
2

•

•
•
•
2
3

•

•
5

3

4
4
4

•
•
•
•
•

•
•
•
•

2

3

•

•
•
•
•
•

•
•

•

•

3
6
4
5
5
5

3

6
4
5
5

5

6

6

•

•

•

•

•

4

4

•
•

•

•

•

•
•

2

•
•
•
6

•
•
•

•
•
•

•
•
•

2

3

4

4

•
•
•
•

•
•

•
•
•

•
•

4
4

•

5

4

5

4

5

6

•
4
5
5

2

4

5
4

4

6

6

•
•
•

•
•
•
•
•

•
•
•
•

•
•
•

•
•
•
•
•

•
4

•
5

•
10

5

2

•
2
2
2

•
•
•
•
•
12

6

6

•
•
•

•
•
•

•
•
•
•
•
•
•

3
10

6

6

6
6

•
•
•

3

•
•
•
•
•
•
•

Re·
lative

2
2
2
2

•

•

•

•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

•
•
•
•
•
•
•
•
•
•

3

•
9

127

HD6803,HD6803-1---------------------------•

Summary of Cycle by Cycle Operation
Table 12 provides a detailed description of the information
present on the Address Bus. Data Bus, and the Read/Write line
(R/W) during each cycle for each instruction.
This information is useful in comparIng actual with expected
results during debug of both software and hardware as the

control program is executed. The information is categorized in
groups according to addressing mode and number ot cycles per
instruction. (In general. instructions with the same addressing
mode and number of cycles execute in the same manner: ex·
ceptions are indicated in the table).

Table 12 Cycle by Cycle Operation
Address Mode &
Instructions

Data Bus

Address Bus

IMMEDIATE
ADC
ADD
AND
BIT
CMP

2

EOR
LOA
ORA
SBC
SUB

1

I

LOS
LOX
LDD

3

CPX
SUBD
ADDD

4

2

1
2

3
1

2
3
4

Op Code Address
Op Code Address + 1

1
1

Op Code
Operand Data

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F

1
1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

DIRECT

-

ADC
ADD
AND
BIT
CMP

3

EOR
LOA
ORA
SBC
SUB

1
2

3

I
3

STA

1
2

3
LOS
LOX
LDD

4

1
2

3

i

4
STS
STX
STD

I

1
2

4

3
4

CPX
SUBD
ADDD

5

I

1
2

3
4

5
JSR

5

1
2

3
4

5

, Op Code Address

1
1
0

Op Code
Destination Address
Data from Accumulator

Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1

1
1
0
0

Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1

1
1
1
0
0

Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

II Op Code Address + 1
I DestinatIon Address

Op Code Address

I Op Code Address + 1

(Continued]

128

_HITACHI

----------------------------HD6803,HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

INDEXED
JMP

ADC
ADD
AND
BIT
CMP

3

EOR
LDA
ORA
SBC
SUB

---

---------------

-------

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Offset
Low Byte of Restart Vector

1
2

3
4

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data

-~~.

4

,
----

----

STA

4

1
2
3
4

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset

1
1
1
0

Op Code
Offset
Low Byte of Restart Vector
Operand Data

LDS
LDX
LDD
LDD

5

1
2

3
4
5

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

STS
STX
STD

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
0
0

Op Code
Offset
Low Byte of Restar,t Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

6

1
2
3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

1
1
1
1
1
0

Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

1
2

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus FFFF

1
1
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

1
1
1
1
0
0

Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST*

-- --- ------

CPX
SUBD
ADDD

- - - --6

3
4
5
6

----

JSR

6

1
2
3
4
5
6

' Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Stack Pointer
Stack Pointer - 1

--

._-------

• In the TST instructIon, R/W ',ne of the sixth cvcle is "1" level, and AS'" FFFF, DB = Low Byte of Reset Vector.

•

HITACHI

(Continued)

129

H D 6 8 0 3 , H D 6 8 0 3 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - -__
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

EXTENDED
3

1
2
3

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

4

1
2
3
4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data

STA

4

1
2
3
4

Op Code
Op Code
Op Code
Operand

1
1
1

0

Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

LOS
LOX
LDD

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

STS
STX
STD

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

1
2
3

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand

0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1

Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

JMP

ADC
ADD
AND
BIT
CMP

ASL
ASR
CLR
COM
DEC
INC

EOR
LOA
ORA
SBC
SUB

LSR
NEG
ROL
ROR
TST*

CPX
SUBD
ADDD

6

4
5
6
6

1
2
3

4
5
6

JSR

6

1
2
3

4
5
6

Address
Address + 1
Address + 2
Destination Address

• In the TST instruction, R/W line of the sbeth cvcle is ","Ievel. and AS

130

$

0
0
1
1
1
1
1

0
0

=FFFF. DB = Low Bvte of Aeset Vector.

HITACHI

(Continued)

-----------------------------HD6803.HD6803-1
Table 12 Cycle by Cycle Operation (Continued}
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
ABX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

Address Bus

2

Op Code Address
Op Code Address + 1

Op Code
Op Code of Next Instruction

1
1

i

!

3

ASLD
LSRD

3

DES
INS

3

INX
DEX

3

PSHA
PSHB

3

--"

TSX

3

TXS

3

PULA
PULB

4

PSHX

4

PULX

5

RTS

5

WAI"

1
2

Data Bus

9

1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4

Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Address Bus FFFF
OP Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Po inter +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1

5

Stack Pointer + 2

1

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1

1
1
0

1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3

1
1
1
1
1
1
1
1
1
1
1
1
1
1

0

0

I
I

Op Code
Irrelevant Data

! Low Byte of Restart Vector
lop Code
j Irrelevant Data
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Irrelevant Data
Index Register (Low Order Byte}
Index Register (High Order Byte i
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte}
Index Register (Low Order Byte}
OpCode
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte}
Address of Next Instruction
(Low Order Byte}
Op Code
Op Code of Next Instruction
Return Address (Low Order Byte}
Return Address (High Order Byte}
(Continued}

•

HITACHI

131

HD6803,HD6803-1--------------------------Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Cycles

Cycle
;:

5
6
7

WAI"*

8
9
MUL

10

SWI

10

12

Stack
Stack
Stack
Stack
Stack

Pointer
Pointer
Pointer
Pointer
Pointer

-

2
3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Op Code Andress
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

5

Stack Pointer + 2

1

6

Stack Pointer + 3

1

7

Stack Pointer + 4

1

8

Stack Pointer + 5

1

9

Stack Pointer + 6

1

10

Stack Pointer + 7

1

10
11

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)

1
1
0
0
0
0
0
0
0
1
1

12

Vector Address FFFB

(He~)

1

1
2
3
4
5
6
7

8
9

Rn---

RIW
line
0
0
0
0
0

Address Bus

10
1
2
3
4

1
2
3
4
5
6
7

8
9

Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code
Irrelevant Data
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
OpCode
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)'
Next Instrliction Address from
Stack (Low Order Byte)
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
(Continued)

• * While the MPU is in the "Wait" state. its bus state will appear as a series of MPU reads of an address which IS seven locations less thap the
original contents of the Stack Pointsr. Contrary to the HD6800. none of the ports are driven to the high impedance state by a WAf
instruction.

132

•

HITACHI

----------------------------H06803,H06803-1
Table 12 Cycle by Cycle Operation (Continued'
RElATIVE
Address Mode &
Instructions
BCC
BCS
BEQ
BGE
BGT
BRN

BHT
BlE
BlS
BlT
BMT

Cycles

Cycle

3

1
2

BNE
BPl
BRA
BVC
BVS

3

BSR

6

1

2
3
4

5
6

R/W
Line

Address Bus

#

Data Bus

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Branch Offset
low Byte of Restart Vector

-----Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack POinter
Stack POinter - 1

1
1
1
1
0
0

Op Code
Br anch Offset
low Byte of Restart Vector
Op Code of Next Instruction
Return Address (low Order Byte'
Return Address (High Order Byte'

• Summary of Undefined Instruction Operations

When the op codes (4E, 5E) are used to execute. the MPU
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the

The HD6803 has 36 underlined instructions. When these are
carried out, the contents of Register and Memory in MPU
change at random.

LSI.

Table 13 Op codes Map

HD6803 MICROPROCESSOR INSTRUCTIONS
OP
CODE

~
LO

a

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

4
5
6
7
B
9
A
B
C

1101

0

-----0000

NOP

1
2
3

-----

~

..-----..------

LSRD (+11
ASLD (+11 ~
TAP
TAB
TPA
TBA
INX (+11
DEX (+11 DAA
CLV
~
SEV
ASA
CLC
~

..------

SEC

1110
E
F
1111
BYTE/CYCLE
[NOTESI

0001
1
SBA
CBA

a

CLI
SEI
112

/

ACCA orSP
ACCB or X
ACC ACC INO EXT
A
B
IMM lOlA liND I EXT IMM lOlA liND LEXT
0010
0011
0100 0101 0110 0111 1000\1001\101011011 110011101 \1110jll1.'
2
3
4
5
7
6
S I 9 I A I B
C I D I E I F
0
BRA
TSX
SUB
NEG
CMP
1
BRN
INS
~+
-::~-==BHI PULA (+11
SBC
2
BLS PULB (+11
COM
SUSD (+21
ADDDI;::~~~=-~
4
AND
DES
LSA
BCC
5
BIT
BCS
TXS
LDA
BNE
PSHA
AOA
6
STA
STA
BEQ
PSHB
ASA
j7
EOA
BVC PULX (+21
ASL
S
ADC
9
BVS ATS (+21
ROL
A
ORA
BPL
ABX
DEC
ADD
B
BMI
RTI (+71
: CPX (+21
LDD (+11
INC
BGE PSHX (+11
'C

----

BLT

~.

,-/'
1/2

BGT
BLE
2/3

MUL (+71
WAII+61
SWII+91
1/3

II Undefined Op codes are marked with
2) (

·

Ll

--

-- .. -1/2

~

Ll

.

·
r1.t~j

TST

JMP (-31

CLR
112
2/6

I·

·

JSR (+21

• (+lil
3/6

2/2

LDS 1+11
STS 1+11
2/3

I

2/4

(+1~

STD 1+11

• (+11

LOX 1+1)
STX (+1)

•

3/4

.

2/2

I 2/3 I 2/4

/0
I

E
F

\ 3/4

.

) indicate that the number in parenthesis must be added to the cycle count for that instruction.

3) The instructions shown below are all 3 bytes and are marked with ......
Immediate addressing mode of SUBD. CPX. LOS. ADDD. LDD and LOX Instructions. and undefined op codes

ISF,CD, CFI.

4) The Op codes (4E. 5E) are 1 byte! ... cycles instructions, and are marked with

$

HITACHI

"If If"

133

-

:I:

....

Co>

C

0)

~
:I:

C

0)

~
'tJ

•
l:

~

()

~

'SCI

= TIE·TORE + RIE'(RORF + ORFEI

Vector'" PC
NMI
SWI
IRQ,
ICF
OCF
TOF
SCI

Figure 16 Interrupt Flowchart

FFFC FFFO
FFFA FFFB
FFFB FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFF~

Non-Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFEI

----------------------------HD6803,HD6803.1

Address Bus

Data Bus

Fi9ure 17 HD6803 MPU Expanded Multiplexed Bus

_HITACHI

135

HD6805S1--~---------­
MCU (Microcomputer Unit)
The HD680SS1 is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD
6800-based instruction set.
The following are some of the hardware and software
highligh IS of the MCU.
• HARDWARE-FEATURES
• 8-Bit Architecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 1100 Bytes of User ROM
• Internal 8·Bit Timer with 7-Bit Prescaler
• Vectored Interrupts - External and Timer
• 20 TTL/CMOS Comll!!tible -I/O Lines; 8 Lines LED
Compatible
• On-Chip Clock Circuit
• Self-Check Mode
• Master Reset
• Low Voltage Inhibit
• Complete Development System Support by Evaluation
kit
• 5 Vdc Single Supply
• Compatible with MC6B05P2
• SOFTWARE FEATURES
• Similar to HD6800
• Byte Efficient Instruction Set
• Easy to Program
• True Bit Manipulation
• Bit Test and Branch Instructions
• Versatile Interrupt Handing
• Powerful Indexed Addressing for Tables
• Full Set of Conditional Branches
• Memory Usable as Registers/Flags
• Single Instruction Memory Examine/Change
TIMER
• 10 Powerful Addressing Modes
• All Addressing Modes Apply to ROM, RAM and I/O
• Compatible with MC6B05P2

Pori
A

HD6B05S1P

(DP-28)
• PIN ARRANGEMENT

Vss
iN'f

RR

Vee

A,

A,

EXTAL

A,

XTAL

A.

NUM

A,

TIMER

HD68Q5S1

c.
C,

A.

C,

B,

C,

B,

B.

B,

B,

B.

B,

B,

(Top View)
• BLOCK DIAGRAM

Cpu

..
..

B

A,
A,
A,

Indell
Regtlle,

Control
X

Condition

110 "'.
Lines A.
A,

Pori
A

Oeta

R"

ROO

e"

Cod'
S

Regllter CC

S

Stack
POinter

Cpu

SP

Program

Counte,
3

"Htgh .. peM

Program

Count8'
"Low" pel

1100 M8

ROM
Self(hKk
ROM

136

•

HITACHI

ALU

---------------------------------------------------------------HD6805S1
• ABSOLUTE MAXIMUM RATINGS
Item

.
.

Value

Symbol

Supply Voltage

Vee

Input Voltage (EXCEPT TIMER)
Vi"

Unit

-0.3-+7.0

V

-0.3-+7.0

V

-0.3-+12.0

Operating Temperature

To","

0-+70

V
DC

Storage Temperature

T stg

- 55-+150

DC

Input Voltage (TIMER)

• With respect to Vss (SYSTEM GNO)
(NOTE)

Permanent LSI damage may occur If maximum ratings are exceeded. Normal operation should be under

recommended operating conditions. If these conditions are exceeded.

It

could affect reliability of LSI.

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (VCC·5.25V ± 0.5V. Vss=GND. Ta=o-+70DC. unless otherwise noted )
Item
Input "High" Voltage

Symbol

min typ

-

Vee

V

INT

3.0

-

Vee

V

2.Q

-

Vee

V
V

V'H

Timer Mode

2.0

-

Vee
11.0
0.8

-0.3

-

0.8

V

-0.3

-

0.6

-0.3

V
V

Self-Check Mode

9.0

RES

-0.3

INT

Input "Low" Voltage

max Unit

4.0

All Other
Input "High" Voltage Timer

Test Condition

RES

EXTAL(Crystal Mode)

V'L

V
V

-

0.8

-

-

700

Low Voltage Recover

Po
LVR

-

4.75

V

Low Voltage Inhibit

LVI

-

-

1--.

V

All Other
Power Dissipation

TIMER
INT

Input Leak Current.

"L

V,n=0.4V-V ee

EXTAL(Crystal Mode)

4.0

-20

-

-50

-

-1200

mW

20

IJ.A

50

IJ.A

0

IJ.A

• AC CHARACTERISTICS (Vcc=5.25V ± 0.5V. Vss=GND. Ta=O - +70DC. unless otherwise noted.)
Item
Clock Frequency
Cycle Time

Symbol

-----

fe'

4.0

1.0

-

10

IJ.s

-

3.4

-

MHz

-

-

ns

-

-

ns

-

-

ns

-

-

100

ms

,100

-

-

ms

-

30
10

pF
pF

t'WL

RES Pulse Width

tRWL

TIMER Pulse Width

tTWL

Oscillation Start·up Time (Crystal Mode)

tose
tRHL

I
I

C,n

•

max Unit

tCYC

INT Pulse Width

Input Capacitance

typ

-

f EXT

XTAL
All Other

min
0.4

Oscillation Frequency (External Resistor Mode)

Delay Time Reset

Test Condition

Rep=15.0kS!±1 %

tCYC +

250

t Cyc +

250
t cvc +

250
C L=22pF±20%.
Rs =60n max.
External Cap. = 2.21J.F
V;n=OV

HITACHI

-

,
,

MHz

137

HD6805S1--------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee
Item

=S 2SV ± O.SV

Port A
Output "High" Voltage

Output "Low" Voltage

Port B

VOH

Ta

=0 -

IOH

= -10j.lA
= -100j.lA
IOH = -200j.lA

3.S

-

IOH

2.4
2.4
1.S

-

-

-

-

V

-

-

V

0.4

V

-

0.4

V

=-l00j.lA
= 1.6mA
IOL =3.2 rnA
IOL = lOrnA

IOH

2.4

Port A and C

IOL

-

VOL

Port B
Port A, B, C

;

-

VIH

2.0

VIL

-0.3

=0.8V
Yin =2V
Yin =0.4V -

Port B, C

-

-SOO

Yin
IlL

+70"C, unless otherwise noted.)
typ
max
Unit

min

Port C

Port A

Input Leak Current

= GND

IOH - -1 rnA

Input "High" Voltage
Input "Low" Voltage

Vss

Test Condition

SVmbol

-300
Vee

TTL Equiv. (Port B)

-20

3.2mA

V

V

1.0

V

Vee

V

0.8

V
j.lA

-

.j.lA

20

j.lA

TTL Equiv. (Port A and C)

vee

vee
li~

V

1.2k!l

•

Test Point
0-

Test Point

Vi

Ii

=

1.6mA

2.4kfl

Vi
40pF

30 pF

12k!l

24 k!l

(NOTE} 1. Load capacitance include. the floating capacitance of tt.e probe and the jig etc.
2. All diod .. are 152074 (!3l or equivalent.
Figure 1 Bus Timing Test Loads

• SIGNAL DESCRIPTION

• TIMER

The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.

This pin allows an external input to be used to decrement the
internal timer circuitry. Refer to TIMER for additional informa.
tion about the timer circuitry.

•

VCC and Vss

Power is supplied to the MCU using these two pins. VCC is
+5.25 V ±O.5 V. VSS is the ground connection.
•

INT

This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.

•

XTAL and EXTAL

These pins provide connections for the on·chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stabilitylcost tradeoffs. Refer to INTERNAL OS·
CILLATOR OPTIONS for recommendations about these inputs.

138

•

•

RES

•

NUM

This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MeU. Refer to
RESETS for additional information.
This pin is not for user application and should be connected
to VSS.

•

Input/Output Lines

(Ao - A 7 , Bo - B7 , Co - C31

These 20 lines are arranged into tow 8·bit ports (A and B)
and one 4-bit port (C). All lines are programmable as either
inputs or outputs under software control of the Data Direction
Registers (DDR). Refer to INPUT/OUTPUT for additional
information .

HITACHI

---------------------------------------------------------------HD6805S1
• MEMORY

increments when it pulls data from the stack; A subroutine call
will cause only the program counter (PCH, Pel) contents to be
pushed on to the stack.

The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers
are pushed onto the stack in the order shown in Figure 3. Since
the stack pointer decrements during pushes, the low order byte
(PCl) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer

o

7

000

o

~'

Page Zero
ROM
(128 Bytes)

255
256

$0 F
$10 o

Not Used
ROM
(704 Bytes)

959
960

Port B
1

1

1

$783
$7 84

1

$000
$001

I

$002

Port C

3

Not Used

$003

4

Port A DDR

$004'

Port B DDR

$005'

I

$006'

5

$3B
$3C

Self Check
ROM
(116 Bytes)

2039
2040

1

Not Used

6

Main
ROM
(964 Bytes)

1923
1924

Port A

o

2

3

0

2

$07 F

4

5

6

7

$00o

I/O Ports
Timer
RAM
(1288ytes)

127
128

Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user p;ogram.
If the user's program is in this location, it will be removed when
manufacturing mask for production.

Port C DDR

7

Not Used

$007

8

Timer Data Reg

$008

9

Timer CTRL Reg

$009
$OOA

0
Not Used (54 Bytes)

$7F
$7F

Interrupt

63
6

Vectors

~

St~ck

12

ROM
(8 Bytes)

$07F

'Write only registers

$7F F

2047

$03F
$040

RAM (64 Bytes)

Figure 2 MCU Memory Configuration

6

0-4

5

,,

4

3

o

o

2

1\
Condition
1 Code Aegister

Pull

--'l
°I

L-_ _ _ _
A_ _ _

0+1

X
L-______________

Accumulator

Index Register

0-3

Accumulator

n+2

10

n-2

Index Register

n+3

IL_______P_C_ _ _ _ _ _.....I Program Counter

n-1

1

1

1

1

1\

PCL"

PCH"

10

n+4

5 4

~O

°

I'-0....1,-0....11-0--,-10....1L..-1....1_1....I __s_p_--'I

Stack Pointer

n+5
Condition Cod. Aegister

Push
" For subroutine calls, only PCH and PCL ara stacked

carry/Borrow

Figure 3 Interrupt Stacking Order

Zero
Negative
Interrupt Malk
~------ Half carry

Figure 4 Programming Model

•

HITACHI

139

HD6805S1-----------------------------------------------------------• REGISTERS

Half Carry IH I

The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.

Used during arithmetic op'erations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
Interrupt III
This bit is set to mask the timer and external in terrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.

• Accumulator (AI
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.

• Indell Reginer IXI
The index register is an 8·bit register used for the indexed
addressing mode. It contains an 8·bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter IPCI
The program counter is an II·bit register that contains the
address of the next instruction to be executed.
• Steck Pointer ISPI
The stack pointer is an II·bit register that contains the
address of the next free •location on the stack. Initially, the
stack pointer is set to location S07F and is decremented as data
is being pushed onto the stack and incremented as data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 0000 11. During a MCU reset or
the reset stack pointer (RSP) instruction, the stack pointer is set
to location S07F. Subroutines and interrupts may be nested
down to location S061 which allows the programmer to use up
to 15 levels of subroutine calls.
• Condition Code Register ICCI
The condition code register is a S·bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each
individual condition code register bit is explained in the
following paragraphs.

Negative IN I
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).

Zero IZI
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.

Carry/Borrow ICI
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.

• TIMER
The MCU timer circuitry is shown in Figure 5. The 8·bit
counter, the Timer Data Register (TOR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer inter·
rupt request bit (bit 7) in the Timer Control Register (TCR) is
set. the CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $7F8 and $7F9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer inter·
rupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a time interrupt from
being processed.
, The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal q,2
signal. When the q,2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user

~,

(lntornall

TlR; Timer Interrupt Roquest
TIM; Timer Interrupt Mask

Timer
Input

Pin

r-·---'

I
I

I
I

I _____ .tI
&.
I
I

Manufacturing
Mask Option.

Write

Read

Figure 5 Timer Block Diagram

140

•

HITACHI

Write

Read

-------------------------------HD6805S1.
to easily perform pulse.width measurements. The TIMER input
pin must be tied to Vee, for ungated ~2 clock input to the
timer prescaler. The source of the clock input is one of the
options that has to be specified before manufacture of the
MCU. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter (TOR). The timer continues
to count past zero, falling through to $FF from zero and then
continuing the count. Thus, the counter (TOR) can be read at
any time by monitoring the TOR. This allows a program to
determine the length of time since a timer interrupt has occur·
red and not disturb the counting process.
At power·up or reset, the prescaler and counter are initialized
with all logical ones; the timer interrupt request bit (bit 7) is
cleared, and the timer interrupt mask bit (bit 6) is set.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.

~ INT

•

SELF CHECK

The self·check capability of the MCU provides an internal
check to determine if the part is functionaL Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz.
•

RESETS

The MCU can be reset three ways; by initial power·up, by
the external reset input ~ and by an optional internal low
voltage inhibit circuit, see Figure 7. All the I/O port are initia·
lized to input mode (OORs are cleared) during reset.
During power·up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.

A, 27
A, 26

28 RES

$

2.2J'F

c:

+9V

7

A, 25

A.~
XTAL

A, 23
A, 22

EXTAL

A, 21

A,~
HD6805S1
TIMER (Resistor option)

B,~

~

V cc

1~;: .iii.::
'C
b
1~J!

.::

NUM

B, 17
B. 16

8

c,

B,~

9

C,

B, 14

10

c,

B, 13

J~n

tC :::.:'

)',,3~R
v

~ (.;:).. II
C,
~

~'!,

B, 18

Bo 12

Vee = Pin 3
VSS • Pin 1

* Refer to Figure 9 about crvstal option

Figure 6 Self Check Connections

RES

Pin

---------r'

Internll

Rent _ _ _ _ _ _ _ _ _ _-J

Figure 7 Power Up and RES Timing

•

HITACHI

141

HD6805S1--------------------------------------------------------------• INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a mini-.
mum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure II.

Part,of

H06805S1
MCU

Figure 8 Power Up Reset Delay Circuit

5 XTAL

5 XTAL
MaH
4m
xZ CJ

4 EXTAL

HD6805S1
MCU

4 EXTAL

H06805S1
MCU

22PF±20%::;:t:;:

Crystal

Approximately 25% Accuracv
External: Jumper

Vee

..

5

~

R
External

Clock

XTAL

.... ".".--

5 XTAL

4 EXTAL

H06805S1
MCU

4 EXTAL

H06805S1
MCU

No

Input

Connection

External Clock

ApprOXimately 15% Accuracy
External Resistor

CRYSTAL OPTIONS

RESISTOR OPTIONS

Figure 9 Internal Oscillator Options

5
C,

XTAL~~EXTAL
5

~~

4

>
u
c

3

'\.

.a
~

AT - Cut Parallel Resonance Crystal
Co = 7 pF max.
1= 4 MHz IC, =22pF±20%1
Rs· 60n max.

~

u.

2

~

~

~ po......
~

Figure 10 Crystal Parameters

o

5

10

15

20

25

30

35

40

Resistance (knl

Figure 11 Typical Resistor Selection Graph

142

J

Vee· 5.25V_
T A -25·C

\,

.

:I:

!

I

\

4

_HITACHI

r-

45

50

------------------------------------------------------------HD6805S1

1-1
7F _SP

o _DOR',

Stack
PC,X,A,CC

CLR I NT Logic
FF - Timer
7 F _ Prescaler

7F _TCR

Y

TIMER

Load PC From
Reset: $7FE, $7FF

Load PC From
SWI :$7FC, $7FO
i1If'r:$7FA, $7FB
TIMER :$7FB, $7F9
Fetch
Instruction

SWI

Y

Execute
Instruction

Figure 12 Interrupt Processing Flowchart

Oat8
Direction

Rlgister
Bit

Figure 13 Typical Port 1/0 Circuitry

•

HITACHI

1
1
0

OUIPut
0818 Bit

OUIPUI
St811

Inpullo
MeU

0
1

0
1
3·$t811

Pin

0

143

HD6805S1--------------------------------------------------------------•

INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (IJilT) input pin, the internal timer
interrupt request, and a software interrupt instruction (SWI).
WheJl any interrupt occurs, processing is suspended, the present
CPU state is pushed onto the stack, the interrupt bit (I) in the
Condition Code Register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. The interrupt
service routines normally end with a return from interrupt
(RTI) instruction which allows the CPU to resume processing
of the program prior to the interrupt. Table I provides a listing
of the interrupts, their priority, and the vector address that
contain-the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given in
Figure 12.

Table 1 Interrupt Priorities
Interrl!pt
RES
SWI
INT
TIMER

Priority
1

2
3
4

Vector Address
$7FE and $7FF
$7FC and $7FD
$7FA and $7FB
$7F8 and $7F9

•

INPUT/OUTPUT
There are 20 input/output pins. All pins are programmable
as either inputs or outputs under software- control of the corresponding Data Direction Register (DDR). When programmed
as outputs, all I/O pins the latched output data is readable as
input data, regardless of the logic levels at the output pin due to
output loading (see Figure 13). When port B is programmed
for outputs, it is capable of sinking 10mA on each pin (VOL =
IV max), All input/output lines are TTL compatible as both
inputs and outputs. Port A is CMOS compatible as outputs, and
Port Band C are CMOS compatible as inputs. Figure 14 provides some examples of port connections.

• BIT MANIPULATION
The MCU has the ability to set or clear any single random
access !l)emory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 15
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crOSSing detector circuit and that bit I of port A is connected to
the trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven ROM locations,
provides turn-on of the TRIAC within 14 microseconds of the
zero crossing. The timer could also be incorporated to provide
turn-on at some later time which would permit pulse-width
modulation of the controlled power.

B.
o
o
o
o

Port A

o

Port B

o
o
o

B,
Port A Programmed as output Is), driving CMOS and TTL Load directly.
la)

Port B Programmed as output Is), driving Oarlington-base directly.
Ib)

+V

+V

R

R

C.
PortC

Port B

o
o
o
o
o
o
o
o

CMOS Inverter

C,

Port B Programmed as output Is), driving LEOls) directly.
lei

Port C Programmed as output Is), driving CMOS loads, using external
pull.up resistors.

Figure 14 Typical Port Connections

144

•

HITACHI

(d)

------------------------------------------------------------HD6805S1

··
·
··
·
•
•

SELF t

BRClR 0, PORT A, SELF t
BSET t, PORT A
BelR I, PORT A

Figure 15 Bit Manipulation Example
• ADDRESSING MODES
The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 16. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 17. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 18. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instruc·
tions are three bytes long.
• Relative
Refer. to Figure 19. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pc)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offsetl
Refer to Figure 20. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (8-bit Offset)
Refer to Figure 21. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 5 II low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16·bit Offset)
Refer to Figure 22. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.

• Bit Set/Clear
Refer to Figure 23. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 24. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
(SOO·$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condi·
tion is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 25. The implied mode of addressmg has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All intplied addressing instructions are one byte long.
• INSTRUCTION SET
The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modity!Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are lIsed on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control Instructions
The control instructions control the MCV operations during
program execution. Refer to Table 6.
• Alphabeticallisting
The complete instruction set is given in alphabetical order in
Table 7.
• OpcodeMap
Table 8 is an opcode map for the instructions used on the
MCV.

_HITACHI

145

HD6805S1--------------------------------------------------------------lEA
j

I

I

Melorv

I

j

j
j

t

j

I

Adder

j

8
A6

05BF

Fa

A
Fa
IndFq

I

I

I

I
I

I
Prog Count

I
I

05CO
CC

I
,

I

Stack Point

,

I
I

PROG LOA #$F8 05BE

~

j

§
,
I

,I

Figure 16 Immediate Addressing Example

t

,,
,I

I

FCB

32

I

I
j
j
j
j

j

CAT

lEA

Memory

j

/

1
Adder

~

A

ooto

20

004B

I

004B

20

I

Index Reg

I
I

I

PROG

LOA

CAT

0520

B6

052E

4B

Stack Point

I
I

I
Prog Count
052F
CC

t@
j

I

I

I

I
I

I

:

I

Figure 17 Direct Addressing Example

146

•

HITACHI

I
I
I

------------------------------------------------------------------HD6805S1

Memory

,•

,•

~

,

PROG

LOA

CAT

-~1

O4OA

06

040B

ES

64

40
'nd•• Reg

Stack Point

I
I

I

FCB

A

I

I

CAT

0000

Prog Count

040C

40

06ES

CC

Figure 18 Extended Addressing Example

lEA
Memory

I
I

,,,
I

I

~
PROG

BEQ

PROG2

04A7

27

04A8

18

I

/

Adder

f
OR

t

~

l-

0000

A

I
I
I

Inde. Reg

Stack Point

I

I
I
I

Prog Count

i

1

04Cl

cc

I

z

I

I

I

~

I

I

~

I

I
I

I

I

04Cl

I

!

Figure 19

Relative Addressing Example

•

HITACHI

147

HD6805S1--------------------------------------------------------------lEA
Melorv

,

I

TABL

I

I

I
I
I

I

I

I

I

OOBS

/'

Adder

t

I

I

~

o!o

4C

FCC I Lli OOBS

I

A
4C

49

BS
I

PROG

LOA

X

I

Index Reg

I

I

Stack Point

""~

[
Prog Count

05F5
CC

@
I

Figure 20 Indexed (No Offset) Addressing Example

lEA
Me!orv
I
I

I

TABL

,I
I

FCB

#BF

00S9

BF

FCB

#86

008A

S6

FCB

#OB

OOSB

DB

FCB

#CF

OOSC

CF
I
I

I

t

/'

I

OOSC

Adder

~

A
CF

I

,

I

Index Reg

J

I

03

I

Stack Point

PROG

LOA

TABL. X 075B

E6

075C

B9

I

I
I

I

Figure 21

148

I

I

Prog Count

Indexed (S·Sit Offset) Addressing Example

_HITACHI

0750
CC

I

------------------------------------------------------------HD6805S1
lEA

L

Melory
i

t

I

I

lOA TABl. X 0692
0693
0694

Adder

I

'"

A
DB

I
I

JJ

#BF

077E

BF

FCB

#86

077F

86

FCB

#oB

0780

DB

FCB

#CF

0781

CF

---i
I

02

I
I
I

Prog Count

0695
CC

I

FCB

I

Index Aeg

Stack Point

11

07

7E

I

TABl

L

~
~

I
PAOG

t

I

I

I

0780

I

I

Figure 22 Indexed (16·Bit Offset) Addressing Example

Memory

POATB

EQU

BF

0001

A
0000
Index Reg

PAOG BClA 6. POAT B

058F
0590

10

Stack Point

t - - -0- 1- - ;

Prog Count

0591
I

I

CC

~
Figure 23 Bit Set/Clear Addressing Example

•

HITACHI

149

HD6805S1

PORT C

EaU

2

FO

0002

A

Index Reg

Stack POint

PROG BRCLR 2. PORT C. PROG 2

0574

r------'
05

Prog Count

0575

02

0594

0576r-----1D~---rr----~

CC

,

§
I

Figure 24 Bit Test and Branch Add resslng
. Example

EA
Memory

I

,I

§
I,

PROG

TAX

A

I

'~A~

05B8

,

CC

I

~
I

I
I

I
I

I

I

!

I
I

Figure 25

150

Implied Addressing Example

•

HITACHI

---------------------------------------------------------------HD6805S1
Table 2 Register/Memory Instructions

Function

I
I MnemOniC

Addressing Modes

~"-------""-'"--------__,___----~:~=r~~ln~d-ex-e~d----TI--~ln-d7."-X.~d~--.---~I~~~.-Q-d~--Immediate

op

#

I

Direct

#

Op

#

Extended

Op

#

Code Bvtes Cycles Code Bytes Cycles Code

Load Alrom Memory

LOA

A6

2

2

B6

2

4

C6

Load X Irom Memory
LOX
S.oreAinM.mory
STA
--S.-o-ro-X--in-M-.-m-o--'ry'----'f-ST-

AE

2

2

BE
B7

2
2
t--- 2

4_
5
5

CE
C7
CF

BB

2

4

CB

X-

Add Memory to A

~-f--::- r--_-- -8F

ADD

AB

2

2

#

(No Offset)
#

Op

#

I

(la·Bit Offstt)

IB·Bit Offset)

I Op

#

#

#

#

Qp

#

Bvtes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles

~__ ~_ ~-~~t~
3
-=5-__+-=-F-=E--l----=-1 -"L~- ~_
3
3

6
6

F7
FF

1±5
1
5

3

5

FB

1

1

4

2

5

06

3

6

E7
EF

2
2
2

5
6
6

DE
07
OF

3
3
3

6
7
7

EB

2

5

DB

3

8

Add Memory and

AOC
A9
2
2
B9
2
4
C9
3
5
F9
1
4 ! E9
2
5
09
3
6
~Qv~ry~t=o~A'_________+-______f-__+-__+-__--l-____l_----l---_+--_+--~----+_--f-----~~"~--__l_--_+--_+___+---Subtract Memory
SUB
AO
2
2
BO
2
4
CO
3
5
FO
,1
4 I EO
2
5
DO
3
6

~!~;~c~:::ry from

sse

A2

2

2

82

2

4

C2

3

5

F2

1

4

E2

2

5

02

3

6

__A~N~O__'M~e~m__'O~ry~to__'A~__+_~A--'N~0--_+~A~4~~2_+~2'---~B--'4_+~2C-j--4'___+-C4~4--3~+-~5_+--F4~--1'---+--4--+-E-4_+---=-2_+--5~+-0~4_+--=3~f_6~
OR Memory with A
ORA
AA
2
2
BA
2
4
CA
3
5
FA
1
4
EA
2
5
OA
3
6
Exclusive OR Memory

with A
Arithmetic Compare A

with Memory
Arithmetic Compare X

EOR

AS

BB

CB

FS

ES

OS

CMP

Al

B1

Cl

Fl

El

01

B3

C3

F3

E3

03

F5

E5

FC

EC

4

DC

FO

ED

8

DO

CPX

A3

Bit Test Memory with A
(Logic.1 Compare)

BIT

AS

B5

C5

Jump Unconditional

JMP

BC

CC

Jump to Subroutine

JSR

BO

CD

with Memory

3
4

6

05

Table 3 Read/Modify/Write Instructions
Addressing Mode.
Function

Implied (A)

Mnemonic

Implied (X)

Indexed
(No Offset)

Direct

Indexed
(8·Bit Offset)

Op
Op
Op
Op
Op
#
#
#
#
#
#
#
#
#
#
Code 8yte. Cycle. Code Bytes Cycle. Code Byte. Cycle. Code Byte. Cycle. Code Byte. Cycles
Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

7

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Cle.r

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

Negate
(2's Complementl

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7
7

Rotate Loft Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Loft

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7
7

Logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

Arithmetic Shift Right

ASR

47

1

4

57

1

4

31

2

6

77

1

6

67

2

1

Arithmetic Shift Loft

ASL

48

1

4

58

1

4

38

2

6

18

1

6

68

2

1

TISt for Negative or
Zero

TST

40

1

4

50

1

4

3D

2

6

10

1

6

60

2

1

_HITACHI

lSI

HD6805S1--------------------------------------------------------------Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic

Function

Op
Code
20
21

#

#

Bytes
2
2
2

Cycles
4
4
4

2

Branch Always
Branch Never
Branch IF Higher

BRA
BRN
BHI

Branch I F lower or Same
Branch I F Carry Clear
(Branch IF Higher or Same)

BlS

Branch I F Carry Set

BCS
(BlO)

25

2

4
4
4
4

25

Branch IF Not Equal
Branch I F Equal

BNE

26

2
2

4
4

BEO

Branch I F Half Carry Clear

BHCC
BHCS

27
28

2
2

4
4
4

22
23
24
24

BCC
(BHS)

(Branch IF lower)

Branch I F Half Carry Set

2
2

BPl

29
2A

2

Branch I F Plus
Branch I F Minus

2

4

BMI

2B

4

Branch I F Interrupt Mask Bit is Clear
Branch I F Interrupt Mask Bit is Set

BMC
BMS

2C
20

2
2

Branch I F Interrupt Line is low

Bil

2E

2

4
4
4

Branch IF Interrupt Line is High

BIH

2F

2

4

Branch to Subroutine

BSR

AD

2

8

2

Table 5 Bit Manipulation Instructions
Function

Bit Set/Clear

Mnemonic

Branch IF Bit n is set
Branch I F Bit n is clear

BRSET n (n-O ..... 7)
BRClR n (n=O ..... 7)

Set Bit n

BSET n (n=O ..... 7)
BClR n (n=O ..... 7)

Clear bit n

Addressing Modes
Bit Test and Branch
Op
#
#
#
Cycles
Cycles
Code
Bytes

Op
Code

Bytes

-

-

-

10+2'n

2

11+2'n

2

#

2'n
01+2'n

3
3

10
10

7

-

-

-

-

7

-

-

Table 6 Control Instructions
Implied
Function

152

Mnemonic

Transfer A to X

TAX

Transfer X to A
Set Carry Bit

TXA
SEC

Op
Code
97
9F
99

#

#

Bytes

Cycles

1

2

1
1

2
2

Clear Carry Bit

ClC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit
Software Interrupt

CLI
SWI

9A

1

2

1
1

11

Return from Subroutine

RTS

83
81

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP
NOP

9C
90

1
1

2

No·Operation

$

HITACHI

6

2

---------------------------------------------------------------HD6805S1
Table 7 Instruction Set

Mnemonic
Implied
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BRSET
BSET
BSR
ClC
Cli
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lOA
lOX

Immediate
x
x
x

ExDirect tended

x

x
x
x
x

x

x

Relative

x
x
x

Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
X
x
x
x
x
x

Condition Code
Bit

I

Bit
Setl
Test &
Clear i Branch

I

!
,

x

x

x

x

x

x
x
x
x
x
x
x
x
x

x
x

x

x

x

)(

x
)(

)(

x

x
x

)(

x

x

)(

)(

)(

x
x
x

x
x

x

x

x
x

x

)(

x
x
x

)(

x

x

)(

)(

)(

x

x
x

x
x

x

x

)(

)(

)(

)(

)(

)(

)(

)(

)(

)(

Condition Cod. Symbols:
H
Half Carry IFrom Bit 3)
I
Intorrupt Mask
N
Negative ISign Bit)
Z
Zero

•
•

1\
1\
1\
1\
1\

1\
1\
1\
1\
1\

1\
1\
1\
1\

•
•
•
•

•
•
•
•

•
•
•

x
x

x

1\

•
•
•
•
•
•
•
•

x

x

C

•
•
•
•
•

x
x
x

x
x
x

Z

• •
•

x
x

x

N

•
•
•
•

;

x

x

I

1\

x

x

H

•
• •
• •
• •
• •
• •
• •
• •
• •
• •

• •
• 1\

• •

• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
0 •
• 0

•

• •
• •
• •
• •
• •
• •
1\ •
• •
• •
• •
• •
• •

• •
• •
• •
• •
• 1\
• 1\
• •
• •

•
•
•
•
•
•
• 0
•
•
• •
1 •
•
• • 1\ 1\ 1\
• • 1\ 1\ 1
1\
• • 1\ 1\ r-• • 1\ 1\ •
• • 1\ 1\ •
• • 1\ 1\ •
• • • • •
• • • • •
• • 1\ 1\ •
• • 1\ 1\ •
(to be continued)

C

1\
•

Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected

_HITACHI

153

HD6805S1--------------------------------------------------------------Table 7 Instruction Set
Condition Code

Addressing Modes
Mnemonic

Implied

LSL

x

LSR

x

NEG

x

NOP

x
x

ROR

x

RSP

x

Extended

Relative

x
x
x

x

(No
Offset)

Indexed Indexed
(8 Bits) (16 Bits)

x
x
x

x
x
x

x

x
x
x

x

x

Bit

Setl
Clear

x

Bit
Test &
Branch

I

N

Z

• •

/\

/\

H

C

/\

•
•
•
•
•
•
•

•
• /\ /\ /\
• • • •
• /\ /\ •
• /\ /\ /\
• /\ /\ /\
• • • •
?

0

/\

/\

?

?

?

RTI

x

?

RTS

x

• • • • •

x

SBC
SEC

x

SEI

x

STX
x

SUB
SWI
TAX
TST
TXA

x

x
x

STA

x
x
x
x

Condition Code Symbols:
H
Half Carry IFrom Bit 3)
I
I nterrupt Mask
N
Negative ISign Bit)
Z
Zero

154

Direct

x
x
x
x

ORA
ROL

Immediate

Ind~xed

x

x

x

x
x
x

x
x
x

x

x

x

x

x

x

x
x

x
x

x

C

Carry IBorrow

/\

Test and Set if True. Cleared Otherwise

•
?

Not Affected

Load CC Register From Stack

$

HITACHI

• •

/\

/\

/\

• • • • 1
• 1 • • •
• • /\ /\
• • /\ /\
• • /\ /\
• 1 • •
• • • •
• • /\ /\
• • • •

•
•
/\

•
•
•

•

---------------------------------------------------------------HD6805S1
Table 8
Bit Manipulation
Branch
Te.t&
Setl
Rei
Branch
Clear
1
2
0
0 BRSETO BSETO BRA
1 BRClRO BClRO BRN

Re.d/Modify!Write
OIR

I I
A

I

3

4

I

X

5
NEG

I
I

,X1

I

6

i

Opcode Map
Control

,XO

IMP

IMM

I

OIR

I

EXT

I

7

8
RTI*
RTS*

9

A

I

8

I

C

!

-

-

-

2 BRSET1

BSET1

BHI

-

3 BRClR1
4 BRSET2
5 BRClR2
6 BRSET3
7 BRClR3
8 BRSET4
9 BRClR4
A BRSET5
B BRClR5
C BRSET6

BClR1
BSET2
BClR2
BSET3
BClR3
BSET4
BClR4
BSET5

BlS
BCC
BCS
BNE
BEQ

COM

-

-

ROR
ASR

-

TAX

lSl/ASl
ROl
DEC

-

-

-

BSET6
BClR6

BHCC
BHCS
BPl
BMI
BMC
BMS

INC
TST

BSET7
BClR7

Bil
BIH

ClR

-

ClC
SEC
Cli
SEI
RSP
NOP

0 BRClR6
E BRSET7
F BRClR7
3/10

~ClR5

2/7

2/4

-

-

I

1/4

I

1/4

-

SWI*

lSR

2/6

I

2/7

I

Register/Memorv

IMP

1/6

-

- I

- I
BSR*I

TXA

-

I

1/2

2/2

I

1/*

2/4

I 3/5

,X2

I

,X1

0
I E
SUB
CMP
SBC
CPX
AND
BIT
lOA
STAC+1)
EOR
AOC
ORA
ADO
JMPH)
JSRI-3)
lOX
STXI+1)

I 3/6

I 2/5

I,xo
I

F

-

HIGH

0

1

2
3 l
4 o
5 W
6
7

8
9
A
B
C
0
E
F

I 1/4

INOTE) 1. Undefined opcode. are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles rflQuired IBytes/Cycle.).
Mnemonics followed by a

3. «

If." require a different number of cycles as follows:

RTI
9
RTS
6
SWI
11
BSR
B
indicate that the number in parenthesis must be added to the cycle count for that instruction.

_HITACHI

155

HD6805S6-------------MCU (Microcomputer Unit)
The H06805S6 is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, 1/0 and
timer_ It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD
6800-based instruction set.
The following are some of the hardware and software
highlights of the M CU.
• HARDWARE FEATURES
• B-Bit Architecture
• 64 Bytes of RAM
• Memory Mapped I/O
• 1804 8ytes of User ROM
• Internal B-Bit Timer with 7-Bit Prescaler
• 20 TTL/CMOS Compatible I/O Lines;
8 Lines LED Compatible
•
•
•
•
•

On-Chip Clock Circuit
Self-Check Mode
Master Reset
Low Voltage Inhibit
Complete Development System Support by Evaluation kit

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

5 Vdc Single Supply
Compatible with MC6805P6
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Po_rfullndexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memorv Examine/Change
10 Pa-rful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P6

-PRELIMINARV-

HD6805S6P

(DP-28)
• PIN ARRANGEMENT

A,
A.

A,
A.
A,

A,

A,
B,
B.

C,
B.

B,

B.

B,

B,

(Top View)
• BLOCK DIAGRAM
TIMER

Accumulator
A

8

A,
A,

Port
A
110
LIMS

A,
A,
A.
A,
A.
A.

IncW.
Refilter

Control

X

Data
O'f
Reg

Colle
5

Register

cc

5

Stack
POinter

sp

J

Program
Count...
"Htgh" PCH

8

Counter
"low" pel

1804118

ROM

111".
Self dteck
ROM

~HITACHI

B,
B,
B, Pori
B,
B
B. I/O
8, Lines
B,

B.

CondItIOn

Pori
A
Reg

Program

156

CPU

CPU

C.
C,
C,
ALU

Port
C
I/O

Co unn

HD6805S6
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Supply Voltage

Value

Input Voltage (EXCEPT TIMER)

V in

Input Voltage (TIMER)

Unit

-0.3~+7.0

.

Vee *

V

-0.3~+7.0

V

-0.3~+12.0

V

Operating Temperature

Topr

o ~+70

°c

Storage Temperature

Tstg

-SS~+l50

°c

• With respect to Vss (SYSTEM GNDI
(NOTE)

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI.

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (VCC"5.25V ± O.SV, VSS=GND, Ta=~+70°C, unless otherwise noted.)
Item
Input "High" Voltage

Symbol

min typ

2.0

-

9.0

-

INT

3.0
V ,H

Timer Mode
Self-Check Mode
RES

-0.3

INT

Input "Low" Voltage

2.0

-

4.0

All Other
Input "High" Voltage Timer

Test Condition

RES

EXTAL(Crystal Mode)

-

-0.3

V ,L

-

-0.3

max Unit
Vee

V

Vee

V

Vee

V

Vee
11.0

V

0.8

V

0.8

V

0.6

V
V

-0.3

-

0.8

Power Dissipation

Po

-

700

Low Voltage Recover

LVR

Low Voltage Inhibit

LVI

-

-

All Other

TIMER
INT

I nput Leak Current

I,L

Vin=0.4V~Vee

EXTAL(Crystal Mode)

V

mW

4.7S

V

-

V
IJA

4.0

-20

-

20

-SO

-

SO

IJA

0

IJA

-1200

• AC CHARACTERISTICS (Vcc=S.2SV ± O.SV, Vss=GND, Ta=O ~ +70°C, unless otherwise noted.)
Item

Symbol

Test Condition

min

typ

max Unit

Clock Frequency

fCI

0.4

-

4.0

Cycle Time

1.0

-

10

Oscillation Frequency (External Resistor Mode)

tCYC
f EXT

INT Pulse Width

t,WL

tC"5c +
2 0

RES Pulse Width

tRWL

tC"5c +
2 0

TIMER Pulse Width

tTWL

t2~

-

Oscillation Start·up Time (Crystal Mode)

tosc

C L=22pF±20%,
Rs =60n max.

-

Delay Time Reset

tRHL

External Cap. = 2.2 IJF

Input Capacitance

I
I

XTAL

C in

All Other

•

Rep=lS.0kn±1%

Vin=OV

HITACHI

-

100

-

MHz
IJS

-

MHz

-

ns

-

ns

-

100

ms

-

-

ms

3.4

-

ns

35

pF

10

pF

157

HD6805S6
e PORT ELECTRICAL CHARACTERISTICS (Vee" 5.25V ± 0.5V, Vss - GND, Ta = 0-+7ri'C, unless otherwise noted I
typ
max
Unit
min
Symbol
Test Condition
Item
3.5
V
IOH = -10pA
Port A
V
2.4
IOH '" -100pA

-

-

Output "High" Voltage

PortB

VOH

PortC
Port A and C
Output "Low" Voltage

Port B

Input "High" Voltage
Input "Low" Voltage

PortA, B, C
PortA

Input Leak Current

Port B, C

VOL

IOH" -200pA
IOH = -1 mA

2.4
1.5

IOH = -100pA
IOL = 1.6 mA

2.4

-

IOL =3.2mA
IOL'" 10mA

-

-

V
V

-

V

0.4

V

-

0.4
1.0

V
V

-

Vee

V

O.B

V
pA

VIH

2.0

VIL
Yin -O.BV

-0.3
-500

Vln = 2V

-300

-

Yin = 0.4V - Vee

-20

-

IlL

-

-

20

pA
j.lA

TTL Equiv. (Port A and CI

TTL Equiv. (Port BI

~

Ii- 3.2mA

Test Point

Test Point

li= 1.6mA

V.cc

.: 2.4kn

Vi
40pF

(NOTE)

12kn

I. Load capacitance includes the floating capacitance of tt" probe and the jig etc.
2. All diod.. are I S2074  or equivalent.

Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION

e TIMER

The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.

This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.

e VCC andVss

Power is supplied to the MCU using these two pins. VCC is
+5.25 V ± 0.5 V. VSS is the ground connection.
elNT

This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
e XTAL and EXTAL

'fI.ese pins provide connections for the on.chip clock circuit.
A crystal (AT cut, 4 MHz maximum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL
OSCILLATOR OPTIONS for recommendations about these
inputs.

158

e RES

This pin allows resetting of the MeU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.
eNUM

This pin is- not for user application and should be connected
toVSS·
elnput/Output Lines (Ao - A7, Bo - B7, Co - C31

These 20 lines are arranged irito two 8·bit ports (A and B)
and one 4·bit port (C). All lines are programmable as either
inputs or outputs under software control of the data direction
registers. Refer to INPUT/OUTPUT for additional informa·
tion.

_HITACHI

HD6805S6
order three bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer
increments when it pulls data from the stack: A subroutine call
will cause only the program counter (pCH, PeL) contents to be
pushed onto the stack.

• MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of the CPU registers
are pushed onto the stack in the order shown in Figure 3. Since
the stack pointer decrements during pushes, the low order byte

(PeL) of the program counter is stacked first; then the high

Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location. it will be removed when
manufacturing mask for production.

o

7

000

7

$000

I/O Ports
Timer
RAM
(128 Bytes)

127
128

~

Page Zero
ROM
(128 Bytes)

255
256

1

Port B

$0 FF
$1 00

1

ROM

(1668 8vtes)

1923
1924

$7 83
$7 84

Self Check
ROM
(116 Bytes)

2039
2040

1

I

$002

Not Used

$003

4

Port A DDR

$004"

5

Port B DDR

$005"

I

$006"

Not Used

Port C DDR

7

Not Used

$007

8

Timer Data Reg

$008

9

Timer CTRL Reg

$009
$OQA

Not Used (54 Bytes)
63

6

\

$03F
$040

RAM (64 Bytes)
Stack (31 Bytes Maximum)
'f

12

$07F

'Write only registers

$7 FF

2047

$001
Port C

0

$7 F7
$7 F8

Interrupt
Vectors
ROM
(8 Bytes)

1

$000

3

6
Main

1

0

2

3

4

Port A

2

$0 7F
80

5

6

0

Figure 2 MCU Memory Configuration

6
n-4

1

5
1

4

11

3

2

Condition
Code Register

0-1

1

1

1

1

11

PCl'

PCH*

Accumulator

0

I

X

I

n+3

Index Register

I

A

n+l

8 7

10
n-2

0

I

Pull

n+2

Accumu lator

n-3

7

0

PCl

PCH

10

n+4

1 01010

n+5

1111

I
I

Program Counter

0

5 4

101

Index Register

0

SP

Stack Pointer

Condition Code Register

Push
.. For subroutine calls, only PCH and pel are stacked,

Carry IBorrow

Figure 3 Interrupt Stacking Order

Zero
L _ _ _ 'Nagative
Interrupt Mask

Half Carry

Figure 4 Programming Model

•

HITACHI

159

HD6805S6--------------------------------------------------------------•

REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
• Accumulator (AI
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (XI
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for lim ited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PCI
The program counter is an ll·bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SPI
The stack pointer is an ll·bit register that contains the
address of the next free location on the stack. Initially, the
stack pointer is set to location S07F and is decremented as data
is being pushed onto the stack and incremented as data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 000011. During a MCU reset or
the reset stack pointer (RSP) instruction, the stack pointer is set
to location S07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to 15 levels of subroutine calls.
• Condition Code Register (CCI
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each
individual condition code register bit is explained in the
following paragraphs.

Ha" Carry (H I
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
Interrupt III
This bit is set to mask the timer and external interrupt (INT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.

Negative (N I
Used to indicate that the result of the last arithmetic,logical
or data manipulation was negative (bit 7 in result equal to a

logical one).
Zero (ZI
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (CI
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
• TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TOR), is loaded under pro·
gram control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer inter.
rupt request bit (bit 7) in the' Timer Control Register (TCR), is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $7F8 and $7F9 and executing the interrupt routine.
The timer interrupt can be maksed by setting the timer inter.
rupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prevents a timer interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal tin
signal. When the 1/12 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user

<1>,

(lnternan
TIR;Timer Interrupt Request

TIM; Timer Interrupt Mask
Timer

Input
Pin

TlR TIM

r-----'
I
I

I

I
I
I

IL _____ .II

Manufacturing

Mask Options
Write

Read

Figure 5 Timer Block Diagram
160

•

HITACHI

Write

Read

--------------------------------------------------------------HD6805S6
to easily perform pulse-width measurements. The TIMER input
pin must be tied to Vee, for ungated q,2 clock input to the
timer prescaler. The source of the clock input is one of the
options that has to be specified before manufacture of the
MCV. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter (TDR). The timer continues
to count past zero, falling through to $FF from zero, and then
continuing the count. Thus, the counter can be read at any
time by reading the TDR. This allows a program to determine
the length of time since a timer interrupt has occurred and
not disturb the counting process.
At power·up or reset, the prescaler and counter are initialized
with all logical ones; the timer interrupt request bit (bit 7) is
cleared, and the timer interrupt mask bit (bit 6) is set.
(NOTE) If the MCV Timer is not used, the TIMER input pin
must be grounded.

• SELF CHECK

The self-check capability of the MCV provides an internal
check to determine if the part is functional. Connect the MCV
as shown in Figure 6 and monitor the output of port C bit 3
for an oscillation of approximately 3Hz.
• RESETS

The MCV can be reset three ways: by initial power-up, by
the external reset input (RES) and by an optional internal low
voltage detect circuit, see Figure 7. All the I/O port are initialized to Input mode (DDR's are cleared) during RESET.
During power·up, a minimum of 100 milliseconds is needed
before allowing the RES inpu t to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.

~ INT

A, 27
A, 26

28 RES

A, 25

~2.2pF

A. ~
A, 23

XTAL

C

A, 22

EXTAL

+9V

7

A, 21
Ao ~

TIMER

HD6805S6
(Resistor option)*

B,

~

v CC
,1300

,r,;:;

8

~~;: ~ 0.
,;t
~~o

NUM

~

B, 18
B, 17
B. 16
B, ~

Co

9 C,

B, 14

to:.:::; ::;,.y 10 C,

B, 13

11 C,

Bo 12

.1~0f!
~ Q..
v
oCY

Vcc=Pin3
Vss

= Pin

1

* Refer to Figure 9 about crystal option

Figure 6 Self Check Connections

REi
Pin

Intarnal
R••et

-------f"

---------'
Figure 7 Power Up and RES Timing

_HITACHI

161

HD6805S6i------------------------------------------------------------

RES

• INTERNAL OSCILLATOR OPTIONS
The internal oscil~ator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator
or the RC oscillator circuit. The different connection methods
are shown in Figure 9. Crystal specifications are given in Figure
10. A resistor selection graph is given in Figure II.

28

Part 01
HD6805S6
MCU

Figure 8 Power Up Reset Delay Circuit

5 XTAL

5 XTAL
MaHxZ c:::J
4m

4 EXTAL

HD6805S6
MCU

4 EXTAL

HD6805S6
MCU

22PF±20%::;:t:;:

Crystal

Approximately 25% Accuracy
External: Jumper

Vee
5 XTAL

5 XTAL
External
Clock
Input

"'r."_~

R
4 EXTAL

HD6805S6
MCU

4 EXTAL

HD~~5S6

No
Connection

External Clock

Approximately 15% Accuracy
External Resistor

CRYSTAL OPTIONS

RESISTOR OPTIONS

Figure 9 Internal Oscillator Options

5

C,

XTAL~~EXTAL
5

~~

AT - Cut Parallel Resonance Crystal
Co = 7 pF max.
I • 4 MHz CC, =22pF± 20%.

4

\

N

J:

!

>
u
c

I

1\

4

3

l\

\

.

"e
<7

u.

2

Rs· 60n max.

~

~

~ r-.....

Figure 10 Crystal Parameters

o

5

10

15

20
25
30
Resistance Ckn.

35

)

~
40

Figure 11 Typical Resistor Selection Graph

162

_HITACHI

J.

Vee= 5.25V_
T A =25°C

~

45

50

------------------------------------------------------------HD680556

1-1
$7F -SP
o _DDA',
CLA INT Logic
$FF _Timer
$7F _ Presealer
$7F_TCA

Stack
PC,X,A,CC

y

Y

TIMEA

Load PC From
Aeset: $7FE, $7FF

Load PC From
SWI; $7FC, $7FD
INT: $7FA, $7FB
TlMEA: $7FB, $7F9
Fetch
Instruction

Y

SWI

Execute
Instruction

Figure 12 Interrupt Processing Flowchart

Data
Direction
Register

Input to
MCU

Output
Data Bit

Output
State

o

o

o

x

3-Stata

Pin

Bit

Figure 13 Typical Port I/O Circuitry

•

HITACHI

o

163

HD6805S6-----------------------------------------------------------•

INTERRUPTS

•

The CPU can be interrupted three different ways: through
the external interrupt (IJiiT) input pin, the internal timer
interrupt request, and a software interrupt instruction (SWI).
When any interrupt occurs, processing is suspended, the present
CPU state is pushed onto the stack, the interrupt bit (I) in the
Condition Code Register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. The interrupt
service routines normally end with a return from interrupt
(RTI) instruction which allows the CPU to resume processing
of the program prior to the interrupt. Table I provides a listing
of the interrupts, their priority, and the vector address that
contain-the starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given in
Figure 12.

Table 1 Interrupt Priorities
Interrupt

Priority

SWI

1
2

INT
TIMER

3
4

RES

Vector Address
$7FE and $7FF
$7FC and $7FD
$7FA and $7FB
$7F8 and $7F9

INPUT/OUTPUT

There are 20 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding data direction register (DDR). When programmed as
outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Figure 13). When port B is programmed for out·
puts, it is capable of sinking 10 rnA on each pin (VOL = IV
max). All input/output lines are TTL compatible as both inputs
and outputs. Port A are CMOS compatible as outputs, and
Port Band C are CMOS compatible as inputs. Figure 14 provides some examples of port connections.
•

BIT MANIPULATION

The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 15
illustrates the usefulness of the bit manipulation and test
instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit I of port A is connected to
the trigger of a TRIAC. which powers the controlled hardware.
This program, which uses only seven ROM locations,
provides tum-on of the TRIAC within 14 microseconds of the
zero crossing. The timer could also be incorporated to provide
turn-on at some later time which would permit pulse-width
modulation of the controlled power.

Bo

Port A

···•
·

Port B

B,
Port A Programmed a. output!.), driving CMOS and TTL Load directly.
la)

Port B Programmed a. output!.), driving Darlington ba.e directly.
Ib)

+V

+v

R
Co
Port B

Port C

••
•
••
••

·

CMOS Inverter

C,
Port B Programmad a. output!s), driving LED!a) diractly.
!e)

Port C Programmed aa output!.), driving CMOS load., u.ing externel
Id)
pull·up resi.tor..

Figure 14 Typical Port Connections

164

•

HITACHI

---------------------------------------------------------------HD6805S6

SELF 1

··•
·•

• Bit Set/Clear

Refer to Figure 23. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.

BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A

• Bit Test and Branch

The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.

Refer to Figure 24. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.

•

•

··
·

Figure 15 Bit Manipulation Example
• ADDRESSING MODES

Immediate

Refer to Figure 16. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.

• Direct

Refer to Figure 17. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.

• Extended

Refer to Figure 18. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.

•

Relative

Refer to Figure 19. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pc)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
•

Indexed (No Offset)

Refer to Figure 20. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and ·their EA is the contents of the index register.
•

Indexed (8-bit Offset)

Implied

Refer to Figure 25. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
• INSTRUCTION SET

The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions

Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory' using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
•

Read/ModifvlWrite Instructions

These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions

The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions

These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.

Refer to Figure 21. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
acce~sable. These instructions occupy two bytes.

• Controllnstructions

•

• Alphabeticallisting

Indexed U6-bit Offset)

Refer to Figure 22. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.

•

The control instructions control the MCU operations during
program execution. Refer to Table 6.
The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map

Table 8 is an opcode map for the instructions used on the
MCU .

HITACHI

165

HD6805S6--------------------------------------------------------------,

~

Memory

i

I
I
I

/

I

8
A6

OS8F

F8

F8

Inde

I

I

I

Stack Point

I
I

PROG LOA #$F8 OS8E

A

I

I
I

I
I

I

Prog Count

I

OSCO
CC

I

I

~
I

I
,I

Figure 16 Immediate Addressing Example

lEA
Melory
i

i

I
I

I
I
I

I

I

I

i

CAT

FCB

32

I

L.OA

CAT

I

004B

~

/

'"

Add.r

20

0048

I

PROG

I

Jo

A

-'

I

0620

B8

052E

48

I
I

Steck Point

(

I
I

Pros Count
062F
CC

~
I

I
I

I

,

I

I

I

I

;
Figure 17 Direct Addressing Example

166

_HITACHI

20
Ind." Reg

I

HD6805S6

Memory

i
I
I
I

I

~
I

PROG

LOA

CAT

0000
A

I

-~ J

O4OA

06

040B

ES

40
Index Reg

Stack Point

I
I

CAT

FCB

64

06ES

Prog Count

40

040C
CC

Figure 1 B Extended Addressing Example

lEA

L

Memory
i

I

I

I

L

I

~

BEQ

PROG2

I

I

I
PROG

~

I

I

I

04A7

27

O4A8

18

I

04C1

Adder

1
OR

~

oota

'"

A

I
I

Stack Point

I

I
Prog Count

J

04C1

r
I

I

~

I
I
I

Index Reg

cc

l

z

I

J

I

I

Figure 19

•

Relative Addressing Example

HITACHI

167

HD6B05S6------------------------------------------------------------

,

lEA

Me1.v
i

i

0088

J

/'

Adder

'"

I

I

i

i

I

I

i

i

I

I

TABL

I

010

4C

FCC I LII OOB8

49

A
4C

I

Index Reg
B8

I

Stack Point
PROG

LOA

X
Prog Count
05F5
CC

Figure 20 Indexed (No Offset) Addressing Example

lEA
I
I

Me1rv

i
I

FCB

#8F

0089

BF

FCB

#86

008A

8B

FCB

#OB

008B

DB

FCB

#CF

008C

CF
I
I

PROG

LOA

/'

Adder

I
I
I

TABL. X 0758

E6

075C

89

I

008C

t

i

i

TABL

I

'"
I

I

03

I

I

I

Prog Count

I

~
I,

Figure 21 Indexed (B·Bit Offset) Addressing Example

16B

CF
Index Reg

Stack Point

I

I,

A

_HITACHI

0750
CC

I

------------------------------------------------------------HD6805S6

lEA

Melorv

,

I

I

0693
0694

/'

~
§

Adder

~

A
DB

02

I
I

IJ

#BF

077E

BF

FCB

#86

077F

86

FCB

#OB

0780

DB

FCB

#CF

0781

CF

I
I

I
Prog Count
0695
CC

I

FCB

I

Stack Point

11

07

7E

I

IndeK Reg

I

,

TABl

t

I

I

lOA TABl. X 0692

J

0780

I

I

PROG

I

I

I

Figure 22 Indexed (l6-Bit Offset) Addressing Example

Memory

PORTB

EQU

BF

0001

A

0000
IndeK Rag
PROG BClR 6. PORT B

058F
0590

10

Stack Point

t - - -0-1- - - t

Prog Count
0591
,

I

CC

§
Figure 23 Bit Set/Clear Addressing Example

_HITACHI

169

HD6805S6---------------------------------------------------------------

Memtrv
i

I

i
i
i

PORT C

Eau

0002

2

lEA
0002

I

i

FO

J

t

I

/

Adder

Bit
2

'"

010
I

i
i

PROG BRCLR 2. PORT C. PROG 2

05

0575

02

0576

I

i

0574

10

--I
i

i

OR

Index Reg

I

I

rI

I

0594
CC

I

I

C

Adder

I

/

i

Figure 24 Bit Test and Branch Addressing Example

Memory

I
I
I

~
PROG

TAX

i

i

i
i

I

E5

E5

i

'-~

Prog Count

058B
CC

i

i

I

I

~
Figure 25 Implied Addressing Example

170

•

HITACHI

I

Stack Point

~

~ '"
i

I
I
I

Prog Count

or

i

A

I

------------------------------------------------------------HD6805S6
Table 2 Register/Memory Instructions
Addressing Modes

Function

Mnemonic

Direct

Immediate
Op

#

#

OP

Extended

#

Op

#

#

#

Op

Indexed

Indexed

Indexed

INoOII... )

18·8i.Oll5O.)

116·8i.Olfse.)

#

#

Op

#

Op

#

#

#

Cod. Bvtes Cycles Cod. Bvtes Cycles Cod. Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles
Load A from Memory

LOA

A6

2

2

B6

2

4

C6

3.

5

F6

1

4

E6

2

5

06

3

6

Load X from Memory

LOX

AE

2

2

BE

2

4

CE

3

5

FE

1

4

EE

2

5

DE

3

6

Store A in Memory

STA

-

2

5

C7

3

6

F7

1

5

E7

2

6

07

3

7

STX

-

-

B7

Store X in Memory

-

BF

2

5

CF

3

6

FF

1

5

EF

2

6

OF

3

7

Add Memory to A

AOO

AB

2

2

BB

2

4

CB

3

5

F8

1

4

EB

2

5

DB

3

6

AOC

A9

2

2

B9

2

4

C9

3

5

F9

1

4

E9

2

5

09

3

6

2

eo

2

4

CO

5

FO

1

4

EO

2

5

DO

3

6

Add Memory and

carry to A
SUbtract Memory

AO

SUB

2

3

Subtract Memory from
A with Borrow

sec

A2

2

2

B2

2

4

C2

3

5

F2

1

4

E2

2

5

02

3

6

AND Memorv to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

1

4

E4

2

5

04

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

OA

3

6

EOR

A8

2

2

B8

2

4

CB

3

5

F8

1

4

E8

2

5

08

3

6

CMP

Al

2

2

81

2

4

Cl

3

5

Fl

1

4

El

2

5

01

3

8

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

03

3

6

Exclusive OR Memory
with A
Arithmetic Compare A

with Memory
Arithmetic Compare X

CPX

A3

2

Bit Test Memory with A
ILogical Compere)

BIT

A5

2

2

B5

2

4

C5

3

5

F5

1

4

E5

2

5

05

3

6

Jump Unconditional

JMP

-

-

BC

2

3

CC

3

4

FC

1

3

EC

2

4

DC

3

5

Jump to Subroutine

JSR

80

2

7

CD

3

8

FO

1

7

ED

2

8

DD

3

9

with Memory

-

-

-

Table 3 Read/ModifylWrite Instructions
Addressing Made.
Function

Implied (X)

Implied (A)

Mnemonic

Indexed
(No Offset)

Direct

Indexed
(8-Bit Offset)

Op
Op
#
Op
Op
Op
#
#
#
#
#
#
#
#
#
Code Byte. Cycle. Code Byt.. Cyc)e. Code Bytes Cycle. Code Byte. Cycle. Code Bytes Cycle.
l"ncrement

INC

4C

1

4

5C

1

4

3C

2

8

7C

1

6

8C

2

7

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

CI••r

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

8F

2

7

Compl.ment

COM

43

1

4

53

1

4

33

2

8

73

1

6

83

2

7

Negate
(2's Complement)

NEG

40

1

4

60

1

4

30

2

6

70

1

6

80

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

2

8

1

4

66

1

4

2

6

1

logical Shift Left

LSL

4B

1

4

66

1

4

38

2

6

78

1

6

6B
68
68

7

48

6
6

2

ROR

39
38

1

Rotate Right Thru Carry

79
78

2

7

2

7

LogIc.1 Shift Right

LSR

44

1

4

64

1

4

34

2

6

74

1

6

64

2

7

Arithmetic Shift Right

ASR

47

1

4

57

1

4

37

2

8

77

1

6

67

2

7

Arithmetic Shift Left

ASL

48

1

4

58

1

4

38

2

6

78

1

6

88

2

7

Test for Negative or
Zero

TST

40

1

4

50

1

4

3D

2

6

70

1

8

SO

2

7

•

HITACHI

171

HD6805S6--------------------------------------------__________________
Table 4 Branch Instructions
Relative Addressing Mode
Function

Mnemonic

Branch Always
Branch Never
Branch I F Higher

BRA
BRN
BHI
BlS

Branch IF lower or Same
Branch I F Carry Clear
(Branch IF Higher or Same)
Branch I F Carry Set

22
23
24
24
25
25
26
27
28
29
2A

BCC
(BHS)
BCS
(BlO)
BNE
BEQ

(Branch IF lower)
Branch I F Not Equal
Branch I F Equal
Branch I F Half Carry Clear
Branch I F Half Carry Set
Branch
Branch
Branch
Branch

Op
Code
20
21

BHCC
BHCS
BPl
BMI
BMC

IF Plus
I F Minus
IF Interrupt Mask Bit is Clear
I F Interrupt Mask Bit is Set

4

4
4
4
4
4
4
4
4

2
2
2
2
2
2
2

4
4

4
4

2
2
2

20
2E
2F

BIH
BSR

Branch to Subroutine

#
Cycles

2B
2C

BMS
Bil

Branch I F Interrupt Line is low
Branch IF Interrupt Line is High

#
Bytes
2
2
2
2
2

4
4
4
4

2
2

4

2
2

AO

8

Table 5 Bit Manipulation Instructions
Function

Mnemonic

Bit Set/Clear
Op
Code

Branch IF Bit n is set
Branch I F Bit n is clear
Set Bit n
Clear bit n

BRSET n (n-O ..... 7)

-

BRClR n (n=O ..... 7)
BSET n (n=O ..... 7)
BClR n (n=O ..... 7)

-

#
Bytes

-

10+2 n
11+2 n
0

0

2
2

Addressing Modes
-Bit Test and Branch
Op
#
#
#
Cycles
Code
Bytes
Cycles
2 n
3
10
01+2 n
3
10
7
7
-

-

0

0

-

-

Table 6 Control Instructions
Implied
Function
Transfer A to X
Transfer X to A
Set Carry Bit
Clear Carry Bit
Set Interrupt Mask Bit

TAX
TXA
SEC

Clear Interrupt Mask Bit
Software Interrupt

CLI
SWI
RTS

Return from Subroutine
Return from Interrupt
Reset Stack Pointer
No·Operation

172

Mnemonic

ClC
SEI

RTI
RSP
NOP

~HITACHI

Op
Code
97
9F
99
98
9B
9A

#

#

Bytes

Cycles

1
1
1
1

2
2
2
2

1

2
2
11

81
80

1
1
1
1

9C
90

1
1

2
2

83

6
9

----------------------------------------------------------HD6805S6
Table 7 Instruction Set

Mnemonic

ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bll
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BRSET
BSET
BSR
ClC
Cli
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lOA
lOX

ImmeImplied diate
x
x
x
x
x

Zero

x

x

l!

)(

l!

x

Relative

x
x

Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
X
X
X

l!

x
x

l!

Condition Code
Bit
Setl
Clear

Bit
Test &
Branch

x
x

)(

x
l!
l!

x
x
x
l!

x

x

l!

l!

X

X

l!

x
l!

x
x
x
x
x

x
x
x

x
x

x
x
x
x
x
x

x

x
x
x

x

x

x

x

x
x
x
x
x
x

x

l!

x
x

x

x

x
x
x

x
x

x

x
x

x

x
x

x

x

x

x
x

x
x
x

x
X

x

x

x
x
x
x

X

X

X

x

x

H

I

N

Z

1\
1\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

1\
1\
1\
1\
1\

1\ 1\
1\ 1\
1\
1\ 1\
1\ 1\

•
•
•
•
•
•
•
• •
• •
• •1\
•
• •
• •
• •
• •
•
•
• •
• •
• •
• •
• • •
• • •
• • •
• • •
• •0 •
• •
• • 1\0
• •
• • 1\
• • 1\1\
• •
• • 1\
• • 1\
• • •
• • •
• • 1\1\
• •

• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
1\ •
• •
• •
• •
• •
• •
• •
• •
• •
• •1\
•
• 1\
• •
• •0
•
• •

•
•
•
•
•
•
•
•
•
•

X

x

CondltiDn Code Symbols:
H Hall Carry (From Bit 3)
I
Interrupt Mask
N Negative (Sign Bid

Z

ExDirect
tended

C

•

1
1\
1\
1\
1\
1\
1\

•

1\
1
1\

•
•
•
• •
• •
1\ •
1\ •

(to be continued)

C

1\
•

Carry Borrow
Test and Sat II True. Cleared Otherwise
Not Affected

•

HITACHI

173

HD6805S6----------------~-----------------------------------------Table 7 Instruction Set
Addressing Modes
Mnemonic

Implied

Immediate

LSL

x

x

LSR

x

x
x

NEG

x

NOP

x
x

ORA
ROL

x

ROR

x

RSP

x

RTI

x

RTS

x

SEC

x

SEI

x

x

Extended

x
x
x

x

x
x

x

SBC

x

x
x

x

x

x
x
x

x

x

x

x

x

x

x

STX

x

x

x

x

x

x

x

x

x

x

x

SWI

x

TAX

x

TST

x

TXA

x

Condition Code Symbols:
H
Half Carry (From Bit 3)

I
N

Z

Interrupt Mask
Negative (Sign Bit)
Zero

x

x

C
/\
•

?

Bit
Set/
Clear

x
x

STA
SUB

174

Direct

Condition Code

R ---. Indexed
Indexed Indexed
e(No
(8 Bits) (16 Bits)
lative
Offset)
x
x

x

x

Carry IBorrow
Test and Set if True, Cleared Otherwise"
Not Affected
Load CC Register From Stack

~HITACHI

Bit
Test &
Branch

H

I

N

Z

C

• •
• •
• •

1\
0
1\

1\
1\

1\
1\
1\

1\

• • • •
• • 1\ 1\
• • 1\ 1\
• • 1\ 1\
• • • •
? ? ? ?
• • • •

•
•

1\

1\

• • 1\
• • •
• 1 •
• • 1\
• • 1\
• • 1\
• 1 •
• • •
• • 1\
• • •

1\
1\

•
?

•

• 1
• •
1\ •
1\ •
1\

1\

•
•
1\
•

•
•
•
•

------------------------------------------------------------HD6805S6
Table 8
Bit Manipulation

Test &
Branch

0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F

0
BRSETO
BRCLRO
BRSETI
BRCLRI
BRSET2
BRClR2
BRSET3
BRCLR3
BRSET4
BRClR4
BRSET5
BRCLR5
BRSET6
BRCLR6
BRSET7
BRClR7
3/10

Set/
Clear
1
BSETO
BClRO
BSET1
BClRl
BSET2
BCLR2
BSET3
BClR3
BSET4
BClR4
BSET5
BClR5
BSET6
BClR6
BSET7
BClR7
2/7

Branch

Opcode Map
Control

Read/Modify/Write

Rei

OIR

2
BRA
BRN
BHI
illS
BCC
BCS
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
Bil
BIH
2/4

3

I
I

A
4

I
I

X
5
NEG

I
I

,Xl

I

6

I

,XO

IMP

IMM

J

OIR

7

B
RTI"
RTS"

9

A

I

B

I

-

I

2/4

J

-

SWI"

-

-

-

-

INC
TST

ClR
1/4

I 2/7 I 1/6

1/"

IEXT I ,X2 I )<1 I ,XO
C

-

-

ROR
ASR
lSL/ASl
ROL
DEC

I 1/4 I

-

-

COM
lSR

2/6

Register/Memory

IMP

TAX
ClC
SEC
Cli
SEI
RSP
NOP

TXA
1/2

-

I
BSR"I

- I
2/2

I

3/5

I

I

I

I 2/5

I 1/4

0
E
SUB
CMP
SBC
CPX
AND
BIT
lOA
STA(+l1
EOR
AOC
ORA
ADD
JMPH)
JSR(-3)
lOX
STXI+l)

I 3/6

F

-

HIGH
0
1
2
3 l
4 o
5 W
6
7
8
9
A
B
C
0
E
F

(NOTE) 1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles reQuired IBytes/Cvcles).
Mnemonics followed by a

U." require a different number of cycles as follows:

RT!

3. (

9
RTS
6
SWI
11
BSR
8
indicate that the number in parenthesis must be added to the cycle count for that instruction .

•

HITACHI

175

HD6805U1

MCU (Microcomputer

Unit)

The HD6805Ul is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, 1/0 and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the HD6800based instruction set.
The following are some of the hardware and software highlights of the MCU.

HD6805U1P

• HARDWARE FEATURES
• 8-Bit Architecture
• 96 Bytes of RAM
• Memory Mapped I/O
• 2056 Bytes of User ROM
• Internal 8-Bit Timer with 7·Bit Prescaler
• Vectored Interrupts - External and Timer
• 24 I/O Ports + 8 Input Port
(8 Lines LED Compatible, 7 Bits Comparator Inputs),
• On-Chip Clock Circuit
• Self-Check Mode
• Master Reset
• Low Voltage Inhibit
• Complete Development System Support by Evaluation Kit
• 5 Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•

(DP·40)

•

SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instruction Set with MC6805P2

•

PIN ARRANGEMENT

A,
A.
A,
A,
A,
A,
AO

C,

c,
c,

BLOCK DIAGRAM

HD6805U1

C.
C.

TIMER

C.

B,

C,

Bo

..

0,

D,

B, ":"

D.

D,

..

D.

B,

II'IGI,.

A,
A,

Port A,
A
110

t.,.,...

A,
A.
A,
A,
A,

::

III"t,It,

"'''

lit..

B,

CoO.
1It1l'11I' CC

(Top View)

CPU

S"Ch
POIl'l,I'

110

8, Llnel

Condol,OI'l

Por,
0"1
AD"

C.
C,

II

"0.,'
11'1
COIInl1tf
"H....." PC"

ALU

PrOI"m
Coun."
"Low" pet..

e,

POri

C,

C

C. I/O
C, 1..1""
C,
C,

... B
.AM

176

.,
••
.,••
.2

_HITACHI

----------------------------------------------------------HD6805U1
• ABSOLUTE MAXIMUM RATINGS

Input Voltage (EXCEPT TIMER)

*

V in

*

-0.3-+7.0

V

-0.3-+7.0

V

-0.3-+12.0

Operating Temperature

T_

0-+70

V
·C

Storage Temperature

Tstg

- 55 - +150

·C

Input Voltage (TIMER)

•

Vee

Unit

Value

Symbol

Item
Supply Voltage

With respect to Vss (SYSTEM GNO)

(NOTE)

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are exceeded. it could affect reliability of LSI.

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc·5.25V ± O.5V, VSS=GND, Ta=G-+70·C, unless otherwise noted. I
Item
Input "High" Voltage

Symbol

min typ
4.0

INT

3.0

All Other
Input "High" Voltage Timer

Test Condition

RES
V IH

2.0

Timer Mode

2.0

Selt·Check Mode

9.0

RES
V IL

-0.3

EXTAL(Crystal Mode)

-0.3

All Other

-0.3

Power Dissipation

-

Low Voltage Rel:Over

Po
LVR

Low Voltage Inhibit

LVI

-

IlL

-20
-50

TIMER
INT

I nput Leak Current

-

-0.3

INT

Input "Low" Voltage

-

V in =0.4V-V ec

EXTAL(Crystal Mode)

-

4.0

-1200

-

max Unit
Vee

V

Vee

V

Vee

V

Vee

V

11.0

V

0.8

V

0.8

V

0.6
0.8

V
V

700

mW

4.75

V

20

pA

50

pA

0

pA

-

V

• AC CHARACTERISTICS (Vcc=5.25V ± 0.5V, Vss=GND, Ta=O - +70°C, unless otherwise noted.)
Item

Symbol

Test Condition

min

typ

max Unit

Clock Frequency

tel

0.4

-

4.0

Cycle Time

tc:vc

1.0

-

10

/..IS

Oscillation Frequency (External Resistor Mode)

teXT

-

3.4

-

MHz

INT Pulse Width

t lWL

-

ns

RES Pulse Width

tRWL

ns

TIMER Pulse Width

tTWL

ns
ms

Rep= 15.0kH±1 %

tCyc-t

250

Oscillation Start·up Time (Crystal Mode)

tose

C L=22pF±20%,
Rs =60n max.

Delay Time Reset

tRHL

External Cap. = 2.2 /..IF

Input Capacitance

I
I

XTAL
All Other

C in

Vin=OV

_HITACHI

-

tcSc-t
2 0
t Cyc +
250

-

-

-

-

100

100

-

- -

-

MHz

ms

35

pF

10

pF

177

HD6805Ul--------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ± 0.5V, Vss = GNO, Ta
Symbol
Test Condition
Item
IOH - -101lA
Port A
IOH = -1001lA
Output "High" Voltage
IOH = -200 p.A
VOH
Port B
IOH = ~1 mA
Port C
IOH = -1001lA
Port A and C
IOL = 1.6 mA
-Output "Low" Voltage
IOL =3.2mA
VOL
Port B
IOL = 10mA
Input "High" Voltage
VIH
Port A, B, C,
and 0*
Input "Low" Voltage
VIL

Input "High" Voltage
Input "Low" Voltage
Threshold Voltage
..
• Port 0 as digital mput
.. Port 0 as analog input

(Do - 0 6 )
Port 0**
(Do - 0 6 )
Port 0**(0 7 )

-

-

-

-

Yin =2V
Yin = 0.4V - Vee

- 20

-

V IH

-

VTH+0.2

VIL

-

VTH

0

IlL

Port B, C,
and 0
Port 0**

-

-

2.0
-0.3
-500
-300

Yin = 0.8V

Port A

Input Leak Current

= 0 - +70"C, unless otherwise noted.)
typ
min
max
Unit
V
3.5
V
2.4
V
2.4
V
1.5
V
2.4
V
O.~
V
0.4
V
1.0
V
V
IlA

-

IlA

20

IlA

-

V

VTwO.2

-

V

-

0.8xVee

V

TTL Equiv. (Port A and C)

TTL EQuiv. (Port B)

~

Vee
Ii = 3.2mA

Vee
0.8

-

1.2kn

Test Point

Test Point

Ii = 1.6 mA

vee
2.4kSl

Vi

Vi
40pF

24 kn

12 kn

,
(NOTE) 1. Load capacitance includes the floating capacitance of the probe and the jig etc.
2. All diode. are 1S20748 or equivalent.

Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION
The input and output signals for the MCV, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
• Vee and Vss
Power is supplied to the MCV using these two pins. Vee
is +S.2SV ±O.SV. Vss is the ground connection.
• INT
This pin provides the capability for asynchronously applying
an external interrupt to the MCV. Refer to INTERRUPTS for
additional information.
• XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maxinlum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OS-

178

•

CILLATOR OPTIONS for recommendations about these inputs.
• TIMER
This pin allows an external input to be used to decrement
the internal tinler circuitry. Refer to TIMER for additional
infom:lation about the tinler circuitry.

• This
m

pin allows resetting of the MCU at times other than
the automatic resetting capability already in the MCU. Refer
to RESETS for additional information.

• NUM
This pin is not for user application and should be connected
to VSS .

HITACHI

-------------------------------------------------------------HD6805U1
• MEMORY
The MCU memory is configured as shown in Figure 2. During
the processing of an interrupt, the contents of -the CPU regi,
sters are pushed onto the stack in the order shown in Figure 3,
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked fust; then the
high order four bits (PCH) are stacked. This ensures that the
program counter is loaded correctly as the stack pointer increments when it pulls data from the stack. A subroutine caU
will cause only the program counter (pcH, PeL) contents to
be pushed onto the stack.
Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.

• Input!Output Lin.. lAo - A,. So - 8,. Co - C,I
These 24 lines are uranged into three 8·bit ports (A, Band
C), All lines are programmable as either inputs or outputs under
software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional infonnation.
• Input Linn IDo - D,I
These are 8,bit input lines, which has two functions. Firstly,
these are TTL compatible inputs, in location $003. The other
function is 7 bits comparator, in location $007. Refer to INPUT
for more detail.

sooo

000

121
12B

256
256

Port B

5001
5002

$01 F

2

Port C

S080

3

Port 0 {digtt.11

5003"

•

Port A OCR

$004"

5

Porl BOOR

5005'

6

Port CODR

~

ROM

(128 Bvt.sl

sooo

Port A

0

,

110 Ports Tuner
RAM 028 Bytes)

F

S1 00

Not Used

2041

S1F F

2048

$BOO

SOOS"

Port 0 (analog)

5001"

8

Timer Data Reg,

$008

9

Timer CTRl Reg.

$009

1

500A

0
Not Used 122 Bvtesl

1
2

ROM

11920 By,",

=
3987
39B8

2~

Interrupt Vector.

n-4

1

SFF

5
1

4

11

3

2

Condition
Code Register

°

$020

St;ck
S01F

.. Write only registers
.... Read only register

SF7 F
SF SO
SFF 1
SFF 8

Self·rftt

40911

6

S01F
RAM 196 Byte.1

Figure 2 MCU Memory Configuration

Pull

°I
°

' -_ _ _ _A
_ _ _ _....... Accumulator

n+1

7

1
.._____X_"_ _ _ _...'lndex Register

n-3

Accumu lator

n+2

n-2

Index Register

n+3

~--------P-c-------.J1

n+4

11

11

n-1
n

1

1

1

'1
PCL"

PCH'

5 4

°
°

Program Counter

...lo. .l. .o...l_o...l_o-'l...o...I---'I...1_1L.-_ _s_p_--.l1 Stack Poonter

n+5

Condition Code Register

PUSh

• For subroutine calls, only PCH and pel are stacked.
Carry IBorrow

Figure 3 Interrupt Stacking Order

Zero
Negative

Interrupt Mask
Half Carry

Figure 4 Programming Model

_HITACHI

179

HD6805Ul--------------------------------------------------------------• REGISTERS
The CPU has five registers available to the programmer.
They are shown in Figure 4 and are explained in the following
paragraphs.
• Accumulator (AI
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (XI
The index register is an 8-bit register used for the indexed
addr~ssing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence bein~ executed, the index
register can be used as a temporary storage area.
• Program Counter (PCI
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer (SPI
The stack pointer is a 12·bit register that contains the addre~s
of the next free location on the stack. Initially, the stack pointer is set to location S07F and is decremented as data is being
pushed onto the stack and incremented as data is being pulled
from the stack. The six most significant bits of the stack pointer
are permanently set to 0000011. During an MCU reset or the
reset stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be nested
down to location $061 which allows the programmer to use up
to IS levels of subroutine calls.
• Condition Code Register (CCI
The condition code register is a 5-bit register in which each
bit is used to indicate or nag the r~sults of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following
paragraphs.
Half Carry (HI
Used during arithmetic operations (ADD and ADC) to

indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
This bit is set to mask the timer and external interrupt (00).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (NI
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero (ZI
Used to indicate that the result of the last arithmetic, logical
or data manipulation was zero.
Carry/Borrow (CI
Used to indicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected during bit test and branch instructions,
shifts, and rotates.
• TIMER
The MCU timer circuitry is shown in Figure 5. The 8-bit
counter, the Timer Data Register (TDR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. The CPU responds to this interrupt by saving the present
CPU state on the stack, fetching the timer interrupt vector from
locations $FF8 and $FF9 and executing the interrupt routine.
The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in the
Condition Code Register also prev.ents a time interrupt from
being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal 1/>2
signal. When the 1/>2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the user
to easily perform pulse-width measurements. The TIMER input
pin must be tied to Vee, for ungated 1/>2 clock input to the
timer pre scaler. The source of the clock input is one of the
options that has to be specified before manufacture of the

4>,
IIn,ornoll

TIR;
TIM;

Timer Interrupt Request
Timer Interrupt Mask

Timer
Inpu,
Pin

r-----'
I

I

I

I

I

I

I

I

L . . . . . ..

Manufacturing

Mask Option.
Write

Read

Figure 5 Timer Block Diagram

180

•

HITACHI

Write

Read

---------------------------------------------------------------HD6805Ul
MCU. A prescaler option can be applied to the clock input that
extends the timing interval up to a maximum of 128 counts
before decrementing the counter (TDR). The timer continues
to count past zero, falling through to $FF from zero and then
continuing the count. Thus, the counter (TDR) can be read at
any time by reading the TDR. This allows a program to determine the length of time since a timer interrupt has occurred
and not disturb the counting process.
The TDR is 8-bit Read/Write Register in location $008.
At power-up or reset, the TDR and the prescaler are initialized
with all logical ones.
The Timer Interrupt Request bit (bit 7 of the TCR) is set
by hardware when timer count reaches zero, and is cleared by
program or by hardware reset. The bit 6 of the TCR is writable
by program. Both of those bits can be read by CPU.
(NOTE) If the MCU Timer is not used, the TIMER input pin
must be grounded.

•

SELF CHECK

The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the MCU
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz.
•

RESETS

The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal
low voltage inhibit circuit, see Figure 7. All the I/O port are
initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.

A, 40

2-

INT

2

RES

A, 38

XTAL

A'rE-A, 36
A, 35

EXTAL

A, 34

A, 39

=F

2 .2J.I F

C

A" E-HD6805Ul •
8 TIMER (Resistor option)
B, E---

+9V

~

V cc

1 30n

/i:j

9

NUM

B, 31
B, 30
B. 29

C.

8,~

330n

\:'J b 1 0

C,

B, 27

330n

~
C,
~ ~12
C,

B, 26

J30n
10kn
~

.~

)Ok~

.)Okn
10k~
v

U

11

B" 25

'CY 13

C.
14 C,
15 C,

16 C,

V cc '" Pin 4

vss

= Pin 1

• R e f er to F, gure 9

about crystal option

Figure 6 Self Check Connections

RES Pin _ _ _ _ _ _ _ _.,

Internal

Reset _ _ _ _ _ _...J

Figure 7 Power Up and RES Timing

$

HITACHI

181

HD6805U1--------------------------------------------------------------•

INTERNAL OSCILLATOR OPTIONS

The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure II.

2

Pert of

-----

H06805Ul

MCU'

....

Figure 8 Power Up Reset Delay Circuit

6 XTAL

4

:a~"

22P F t

6 XTAL

c:::J 5 EXTAL HD6805Ul

5 EXTAL

H06805Ul
MCU

MCU,

20%T'

Crvstal

Approximately 25% Accuracv
External: Jumper

6 XTAL

External
Clock
Input

R
5 EXTAL

H06805Ul
MCU

5 EXTAL

H06805Ul
MCU

No
Connection

External Clock

ApprOKlmately 15% Accuracv
External Aeslstor

CRVSTAL OPTIONS

RESISTOR OPTIONS

Figure 9 Internal Oscillator Options

5
C,

XTAL~~EXTAL
6

~~

5

>
u
c

T A • 25°C

\

X

~

vJ=5.L

1\

4

3

'\

.
~

<7

AT - Cut Parallel Resonance Crvstal
Cn == 7 pF max.
I· 4 MHz
Rs' 60n max.

f

u..

2

~

""

Figure 10 Crystal Parameters

o

5

10

15

~~

20
25
30
ReSistance (kn)

............
35

40

Figure 11 Typical Resistor Selection Graph

182

•

HITACHI

-

r'-

45

50

---------------------------------------------------------------HD6805U1

1-1
7F -SP

o _DDR's

Stack
PC, X,A,CC

CLR I NT Logic
FF -+ Timer
7 F -+ Prescaler
7F _ TCR

y

TIMER

Load PC From
Reset :$FFE, $FFF

Load PC From
SWI :$FFC, $FFD
iNT:$FFA, $FFB
TIMER:$FFB,$FF
Fetch
Instruction

Y

SWI

Execute
Instruction

Figure 12 Interrupt Processing Flowchart

Data
Direction
Register
Bit

Output
Data Bit

0

Figure 13 Typical Port I/O Circuitry

•

HITACHI

1
0

Output

Input to

State

MCU

0

0

3·State

Pin

183

HD6805U1------------------------------------------------------~-------

•

INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request, and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack, the interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed. The interrupt service routines
normally end with a return from interrupt (RTI) instruction
which allows the CPU to resume processing of the program
prior to the interrupt. Table I provides a listing of the interrupts, their priority, and the vector address that contain the
starting address of the appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 12.
Table 1 Interrupt Priorities
Priority

Interrupt
RES
SWI

Vector Address
$FFE and $FFF
$FFC and $FFD
$FFA and $FFB
$FF8 and $FF9

1

2

fNT

3
4

TIMER

• INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the cor·
responding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 13). When Port B is programmed for outputs,
it is capable of sinking lOrnA on each pin (VOL = IV max).
All input/output lines are TTL compatible as both inputs and

outputs. Port A is CMOS compatible as outputs, and Port Band
C lines are CMOS compatible as inputs. Figure 14 provides some
examples of port connections.
•

INPUT
Port D can be used as either 8 TTL compatible inputs or I
threshold input and 7 analog inputs pins. Fig. IS (a) shows the
construction of port D. The Port D register at location $003
stores TTL compatible inputs, and those in location $007 store
the result of comparison Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. IS (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant, apply the charging curve to the D7 pin. The construction described above is shown in Fig. IS (c). The compared
result of Do to D6 is regularly monitored, which gives the
analog input electric potential applied to Do to D6 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two functions gives 3 level voltages from Do to D6. Fig. IS (d) provides
the example when VTH is set to 3.SV.

• BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test

A.

B.

Port A

Port B
A,

_ _ _ _~IC· hFE' 18

/

···
•
•
••
•

B,

Port A Programmed a. outputlsl,driving CMOS and TTL Load directlv.
lal

Port B Programmed as output(s) ,driving Darlington ba.e directlV·

Ibl

+V

+V

A

A

c.

··•
·•

-

Port B

IOmA max
B,

CMOS Inverter

C,

Port B Programmed as outputlsl,driving LEOI.I directlv.
lei

Port C Programmed as outputlsl, driving CMOS loads, using
(dl
external pull·up

Figure 14 Typical Port Connections

184

.....- - -....-

•

HITACHI

---------------------------------------------------------------HD6805Ul
vides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide turnon at some later time which would permit pulse.width modida·
tion of the controlled power.

instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit 1 of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro·

$003 Read

Input Port
(0 0 -0 6 1

Internal Bus

(BilO - Bit61

+

$003 Read

Input Port (0,1

Internal Bus

(Bit 71
(al The logic configuration of Port 0

Port
C

r--..._
0,

Reference Level

D.

Port
0

Analog Input 6

0,

Port

\
D.

c.

o

0,
I-=---Analog Input 6

D.

1-"'--- Analog Input 0

Analog Input 0

(bl Seven analog inputs and a reference level input of Port 0

c.

~

D7~

(cl Application to AID convertor

0,
VTH (= 3.5V)
D.

3 Levels Input 6

Input

($003)

($0071

OV-O.SV

0
1
1

0
0
1

Voltage
Port
0

2.0V - 3.3V

\
D.

3.7V - Vee

3 Levels Input 0

(dl Application to 3 levels input

Figure 15 Configuration and Application of Port 0

•

HITACHI

185

HD6805U1---------------------------------------------------------------

SELF 1

··•
·
··•
·

BRCLR 0, PORT A, SELF 1
BSET I, PORT A
BClR I, PORT A

Figure 16 Bit Manipulation Example

• ADDRESSING MODES
The CPU has ten addressing modes available for use by the
programmer. They are explained and .illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 17. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 18. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 19. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 20. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pc)t2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign -bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 21. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
• Indexed (8-bit Offset)
Refer to Figure 22_ The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
• Indexed (16-bit Offset)
Refer to Figure 23. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.

186

•

• Bit Set/Clear
Refer to Figure 24. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 25. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 26. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All implied addressing instructions are one byte long.
•

INSTRUCTION SET
The MeU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
• Read/Modity/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.
• Control I nstructions
The control instructions control the MeU operations during
program execution. Refer to Table 6.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 7.
• OpcodeMap
Table 8 is an opcode map for the instructions used on the
MeV .

HITACHI

---------------------------------------------------------------HD6805Ul
lEA

I

Melorv
i
i
i
i

i

/'

I

8
05BF

F8

A
F8

I
I

I
I

I

I
I
I

Stack POlOt

I

AS

~

Adder

IndFq

•

PROG LOA #$F8 058E

I

t

i
i

I
Prog Count

05CO
CC

•

I

I

i

§
I
I
I
I

Figure 17 Immediate Addressing Example

lEA

,

Melorv

i

I
i
i
i
i
i

i
i

I
i

CAT

FCB

32

I

1

/

Adder

.~

A

ooto

20

004B

I

004B

L

20

I

Index Reg

i

I

PROG

LOA

CAT

0520

B6

052E

4B

I

I

I

I

Stack Point

I

Prog Count

I

052F
CC

I

~

i

I
i

I

I

I

i

•

:
,

Figure 18 Direct Addressing Example

_HITACHI

187

HD6805U1------------------------------------------------------------

Memory

0000
A
40
PROG

LOA

CAT

Index Reg

Stack Point

Prog Count
CAT

FCB

64

~E5~____~~_____t------------------------~

040C
CC

Figure 19 Extended Addressing Example

Memory

iI

@

A

Index Reg

Stack Point

I

PROG

SEQ

PROG2

04A7
04AS

0000

27

t---,-S----i

~
I

,

I

,

Figure 20 Relative Addressing Example
188

•

HITACHI

-----------------------------------------------------------------HD6805Ul
lEA

I

Melorv

I

i

t

i

I

I

I
I

I
I

I

I

I

I

0068

/

~

Adder

A
TABL

010

4C

FCC / LI/ 00B8

4C

49

68
I

PROG

LOA

X

I

Index Reg

I

1

Stack POint

""~

Prog Count

05F5
CC

§
I

I

,

I

Figure 21

Indexed (No Offset) Addressing Example

1EA
MeJorv
I
I

i
I

FCB

#BF

0089

BF

FCB

#86

oo8A

86

FCB

#OB

008B

DB

FCB

#CF

008C

CF
I
I

/

I

008C

t

I

I
TABL

I

Adder

~
A
CF

I

I

Index Reg

I

I
I

03

I

Stack POint

PROG

LOA

TAB L. X 075B

E6

075C

B9

I

I

,

Prog Count

I

0750
CC

I

I

I

~
i

I

Figure 22 Indexed (8·Bit Offset) Addressing Example

•

HITACHI

189

HD6805U1--------------------------------------------___________________

PROG

lOA TABl. X

,

,

I

I

L

~

0780

/

I

Adder

A
-1

I

0692~

I I

0693

07

0694

7E

DB

02

11

I

I
Prog Count

I

0695.

TABl

CC

I

FCB

#BF

077E

BF

FCB

#86

077F

86

FCB

#oB

0780

DB

FCB

#CF

0781

CF

I

I

Figure 23 Indexed (l6-Bit Offset) Addressing Example

Memory

PORTS

EaU

BF

0001

I

A

0000
Index Reg
PROG BClR 6. PORT B

058F

1-_ _1_0_ _-1

0590

01

Stack Point

Prog Count
0591
I

I

CC

~
I
I

I
I

Figure 24 Bit Set/Clear Addressing Example

190

J

Stock Point

IJ1-------'

I

J

Index Reg

•

HITACHI

HD6805U 1

PORT C

EQU

0002

2

A

FO

Index Reg

Stack POint

PROG BRCLR 2. PORT C. PROG 2

0574
0575
0576

r-----~
05

Prog Count

02

0594

r----1-0- - -1

CC

I

§
I

. Example
Figure 25 B'It T est and B ranch Add ressmg

EA
Memory

I
I
I

~

II
I

PROG

TAX

A

I

E5

!

O~As

Stack Point

Prog Count

05BB
CC
I

I

I

I

~
I

Figure 26 Implied Addressing E xample

•

HITACHI

191

HD6805U1--------------------------------------------------------------Table 2 Register/Memory Instructions
Addressing Modes
Function

Mnemonic

Indexed

Indexed
(No 011 .. ,)

Extended

Direct

Immediate

Op
Op
Op
#
#
Op
#
#
#
#
Cod. Bvtes Cycles Code By,•• Cycles Cod. Bytes Cycles Cod.

Indexed
(16-Bi,Ollse,)

(S-Bi,Ollse"

#
Op
#
Bytes Cycles Code

#
#
Op
#
#
Bytes Cycles Code Bytes Cycles

Load A from Memory

LOA

A6

2

2

S6

2

4

C6

3_

5

F6

1

4

E6

2

5

06

3

6

Load )( from Memory

LOX

AE

2

2

BE

2

4

CE

3

5

FE

1

4

EE

2

5

OE

3

6

Store A in Memory

-Store
- X in Memory

STA

-

-

B7

2

5

C7

3

6

F7

1

5

E7

2

6

07

3

7

STX

-

-

BF

2

5

CF

3

6

FF

1

5

EF

2

6

OF

3

7

Add Mttmory to A

ADD

AB

2

2

BB

2

4

CB

3

5

FB

1

4

EB

2

5

OS

3

6

ADC

A9

2

2

S9

2

4

C9

3

5

F9

1

4

E9

2

5

09

3

6

SUB

AO

2

2

SO

2

4

CO

3

5

FO

1

4

EO

2

5

DO

3

6

SBC

A2

2

2

B2

2

4

C2

3

5

F2

1

4

E2

2

5

02

3

6

AND Memory to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

1

4

E4

2

5

04

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

DA

3

6

EOR

AS

2

2

BS

2

4

ca

3

5

Fa

1

4

ES

2

5

OS

3

6

CMP

AT

2

2

Bl

2

4

Cl

3

5

Fl

1

4

El

2

5

01

3

6

CPX

A3

2

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

03

3

6

Add Memory and
~.YtoA

Subtract Memory
Subtract Memory from

A with Borrow

Exclusive OR Memory
with A

ArithlTletic Compare A
with Memory
Arithmetic Compare X
with Memory

Bit Test Memory with A

-

BIT

A5

2

2

Jump Unconditional

JMP

-

Jump to Subroutine

JSR

-

-

-

(Logical ComPMI)

B5

2

4

C5

3

5

F5

1

4

E5

2

5

05

3

6

BC

2

,3

CC

3

4

FC

1

3

EC

2

4

DC

3

5

BD

2

7

CD

3

a

FD

1

7

ED

2

a

DO

3

9

Table 3 Read/Modify/Write Instructions
Addressing Modes
Function

Implied (A)

Mnemonic

Implied (X)

Indexed
(No Offset)

Direct

Indexed
(8-Bit Offset!

Qp
Op
Op
Op
#
#
#
#
#
#
#
#
#
#
Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles

Op
Code

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

7

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

Negate
(2', Complement)

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7

Rot.t. Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

7

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

7

Arithmetic Shift Right

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

2

7

Arithmetic Shift Left

ASL

48

1

4

58

1

4

38

2

6

78

1

6

6B

2

7

6

60

2

7

Test for Negative or
Zero

192

TST

40

i

1

4

50

1

4

30

_HITACHI

2

6

70

1

----------------------------------------------------------HD6805U1
Table 4 Branch Instructions
Relative Addressing Mode
Function

Mnemonic

Branch Always
Branch Never
Branch IF Higher

BRA
BRN
BHI

Branch I F Lower or Same
Branch I F Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set

BLS
BCC
(BHS)

Op
Code
20
21
22
23
24
24

BCS
(BLO)

(Branch IF Lower)
Branch I F Not Equal
Branch I F Equal

BNE
BEQ

Branch I F Half Carry Clear

BHCC
8HCS

Branch I F Half Carry Set
Branch I F Plus

BPL
BMI
BMC

#

#

Bytes
2
2

Cycles
4
4
4
4
4
4

25
25
26

2
2
2
2
2
2
2

27
28

2
2

29
2A

2
2
2
2

Branch IF Minus
Branch I F Interrupt Mask Bit is Clear
Branch I F Interrupt Mask Bit is Set
Branch IF Interrupt Line is Low
Branch IF Interrupt Line is High

BMS
BIL
BIH

2C
20
2E
2F

Branch to Subroutine

BSR

AD

2B

4
4
4
4
4
4
4
4
4

2
2

4
4

2
2

4
8

Table 5 Bit Manipulation Instructions
Function

Mnemonic

Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear bit n

Bit Set/Clear

BRSET n (n=O ..... 7)
BRCLR n (n=O ..•.. 7)
BSET n (n=O •.... 7)
BCLR n (n=O ..... 7)

Op
Code

Bytes

-

-

10+2 o n
11+2 o n

2
2

#

Addressing Modes
Bit Test and Branch
Op
#
#
#
Cycles
Cycles
Bytes
Code
2 n
3
10
01+2 o n
3
10
7
7

-

0

-

-

-

-

-

Table 6 Control Instructions
Implied
Function

Mnemonic

Transfer A to X

TAX
TXA
SEC

Op
Code
97
9F

#

#

Bytes

Cycles

1
1
1

CLC

99
98

2
2
2

1

2

Set Interrupt Mask Bit
Clear Interrupt Mask Bit

SEI

9B

CLI

9A

Software Interrupt

SWI
RTS
RTI

83
81

2
2
11

Return from Subroutine
Return from Interrupt

1
1
1
1

80

1

9

Reset Stack Pointer
No·Operation

RSP
NOP

9C
90

1
1

2
2

Transfer X to A
Set Carry Bit
Clear Carry Bit

•

HITACHI

6

193

HD6805U1----------------------------------------____________________
Table 7 Instruction Set
Addressing Modes
Mnemonic

ImmeImplied diate

ADC

x

ADD

x
x

AND

Direct

x
x
x

ASl

x

x

ASR

x

x

Extended

Relative

x

Condition Code

Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x

x

x

x

x

x

x

x

x

x

x

x

Bit
Set/
Clear

BCS

x

BEQ

x

BHCC

x

BHCS
----

x

BHI

x

BHS

x

BIH

x
x

BIT

x

x

BlO

x
x

BMC

x

BMI

BMS

x
x

BNE

x

BPl

x
x
x

--------

BRA
BRN

x

BRSET

x

BSET

x
x
x
x

CLI
ClR

x
x

CMP

x

COM
DEC

.

x

x

x

x

x

x

x
x

x

x

x

x

x

x

lOA

x

x

x

x
x
x
x

lDX

x

x

x

x

x

x

INC

x
x

JMP
JSR

Condition Code Symbols:
H
Half carry (From Bit 3)
I
Interrupt Mask
N
Negativa (Sign Bit)

194

x

x

x

EaR

x
x

x
x

CPX

x

x

x

1\

•

1\
1\

1\
1\

1\
1\

•
•
•
•

x

x
x

ClC

C

•
•

BRClR

BSR

Z

•
•

x

BlS

N

•
•
•
•
•
•
•

x

Bil

I

•
• •

x

BClR

H

1\

x

BCC

Z

Bit
Test &
Branch

x

x

x
x

x

x

x
x

x

x

x

x

x

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•

•
•
•
•

•
1\
•
1\
•
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• 1\ 1\ •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • •
• • • 1\
• • • 1\
• • • •
• • • •
• • • 0
0 • • •
• 0 1 •
• 1\ 1\ 1\
• 1\ 1\ 1
• 1\ 1\ 1\
• 1\ 1\ •
• 1\ 1\ •
• 1\ 1\ •
• • • •
• • • .
• 1\ 1\ •
• 1\ 1\ •
1\
1\
1\

1\
1\
1\

~

(to be continued)
C

1\
•

Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected

Zero

_HITACHI

---------------------------------------------------------------HD6805U1
Table 7 Instruction Set
Addressing Modes
Mnemonic
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STX
SUB
SWI
TAX
TST
TXA

Implied

Immediate

x
x
x

Direct

Extended

Relative

x

x
x

Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x

x

X

x

X

x

X

x

X

x

X

Bit
Setl
Clear

x
x

x
x

x

x

x

x

X

x
x

x
x

x

x

X

x

x

x

x

X

x

x
x

x
x

x
x

x

X

X

X

x

x

x

x
x

x
x
x

x
x

Condition Code Symbols:
H
Half Carry (From Bit 31
I
Interrupt Mask
N Negative (Sign Bid
Z
Zero

x

C

Bit
Test & H
Branch

I

N

Z

•
•
•
•
•
•
•
•
?
•
•
•
1
•
•
•
• 1
• •
• •
• •

/\

/\

/\

0

/\

/\

/\

/\

/\

•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•

C

• • •
•

/\

/\

1\

/\

/\

/\

/\

/\

• • •
? ? ?
• • •
/\ /\ 1\
• • 1
• • •
/\ 1\ •
/\ /\ •
/\ /\ /\
• • •
• • •
/\ 1\ •
• • •

Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Afleeted
Load CC Register From Stack

1\
•
?

•

HITACHI

195

HD6805U1--------------------------------------------______________~-Table 8
Bit Manipulation

,XO

IMP

IMP

IMM

I

OIR

EXT

I

6

I

7

8

9

A

I

I

B

I

C

I

A

1

2

3

I

4

BSETO

BRA

NEG

RTI'

-

RTS'

Branch

Clear

(NOTE)

I

I

I

X

I

5

I
I

BCLRO

BRN

BSETl

BHI

BCLRl

BLS

COM

BSET2

BCC

LSR

BCLR2

BCS

BSET3

BNE

ROR

BCLR3

BEQ

ASR

BSET4

BHCC

LSL/ASL

BCLR4

BHCS

ROL

BSET5

BPL

DEC
INC

BClR6

BMS

TST

BSET7

Bil

-

BClR7

BIH

2/7

2/4

SWI'

-

-

-

-

BMC

BSET6

-

-

BCl_~ yMI

ClR

2/6

I 1/4

I 1/4

RegisterIMemory

,Xl

OIR

Setl

3/10

Control

Read/Modify!Write

Branch
Rei

Test &

0
0 BRSETO
1 BRCLRO
2 BRSETl
3 BRCLRl
4 BRSET2
5 BRCLR2
6 BRSET3
7 BRCLR3
8 BRSET4
9 BRCLR4
A BRSET5
B BRCLR5
C BRSET6
0 BRClR6
E BRSET7
F BRCLR7

Opcode Map

I 2/7

I 1/6

-

,X2

0
SUB
CMP

I

)<1

I

,XO

I

E

I

F

1

SBC

2

CPX

3

l

-

AND

4

o

-

BIT

5 W

LOA

6

TAX

-

I

STA(+lI

7

EOR

SEC

ADC

8
9

CLI

ORA

A

SEI

ADD

B

JMPH)

C

JSR(-3)

0
E
F

CLC

RSP
NOP

-

-

TXA

1/'

1/2

-

I
BSR'I

lOX

- I
2/2 I 2/4

STX(+l)
I 3/5

I 3/6

I 2/5

2. The number at the bottom of each column denote the number of bytes and the number of cycles reQuired (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cvcles as follows:

RTI
9
RTS
6
SWill
BSR
8

196

indicate that the number in parenthesis must be added to the cycle count for that instruction .

•

HITACHI

HIGH

0

1. Undefined opcodes are marked with "-".

3. (

-

I 1/4

HD6805V1--------------MCU (Microcomputer

Unit)

The H0680SVI is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, I/O and
timer. It is designed for the user who needs an economical
microcomputer with the proven capabilities of the H068oo·
based instruction set.
The foUowing are some of the hardware and software high.
lights of the MCU.
•
•
•
•
•
•
•
•
•
•
•
•
•
•

HD6805V1P

HARDWARE FEATURES
8·8it Architecture
96 8ytes of RAM
Memory Mapped I/O
3848 Bytes of User ROM
Internal 8·Bit Timer with 7·8it Prescaler
Vectored Interrupts - External and Timer
24 I/O Ports + 8 Input Port
18 Lines LED Compatible; 7 Bits Comparator Inputs)
On-C;hip Clock Circuit
Self-Check Mode.
Master Reset
Low Voltage Inhibit
Complete Development System Support by Evaluation Kit
5 Vdc Single Supply
• PIN ARRANGEMENT

SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM. RAM and I/O
Compatible Instruction Set with MC6805P2
•

IDP-40)

A.
A.
A,
A.
A,
A,

.
A,

B.

HD6805Vl

BLOCK DIAGRAM

...
...
B,
B,
B,
B.
Do

..
pr ::

....

,

LIII,
IInternall

TIR; Timer Interrupt Request
TIM; Timer Interrupt Mask
Timer
Input

Pin

,.-----,
•

I

I

I

I

I

IL _____ ..II

Manufacturing

Mask Options
Write

Read

Figure 5 Timer Block Diagram

_HITACHI

201

HD6805V11-----------------------------------------------------------------before decrementing the counter (TOR). The timer continues
to count past zero, falling through to $FF from zero and then
continuing the count. Thus, the counter (TOR) can be read at
any time by reading the TOR. This allows a program to determine the length of time since a timer interrupt has occurred
and not disturb the counting process.
The TOR is 8-bit Read/Write Register in location $008.
At power-up or reset, the TOR and the prescaler are initialized
with alii ogical ones.
The Timer Interrupt Request bit (bit 7 of the TCR) is set by
hardware when timer count reaches zero, and is cleared by program or by hardware reset. The bit 6 of the TCR is writable by
program. Both of those bits can be read by CPU.
(NOTE) If the MCU Timer is not used. the TIMER input pin
must be grounded.

•

SELF CHECK

The self-check capability of the MCU provides an internal
check to determine if the part is functional. Connect the MCV
as shown in Figure 6 and monitor the output of port C bit 3 for
an oscillation of approximately 3Hz.
•

RESETS

The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal
low voltage inhibit circuit, see Figure 7. All the I/O port are
initialized to input mode (OORs are cleared) during reset.
During power-up, a minimum of 100 milliseconds is needed
before allowing the RES input to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure 8,
typically provides sufficient delay.

A, 40

2..

INT

2

RES

A, 38

XTAL

A, 36

A, 39

T

A.~

2 .2I'F

C

A, 35
A, 34

EXTAL

~

V cc

~

f..E.--

B, 31

NUM

B, 30
B. 29

330n

to:l

9

C,

B.~

33~n

\C b 1 0

C,

B, 27

33C{ n

r-; ~11 C,

B, 26

C,

B" 25

1.30n '!:! fc.12
~13
10kn
10kn

.J..ot. nv
J.0t.~v
V cc

=:

Pm 4

vss

=:

Pin 1

~Pin

A,

HD6805V1.
8 TIMER (Resistor option)
B,

+9V

C.
14 C,
15 C,
16

c,
• Refer to F, gure 9 about crystal option

Figure 6 Self Check Connections

------f

Internal

Reset

--------'
Figure 7 Power Up and RES Timing

202

•

HITACHI

-------------------------------------------------------------HD6805Vl
•

INTERNAL OSCILLATOR OPTIONS
The internal oscillator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper
wire, or an external signal may be used to generate a system
clock with various stability/cost tradeoff. A manufacturing
mask option is required to select either the crystal oscillator or
the RC oscillator circuit. The different connection methods are
shown in Figure 9. Crystal specifications are given in Figure 10.
A resistor selection graph is given in Figure 11.

2

Part of

------

HD6805Vl

MCU

Figure 8 Power Up Reset Delay Circuit

6 XTAL

6 XTAL
MaH
4m
xZ

c::J

5

HD6805Vl

EXTAL

5 EXTAL

HD6805Vl

MCU

MCU

22P F±20"T

Crystal

Approxlmatelv 25% Accuracy
External: Jumper

6 XTAL

6 XTAL
External
Clock
Input

5 EXTAL

HD6805Vl

5 EXTAL

MCU

H06B05Vl

MCU

No
Connection

External Clock

Approximately 15% Accuracv

External Resistor

CRYSTAL OPTIONS

RESISTOR OPTIONS

Figure 9 Internal Oscillator Options

5
C,

~+--

XTALC'
6
C-

•

HS

I

I

EXTAL
5

\

...

:I:

~
>

3

Vce= 5.25V_
TA=25°C

\

'\

u

c

":>0-

AT - Cut Parallel Resonance Crvstal
COl = 7 pF max.

I!!

u.

2

"

~

104 MHz
RS = 50!! max.

~

~

~

Figure 10 Crystal Parameters

o

5

10

J

I

~

4

15

20
25
30
Resistance (knl

35

40

~

45

50

Figure 11 Typical Resistor Selection Graph

•

HITACHI

203

HD6805Vl------------------------------______________________________

1-1
7F -SP

Stack
PC,X,A,CC

o -DDR's

CLR INT Logic
FF -+ Timer
7F -+ Prescaler

7F _TCR

TIMER
Load PC From
SWI :$FFC, $FFD
fNi:$FFA, $FFB
TIMER:$FF8,$FF9

Load PC From
Reset:$FFE, $FFF

Fetch
Instruction

Y

SWI

Execute
Instruction

Figure 12 Interrupt Processing Flowchart

Data
Direction

Output
Data Bit

Output
State

Input to

Register

o

o

o

3-State

Pin

MCU

Bit

Figure 13 Typical Port 1/0 Circuitry

204

•

HITACHI

o

---------------------------------------------------------------HD6805Vl
• INTERRUPTS
The CPU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request, and a software interrupt instruction (SWI)_ When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack, the interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is
obtained from the appropriate interrupt vector address, and the
interrupt routine is executed_ The interrupt service routines
normally end with a return from interrupt (RTI) instruction
which allows the CPU to resume processing of the program
prior to the interrupt. Table 1 provides a listing of the interrupts, their priority, and the vector address that contain the
starting address of the appropriate interrupt routine_
A flowchart of the interrupt processing sequence is given
in Fig. 12.
Table 1 Interrupt Priorities
Interrupt

RES
SWI

TNT
TIMER

Priority
1·
2
3
4

Vector Address
$FFE and $FFF
$FFC and $FFD
$FFA and $FFB
$FF8 and $FF9

• INPUT/OUTPUT
There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the corresponding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output
loading (see Fig. 13). When Port B is programmed for outputs
it is capable of sinking lOrnA on each pin (VOL = IV max).
All input/output lines are TTL compatible as both inputs and

outputs. Port A is CMOS compatible as outputs, and Port Band
C lines are CMOS compatible as inputs. Figure 14 provides some
examples of port connections.
• INPUT
Port D can be used as either 8 TIL compatible Inputs or I
threshold input and 7 analog inputs pins. Fig. 15 (a) shows the
construction of port D. The Port D register at location $003
stores TIL compatible inputs, and those in location $007 store
the result of comparison Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 15 (b). Also, using
one output pin of MCU, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
constant, apply the charging curve to the D7 pin. The construction described above is shown in Fig. 15 (c). The compared
result of Do to D6 is regularly monitored, which gives the
analog input electric potential' applied to Do to D6 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two functions gives 3 level voltages from Do to D6. Fig. 15 (d) provides
the example when VTH is set to 3.5V.
• BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 16
illustrates the usefulness of the bit manipulation and test
Bo

Port A

Port B

··

·

B,
Port A Programmed as outputlsl, driving CMOS and TTL Load directly.
lal

Port B Programmed as output(s), driving Darlington base directly.

Ibl
+V

+v

R

Bo
Port B

···•••
·

Co

-

Port C

10mAmax

B,

···

t----+--.

CMOS Inverter

C,

Port B Programmed as outputlsl, driving LEDlsl directly.
lei

Port C Programmed as output lsi, driving CMOS loads, using external pull-up
resistors.
(d)

Figure 14 Typical Port Connections

_HITACHI

205

HD6805V1------------------------------------------------------------vides turn-on of the TRIAC within 14 microseconds of the zero
crossing. The timer could also be incorporated to provide tumon at some later tinte which would permit pulse-width modUlation of the controlled power.

instructions. Assume that bit 0 of port A is connected to a zero
crossing detector circuit and that bit I of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, pro$003 Read
Internal BUI
IBitO - Bit61

+

$003 Read

Input Port 10,1

Internal' Bus

IBit 71
lal The logie configuration of Port 0

Port
C

r----._
0,

Reference Level

O.

Port
0

c.

Analog Input 6

0,

Port

\

o

o.

I-~--Analog

D.

D.

I-~--Analog

Analog Input 0

Ibl Seven analog input. and a reference level input of Port 0

Q,

VTH

o.

(=

Input 0

leI Application to AID convertor

3.5VI

3 Levell Input 6

Port
0

~':!....
OV-O.BV
2.0V- 3.3V

\
D.

Input 6

3.7V-V CC

1$0031

1$0071

0
1
1

0
0
1

3 Levels Input 0

Idl Application to 3 levels input

Figure 15 Configuration and Application of Port 0

206

•

HITACHI

---------------------------------------------------------------HD6805V1

SELF 1

··
··

•

Bit Set/Clear

Refer to Figure 24. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.

BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A

•

Bit Test and Branch

The CPU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.

Refer to Figure 25. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.

•

•

Implied

•

INSTRUCTION SET

Figure 16 Bit Manipulation Example
• ADDRESSING MODES

Immediate

Refer to Figure 17. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
•

Direct

Refer to Figure 18. In direct addressing, the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
•

Extended

Refer to Figure 19. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
•

Relative

Refer to Figure 20. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pC)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of + 129 bytes to -127 of the present instruction. These
instructions are two bytes long.
•

Indexed (No Offset)

Refer to Figure 21. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
•

Indexed (S-bit Offset)

Refer to Figure 26. The implied mode of addressing has no
EA. All the information necessary to execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belong to this
group. All in1plied addressing instructions are one byte long.
The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write, branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
•

Register/Memory Instructions

Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 2.
•

Read/Modity/Write Instructions

These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
3.
•

Branch Instructions

The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 4.
• Bit Manipulation Instructions

These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 5.

Refer to Figure 22. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.

• Control Instructions

•

•

Indexed (16-bit Offset)

Refer to Figure 23. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.

The control instructions control the MCU operations during
program execution. Refer to Table 6.
Alphabetical Listing

The complete instruction set is given in alphabetical order in
Table 7.
• Opcode Map

Table 8 is an opcode map for the instructions used on the
MCU.

~HITACHI

207

HD6805V1---------------------------------------------------------------

I

I
I

8

F8
In1xROQ
Stack Point

I

PROG LOA #$F8

I
I

::::I~---;:::~-~Ii-----------'

Prog Count
05CO
CC

~
I

I

I
I

Figure 17 Immediate Addressing Example

I

Melorv

I

I

I
I
I

I
I

FCB

32

LOA

CAT

/

+

Adder

I

'"

Jo

20

OO4B

I

PROG

i

0048

I

I
I

CAT

lEA

I

A
_I

I

I

0520

86

052E

4B

Stack Point

I
I

I
Prog Count
052F
CC

~
I
I

I
I

,

I
I
I

:,

Figure 18 Direct Addressing Example
208

•

HITACHI

20
Index Reg

I

-------------------------------------------------------------------HD6805V1

Memory
I

I
I
I

I

~
I

PROG

LOA

CAT

FCB

64

A

I

-~J

O4OA

06

040B

E5

40
Index Reg

Stack Point

I
I

I
I

CAT

0000

Prog Count
040C

40

06E5

CC

Figure 19 Extended Addressing Example

lEA
Memory

i
i

I

I

~
I

BEQ

PROG2

~

/
I

I
I

04A7

27

O4A8

18

I

04Cl

i
i

I

PROG

I

Adder

t
OR

l-

oot

'"
I

A

I
I
I

Index Reg

..J
I

Stack Point

Prog Count

y

I

04Cl

iI

CC

I

I

~
I

,

I

z

I

I

I

,

Figure 20 Relative Addressing Example

•

HITACHI

209

HD6805Vl-----------------------------------------------------------lEA
Melorv

,i

I

I
I
I

I

I
I

I

TABL

,,

I

OOB8

/

Adder

""

Jo

4C

FCC I LI/ 0088

I

t

49

A

LOA

I

B8
Stack Point

./

PROG

I

4C
Index Reg

X

Prog Count
05F5
CC

Figure 21

Indexed (No Offset) Addressing Example

lEA
Melorv
I

I

•i
TAIL

I

0089

#86

008A

86

#OB

OOBB

DB

#CF

008C

CF

#BF

FCB
FCB
FCB

I

/

Adder

I
I
I

•
PROG

ooac

LOA TABL. X 0758

E6

075C

89

I

t

I

SF

FCB

I

""

CF

I

Index Reg

I

03

I

Stack Point

I

I

I

Prog Count

I
I

~
,
I

Figure 22 Indexed (S·Bit Offset) Addressing Example

210

A

eHITACHI

0750
CC

I

---------------------------------------------------------------HD6805Vl
lEA

I

Melorv
i
i

i
i

lOA TABl. X 0692
0693
0694

Adder

~

A

_I
1

I
I

IJ

#BF

077E

BF

FeB

#86

077F

86

FeB

#OB

0780

DB

FeB

#CF

07Bl

CF

02

I

I

I
I
I

Prog Count

0695
CC

i

FeB

I

Stack Point

07

7E

DB
Index Reg

I

i

TABl

L

~
~

I
PROG

~

I

I

I

0780

I

Figure 23 Indexed (16·Bit Offset) Addressing Example

Memory

PORTB

EOU

BF

0001

A
0000
Index Reg
PROG BClR 6. PORT B

058F

t-___10_ _- i

0590

01

Stack Point

Prog Count

0591
,

I

CC

~
,
i

I

Figure 24 Bit Set/Clear Addressing Example

•

HITACHI

211

HD6805Vl------------------:========-________________________________

PORT C

EOU

ooo2.-----.....i
FO

2

A

Index Reg

0000

Stack Point

PROG BRCLR 2. PORT C. PROG 2

0574
0575
0576

r------~
05

Prog Count

r---0;';;2--J

r---,;;.:O:.....-Jr----.J

0594
CC

T

I

§
•

. Example
Figure 25 B'It Test and Branch Add ressmg

EA
Memory

I
I
I

§
I

I

PROG

TAX

I

~As
I

'

0588

,,

CC
I

I

~
I

I
I
I

!
Figure 26 Implied Addressing E xample

212

•

HITACHI

----------------------------------------------------------------HD6805V1
Table 2 Register/Memory Instructions
Addressing Modes
Mnemonic

Function

Extended

Direct

Immediate

Indexed

Indexed

Indexed

INoOf'..,)

18·8i,Oll..,)

116·Bi,Oll••,)

Qp
#
#
Bytes Cycles Cod.

Qp
Op
Op
#
#
#
#
Cod. Bytes Cycles Cod. Bytes Cycles Cod.

Op
#
#
Bytes Cycles Cod.

Op
#
#
Bvtes Cycles Code

#

#

Bytes Cycles

Load A from Memory

LOA

A6

2

2

B6

2

4

C6

3_

5

F6

1

4

E6

2

5

06

3

6

Load X from Memory

LOX

AE

2

2

BE

2

4

CE

3

5

FE

1

4

EE

2

5

DE

3

6
7

Store A in Memory

STA

-

-

2

5

C7

3

6

F7

1

5

E7

2

6

07

3

STX

-

B7

Store X in Memory

BF

2

5

CF

3

6

FF

1

5

EF

2

6

OF

3

7

Add Memory to A

ADD

AB

2

2

BB

2

4

C8

3

5

FB

1

4

EB

2

5

DB

3

6

6

Add Memory
Carry to A

and

AOC

A9

2

2

69

2

4

C9

3

5

F9

1

4

E9

2

5

09

3

Subtract Memory

SUB

AO

2

2

BO

2

4

CO

3

5

FO

1

4

EO

2

5

DO

3

6

Subtract Memory from
A with Borrow

SBC

A2

2

2

62

2

4

C2

3

5

F2

1

4

E2

2

5

02

3

6

AND Memory to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

1

4

E4

2

5

04

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

OA

3

6

E)(clusive OR Memory

E06

A8

2

2

B8

2

4

C8

3

5

F8

1

4

E8

2

5

08

3

6

Arithmetic Compare A
with Memory

CMP

Al

2

2

Bl

2

4

Cl

3

5

Fl

1

4

El

2

5

01

3

6

Arithmetic Compare X
wnh Memory

CPX

A3

2

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

03

3

6

with A

alt Test Memorv with A

BIT

A5

2

2

B5

2

4

C5

3

5

F5

1

4

E5

2

5

05

J

6

Jump Unconditional

JMP

-

-

BC

2

J

CC

J

4

FC

1

J

EC

2

4

DC

J

5

Jump to Subroutine

JSR

-

BO

2

7

CD

J

8

FO

1

7

ED

2

8

DO

J

9

(Logical Compare)

-

-

Table 3 Read/Modify/Write Instructions
Addressing Modes
Function

Implied (X)

Implied (A)

Mnemonic

Op
Code

Indexed
(No Offset)

Direct

Op
Op
#
#
#
#
Bytes Cycles Code 8ytes Cycles Code

Op
#
#
Bytes Cycles Code

Indexed

(8·8it Offset)

Op
#
#
#
#
Bytes Cycles Code 8ytes Cycles

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

7

Decrement

DEC

4A

1

4

SA

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

SF

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

Negate
(2's Complement)

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

7

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

Logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

7

Arithmetic Shift Right

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

2

7

Arithmetic Shift Left

ASL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

Test for Negative or
Zero

TST

6

70

1

6

60

2

7

40

1

4

50

•

1

4

HITACHI

3D

2

213

HD6805Vl-----------------------------------------------------------Table 4 Branch Instructions
Relative Addressing Mode
Mnemonic

Function
Branch Alwavs
Branch Never
Branch I F Higher

BRA
BRN
BHI

Branch IF Lower or Same
Branch I F Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set

BLS

#

22
23

2
2

Cycles
4
4
4

24
24
25

2

4
4

2
2

4
4

2
2

4
4
4
4
4

BCS
(BLOI
BNE
BEQ

(Branch IF Lower)

Branch I F Half Carry Clear
Branch I F Half Carry Set
I F Plus
IF Minus
I F Interrupt Mask Bit is Clear
IF Interrupt Mask Bit is Set

-------

--~-----

Branch I F Interrupt line is Low

------

#
Bvtes
2
2

BCC
(BHS)

Branch I F Not Equal
Branch IF Equal

Branch
Branch
Branch
Branch

Op
Code
20
21

---------

__~_~c':!..!F Interrupt Line is High
Branch to Subroutine

25
26
27

2

BHCC
BHCS

28
29

2
2

BPL

2A

2

4

BMI

2B

2

4

BMC

2C

2

4

BMS
BIL

20
2E

2
2

4
4

BIH

2F

2

4

BSR

AD

2

8

Table 5 Bit Manipulation Instructions
Mnemonic

Function

Bit Set/Clear
Op
Code

Branch IF Bit n is set
-------------Branch IF Bit n is clear

----------------

- -Set-Bit
- n--- .-----Clear bit n

#
Bvtes

Addressing Modes
Bit Test and Branch
Op
#
#
#
Code
Cvcles
Bvtes
Cycles

BRSET n (n-O ..... 71
BRCLR n (n=O ..... 7)
BSET n (n=O ..... 7)

-

-

-

10+2'n

2

BCLR n (n=O ..... 7)

11+2'n

2

7
7

-

2'n
-01+2'n

3
3

-

-

10
10

-

Table 6 Control Instructions
Implied
Function

Mnemonic

#

#

Bvtes
1

Cycles

T ransler A to X

TAX

T ransler X to A

TXA

97
9F

Set Carry Bit

SEC
CLC

99
98

1
1

2

S£I

9B

1

2

Software Interrupt

CLI
SWI

9A
83

1
1

2
11

Return Irom Subroutine
Return Irom Interrupt

RTS
RTI

81

1
1

6

Reset Stack Pointer

RSP
NOP

1
1

2
2

--------

------

Clear Carr V Bit
Set Interrupt Mask Bit
Clear Interrupt Mask Bit

-----------No·Operation

214

Op
Code

•

HITACHI

80
9C
90

1

2
2
2

9

-----------------------------------------------------------------HD6805V1
Table 7 Instruction Set
Addressing Modes
Mnemonic
Implied

Immediate

ADC

x

ADD

x

x

AND

x
x

ASl
ASR

Direct

x
x
x

Extended

Relative

x
x

x

x

x
x
x

x

x

Cond ition Code

Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x

x
x
x
x

Bit
Set/
Clear

x
x

x

BClR

x
x
x
x
x
x
x
x

BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil

x

BIT

x

x

BlS
BMC
BMI
---------BMS
BNE
BPl
BRA
BRN

-----

-- r - - - - ----1--x

x

x

x
x

BRClR

x

BSET

x
x
x

CLI
ClR

x

CMP

x

COM

x

CPX

x

DEC
INC

--

x

x

JMP
JSR
lDA
lDX

x
x

Condition Code Symbols:
Half CarrV (From Bit 3)
H
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x

1\

1\

•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

•
•
•
•
•
•
•

• •
• •
• •
• •
• •
• •
• •

• •
• •

x

ClC

N

• •
• •
-- • •
• •

BRSET
BSR

I

• •

x
x
x
x
x
x
x
x
x

BlO

H

1\

x

BCC

EaR

Bit
Test &
Branch

x
x
x
x
x
x
x
x
x
x
x

x
x
x

x
x
x
x

•
•
•
•
•

0

•
•
•
•

• •

•
•
•
•
•
•

•
•

1\
1\
1\
1\

Iz
1\
1\
1\
1\
1\

C

1\
1\

•

1\
1\

• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
1\ 1\ •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • 1\1\
• •
• • •
• • •
• • 0
• • •
0
1 •
1\
1\
1\
1\
1\

1\
1\
1\
1\
1\
1\

1\
1
1\
--

•
•

•
• • • •
• • • •
• 1\ 1\ •
• 1\ 1\ •
1\

(to be continued)
C

/\

•

Carry Borrow
Test and Set if True, Cleared Otherwise
Not Affected

HITACHI

215

HD6805Vl------------------------------------------------------~----

Table 7 Instruction Set

Mnemonic
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STX
SUB
SWI
TAX
TST
TXA

Implied

x
x
x
x
x

216

Zero

x
x
x

x
x
x

x

x
x
x

x
x

Condition Code
Bit
Setl
Clear

x

x

x
x
x

x

x

X

X

X

x
)(

,
x

x
x
x

x
x
x

x
x
x

x
x

x

x

x

)(

x
x

x

x
x

x

x

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N Negative (Sign Bitl
Z

Addressing Modes
R-........, Indexed
Indexed Indexed
Ex~(No
Direct tended
latlVe Offset) (8 Bits) (16 Bits)
x
x
x
x
x
x
x
x
x

Immediate

C

1\
•
?

Carry!Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

_HITACHI

Bit
Test & H
Branch

I

N

Z

C

•
•
•

1\

0

1\
1\

1\
1\

1\

1\

1\

• • •
• 1\ 1\
• 1\ 1\
• 1\ 1\
• • •
? ? ? ?
• • • •
• • 1\ 1\
• • • •
• 1 • •
• • 1\ 1\
• • 1\ 1\1\
• • 1\
• 1 • •
• • • •
• • 1\ 1\
• • • •

•

•
•
•
•
•
•
•

'.

•

1\
1\

•
?
•
1\

1

•
•
•

1\

•

•
•
•

-------------------------------------------------------------HD6805V1
Table 8 Opcode Map
Bit Manipulation

Branch
OIR

I

A

3

I

4

BSETO

2
BRA

BCLRO

BRN

BSETI

BHI

-

BCLRI

BLS

COM

BSET2

BCC

LSR

5 BRCLR2
6 BRSET3
7 BRCLR3
8 BRSET4

BCLR2
BSET3

BCS
BNE
BEQ

ROR

9 BRCLR4

BCLR4

A BRSET5
B BRCLR5
C BRSET6

0
0 BRSETO
1 BRCLRO
2 BRSETI
3 BRCLRI
4 BRSET2

SM.I

Clear
1

Control

Read/ModifvlWrite

Rei

Test 8t
Branch

I

X

L

5
NEG

I
I

)(1

I

.XO

6

I

7

IMP

IMM

8

9

A

RTI'

-

I OIR
I

B

I I
EXT

I

C

SWI'

-

-

.X2

0

I )(
I

1

E

I·xo
I

F

-

HIGH

0
1
2

CMP

-

-

I

SUB

-

RTS'

-

Register IMemory

IMP

SBC
CPX

3
4

AND
BIT
LOA
STA(+I)

5 W
6
7

ASR

-

TAX

-

ClC

EOR

B

BHCS

lSl/ASl
ROL

SEC

BSET5

BPL

DEC

AOC
ORA

A

BCLRS
BSET6

BMI

-

BMC

INC

-

BRCLR6

BCLR6

BM!

TST

-

E BRSET7

BSET7

BIL

-

F BRCLR7

BCLR7

BIH

CLR

0

3/10

BCLR3
BSET4

2/7

BHCC

2/4

2/6

I

1/4

I

114

-

I

Cli
SEI
RSP
NOP

-

-

I 2/7 I 116

-

-

TXA

II"

112

I
BSR" I
-

- I
2/2

J

9

ADD
JMP(-t)

B

JSR(-3)

0

lOX

E

C

STX(+I)

2/4

J 3/5

L

o

I 3/6 I

F

2/5

I 114

(NOTE) 1. Undefined opcode. are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles required 'Bytes/Cycles).
Mnemonics followed bV a "." require a different number of cvcles as follows:
RTI
9
RTS
6
SWI
11
BSR
B
3. I
indicate that the number in parenthesis must be added to the cycle count for that instruction .

•

HITACHI

217

HD6805T2--------------MCU (Microcomputer Unit

with PLL Logic)

-ADVANCE INFORMATIONThe H06805T2 is the 8·bit Microcomputer Unit (MCU)
which contains a CPU, on·chip clock, ROM, RAM, I/O, Timer
and the PLL Logic for an RF synthesizer. It is designed for the
user who needs an economical microcomputer with the proven
capabilities of the HD6800·based instruction set.
The following are some of the hardware and software high·
lights of the MCU.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

HD6805T2P

HARDWARE FEATURES
8·Bit Arthitecture
64 Bytes of RAM
Memory Mapped I/O
2508 Bytes of User ROM
Internal8·Bit Timer with 7·Bit Prescaler
Timer Start/Stop and Source Select
Vectored Interrupts - External and Timer
19 TIL/CMOS Compatible I/O Lines; 8 Lines are LED com·
patible
On-Chip Clock Circuit
Self-Check Mode
Master Reset
Low Voltage Inhibit
14·Bit Binary Variable Divider
10-Stage Mask·Programmable Reference Divider
Three-State Phase and Frequency Comparator
Suitable for TV Frequency Synthesizers
5 Vde Single Supply
SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805T2

(DP·28)
• PIN ARRANGEMENT

A,
A,
A,
A,

A,
A.

A.

8,
8,
B.

B.

B,

B.

B.

8,

(Top View)
• BLOCK DIAGRAM

POrt

A

liD
LIft"

A,
A.
A.
A.
A,
A.

Port
A

00..

R ...

R ...

D"

'"

A'

•
S

lode"
Register

X

CondItion
Cod.
RegISter

CPU

Steck

""
• '.B.B.

Pon

110

Lints

....

Pointer

Po..

D...
0 ..

R...

R ...

•

B.

Progr.m
Counter

• .....om

"High" PCH

Counter

8

218

eHITACHI

"Low" pel

HD6805W1

MCU

(Microcomputer Unit)

The H06805Wl is an 8·bit microcomputer unit (MCU)
which contains a CPU, on-chip clock, ROM, RAM, standby
RAM, an A/D Converter, I/O and two timers. It is a member of
the H06805 family which is designed for user who needs an
economical microcomputer with proven capabilities of the
H06800·based instruction set.
The following are some of the hardware and software high·
lights of the MCU.
•
•
•

•
•
•
•
•
•
•

HARDWARE FEATURES
8·Bit Architecture
96 Bytes of RAM
(B bytes are standby RAM functions)
Memory Mapped I/O
3848 Bytes of User ROM
Internal8·Bit Timer (Timer 1) with 7·Bit Prescaler
Internal8·Bit Programmable Timer (Timer 2)
I nter,upts - 2 External and 4 Timers
23 TTL/CMOS compatible I/O Lines; 8 Lines Directly
Drive LEOs.
On·Chip 8-Bit, 4·Channel A/D Converter
On-Chip Clock Circuit
Self·Check Mode
Master Reset
Low Voltage Inhibit
Complete Development System Support by Evaluation Kit
5 Vdc Single Supply

•
•
•
•
•
•
•
•
•
•
•
•
•
•

SOFTWARE FEATURES
Similar to HD6800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/F lags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible with MC6805P2, HD6805S1 and HD6805V1

•
•
•
•
•
•

$

-PRELIMINARY-

HD6805W1P

(DP-40)

•

PIN ARRANGEMENT

Vss
RAME/RES
INT,
vee
EXTAL
XTAL

A,
A.
A,
A.

A,

TIMER

Co

c,
c,
c,

HD6805W1

C.
IC/C,

oc/c.
INT,/D.
AN./D,
AN,/D,
AN,/D,
AN,/D.

A,
A,
A.
B,
B.
B,
B.
B.
B,
B,
B.
AVec
AVss
VRH/D,
Vee Standby

(Top View)

HITACHI

219

HD6805W1--------------------------~----------------------------------

•

BLOCK DIAGRAM

TIMER

TlMER-l
Prescaler 1

7

XTAl

EXTAl

RES
(RAME) NUM

INT.

Timer Data
8 Register 1

Timer Control Register 1

8

Port B
I/O Lines

TIMER-2

c

Accumulator

Prescaler Control

8 Register 2

'£

CPU Control

8

i'~

X

..

'0.

~!

Index Register

Timer Oats

£!

0

A

8

Prescaler 2

ea:

a:

'"l;
0..

Condition Code

S Register 2

5

Timer

Register

CC

8 Status Register 2

CPU

Stack Point
Output Compare

(DC)

8 Register
Input Capture
8 Register

(lC)

4

Timer Control

A.
Ai
A,
A,
A.
A,
A.
A,

8

!

c

.g

Program Counter

8 Register 2
PortA

SP

6

"High"

~

u

'0.

Program Counter

~S
CIlI·!!

u

"Low"

ea:

0..

PCH

AlU

a:"

102'

PCl

~

c

a:"

.~

«

.: ...
e!l

t:

ca'!!

0
0..

ea:

Port C
I/O Lines
C.
C.
C,
C,
C.
C, (lC)
C. (DC)

Port 0

0

'6>

B.
B.
B,
B,
B.
B,
B.
B,

Input Lines

102'

Port

o
(RAME) Vee Standby

D.
D.
0,
0,
D.

(lNT,)
(AN.)
(AN.)
(AN,)
(AN,)

0, (VRH)

ADC lines
. - - - - - - - - AVee
,------AVsS
(VRH)

(AN.)
(AN.)
(AN,)
(AN,)
A/D Control
Status Register

8
A/D Result
Register

8
(NOTE)

220

•

HITACHI

The contents of ( ) items can be changad by software,

---------------------------------------------------------------HD6805W1
• ABSOLUTE MAXIMUM RATINGS
Symbol

Item
Supply Voltage
Input Voltage (EXCEPT TIMER)

V in

Input Voltage (TIMER)

-0.3- +7.0

V

-0.3 -+7.0

V
V
·C
·C

Operating Temperature

Top,

-0.3 - +12.0
0-+70

Storage Temperature

Tstg

-55 - +150

(NOTE'

Unit

Value

Vee

This device has an input protection circuit for high quiescent voltege and field. however. be careful not
to impress a high input voltage than the insulation maximum value to the high input impedance circuit.
To insure normal operation. the following are recommended for Vi" and V out :

VSS ~ (Vln or Vout' ~ Vee

•
•

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = S.25V to.SV. Vss = GND. Ta" 0-+70·C. unless otherwise noted.)
min

typ

max

Unit

RES

4.0

Vee

V

wr.. iNT;
All Others

3.0

-

Vee

V

Item

Symbol

Input "High" Voltage

Test Condition

V IH

2.0

Timer Mode

Input "High" Voltage Timer

2.0

Self·Cheek Mode

Input "Low" Voltage

9.0

RES

-0.3

wr..INT 1
All Others
(except EXTAL)

-0.3

V IL

-0.3

Power Dissipation

-

Po
LVR

Low Voltage Recover
Low Voltage Inhibit

LVI
TIMER

Input Leak Current

Standby Voltage
Standby Current

•

IlL

Nonoperation Mode
Operation Mode

Vsaa
Vsa

Nonoperation Mode

Isaa

Vln =O·4V-V ee

Vsaa=4.0V

V

Vee
11.0

V

0.8

V

V

0.8

V

0.8

V

-

750

mW

-

4.75

V

4.0

-

V

20

IJ.A
IJ.A

-50

-

-1200

-

50
0

4.0

-

Vee

4.75

-

Vee
3

min

typ

max

Unit

0.4

-

4.0

MHz

-

10

IJ.S
MHz

-20

wr..INTl
EXTAL(Crystal Mode)

Vee

-

IJ.A
V
mA

AC CHARACTERISTICS (Vee = S.25V to.SV. Vss .. GND. Ta .. 0 - +70·C. unles. otherwise noted.)
Item

Symbol

Clock Frequency

Test Condition

fel

Cycle Time

teye

Oscillation Frequency (External Resistor Mode)

fEXT

fliITI Pulse Width

1.0

-

3.4

tlWL

t2~

RES Pulse Width

tAWL

'2~

TIMER Pulse Width

tTWL

'2;;

Oscillation Start·up Time (Crystal Mode)

tose

-

Delay Time Reset

tAHL

I nput Capacitance

I
I

XTAL. VRH/Ds
All Others

Cln

Rep =15.0kntl%

C L =22pF±20%
Rs=6On max.
External Cap. = 2.21J.F
V1n=OV

_HITACHI

100

-

-

-

ns
ns

-

ns

100

ms

-

ms

35

pF

10

pF

221

HD6805W1-------------------------------------------------------------•

PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ±O.5V, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)

min

typ

max

IOH = -10J.lA

3.5

-

IOH=-l00J.lA

2.4

-

IOH = -200J.lA

2.4

-

IOH = -1 mA

1.5

-

Port C

IOH = -l00J.lA

2.4

Ports A and C

IOL = 1.6 mA

-

-

0.5

V

-

0.5

V

1.0

V

Vee
0.8

V

Symbol

Item
Port A
Output "High" Voltage

Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage
Input Leak Current

V OH

Port B

IOL = 3.2 mA

VOL

Port B

Test Condition

IOL=10mA

Ports A, B, C
and D
Port A

-

V IH

2.0

-

V IL

-0.3

---------

V in = 0.8V
Vin = 2V

IlL

-500
-300
-~----

•

-20

Vin = 0.4V-V ee

Ports B, C and 0

Unit
V
V
V
V
V

V

J.lA
-_._------ ._- r - -J.lA- - - ---20

J.lA

AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±O.5V, Vss = AVSS = GMD, Ta = 0 - +70 o C, unless
otherwise noted.)
Item

min

typ

AVee

4.75

5.25

5.75

V

AV;n

0

-

V RH

V

-

Vee
5.25

V

Symbol

Analog Power Supply
Voltage
Analog I nput Voltage
Reference Voltage

V RH

Test Condition

4.75V~Vee ~5.25V

5.25V

< Vee ~ 5.75V

4.0
4.0

-

max

Unit

V

Analog Multiplexer Input
Capacitance

-

-

7.5

pF

Resolution Power

-

8

-

Bit

76

76

76

tCyc

4

4

4

Channel

Ta = 25°C

-

-

±1.5

LSB

AV in = 5.0V, AVee =4.75V, Ta = 25°C,
On-channel
AV in =OV
AVin = OV, AVee = 4.75V, Ta = 25°C,
On·channel
AV in =5V

-

10

100

nA

-100

-10

-

nA

Conversion Time

at 4MHz

I nput Channels
Absolute Accuracy
Off-channel Leak Current
Off-channel Leak Current

222

•

HITACHI

------------------------------------------------------------HD6805W1
TTL Equiv. (Port Bt

TTL Equiv. (Ports A. C and D)
Vee

Vee

1, = 3.2 rnA

1.4kn

I,

Test POlOt

Test Point
V,

V,

=

1.6 rnA

2.4kll

>

12kfl

24kl1

I

(NOTE)

1. Load capacitance includes the floating capacitance of the probe and the jig etc.

2. All diode. are 1S2074(j3i or equivalent.

Figure 1 Bus Timing Test Loads

• SIGNAL DESCRIPTION

The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
• Vee and Vss
Voltage is supplied to the MeU using these two pins. Vee is
5.25V ±O .SV. V ss is the ground connection.
•

INTI/INT2

•

XTAL and EXTAL

This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS
for additional information.
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4 MHz maxilnum), a resistor or an external
signal can be connected to these pins to provide a system clock
with various stability/cost tradeoffs. Refer to INTERNAL OSCILLATOR OPTIONS for recommendations about these inputs.
• TIMER

This pin allows an external input to be used to count for the
internal timer circuitry. Refer to TIMER 1 and TIMER 2 for
additional information about the timer circuitry.
•

• Vee Standby
Vee Standby provides power to the standby portion of the
RAM and the STBY PWR and RAME bits of the RAM Control
Register. Voltage requirements depend on whether the MCU
is in a powerup or powerdown state. In the powerup state, the
power supply should provide Vee and must reach VSB before
RES reaches 4.0V. During powerdown, Vee standby must
remain above VSBB (min) to sustain the standby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB.
It is typical to power both Vee and Vee Standby from the
same source during normal operation. A diode must be used
between them to prevent supplying power to Vee during
powerdown operation shown Figure 2.
To sustain the standby RAM during powerdown, the following software or hardware are needed.
(I) Software
When clearing the RAM Enable bit (RAME) which is bit 6
of the RAM Control Register at location $OOIF, the RAM
is disabled.
Vee Standby must remain above VSBB (min).
(2) Hardware
When RAME pin is "Low" before powerdown, the RAM is
disabled. Vee Standby must remain above VSBB (min).

RES

This pin allows resetting of the MCU at times other than the
automatic resetting capability already in the MCU. Refer to
RESETS for additional information.

•

Vee Standby

i

Power line

NUM

This pin is not for user application and should be connected
toVSS'

I/O Lines (Ao - A,. Bo - B,. Co - C.)
There 23 lines are arranged into three ports (A, B and C). All
lines are programmable as either inputs or outputs under software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
•

•

Input Lines (Do - Os!

These are TTL compatible input lines, in location $003.
These also allow analog inputs to be used for an A/D converter.
Refer to INPUT for additional information.

Figure 2 Battery Backup for Vee Standby

•

RAME

This pin is used for the external control of the RAM. When
it is "Low" before powerdown, the RAM is disabled. If Vee
Standby remains above VSBB (min), the standby RAM is
sustained.

_HITACHI

223

HD6805W11--------------------------------------------------------------• AVec

This pin is used for the power supply of the AID converter.
When high accuracy is required, a different power source from
Vee is impressed as
AVec =5.25 ± O.5V
Connect to Vee for all other cases.
•

ANo - AN]

These pins allow analog inputs to be used for an AID converter. These inputs are switched by the internal multiplexer
and selected by bit 0 and I of the AID Control Status Register
(ADCSR: $OOE).

VRH and AVss
The input teJminal reference voltage for the AID converter is
"High" (VRH) or "Low" (AVss). AVss is fIXed at OV.

•

• Input Capture (lCI
This pin is used for input of Timer 2 control, in this case.
Port C, should be configured as input. Refer to TIMER 2
for more details.
• Output Compare (OCI
This pin is used for output of Timer 2 when the Output
000

Compare Register is matched with the Timer Data Register
2. In this case, Port C. should be configured as an output.
Refer to TIMER 2 for more details.

• MEMORY
The MCV memory is configured as shown in Figure 3. During
the interrupt processing, the contents of the CPU registers are
pushed onto the stack in the order shown in Figure 4. Since
the stack pointer decrements during pushes. the low order byte
(PCl) of the program counter is stacked first; then the high
order three bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call will cause
only the program counter (PCH, PCl) contents to be pushed
onto the stack.

Caution: - Self Test ROM Address Area
Self test ROM locations can not be used for a user program.
If the user's program is in this location, it will be removed when
manufacturing mask for production.

1000
II0Porli

T,me.
031

03'

SO"

\"".

RAM
!96 B)

127

S07F
S080

".

PD •• Po

$000

POrt B

'00.

Pone

$002

Pori 0

$003"

POri A aDA

$00••

Port BOOR

$00"

POri C OOR

$008'

SOO,
T,tne, Dltl Aeo 1

$008

SOO9

T,me. CTRL A&g 1

ROM

~neou$Reg

_ _ SOOA

_ _ _ _ _ _ _ _ _--1'008

1383481

f-_ _ _ _ _ _ _ _

~sooc

SOO •
1----------4
AID CTRL StanIS Req
SOOE

AID Result AII9

SOOF"

1-_________-4 SO ••
I--_ _ _ _ _ _ _ _
1--___.._ _ _ _ _-1$0"
~.$O"

_ _ _ _ _ _ _ _ _ _....-j$01J

1--_________-1$014
1--_________ SOIf1

1
- - - - - - - . - - - S016
1--_________-1$011
1--_ _ _ _ _ _ _ _-1 5018
Presc..., eTR L "'119 '1

SOl.

T,mt,S'IIUSAeo'1

$OIA"

T,me, CTRL R.g '1

$018

Tim"

D~II'

RIg '1

SOIC

OUlpul Com!»', Rq

:~I--------~:;;:

-1:;:

""'' =--__
_~ __S~.:d~ _A~:I~ ~~~ ____ SO~,

f-_.;..R",AM=CO","'::.:"",'

Se"'1IIt ROM 112081

::~ f - - - - - - - - - - j :::~

SO,"
RAM 19681

":'k

)

\ -_ _ _ _ _ _...1....
1_---'S07F

'""rrvpIVtcton

·Wrll,R..
·'R.ICIA..
• ··S,.ndby RAM "'lI' Iorst 8 bY111 01 RAM

.... ' -_ _ _ _ _ _ _---'.FFF

Figure 3 MCU Memory Structure

224

SO' 0

1f-_...:'::'O::::"'c:C:::
..:::'":.:.,,:::R':.:.'_ _ _-lSOlE ••

•

HITACHI

--------~-----------------------------------------------------HD6805Wl
6
n-4

1

5
1

4

1[

3

2

0
n+1

Code Register

n-3

Accumulator

n+2

n-2

Index Register

n+3

n-1

1

1

1

1

11

PCH"

peL"

• Stack Pointer (SPI
The stack pointer is a 12-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $07F and is decremented as data is being
pushed onto the stack and incremented while data is being
pulled from the stack. The six most significant bits of the stack
pointer are permanently set to 00000 I. During an MeV reset
or reset stack pointer (RSP) instruction. the stack pointer is
set to location $07F. Subroutines and interrupts may be nested
down to location $041 which allows the programmer to use up
to 31 levels of subroutine calls.

Pull

Condition

n+4
n+5

Push
• For subroutme calls, only PCH and pel are stacked

Figure 4 Interrupt Stacking Order

REGISTERS
The CPU has five registers available to the programmer,
as shown in Figure 5 and explained below.

• Condition Code Register (CCI
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just
executed. These bits can be indiVidually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained below.

•

7

0

I

A

11

Index Register

0
PC

11

I
I
I

6 5

1010101010111

Negative (N I
The negative bit is used to indicate that the result of the last
arithmetic. logical or data manipulation was negative (bit 7 in
a result equal to a logical one).

Program Counter

0
SP

The half carry bit is used during arithmetic operations (ADD
or ADC) to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
This bit is set to mask everything. If an interrupt occurs
while this bit is set. it is latched and will be processed as soon as
the interrupt bit is reset.

Accumulator

0
X

Half Carry (HI

Stack Pointer

Condition Code Register
Carry IBorrow

Zero
Negative
Interrupt Mask

Zero (ZI
Zero is used to indicate that the result of the last arithmetic,
logical or data manipulation was zero.
CarrylBorrow (CI
Carry/borrow is used to indicate that a carry or borrow out
of the arithmetic logic unit (ALU) occurred during the last
arithmetic operation. This bit is also affected during bit test and
branch instructions, shifts and rotates.

Half CarrV

Figure 5 Programming Model

• Accumulator (AI
The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (XI
The index register is an 8-bit register used for the indexed
addressing mode and contains an 8-bit address that may be
added to an offset value to create an effective address. The
index register can also be used for limited calculations or data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PCI
The program counter is a 12-bit register that contains the
address of the next instruction to be executed.

• TIMER 1
The MCU timer circuitry is shown in Figure 6. The 8-bit
counter, Timer Data Register I (TORI), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the TORI reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register I (TCRI)
is set. The CPU responds to this interrupt by saving the present
CPU state in the stack, fetching the timer I interrupt vector
from locations $FF8 and $FF9 and executing the interrupt
routine. The timer I interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the TCRI. The interrupt
bit (I bit) in the Condition Code Register also prevents a timer I
interrupt from being processed.
The clock input to the timer I can be from an external
source applied to the TIMER input pin or it can be the internal
,
clock input.

Clock I"put Source

Table 2 Selection of Presealer Dividing Ratio

Timer Interrupt Ma.k
L - - - - - - - - - - T i m e r Interrupt Reque.t Flag

Bit 2
As shown in Table I, the selection of the clock input source
is ISO and IS 1 in the TCRI (bit 4 and bit 5) and 3 kinds of
input are selectable. At reset, internal clock 1/12 controHed by
the TIMER input (bit 4=1, bitS=O) is selected.
The prescaler dividing ratio is selected by MSO, MSI, and
MS2 in the TCRI (bit 0, bit I, bit 2) as shown in Table 2. The
dividing ratio is selectable from eight ways (+ I, +2, +4, +8,
+16, +32, +64, +128). At reset, +1 mode is selected. The prescaler is initialized by writing in the TDRI.
Timer I interrupt mask bit (TIM) aHows the Timer 1 into

226

Clock Input Source

TCRl
Bit 1

BitO

0
0
0
0

0
0

0

1
1

Q

1
1
1
1

0
0

0

1
1

0

_HITACHI

1
1

1
1

Presealer Dividing Ratio
+1
+2
+4
+8
+16
+32
+64
+ 128

---------------------------------------------------------------HD6805Wl
• TIMER2
The HD6805WI includes an 8-bit programmable timer
(Timer 2) which can not only measure the input waveform but
also generate the output waveform_ The pulse width for both
input and output waveform can be varied from several microseconds to several seconds_
(NOTE) If the MCV Timer 1 and Timer 2 are not used, the
TIMER input pin must be grounded.
Timer 2 hardware consists of the followings.

an 8-bit control register 2
an 8-bit status register 2
an 8-bit timer data register 2
an 8-bit output compare register
an 8-bit input capture register
as-bit prescaler control register 2
a 7-bit prescaler 2
A block diagram of the timer 2 is shown in Figure 7.

Output Compare Register
COCR: $010)

8 bit Register

8

L..._ _ _;"""_....J ReadlWrite

Input Capture Register (lCR: $OlE)

8 bit Register

8

Read

Timer Control Register 2
(TCR2: $018)

ICI

OCI TOI

Internal Interrupts Request Signal

Figure 7 Block Diagram of Timer 2

• Timer Date Register 2 (TOR2: $01C)
The main part of the Timer 2 is the 8-bit Timer Data Register
2 (TDR2) as free-running counter, which is driven by internal
clock tP2 or the TIMER input and increments the value. The
values in the counter is always readable by software.
The Timer Data Register 2 is Read/Write register and is
cleared at reset.
• Output Compare Register (OCR: $010)
The Output Compare Register (OCR) is an 8-bit Read/
Write register used to control an output waveform. The contents
of this register are always compared with those of the TDR2.
When these two contents conform to each other, the flag (OCF)
in the Timer Status Register 2 (TCR 2) is set and the value of
the output level bit (OLVL) in the TCR2 is transferred to Port
C6 (OC).

If Port C6 's Data Direction Register (DDR) is "\" (output),
this value will appear at Port C6 (OC)_ Then the values of OCF
and OLVL can be changed for the next compare. The OCR is
set to $FF at reset.
.
• Input Capture Register (lCR: $01E)
The Input Capture Register (ICR) is an 8-bit Read-only register used to store the value of the TDR2 when Port Cs (IC)
input transition occurs as defined by the input edge bit (IEDG)
of the TCR2.
In order to apply Port C5 (IC) input to the edge detect
circuit, the DDR of Port C5 should be cleared ("0"). *
To ensure an input capture under a\1 condition, Port Cs (IC)
input pulse width should be 2 Enable-cycles at least.
*The edge detect circuit always senses Port C5 (IC) even if the
DDR is set with Port Cs output.

_HITACHI

227

HD6805W1--------------------------------------------------------------• Timer Control Register 2 (TCR2: SOlB)
The Timer Control Register 2 (TCR2) consi.ts of an 5-bit
'
register of which all bits can be read and written.
Timer Control Register 2 (TCR2: $OlB)
76543210
I Z V I 2 1 IC,M I OCIM I TOIM IIEDG I OLVL I

Bit 0 OLVL Output Level
This bit will appear at Port C. when the value in the TDR2
equals the value in the OCR, if the DDR of Port C. is set. It is
cleared by reset.
Bit 1 IEDG Input Edge
This bit determines which level transition of Port Cs (IC)
input will trigger a data store to ICR from the TDR2. When this
function is used, it is necessary to clear DDR of Port Cs . When
!EDG = 0, the negative edge triggers ("High" to "Low" transition). When !EDG = I, the positive edge triggers ("Low" to
"High" transition). It is cleared by reset.
Bit 2 TOIM Timer Overflow Interrupt Mask
When this bit is cleared. internal interrupt (TO!) is enabled
by TOF interrupt but when set, interrupt is inhibited.

Bit 6 OCF Output Compare Flag
This read-only bit is set when a match is found between the
OCR and the TDR2. It is cleared by reading the TSR2 and then
writing to the OCR.
Bit 7 ICF Input Capture Flag
This read-only bit is set to indicate a proper level transition
and cleared by reading the TSR2 and then reading the TCR2.
User can write into port C. by software.
Accordingly, after port C. has output by hardware and is
immediately write into by software, simultaneous cyclic pulse
control with a short width is easy.
• Prescaler Control Register 2 (PCR2: $019)
The selection of clock input source and prescaler dividing
ratio are performed by the Prescaler Control Register 2 (PCR2).

Prescaler Control Register 2 (PCR2: $019)
7

6

VVI

5

4

IS1

ISO

3

IZI

2

1

MS2 I MSI

0

MSO

Prescaler Dividing Ratio

Bit 3 OCIM Output Compare Interrupt Mask
When this bit is cleared, internal interrupt (OCI) by OCF
interrupt occurs. When set, interrupt is inhibited.
Bit 4 ICIM Input Capture Interrupt Mask
When this bit is cleared, internal interrupt (lCI) by ICF
interrupt occurs. When set, interrupt is inhibited.
• Timer Status Register 2 (TSR2: $OlA)
The Timer Status Register 2 (TSR2) is an 8-bit read-only
register which indicates that;
(I) A proper level transition has been detected on the input
pin with a subsequent transfer of the TDR2 value to the
ICR (ICF).
(2) A match has been found between the TDR2 and the OCR
(OCF).
(3) The TDR2 is zero (TOF).
Each of the event can generate 3 kinds of internal interrupt
request and is controlled by an individual inhibit bits in the
TCR2. If the I bit in the Condition Code Register is cleared,
priority vectors are generated in response to clearing each
interrupt mask bit. Each bit is described below.

Timer Status Register 2 (TSR2: SOlA)
765432
ICF

L - - - - - - - - C l o c k Input Source

The selection of clock input source is performed in three
different ways by bit 4 and bit 5 of the PCR2, as shown in
Table 3. At reset, internal clock 1P2 controlled by the TIMER
input (bit 4 = I, bit 5 = 0) is selected.
The prescaler dividing ratio is selected by three bits in the
PCR2 (bits 0, 1, 2), as shown in Table 4. The dividing ratio
can be selected in 8 ways (+1, +2, +4, +8, +16, +32, +64, +128).
At reset, + 1 (bit 0 = bit 1 = bit 2 = 0) is selected.
When writing into the PCR2, or when writing into the TDR2,
prescaler is initialized to $FF.
Table 3 Selection of Clock Input Source
PCR2
Bit 5

0
0

Bit4
0
1

1

0

1

1

Internal Clock 1P2 *
1P2 Controlled by TIMER Input
Event Input from TIMER

• The T!MER input pin must be tied to Vee. for uncontrolled cp,

0

clock Input.

I OCF I TOF L Z l Z V I / 1 Z l

Bit 5 TOF Timer Overflow Flag
This read-only bit is set when the TDR2 contains $00.
It is cleared by reading the TSR2 followed by reading of the
TDR2.

228

Clock Input Source

_HITACHI

.

---------------------------------------------------------------HD6805W1
Table 4 Selection of Presealer Dividing Ratio

Bit 2
0
0
0
0
1
1
1
1

PCR2
Bit 1
0
0
1
1
0
0
1
1

• SELF CHECK
The MCU self check easily determines whether the LSI
functions normally or not. When the MCU is connected as
shown in Fig. 8, the outputs of port C3 (LED) flicker in normal
operation.

Presealer Dividing Ratio

Bit 0
0
1
0
1
0
1
0
1

+1
+2
+4
+8
+16
+32
+64
+ 128

•

RESETS
The MCU can be reset three ways; by initial power-up, by
the external reset input (RES) and by an optional internal low
voltage detect circuit, see Figure 9. All the I/O ports are initialized to inpu t mode (DDRs are cleared) during reset.
During power-up, a minimum 100 milliseconds is needed
before allowing the RES input to go "High". This time allows
the internal crystal oscillator to stabilize. Connecting a capacitor
to the RES input, as shown in Figure 10, typically provides
sufficient delay.

CAUTION
The flag of the TSR2 will be sometimes cleared when manipulating or testing the TSR2 by Read/Modify/Write instruction
shown in Table S. Don't use these instructions for read/write/
test operation of the TSR2 flags.

~R

ASR
ASL
TST

# Bytes
2
2
2
2
2
2
2
2
2
2
2
2

OpCode
3C
3A
3F
33
30

39
36
38
34
37
38
3D

INT

2

RES

A, 38

XTAL

A.~
A, 36

A. 39

$2.2I'F

Table 5 Read/Modify/Write Instruction
Mnemonic
INC
DEC
CLR
COM
NEG
ROL
ROR
LSL

A, 40

2...

6

~

#Cyeles
6
6
6
6
6
6
6
6
6
6
6
6

A, 35
A, 34

EXTAL

Ao

22PFr
+9V

8

~

V CC

330 l!

r.::J

TIMER

B, 30
B. 29

330 l!

r.:-: ~"

b

Vee

Vss

= P,n 1

330n

B, 27
B, 26

C,

'C ~12 C,
v
c. Cs
= Pm 4 '-a

330l!

B,~

C"
10 C,

~

.A

B, 31

NUM

9

330 l!

..E--

HD6805Wl
(Crystal option)
B,E--

B" 25

c,

Vec Standby 21

Vcc

15
13 14
1

330n
330n

Figure 8 Self Cheek Connections
5V ----------LV~

LVI

Vee

"Dip" in
Power

QV
RES

. /I'"" V'H RES

Pm
--;0.

tAHL

t

LVR

/

/
---... tAHL :--

I--

Internal

Part of
HD6805Wl

MCU

Reset

Figure 9 Power Up and Reset Timing

•

Figure 10 Power Up Reset Delay Circuit

HITACHI

229

HD6805W1----------------------------------------------------------__
• INTERNAL OSCILLATOR OPTIONS

crystal oscillator or the RC oscillator circuit. Four different
connection methods are shown in Figure II. Crystal specifications are given in Figure 12. A resistor selection graph is
shown in Figure 13. EXTAL may be driven with a duty cycle
of 50% with XTAL connected to ground.

The internal oscillator circuit is designed to require a minimum of external components. A crystal (AT cut. 4 MHz max).
a resistor. a jumper wire or an external signal may be used to
generate a system clock with various stability/cost tradeoffs.
A manufacturing mask option is required to select either the

6 XTAL

6 XTAL

4~a~Z

c:J

5 EXTAL

H0680SWI
MCU

5 EXTAL

HD680SWI
MCU

22pF t 20%7tr

Crystal

Approximately 2S% Accuracy
External Jumper

Vee
6 XTAL

6 XTAL
External

Clock
Input

5 EXTAL

R

HD6605Wl
MCU

HD6805Wl
5 EXTAL
MCU
No

Connection

External Clock

Approximately 15% Accuracy
Externa' Resistor

CRYSTAL OPTIONS

RESISTOR OPTIONS

Figure 11

Internal Oscillator Options

S
Co

XTAL~~EXTAL
6

~~

5

>
c

3

""'-

."
:>

AT - Cut Parallel Resonance Crystal
C. = 7 pF max.
1= 4 MHz IC o =22pF t 20%1
Rs:l 60n max.

"l!!

u.

2

i'-.f'...

..........

'"""""- I'---

Figure 12 Crystal Parameters

o

5

10

15

20
25
30
Resistance IkOI

35

40

Figure 13 Typical Resistor Selection Graph

230

J.

Vee· 5.2SV_
Ta·25°C

\

~

!

I

!\

4

_HITACHI

45

50

---------------------------------------------------------------HD6805Wl
•

Table 6 Interrupt Priorities

INTERRUPTS

The MCU can be interrupted in seven different ways: through
external interrupt input pin (INTi and 1NT2), internal timer
interrupt request (Timer 1, ICI, OCI and OFI) and a software
interrupt instruction (SWI). 002 and Timer 1 are generated by
the same vector address. When interrupt occurs, processing
of the program is suspended, the present CPU state is pushed
onto the stack in the order shown in Figure 4. The interrupt
mask bit (I) of the Condition Code Register is set and the external routine priority address is achieved from the special external vector address. After that, the external interrupt
routine is executed. The interrupt service routines normally
end with a return from interrupt (RT!) instruction which allows
the CPU to resume processing of the program prior to the interrupt. The priority interrupts are shown in Table 6 with the
vector address that contains the starting address of the appropriate interrupt routine. The interrupt sequence is shown as
a flowchart in Figure 14.

Interrupt
RES
SWI
INTI
TlMERI/INT2
ICI
OCI
OFI

Priority

Vector Address

1

$FFE, $FFF

2
3
4

$FFC.$FFD
$FFA,$FFB

5

$FF6. $FF7
$FF4. $FF5
$FF2, $FF3

6
7

$FF8. $FF9

Clear

y TIMER 1

y

ICI

y

OCI

1 -+1

7F -+SP
O .... DDR·'
CLR INT Logic
7F .... MR
FF -+TDRI
00 .... TDR2
7 F -+ Prescaler 1
7 F .... Prosealer 2
50 .... TCRI
lC-+TCR2
00 -+TSR2
10-+PCR2

Fetch Instruction

N

y

Stack PC. X. CC. A
Execute Instruction

Load PC From
SWI: $FFC. $FFD
INT, : $FFA. $FFB
TIMER,: $FFB. $FF9
INT,: $FF8. $FF9
ICI: $FF6. $FF7
OCI: $FF4. $FF5
OFI: $FF2. $FF3

Figure 14 Interrupt Flowchart

~HITACHI

231

HD6805W1------------------------------------------------------~------

• Miscellaneous Register (MR: SOOAI
The vector address generated by the external interrupt
(1NT2) is the same as that of TIMER I as shown in Table 6.
The Miscellaneous Register (MR) controls tije INTi interrupt.
Bit 7 (IRF) of the MR is used as an 1N'f2 interrupt request
flag. IN'F2 interrupt occurs at the 1NT2 negative edge, and IRF
is set. 1liIT2 interrupt or not can be proved by checking IRF
by software in the interrupt routine of the vector address
($FF8, $FF9). IRF should be reset by software (BCLR' in·
struction ).
Bit 6 (1M) of the MR is an INT2 interrupt mask bit. When
m is set, 1NT2 interrupt is disabled. iNT2 interrupt is also
disabled by bit (I) of the Condition Code Register (CC) like
other interrupts.

Miscellaneous IRegister (MR: SOOAI
765432

IRF

1M

0

IZIZIZIZIZIZI

' - - - - - - - INT, Interrupt Mask

L - - - - - - - - - I N T , Interrupt Request Flag

IRF is available for both read and write. However, IRF is
not writable by software. Therefore, INTi interrupt cannot be
requested by software. At reset, IRF is cleared and 1M is set.
•

INPUT/OUTPUT

There are 23 input/output pins. All pins (port A, B, and C)
are programmable as either inputs or outputs under software

control of the corresponding Data Direction Register (DDR).
The port I/O programming is accomplished by writing the
corresponding bit in the port DDR to a logic "I" for outpt or
a logic "0" for input. On reset, all the DDRs are initialized
to a logic "0" state to put the ports in the input mode. The port
output registers are not initialized on reset but may be written
to before setting the DDR bits to avoid undefined levels.
When programmed as outputs, the latched output data is
readable as input data, regardless of the logic levels at the
output pin due to output loading; see Figure 15. When port B
is programmed for outputs, it is capable of sinking 10 mA and
sourcing 1 mA on each pin.
All input/output lines are TTL compatible as both inputs
and outputs. Ports Band C are CMOS compatible as inputs.
Port A is CMOS compatible as outputs. Figure 16 provides some
examples of port connections.
Port Cs and C6 are also used for Timer 2.
When Port Cs is used as Timer 2 Input Capture (IC), Port
Cs's DDR should be cleared (Port Cs as input) and bit 4 (ICIM)
in the Timer Control Register 2 (TCR2) should be cleared too.
The Input Capture Register (ICR) stores the TDR2 when a
Port Cs input transition occurs as defined by bit 1 (IDEG) of
the TCR2.
When Port C6 is used as Timer 2 Output Compare (OC),
Port C6 's DDR should be set (Port C6 as output). When the
Output Compare Register (OCR) matches the TDR2, bit 0
(OLVL) in the TCR2 is set and OLVL will appear at Port C6.
Port C6 is writable by software. But the writing by software is
unavailable when a match between the TDR2 and the OCR is
found at the same time.
•

INPUT

Port D is usable as either TTL compatible inputs or a 4·
channel input for an A/D converter. Figure 17 shows port D
logic configuration .
The Port D register at location S003 stores TTL compatible
inputs. When using as analog inputs for an A/D converter, refer
to A/D CONVERTER.

Data
Direction

Ragister

Output
Data Bit

Output
State

Input to

MCU

Bit

Figure 15 Typical Port I/O Circuitry

232

,

,

0

,

0

0

0

x

3·State

Pin

_HITACHI

---------------------------------------------------------------HD6805W1
B.

··
·

A.

Port B

Port A

B,

A,

Port B Programmed as output(s), driving Darlington base directly.

Port A Programmed as output(s). driving CMOS and TTL load directly.

(b)

(a)

+V

+V

R

R

C.
Port C

Port B

··•
··•

CMOS Inverter

C,

Port C Programmed as output{s). driving CMOS loads, using external
pull·up resistors.
(d)

Port B Programmed as output(s). driving LEO(.) directly.
(c)

Figure 16 Typical Port Connections
• AID CONVERTER
The HD6S05Wl has an internal S-bit AID converter. The
AID converter, shown in Figure IS, includes 4 analog inputs
(ANo to AN3), the Result Register (ADRR) and the Control
Status Register (ADCSR).

CAUTION
The MCU has circuitry to protect the inputs against damage
due to high static voltages or electric field; however, the design
of the input circuitry for the AID converter, ANo - AN., V RH
and AVec, does not offer the same level of protection. Precautions should be taken to avoid applications of any voltage
higher than maximum-rated voltage or handled in any environment producing high-static voltages.

$003 Read

Internal Bus

1-......_____

O/A

Port 0

Do taOs

4

:l

AVS S - - - - - '

A"llog Input

~

ANo

0<:
-0

AN,

0----_

sv

AID COfnrol SUlt"'l RIgISler
(ADeSR $OOEI

AID Reau't Aeglsllff ("DAR SOOF I

Figure 1B AID Converter Block Diagram

•

HITACHI

233

HD6805VV11--------------------------------------------------------------• Analog Input (ANo to AN3)
Analog inputs ANo to AN3 accept analog voltages of OV
to 5V. The resolution is 8-bit (256 divisions) with a conversion time of 76 IlS at I MHz. Analog conversion starts selecting
analog inputs by bit 0 and bit I of the ADCSR analog input.
Since the CPU is not required during conversion, other user
programs can be executed.

• RAM Control Register (RCR: $OlF)
This register at location SOl F gives the status information
about the RAM. When RAM Enable bit (RAME) is "0", the
RAM is disabled. When Vee Standby is greater than VSBB,
Standby Power bit (STBY PWR) is set and the standby RAM is
sustained during powerdown.

Table 7 Analog Input Selection

RAM Control Register

ADCSR
Bit 1
0
0
1
1

Bit 0
0
1
0
1

Analog Input Signal
SOlF

ANo
ANI
AN%
AN3

• AID Control Status Register (ADCSR: $OOE)
The Control Status Register (ADCSR) is used to select an
analog input pin and confirm AID conversion termination. An
analog input pin is selected by bit 0 and bit I as shown in Table

7.
A/D conversion begins when the data is written into bit 0
and bit I of the ADCSR. When A/D conversion ends, bit 7
(CEND) is set. Bit 7 is reset after the ADRR is read. Even
if bit 7 is set, AID conversion execution still continues. To end
the A/D conversion, the A/D Result Register (ADRR) stores
the most current value. During A/D conversion execution, new
data is written into the ADCSR selecting the input channel and
the A/D conversion execu tion at that time is suspended. CEND
is reset and new AID conversion begins.
• AID Result Register (ADRR: $OOF)
When the AID conversion ends, the result is set in the A/D
Result Register (SOOF). When CEND of the ADCSR is set,
converted result is obtained by reading the ADRR. Furthermore, CEND is cleared.
• STANDBY RAM
The portion from S020 to S027 of the RAM can be used
for the standby RAM.
When using the standby RAM, Vee Standby should remain
above VSBB (min) during powerdown. Consequently, power is
provided only to the standby RAM and STBY PWR bit of the
RAM Control Register. 8 byte RAM is sustained with small
power dissipation. The RAM including the standby RAM is
controlled by the RAM Control Register (RCR) or RAME pin.

7

6

STBY
PWR

RAME

5

4

3

2

1

0

IZIM/INI

Bit 6 RAM Enable
RAME bit is set or cleared by either software or hardware.
When the MCU is reset, RAME bit is set and the RAM is
enabled. If RAME bit is cleared, the user can neither read nor
write the RAM.
When the RAM is disabled (logic "0"), the RAM address is
invalid.
Bit 7 Standby bit
STBY PWR bit is cleared whenever Vee standby decreases
below VSBB (min). This bit is a read/write status bit that the
user can read. When this bit is set, it indicates that the standby
power is applied and data in the standby RAM is valid.
• RAME Signal
RAME bit in the RCR can be cleared when RAME pin goes
"Low" by hardware (RAM is disabled). To make standby mode
by hardware, set RAME pin "Low" during Vee Standby
remains above VS BB (min) and powerdown sequence should be
as shown in Fig. 20.
When RAME pin gets "Low" in the powerup state, RAME
bit of the RCR is cleared and the RAM is disabled. During
powerdown, RAME bit is sustained by Vee Standby. When
RAME pin gets "High" in the powerup state, RAME bit of the
RCR is set and the RAM is enabled.
RAME pin can be used to control the RAM externally without software.
Vee
\

RAME pin

vee OFF /

~

AAMCTRL

Vee'l.ndby

~~so.o=r~""""""'"
..I'

R.o.IS01FI

RAM Enabl.+

S1endby RAM

Vee

Figure 20 RAM Control Signal (RAME)
"AM

1111'

I - - - - - l S07.
Figure 19 Standby RAM

234

• BIT MANIPULATION
The MCU has the ability to set or clear any single RAM or
input/output port (except the data direction registers) with a
single instruction (BSET and BCLR). Any bit in the page zero
read only memory can be tested by using the BRSET and

_HITAOHI

--------------------------------------------------------------HD6805W1
BRCLR instructions, and the program branches as a result of
its state. This capability to work with any bit in RAM, ROM or
I/O allows the user to have individual flags in RAM or to handle
single I/O bits as control lines. The example in Figure 21 shows
the usefulness of the bit manipulation and test instructions.
Assume that bit 0 of port A is connected to a zero crossing
detector circuit and that bit I of port A is connected to the
trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven bytes of ROM provides tum-on of the TRIAC within 14 microseconds of the zero
crossing. The timer is also incorporated to provide tum-on at
some later time which permits pulse-width modulation of the
controlled power.
•

SELF 1

Figure 21

···
·
···

to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA = (PC) +2 + ReI. ReI is the contents of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken, Rei = 0, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 bytes of the present instruction.
These instructions are two bytes long.
•

Indexed (No Offset!
Refer to Figure 26. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.

•

Indexed (B-bit Offset!
Refer to Figure 27. The EA is calculated by adding the contents of the byte following the opcode to the contents of the
index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.

BRClRO, PORTA, SELF 1
BSET 1, PORTA
BClR 1, PORTA

•

Indexed (16-bit Offset!
Refer to Figure 28. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are
three bytes long.

·

Bit Manipulation Example

• ADDRESSING MODES
The MCU has ten addressing modes available for use by the
programmer. These modes are explained and illustrated briefly
in the following paragraphs.
• Immediate
Refer to Figure 22. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure 23. In direct addressing, the address of the
operand is contained in the secondbyte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of
this efficient memory addressing mode.
• Extended
Refer to Figure 24. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode, Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 25. The relative addressing mode applies only

• Bit Set/Clear
Refer to Figure 29. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 30. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($00 through $FF) and branch to any location relative to the
PC. The byte to be tested is addressed by the byte following
the opcode. The individual bit within that byte to be tested
is addressed by the lower three bits of the opcode. The third
byte is the relative address to be added to the program counter
if the branch condition is met. These instructions are three
bytes long. The value of the bit to be tested is written to the
carry bit in the condition code register.
• Implied
Refer to Figure 31. The implied mode of addressing has
no EA. All of the information necessary to execute an instruction is contained in the opcode. Direct operations on the
accumulator and the index register are included in this mode
of addressing. In addition, control instructions such as SWI
and RTI belong to this group. All implied addressing instructions are one byte long.

~HITACHI

235

HD6805Wl---------------------------------------------------------------

~

I

Memory

i
I
I
•

I

8
••

PROG LOA #$F8 OSSE

AS

OSSF

F8

/

A
Index

I

F8

I

20

J

III

Stack Point

•I

I

I

Prog Count

I

05CO
CC

I

~
••!

Figure 22 Immediate Addressing Example

,

lEA

,

i

•

I
I
I

•••
•
CAT

FCB

32

I

LOA

CAT

Adder

20

OO4B

J

0048

/

I
I

•
PROG

I

Me!ory

'"

Jo

A

.J

Index Reg

I

I

0520

B6

052E

4B

Stack Point

I

I
Prog Count

I

052F
CC

~
•
•I

,•

I

:I

,

I

Figure 23 Direct Addressing Example

236

eHITACHI

I
I
I

-----------------------------------------------------------------HD6805W1

Memorv

i
I
I
I

~
I

PROG

LOA

CAT

FCB

64

A

I

~'~ J

040A

06

040B

ES

I
I

CAT

0000

40
Index Reg

Stack Point

I
I

Prog Count

040C

40

06ES

CC

Figure 24 Extended Addressing Example

lEA
Memory
I

I

I
I
I

I

I

S
I

PROG

BEQ

PROG2

04A7

27

04AB

1B

I

I

~

/
I

I

I

04C1

Adder

i

~

OR

t

'"

,

I
I

Index Reg

Stack Point

I
I
I

I

I

0000

Prog Count

y

I

i

I

04C1
CC

r

z

I

1

~
I

A

I

,

Figure 25 Relative Addressing Example

_HITACHI

237

HD6805W1------------------------------------------------------------

,

lEA

Melorv

•

I

•I

OOBS

•

/

Adder

I

I

•I
TASL

,,

I

I

ooto

4C

FCC I Lli OOBB

49

I

PROG

LOA

X

I

'"

A

J

4C
Index Reg

I

BS

I

Stack POint

~"~

Prog Count

05F5
CC

§
I

Figure 26 Indexed (No Offset) Addressing Example

lEA

,

Melorv

I

I
I
I

•
TABL

FCB

#BF

0089

SF

FCB

#86

OOHA

86

FCB

#OB

OOSB

DB

FCB

"CF

008C

CF

LOA

008C

L

Adder

I
I

TABL. X 0758

E6

075C

89

I

t

,

I
I

PROG

L

'"
I

CF

J

Index Reg

~

03

J

I

I

Prog Count

I

§
Figure 27 Indexed (B·Bit Offset) Addressing Example

238

L

Stack Point

I
I

_.A

_HITACHI

0750
CC

I

HD6805Wl
lEA
i

,

:

I

I

§
PAOG

LOA

TABL. X 0692

I

0780

1

/

Adder

~

08

06
07

0694

7E

02

I

I

.BF

077E

BF

FCB

#86

077F

86

FCB

"DB

0780

FCB

"CF

0781

I-__

I
Prog Count

I

0695,

I
I

CC

I

FCB

J

Stack POint

1------'

I

TABL

J

Index Reg

~I

0693

A

I

I

':O~B~_-f_ _ _- - - - - - - - - - - - - '

CF

Figure 28 Indexed (16·8it Offset) Addressing Example

Memory

POATB

EQU

PAOG BCLR 6. PORT B

0001

BF

058F

10

0590

01

I

I

~

I
I

I

Figure 29 Bit Set/Clear Addressing Example

•

HITACHI

239

HD6805W1-----------------------------------------------------------lEA
Memtry
i

I

•i
eau

0002

2

i

FO

t

/

Adder

Bit
2

i
i

PROG BRCLR 2. PORT C. PROG 2

05

0575

02

0576

I
W

10

H
i

-I

oor

OR

~ ""

A

I
I

Index Reg

Stack Point

I

I

0594

J

Prog Count

c

I

I

Adder

I

/

I

Figure 30 Bit Test and Branch Addressing Example

EA
Memory

lI
I

~

e5
Index Reg

i

I

PROG

TAX

E5

I
i

_A~

Prog Count

05BB
CC
i

i

I

I

~
Figure 31

240

Implied Addressing Example

•

HITACHI

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CC

!

i

•

""

Joo

I
I

0574

I

0002

I

i

PORT C

I

J

------------------------------------------------------------HD6805W1
• INSTRUCTION SET
The MCU has a set of S9 basic instructions. These instructions can be divided into five different types; register/memory,
read/modify/write, branch, bit manipulation and control. Each
instruction is breifly explained below. All of the instructions
within a given type are presented in individual tables.
• Regiltllr/Memory Instructions
Most of these instructions use two operands. One operand
is either the accumulator or the index register. The other
operand is obtained from memory by using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to
Table 8.
• Read/Modlfy/Write Instructions
These instructions read a memory location or a register,
modify or test its contents and write the modified value back
to the memory or register. The TST instruction for test of
negative or zero is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
9.

•

• Branch Instructions
The branch instructional cause a branch from a program
when a certain'condition is met. Refer to Table 10.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 2S6 bytes
of the memory. One group either sets or clears. The other
group performs the bit test and branch operations. Refer to
Table II.
• Control Instructions
The control instructions control the MCU operations during
program execution. Refer to Table 12.
• Alphabetical Listing
The complete instruction set is given in alphabetical order
in Table 13.
• Opcode Map
Table 14 is an opcode map for the instructions used on the
MCU.

HITACHI

241

::J:

.,.....,
...,

o

0>

CO

o

0'1

Table 8

~

Register/Memory Instructions

~

Addressing Modes
Function

Mnemonic

Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code
Load A from Memory

LDA

A6

2

2

B6

2

Indexed
(No Offset)

Extended

Direct

Immediate

4

C6

Op
#
#
Bytes Cycles Code
3

5

F6

Indexed
(8-Bit Offset)

Op
#
#
Bytes Cycles Code

Indexed
(16-Bit Offset)

Op
#
#
Bytes Cycles Code

#

#

Bytes Cycles

4

E6

2

5

D6

3

6

1

4

EE

2

5

DE

3

6

1

Load X from Memory

LOX

AE

2

2

BE

2

4

CE

3

5

FE

Store A in Memory

STA

-

-

B7

2

5

C7

3

6

F7

1

5

E7

2

6

D7

3

7

Store X in Memory

STX

-

-

-

BF

2

5

CF

3

6

FF

1

5

EF

2

6

DF

3

7

Add Memory to A

ADD

AB

2

2

BB

2

4

CB

3

5

FB

1

4

EB

2

5

DB

3

6

Add Memory and
Carry toA

ADC

A9

2

2

B9

2

4

C9

3

5

F9

1

4

E9

2

5

D9

3

6

Subtract Memory

SUB

AO

2

2

BO

2

4

CO

3

5

FO

1

4

EO

2

5

DO

3

6

~

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

4

C2

3

5

F2

1

4

E2

2

5

D2

3

6

-

AND Memory to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

1

4

E4

2

5

D4

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

DA

3

6

Exclusive OR Memory
with A

EOR

AS

2

2

B8

2

4

C8

3

5

F8

1

4

E8

2

5

D8

3

6

Arithmetic Compare A
with Memory

CMP

A1

2

2

B1

2

4

C1

3

5

Fl

1

4

E1

2

5

D1

3

6

Arithmetic Compare X
with Memory

CPX

A3

2

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

D3

3

6

Bit Test Memory with A
(Logical Compare)

BIT

A5

2

2

B5

2

4

C5

3

5

F5

1

4

E5

2

5

D5

3

6

Jump Unconditional

JMP

-

-

-

BC

2

3

CC

3

4

FC

1

3

EC

2

4

DC

3

5

Jump to Subroutine

JSR

-

-

-

BD

2

7

CD

3

8

FD

1

7

ED

2

8

DD

3

9

•
:t

()

:t

-

Symbols;
Op; Operation Abbreviation
# : Instruction Statement

I

Table 9

Read/Modify/Write Instructions

Addressing Modes
Function

Implied (A)

Mnemonic

Implied (X)

Op
#
#
Bytes Cycles Code

Op
Code

Op
#
#
Bytes Cycles Code

Indexed
(8-Bit Offset)

Indexed
(No Offset)

Direct

Op
#
#
Bytes Cycles Code

Op
#
#
Bytes Cycles Code

#

#

Bytes Cycles

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

7

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

~

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

~
o

Negate
(2's Complement)

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

7

1

4

36

2

6

76

1

6

66

2

7

38

2

6

78

1

6

68

2

7

34

2

6

74

1

6

64

2

7

6

77

1

6

67

2

7

68

2

7

6D

2

7

J:

J:

Rotate Right Thru Carry

ROR

46

1

4

58

1

4

54

1

4

Logical Shift Left

LSL

48

1

4

Logical Shift Right

LSR

44

1

4

Arithmetic Shift Right

ASR

47

Arithmetic Shift Left

ASL

48

Test for Negative or
Zero

TST

4D

1

I

4

56

57

1

4

37

2

1

4

58

1

4

38

2

6

78

1

6

1

4

50

1

4

3D

2

6

7D

1

6

Symbols:
Op: Operation Abbreviation
# : I nstruction Statement

::r:

o

O'l

00

o
~

w

t11

~
~

HD6805W1--------------------------------~----------------------------

Table 10 Branch Instructions
Relative Addressing Mode
Function

Mnemonic

Branch Always

Op
Code
20
21
22
23

BRA
BRN
BHI
BlS

Branch Never
Branch IF Higher
Branch I F lower or Same
Branch IF Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set

BCC
(BHS)

#

#

Bytes
2
2

Cycles
4
4

2
2

4
4
4

24
24
25

2
2
2

25

2
2

4
4

4
4

(Branch IFlower)

BCS
(BlO)

Branch IF Not Equal
Branch I F Equal

BNE
BEQ

26
27

2

4

Branch IF Half Carry Clear
Branch IF Half Carry Set

BHCC
BHCS

28
29

2
2

4
4

2A
2B

2

4

2
2

4

2
2

4
4

2
2

4

Branch I F Plus

BPl

Branch IF Minus

BMI

Branch IF Interrupt Mask B it is Clear

BMC

Branch IF Interrupt Mask Bit is Set

BMS
Bil

2C
20
2E

BIH
BSR

AD

Branch I F Interrupt Line is low
Branch IF Interrupt line is High
Branch to Subroutine
Symbols: Op: Operation Abbreviation

2F

4

8

#: Instruction Statement

Table 11 Bit Manipulation Instructions

Function

Bit Set/Clear

Mnemonic
Op
Code

Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear bit n

-

BRSET n (n=O ..... 7)
BRClR n (n=O ..... 7)
BSET n (n=O ..... 7)
BClR n (n=O ..... 7)

Symbols: Op: Operation Abbreviation

#
Bytes

-

-

10+2·n

2

11+2·n

2

Addressing Modes
Bit Test and Branch
Op
#
#
#
Cycles
Cycles
Bytes
Code
2·n
3
10
01+2·n
10
3
7
7

-

-

-

-

#: Instruction Statement

Table 12 Control Instructions
Implied
Function

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit
Clear Carry Bit

SEC

#

#

Bytes

Cycles

97
9F

1
1

2
2

99
98

1
1

2

9B

1

2

Set Interrupt Mask 8it

ClC
SEI

Clear Interrupt Mask Bit
Software Interrupt

Cli
SWI

9A
83

1
1

2
11

Return from Subroutine
Return from Interrupt

RTS
RTI

81

80

1
1

6
9

Reset Stack Pointer
No-Operation

9C
90

1

NOP

1

2
2

RSP

Symbols: Op: Operation Abbreviation #: Instruction Statement

244

Op
Code

•

HITACHI

2

------------------------------------------------------------HD6805W1
Table 13 Instruction Set
Mnemonic
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA
BRN
BRClR
BRSET
BSET
BSR
ClC
Cli
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
lOA
lOX

Implied Imme·
diate
x
x
x
x
x

Ex·
Direct tended
x
l(

x
x

Re·
lative

x
x
l(

l(

Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
x

Condition Code
Bit
Setl
Clear

Bit
Test &
Branch

x
x
)(

x
x
)(

x
x
x
x

x

x

x

x

x
)(

x
)(
)(

)(

x
)(
)(

x
x
)(

x
)(

x
x
)(

x
)(
)(

x

Interrupt Mask

Negative (Sign Bit)
Zero

x

x
x

x
x
x
x

)(

x

x

)(

)(

x
x

)(

)(

)(

x
x
x
x
x
x

)(

x
x

x
x

)(

Condition Code Symbols:
H
Half Carry (From Bit 3)
I

)(

)(

x

N
Z

x
x
x
x

x
x
x

l(

)(
)(

)(

x

x
x
x
x
x
)(

C

Carry Borrow

/\
•

Test and Set if True, Cleared Otherwise
Not Afleeted

•

HITACHI

I

N

Z

C

/\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

/\

/\

/\

/\

/\

/\

/\
/\
/\

/\

/\
/\

•

•
•
•
•
•
•
•
•
•
•
/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
/\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

0
/\

1

•
0
•
•

/\

/\

/\

x

x

H

•
•
•
•
•
-.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

•
•
•
•
•
•
•
0

•
•

/\
/\

•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\
/\

•

• /\ /\ 1
• /\ /\ /\
• /\ /\ •
• /\ /\ •
• /\ /\ •
• • • •
• • • •
• /\ /\ •
• /\ /\ •

(to be continued)
245

HD6805Wl----------------------------------------------------________
Table 13 Instruction Set
Addressing Modes
Mnemonic

Implied

Immediate

Direct

x
x
x
x

LSL
LSR
NEQ
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STX
SUB
SWI
TAX
TST
TXA

Extended

Condition Code
Indexed
Indexed Indexed
(No
Offset) (8 Bits) (16 Bits)
x
x
x
x
x
x

Relative

x
x
x

x

x
x
x

x

x
x
x

x
x
x

x

x

x

x

x

X

x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x

x

x
x
x
x
x

x
x

x
x
x
x

-

x

Condition Code Symbols:
H Half Carry (From Bit 3)
I
Interrupt Mask
N Negative (Sign Bitl
Z
Zero

C

Bit

Bit
Test & H
Branch

Setl

Clear

I

N

C

Z

• • 1\ 1\ 1\
• • 0 1\ 1\
• • 1\ 1\ 1\
• • • • •
• • 1\ 1\ •
• • 1\ 1\ 1\
• • 1\ 1\ 1\
• • • • •
?
?
?
?
?
• • • • •
• • 1\ 1\ 1\
• • • • 1
• 1 • • •
• • 1\ 1\ •
• • 1\ 1\ •
• • 1\ 1\ 1\
• 1 • • •
• • • • •
• • 1\ 1\ •
• • • • •

x

Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

1\
•
?

Table 14 Opcode Map
Bit Manipulation
Test&:
Setl

8rnch

Branch

Clear

Rei

0

1
BSETO

2
BRA

0 BRSETO

DIR

j

3

I

A
4

I

x

I

)(1

I

,XO

I

5

I

6

I

7

NEQ

-

BRCLRO

BCLRO

BRN

2 BRSET!
3 BRCLRI

BSET!
BCLRI

BHI

4

BRSET2
5 BRCLR2
6 BRSET3
7 BRClR3
8 BRSET4

BSET2
BCLR2

9 BRClR4

BClR4

BHCS

A BRSET6
B BRClR5
C BRSETS

BSETS
BSETS

BPl
BMI
BMC

BClR6
BSET7

BMS
Bil

TST

BClR7

BIH

ClR

1

0 BRClRS
E BRSET7
F BRCLR7

3/10 .

BSET3
BClR3
BSET4

~ClR5

2/7

-

-

ROR
ASR

BHCC

-

LSl/ASl
ROl

-

DEC

-

INC

-

2/4

2/6

\ 114

\ 1/4

8
RTI'
RTS'
SWI'

LSR

BCS
BNE
BEQ

IMP

-

COM

BLS
BCC

\ 217

Register IMemory

Control

Read/Modify !Write

\1/6

II'

IMP

IMM

I

OIR

I

9

A

I

B

I

EXT

-

TAX

RSP
NOP.

-

TXA

1/2

)(2

I

)(1

DIE
SUB

3. (

246

9

6
II

6SR
B
) i"dlut. thlt thl "1.1mbif' in

-

-

2

cpx

3
4

-

BIT
lOA
STA!_1l

5

EOR

8

HITACHI

6
7

9
B
C
0
E
F

lOX
STX!+11

\

2/2 \ 2/4

A

JSR!-31

BSR'\

\ 3/5

~H

3/6

\ 2/5

IGH

0
1

ADC
ORA
ADD
JMPI-1l

pet9nrh",. mu~ be added to the evel. ooU"t for thlt innruction .

•

F

SBC

2. The number at the bottom of tach column denote the numb.r of bytes Ind the number of Clvcl" required (Svttl/eVa'..).
Mntmoniot followed bV • fl." require, different number of CVcftl .. fonaws;

RTI

,XO

AND

(NOTE) 1. Und.fI"ed OlXlodu ", mIIrked with "_Of.

RTS
SWI

I
J

CMP

CLC
SEC
Cli
SEI

I

Cl

J 1/4

L

o
w

H06301 V1 ,H063A01 V1 , - - H063B01V1
CMOS MCU (Microcomputer Unit)
The HD6301VI is an 8-bit CMOS single-chip microcomputer unit, Object Code compatible with the H1>6801. 4kB
ROM, 128 bytes RAM, Serial Communication Interface (SCI).
parallel I/O ports and multi function timer are incorporated
in the lID6301 VI. It is bus compatible with HMCS6800. Execution time of key instructions are improved and several
new instructions are added to increase system throughput.
The HD6301VI can be expanded up to 65k words. Like the
HMCS6800 family, I/O level is TIL compatJ."le with +5.0V
single power supply. As H06301 VI is fabricated by the ad·
vanced CMOS process technology, power dissipation is extreme·
ly reduced. In addition to that, HD630 I V I has Sleep Mode and
Standby Mode at lower power dissipation mode. Therefore
flexible low power consumption application is possible.
•
•
•

FEATURES
Object Code Upward Compatible with HD6801 Family
Abundant On..chip Functions Compatible with HD6801VO;
4kB ROM.128 Bytes RAM,29 Parallel I/O Lines, 2 Lines of
Data Strobe, 16·bit Timer, Serial Communication Interface
Low Power Consumption Mode: Sleep Mode, Standby Mode
Minimum Instruction Execution Time
IllS (f=IMHz), 0.671ls (f=I.5MHz), 0.5Ils (f=2MHzl
Bit Manipulation, Bit Test Instruction
Protection from System Upset: Address Trap, On·Code Trap
Up to 65k Words Address Space
Wide Operation Range
Vcc=3 to 6V (f-0.l-D.5MHz),
f=O.1 to 2.0MHz (Vcc=5V±10%)

•
•
•
•
•
•

•

HD6301V1P, HD63A01V1P, HD63B01V1P

HD6301Vl F, HD63A01Vl F, HD63B01Vl F

(FP·54)
HD6301 Vl CG,HD63AOl Vl CG,HD63BOl Vl CG

TYPE OF PRODUCTS
Type No.

HD6301Vl

Bus Timing
1 MHz

HD63A01Vl

1.5 MHz

HD63B01Vl

2MHz

(CG-40)

•

HITACHI

247

HD6301Vl,HD63A01Vl,HD63B01Vll---------------------• PIN ARRANGEMENT
• HD6301V1P, HD63A01V1P,
HD63B01V1P

•

HD6301V1F, HD63A01V1F,
HD63B01V1F

•

HD6301V1CG,HD63A01V1CG,HD63B01V1CG

~
~

a..

~
~

CL

. .... .... ....
0

CL

~~J L;J L~J :"~J ~;:;J ~~J L~J t~ L~J L~J
Pl1

f~

[~s

P44

P30

J!J

~~
~)

P46

3:8J
sc, 3jJ
E {oj
se2

P'3

- ,_ _ _ _ _ _ _r-'

(Top View)

22

1J

[~o

PH

~J

[(9

P'6

EXTAL

~J

~~8

P'5

NMI

~]

~!

P'4

IRQ,

~]

[1~ P13

r.oi rr:..~ fcOl f;1 r~1 r::1 r~l r~-: f:1 r~1
(Top View)

(Top View)

P21
~p"

P20

P23

p"

.....- - - P , o

E=::Pll
P12

..'::==:::

P"
P14
P,.

.....---P16

.....---p"

HITACHI

P47

Vee

Vss

vee

•

[2j
[~1

XTAL

• BLOCK DIAGRAM

248

P4S

----------------------HD6301Vl,HD63A01Vl,HD63B01Vl
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Supply Voltage

Value

Unit

-0.3 -+7.0

V

Operating Temperature

Vee
V ln
T opr

-0.3 - Vee+D.3
0- +70

V
°c

Storage Temperature

T""

-55 -+150

°c

Input Vo Itage

(NOTEI This product has protection circuits in input terminal from high static electricitv voltage and high electric field.
But be careful not to apply avervoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vin. V out : Vss :;; (Vin or Vout) :; Vee.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS !Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.'
Test Condition

Symbol

Item

"RES, SiiiY
Input "High" Voltage

EXTAL

min
Vee-0.5
Vee xO.7

VIH

Other Inputs

2.0

Input "Low" Voltage

All Inputs

V IL

Input Leakage Current

NMi, iR""Cl., RES, STBY

IIln I

V ln =0.5-V ee -0.5V

Three State (off-state'
Leakage Current

p. O-P 17 , P20 -P24 ,
P30 -P37 , P40 -P. 7 , TS3"

IITSII

VI" =0.5-V ee -0.5V

Output "High" Voltage

All Outputs

V OH

10H = -200IJA
10H = -lOp.A

Output "Low" Voltage

All Outputs

VOL

10L = 1.6mA
Vin=OV, f= 1.0MHz,
Ta = 25°C
Operating(f=l MHz'"

Input Capacitance

All Inputs

Cln

Standby Current

Non Operation

I~e

Current Dissipation'

lee

RAM Stand·By Voltage

V RAM

-0.3

Sleeping (f=l MHz",

-

typ

-

-

-

max

Unit

Vee
to.3

V

0.8

V

1.0

IJA

1.0

IJA

-

V
V

-

-

0.55

V

-

-

12.5

pF

-

2.0

15.0

IJA

6.0
1.0

10.0
2.0

mA

-

-

2.4
Vee- 0.7

2.0

V

vcc-1.OV, V IL max = O.SV
•• Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current DissipatiOns at f = X MHz operation are decided according to the following formula;
,VIM,min

z

typ. value If· x MHzl = typ. value (f· 1 MHzl x x
max. value (f = x MHzl • max. value (f • 1 MHzl x x
(both the sleeping and operatingl

•

HITACHI

249

HD6301V1,HD63A01V1,HD63B01V1--------------------------------------------• AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta - O-+70·C, unless otherwise noted.)
BUS TIMING
Item

Symbol

Cycle Time
Address Strobe Pulse Width
"High"

Test
Condition

HD6301V1
HD63A01V1
HD63B01Vl
Unit
typ max min typ max min typ max

min

1

tcyc

Address Strobe Rise Time
Address Strobe Fall Time

PWASH

220

tAS,

-

-

tASf
tASD
tE,

Adllress Strobe Delay Time
Enable Rise Time
Enable Fall Time
Enable Pulse Width "High" Level
Enable Pulse Width "Low" Level

tEf
PWEH
PWEL

450

Address Strobe to Enable Delay
Time

t ASED

60

~
Fig. 1
tAD2
Fig. 2
tADL

-

Address Delay Time
Address Delay Time for Latch
Write
Read
Read

Data Set·up Time
Data Hold Time

Write
Address Set·up Time for Latch
Address Hold Time for latch
Address Hold Time
Ao - A, Set·up Time Before E
P
eripheral Read
Access Time

I

60

450

tosw
tOSR
tHR
tlolW

230
'80

tAS L
tAHL
tAH
tASM

60
30
20
200

0
20

Non·Multiplexed
(tACCN)
Bus

IMultiplexed Bus

Oscillator stabilization Time
Processor Control Set·up Time

-

(tACCM

-

10 0.66'6

-

150

20

-

20

-

40

-

20
20

-

-

20

-

-

-

300
300

-

-

-

40

-

-

-

250
250

-

-

190
190

-

250

tRC
tpcs

Fig. 10 20
Fig. 11 200

Symbol

Test
Condition

min typ

Port 1, 2, 3, 4

tpDSU

Fig. 3

200

-

Port 1, 2, 3, 4

tpDH

Fig. 3

200

Delay Time, Enable Positive
Transition to 0S3 Negative
Transition

toSD1

Fig. 5

Delay Time, Enable Positive
Transition to ~ Positive
Transition

tOSD2

-

20

-

-

- - 20 - - 220 220 20 - - 100 50 0 -

10 0.5

20
20

110

0
20
40
20

-

20
110

-

-

650

-

-

395

650

-

-

395

-

20

-

20

-

200

-

-

200

-

-

150
60

190

20
20
20

20
60

-

10

20
20

20
20

j.IS

ns
ns
ns
ns
ns
ns

-

ns
ns

-

ns

160
160

ns
ns

160

ns
ns
ns
ns

-

- -

-

-

-

-

270

ns

270

ns
ms
ns

- -

ns
ns
ns
ns
ns

PERIPHERAL PORT TIMING
Item
Peripheral Data
Set·up Time
Peripheral Data
Hold Time

Neg8-' Port 1

Delay Time, Enable
tive Transition to Peri·
pheral Data Valid

2" 3
' ,

4 lpwD

Input Strobe Pulse Width
Input Data Hold Time I Port 3
Input Data Setup Time

I

Port 3

lpwlS
tlH
tiS

HD6301V1

HD63B01V1

max min typ

ns

200

-

ns

300

-

-

300

ns

-

300

-

-

300

ns

-

300

-

-

300

ns

-

200
150

-

-

200

-

200

-

-

-

-

300

-

-

Fig. 5

-

-

300

-

Fig. 4

-

300

-

Fig. 6
Fig. 6

200
150

-

-

Fig. 6

0

200
150
0

•

HITACHI

Unit

-

200

- - -

max

-

-

• Except P21

250

HD63A01V1

max min typ

-

0

- - - -

ns
ns
ns

-----------------------HD6301V1,HD63A01V1,HD63B01V1
TIMER. SCI TIMING
Item
Timer Input Pulse Width

Test
Symbol Condition

min

typ

tPWT

2.0

-

-

2.0

-

-

-

400

-

-

-

2.0

-

0.6

0.4

-

HD6301V1

Delay Time, Enable Positive
Transition to Timer Out

tTO D

SCI Input Clock Cycle

t Scvc

2.0

SCI Input Clock Pulse Width

tPWSCK

0.4

Test
Symbol Condition

min

PW RSTL

3

-

2

-

150

-

Fig. 7

HD63B01Vl

HD63A01V1

max min

typ

Unit

typ

max

2.0

-

-

-

-

400

-

2.0

tcyc

0.4

-

-

0.6

0.6

tScvc

max min

400

tcyc

ns

MODE PROGRAMMING
Item

RES "low" Pulse Width
Mode Programming Set·up Time

tMPs

Mode Programming Hold Time

tMPH

Fig. 8

typ

HD63B01V1

HD63A01V1

HD6301V1

max min typ

-

3

-

2

-

-

150

-

-

max min

-

typ

3

-

2

-

150

max

-

-

Unit
tcyc
tCyc

ns

Address Strobe

(AS I

RJW .Ar-A.
ISC,.

IPort4)

MCUWrite

Oo-O"Ao-A,
IPor13)

MCU Read

0 0 -0" A,-A,
(Pou 3)

~ NotValid

Figure 1 Expanded Multiplexed Bus Timing

_HITACHI

251

HD6301Vl,HD63A01Vl,HD63B01Vl---------------------------------------------

E .....

IE'

A.... A.fPOlI4.

Rlii

RJS

tSC~

{SCII

MCUWrlte
0,-0,

--oool-----1------t-.

(Pori 31

MCU.Read

0,-0,
(Pori 31

---+--------------<1
uv
O.8V

~

NotValid

Figure 2 Expanded Non-Multiplexed Bus Timing

r

rMCURead

MCUW"te

E~
O.BV

Pili - PI'
PJO
p. 1I

-

PI'
p.,

_lPWO'

2.0V

DBV
All Oata

l"pulS

2.4V Data Valid

Port Outputs _ _ _ _ _ _ _-J "Jt::O;:.8::.V_ __

2.0V

O.BV

Notel Port 2: Except P"

Figure 4 Port Data Delay Times
(MCU Write)

·Port 3 Non-Latched Operation

Figure 3 Port Data Set-up and Hold Times
(MCU Read)

iS3
t,s
t'H

Add, ..,

Bu.

P IO

-

PI' 2.0V

Inputs

053-----..:..

O.BV

20V
OBV

Figure 6 Port 3 Latch Timing
(Single Chip Mode)
Figure 5 Port 3 Output Strobe Timing
(Single Chip Mode)

252

•

HITACHI

---------------------------------------------HD6301V1.HD63A01V1.HD63B01V1
1.4V

Timer

Counter _ _ _ _...J

'-"""1~="-:-..J

' -____

1~~)I~~p:: I _ _ _ _ _.:;.;.~
08V

P"
Output

"]'<:~

1>:2~0~V:--_

Oat8 Vahd

_____

~

08V

Figure B Mode Programming Timing
Figure 7 Timer Output Timing

r

v"

RL "2.2kn !4.0kn for E)

T'''''''"'lflH:

o.Equov

C

R

1S20"8

C =90pF for P30-P37. P40-P47. SCI. SC2
=30pF for PIO-Pn. P20-PU
=40pF for E
R =12kQ for PIO-PI7. P21l-P24, P:IO-P.17. P~O-P47. E. SCI. SCI

Figure 9 Bus Timing Test Loads (TTL Load)
Interrupt

Tes'

Internal
Addre.s Bus _ _Jl....._"'-_-"_ _I\._-J"-_.A _ _I\._..J"-_Jl. _ _"-_-"'-_I\._.J"-_A_....

"-_J....

NMi.

IRQt.

iRlh

Intern,l

---V--V--"",r--v-",",r--v--v-",",r-'"\I--v--"",,...-v-",",r-'V--'v--"",~

D.W~_-~--~o~p~o~~~~~~~~.n~r-~~""~~.n~~~~r'~~~~~~=r.~~~~~-'~
Internal
Raod

\~--------------

I

Internal
Write

Figure 10 Interrupt Sequence

E

-.-55~~"'--

-+_ _ _ _ _ _:Y:"_'-.
--I'~I~

_ _ _1_ _

~

~c~

Vee II--'=-''-'----'.e-----l
~~~~-----..,t--~-+--------~:~ ~~~vv~ee~ee~~~.~v-------

~
-I.__ ~ve~e-~~~v~------~I~~_i\OI------.•

" ' " _ ..
I ______

J1

~1III£)IfiiM&iiiu"I"gp

.

I~I--~~------Figure 11

Reset Timing

_HITACHI

253

HD6301Vl,HD63A01Vl,HD63B01Vl--------------------------------------------• FUNCTIONAL PIN DESCRIPTION

• Vee, Vss
These two pins are used for power supply and GND. Re·
commended power supply voltage is 5V ±IO%. 3 to 6V can
be use~ for low speed operation (100 - 500 kHz).
• XTAL, EXTAL

These two pins are connected with parallel resonant funda·
mental crystal, AT cut. For instance, in order to obtain the
system clock IMHz, a 4MHz resonant fundamental crystal is
used because the devide by 4 circuitry is included. EXTAL
accepts an external clock input of duty 50% (±10%) to drive,
then internal clock is a quarter the frequency of an external
clock. External· driving frequency will be less than 4 times as
maximum internal clock. For external driving, XTAL pin
should be open. An example of connection circuit is shown in
Fig. 12.
AT Cut Parallel Resonance Crystal

Co = 7 pF max
Rs = 60 n max
XTALr---~-----.

This output pin supplies system clock. Output is a single·
phase, TTL compatible and 1/4 of the crystal oscillation frequency. It will drive two LS TTL load and 40pF.
• Non maskable Interrupt

tL2

This level sensitive input requests maskable interrupt sequence. When IRQ! goes to "Low", the CPU waits until it
completes the current instruction that is being executed. Then,
if the interrupt mask bit in Condition Code Register is not set,
CPU begins interrupt sequence; otherwise, interrupt request is
neglected.
Once the sequence has started, the information of Pregram
Counter, Index Register, Accumulators, Condition Code Register are stored on the stack. Then the CPU sets the interrupt
mask bit so that no further maskable interrupts may be responded.

Jr

CL

'

(a) Crystal Interface

N.C.

Table 1 Interrupt Vectoring memory map

External Clock

Vector

(b) External Clock
Figure 12 Connection Circuit

Highest
Priority

• Stand' , (STBY)

This pin is used to place the MCU in the Standby mode.
If this goes to "Low" level, the oscillation stops, the internal
clock is tied to Vss or Vee and the MCU is r~set. In order to
retain information in RAM during standby, write ''0'' into RAM
enable bit (RAME). RAME is bit 6 of the RAM Control Register
at address $0014. This disables the RAM, so the contents of
RAM is guaranteed. For details of the standby mode, see the
Standby section.
• Reset ("II"n)

This input is used to reset the MCU. RES must be held
"Low" for at least 20ms when the power starts up. It Should be
noted that, before clock generator stabilize, the internal state
and I/O ports are uncertain, because MCU can not b~ reset
without clock. To reset the MCU during system operation, it
must be held "Low" for at least 3 system clock cycles. From
the third cycle, all address buses become "High-impedance"
and it continues while RES" is "Low". If R£S goes to "High",
CPU does the following.

254

0IiMT)

When the falling edge of the inpu t signal of this pin is recognized, NMI sequence starts. The current instruction is continued to complete, even if NMI signal is detected. Interrupt
mask bit in Condition Code Regist~r has no effect on NMI
detection. In response to NMI interrupt, the information of
Program Counter, Index Register, Accumulators, and Condition
Code Register are stored on the stack. On completion of this
sequence, vectoring address $FFFC and $FFFD are generated
to load the contents to the program counter. Then the CPU
branch to a non maskable interrupt service routine.
• Interrupt Request (fRQi)

!32-8MHz)

EXTAL f---""

XTAL

• Enable (E)

C LI • C L2 = 10-22pF , 20%

Cl

EXTAL

(I) I/O Port 2 bits, 2,1,0 are latched into bits PC2, PCl, PCO of
program con trol register.
(2) The contents of the two Start Addresses, $FFFE, $FFFF
are brought to the program counter, from which program
starts (see Table 1).
(3) The interrupt mask bit is set. In order to have the CPU
recognize the maskable interrupts IRQ! and IRQ2, clear
it before those are used.

Lowest
Priority

Interrupt

Msa

Lsa

FFFE

FFFF

m

FFEE

FFEF

TRAP

FFFC

FFFO

FFFA

FFFI

NM1
So'~.

In",rupt (SWIt

ilm,

FFFI

FFFI

FFFe

FFF7

leF ITu"" Input C.-ur••

OCF (T imer OutPUt Com.,.,.

lor 1$3)

FFF4

FFF5

FFF,

FFF3

TOF ITuN' Odrflowl

FFFO

FFFI

SCI (RDRF + OAFE + TORE I

At the end of the cycle, the CPU generates 16 bit vectoring
addresses indicating memory addresses $FFF8 and $FFF9, and
load the contents to the Program Counter, then b ranch to an
interrupt service routine.
The Internal Interrupt will generate signal (IRQ2) which is
quite the same as IRQ! except that it will use the vector address
$FFFO to $FFF7.
When ffiQi and 1RQi are generated at the same time, the
former precede the latter. Interrupt Mask Bit in the condition
code register, if being set, will keep the both in terrupts off.
IRQi has no internal latch. Therefore, if lRQl is removed
during suspension, that IRQi is ignored.

_HITACHI

-----------------------------------------------HD6301V1,HD63A01V1,HD63B01V1
On occurrence of Address error or Op·code error, TRAP
interrupt is invoked. This interrupt has priority next to RES.
Regardless of the Interrupt Mask Bit condition, the CPU will
start an interrupt sequence. The vector for this interrupt will be
$FFEE, $FFEF.

Table 2 Port and Data Direction Register Addresses
Ports
I/O
I/O
I/O
I/O

Port 1
Port 2
Port 3
Port 4

Port Address

Data Direction
Register Address

$0002
$0003
$0006
$0007

$0000
$0001
$0004
$0005

The following pins are available only in single chip mode.
•

• I/O Port 1

Input Strobe (lS3) (Sed

This signal controls IS3 interrupt and the latch of Port 3.
When the falling edge of this signal is detected, the flag of
Port 3 Control Status Register is set.
For detailed explanation of Port 3 Control Status Register,
see the I/O PORT 3 CONTROL STATUS REGISTER section.
•

Output Strobe (OS3) (SC2 )

This signal is used to send a strobe to an external device,
indicating effective data is on the I/O pins. The timing chart for
Output Strobe are shown in Figure 5.

This is an 8-bit port, each bit being defined individually as
input or outputs by associated Data Direction Register. The
8-bit output buffers have three-state capability, maintaining in
high impedance state when they are used for input. In order to
be read accurately, the voltage on the input lines must be more
than 2.0Y for logic" I" and less than 0.8 Y for logic "0".
These are TTL compatible. After the MCU has been reset, all
I/O lines of Port 1 are configured as inputs in all modes except
mode I. In all modes except expanded non multiplexed mode
(Mode 1), Port 1 is always parallel I/O. In mode 1, Port 1 will be
output line for lower order address lines (Ao to A7).

The follOWing pins are available for Expanded Modes.
•
• ReadlWrite (R/W) (SC2)

This TTL compatible output signal indicates peripheral and
memory devices whether CPU is in Read ("High"), or in Write
("Low"). The normal stand-by state is Read ("High"). Its
output will drive one TTL load and 90pF.
•

I/O Strobe (lOS) (SCI)

In expanded non multiplexed mode 5 of operation, IDS
goes to "Low" only when A9 through Au are "0" and As is
"\" . This allows external access up to 256 addresses from
$0100 to SOIFF in memory. The timing chart is shown in
Figure 2.
• Address Strobe (AS) (SCd

In the expanded multiplexed mode, address strobe signal
appears at this pin. It is used to latch the lower g bits addresses
multiplexed with data at Port 3. The g-bit latch is controlled
by address strobe as shown in Figure 18. Thereby, I/O Port 3
can become data bus during E pulse. The timing chart of this
signal is shown in Figure I.
Address Strobe (AS) is sent out even if the internal address
area is accessed.
• PORTS

There are four I/O Ports on HD630lYI MCU (three 8·bit
ports and one S-bit port). 2 control pins are connected to one
of the g-bit port. Each port has an independent write·only data
direction register to program individual I/O pins for input or
output.'"
When the bit of associated Data Direction Register is "I ".
I/O pin is programmed for output, if "0", then programmed for
an input.
There are four ports: Port I, Port 2, Port 3, and Port 4.
Addresses of each port and associated Data Direction Registers
are shown in Table 2.
'" Only one exception is bit 1 of Port 2 which becomes either a
data input or a timer output. It cannot be used as an output
port.
does not affect I/O port Data Register. Therefore, just
Data Register is uncertain. Data Direction Registers
after
are reset.

m

m,

•

I/O Port 2

This port has five lines, whose I/O direction depends on its
data direction register. The 5-bit output buffers have three-state
capability, going high impedance state when used as inputs. In
order to be read accurately, the voltage on the input lines must
be more than 2.OY for logic "I" and less than O.8Y for logic
"0". After the MCU has been reset, I/O lines are configured as
inpu ts. These pins of Port 2 (pins P20, P21, P22 of the chip) are
used to program the mode of operation during reset. The values
of these three pins during reset are latched into the upper 3 bits
(bit 7, 6 and 5) of Port 2 Data Register, which is explained in
the MODE SELECTION section.
In all modes, Port 2 can be configured as I/O lines. This port
also provides access to the Serial I/O and the Timer. However,
note that bit 1 (P21) is the only pin restricted to data input or
Timer output.
•

I/O Port 3

This is an 8·bit port which can be configured as I/O lines, a
data bus, or an address bus multiplexed with data bus. Its
function depends on hardware operation mode programmed by
the user using 3 bits of Port 2 during Reset. Port 3 as a data bus
is bi-directional. For an input from peripherals, regular TTL
level must be supplied, that is greater than 2.OY for a logic "I"
and less than O.8Y for a logic "0". This TTL compatible threestate buffer can drive one TTL load and 90pF. In the expanded
Modes, data direction register will be inhibited after Reset and
data direction will depend on the state of the R/W line. Function of Port 3 is shown below.
Single Chip Mode (Mode 7)

Parallel Inputs/Outputs as programmed by its corresponding
Data Direction Register.
There are two control lines associated with this port in this
mode, an input strobe (ID) and an output strobe (0S3), both
being used for handshaking. They are can trolled by I/O Port 3
Control/Status Register. Function of these two cont(ol lines of
Port 3 are summarized as follows:
(I) Port 3 input data can be latched using 1S3 (SCI) as a
input strobe signal.
(2) US3 can be generated by CPU read or write to Port 3's
data register.
(3) IRQI interrupt can be generated by an m falling
edge .

HITACHI

255

HD6301 Vl ,HD63A01Vl ,HD63BOl V l - - - - - - - - - - - - - - - - - - - - - Port 3 strobe and latch timing is shown in Figs. 5 and 6
respectively.
I/O Port 3 Control/Status Register is explained as follows:
I/O Port 3 Control/Status Register

Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit3 LATCH ENABLE.
Bit 3 is used to control the input latch of Port 3. If the bit is
set at "I", the input data on Port 3 is latched by the falling edge
of IS3. The latch is released by the MCU read to Port 3; now
new data can be latched again by IS3 falling edge. Bit 3 is
cleared by a reset. If this bit is "0", IS3 does not affect I/O
Port 3 latch operation.
Bit 4 OSS (Output Strobe Selectl
This bit ideritifies the cal}se of output strobe generation: a
write operation or read operation to I/O Port 3. When the bit is
cleared, the strobe will be generated by a read operation to Port
3. When the bit is not cleared, the strobe will be generated by a
write operation. Bit 4 is cleared by a reset.
Bit 5 Not used.
Bit 6 TS3 fROi ENABLE.
If this bit is set, IRQi' interrupt by IS3 Flag is enabled.
Otherwise the interrupt is disabled. The bit is cleared by a
reset.
Bit 7183 FLAG.
Bit 7 is a read-only bit which is set by the falling edge of IS3
(SCI). It is cleared by a read of the Control/Status Register followed by a read/write of I/O Port 3. The bit is cleared by reset.
Expanded Non Multiplexed Mode (mode 1,5)
In this mode, Port 3 becomes data bus. (Do - D7)
Expanded Multiplexed Mode (mode 0, 2,4,6)
Port 3 becomes both the data bus (Do - D7) and lower bits
of the address bus (Ao - A7). An address strobe output is "High"
while the address is on the port.

• 1/0 Port 4
This is an 8-bit port that becomes either I/O or address
outputs depending on the selected operation mode. In order
to be read accurately, the voltage at the input lines must be
greater than 2.0V for a logic "I", and less than 0.8V for a logic
"0". For outputs, each line is TTL compatible and can drive one
TTL load and 90pF. Function of Port 4 for each mode is
explained below.
Single Chip Mode (Mode 7): Parallel Inputs/Outputs as programmed by its associated data direction register.
Expanded Non Multiplexed Mode (Mode 5): In this mode,
Port 4 becomes the lower address lines (Ao to A 7) by writing
"I "s on the data direction register. After reset, this port
becomes inpu ts. In order to use these pins as addresses, they
should be programmed as outputs.
When all of the eight bits are not required as addresses, the
remaining lines can be used as I/O lines (Inputs only).
Expanded Non Multiplexed Mode (Mode 1): In this mode, Port
4 becomes output for upper order address lines (As to AIS)
regardless of the value of the direction register.
Expanded Multiplexed Mode (Mode 6): In this mode, Port 4
becomes the upper address lines (As to Au). After reset, this

256

•

port becomes inputs. In order to use these pins as addresses,
they should be programmed as outputs. When all of the eight
bits are not required, the remaining lines can be used as I/O
lines (input only).
Expanded Multiplexed Mode (Mode 0, 2, 4): In this mode, Port
4 becomes output for upper order address lines (As to Au)
regardless of the value of data direction register.
The relation between each mode and I/O Port 1 to 4 is
summarized in Table 3.
• MODE SELECTION
The operation mode after the reset must be determined by
the user wiring the P20, P21 and P22 pins externally. These three
pins are lower order bits; I/O 0, I/O I, I/O 2 of Port 2. They are
latched into the control bits PCO, PC I, PC2 ofI/O Port 2 register when reset goes "High". I/O Port 2 Register is shown below.
Port 2 DATA REGISTER
•

$00031

pc21

PC'

I

PeG

•

0

1"0.1"031,1021,10, 1"00 I

An example of external hardware used for Mode Selection is
shown in Fig. 13. The HDI4053B is used to separate the peripheral device from the MCU during reset. It is necessary if
the data may conflict between peripheral device and Mode
generation circuit.
No mode can be changed through software because the bits
5, 6, and 7 of Port 2 pata Register are read-only. The mode
selection of the HD6301VI is shown in Table 4.
The HD630lVI operates in three basic modes: (I) Single
Chip Mode; (2) Expanded Multiplexed Mode (compatible with
the HMCS6800 peripheral family), (3) Expanded Non Multiplexed Mode (compatible with HMCS6800 peripheral family).
• Single Chip Mode (Mode 7)
In the Single Chip Mode, all ports will become I/O. This is
shown in Figure 15. In this mode, SCI ,SC2 pins are configured
for control lines of Port 3 and can be used as input strobe (lS3)
and output strobe (O'SJ) for data handshaking.
• Expanded Multiplexed Mode (Mode 0, 2,4,6)
In this mode, Port 4 is configured for I/O (inputs only) or
address lines. The data bus and the lower order address bus are
multiplexed in Port 3 and can be separated by the Address
Strobe.
Port 2 is configured for 5 parallel I/O or Serial I/O, or Timer,
or any combination thereof. Port 1 is configured for 8 parallel
I/O. In this mode, HD6301VI is expandable up to 6Sk words
(See Fig. 16).
•

Expended Non Multiplexed Mode (Mode 1, 5)
In this mode, the HD630lVI can directly address HMCS6800
peripherals with no external logic. In mode 5, Port 3 becomes a
data bus. Port 4 becomes Ao to A 7 address bus or partial
address bus and I/O (inputs only). Port 2 is configured for a
parallel I/O, Serial I/O, Timer or any combination thereof.
Port I is configured as a parallel I/O only.
In this mode, HD630lVI is expandable to 256 locations.
In mode I, Port 3 becomes a data bus and Port I becomes
Ao to A 7 address bus, and Port 4 becomes As to Au address
bus.

HITACHI

---------------------------------------------HD6301V1,HD63A01V1,HD63B01V1
In this mode, the HD6301 VI is expandable to 65k words
with no extema1logic. (See Fig. 17)
•

Lower Order Address Bus Latch

address bus in Port 3 in the expanded multiplexed mode,
address bits must be latched. It requires the 74LS373 Trans·
parent octal Ootype to latch the LSB. Latch connection of
the HD630lVI is shown in Figure 18.

Because the data bus is multiplexed with the lower order
Vee

R

.---

AI RI R,

1m

RES

W

H06301Vl

X,

V,

X

PlO (PCOI

~z,

v

PI1 (PC1)

X,

z

PII (PC21

V,
Z,

C

I

Inh

H014053B

??? ~n"ol
~

Note

1) Figure of Mode 7
2) RC .. Reset Constant
3) R,=10kn

L......-

Mode

Swhoh

Figure 13 Recommended Circuit for Mode Selection

Truth Table
COntrol Input

Inh
Inhlbll

A
B
C

X.
X,

X

V.
V,

V

Z.
Z,

Z

Select

On SWitch

C B A H014053B

0

0 0 0

Z, Yo X..

0

0 0 I

Zo Yo X.

0

0 I

0

Zo V. X,

0

0 I

I

20'''1. XI

0

I

0 0

Z.

0

I

0 I

0

I

I

0

2. ""0 XI
Z. V. X,

0

I

I

I

2. V. XI

I

X X X

y~

X,

..

Figure 14 HD14053B Multiplexers/De·Multiplexers
Vcc
Enable

Port 1
81/0 Line.

Port 3

Port 1
8 I/O Line.

8 I/O Line.

Port 4

Port 2

51/0 Lin..

5 I/O Line.
SCI
Timer

Tim.r

Port 2

8 I/O Line.
vss

POI. 4

8 Addre..

SCI

LiMlor
81/0 Lin ..
VSS

Figure 15 HD6301Vl MCU Single·Chip Mode

(Inputs Onlvl

Figure 16 HD6301Vl MCU Expanded
Multiplexed Mode

•

HITACHI

257

HD6301V1,HD63A01V1,HD63B01V1---------------------Vee

Vee

Port 1
8 Parallel I/O

Port 3
8 Data Lines

Port 2
5 Parallel 110
SCI

Port 4
8 Address

Port 2
5 Parallel I/O
SCI

Lines or
8110 Lines

Timer

Port 3
8 Data Lines

Port 1
To 8 Address Lines

Port 4
8 Address
Lines

Timer

l!nputs Only)

V"

Vss

(a) Mode 5

(b) Mode 1

Figure 17 HD6301Vl MCU Expanded Non Multiplexed Mode
GNO

,

~

AS

a,

0,

Po•• 3

Address/Data

1
)

74lS373

[

Function Table
Add .... ",-A,
Output
Control

~

)

~,O,-o

Output

Enable

a

lOCI
l
l
l

G

0

H
H

H

l

l

l

X

H

x

x

a,

H

z

Figure 18 Latch Connection

•

Summary of Mode and MCU Signal

This section gives a description of the MeU signals for the
various modes. SC', and SC' 2 are Signals which vary with the mode.

Table 3

--

Feature of each mode and lines

MODE

PORT 1
Eight lines

PORT 2
Five lines

PORT
3
Eight lines

PORT 4
Eight lines

SINGLE CHIP (Mode 7)

I/O

I/O

SCI

SC,

I/O

I/O

IS3 (I)

OS3(0)

EXPANDED MUX
(Mode 0, 2, 4, 6)

I/O

I/O

ADDRESS BUS
(Ao-A,)
DATA BUS

ADDRESS BUS'
(A,-A,,)

AS(O)

RiW(O)

ADDRESS BUS'
(Ao-A,)

10S(0)

RIW(O)

ADDRESS BUS
(A.-A,,)

Not Used

R/W(O)

I

(00-0,)

EXPANDED

I (Mode 5)

I/O

I/O

NON·MUX

i (Mode 1)

ADDRESS BUS
(Ao-A,)

I/O

DATA BUS
(00-0,)

I

DATA BUS
(00-0,)

'These lines can be substituted for 110 (Input Only) (except Mode 0, 2,4)
I

o
R/W

258

Input
Output
• ReadlWrtle

=

153
053
lOS

• Input Strobe
• Output Strobe
= 110 Select

SC
= Strobe Control
A S ' Addre .. Strobe

$

HITACHI

---------------------------------------------HD6301V1.HD63A01V1.HD63B01V1
Table 4 Mode Selection Summary

-

1~l:~1

7

6

I~l:°'}

I~CO}

H

H

H

I

I

I

I

H

H

L

I

I

I

5

H

L

H

I

I

I

MUxI41
NMUxl41

4

H

L

L

E(21

1(11

E

3
2

L

H

H

-

'L

H

L

1111

1

L

L

H

0

L

L

L

ROM

EI21
E12}

Vectors

I
I

I

Bu.

Interrupt

RAM

Mode

Operating
Mod.
Singl.Chip
Multlplexed/PartillOecode

Non·Multiple.edJPartial Decode

-

MUX
-

Multiplexed/RAM
Not Used

E
E
1131

MUX
NMUX
MUX

Non-Multiplexed

Multiplexed/RAM
Multiplexed Tilt

INOTES)
,) Internal RAM is addressed ., $0080.
2) I nternal ROM is disabled.

LEGEND:
I - }!llernal

E - External
MUX
- Multiplexed
NMUX
- Non-Multiplexed
L - Logic "0"

3) Reset vector is external for 3 or 4 cycles after

RES goes "high".
4) Idle lines of Port 4 address outputs can
be assigned to I nput Port.

H - Logic "'"

• MemoryMap

The MCU can provide up to 65 k byte address space
depending on the operating mode. Fig. 19 shows a memory map
for each operating mode. The first 32 locations of each map are
for the MCU's internal register only, as shown in Table 5.

Table 5 Inter nal Register Area
Register

Addreu

Port 1 DatI Direction Register ••••

00'

Port 2 Data DirectIon Register ••••
Port 1 Olta Register
Port 2 Data Register

02'
03

Port 3 Data Dir8Ctton Register····

Port 4 Data Direction Register ••••

01

04"
05'"

Port 3 Oa,. Regtlt.,
Port 4 Data Register

06"

Timer Control and StatuI Regist.r
Count" IHogh Byte}
Counter (Low By tit
Output Com_e Regist., IHigh Byte)

DB
09

Output Compere Aeglster CLow Byte)
Input Capture Regist.r tHigh Byte)
Input Capture Aeglster (Low Byt.)
Pon 3 ContrOl and Status Register

DC

Rate and Mode Control Reglstet'
Transmit/Receive ContrOl and Status Register
RecetYe Data Register
Transmit Data Register

10
11

07'"

OA
OB

DO
OE

OF"-

12
13
14
IS'IF

RAM ContrOl Register

Reserwct

• External address in Mode 1
External address In Modes 0,1,2,4,6; cannot be
accessed In Mode 5
External address In Modes O. 1. 2. 4
, = Output. 0 = Input

$

HITACHI

259

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------

HD6301V1Q
Mode

HD6301Vl
Mode

1

Non-MultipleKed, Partial Decode

MultipleKed Test mode
SOOOO(1)

$0000
Internal A.glsters

Internal Registers

SOOIF

SOOIF

External Memory Space

Externa) Memory Space

S0080

SOO80

Internal RAM

Internal RAM

SOOFF
$OOFF

External Memory Space
External Memory Space

Internal ROM

$FFFF ' - - - -.... '

INOTEI

(NOTESI
11 Excludes the follOWing addresses which may be

Excludes the following addresses which may be

used externally: $04, $05, $06, $07 and $OF,
2) Addresses $FFFE and $FFFF are conSIdered

used externally; $00, $02, $04, S05, $06, $07
and $OF,

external If accessed within 3 or 4 cvcles after a

positive edge of RES and IOternal at all other 'Imes.
3) After 3 or 4 CPU cycles, there must be no overlapping
of Internal and external memory spaces to avoid
driving the data bus wIth more than one device.
41 ThiS mode IS the only mode which is used for

testmg.

Ito be continued)

Figure 19 HD6301Vl Memory Maps

260

•

HITACHI

----------------------HD6301V1,HD63A01V1,HD63B01V1

HD6301V12
Mode

HD6301Vl,J1
Mode
.....

HD6301V15
Mode

Multiplexed/RAM

Non·MultlpleKed/Partial Decode

$0000

$0000
Internal Registers

} Internal Registers

$OOlF

SOOlF
E xt.rnal Memory Space

$0080

I

S0080

Internal RAM

Internal RAM

SOOFF

$0100

SOOFF

} ElCternal Memory Space

$01 F F '----,_.....

External Memoc.y Space

SFOOO

Internal ROM
SFFFF ' -_ _ _... ,
Internal Interrupt Vectors

$FFFF
(NOTE]

Excludes the followmg address which

may be used externally; $04. $05. $06.

(NOTE]

$07. $OF.

Excludes $04, $06. $OF.
These address cannot be used
externally.

(to be continued)

Figure 19 HD6301Vl Memory Maps

$

HITACHI

261

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------

HD6301V16
Mode

HD6301V17
Mode
Single Chip

Multiplexed/Partial Decode
$0000

SOOOO

Internal Registers

Internal Registers

s00IF

$00IF
External Memory Space

SOOBO

S0080
Internal RAM

SOOFF

SOOFF

external Memory Space

$FOOO
Internal ROM

SFFFF

Internal Interrupt Vectors

Internal Interrupt Vectors

$FFFF

(NOTE(
Excludes the following address which may be

used externally: $04, S06, $OF.

Figure 19 HD6301Vl Memory Maps

262

•

HITACHI

---------------------------------------------HD6301V1,HD63A01V1,HD63B01V1
• PROGRAMMABLE TIMER
The HD6301VI contains 16-bit programmable timer which
may be used to make measurement of input waveform. In
addition to that it can generate an output waveform by itself.
For both input and output waveform, the pulse width may vary
from a few microseconds to several seconds.
The timer hardware consists of
• an 8-bit control and status register
• a 16-bit free running counter
• a 16-bit output compare register, and
• a 16-bit input capture register
A block diagram of the timer is shown in Figure 20_

Sit 1
Port 2
OOR

r--w __
_____ J Output
Ltvel
Bit 1
Port2

tSAF3 written to the counter)

Figure 21 Counter Write Timing
• Output Compare Register ($OOOB:$OOOC)
This is a 16-bit read/write register which is used to control an
output waveform. The contents of this register are constantly
being compared with current value of the free running counter.
When the contents match with the .value of the free running
counter, a flag (OCF) in the timer control/status register
(TCSR) is set and the current value of an output level Bit
(OLVL) in the TCSR is transferred to Port 2 bit I. When bit I
of the Port 2 data direction register is "I" (output), the OLVL
value will appear on the bit I of Port 2. Then, the value of Output Compare Register and Output level bit may be changed
for the next compare.
The output compare register is set to $FFFF during reset.
The compare function is inhibited at the cycle of writing
to the high byte of the output compare register and at the
cycle just after that to ensure valid compare. It is also inhibited
in same manner at writing to the free running counter.
In order to write a data to Output Compare Register, a
double byte store instruction (ex. SID) must be used.

w

•

nput
Edge

81tO
Port2

Figure 20 Programmable Timer Block Diagram
•

Free Running Counter ($0009: $OOOAI
The key element in the programmable timer is a 16-bit free
running counter, that is driven by an E (Enable) clock to
increment its values. The counter value will be read out by the
CPU software at any time with no effects on the counter.
Reset will clear the counter.
When the MSB of this counter is read, the LSB is stored
in temporary latch. The data is fetched from this latch by the
subsequent read of LSB. Thus cons!stent double byte data can
be read from the counter.
When the CPU writes arbitrary data to the MSB ($09), the
value of $FFF8 is being pre-set to the counter ($09, $OA)
regardless of the write data value. Then the CPU writes arbitrary data to the LSB ($OA), the data is set to the "Low" byte
of the counter, at the same time, the data preceedingly written
in the MSB ($09) is set to "High" byte of the counter.
When the data is written to this counter, a double byte
store instruction (ex. STD) must be used. If only the MSB of
counter is written, the counter is set to $FFF8.
The counter value written to the counter using the double
byte store instruction is shown in Figure 21.
To write to the counter may disturb serial operations, so it
should be inhibited during using the SCI in internal clock mode.

Input Capture Register ($OOOD:$OOOE)
The input capture register is a 16-bit read-only register used
to hold the current value of free running counter when the
proper transition of an external input signal occurs.
The input transition change required to trigger the counter
transfer is controlled by the input edge bit (IEDG).
To allow the exterl1al input signal to go in the edge detect
unit, the bit of the Data Direction Register corresponding to bit
oof Port 2 must have been cleared (to zero).
To insure input capture in all cases, the width of an input
pulse requires at least 2 Enable cycles.

• Timer Control/Status Register (TCSR) ($0008)
This is an 8-bit register. All 8 bits are readable and the lower
5-bit may be written. The upper 3 bits are read-only, indicating
the timer status information as is shown below.
(I) A proper transition has been detected on the input pin
(ICF).
(2) A match has been found between the value in the free
running counter and the output compare register (OCF).
(3) When counting up to $0000 (TO F).
Each flag has an individual enable bit in TCSR which
determines whether or not an interrupt request may
occur (IRQa). If the I-bit in Condition Code Register has
been cleared, a priority vectored address occurs corresponding to each flag. A description of each bit is as follows.
Timer Control I Status Register
76543210
'ieF

Bit 0

$

HITACHI

I

OCF

I I I I
TOF

flel

EOCI

ETOI'IEOG

I

OlVll SOOO8

OLVL (Output Level); When a match is found in the
value between the counter and the output com-

263

HD6301V1,HD63A01V1,HD63B01V11---------------------pare register, this bit is transferred to the Port 2
bit 1. If the DDR corresponding to Port 2 bit I is
set "I", the value will appear on the output pin of
Port 2 bit 1.
Bit 1 IEDG (Input Edge): This bit control which transition
of an input of Port 2 bit 0 will tril!!; me data
transfer from the counter to the input capture
register. The DDR corresponding to Port 2 bit 0
must be cleared in advance of using this function.
When IEDG =0, trigger takes place on a negative
edge ("High" to "Low" transition). When IEDG =
I, trigger takes place on a positive edge ("Low" to
"High" transition).
Bft 2 eTOI (Enable Timer Overflow Interrupt); When set,
this bit enables TOF interrupt to generate the
interrupt request (IRQ2). When cleared, the interrupt is inhibited.
Bit 3 EOCI (Enable Output Compare Interrupt); When set,
this bit enables OCF interrupt to generate the
interrupt request (lRQ2). When cleared, the interrupt is inhibited.
Bit 4 EICI (Enable Input Capture Interrupt); When set, this
bit enables ICF interrupt to generate the interrupt
request (lRQ2). When cleared, the interrupt is
inhibited.
Bit 5 TOF (Timer Over Flow Flag); This read-only bit is set
at the transition of $FFFF to $0000 of the
counter. It is cleared by CPU read of TCSR (with
TOF set) followed by an CPU read of the counter
($0009).
Bit 6 OCF (Outpu,t Compare Flag); This read-only bit is set
when match is found in the value between the
output compare register and the counter. It is
cleared by a read of TCSR (with OCF set) followed by an CPU write to the output compare
register ($OOOB or $OOOC).
Bit 7 ICF (Input Capture Flag); The read-only bit is set by a
proper transition on the input, and is cleared by
a read of TCSR (with ICF set) followed by an
CPU read ofinput Capture Register ($OOOD).
Reset will clear each bit of Timer Control and Status
Register.

a

• SERIAL COMMUNICATION INTERFACE
The HD6301VI contains a full-duplex asynchronous Serial
Communication Interface (SCI). SCI may select the several
kinds of the data rate. It consists of a transmitter and a receiver
which operate independently but with the same data format
and the same data rate. Both the t(ansmltter and receiver communicate with the CPU via the data bus and with the outside
world through Port 2 bit 2, 3 and 4. Description of hardware,
software and register is as follows.
• Wak.Up Feature
In typical multiprocessor applications the software protocol
will usually have the designated address at the initial byte of the
message. The purpose of Wake-Up feature is to have the nonselected MCU neglect the remainder of the message. Thus
the non-selected MCU can inhibit the all further interrupt
process un til the next message begins.
Wake-Up feature is re-enabled by a ten consecutive "I "s
which Indicates an idle transmit line. Therefore software protocol must put an idle period between the messages and must
prevent it within the message.

264

With this hardware feature, the non-selected MCU is reenabled or ("waked-up") by the next message.
• Programmable Options
The HD630lVI has the following programmable features.
• data format; standard mark/space (NRZ)
- clock source; external or internal
• baud rate; one of 4 rates per given E clock frequency or
1/8 of external clock
• wake-up feature; enabled or disabled
• interrupt requests; enabled or masked individually for
transmi tter and receiver
• clock output; internal clock enabled or disabled to Port
2 bit 2
• Port 2 (bits 3, 4); dedicated or not dedicated to serial
I/O individually
.
• Serial Communication Hardware
The serial communications hard~are is controlled by 4
registers as shown in Figure 22. The registers include:
• an 8-bit control/status register
• a 4-bit rate/mode control register (write-only)
• an 8-bit read-only receive data register
• an 8-bit write-only transmit data register
Besides these 4 registers, Serial I/O utilizes Port 2 bit 3
(input) and bit 4 (output). Port 2 bit 2 can be used when an
option is selected for the internal-clock-out or the externalclock-in.
• Transmit/Receive Control Status Register (TRCSR)
TRCS Register consists of 8 bits which all may be read while
only bits 0 to 4 may be written. The register is initialized to $20
on RES. The bits of the TRCS register are explained below.
Transmit I Receive Control Status Register
78543210

Bit 0 WU (Wake Up); Set by software and cleared by hardware
on receipt of ten consecutive "I "s. While this bit
is "I", RDRF and ORFE flags are not set even
if data are received or errors are detected. therefore received data are ignored. It should be noted
that RE flag must have already been set in advance
ofWU flag's set.
.
Bit 1 TE (Transmit Enable); This bit enables transmitter. When
this bit is set, bit 4 of Port 2 DDR is also forced
to be set. It remains set even if TE is cleared.
Preamble of ten consecutive "I "s is transmitted
just after this bit is set, and then transmitter
becomes ready to send data.
If this bit is cleared, the transmitter is disabled
and serial I/O affects nothing on Port 2 bit 4.
Bit 2 TIE (Transmit Interrupt Enable); When this bit is set,
TDRE (bit 5) causes an IRQ2 interrupt. When
cleared TDRE interrupt is masked.
Bit 3 RE (Receive Enable); When set, Port 2 bit 3 can be used
as an input of receive regardless of DDR value for
this bit. When cleared, the receiver is disabled.
Bit 4 RIE (Receive Interrupt Enable); Whell this bit is set,
RDRF (bit 7) or ORFE (bit 6) cause an rRQ2
interrupt. When cleared, this interrupt is masked.

_HITACHI

----------------------HD6301V1,HD63A01V1,HD63B01V1
Bit 5 TORE (Transmit Data Register Empty); When the data
is transferred from the Transmit Data Register
to Output Shift Register, this bit is set by hardware. The bit is cleared by reading the status register followed by writing the next new data into
the Transmit Data Register. TORE is initialized
to 1 by RES.
Bit 6 OR FE (Over Run Framing Error); When overrun or
framing error occurs (receive only), this bit is set
by hardware. Over Run Error occurs if the attempt
is made to transfer the new byte to the receive
data register while the RDRF is "I". Framing
Error occurs when the bit counter is not synchro-

Bit 7

I

nized with the boundary of the byte in the receiving bit stream. When Framing Error is detected, RDRF is not set. Therefore Framing Error
can be distinguished from Overrun Error. That is,
if ORFE is "I" and RDRF is "I", Overrun Error
is detected. Otherwise Framing Error occurs.
The bit is cleared by reading the status register
followed by reading the receive data register, or
byImS.
Bit 7 RDRF (Receive Data Register Full); This bit is set by
hardware when the data is transferred from the
receive shift register to the receive data register.
It is cleared by reading the status register followed
by reading the receive data register, or by

m.

Rate and Mode Control Register

Bit 0

I Icco I Isso 1.
CCI

551

,0

Transmit/Receive Control and Status Register

Port 2
RII:

~it

Clock

8;1

2

I.....:"--....,L___.-:::::::~:::::.---..J
11

to

1---'-"-------1

~.----------Figure 22 Serial I/O Register
6

5

x

4

2

1

0

I x I eel I eeo I SSl I sso I "OOR:

$0010

Tran,fer Rite 1 Mode Control Register

Table 6 SCI Bit Times and Transfer Rates
XTAL

SSI : SSO
0
0
1
1

0
1
0
1

E

2.4576 MHz
614.4 kHz

4.0 MHz
1.0MHz

E + 16
E + 128
E + 1024
E + 4096

26 1'./38,400 Baud
20811,/4,800 8aud
1.67mI/600 Baud
6.67ms/150 Baud

16 I's/62,500 Baud
128 I',I7BI2.6 Baud
1.024ms/976.6 Baud
4.096ms/244.1 Blud

_HITACHI

4.9152MHz
1.22B8MHz
13 I's/78,800Baud
104.21'.1 9,600Baud
833.31'sl 1,200Baud
3.333msl 3008aud

265

HD6301Vl,HD63A01Vl,HD63B01Vl--------------------------------------------Table 7 SCI Format and Clock Source Control
Clock Sourc.

PorI 2 Bil2

PorI 2 Bil3

PorI 2 Bit 4

0
0

0

-

-

-

1

1
1

0

NRZ
NRZ
NRZ

Inl.rnal
Inl.rnal
EXI.rnal

....
..

......

CC1:CCO

1

Formal

NOI Used'"
OUIPUI'
Inpul

-

* Clock output is available regardless of values for bits R E and TE .
•• Bil3 is used for serial inpul,f RE = "I" ,n TRCS.
Bil4 is used for serial OUlput if TE • "I" in TRCS.
*** This pin can be used as I/O port.

• Transfer rate/Mode Control Register (RMCR)
The register controls the following serial I/O functions:
• Bauds rate
·data format
• clock source
• Port 2 bit 2 feature
It is 4·bit write-only register, cleared by lffiS. The 4 bits are
considered as a pair of 2-bit fields. The lower 2 bits control the
bit rate of internal clock while the upper 2 bits control the
format and the clock select logic.
Bit 0 SSO}
Bit I SSI
Speed Select
These bits select the Baud rate for the internal clock. The
rates selectable are function of E clock frequency of the CPU.
Table 6 lists the available Baud Rates.

Bil2 CCO }
Clock Control/Format Select
Bit 3 CCI
They control the data format and the clock select logic.
Table 7 defmes the bit field.
• Internally Generated Clock
If the user wish to use externally an internal clock of the
serial I/O, the following requirements should be noted.
'CCI, CCO must be set to "10".
• The maximum clock rate must be E/I6.
• The clock rate is equal to the bit rate.
• The values of RE and TE have no effect.
• Externally Generated Clock
If the user wish to supply an external clock to the Serial
I/O, the following requirements should be noted.
• The CCI, CCO must be set to "11" (See Table 7).
• The external clock must be set to 8 times of the desired
baud rate.
• The maximum external clock frequency is E/2 clock.
• Serial Operations
The serial I/O hardware must be initialized by the software
before operation. The sequence will be normally as follows.
• Writing the desired operation control bits of the Rate and
Mode Control Register.
• Writing the desired operation control bits of the TRCS
register.
If Port 2 bit 3, 4 are used for serial I/O, TE, RE bits may be
kept set. When TE, RE bit are cleared during SCI operation,
and subsequently set again, it should be noted that TE, RE
must be kept "0" for at least one bit time of the current baud
rate. If TE, RE are set again within one bit time, there may be
the caSe where the initializing of internal function for transmitter and receiver does not take place correctly.
• Transmit Operation
Data transmission is enabled by the TE bit in the TRCS

266

•

register. When set, the output of the transmit shift register
is connected with Port 2 bit 4 which is unconditionally configured as an output.
After RES, the user should initialize both the RMC register
and the TRCS register for desired operation. Setting the TE bit
causes a transmission of ten-bit preamble of "I "s. Following the
preamble, internal synchronization is established and the transmitter is ready to operate. Then either of the following states
exists.
(1) If the transmit data register is empty (TDRE = 1), the
consecutive "I "s are transmitted indicating an idle
states.
(2) If the data has been loaded into the Transmit Data
Register (TDRE = 0), it is transferred to the output
shift register and data transmission begins.
During the data transfer, the start bit ("0") is first transferred. Next the 8-bit data (beginning at bit 0) and finally the
stop bit ("I "). When the contents of the Transmit Data Register
is transferred to the output shift register, the hardware sets the
TDRE flag bit: If the CPU fails to respond to the flag within
the proper time, TORE is kept set and then a continuous string
of 1's is sent until the data is supplied to the data register.
• Receive Operation
The receive operation is enabled by the RE bit. The serial
input is connected with Port 2 bit 3. The receiver operation
is determined by the contents of the TRCS and RMC register.
The received bit stream is synchronized by the first "0" (statt
bit). During IO-bit time, the data is strobed approximately at
the center of each bit. If the tenth bit is not "1" (stop bit),
the system assumes a framing error and the ORFE is set.
If the tenth bit is "I ", the data is transferred to the receive
data register, and the RDRF flag is set. If the tenth bit of the
next data is received and still RDRF is preserved set, then
ORFE is set indicating that an overrun error has occurred.
After the CPU read of the status register as a response to
RDRF flag or ORFE flag, followed by the CPU read of the
receive data register, RDRF or ORFE will be cleared.
• RAM CONTROL REGISTER
The register assigned to the address $0014 gives a status
information about standby RAM.

s001.1 s~
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used •

HITACHI

RAM ContrOl Regisler
8
5
4
3

IRAMEI

X

0

I I I I I I
x

X

x

x

X

----------------------HD6301Vl.HD63A01Vl.HD63B01Vl
Bit 3 Not used.
Bit 4 Not used.
Bit 5 Not used.
Bit 6 RAM Enable.
Using this control bit, the user can disable the RAM. RAM
Enable bit is set on the positive edge of lffiS and RAM is
enabled. The program can write "I" or "0". If RAME is
cleared, the RAM address becomes external address and the
CPU may read the data from the outside memory.
Bit 7 Standby Bit
This bit can be read or written by the user program. It is
cleared when the Vcc voltage is removed. Normally this bit
is set by the program before going into stand.by mode. When
the CPU recovers from stand-by mode, this bit should be
checked. If it is "I ", the data of the RAM is retained during
stand.by and it is valid.
• GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6301VI has an upward object code compatible with
the HD6801 to utilize all instruction sets of the HMCS6800.
The execution time of the key instruction is reduced to increase
the system through-put. In addition, the bit operation instruction, the exchange instruction between the index and the
accumulator, the sleep instruction are added. This section
describes:
• CPU programming model (See Fig. 23)
• Addressing modes
• Accumulator and memory manipulation instructions (See
Table 8)
• New instructions
• Index register and stack manipulation instructions (See
Table 9)
• Jump and branch instructions (See Table 10)
• Condition code register manipulation instructions (See
Table II)
• Op-code map (See Table 12)
• Cyc1e-by-Cycle Operation (See Table 13)
• CPU Programming Model
The programming model for the HD6301VI is shown in Figure 23. The double accumulator is physically the same as the
accumulator A concatenated with the accumulator D, so that
the contents of A and D is changed with executing operation of
an accumulator O.
~ ____ A____

1J: ____ !!. ____ ~B.Bi.

Accumul.'.r1A .nd B

15

0

R Or l6·Blt Double Accumulator 0

116

X

01 IndeK Aagilt., IX)

116

SP

oIStack Pointer (SP)

116

PC

• CPU Addressing Modes
The HD630 I V I has seven address modes which depend on
both of the instruction type and the code. The address mode for
every instruction is shown along with execution time given in
terms of machine cycles (Table 8 to 12). When the clock
frequency is 4 MHz, the machine cycles will be microseconds.
Accumulator (ACCX) Addressing
Only the accumulator (A or B) is addressed. Either accumulator A or B is specified by one-byte instructions.
Immediate Addressing
In this mode, the operand is stored in the second byte of the
instruction except that the operand in LOS and LOX, etc are
stored in the second and the third byte. These are two or
three-byte instructions.
Direct Addressing
In this mod~, the second byte of instruction indicates the
address where the opel and is stored. Oirect addressing allows
the user to directly address the lowest 256 Bytes in the machine
locations zero through 255. Improved execution times are
achieved by storing data in these locations. For system
configuration, it is recommended that these locations should be
RAM and be utilized preferably for user's data realm. These are
two-byte instructions except the AIM, OIM, ElM and TIM
which have three- byte.
Extended Addressing
In this mode, the second byte indicates the upper 8 bits
addresses where the operand is stored, while the third byte
indicates the lower 8 bits. This is an absolute address in
memory. These are three-byte instructions.
Indexed Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the Index Register. For each of AIM, OIM, ElM
and TIM instructions, the contents of the third byte are added
to the lower 8 bits in the Index Register. In addition, the
resulting "carry" is added to the upper 8 bits in the Index
Register. The result is used for addressing memory. Because the
modified address is held in the Temporary Address Register,
there is no change to the Index Register. These are two-byte
instructions but AIM, OIM, ElM, TIM have three-byte .
Implied Addressing
In this mode, the instruction itself gives the address; stack
pointer, index register, etc. These are I-byte instructions.
Relative Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the program counter. The resulting carry or
borrow is added to the upper 8 bits. This helps the user to
address the data within a range of -126 to +129 bytes of the
current execution instruction. These are two·byte instructions.

oIprog,.." Counter fPC)
7

'

0

~

H I N Z V C Condition Cod. Reglltl' {CCRI
Clrry/Bo,row from MSa

Overflow
ZItO

Negative
Interrupt
Half Carry (From Bit 31

Figure 23 CPU Programming Model

_HITACHI

267

HD6301 V1,HD63A01 V1,HD63B01 V1
Table 8 Accumulator, Memory Manipulation Instructions
Condition Code
Addressing Modes
OperettOnl

Mnemonic

IMMEO
OP

AOOA

8B

A008

C8

Add Doabl.

AOOO

C3

Add Accumulator.

ABA

Add With Cerry

ADCA

Add

AOCB
AND

Bit Te't

ANOA
ANOB
BITA
BIT B

Cle.,

Compare

Com",,.
AccumulMor.

Compliment, 1',

Complernent. 2',

1"-"1

OIRECT

- " OP
2 2 98

-

EXTENO

INOEX

#

OP

-

"

OP

-

#

4

3

A+M+C-A

4

3

B+M+C-B

4

3

A'M-A

4

3

B'M-B

4

3

A·M

4

3

B'M
OO-M

3 2 A5 4 2 B5
3 2 E5 4 2 F5
6F 5 2 7F

5 3
4F
5F

8.1
Cl

2 2 91
2 2 01

3 2 AI
3 .2 El

4 2 81
4 2 Fl

COM
COMA
COM8

63

NEG
NEGA
NEG8

60

DEC

6

2 73

6 2 70

6

40

oo-M-M
1 1 OO-A-A

50

1 1 00-8-8

19

Converts bln.ry add of BCD
2 1 cherlcters ,nto BCD format

iiii-M

4A
5A

exclusive OR

EORA

Increment

INC

2 2 98 3 2 AS 4 2 88 4 3
CB 2 2 DB 3 2 EB 4 2 F8 4 3
6C 6 2 7C 6 3

AGlM-A
8 Gl M- 8
4C

INCB

5C

L_
Accumulator

LOAA
LOA8

86 2 2 96 3 2 A6 4 2 86 4 3
C6 2 2 06 3 2 E6 4 2 F6 4 3

L_Doubl.
Accumulator

LOO

CC

Mull",ly Unltgned

MUL

OR, Inclusive

ORAA
ORAB

P..... O...

PSHA

Pull Dati

PSHB
PULA

3 3

DC 4 2

PULB
ROL

69

6

2 79

88 6 2 76

ROR
RORA

6

36
37

4 1 A .... MSP. SP - , .... SP
4 1 8 - Mil'. SP - 1 - SP

32
33

3

49

1

59

1 1

1 SP+l-SP.MIP-A

3 1 SP+l-SP.MIP-8
1

3

RORB

Note) Condition Code Register will be explained in Note of Table 11.

•

B + M- B

6 3

ROLA
ROLB

HITACHI

46

1 1

56

1

1

~}L:{}'fll

•

Ii.,

IIII 11:1

GO

:}'{li' I II II I HI
•

I

I

I

I

I

I

I

I
I
I

I

R S
R 5

I R S
I (\)1)
I '-I~ '1}
I (f) ').,
I

~)

t

I

I

I (4) •

t

t
t

(4) •
(4) •

R

I

R

@ •

I

@ •

 Zlro
If Htgh.r

Sranch
Sranch
Some
Branch
Branch
Branch
Zero
Branch
Clear
Branch

If " Zero

If Lower Or

OP
8RA
20 3
BRN-- 21 3
"BCC
24 3
Bes
25 3
8EO
27 3

#

DIRECT
OP
#

-

INDEX
DP
#

-

Register

EXTEND
OP
#

-

IMPLIED
OP
#

-

2

< Zero

If Minus
If Not Equal
If Overflow
If Overflow Set

2
2

C =I
Z -I

2E
22
2F

3 2
3 2

C+Z=O

BlE
BLS

23

3 2

C +Z

BLT

20

3 2

2C

N$ v-o
Z + IN $ VI- 0
Z + IN $ VI- I

BMI

2B

3

2

N -I

26

3 2

Z·O

BVe

28

3 2

8VS

29

3 2

v-o
V -I

.. -f--- 1----

2A

3 2

BSR
JMP

80

5

No Operation

NDP

01

JSR

N-O

2
6E 3 2 7E 3 3
90 5 2 AD 5 2 80 6 3
1 1

RT!

38 10 I

RTS

39

SWI

3F 12 I
3E 9 I
lA 4

Advances Prog. Cntr.
Only

5 I

,

WAI

SlP

Note. -WAI puts AtW hIgh; Address Bus goes to FFFF; Oata Bus goes to the three state.
Condition Code Register will be explained in Note of Table 11 .

270

=1

N$V-I

BNE

BPL

~

-f---

•

HITACHI

5 4 3 2 I 0
H I N Z V C

·· ·: -;-· ·: · ·
·· · · · ·· ··
··· ··· ··· ··· ······
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·· ··
·· ·· ·· ·· ·• ··
·· ·· ·· ·..• ·· ··
·· ·· ·· · ·· ··
······
• ·· • ··
·• • ·• ··• ··• ·••

.~

2
3 2
3 2

8GE
BGT
8HI

'finch If Plus
Branch To Subroutin.
Jump
Jump To Subroutine

R.turn From Int.rruptl
R.turn From
Subroutine
Softw." Interrupt
Wait for InterruPt-

None

None
CoO

2

C-._

If

Branch Test

-@-

5

• (j) •

----------------------HD6301V1,HD63A01V1,HD63B01V1
Table 11

Condition Code Register Manipulation Instructions
JAddr... ;ngMode<

OperMtoni

-, ,•

OP

Cln,Clrry

CLC

OC

Cln, Interrupt MII'k

CLI

OE

CI..,Owrflow

CLV

OA

Set Interrupt Ma.1c

Sot Owrflow
Accumulator A -

eeR -

[NOTE 1]

eeR
A

Accumulator

,
,
,
,
,
,

00

SEC

So. Corrv

Condition Cod, Aegls,er
Boolean Opera, Ion

IMPLIED

MnemonIC

SEI

OF

SEV

OB

TAP

06

TPA

07

,
,

2

,

N

Z

V

0
C

A

o-v

A

, -C

S

, -I

S

,-V

5

'0---

A_ CCA

, ,

3

I

A

0-1

,
,

4

H

·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
··- -·-·· ·· · ··

O-C

,
,

5

CCA- A

• 1 •

1•

··

1 •

Condition Code Register Notes: (Bit set if test is true and cleared otherwise)

(1)
@
@
@
@

®
ClJ

@

®

@l

®

IBit VI
IBit CI
IBit C)
(Bit V)

Test:
Test:
Test:
Test:

Result = looooooo?
Result'" 00000000?
BCD Character of high-order byte greater than 9? (Not cleared if previously sed
Operand = 10000000 prior to execution?

{Bit V)
(Bit V)

Test: Operand ""01111111 priortoexecutioni'
Test: Set equal to Nee",,1 after the execution of instructions

(Bit N)
IAII Bit)

Test: Result less than zero? (Bit 15=1)
Load Condition Code Register from Stack.

IBit I)

Set when interrupt occurs. If previously set. a Non-Maskable Interrupt is required to exit the wait
state.

(All Bit)
IBit C)

Set according to the contents of Accumulator A.
Result of Multiplication Bit 7= 1 of ACCB?

[NOTE 2] ell instructions and interrupt.
_ _ __
If interrupt mask-bit is set 11="1") and interrupt is requested (IRQ, = "0" or IRQ, = "0"),.
and then CLI instruction is executed, the CPU responds as follows.
, the next instruction of CLI is one..machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
2 the next instruction of CLI is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
Even if TAP instruction is used, instead of CLI, the same thing occurs.

Table 12 OP-Code Map
OP

ACC

ACC

CODE

A

B

0100
4

0101
5

~/

0000

LO

0000
0001
0010
0011
0100
0101

0
1
2
4
5

0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

6

3

0001

0

I

0010
2

0011
3

SBA

BRA

TSX

NOP

CBA

BAN

INS

/

PULA

BLS

PULB

BCC

DES

ASLD

/
/
/
/

BHI

BCS

TXS

TAP

TAB

BNE

PSHA

L
LSAO

IND

lZ
DIA'

0110 1 0111
7
6

ACCA or SP
IMM

I

DlA

liND

ACCB or X

I

EXT

.000 1 1001 1 1010 1 1011
B
8 ! 9
A

C

---I
1
COM

AIM

CMP

OIM

SBC

LSA

-r

ElM

ASA

PULX

ASL

EOA

DEX

OAA

BVS

ATS

ROL

AOC

A

CLV

SLP

BPL

ABX

DEC

QRA

BMI

ATI
PSHX

0

SEC

MUL

CLI

/
/

BLT

E
F

BGT

WAI

,

SWI

SEI

0

..........
I

BLE

3

STA

TIM

- - - INC
i
TST

I

-.

.......... l
7

8

9

9

I

B
C

STO

0

LOX

STS

I

A

I

B

- 2.- ,..!..
A

.......... -1

LOS

CLA

6

STA

LDD

JSA

BSA 1
JMP

5

2
3
4
5
6

ADD
CPX

.........-1/
4

I

1"""""""-1

PSHB

BGE

0

LOA

/-1

BEQ

ABA

F-

E

BIT

ROA

XGOX BVC

../"

I

ANO

TBA

SEV

0

AODO

TPA

CLC

!

I

SUBD

INX

C

INO TEXT

SUB

7
8
9
B

I

1100 1 1101 1 1110 +.'111

i

I

NEG

---

IMM lOlA

..........l
C I o I

E

STX
E

F

1

F

UNDEFINED OP CODE ~
• Dnlv for instructions of AIM, OIM, ElM, TIM

•

HITACHI

271

HD6301V1,HD63A01V1,HD63B01V1-------~---------------

• Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the
current instruction fetch and just before the start of the subsequent instruction fetch.
The HD6301Vl uses a mechanism of the pipeline control for the instruction· fetch and the subsequent instruction
fetch is performed during the current instruction being exe-

cuted.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction cycles such as MULT, PULL, OAA and XGOX in the HD6301Vl.
Table 13 provides the information about the rell!!jonship
among each data on the Address Bus, Data Bus, and R/W status
in cycIe·by-cycIe basis during the execution of each instruction.

Table 13 Cycle-by-Cycle Operation
Address Mode &
Instructions

IMMEDIATE
ADC
ADD
AND
BIT
EOR
CMP
ORA
LOA
SUB
SBC
ADDD CPX
LDD
LOS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

Address Bus

CPX
LOS
SUBD

STD
STX

STS

1
1

Operand Data
Next Op Code

1
2
3

Op Code Address+ 1
Op Code Address+2
Op Code Address+3

1
1
1

Operand Data (MSB)
Operand Data (LSB)
Next Op Code

1
2
3

Op Code Address+ 1
Address of Operand
Op Code Address+2

1

1

Address of Operand (LSB)
Operand Data
Next Op Code

I
I

3

4

1
2
3
1
12
3

4
4

1
2
3

4
JSR

5

1
2
3

4
5
TIM

4

1
2
3

4
AIM
OIM

ElM

1
2

6

ii

I

3

3
AD DO
LDD
LOX

Op Code Address+ 1
Op Code Address+2

1
2
2

Data Bus

3

4
5
6

Op Code Address+ 1
Destination Address
Op Code Address+2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+l
Destination Address
Destination Address+ 1
Op Code Address+2
Op Code Address+l
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3

1

1

0
1
1
1
1
1
1

0
0
1
1
1

0
0
1
1
1
1
1
1
1
1
1

0
1

Destination Address
Accumulator Data
Next Op Code
Address of Operand (CS"i3r
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
-Continued -

272

•

HITACHI

----------------------HD6301V1.HD63A01V1.HD63B01V1
Table 13 Cycle-by.cycle Operation (Continued)
Address Mode 8<
Instructions

Address Bus

INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA

ADD
BIT
EOR
ORA
SUB

4

4

1
2
3
1
2
3

4

1
2
3

4
ADDD
CPX
LOS
SUBD

LDD
LOX

5

1
2
3

4

5
STD
STX

STS

5

1
2
3

4

5
JSR

5

1
2
3

4

5
ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

6

1
2
3

4

5

TIM

5
CLR

5

6
1
2
3
4
5
1
2
3
4

5
AIM
OIM

ElM

1
2
3

7

4
5
6

7

Data Bus

Op Code Address+ 1
FFFF
Jump Address
Op Code Address + 1
FFFF
IX + Offset
Op Code Address+2

1
1
1
1
1
1
1

Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restar( Address (LSB)
Operand Data
Next Op Code

Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-l
IX + Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 1
Op Code Address + 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address + 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address + 1
Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+3

1
1

Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data

•

HITACHI

0
1
1
1
1
1
1
1
1

0
0
1
1
1
0

0
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1

0

00

1
1
1
1
1
1

Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next {jp Code
- Continued -

0
1

273

HD6301 V1 ,HD63A01 V1 ,HD63B01V1 - - - - - - - - - - - - ' - - - - - - - - - - - Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode 8.
Instructions

Address Bus

EXTEND
JMP

3
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

TST

4

1
2
3
1
2
3

4

!
I
4

1
2
3

4
ADDD
CPX
LOS
SUBD
-

STD
STX

LDD
LOX

I

5

1
2
3

4
5

STS

5

1
2
3

4
5
JSR

6

ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

6

CLR

5

1
2
3

4
5
6
1
2
3

4
5
6
1
2
3

4
5

Data Bus

Op Code Address + 1
Op Code Address+2
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address + 3

1
1
1
1
1
1
1

Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code

Op Code Address+ 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Destination Address
Destination Address+ 1
Op Code Address+3
Op Code Address + 1
Op Code Address+2
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
Op Code Address+3

1
1

Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operend (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)·
First Subroutine Op Code
Address of Operand (MSB)
Address of Operend (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data

0
1
1
1
1
1
1
1
1

0
0
1
1
1
1

0
0
1
1
1
1
1

0
1
1
1
1

0

00

1

Next Op Code

-

- Continued -

274

•

HITACHI

---------------------------------------------HD6301V1,HD63A01V1,HD63B01V1
Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA

ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX

PSHA

Op Code Address + 1

1

Next Op Code

1
2
1
2

Op Code Address + 1

3

Stack Pointer + 1
Op Code Address + 1

1
1
1
1
1
1
1

Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
-Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
- Continued -

1

2

PULB

3
..

1

PSHB

4
PULX

4
PSHX

,

1
2

3
4
1
2

3
4
1
2

5

RTS

3
4
5
1
2

5
MUL

3
4
5
1
2

7

3
4
5

6
7

FFFF

Op Code Address + 1

FFFF
FFFF

Stack Pointer
Op Code Address + 1
Op Code Address + 1

0
1
1
1
1
1
1
1

FFFF
Stack Pointer + 1
Stack Pointer + 2
Op Code Address + 1

FFFF

0
0

Stack Pointer
Stack Pointer-l
Op Code Address + 1
Op Code Address + 1

FFFF

Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address + 1

FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

•

HITACHI

I

1
1
1
1
1
1
1
1
1
1
1
1
1

275

HD6301Vl,HD63A01Vl,HD63B01Vl---------------------Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode 8&
Instructions

Address Bus

IMPLIED
WAI

9

1
2
3
4
5
6

7

8
9
RTI

10

1
2
3
4
5
6
7

8
9
SWI

12

10
1
2
3
4
5
6

7

8
9
10
11
12
1
2

SLP

4

1

Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer +4
Stack Pointer + 5
Stack Pointer + 6
Rl!turn Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF
FFFF

Sleep

I

3
4

FFFF
Op Code Address + 1

Data Bus

I

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1

Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Restart Addrass (LSB)
High Impedance-Non MPX Mode
Address Bus -MPX Mode

1

Restart Addrass (LSB)
Next Op Code
- Continued -

276

•

HITACHI

---------------------------------------------HD6301Vl,HD63A01Vl,HD63B01Vl
Table 13 Cycle·by·Cycie Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

RELATIVE

..

BCC
BEQ
BGT
BlE
BlT
BNE
BRA
BVC
BSR

BCS
BGE
BHI
BlS
BMT
BPl
BRN
BVS

1
3

I

2
3

I

Op Code Address+ 1
FFFF
"..
Branch Address······Test= 1
Op Code Address+ 1···Test="O·

1

i

I

J

1

2

5

3

4
5

I Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Branch Address

• LOW POWER CONSUMPTION MODE
The HD6301 VI has two low power consumption modes; sleep
and standby mode.

1
1

Branch Offset
Restart Address (lSB)
First Op Code of Branch Routine
Next Op Code

1

._-- -----".

1
1

0
0
1

I

1

Offset
Restart Address (lSB)
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine

CPU.
This sleep mode is available to reduce an average power
consumption in the applications of the HD630lVI which may
not be always running .

• SleepMocle

On execution of SLP instruction, the MCU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of
a normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The RES resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the

• Standby Mode

Bringing STBY "Low", the CPU becomes reset and all
clocks of the HD6301VI become inactive. It goes into the
standby mode. This mode remarkably reduces the power con·
sumptions of the HD6301VI.
In the standby mode, if the HD630IVI is continuously
supplied with power, the contents of RAM is retained. The
standby mode should escape by the reset start. The following
is the typical application of this mode.
First, NMI routine stacks the MCU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the Standby bit, and then goes into the standby
mode. If the Standby bit keeps set on reset start, it means
that the power has been kept during standby mode and the
contents of RAM is normally guaranteed. The system recovery
may be possible by returning SP and bringing into the condition
before the standby mode has started. The timing relation for
each line in this application is shown in Figure 24.

Vo<

~------~III~---4r-

HD6301Vl

----I,r--rr

!--I

I

I

I

I->t

I

.
I

~

:/Stack registers

Oscillator I

... RAM control
reg.ster set

stabilizing

time

~

restart

Figure 24 Standby Mode Timing

•

HITACHI

277

HD6301Vl,HD63A01Vl,HD63B01Vl---------------------• ERROR PROCESSING
When the H06301 VI fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due 10 noise or a program error.

Table 14 Address Error
Mod.

2,4
1
7
0
5
6
S_ S_ S_ S_ S_ S_
I

Addr ... SGOIF

• Op-Code Error

Fetching an undefined op-code, the H0630lVI will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP (SFFEE. SFFEF). that has a second highest priority
(RES is the highest).

• Add ..... Error

I

I

I

I

I

I

SEFFF

SEFFF

System Flow chart ofHD6301VI is shown in Fig. 25.

When an instruction is fetched from other than a resident
ROM, RAM, or an external memory area, the CPU starts the
same interrupt as op-code error. In the case which the instruction is fetched from external memory area and that area is not
usable, the address error cannot be detected.
The addresses which cause address error in particular mode
are shown in Table 14.
This feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.

278

I

SGOIF SGOIF SG07F SGOIF SGOff
S0200
SOIOO

Transitions among the active mode, sleep mode, standby
mode and reset are shown in Fig. 26.
Figures 27, 28, 29 and 30 shows a system configuration.

_HITACHI

----------------------HD6301Vl,HD63A01Vl,HD63B01Vl

A

VECT RI
FF .

PCL·~

MSP

PCH. Msp·,

IXL .• MSP·2
IXH • MSp·3
ACCA • MSP-4

Acea .MSP·5

CCR .• MSP-6

Figure 25 HD6301Vl Systsm Flow Chart

•

HITACHI

279

HD6301Vl,HD63A01Vl,HD63B01Vl----------------------

Figure 26 Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset

vee

Vee

c:::J

Enable

Enable

NMI

NMi

IRQ.

imi,

Por13

8 Transfe'
Lines

RES
Port 1

Port 1

8110
lu'les

81/0 Lines

Pori 4
81/0 LIMS

Port 2

Por,2

5110 Lines

51/0 LIMS
SCI

SCI
16 Bit Time'

Port 4

81/0 LIne,

vss

VSS

Figure 27 HD6301Vl MCU Single-Chip Dual Processor Configuration

280

•

HITACHI

-----------------------------------------------HD6301V1,HD63A01V1,HD63B01V1

HD6301Vl

MCU

Addre5S

Bu,

Data
Bu,

Address Bus

Figure 28 HD6301V1 MCU Expanded Non-Multiplexed Mode
(Mode 51

Figure 29

Data Bus

HD6301V1 MCU Expanded Multiplexed Mode

HD6301Vl MCU

16

Address Bus

Data Bus

Figure 30 HD6301V1 MCU Expanded Non-Multiplexed Mode (Mode

~HITACHI

11

281

HD6301V1,HD63A01V1,HD63B01V1---------------------------------------------• Standby State

• PRECAUTION TO THE BOARD DESIGN OF OSCILLA·
TION CIRCUIT

Only power supply pins and STBY pin are active. As for the
clock pin EXTAL, its input is fixed internally so the MCU is
not influenced by the pin conditions. XTAL is in "I" output.
All the other pins are in high impedance.

As shown in Fig. 31, there is a case that the cross talk dis·
turbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD630lVI as
possible.

• DIFFERENCE BETWEEN HD6301VO and HD6301Vl

The HD630lVI is an upgraded version of the HD630IVO.
The difference between HD630lVO and HD630lVI is shown
in Table 17.
Table 17 Difference between HD6301 VO and HD6301V1

XTAL
Item

EXTAL

Operating
Mode

HD6301V1

HD6301V1
Mode 2: Expanded
Multiplexed Mode
(Equivalent to Mode 4)

Mode 2: Not defined

The electrical character·
Electrical
istics of 2MHz version
Character·
(B version) are not speci·
istics
fied.

Do not use this kind of print board design.
Figure 31

HD6301VO

Precaution to the boad design of
oscillation circuit

Timer

Has problem in output
compare function.
(Can be avoided by soft·
ware.)

Some characteristics
are improved.
The 2MHz version is
guaranteed.
The problem is solved.

• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State

The conditions of power supply pins, clock pins, input pins
and E clock pin are the same as those of operation. Refer to
Table 15 for the other pin conditions.

Table 15 Pin Condition in Sleep Mode
-------- ____ Mode
Pin
- _____
Port 1
PIO- PI7

Function

1/0 Port
Keep the condition

Lower Address Bus

1/0 Port

Keep the condition

+-

+-

+-

+-

+-

+-

+-

Condition

Keep the condition I
just before sleep

+-

+-

+-

+-

+-

Function

just before sleep

Bus
E: Data Bus

E: Lower Address
Bus

Data Bus

Data Bus

E: Lower Address
Bus
E: Data Bus

High Impedance

Keep the condition
E: Output "1"
E: High Impedance just before sleep
Upper Address Bus
or Input Port

E: Data Bus

E: Output "1"

1/0 Port

Condition

E: Output "1"
E: High Impedance

Function

Upper Address

+-

-

Lower Address Bus
or I nput Port

Condition

Output "1"

+-

+-

Address Bus: Out·
put "1"
Port: Keep the condition just before
sleep

+-

Keep the condition
just before sleep

SC2

Output "1"
(Read Condition)

+-

+-

+-

+-

Output "1"

SCI

Output Addre ..
Strobe

+-

+-

----

282

7
+-

+-

PJO-Pj.1

Port 4
P40 -P47

6
+-

1/0 Port

just before sleep

Output "1"

E: Lower Address
Port 3

5
+-

2,4

1

I

Function

Condition

Port 2

PlO -P24

0

High Impedance

E: High Impedance

•

HITACHI

Output "1"

Output Address
Strobe

1/0 Port

Input Pin

- - - - - - - - - - - - - - - - - - - - - - - HD6301 V1,HD63A01 V1,HD63B01 V1
Table 16

~e
pin
Port 1
PIO - PI7
Port 2
P20 - P24
Port 3
P30 - P37
Port 4
P40 - P47
SC2
(R!W)
SCI
(AS)

Pin Condition during RESET

0,2,4,6

high impedance (input)

high impedance (i nput)
E: "1" output
E: high impedance

1

..

high impedance

high impedance (input)

..

"1" output (Read)

..

1:: "1"output

.

E: "0" output

5

..
..

..

..

..

..
..

..

..

"1" output

"1" output

•

HITACHI

7

high impedance (input)

283

HD6301 XO ,HD63A01 XO , - - HD63B01XO
CMOS M.CU (Microcomputer Unit)
-PRELIMINARYThe HD630IXO is a CMOS single-chip microcomputer unit
(MCV) which includes iI CPU compatible with the HD630lVI,
4k bytes of ROM, 192 bytes of RAM, 53 parallel I/O pins, a
Serial Communication Interface (SCI) and two timers on chip.

HD6301XOP, HD63A01XOP,
HD63B01XOP

• FEATURES
•
•

•
•

•

•

Instruction Set Compatible with the HD6301Vl
Abundant On-chip Functions
4k Bytes of ROM, 192 Bytes of RAM
53 Parallel I/O Ports
16·Bit Programmable Timer
8-Bit Reloadable Timer
Serial Communication Interface
Memorv Readv
Halt
Error-Detection (Address Trap, Op Code Trap)
Interrupts .•. 3 External, 7 Internal
Operation Mode
Mode 1 _ .. Expanded (Internal ROM Inhibited)
Mode 2 ••. Expanded (Internal ROM Valid)
Mode 3 •.. Single-chip Mode
Low Power Dissipation Mode
Sleep
Standby
Wide Range of Operation
Vee = 3 - 6V (f = 0.1 - 0.5MHz).
Vee = 5V±10%(f = 0.5 -1.0MHz; HD6301XO )
f = 0.5 - 1.5MHz; HD63AOl XO
f = 0.5 - 2.0MHz; HD63B01XO

284

(DP-64S)
HD6301XOF, HD63A01XOF,
HD63B01XOF

(FP-60)

_HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
• PIN ARRANGEMENT
•

HD6301XOP, HD63A01XOP, HD63B01XOP

v"

XTAL
EXTAL

MP.
MP,

liES
STBV

,

l :. l

;

""',

I P72

P"
P,.
P,.
P"
P"
P"
P,.

•
7

PZo •
I

Pn

P"

P"
Pn

, P37

NO'

56P ..

P"

P"

p,.

P"
p..

POI
P"
P"

~:~I
p,. '

P"

PI'
P"
flO

p..

P"

p..

V..

P"
P",
POI

P"
P"

..

p..

.,
"'"

P"
Po.
P"
P"
P"

P"
P"

p..
P"
P"
P"

HD6301XOF, HD63A01XOF, HD63B01XOF

p,.
P"

Niii
P"
Pn

•

0

I

Vee

(Top View)

(Top View)

• BLOCK DIAGRAM
N

I
I

j
I I

P.(Tin)

p"ITOUIlI-----1+_i

r"""",-LLl'-'-_"""

PI~SCLKI--_..!+_i

P,.JWlI

PnlHIl!

Pu/A/W

'.iOIi
'-----'""---,,.,.,IIA

.",,~

• ...,.....,--fl.+H+_i

PaCTouI31-;ntmtl
PuITCLKI-

.-,
'1,1IIRJd
P,ICMft)

......
......
...
......
.........
..,

...1In'IJ

p..

•

HITACHI

285

HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage

Symbol

Value
-0.3-+7.0

Vee
V ln

Operating Temperature
Storage Temperature

Unit
V
V
·C
·C

-0.3 - Vee+0.3
0-+70
-55-+150

Topr
Tstg

(NOTE I This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply ovarvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation. we recommend Vin. V out : VSS ~ (Vin or V out) ~ Vee.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee = 5.0V±10%, Vss
Item

=OV, Ta· 0-+70·C, unless otherwise noted.'
Symbol

Test Condition

RES,STBY
Input "High" Voltage

EXTAL
Other Inputs

V 1H

Input "Low" Voltage

All Inputs
NMI, RES, STBY,
MP o , MP 1 , Port 5

V IL
IIlnl

V ln = 0.5-V ee -0.5V

Ports 1,2,3,4,6,7

IITSd

Vln =0.5-V ee -0.5V

Input Leakage Current
Three State (off ·state'
Le3kage Current

All Outputs

V OH

Output "Low" Voltage

All Outputs

VOL

10H =-200IlA
10H - -101lA
10L = 1.6mA

Darlington Drive
Current

Ports 2, 6

-loH

Vout = 1.5V

Input Capacitance

All Inputs

C in

V in =OV, f
Ta =25·C

Standby Current

Non Operation

ISTB

Output "High" Voltage

ISLP

Sleeping (f = 1 MHz* *'
Sleeping (f = 1.5MHz**'
Sleeping (f = 2MHz**'

Icc

Operating (f = lMHz**'
Operating (f = 1.5MHz**'
Operating (f =2MHz**'

Current Dissipation *

RAM Standby Voltage

= lMHz,

V RAM

min

typ

Vee-0.5

-

Vee xO.7
2.0
-0.3

max

Unit

-

Vee
+0.3

V

-

0.8

V

-

1.0

IlA

1.0

IlA

-

-

0.4

V
V

1.0

-

10.0

mA

2.4
Vee-0 .7

2.0

'VIH min· Vee-1.0V, VIL max· O.BV (All output terminals are at no 10ad.1
··Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.

values about Current Dissipations at X MHz oparation are decidad according to the following formula;
typo value (f = X MHz) = typo value (f = 1MHz) x X
max. value (f = x MHz) = max. value (f· 1MHz) x x
(both the sleeping and operatingl

286

_HITACHI

-

V

-

12.5

pF

3.0

15.0

1.5
2.3

3.0
4.5

3.0
7.0
10.5
14.0

6.0
10.0
15.0

IlA
mA'
mA
mA
mA

20.0

-

mA
mA
V

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
•

AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70'C, unless otherwise noted.)

BUS TIMING
Symbol

Item
Cycle Time

Test
Condition

tcve
tE,

HD6301XO
min

typ

HD63A01XO

max

min
0.666

-

10

0.5

-

10

-

25

-

25

25

-

-

25

ns

-

220
220

-

ns

120

ns

-

70

-

ns

-

35

-

ns

40

-

160

160

-

-

ns

-

-

ns

-

0

-

-

220

-

40

ns

25

ns

120

ns

-

ns

Enable Pulse Width "Low" Level·

PWEL
tAD

-

toow

-

-

200

tOSR

80

-

70

Address, R/WHold Time·
Write*
Data Hold Time
I Read
RD, WR Pulse Width·

tAH

-

-

50

-

50
0

-

300

40

-

30

-

200

-

-

10

450

80

tHW

80

tHR
PW RW

0
450

RD, WR Delay Time

tRWO

RD, WR Hold Time

tHRW

-

OR Delay Time

tOLR

-

mHoldTime

tHLR

10

MR Set-up Time·

tSMR

400

MR Hold Time·

tHMR

E Clock Pulse Width at MR

PWEMR

Processor Control Set-up Time

tpcs

Processor' Control Rise Time

tpc,

Processor Control Fall Ti me

tPCf

BA Delay Time

taA

Fig. 3

-

Oscillator Stabilization Time

tRC

Fig. 11

20

Reset Pulse Width

PWRST

-

Fig_ 2
Fig. 3,
10 11

200

Fig. 2, 3

Unit

10

450

I

max

25

tEf
PW EH

Fig. 1

typ

-

Enable Pulse Width "High" Level*

I
I

min

1

Address, R/WDelay Time·
Data Delay Time
Write
Data Set-up Time
Read

Enable Fall Time

HD63B01XO

max

-

-

Enable Rise Time

typ

3

25

-

-

-

300

-

300

250

-

-

-

280

9

-

-

200

100

-

100

-

250

90

-

190

-

40
30
160

-

10
230

-

9

-

-

-

200

100

-

-

190

-

20

-

-

20

3

-

-

-

3

-

40

100

/.IS
ns

ns

ns
ns

ns

0

ns

9

/.IS

-

ns

100

ns

100

ns

160

ns

-

ms
t eve

• These timings change in approximate proportion to tcyco The figures in this characteristics represent those when tcyc is
minimum (= in the highest speed operation),

PERIPHERAL PORT TIMING
Item

Symbol

HD6301XO

HD63A01XO

min

typ

max

min

typ

max

min
200

Peripheral Data
Set·upTime

Ports 2, 3, 5, 6

tposu

Fig. 5

200

-

-

200

-

Peripheral Data
Hold Time

i'orts 2, 3, 5, 6

tpOH

Fig. 5

200

-

-

200

-

-

2
Ports 1'7 ' tpwo
3,4,6,

Fig. 6

-

-

300

-

-

300

Delay Time (Enable
Negative Transition to
Peripheral Data Valid)

I

HD63B01XO
typ
max

Test
Condition

_HITACHI

Unit

-

ns

200

-

-

ns

-

-

300

ns

287

HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------TIMER , SCI TIMING
Item
Timer 1 Input Pulse Width
Delay Time (Enable Positive
Transition to Timer Output)
SCI Input
Clock Cycle

I Async. Mode
1 Ciock Sync.

HD6301XO
typ
max

Symbol

Test
Condition

min

tpwT

Fig.B

2.0

tTOD

Fig. 7

-

Fig. B

1.0

Fig. 4, B

2.0

tScyC

-

-

2.0

400

-"

400

-

-

-

1.0

200

-

-

290

-

100

-

0.6

0.4

-

-

2.0

2.0

200

-

290

-

290

-

100

0.6

0.4

-

2.0

-

200

-

SCI Receive Data Hold Time
(Clock Sync. Mode)

tHRX

100

-

100
100

SCI Input Clock Pulse Width

tPWSCK

0.4

Timer 2 Input Clock Cycle

ttcyC

2.0

Timer 2 Input Clock Pulse
Width

tpwTCK

200

Timer 1-2, SCI Input Clock
Rise Time

tCKr

-

-

Timer 1-2, SCI Input Clock
Fall Time

tCKf

-

-

_HITACHI

-

1.0
2.0

-

-

-

-

-

tSRX

288

min

2.0

tTxD

Fig. B

max

-

SCI Receive Data Set·up
Time (Clock Sync. Mode)

HD63B01XO
typ
max

typ

-

SCI Transmit Data Delay
Time (Clock Sync. Mode)

Fig. 4

HD63A01XO
min

100
100

200

-

Unit
tcyc

-

400

ns

-

toyc
tcyC

-

200

ns

-

ns

0.6

tSCYC

100

ns

-

100

ns

-

ns

tCYC

ns

---------------------HD6301XO,HD63A01XO,HD63B01XO

E

\4V

Ie,.

I
PW"

~O.BV

)<

R;W

/
J

PW'H

\

-

lEI

~ r--I"

t--lAo-

Ao-A, ••

\

I.H--

K

2.4V
O.BV

~ IHAW
IRWO

PWAW

~

V

IC2 .4V

O.BV

I--IoowMCUWrite

~

00-0,

I--IHW-

2.4V

'!! O.BV

I--ID"R-

t-- IHR

~IC2.0V

MCU Read

00-0,

t--

~ k.

O.BV

"
j£

O.BV
t--IDLR-

r-

IHLR

V-

Figure 1 Mode 1, Mode 2 Bus Timing

t------PW'MRI-----~

E

\
\

\

'-----

O.SV

MR

Figure 2 Memory Ready and E Clock Timing

_HITACHI

289

HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Last Instruction

I nstruction Execution

Execution Cycle

Cycle

HALT Cycle

I
E

BA

Figure 3 HALT and BA Timing

Synchronous Clock

Transmit Data

Receive Data

• 2.0V is high level when clock input.
2.4V is high level when clock output.

Figure 4 SCI Clocked Synchronous Timing

I
E

MCUWrite

--"""

P,O-P17, P20-P27------~h~:-:--­
P30- P37, P40- P47
Pao-Pa7, P70-P'4------- 1'0".....: . - - (Outputs)

Figure 5 Port Data Set-up and Hold Times

290

(MCU Read)

$

Figure 6 Port Data Delay Times

HITACHI

(MCU Write'

---------------------HD6301XO,HD63A01XO,HD63B01XO

E

Timer 1 ----,..."!'I!i=:;;:~,,---­
FRC
P21 , Pu ------..:....;;.:.:;; .n~..--­

Outputs------_....J F=I......--

(al Timer 1 Output Timing

(bl Timer 2 Output Timing
Figure 7 Timer Output Timing

m
Vee

RL =2.2kQ

Test Point

C

• Timer 2; ttcye
SCI
; tSeye

R

15207418
or Equiv.

C = 90pF for Port 1, Port 3. Port 4. E
=30pF for Port 2, Port 6. Port 7
R= 12kQ for Port 1 - Port 4, Port 6, Port 7, E

•• Timer 1; tPWT

Timer 2; tPWTCK
SCI
;tPWSCK

Figure 9 Bus Timing Test Loads (TTL Loadl

Figure 8 Timer 1·2, SCI Input Clock Timing

Interrupt
Te..

Inter"" . . ___
~

~~~_...J~_~_~_~'_

__

~_~~~~_~_~~~'_

__

~_~

__

-J~

__A-

~.~

-

Inter"'l

1~9-

,
________

1~'5

ACCA

ACCB

eeR

Vector Vector First Inst. of
MSB
LSB
Interrupt Routine

....J/~------------------~\~

___________

Figure 10 Interrupt Sequence

•

HITACHI

291

HD6301XO,HD63A01XO,HD63B01XO---------------------------------------------

A--~~---.c-----I

~ ~CC"().5V

-.cs

m~~I----------~

a::~'M·_.\\\\\\\\\·\c:X:X::X=x::X:X::x::x::::::x:=:r~~
'~FF
FFFF

FFFF fFFF FFFF

FFFF FFFE

FFFF NewPC

FFFF FFFF

I>--y----,

'~~~f-----------

~..", .'n'\\\\\\\\\\\\\\\\\\~

:~l------frl-'---------

Rmlll:.IMiIlIlI+r'--;~--------------~:~~~f-------

------

"" _~\\lM\\".\.

'--VVV~j-I""""'il"'"

_:\\\\\\\\I\I\\\I\~\\\\\\.

11:TD->~I"'"

WR

----

g~JII£')~WMmmi!.lil'liMlimiMitl!~----------~()-{)-1:}~~~'---------Itll
PC8- PCO- First
pelS pe7

Instruction

Figure 11 Reset Timing

• FUNCTIONAL PIN DESCRIPTION

• Vee. Vss
Vee and Vss provide power to the MCUwith 5V±10% sup·
ply. In the case of low speed operation (fmax = 500kHz), the
MCU can operate with three through six volts. Two Vss pins
should be tied to ground.
• XTAL.EXTAL
These two pins interface with an AT-cut parallel resonant
crystal. Divide-by-four circuit is on chip, so if 4MHz crystal
oscillator is used, the system cIock is IMHz for example.
EXTAL pin is drivable with the external clock of 45 to
50% duty, and one fourth frequency of the external clock
is produced in the LSI. The external clock frequency should
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max

CLl =CL2

= 10pF-22pF±20%
(3.2-SMHz)

EXTAL~--""-'

Jr

CL2

t

Ll

(a) Crystal Interface
XTAL!-- N.C.
EXTAL!---tions are applicable only for the
expanded mode.
• R8ad/Write (R/W; P n )

This signal, usually be in read state ("High"), shows whether
the MCU is in read ("li16h") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load
and 30pF capacitance.
• RD. WR (P 70 • P7.)
These signals show active low outputs when the CPU is
reading/writing to the peripherals or memories. This enables
the CPU easy to access the peripheral LSI with RD and WR
input pins. These pins can drive one TTL load and 30pF capacitance.
• Load Instruction Register (lIR; P 73 )

This . signal shows the instruction opecode being on data
bus (active low). This pin can drive one TTL load and 30pF
capacitance.
•

Memory Ready (MR; P52 )

This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. During
this signal being in "High", the system clock operates in normal
sequence. But this signal in "Low", the "High" period of the
system clock will be stretched depending on its "Low" level
duration in integral multiples of the cycle time. This allows the

294

•

CPU to interface with low-speed memories (See Fig. 2). Up to
9/ls can be stretched.
During internal address space ---f-- ~-M

43

LoodOouble
Accumulator

Push Oltl

4_~ ~~ 00- A
5F 1 1 00 ~ B

3

2 2 96 3 2 A6 4 2 8!! 4 3
2 2 06 3 2 E6 4 2 F6 4 3

OA, Inclusive

B'M
OO-M

~3

INCB
Lood

8'M-~B

A'M

3
5 3

6

a

.I\'M-A

~~ ~..!... ~3

INCA

Accumu'-tor

B+M+C .....

4

f---

A:B+M:Mt1 .... A:B
A +S· .... A
A+M+C-A

11
63

Oecrement

1

3

CBA
COM
COMA
COMB

Complement. ,',

1

2 A5 4 2 85 4 3

CLA

CMPA

B+M-B
lB

I N Z V C

1
1

A +M ..... A

2 F9 4 3

4

H

#

3

4
4

CLAB
Compare

DP-

3

CLAA

Comper.
Accumulators

IMPLIED

2 2 98 3 2 AB 4+~ 8B 4 3

A.gllter
6 4 3 2 1 0

8oole.n!
Arithmtdc Ope"tlon

••

:•P.'f?1'II' I II Ii iiir~ •• ••
••

I 1
1 I
If
IT
I I
I I

(tl I
(tl I

(J)IT
(J)iT
@I
(tll

(continued)

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Table 13 Accumulator, Memory Manipulation Instructions
Addressing Modes

()perations

Mnemonic

IMMED
OP

Shift Left
Arithmetic

-

DIRECT

# OP -

INDEX

# OP

ASL

68

-

EXTEND

# OP

6 2 78

-

# OP

-

1 1

48

ASL8

58

1 1

Left. Arithmetic

ASLD

05

1 1

Shift Righ.
Arithmetic

ASR

Double Shif.

Shif.Rith.
LOIIlcol

Double Shift
Right Logic.1
Store
Accumulator

Store Double
Accumulator

67

6

2

77

6

3

ASRA

47

1

ASRB

57

1

LSR

64

6

2

74

6

3

[J4i ! I ! I I I I

8

C

£ttl
8

b7

2

B1

4

3

B

b7

'7

AD

07 3

2 E7

4

2

f7

4

3

B~M

DO 4

2

ED 5

2

fD 5

3

8 _ M+1

3 2

AO 4

2

3

A-M~A

2

BO
fO

4

EO

4

3

B

2

2 90

2

2

Double Subtract

SUBD

83

3 3 93 4 2 A3 5 2 B3 5 3

Subtract

Accumulators
Subtract
With Carry

SBA

Trens'"

Accumulators

TAB
TBA

Tilt Zero or

TST

DO 3

2

4

82

SBCB

C2

2

2 92
2 2 02

3 2
3 2

A2

4 2

B2
2 f2

E2

4

2

-M~B

A-M-C-A
B-M-C~B

1 1
1 1

A~

B

B~A

M-OO

3
40

TSTA
TSTB

C

1 1 A-B-A

4 3
4 3

70 4

f.o[]
80

A:B-M:M+l~A:B

16
.7
60 4

.,

A~M

'0

SBCA

bO

A~M

STAB.

CO

-

Ace AI ACC 8

STD

80

C

Ao+illllll'~

04
4

bO

_

1 1 o-+i

2 A7

AiACC
8
I+- 0
AO B7
so

• ~ll;' I 1!Iii I f.o

• Mj

1 1

3

t+O

bO

ACC

1 1

97

b7

A7

44

SUBB

Minus

A

54

SUBA

Subtract

_

LSRB

STAA

50

Condition Code
Regist.r
4 3 2 I 0

H

Mj

LSRA

LSRD

5

#

6 3

ASLA

Boolean'
Arithmetic Operation

IMPLIED

1 1 A -00
1 1 B - 00

And Immediate

AIM

71

6

3

61

7

3

M·IMM-M

OR Immediate

OIM

72

6

3 62

7

3

M+IMM_M

EOR Immedi.'.

ElM

75

M(fJIMM-M

Test Immediate

TIM

6 3 65 7 3
7B 4 3 6B 5 3

M·IMM

I N Z V C

··· ···
·· ··
•·
•
·· ··•
·• ·
·· ··•
•·
·· ··
·· ··
·· ··
··• ··
··• ···•
••
••
••

I
I
I

I @I
I @I
I 6 I

~I

I

I

I
I
I
R
R
R

I
I
I 6 I
I 6 I
I
I
I @I
I @I

R

I~

I
I

I R
I R

I

I R

I
I
I

I
I
I

I I
I I
I I

I

I

I

I

I I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I I

I
I

I
I

R
R

I

•

··
··

R R
R R
R R
R
R
R
R

•
•
•
•

(Note) Condition Code Register will be explained in Note of Table 16.

• Additional Instruction
In addition to the HD6801 instruction set, the HD6301XO
prepares the following new instructions.
AIM • . . . . . . (M)' (IMM) -+ (M)
Executes "AND" operation to immediate data and the
memory contents and stores its result in the memory.
OIM . . . . • . . (M) + (IMM)

-+

TIM . . . . . . . (M). (IMM)
Executes "AND" operation to immediate data and
changes the relative flag of the condition code register.
These area 3-byte instructions; the first byte is op code, the
second immediate data and the third address modifier.
XGDX •.... (ACCD) <-+ (IX)

(M)

Exchanges the contents of accumulator and the index
register.

Executes "OR" operation to immediate data and the
memory contents and stores its result in the memory.
ElM • • • . . . • (M) ~ (IMM) -+ (M)
Executes "EOR" operation to immediate data and the
memory contents and stores its result in the memory .

•

SLP
Goes to the sleep mode. Refer to "LOW POWER DIS·
SIPATION MODE" for more details of the sleep mode.

HITACHI

311

HD6301XO,HD63A01XO,HD63B01XO--------------------Table 14 Index Register, Stack Manipulation Instructions
Add,es.ino Modes
POinter Operation.

Mnemonic
CPX
DEX

Co....,.,. Inde. All

Decrement Ind.x Reg
Decrement S1ack Pnt,
Increment Index RII
'ncrem,n, Stick Pn~_
Lood Ind.. A~_
Lood Stack Pntr
Store Inde. Reg
Sior. Stick Pntr
Indlx Reg ... Stack Pnt,

DES

-

-

-

---

I- -

INS

~t~~3~
STX

--STS

'
TXS - - - - - -

--

f--

-

- l - f--

- --

-------

PSHX

-19~

3
3
3
_3

j--f---

---

-

Oe
31

'42

EE 5 2 FE 5
~ 2 AE 5 2 BE 5
~-t~~
DF 4 2 EF 5 2 FF 5
1-I-~ ~ AF ~ 2_ BF ~~

3 DE

f-------- e-- - - --- -

-Push
-Oa.a
----- -

Exc:hange

-

" '''--- ~ ,...- ---

Slack Pn.r'" Index Rei ~SX
Add
-:.:"
ABX

""" Do••

Arithmetic Operation
DIAECT
INDEX
EXTEND IMPLIED
IMMED.
OP
/I OP
/I DP
/I OP
/I OP
/I
8C 3 3 9C 4 2 AC 5 2 ac 5 3
X-M:M+l
09 1 1 X-I-X
34
1 SP-l-SP

-

Condition Cod.
Alii...,

Soolllni

--f--

PULX

X + 1- X

1 1 SP.1-SP
M- XH. (M+1)- XL
M- SPH. IM+ll-SPL

XH - M. XL - 1M + 11
SPH - M. SPL - 1M +11
35 1 1 X-l-SP
30 1 1 $P+1-X
3A 1 1 B +X- X
3C 5 1 XL - Mil" SP - 1 ... SP
XH- MtP • SP -1 ... SP
38 4 1 SP+1-SP,MtP -XH
SP+l- SP. Mw.- XL
18

XGDX

+.,

2

1 ACeO··IX

5 4 3 2 1 0
H

I N Z V C

•
•
•
•
•
•
•
•
•
•
•
•

• : I :
•• I •
••••
• I •
• •

I

•
•
•

·· · · ·••
•
·· ·· ·• ·• ··••
· ·· ·• ·•• ·· ••
·
• •• •
 Zero
Br.nch If Higher
Branch If < Zero
Srench If Lower Or

Mnemonic

BRA
BRN
BCe
BCS
aEa
BGE
aGT
BHI
BLE

AELATIVE
OP 20 3
21 3
24 3
25 3
27 3

/I OP -

22
2F

3 2

2E

INDEX

/I OP -

Register

-

EXTEND

/I OP -

Branch Test

IMPLIED
/I OP
/I

2

2
2
2
2
3 2
3 2
3 2
3 2

2C

DIAECT

None
None

CoO
C-l
Z-1
N V-O
Z + IN  VI - 0
C+Z'O
Z + IN  VI - 1
C+Z-l

Some

BLS

23

Bronell If < Zero

aranch If Minul

BLT
aMI

2D 3 2
2B 3 2

N  V-I
N-l

aranch If No. EquII
Ziro
Bronell If O..rflow
CIN,

BNE

26

3 2

ZoO

BVC

28

3 2

V-O

BVS
BPL

28 3 2
2A 3 2
8D 5 2

V-I
N-O

aranch If Overflow Set
Branch If PlUI
Bl'llnch To Subroutine
Jump

BSA
JMP

Jump To Subroutlnt

JSA

No Optro.lon

NOP

Retu,n From InterruPt
Retum From
Subroutine
Softwlre Interrupt
Welt for Interrupt-

ATI

3B 10

ATS~

39

SWI
WAI
SLP

3F 12 1
3E 9 1
lA 4 1

-

· • ·• ·· · ·
· ·• · ·· ·· ··
·• · ··• ··• · ···
·• · ·· · ·
· ·• · · •• ·
·• ·· ·
• ·• • • ·
·• · • ··•
· ·• • • ··• ·•
•••••
• • ·•
•
·
·
• •••••
0

0

8E 3 2 7E 3 3
9D 5 2 AD 5 2 BD 6 3
01

,

0

0

,

AdY8ncel, Prot. Cntr.

Only

5 1

_HITACHI

0

0

0

0

0

0

0

0

0

0
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

(Notel • WAI puts R/W high; Addr... Bus goes to FFFF; Oatl BUI goes to the three stete.
Condition Codl Register will be explained in Note of Table Ie.

312

5 4 3 2 1 0
H I N Z V e

0

0

-00-

0

0

0

S

0

00·

0

0

0

0

- - - - - - - - - - - - - - - - - - - - - HD6301 XO,HD63A01 XO,HD63B01 XO
Table 16 Condition Code Register Manipulation Instructions
jAddreuingMode

Oper.tfonl

Mnemonk:

Clee,C"ry
Clnt Intlrrupt

IMPLIEO
OP
#
OC
1
1
OE
1
OA
1
00
1
OF
1
OB
1
06
07
1

,

CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA

~tk

Cln, Overflow
Set CIIrty
SIt Int.rrupt M..k
Set Ovarflow
Accumul.tor A - etR
Accumulator A

eeR -

0-1

,

A~ CCR
CCR-A

N

Z

V

C
R

R

R

'~C

S

S

'~I

, ,

I

-- - -- -- -- -- -- -- -- - -- - -- -- - --

O~V

S
@--

'~V

LEGEND
OP Operation Code (Hexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus
Arithmetic Minus
•
Boolean AND
+ Boolean Inclusive OR
III
Boolean Exclusive OR
M Complement of M
..... Transfer into
OBit = Zero
00 Byte = Zero
(Note)

5
H

O~C

,
,
,
,

,

Condition Cod. Regilt.'
4
3
2
0

Booleln Operation

-1-1-1-'-'-

CONDITION CODE SYMBOLS
H
Half ....rry from bit 3 to bit 4
I
Interrupt mesk
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow, 2's complement
Carry/Borrow from/to bit 7
C
R
Reset Always
S
Set Always
l Set if true after test or clear
Not Affected
•

Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
(Bit V)
Test: Result = l0000000?
(Bit C)
Test: Result l; OOOOOOOO?


W

o

~

X

!J
r

o

0>

w

»

o

~

X

!J
r

o

0>

W
to

~
en

Figure 27 HD6301 XO System Flow Chart

o

~

X

o

HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Table 19 Cycle-by-Cycle Operation
Address Mode &

Address Bus

Instructions

IMMEDIATE
ADC
ADD
BIT
AND
CMP
EOR
LDA
ORA
SBC
SUB
ADDD CPX
LDD
LDS
LDX
SUBD
DIRECT
ADC
AND
CMP
LDA
SBC
STA

ADD
BIT
EOR
ORA
SUB

CPX
LOS
SUBD

1
2

Op Code Address + 1
Op Code Address + 2

1
1

1
2
3

Op Code Address + 1
Op Code Address + 2
Op Code Address + 3

1
2
3

Op Code Address + 1

1
2
3
1
2
3

3

3

4

4
STD
STX

STS

4

1
2
3

4
JSR

5

TIM

4

1
2
3

1
1

1
1
1

0
0
0

1
1
1

0

1
1
1

0
0
0

1
1
1

0

Address of Operand (LSB)
Operand Data
Next Op Code

Op Code Address'" 1

1

0

1

Destination Address

0

1

0

1
1

Destination Address
Accumulator Data

Op Code Address'" 2
Op Code Address+ 1

0
0
0
0
0
0

Destmation Address
Destination Address + 1

0
0

Op Code Address+2
Op Code Address + 1
FFFF

1

1
1
0

1
1
1
1
1
1
0
0

0

Op Code Address+2
Op Code Address+ 1

1
1
1
1
1
1

1

0

1

1
1
1

Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
DestinallOn Address (LSB)
Reg,ster Data (MSB)
Reg,ster Data (LSB)
Next Op Code
Jump Address (LSBI
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)

ElM

6

Address of Operand

Op Code Address +2

Address of Operand
Address of Operand + ,

!

0
0

Stack Pointer

4

Stack POlnter-1

5

Jump Address

1
2
3

Op Code Address + 1
Op Code Address + 2

0
0
0
0
0
0
0
0

4

FFFF

1
1
1
1
1
1
1
1
1

5
6

Address of Operand

0

1
1

Op Code Address + 3

1

0

4
AIM
DIM

0
0

2

3
ADDD
LOO
LOX

Data Bus

1
2
3

Address of Operand

Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand

I

1

1
1

0
0
1
1
1
1
1
1
1
1
1
0
1

1

0

1
1

1
1

1
1
1

0
1
1
1
0
1
1
1
1

0
1
1
1

Operand Data
Next Op Code

Operand Data (MSB)
Operand Data (LSB)
Next Op Code

First Subroutine Op Code
Immediate Data

Address of Operand (LSB)
Operand Data

0

Next Op Code

1
1
1
1
1

Immediate Data

0

Next Op Code

Address of Operand (LSB)
Operand Data

Restart Address (LSB)
New Operand Data

(Continued)

316

•

HITACHI

---------------------HD6301XO,HD63A01XO,HD63B01XO
Address Mode 80
Instructions

Address Bus

Data Bus

INDEXED
JMP
3
ADC
AND
CMP
lOA
SBC
TST
STA

ADD
BIT
EOR
ORA
SUB

4

4

1
2
3
1
2
3

4

1
2
3

4
ADDD
CPX
lOS
SUBD

lDD
lOX

5

1
2
3

4

5
STD
STX

STS

5

1
2
3

4

5
JSR

5

1
2
3

4

5
ASl
COM
INC
NEG
ROR

ASR
DEC
LSR
ROl

6

1
2
3

4

5
6

TIM

5

1
2
3

4

5
ClR

5

1
2
3

4
5
AIM
OIM

ElM

1
2
3

7

4

5
6
7

Op Code Address+ 1
FFFF
Jump Address
Op Code Address + 1
FFFF
IX + Offset
Op Code Address +2

Op Code Address + 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset+1
Op Code Address + 2
Op Code Address+ 1
FFFF

1
1
1
1
1
1
1

1
1

0
1
1
1
1
1
1
1
1

0
0
1
1
1

Stack Pointer
Stack Pointer - 1

0
0

IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address+ 1
Op Code Address + 1

1
1
1
1
1

Op Code Address + 2

FFFF
IX + Offset
Op Code Address + 3
Op Code Address + 1
FFFF
IX + Offset
IX+Offset
Op Code Address+2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX+Offset
Op Code Address+3

0
1
1
1
1
1
1
1
1
1

0
1

0
0
1

0
0

u
1
1

0
0
1

0
0
0
0
1
1
1

0
0
1
1
1

0
0
1

0
1
1

0
0
0

1
1
1
1
1
1
1

1
1

0
1
1
1
1
1
1
1
1

0
0
1
1
1

0
0
1
1
1
1
1

0

0

1
1
1
1
1
1
1
1
1

0

1

0

1
1
1
1
1
1

0
0
0

1
1
1
1
1
1

1

0
0
0
1

1
1

0
1
1
1

0

1
1
1

Offset
Restart Address (lSB)

0

Next Op Code
Offset
Restart Address (lSB)
Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Offset

1
1
1
1

0
1
1
1
1

Restart Address (LSBI

1
1
1
1

0

First Subroutine Op Code

1
1
1
1
1

Offset
Restart Address (LSB)

0

Next Op Code

0

1
1
1
1

0
1
1
1
1

Operand Data

Restart Address (LSB)
New Operand Data
Immediate Data
Offset

Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data

00

0

Next Op Code
Immediate Data

0

1
1

0

1

0

1

0

1

Accumulator Data

RegISter Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)

1
1
1
1
1
1

0

Offset
Restart Address (lSB)
First Op Code of Jump Routine
Offset
Restart Address (lSB)
Operand Data
Next Op Code

Offset
Restert Address (lSB)
Operand Data
Restart Address (lSB)
New Operand Oat.
Next Op Code

(Continued)

•

HITACHI

317

HD6301XO,HD63A01XO,HD63B01XO--------------------------------------------Address Mode &
Instructions

Address Bus

EXTEND
JMP
3
ADC
ANO
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

TST

4

4
ADOO
CPX
LOS
SUBD

LOO
LOX

5

1
2
3
1
2
3

Op Code Address + 1
Op Code Address + 2

Op Code Address+3

1
1
1
1
1
1
1

0
0
0
0
0
0
0

1
1
1
1
1
1
1

4
1
2
3

Op Code Address + 1
Op Code Address+2

1
1

0
0

1
1

Destination Address

0

1

0

4

Op Code Address+3
Op Coda Address+ 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

Destination Address
Destination Address + 1

0
0

1
1

0
0

Op Code Address +3
Op Code Address + 1
Op Code Address + 2

1
1
1
1

0
0
0

1
1
1
1

1
2
3

4

5
STD
STX

STS

5

1
2
3

4
5
JSR

6

ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

6

CLR

5

Data Bus

1
2
3

4
5
6

Jump Address

Op Code Address + 1
Op Code Address + 2
Address of Operand

FFFF
Stack Pointer

Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address + 2

0
0

1
1
1

0
0
0
0

0
0

1
1

0
1
1
1

Next Op Code

1
1
1

Destination Address (MSB)
Destination Address (LSB)

0

1
1
1
1
1

0

First Subroutine Op Code

1
1
1
1
1

Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data

0
1
1
1
1

0

FFFF

5
6

Address of Operand

0

1
1

0

1
2
3

Op Code Address+3
Op Code Address+ 1
Op Code Address + 2
Address of Operand

1
1
1
1

0
0
0
0

1
1
1
1

4
5

Address of Operand

0

1

0

1
1
1
1

Op Code Address+3

1

0

1

0

Address of Operand

Accumulator Data

Next Op Code
Addr,;ss-ofO-perand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Deta (LSB)
Next Op Code
juriip-Address (MSS-)- - Jump Address (LSB)
Rostart Address (LSB)
Return Address (LSB)
Return Address (MSB)

1
1
1
1

4

1
1
1
1
1

Operand Data

0

1
1
1
1
1

1
2
3

Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)

0

00
Next Op Code

(Continued)

318

•

HITACHI

---------------------------------------------HD6301XO,HD63A01XO,HD63B01XO
Address Mode &
Instructions

IMPLIED
ABA
ASl
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA

Address Bus

1

ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
XGDX

2

2
3
1

PSHB

4

-4

PSHX

2
3
4

0

1

0

Next Op Code

Op Code AddreSs+1-- --1
1
FFFF
1
Op Code Address + 1
1
FFFF
1
Stack Pointer + 1
--------Op Code Address + 1
1
FFFF

0

1
1
1
1
1
1
1

0

Next Op Code

1

Op Code Address + 1

FFFF

RTS

5

1

Op Code Address+1FFFF

2
3
4
5

,-

-

2
3
7

4

5
6
7

0
0

0

0
0

1
1
1
1
1

1

-01'> Code Address+l
FFFF

1

----,

- - ~}

Stack Po.nter + 1
Stack Pointer + 2

2
3
4
5

1

0

1
1

Stack Pointer

Op Code Address + 1

2
3
4
1

5

MUL

1

2
1

PULB

"ULX~~-~

1

Op Code Address+ 1

1

3
PSHA

Data 8us

0
0
0
1
1
1

Stack Pointer-1

0
0

Op Code Address + 1

1

c------,

0
0

1
1
Stack Pointer + 1
1
Stack Pointer + 2
1
Return Address
c---OP-CodOAddre-ss+T----- I--j

1

0
0
0
0

1
1
1
1
1
1

1
1
1
1
1
1

Stack Pointer

FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

--

0
1
1
1
1
1
1
1

0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1

Restart Address (lSB)

0

Next Op Code
Restart Address (LSB)

1
1
1
1
1

Data from Stack

Next Op Code
Restart Address (LSB)
Accumulator Data

0
0

Next Op Code

1
1
1
1
1
1
1

Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LS8)
Index Register (LSB)
Index Register (MSB)

Next Op Code

0

Next Op Code

1
1
1
1

Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)

0
0
1
1
1
1
1
1

Restart Address (LSB)

Restart
Restart
Restart
Restart

Address
Address
Address
Address

(LSB)
(LSB)
(LSB)
(LSB)

(Continued)

•

HITACHI

319

HD6301XO.HD63A01XO.HD63B01XO------------------------------------------~
Address Mode &
Instructions

Address 8us

IMPLIED
WAI

1
2

9

3
4
5

Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer - 6
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3

6

Stack Pointer+4

7

Stack Pointer+5
Stack Pointer + 6
Stack POlnter+7
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack POlnter-1
Stack Pointer - 2
Stack Pointer - 3

3
4
5
6

7
B
9
1
2

RTI

10

8
9
10
1
2

SWI

12

3
4
5
6
7
8
9
10
11
12
1
2

SLP

4

BCS
BGE
BHI
BLS
BMT
BPL
BRN
BVS

3

320

Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF

0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1

1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1

11

I I

I

3
4

FFFF
Dp Code Address + 1

1
2

Op Code Address + 1
FFFF
Br.nch Addr...·.. ·.. r.st=·I"
Op Code Addr... +l .. ·rest=·O"

3

1
2

5

Stack Pointer-4

i

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1

Sleep

1

RELATIVE
Bce
BEQ
BGT
BLE
BLT
BNE
BRA
BVC
BSR

Data Bus

3
4
6

1

Op Code Address + 1
FFFF
Stack Pointer
. Stack Pointer - 1
Branch Addru"

•

11

1

1

1
0

1
1

Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A

Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (LSB)
First Op Code of SWI Routine
Next Op Code
Rest.rt Address (LSB)

1

1
0

Restart Address (LSB)
Next Op Code

0
1

1
1

1

1

1

0

1

0

Branch Offset
Restart Addres. (LSB)
First Op Code of Branch Routine
Nexi Op Code

1
1
0
0
1

0

1

1

1
0
0
1

1
1
1
1
0

HITACHI

1
1
0

Offset
Rutarl Address (LSB)
Return Address (LSB)
Return Addr.s. (MSB)
First Op Code of Subroutina

HD6301 YO,HD63A01 YO,--HD63B01YO
CMOS MCU (Microcomputer Unit)
-ADVANCE INFORMATIONThe HD630lYO is a CMOS 8-bit single-chip microcomputer
unit which contains a CPU compatible with the CMOS 8-bit
microcomputer HD6301VI, 16k bytes of ROM, 256 bytes of
RAM, 53 parallel I/O pins, Serial Communication Interface
(SCI) and two timers.
•
•
•

•
•

•

•
•

•

•

FEATURES
Instruction Set Compatible with the HD6301 Family
Abundant On-chip Resources
• 16k Bytes of ROM, 256 Bytes of RAM
• 53 Parallel liD Pins (48 liD Pins, 5 Output Pins)
• Handshake Interface (Port 6)
• Darlington Transistor Direct Drive (Port 2, 6)
• 16-bit Programmable Timer
1 I nput Capture Register
1 Free Running Counter
2 Output Compare Registers
• 8-Bit Reloadable Timer
1 8-bit Up Counter
1 Time Constant Register
• Serial Communication Interface
Asynchronous Mode
8 Transmit Formats
Hardware Parity
Clocked Synchronous Mode
Interrupts - 3 External, 7 Internal
CPU Functions
• Memory Ready, Auto Memory Ready
• Halt
• Error Detection
(Address Trap, Op-code Trap)
Operation Mode
• Mode 1; Expanded Mode
(Internal ROM Inhibited)
• Mode 2; I'xpanded Mode
(Internal ROM Valid)
• Mode 3; Single Chip Mode
Up to 65k Bytes Address Space
Low Power Dissipation Mode
• Sleep
• Standby (Hardware Set, Software Set)
Wide Range of Operation
Vee = 3 to 6V
(f = 0: 1 to 0.5 MHz)
f=O.l to 1.0MHz;HD6301VO ~
(
Vee = 5V ± 10%
f = 0.1 to 1.5MHz; HD63A01VO
f = 0.1 to 2.0MHz; HD63B01VO
Minimum Instruction Cycle Time; 0.51ls (f = 2.0 MHz)

HD6301VOP, HD63A01VOP,
HD63B01VOP

(DP-64S)
HD6301VOF, HD63A01VOF,
HD63B01VOF

eHITACHI

(FP-64)

321

HD6301YO,HD63A01YO,HD63B01YO--------------------------------------------• PIN ARRANGEMENT
• HD6301YOP, HD63A01VOP, HD63B01VOP
Vss 1
XTAL 2
EXTAL 3
MPo 4

MP,

• HD6301VOF,HD63A01VOF,HD63B01VOF

0

5

RES 6

38 P43
37

p....

P.s
p.t
3 P.,
.

36
3

""'IL......_ _ _ _ _.J'-3 Vee

(Top View)

(Top View)

• BLOCK DIAGRAM
Vcc_

Vss_
Vss -

P50(fR'O', )
P61(ilfCi2 )
PS2(MR )
PSJ(RArf)
PS4(f'S
)
PS5(OS )

P4o/As

P4dA9

P421A,,,

P"
P"

P43/Al1
P44!A,2
P4s/A13
P46/A,4
P47/Aa

P"
P"
P"
P"

Po.
P..
p..

P"

322

~HITACHI

HD6303R,HD63A03R,---HD63B03R
CMOS MPU (Micro Processing Unit)
The HD6303R is an 8·bit CMOS micro processing unit
which has the completely compatible instruction set with the
HD6301Vl. 128 bytes RAM. Serial Communication Interface
(SCI). parallel I/O ports and multi function timer are incorpora·
ted in the HD6303R. It is bus compatible with HMCS6800 and
can be expanded up to 65k words. Like the HMCS6800 family.
I/O levels is TTL compatible with +5.0V single power supply.
As the HD6303R is CMOS MPU. power dissipation is extremely
low. And also HD6303R has Sleep Mode and Stand·by Mode
as lower power dissipation mode. Therefore. flexible low power
consumption application is possible.
• FEATURES
• Object Code· Upward Compatible with the H06800. H 06801.
HD6802
• Multiplexed Bus (Oo-O,/Ao-A,). Non Multiplexed Bus
• Abundant On-Chip Functions Compatible with the
HD6301V1; 128 8ytes RAM. 13 Parallel I/O Lines. 16·bit
Timer. Serial Communication Interface (SCI)
• Low Power Consumption Mode; Sleep Mode. Stand·By Mode
• Minimum Instruction Execution Time
1j.1S (f-1MHzl. 0.67115 (f=1.5MHz). O.S/ls (f=2.0MHzl

•
•

(DP-401
HD6303RF. HD63A03RF.
HD63B03RF

Bit Manipulation. Bit Test Instruction
Error Detecting Function; Address Trap. Op Code Trap

• Up to 65k Words Address Space
•

HD6303RP. HD63A03RP.
H063B03RP

TYPE OF PRODUCTS
Bus Timing
Type No.
1.0MHz
H06303R
HD63A03R
1.5 MHz

H063B03R

(FP-54)
HD6303RCG.HD63A03RCG,
HD63B03RCG

•

2.0 MHz

(CG-40)

@HITACHI

323

HD6303R,HD63A03R,HD63B03R-----------------------------------------------• PIN ARRANGEMENT
•

• HD6303RP, HD63A03RP,
HD63B03RP

I gl:l;z-~~x

0

w

In"ltMN ....

-

AS

•

HD6303RF, HD63A03RF,
HD63B03RF

L~J L;J L8J :"~J Lc:;J t~J
O,/A, :f~

ColAo

t&: t~J L~J L~J
[~5 A12

J!J

~~

0 3 /.6 3

R/W 3~J

D"fA ..

AS 3jJ

[2~
f22

D,/A,

Do/Ao

02 /A 2

Os/As

.-

OT/~i

Vss

1J

[2:0 A7/P17
[(9 Aa/P'6

t2_1

ycc

XTAl

~]

A,o

EXTAL

~]

D:s As/plfJ

A"

NMI

~J

IRQ,

§J

VI

A"

A"
A,.

33 (NC)

Vee

(Top View)

(Top View)

(Top View)

BLOCK DIAGRAM
..J
..J«

!l !a~ ~ 1:iIO~
»xwwz!!:lii:

.......-+~-

P••

~~""'·~-P.,

~-+.-r<'-'- P ••
~-+~~-P23

Address!

p ••

Data
Buffers

As

...- - - - P,.IA.
..._ _ _ _ P"IA,

A"

....---....- - - ....- - - ....- - - -

A.
A,.

PulA,
P13IA3
P,.IA.
PulA.
PlIIA.
...----P17IA'

Buffers

A,.·.-A".

eHITACHI

A4/PI4

[1~ A3/P'3

A"

324

A,s

~oJ

r-

E

A,

Au
A13

A'4

D,/A,

A,

•

All

-----------------------HD6303R,HD63A03R,HD63B03R
•

ABSOLUTE MAXIMUM RATINGS
Symbol

Item

Value

Unit

-0.3 -+7.0

V

Input Voltage

Vee
V in

-0.3 -

Operating Temperature

T opr

0- +70

V
°c

Storage Temperature

Tstg

Supply Voltage

(NOTE)

Vee+0.3

°c

-55 -+150

This product has protection circuits in input terminal from high static electricity voltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation, we recommend Vin. Vout : VSS :;;; (V in or Vout) :;;; Vee.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70°C, unless otherwise noted.!
Item

Symbol

Test Condition

RES, STBY
Input "High" Voltage

EXTAL

V 1H

Vee xO.7

Other Inputs
Input "Low" Voltage

All Inputs

Input Leakage Current

NMI,

Three State (off-state)
Leakage Cu rrent

min
vee-0.5
2.0
-0.3

V 1L

1.0

/J. A

-

V

-

-

0.55

V

-

-

12.5

pF

-

2.0

15.0

/J.A

6.0

10.0
2.0

mA

V,n =0.5-Vee -0.5V

-

Output "High" Voltage

All Outputs

V OH

Output "Low" Voltage

All Outputs

VOL

IOL = 1.6mA
V;n=OV. f= 1.0MHz.
Ta = 25°C
Operating (f=l MHz")

C,n

Standby Cu rrent

Non Operation

lee

Current Dissipation'

lee

RAM Stand-By Voltage

V RAM

Sleeping (f=l MHz")

V
V

IITsl1

All Inputs

Vee
to.3

/J.A

PIO-P", P20 -P 24 •
0 0 -0,. A.-A ls

Input Capacitance

Unit

1.0

-

IOH - -10/J.A

max

0.8

V;n =0.5-Vee -0.5V

IOH = -200/J.A

-

-

lI;n I

iRal , RES, STBY

typ

2.4
Vee- 0.7

2.0

1.0

-

-

V

V

• V1H min = Vee-1.OV. VIL max = O.8V

.*

Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max.
values about Current Dissipations at f = x MHz operation are decided according to the following formula;
typo value

(f = xMHz) = typo

max. value (I

=xMHz)

=

value (I = 1MHz) x x
max. value (f = 1MHz) x x
(both the sleeping and operating)

•

HITACHI

325

HD6303R,HD63A03R.HD63B03R------------------_ _ _ __
•

AC CHARACTERISTICS (Vee = 5.0V±10%, Vss ~ OV, Ta = 0-+70·C, unless otherwise noted.)

BUS TIMING
Item

Test
Con·
dition

Symbol

HD6303R
min

Cycle Time

t eve

Address Strobe Pulse Width
"High"

PWASH

220

Address Strobe Rise Time

tASr

Address Strobe Fall Time

tASt

-

Address Strobe Delay Time

tASO

Enable Rise Time

tEr

Enable Fall Time

tEt

Enable Pulse Width "High" Level

PWEH

Enable Pulse Width "Low" Level

PWEL

Address Strobe to Enable Delay
Time

tASEO

Address Delay Time for Latch

Data Hold Time

60

450
450

,

60

:--

-

tA01

Address Delay Time

Data Set·up Time

1

tAo2

Fig. 1

tAOL

Fig. 2

-

-

Write

tosw

230

Read

tOSR

BO

Read

tHR

0

Write

tHW

20

10 0.666

20
20

20
20

-

-

-

250
250
250

-

-

-

-

650

-

650

60

tAHL

30

Address Hold Time

tAH

Ao - A, Set·up Time Before E

tASM

20

150

-

-

typ

-

10 0.5

-

-

20

300

-

-

40

-

-

40

-

300

- -

- - 150
60
0
20
40
20
20
110

-

-

-

20
20

190
190
190

110

20

220
220
20

-

-

max
10

-

-

395

20
60

-

-

fJS
ns

20

ns
ns

-

ns

20

ns

20

-

- -

Unit

20

160

- 160
- - 160
- 100 - - 50 - - 0 - - 20 - - 20 - - 20 - -

- -

-

HD63B03R

max min typ

20

- -

200

tASL

Address Hold Time for Latch

Access Time

-

-

HD63A03R

max min

-

Address Set·up Time for Latch

INon-Multiplexed (tACCN)
Peripheral Read Bus

typ

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

-

ns

270

ns

- 270
- -

ms

ns

.
Multiplexed Bus (tACCM
Oscillator stabilization Time
tRC

Fig.B

20

Processor Control Set-up Time

tpcs

Fig.9

200

Symbol

Test
Condition

HD63B03R
HD63A03R
HD6303R
Unit
min typ max min typ max min typ max

I

-

-

-

20
200

395

- -

20
200

ns
ns

PERIPHERAL PORT TIMING
Item
Peripheral Data.
Set-upTime

Port 1, 2

tposu

Fig. 3

Peripheral Data
Hold Time

Port 1,2

tpoH

Fig. 3

Delay Time, Enable Nega-I Port 1
tive Transition to Peri2*
' tpwo
pheral Data Valid

Fig. 4

- - 200 - - 200 - 200 - 200 - - 200 - - - 300 - - 300 - - 300
200

• Except Pu

326

•

HITACHI

ns
ns
ns

------------------------HD6303R,HD63A03R,HD63B03R
TIMER, SCI TIMING
Test
Symbol Con·
dition

min

typ

max min

typ

max min typ

max

Timer Input Pulse Width

t pWT

2.0

-

-

2.0

-

-

2.0

-

-

t cvc

Delay Time, Enable Positive
Transition to Timer Out

tToo

-

-

-

-

400

-

-

400

ns

SCI Input Clock Cycle

t ScyC

2.0

-

-

2.0

-

-

tcyc

0.4

0.6

0.4

-

2.0

tpWSCK

-

-

SCI Input Clock Pulse Width

0.6

0.4

-

0.6

tScyc

Test
Symbol Con·
dition

min

typ

max min

typ

max min typ

-

-

3

-

2

-

-

150

-

-

Item

Fig. 5

HD63A03R

HD6303R

400

HD63B03R

Unit

MODE PROGRAMMING
Item

PW RSTL
Fig. 6
t MPS

3

Mode Programming Set·up Time

RES "low" Pulse Width
Mode Programming Hold Time

tMPH

150

2

HD63B03R

HD63A03R

HD6303R

2

-

150

-

3

max

Unit

-

tcyC

-

tcyc
ns

~---------------------tcvc------------------------I
Address Strobe

2.4V

IASI

Enable

lEI

MPUWtlte

D.-D.,.A.-A,

MPU Read

0.-0,. A.-A,

_

Not Valid

Figure 1 Multiplexed Bus Timing

•

HITACHI

327

HD6303R,HD63A03R,HD63B03R----------------------------------------------tcyC

Enable

eEl

2.4V

O.BV

MPUWrite
0.-0,

---+-----+------0(
-+____-1___________-<1

MPU Read _ _ _
DD-D,

r

I'.?2JlI Not Valid

Figure 2 Non-Multiplexed Bus Timing
rMPUROId

MPUWr;te

E~
D.lV

D.lV

'I.'10 - ,,.

~tpWD

-P"

Inputs

All Oete
2.4V Data V.ltd
Pori Outputs _ _ _ _ _ _ _-'''''0;..:8'''"_ __

Note) Port 2: Except P"

Figure 3 Port Data Set-up and Hold Times
(MPU Read)

Figure 4 Port Data Delay Times
(MPU Write)

Timer

Counter - _ _ _- ' '---1""'''-''--' ' - - - p ..
Output

Figure 5 Timer Output Timing

328

Figure 6 Mode Programming Timing

•

HITACHI

----------------------HD6303R,HD63A03R,HD63B03R
Vee
RL

2.2k!l
(4.0k!l for E)

=

C=90pF for AS, R/W, D,/A, - D,/A" and A. - A"

Test Point

152074

=30pF for P,;!o ....
=40pF for E

(8)

or Equiv.

P24

and Ao/P ,o .... A,,/P'"I

R=12kQ

e

Figure 7 Bus Timing Test Loads (TTL Load)
Interrupt

Test

IntMnal
Address Bus

SP

SP·,

SP·2

SP·3

SP-4

SP·5

SP·6

NMl,lRQl

Vector

MSB

Vector

LSB

Address Address

Internal
Data Bus

Op Code pe:rand Irrelevant PCO _

_ _~~8ta

Internal

Re.d

PC7

PCB
PC1S

IXOIX7

lXB IX1S

Ace A Ace a

CCR

\

I

Internal

Wnte

New PC
Address

Figure B Interrupt Sequence

---55~V~----------*-------+_--------------~~~~
~flRC

Vee II-="-'----'"e-----

H----!~---

ve/osv

tPc~

tpes

VCc-O 5V

O.BV

RES~~I----------~~----JI

~"''''- )\\\\\\\\\\\\\\\\\\\\\\\

~~f------------

I~
1~~;~I----

________

..

~'., ,_~\\\\\\\\\\\\\\\\\\~\\

\\\\\\\\\\\\\\\\\\\\\\1

Aiii • •

~_,\\\\\_\\\\\\\\\\\\\\\\\fl------------

I I
f I
I I
R I
R I
R I

I

I
I
I
I
I
I

R Ii@ I

I I R
I I R
I I R

I I I I
I I I
I I I I

I

I

I I I

I I I f
I I f I
I I R
I I R
I
f
f

•
••

••

I R R
I R R
f R R

I I R
I I R
I I R
I I R

•
•
•

Notel Condition Code Register will be explained in Note of Table 10.

• New Instructions
In addition to the HD6801 Instruction Set, the HD6303R
has the following new instructions:
AIM----(M)· (IMM) .... (M)
Evaluates the AND of the immediate data and the
memol)', places the result in the memol)'.
OIM---- (M) T (IMM) -. (M)
Evaluates the OR of the immediate data and the
memol)'. places the result in the mem0l)'_
EIM----(M)~ (IMM) .... (M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memol)' .

340

•

TIM----(M)' (IMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the fust is op-code. the
second is immediate data, the third is address modifier.
XGDX--(ACCD)" (IX)
Exchanges the contents of accumulator and the index
register.
·SLP----The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.

HITACHI

-----------------------HD6303R.HD63A03R,HD63B03R
Table 8 Index Register, Stack Manipulation Instructions
Condition Code
Regi• •

Addressing ModIl
Pointer Opera'lons

Mnemonic

Compere I"del( Reg

CPX

Decrement Ind•• Reg

DEX

Decrement Stick Pnt,

DES

Increment Ind.x Reg

INX

Increm.nt StIck Pnt,

INS

---

800l••nl

Arithmetic Open. ton
INDEX
EXTEND IMPLIED
DIRECT
IMMED.
1/ OP
OP
1/ OP
1/ OP 1/ OP
/I
8C J 3 9C 4 2 AC 5 2 BC 5 3
'X-M:M+l
09 1 1 X-I-X

-

lOS
STX

Loed Stack Pnt,
Store Index Reg

Store Stack Pnt,

-------;-;:--:Index Reg .... Stack Pnt,

STS
TXS

--- r-rs-X---

-

34

--

':~ ~E

LOlid Inde. Reg

-

-

8E

1 1 SP-l-SP
1 1 X + 1- X

08
31

f---- 1--- -

2 FE 5 3
2 BE 5 3
2 FF 5 3
2 BF 5 3

5
5
5
5

3 3 DE 4 2 EE
3 3 9E 4 2 AE
OF 4 2 EF
9F 4 2 AF

-

Stack Pn.r ..... I"ct.. Reg

1

1 sP+l-sP
M- XH • IM+ll- XL
M- sPH. IM+ll-sPL
XH .... M, XL ..... eM + 11

SPH - M. SPL - 1M + 11
1 X -1- sP
30 1 1 $P+1-X
3A 1 1 B +x- X

35

1

3C

5 1 XL - M... SP - 1 - SP

Push Dati

ABX
PSHX

Pull Oa.a

PUlX

38 4

XH- M•• SP -1- SP
1 SP + 1- SP,M.- XH
sP+1-sP.M..... X L

Exchange

XGDX

18

1 ACCD-IX

Add

2

5 4 3 2 1 0
H

I N Z V C

•• t I t
•••I •
•
••
••• I •
• •
• (i) I R
• .0 Zero

Brench If > Zero
Br.nch If Higher

BGE
8GT
BHI

< Zero

RELATIve
OP
20
21
24
26
27
2C
2E

3
3
3
3

1/

DIRECT
OP -

1/

INDEX
OP -

1/

Regilt.,

EXTEND

IMPLIED

OP -

OP -

1/

Branch Test

1/

None

2
2
2
2
3 2

None

CoO
C· ,
Z·'
NGlV-O
Z +IN Gl VI- 0
e+z-o

3 2

8lE

22
2F

3 2
3 2
3 2

Som.

BlS

23

3 2

Branch If < Zero

BlT
BMI

20 3 2
2B 3 2

NGlV-'
N -,

BNE

Z'O

Brench If

Brlnch If Lower Or

Brlnch If Minul
aranch If Not EQu.1

- -f-

Z + IN Gl VI-I
C+Z'll1

26

3 2

Clnr

BVC

28

3 2

V-O

Branch If O..rflow Sot

BVS
8Pl

28

3 2

V-I

2A 3 2
80 5 2

N-O

Zero
Sr.nch If O\Mrflow

Branch If Plul

Jump To Subroutine

BSR
JMP
JSR

Sr.nch To SUbroutine

Jump

BE

3 2 7E

3 3

go 6 2 AD 6 2 BD B 3

,

No (lporatlon

NOP

01

Retu,n From Interrupt

RTI

38 10 1

Retum From
SUbroutine

RTS

38

SWI
WAI
SlP

3F 12 1
3E 9 1
'A 4 1

-

Sottw.,. Interrupt

Wait for Interrupt-

1

Adv.nC8. Prog. Cnt'.
Only

5 1

Notel 'WAI put. R/W high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 10.

•

HITACHI

5 4 3 2 1 0
H

I N Z V C

•
•
•
•
•
•
•

••

· · ••• ·••

•
•••
•••
•••
••
•••
•
••••
•••
••••
••••
• ••
•• •
• ••
• .- • •
•••
• ••
••••
•
••••

· ·•• •••
· · •• ••
· ••
•
· · ·•• ••
· •• ••
· · •• •••
· · · ·• •
••

-ill-

••••
·• • ••·· ··•· ··••
S •

• ill •

341

HD6303R,HD63A03R,HD63B03R----------------------Table 10 Condition Code Register Manipulation Instructions

!Add,..s;ngMode
OperMions

CI_Cany
C"', Overflow
Sit Cerry
Set Interrupt Melk
Set Overflow
Accumul.tor A .... etA

eeA .... Accumulator A

[NOTE

11

O-C
0-1
--O-V
I -C
I -I
I-V
A- CCR
CCR-A

5

4

H

I

3
N

2
Z

I
V

0
C
R

°

0

0

0

0

°

R

0

0

0

°

0

°S

o_f-0_ ~ c-!0
0
0

0

0

°

0

°
°---° 1°

0

0

R

°
°

0
S
°
14---

0

0

0

0

Condition Code Register Notes: (Bit set if test is true and cleared otherwise)
(j)
(Bit VI
Test: Result = 10oooooo?

®

@

(Bit CI
(Bit CI
(Bit VI
(Bit VI

@

(Bit V)

CD

(Bit NI
(All Bitl

Result'" OOOOOOOO?
BCD Character of high-order byte greater than 9? (Not cleared if previouslV setl
Operand = 10000000 prior to execution?
Operand' 01111111 prior to execullon?
Test: Set equal to Nee=1 after the execution of instructions
Test: Resultle55than zero? (Bit 15=1)
Load Condition Code Register from Stack.

(Bit

Set when interrupt occurs. If previously set, a Non-Maskable Interrupt

@
@

@

(§)
ifg)

®
(NOTE

-

CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA

elft' Interrupt Milk

Condition Code R~lster
Boolean Operation

IMPLIED
/I
OP
I
I
OC
I
I
OE
I
OA
I
I
0[1
I
I
OF
I
I
OB
I
I
I
06
I
I
07

Mnemonic

Test:
Test:
Test:
Test:

n /

(All Bitl
(Bit CI

IS

reqUired to exit the wait

state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7= 1 of ACCS?

21 eLi

instruction and interrupt.
If interrupt mask-bit is set 0="''') and interrupt is requested (lRQI =: "0" or T'RQ'; =: "0"),
and then Cli instruction is executed, the CPU responds as follows.
The next instruction of CLI is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
<%> The ,next instruction of CLI is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
EVen if TAP instruction is used, instead of CLI, the same thing occurs.

CD

Table 11 OP-Code Map
OP
CODE

ACC
A

~ °
°

0000

lO
0000
0001
0010
0011
0100
0101
OliO
0111
1000
1001
1010
lOll
1100
1101
1110
1111

~

I NOP
2 ~
S ~
4 lSRD
5 ASlD
6 TAP
7 TPA
8 INX
9 .OEX
A ClV
B SEV
C CLC
0 SEC
E CLI
F SEI

0001
1
SBA
CBA

.-./
~
~
~

0010
2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ

TAB
TBA
XGOX evc
OM BVS
SlP
BPl
ABA
BMI
. / BGE
BlT
~
BGT
/
~ BlE
1
2

0011
3
TSX
INS
PULA
PULB
DES
TXS
PSHA
PSHB
PUlX
RTS
ABX
RTI
PSHX
MUl
WAI
SWI

3
°
UNDEFINED OP CODE c:;;::::::J

1/6:

ACC
IND
IR
B
0101
OliO
Dill
5
6
7
NEG
AIM
OIM
COM
LSR
ElM
ROR
ASR
ASl
ROl
DEC
TIM
INC
TST
JMP
""""""'--1
ClR
8
7
5

----

0100
4

--

./'
4

1

Ar-CA or SP
IMM1 DIR -1 INO -1 EXT
1000
8

1 1001 1 1010 1 1011

1

•

1

Al

J

c

J

B

SUB
CMP
SBC

1

ACCB or X
DIR liND
1101 1 1110

o

1

E

1 EXT
1 1111

1

F

0

I
2

SUBD

AD DO

3

AND
BIT
LOA

;.::;--:r__ ~r..A

4

5
6

STA

"""'--1

7
8
9
A

EOR
AOC
QRA
ADD

B

CPX
BSR

1

8

1

HITACHI

~-I

JSR
LOS
STS

~1

• Onlv for Instructions of AIM, OIM, ElM, TIM

342

9

IMM
liDO

9

1

A

~-I

1

B

C

lOO
STO
lOX
STX

1 o 1

E

C
0
E
F

1

F

-----------------------HD6303R,HD63A03R,HD63B03R
• Instruction Execution Cycles
In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the current
instruction fetch and just before the start of the subsequent
instruction fe tch.
The HD6303R uses a mechanism of the pipeline control
for the instruction fetch and the subsequent instruction fetch
is performed during the current instruction being executed.

Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction
cycles such as MULT, PULL, DAA and XGDX in the HD6303R.
Table 12 provides the information about the relationship
among each data on the Address Bus, Data Bus, and R/W status
in cycle-by-cycle basis during the execution of each instruction.

Table 12 Cycle·by-Cycle Operation
Address Mode &
Instructions

Address Bus

IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
ADD'D CPX
LDD
LOS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB
.. _-

1
2

'f
3

I
.~

---

3

,-----

-1>.000--CPX

- st-b---

LOS
SUBD

4

4

5

1
2
3

Op Code Address + 1
Address of Operand
Op Code Address+2

-,
2
3
1
2
3
1
2
3
1
2
3

4
5

- ffM---4

1
2
3

4
AIM
OIM

1
1

ElM

6

_._---

2
3

4
JSR--

-

Op Code Address+1
Op Code Address+2
Op Code Address+3

4

STS ---,-

STX

Op Code Address+ 1
Op Code Address+2

Operand Data
Next Op Code

2

3

LDD
LOX

Data Sus

1
2
3

4
5
6

Op Code Address + 1
Destination Address
Op Code Address+2
Op Code Address + 1
Address of Operand
Address of Operand+1
Op Code Address+2
Op Code Address + 1
Destination Address
Destination Address + 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3
Op Code Address+ 1
OP Code Address+2
Address of Operand
'FFFF
Address of Operand
Op Code Address+3

--,-1
1

1
1
1

Operand Data (MSB)
Operand Data (LSB)
Next Op Code

Address of Operand (LSB)
Operand Data
Next Op Code

1
Destination Address
0
Accumulator Data
1
Next Op Code
1
Address of Operand (LSB)
Operand Data (MSB)
1
1
Operand Data (LSB)
Next Op Code
1
Destination Address (LSB)
1
Register Data (MSB)
0
Register Data (LSB)
0
1
Next Op Code
1
Jump Address (LSB)
Restart Address (LSB)
1
Return Address (LSB)
0
1
0
Return Address (MSB)
i 1 I First Subroutine Op Code
Immediate Data
1
Address of Operand (LSB)
1
i 1 i Operand Data
1
'Next Op Code
- ,-- t--rinmediate Data-'----1
1
1
0
1

Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
- Continued -

•

HITACHI

343

HD6303R,HD63A03R,HD63B03R-----------------------

Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

INDEXED
JMP
3
ADC
AND
CMP
LOA
SBC
TST
STA

ADD
BIT
EOR
ORA
SUB

4

4
---

ADDD
CPX
LOS
SUBD

LDD
LOX

5

1
2
3
1
2
3
4

Op Code Address + 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2

1
1
1
1
1
1
1

Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code

1
2
3
4
1
2
3
4

Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
rap Code Address + 1
FFFF
Stack Pointer
Stack Pointer-l
IX + Offset
Op Code Address+ 1
FFFF
IX + Offset
FFFF
I
IX + Offset
Op Code Address+ 1
Op Code Address+ 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address+2
Op Code Address+ 1
Op Code Address+2
FFFF
IX+Offset
FFFF
IX + Offset
Op Code Address+3

1
1
0
1
1
1
1
1
1
1
1
0

Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
---Immediate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
00
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code

5
-~STS--

STX

I

5

1
2
3
4

5
JSR

5

1
2
3
4

5
ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

6

1
2
3
4

5
6

I

TIM

5

1
2
3
4

5
~--

5

1
2
3
4

5
AIM
OIM

ElM

7

1
2
3
4

5
6
7

0
1
1
1
0

0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1

- Continued -

344

•

HITACHI

-----------------------HD6303R,HD63A03R,HD63B03R
Table'2 Cy.cle·by·Cycle Operation (Continued)
Address Mode &
Instructions
EXTEND
JMP

Address Bus

Data Bus

, Op Code Address + ,
2
: Op Code Address+2
! 3
. Jump Address
TST-~--'--Op Code A""d""d7-r-es-s--'+--=, '--~'-1

3

ADC
AND
CMP
LOA
SBC
- STA

ADD

BIT
EOR
ORA
SUB,

4

.

4

2
3
4

Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand-(MSe)
Address of Operand (LSB)
Operand Data
Next Op Code

Op Code Address+2
,
Address of Operand
,
'Op Code Address+3
,
.
--------:----'--f-~ Op Co-de Address+T----- --.- ---,-'--Oestinatlon Address(IIi1SS)

~. g~s~~::0~d~~~~:~s2

~

~;~~:~Ii;t~~g~~:ss (LSB)

Op Code Address+3
,
Next Op Code
----:--,--t-OP Code Address:i='l--'-,-- AddreSS of operand (MSB)
CPX
LDD
2 . Op Code Address+2
,
Address of Operand (LSB)
LOS'
LOX
5
3
Address of Operand
,
Operand Data (MSB)
4
Address of Operand+'
,
Operand Data (LSB)
SUBD
5
Op Code Address+3
,
Next Op Code
STD-SIS -- - -·-----~T
Op Code Address+'
-----,Destination Address (MSB)
STX
2
Op Code Address+2
1
Destination Address (LSB)
3
Destination Address
0
Register Data (MSB)
5
4
Destination Address + 1
0
Register Data (LSB)
5
Op Code Address+3
1
Next Op Code
1
Op Code Address+ 1
1.
Jump Ad.-:id;C:re::=s~s'(M"""S"'B')
JSR
2
Op Code Address+2
Jump Address (LSB)
3
FFFF
1
Restart Address (LSB)
6
4
Stack Pointer
0
Return Address (LSB)
5
Stack Pointer-'
0
Return Address (MSB)
----~.----~ -~--L Jump Address
,
First Subroutine Op Code
ASL
ASR
,
I Op Code Address + ,
Address of Operand (MSB)
DEC
2
I Op Code Address+2
Address of Operand (LSB)
COM
INC
LSR
6
3
Address of Operand
Operand Data
NEG
ROL
4
FFFF
1
Restart Address (LSB)
ROR
5
Address of Operand
0
New Operand Data
._______ --__--1 6
Op Code Address+3
. 1
Next Op Code
CLR
.
I 1
Op Code Address+l
Address of Operand (MSB)
2
Op Code Address+2
Address of Operand (LSB)
3
Address of Operand
Operand Data
5
0
00
4
Address of Operand
5
OJ:) Code Address+3
Next Op Code

-"oob-- .-- ---

_________

.

4

..

- Continued -

•

HITACHI

345

'---~------------------HD6303R,HD63A03R,HD63B03R

Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

IMPLIED
WAI

Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer+3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer+6
Return Address
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA

1
2
3
4
5
6
7
8

9

9
1

RTI

I

2
3
4
5

10

6

7
8

SWI

12

_. ..-_-+1

I

9
10
1
2
3
4
5
6
7
8
9
10

I

I
4

s'r
3
4

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1

Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)

1
1
1

First Op Code of SWI Routine _
Next Op Code
Restart Address (LSB)
High Impedance-Non MPX Mode
Address Bus -MPX Mode

- ;v.<'e: .:c:-;.to: :r: ;:A=-,d~d-:ire=:;s=,=s,-: F,=,F",F'iB:, :,:, : _+- ;c1_hA.Td~d: -re:;s <: 0=-f;,-:S~Wci:I:-R-=-o,-,ut-,- in.:.:.e: .:(L:.: S" B=-)

_J'_11'-;i21=--t' Address of SWI Routine
I 1
I Op Code Address+ 1
2]
I FFFF
FFFF

SLP

Data Bus

1

P
FFFF
Op Code Address+ 1

Restart Address (LSB)
Next Op Code
- Continued -

•

HITACHI

347

HD6303R.HD63A03R.HD63B03R-----------------------Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

RELATIVE
BCC
BCS
BEQ
. BGE
BGT
BHI
BlE
BLS
BLT
BMT
BNE
BPl
BRA
BRN
BVC
BVS
-SSR---

Address Bus

Op Code Address+ 1
FFFF
Branch Address· .. ···Test=" 1"
Op Code Address +1... Test= "0"

1
3

2

1

3

1

5

Data Bus

Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
Branch Address

2
3

4
5

II

1
1
1

Branch Offset
Restart Address (LSB)

1_
I

of . "..h """~
Next0,
OpCod.
Code

-- - 1- Offse-t--------1
0
0

1

Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine

• LOW POWER CONSUMPTION MODE
The HD6303Rhas two low power consumption modes; sleep
and standby mode •

This sleep mode is available to reduce an average power
consumption in the applications of the HD6303R which may
not be always running.

• SleepMode
On execution of SLP instruction, the MPU is brought to the
sleep mode, In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active, So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of a
normal operation,
The escape from this mode can be done by interrupt, RES,
'S'fBY, The 1rnS resets the MPU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
CPU.

•

v"

I

Bringing 'STBY "Low", the CPU becomes reset and all
clocks of the HD6303R become inactive, It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD6303R.
In the standby mode, if the HD6303R is continuously supplied with power, the contents of RAM is retained. The standby
mode should escape by the reset start. The following is the
typical application of this mode.
First, NMI routine stacks the CPU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the standby bit, and then goes into the standby
mode. If the standby bit keeps set on reset start, it means that
the power has been kept during stand-by mode and the contents
of RAM is normally guaranteed, The system recovery may be
possible by returning SP and bringing into the condition before
the standby mode has started. The timing relation for each line
in this application is shown in Figure 21.

,

\~

,..u ~

NMI

HD6303R

Standby Mode

iii

mv

II

r+

.sm~~:
II

1

I

I<--ot
, Stack registers

'RAM control
register set

I

r

~

~~:II~Z~~~ I
time

~

restart

Figure 21 Standby Mode Timing

348

•

HITACHI

------------------------HD6303R,HD63A03R,HD63B03R
• ERROR PROCESSING
When the HD6303R fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.
• Op-Code Error
Fetching an undefmed op-code, the HD6303R will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP ($FFEE, $FFEF), that has a second highest priority
is the highest).

(ims

• Add..... Error
When an instruction is fetched from other than a resident
RAM, or an external memory area, the CPU starts the same
interrupt as op·code error. In the case which the instruction is
fetched from external memory area and that area is not usable,
the address error can not be detected.
The address which cause address error are shown in Table

13.
'This feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.
Transitions among the active mode, sleep mode, standby
mode and reset are shown in Figure 22.
Figures 23, 24 show a system configuration.
The system flow chart of HD6303R is shown in Figure 25.

Figure 22

Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset

Table 13 Address Error
Addre•• Error

$0000 - $001 F

HD6303R MPU

18

Addr." BUI

Oata BUI

Add'II.Bu.

Figure 23 HD6303R MPU Multiplexed Mode

8

Oltl BUI

Figure 24 HD6303R MPU Non·Multiplexed Mode

•

HITACHI

349

HD6303R,HD63A03R,HD63B03R-------------'-------------

A

VE
I
FFE·FF

PCL~MSP
PCH~MSP-1
IXL~MSP-2

IXH~MSP-3

ACCA .MSP-4

AceB .MSp·5
CCR~MSP-6

A

Figure 25 HD6303R System Flow Chart

350

eHITACHI

------------------------HD6303R,HD63A03R,HD63B03R
• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT

• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State

As shown in Fig. 26, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD6303R as
possible.

• Standby State

The conditions of power supply pins, clock pins, input pins
and E clock pin are the same as those of operation. Refer to
Table 14 for the other pin conditions.
Only power supply pins and "STI3Y are active. As for the
clock pin EXTAL, its input is fixed internally so the MPU is
not influenced by the pin conditions. XTAL is in "I" output.
All the other pins are in high impedance.

XTAL
EXTAL
HD6303R

Do not us. this kind of print board design.

Figure 26

Precaution to the boad design
of oscillation circuit
Table 14 Pin Condition in Sleep State

~e
Pin

Ao/Plo A7/PI7
AI - Au
Do/Ao D7/A7
R/W

-- AS

Condition

I/O Port

I/O Port

Function
P20 - P24

Multiplexed Mode

Non Multiplexed Mode

Keep~t~e

condition just before sleep

Function
Condition

Address Bus (Ao -A 7)
Output "1"

Function

Address Bus (As -Au)

Condition

Output "1"

Function
Condition

Data Bus (Do -0 7)

--.

-

--'~

..

-

~-~~-----~-----

I/O Port

Keep the condition just before sleep

-

-

Address Bus (As -Au)

High Impedance

E: Address Bus (AD -A7), E: Data Bus
E: Output "1". E: High Impedance

Function

R/W Signal

R/W Signal

Condition

Output "1"

-

.---.-

-

-

Output AS

Table 15 Pin Condition during RESET

~
Pin

P20 - P24

Non·Multiplexed Mode

High Impedance

Multiplexed Mode

•

.

Ao/Plo - A7/P17

High Impedance

As - Au

High Impedance

Do/AD - D7/A7

High Impedance

R/W

"1" Output

+------

AS

E': "1" Output
E : "0" Output

•

•

HITACHI

•
E : "1" Output
E : High Impedance

351

HD6303R,HD63A03R,HD63B03R-----------------------------------------------•

Table 16 Difference between HD6303 and HD6303R

DIFFERENCE BETWEEN HD6303 AND HD6303R

The HD6303R is an upgraded version of the HD6303. The
difference between HD6303 and HD6303R is shown in Table
16.

Item

•

HD6303R
Mode 2: Multiplexed
Mode
(Equivalent to Mode 4)

The electrical character·
Electrical
istics of 2MHz version
Character·
(B version) are not spec·
istics
ified.

Some characteristics
are improved.
The 2MHz version is
guaranteed.

Timer

352

HD6303

Operating
Mode 2: Not defined
Mode

HITACHI

Has problem in output
compare function.
(Can be avoided by software.)

The problem is solved.

HD6303X,HD63A03X,--HD63B03X
CMOS MPU (Micro Processing Unit)

-PRELIMINARY-

The HD6303X is a CMOS 8-bit microprocessing unit (MPU)
which includes a CPU compatible with the HD630IVl, 192
bytes of RAM, 24 parallel I/O pins, a Serial Communication
Interface (SCI) and two timers on chip.
• FEATURES
• Instruction Set Compatible with the HD6301V1
• Abundant On-chip Functions
192 Bytes of RAM
24 Parallel I/O Ports
16-Bit Programmable Timer
B-Bit Reloadable Timer
Serial Communication Interface
Memory Ready
Halt
Error-Detection (Address Trap, Op Code Trap)
• Interrupts .•• 3 External, 7 Internal
•• Up to 65k Words Address Space
• Low Power Dissipation Mode
Sleep
Standby
• Wide Range of Operation
Vee· 3 - BV (f· 0.1 - 0.6MHz),
f. 0.6 -1.0MHz; HD6303X )
Vee· 6V :l: 10%( f· 0.6 -1.6MHz; HDB3A03X
f • 0.6 - 2.0MHz; HD63B03X

• PIN ARRANGEMENT
• HDB303XP. HDB3A03XP. HDB3B03XP
V.

XTAL

0

HD6303XP, HD63A03XP,
HD63B03XP

HD6303XF, HDB3A03XF,
HD63B03XF

(FP-80)

• HD6303XF, HD63A03XF, HDB3B03XF
~

E

'"'

I'll!

IXTAL

MP,

P.tW

~.

ClI!

m

m'
NC •

IA

D,
D,
D.
D.
D.
D.
D.
D,

1'I'IV
1m!
p..

P"
p..

P..
p..
p..

P..
P"
P"
P"

A,
A,
A.
A.

P..

A.

p ..

p ..
P..

A.
A.
A,

p..

VII

P"
P..
P..

A,
A,

P..
P..

PIO

A..

P..
P..

A ..

• D,
II NC

NC
II Os

•,

..

Pu

•

" 0,
"0,

'II

1O

•

P"
P"
Pu •

II
..
U
I.

p.. "

P" "
NC
P.I

I~

t.

It

Pit"
PII

P..
PI~

PII

D~

D,
NC
NC
A.
A.

A.
.. A.
.. A.

II

~

t.

41 A,

.. A,

"

p.. "

'1 A,

P.,

.. Vu
n A,

21

NC
NC IJ
NC ..

An

p..

• D,
., NC

NC •
NC •

A"
A"
7 An

p..

/

~~~'~~~l.~~~~~ad
•

tii :~
J~~,E~~~,E~JJJ~.fJc

Vee

(Top View)

(Top View)

_i~:I-J- - - -

w~ _:~\\\\~\\\\\\\\\\\\\• •

~8I111JJm~iMI.liI4111111~-----~:

Figure 11 Reset Timing
• FUNCTIONAL PIN DESCRIPTION
•

Vee. Vss
Vee and Vss provide power to the MPU with 5V±1O% supply. In the case of low speed operation (fmax = 500kHz), the

MPU can operate with three through six volts. Two Vss pins
should be tied to ground.
• XTAL.EXTAL
These two puis interface with an AT -cut parallel resonant
crystal. Divide-by-four circuit is on chip, so if 4MHz crystal
oscillator is used, the system clock is IMHz for example.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
XTALr---~-----'

CJ

CLl =CL2
(3,2-SMHz)

-I -ICL2

• STBY
This pin makes the MPU standby mode. In "Low" level, the
oscillation stops and the internal clock is stabilized to make
reset condition. To retain the contents of RAM at standby,
''0'' should be written into RAM enable bit (RAME). RAME
is the bit 6 of the RAM/port 5 control register at $0014. RAM
is disabled by this operation and its contents is sustained.
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
• Reset (RES)
This pin is used to reset the MPU from power OFF state
and to provide a startup procedure. During power-on, RES
pin must be held "Low" level for at least 20ms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM
and the data register of a port are not initialized during reset,
so their contents are unknown in this procedure.
To reset the MPU during operation, RES should be held
"Low" for at least 3 system-clock cycles. At the 3rd cycle
during "Low" level, all the address buses become "High". When
RES remains "Low", the address buses keep "High". If RES
becomes "High", the MPU starts the next operation.
(I) Latch the value of the mode program pins;MPo and MP •.

= 10pF-22pF + 20%

EXTALI---+-...,

EXT AL pin is drivable with the external clock of 45 to
50% duty, and one fourth frequency of the external clock
is produced in the LSI. The external clock frequency should
be less than four times of the maximum operable frequency.
When using the external clock, XTAL pin should be open.
Fig. 12 shows examples of connection circuit. The crystal and
CLI , CL2 should be mounted as close as possible to XT AL
and EXTAL pins. Any line must not cross the line between the
crystal oscillator and XTAL, EXTAL.

CL 1

(a) Crystal Interface
XTALf--- N,C.
EXTALt--- so it provides an enable bit to
Bit 0 and 1 of the RAM port S control register at $0014. Refer
to "RAM/PORT S CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or
SIO' is generated, the CPU produces internal interrupt signal
(IRQ3). IRQ3 functions just the same as IRQ I or IRQ2 except
for its vector address. Fig. 13 shows the block diagram of the
interrupt circuit.
•

Table 1 Interrupt Vector Memory Map
Priority
Highest

Lowest

362

Vector
MSB
FFFE
FFEE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFEC
FFEA
FFFO

LSB
FFFF
FFEF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFED
FFEB
FFF1

Interrupt
RES
TRAP
NMI
SWI (Software Interrupt)
IRQ I
ICI (Timer 1 Input Capture)
OCI (Timer 1 Output Compare 1, 2)
TOI (Timer 1 Overflow)
CMI (Timer 2 Counter Match)
IRQ 2
SIO (RDRF+ORFE+TDRE)

_HITACHI

-----------------------HD6303X,HD63A03X,HD63B03X
Each Register's Interrupt

Enable Flag
"1"; Enable. "0"; Disable
..-~

iROi

--

11m2

Condition

Code
Register

.......

ICF

ICI

"O";Enable

",";Disable

....

OCF'

I-MASK

~

--0- r-'

OCF2

TOI

TOF
IRQ,

CMI

.-.:.

CMF
RDRF

--0ORFE
TORE

""".-.:

--0-

Interrupt

~ Signal

Request

~
Sleep

J

Edge
Detective

Cancel
Signal

Circuit

I

Addre.. Error

Op Code Error
Detective Circuit

TRAP

SWI

Figure 13 Interrupt Circuit Block Diagram

• Mode Program (MP o, MP,I
To operate MPU. MP o pin should be connected to "High"

This signal, usually be in read state ("High"), shows whether
the MPU is in read ("High") or write ("Low") state to the
peripheral or memory devices. This can drive one TTL load
and 30pF capacitance.

9 liS can be stretched.
During internal address space access or nonvalid memory
access, MR is prohibited internally to prevent decrease of operation speed. Even in the halt state, MR can also stretch "High"
period of system clock to allow peripheral devices to access
low-speed memories. As this signal is used also as P 52 , an enable
bit is provided at bit 2 of the RAM/port 5 control register at
$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for
more details.

•

RD,WR

•

•

Load Instruction Register (LIR)

level and MP, should be connected to "Low" level (refer to
Fig. 15).
•

ReadlWrite (R/W)

These signals show active low outputs when the CPU is
reading/writing to the peripherals or memories. This enables
the CPU easy to access the peripheral LSI with RD and WR
input pins. These pins can drive one TTL load and 30pF capacitance.
This signal shows the instruction opecode being on data
bus (active low). This pin can drive one TTL load and 30pF
capacitance.

• Memory Ready (MR; P s2 1

This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. During
this signal being in "High", the system clock operates in normal
sequence. But this signal in "Low", the "High" period of the
system clock will be stretched depending on its "Low" level
duration in integral multiples of the cycle time. This allows the
CPU to in terface with low-speed memories (see Fig. 2). Up to

•

Halt (HALT; P S3 )

This is an input control signal to stop instruction execution
and to release buses free. When this signal switches to "Low",
the CPU stops to enter into the halt state after having executed
the present instruction. When entering into the halt state, it
makes BA (P74) "High" and also an address bus, data bus, RlJ,
WR, R/W in high impedance. When an interrupt is generated
in the halt state, the CPU uses the interrupt handler after the
halt is cancelled. When halted during the sleep state, the CPU
keeps the sleep state, while BA is "High" and releases the buses.
Then the CPU returns to the previous sleep state when the
HALT signal becomes "High ". The same thing can be said when
the CPU is in the interrupt wait state after having executed the
WAI instruction.
• Bus Available (BA)

This is an output control signal which is normally "Low"
but "High" when the CPU accepts HALT and releases the buses.
The H06800 and H06802 make BA "High" and release the
buses at WAI execution, while the HD6303X doesn't make

HITACHI

363

HD6303X,HD63A03X,HD63B03X----------------------BA "High" under the same condition. But if the HALT becomes
"Low" when the CPU is in the interrupt wait state after having
executed the WAI, the CPU makes BA "High" and releases the
buses. And when the HALT becomes "High", the CPU returns
to the interrupt wait state.
• PORT

The HD6303X provides three I/O ports. Table 2 gives the
address of ports and the data direction register and Fig. 14
the block diagrams of each port.

(DDR) of port 2 is responsible for I/O state. It provides two
bits; bit 0 decides the I/O direction of p.o and bit 1 the I/O
direction of P2I to P., ("0" for input, "I" for output).
Port 2 is also used as an I/O pin for the timers and the
SCI. When used as an I/O pin for the timers and the SCI, port
2 except p.o automatically becomes an input or an output
depending on their functions regardless of the data direction
register's value.
Port 2 Data Direction Register

Table 2 Port and Data Direction Register Address
Port
Port 2
Port 5
Port 6

5

6

Port Address

Data Direction Register

$0003
$0015
$0017

$0001

-

4

3

2

1

0

A reset clears the DDR of port 2 and configures port 2 as an
input port. This port can drive one TTL and 30pF. In addition,
it can produce 1rnA current when Vout = 1.5V to drive directly
the base of Darlington transistors.

$0016

• Port 2

An g·bit input/output port. The data direction register

Port Write Signal
Data Bus

Data Bus

2,.-+-___..r-.......J

Timer 1.
SCI Output

Port Read Signal

Tri~state

Control

...L.

Timer 1, 2, _ _ _ _ _ _ _ _ _<
SCI Input

Timer 1 Input
(P" only)

Port 2

_--------<

Port Read Signal

...L

Data Bus _ _ _.r-........_ . £

Port 5
Figure 14 Port Block Diagram
• Port 5

• Ao-A ls

An 8·bit port for input only. The lower four bits are also
usable as input pins for interrupt, MR and HALT.

These pins are address bus and can drive one TTL load and
90pF capacitance respectively.

• Port6

• RAM/PORT 5 CONTROL REGISTER

An 8·bit I/O port. This port provides an 8·bit DDR corre·
sponding to each bit and can specify input or output by the
bit ("0" for input, "I" for output). This port can drive one
TTL load and 30pF. A reset clears the DDR of port 6. In
addition, it can produce ImA current when Vout = 1.5V to
drive directly the base of Darlington transistors.
• BUS
• 0 0 -0 7
These pins are data bus and can drive one TTL load and
90pF capacitance respectively.

The control register located at $0014 controls on-chip
RAM and port 5.
RAM/Port 5 Control Register
7

6

5

4

321

0

Bit 0, Bit 1 IRQI, IRQ. Enable Bit (lRQI E, IRQ.E)

When using Pso and PSI as interrupt pins, write "I" in
these bits. When "0", the CPU doesn't accept an external

364

•

HITACHI

-----------------------HD6303X,HD63A03X,HD63B03X
interrupt or a sleep cancellation by the external interrupt.
These bits become ''0'' during reset.

Vee

Bit 2 Memory Ready Enable Bit (MRE)
When using P S2 as an input for Memory Ready signal, write
"1" in this bit. When ''0''. the memory ready function is prohibited. This bit becomes "'" during reset.

E

Rl5
WR

D

Bit 3 Halt Enable bit (HL TE)
When using P S3 as an input for Halt signal, write "'" in this
bit. When "0", the halt function is prohibited. This bit becomes
"'" during reset.

R/W

liES
S'fiiY

OR

H06303X

NMI

BA

Port 2

81/0 lines
Timer 1, 2
SCI

8 Data Bus

PortS

Bit 4, Bit 5 Not Used.

8/Rr[,~~

Bit 7 Standby Power Bit (STBY PWR)
When Vee is not provided in standby mode. this bit is
cleared. This is a flag for both read/write by software. If this bit
is set before standby mode. and remains set even after returning
from standby mode, Vee voltage is provided during standby
mode and the on-chip RAM data is valid.

16 Address
Bus

MR. HALT
Port 6

Bit 6 RAM Enable (RAME)
On-chip RAM can be disabled by this control bit. The
MPU Reset sets "1" at this bit and enables on-chip RAM
available. This bit can be written "I" or ''0'' by software.
When RAM is in disable condition (=logic "0"), on-chip RAM
is invalid and the CPU can read data from external memory.
This bit should be "0" at the beginning of standby mode to
protect on-chip RAM data.

81/0 LInes

Figure 15 Operation Mode
• MEMORY MAP
The MPU can address up to 65k bytes. Fig. 16 gives memory
map of HD6303X. 32 internal registers use addresses from "00"
as shown in Table 3.

Table 3 Internal Register
Address
00
01
02'
03
04'
05
06"
07"
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16

Registers

RIW'"

-

-

-

W

$FC

R/W

Undefined

Port 2 Data Direction Register
Port 2

-

-

-

-

-

Timer Control/Status Register 1
Free Running Counter ("High")
Free Running Counter ("Low")
Output Compare Register 1 ("High")
Output Compare Register 1 ("Low")
Input Capture Register ("High")
Input Capture Register ("Low")
Timer Control/Status Register 2
Rate. Mode Control Register
Tx/Rx Control Status Register
Receive Data Register
Transmit Data Register
RAM/Port 5 Control Register
Port 5
Port 6 Data Direction Register

_HITACHI

RIW
RIW
RIW
RIW
RIW
R
R
RIW
R/W
RIW
R
W
RIW
R
W

Initialize at RESET

-

$00
$00
$00
$FF
$FF
$00
$00
$10
$00
$20
$00
$00
$7C or $FC

$00
(continued)

365

HD6303X,HD63A03X,HD63B03X-----------------------Table 3 Internal Register
Registers

Address
17
18*
19
lA
18
lC
10
lE
IF**

Port 6

RIW***

Initialize at RESET

RIW

Undefined

RIW
RIW
RIW
W
RIW

$FF
$FF
$20
$FF
$00

-

Output Compare Register 2 ("High")
Output Compare Register 2 ("Low")
Timer Control/Status Register 3
Time Constant Register
Timer 2 Up Counter

-

-

-

Test Register

-

-

* External Address.
** Test Register. Do not access to this-register .

.*.

R

: Read Only Register

W : Write Only Register
RIW: Re.dlWrite Register

and incremented by system clock. The counter value is readable
by software without affecting the counter. The counter is
cleared by reset.
When writing to the MSB byte ($09), the CPU writes the
preset value ($FFF8) into the counter (address $09, $OA)
regardless of the write data value. But when writing to the
LSB byte ($OA) after MSB byte writing, the CPU write not
only LSB byte data into lower 8 bit, but also MSB byte data
into higher 8 bit of the FRe.
The counter will be as follows when the CPU writes to it
by double store instructions (STD, STX etc.).

H06303X
Expanded Mode
Internal*

Registers
External
Memory

Space
Internal
RAM

$09 Write

$OAWrite

External
Memory

Space

Counter value

$FFF8

$5AF3

In the case of the CPU write ($5AF3) to the FRC

Figure 17 Counter Write Timing

* Excludes the following addresses

which may be used externally:
$02, $04, $06, $07, $18.

Figure 16 H06303X Memory Map
• TIMER 1
The HD6303X provides a 16-bit programmable timer which
can measure an input waveform and generate two independent
output waveforms. The pulse widths of both input/output
waveforms vary from microseconds to seconds.
Timer I is configurated as fol1ows (refer to Fig. 18).
Control/Status Register I (8 bit)
Control/Status Register 2 (7 bit)
Free Running Counter (\6 bit)
Output Compare Register I (16 bit)
Output Compare Register 2 (16 bit)
Input Capture Register (\ 6 bit)

• Output Compare Register (OCR)
($OOO8.$OOOC; OCR1) ($0019.$001A;OCR2)
The output compare· register is a 16-bit read/write register
which can control an output waveform. It is always compared
with the FRC.
When data matches, output compare flag (OCF) in the timer
control/status register (TCSR) is set. If an output enable bit
(OE) in the TCSR2 is "I", an output level bit (OLVL) in the
TCSR will be output to bit 1 (Tout I) and bit 5 (Tout 2) of
port 2. To control the output level again by the next compare, a
change is necessary for the OCR and OLVL. The OCR is set to
$FFFF at reset. The compare function is inhibited for a cycle
just after a write to the OCR or to the upper byte of the
FRC. This is to set the 16-bit value valid in the register for
compare. In addition, it is because $FFF8 is set at the next
cycle of the CPU's MSB byte write to the FRC.
* For data write to the FRC or the OCR, 2-byte transfer
instruction (such as STX etc.) should be used.
•

•

Free-Running Counter (FRC) ($0009 : OOOA)
The key timer element is a l6-bit free-running counter driven

366

•

Input Capture Register (lCR) ($0000: OOOE)
The input capture register is a l6-bit read only register which
stores the FRC's value when external input signal transition

HITACHI

-----------------------HD6303X,HD63A03X,HD63B03X
generates an input capture pulse. Such transition is defined by
input edge bit (IEDG) in the TCSRI .
In order to input the external input signal to the edge
detecter, a bit of the DDR corresponding to bit 0 of port 2
should be cleared ("0"). When an input capture pulse occures
by input transition at the next cycle of CPU's high·byte read of
the lCR, the input capture pulse will be delayed by one cycle.
In order to ensure the input capture operation, a CPU read of
the ICR needs 2·byte transfer instruction. The input pulse width
should be at least 2 system cycles. This register is cleared
($0000) during reset.
•

Timer Control/Status Register 1 (TCSR 1) ($0008)

The timer control/status register 1 is an 8-bit register. All bits
are readable and the lower 5 bits are also writable. The upper 3
bits are read only which indicate the following timer status.
Bit 5 The counter value reached to $0000 as a result of
counting-up (TOF).
Bit 6 A match has occured between the FCR and the OCR 1
(OCFI).
Bit 7 Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are each bit descriptions.
Timer Control/Status Register 1

the OCRI ($OOOB or $OOOC) following the TCSRI or
TCSR2 read.
ICF Input Capture Flag
This read only bit is set when an input signal of
port 2, bit 0 makes a transition as defined by IEDG and
the FRC is transferred to the ICR. Cleared when reading
the MSB byte ($OOOOD) of the ICR follOWing the
TCSRI or TCSR2 read.

Bit 7

•

Timer Control/Status Register 2 (TCSR2) ($OooF)

The timer control/status register 2 is a 7-bit register. All bits
are readable and the lower 4 bits are also writable. But the
upper 3 bits are read.(mly which indicate the following timer
status.
Bit 5 A match has occured between the FRC and the OCR2
(OCF2).
Bit 6 The same status flag as the OCFI flag of the TCSRl,
bit 6.
Bit 7 The same status flag as the ICF flag of the TCSRI, bit 7.
The followings are each bit descriptions.
Timer Control/Status Register 2

76543210
IICF IOCF110CF21 - fOClfLVL1 DE21 D~$OOOF

3

Bit 0

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

OLVL1 Output Levell
OLVL! is transferred to port 2, bit I when a match
occurs between the counter and the OCRI. If OEI,
namely, bit 0 of the TCSR2, is set to "I", OLVL! will
appear at bit I of port 2.
IEDG Input Edge
This bit determines which rising edge or falling of
input signal of port 2, bit 0 will trigger data transfer
from the counter to the ICR. For this function, the
DDR corresponding to port, 2, bit 0 should be cleared
beforehand.
IEDG=O, triggered on a falling edge
("High" to "Low")
IEDG= I, triggered on a rising edge
("Low" to "High")
ETOI Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQ3) by
TOI interrupt is enabled. When cleared, the interrupt is
inhibited.
EOCll Enable Output Compare Interrupt 1
When this bit is set, an internal interrupt (IRQ3) by
OCII interrupt is enabled. When cleared, the interrupt
is inhibited.
EICI Enable Input Capture Interrupt
When this bit is set, an internal interrupt (IRQ3) by
ICI interrupt is enabled. When cleared, the interrupt is
inhibited.
TOF Timer Overflow Flag
This read only bit is set when the counter increments from $FFFF by 1. Cleared when the counter's
MSB byte ($0009) is ready by the CPU following the
TCSRI read.
OCF 1 Output Compare Flag 1
This read only bit is set when a match occurs between the OCRI and the FRC. Cleared by writing to

•

OEl Output Enable 1
This bit enables the OLVL! to appear at port 2, bit
I when a match has occurred between the counter and
the output compare register I. When this bit cleared, bit
I of port 2 will be I/O port. When set, it will be an
output of OLVL! automatically.
Bit 1 OE2 Output Enable 2
This bit enables the OLVL2 to appear at port 2, bit
5 when a match has occurred between the counter and
the output compare register 2. When this bit cleared,
port 2, bit 5 will be I/O port. When set, it will be an
output ofOLVL2 automatically.
Bit 2 OL VL2 Output Level 2
OLVL2 is transferred to port 2, bit 5 when a match
has occurred between the counter and the OCR2. If'
OE2, namely bit 5 of the TCSR2, is set to "I", OLVL2
will appear at port 2, bit 5.
Bit 3 EOCI2 Enable Output Compare Interrupt 2
When this bit is set, an internal interrupt (IRQ3) by
OCl2 interrupt is enabled. When cleared, the interrupt
is inhibited.
Bit 4 Not Used
Bit 5 OCF2 Output Compare Flag 2
This read-only bit is set when a match has occurred
between the counter 'and the OCR2. Cleared when
writing to the OCR2 ($0019 or $OOIA) following the
TCSR2 read.
Bit 6 OCFl Output Compare Flag 1
Bit 7 ICF Input Capture Flag
OCFI and ICF addresses are partially decoded.
CPU read of the TCSRI/TCSR2 makes it possible to
read OCFI and ICF into bit 6 and bit 7.
Both the TCSRI and TCSR2 will be cleared during reset.
(Note) If OEI or OE2 is set to "I" before the first output
compare match occurs after reset restart, bit I or bit 5
of port 2 will produce ''0'' respectively.

HITACHI

367

HD6303X,HD63A03X,HD63B03X-----------------------

Figure 18 Timer 1 Block Diagram

(Note) Because the set condition of ICF precedes its reset
condition, ICF is not cleared when the set condition
and the reset condition occur simultaneously. The
same phenomenon applies to OCF I, OCF2 or TOF
respectively.
• TIMER2
In addition to the timer I, the HD6303X provides an S·bit
reloadable timer, which is capable of counting the external
event. This timer 2 contains a timer output, so the MPU can
generate three independent waveforms (refer to Fig. 19).
The timer 2 Is configured as follows:
Control/Status Register 3 (7 bit)
S·bit Up Counter
Time Constant Register (S bit)
• Timer 2 Up Counter (nCNT) ($0010)
This is an S·bit up counter which operates with the clock
decided by CKSO and CKSI of the TCSR3. The counter is
always readable without affecting itself. In addition, any value
can be written to the counter by software even during counting.
The counter is cleared when a match occurs between the
counter and the TCONR or during reset.
If a write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the
write data to the counter.

368

•

• Time Conltllnt Regllter (TCONR) ($001C)
The time constant register is an S·bit write only register. It
is always compared with the counter.
When a match has occurred, counter match flag (CMF) of
the timer control status register 3 (TCSR3) Is set and the value
selected by TOSO and TOSI of the TCSR3 will appear at port 2,
bit 6. When CMF is set, the counter will be cleared simultane·
ously and then start counting from SOO. This enables regular
interrupts and waveform outputs Without any software support.
The TCONR is set to "SFF" during reset.
• Timer Control/Stetul Regilter 3 (TCSR3) ($001B)
The timer control/status register 3 is a 7·bit register. AU bits
are readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.
Timer Control/Status Register 3

78543210
ICMFIECMII-I T2E ITOSllTOSolCKSllCKSol $001e

HITACHI

-----------------------HD6303X,HD63A03X,HD63B03X

HD6303X Internal Data Bus
~---Timerl

FRC

1----<-- Port 2
Bit 7

~+_--4-------<-... Port 2

BitS

IRQ3
Figure 19 Timer 2 Block Diagram
Bit 0
Bit 1

CKSO Input Clock Select 0
CKSI Input Clock Select 1
Input clock to the counter is selected as shown in
Table 4 depending on these two bits. When an external
clock is selected, bit 7 of port 2 will be a clock input
automatically. Timer 2 detects the rising edge of the
external clock and increments the counter. The external
clock is countable up to half the frequency of the
system clock.
Table 4 Input Clock Select

CKSI
0
0
1
1

CKSO
0
1
0
1

is selected as an input clock to the up counter. the CPU should not
write to the FRC of the timer 1.

TOSO Timer Output Select 0
TOS1 Timer Output Select 1
When a match occurs between the counter and the
TCONR timer 2 outputs shown in Table 5 will appear at
port 2, bit 6 depending on these two bits. When both
TOse and TOSI are "0", bit 6 of port 2 will be an I/O
port.

•

TOSI
0
0
1
1

TOSO
0
1
0
1

Timer Output
Timer Output Inhibited
Toggle Output *
Output "0"
Output "I"

.. When a match occurs betvveen the counter and the TeONR, timer 2
output level is reversed. This leads to production of a square wave with
50% duty to the external without any software support.

Bit 4

Input Clock to the Counter
E clock
E clock/B*
E clock/12B*
External clock

.. These clocks come from the FAC of the timer 1. If one of these clocks

Bit 2
Bit 3

Table 5 Timer 2 Output Select

T2E Timer 2 Enable Bit
When this bit is cleared, a clock input to the up
counter is prohibited and the up counter stops. When set
to "I", a clock selected by CKS J and (,KSO (Table 4)
is input to the up counter.
(Note) P26 produces "0" when T2E bit cleared and timer 2 set
in output enable condition by TOSI or TOSO. It also
produces "0" when T2E bit set "I" and timer 2 set in
output enable condition before the first counter match
occurs.
Bit 5 Not Used
Bit 6 ECMI Enable Counter Match Interrupt
When this bit is set, an internal interrupt (IRQ3) by
CMI is enabled. When cleared, the interrupt is inhibited.
Bit 7 CMF Counter Match Flag
This read only bit is set when a match occurs between
the up counter and the TCONR. Cleared by a software
write (unable to write "I" by software).
Each bit of the TCSR3 is cleared during reset .

HITACHI

369

HD6303X,HD63A03X,HD63B03X-----------------------• SERIAL COMMUNICATION INTERFACE (SCI)
The HD6303X SCI contains two operation modes; one is an
asynchronous mode by the NRZ format and the other is a
clocked synchronous mode which transfer data synchronizing
with the serial clock.
The serial interface is configured as follows:
Control/Status Register (TRCSR)
Rate/Mode Control Register (RMCR)
Receive Data Register (RDR)
Receive Data Shift Register (RDSR)
Transmit Data Register (TOR)
• Transmit Data Shift Register (TDSR)
The serial I/O hardware requires an initialization by software
for operation. The procedure is usually as follows:
I) Write a desirable operation mode into each correspond·
ing control bit of the RMCR.
2) Write a desirable operation mode into each correspond·
ing control bit of the TRCSR.
When using bit 3 and 4 of port 2 for serial I/O only, there is
no problem even if TE and RE bit are set. But when setting the
baud rate and operation mode, TE and RE should be "0". When
clearing TE and RE bit and setting them again, more than 1 bit
cycle of the current baud rate is necessary. If set in less than 1
bit cycle, there may be a case that the internal transmit/receive
initialization fails.
•

Asynchronous Mode

An asynchronous mode contains the following two data
formats:
I Start Bit + 8, Bit Data + 1 Stop Bit
I Start Bit + 9 Bit Data + 1 Stop Bit
In addition, if the 9th bit is set to "I" when making 9
bit data format, the format of
I Start bit + 8 Bit Data + 2 Stop Bit
is also transferred.
Data transmission is enabled by setting TE bit of the TRCSR,
then port 2, bit 4 will become a serial output independently of
the corresponding DDR.
,
For data transmit, both the RMCR and TRCSR should be
set under the desirable operating conditions. When TE bit is
set during this process, 10 bit preamble will be sent in 8·bit data
format and II bit In 9.\)lt data format. When the preamble is
produced, the internal synchronization will become stable and
the transmitter Is ready to act.
The conditions at this stage are as follows.
I) If the TDR is empty (TDRE"I), consecutive I '. are
produced to Indicate the idle state.
2) If the TDR contains data (TDRE=O), data is sent to the
transmit data shift register and data transmit starts.
During data transmit, a start bit of "0" Is transmitted first.
Then 8·blt or 9·blt data (starts from bit 0) and a stop bit of "1"

370

•

are transmitted .
When the TDR is "empty", hardware sets TDRE flag bit. If
the CPU doesn't respond to the flag in proper timing (the TDRE
is in set condition till the next normal data transfer starts from
the transmit data), "I" is transferred instead of the start bit "0"
and continues to be transferred till data is provided to the data
register. While the TDRE is "1", "0" is not transferred.
Data receive is possible by setting RE bit. This makes port 2,
bit 3 be a serial input. The operation mode of data receive is
decided by the contents of the TRCSR and RMCR. The first
"0" (space) synchronizes the receive bit flow. Each bit of the
following data will be strobed in the middle. If a stop bit is not
.. I", a framing error assumed and ORFE is set
When a framing error occurs, receive data is transferred to
the receive data register and the CPU can read error-generating
data. This makes it possible to detect a line break.
If the stop bit is "I", data is transferred to the receive data
register and an interrupt flag RDRF is set. If RDRF is still
set when receiving the stop bit of the next data, ORFE is set to
indicate overrun generation.
When the CPU read the receive data register as a response to
RDRF flag or ORFE flag after having read TRCS, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
When using an internal clock for serial I/O, the follow·
ings should be kept in mind.
Set CC I and CCO to "1" and "0" respectively.
A clock is generated regardless of the value of TE,
RE.
Maximum clock rate is E+16.
Output clock rate Is the same as bit rate.
When using an external clock for serial I/O, the follow·
ings should be kept in mind.
Set CCI and CCO in the RMCR to "I" and "I" reo
spectlvely.
The external clock frequency should be set 16 times
of the applied baud rate.
Maximum clock frequency Is that of the system
clock.
• Clocked Synchronoul Mode
In the clocked synchronous mode, data transmit is
synchronized with the clock pulse. The HD6303X SCI
provides functlona\1y independent transmitter and receiver
which makes fu\1 duplex operation possible In the asynchronous
mode. But in the clocked synchronous mode an SCI clock I/O
pin is only Pu , so the simultaneous receive and transmit
operation is not available. In this mode, TE and RE should
not be in set condition ("I ") simultaneously. Fig. 21 gives a
synchronous clock and a data format in the clocked synchro.
nousmode .

HITACHI

------------------------HD6303X,HD63A03X,HD63B03X

HD6303X Internal Data Bus

Tlmer1 FRC,
Ttmer2
Up Counter

Figure 20 Serial Communication Interface Block Diagram
Data transmit is realized by setting TE bit in the TRCSR.
Port 2, bit 4 becomes an output unconditionally independent
of the value of the corresponding DDR.
Both the RMCR and TRCSR should be set in the desirable
operating condition for data transmit.
When an external clock input is selected, data transmit is

performed under the TDRE flag "0" from port 2, bit 4, synchronizing with 8 clock pulses input from external to port 2,
bit 2.
Data is transmitted from bit 0 and the TDRE is set when the
transmit data shift register is "empty". More than 9th clock
pulse of external are ignored.

Transmit Direction

Synchronous

clock
Data

~NotValid

• Transmit data is produced from a falling edge of a synchronous clock to the next falling edge .

• Receive data is latched at the rising edge.

Figure 21

Clocked Synchronous Mode Format

When data transmit is selected to the clock output, the MPU
produces transmit data and synchronous clock at TDRE flag
clear.
Data receive is enabled by setting RE bit. Port 2, bit 3 will
be a serial input. The operating mode of data receive is decided
by the TRCSR and the RMCR.
If the external clock input is selected, RE bit should be
set when P22 is "High". Then 8 external clock pulses and
the synchronized receive data are input to port 2, bit 2
and bit 3 respectively. The MPU put receive data into the
receive data shift register by this clock and set the RDRF
flag at the termination of 8 bit data receive .. More than 9th
clock pulse of external input are ignored. When RDRF is
cleared by reading the receive data register, the MPU starts

•

receiving the next data. So RDRF should be cleared with P22
"High".
When data receive is selected to the clock output, 8 synchronous clocks are output to the external by setting RE bit. So receive data should be input from external, synchronously with
this clock. When the first byte data is received, the RDRF flag
is set. After the second byte, receive operation is performed and
output the synchronous clock to the external by clearing the
RDRF bit.

• Transmit/Receive Control Status Ragistar (TRCSR) (S0011)
The TRCSR is composed of 8 bits which are all readable. Bits
o to 4 are also writable. This register is initialized to $20 during
reset. Each bit functions as follows.

HITACHI

371

HD6303X,HD63A03X,HD63B03X-----------------------Transmit/Receive Control Status Register
76543210

IRORFIORFEITOREI RIE I RE ITIE I TE
Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

372

I

wu 1$0011

WU Wake-up
In a typical mUlti-processor configuration, the
software protocol provides the destination address at
the first byte of the message _ In order to make uninterested MPU ignore the remaining message, a wake-up
function is available_ By this, uninterested MPU can inhibit all further receive processing till the next message
starts_
Then wake-up function is triggered by consecutive
l' s with 1 frame length (10 bits for 8-bit data, 11 for
9-bit). The software protocol should provide the idle
time between messages.
By setting this bit, the MPU stops data receive till the
next message. The receive of consecutive" 1" with one
frame length wakes up and clears this bit and then the
MPU restarts receive operation. However, the RE flag
should be already set before setting this bit. In the
clocked synchronous mode WU is not available, so this
bit should not be set.
TE Transmit Enable
When this bit is set, transmit data will appear at port
2, bit 4 after one frame preamble in asynchronous mode,
while in clocked synchronous mode appear immediately.
This is executed regardless of the value of the cor·
responding DDR. When TE is cleared, the serial I/O
doesn't affect port 2, bit 4.
TIE Transmit Interrupt Enable
When this bit is set, an Internal Interrupt (IRQ3) is
enabled when TDRE (bit 5) is set. When cleared, the
interrupt is inhibited.
R E Receiva Enable
When set, a signal is input to the receiver from port
2, bit 3 regardless of the value of the DDR. When RE
is cleared, the soriall/O doesn't affect port 2, bit 3.
RIE Receive Inte~rupt Enable
When this bit is set, an internal interrupt, IRQ, is
enabled when RDRF (bit 7) or ORFE (bit 6) is set.
When cleared, the interrupt is inhibited.
TORE Transmit Data Registar Empty
TDRE is set when the TDR is transferred to the
transmit data shift register in the asynchronous mode,
while in clocked synchronous mode when the TDSR is
"empty". This bit is reset by reading the TRCSR and
writing new transmit data to the transmit data register.
TDRE Is set to "I" during reset.
OR FE Overrun Framing Error
ORFE is set by hardware when an overrun or a fram·
ins error Is generated (during data receive only). An
overrun error occurs when new receive data is ready to
be transferred to the RDR during RDRF still being set.
A framing error occurs when a stop bit is "0". But in

clocked synchronous mode, this bit is not affected. This
bit is cleared when reading the TRCSR, then the ROR,
or during reset.
Bit 7 RDRF Receive Data Register Full
RDRF is set when the RDSR is transferred to the
RDR. Cleared when reading the TRCSR, then the RDR,
or during reset.
(Note) When a few bits are set between bit 5 to bit 7 in the
TRCSR, a read of the TRCSR is sufficient for clearing
those bits. It is not necessary to read the TRCSR everytime to clear each bit.
• Transmit Rate/Mode Control Register (RMCR)
The RMCR controls the following serial I/O:
. Baud Rate
• Clock Source

• Data Format
• Port 2, Bit 2 Function

In addition, if 9-bit data format is set in the asynchronous
mode, the 9th bit is put in this register. All bits are readable and
writable except bit 7 (read only). This register is set to $00
during reset.
Transfer Rate/Mode Control Register
76543210

I

I Roe Toe I SS21 CC21 CCl Icco ISS1 I sso 1$0010
Bit 0
Bit 1
Bit 5

SSO}

SSl
SS2

Speed Select

These bits control the baud rate used for the SCI. Table
6 lists the available baud rates. The timer 1 FRC (SS2=0) and
the timer 2 up counter (SS2= I) provide the internal clock to the
SCI. When selecting the timer 2 as a baud rate source, it func·
tions as a baud rate generator. The timer 2 generates the baud
rate listed in Table 7 depending on the value of the TCONR.
(Note) When operating the SCI with internal clock, do not
perform write operation to the timer/counter which is
the clock source of the SCI.
Bit2
Bit 3
Bit 4

CCO}
CCl
CC2

Clock Control/Format Select·

These bits control the data format and the clock source
(refer to Table 8).
* CCO, CC 1 and CC2 are cleared during reset and the MPU
goes to the clocked synchronous mode of the external
clock operation. Then the MPU forces port 2, bit 2
In the clock input state. When using port 2, bit 2 as an
output port, the DDR of port 2 should be set to "I" and
CC 1 and CCO to "0" and "I" respectively.

_HITACHI

------------------------HD6303X,HD63A03X,HD63B03X
Table 6 SCI Bit Times and Transfer Rates
Asynchronous Mode

(1)

SS2

SSI

0

0

0
0

, f---_XTAL
SSO
E

2.4576MHz

4.0MHz

614.4kHz

1.0MHz

4.9152MHz
1.2288MHz

o !

E.,.16

26 "s/38400Baud

16"s/62500Baud

0

1

E.,.128

208"s/4800Baud

128"s/7812.5Baud

104.2 "s/9600Baud

1

0

E.,.1024

1.67ms/600Baud

1.024ms/976.6Baud

833.3"s/1200Baud

0

1

6.67ms/150Baud

4.096ms!244.1 Baud

3.333ms/300Baud

-

1
-

E.,.4096

1

-

*

*

*

13 "s/76800Baud

* When SS2 is "I", Timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N.
Baud Rate

f
32 (N+I)

f: input clock frequency to the)
timer 2 counter

(

N=O-255
(2) Clocked Synchronous Mode'

XTAL

4.0MHz

6.0MHz

8.0MHz

E

1.0MHz

1.5MHz

2.0MHz

SS2

SSl

SSO

0

0

0

E.,.2

0

0

1

E.,.16

0

1

0

E.,.128

0

1

1

E.,.512

1

-

-

-

2"s'bit

1.33"s'bit

l"s 'bit

16"s/bit

10.7"s,bit

8"sfbit

128"s'bit
512"s.·bit

85.3"s 'bit

64.us/bit

341"s 'bit

256"s/bit

**

**

**

* Bit rates in the case of internal clock operation. In the case of external clock operation, the external clock is
operatable up to DC - 1/2 system clock.

** The bit rate is shown as follows with the TCONR as N.
Bit Rate (IlS/bit)

= 4 (~+ 1)

(

f: input clock frequency to the)
timer 2 counter

N = 0 -255
Table 7 Baud Rate and Time Constant Register Example

-~~L

2.4576MHz

3.6864MHz

110
150
300
600
1200
2400
4800
9600
19200
38400

21127
63
31
15
7
3
1
0

32191
95
47
23
11
5
2

Baud Rate (Baud

4.0MHz
35207
103
51
25
12

4.9152MHz
43255
127
63
31
15
7
3
1
0

8.0MHz
7051207
103
51
25
12

* E/8 clock is input to the timer 2 up counter and E clock otherwise.

_HITACHI

373

HD6303X,HD63A03X,HD63B03X----------------------Table a
CC2
0
0
0
0
1
1
1
1

CCI
0
0
1
1
0
0
1
1

CCO
0
1
0
1
0
1
0
1

Format
a·bit data
a·bit data
a·bit data
a·bit data
a·bit data
9-bit data
9-bit data
9-bit data

SCI Format and Clock Source Control

Mode
Clocked Synchronous
Asynchronous
Asynchronous
Asynchronous
Clocked Synchronous
Asynchronous
Asynchronous
Asynchronous

Clock Source
External
Internal
Internal
External
Internal
Internal
Internal
External

Port 2, Bit 2
Input
Not Used··
Output"
Input
Output
Not Used""
Output"
Input

Port 2, Bit 3

J

Port 2, Bit 4

When the TRCSR, RE bit is "1",
bit 3 is used as a serial input.

When theTRCSR, TE bit is "1",
bit 4 is used as a serial output.

* Clock output regardless of the TRCSR, bit RE and TE.
** Not used for the SCI.
Bit 6

Bit 7

Toa Transmit Data Bit a
When selecting 9-bit data fonnat in the asynchron·
oU's mode, this bit is transmitted as the 9th data. In
transmitting 9-bit data, write the 9th data into this bit
then write data to the receive data register.
ROB Receive Data Bit a
When selecting 9-bit data fonnat in the asynchronous
Table 9

Timer
1

Timer
2

mode, this bit stores the 9th bit data. In receiving 9-bit
data, read this bit then the receive data register.
• TIMER, SCI STATUS FLAG
Table 9 shows the set and reset conditions of each status
flag in the timer 1, timer 2 and SCI.

Timer I, Timer 2 and SCI Status Flag

ICF

Set Condition
FRC ... ICR by edge input to P 2".

1.

OCFl

OCR1=FRC

2.
1.

OCF2

OCR2=FRC

2.
1.

TOF

FRC-$FFFF+l cycle

CMF

T2CNT=TCON R

RORF

Receive Shift Register

ORFE

1.
2.

SCI
TORE

1.
2.

3.

~

ROR

Framing Error (Asynchronous Mode)
Stop Bit = 0
Overrun Error (Asynchronous Mode)
Receive Shift Register'" ROR when
RORF=1
Asynchronous Mode
TOR .... Transmit Shift Register
Clocked Synchronous Mode
Transmit Shift Register is "empty"
RtS=O

(Notel 1.... ; transfer
2. For example; "ICRH" means High byte of ICR.

374

_HITACHI

2.
1.
2.
1.
2.
1.
2.
1.
2.

Reset Condition
Read the TCSR 1 or TCSR2 then ICRH,
when ICF=1
"FfES=0
Read the TCSR 1 or TCSR2 then write to the
OCRI H or OCR 1 L, when OCFl = 1
"FfES=0
Read the TCSR2 then write to the OCR2H or
OCR2L, when OCF2=1
m=O
Read the TCSRI then FRCH, when TOF=1
m=O
Write "0" to CM F , when CM F = 1
RES=o
Read the TRCSR then ROR, when RORF=1
m=O
Read the TRCSR then ROR, when ORFE=1
RES=O

Read the TRCSR then write to the TOR,
when TORE=1

------------------------HD6303X,HD63A03X,HD63B03X
•

for a system with no need of the HD6303X's consecutive
operation.

LOW POWER DISSIPATION MODE

The HD6303X provides two low power dissipation modes;
sleep and standby.

• Standby Mode
The HD6303X stops all the clocks and goes to the reset
state with STBY"Low". In this mode, the power dissipation is
reduced conspicuously. All pins except for the power supp\y.
the STBY and XTAL are detached from the MPU internaUy
and go to the high impedance state.
In this mode the power is supplied to the HD6303X, so
the contents of RAM is retained. The MPU returns from this
mode during reset. The foUowings are typical usage of this
mode.
Save the CPU information and SP contents on RAM by NMI.
Then disable the RAME bit of the RAM control register and set
the STBY PWR bit to go to the standby mode. If the STBY
PWR bit is stiIl set at reset start, that indicates the power is
supplied to the MPU and RAM contents are retained properly.
So system can restore itself by returning their pre·standby informations to the SP and the CPU. Fig. 22 depicts the timing at
each pin with this example.

• Sleep Mode
The MPU goes t.o the sleep mode by SLP instruction execu·
tion. In the sleep mode, the CPU stops its operation, while the
registers' contents are retained. In this mode, the peripherals
except the CPU such as timers, SCI etc. continue their functions. The power dissipation of sleep-condition is one fifth that
of operating condition.
The MPU returns from this mode by an interrupt, RES or
STBY; it goes to the reset state by RES and the standby mode
by STBY. When the CPU acknowledges an interrupt request, it
cancels the sleep mode, returns to the operation mode and
branches to the interrupt routine. When the CPU masks this
interrupt, it cancels the sleep mode and executes the next
instruction. However, for example if the timer 1 or 2 prohibits
a timer interrupt, the CPU doesn't cancel the sleep mode be·
cause of no interrupt request.
This sleep mode is effective to reduce the power dissipation

Vee

HD6303X

s'

RES

I

I

I
I

---II

----1jl---\

fWL'-11111

I
I

I

I

r:-

~:

----If

I!W"-IIIIII
I

I

I

~

Save registers
RAM/Port 5 Control
Register Set

I

~

Oscillator
Start Time
~

Restart

Figure 22 Standby Mode Timing
•

TRAP FUNCTION

The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruc·
tion from non·memory space. The TRAP prevents the system·
burst caused by noise or a program error.
• Op Code Error
When fetching an undefined op code, the CPU saves CPU
registers as weU as a normal interrupt and branches to the TRAP
($FFEE. $FFEF). This provides the priority next to reset.

• Address Error
When an instruction fetch is made from internal register
($OOO(}-$OO\ F), the MPU generates an interrupt as well as an
op code error. But on the system with no memory in its external memory area, this error processing is not applicable if
an instruction fetch is made from the external non-memory

$

area.
This processing is available only for an instruction fetch and
is not applicable to the access of normal data read/write.
(Note) The TRAP interrupt provides a retry function different·
ly from other interrupts. This is a program flow return
to the address where the TRAP occurs when a sequence
returns to a main routine from the TRAP interrupt
routine by R TI. The retry can prevent the system burst
caused by noise etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration is
necessary in programming.
•

INSTRUCTION SET

The HD6303X provides object code upward compatible
with the HD680 I to utilize aU instruction set of the
HMCS6800. It also reduces the execution times of key instruc·

HITACHI

375

HD6303X.HD63A03X.HD63B03X----------------------tions for throughput improvement.
Bit manipulation instruction, change instruction of the
index register and accumulator and sleep instruction are also
added.
The foDowings are explained here.
CPU Programming Model (refer to Fig. 23)
Addressing Mode
Accumulator and Memory Manipulation Instruction
(refer to Table 10)
New Instruction
Index Register and Stack Manipulation Instruction
(refer to Table II)
Jump and Branch Instruction (refer to Table 12)
Condition Code Register Manipulation
(refer to Table 13)
Op Code Map (refer to Table 14)
• Programming Model

Fig. 23 depicts the HD6303X programming mode\. The
double accumulator D consists of accumulator A and B, so
when using the accumulator D, the contents of A and Bare
destroyed.

In this addressing mode, the second byte of an instruc·
tion shows the address where a data is stored. 256 bytes (SO
through S255) can be addressed directly. Execution times
can be reduced by storing data in this area so it is recommended
to make it RAM for users' data area in configurating a system.
This is a 2-byte instruction, while 3 byte with regard to AIM,
OIM,EIM and TIM.
Extended Addressing

In this mode, the second byte shows the upper 8 bit of the
data stored address and the third byte the lower 8 bit. This
indicates the absolute address of 3 byte instruction in the
memory.
Indexed Addressing

The second byte of an instruction and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM
and TIM, the third byte of an instruction and the lower 8 bits
of the index register are added.
This carry is added to the upper 8 bit of the index register
and the result is used for addressing the memory. The modified
address is retained in the temporary address register, so the con·
tents of the index register doesn't change. This is a 2·byte
instruction except AIM, OIM, ElM and TIM (3.byte instruc·
tion).
Implied Addressing

I"
I"
I"

SP

PC
1

01

Ind.. Aq+lllrtxl

01

$I_k Po,n,eI' tsP!

01

'"'OlrMl Coun'" ,PCI

Relative Addressing

0

~
'

H

I

N Z

V C

-

An instruction itself specifies the address. That is, the
instruction addresses a stack pointer, index register etc. This is a
one-byte instruction.

Cond,"_

The second byte of an instruction and the lower 8 bits of
the program counter are added. The carry or borrow is added to
the upper 8 bit. So addressing from -126 to +129 byte of the
current instruction is enabled. This is a 2·byte instruction.
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with the help
of CLI and SEI instructions, more than 2 cycles are
necessary between the eLI and SEI instructions. For
example, the following program (a) (b) don't accept the
IRQ but (c) accepts it.

Co"'''''''''' ICCAI

c.r."JIor,_"om MS.
()IIerllow

Z.,o
. . . .1'~

I"""YDI

H.II C•• v IFrom

.,1 3)

Figure 23 CPU Programming Model
• CPU Addressing Mode

The HD6303X provides 7 addressing modes. The addressing
mode is decided by an instruction type and code. Table 10
through 14 show addressing modes of each instruction with
the execution times counted by the machine cycle.
When the clock frequency is 4 MHz, the machine cycle time
becomes microseconds directly.

CLI
SEI

eLI
NOP
SEI

eLI
NOP
NOP
SEI

(a)

(b)

(c)

Accumulator (ACeX) Addressing

Only an accumulator is addressed and the accumulator A or
B is selected. This is a one·byte instruction.
Immediate Addressing

This addressing locates a data in the second byte of an
instruction. However, LDS and LDX locate a data in the second
and third byte exceptionally. This addressing is a 2 or 3·byte
instruction.

The same thing can be said to the TAP instruction
instead of the eLI and SEI instructions.

Direct Addressing

376

•

HITACHI

------------------------HD6303X,HD63A03X,HD63B03X
Table 10 Accumulator, Memory Manipulation Instructions

Condition Code

Addressing Moeles

Operations

Mnemonic

IMMED.

INDEX

DIRECT

Register

EXTEND

-

#

ADDA

' 8B

2

2 98

ADDB

CB

2

2

DB 3

2

EB

4

2

FB

4

3

Add Double

ADDD

C3

3

3

03

2 E3

5

2

F3

5

3

Add Accumulators

ABA

Add With Carry

ADCA

OP

Add

AOCB
ANDA

AND

Bn Test

Clear

-

#

OP

3

2

4

89

2

2 99

3

AB 4

2 BB

4

3

A+M-A

B+M-S

OP

A

C9

2

2

09

3

~2 2 .94

3

4

2 B9

2

E9

4

2

2

A4

4

2 B4

F9

I

1

B+M'M+l-A' B

4

3

A+M+C-A

t_"_
4

3
3

A·M-A

04

3

2

E4

4

2

F4

4

3

B·M-B

BITA

85

2

2 95

3

2

A5

4 2

B5

4

3

A·M

BIT B

C5

2 2 05 3 2 E5

~ ~ "- - - ~M
OO-M

4 2 F.!;_
6F "'5-2 7F 5 3

CLRA

4F

1 1 00- A

CLRB

5F

1

81

CMPB

Cl

CBA

2
·2

2 91

3

2

AI

2 Bl

4

3

2

3

2

El 14 2 Fl

4

3

73

6

3

01

4

11
63

6

2

43
53

(Noga.e)

NEGA
NEG8

Decimal Adjust. A

DAA

Decrement

DEC

60

6

2 70

6

6

2

7A

6

1
1

A-B

1

A-A

1

8 -8
OO-M-+M

3

I
6A

1 1

M-M

COMA
NEG

1 00 - B
A-M
BOoM

COMB
Complement. 2's

40

1 1 OO-A-A

50

1 1 00-8-8

19

2 1 characters

Converts binary add of BCD
Into BCD form.t

M-l-M

3

DECA

4A

1 1 A -1- A

DECa

5A

1

3

A(!) M-A

F8

4

3

a (!) M- 8

2 7C

6

3

M+l-M

2

B8

E8

4

2

6C

6

88

2

2 98

3

2

A8

EORa

C8

2

2

08

3

2

INC

4

4

EORA

1 8-1-8

INCA

4C

1.1

A+l-A

INCB

5C

1 1

Load

LDAA

86

2

2 96

A6

4

2

86

4

3

B "- B
M-A

Accumulator

LDAB

C6

2

2 06 3 2 E6

4

2

F6

4

3

M-B

LOIId Double
Accumulator

LDD

CC

3 3

Multiply Unsigned

MUL

OR, Inclusive

ORAA

8A

ORAB

CA 2

Push Data

PSHA

36

PSHB
Pull Data

PULA

3

DC 4

2

2

EC

3D

ROL

2

DA 3

2

EA 4

2

FA 4

69

6

2

79

6

ROLB
ROR

66

6

2

76

6

B +M- B

4

1

37

4

32

3

1 B - Msp. SP - 1 - SP
1 SP -+ 1 - SP, Msp - A

33

3 1 SP -+ 1- SP, Msp-+ B

49

1

1

59

1

1

3

3

RORA

46
56

RORB

(Note) Condition Code Register will be explained in Note of Table 13.

_HITACHI

1
1

1
1

A - MSP. SP - 1 - SP

=114{]4i I I I I I I nJ
bO
8

C

b7

=lb,
8

C

C

b7

2

I
I
I
I

I
I
I
I
: I
I I
I I
I I
I I
I I
R 5
R 5
R 5
I I
I I

I
I
I
I
I
I

I
I
I
I
I
I

R
R
R
R

R R
R R
R R

I
I

I
I
I

I

I

I

I
I
I
I
I
I

I
I
I
I

R 5

 Zero
------Branch If > Zero

Branch If Lower Or

Some
Branch If

< Zero

Branch If Minus

---- I-""

I

26

2
3 2
3 2
3 2

'3'
r'3

None

Z + IN G) VI - ,

..

_-- -

I

C+Z·'

~- --

NG)V"
---_._._._----

---+--

-

-

6E
90

5

2

AD

3 2 7E

1 1

NOP

0'

Return From Interrupt!

RTI

38 10 I

Return From
Subroutine

-----Software Interrupt

RTS

39

SWI

Wait for InterruptSleep

Wi'll
5LP

3F '2
3E 9
'1'1 4

No O"el'ltlon

Z'O

--5

.~

I--"-~

. f-

=,

3 3

~. 2.. 80 6 3 f--- -_.

-f--

..

._._--- :-~

N-'

V-O

2

·· ·· · · · ·
·· ·· ·· ·· ·· ··
··· ··· ··· ··· ··· ···
··· ··· ··· ··· ··· ···
······
· · · · · ··...· ·· ·· ·· ··
··· ···• ··· ··· ··· ···
·· · ·· ·· ·· ··
·· · ·· ·· ·• ·•
·• • • ·• •• ••

.~ ~~

C'O
C· ,
Z· ,

---- - .-

3 2 1 0
I N Z V C

4

H

#

Branch Alwavs

3

5

Advances Prog.
Only

,
,
,,

Cn~r.

--('..- -S

'j', •

(Notel • WAI puts R/Vii high; Addre.. Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 13 .

•

HITACHI

379

HD6303X,HD63A03X,HD63B03X----------------------Table 13 Condition Code Register Manipulation Instructions
iAddreuingMod..
Operation,

elM, Carrv
Clar Overflow

Set Carrv
Set Interrupt Mask
SetOwrflow
Accumulator A ....

eeR
eeR .... Accumulator A

Bool.an Operation

-

CLC
Cll
CLV
SEC
SEI
SEV
TAP
TPA

Clnr Interrupt M ••k

CondItion Code Regist.r

IMPLIED
OP
#
1
1
OC
1
OE
1
OA
1
1
00
1
1
OF
1
1
OB
1 1
06
1 1
07
1 1

Mnemonk:

e

M

Boolean Inclusive OR
Boolean Exclusive OR
Complement of M

-II-

Transfer into

I

3
N

2
Z

1

0

V

C
R

R

O~I

O-V
l-C
1-1
I_V

R

S

S

S

A_ eeR

@

• .1.

CCR-A

• .1 •

CONDITION CODE SYMBOLS
H
Half-carry from bit 3 to bit 4
I
Interrupt mask
N
Negative (sign bit)
Z
Zero (byte)
V
Overflow, 2's complement
C
Carry/Borrow from/to bit 7
R
Reset Alwavs
S
Set Always
~
Set if true after test or clear
•
Not Affected

Arithmetic Minus
Boolean AND

•

+

4

H

·• · ·· ·· ·· ·
·• ·· ·· ·• •• ·
·· · ·• ·· ··
•
·

O~C

LEGEND
OP Operation Code IHexadecimal)
Number of MCU Cycles
Msp Contents of memory location pointed to by Stack Pointer
#
Number of Program Bytes
+
Arithmetic Plus

5

OBit = Zero
00 Byte = Zero
INote) Condition Code
(j)
(Bit V)
(2' (Bit C)
(3)
(Bit C)
(4)
(Bit V)
(5' (Bit V)
'6'·
(Bit V)
-:71 (Bit N)
® (All Bid
C9' (Bit I)
(fo~
(All Bit)
(Ii)
(Bit C)

Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = loooooo0?
Test: Result l; 00000000?
Test: BCD Character of high-order byte greater than 10? (Not cleared if previouslV set)
Test: Operand = 10000000 prior to execution?
Test: Operand::: 01111111 prior to execution?
Test: Set equal to N$ C = 1 after the execution of instructions
Test: Result le.s than zero? (Bit 15=1)
Load Condition Code Register from Stack.
Set when interrupt occurs. If previously set, a Non·Maskable Interrupt is required to exist the walt state.
Set according to the contents of Accumulator A.
Result of Multiplication Bit 7=1? (ACCB)

Table 14 Op.code Map

~

OP
CODe

ACC
ACe
ACCA or SP
ACCe or X
INO
IR IMM I OIR liND I eXT
A
8
IMM I OIR liND 1 EXT
0110
0111
0000
0001
0010
0100
0101
l000-t--'-0Pi- 1010_1 1011
1100.1 "0~t"I~7
- 7'0-- I j--~ 00" t---;--8
9
A I B
lO
4
6
C IDE
F
5
BRA
TSX
NEG
SUB
0
0000 0 ,/'"' SBA
CMP
BRN
INS
AIM
I
0001 I NOP CBA
!
OIM_
BHI
PULA
SBC
0010 2 ,/"" / .
2
j - - - - - - - - - - - _ ..
PUlB
COM
SUBD
ADDD
0011 3 ,/"" ,/'"' BlS
3
lSR
AND
4
~oo 4 LSRO ,/"" BCC OES
ElM
TXS
BIT
0101 5 ASlD .../' BCS
~
I
-- _.- -------- ---- lOA
---- ---- --. - - -- --.-- f'6
ROR
OliO 6 TAP TAB BNE PSHA
-------_._--~-.-STA---~-5
T
A
1-7
BEQ
TBA
PSHB
ASR
0111 7 TPA
- ------ASL
-- ----- -.--------- EOR
XGDX BVC
PULX
1000 8 INX
OAA
BVS
RTS
ROl
1001 9 OEX
9
--:ClV
BPl
SlP
ABX
DEC
A
-_.
SEV I ""BA
BMI
RTI
TIM
A'DD
B
lDD
BGE
PSHX
INC
CPX
1100 C ClC
/
- - 0C
STD
1101 0 SEC
TST
,/'"' BlT MUl
BSR...l ___ ~ ____
JMP
lOX
1110 E Cll
LOS
E
,/"" BGT WAI ,/"" """'-:-1
-SWI
STX
CLR
STS
l~F SEI
F
,/'"' BLE
I"
1
2
3
4
C
0 1 E 1 F
~
7
8 I 9 ! A I B
! 6
•UNDEFINED OP CODE
EZ:J
• Onlv each instructions of AIM, DIM, ElM, TIM

~

s--

--

______± __
---:-

---

-ffii- ~
""

380

'--r--

-"

--==----=--c-=

+=~~==------~~~

I

--S--:--J

V--

1

°

_HITACHI

t-s

------------------------HD6303X,HD63A03X,HD63B03X
•
•

CPU OPERATION
CPU Instruction Flow

When operating, the CPU fetches an instruction from a
memory and executes the required function. This sequence
starts with RES cancel anti repeats itself limitlessly if not
affected by a special instruction or a control signal. SWI, RTI,
WAI and SLP instructions are to change this operation, while
NMI, IRQ" IRQ2, IRQ3, HALT and STBYare to control it.
Fig. 24 gives the CPU mode transition and Fig. 25 the CPU
system flow chart. Table 15 shows CPU operating states and
port states.
•

Operation at Each Instruction Cycle

Table 16 provides the operation at each instruction cycle.
By the pipeline control of the HD6303X, MULT, PUL, DAA
and XGDX instructions etc. prefetch the next instruction. So
attention is necessary to the counting of the instruction cycles
because it is different from the existent one -----op code fetch
to the next instruction op code.
Table 15 CPU Operation State and Port State
Port

Reset

Ao - A7
Port 2

H
T
T
H
T

00 - 07
A. -A,s
Port 5
Port 6
Control
Signal

~r---T

-.~-----

.

~-~

-

STBY'"
T
T
T
T
I T
T
T

HALT
T
Keep
T
T
T
Keep

I

..

Sleep
H
Keep
T
H
T
Keep

Figure 24 CPU Operation Mode Transition

.

H ; High, L; Low. T; High Impedance
• RD, WR, R/W, DR = H, BA = L
.. RD. WR, RIW = T, LlR. BA = H
*** E pin goes to high impedance state.

•

HITACHI

381

w

:l:
C

co

I\l

0)

~

w

IR

X

pc·I

,-\

J::

c0)

PC·I

VECTORtNG

"FFFE.mf

~

STACK

X

J::

c0)
W

(Note) 1. The program sequence will come to the RES start from
any place of the flow during RES. When STBY=O. the
sequence will go into the standby mode regardless of the CPU
condition.

2. Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts .

•
J:

~

(')

3:

N

Figure 25 HD6303X System Flow Chart

ttl

o

W

X

------------------------HD6303X,HD63A03X,HD63B03X
Table 16 Cycle-by-Cycle Operation
Address Mode &
Instructions

IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
ADDD CPX
LDD
LDS
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

Address Bus

CPX
LOS
SUBD

STD
STX

STS

1
2

Op Code Address + 1
Op Code Address + 2

1
1

0
0

1
1

1

Operand Data

0

Next Op Code

1
2
3

Op Code Address + 1
Op Code Address+2
Op Code Address+3

1
1
1

0
0
0

1
1
1

1
1
0

Operand Data IMSB)
Operand Data ILSB)
Next Op Code

1
2
3

Op Code Address + 1
Address of Operand
Op Code Address+2

1
1
1

0
0
0

1
1
1

1
1

Operand Data

0

Next Op Code

1
2
3
1
2
3

Op Code Address + 1
Destination Address
Op Code Address+2
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address + 2
Op Code Address+ 1
Destination Address
Destination Address+ 1
Op Code Address + 2
Op Code Address + 1

1

1
1

Destination Address
Accumulator Data
Next Op Code
Address of Operand ILSB)
Operand Data IMSB)
Operand Data ILSB)
Next Op Code
Destination Address (LSB)
RegISter Data IMSB)
Register Data ILSB)
Next Op Code
Jump Address ILSB)
Restart Address ILSB)
Return Address ILSB)
Return Address IMSB)
First Subroutine Op Code
ImmedIate Data
Address of Operand ILSB)
Operand Data
Next Op Code

2

3

3

3
ADDD
LDD
LOX

4

4

4

1
2
3

4
JSR

5

1
2
3

4

5
TIM

4

1
2
3

ElM

6

FFFF
Stack POinter
Stack POlnter-1
Jump Address
Op Code Address + 1

Op Code Address+2

1
2
3

Address of Operand
Op Code Address+ 3
Op Code Address + 1
Op Code Address + 2
Address of Operand

4

FFFF

5
6

Address of Operand
Op Code Address + 3

4
AIM
OIM

Data Bu.

0

1

0

1

0

1
1
1
1
1
1

0
0
0
0
0
0

1
1
1
1
1
1

0
0

1
1

0
0

1
1
1

0
0

1
1
1

0
0
1
1
1
1
1
1
1
1
1

0
1

1
1
1

0
0
0
0
0
0
0
0

0
0
1
1
1
1
1
1
1
1
1

0
1
1
1

0
1
1
1

0
1
1
1
1

0
1
1
1

0

1
1

0

1
1
1
1
1

0

1

0

Address of Operand ILSB)

Immediate Data
Address of Operand ILSB)

Operand Data

Next OP Code

Restart Address ILSB)

New Operand Data

(Continued)

•

HITACHI

383

HD6303X,HD63A03X,HD63B03X.----------------------Addre.. Mode &
Instructions

Address Bus

Data Bus

INDEXED
JMP

3

-ADC- -'\00AND
CMP
LOA
SBC
TST

BIT
EOR
ORA
SUB

1--4

----

S'fA

4
AOOO
CPX
LOS
SUBO
STO
STX

LOO
LOX

3
1
2

3
4

_.,.
2

3
4
1
2

5

3
4
5
1
2

STS

5

3
4
5
1
2

JSR

5

ASL
COM
INC
NEG
ROR

1
2

ASR
DEC
LSR
ROL

3
4
5
1
2

6

TIM

3
4
5
6
1
2

5

CLR

5

3
4
5
1
2
3

4

5
AIM
DIM

1
2
3

ElM

7

4
5
6
7

Op Code Address + 1
FFFF
Jump Address
Op Code Address + 1
FFFF
IX+OIIset
Op Code Address+2

1
1
1
1
1
1
1

1
1
1
1
1
1
1

0
1

0
0
1

0
0

1
1

0
1
1
1

0

Ollsat
Restart Address (LSB)
First Op Code _of Juml>. ~~i'!"__
Ollsat
Restart Address (LSB)
Operand Data
Next Op Code

\

°Op-Code Address+T---FFFF
IX + Ollset
Op Code Addre.s + 2
Op Code Addre •• + 1
FFFF
IX + Ollset
IX + Ollset + 1
Op Code Addre.s + 2
Op Code Addre•• + 1
FFFF
IX + Ollset
IX + Ollsat + 1
Op Code Address+2
Op Code Address + 1
FFFF

1
1

0
1
1
1
1
1
1
1
1

0
0
1
1
1

Stack Pointer
Stack Pointer - 1

0
0

IX + Ollset
Op Code Address + 1
FFFF
IX+OIIset
FFFF
IX + Ollset
Op Code Addre .. + 1
Op Code Addre.. + 1
Op Code Address + 2

1
1
1
1
1

0

0
1
1

0
0
1

0
0
0
u
1
1
1

0
0
1
1
1

0
0
1

0
1
1

1
1
0
1
1
1
1
1
1
1
1

0
0
1
1
1

0
0
1
1
1
1
1

0

1
1
1
1
1
1
1
1

0

1
0
1
1

0
1
0

1
0

0

1

1
1

0

FFFF

FFFF
IX+OIIset
Op Code Address+3
op Code Addres. + 1

FFFF
IX+OIIset
IX+Ollsat
Op Code Addre.s+2
Op Code Addre.s + 1
Op Code Addr ••s+2

0

0
1

0
0

~

,

1
1
1
1
1
1
1

,
,
,
1
1
1

-

1
1
1

Ollset
Restart Address (LSB)

0

Next Op Code
-----Ollset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Ollset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Ollset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Ollset
Restart Address (LSB)
Operand Data
Re.tart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Oll.et
Restart Addre•• (LSB)
Operand Data
Next Op Code
Oll.et
Restart Addre•• (LSB)
Operand Data

1
1
1
1

0
1
1
1
1

0
1
1
1
1

0
1
1
1
1
1

0
1
1
1
1

0
1
1
1

1
0
1

1
1

1

IX+Ollsat

1

0

FFFF

1

IX + Ollsat
Op Code Addre.s + 3

0

1
1

0

1
1

1

0

1

0

Accumulator Data

00
Next Op Code
Immediate Data
Oll••t
Restart Addr••• (LSB)
Operand Data
R.star, Addrass (LSB)
New Operal\d''Data
Next Op Code

(Continued)

384

•

HITACHI

------------------------HD6303X,HD63A03X,HD63B03X
Address Mode &
Instructions

: Cvcles : Cv;le

EXTEND
JMP
I

A"DC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

1
2

3

3.
1
2
3

TST I

4

LDD
LOX

SiD

STS

i-

STX

5

JSR
6

ASR·· - .-.~--

COM
INC
NEG
ROR

DEC
LSR
ROL

.Jump.~~dr~,,-s.. ,__ .

-.J-

,

6

:--0"

5

i

100-

'1'
1

0
0

1

0

1
1

o
1

1
1
1
1
1
1
1

·~-O--

:

1

o
o
-11

I Address of Operand

o

6

Op Code Address+3
-- Op' Co"d.'Address + ,
Op Code Address+2
Address of Operand
: Address of Operand
Op Code Address + 3

1
1
1
1

-1- , -

1
1

1
1

o

--0-

o
1

1

o

--0-

1

1

1

Operand Data

1

o

1
1

Restart Address (LSB)

1

0

1
1

1
1
1
0

Next Op Code
Ad'dresso! Operand (llilSS)
Address of Operand (LSB)

o
1

1

0

1

o

o

1
1
1

1

0

-1-----r1

1

1

1

o
o

1
1

1

0

o
'-0-o
o
1

o

Destination Addr-ess (MSB)-

1

1

1

,--,'

1
1
1

-t-{--

Jump Address (MSB)
Jump Address (LSB)
Next Op Code
"AddresSoIOperarid-(MSB)'
Address of Operend (LSB)
Operand Data
Next Op Code

Dest,nation Address ILSB)
Accumulator Data
Next Op Code
Address 01 Operand (MSS)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data ILSB)
Next Op Code
Dest",ati,,'; Adclress-(MS-B)
Destination Address ILSB)
Reg,ster Data IMSB)
Reg,ster Data (LSB)
Next Op Code
Jump AMras. (MSEiI
Jump Address ILSB)
Restart Address (LSB)
Return Address (LSB)
Return Address IMSB)
First Subroutine Op Code
Address of Operand (NlSB)
Address of Operand (LSB)

o

1
1

5

0

1
1

0

o
o

1

I

1

0

"-0- - ' - 1

FFFF

3

---'f-

1
1
0

Address of Operand

Op Code Address + 2

1
1

1
0
1

o
o
1
1
1

1
1
1
-11
1

0
1
:, 0

o
o

i,

2
3
4
5

i

00

1
1

2

;

!

11

_ ..1:' __ . 11--

Op Code Address+ i
Op Code Add,ess+2
DestlO8tlon Address
4 ,Op Code Address + 3
oP" Code Address + ,.
1
2
Op Code Address+2
3
Address of Operand
4
Address of Operand + 1
5
Op Code Address+3
1
bi,COdeAddress+1
2
Op Code Address + 2
3
Destination Address
4
OestlOatlon Address+ 1
5
Op Code Address+3
T . ,. oi>' Code Addres'+ 1
2
Op Code Address+2
3
FFFF
4
Stack Pointer
5
Stack POinter - 1
6 i Jump Address
-,-Code-Address-+ f'

4

. elR

!

Op Code Address+ 1
Op Code Address+2
Address of Operand
Op Code Address + 3

1
2
3

5

ASL

Data Bus

Op Code Address+ 1
Op Code Address + 2

4

4
ADDD
CPX
LOS
SUBO

Address Bus

'-'-1-

-1-'---'o
1

New Operand Data

Operand Data

00
Next Op Code

(Continued)

$

HITACHI

385

HD6303X,HD63A03X,HD63B03X----------------------Address Mode 8.
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA

ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
R(J)L
NOP
SEC
SEV
TAP
TPA
TSX
XGDX

Address Bus

1

Op Code Address + 1

1

0

1

0

Next Op Code

1

Op Code Address + 1
FFFF
Op Code Address + 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF

1
1
1
1
1
1
1

0

1
1
1
1
1
1
1

0

Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)

Stack Pointer

0

Op Code Address + 1
Op Code Address+ 1
FFFF

1
1
1
1
1
1
1

1

2

PULB

2
1

3
PSHA

Data Bus

PSHB

2
3
1

4
PULX

2
3
4
1

4
PSHX

2
3
4
1

5

RTS

2
3
4
5
1

5

MUL

2
3
4
5
1

7

2
3
4
5
6
7

Stack Pointer+ 1
Stack Pointer + 2

Op Code Address + 1
FFFF

0
0

Stack Pointer

Stack Pointer-l
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address

Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

1
1
1
1
1
1
1
1
1
1
1
1
1

1

0
1

0
0
1
1

0
0
1

0
0
0
1
1
1

0
0
1

0
0
0
0
1
1
1
1
1
1

0
1
1
1
1
1
1
1

0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1

0
1
1
1
1
1

0
0
1
1
1
1
1
1
1

0
1
1
1
1

0
0

1
1
1
1
1
1

---

Data from Stack

Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Code
Restart Address (LSBI
Index Register (LSBI
Index Register (MSBI
Next Op Code
Next Op Code
Restart Address (LSBI
Return Address (MSBI
Return Address (LSBI
First Op Code of Return Routine
-Next Op Ccide- . - - -.~~~
Restart
Restart
Restart
Restart
Restart
Restart

Address
Address
Address
Address
Address
Address

(LSB)
(LSBI
(LSBI
(LSBI
(LSBI
(LSBI

(Continued)

386

$

HITACHI

------------------------HD6303X,HD63A03X,HD63B03X
Address Mode &
Instructions
IMPLIED
WAI

9

I

-l
,

.---c--

I

0
1
1
Next Op Code
1
Op Code Address+ 1
1
1
1
1
Restart Address (LSB)
FFFF
0
1
0
1
Return Address (LSB)
3 i Stack Pointer
I Staok Pointer-l
0
1
0
1
Return Address (MSB)
! Stack Pointer - 2
0
1
0
1
Index RegIster (LSB)
0
1
0
1
Index Register (MSB)
i Stack Pointer-'3
7
! Stack POinter -4
0
1
0
1
Accumulator A
8
Stack POInter - 5
0
1
0
1
Accumulator B
9
! Stack POlnter-6
0
1
0
1
Conditional Code Register
T l o p Code Addressn' ---I---..;I'---+--;.O-+--..;I;.....-+-....;I--1-..;N:;:e-::x'"'t::;O~p:::C::::o:..cd:;:e='- '-'~-""o.",,_
1
2

-·Ffn-- ---

Data Bus

Address Bus

I

I

FFFF

,2

!

3
4
5

I

I

10

I

6
7
8

I
!

, t-

SWI

I
i
,

12

! Stack Pointer + 1
Stack POinter + 2
I Stack Pointer + 3

i

I

Stack Pointer +4
Stack Pointer+5
Stack Pointer+6
9
Stack Pointer + 7
10 ! Return Address
_____
i" t, Op Code Address+ j
2 ; FFFF
3
Stack Pointer
4
! Stack POInter-I
5 I Stack POInter - 2
6 ! Stack POlnter-3
7 ,I Stack POinter - 4
8
1 Stack POinter - 5
Stack POinter -6
9
I'

I

i

10
11

Vector Address FFFA
Vector Address FFF8

1
1
1
1
1
1

1
0
0

1
Restart Address (LSB)
1
Conditional Code Register
1
Accumulator B
0
1
1
Accumulator A
0
1
1
Index RegIster (MS8)
0
1
1
Index Register (LS8)
1
0
1
1
Return Address (MSB)
1
0
1
1
Return Address (LSB)
__-:1:_-+-....;0_+-.-:1;.....+....;0
.-.£!.rst Qp Cod~.~~__~~!~~_~~~
1
0
1
1
Next Op Code
1
1
1
1
Restart Address (LSB)
0
1
0
1
I Return Address (LSB)
0
1
0
1 , Return Address (MSB)
0
1
0
1
Index Register (LSB)
0
1
0
1
Index Register (MSB)
0
1
0
1
Accumulator A
0
1
0
1
Accumulator B
0
1
0
1
I Conditional Code Register

1

1
1

J'

1,1

I

1
1

0
0

1
1

1~'

1

12
Address of SWI Routine
1
0
1
0
--S"L..
P-----+--+..:.;.I=-t---;O<'P:.::;,C:.:od:;:e~A..;d:.;dr..:.e:...ss:.:+:;:.:;:I=-+--;'-+-~O~+--;I-+--I;2
FFFF
1
1
1
1
4

RELATIVE
BCC
BEO
8GT
BLE
8LT
8NE
8RA
BVC
BSR

BCS
BGE
BHI
BLS
8MT
BPL
8RN
BVS

I

3

S'i

ep
FFFF
Op Code Address + 1

1
3

I Restart Address (LSB)

Ij II I
i

3
4

2

Address,of, SWI ROU, tl,ne (MS8,I
Address of SWI Routone (LS8)
Forst Op Code of SWI Routone
""NextOp COde- ....

1
1

1
0

1
1

1
0

Op Code Address+ 1
FFFF
{BranCh Address· .. · oTest=" 1"
()p Code Address+l,,'Test="O"

1
1

0
1

1
1

1
1

1

0

1

0

Op Code Address+ 1
FFFF

1
1

0

1
1

I

Restart Address (LSB)
Next Op Code

Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code

I

I
1

!

I

2
5

3
4
5

Stack POinter

Stack Pointer - 1
Branch Address

•

0
0

1
1
1

0
0

1
1
1
1

1

0

1

0

HITACHI

Offset
Restart Address (LS8)
Return Address' (LSB)
Return Address (MSB)
First Op Code of Subroutine

387

HD6303V ,HD63A03V ,
HD63B03V
CMOS MPU (Micro Proces$ing

Unit)

-ADVANCE INFORMATIONThe HD6303Y is a CMOS g·bit micro processing unit which
contains a CPU compatible with the HD6301Vl, 256 bytes of
RAM, 24 parallel I/O Pins, Serial Communication Interface
(SCI) and two timers.
•
•
•

•
•

•
•

•

•

FEATURES
Instruction Set Compatible with the HD6301 Family
Abundant On·chip Resources
• 256 Bytes of RAM
• 24 Parallel I/O Pins
• Handshake I nterface (Port 6)
• Darlington Transistor Direct Drive (Port 2, 6)
• 16·bit Programmable Timer
1 Input Capture Register
( 1 Free Running Counter
2 Output Compare Registers
• a·Bit Reloadable Timer
( 1 a·bit Up Counter
1 Time Constant Register
• Serial Communication Interface
Asynchronous Mode
( a Transmit Formats
Hardware Parity
Clocked Synchronous Mode
Interrupt - 3 External, 7 Internal
CPU Functions
• Memory Ready, Auto Memory Ready
• Halt
• Error Detection
(Address Trap, Op·code Trap)
Up to 65k Bytes Address Space
Low Power Dissipation Mode
• Sleep
• Standby (Hardware Set, Software Set)
Wide Range of Operation
Vee=3t06V
(f=0.1toO.5MHz)
f = 0.1 to 1.0 MHz; HD6303Y )
Vee = 5V ± 10% ( f=0.1 to 1.5MHz;HD63A03Y
f = 0.1 to 2.0 MHz; HD63B03Y
Minimum Instruction Cycle Time: 0.5 jI.S (f = 2.0 MHz)

388

•

HD6303YP, HD63A03YP,
HD63B03YP

(DP-64S)
H D6303Y F, H D63A03Y F,
HD63B03YF

(FP-64)

HITACHI

H D6303Y.H D63A03Y. H D63B03Y

•

PIN ARRANGEMENT

• HD6303YP. HD63A03YP. HD63B03YP
v..
XTAl

STiW
NMi

• HD6303YF. HD63A03YF. HD63B03YF
I~t;

2

I'" .:

. ..

-'

0

~ ~ ::;

-'
.... ;!

~

)(

~

..

I~ I~ I~a:

~

..
0.

p,.

D.

7

0,

8
0,

0,

0,

0.

D.
D.

D.

"-

P"

D.

0,
A.

A.

A,
A,

P,.

A.

P"
P"

A,

A,

A.

A.

A.

...

A.

A,

A,

Vss
A.

A.

A.

Pot

.. .. . .= .. . .. ..

A"

:

:&

:

u

~

~

-< -< -<

(Top View)

(Top View)

~HITACHI

389

HD6303~HD63A03~HD63B03Y-----------------------------------------------•

BLOCK DIAGRAM

VCC-------

r01! J111 J

V SS
V ss

...J

~

P2 • (Tin)
P 2 , (Tout,)
P 22 (SCLK)
P 23 {Rx)

x

a:

RD
WR
R/W
LlR
BA

CPU

0:

N

f-

f-

a:

a:

0
a..

p .. (Tout,)
p .. (Tout.)

x

w

c3

Cl
Cl

N

p,. (Tx)

...J
<{

I-

0
a..

P 27 {TCLK)

r-~

L..L--

£:l

~

0:
LU

::!

f=

U
en

It

'"

:l

co
0:

::!

f=

K

---

Po. Po, P.,-

p.,P•• -

p.,-

0
a..

Cl
Cl
LO

f-

a:
0
a..

aa..

0:
0
0

'"

,/

'"
on

~
"0
"0

----+---'
Time required for oscillation to become
stabilized (tose!

STOP instruction
executed

Reset
start

(b) Restart by Reset
Figure 20 Timing Chart of Releasing from Stop Mode

\'-----(111--

·

_----'I

i

,

•

••
I

I

~-~-~--'~~--------~r-----------r---------J
tosc

Figure 21

Table 4

Start

Mode

WAIT

-

Soft·
ware

STOP
Stand·
by

Hard·
ware

Restart

Timing Chart of Releasing from Standby Mode

Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Timer,
Register
Serial

Oscil·
lator

CPU

WAIT in·
struction

Active

Stop

Active

STOP in·
struction

Stop

Stop

STBY="Low"

Stop

Stop

Escape

RAM

I/O
terminal

Keep

Keep

Keep

STBY, RES, INT, INT2,
each interrupt request of
TIMER, TIMER 2, SCI

Stop

Keep

Keep

Keep

STBY, RES, INT, INT2

Stop

Reset

Keep

High im·
pedance

_HITACHI

STBY="High"

411

HD6305XO,HD63A05XO,HD63B05XO--------------------------------------------

Figure 22 Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset

-BIT MANIPULATION
The HD6305XO MCV can use a single instruction (BSET
or BCLR) to set or clear one bit of the RAM or an I/O port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 $FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM, or I/O can be
manipulated, the user may use a bit within the RAM as a flag
or handle a single I/O bit as an independent I/O terminal.
Fig. 23 shows an example of bit manipulation and the validity
of test instructions. In the example, the program is configured
assuming that bit 0 of port A is connected to a zero cross
detector circuit and bit 1 of the same port to the trigger of a
triac.
The program shown can activate the triac within a time of
lO~s from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SELF 1.

BRCLRO,PORTA,SELFI
BSET 1, PORT A
BCLR 1, PORT A

Figure 23 Example of Bit Manipulation

-ADDRESSING MODES
Ten different addressing modes are available to the
HD6305XO MCV.
elmmediate
See Fig. 24. The immediate addressing mode provides
access to a constant which does not vary during execution of

412

•

the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
e

Direct
See Fig. 25. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
2SSth address. All RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized.

eExtended
See Fig. 26. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction reqUires a length of 3 bytes.
e Relative
See Fig. 27. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.
elndexed (No Offset!
See Fig. 28. The indexed addressing mode allows access
up to the lower 25Sth address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.

HITACHI

----------------------HD6305XO,HD63A05XO,HD63B05XO
• Bit Test and Branch

• Indexed (S-bit Offset)

See Fig. 29. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
• Indexed (16-bit Offset)

See Fig. 30. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.

See Fig. 32. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
• Implied

• Bit Set/Clear

See Fig. 31. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.

See Fig. 33. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and R TI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.

EA
Memory

PROG LOA .$F8

~

A

F8
Index Reg

I
Stack POint

058Et-:~A~6=~------J

05BFt-

Prog Count
05CO
CC

Fa

~
,

,,

Figure 24

Example of Immediate Addressing

EA
0048

Memory

CATFC8320048f:~20[:~~~==i===~~~~~----iA~~2~0~:J
Index eg

...J

PROG LOA CAT 0520 t-:~8~6t:=l_ _
052E!- 48

Stack

'Oint

Prog

Aount

052F
CC

~
,

,,,
!

,,,
,
I

Figure 25

Example of Direct Addressing

_HITACHI

413

HD6305XO,HD63A05XO,HD63B05XO--------------------------------------------

EA
Memory

A

40

--I-.}-040BI---"E;;..5--r

PROG LDA CAT :~!t-""*~6~6

CAT FeB 64

I
Stack Point

06E5E=4~0~jl--------------J

Figure 26

,,

Memory

PrOQ Count

040C
CC

Example of Extended Addressing

EA

.

~.

A

Index Reg

I

.
PROG BEQ PROG2 04A7
04A8

I

Index Reg

Stack Point
Prog

bount

04Cl

27
lB

Figure 27

Example of Relative Addressing

EA
Memory

0088

TABLFCClIOOB8~~~4~C~~I---~~L--------t======~~~A~~4~C~~
n ex e
BB

49

Stack Point
Prog Count

05F5
CC

Figure 28

414

Example of I ndexed (No Offset) Addressing

•

HITACHI

----------------------HD6305XO,HD63A05XO,HD63B05XO

:,
TABl FCB
FCB
FCB
FCB

BF
86
DB
CF

BF
86
DB
CF

0089
008A
OOBB
OOBC

EA
OOBC

,
:

MeJory

./

Adder

-~

,,

I

"

1

E6
89

PROG lOA TA8L.X 075B
075C

A
CF

I

I

Index Reg

03
Stack Pomt

I
,

I

I

0750

I

Prog Count

I

CC

@
,

,

Figure 29

Example of Index (S-bit Offset) Addressing

EA
0780

MeJorv

I

~

--rr

Adder

06
07
7E

PROG lOA TABL.X 0692
0693
0694

""'"

BF
86
08
CF

DB
Index Reg
02
Stack

Prog Count

0695
CC

I

BF
86
DB
CF

077E
077F
0780
078'

Figure 30

I

,nl

I

I

I
TABl FCB
FC8
FCB
FC8

A

I
I
I

Example of Index (16-bit Offset) Addressing

EA
0001

Memorv

PORT 8 EQU , 000' ~.....:B;::F~--t"l
A
Index Reg

PROG BClR 6. PORT B 058F
0590

t =1----.-J

t:=~'D

I-

0'

I
Stack Point

I

Prog Count

059'
CC

~

I,

Figure 31

:,

Example of Bit Set/Clear Addressing

•

HITACHI

415

HD6305XO,HD63A05XO,HD63B05XO---------------------------------------------

EA

Memory

0002

A

PORT C EQU 2. 0002 t-....;F..;;.O_-II.<--..--'

I
Index Reg

s,ac~ PO,n'
PROG BRCLR 2.PORT C.PROG 2 0574

05

Prog Count

0575~::%02t::"h--

0594
CC

05761---:;10::""'--4 H::::::9iCl

C

Figure 32

Example of Bit Test and Branch Addressing

r--------,

EA

Memory

~
'~'''~~§

A
E5
In ex 8g

E5
Stack

I

Prog Count

05B8

cc
I

~
,,
,!

Int

,,
,,

Figure 33

Example of Implied Addressing

-INSTRUCTION SET

• Branch Instructions

There are 62 basic instructions available to the HD6305XO
MeU. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Regi.ter/Memory In.truction.

Most of these instructions use two operands. One operand

A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instruction.

These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.

is either an accumulator or index register. The other is derived

from memory using one of the addressing modes used on the
HD6305XO MeU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.

• Control Instruction.

The control instructions control the operation of the MeU
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order

• Re.dlModify/Write Instruction.

These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.

416

•

Table 10 lists all the instructions used on the HD6305XO
MeU in the alphabetical order.
• Operation Coda Map

Table 11 shows the operation code map for the instructions
used on the MeU .

HITACHI

----------------------HD6305XO,HD63A05XO,HD63B05XO
Table 5 Register/Memory Instructions
Addressing Model
Indexed

Indexed

Operations

MnemoniC

Immediate
-

OP #

-

OP #

-

OP #

-

OP #

-

OP #

-

3

E6

2

4

06 3

5

M-A

3

EE

2

4

DE 3

5

M-X

4

E7

2

4 07 3

5

A-M

4

EF

2

4

OF

3

5

X_M

3

EB

2

4

DB 3

5

A+M-·A

3

E9

2

4 09 3

5

A+M+C .A

3

EO

2

4

DO 3

5

A-M-A

3

E2

2

4 02 3

5

A-M-C-A

3

E4

2

4

04 3

5

A·M-A

3

EA

2

4 OA 3

5

A+M-A

3

E6

2

4

08 3

5

,
,

LOA

A6

2

2

B6

2

3

C6

3

4

F6

-Store
-A in Memory

Load X from Memory

LOX

AE

2

2

BE

2

3

CE

3

4

FE

STA

B7

2

3 C7

3

4

F7

Store X In Memory

STX

BF

2

3

CF

3

4

FF

Add Memory to A

ADD

AB 2

2

BB

2

3

CB

3

4

FB

toA

AOC

A9

2 B9

2

3

C9

3

4

F9

Subtract Memory

SUB

AO 2

2

eo

2

3

CO 3

4

FO

,
,
,
,
,

A W1th Borrow

SBC

A2

2 B2

2

3 C2

,

AND Memory to A

AND

A4 2

2

2

3

OR Memory with A

ORA

AA 2

EOR

AB 2

Add Memory and Carry

2

Subtract Memory from
2

3

4

F2

C4 3

4

F4

2 BA 2

3 CA 3

4

FA

,
,

2

B8

3

4

F8

,

2

3

C,

3

4

F'

B4

Exclusive OR Memory

with A

2

C8

3

Arithmetic Compare A
CMP

A'

2

2

B,

CPX

A3 2

2

B3

2

3 C3

3

4

F3

A {Logical Compare}

BIT

A5

2

B5

2

3

C5

3

4

F5

Jump Unconditional

JMP

BC

2

2 CC

3

3

FC

Jump to Subroutine

JSR

BO

2

5 CD 3

6

FO

with Memory
Arithmetic Compare X

with Memory

Arithmetic
Operation

OP #
Load A from Memory

Bit Test Memory with

2

,
,
,
,
,

Condition

Booleanl

Indexed

Extended (No Ollset) I8-Bit Offset) (16·BnOffset)

Direct

Code
H

...

I

N

• •
• •
••
• •
•

_-

~---

--- -

•
• •

Z

C

•
•
•
•
-;-1-- I--

• •
• •
• •

•

A+M-A

• •

•

•

3 E'

2

4

0,

3

5

A-M

• •

3

E3

2

4

03 3

5

X-M

• •

3

E5

2

4 05 3

5

A·M

2

EC

2

3 DC 3

4

5 ED

2

5 DO 3

6

• •
•
• • • • •
• • • • •

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

Table 6 Read/Modify/Write Instructions
Operations

Mnemonic

Imph.dIA)
OP #

-

OP #

INC

4C

2

5C

Decrement

DEC

4A

2

5A

Clear

CLR

4F

Complement

COM

43

NEG

40

Negate
(2's Complement)

Rotate left Thru Carry

ROL

49

Rotate Right Thru Carry

ROR

46

Logical Shift Left

LSL

4B

logical Shih Right

LSR

44

,
,
,
,

Arithmetic Shift Right

ASR

47

,

Arithmetic Shih left

ASL

4B

TST

40

Test for Negative
or Zero

,
,

Indexed

Imphed(XI

Increment

,
,
,
,
,

Addressing Modes

,

2

59

,
,
,
,

2

56

2

58

2

54

2

57

2

58

,
,
,

2

50

,

Direct

-

OP

•

-

2

3C

2

5 7C

2

3A

2

5 7A

OP

2

5F I ,

2

3F

2

5

2

53

2

33

2

5 73

2

50

2

30 2

2

39

Indexed

INoOII..t) IB·BII Offset)

5

7F

70

2

5

79

,

2 36 2

5

76

,

2

3B

2

5

78

2

34

2

5

74

2

37

2

5

77

2

3B

2

5

7B

2

3D 2

4

70

Condition
Code

Boolean/Arithmetic Operation

•,

-

OP •

-

5 6C 2

6

A+l-A or X+l--X or M+l-M

,
,
,

5

6A 2

6

A-1--A or X-l--X or M-l--M

5

6F

2

6

OO ......A or OO_X or 00 -.. M

5

63

2

6

A-A or X ... X or M_M

5

60

2

6

,

,

,
,

,
,
,
,

H

69

• • ,

Aori orlill

II I boiJ

• •

lEH"'1 j-i·HMI 1"iJ
..
c b,
04 1~":'r~ 11 1-b,
.. c
.-1 1 I·H ..:MI 1 HJ
c
b
:1 ' H'300: MI 1 1-0

• •

2

6

5 66 2

6

5 6B 2

6

5

64

2

6

5

67

2

6

5

6B

2

6

Equal to lSl

4

60 2

5

A-OO or X-OO or M-OO

Symbols: Op = Operation
# = Number of bytes

II

0

cr

..

Z

C

•

0

or OO-M-M

Lb4b' I

N

• • ,
• •

OD-A-A or OD-X-X

5

I

• •
• •

, ••
,
'.

.,

, ,
A

A,

• • "
• • "
• • " "
• • " "
A

0

,

,
"

"
"
• • " " •

... - Number of cycles

•

HITACHI

417

HD6305XO,HD63A05XO,HD63B05XO-------------------------------------------Table 7 Branch Instructions
Addressing Modes
Operations

Mnemonic

Relative
OP

#

-

Branch Always

BRA

20

2

3

None

Branch Never

BRN

21

2

3

None

Branch IF Higher

BHI

22

2

3

C+Z=O

Branch IF Lower or Same

BLS

23

2

3

C+Z=l
C=O

Branch IF Carry Clear
.

--

(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF Lower)
Branch IF Not Equal
Branch IF Equal

Condition Code

Branch Test
H

BCC

24

2

3

(BHS)

24

2

3

C=O

BCS

25

2

3

C=l

(BLO)

25

2

3

C=l

BNE

26

2

3

Z=O
Z=l

BEQ

27

2

3

Branch IF Half Carry Clear

BHCC

28

2

3

H=O

Branch IF Half Carry Set

BHCS

29

2

3

H=l

Branch IF Plus

BPL

2A

2

3

N=O

Branch IF Minus

BMI

2B

2

3

N=l

BMC

2C

2

3

1=0

BMS

2D

2

3

1=1

BIL

2E

2

3

INT=O

Branch IF Interrupt Mask
Bit is Set

Branch IF Interrupt Line
is High

BIH

2F

2

3

Branch to Subroutine

BSR

AD

2

5

Symbols: Op

INT=l

----------

= Operation

#

=

-

= Number of cycles

Z

C

.~

Branch IF Interrupt Line
is Low

N

• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • •
• • • ·1·
• • • • •

Branch IF Interrupt Mask
Bit is Clear

I

Number of bytes

Table B Bit Manipulation Instructions
Operations

Addressing Modes
Boolean/
Set/Clear
Bit Test and Branch Arithmetic
Operation
OP
OP
1-1:
1-1:
..
-BRSET n(n=0· .. 7)
2·n
3 5
-- 01 +2·n 3
-BRCLR n(n=O .. · 7)
5
BSET n(n=O .. · 7)
l .... Mn
10+2·n 2 5
-- O->Mn
BCLR n(n=0 .. ·7)
11 +2·n 2 5
Mnemonic

I-'Bit

-

Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n

= Operation
# = Number of bytes
- = Number of cycles

Symbols: Op

418

$

HITACHI

Branch
Test
Mn=l
Mn=O

-

---

Condition Code
H

I

N

•
•
•
•

• • •
• • •
• • • •
• • • •

Z

C
1\
1\

----------------------HD6305XO,HD63A05XO,HD63B05XO
Table 9

Control Instructions

Addressing Modes
Operations

Mnemonic

Implied

Condition Code

Boolean Operation

-

OP
97

#

TXA

9F

1

2
2

99

1

1

I~C

Clear Carry Bit

SEC
CLC

98

1

1

O~C

Set Interrupt Mask Bit

SEI

9B

1

1~1

Clear Interrupt Mask Bit

CLI

9A

1

2
2

Software Interrupt

SWI

1

10

Return from Subroutine

RTS

83
81

1

5

Return from Interrupt

RTI

80

1

8

Reset Stack Pointer

RSP

9C

1

2

$FF~SP

No-Operation

NOP

1
1

Advance Prog. Cntr. Only

OM

90
80

1

Decimal Adjust A

2

Converts binary add of BCD charcters Into

Stop

STOP
WAIT

8E

1

4

8F

1

4

Transfer A to X

TAX

Transfer X to A
Set Carry Bit

Wait
Symbols: Op = OperatIon
# = Number of bytes
.....

:c:

1

H

I

• •
• •
• •
• •1
• 0
•
• 1
• •
? ?
• •
• •

A~X

X~A

Z

•
•
•
•
•
•
•

• •
• •1

•
•
•
•
•
• •
? ?
• •
• •
• •
• • • •
• • • •

O~I

1\

BCD format

1\

C

0

•
•
•

•
?

•
•
•
•

1\*

* Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)

Number of cycles

Table 10

Instruction Set (in Alphabetical Order)
Addressing Modes

Condition Code

Bit
Mnemonic

Implied
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
(BHS)
BIH
Bil
BIT
(BlO)
BlS
BMC
BMI
BMS
BNE
BPl
BRA

N

Indexed Indexed
Extended Relative (No Offset) (B-Bit)

Indexed
(16-Bit)

Immediate

Direct

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

X

X

Set!
Clear

X

X
X
X
X
X
X
X
X
X
X
X

X

X

X
X
X
X
X
X
X
X
X

X

X

Bit
Test &
Branch

H

N Z

C

1\

I

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•

•
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •

1\

1\

•

•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

•

(to be continued)
C
1\

•

Carry/Borrow
Test and Set if True. Cleared Otherwise
Not Affected
load CC Register From Stack

•

HITACHI

419

HD6305XO,HD63A05XO,HD63B05XO-------------------------------------------Table 10 Instruction Set (in Alphabetical Order)
Addressing Mode.

Condition Code
Bit

Indexed

Mnemonic
Implied

Immediate

Direct

Extended Relative (No Offset)

BRN

Bit

Indexed

Indexed

Setl

Test &

(B-Bit)

(16-Bit)

Clear

Branch

X

BRCLR

x

BRSET

X

x

BSET
BSR
CLC

X

x

CLI

X

CLR

x

COM

OEC

X

x
x

x

x
x

x
x

LOA

X

X

LOX

x

x
x

LSR
NOP

x
x
x
x

ROL

x

x
x

ROR

X

X

RSP

x
x
x

RTI
RTS

x

SBC
SEC
SEI

x

x

SUB
TAX
TST
TXA
WAIT

x
x
x
x
x

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

420

x
x
x
x
x

x
X

x
x

x

x

x

x

x
x
x
x
x

x

x
x
x

x

x

x

x
x

x

x

x

x
x

x
x
x

x
x
x

x

x

x

x

x

x

x

x

x
x

x

x
x

x
x

x

x

x

STX
SWI

x

x
x

x
x
x
x

x
x

STA
STOP

x

x
x

x

ORA

x

x

JSR

NEG

x

x

JMP

LSL

x
x

x

X

x

EOR
INC

x

x

CPX
OAA

x
x

CMP

x

C
1\

•?

x

Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

•

HITACHI

x

x

H

I

N

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• • •
• •
• •

Z

C

1\
1\

•
•
•
•0

• •
• •
• 0
•1 •
•

1\

1\

1\

1\

1

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

•
•

•
• • •
• • •
•

,\

1\

1\

1\

1\

1\

•

1\

1\

1\

0

1\

1\

1\

1\

1\

• • •
•
1\

1\

1\

I,

1\

1\

1\

1\

• •
? ?
• •
•
•1 •
•
1\

•
• •
•
•1
•
• •
•
• •
• •

• •
? ?
• •
1\

1\

•

1

• •

•
• •
•

1\

1\

1\

1\

1\

1\

1\

• •
• •
•
• •
• •
(,

1\

----------------------HD6305XO,HD63A05XO,HD63B05XO
Table 11
Bit Manipulation

0
1

Branch

Test &

Set

Branch

Clear

0
BRSETO

1
BSETO

BRA

BRCLRO

BCLRO

BRN

Operation Code Map

Read Modify Write

-

Control

Register Memory

---

!

-

Rei

DIR

2

3

A
4

X

,Xl

,XC

IMP

5

6

7

8
RTI'

NEG

f---

IMP IMMIDIR

9

~~B

EXT

,X2

,Xl

,XC

C

D

E

F

SUB

~H IGH

0
1

RTS'

CMP
SBC

2

SWI'

CPX
AND

3
4

BIT

5

LOA

6
STAI+ll 7
8

2

BRSETI

BSETI

BHI

3

BRCLRI

BCLRI

BLS

COM

4

BRSET2

BSET2

BCC

LSR

5

BRCLR2

BCLR2

BCS

6

BRSET3

BSET3

BNE

ROR

7

BRCLR3

BCLR3

BEQ

ASR

TAX'

8

BRSET4

BSET4

BHCC

LSL ASL

CLC

STA
EOR

9

BRCLR4

BCLR4

BHCS

ROL

SEC

ADC

9

A

BRSET5

BSET5

BPL

DEC

CLI'

ORA

A

SEI'
RSP'

ADD

INC

-

LOX

B

BRCLR5

BCLR5

BMI

C

BRSET6

BSET6

BMC

D

BRCLR6

BCLR6

BMS

E

BRSET7

BSET7

F

BRCLR7

BCLR7

BIL
BIH

3/5

2'5

23

(NOTES)

TST

TSTHI

-

TST(-I)

CLR
1 2

I

1 2

26

1 5

B

JMP(-I)
I
DAA' NOP BSR'I JSR(+2)
JSR(+I)

STOP'
2 5

I

WAIT' TXA'
I
1 ' 1 1 221 23

STX
34 35

L

o

W

C

JSRI+21 0
E
STXI+ll F
24 13

1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cycles).
The number of cycles for the mnemonics asterisked (*) is as follows:

RTI
RTS
SWI
DAA
STOP
WAIT

8
5

10
2
4
4

TAX
RSP
TXA
BSR
eLI
SEI

2
2

2
5
2
2

3. The parenthesized numbers must be added to the cycle count of the particular instruction.

•

WAIT Causes the MCU to enter the wait mode. For this mode,

Additional Instructions

The following new instructions are used on the HD6305XO:
DAA Converts the contents of the accumulator into BCD
code.

•

see the topic, Wait Mode.
STOP Causes the MCU to enter the stop mode. For this mode,

HITACHI

see the topic, Stop Mode.

421

HD6305X1 ,HD63A05X1 ,HD63B05X1-HD6305X2,HD63A05X2,HD63B05X2
CMOS MCU (Microcomputer Unit)
-PRELIMINARYThe HD6305Xl and the HD6305X2 are CMOS versions of
the HD6805Xl and the HD6805X2, which are NMOS 8-bit
single chip microcomputers. A CPU, a clock generator, a 128byte RAM, I/O terminals, two timers and a serial communication interface (SCI) are built in both chip of the HD6305Xl
and the HD6305X2. Their memory spaces are expandable to
16k bytes externally.
The HD6305Xl and the HD6305X2 have the same functions
as the HD6305XO's except for the number of I/O terminals.
The HD6305XI has a 4k byte ROM and its memory space is
expandable to 12k bytes externally. The HD630SX2 is a microcomputer unit which includes no ROM and its memory space
is expandable to 16k bytes externally.
• HARDWARE FEATURES
• S-bit based MCU
• 4k-bytes of internal ROM (HD630SXlI
No internal ROM (HD630SX2)
• 128-bytes of RAM
• A total of 3fterminals, including 24 I/O's, 7 inputs
• Two timers
- 8-bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
- IS-bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt func·
tion is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby.. I n this mode, the clock stop~, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
- HD630SX1/X2 .. 1 J.l.s (f = 1 MHz)
- HD63AOSX1/X2 .. 0.67 J.l.S (f = 1.5 MHz)
- HD63BOSX1/X2 .. 0.5 J.l.s (f = 2 MHz)
• Wide operating range
VCC = 3 to 6V (f = 0.1 to 0.5 MHz)
- HD630SX1/X2 .. f = 0.1 to 1 MHz (VCC = SV ± 10%)
- HD63AOSX1/X2 .. f = 0.1 to I.S MHz (VCC = 5V ± 10%)
- HD63BOSX1/X2 .. f = 0.1 to 2 MHz (VCC = 5V ± 10%)
• System development fully supported by an evaluation kit

422

•

HD630SX1P, HD63AOSX1P,
HD63BOSX1P, HD630SX2P,
HD63AOSX2P, HD63BOSX2P

H D630SX 1F, H D63AOSX 1F,
HD63BOSX1F, HD630SX2F,
HD63AOSX2F, HD63BOSX2F

(FP-64!

• SOFTWARE FEATURES
.Similar to HD6S00
• Byte efficient instruction set
.Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for all RAM bits and all I/O terminals)
• A variety of interrupt operations
.1 ndel( addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
.AII addressing modes adaptable to RAM, and I/O instructions
• Three new instructions, STOP, WAIT and DAA, added to the
HD680S family instruction set
.1 nstructions that are upwaFd compatible with those of Motorola's MC680SP2 and MCI4680SG2

HITACHI

HD6305X 1,HD6305X2
• PIN ARRANGEMENT
HD6305X1P, HD63A05X1P, HD63B05X1P, HD6305X2P,
HD63A05X2P. HD63B05X2P

HD63A05X1F, HD63B05X1F, HD6305X2F •
• HD6305X1F,
HD63A05X2F. HD63B05X2F

•

DATA.
DATA,
DATA,
DATA3
DATA.
DATA.
DATA.
DATA,

0

XTAL
EXTAL
NUM
TIMER.
A,
A.

0

OATA 6
DATA 7
E

E

RIW

R/W
ADR"
ADR ..
ADR ..
ADR,.
ADA.
ADR,
ADR,
ADR,
ADR.
ADR.
ADR3
ADR,
ADR,
ADRo
0,
D.IINT,
D.
D.
03
0,
0,

B,

B.
B.
B.
B3

B,
B,
B.
CdT.
C,/R·.
C./CK

C.
C3
C,
C,
Co

ADR'3
ADA'2

ADR,!
ADR,O

ADR g
ADRa
ADA7

ADRs
ADR5
ADR4
ADA3
B,

ADRl
ADR,
AORo

D,

~ to U U u

Vee



I~
0

(Top View)

BLOCK DIAGRAM

XTAL EXTAl

E

RtW

Accumulator
A

Index
Register

CPU
Control

x

Condition Code
Register
CC

.---"

I

D,

00/00,
D,
0,
01

g:

Port 0
Input

Terminals

Stack
Pointer

Port 8

6

Program
Couoter

ADRl)

"High" pel-!

ADR"
ADR"

I/O
Terminals

ADR,o
ADR~

ADR.
ADR,
ADR.
ADR~

ADR,
--ADA,
ADR,
AOR,

Port C
I/O
Terminals

AORo

CrJCK
CelR~

C,rr·----,-TT--...._-'-------'

• No internal ROM

In

HD6305X2

DATA,
DATA~

DATA.
DATA.,

DATA,
DATA,
O.6.TA,
OAlAo

@HITACHI

423

HD6305X1,HD6305X2------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item

'\

Symbol

Value

Unit

Supply Voltage

Vee

-0.3-+7.0

V

Input Voltage

Vin

-0.3 - Vee + 0.3

V

Operating Temperature

Topr

0-+70

·C

Storage Temperature

T stg

-55-+150

·C

[NOTE)

•
•

These products have a protection circuit in their input larminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to the.. high input impedance circuits. To assure normal
operation, we recommended Vln, Vout ; Vss ~ (V In or Vout ) ~ Vee.

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee· 5.0V±10%, Vss '" OV, Ta - 0 - +70·C, unless otherwise noted.)
Symbol

Item
RES,STBY
Input "High" Voltage
Input "Low" Voltage

EXTAL
Other Inputs

VIH

All Inputs

V IL
V OH

Output "Low" Voltage All Outputs

VOL

Three-state Current

TIMER,INT,

0 - 0"

min

typ

max

Vee-0.5

-

Vee+0 .3

Vee xO.7
2.0

-

V~+0.3

-0.3

Output "High" Voltage All Outputs

Input Leakage Current

Test Condition

IOH - -200j,lA

2.4

=-10j,lA
IOL = 1.6mA

Vee- 0.7

IOH

-

!lId

S'i'BY

Ao - A" Bo - B"
C9. - C" ADRo - ADR I3· ,
E ,R/W·

Vin" 0.5 - Vee-0.5
!lTSII

Operating
Current Dissipation"

Wait
Stop
Standby
All Terminals

Input Capacitance

lee

f-1MHz·"

Cin

f· lMHz, Vin" OV

-

Unit
V

Vee+0.3
O.B

V

-

-

V

0.55

V

1.0

j,lA

-

1.0

j,lA

5
2

10

mA

5

2
2

10
10
12

mA
j,lA

-

j,lA
pF

• Only at standby
•• VIM min = Vee-1.0V, VIL max" O.BV

*.* The value at f · xMHz is given by USing.
lee If ·xMHz)
•

=

lee If· lMHz) xx

AC CHARACTERISTICS (Vee" 5.0V±10%, Vss" OV, Te- 0 - +70·C, unless otherwise noted.)
Item

Symbol

Cycle Time

teye

Enable Rise Time
Enable Fall Time

tEr
tEf

Enable Pulsa Width{"High" Level)
Enable Pulse Width {"Low" Level)
Address Delay Time

PWEH
PW EL

Address Hold Time
Date Delay Time
Data Hold Time (Write)
Data Set-up Time (Read)
Data Hold Time (Read)

424

tAO
tAH
tow
tHW
tosA
tHA

Test
Condition

HD6305Xl/X2
typ
max

min
1

-450
450
Fig. 1

20

20
80
0

-

-

_HITACHI

10
20
20

-

250

250

-

HD63A05Xl/X2
typ
min
max
10
0.666

300
300

20

20
60
0

-

-

-

20
20

190

160

-

HD63B05Xl/X2
typ
min
max
10
0.5

-

220
220

20

20
TBD
0

-

-

Unit
j.IS

20
20

ns
ns

-

ns

TBD

ns
ns
ns

TBD
-

ns

ns
ns
ns

------------------------------------------------------HD6305X1,HD6305X2
• PORT TIMING (Vee = 5.0V±10%, Vss = OV, Ta = 0 - +70o C, unless otherwise noted.)
Item
Port Data Set·up Time
(Port A, B, C, D)
Port Data Hold Time
(Port A, B, C, D)
Port Data Delay Time
(Port A, B, C)

•

Symbol

Test
Condition

HD6305Xl/X2
min
typ
max
200

tpDS
Fig. 2

200

tpOH
tpow

-

Fig. 3

-

HD63A05Xl/X2
min
typ
max

-

200

-

200

300

-

-

HD63B05X I/X2
typ
min
max

Unit
ns

ns

-

200

-

-

200

-

-

300

-

-

300

ns

CONTROL SIGNAL TIMING (Vee=5.0V±10%, Vss = OV, Ta=0-+70°C, unless otherwise noted.)
Item
INT Pulse Width

Symbol

Test
Condition

t,vc

t'WL

INT2 Pulse Width

t'WL2

RES Pulse Width
Control Set·up Time

tRWL
tcs

Timer Pulse Width

tTWL

Oscillation Start Time (Crystal)
Reset Delay Time

tose
tRHL

HD6305Xl/X2
typ
min
max
+250
t cvc

+250
5
250

Fig. 5

tcyc

+250
Fig.5.Fig.20*

-

Fig. 19

80

HD63A05Xl/X2
typ
min
max

-

teye
+200
teye
+200

-

-

-

-

5
250

-

-

-

-

-

-

-

HD63B05Xl/X2
min
typ
max
teye
+2130
teye
+200

-

-

-

-

teye
+200

-

-

5
250
teye
+200

20

-

-

80

-

20

-

-

80

Unit

-

-

t cvc

-

-

ns

-

20

ms
ms

-

ns
ns

ns

* CL = 22pF ±20%, R. = 600 max.
• SCI TIMING (Vee = 5.0V±10%, Vss= OV, Ta = 0 - +70°C, unless otherwise noted.)
Item
Clock Cycle
Data Output Delay Time
Data Set·up Time
Data Hold Time

Symbol
tSeye
tTXD
tSRX
tHRX

Test
Condition

HD6305Xl/X2
HD63A05Xl/X2
typ
typ
min
max
min
max
1
32768 0.67
21845

-

Fig. 6,
Fig. 7

200
100

•

-

-

250

-

-

250

-

200
100

-

-

HITACHI

HD63B05Xl/X2
Unit
typ
min
max
0.5
16384 /.1.5
ns
250
ns
200
ns
100

-

-

425

HD6305Xl,HD6305X2--------------------------------_______________________

~---------_

t,., __________--I

E
'----PWEL---~

~---PWEHI---_+i

2.4V

Ao-AI3
R/W

Address Valid

O.6V

tow
MCU Write
00-07

MCU Read
00-07
Figure 1 Bus Timing

E

E
tV';"tP-ow--.J

Port
A,B,C,O

Port
A,B,C

2.4V
O.6V

Data
Valid

Figure 3 Port Data Delay Time (MCU Write)

Figure 2 Port Data Set-up and Hold Times
(MCU Read)
Interrupt
Test
E

Address
Bus

Vector Vector
MSB
LSB

New PC
Address

Address Address

Data Bus
Op
Code

R/W

PCsPC'3

Operand Irrelevant
Op Code Data

ACC

CC

\\-_____~I
Figure 4

426

IX

•

I nterrupt Sequence

HITACHI

Ve"ar Veclar

~:d~ess~~~r.ss

First Inst. of
Interrupt Routine

-------------------------------------------------------HD6305X1,HD6305X2

==::=u-t

E

5.5V4.5V

Vee

tose
STBY

Vee-O.SV

RES
Address
Bus

~

R/W

f!lllllI!JJ.w.

Data Bus

~II--------------~,---~#ho/~A____

:=r~
Figure5 Reset Timing
tSeye

Clock Output

2.4V

Cs/CK

O.6V

O.6V

Data Output

O.6V

2.4V

C7/TX

O.6V
tSRX

Data Input

2.0V

2.0V

Ca/Rx

O.BV

O.BV

Figure6 SCI Timing (internal Clock)

tscyC
Clock Input

Cs/CK

\

O.BV
~

Data Output
C7!TX

tTxD

)

O.BV

LI

2.0V

\

)

O.BV

t--

,

2.4V
O.6V

)

~ I---

tHRX

Data Input

\

2.0V

2.0V

Ca/RX

I

O.BV

O.BV

K

(

\

Figure7 SCI Timing(External Clock)

~HITACHI

427

HD6305Xl.HD6305X2-------------------------------------------------------Data Bus (DATAo - DATA 7)

Vcc
TTL Load
(Port)
Test point
terminal

IOL=1.6mA

This TTL compatible three-state buffer can drive one TTL
load and 90pF.

2.4kQ

C~--"""'----1'===i4i=~
90pF

-Address Bus (ADRo - ADR 13 )

Each terminal is TTL compatible and can drive one TTL
load and 90pF.

12kQ

-Input/Output Terminals (Ao - A7, Bo - B7, Co - C,)

These 24 terminals consist of four 8-bit I/O ports (A, 8, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
[NOTES I 1. The load capacitance in cludes story capacitance caused
by the probs. atc.
2. All diodas are 152074

®.

Figure 8 Test Load

-Input Terminals (Dt - 07)

These seven input-only terminals are TTL or CMOS compatible. Of the port D's, 06 is also used as INT2. If 06 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "I" to prevent an INT2 interrupt
from being accidentally accepted.
_STBY

- DESCRIPTION OF TERMINAL FUNCTIONS

The input and output signals of the MCU are described
here.
eVee. V5S

Voltage is applied to the MCU through these two terminals.
Vee is 5.0V ± 10%, while VSS is grounded.
_INT,INT2

External interrupt request inputs to the MCU. For details,
refer to "INTERRUPT". The (NT 2 terminal is also used as
the port 0 6 terminal.

This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
-CK (Cs)

Used to input or output clocks for serial operation.
-XTAL, EXTAL

These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
filter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.

- Rx (C6)

Used to receive serial data.
_Tx (C,)
Used to transmit serial data.

_TIMER

This is an input terminal for event counter. Refer to
"TIMER" for details.
_RES

Used to reset the MCU. Refer to "RESET" for details.
-NUM

This terminal is not for user application. In case of the
HD6305XI, this terminal should be connected to Vee
through IOkn resistance. In case of the H06305X2, this
terminal should be connected to VSS.
'
_Enable (E)

This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load
and a 90pF condenser.

-MEMORY MAP

The memory map of the MCU is shown in Fig. 9. $1000$IFFF of the HD6305X2 are external addresses. However,
care should be taken to assign vector addresses to $1 FF6 $1 FFF. During interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 10. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (pCH and PCL)
are stacked.

_ Read/Write (R!Wl

This TTL compatible output signal indicates to peripheral
and memory devices whether MCV is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser.

428

•

HITACHI

-------------------------------------------------------HD6305Xl,HD6305X2

o
12 7
12 8

255
25 6

$0000

1/0 Ports

Timer
SCI
'$007F

~0080
RAM
(128Bytes)
Stack

I~Off

8182
819 1
819 2

ROM'
(4,096Bytes)

---------

PORT
PORT
PORT
PORT

A
B
C
D

PORT A DDR

PORT B DDR
PORT C DDR

-REGISTERS
There are five registers which the programmer can operate.

o

. .J1 Accumulator

1-_ _ _ _ _ _ _ _

o

index
...JIRegister

I -_ _ _ _ _ _ _ _

\

Timer Data Reg
Timer CTRL Reg

Mlsc Reg

$08
$09
$OA

o
1-_ _ _ _ _ _

13

~"

$1 FF6

17
18

31
32
lJ

0

~~~~fer

r--r---r-r--r-.... Condition

Code

SCI CTRL Reg
SCI STS Reg
SCI Data Reg

Not Used
External
Memory Space

$10
$11
$12

~gg~~

Zero

L----Negative
L-----Interrupt
L-_ _ _ _ _ Mask
Half
Carry

$lF

$20

$7F

Figure 11 Programming Model

* Write only reg ister

$3FFF
area 1$1000 -

6 5

. ,............-r-'-r......,...., Reg ister

$2000

'ROM

IProgram

_ _ _ _ _ __J.Counter

Not Used

~!~~~~~t • $lFFF

16383

~~

1L..?_IL..0..l.10....11..:..01.:1
0.1.10:.J1_1.J.1..:..1.1..1_ _S_p_----II

$OFFF
$1000

External
Memory Space

$00
$01
$02
$03"
$04'
$05'
$06'

Not Used
8
9
10

$ 100

External
Memory Space

409 5
409 6

0
1
2
3
4
5
6

$1FFF)

** Read only regi ster

in the

• Accumulator (AI
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.

HD6305X2

is changed into External Memory Space.

Figure 9 Memory Map of MCU

I

7 6 543 2 1 0
Condition
n-4 1 1 1
n+l
Code Register
n-3

Accumulator

n+2

n-2

Index Register

n+3

n-l 1 1
n

I

PCW
PCl'

• Index Register (XI
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addreSSing mode, the register can
be used to store data temporarily.

Pull

n+4
• Program Counter (PC)
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.

n+5

Push

* In a subroutine call, only pel and PCH are stacked.

• Stack Pointer (SPI
The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fixed to 000000 II. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels .

Figure 10 Sequence of Interrupt Stacking

• Condition Code Register (CCI
The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-

•

HITACHI

429

HD6305Xl,HD6305X2--~--------------------------------------------____

tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"I").
Zero (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
CarryI
Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.

-INTERRUPT
There~

six different types of interrupt: external.interrupts (lNT,. IN.T.), internal timer interrupts (TIMER,
TIMER.), senal mterrupt (SCI) and interrupt by an instruction (SWI).

Of these six interrupts, the INT. and TIMER or the SCI
and TIMERl generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1
Interrupt

Priority of Interrupts
Priority

RES

Vector Address

1

$lFFE,

$lFFF

SWI

2

$lFFC,

$lFFD

INT

3

$lFFA,

$lFFB

TIMER/INT.

4

$lFFB,

$lFF9

SCI/TIMER.

5

$lFF6,

$lFF7

A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.
,---------,

IJiIT

y

iN'i2

y

1-1
$FF-SP
O-DDR',
CLR INT Logic
SFF-TDR
$7F-Timer Prescaler
$50-TCR
$3F-SSR
SOO-SCR
$7F-MR

TIMER
Y

Figure 12 Interrupt Flow Chart

430

y

eHITACHI

SCI

-------------------------------------------------------HD6305X1,HD6305X2
Bit 7 of this register is the INTi interrupt request flag.
When the faIling edge is detected at the INTz terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, SIFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.

In the block diagram, both the external interrupts INT and
INTz are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT interrupt request is automatically cleared if jumping is made to
the iN'f processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneoL !gister.
For the external interrupts (INT, INTz), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th~ority.
The INTz interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the 00 terminal can be tested by a BIL or
BIH instruction. The 00 falling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.

Miscellaneous Register (MR;$OOOA)

76543210

!

IMR7IMR61Z1Z1Z1Z1Z1Z1

f'--_________ INn Interrupt Mask

L..- - - - - - - - - - -

INT2 Interrupt Request Flag

Miscellaneous Register (MR; $OOOA)

Bit 6 is the INT2 interrupt mask bit. If this bit is set to "1",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "1" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "1" .

• Miscellaneous Register (MR; $OOOA)

The interrupt vector address for the external interrupt
INTz is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register caIled the miscellaneous register (MR; $OOOA) is available to control the
INTi interrupts.

-TIMER
Figure 14 shows a MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data

Vectoring genereted
$1 FFA, $1 FFB
BIH/BIL Test
Condition Cod. Register (CCI
fjij'f Inter·

rupt Latch

INT
Falling Edge Detector

>--4>_f---- Vectoring generated

$lFFB,$lFF9
TIMER

Serial Status

Register (SSR I
SCI/TIMER2

>---.....--- Vectoring generated
$lFF6,$lFF7

Figure 13 Interrupt Request Generation Circuitry

_HITACHI

431

HD6305Xl,HD6305X2---------------------------------------------------register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into 'the stack
and fetches timer interrupt routine address from addresses
$IFF8 and $IFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "I". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.

• Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)

' - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - T i m e r interrupt request

After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = 1). If the timer terminal is
"1", the counter starts counting down with "$FF" immediately after reset.
When "I" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2

TCR7

Timer interrupt request

o

Absent

TCR
Bit 5

Bit4

0

0

Present

Clock input source
I nternal clock E

TCR6

Timer interrupt mask

0

1

E under timer terminal control

o

Enabled

1

0

No clock input (counting stopped)

Disabled

1

1

Event input from timer terminal

Initialize

(Internal

Clockl
E--+--I

3

......_ _-r-_ _ _-,-_ _...... Timer Interrupt

Write

Read

Figure 14 Timer Block Diagram

432

Clock Source Selection

_HITACHI

-------------------------------------------------------HD6305Xl,HD6305X2
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3

-SERIAL COMMUNICATION INTERFACE (SCII
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from IllS to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 15.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.

Prescaler Division Ratio Selection

TCR
Bit 2

Bit 1

BitO

Prescaler division ratio

0

0

0

+1,

0

0

1

+2

0

1

0

+4

0

1

1

+8

1

0

0

+16

1

0

1

+32

1

1

0

+64

1

1

1

+128

A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer
interrupt occurs, "I" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.

-SCI Control Register (SCR; $0010)

SCI Control Registers (SCR; 0010)
E
Transfer
Clock
I...-,,--J~r-'

SCI Data Registers
(SOR: $0012)

Generator

L--L~.....I

+-____-1
Initialize

SCI Status Registers
(SSR :$00111

Not Used

SCI/TIMER2

Figure 15 SCI Block Diagram

•

HITACHI

433

HD6305X1,HD6305X2-------------------------------------------------------Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCR5="l" _ The bit can also be
cleared by writing "0" in it.

C, terminal

SCR7

o

Used as I/O terminal (by DOR).
Serial data output (DDR output)

Bit 6 (SSR6)
Bit 6 is the TIMERl interrupt request bit. TIMERl is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMERl')

C6 terminal

SCR6

o

Used as I/O terminal (by DDR).
Serial data input (DDR input)

SCR5 SCR4
0

0

0

Clock source

C s terminal

-

Used as I/O terminal (by
DDR).

I

-

1

0

Internal

Clock output (DDR output)

1

1

External'

Clock input (DDR input)

Bit 7 (SCR7)
When this bit is set, the OOR corresponding to the C,
becomes "\" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the OOR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".

Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When reset, it is set to "I".
Bit 4 (SSR4)
Bit 4 is the TIMERl interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMERl
interrupt (SSR6) is masked. When reset, it is set to "I".
Bit 3 (SSR3)
When "I" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits2-0
Not used.
SSR7

o

Bits 5 and 4 (SCR5, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".

SCRI

SCRO

Transfer clock rate
4.00 MHz
4.194 MHz

SCR2

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

I

I

I

I

I

1

1

1

1

32768 f.lS

1/32 s

TIMERl interrupt request

o

Absent
Present

SSR5

o

O.95 f.ls

2 f.lS

1.91 f.ls

4f.ls

3.82 f.lS

8f.ls

7.64f.ls

SSR4

I

o

-SCI Status Register (SSR; $0011)
76543210

434

SSR6

1 f.ls

-SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.

Absent
Present

Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".

SCR3

SCI interrupt request

SC I interrupt mask
Enabled
Disabled

TlMER2 interrupt mask
Enabled
Disabled

• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C, /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. \6.) When 8 bit of

_HITACHI

-------------------------------------------------------HD6305X1,HD6305X2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cs /
CK terminal is set as input. If the internal clock has been
selected, the Cs /CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 - 3 of the SCI
control register.

InpUt o.ta utch
TlmnglC.JRId

Figure 16 SCI Timing Chart

TIMER2 is commonly used with the SCI transfer clock
generator. If wanting to use TIMER2 independently of the
SCI, specify "External" (SCRS = 1, SCR4 = I) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the· prescaler of the transfer clock
generator to be initialized.
-I/O PORTS

There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load_ (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.

• Data Reception

By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are de·
termined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed afterreading subsequent received data. It must be taken
after reset and after not reading subsequent received data.
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register.

Bit of data
direction
register

Bit of
output
data

Status of
output

Input to
CPU

1

0

0

0

1

1

1

1

0

X

Figure 17

3-state

Pin

Input/Output Port Diagram

.TIMER2

The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 - 0 of the SCI control register
(4 p.s - approx. 32 ms (for oscillation at 4 MHz» is input to
bit 6 of the SCI status register and the TlMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMER2 can be used as a
reload counter or clock.
,--_ _@:::;4@

L

G)

Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET

: Transfer clock generator is reset and mask bit (bit 4
of SCI status register) is cleared.

®,@ : TIMER2 interrupt request
@.@ : TlMER2 interrupt reque.t bit cleared

•

The MCU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19 .

HITACHI

435

HD6305X1,HD6305X2-----------------------------------------------------5V

4.5V

Vcc

O V - - - - - -J

RES
Terminal

j

I ...... 1"':V'H V
RES

--------i'"
-

~::~al

k---------

tRHl

___________________

requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.

J----

AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-8.0MHz
Rs=6OQ max.

~

Figure 18 Power On and Reset Timing

Figure 21
100kU typ

Parameters of Crystal

2

Vee ....J"\A,"v--t---,

(a)

RES:;t;: 2.2/IF
HD6305X
MCU

Figure 19

Input Reset Delay Circuit

-INTERNAL OSCILLATOR
The internal oscillator circuit is designed to meet the
{NOTE) Use as short wirings as possible for connection of the crystal

with the EXTAL and XTAL terminals. Do not allow the..
wirings to cross others.

1-~>--6-t EXTAL

l·O-~.OMHzCJ 5

XTAL

10-22pF±20%

HD6305X
MCU

External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC 5 XTAL HD6305X
MCU

External Clock Drive

436

Typical Crystal Arrangement

-LOW POWER DISSIPATION MODE
The HD6305X has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator

Figure 20

Figure 22

HD6305X
MCU

Internal Oscillator Circuit

• Wait Mode
When WAlT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (iNT,
TIMER/INT2 or SCI/TIMER2), RES or SfBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releas·
ing from the wait mode the MeU executes the instruction
next to the WAIT. If an interrupt other than the INT (i.e.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control

_HITACHI

-------------------------------------------------------HD6305Xl.HD6305X2
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (mT or INTi), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop rnode escapes, then the CPU is brought to the opera·
tion mode and vectors to the interrupt routine. If the: inter·
rupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.

•

Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscilla·
tion starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "I". The dura·
tion of RES="O" must exceed tose to assure stabilized oscil·
lation.

• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high·impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.

HITACHI

437

HD6305Xl,HD6305X2------------------------------------------------------

Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop

Initialize
CPU. TIMER; SCI.
1(0 and All
Other Functions
No

No

1=1
Load PC from
Interrupt Vector
Addresses

Fetch
Instruction
Figure 23 Wait Mode Flow Chart

438

•

HITACHI

-------------------------------------------------------HD6305Xl,HD6305X2

Stop Oscillator
and All Clocks

No

Turn on Oscillator
Wait for Time Delay
to Stabilize

:)

Turn on Oscillator
Wait for Time Delay
to Stabilize

1=0
1=1
Load PC from
Interrupt Vector
Addresses

Fetch
Instruction

Figure 24 Stop Mode Flow Chart

_HITACHI

439

HD6305X1,HD6305X2----------------------------------------______________

O~I:'"'~

__I\_--+\._.:rr_~

!

Time required for oscillation to become
stabilized (built·in delay time)

Interrupt

STOP instruction
executed

Instructions
restart

(a) Restart by Interrupt

Oscillator 11111111111111111111111111111

E

Time required for oscillation to become
stabilized (tos e )

STOP instruction
executed

Reset
start

(b) Restart by Reset
Figure 25 Timing Chart of Releasing from Stop Mode

'-----~}I)--j_----'I
\
t

I

I

I

\

~-~-~--·~·~---------4Ir---------~r_--------J

tosc

Figure 26

Table 4

Mode

WAIT

-

Start

Soft·
ware

STOP
Stand·
by

440

Hard·
ware

Restart

Timing Chart of Releasing from Standby Mode

Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Timer,
Register,
Serial

Escape

Oscil·
lator

CPU

WAIT in·
struction

Active

Stop

Active

Keep

Keep

Keep

STBY, RES, INT, INT"
each interrupt request of
TIMER, TIMER" SCI

STOP in·
struction

Stop

Stop

Stop

Keep

Keep

Keep

STBY, RES, INT, INT,

STBY="Low"

Stop

Stop

Stop

Reset

Keep

High im·
pedance

•

HITACHI

RAM

1/0

terminal

STBY="High"

-------------------------------------------------------HD6305X1,HD6305X2

Figure 27

Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset

-BIT MANIPULATION
The MCU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM or an I/O port (except the
write-only registers such as the data direction register). Every
bit of memory or I/O within page 0 ($00 - $FF) can be tested
by the BRSET or BRCLR instruction; depending on the result
of the test, the program can branch to required destinations.
Since bits in the RAM, or I/O can be manipulated, the user
may use a bit within the RAM as a flag or handle a single I/O
bit as an independent I/O terminal. Fig. 28 shows an example
of bit manipulation and the validity of test instructions. In
the example, the program is configured assuming that bit 0
of port A is connected to a zero cross detector circuit and
bit I of the same port to the trigger of a triac.
The program shown can activate the triac within a time of
lOps from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse ~idth modulation of power is also possible.
SELF 1.

Figure 28

BRClR 0, PORT A, SELF 1
BSET 1 , PORT A
BClR 1, PORT A

Example of Bit Manipulation

the byte that follows the operation code.
• Direct

See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
2SSth address. All RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized.
• Extended

See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
• Relative

See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + ReI., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range + 129 to -127. A branch instruction
requires a length of 2 bytes.

-ADDRESSING MODES
• Indexed (No Offset)

Ten different addressing modes are available to the MCU.
• Immediate

See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The
effective address (EA) is PC and the operand is fetched from

•

S~e Fig. 33. The indexed addressing mode allows access
up to the lower 2SSth address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.

HITACHI

441

HD6305X1,HD6305X2---------------------------------------------------e Bit Test and Branch

e Indexed (8-bit Offset)

See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.

See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
elndexed (16-bit Offset!

See Fig. 35. The contents of the 2 bytes follOWing the
operation code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.

elmplied

See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.

e Bit Set/Clear

See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page O.

Me~Ory

EA

~

Adder

./

-

A

F8
Index Reg

I

:

:

Stack Point

PROG LOA #$F8 05BEI-:~A~6=:}-_ _ _ _ _ _~
05BFIF8

Prog Count

05CO
CC

~

·.

Figure 29

Example of Immediate Addressing

r--------.EA
Memory

oo4B

CATFCB32004BE::2~Oc:~~~==t===~~~~~----{A~~2~0~:J
kmt
Index Reg

PROG LOA CAT

J

0520~3]B6E~~_ _
052E~

·
··

4B

8
·
:

Prog !ount
052F
CC

..

Figure 30

442

Stack

Example of Direct Addressing

•

HITACHI

-------------------------------------------------------HD6305X1,HD6305X2

M.mbor~y==~--c:::::~0~6~E!::'::::::J

~

0000
A

:

:

40

~

Index Reg

I
Stack Point

CAT FCB 64 06E5~=4!!OC~~--------------J

Figure 31

Prog Count

040C
CC

Example of Extended Addressing

EA
04Cl

Memory
i

~.

A
Index

Reg

I

.

prog Count

04Cl

7
PROG BEQ PROG2 04A
04ABI-t::j2:[7:::::J:-t-..J
18

CC

~----1---------~

~
;

I

Figure 32

Example of Relative Addressing

EA
Memory

00B8

A

TABLFCCLIOOBB~~~4~C~~~--~~L--------t======~~~~~4~C~~
B6
49

n ex

e

Stack Point

Prog tount

05F5
CC

Figure 33

Example of I ndexed (No Offset) Addressing

•

HITACHI

443

HD6305X1,HD6305X2------------------------------------------------------

:,
TABl FCB
FCB
FCB
FCB

BF
86
DB
CF

EA
008C

,
:

MeJory

/

BF
86
DB
CF

0089
008A
008B
008C

Adder

""-

1

E6
89

§
.

I

I

0750

I

Prog Count

I

CC

Example of Index (8·bit Offset) Addressing

EA
0780

:

,

~

BF
86
DB
CF

03
Slack Pomt

,

Figure 34

TABl FCB
FCB
FCB
FCB

Index Reg

I
,

PROG lOA TABl X 069 2\
069 3L
0694

CF

I

:

:
PROG lOA TABL.X 075B
075C

A

06
07
7E

I

-iJ-----

I

BF
86
DB
CF

077 E
077 F
07B0
078 1

Figure 35

Example of Index (l6·bit Offset) Addressing

EA
0001

Memory

PORT B EQU 1 0001 I-~B~F_-f'"
0000

A
Index Reg

PROG BClR

6.

PORT B 058F
0590

t:=['Dt::::l
_____
j.
01

I

Stack Pomt

I
Prog Count

0591
CC

~
,,

Figure 36

444

,,
Example of Bit Set/Clear Addressing

•

HITACHI

---------------------------------------------------------HD6305Xl,HD6305X2
EA
Memory

0002

A

PORT C EOU 2 00021--.:.F,::.0_--fI

Index Reg

I

Stack POint

PROG SRCLR 2.PORT C PROG 2

~~~:~::~~t~::~I1-

Prog Count

0594
CC

05761--':"::.0--I L.r---,,;;--,

Figure 37

Example of Bit Test and Branch Addressing

EA

A
E5
Index eg
E5
Stack

Oint

Prog Count

0568
CC

Figure 38

Example of I mpl ied Addressing

• Branch Instructions

-INSTRUCTION SET

There are 62 basic instructions available to the HD6305X
Mev. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through 11.
• Register/Memory Instructions

Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305X MeV. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.

A branch instruction branches from the program sequence
in progress if a particular condition is established. See Table 7.
• Bit Manipulation Instructions

These instructions can be used with any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions

The control instructions control the operation of the MeV
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order

• Read/Modify/Write Instructions

These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify /
write group. See Table 6.

Table 10 lists all the instructions used on the HD6305X
MeV in the alphabetical order.
• Operation Code Map

Table 11 shows the operation code map for the instructions
used on the MeV.

@HITACHI

445

HD6305X1,HD6305X2-----------------------------------------------------Table 5 Register!Memory Instructions
Add_Inti Modes

Mnemonic

Operations

Indexed

Indexed
Immediate

OP #

-

OP #

-

OP #

OP #

-

load A from Memory

LOA

A6 2

2 B6 2

3 C6 3

AE 2

2 BE 2

3 CE 3

4

B7 2

3 C7 3

FF

1

-

OP #

-

OP #

-

Condition

Booleanl
Arithmetic
Operation

Indexed

Extended (No 0Ihet1 (B-BitOf!setl 116·BitOllsotl

Direct

4 F6

1

3 E6 2

4 06 3

5

M-A

FE

1

3

EE 2

4 OE 3

5

M-X

4 F7

1

4

fi,7

2

4 07 3

5

A_M

4 EF

2

4

Coda
H

1

N

Z

•
•
•
•

•

1\

1\

Load X from Memory

LOX

Store A in Memory

STA

Store X in Memory

STX

2

3 CF 3

4

OF 3

5

X_M

Add Memory", A

AOO

AB 2

2 BB 2

3 CB 3

4 FB 1

3 EB 2

4 OB 3

5

A+M_A

'oA

ADC

A9 2

2 B9 2

3 C9 3

4 F9

1

3 E9 2

4 09 3

5

A+M+C-A

1\

Subtract Memory

SUB

AO 2

2 60 2

3 CO 3

4 FO

1

3 EO 2

4 DO 3

5

A-M-A

A with Borrow

SBC

A2 2

2 B2 2

3 C2 3

4

F2

1

3 E2

2

4 02 3

5

A-M-C-A

AND Memory to A

ANO

A4 2

2 B4 2

3 C4 3

4

F4

1

3 E4 2

4 04 3

5

A·M-A

OR Memory with A

ORA

AA 2

2 BA 2

3 CA 3

4 FA

1

3 EA 2

4 OA 3

5 A+M-A

•
•
•

EOR

A8 2

2 B8 2

3 C8 3

4

F8

1

3 E8 2

4 08 3

5

A(f)M-A

•

CMP

Al

2 Bl

3 Cl

4 Fl

t

3 El

2

4 01

3

5

A-M

•

CPX

A3 2

2 B3 2

3 C3 3

4

F3

1

3 E3

2

4 03 3

5

X-M

A5 2

A·M

•
•
•
•

SF

1\

Add Memory and Carry

Subtract Memory from

•

Arithmetic Compare A
with Memory

2

2

3

Arithmetic Compare X
with Memory
Bit Test Memory with

A (Logical Compare)

BIT

2 B5 2

3 C5 3

4

F5

1

3 E5 2

4 05 3

5

Jump Unconditional

JMP

BC 2

2 CC 3

3 FC

1

2 EC 2

3 OC 3

4

Jump to SUbroutme

JSR

BO 2

5

co

6 FO

1

5 EO 2

5 00 3

6

3

•
•
•
•
• ,
•
•
•
•
•
•
• ,
•
• • •
• • •
1\

1\

1\

1\

1\

1\

1\

1\

1\

Exclusive OR Memory
with A

C

1\

1\

1\

1\

f,

1\

1\

1\

1\

t

1\

t

1\

r

1\

•
•
•
•
"
1\

/,

1\

•
•
•
"

,
•

•
•

Symbols: Op = Opsra'ion

# = Number of bytes
-

= Number of cycles

Table 6 Read/Modify/Write Instructions
Addressing Modes
()Perations

I
I

Indexed

Indexed

Mnemonic

Impl,ed(AI

Imph.d(XI

OP #

-

Increment

INC

4C

1

2 5C

1

2 3C 2

OP #

-

Direct

OP #

(NoOff18'1 18·S" Offsetl

- OP

#

-

OP #

-

H

5

7C

1

5 6C 2

8

•
A-l-A or X-l-X or M-l-M
•
OO-A or OO-X or OO-M
•
'A .....
X.....
•
OO-A-A or DO-X-X
OO-M ....
•
LotI I I I I I IbjJ •
1 H+H 1Oo~ •
LEH"'
c
D-i 1Hxr~ 1 1 1- 0 •
0; 1 l-f3": I I I-Dc •
:II-H":"I I 1-0 •
Equal '0 LSL
•
A-DO or X-DO or M-DO
•

Decrement

OEC

4A

1

2 SA

1

2 3A 2

5

7A

1

5 8A 2

8

Clear

CLR

4F

1

2

5F

1

2

3F 2

5

7F

1

5

6F 2

6

Complement

COM

43

1

2 53

1

2

33 2

5

73

1

5 63 2

6

(2'5 Complement)

NEG

40

1

2 50

1

2

30 2

5

70

1

5 60 2

6

Rotate Left Thru Carry

ROL

49

1

2 59

1

2 39 2

5

79

1

5 69 2

6

Rotate Right Thru Carry

ROR

46

1

2 56

1

2

5 76 1

5 66 2

6

Negate

36 2

A+1-A or X+1 ..... X or M+1 .....M

A or

X or M-M

or

M

AOfXorU

C

b,

Log«al SM, Lef,

LSL

48

1

2

58

1

2 38 2

5

78

1

5 6B 2

6

Logical Shift Right

LSR

44

1

2 54

1

2 34 2

5

74

1

5 64 2

II

ArithmetiC Shtft Right

ASR

47

1

2

57

1

2 37 2

5

77

1

5 67 2

6

Arithmetic Shift Left

ASL

48

1

2 58

1

2 38 2

5

78

1

5 68 2

6

TST

40 1

2 50 1

2 3D 2

4 70 1

4

5

---

rest for Negative

60 2

Symbols: Op· Operatton

# • Number of bytes
-

446

Oo

.

b,

or Zero

- Number of cycles

•

Condition
Code

Boolean/Arithmetic Operation

HITACHI

M

cr

b

Oo

'

C

t

N

Z

C

• , ", •
•
•
• 0, 1 •
1
•
• ,
• ,
•
1\

t

1\

•
•
•
•
•

A

A

A

1\

A

t

1\

1\

f,

0

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

•

-------------------------------------------------------HD6305X1,HD6305X2
Table 7 Branch Instructions
Addressing Modes
Operations

Mnemonic

Relative
OP

#

-

Branch Always

BRA

20

2

3

None

Branch Never

BRN

21

2

3

None

Branch IF Higher

BHI

22

2

3

c+z=o

Branch IF lower or Same

BlS

23

2

3

C+Z=l
c=o

Branch IF Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
Branch IF Equal

Condition Code

Branch Test
H

BCC

24

2

3

(BHS)

24

2

3

C=O

BCS

25

2

3

C=l

(BlO)

25

2

3

C=l

BNE

26

2

3

z=o
Z=1

BEQ

27

2

3

Branch IF Half Carry Clear

BHCC

28

2

, 3

H=O

Branch IF Half Carry Set

BHCS

29

2

3

H=l

Branch IF Plus

BPl

2A

2

3

N=O

Branch IF Minus

BMI

2B

2

3

N=l

3

1=0

Bit is Clear

2C

BMC

Bit is Set

2

I

I

i

•
•
•
•
•
•
•
•
•
•
•
•
•

C

.1.

--

I. • ~

!

BMS

20

2

3

1=1

Bil

2E

2

3

INT=O

BIH

2F

2

3

INT=l

BSR

AD

2

5

--

• • ~-~
• • • ·1·
i· • • • •
I

Branch IF Interrupt Line
is High
I

Branch to Subroutine

•
•
•
•
•
•
•
•
•
•
•
•
•
•

Z

i

Branch IF Interrupt Line
is low

N

• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
I
i·! • ·1· •
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Branch IF Interrupt Mask
Branch IF Interrupt Mask

I

Symbols: Op"" Operation
# s Number of bytes
- = Number of cycles

Table 8 Bit Manipulation Instructions
Operations
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n

Mnemonic

l

r

J

Addressing Modes
Boolean/
Bit Set Clear I Bit Test and Branch I Arithmetic
OP
OP
I Operation

:t ' -,

' BRSET n(n-0···7)
BRClR n(n =0···7)
BSET n(n=0···7)
10+2·n
BClR n(n=0···7)
11 +2·n

!:t: _

2·n I 3
101 +2·n i 3
I

!

2

2

51
51

Symbols: Op = Operat,on
# = Number of bytes

I5

!

51

I

,
Branch
Test

- - - - Mn=1

Mn=O

·11-Mn

--

I I -I O-Mn

--

I

Condition Code

L
, H , I

.'.•• •

IN ZC

•
• •
•
• • •

•
•
• •
• •
I'.

1\

- = Number of cycles

•

HITACHI

447

HD6305X1,HD6305X2-----------------------------------------------------Table 9 Control Instructions

Mnemonic

Operations

#

-

1
1

2
2

A~X

99
98

1
1

1

I~C

1

O~C

CLI
SWI
RTS
RTI
RSP

9B
9A
83
81
80
9C

1
1
1

2
2

O~I

NOP
OAA
STOP
WAIT

90
80
8E
8F

TXA
SEC
CLC
SEI

Clear Carry Bit
Set Interrupt Mask Bit
Clear Interrupt Mask Bit
Software Interrupt
Return from. Subroutine
Return from Interrupt
Reset Stack Pointer
No-Operation
Decimal Adjust A
Stop
Wait
Symbols: Op'" Operation
# = Number of bytes
.... = Number of cycles

Condition ~e

Boolean Operation

OP
97
9F

TAX

Transfer A to X
Transfer X to A
Set Carry Bit

Addressing Modes
Implied

H
X~A

1~1

10

1
1
1
1
1

5
8

1
1

2

$FF~SP

1

Advance Prog. CnU. Only

2
4
4

Converts binary add of BCD charcters Into
BCD format

•
•
•
•
•
•
•
•
?
•
•
•
-- •
•

I

N

Z

•
•
•
•1

•
•
•
•
•
•
•
•
?
•
•
•
•

• •

0
1

•
?
•
•
•
•
•

/\

C

• •1
• 0
•
• •
• •
• •
• •
? ?
• •
• •
• •
• •
/\

/\*

• Are BCD characters of upper byte 10 or more? (They are not cleared if set in advance.)

Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes

Condition Code

Bit
Indexed

Indexed

Set!

Test &

(S-Bit)

(IS-Bit)

Clear

Branch

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Mnemonic

Indexed
Implied

Immediate

Direct

ADC

X

X

X

ADD

X

X

AND

X

X

ASL

X

X

ASR

X

X

Extended Relative (No Offset)

BCC

X

BCS

X

BEQ

X

BHCC

X

BHCS

X

BHI

X

(BHS)

X

BIH

X

BIL
X

X

X

(BLO)

X

BLS

X

BMC

X

BMI

X

BMS

X

BNE

X

BPL

X

BRA

X

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

448

X
X

X

X

H

I

N

Z

C

/\

•

/\

/\

/\

/\

/\

/\

/\

/\

•

/\

/\

/\

/\

/\

/\

•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
/\

X

BCLR

BIT

Bit

• • •
• • •

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
/\

•
•
•
•
•
•
•

•
•
•
•
/\

•
•
•
•

• •

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

(to be continued)
C
/\

•?

CarrylBorrow
Test end Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

•

HITACHI

-------------------------------------------------------HD6305X1,HD6305X2
Table 10 Instruction Set (in Alphabetical Order)
Addressing Modes

Condition Code

Bit
Indexed

Mnemonic

Implied

Immediate

Direct

Extended RelatIve (No Offset)

BRN

Bit

Indexed

Indexed

Set·

Test &

(8-Bit)

(16-Bit)

Clear

Branch

X

BRCLR

X

BRSET

x

BSET

X

x

BSR
CLC

X

CLI

X

CLR

X

CMP
COM

X

X

CPX
X

DEC

X

EOR

X

X
X

DAA

INC

X
X

X

X

X
X

X

JMP

X

JSR

X

X

X

X

X

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

X

X

X

X

LOA

X

X

X

X

X

X

LOX

X

X

X

X

X

X

LSL

X

X

X

X

LSR

X

X

X

X

NEG

X

X

X

X

NOP

X

ORA

X

X

X

ROL

X

X

X

X

ROR

X

X

X

X

RSP

X

RTI

X

RTS

X

X

SBC

X

SEC

X

SEI

X

STA
STOP

X

SUB

X

SWI

X

TAX

X

TST

X

TXA

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

WAIT

X

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

X

C
1\

•?

I

• • • •

N

Z

C

• • •
• • •
• • • •
• • • •
• • • 0
0 • • •
• • 0 1 •
• •
1
• •
• •
• •
• •
•
• •
•
•
• •
• • • • •
• • • • •
• •
•
•
• •
• •
• • 0
• •
• • • • •
•
• •
• •
• •
• • • • •
? ? ? ? ?
• • • • •
• •
• •1 • • 1
• • • •
•
• •
• • • • •
•
• •
• •1
• • • •
• • • • •
• •
•
• • • • •
• • • • •
1\
1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

.\

1\

\

1\

,\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

(,

1\

(,

1\

1\

1\

x

STX

H

•
•
•
•
•
•
•

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

1\

Carry /Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

$

HITACHI

449

HD6305Xl,HD6305X2---------------------------------------------------Table 11
Bit Manipulation

0

Test 8.
Branch

Setl
Clear

0

1
BSETO

1

BRSETO
BRCLRO

2

Branch
Rei

OIR

2

3

BCLRO

BRA
BRN

BRSETl

BSETl

BHI

3
4

BRCLRl
BRSET2

BCLRl

BLS
BCC

5

BRCLR2

6
7

BRSET3

8
9

BSET2
BCLR2

Operation Code Map
Control

Read/Modify/Write
A
4

X

.Xl
6

5

.XO
7

NEG

IMP

IMP IMM

...

CMP

1

.-

-

SBC

2

BRSET4

BSET4

BHCC

LSlIASL

CLC

BCLR4
BSET5

BHCS
BPL

ROL

SEC

A

BRCLR4
BRSET5

DEC

B

BRCLR5

BCLR5

BMI

C

BRSET6

BSET6

BMC

ClI*
SEI*
RSP"

0

BRCLR6
BRSET7
BRCLR7

BCLR6
BSET7

BMS

E

3/5
(NOTES)

2/5

INC

2'5

12

-H IGH

0

CPX

3
4
5

STA
EOR
AOC
ORA
ADD
JMP(-l)

L

o

W

6
STA(+I} 7

8
9
A
B
C

OAA" NOP BSR" JSR(+2)
JSR(+l) JSRI+2} 0
LOX
STOP' WAIT' TXA'
STXltl} F
STX
1 5 1·' 1 '1 22 2/3 3/4 3/5 214 1/3

TST(-l)

2.'6

F

AND
BIT
LOA
TAX"

CLR
112

.XO

RTS"

BRCLR3

BCLR7

.Xl
E

SUB

ROR
ASR

TST

0

-

BNE
BEQ

TSTI-l}

.X2

C

RTI"·

A

BCS

BIL
BIH
213

EXT

9

SWI"

COM
LSR

OIR
B

8

BSET3
BCLR3

F

Register /Memory

re-

1. "-" is an undefined operation code.
2. The lowermost numbers in each column represent a byte count and the number of cycles required {byte count/number of cycles}.
The number of cycles for the mnemonics asterisked (*) is as follows:

AT1
8
TAX
2
5
ASP
2
ATS
SWI
10
TXA
2
DAA
2
BSA
5
STOP
4
eLi
2
WAIT
4
SEI
2
3. The parenthesized numbers must be added to the cycle count of the particular instruction.

•

Additional Instructions
The following new instructions are used on the HD6305X:
DAA Converts the contents of the accumulator into BCD
code.

450

WAIT Causes
see the
STOP Causes
see the

~HITACHI

the MCU to enter the wait mode. For this mode,
topic, Wait Mode.
the MCU to enter the stop mode. For this mode,
topic, Stop Mode.

HD6305YO,HD63A05YO,--HD63B05YO
CMOS MCU (Microcomputer Unit)
-PRELIMINARYHD6305YO is a CMOS 8-bit single-chip microcomputer
which includes a CPU upward compatible with the HD6305XO.
On the chip of the HD6305YO, 7872 byte ROM, 256 byte RAM,
55 I/O terminals, two timers and a serial communication interface (SCI) are built in. And three low power dissipation modes
(stop, wait and standby) support the low power operating.
Instruction set is upward compatible with the HD6805 family.

HD6305YOP, HD63A05YOP,
HD63B05YOP

• HARDWARE FEATURES
.8-bit based MCU
.7872 bytes of ROM
.256 bytes of RAM
.A total of 55 terminals, including 32 I/O's, 7 inputs and 16
outputs
• Two timers
8-bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
15-bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
.Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation. modes
- Wait .... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt function is operatable.
- Stop .... In this mode, the clock stops but the RAM
data, I/O status and registers are held.
- Standby.. I n this mode, the clock stops, the RAM data
is held, and the other internal condition is
reset.
• Minimum instruction cycle time
HD6305YO ..., 1115 (f = 1 MHz)
- HD63A05YO .... 0.67115 (f = 1.5 MHz)
- HD63B05YO .... 0.5115 (f 2 MHz)
• Wide operating range
VCC = 3 to 6V (f = 0.1 to 0.5 MHz)
HD6305YO
f =0.1 to 1 MHz (VCC =5V ± 10%)
HD63A05YO .... f = 0.1 to 1.5 MHz (VCC = 5V ± 10%)
HD63B05YO .... f = 0.1 to 2 MHz (VCC = 5V ± 10%)
.System development fully supported by an evaluation kit

(DP-64S)
HD6305YOF, HD63A05YOF,
HD63B05YOF

(FP-64)

• Three new instructions, STOP, WAIT and DAA, added to the
HD6805 family instruction set
• I nstructions that are upward compatible with those of Motorola's MC6805P2 and MC146805G2

=

• SOFTWARE FEATURES
.Similar to HD6800
• Byte efficient instruction set
• Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
o and all I/O terminals)
• A variety of interrupt operations
.Index addressing mode useful for table processing
• A variety of conditional branch instructions
• Ten powerful addressing modes
• All addressing modes adaptable to RAM, and I/O instructions

$

HITACHI

451

HD6305YO,HD63A05YO,HD63B05YO--------------------------------------------• PIN ARRANGEMENT
• HD6305YOP, HD63A05YOP, HD63B05YOP

o

•

HD6305YOF. HD63A05YOF. HD63B05YOF

Go

G,
G2
G3

G.
G,
G.
G,

EXTAL

NUM
TlMEA
A,

Ge

F,
F.
F.
F.
F3

F2
F,
Fo

E,
B.

E.

B.
B.

E.
E.

B3
B2

E3
E2

B,

E,

Bo

Eo

C,/Tx
C.I Ax
C,/a<

0,
D./iiii';
0,
D.

c.
C3

03

C2
C,

0,

02

CO-,L-_ _ _ _ _ _...r- Vee

(Top View)

(Top View)
•

BLOCK DIAGRAM
HUM

iN'f

TIMER

D,

o.Am;"
PortO

PortA

0,
D.
D,
D,
D,

o.

Port B

wii

I/O

t:·t
.eo::

Terminals

E,
E,
E,
E.
E,
E,
E,

F,
F,
F,
F,
F.
F.
F,
F,

Seo-iol

08ta
Register

Port E
Output
Terminals

Port F
Output

Terminals

...

Serial
Control

Register

G,

G,
G,

Go
Go
Go
G,

452

Input

Terminals

•

HITACHI

PortG
I/O
Terminals

-----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply voltage

Vee

-0.3- +7.0

V

I nput voltage

Yin

-0.3 - Vee + 0.3

V

Operating temperature

Topr

0-+70

°c

Storage temperature

T stg

-55-+150

°c

-

[NOTE1

These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal

operation, we recommended Vln, V out ; Vss;;; (V in or Vout );;; Vee .

• ELECTRICAL CHARACTERISTICS
• DC Characteristics IV ~
Item

Input
voltage
"High"

=5.0V ± 10%, Vss =GND and T. =0 SymDol

+70°C unless otherwise specified)

Test
condition

RES,STBY
EXTAL

VIH

min

typ

max

Unit

Vee- 0.5

-

Vee+ 0.3

V

Vee x 0.7

-

Vee+ 0.3

V

2.0

-

Vee+ 0.3

V

-0.3

-

0.8

V

Others
Input volt·
age "Low"

Current
dissipation

Input
leakage
current

All Input

VIL

Operating

-

5

10

mA

Wait

-

2

5

mA

lec

f = lMHz*

Stop

-

2

10

/J.A

Standby

-

2

10

/J.A

-

-

1

/J.A

-

-

1

/J.A

-

-

12

pF

TIMER,

INT,
0,-0"
STBY

Threestate
current

Ao -A7,
Bo -B 7,
Co -C 7,
Go -G 7,
Eo - E7**
Fo - F7**

Input
capacity

All
terminals

IIILI
Yin = 0.5IITSiI

Cin

Vee - 0.5V

f = 1MHz,
Yin OV

=

* The value at f == xMHz can be calculated by the following equation:
* * A t standby mode

•

ICC (f

= xMHz) = ICC If = 1MHz) multiplied by x

HITACHI

453

HD6305YO,HD63A05YO,HD63B05YO--------------------------------------------• AC Characteristics CVee = 5.0V ± 10%, Vss = GND and T. = 0 - +70o C unless otherwise specified)
HD6305YO

Test
condition

Symbol

Item

min

typ

-

HD63A05YO

HD63B05YO

max

min

typ

max

min

typ

4

0.4

10

0.666

-

6

0.4

10

0.5

-

-

-

tcyc
+200

Clock
frequency

fol

0.4

Cycle time

tcyo

1.0

INT pulse
width

tlwl

tO$c
+2 0

-

-

tcyc
+200

INT2 pulse
width

tlWl2

toyo
+250

-

-

tcyc
+200

-

-

tcyc
+200

RES pulse
width

tRwl

5

-

-

5

-

-

TIMER pulse
width

tTWl

toye
+250

-

-

tcyc
+200

-

-

-

-

20

-

-

80

-

-

80

-

=22pF ±
20%
Rs = 60n

tose

Reset delay
time

tRHl

MHz

10

Ils

-

ns

-

-

ns

5

-

-

tcye

tcyc
+200

-

-

ns

20

-

-

20

ms

-

80

-

-

ms

max
External cap.
2.21lF

• Port Electrical Characteristics CVee

=5.0V ± 10%, VSS = GND and Ta= 0 -

Output volt·
age "High"

typ

max

Unit

IOH = -2001lA

2.4

V

Vee - 0.7

-

V

IOl = 1.6mA

-

-

-

IOH = -lOpA

0.55

V

VIH

2.0

-

Vee + 0.3

V

Vil

-0.3

-

0.8

V

-1

-

1

/-I A

VOL

Input volt·
age "High"
Ports A,
B,C,D,
G

Input volt·
age "Low"

min

VO H

Ports A,
B,C,G,
E,F

Output volt·
age "Low"

+70°C unleSl otherwise specified)

Test
condition

Symbol

Item

Input leak·
age current

Yin = 0.5Vee - 0.5V

III

CVee = 5.0V±10%, Vss= GND and Ta= 0 - +70o C unleSlotherwise specified)
Item

Symbol

Clock~ycle

tScvo

Data Output Delay Time

tTXD

Data Set-up Time

tsRX

Data Hold Time

tHRX

454

8

Cl

Oscillation
start time
Ccrystal)

• SCI Timing

Unit

max

Test
Condition

HD6305YO
min

typ

1

-

-

Fig. 1,
Fig. 2

200
100

•

HD63A05YO

max

min

32768 0.67

HITACHI

-

max

min

-

21845

0.5

250

-

-

200

-

-

100

-

250

HD63B05YO

typ

-

200
100

typ

max

-

16384

-

Unit

250

/-Is
ns

-

ns

ns

-----------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
-

.INT,INT2

tscyC

External interrupt request inputs to the HD630SYO. For
details, refer to "INTERRUPTS". The INT2 terminal is also
used as the port D6 terminal.

Clock Output

CsiCK

o 6V

Data Output

...".,4 " ' V , - - i + - - - - - . r - - - - ; \ - - - - -

C1/TX

O""OP",

Cs/RX

.XTAL, EXTAL

o6v

', , --- 'OV~I-I

~r2'::

----

~'""B"'-V_ _ _ _ _----'O"'B!..VfL___,I-,_ _ __

These terminals provide input to the on-chip clock circuit.
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
fllter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals .
• TIMER

Figure 1 SCI Timing (Internal Clock)

This is an input terminal for event counter. Refer to
"TIMER" for details .
• RES

Used to reset the MCU. Refer to "RESET" for details .
• NUM

This terminal is not intended for user applications. It must
be grounded to Vss.
Data Input - - - - \ t 2 0 V

Ce/RX

20V~1;---

'

-'f.l!.O"'BV'----_ _ _ _ _"-OB'-"-V~~

Figure2 SCI Timing(External Clock)

Vcc
TTL Load
(Port)
Test
point
terminal

IOL=1.6mA

G,)
These 32 terminals consist of four 8-bit I/O ports (A, B, C,
G). Each of them can be used as an input or output terminal
on a bit through program control of the data direction register.
For details, refer to "I/O PORTS."
• Input Terminals (01 - 07)

These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to ~'I" to prevent an INT2 interrupt
from being accidentally accepted.

2.4kQ

o - - -.......---.-:==i4==-~
12kQ

40pF

• Input/Output Terminals (Ao - A7, Bo - B7. Co - C7. Go -

• Output Terminals (Eo - E7. Fo - F7)

These 16 output-only terminals are TTL or CMOS compatible .
• STBY
[NOTES]

1. The load capacitance includes stary capacitance caused
by the probe, etc.
2. All diodes are 152074

®

Figure 3 Test Load

This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby
Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI). They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."

• DESCRIPTION OF TERMINAL FUNCTIONS

The input and output signals of the HD630SYO are described
here.
eVee, Vss
Voltage is applied to the HD630SYO through these two
terminals. Vee is S.OV ± 10%, while VSS is grounded.

.CK ICs)
Used to input or output clocks for serial operation.
.Rx (C6)

Used to receive serial data.
.Tx (C7)

Used to transmit serial data .

•

HITACHI

455

HD6305YO,HD63A05YO,HD63B05YO-------·---------------MEMORY MAP
The memory map of the HD6305YO MCV is shown in
Fig. 4. During interrupt prqcessing, the contents of the MCV
registers are saved into the stack in the sequence shown in
Fig. 5. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (pCH and PCL)
are stacked.

-REGISTERS
There are five registers which the programmer can operate.

o

7

A _ _ _- - 11Accumulator
1....._ _ _ _
7
o
Index
X _ _ _- - 1 Register
1""'_ _ _ _

I

13
o
Program
PC_ _ _ _ _ _--'.Counter
1....._ _ _ _ _ _ _

I

13

6 5

0

1...0-'-10...
10....1.....
01....
0 ....
10......1_1....
1 .....
1 11--_ _
sP_ _....1~~~~fer

0
I '0 Ports
Timer
SCI

63

64

PORT A
0
1 PORT B
2 PORTC
3 PORT 0
4 PORT A DDR
5 PORT BOOR
6 PORT C DDR
7 PORT G DDR
8 Timer Data Reg
9 TImer CTRL Reg
10 MISC Reg
11
PORT E
12 PORT F
13 PORT G

1$0000

$003F

~0040
RAM
(192Bytes)

25 5
25 6

~FF\

Stack

$ 100

RAM
(64Bytes)

$013F
$0140

31 9
32 0
ROM
(7,872Bytes)

---------

818 2

,

819 1
819

Interrupt
Vectors

SOO

$1FFF
$2000

Not Used

16383

$3FFF

Figure 4

$3F
... Write only regi ster
...... Read only regis ter

Memory Map of HD6305YO MCU

Figure 6

Programming Model

$00

Not Used
63

.....r'-"""""'"

$OA
SOB
SOC

Not Used
16 SCI CTRL Reg $10
17 SCI STS Reg $11
18 SCI Data Reg $12

$1FF6

'--""'''''''"="1~ Code
Condition
~.....,
Register
Carry/
Borrow
Zero
'----Negative
'-----Interrupt
Mask
' - - - - - - - Half
Carry

S01
$02
$03"
$04'
$05'
$06'
$07*
$08
$09

• Accumulator (AI
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
• Index Register (X)
The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
• Prodl;am Counter (PCI
The program counter is a 14-bit register that contains the
address of the next instruction to be executed.

7 6 543 2 1 0
Pull
n-4 1 1 1 1 Condition
n+1
Code Register
n-3

Accumulator

n+2

n-2

Index Register

n+3

n-1 1 11
n

PCW
PCl'

n+4
n+5

Push
• In a subroutine call, only PCl and PCH are .. acked.

Figure 5

456

Sequence of Interrupt Stacking

• Stack Pointar (SPI
The stack pOinter is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address SOOFF. It is decremented when data
is pushed, and increiliented when pulled. The upper 8 bits
of the stack pointer are fIXed to 00000011. During the MeV
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address SOOFF. Since a subroutine or
interrupt can use space up to address SOOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels .
.Condition Code Registar (CCI
The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-

_HITACHI

---------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interr' ·,ts, except
a software interrupt, to be ma>,,~d. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed_)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic
"1").
Z~ro (Z):
Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is zero.
Carry/Represents a carry or borrow that occurred
Borrow (C): in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.
-INTERRUPT
There are six different types of interrupt: external interrupts (INT, INT2), internal timer interrupts (TIMER,
TIMER2), seridl interrupt (SCI) and interrupt by an instruction (SWI).

Of these six interrupts, the INT2 and TIMER or the SCI
and TIMER2 generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1 Priority of Interrupts
Interrupt

Priority

Vector Address

RES

1

$lFFE,

$lFFF

SWI

2

$lFFC,

$lFFD

INT

3

$lFFA,

$lFFB

TIMER/INT2

4

$lFF8,

$lFF9

SCIITIMER2

5

$lFF6,

$lFF7

A flowchart of the interrupt sequence is shown in Fig. 7.
A block diagram of the interrupt request source is shown in
Fig. 8.
y

ll'IT

y

1~1

TIMER

$FF~SP
O~DDR'S

CLR fN'i' Logic

Y

SCI

SFF~TDR
S7F~

Timer Prescaler

$50~TCR
S3F~SSR

$OO~SCR

S7F-MR

Figure 7

•

Interrupt Flowchart

HITACHI

457

HD6305YO,HD63A05YO,HD63B05YO--------------------------------------------In the block diagram, both the extemal interrupts INT and
INT2 are edge trigger inputs. At the falling edge of each input,
an interrupt request is generated and latched. The INT inter·
rupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT. request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT.), internal timer
interrupts (TIMER, TIMER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts accord·
ing to th~ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT falling edge detector circuit and
its latching circuit are independent of testing by these instruc·
tions. This is also true with the status of the INT2 terminal.

Bit 7 of this register is the INT2 interrupt request flag.
When the falling edge is detected at the INT2 terminal, "1"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: SIFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
76543210

IMR~MR61Z1Z1Z1Z1Z1Z1

1 1

-INT2 Interrupt Mask

L ____________

INT2 Interrupt Request Flag

Bit 6 is the INT. interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "1".

eMiscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT. is the same as that for the TIMER interrupt, as shown
in Table 1. For this reason, a special register called the miscel·
laneous register (MR; SOOOA) is available to control the
INT2 interrupts.

-TIMER

Figure 9 shows an MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data

Vectorin9 generated

$lFFA,$lFFB
BI H/BI L Test
Condition Code Register (C C I
i1\ff Interrupt Latch

INT
Falling Edge Detector

>--_+----

Vectoring generated
$lFFB,$lFF9

TIMER

Serial Status
Register (SSRI
SCI/TIMER.

r--......--- $lFF6,$lFF7
Vectoring generated
Figure 8

458

Interrupt Request Generation Circuitry

•

HITACHI

---------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the MCV saves its status into the stack
and fetches timer interrupt routine address from addresses
SIFF8 and SIFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "SFF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the can·
tents of the counter.
When the MCV is reset, both the prescaler and counter are
initialized to logic "I ". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
TCR7

Timer interrupt request

0

Absent

1

Present

TCR6
0
1

• TImer Control Register (TCR, $00091
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; S0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).

Timer Control Register (TCR; $0009)

L Presesler division ratio selection
Presesler initialize
' - - - - - - - - - Clock input source
' - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - T i m e r interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = I). If the timer terminal is
"1", the counter starts counting down with "SFF" immediately after reset.
When "I" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR

Clock Source Selection
Clock input sou~ce

Bit 5

Bit 4

0

0

Internal clock E

Timer interrupt mask

0

1

E under timer terminal control

Enabled

1

0

No clock input (counting stopped)

Disabled

1

1

Event input from timer terminal

Initialize

IInternal
Clock)

E--t--LJ

L...._ _...._ _ _-.-_ _- - ' Timer Interrupt

Write

Read

Figure 9

Timer Block Diagram

_HITACHI

459

HD6305YO,HD63A05YO,HD63B05YO------------------------------------------___
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +I, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3

-SERIAL COMMUNICATION INTERFACE (SCII
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from I /.Is to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. 10.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.

Prescaler Division Ratio Selection

TCR
BitO

Prescaler division ratio

Bit 2

Bit 1

0

0

0

+1'

0

0

1

+2

0

1

0

+4

0

1

1

+8

1

0

0

+16

1

0

1

+32

1

1

0

+64

1

1

1

+128

A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer
interrupt occurs, "I" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.

-SCI Control Register (SCR; $0010)

SCI Control Registers (SCR; $0010)
E
Transfer

Clock

L....-r-...L.-,--'

Gen era tor

Initialize

SCI Status Registers
(SSR :$0011)

SCI TIMER2
Figure 10

460

SCI Block Diagram

•

HITACHI

---------------------------------------------HD6305YO,HD63A05YO,HD63B05YO
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS="I". The bit can also be
cleared by writing "0" in it.

C7 terminal

SCR7

o

Used as I/O terminal (by DDRI.
Serial data output (DDR output)
C6 terminal

SCR6

o

Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit. TIMER2 is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER2')

Used as I/O terminal (by DDRI.
Serial data input (DDR input)

SCR5 SCR4

Clock source

Cs terminal

'0

1

-

1

0

Internal

Clock output (DDR outputl

1

1

External

Clock input (DDR inputl

0

0

Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set 01
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When reset, it is set to "I".

Used as I/O terminal (by
DDRI.

Bit 4 (SSR4)
Bit 4 is the TIMER2 interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TlMER2
interrupt (SSR6) is masked. When reset, it is set to "\".

Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C7
becomes "1" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0" .
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0" .

Bit 3 (SSR3)
When "I" is written in this bit, the prescaler of the tr'lDsfer
clock generator is initialized. When read, the bit always~, "0" ..
Bits2-0
Not used.
SSR7

o

Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".

SCR2
0

0

SCRl
0

SCRO
0

SSR6

TIMER2 interrupt request

o

Absent
Present

Transfer clock rate
4.00 MHz
4.194 MHz
11.15

Absent
Present

Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. Mter
reset, the bits are cleared to "0".

SCR3

SCI interrupt request

SSR5

o

0.951.1s

SCI interrupt mask
Enabled
Disabled

0

0

0

1

21.1s

1.911.1s

0

0

1

0

41.1s

3.821.1s

0

0

1

1

81.1s

7.641.1 5

SSR4

TIMER2 interrupt mask

I

I

I

I

I

I

o

1

1

1

1

32768l.1s

1/32 s

Enabled
Disabled

eSCI Data Reglltar (SDR;$OO121
A aerial-para1lel conversion register that is used for transfer
of date.
eSCI Statui Rlgiltar (SSR; $00111

7

§

543210

ISSR7ISSR§ISSR5ISSR4ISSR3~

$

• Data Transmission
By writing the desired control bits into the SCI conlrd
registers, a transfer rate and a source of transfer c10,';: il"
determined and bits 7 and 5 of port C are set at the \·,';'ai
data output terminal and the serial clock terminal, 1"'·7.·,;:·
tively. The transmit data should be stored from the ac,'~,:n"
lator or index register into the SCI data register. Th,'  have a protection circuit In their Input terminals against high electrostetic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to the.. high Input impedance circuits. To assure normal
operation, we recommended Vln. Vout: Vss:i! (Vln or Vout):i! Vee.

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee '" !\.OV±10%, Vss" OV, Ta '" 0 - +70oC, unless otherwise noted.)
Item

Symbol

Test Condition

RES, STBY
Input "High" Voltage

EXTAL

V 1H

All Inputs

V OH

Output "Low" Voltage

All Outputs

VOL

I nput Leakage Current

TIMER,INT,
0 1 -D 7 ,STBY

illd

A o -A 7 ,Bo -B 7 ,
Co -C 7 , ADRo - ADR I3' ,
E', Rm'

max

-

Vcc+0.3

O.B

V

-

-

V

0.55

V

1.0

/lA

-

1.0

/lA

5

10

mA

2

5

mA

2

10

/lA

2

10

-

12

/lA
pF

-0.3

V 1L

Output "High" Voltage All Outputs

Three-state Current

typ

Vcc xO.7
2.0

Other Inputs
Input "Low" Voltage

min
Vce-0.5

IOH '" -200/lA

2.4

IOH '" -10/lA

V c e- D.7

-

IOL-l.6mA

Vin '" 0.5 - V cc-0.5

-

ilTSl1

Operating
Current Dissipation"

Input Capacitance

Wait

f = lMHz"'-

Icc

Stop
Standby
All Terminals

-

f = 1MHz. Vin = OV

Cin

Unit
V

V cc +O·3
Vcc +O·3

• Only at standby
•• VIH min = Vec-1.OV. VIL max = O.8V
*.* The value at f = xMHz is given by using.
Icc (f· xMHz) • Icc (f = lMHz) x x
•

AC CHARACTERISTICS (Vee = 5.0V±10%, Vss '" OV, Ta '" D - +70°C, unless otherwise noted.)
Item

Symbol

Test
Condition

HD6305Y1/Y2
typ
max

min

HD63A05Y1/Y2
min

typ

HD63B05Y1/Y2
min

typ

max
20

/ls
ns

20

ns

-

ns

-

10

0.666

-

10

0.5

20

-

-

20

-

20

-

-

-

20

-

300

-

220

-

-

300

-

250

-

-

-

220

-

-

-

190

-

-

20

-

20

-

-

20

-

tow

-

-

-

-

20

tOSR

80

60

TBD

Data Hold Time (Read)

tHR

0

-

-

20

Data Set-up Time (Read)

-

160

20

-

250

tHW

-

0

Cycle Time

tCYC

Enable Rise Time

tEr

Enable Fall Time
Enable Pulse Width("High" Level)

tEf
PW EH

450

Enable Pulse Width("Low" Level)

PW EL

450

Address Delay Time

tAO

Address Hold Time

tAH

Data. Delay Time
Data Hold Time (Write)

480

1

-

Fig. 1

•

-

-

HITACHI

0

Unit

max

10

ns

TBD

ns
ns

-

TBD

ns

-

-

ns

-

ns
ns

-------------------------------------------------------HD6305Yl,HD6305Y2
•

PORT TIMING (Vee

=5.0V±10%, Vss =OV, Ta =0 -

Item
Port Data Set-up Time
(Port A, B, C, D)

•

Symbol

Test
Condition

-

-

HD63A05Yl/Y2
typ
min
max

min

-

200

200

-

HD63B05Yl/Y2
typ
max

-

Fig. 2
tpDH

Port Data Delay Time
(Port A, B, C)

tpDw

Fig_ 3

CONTROL SIGNAL TIMING (Vee = 5.0V±10%, Vss

INT Pulse Width

HD6305Yl/Y2
typ
max
min
200

tpDs

Port Data Hold Time
(Port A, B, C, D)

Item

+70°C, unless otherwise noted.)

Symbol

Test
Condition

t lWL2

-

-

200

-

-

200

-

-

300

-

-

300

-

=OV, Ta =0 min

ns

300

ns

HD63A05Yl/Y2

HD63B05Yl/Y2

typ

max

min

typ

max

min

typ

max

-

-

-

-

-

-

-

teye
+200
teye
+200

-

-

teye
+200
teye
+200

-

-

5

-

250

-

-

+250
tcyc

+250

RES Pulse Width

tAwL

Control Set-up Time

tes

Timer Pulse Width

tTWL

Oscillation Start Time (Crystal)
Reset Delay Time

tose

Fig.5.Fig.20·

-

tAHL

Fig. 19

80

Fig. 5

-

-

tcyc

+250

ns

+70°C, unless otherwise noted.)

HD6305Y1IY2
tcyc

tlWL

!NT 2- Pulse Width

200

i

Unit

-

Unit
ns
ns

5

-

-

5

250

-

250

-

-

teye
+200

-

-

tcye
+200

-

-

20

-

-

20

-

ms

80

-

-

80

-

20

-

-

ms

tCyc

ns
ns

• CL = 22pF ±20%, R. = 600 max.

• SCI TIMING (Vee = 5.0V±10%, Vss= OV, Ta = 0 - +70o C, unless otherwise noted.)
Item

Symbol

Clock Cycle

tScye

Data Output Delay Time

tTXD

Data Set-up Time

tSRX

Data Hold'Time

tHRX

Test
Condition

HD6305Yl/Y2
typ
max

min
1

-

Fig. 6,
Fig. 7

200
100

•

-

HD63A05Yl/y2
min

21845

0.5

-

16384

jJs

250

-

-

250

ns

-

200
100

-

-

ns

-

-

-

200

-

100

-

-

HITACHI

Unit

max

250

32768 0.67

H D63B05Y 1IY2
typ
min
max

typ

ns

481

HD6305Y1,HD6305Y2-------------------------------------------------------

\4----------- t c v c - - - - - - - - - - . - . i
E

2.4V

Ao-A13
R/W

O.6V
tow

MCU Write

00-07

MCU Read

00-07
Figure 1 Bus Timing

E

2.4V

t=v /

E

tpow

Port
A,B,C,D

Port
A,B,C

2.4V
O.6V

Data
Valid

Figure 3 Port Data Delay Time (MCU Write)

Figure 2 Port Data Set-up and Hold Times
(MCU Read)
Interrupt
Test
E

Address
Bus

Data Bus

R/W

Op

Operand Irrelevant

Code

Op Code Dala

PC8PC'3

IX

Vee10r Vector

~dsd~.ss~~:r.ss

1

\ \ -_ _ _ _ _ _....J

Figure 4 I nterrupt Sequence

482

CC

_HITACHI

First Inst. of
Interrupt Routine

-------------------------------------------------------HD6305Yl,HD6305Y2
~:=-u--L

E

'~
4.5V

Vee

tose

I

STBY

Vee-O.5V

RES

------II

Address
Bus

B\I

R/W

ij!l.~/!l!l/ll

Data Bus

Figure5 Reset Timing
tSeye
Clock Output
Cs/CK

\

2.4V
O.6V

-

O.6V

\

II

-,'1
O.6V

tTXD I---

Data Output

)

C7/TX

,I

2.4V
O.6V

,/

~

~ t---

Data Input
Ca/Rx

tHRX

2.0V

2.0V

O.8V

O.8V

K

(

\

Figure6 SCI Timing (Internal Clock)

tseye
Clock Input
Cs/CK

\

2.0V

Data Output
C7/TX

O.8V

O.8V

1/

Ca/Rx

I
O.8V

tTxD I---

'I

'l-2.4V

)

O.6V

)

~ r- Data Input

\

tHRX

). 2.0V

2.0V

O.8V

O.8V

(

K

,

,

Figure7 SCI Timing(External Clock)

_HITACHI

483

HD6305Y1,HD6305Y2-------------------------_Data Bus (DATAo -DATA 71

Vee
TTL Load
(Port)

Test point
terminal

IOL=1.6mA

This TTL compatible three-state buffer can drive one TTL
load and 90pF.

2.4kQ

o>-----4t----1==~i=~
90pF

-Address Bus (ADR o - ADR131

Each terminal is TTL compatible and can drive one TTL
load and 90pF.

12kQ

-Input/Output Terminals lAo - A7, Bo -- B7, Co - C7 I

These 24 terminals consist of four,8-bit I/O ports (A, B, C).
Each of them ,can be used as an input or output terminal on
a bit thrQugh program control of the data direction register.
For details, refer to "I/O PORTS."
[NOTES] 1. The load capacitance includes stary capacitancecausad
by the probe, etc.
2. All diodes are 1S2074(8).

Figure 8 Test Load
- DESCRIPTION OF TERMINAL FUNCTIONS

The input and output signals of the MCU are described
here.
.Vcc,VSS
.
Voltage is applied to the MCU through these two termmals.
Vee is S.OV ± 10%, while Vss is grounded.
-INT,INT2

External interrupt request inputs to the MCU. For details,
refer to "INTERRUPT". The INT2 terminal is also used as
the port D6 terminal.

- Input Tarminals 101 - 07 I

These seven input-only terminals are TTL or CMOS compatible. Of the port D's, D6 is also used as INT2. If D6 is
used as a port, the INT2 interrupt mask bit of the miscellaneous register must be set to "I" to preve~t an INT2 interrupt
from being accidentally accepted.
_STBY

This terminal is used to place the MCU into the standby
mode. With STBY at "Low" level, the oscillation stops and
the internal condition is reset. For details, refer to "Standby Mode."
The terminals described in the following are I/O pins for
serial communication interface (SCI)_ They are also used as
ports Cs , C6 and C7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
_CK (Csi

Used to input or output clocks for serial operation.

-XTAL, EXTAL

These terminals provide input to the on-chip clock circuit .•
A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic
filter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.

_Rx IC61

Used to receive serial data.
_Tx IC71

Used to transmit serial data.

_TIMER

This is an input terminal for event counter. Refer to
"TIMER" for details.
-RES

Used to reset the MCU. Refer to "RESET" for details.
_NUM

This terminal is not for user application. In case of the
HD630SY I, this terminal should be connected to Vee
through 10kn resistance. In case of the HD630SY2, this
terminal should be connected to Vss.
eEnable (EI

This output terminal supplies E clock. Output is a singlephase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external clock frequency. It can drive one TTL load
and a 90pF condenser.

-MEMORY MAP

The memory map of the MCU is shown in Fig. 9. $0140$IFFF of the HD6305Y2 are external addresses. However,
care should be taken to assign vector addresses to $1 FF6 $1 FFF. During interrupt processing, the contents of the CPU
registers are saved into the stack in the sequence shown in
Fig. 10. This saving begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the higher byte (PCH) of the program
counter, index register (X), accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call, only the contents of the program counter (PCH and PCL)
are stacked.

e Read/Write (RJW)

This TTL compatible output signal indicates to peripheral
and memory devices whether MCU is in Read ("High"), or
in Write ("Low"). The normal standby state is Read ("High").
Its output can drive one TTL load and a 90pF condenser .

484

•

HITACHI

-------------------------------------------------------HD6305Yl,HD6305Y2

o

o Ports
Timer
SCI

63
64

255
256

319
320

-REGISTERS

I

RAM
(192Bytes)
Stack

$0000

0
1
2
3
4
5
6

$003F
$0040

~OFF

PORT A DDR
PORT BOOR
PORT C DDR

\
$013F

B

TImer Data Reg

9

Timer CTRl Reg

10

_IIIIISC

He9

S08
$09
$OA

$0140

ROM·

There are five registers which the programmer can operate.

$00
SOl
S02
S03"
S04'
$05'
S06'

Not Used

$ 100

RAM
(64Bytes)

PORT A
PORT B
PORT C
PORT D

Not Used

o

7

I'-_ _ _ _A_ _ _ _.....IAccumulator
7
o
Reglster
I'-_ _ _ _X_ _ _ _.....Iindex
o

13

IProgram

I

L.-_ _ _ _ _ _ _
PC_ _ _ _ _ _ _...... Counter

13

6 5

0

IL.°...JIL...°.L.lo.....
I0...l.lo.....IL...°L..I'.....I_'.1..I_ _s_p_--.J~~~~fer

(7,872Bytes)
8182
8191
8192

16
17
18

---------

$lFF6
117~~~~~~t • $lFFF
$2000

31

SCI STS Reg
SCI Data Reg

Not Used

$10
$11
$12

~g~~~~

Zero
'-----Negative
'-------Interrupt
Mask
'--------Half
Carry

$lF

3.,\ Memory Space $20

External
Memory Space

16383

SCI CTRL Reg

External

63
$3FFF

$3F

Figure 11 Programming Model

* Write only regi ster
* * Read only regi ster

'ROM are a ($0140 - $1 FFF) in the HD6305Y2
is changed into External Memory Space.

_ Accumulator (A)
This accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.

Figure g Memory Map of MCU
_Index Register (X)

I

7 6 543 2 1 0
Condition
n-4 1 1 1 Code
Register n+l
n-3

Accumulator

n+2

n-2

Index Register

n+3

n-l 1

'1

n+4

n

PCW

Pull

The index register is an 8-bit register, and is used for index
addressing mode. Each of the addresses contained in the
register consists of 8 bits which, combined with an offset
value, provides an effective address.
In the case of a read/modify/write instruction, the index
register can be used like an accumulator to hold operation
data or the result of operation.
If not used in the index addressing mode, the register can
be used to store data temporarily.
_ Program Counter (PC)

PCl'

n+5

Push

, In a subroutine call, onlv PCl and PCH are stacked.

Figure 10 Sequence of Interrupt Stacking

The program counter is a 14-bit register that contains the
address of the next instruction to be executed.
_ Stack Pointer (SP)

The stack pOinter is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address SOOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fIXed to 000000 11. During the MCU
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address SOOFF. Since a subroutine or
interrupt can use space up to address SOOCI for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels.
_ Condition Code Register (CC)

The condition code register is a 5-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-

_HITACHI

485

HD6305Y1,HD6305Y2--------------------------------~-------------------

tions. The CC bits are as follows:
Half Carry (H): Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I): Setting this bit causes all interrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, it is
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the instruction following the
CLI has been executed.)
Negative (N): Used to indicate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bit 7 is logic

Of these six interrupts, the INTz and TIMER or the SCI
and TIMERz generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status is saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
is obtained from a particular interrupt vector address. Then
the interrupt routine starts from the start address. System
can exit from the interrupt routine by an RTI instruction.
When this instruction is executed, the CPU status before
the interrupt (saved onto the stack) is pulled and the CPU
restarts the sequence with the instruction next to the one at
which the interrupt occurred. Table 1 lists the priority of
interrupts and their vector addresses.
Table 1

"1 ").
Zero (Z):

Carry!
Borrow (C):

Used to indicate that the result of the most
recent arithinetic operation, logical operation
or data processing is zero.
Represents a carry or borrow that occurred
in the most recent arithmetic operation. This
bit is also affected by the Bit Test and Branch
instruction and a Rotate instruction.

-INTERRUPT
There~ six different types of interrupt: external interrupts (INT,. IN.Tz), internal timer interrupts (TIMER,
TIMERz), senal mterrupt (SCI) and interrupt by an instruction (SWI).

Interrupt

Priority of Interrupts
Priority

RES

1

$lFFE,

$lFFF

SWI

2

$lFFC,

$lFFD

INT

3

$lFFA,

$lFFB

TIMER/INT2

4

$lFF8,

$lFF9

SCI/TIMERz

5

$lFF6,

$lFF7

r-------,

1~1

$FF~SP
O~DDR's

CLR INT Logic
$FF~TDR

Prescaler

$50~TCR
$3F~SSR

$OO~SCR
$7F~MR

Figure 12 Interrupt Flow Chart

486

•

----------

-

A flowchart of the interrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source is shown in
Fig. 13.

$7F~ Timer

Vector Address

HITACHI

-------------------------------------------------------HD6305Y1,HD6305Y2
In the block diagram, both the external interrupts INT and
INT2 are edge trigger inputs. At the faIling edge of each input,
an interrupt request is generated and latched. The INT inter·
rupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT2 request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT2), internal timer
interrupts (TIMER, T1MER2) and serial interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code register is set. Immediately after the I bit is
cleared, the corresponding interrupt processing starts according to th~ority.
The INT2 interrupt can be masked by setting bit 6 of the
miscellaneous register; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by setting bit
5 of the serial status register; and the TIMER2 interrupt by
setting bit 4 of the serial status register.
The status of the INT terminal can be tested by a BIL or
BIH instruction. The INT faIling edge detector circuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the INT2 terminal.

• Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT2 is the same as that for the TIMER interrupt, as shown
in Table I. For this reason, a special register called the miscellaneous register (MR; SOOOA) is available to control the
INTi interrupts.

Bit 7 of this register is the iN'f2 interrupt request flag.
When the faIling edge is detected at the iN'f2 terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: $IFF8, $IFF9) checks bit 7 to see if it
is INT2 interrupt. Bit 7 can be reset by software.
Miscellaneous Register (MR;$OOOA)
76543210

IM~R6iZlZlZlZlZlZl

Q-----------

iNTi Interrupt Mask
INTl Interrupt Request Flag

Bit 6 is the INT2 interrupt mask bit. If this bit is set to "I",
then the INT2 interrupt is disabled. Both read and write are
possible with bit 7 but "I" cannot be written in this bit by
software. This means that an interrupt request by software
is impOSSible.
When reset, bit 7 is cleared to "0" and bit 6 is set to "I" .
-TIMER
Figure 14 shows a MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data

Vectoring generated
$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register (CC)

Falling Edge Detector

r-.....+---- Vectoring generated
$IFF8,$IFF9
TIMER

Serial Status

Register (SSR)
SCI/TIMER.

>---......- - - Vectoring generated
$IFF6,$IFF7

Figure 13 Interrupt Request Generation Circuitry

•

HITACHI

487

HD6305Y1,HD6305Y2------------------------------------------------------register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into the stack
and fetches timer interrupt routine address from addresses
$lFF8 and $lFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer input terminal.
Once the timer count has reached "0", it starts counting
down with "$FF". The count can be monitored whenever
desired by reading the timer data register. This permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "1". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.

• Timer Control Register ITCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TCR; $0009)

L Prescater division ratio selection
Prescaler initialize
' - - - - - - - - - - - C l o c k input source
' - - - - - - - - - - - - Timer interrupt mask
- - - - - - - T i m e r interrupt request
After reset, the TCR is initialized to "E under timer terminal control" (bit 5 ~ 0, bit 4 ~ 1). If the timer terminal is
"I ", the counter starts counting down with "$FF" immediately after reset.
When "I" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2

TCR7

Timer interrupt request

o

Absent

TCR

Clock input source

Bit 5

Bit 4

0

0

Internal clock E
E under timer terminal control

Present
TCR6

Timer interrupt mask

0

1

o

Enabled

1

0

No clock input (counting stopped)

Disabled

1

1

Event input from timer terminal

Initialize

(Internal
Clock)

E ---+--L~

3

' -_ _--.-_ _ _ _. -_ _...J Timer Interrupt

Write

Read

Figure 14 Timer Block Diagram

488

Clock Source Selection

•

HITACHI

--------------------------------------------------------HD6305Y1,HD6305Y2
A prescaler division ratio is selected by the combination of
three bits (bits 0, I and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2,74,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3

-SERIAL COMMUNICATION INTERFACE (SCn
This interface is used for serial transmission or reception
of 8·bit data. Sixteen transfer rates are available in the range
from I jJS to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one eighth counter and
one prescaler. (See Fig. IS.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.

Prescaler Division Ratio Selection

TCR
Bit 2

Bit 1

0

0

0

0

BitO
0

Prescaler division ratio
+1

,.

1

+2

0

0

+4

0

1

1

+8

1

0

0

+16

1

0

1

+32

1

1

0

+64

1

1

1

+128

A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer
interrupt occurs, "I" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.

-SCI Control Register (SCR; $0010)

SCI Control Registers (SCR; $0010)
E
Transfer
Clock
L-r--'~r--I

Generator

SCI Data Registers ........L~---I
(SOR: $0012)
...._ _ _ _- ;
Initialize

SCI Status Registeis
(SSR :$00111

Not Used

SCI/TIMERz
Figure 15 SCI Block Diagram'

$

HITACHI

489

HD6305Y1,HD6305Y2------------------------------------------------------Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCR5="I". The bit can also be
cleared by writing "0" in it.

C7 terminal

SCR7

o

Used as I/O terminal (by DDR).
Serial data output (DDR output)

SCR6

C6 terminal

o

Bit 6 (SSR6)
Bit 6 is the TIMERl interrupt request bit. TIMERl is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER1')

Used as I/O terminal (by DDR).
Serial data input (DDR input)

SCR5 SCR4

Clock source

Cs terminal

Bit 5 (SSR5)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When reset, it is set to "I ".

0

0

-

0

1

-

1

0

Internal

Clock output (DDR output)

1

1

External

Clock input (DDR input)

Used as I/O terminal (by
DDR).

Bit 4 (SSR4)
Bit 4 is the TIMERl interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMERl
interrupt (SSR6) is masked. When reset, it is set to "I".

Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C7
becomes "I" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C6
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".

Bit 3 (SSR3)
When "I" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 - 0
Not used.
SSR7

o

Bits 5 and 4 (SCR5, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0".

SCRO

Absent
Present

Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".

SCRI

SCI interrupt request

SSR6

TIMERl interrupt request

o

Absent
Present

Transfer clock rate
4.194 MHz
4.00 MHz

SCR3

SCR2

0

0

0

0

l/ts

0.95/ts

0

0

0

1

2/ts

1.91 /ts

0

0

1

0

4/ts

3.82/ts

0

0

1

1

8/ts

7.64/ts

SSR4

TIMERl interrupt mask

I

I

I

I

I

I

1

1

1

o

1

32768/ts

1/325

Enabled
Disabled

SSR5

o

76543210

490

•

Enabled
Disabled

-SCI Data Registar (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
-SCI Status Register (SSR; $0011)

SCI interrupt mask

• Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written in the SCI data register is output from the C7 /Tx
terminal, starting with the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of

HITACHI

-------------------------------------------------------HD6305Y1,HD6305Y2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cst
CK terminal is set as input. If the internal clock has been
selected, the CS /CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 - 3 of the SCI
control register.

Inpul Oal. Lalch
T,mlng ~C.IAx~

Figure 16 SCI Timing Chart

• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy-writing or -reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the in terrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the Cs /CK terminal. If the internal
clock has been selected, the Cs/CK terminal is set as output
and clocks are output at the transfer rate selected by bits 03 of the SCI control register.

TIMERl is commonly used with the SCI transfer clock
generator. If wanting to use TIMER:z independently of the
SCI, specify "External" (SCRS = I, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
writing the SDR causes the' prescaler of the transfer clock
generator to be initialized.
-I/O PORTS

There are 24 input/output terminals (ports A, B, C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "1" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset. the data direction register and data register go
to "0" and all the input/output terminals are used as input.

Bit of data
direction
register

Bit of
output
data

Status of
output

Input to
CPU

1

0

0

0

1

1

0

X

Figure 17

1

3-state

1

Pin

Input/Output Port Diagram

.TIMERl

The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 - 0 of the SCI control register
(4).1s - approx. 32 ms (for oscillation at 4 MHz» is input to
bit 6 of the SCI status register and the TIMERz interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TIMERl can be used as a
reload counter or clock.

CD

·----1

!

@@

t

@@

L

Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to Vss via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET

: Transfer clock generator is reset and mask bit (bit 4

of SCI status register) is cleared.

oo.@ : TlMERl interrupt request
@.@ : TlMERl interrupt request bit cleared

•

The MCV can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19 .

HITACHI

491

HD6305Y1.HD6305Y2------------------------------------------------------requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.

4.5;

J~

OV-------....,....J

RES

..... r-:-V,H -RES

/'

Terminal --------~
-

~::~al

tRHL-

__________

AT Cut
Parallel
Resonance
Co=7pF max.
f=2.0-8.0MHz
Rs=6OQ max.

~

Figure 18 Power On and Reset Timing

Figure 21

Parameters of Crystal

100kn typ 2

Vee ~W'v--I==...,

(a)

RES*2.2/.lF

HD6305Y
MCU

Figure 19

Input Reset Delay Circuit

-INTERNAL OSCILLATOR

The internal oscillator circuit is designed to meet the
[NOTE] Use as short wirings as possible for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wirings to cross others.

f-----6-i EXTAL

JO~~iOMHzCJ 5 XTAL

Figure 22

Typical Crystal Arrangement

HD6305Y
MCU
-LOW POWER DISSIPATION MODE

10-22pF±20%

The HD6305Y has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator

• Wait Mode
When WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition just before entering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT2 or SCI/TIMER2), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to ~WAIT. If an interrupt other than the INT (i.e.,
TIMER/INT2 or SCI/TIMER2) is masked by the timer control

HD6305Y
MCU

External
Ceramic Oscillator
Clock
Input 6 EXTAL
NC 5 XTAL HD6305Y
MCU

External Clock Drive
Figure 20 Internal Oscillator Circuit

492

$

HITACHI

-------------------------------------------------------HD6305Yl,HD6305Y2
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an extemal
interrupt (00 or INT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT2 interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.

Fig. 24 shows a flowchart for the stop function. Fig. 25
shows a timing chart of return to the operation mode from
the sto p mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and~ CPU restarts when the RES goes "I". The duration of RES="O" must exceed 30 ms to assure stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode. all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing SfBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STB)' terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MCU in each
low power dissipation modes. Transitions between each mode
are shown in Fig. 27.

_HITACHI

493

HD6305Y1,HD6305Y2-------------------------------------------------------

Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop

Initialize
CPU, TIMER, SCI.
I/O and All
Other Functions
No

No

1=1

load PC from
Interrupt Vector
Addresses

Fetch
Instruction
Figure 23 Wait Mode Flow Chart

494

•

HITACHI

-------------------------------------------------------HD6305Y1.HD6305Y2

Stop Oscillator
and All Clocks

No

Turn on Oscillator
Wait for Time Delay
to Stabilize

Turn on Oscillator
Wait for Time Delay
to Stabilize

1=1
Load PC from
Interrupt Vector
Addresses

Fetch
Instruction

Figure 24 Stop Mode Flow Chart

$

HITACHI

495

HD6305Y1,HD6305Y2:-------------------------------------------------------

Oscillator

1111111111111111111111111111

II

AIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII111I

r

Interrupt

STOP instruction
executed

stabilized (built-in delay time)

Instructions
restart

(a) Restart by Interrupt

Oscillator 11111111111111111111111111111

I

I

u111III1111111111111111111111111111111 II 1111111111111111111111

~_..:...T..:...im....:e_re.:...:q::.u_ire.:...:d_f_.:..o_rO....:sc..:...i_lIa..:...t...:.io_n_to..:...be....:..:...co::..:.m:..:.:e'--_.~

STOP instruction
executed

! Reset

stabilized (toscl

i start
I

(b) Restart by Reset
Figure 25 Timing Chart of Releasing from Stop Mode

\'-----~Il~_---'I
tosc

Figure 26

Table 4

Start

Mode

WAIT

-

Software

STOP
Standby

496

Hardware

Restart

Timing Chart of Releasing from Standby Mode

Status of Each Part of MCU in Low Power Dissipation Modes
Condition
Timer,
Register
Serial

Escape

RAM

I/O
terminal

Keep

Keep

Keep

STBY, RES, INT, INi2,
each interrupt request of
TIMER, TIMER 2 , SCI

Stop

Keep

Keep

Keep

STBY, RES, INT, INT2

Stop

Reset

Keep

High impedance

Oscillator

CPU

WAIT instruction

Active

Stop

Active

STOP instruction

Stop

Stop

STBY="Low"

Stop

Stop

_HITACHI

STBY="High"

-------------------------------------------------------HD6305Y1,HD6305Y2

Figure 27

Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset

-BIT MANIPULATION
The MCU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM within page 0 or an [/0 port
(except the write-only registers such as the data direction
register). Every bit of memory or I/O within page 0 ($00 $FF) can be tested by the BRSET or BRCLR instruction;
depending on the result of the test, the program can branch to
required destinations. Since bits in the RAM on page 0, or I/O
can be manipulated, the user may use a bit within the RAM on
page 0 as a flag or handle a single [/0 bit as an independent
[/0 terminal. Fig. 28 shows an example of bit manipulation
and the validity of test instructions. [n the example, the program is configured assuming that bit 0 of port A is connected
to a zero cross detector circuit and bit I of thr. same port to
the trigger of a triac.
The program shown can activate the triac within a time of
10j.ts from zero-crossing through the use of only 7 bytes on
the ROM. The on-chip timer provides a required time of
delay and pulse width modulation of power is also possible.
SE l F 1.

Figure 28

BRClR 0, PORT A, SELF 1
BSET 1 , PORT A
BClR 1, PORT A

Exa';'ple of Bit Manipulation

-ADDRESS[NG MODES
Ten different addressing modes are available to the MCU.

elmmediate
See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary during execution of
the program.
This access requires an instruction length of 2 bytes. The

effective address (EA) is PC and the operand is fetched from
the byte that follows the operation code.
- Direct
See Fig. 30. In the direct addressing mode, the address of
the operand is contained in the 2nd byte of the instruction.
The user can gain direct access to memory up to the lower
255th address. 192 byte RAM and I/O registers arc on page 0
of address space so that the direct addressing mode may be
utilized.

_ Extended
See Fig. 31. The extended addressing is used for referencing to all addresses of memory. The EA is the contents of
the 2 bytes that follow the operation code. An extended
addressing instruction requires a length of 3 bytes.
_ Relative
See Fig. 32. The relative addressing mode is used with
branch instructions only. When a branch occurs, the program
counter is loaded with the contents of the byte following the
operation code. EA = (PC) + 2 + Rei., where ReI. indicates a
signed 8-bit data following the operation code. If no branch
occurs, ReI. = O. When a branch occurs, the program jumps
to any byte in the range +129 to -127. A branch instruction
requires a length of 2 bytes.

-Indexed (No Offsetl
See Fig. 33. The indexed addressing mode allows access
up to the lower 255th address of memory. In this mode, an
instruction requires a length of one byte. The EA is the
contents of the index register.

_HITACHI

497

HD6305Yl,HD6305Y2------------------------------------------------------• Indexed (S-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of2 bytes.
• Indexed (16-bit Offset)
See Fig. 35. The contents of the 2 bytes following the
operdtion code are added to content of the index register
to compute the value of EA. In this mode, the complete
memory can be accessed. When used in the indexed addressing mode (i6-bit offset), an instruction must be 3 bytes long.
• Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte' that follows the operation code
indicates an address within page O.

I

Memorv

PROG LOA #$.8

• Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. Individual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code register.
• Implied
See Fig. 38. This mode involves no EA. All information
needed for execution of an instruction is contained in the
operation code. Direct manipulation on the accumulator
and index register is included in the implied addressing mode.
Other instructions such as SWI and RTI are also used in this
mode. All instructions used in the implied addressing mode
should have a length of one byte.

ili
A

:

I

~ :~ r=4~ :=~I:~- - -A-d-de-r.JI- - :-: -: -I!~ ,; : ~x~ ~[:;: :J
I

Figure 29

Example of Immediate Addressing

EA
0048

Memorv

cATFcB32004Bc:~20[::3~~==i===~~~~~----ii~~2~0~:J
~
lndex Reg

I

PROIl LOA CAT 0520

C:38~eE3-_J

052E~

·
···

4B

Aount

052F

....

Figure 30

498

Prog

cc

8
,

Stack Pomt

Example of Direct Addressing

•

HITACHI

-------------------------------------------------------HD6305Y1,HD6305Y2

Memory

~

PROG LOA CAT

0000
A

:

:

40

g:g!I--"~~:~-L

Index Reg

I

040BI-_:E:;5:..._......

Stack POint

CATFCB6406E5~::4~0[:::i_--------------~

Prog Count

040C
CC

Figure 31

,

PROG BEO PROG2 04A7

04AB

Example of Extended Addressing

Memory

~

A
Index Reg

I

Stack POint

27

1B

Figure 32

Example of Relative Addressing

EA
Memorv

OOBB

A

TABlFCCUOOB8~~~4~C~~t_----~~--------i=======~:=~~~4~C~~
49

BB

Stack POint

Prog Count

05F5
CC

I

Figure 33

Example of Indexed (No Offset) Addressing

•

HITACHI

499

HD6305Y1,HD6305Y2~-------------------------------------------------------

I

EA
008C

Memory

"" :g: ;::

~~I r:

FeB :: CF oose;

I

CF-

A

-----C CF
Index Rf'g
_____--1 03

: __

Stat.k POIl't

~

OIbLE::3---

P'WG LOA TAB!... X 075B

Prog Count

0750
CC

~

L.__----'

~ iY

~

:5
u
O

0::

~

-c

<0
U

Code Reg.
CCR

5

co

CPU

- C H•
- ( C H,I
~(C H,I
I-(C H.I
I-(C H,I
I---(C H.I
I---(C H,I
(C HII

Steck

0

Pointer

SP

5

t-

"High" PCH

4

I

.

a..&;

4kB
ROM

96 Byte
RAM

J

.!!

~~

Self-check
ROM

err
~o:

0

HITACHI

I--

r:=:

--

B,
B.

~ B.B,

c

~

•

~.ij,

0

"Low" PCL

I

~!

!D!!

fla:

Program
Counter

B

.!!

O·~

ALU

~ B.B,
B.

c

Program
Counter

508

LCD7
LCD8

'0

System
8 Cont. Reg.

Condition

t-

r - SE G ••

....

1-t-

[

....

E r - - SE G ••
E I--SE G..
I/)
I--SE G..
t--SE G"

0c
'f !!

Control

X

8

~ i--SE G,
~ r--SE G.

LCD6
7
7
4

l]B
CPU

Index
Register

A.

7

RES

~

Accumulator

B

LCD5

NUM

L EXr L
XT

Timer Control

8

XO(T

r--SE G,

9" t--SE G.
0" t--SE G,

u~

~ 's,

a..&;

B,

I - - C.

~ C,C,
C.

I--

--------------------------------------------------------------HD63L05Fl
•

ABSOLUTE MAXIMUM RATINGS

-0.3-+5.5

Vee
V in

V
V

Topr

-0.3 - Vee +0.3
-0.3 - V ee +o.3
-20-+75

V
·C

Tstg

-55-+125

·C

Input Voltage
Output Voltage

Vout

Operating Temparature
Storage Temparature
(NOTE)

Unit

Value

Symbol

Item
Supply Voltage

Permanent LSI damage may occur if maximum ratings are exceeded.
Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.

•

ELECTRICAL CHARACTERISTICS (Vee = 3.0V ±O.BV, Vss = OV, Ta = -20 - +75u C, typ means typic:al value at Vee = 3.0V,
unless otherwise noted.1

•

DC CHARACTERISTICS
Item

Symbol

XTAL, XIN
Input "High"
Level Voltage

Test Condition

min

typ

max

Unit

V ee -O·3

-

Vee

V

0.5V ee +O·9

-

Vee

V

O.aVee
V ee -O.2

-

Vee

V

Vee

V

V ee -2.1

Vee- 1.a

V

0.2Vee

V

Vss

-

Vss

-

0.2Vee
0.2

V

0.5Vee-0.2

-

0.5Vee+0.2

V

Vee = 3.0V, V in = OV

3

15

30

IIA

V in =OV-V ee

-

-

1.0

IIA

-

100

200

IIA

-

40
2

ao
5

IIA

200

600

IIA

-

120

200

IIA

Connect CL - 0.511F to
V eH

RES,INT,SB

V IH

TIMER
NUM (Normal Mode)
Connect C L - 0.511F to
V eH

XTAL,XIN
Input "Low"
Level Voltage

Self Check Input
Voltage

--

Input Pull-Up
Current
Input Leakage
Current

RES, INT, SB
TIMER
NUM (Test Mode)
NUM (Self Check Mode)

VIM

V

RES (00: Mask Op'tion)

-IA1

NUM
TIMER. SB

Crystal'
Oseillation
Current Dissipation
RC'
Oseillation

--

IIINI

During
System
Operation
At Halt

f = 400kHz
No load.
lee1

At Standby
At AID
Operation
DurIng
System
Operation
At Halt

E

Tested after setting
up the internal status
by self check.

R = l00kn
No load.
lee2

At Standby
At AID
Operation

Output "Low"
Level Voltage

Vss

V IL

VOL

Tested after setting
up the internal status
by self check.

IOL = 30llA

p.A

-

60··

100··

p.A

-

2

5

IIA

-

220

600

IIA

-

-

0.3

V

* Depends on the mask-option .
•• 60"A -+ 3O"A and 1 OO"A -+ 60"A when OSCI is stopped by Halt.

$

HITACHI

509

HD63l05F1-------------------------------------------------------------• AC CHARACTERISTICS
Item
Operating Clock Frequency
Cycle Time
Oscillation Frequency *
(Resistor Option)
External Clock Duty
Oscillation Start Time *
(Crystal Option)

Symbol
t evc

I

Duty

EXTAL

Delay Time of Oscillation Delay
Time'
Reset Delay Time

R = 100k!l±1%,
Connect CL = 0.5pF to VCH
Co = 10pF ±20%, Rs = 20k!l max

tOSCR
tOSCl
CD

8

typ
400
10

max
500
40

Unit
kHz
ps

300

400

500

kHz

45

50

55

%

-

-

150

ms

min
100

-

-

-

t OLY

Selected by mask option

tRLH

External Capacitance - 2.2pF
With 32kHz OSC
Without 32kHz OSC
When OSCl is not stopped by Halt
When OSCl is stopped by Halt
-_.
In the case of counter

tRWL

INT Pulse Width'
.--.
TIMER Pulse Width
* Depends on

Co = 10pF ±20%, Rs = 1k!l max

tOSC!

I XOUT

RES Pulse Width'

R = l00k!l ±1%

foscR

Oscillation Start Time *
(Resistor Option)
Oscillation Start Time (32kHz) *
I nternal Capacitance
of Oscillator

Test Condition

fel

tlWL
tTWL

0
200
48
1.5tcyc + 1
tcye+ 1
32
tcye+ 1

2

ms

1

.s
pF

10
10

-

-

1

s

-

ms

-

ps
ps
ps

-

-

ps
ps

-

pF

mask~ption.

• PORT CHARACTERISTICS

Output "High" Level Voltage *
Output "Low" Level Voltage
Input "High" Level Voltage
Input "Low" Level Voltage
Input leakage. Current
.----;;Input Pull-Up Current'

__

Test Condition

min

typ

max

Unit

CMOS Output, IOH = -100pA
Key Load CMOS Output
IOH =-10pA
IOL = 100pA

Vcc -O·3

-

-

V

Vec -O·3

-

-

V

0.3

V
V
V
pA
pA

Symbol

Item
Port A, B, C
Port A, B, C

VOH

Port A, B, C
VOL
PortA, B, C
V IH
Port A, B, C
V IL
Port A, B, C _J!I~_I_
._-----Port A, B, C
-IR2

•

-

V;n=OV-V ee

-

-

Vec = 3.0V, V in = OV

4

20

-;---

* Depends on mask-option.

510

0.8Vee
Vss

HITACHI

Vee
0.2Vcc
1.0
40

--------------------------------------------------------------HD63L05F1
•

=3.0V, Vss =OV, Ta = -20 -

LCD DRIVER OUTPUT CHARACTERISTICS (Vee
Item

Symbol
V OH1

Output "High" Level Voltage

Segment

V,

V OH2
V OH3
V OL1

Output "Low" Level Voltage

Segment

V,

V OL2
V OL3

----

V OH1

Output "High" Level Voltage

---

Common

VOH2
V OH3

V,

-Output "Low" Level Voltage

--- -- ---

"-----

-

Common

V,

---

R LCD
Segment

= 1.00V, V 2 = 2.00V
IOL = l/.1A
= l.00V. V 2 = 2.00V

=-5/.1A

= 1.00V, V 2

= 2.00V

IOL =5/.1A

V OL3

Dividing Resistor

Output "High" Level Voltage'

VOL 1
V OL2

= 1.00V, V 2 = 2.00V
IOH = -l/.1A

IOH

----:-~-

-.

+75°C, unless otherwise noted.)

Test Condition

Tested between V I and V 2
I n the case of Output Port,
IOH = -30/.IA
---In the case of Output Port,
IOL = 30/.lA

V OH

min
1.8
0.8

-

Segment

VOL

max

-

-

Unit
V

-----

V
V
V- '

2.2
1.2

V

-

0.2

V

--

-

..

-

V

2.2

V

-

-

1.2

V

-

0.2

V

45

90

180

kn

Vce-0.3

-

-

V

0.3

V

2.8
1.8
0.8

-

-

--~-

Output "Low" Level VOltage*

typ

2.8

-

V

--

V

* Oepends on mask-option.

Vee

VOH'

O.'.F

Common Output

V2

VOH2
V,
Segment Output

VOH3

Vss

Output Level of SEG and COM

Power Supply Circuit for LCD Display

_HITACHI

511

HD63L05F1-------------------------------------------------------------•

AID CONVERTER CHARACTERISTICS

(Vee = 3.0V. Vss = OV. Ta = _20°C - +7SoC. unless otherwise noted.)
Symbol

Item
Conversion Accuracy

Reference Voltage

I nput Voltage Range

V RL = 0.2V, or .p"k)) at "I"
COUNTER (External clock) at "0"
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .p, (frequency is 1/4 of OSC1) at "I"
.p"k (frequency is 1/12 of OSCI or 32.768 kHz) at "0"

Figure 6 Timer Control Register Configuration

Vee

"" '-------------'1 ~VIL
1,,~,~'----------

V1H

1.

V1H

---Ir-,- -

L....-_ _ _

Built-in Reset

Figure 7 Application of Power and Reset Timing

516

_HITACHI

HD63L05Fl
MCU

Figure 8 Input Reset Delay Circuit

---------------------------------------------------------------HD63L05F1
•

SELF CHECK

The self check capability of the MCV provides an internal
check to determine if the port is functional. Connect the MCV
as shown in Figure 9 and monitor the output of port C bit 3
for an oscillation of approximately O.SHz. This self check
capability also provides the internal state of the MCV to measure the LSI current. After a system reset, the MCV goes into
each current measurement mode by the combination of the
control switches. The LSI current can be measured when the
NUM is returned to Vee after setting of the current mode.
+3V

vee

LED

HD63L05Fl

B,
B.
B,
B,
B,
B,
B,
B.

c, I-------~
C,i---------------J
C,I---------------------~

C.I---------------------------~

1/2V ec""(1)' S.

• The connection of OSCI and OSC2

depend on their mask option.

S,

Selection of Switch

LSI Function
During

Current

S,

S,

---S,

S,

S,

S.

S,

X

X

X

X

X

X

(1)

0

0

X

X

X

o ....X

X

(l)-'j>(~

X

Halt

0

0

0

X

O ....X

X

'"1)-'j>(ij

X

AID

0

0

X

X

X

Standby

0

0

0

X

o ....X
-o ....X

X-+O (j)-+@

X

operation

LSI

S.

X: OFF

o

:ON

---- ------

---ri)-+@ X
---- ---

-+ : Change the state

Figure 9 Self Check Connections

•

HITACHI

517

HD63L05Fl--------------------------------------------------------------•

INTERNAL OSCILLATOR OPTIONS
The MCU incorporates two oscillators: Oscillator I for system clock supply and Oscillator 2 for peripheral modules such
as time base, AID converter, LCD drivers, etc ..

• Oscillator 1 (OSC1;XTAL. EXTAL)
The internal oscillator circuit can be driven by an external
crystal or resistor depending on the stabilitY' A manufacturing
mask option is available to provide better matching between
the external components and the internal oscillator. The oscillator I can stop when power is applied in either Halt or Standby
mode. Figure 10 shows the connection. A resistor selection
graph is given in Figure 11.

• Oscillator 2 (OSC2; XIN. XOUTI
Clocks for time base, LCD drivers, an AID converter, and
a timer can be supplied by the OSC2 (32.768kHz crystal) or by
the OSCI through the frequency divider. In Halt mode, oscillator 2 operates and permits the operation of the peripheral
modules with low power consumption. In Standby mode,
only OSC2 keeps on running. Figure 12 shows the connection
and the relation between oscillator I and oscillator 2 is shown
Figure 13 and Table 1.

(Note)
When OSC2 is not available or OSC1 is the crystal option,
OSC1 is not allowed to stop at Halt mode. The accuracy of
the time base is kept only when OSC2 is 32.768kHz crystal
oscillator.

Vee
10pF

~
EXTAL

Rs= IkSl

CJ
XTAL

HD63LOSFI
MCU

lOOkSl

HD63LOSFI
MCU

RC Oscillator

Crvstal Oscillator

EXTAL

EXTAL
Ext. Clock
Input

XTAL

HD63LOSFI
MCU

Ext. Clock
Input

HD63LOSFI
MCU

XTAL

Ext. Clock

Ext. Clock

Crvstal Option

Resistor Option

Figure 10 Mask Option for Oscillator 1

SOO

400

N

:r

:'!

300

~
0::
II

"

...g

200

I

\

\

Vec=3.0V
Ta = 2S"C

"

~

100

0

100

200

300

.........

r-- r--

400

SOO

600

Resistance (kSlI

Figure 11 Typical Resistor Selection Graph

518

•

HITACHI

700

---------------------------------------------------------------HD63L05Fl

XOUT
Rs = 20kO c:::J

HD63L05Fl
MCU

XIN
lOpF

CPU Clock

vee6
HALT---J
Crystal Oscillator

STANDBY

Time base
Interrupt

XOUT
(Open I

XIN

Vee

HD63L05Fl
MCU

Figure 13 Relation between Oscillator 1 and Oscillator 2
Not Used

Figure 12 Connection of Oscillator 2

Table 1 Oscillator 2 Mask-option and System Operation
When OSC1 is Crystal
Mask Option
State
~~

OSC2
Not Available

CPU Peripheral OSCI

CPU Peripheral OSC1

OSC1

When OSCI is RC
OSC2
OSC2
Not Available
Available

OSC2
Available

CPU Peripheral OSC1

CPU Peripheral

During System
Operation

0

0

0

0

0

0

0

0

0

0

0

0

At Halt
At Standby

0
X

X
X

0
X

0
X

X
X

0
X

0
X

X
X

0
X

X
X

X
X

0
X

(NOTE) 0 ..... run

x

. stop

Table 2 Mask-options of Oscillation Circuits and the Delay Time
Type of OSCI

Use of OSC2
Used

Standby mode

Not used

Standby mode

CR Option
Not used

0

Used

1 - - - - - - - t-.

Not used
Used
Not used

Crystal Option

Used

Delay Time of Restart (second)

Condition

Oscillation
of OSCI
at HALT
Oscillation
ofOSCl
at HALT

Stop
Continue
Stop
Continue

X
0
X
0
0
0
X
0

1/16
X
0
X
0
X
0
X
0

112

0
0
0
0
X
0
X
0

1

0
0
0
0
X
0·X
0

Note) Combinations of the mask-option indicated X is not available.
• STANDBY

When the STANDBY (SB) terminal becomes "High" level,
the MCU goes into standby mode at its instruction fetch cycle.
On standby mode, only 32 kHz oscillator (OSC2) keeps on
running while the others are stopped with holding the current
data except AID converter, timer, and time base. Restarting

•

of the MCU from standby mode is controlled by the Delay Time
which is available by counting the OSC2 oscillation or 1/12
frequency of the OSC 1 in frequency divider after the STANDBY terminal turned to "Low" level. Therefore, the CPU restarts
operation from the previous state after the Delay Time (0 sec,
1/16 sec, 1/2 sec, or 1 sec), and the accuracy of the Delay Time

HITACHI

519

HD63L05F1-------------------------------------------------------------is kept when aSC2 is 32.768 kHz crystal oscillator. When 1/12
frequency of ascI is provided to the frequency divider, the
Delay Time depends on the stability of asc 1 after restarting
from standby mode and is not acculate.
•

HAROWARE RESET

"'''-+1
$7F -+ SP
"0" -+ DOR,
CLR iNT logic
$FF -+ Timer Date Reg.
S7F -+ Timer Prescaler
S7F -+ Timer Control Reg.

DelayTime

Since asc 1 stops in standby mode, it is needed to inhibit
restarting of CPU untill the asc I oscillation is stabilized after
the STANDBY terminal has turned to "Low" level. To take
this stabilizing time of asc I, user can select the Delay Time
out of 0 sec, 1/16 sec, 1/2 sec or I sec by mask-option depending on a combination in the Table 2. STANDBY terminal has to
be kept at "Low" when resetting the MCU and has to be kept
at "Low" during the Delay Time. Starting of the MCU by reset
is also controlled by the Delay Time.
•

$48 -+ AID Control R".
$63 -+ Syttlm Control Reg.
''0'' -+ LCD1, LCD2,lCD3 Reg.

INTERRUPTS

There are six different interrupts to the MCU: external
interrupt via external interrupt terminal (INT), internal timer
interrupt, interrupt by termination of A/D conversion, time
base interrupt, and software interrupt by an instruction (SWI).
When any interrupt occurs, processing is suspended, the present MCU state is pushed onto the stack, the interrupt bit (I) in
the condition code register is set, the address of the interrupt
routine is obtained from the appropriate interrupt vector
address, and the interrupt routine is executed. The interrupt (
service routines normally end with a return from interrupt
'---...._.J
instruction (RTI) which allows the MCU to resume processing
of the program prior to the interrupt. Table 3 provides a listing
of the interrupts, their priority, and the vector address that
contains the starting address of the appropriate interrupt
I
routine.
Figure 14 shows the system operation flow, in which the (
portion surrounded with dot-dash lined contains interruption '---._..J
execution sequence.
(Note)
A clear interrupt bit instruction (CLi) allows to suspend the
processing of the program by an interruption after execution
of the next instruction while a set interrupt bit instruction
(SEI) inhibits any interrupts before execution of the next
instruction. When a mask bit of a control register is cleared by
an instruction, interruption is allowed before execution of the
next instruction.

Standby
Operation
Sequence

I SET

Figure 14 System Operation Flowchart
Table 3 I nterruption Priority
•

520

Interruption
RES
SWI
INT
TIMER

Priority

AID
TIME BASE

5
6

1
2

3
4

Acknowledging an INT in Halt mode

In HALT mode, the CPU is not operating but the peripherals
are operating. When an interruption is acknowledged, the CPU
is activated and executes interruption service matching the
interruption condition by means of vectoring.

Vector Address
$FFE, $FFF
$FFC,$FFD
$FFA, $FFB
$FF8,$FF9
$FF6,$FF7
$FF4, $FF5

•

Acknowledging an INT in Standby mode

In Standby mode, the system is not operating with power
supplied to it. therefore. any interruption request (including
1ffiS) is not acknowledged .

•

HITACHI

--------------------------------------------------------------HD63L05F1
•

INPUT/OUTPUT

There are 20 input/output terminals, which are program
controlled by data direction registers for use as either input or
output. If an I/O port has been programmed as an output and
is read. then the latched logical level data is read even though

the output level changes due to the output load.
If a port is to be used as an input terminal, the user must
specify whether or not it will be equipped with a pull-up PMOS.
Figure 15 shows the port I/O circuit.

Bits of
Data
Direction

Bit of Out·
put Data

Output
State

Input to

0

0

0

x

3·State

Pin

CPU

Register

Figure 15 Port I/O Circuit

•

1
0

Configuration of Port

Figure 16 shows the configuration of I/O ports. As the
output is on/off controlled by a data direction register. an I/O
port may directly be applied as an input terminal. No problem

is involved with the input if both "High" and "Low" levels
are applied. For only one level. the user must specify the use
of a pull-up PMOS for "Open/Low" input application.

Pull·up PMOS available

Pull·up PMOS not available

rVss--+--J

,t--,,
:

I

r

t-I

--.£. - - ' - - ' - - . .

Vss

Vss

Vss

Figure 16 Selection of Input Configuration for I/O Port

•

HITACHI

521

HD63l05F1------------------------------------------------------________
•

Only logical "0" can be written into this bit by software.

AID CONVERTER

The MCV incorporates an 8 bits AID converter based on the
resistor ladder system. Figure 17 shows its block diagram.
The "High" side of reference voltage is applied to V RH ,
while the "Low" side of reference voltage is applied to V RL.
The reference voltage is divided by resistors into voltages matching each bit, which is compared with analog input voltage for
AID conversion. As the analog input voltage is applied to the
MOS gate of the comparator through the analog multiplexer,
this voltage comparison system achieves high input impedance.
The AID Data Register stores the results of an AID conversion or can be set 8 bit data for programmed comparator,
These functions are controlled by software-controlled AID
CTRL Register. The result of AID conversion is not assured
if the conversion is interrupted by STANDBY. Figure 18 shows
the configuration of the AID control register.
• AID Interrupt Request Flag (AID INT)
The AID INT bit is set to logical "1" after completion of
AID conversion and is cleared by program or by system reset.

• AID Interrupt Mask (AID MASKI

If this bit is set, interrupt from the AID converter is not
acknowledged. This bit can be written by program.
• AID Conversion Flag (CNVI
To start auto AID conversion, set this bit to logical "1".

During conversion, data of this bit stays at "1". The bit is
automatically reset to "0" when the auto AID conversion ends.
In auto AID conversion, supply voltage is applied to the comparator only when CNV = "I". The digital data which is obtained by the AID conversion is held in the AID Data Register.
This data is reset when the CNV is set to "I" again.
• AID Operation Mode Select Bit (Auto/Programl
Used to select either auto-run 8 bits AID conversion or
8 bit programmed comparator operation (Auto 8 bits AID

conversion at "0").

Offset Compo Capacitor

Analog Input
r-----,L-~

____ CH,

i~~::l

Reference

Input

(Cr')
L-_ _--Ir----(CH.)

i.Ji

MASK OPTION
( ) indicates that these channels are
shared the terminal with segment.

.~

MPX

Xl
a:

===~~==============

Oata Bus

CH,

001

(CH,)

010

(CH,)

011

(CH.)

100

(CH,)

101

(CH.)

110

(CH,)

111

(CH,)

-Figure 17 8 Bits AID Converter Block Diagram

AID CTRL Register
AID CTRL
Register

7-~~-~-L~~~~~~~--I~-~~~~)--Re~t

Figure 18 AID Control Register Configuration

522

•

HITACHI

Channel

000

-----------------------------------------------------------------HD63L05Fl
• Comparator Output (COMP OUT)

The result of comparator operation under program control
can be read from this bit (Logical "I" means that input voltage
is higher than programmed reference voltage).
• Analog Input Channel Select Bits (MPX)

Used to select 8-channel analog inputs. The multiplexer is
an analog switch based on CMOS. Note that the analog inputs
from CH 2 to CH 8 are mask option while CHI is exclusive.
When 1/3 bias - 1/3 duty or static LCD is used, CH 7 and
CH 8 are not available because these two terminals are used for
LCD power supply as V, and V2 .
•

LCD CIRCUIT

The system configuration of the LCD circuits is shown in
Figure 19. Segment data for display are stored in data registers
LCDI to LCD8. Since the circuits are connected to the output
terminals via pin location block, the user may specify a combination of data to be multiplexed to the segment output terminals.
The bit data of the LCD register is combined with the timing
clock (tP, , tP2 or 4J3) and three combined bit data are gathered to
make a segment output data for 1/3 bias - 1/3 duty driving in
the pin location block. In case of static LCD drive of output
port, timing is always fixed at tP, (always "High") and one bit

data of the LCD register is transferred for an output terminal.
Note that the output terminals from SEC '3 to SEC l7 are
mask option while the others (SEC, to SEC '2) are always available when the Duty bits are "01" or "II".
When the form of output port is selected by Duty bit ("00"),
tPWRITE can be got every time data is written into LCDI
register in the case that EXT bit is "I". As LCDI register has
8 bits latches, it is easy to transfer the internal 8 bits data to
external devices via output port,s, with automatically generated
write clock tPWRITE. The cycle clock pulse can be also available
as an internal data source for the output terminal when output
port is selected as 1/4 ascI.
Assignment of segment terminals to the bits of the LCD
data register, including the case where they are used as output
terminals, is to be specified by the user when he orders masks.
In case of static LCD or output ports, only LCD), LCD2, and
LCD3 are allowed to be used. These registers are initialized at
"0" by system resetting.
•

LIQUID CRYSTAL DRIVER WAVEFORMS

The LCD circuit is based on 1/3 bias - 1/3 duty driving.
Figure 20 shows the common electrode output signal waveforms
(COM" COM 2 , COM 3 ), segment signal waveforms (SEC, to
SEC l7 ) and LCD bias waveforms (between COM and SECMENT)_

SEG 1
SEG,

SEG,
SEG ..

seGs
SEG,

SEG u -SEG I1
Mask Option

seG,
seG"
SeGt
SEGlo

Pin Location

Block

SeGIl
SEGI!
SEGu
SEG ...

SEGu

SEG. 6
SEG.,

System
Cont,
Duty

SEG, -SEG"

00

OUTPUT PORT

01

STATIC LCD

COM.
COM,
COM.

SVS CTRL Reg.

Contents of

10

---

II

1/3 Bias
1/3 Duty LCD

Note)
Both of mask-option and software
control are needed to specify the
contents of SEG I .... SEG 1,.

Figure 19 LCD Circuit System Configuration

•

HITACHI

523

HD63L05Fl-------------------------------------------------------------Vee

2/3Vcc- _ ---

COM"AONl

1J3VCC' -

GND"- --.COMMON 2

COMMON 3

SEGMENT

0.2,31

COM, -SEGMENT

COM, -SEGMENT

COM, -SEGMENT

Vee

Fb::

GND

OlJtput levell

"'" "0" match,n;DatillO
Regllter

Figure 20 LCD Driving Waveforms

• BIT MANIPULATION
The MCU has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines.

(Note)
It is needed to pay attention to the system control register,
the timer control register, and AID control register when
BSET, BCLR, or Read/Modify/Write instructions are applied
to them. If own interrupt request occured onto the interrupt
request bit (bit 7) of the control register between read cycle and
write cycle of these instructions, the bit 7 might be cleared in
the write cycle and not acknowledged by CPU.

The instruction used for that purpose has a length of 2 bytes.
The effective address (EA) is PC. The operand is fetched from
the byte that follows the OP code.
•

Direct

•

Extended

See Figure 22. In direct addressing mode, the address of the
operand is contained in the second byte of the instruction.
The user can gain direct access to the LSB 256 of memory. All
RAM bytes, I/O registers. and 128 bytes of ROM are located
on page 0 in order to utilize this useful addreSSing mode.
See Figure 23. The extended addressing mode is used for
referencing to all addresses of memory. The EA consists of
the contents of the two bytes that follow the OP code. The
instruction used for extended addreSSing has a length of 3
bytes.
•

•

ADDRESSING MODE

There are 10 addressing modes available to the MCU for
programming. Familiarize yourself with these modes by reading
the information and referring to the diagrams that follow.
•

Immediate

See Figure 21. In immediate addressing mode, constants
that will not change during execution of a program are accessed .

524

•

Relative

See Figure 24. Only Branch instructions are used in relative
addressing mode. When a branching takes place, the contents
of the byte next to the OP code are added to the program
counter. EA = (PC) + 2 + ReI., where ReI. indicates signed 8 bits
data at the address following the OP code. When no branching
takes place, ReI. = O. When a branching occurs, the program
jumps to any byte of +129 to -127 of the current instruction.
The length of the Branch instruction is 2 bytes.

HITACHI

---------------------------------------------------------------HD63L05F1
•

Indexed (without Offset)
See Figure 25. In this addressing mode, the lower 256 bytes
of memory are accessed. The length of the instruction used
for this mode is one byte. The EA consists of the contents of
the index register.

•

Indexed (8 Bits Offset)
See Figure 26. The EA consists of the contents of the byte
following the OP code, and the contents of the index register.
In this mode, the lower addresses of memory up to 511 can be
accessed. Two bytes are required for the instruction.

•

Indexed (16 Bits Offsetl
See Figure 27. The EA consists of the contents of the two
bytes following the OP code. and the contents of the index
register. In this mode. the whole of the memory can be accessed. The instruction using this addressing mode has a length of
3 bytes.

• Bit Set/Clear
See Figure 28. This addressing mode can be applied to any
instruction that permits any bit on page 0 to be set or cleared.
The byte following the OP code indicates an address within

page O.
• Bit Test, Branch
See Figure 29. This addressing mode can be applied to instructions that test bits at the first 256 addresses ($00 to $FF)
and are branched by relative qualification. The byte to be tested
is addressed by the contents of the address next to the OP code.
The individual bits of the byte to be tested are designated by
the lower 3 bits of the OP code. The third byte indicates a
relative value that is to be added to the program counter when
a branch condition is satisfied. The instruction has a length
of 3 bytes. The value of the bit that has been tested is written
at the carry bit of the condition code register.
•

Implied
See Figure 30. There is no EA for this mode. All information
needed for execution of instructions is contained in the OP
code. Operations that are carried out directly on the accumulator and index register are included in the implied addressing
mode. In addition, the SWI and RTI instructions are also included in the group of this operation. The instruction using
this addressing has a length of one byte.

lEA
Melorv

i
i
i
i

I
i
i
I

~
I
I

I

l

t

/

Adder

~

Indr~ea.

Stack Point

I

I

I

PROG LOA # $F8 05BE

AS

05BF

F8

A
.J

I

I
Prog Count

OSCO

cc

I

F8

I

I
I
I
I

~
I

I

.
I

Figure 21 Example of Immediate Addressing

•

HITACHI

525

HD63L05F1-------------------------------------------------------------lEA

I

Melorv

,,
i

I

t

i
i
i
i
i

i

,

I

/

Adder

'"

A

o!o

20

CAT FCB 32 oo4B

I

OO4B

20

I

,

,
PROG LOA CAT 0520

B6

052E

4B

I
I
I

Stack Point

I
I

I
Prog Count
052F
CC

~
i

i

I
I

I

Figure 22 Example of Direct Addressing

Memory
i
I

,

§
I

PROG

LOA CAT

0000
A
I

0409~6 l

040A
040B

06
E5

40
Index Reg

J------'

Stack Point

I

Prog Count

I

CATFCB6406E5~----~40~----~-------------~

040C
CC

Figure 23 Example of Extended Addressing

526

•

HITACHI

I

Index Reg.

-----------------------------------------------------------------HD63L05F1

,

lEA

Memory
I

i
i

I

04Cl

/

Adder

i
i

I

I

~

I

f

I

27

04AB

18

OR

oot

I

PAOG BEQ PAOG2 04A7

i

I

~

r-

I
I
I

Index Aeg

Stack Point

I

I

i

J

04Cl
CC

I

z

~

i

,

I

I

I

I

f

I
I

Prog Count

y

I

A

Figure 24 Example of Relative Addressing

lEA
Melory
I

I

OOB8

/

Adder

t

I

I

I

i
i

TABL FCC/LII OOB8

l

I

i
i

I

I

4C

Joo

I

~

A
4C

49

I

Index Reg
B8

I

Stack Point

Prog Count

05F5

CC

Figure 25 Example of Indexed (without Offset) Addressing

_HITACHI

527

HD63L05F1-------------------------------------------------------------lEA
Me!orv
i

I

I

ooac

I

t

I

I

I

TABL FCB 4/< BF 0089

BF

FCB # 86 008A

86

FCB # 08 OO8B

DB

FCB # CF OO8C

CF

/

Adder

I

~

A

Index Reg

I

PROG LOA T ABL.X 075B

E6

075C

89

Stack Pbint

I

I

I

Prog Count

I
I

I

03

i

I
I

J

CF

I

I

0750
CC

i

§
Figure 26 Example of Indexed (8 Bits Offset) Addressing

lEA
Melorv

PROG LOA TABL.X 0692
0693

0694

i
i

i

I

i

I

0780

L

Adder

~

§

'"
I
I

BF

FCB #86 077F

86

FCB # DB 0780

DB

FCB # CF 0781

CF

I

Index Reg
02

I
Prog Count

0695

I

Figure 27 Example of Indexed (16 Bits Offset) Addressing

528

DB

CC

I

TABL FCB # BF 077E

A

I

Stack Point

7E

i

I

~

I

•

HITACHI

I
I
I

-----------------------------------------------------------------HD63L05F1
EA
0001

Memory

PORT B EQU 1 0001

BF
A

0000
Index Reg

PAOG BClA 6. POAT B 058F

1-___1D_ _~

0590

Stack Point

01
Prog Count

0591
I

cc

~
Figure 2B Example of Bit Set/Clear Addressing

lEA
MeJory
I
I
I
I

PORT C EQU 2 0002

I

I

t

I

FO

'/

Adder

Bit
2

.~
oaL

,,

,
I

PROG BRClR 2. PORT C. PROG 2 0574

J

0002

02

0576

10

,

I
I

I

I

I

I
Prog Count

,

H

rl

or

t

~
I

Index Reg

Stack Point

05

0575

A

I

OR

~

~

I

0594
CC

I

I
Adder

l

C

I

/

I

Figure 29 Example of Bit Test and Branch Addressing

~HITACHI

529

HD63L05F1-------------------------------------------------------------EA
Memory
i

I
I
i

~

E5
Index Reg

i

E5

i

i

I

"00 'A''''A~
Prog Ct>unt

osss

cc
i

i

i

i

~
Figure 30 Example of Implied Addressing

•

INSTRUCTION SET
There arc 59 instructions available to the MCU. They can
be divided into five groups: Register/Memory. Read/Modify/
Write. Hranch. Hit Processing. and Control. All of these instructions arc explained below according to the groups. and arc
summarized in individual tables.

•

Register/Memory
Most of these instructions use two operands. One operand
is either the accumulator or index register, while the other is
acquired from memory using one of the addressing modes.
No operand of register is available in the unconditional Jump
(JMP) and Subroutine Jump (JSR) instructions. See Table 4.

•

Read/Modify/Write
These instructions read a memory address or register. modify
or test its contents. and writes a new value into the memory or
register. Negative or Zero instructions (TST) do not provide
writing. and arc exceptions for the Read/Modify/Write. Sec
Table 5.

530

•

• Branch
A Branch instruction will branch from the program sequence
in progress if the specific branch condition is satisfied. See
Table 6.
• Bit Processing
This instruction can be used for any bit of the first 256
bytes of memory. One group is used for setting or clearing,
while the other is used for bit testing and branching. See Table 7.
• Control
The Control instruction controls the operation of the MeU
for which a program is being executed. See Table 8.
• A List of Instructions Arranged in Alphabetical Order
All instructions are listed in Table 9 in the alphabetical
order.
• OP Code Map
Table 10 shows an OP code map of the instructions used
with the MCU .

HITACHI

--------------------------------------------------------------HD63L05F1
Table 4 Register/Memory Instructions
Addressing Mode
--~-

Immediate
Operation

Mnemonic

load A from Memory

LOA

Load X from Memory

LOX

Store A in Memory

STA

Store X in Memory

STX

Op
Code
A6

#

I---:F~:-r--Op
#
#

#

-

~--

Add Memory to A
Add Memory and

Carry to A

Op

#

#

#

Op

Indexed
(8-Bi.Oll,e.1

#

Op

#

Indexed
(16-Bi.Oll,.'1

#

#

Op

#

Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bvtes Cycles Code Bytes Cycles Code Bytes Cycles

-:H--~
- - - --

2

2

--2
2
_. ------ --.~.-

AE

---

Indexed
(NoOII.e.1

Extended

Direct

---

3

C6

3

4

F6

1

2

E6

2

4

06

3

5

3

CE

3

4

FE

1

2

EE

2

4

DE

3

5

3

5

F7

1

3

E7

2

5

07

3

6

3

5

FF

1

3

EF

2

5

OF

3

6

-- -B7
2
4
C7
c--- f------ --- - - 4
CF
- BF 2
r---- )-~ --- --

_.

ADD

AB

2

AOC

A9

2

SUB

AO
2
-_.-.-

SBC

A2

2

-AA

2

2

BB

2

3

CB

3

4

FB

1

2

E8

2

4

DB

3

5

2

B9

2

3

C9

3

4

F9

1

2

E9

2

4

09

3

5

2

3

CO

3

4

FO

1

2

EO

2

4

DO

3

5

3

4

F2

1

2

E2

2

4

02

3

5

---

Subtract Memory
Subtract Memory from
A with Borrow

AND Memory to A

AND
ORA--

OR Memory with A
Exclusive OR Memory
with A

-,-- - - AA-

-i-

2

BO

---

)----

2

B2

2

3

C2

B4

2

3

C4

3

4

F4

1

2

E4

2

4

04

3

5

3

CA

3

4

FA

1

2

EA

2

4

OA

3

5

3

C8

3

4

F8

1

2

E8

2

4

08

3

5

2
-:2

-- --

--- _..

BA r~

EOR

A8

2

2

B8

2

CMP

AI

2

2

Bl

2

3

Cl

3

4

Fl

1

2

El

2

4

01

3

5

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

2

E3

2

4

03

3

5

Bit Test Memory with
A (Logical Comparel

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

2

E5

2

4

05

3

5

Jump Unconditional

JMP

BC

2

2

CC

3

3

FC

1

1

EC

2

3

DC

3

4

JSR

-

-

Jump to Subroutine

-

BO

2

4

CO

3

5

FO

1

3

ED

2

4

DO

3

5

Arithmetic Compare A

with Memory
Arithmetic Compare X
with Memory

Symbols: Op

=

Operation

-

#. Instruction

Table 5 Read/Modify/Write Instructions
Addressing Mode

Implied (AI
Operation

MnemoOic

Implied (X)

-----------

Op
Code

#

#

#

Cycles

Op
Code

#

Bytes

Bytes

Indexed
(B-Bi.Oll,et)

Indexed
(NoOII.et)

Direct

#

#

Cycles

Op
Code

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles

Op
Code

#

#

Bytes

Cycles

Increment

INC

4C

1

1

5C

1

1

3C

2

4

7C

1

--

2

5

DEC

4A

1

1

5A

1

1

3A

2

4

7A

1

-3 -

6C

Decrement

6A

2

5

Clear

CLR

4F

1

1

5F

1

1

3F

2

4

7F

1

3

6F

2

5

Complement

COM

43

1

1

53

1

1

33

2

4

73

1

3

63

2

5

Negate
(2's Complement)

NEG

40

1

1

50

1

1

30

2

4

70

1

3

60

2

5

Rotate Left Thru Carry

ROL

49

1

1

59

1

1

39

2

4

79

1

3

69

2

5

Rotate Right Thru Carry

ROR

46

1

1

56

1

1

36

2

4

76

1

3

66

2

5

Logical Shift Left

LSL

48

1

1

58

1

1

38

2

1

3

68

2

5

logical Shift Right

LSR

44

1

1

54

1

1

34

2

4

74
. _.

1

3

64

2

5

ASR

47

1

1

57

1

1

37

2

4

77

1

3

67

2

5

Arithmetic Shift left

ASL

48

1

1

58

1

1

38

2

4

78

Tes! for Negative or
Zero

TST

40

1

1

50

1

1

3D

2

4

70

--

Arithmetic Shift Right

Svmbols

Op" Operation

# '"

I
I

-- ------- -- ----4

- -----

--

-78

----

3

-

3
1
- ----- _.1

3

--

68
~-

60

2

5

2

5

Instrucllon

•

HITACHI

531

HD63L05F1-------------------------------------------------------------Table 6 Branch Instructions
Relative Addressing Mode

#

#

Bytes

Cycles

Mnemonic

Op
Code

Branch Always

BRA

20

2

Branch Never

BRN

21

2

2 or 3 *

Operation

3

Branch IF Higher

BHI

22

2

2 or 3'

Branch --I F lower or Same

BlS

23

2

2 or 3'

BCC
(BHS)

24

2

2 or 3'

24

2

2 or 3'

Branch I F Carry Clear
___
(Branch IF

H_ijl~r

or Sam_e)

BCS

25

2

2 or 3'

(BlO)

25

2

2 or 3'

__ ~~nch _~l\Iot Equal

BNE

26

2

2 or 3'

___ Bra"-(;~_!~ __Egu~~ ____
Branch I F Half Carry Clear

BEQ

27

2

2 or 3'

BHCC

28

2

2 or 3'

BHCS

29

2

2 or 3'

Branch I F Carry Set

--------

(Branch I Flower)

-------

Branch I F Half Carry Set

BPl

2A

2

2 or 3'

Branch IF Minus

BMI

2B

2

2 or 3'

Branch IF Interrupt Mask Bit is Clear

BMC

2C

2

2 or 3 *

Branch I F I nterrupt Mask Bit is Set

BMS

2D

2

2 or 3'

Branch I F I nterrupt Line is low

Bil

2E

2

2 or 3 *

Branch IF Interrupt Line is High

BIH

2F

2

2 or 3 *

Branch to Subroutine

BSR

AD

2

Branch
-------

IF Plus

4

Symbol: Op = Operation
# = Instruction
* If branched, each Instruction will be a 3-cycle instruction.

Table 7 Bit Processing Instructions
Addressing Mode
Bit Set/Clear
Operations

Mnemonic

Branch IF Bit n is Set

BRSET n (n = 0 ..... 7)

Branch IF Bit n is Clear

BRClR n (n = 0 ..... 7)

----.
_ _

-- --- - - ._------- ------_.

Set Bit n

-----

----------BSET n (n = 0 ..... 7)
------------ 1 - - - -

•••• _ _ _ _ _

-

0_ _-

_____

Clear Bit n

BClR n (n=0 ..... 7)

Symbol: Op = Operation

# = Instruction

Op
Code

#

Bytes

Cycles

--- - - , - - - t-----.--- 1--10+ 2· n

2

4

11 + 2· n

2

4

* If Branched, each instruction will be a 5-cycle instruction.

532

Bit Test and Branch

#

_HITACHI

Op
Code

#

#

Bytes

Cycles

2· n

3

4 or 5

01 + 2· n

3

4 or 5

-

-

-

*
*

--------------------------------------------------------------HD63L05F1
Table 8 Control Instructions
Implied

#

#

Mnemonic

Op
Code

Transfer A to X

TAX

97

1

1

Transfer X to A

TXA

9F

1

1
1

Operation

Bytes Cycles

Set Carry Bit

SEC

99

1

Clear Carry Bit

ClC

98

1

1

Set Interrupt Mask Bit

SEI

9B

1

1

Clear Interrupt Mask Bit

CLI

9A

1

1

Software Interrupt

SWI

83

1

9

Return from Subroutine

RTS

81

1

4

Return from Interrupt

RTI

80

1

7

Reset Stack Pointer

RSP

9C

1

1

No-Operation

NOP

90

1

1

Symbol: Op = Operation

# =- Instruction

Table 9 Instruction Set
Addressing Modes
Mnemonic

ImmeImplied
diate

Direct

Extended

Relative

Condition Code

Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x

Bit
Setl
Clear

Bit
Test &
Branch

H

I

N

Z

C

/\

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

/\

/\

/\

/\

/\

/\

/\
/\

/\

•

/\

/\

/\

/\
/\

ADC

x

x

x

ADD

x

x

x

x

x

x

/\

AND

x

x

x

x

x

x

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• •
• •

ASl

x

x

x

x

ASR

x

x

x

x

x

BCC

x

BClR
BCS
BEQ

x

BHCC
BHCS

x
x

BHI

x

BHS

x

x

BIH

x

Bil

x
x

BIT

x

x

x

BlO

x

BlS

x

BMC

x

BMI

x

BMS

x

BNE

x

BPl

x

BRA

x

x

x

Half Carry (From Bit 3)
Interrupt Mask
Negative (Sign Bit)
Zero

• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
/\

•
•
•
•
•

/\

•
•
•
•
•
• •
• •
• •

•

•
•
•
•
•
•
•

•

(Continued)

Symbols for condition code:
H
I
N
Z

• • •

C
/\

Carry/Borrow
Test and Set if True, Cleared Otherwise

•

Not Affected

~HITACHI

533

HD63L05F1-------------------------------------------------------------Table 9

Instruction Set (Continued)

Addressing Modes
Mnemonic
Implied

Immediate

Direct

Extended

Relative

Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)

Bit

Setl
Clear

x

BRN

x

BRCLR

x

BRSET
x

BSET
BSR
CLC
CLI
CLR

x
x
x
x
x

CMP
COM

x
x

CPX
DEC

x
x

EOR
INC

x

JMP
JSR

x
x

LDA
LDX
LSL
LSR
NEG
NOP

x
x
x
x
x

ORA
ROL
ROR
RSP
RTI
RTS

x
x
x
x
x

SBC
SEC
SEI

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x

x

x
x

x

x

x

x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x

x
x
x

x
x
x
x
x
x
x

x

x

x

x

x

x

x

x

x
x
x

x
x
x

x
x
x

x
x
x

x
x
x

x

x

STX
SWI

x

TAX
TST

x
x

TXA

x

Z

•
•
•
•
•
• •
0 •
• 0
• 1\
• • 1\
• • 1\
• • 1\

•
•
•
•
•
•
•

I

•
•
•
•
•
•
•
•

•
•
•
•
•

•

Symbols for condition code:
Half Carry (From Bit 31
H
I
Interrupt Mask
N
Negative (Sign Bitl
Z
Zero

x

C

1\
•

?

•

Carry IBorrow
Te" and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

HITACHI

C

•

1\
1\

•
•
0
•

1

•

1\

1\

1\
1\

1
1\

•
•
1\ 1\ •
• • • • •
• • • • •
• • 1\ 1\ •
• • 1\ 1\ •
• • 1\ 1\ 1\
• • 0 1\ 1\
• • 1\ 1\ 1\
• • • • •
• • 1\ 1\ •
• •
• •

1\

1\

1\

• • 1\ 1\ 1\
• • 1\ 1\ 1\
• • • • •

x
x

SUB

N

H

?

STA

534

Bit
Test &
Branch

?

?

?

?

• • • • •
• • 1\ 1\ 1\
• • • • 1
• 1 • • •
• • 1\ 1\ •
• • 1\ 1\ •
• • 1\ 1\ 1\
• 1 • • •
• • • • •
• • 1\ 1\ •
• • • • •

--------------------------------------------------------------HD63L05F1
Table 10 OP Code Map
Bit Manipulation

Test &
Branch

0
1

2

Setl
Clear

Rei

OIR

I

I

A

X

I

J

I

Register/Memory

Control

Read/Modilv/Write

Branch

I

,Xl

I

,XO

IMP

IMP

IMM

I

I

OIR

I

EXT

I

,X2

I

B

I

C

1

0

A
2
4
5
6
7
B
9
3
BSETO BRA
NEG
RTI'
RTS'
BRClRO BClRO BRN
1--- - '
BHI
BRSETl
BSETl
- - - - - - - -- ----- BRClRl BClRl BlS
SWI'
- --- c--- COM
BRSET2 BSET2 BCC
lSR
BRClR2 BClR2 BCS_ - _.._ - - - - - - - - - - 1---=-'-'-- ~BRSET3 BSET3 BNE
ROR
----------ASR
TAX
BRClR3 BClR3 BEQ
- 1
BRSET4 BSET4 BHCC
lSl/ASl
ClC
--SEC
BRClR4 BClR4 BHCS
.. _----- I-- ._. --- ._- - ROl
-Cli
BRSET5 BSET5 BPl
DEC
. --------_.BRClR5 Bf.I,.R_5_ r!-~I- _._~~I_. . - -- - - - - - ---------RSP
BMC
BRSE~fL. c!'.!~6_
._.. .. _--INC._-- _.. _- --_.
1-. --::.- - _._._NOP
ElSR'1
BRClR6 BClR6 ~~L __________TS.!.. _____
0
BRSETO

3
4
5
6
7
B
9
A
B
C
0
E BRSET7
F BRClR7

3/4 or 5
lNOTES)

1

-=-.-

--

f--_-r------

B§!.!2.... I!I!-.- ---------:::.----- ._-----BClR7 BIH
ClR
1/1
2/20r3 2/4
2/4
2/5
1/3

-Tm- I

I

I

-

TXA

-

1/'

1/1

2/2

JSRl+l)

-

I
I

I

I,xo

,Xl

1E

SUB
CMP
SBC
CPX
AND
BIT
lOA
STA 1+1)
EOR
AOC
ORA
ADD
JMPl-l)
JSR
1

j

F

-r3/4T 3/5 I

HIGH

0
1

2
3 l
4 o
5 W
6
7
B

IJSRl+l

lOX
STXl+l)
2/3

~

9
A
B
C
0
E
F

2/4

1 1/2

1. "-" is an undefined operation code.
2. The figure in the lowest row of each column gives the number of bytes and the cycles needed for the instruction.
The number of cycles for the asterisked (-) mnemonics is a follows:

RTI
RTS
SWI
BSR

7
4
9
4

3. The parenthesized figure must be added to the cvcle count of the associated instruction.
4. If the instruction is branched. the cycle count is the larger figure .

•

HITACHI

535

HD63L05F1----------------------------------------------------------------DATE OF ORDER
CUSTOMER

HD63L05F
MASK OPTION LIST

DEPT.
ACCEPTED BY
ROM CODE ID.

* Select one type for each item and check •

HD63L05F

LSI TYPE NO.

(1) OSC OPTION

Type
of
OSC1

Use
of
OSC2
Used

STANDBY
mode

Not used

STANDBY
mode

XTAL
Option

Used

CR
Option

Delay Time of
Restart (sec.)
1/16
112
***

Condition

Not Used

Oscillation
of OSC1
at HALT
Oscillation
ofOSC1
at HALT

0
***

Used

* Specify B type of
OSC option.

1

• Crystal option of OSel

is not allowed to stop
at HALT.

Not Used
Used
Not Used
Stop
Continue

***

Stop

***

-**

• If OSC2 is not used.
the Delay Time is not

acculate.

***

n*

*"

***

***

***

Continue

(2) I/O OPTION

Port

Mask Option
A

B

Pin

Mask Option
E

D

C

A2

Pin

F

I

INT

Ao
Al

I

SEG13/CH6
SEG14/CHs
SEGlS/CH4
SEG16/CH3

I---

A3
A4
As

SEG17/CHz
Ols/CHsN.
019/CH7Nl

A6
A7
Bo
Bl
B.

A
B
C

B3
B4
Bs
~~.

B6

CMOS output without input pull-up PMOS
CMOS output with input pull-up PMOS
CMOS output for key scanning

o

NMOS open-drain output

E
F
G
H
K

Input without pull-up PMOS
Input with pull-up PMOS
AID Input
Segment output
Terminals for LCD display

* Specify an 1/0 option for each terminal.

B7
Co
Cl
C.
C3
(3)

LCD DRIVER
L

Segment

Mask Option
I S I P

I

I

Mask options indicated as *** are not available.

536

L
S
P

1/3 bias-1/3 duty LCD
Static LCD
Output port

• Specify a type of LCD driver.

$

HITACHI

Mask option
G

H

K
***
"*
*n
***
*"

---------------------------------------------------------------HD63L05F1
(4) LCD PIN LOCATION
I~ Timin,

Segment Output Terminal

LCD

Output

1R~lte { COM. COMa COM) SEG. seal sea) SEG~ SEQs SEG. SEG, SEG. SEG. sea" seGu SEG11 SEG'I SEa •• SEGII SEG,. SEa., 0,1 ~!!.LCD1~O~--~--~--~--+_--+_--+_--+_--~~~_4--_+--_+---+--~--~--~--~--+_--+_--+_--4_--~
~--+__r--~4_-+--+__r--~4__+--+__r--~4__+--+__+--~4__4----~
~--~4-_+--~4-_+--+_4__+--+_~_+--+_~_+--+_~_4--+__+---~
~_4--~+_4-~_+~--~4_~_+_4--~+_~_+_4--~+__+-f_!

8

LC02~0:__t_--+--+--+--+_--t___+--- ____

_ __ _

---

~-~-~_+-4-~-~-+__+--j-r.~~r_-_r--~-~-+_~r__+-----

-- f--- +-~-_+-+__+-~-+_~I___--I
- - -- 1--- --- -- I---__+--j---+--r__+-~-+_--------j
---c-- -- - - f---

5

~6;.-t---+---t--jr---+-+-+---+

-

---

--+--+--f--__+-+--!--+--I
f--

8-+---+-+--+-+------+----f-----+----I-- ~---- --f-:L--:C:::D:::3to~~::::::~:::::::::~:::::::::~:::::::::t:::::::::t:::::::::t--+--- f----- --------- . +---~f--~-+__+-~-~-+-~-+___I
r
----------- -f-----

--- f----- ---+---+--I---l---_~
~---+-+--I____+-+_-I___--

---- -

----f----

8

LCD4~O~-t_-t-_j-_t-_r-t_---t__j-_+-_t-+-+_-f-----+--+-~-+--+_--~------,_
- - - ---f--8-+---t-+-I-+--+-~-1----t--+__-+_----

---- --- - ----

----+-+_----+-4---1--+---1.-_+-+---1

--- 1----

---- -- -+------1--+--+--+----+--- '----

LCD5r~;t--+--!--j--t-~-+--+--~--+--t-+-+--f-----+--+--+
~r--+---

____________ __

--- -- +-+_-+--I____+-_+--+-+--+--r__+-~-+-+_-I____+-__+----------j

4

~6+--+--4--+--+--+-4----+--+--~~--+--+~----+--+--~-+---+--+----~+--~
~o

~

~---+~----~+-+-4--+---+-4----~+-+--~-+--Ir~----~+--+--~-+-1

r.q,LWC:R'"'T:::e:t-o=-"--- t - 1/40SC1

0

• Specify the multiplex timing and segment terminal for each bit of LC01 to LCOS.
• When static or output port is selected, the Multiplex timing is fixed at COM 1.
* If there are unspecified bits, Hitachi specifies them as dummy.

• q,WRITE is generated when data is written into the LC01.
• 1/4 OSC1 is a quarter of the OSC1 clock speed. When the MCU is in standby mode, it becomes "Low" .

•

HITACHI

537

/HD63L05EO,------Evaluation Chip for HD63L05F 1
HD63LOSE is a CMOS evaluation chip for the HD63LOSF.
Connecting an external EPROM (HN462732) to the chip, it
can be operated as a single chip microcomputer HD63LOSF.
Interface signals are 12 bit Address Bus (Eo - E7 , Fo - F 3 ), 8
bit Data Bus (Do - D7 ) and Chip Enable (CE).
It is easy to debug the HD63LOSF user program with this
evaluation chip.
•
•
•
•
•
•
•
•
•
•
•

•

PIN ARRANGEMENT

FEATURES
3V Power Supply
96 Bytes RAM
EPROM (HN462732) Interface
LCD Driver
8-bit Programmable Timer with 7-bit Prescaler
8-bit A/D Converter
20 parallel I/O Port
Same Instruction Set as HD63L05F
NMOS Open-drain Output
100 Pin Flat Package (FP-l00)

• TERMINALS
Ao - A7
I/O Port
Bo - B7
I/O Port
Co - C3
I/O Port
Do - 0 7
Data Bus (Input)
Eo - E7
Lower 8 bit Address Bus (Output)
Fo - F3
Upper 4 bit Address Bus (Output)
UlM
Test Terminal
CEIWR
Chip Enable, Read/Write
['fR
Instruction Fetch Signal
ADCLK
E Clock
RA[T
External clock control signal
~
Connected to Vee

HD63L05EO

NC

30

51 Co

(Top View)

538

~HITACHI

------------------------------------------------------------HD63L05EO
• BLOCK DIAGRAM

COM,

",,,J

DRIVER
OUTPUT

COM,
COM,

DATA
lATCH
LC01
8

LIR _ _

ADCLK~
CE.
WlI

LC02

SEG,
SEG,
SEG,
SEG.
SEG,

MSET

SEG.

I

SEGT

U/M

TIMER

LC05

7

LCDS

7

INT

SEG.
SEG,
SEG ••
(SEG,,)
(SEG,,)
(SEG,,)

8

ACCUMULATOR
A

INDEX REGISTER
IX

8

CPU

A.
A,
A,
A,
A4
A,
A.
AT

7

LC08

4

CONTROL

(SEG •• )
(SEG .. )
(SEG,,)
(SEG,,)

8
SYS CTRL

CONDITION CODE
REG. CCR
5
STACK POINTER
5
SP
PR GRAM
COUNTER
HIGH PCH
4
PROGRAM
COUNTER
lOW PCl

LC07

I-

'"

c

a:

C

I-

.(

...

~
l-

c z

ALU

w

a:
w

>
z

0

u

e

< u0 <-

CH,
(CH,)
(CH,)
(CH.)
(CH.)
(CH.)
(CHT)
(CH.)

8.

III

..

I-

a:

0

8.
B,
B,
B.
B.
B.
BT

•

HITACHI

539

HD68P01 V07 ,HD68P01 V07-1HD68P01 MO ,HD68P01 MO-1

MCU (Microcomputer Unit)
- The specifications for HD68P01V07-1 and
HD68P01MO-l are preliminary.The HD68POI is an 8·bit single chip microcomputer unit
(MCU) which significantly enhances the capabilities of the
HMCS6800 family of parts. It can be used in production sys·
tems to allow for easy firmware changes with minimum delay or
it can be.used to emulate the H06801 for software development.
If includes 128 bytes of RAM. Serial Communications Interface
(SCI). parallel 1/0 and a three function Programmable Timer on
chip. and 2048 bytes. 4096 bytes or 8192 bytes of EPROM on
package. It includes an upgrade H06800 microprocessing unit
(MPU) while retaining upward source and object code com·
patibility. Execution times of key instructions have been im·
proved and several new instructions have been added including
an unsigned 8 by 8 multiply with l6·bil result. The H068POI
can function as a monolithic microcomputer or can be ex·
panded to a 65k byte address space. It is TTL compatible and
requires one +5 volt power supply. A summary of HD68POI
features includes:

HD68P01V07, HD68P01V07·1,HD68P01MO, HD6BP01MO·l

•

PIN ARRANGEMENT (Top Viewl
HD68P01V07, HD68P01V07·1

• FEATURES
• Expanded HMCS6800 Instruction Set
• 8 x 8 Multiply Instruction
• Serial Communications Interface (SC I)
• Upward Source and Object Code Compatible with HD6800
• 16·bit Three·function Programmable Timer
• Applicable to All Type of EPROM
4096 bytes; HN482732A
8192 bytes; HN482764
• 128 Bytes of RAM (64 bytes Retainable on Powerdown)
• 29 Parallel 1/0 and Two Handshake Control Line
• Internal Clock Generator with Divide·by·Four Output
• Full TTL Compatibility
• Full Interrupt Capability
• Single-Chip or Expandable to 65k Bytes Address Space
• Bus compatible with HMCS6800 Family
•

TYPE OF PRqOUCTS
Type No.

Bus Timing

HD6BP01V07
HD6BP01V07·1

1.25MHz

HN4B2732A·30

HD6BPOIMO

1 MHz
1.25MHz

HN4B2764-3
HN4B2764·3

HD68P01MO·l

HD68P01MO, HD6BP01MO·l

EPROM Type No.

1 MHz

HN4B2732A·30

Note) EPROM is not attached to the MCU.

540

•

HITACHI

- - - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-1
•

BLOCK DIAGRAM

I+T-~-++ P:w

I+t.------''--i-+ P21
I+t-t-.-~+ P"
1+t-t-+-1r--' P21
I+t-t--Hh-. P",

- i
I

II-

I
Ii-

:=

Address

:_

(HN482732AI
lHN482764 )

I-

A'JI_
Al01_
A!ll_

A121_

CE

0"
0,
02
0"
0,
0,
I

Output

I-

EPROM

1 -

. . . ._ _...

Data
Input
I

0, I
0, I
I

L __________

~

~HITACHI

541

HD68P01V07, HD68POlV07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - •

ABSOLUTE MAXIMUM RATINGS

..

Symbol

Value
-0.3-+7.0

V

I nput Voltage

Vee
V in

-0.3-+7.0

Operating Temperature

Topr

V
·C

Storage Temperature

Tstg

Item
Supply Voltage

Unit

-+70

0

·C

-55 -+150

• With respect to vss ISYSTEM GNO)
[NOTE]

Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating

conditions. If these conditions are exceeded. it could affect reliability of LSI.

•

ELECTRIC~L

•

DC CHARACTERISTICS (Vee =5.0V±5%, Vss .. OV, Ta = 0 - +70·C;unless otherwise noted.)

CHARACTERISTICS

Item
Input "High" Voltage

Symbol
RES

All Inputs·

Input Load Current

P40 - P47
SCI
EXTAL

I nput Leakage Current
Three State (Offset)
Leakage Current
Output "High"·Voltage

V 1H

Other Inputs·

Input "Low" Voltage

VIL

---i

----i

II;nl
PIO -P I7 ,P 30 ·-P37~
IITsd
P20 - P24
P30 - P37
I
P40 - p.7, E, SCI, SC 2 ~ V OH
Other Outputs
'

t-.__ .

All Outputs
Darlington Drive Current PIG - PI7
Power DiSSipation

Vee Standby
Standby Current

II;nl

NMI, IRQ~, RES

Output "Low" Voltage

Input Capacitance

Test Condition

P30 - PJ7 , P40 - p.7, SCI
Other Inputs
---_.
Powerdown

VOL
-l oH

max

-

Vee

2.0

-

-0.3

-

-

-

.-

V;n = 0- Vee

-

V;n = 0 - 5.25V

-

-

Vee
0.8

V
V

0.5
0.8
1.2

mA

2.5

IJ.A
IJ.A

-

I LOAD = -2051J.A
I LOAD = -1451J.A
I LOAD = -1001J.A

2.4
2.4

-

-

2.4

-

-

I LOAD = 1.6 mA

-

-

0.5

V

You. - 1.5V

1.0

10.0

mA

-

1200

mW

-

-

12.5
12.5

pF

V;n = 0.5 - 2.4V

V,n = OV, Ta = 25·C,
f = 1.0 MHz

-

f---

.-

-

----~-

-

V SBB

4.0

-

5.25

Operating

VSB

4.75

-

5.25

Powerdown

ISBB

-

-

8.0

$

Unit

10
100

V SBB = 4.0V

-Except Mode Programming Levels: See Figure 8.

542

typ

~.n =0- 2.~V

Po
Cin

min
4.0

HITACHI

V

V
mA

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01M0-1
• AC CHARACTERISTICS
BUS TIMING (Vee = 5.0V±5%, Vss

=OV, Ta = 0 -

Address Strobe Rise Time
Address Strobe Fall Time
Address Strobe Delay Time
Enable Rise Time
Enable Fall Time
Enable Pulse Width "H igh" Time
Enable Pulse Width "Low" Time
Address Strobe to Enable Delay Time
Address Delay Time
Address Delay Time for Latch (f = 1.0MHz)
Data Set·up Write Time
Data Set·up Read Time

PWASH
tASr

5
5
60
5
5
450
450
60

tASf
tASD
t Er
tEf
PWEH
PWEL
tASED
tAD
tADL
tDSW

-

Fig. 1
Fig.2

225
SO

toSR
t HR
tHW

II Read
Write

Address Set·up Time for Latch
Address Hold Tif!le
Non·Multiplexed Bus

I

Multiplexed Bus
Oscillator stabili~ation Time
Processor Control Set·up Time

PERIPHERAL PORT TIMING (Vee

-

-

-

50
50

-

-

-

5
5
30
5
5
340
350
30

260
270

-

-

115

-

10
20
50
20

70

-

-

-

(610)
(600)

-

100
200

-

-

100
200

-

20

-

-

-

-

50
50

-

-

-

50
50

-

-

-

-

-

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

-

ns

260
260

-

ns
ns

-

ns
ns

(420)
(420)

-

-

+70·C, unless otherwise noted.)

Test Condition

min

typ

max

Unit

t pD5U
t pDH

Fig. 3
Fig.3

200
200

-

-

ns
ns

tOSDl

Fig. 5

-

-

350

ns

tOSD2

Fig. 5

-

-

350

ns

Port 1, 2*,3,4

t pwD

Fig.4

-

-

400

ns

*
Port 2**,4

t CMOS

Fig.4

-

-

2.0

Ils

tPWIS

Fig. 6

200

-

Fig. 6

50

Fig. 6

20

-

-

ns

tlH
tiS

Input Data Hold Time

port 3

Input Data Set·up Time

Port 3

ns
ms
ns

Symbol
Port 1,2,3,4
Port 1, 2,3,4

Delay Time, Enable Positive Transition
to OS3 Negative Transition
Delay Time, Enable Positive Transition
to OS3 Positive Transition
Delay Time, Enable Negative
Transition to Peripheral Data
Valid
Delay Time, Enable Negative
Transition to Peripheral
CMOS Data Valid
Input Strobe Pulse Width

50
50

-

20

Fig. 11
Fig. 12

-

-

-

=5.0V ±5%, Vss =OV, Ta = 0 -

Item
Peripheral Data Setup Time
Peripheral Data Hold Time

10
20
60
20

tASL
tAHL
tAH
(tACCN)
(tACCM)
tRC
tpcs

Address Hold Time for Latch
Peripheral Read
Access Time

min
1

toyc

Cycle Time
Address Strobe Pulse width "High"

I

HD6SP01V07/MO HD6SP01V07·1/MO·l
Unit
typ
typ
max
min
max
10
10
O.S
IlS
150
ns
200
-

Test Condition

Symbol

Item

Data Hold Time

+70·C, unless otherwise noted.)

ns
ns

**10kO pull up register required for Port 2

_HITACHI

543

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - 1 - - - - - - - - - - - - - - - TIMER , SCI TIMING (Vee

=5 OV -+5%, Vss =OV

Ta

Item

=0 -

+70·C unless otherwise noted.)

Symbol

Timer Input Pulse Width
Delay Time, Enable Positive Transition to
Timer Out
SCI Input Clock Cycle
SCI Input Clock Pulse Width

min

typ

max

2tcyc+2OO

-

-

-

-

600

1

-

-

tcyc

0.6

tScYc

min

typ

max

Unit

-

-

1.7

4.0

-

-

V
V

-

-

Test Condition

tpwT
Fig. 7

tTOD

tscvc

0.4

tPWSCK

Unit
ns
ns

MODE PROGRAMMING (Vee = 5.0V ±5%, Vss = OV, Ta = 0 - +70·C, unless otherwise noted.)
Symbol

Item
Mode Programming Input "Low" Voltage
Mode Programming Input "High" Voltage
RES "Low" Pulse Width
Mode Programming Set·up Time

I

Mode Programming
Hold Time

Test Condition

VMPL
VMPH
PW RSTL

Fig.8

3.0
2.0

tMPs

RES Rise Time.:?: l~s
Rise Time < l~s

0
100

tMPH

I m

,

.

teye

22V

Address Strobe
(AS)

o 6V
-0

/

- -

-PW ASH ----

-

-tASr

'ASD

2.4 V'
Enable
(E)

~r
-'ASt

I--

ASEC

-

...,

\.

PW EH

j'

PWEL

\

O,SV

-

-tAD~

R/Vii ,Ar-Au
(SC~

"

(Port 3)

/

Address Valid

J

Do-D,.Ao-A.,

~

::
22V
Address
Valid
o 6V

tosw-

,

1\
1/

22V

0.-0,. A.-A"

J
~

Address
Valid
06V

Data Valid

1\

j

If

"

hACCM)

2.0V

Data Valid
O.BV

Figure 1 Expanded Multiplexed Bus Timing

544

•

-

HITACHI

I---tHW

~
I{

06V

I-tOSR ----22V

-tAH

I

I--'AHL

--'ADL-

MCU Read

-tEf

o 6V

'ASL- .

MCUWrot.

-

-te,

22V

j

(Port4)

(Port 3)

-

-

--tHR

1\

If

tcyc
tcyc
ns

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-1

.
2.4V
IE)

\

-

-tAO-

RNV

iOS

(SC,)
(SCIl

PWEH

~('

PWEL

Ao-A~Port4 )

-'r.

f-

Enable

o 5V

.

tcyc

---,

'1\
-

-tE,

I--tEf

1-

22VJ

--tAH

Address Valid

o 6V'
-'osw-

1-

22V

MCUWrlte

~

06V'

.

~tDSR---'

I'ACCN)

2.0V

----------------------------------------------~

-'1\

Data Valid

0 0 -0.,
(PorI3)

MCU Read
0,-0,
(PorI 3)

~

-

+-tHR

Oala Valid

O.BV

Figure 2 Expanded Non·Multiplexed Bus Timing

r-MCUWrite
r-MCURead
E
E

O.5V
'CMOS-}

p'G - PI.,
P20 - PI ..
P"O -P,,"

-tpWD--+

"
All Data

Inputs

POrt Outputs ________________..J

- - - - 0.7 Vee

2.2V 0
O.6V a'a Valid

P,o - P"

Inputs·

INOTE)
• Port 3 Non·Latched Operation ILATCH ENABLE

Figure 3

~

0)

Data Set-up and Hold Times

1. 10 kn Pull up resistor required for Port 2 to reach 0.7 VCC
2. Not appliceble to PH
3. Port 4 cannot be pulled above Vee

Figure 4 Port Data Delay Timing
(MCUWrite)

(MCU Read)

E

Address

Bu.
053-----;..:.

• Access matches Output Strobe Select (OSS
OSS ~ 1, • write)

Figure 5

=0, a read;

Port 3 Output Strobe Timing
(Single Chip Mode)

Figure 6 Port 3 Latch Timing
(Single Chip Mode)

$

HITACHI

545

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M 0 - 1 - - - - - - - - - - - - - - - - -

Timer

Counter _ _ _ _- J '----1:---:---' '__ __

P"

Output

Figure 7 Timer Output Timing

Figure B Mode Programming Timing

Vee

'1 "'"

1

Te .. POint 0 . . . - - - - -

Test Po lOt o-_~I+--+
152074

®

or Equlv

c

C '" 90pF for p]o""'p". p.o-p.,. E. SC" SCI
'" 30 pF for Pin -p". PH'-PU
R"" 12 kn for P30 ..... P 31. P.O"'P41' E,SC,. SCI
- 24 kn for P 'O -PI~' PIn -PH

Ib) TTL Load

la) CMOS Load

Figure 9 Bus Timing Test Loads

•

INTRODUCTION

The HD68POI is an 8-bit monolithic microcomputer which
can be configured to function in a wide variety of applications. The facility which provides this extraordinary flexibility
is its ability to be hardware programmed into eight different
operating modes. The operating mode controls the configura.
tion of 18 of the MCU's 40 pins, available on-chip resources,
memory map, location (internal or external) of interrupt
vectors, and type of external bus. The configuration of the reo
maining 22 pins is not dependent on the operating mode.
Twenty-nine pins are organized as three 8-bit ports and one
S-bit port. Each port consists of at least a Data Register and a
write-only Data Direction Register. The Data Direction Register
is used to define whether corresponding bits in the Data Register are configured as an input (clear) or output (set).
The term "port", by itself, refers to all of its associated hard·
ware. When the port is used as a "data port" or "I/O port", it is
controlled by its Data Direction Register and the programmer
has direct access to its pins using the port's Data Register. Port
pins are labled as Pij where i identifies one of four ports and j
indicates the particular bit.
The Microprocessor Unit (MPU) is an enhanced HD6800
MPU with additional capabilities and greater throughput. It is
upward source and object code compatible with the HD6800.
The programming model is depicted in Figure 10 where Ac·
cumulator D is a concatenation of Accumulators A and B. A
list of new operations added to the HMCS6800 instruction set
are shown in Table 8.
The basic difference between the HD6801 and the HD68POI
is that the HD6801 has an on-chip ROM while the HD68POI has

546

•

an on the package EPROM. The HD68POI is pin and code com·
patible with the HD6801 and can be used to emulate the
HD680 I, allowing easy software development using the on·
package EPROM. Software developed using the HD68POI can
then be masked into the HD6801 ROM.

fI75- - - _A.. - -_OU
o :- - _!l_ - - ~oo
~

QI

8-Bit Accumulators
AandB
Or 16·Bit Double
Accumulator 0

115

X

01

Index Register (X)

115

SP

01

Stack Pointer (SP)

115

PC

01

Program Counter (PC)

HITACHI

Condition Code
Register ICCR)
Carry/Borrow from MSB
Overflow

Zero
Negative
Interrupt
Half Carry (From Bit 3)

Figure 10

HD6BP01 Programming Model

- - - - - - - - - - - - - - - - HD68P01 V07, HD68P01 V07-1, HD68P01MO, HD68P01M0-1
•

INTERRUPTS

The MCV supports two types of interrupt requests: maskable
and non-maskable. A Non-Maskable Interrupt (NMI) is always
recognized and acted upon at the completion of the current
instruction. Maskable interrupts are controlled by the Condition
Code Register's I-bit and by individual enable bits. The I·bit
controls all maskable interrupts. Of the maskable interrupts,
there are two types: IRQ, and IRQ2 . The Programmable Timer
and Serial Communications Interface use an internal IRQ2 inter·
rupt line, as shown in BLOCK DIAGRAM. External devices
(and IS3) use IRQ, . An IRQ, interrupt is serviced before IRQ2
if both are pending.
All IRQ2 interrupts use hardware prioritized vectors. The
single SCI interrupt and three timer interrupts are serviced in a
prioritized order where each is vectored to a separate location.
All MCV interrupt vector locations are shown in Table I.
The Interrupt flowchart is depicted in Figure 13 and is com·
mon to every MCV interrupt excluding Reset. The Program
Counter, Index Register, A Accumulator, B Accumulator, and
Condition Code Register are pushed to the stack. The I-bit is

I

set to inhibit maskable interrupts and a vector is fetched corresponding to the current highest priority interrupt. The vector
is transferred to the Program Counter and instruction execution
is resumed. Interrupt and RES timing is illustrated in Figure II
and 12.
Table 1

Interrupt Vector Locations

MSB

LSB

FFFE

FFFF

RES

FFFC

FFFD

NMI

FFFA

FFFB

Software Interrupt (SWI)

FFF8

FFF9

IRQ, (or IS3)

FFF6

FFF7

ICF (Input Capture)

FFF4

FFF5

OCF (Output Compare)

FFF2

FFF3

TOF (Timer Overflow)

FFFO

FFF1

SCI (RORF + ORFE + TORE)

-----

Interrupt

Cycle

Last In,lruChon ---+

#1

Internal

i'A'O.

*----'"'

~orlRal

\~~

---+/

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

t+-- Ipes

Internal ""r---v--v--"'""r---'""'r---'V"----.r---"'""r----v---"V'---'V'--"".r----'V'--"'""r---v--'V'-

".-C-O'-.-C,"p"'C-.-'.-CJ,,''-XO-'-x-,' -X-.'-X-,J."-A-CC-A...J·'--A-CC-.-"-CC-R-J~I-".-,'-y.-n'J'.-v-"-,o-,"-v-,-"o-,"""'-"-"-'n~""o-'-

Oa18 Bus -,,--.I\..---''''O-O-C-Od-'''-O-O-Cod--"

f

Data

MSB

LSB

In1errupt Roullne

, ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

InUlfnal RIW'

* IRQ2; Internal Interrupt

Figure 11

E

~\\\\\\\\\\\\\\\\ M\\\\\\\\\\\\\\\

-S2SV
Vee "7I"'475V
'

,

LJLf"1 ~ fl-fl-flJ

l

,.

REs

Interrupt Sequence

II

I

'(l

S ~ 4,OV

1I

I

~ -'pcs

- L -'pc;

'RC

'"

l-'o"',a"'v________

A';;';:;:~' §\\\\\\\\\\\\\\\\\\\~ ~\\\\\\\\~~t:x::::x::::x::
~~
FFFEFFFE
Inl"n" R/W

\\\~\\\\\\\\\\\\\~ ~\\\\\\\\\\\\\\\S\\\\\\\\\\Y

6;,':';~: :\\\\\\\\\\\\\\\\\\\\\'{

~~

,\\\\$\\\\\\\\\\\\\\\\\\SWC:: r--~-~-,,~"'""'r_"'""'r__v_~'
pCB-pelS PCO .... PC1

First

Instruction

~N01V.hd

Figure 12

Reset Timing

~HITACHI

547

en

....

00

::I:

(9

0

Ol
00

"'tI

~

<

0

,"-I

::I:

0

Ol
00

"'tI

~

<

0

':"
....
::I:

0

Ol
00

"'tI

0
....
s:
,0

•
J:

~
(')
3:

::I:

0

y

ZJ

Ol
00

"'tI

~

s:

....9

WAI

Condition Code Register
i .1 ..•. Iu ._ 1 .. 1.
Vector

NMI
SWI
IRQ
ICF
OCF
TOF
SCI

Figure 13

Interrupt Flowchart

~

PC

FFFC:FFFD
FFFA:FFFB
FFF8:FFF9
FFF6:FFF7
FFF4:FFF5
FFF2:FFF3
FFFO:FFFl

Non-Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RDRF + ORFE)

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-1
• FUNCTIONAL PIN DESCRIPTIONS
• Vee and Vss
Vee and VSS provide power to a large portion of the MCU.
The power supply should provide +5 volts (±5%) to Vce, and
Vss should be tied to ground. Total power dissipation (including Vee Standby), will not exceed PD milliwatts.
• Vee Standby
Vee Standby provides power to the standby portion ($80
through $BF) of the RAM and the STBY PWR and RAME bits
of the RAM Control Register. Voltage requirements depend on
whether the MCU is in a powerup or powerdown state. In the
powerup state, the power supply should provide +5 volts (±5%)
and must reach V SB volts before RES reaches 4.0 volts. During
powerdown, Vee Standby must remain above VSBB (min) to
sustain the standby RAM and STBY PWR bit. While in power·
down operation, the standby current will not exceed ISBB.
It is typical to power both Vec and Vee Standby from the
same source during normal operation. A diode must be used
between them to prevent supplying power to Vee during
powerdown operation. Vec Standby should be tied to either
ground or Vee in Mode 3.

Figure 14

Battery Backup for Vee Standby

patible clock to the MCU's internal clock generator. Divide-byfour circuitry is included which allows use of the inexpensive
3.58 MHz Color Burst TV crystals. A 22 pF capacitor is required from each crystal pin to ground to ensure reliable startup and
operation. Alternatively, EXTAL may be driven with an external TTL compatible clock with a duty cycle of 50% (±IO%)
with XT AL connected to ground.
The internal oscillator is designed to interface with an AT-cut
quartz crystal resonator or a ceramic resonator operated in parallel resonance mode in the frequency range specified for 3.2 4 MHz. The crystal should be mounted as close as possible to
the input pins to minimize output distortion and startup stabilization time. The MCU is compatible with most commercially
available crystals and ceramic resonators and nominal crystal
pa~ameters are shown in Figure 15.
• RES
This input is used to reset the MCU's internal state and provide an orderly startup procedure. During powerup, RES must
be held below 0.8 volts: (I) at least tRC after Vee reaches 4.75
volts in order to provide sufficient time for the clock generator
to stabilize, and (2) until Vcc Standby reaches 4.75 volts. RES
must be held low at least three E-cycles if asserted during powerup operation.
When a "High" level is detected, the MCU does the following:
I) All the higher order address lines will be forced "High"_
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
control bits PC2, PCI and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set; must be cleared before the
CPU can recognize maskable interrupts.

• RAM Control Register ($14)
The RAM Control Register includes two bits which can be
used to control RAM accesses and determine the adequacy of
the standby power source during powerdown operation. It is
intended that RAME be cleared and STBY PWR be set as part
of a powerdown procedure.

• E (Enable)
This is an output clock used primarily for bus synchronization. It is TTL compatible and is the slightly skewed divide-byfour result of the MCU input frequency. It will drive one
Schottky TTL load and 90 pF, and all data given in cycles is referenced to this clock unless otherwise noted.

RAM Control Register

• NM.- (Non-Maskable Interrupt)
An NMI negative edge request an CPU interrupt sequence,
but the current instruction will be completed before it responds
to the request. The CPU will then begin an interrupt sequence.
Finally, a vector is fetched from $FFFC and $FFFD. transferred to the Program Counter and instruction execution resumes. NMI typically requires a 3.3 kn (nominal) resistor to
Vee. There is no internal NMI pullup resistor. NMI must be
held low for at least one E-cycle to be recognized under all
conditions.

6

Bit 0-5 Not Used
Bit 6 RAME

Bit 7 STBY PWR

5

4

3

2

x

x

x

x

o
x

x

RAM Enable. This Read/Write bit can be
used to remove the entire RAM from the
internal memory map. RAME is set (enabled) during Reset provided standby
~er is available on the positive edge of
RES. If RAME is clear, any access to a
RAM address is external. If RAME is set
and not in Mode 3_ the RAM is included
in the internal map.
Standby Power. This bit is a Read/Write
status bit which is cleared whenever Vcc
Standby decreases below VSBB (min). It
can be set ..<>!I!Y by software and is not
affected by RES.

• XTAL and EXTAL
These two input pins interface either a crystal or TTL com-

•

• IRQ1 (Maskable Interrupt Request 1)
IRQ, is a level-sensitive input which can be used to request
an interrupt sequence. The CPU will complete the current instruction before it responds to the request. If the interrupt mask
bit (I-bit) in the Condition Code Register is clear, the CPU will
begin an interrupt sequence. Finally, a vector is fetched from
$FFF8 and $FFF9, transferred to the Program Counter, and
instruction execution is resumed.
IRQ, typically reqUires an external 3.3 kn (nominal) resistor to Vee for wire-OR application. IRQ, has no internal
pullup resistor.

HITACHI

549

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M 0 - 1 - - - - - - - - - - - - - - - • SCI and SC2 (Strobe Control 1 and 21
The function of SCI and SC. depends on the operating
mode. SCI is configured as an output in all modes except
single chip mode, whereas SC. is always an output. SC, and
SC. can drive one Schottky load and 90 pF.
SCI and SC2 in Single Chip Mode
In Single Chip Modes, SCI and SC. are configured as an in·
put and output, respectively, and both function as Port 3 con·
trol lines. SCI functions as IS3 and can be used to indicate that
Port 3 input data is ready or output data has been accepted.
Three options associated with IS3 are controlled hy Port 3's
Control and Status Register and are discussed in Port 3 's des·
cription. If unused, IS3 can remain unconnected.
SC. is configured as OS3 and can be used to strobe output
data or acknowledge input data. It is controlled by Output
Strobe Select (OSS) in Port 3's Control and Status Register. The
strobe is generated by a read (OSS= 0) or write (OSS = I) to
Port 3's Data Register. OS3 timing is shown in Figure 5.

SCI and SC2 in Expanded Non-Multiplaxed Moda
In the Expanded Non·Multiplexed Mode, both SCI and SC.
are configured as outputs. SC, functions as Input/Output Select
(lOS) and is asserted only when $0100 through $OIFF is sensed
on the internal address bus.
SC. is configured as Read/Write and is used to control the
direction of data bus transfers. An CPU read is enabled when
Read/Write and E are high.
SCI and SC2 in Expanded Multiplexed Mode
In the Expanded Multiplexed Modes, both SCI and SC. are
configured as outputs. SCI functions as Address Strobe and can
be used to demultiplex the eight least significant addresses and
the data bus. A latch controlled by Address Strobe captures ad·
dress on the negative edge, as shown in Figure 20.
se. is configured as Read/Write and is used to control the
direction of data bus transfers. An CPU read is enabled when
Read/Write and E are high.

Nominal Crystal Parameter

~

4 MHz

5MHz

Co

7 pF max.

4.7 pF max.

R.

6Onmax.

30n typo

Item

2----------~IDI~-----------3

3

2

XTAL ~--4""---...,

CL 1 = CL2 = 22pF '20%
5 MHz)

(3.2-

Co
Equivalent Circuit

EXTAL ~--4"".,

(Note)These are representative
AT cut parallel resonance

crystal parameters.

ta) Nominal Recommended Crystal Parameters

L-4-.7~5-V----------~,F-------------------------------

Vee

E

RES

----------------~--------~
~-----tAe----~
Oscillator
Stabilization
Time, tRC

(b) Oscillator Stabilization Tim. (tRC)

Figure 15

550

Oscillator Characteristics

•

HITACHI

- - - - - - - - - - - - - - - - HD68P01V07, HD68P01V07-1, HD68POl MO, HD68P01MO-l
•

PORTS

There are four I/O ports on the MCU; three 8-bit ports and
one S-bit port. There are two control lines associated with one
of the 8-bit ports. Each port has an associated write only Data
Direction Register which allows each I/O line to be programmed
to act as an input or an output. A "I" in the corresponding
Data Direction Register bit will cause that I/O line to be an out·
put. A "0" in the corresponding Data Direction Register bit will
cause the I/O line to be an input. There are four ports: Port I.
Port 2, Port 3, and Port 4. Their addresses and the addresses of
their Data Direction registers are given in Table 2.

two lines, IS3 and OS3, which can be used to control Port 3
data transfers.
Three Port J options are controlled by the Port 3 Control
and Status Register and available only in Single-Chip Mode: (I)
Port 3 input data can be latched using IS3 as a control signal.
(2) OS3 can be generated by either an CPU read or write to
Port J's Data Register, and (3) an IRQ, interrupt can be enabled by an IS3' negative edge. Port 3 latch timing is shown in
Figure 6.
Port 3 Control and Status Register

Table 2 Port and Data Direction Register Addresses
Ports
I/O
I/O
I/O
I/O

Port 1
Port 2
Port 3
Port 4

Port Address

Data Direction
Register Address

$0002
$0003
$0006
$ooQ7

$0000
$0001
$0004
$0005

Bit 0-2
Bit 3

• P'O-P'7 (Port 1)
Port 1 is a mode independent 8-bit I/O port where each line
is an input or output as defined by its Data Direction Register.
The TIL compatible three-state output buffers can drive one
Schottky TTL load and 30 pF, Darlington transistors, or CMOS
devices using external pullup resistors. It is configured as a data
input port by RES. Unused lines can remain unconnected.
• PZO-PZ4 (Port 21
Port 2 is a mode independent S-bit I/O port where each line
is configured by its Data Direction Register. During lffiS, all
lines are configured as inputs. The TTL compatible three-state
output buffers can drive one Schottky TTL load and 30 pF or
CMOS devices using external pullup resistors. P20 , P 2 • and P 22
must always be connected to provide the operating mode. If
lines P23 and P 2 • are unused, they can remain unconnected.
P 20 , P 2 . , and P 21 provide the operating mode which is
latched into the Program Control Register on the positive edge
of RES. The mode may be read from Port 2 Data Register as
shown where Pe2 is latched from pin 10.
Port 2 also provides an interface for the Serial Communica·
tions Interface and Timer. Bit I, if configured as an output, is
dedicated to the timer's Output Compare function and cannot
be used to provide output from Port 2 Data Register.
Port 2 Data Register

I

7

6

PC21 PCI

543

2

I

0

P22

P21

P20

I I I I I I
PCO

P24

P23

$OOOF

$0003

Bit 4

Bit 5
Bit 6

Bit 7

Not used.
LATCH ENABLE. This bit controls the in·
put latch for Port 3. If set, input data is
latched by an IS3 negative edge. The latch
is transparent after a read of Port 3's Data
~ster. LATCH ENABLE is cleared by
RES.
OSS (Output Strobe Select). This bit determines whether OS3 will be generated by a
read or write of Port 3's Data Register.
When clear, the strobe is generated by a
read; when set, i~enerated by a write.
OSS is cleared by RES.
Not used.
IS3 IRQ, ENABLE. When set, an IRQ.
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt is
inhibited. This bit is cleared by RES.
IS3 FLAG. This read·only status bit is set
by an IS3 negative edge. It is cleared by a
read of the Port 3 Control and Status
Register (with IS3 FLAG set) followed by
a read or write to Port 3's Data Register or
by RES.

Port 3 in Expanded Non-Multiplexed Mode
Port 3 is configured as a bidirectional data bus (Do - 0 7 ) in
the Expanded Non.Multiplexed Mode. The direction of data
transfers is controlled by Read/Write (SC 2 ) and clocked by E
(Enable).
Port 3 in Expanded Multiplexed Mode
Port 3 is configured as a time multiplexed address (Ao - A,)
and data bus (Do - 0, ) in Expanded Multiplexed Mode where
Address Strobe (AS) can be used to demultiplex the two buses.
Port 3 is held in a high impedance state between valid address
and data to prevent potential bus conflicts.

• P30-P37 (Port 31
Port 3 can be configured as an I/O port, a bidirectional8·bit
data bus, or a multiplexed address/ data bus depending on the
operating mode. The TTL compatible three-state output buffers
can drive one Schottky TTL load and 90 pF. Unused lines can
remain unconnected.

• P4Q-P47 (Port 41
Port 4 is configured as an 8·bit I/O port, address outputs, or
data inputs depending on the operating mode. Port 4 can drive
one Schottky TTL load and 90 pF and is the only port with
internal pullup resistors. Unused lines can remain unconnected.

Port 3 in Single-Chip Mode
Port 3 is an 8·bit I/O port in Single-Chip Mode where each
line is configured by its Data Direction Register. There are also

Port 4 in Single Chip Mode
In Single Chip Mode, Port 4 functions as an 8-bit I/O port
where each line is configured by its Data Direction Register.

@HITACHI

551

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - Internal pullup resistors allow the port to directly interface with
CMOS at 5 volt levels. External pullup resistors to more than 5
volts, however, cannot be used.
Port 4 in Expanded Non-Multiplexed Mode
Port 4 is configured from RES as an 8·bit input port where
its Data Direction Register can be written to provide any or all
of address lines, Ao to A7. Internal pullup resistors are intend·
ed to pull the lines high until its Data Direction Register is
configured.
Port 4 in Expanded Multiplexed Mode
In all Expanded Multiplexed modes except Mode 6, Port 4
functions as half of the address bus a.!!!J?rovides As to A ls . In
Mode 6, the port' is configured from RES as an 8-bit parallel input port where its Data Direction Register can be written to
provide any or all of address lines, As to Als . Internal pullup
resistors are intended to pull the lines high until its Data Direction Register is configured where bit 0 controls As.
• OPERATING MODES
The MCV provides eight different operating modes which are
selectable by hardware programming and referred to as Mode 0
through Mode 7. The operating mode controls the memory
map, configuration of Port 3, Port 4, SC I , SC 2 , and the physical
location of interrupt vectors.
• Fundamental Modes
The MCV's eight modes can be grouped into three fundamental modes which refer to the type of bus it supports: Single
Chip, Expanded Non-Multiplexed, and Expanded Multiplexed.
Single chip modes include 4 and 7, Expanded Non-Multiplexed
is Mode 5 and the remaining five are Expanded Multiplexed
modes. Table 3 summarizes the characteristics of the operating
modes.
Single Chip Modes (4, 71
In Single-Chip Mode, the MCV's four ports are configured as
parallel input/output data ports, as shown in Figure 16. The
MCV functions as a monolithic microcomputer in these two
modes without external address or data buses. A maximum of
29 I/O lines and two Port 3 control lines are provided. In addition to other peripherals, another MCV can be interfaced to
Port 3 in a loosely coupled dual processor configuration. as
shown in Figure 17.
In Single-Chip Test Mode (4), the RAM responds to $XX80
through $XXFF and the ROM is removed from the internal address map. A test program must first be loaded into the RAM
using modes 0, I, 2, or 6. If the MCU is Reset and then programmed into Mode 4, execution will begin at $XXFE: XXFF.
Mode 5 can be irreversibly entered from Mode 4 without going
through Reset by setting bit 5 of Port 2's Data Register. This
mode is used primarily to test Ports 3 and 4 in the Single-Chip
and Non-Multiplexed Modes.
Expended Non-Multiplexed Mode (5)
A modest amount of external memory space is provided in
the Expanded Non-Multiplexed Mode while retaining significant on-<:hip resources. Port 3 functions as an 8-bit bidirectional
data bus and Port 4 is configured as an input data port. Any
combination of the eight least-significant address lines may be
obtained by writing to Port 4's Data Direction Register. Stated
alternatively, any combination of Ao to A7 may be provided
while retaining the remainder as input data lines. Internal pull-

552

•

up resistors are intended to pull Port 4's lines high until it is
configured.
Figure 18 illustrates a typical system configuration in the
Expanded Non-Multiplexed Mode. The MCU interfaces directly
with HMCS6800 family parts and can access 256 bytes of
external address space at $100 through $1 FF. IDS provides an
address decode of external memory ($100-$1 FF) and can
be used similarly to an address or chip select line.
Table 3 Summary of H06S00 Operating Modes
Common to all Mode.:

Reserved Register Area
Port 1
Port 2
Programmable Timer
Serial Communication Interface
Single Chip Mode 7
128 bytes of RAM; 2048 bytes of ROM
Port 3 is a parallel 1/0 port with two control lines
Port 4 is a parallel I/O port
SCI is Input Strobe 3 (iS3)
SC2 is Output Strobe 3 (OS31
Expanded Non·Multiplexed Mode 5
128 bytas of RAM; 2048 bytes of ROM
256 bytes of external memory space
Port 3 is an 8-bit data bus
Port 4 i. an input port/addre.s bus
SCI is Input/Output Select (lOS)
SC2 is r.ad/write (RM)
Expended Multiplexed Modes I, 2, 3, 6
Four memory space options (65k address space):
(1) No internal RAM or ROM (Mode 3)
(2) Internal RAM. no ROM (Mode 2)
(3) Internal RAM and ROM (Mod. 1)
(4) Internal RAM, ROM with partial address bus (Mode 6)
Port 3 is a'multiplexed address/data bus

Port 4 is an address bus (inputs/address in Mode 6)
SCI is Addre.. Strobe (AS)
SC2 is Read/Write (RM)
Telt Modes 0 and 4
Expanded Multiplexed Test Mode 0
May be used to test RAM and ROM
Single Chip and Non-Multiplexed Test Mode 4
(1) May be changed to Mode 5 without going thr?ugh Reset
(2) May be used to test Ports 3 and 4 as I/O ports

Expanded-Multiplexed Modes (0, 1,2,3,6)
In the Expanded-Multiplexed Modes, the MCU has the ability
to access a 65k bytes memory space. Port 3 functions as a time
multiplexed address/data bus with address valid on the negative
edge of Address Strobe (AS) and the data bus valid while E is
high. In Modes 0 to 3, Port 4 provides address line~ to A is .
In Mode 6, however, Port 4 is configured during RES as data
port inputs and the Data Direction Register can be changed to
provide any combination of address lines, As to Ais • Stated
alternatively, any subset of As to AIS can be provided while
retaining the remainder as input data lines. Internal pullup
resistors are intended to pull Port 4's lines high until software
configures the port.
Figure 19 depicts a typical configuration for the ExpandedMultiplexed Modes. Address Strobe can be used to control a
transparent D-type latch to capture addresses Ao to A7 , as
shown in Figure 20. This allows Port 3 to function as a Data Bus
when E is high.
In Mode 0, the Reset vector is external for the first two Ecycles after the positive edge of RES and internal thereafter. In

HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07·1, HD68P01MO, HD68P01MO·1
addition, the internal and external data buses are connected and
there must be no memory map overlap to avoid potential bus
conflicts. Mode 0 is used primarily to verify the ROM pattern

and monitor the internal data bus with the automated test
equipment.

Vee

Vee

Vee

_E

XTAL

XTAL
NMI

Port 1

Port 3
81/0 LlRes

8110 lIRes

Port 2
51/0 lines
Senal I/O
16-Slt Timer

Por14
8 I/O Lines

Vss

Port 1

Port 1

8110
llRes

8110
Lines

----------1

Port 2

8110
lines

16-81t Timer

Vss

Figure 16

Por14

51/0 LIRes
SCI

Vss

lines
16·Blt Timer

Single Chip Mode
Figure 17

Vec

Single Chip Dual Processor Configuration

Vee

Port 3
8 Data LIReS

Port 1

81/0 lines

Port 1

8110
Port 2

Port 2

5110
lints
Seriell/O
l6·Bit Timer

5110

Port 4

SCI

To8

Timer

Vss

Vss

Figure 1B

Expanded Non-Multiplexed Configuration

Vee

Vee

a==c:...-

I
XTAL
Port 3

EXTAL

Vee St ondby_

Port 1

IRQ,-

81/0 Lines

H068P01

.....

Port 1

8

Oat8 Bus

COo -0 7 1

e$

Address Bus
(Ao-Alsl

Port 4

AlliiimPori 3

8
latch

RIW

16

RIIN

E

8110
Port 2
51/0 Llnas
$'riaII/O
l6·Bit Timer

Port 4
8 LIRes
Address Sus

Port 2

5110

....

.....

SCI

.....

""0"

Timer

Tfr

Vss

Vss

Figure 19

I

ROM

II

RAM

II

PIA

I

Expanded Multiplexed Configuration

•

HITACHI

553

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 9 8 P 0 1 M 0 - 1 - - - - - - - - - - - - - - - GND
AS

I

G OC

0,

0,

74LS373
(Typical)

Port 3
[
Address/Data

Function Table

Output

Figure 20

Output

G

0

0

L
L
L
H

H
H
L
X

H
L
X
X

H
L

O.

08

Enable

Control

00
Z

Typical Latch Arrangement

• Programming The Mode
The operating mode is programmed by the levels asserted on
P n , P2 , , and P 20 which are latched into PC2, PCI, and PCO of
the program control register on the positive edge of RES. The
operating mode may be read from Port 2 Data Register as
shown below, and programming levels and timing must be met
as shown in Figure 8. A brief outline of the operating modes is
shown in Table 4.

Circuitry to provide the programming levels is dependent
primarily on the normal system usage of the three pins. If configured as outputs, the circuit shown in Figure 21 may be used;
otherwise, three-state buffers can be used to provide isolation
while programming the mode.

Port 2 Data Register
7

6

5

PC21 PCl

I I
PCO

4

321

P241 P231 P221 P21

I

0

P20

$0003

Table 4 Mode Selection Summary
Mode

Pn
(PC2)

P2I
(PC1)

P20
(PCO)

ROM

RAM

Interrupt
Vectors

Bus
Mode

I
I

I

I

I
I

I
I

I
MUX(S.61
NMUX(s.6)

7

H

H

H

6

H

H

L

5
4
3

H

L
L

H

I

H

L

1(2)

1(1)

I

I

L

H

H

2
1

L
L

H

L

E
E

E
I

L

H

I

I

E
E
E

MUX(4)
MUX(4)
MUX(4)

0

L

L

L

I

I

1(3)

MUX(4)

Legend:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non·Multiplexed
L - Logic ··0"
H - Logic "I"

554

-- -----

Operating Mode
Single Chip
Multiplexed/Partial Decode
Non·Multiplexed/Partial Decode
Single Chip Test
Multiplexed /No RAM or ROM
Multiplexed /RAM
Multiplexed/RAM & ROM
Multiplexed Test

Notes:
(1) Internal RAM is addressed at $XX80
(2) I nternol ROM is disabled
(31 RES vector is external for 2 cycles after RES goes high
(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3
(5) Addresses associated with Port ~ are considered external in Modes 5 and 6
(6) Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register

•

HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-l
Vee

R
RI RI RI
6

I I I

A
Xo

B

C

Yo

x

~ Zo

Y

XI

Z

RES
HD6BPOI

8
9
10

P20 (PCO)

P21 (PC1)
P 22 (PC2)

YI
ZI
C

I

???
~

Mode
Control
Switch

Figure 21

HD14053B

Inh

INOTES)

J,

1) Mode 7 as shown
2) RC ~ Reset time constant

3) RI

= 10kn

Recommended Circuit for Mode Selection

Truth Table
Control Input
On Switch
Inh
A
B

Select

Binary to 1-01-2
Decoder with

Inhibit

C B A

Inhibit

C

0
_.
0

-.

Xlo-------------------~~r+_r--~

X

Yoo---------------------~~~+---.

Ylo-----------------------~H_+-~

Y

Zoo-----------------------~~--,

Zlo-------------------------~C*~

Figure 22

Z

-

Zo

Yo

Xo

1

Zo

Yo

XI
Xo

0_. 0

0

0

1 0

Zo

YI

0

0

1

1

Zo

YI

XI

0

1 0

0

ZI

Yo

Xo

-_._-Xoo-----------------~tr~r+_r--,

HD14053B

0 0 0

0

1

0 1 ZI

Yo

XI

0

1

1 0

ZI

YI

Xo

0

1

1

ZI

YI

XI

1

X X X

1

-

HD14053B Multiplexers/Demultiplexers

•

HITACHI

555

HD68P01V07, HD68P01V07-1, HD68POl MO, HD68POl M O - l - - - - - - - - - - - - - - - • MEMORY MAPS
The MeU can provide up to 65k bytes address space depending on the operating mode. The HD68PO I provides 8k bytes ad·
dress space for EPROM, but the maps differ in EPROM types as
follows.
I) HN482732A (a 4k·byte EPROM)
In order to support the HD680IVO, EPROM of the
HD68POIV07/HD68POIV07·1 must be located at $FOOO·
$FFFF.
2) HN482764 (a 8k·byte EPROM)
The HD68POIMO/HD68POIMO·I can provide up to
8k bytes address space using HN482764 instead of
HN482732A. In this case, EPROM of the HD68POIMO/
HD68PO I MO· I is located at $EOOO·$FFFF.
A memory map for each operating mode is shown in Figure
23. The first 32 locations of each map are reserved for the
MeU's internal register area, as shown in Table 5, with excep·
tions as indicated.
Refer to "Precaution when emulating the HD6801 Family".

Table 5 Internal Register Area
Register

Port 1 Data Direction Register·" *
Port 2 Data Direction Aegister·""
Port 1 Data Register

Port 2 Data Aegistar
Port 3 Data Direction Register·"'"

Port 4 Data Direction Register·-Port 3 Data Aegister
Port 4 Data Aegistar
Timer Control and Status Register

Counter (High Byta)
Counter I Low Byte)
Output Compare Aegistar (High Byta)
Output Compare Aegister (Low Byta)
Input capture Aegister (High Byta)
Input capture Aegistar (Low Byta)
Port 3 control and Status Register

Aate and Mode Control Aegister

Address

00
01
02
03
04·
05*·
OS·
07*·
OB
09
OA
OB
OC
00
OE
OF·

Transmit Data Register

10
11
12
13

AAM Control Aegistar
Aeserved

14
15-1F

Transmit/Receive Control and Status Register
Receive Data Register

... External address in Modes 0, 1, 2, 3, 5, 6; cannot be accessed in

Mode 5 (No lOS)
•• External addresses in Modes 0, I, 2. 3

.*. 1

556

•

~

Output.

HITACHI

a

1'&

Input

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01M0-1

HD68POl
Mode

o

HD68POl
Mode

1

Multiplexed/RAM & EPROM

MUltiplexed Test mode
$000011)

$0000 111
Internal Registers

Internal Registers

$OOlF

$OOlF
External Memory Space

External Memory Space

$0080

$0080

Internal RAM

Internal RAM

$OOFF
$OOFF

External Memory Space

External Memory Space

$EOoo
$EOoo

EPROM
$FFEF

EPROM

$FFFO
$FFFFI21

Internal Interrupt Vectors(2

(NOTES)
11 Excludes the following addresses which may

be used externally: $04, $05, $06, $07 and $OF
2) Addresses $FFFE and $FFFF are considered
external if accessed within 2 cycles alter a
positive edge of RES and Internal at all other
times.
3) After 2 CPU cycles, there must be no over·
lapping of internal and external memory

External Interrupt Vectors

$FFFF ' - - - - - "

(NOTES]
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07 and
$OF.
2) EPROM addresses $FFFO to $FFFF are

not usable.

spaces to avoid driving the data bus with more
than one device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in EPROM
using an external Reset vector.

Figure 23

•

HD68POl Memory Maps

HITACHI

557

c

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - -

HD68POl
Mode

2

HD68POl
Mode

3

Multiplexed/RAM
$0000(1)

$0000(1
}

Internal Registers

Internal Registers

$OOIF
External Memory Space

$0080
Internal RAM

$OOFF

External Memory Space
External Memory Space

$FFFO~----t\

$FFFF

L-_ _ _..

External Interrupt Vectors

L-_ _ _. .

I

External Interrupt Vectors

(NOTE)

(NOTE)

1) Excludes the followmg addresses which may
be used eXlernally: $04, $05, $06, $07, and

1) Excludes the following addresses which may
be used externally' $04, $05, $06, $07 and

$OF.

$OF.

Figure 23

558

$FFFO ~----I
$FFFF

HD68POl Memory Maps (Continued)

•

HITACHI

- - - - - - - - - - - - - - - - HD68P01V07, HD68P01V07-1, HD68P01 MO, HD68P01 M0-1

HD68POl
Mode

4

HD6BPOl
Mode

Single Chip Test

5

Non-Multiplexed/Partial Decode
$0000(11

$0000
Internal Registers

Internal Registers

$oolF

$OOlF

$0080
Internal RAM

$OOFF

$0100
External Memory Space

$OlFF

'-_..-_.J

SEOOO

EPROM
Internal RAM
Internal Interrupt Vectors
(NOTES]
11 The internal ROM IS disabled.
2) Mode 4 may be changed to Mode 5 wIthout
having to assert RESET by writing a "1" Into
the peo bit of Port 2 Data RegISter.
3) Addresses A8 to AI 5 are treated as "don't
cares" to decode internal RAM.

4) Internal RAM WIll appear at $XXBO to $XXFF.

$FFFF

Internal Interrupt Vectors

(NOTES]
1) Excludes the following addresses which may

not be used e..ernally: S04, $06, and $OF.
(No 10SI
21 This mode may be entered without going
through RESET by uSIng Mode 4 and subsequently writing a "'" into the pea bit of
Port 2 Data Register.

3) Address lines Ao .... A., will not contain addresses until the Data Direction Register for Port 4
has been written with "l's" in the appropriate
bits. These address lines will assert ",'s" until
made outputs by writing the Data Direction
Register.

Figure 23

HD68POl Memory Maps (Continued)

$

HITACHI

559

HD68P01V07, HD68P01V07·1, HD68P01MO, H D 6 8 P 0 1 M O · 1 - - - - - - - - - - - - - - - -

HD68POl
Mode

6

HD68POl
Mode

7

Single Chip

Multiplexed/Partial Decode
$0000(1)

$OOOO~}

Internal Registers

Internal Registers

$001 F IC-"""'~""'''
Unusable
S0080

SOOIF
External Mel'T,ory Space

S0080
Internal RAM

SOOFF

$OOFF

External Memory Space

$EooO

$FFFF

$EOoo
EPROM

EPROM

Internal Interrupt Vectors

Internal Interrupt Vectors

$FFFF

[NOTES)
1) Excludes the following address which may be
used externally: $04, $06, $OF.
2) Address lines AI ..... A u will not contain
addresses until the Data Direction Register for
Port 4 has been written with "l's" in the

appropriate bits. These address lines will
assert "l's" until made outputs by writing the
Data Direction Register.

Figure 23 HD68POl Memory Maps (Continued)

560

$

HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-1
• PROGRAMMABLE TIME
The Programmable Timer can be used to perform input waveform measurements while independently generating an output
waveform_ Pulse widths can vary from several microseconds to
many seconds. A block diagram of the Timer is shown in Figure

24.
• Counter ($09:0A)
The key timer element is a 16-bit free-running counter which
is incremented by E (Enable). It is cleared during RES and is
read-only with one exception: a write to the counter ($09) will
preset it to $FFF8. This feature, intended for testing, can disturb serial operations because the counter provides the SCI's
internal bit rate clock. TOF is set whenever the counter contains
aliI's.
• Output Compare Register ($OB:OC)
The Output Compare Register is a 16-bit Read/Write register
used to control an output waveform or provide an arbitrary
timeout flag. It is compared with the free-running counter on
each E-cyc1e. When a match is found, OCF is set and OLVL is
clocked to an output level register. If Port 2, bit I, is configured
as an output, OLVL will appear at P 21 and the Output Compare
Register and OLVL can then be changed for the next compare.
The function is inhibited for one cycle after a write to its high
byte of the Compare Resister ($OB) to ensure a valid compare.

The Output Compare Register is set to $FFFF by RES.
•

Input Capture Register ($00: OE)
The Input Capture Register is a 16-bit read-only register used
to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should be configured as an input, but the edge detect circuit always senses P 20
even when configured as an output. An input capture can occur
independently of ICF: the register always contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte CPU read. The input pulse width must
be at least two E-cycles to ensure an input capture under all
conditions.

• Timer Control and Status Register ($08)
The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits 0-4 can be
written. The three most significant bits provide the timer's
status and indicate if:
a proper level transition has been dtected,
a match has been found between the free-running counter
and the output compare register, and
the free-running counter has overflowed.
Each of the three events can generate an IRQ2 interrupt and
is controlled by an individual enable bit in the TCSR.

HD68POl Internal Bus

...----1-'::;';;';;": OE

Timer
Control

I

b~7i:;=j:::;:i::;::::;:=:;::~.l.,...~

And Iy--J....--J-~-.--'--r-'-T"-'-..............
Status

Register

Bit 1

$08

Port 2
DDR

.---I

_____ ~Output Input
Level Edge
Bit 1

BitO

Port 2 Port 2

Figure 24

Block Diagram of Programmable Timer

•

HITACHI

561

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - 1 - - - - - - - - - - - - - - - Time'r Control and Status Register (TCSR)
7

6

Bit 0 OLVL

Bit I IEDG

Bit 2 ETOI

Bit 3 EOCI

Bit 4 EICI

Bit 5 TOF

Bit 6 OFC

Bit 7 ICF

543

2

1

0

Output level. OLVL is clocked to the output
level register by a successful output compare and
will appear at P" if Bit I of Port 2's Data Direction Register is set It is cleared by RES,
Input Edge_ IEDG is cleared by RES and controls
which level transition will trigger a counter transfer to the Input Capture Register:
IEDG =0 Transfer on a negative-edge
IEDG =I Transfer on a positive-edge,
Enable Timer Overflow Interrupt When set, an
IRQ, interrupt is enabled for a timer overflow;
when clear, the interru pt is inhibited, It is cleared
by RES,
Enable Output Compare Interrupt When set, an
IRQ, interrupt is enabled for an output compare; when clear, the interrupt is inhibited, It is
cleared by RES.
Enable Input Capture Interrupt When set, an
IRQ, interrupt is enabled for an input capture;
when clear, the interrupt is inhibited, It is
cleared by RES.
Timer Overflow Flag. TOF is set when the
counter contains all I's. It is cleared by reading
the TCSR (with TOF set) followed by the
counter's high byte ($09), or by RES.
Output Compare Flag. OCF is set when the Output Compare Register matches the free-running
counter_ It is cleared by reading the TCSR (with
OCF set) and then writing to the Output Compare Register ($OB or $OC), or by RES_
Input Capture Flag. ICF is set to indicate a
proper level transition; it is cleared by reading
the TCSR (with ICF set) and then the Input
Capture Register High Byte ($00), or by RES.

• SERIAL COMMUNICATIONS INTERFACE (SCII
A full-duplex asynchronous Serial Communications Interface
(SCI) is provided with a data format and a variety of rates. The
SCI transmitter and receiver are functionally independent, but
use the same data format and bit rate. Serial data format is
standard mark/space (NRZ) and provides one start bit, eight
data bits, and one stop bit "Baud" and "bit rate" are used
synonymously in the following description_
• Wake-Up Feature
In a typical serial loop mUlti-processor configuration, the
software protocol will usually identify the addresse(s) at the
beginning of the message_ In order to permit uninterested MCU's
to ignore the remainder of the message, a wake-up feature is
included whereby all further SCI receiver flag (and interrupt)
processing can be inhibited until its data line goes idle. An SCI
receiver is re-enabled by an idle string of ten consecutive I's or
by RES. Software must provide for the required idle string
between consecutive messages and prevent it within messages.
• Programmable Options
The following features of the SCI are programmable:
• format: Standard mark/space (NRZ)

562

clock: external or internal bit rate clock
Baud (or bit rate): one of 4 per E-clock frequency, or external bit rate (X8) input
wake-up feature: enabled or disabled
interrupt requests: enabled individually for transmitter
and receiver
clock output: internal bit rate clock enabled or disabled
to P22
Port 2 (bit 3, 4): dedicated or not dedicated to serial I/O
individually for transmitter and receiver.

•

• Serial Communications Registers
The Serial Communications Interface includes four addressable registers as depicted in Figure 25. It is controlled by the
Rate and Mode Control Register and the Transmit/Receive Control and Status Register. Data is transmitted and received utilizing a write-only Transmit Register and a read-only Receive
Register. The shift registers are not accessible to software.
Bit 7

Rate and Mode Control Register

Bit 0

I I I I I cCll cco lss+so
X

X

X

X

l$10

Transmit/Receive Control and Status Register

Port 2
Rx

11

B"
3

Tx

Receive Shift Register

12

B"
4

$13

Figure 25

SC I Registers

Rate and Mode Control Register (RMCR) ($10)
The Rate and Mode Control Register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P 22 • The .!!S!ster consists of four write-only
bits which are cleared by RES. The two least significant bits
control the bit rate of the internal clock and the remaining two
bits control the format and clock source.
Rate and Mode Control Register (RMCR)
7

6

5

43210

x

x

x

x

HITACHI

I I I I I
eel eeo SSI

SSO

$0010

- - - - - - - - - - - - - - - - HD68P01V07, HD68P01V07-1, HD68P01MO, HD68P01M0-1
Bit I: Bit 0

SSI: SSO Speed Select. These two bits select the
Baud when using the internal clock. Four rates
may be selected which are a function of the MCV
input frequency. Table 6 lists bit time and rates
for three selected MCV frequencies.
CCI:CCO Clock Control Select. These two bits
Bit 3: Bit 2
select the serial clock source. If CCI is set, the
DDR value for P22 is forced to the complement
of CCO and cannot be altered until CC I is
cleared. If CCI is cleared after having been set,
its DDR value is unchanged. Table 7 defines the
clock source, and use ofP 22 .
If both CCI and CCO are set, an external TTL compatible
clock must be connected to P22 at eight times (8X) the desired
bit rate, but not greater than E, with a duty cycle of 50% (±
10%). IfCCI :CCO = 10, the internal bit rate clock is provided at
P22 regardless of the values for TE or RE.

Bit 2 TIE

Bit 3 RE

Bit 4 RIE

Bit 5 TORE

(Note) The source of SCI internal bit rate clock is the timer's free run·
ning counter. An CPU write to the counter can disturb serial
operations.

Transmit/Receive Control and Status Register (TRCSR) ($11)
The Transmit/Receive Control and Status Register controls
the transmitter, receiver, wake-up feature, and two individual
interrupts and monitors the status of serial operations. All eight
bits are readable while bits 0 to 4 are also writable. The register
is initialized to $20 by RES.

Bit 6 ORFE

Transmit/Receive Control and Status Register (TRCSR)
765432'0

"Wake-up" on Idle Line. When set, WV enables
the wake-up function; it is cleared by ten consecutive I's or by RES. WV will not set if the line
is idle.
Transmit Enable. When set, P2• DDR bit is set,
cannot be changed, and will remain set if TE is
subsequently cleared. When TE is changed from
clear to set, the transmitter is connected to P2•

BitOWU

Bit I TE

Bit 7 RDRF

and a preamble of nine consecutive I's is transmitted. TE is cleared by RES.
Transmit Interrupt Enable. When set, an IRQ2
interrupt is enabled when TORE is set; when
clear, the interrupt is inhibited. TE is cleared by
RES.
Receive Enable. When set, P23 's DDR bit is
cleared, cannot be changed, and will remain clear
if RE is subsequently cleared. While RE is set,
the SCI receiver is enabled. RE is cleared by
RES.
Receiver Interrupt Enable. When set, an IRQ,
interrupt is enabled when RDRF and/or ORFE is
set; when clear, the interrupt is inhibited. RIE is
cleared by RES.
Transmit Data Register Empty. TORE is set
when the Transmit Data Register is transferred to
the output serial shift register or by RES. It is
cleared by reading the TRCSR (with TORE set)
and then writing to the Transmit Data Register.
Additional data will be transmitted only if TORE
has been cleared.
Overrun Framing Error. If set, ORFE indicates
either an overrun or framing error. An overrun is
a new byte ready to transfer to the Receiver Data
Register with RDRF still set. A receiver framing
error has occurred when the byte boundaries of
the bit stream are not synchronized to the bit
counter. An overrun can be distinguished from a
framing error by the value of RDRF: if RDRF is
set, then an overrun has occurred; otherwise a
framing error has been detected. Data is not
transferred to the Receive Data Register in an
overrun or framing error condition. ORFE is
cleared by reading the TRCSR (with ORFE set)
then the Receive Data Register, or by RES.
Receive Data Register Fun. RDRF is set when
the input serial shift register is transferred to the
Receive Data Register. It is cleared by reading
the TRCSR (with RDRF set), and then the Receive Da ta Register, or by RES.

Table 6 SCI Bit Times and Rates
4.0 MHz
2.4576 MHz
XTAL
E
614.4 kHz
1.0 MHz
SSl : SSO
E .;.16
26 I1S/38,400 Baud
16 I1s/62,500 Baud
0
0
E';'128
1
0
208!1s/4,800 Baud
128!1s/7812.5 Baud
0
E.;. ~024
1.67ms/600 Baud
1
1.024ms/976.6 Baud
E ';'4096
1
6.67ms/150 Baud
1
4.096ms/244.1 Baud
• HD68P01V07·1, HD68P01MO·l only
Table 7 SCI Format and Clock Source Control
CC1:
0
0
1
1

CCO
0
1
0
l'

Format

Clock Sou rce

Port 2 Bit 2

-

-

-

NRZ
NRZ
NRZ

Internal
Internal
External

Not Used
Output'
Input

....
....

Port 2 Bit 3

4.9152 MHz'
1.2288 MHz
13/ls/76,800 Baud
104.2/ls/9,600 Baud
833.3 /ls/ 1,200 Baud
3.33 ms/300 Baud

....
....

Port 2 Bit 4

* Clock output is available regardless of values for bits A E and TE .
•• Bit 3 is used for serial input if RE = "'" in TRCS; bit 4 is used for serial output if TE = "'" in TRCS.

$

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563

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - •

Internally Generated Clcok
If the user wishes for the serial I/O to furnish a clock. the following requirements are applicable:
the values of RE and TE are immaterial.
eCI. CCO must be set to 10
the maximum clock rate will be E -;- 16.
the clock will be at 1X the bit rate and will have a rising
edge at mid-bit.
Externally Generated Clock
If the user wishes to provide an external clock for the serial
I/O. the following requirements are applicable:
the eCI. eco. field in the Rate and Mode Control Register must be set to 11.
the external clock must be set to 8 times (X8) the desired
baud rate and
the maximum external clock frequency is 1.0 MHz.

Then the 8 data bits (beginning with bit 0) followed by the stop
bit (1). are transmitted. When the Transmitter Data Register has
been emptied. the TORE flag bit is set.
If the MCU fails to respond to the flag within the proper time, (TORE is still set when the next normal transfer from
the parallel data register to the serial output register should
occur) then a 1 will be sent (instead of a 0) at "Start" bit tirne,
followed by more l's until more data is supplied to the data
register. No O's will be sent while TORE remains a 1.

•

• Serial Operations
The SCI is initialized by writing control bytes first to the
Rate and Mode Control Register and then to the Transmit/R~·
ceive Control and Status Register.
The Transmitter Enable (TE) and Receiver Enable (RE) bits
may be left set for dedicated operations.
Transmit operations
The transmit operation is enabled by TE in the Transmit/Re.
ceive Control and Status Register. When TE is set, the output of
the transmit serial shift register is connected to P2. and the
serial output by fITst transmitting to a ten-bit preamble of I's.
Following the preamble, internal synchronization is established
and the transmitter section is ready for operation.
At this point one of two situation exist:
I) if'the Transmit Data Register is empty (TORE = I), a con·
tinuous string of ones will be sent indicating an idle line.
or,
2) if a byte has been written to the Transmit Data Register
(TORE.= 0), it is transferred to the output serial shift reg·
ister and transmission will begin.
During the transfer itself. the start bit (0) is first transmitted.

Receive Operations
The receive operation is enabled by RE which configures
P23. The receive operation is controled by the contents of the
Transmit/Receive Control and Status Register and the Rate and
Mode Control Register.
The receiver bit interval is divided into 8 sub-intervals for
internal synchronization. In the NRZ Mode, the received bit
stream is synchronized by the first 0 (space) encountered.
The approximate center of each bit time is strobed during
the next 10 bits. If the tenth bit is not a I (stop bit) a framing
error is assumed, and ORFE is set. If the tenth bit is a 1. the
data is transferred to the Receive Data Register, and interrupt
flag RDRF is set. If RDRF is still set at the next tenth bit time,
ORFE will be set, indicating an over·run has occurred. When the
MCU responds to either flag (RDRF or ORFE) by reading
the status register followed by reading the Data Register, RORF
(or ORFE) will be cieared.
•

INSTRUCTION SET
The H068PO 1 is upward source and object code compatible
with the HD6800. Execution times of key instructions have
been reduced and several new instructions have been added,
including hardware multiply. A list of new operations added to
the HD6800 instruction set is shown in Table 8.
In addition, two new special opcodes, 4E and SE, are provided for test purposes. These opcodes force the Program Counter
to increment like a 16-bit counter, causing address lines used
in the expanded modes to increment until the device is reset.
These opcodes have no mnemonics.

Table 8 New Instructions
Instruction

Description

ABX
ADDD
ASLD
BRN
LDD
LSRD
MUL
PSHX
PULX
STD
SUBD

Unsigned addition of Accumulator B to Index Register
Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator
Shifts the double accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C·bit
Branch Never
Loads double accumulator from memory
Shifts the double accumulator right (towards LSB) one bit; the MSB is cleared and the LSB is shifted into the C·bit
Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator
Pushes the Index Register to stack
Pulls the Index Register from stack
Stores the double accumulator to memory
Subtracts memory from the double accumulator and leaves the difference in the double accumulator

564

•

HITACHI

- - - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-l
• Programming Model
A programming model for the HD68POI is shown in Figure
10. Accumulator A can be concatenated with accumulator B
and jointly referred to as accumulator D where A is the most
significant byte. Any operation which modifies the double
accumulator will also modify accumulator A and/or B. Other
registers are defined as follows:

• Addressing Modes
The CPU provides six addressing modes which can be used
to reference memory. A summary of addressing modes for all
instructions is presented in Table 9, 10, II, and 12 where execution times are provided in E·cycles. Instruction execution times
are summarized in Table 13. With an input frequency of 4 MHz,
E-cycles are equivalent to microseconds. A cycle-by·cycle
description of bus activity for each instruction is provided in
Table 14 and a description of selected instructions is shown in
Figure 26.

Program Counter
The program counter is a 16·bit register which always points
to the next instruction.

Immediate Addressing
The operand or "immediate byte(s)" is contained in the following byte(s) of the instruction where the number of bytes
matches the size of the register. These are two or three byte
instructions.

Steck Pointer
The stack pointer is a 16·bit register which contains the address of the next available location in a pushdown/pullup
(LIFO) queue. The stack resides in random access memory at a
location defined by the programmer.

Direct Addressing
The least significant byte of the operand address is contained
in the second byte of the instruction and the most significant
byte is assumed to be $00. Direct addressing allows the user to
access $00 through $FF using two byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, the 256-byte area is reserved for
frequently referenced data.

Index Register
The Index Register is a 16·bit register which can be used to
store data or provide an address for the indexed mode of
addressing.
Accumulators
The CPU contains two 8·bit accumulators, A and B, which
are used to store operands and results from the arithmetic logic
unit (ALU). They can also be concatenated and referred to as
the D ( double) accumulator.

Extended Addressing
The second and third bytes of the instruction contain the abo
solute address of the operand. These are three byte instructions.

Condition Code Registers
The condition code register indicates the results of an instruction and includes the following five condition bits: Negative (N), Zero (Z), Overflow (y), Carry/Borrow from MSB (C),
and Half Carry from bit 3 (H). These bits are testable by the
conditional branch instruction. Bit 4 is the interrupt mask
(I-bit) and inhibits all maskable interrupts when set. The two
unused bits, b6 and b7 are read as ones.

Indexed Addressing
The unsigned offset contained in the second byte of the instruction is added with carry to the Index Register and used to
reference memory without changing the Index Register. These
are two byte instructions.

Table 9 Index Register and Stack Manipulation Instructions

Pointer Operations

Mnemonic

Immed
OP

-

#

OP

3

9C

-5

Extend

Index

Direct

-

#

OP

2

AC 6

#

OP

-

#

Implied
OP

-

Booleanl
Arithmetic Operation

Condo Code Reg.

5 4
H

#

3

2

I N Z

··

1 0
V

C

I

I

Add

ABX

3A

3

1

B+X- X

Push Data

PSHX

3C

4

1

X L -M sp.SP-l-SP

• I
• •
• • •
• • •
•
• • I
• • I
• I
•• I
• • •
• • •
•• •
• • •

Pull Data

PULX

3B

5

1

X H - MSp. SP -1 - SP
SP + 1 - SP. MSp- X H

• • • • • •

Compare Index Reg

CPX

Decrement Index Reg

OEX

Decrement Stack Pntr

DES

Increment lodex Reg

INX

Increment Stack Pntr

INS

Load Index Reg

LOX

Load Stack Pntr

LOS

BC

4

2 BC 6 3

--

CE
f-BE

DE 4

3

3

3

3 9E

2 EE 5 2 FE
2 AE 5 2 BE

5 3
5 3

EF 5 2 FF
2 AF 5 2 BF

5 3

X - M: M + 1
09

3

1

X -1- X
SP-l-SP

34

3

1

OB

3

1

X + I-X

31

3

1

SP+l-'SP
M-XH.IM+lI-XL
M- SP H .IM+l)-SPL
X H -M,XL-I M + 1)

Store Index Reg

STX

4
OF 4

Store Stack Pntr

STS

9F

Index Reg - Stack Pntr

TXS

35

3

1

X-l-SP

Stack Pntr - Index Reg

TSX

30

3

1

SP+l-X

4

2

5

SPH - M. SP L - 1M + 1)

3

· ·
·

I
I

• •
• • •
I • •
• • •
I R •
I R •
I R •
I R •
• • •
• • •
• • •
• • •

SP + 1- SP, Msp- XL
The Condition Code Register notes are listed after Table 12 .

•

HITACHI

565

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - Implied Addressing
The operand(s) are registers and no memory referenr.e is
required. These are single byte instructions.

the branch condition is true, the Program Counter is overwritten
with the sum of a Signed single byte displacement in the second
byte of the instruction and the current Program Counter. This
provides a branch range of -126 to 129 bytes from the first
byte of the instruction. These are two byte instructions.

Relative Addressing
Relative addressing is used only for branch instructions. If

Table 10 Accumulator and Memory Instructions
Accumulator and
Memory Operations

Mnemonic

Add Acmltrs

ABA

AddBtoX

ABX

Add with Carry

Immed

OP

-

Direct

# OP

-

-

Index
# OP
#

-

3 2

A9 4

3 2

E9 4

3

2

A8 4

3

2

EB 4

ADDB
ADDD

C3

4

3

03 5 2

E3

And

ANDA

84
C4

2
2

2
2

94

ANDB
Shift Left, Arithmetic

ADDA

B + X .... X

89

C9

2 99
2 09
2 9B
2 DB

B9 4

3

A+M+C .... A

4

3

B+M+C .... B

BB 4

3

A+ M .... A

FB 4

3

B+M .... A

F3

3

6

3

2

A4 4

04 3

2

E4 4

ASL

-

68

6

2
2
2
2
2
2
2
2

F9

B4 4

3

F4 4

3

B,M .... B

78

3

6

48

Shift Left Obi

ASLD

Shift Right, Arithmetic

ASR

Bit Test

-I-- -.. -- r-

0'-

--

58

-67

05
6

2

77

6

3
47

2

1

ASRB

57

2

1

3 2

85

2 2

95

81TB

C5

2 2

05 3 2

Compare Acmltrs

CBA

Clear

CLR

A5 4

E5 4
---- ,-6F

6

2
2

B5 4

3

F5 4

3

2

7F

3

CLRB

1'$ Complement

CMPA

Bl

2

CMPB

C1

2

COM

DAA

Decrement

DEC

Increment

3

2

A1

4

01

3 2

El

r-- 63

-

- 1--

---

COMB
Decimal Adj, A

91

'1--

COMA

Exclusive OR

2
2
-

Bl

4

3

4

2
2

Fl

4

3

6

2

73

6

3

,-,

,-

-

,---

- c- --

--

--

6A 6

2

7A 6

A- B

OO .... M
1

OO .... A

1

OO .... B
A-M

--t-o

B -M
-- -='
l\iI .... M

43

2

1

7f. .... A

53

2
2

1

B .... B

1

Adi binary sum to BCD

3

M-l .... M

DECA

4A 2

1

A -1 .... A

DECB

5A 2

1

B-l .... B

EORA

B8

2

EDRB

C8

2

2
2

98

3

08 3

A8 4

2
2

E8

INC

4

6C 6

2
2
2

B8 4

3

A\t>M .... A

FB 4

3
3

M+ I .... M

7C 6

LDAA
LDAB

Load Double

LDD

Logical Shift, Left

LSL

B
4C

2
5C 2

INCB

Shift Right, Logical

S-- 1

B'M

--t----

4F 2
5F 2

19

INCA
Load Acmltrs

A'M
11

6

CLRA
Compare

2 1
2 1
3 1

ASRA
81TA

A+B .... A

D+M:M+l .... D
A,M .... A

6

ASLA
ASLB

Boolean Expression

,

Add Double

Add

Implied
# OP
#
- lB 2 1
3A 3 1

-

-'
2
2
8B 2
CB 2

ADCA
ADCB

Extend
OP

B6

2 2
C6 2 2
CC 3 3

A6 4

3

2
06 3 2
DC 4 2

96

2
E6 4 2
EC 5 2
58 6 2

1
1

F6 4

3

M .... B
M:M + 1 .... 0

FC 5 3
78

6

3
1

LSLB

5B
05

2
3

1

LSLD
LSRA

44

2

1

LSRB

54

2

1

LSRD

04

3

1

2

B + I .... B
M .... A

2

6

A+ I .... A

3

48

64

M .... B

B6 4

LSLA

LSR

Gl

74

6

1

3

Condo Code Reg.
H I N Z V C

• t t t t
t • t t t t
t

• • • • • •
t • t t
t • t t
t • t t
• • t t

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

•
•
•
•
•

t
t
t
t
t
t

• t
• t
• t
• t
• t
• t

•

•
•

•
•

• •
• •

• •
• •
• •

t
t

t t
t t

t t
t t
R

•

R •

t t t
t
t
t
t
t
t
t
t
t

t t
t t
t t
t t
t t
t t
R

•

R •

t t

R S R R
R S R R
R S R R

t
t
t
t
t
t
t
t
t
t

t
t
t
t
t
t
t
t

t t
t t
R S
R S
R S

t t
t •
t •

• •
• • t t •
• • t R •
• • t t R •

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

t
• ,t
• t
• t
• t
• t

•
•
•
•
•
•
•
•

t t

t t
t t
t R
t R

•
•
•
•
•

t R •
t t t t
t t t t
t t t t
t t t t
R t t t
R t t t
R t t t
t f t
R
(Continued)

566

•

HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-l
Table 10 Accumulator and Memory Instructions (Continued)
Accumulator and
Memory Operations

Mnemonic

Multiply

MUL

2's Complement
(Negatel

NEG

Immed
OP

-

Index

Direct

OP

#

-

# OP
60

6

Extend
Implied
# OP
# OP
#

-

2

70

6

-

3D 10 1

Boolean Expression
A X B-+O
OO-M-+M

3

NEGA

40

2

1

50

2

1

OO-B-+B

No Operation

NEGB
NOP

01

2

1

PC+l-+PC

Inclusive OR

ORAA

BA 2

2

9A 3

2

AA 4

2

BA 4

3

ORAB

CA 2

2

OA 3

2

EA 4

2

FA 4

3

Push Data

PSHA
PSHB

Pull Data

1-- i--- --

PULA

---

PULB
Rotate Left

ROL

-

.- f-.

ROLA

69

6

--- --

2

79

-

6

ROR

66

1

A

37

3

B -+Stack

32

4

1
1

Stack .... A

33

4

1

Stack .... B

49

2

1

76 '6

2

2

1

2

1

2

1

10

2

1

82

2

2

92

SBCB

C2

2

2

02 3

STAA

97

STAB
STO
SUBA

80

2 2

SUBB

CO

2

2

Subtract Double

SUBO

83

4

3

Transfer Acmltr

TAB

A - B-+A

A2 4

2

B2

4

3

A-M-C .... A

2

E2

4

2

F2

4

3

S-M-C .... S

3

2

A7 4

2

B7

4

3

A .... M

07 3

2

E7

4

2

F7

4

3

B-+M

DO 4

ED 5

2

FO 5

3

O-+M:M+l

90

AO 4

2

BO

4

3

A-M .... A

EO

2
2

FO

4

3

B3
. ..

6

3 -_ ..
16

2

1

A .... B

17

2

1

B .... A

3 2

2
3 2
DO 3 2
93 5 2

---

..

TBA
TST

4

A3 6

60

TSTA

62.

-

_-

70

-

S -M .... B
0-M:M+l .... 0

'6" '3"

M -00
40

2

1

A -00

50 2

1

B -00

-~

TSTB

I

N Z V C

•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• • •

•
•

•
•
•
•
•
•

3
46

SBCA

~Stack

3

56

SBA

Test, Zero or Minus

3

RORA

Subtract with Carry

Subtract

B +M .... B
36

RORB
Subtract Acmltr

Store Acmltrs

6

A+M-+A

-- 59-

ROLB
Rotate Right

OO-A-+A

Condo Code Reg.
H

·

•
•
•
• •
• •
• •
• •

••
• •
••

·• •

l

t t t t
t l l l
l l l t

• • ••
l t R •
l t R •
• • • •
• •• •
• • • •
• • ••
t
t
t
t

l
l
l
l

t

l l t
l t t

t t t
t t t
l t t
t t t
t l t
t t l
t t t

l l
l l

R

t t

R

R

•
•
•

l t t t

t t t t

• t t t t

t
t
• • t
• • t
• • t

• •

t
t
t
t
t

R
R

•
•

R R
R R
R R

The Condition Code Register notes are listed after Table 12.

$

HITACHI

567

HD68POtv07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - Table 11

Operations

Mnemonic

Direct

OP

-

# OP

BRA

Branch Never

BRN

21

Branch If Carry Clear

BCC

Branch If Carry Set

BCS

Branch If· Zero

BEQ

27

Branch If ~ Zero

BGE

2C

> Zero

BGT

2E

Branch If Higher

BHI

Branch If Higher or Same

BHS

Branch If

< Zero

Index

Relative

Branch Always

Branch If

Jump and Branch Instructions

20

-

# OP

-

# OP

-

Cond. Code Reg.

Implied

Extend

-

# OP

#

3

2

3

2

24

3

2

C=O

25

3

2

C=l

3

2

Z -I

3

2

N(±)V=O

3

2

Z + (N (±) V) = a

22

3

2

C+Z=O

24

3

2

BlE

2F

3

2

C=O
Z + (N (±) V) = 1

None

BlO

25

3

2

C=1

23

3

2

C+Z=1

20 3

2

Branch If Mi nus

BMI

2B

3

2

N(±)V=1
N~ 1

Branch If Not Equal Zero

BNE

26

3

2

N=O

Branch If Overflow Clear

BVC

28

V=O

Branch If Overflow Set

BVS

29

3 2
3· 2

Branch If Plus

BPl

2A 3

2

80 6

2

Branch If lower Or Same
Branch If

< Zero

Branch To Subroutine

BSR

Jump

JMP

Jump To Subroutine
No Operation

JSR
NOP

2

2

7E

3

3

AD 6

2

&0 6

3
01

2

Return From Interrupt

RTI
RTS

Software Interrupt

SWI

3B 10 1
39 5 1
3F 12 1

Wait For Interrupt

WAI

3E

9

•

•
•
•
•
•
•

• • • • • •

•
•
•
•
•
•

1

Return From Subroutine

...•• •• • •••

••••••
• •• •• •
• ••• ••

N=O
3

•
•
•
•
•

•
• ••
•••
• • • •
• • • • •
• • • • •
• • • ••
• • •• • •
• • •• • •
• • •• ••

V=1

6E
90 5

•
•
•
•
•
•

None

BlS
. BlT

Branch If Carry Set

5 4 3 2 1 a
H I N Z V C

Branch Test

~

•• •
•••
• • •
• ••
• ••
•• •
~

~

•
•
•
•
•
•

t t

1

Table 12 Condition Code Register Manipulation Instructions
Condo Code Reg.

Implied
Mnemonic

OP

#

Clear Carry

ClC

-

OC

2

1

Clear Interrupt Mask

Cli

OE

2

1

O-C
0-1

Clear Overflow

OA

2

1

a-v

Set Carry

ClV
SEC

00

2

1

l-C

Set Interrupt Mask

SEI

OF

2

1

1-1

Set Overflow

OB

2
2

1

I-V

Accumulator A - CCR

SEV
TAP

1

A- CCR

CCR - Accumulator A

TPA

2

1

CCR-A

06
07

LEGEND
OP Operation Code (Hexedecimal)
- Number of MPU Cycles
MSp Contants of memory location pointed to by Stack Pointer

# Number of Program Bytes
+
•
X

+
(±)

l\iI
-+

a

00

568

Boolean Operation

Arithmetic Plus
Arithmetic Minus
Boolean AND
Arithmetic Multiply
Boolean Inclusive OR
Boolean Exclusive OR
Complement of M
Transfer Into
Bit· Zero
Byte· Zero

•

CONDITION CODE SYMBOLS
H Half·carry from bit 3
I Interrupt mask
N Negative (sign bid
Z Zero (byte)
V Overflow. 2'5 complement
C Carry/Borrow from MSB
R Reset Always
S Set Always
~ Affected
• Not Affected

HITACHI

•

•

•
•
~

•• •• • •
• S • • • •
•• •• • •

The Condition Code Register notes are listed after Table 12.

Operations

•
•

5
H

4

3

I

N

2
Z

• • • •
• R • •
• • • •
• • •
• S • •
• • • •

·

1

a

V

C

• R
• •
R
•
• S
• •

•
~
• • • • • •
t

t

t

~

S

~

- - - - - - - - - - - - - - - - HD68P01 V07, HD68P01V07-1, HD68P01MO, HD68P01 M0-1

Table 13 Instruction Execution Times in E·Cycles
Addressing Mode

Addressing Mode

*'"

'5

E
E

ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS

.,

to
~

is

"0
"0

c:
~
x

UJ

I

.,x
"0
'"c:

.!!!

2
3

"0

•

•
•3

•
•4

•
•4

2
4
2

3

4
6
4
6

4
6
4
6

•2

5
3

•
•
•
•
•
•
•
•
•

•

•

•

•2

•
•
•
•
•
•
•
•
•
•
•

•
•
•
•

•2
•4
•
•
•2
•

•
•

•
•
•

•
•
•
•
•
•
3

•
•

._•

•
•

•
•
•
•

•
•
•
•
•
•3
•5
•
•
•
•3
•

•

"0

c.
E

•
•
•
•2

~

.,

'5'"
'E"
E

>
.;:;

'"
Q;

a:

•
•
•
•
•

•
•

•6 •6 32 •
•
• • • 33
• • •
• • • 33
• • • 3
• • •
• • • 33
•4 •4 •
• •
• • • 33
• • •
• • • 3
• c--~- r--.- ~....3_
f----• • • 33
• • • 3
• • • 3
• • •
• • • 63
• • • 3
• • •
• • •2 3
•
• •
• • 22 •
•6 •6 2 •
•
•4 •4 2 •
• •
6
6
2
•
6
6
•2 •
•6 •6 2 •
•
• • 33 •
•
•4 •4
•
•
6
6
•3 •
•
• •

INX
JMP
JSR
LDA
LDD
LDS
LDX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
f--=-=---RTI
RTS
SBA
SBC
SEC
SEI
~EV._

•
•
•2
3
3
3

•
•
•
•
•
•
•
2
•
•
•
•
•
•
•
•
•2
•
•
•
•
•
•
•2

STA
STD
STS
STX
SUB
4
SUBD
~~--- ~
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

~HITACHI

•
•
•
•
•
•
•
•

"0
"0

'"c:

"0

~

~

is

x

"0

UJ

'"c:

•

•3

•3

3
4
4
4

6
4
5
5
5
6

6
4
5
5
5
6

to

•5

•
•
•
•
•
•
•
3
•
•
•
•
•
•
•
•
•3
•
•
•
3
4
4
4
3

5

•
•
•
•
•
•
•
•
•

'x"

•6
•
•6
•

•6
•
•6
•
4
•
•
•
•6

•
•
•6

6

6

•
•

•
•
•4

•4
•
•
•
4

4

•

•
•

•
4

5
5
5

5
5
5

4
6

4
6

•
•
•
•
•6
•
•
•

•
•
•
•
•6

•
•
•

"0

.!!!

c.

'"

>
.;:;

'"

Q;

E

a:

3

•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

2
3
2
3
10
2
2

•3
4
4

5
2
2
10
5
2

•2
2
2

•
•
•
•
•
•
12
2
2
2
2
2
3
3
9

•
•
•
•
•

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

569

\

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - 1 - - - - - - - - - - - - - - - • SUMMARY OF CYCLE BY CYCLE OPERATION
Table 14 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected
results during debug to both software and hardware as the
program is executed. The information is categorized in groups
according to addressing mode and number of cycles per instruc-

tion. In general, instructions with the same addressing mode
and number of cycles execute in the same manner. Exceptions
are indicated in the table.
Note that during MeV reads of internal locations, the resultant value will not appear on the external Data Bus except in
Mode O. ,"High order" byte refers to the most Significant byte
of a 16-bit value.

Table 14 Cycle by Cycle Operation
Address Mode &
Instructions

Address Bus

Data Bus

IMMEDIATE
ADC
AOD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

2

1
'2

Op Code Address
Op Code Address + 1

1
1

OpCode
Operand Data

LOS
LOX
LDD

3

1
2
3

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

1
2
3
4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus FFFF

1
1
1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

3

1
2
3

Op Code Address
Op Code Address + 1
Address of Operand

1
1
1

Op Code
Address of Operand
Operand Data

STA

3

1
2
3

Op Code Address
Op Code Address + 1
Destination Address

1
1
0

Op Code
Destination Address
Data from Accumulator

LOS
LOX
LDD

4

1
2
3
4

Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

STS
STX
STD

4

1
2
3
4

Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1

1
1
0
0

Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

CPX
SUBD
ADDD

5

1
2
3
4

Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F

1
1
1
1
1

Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

JSR

5

Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1

1
1
1
0
0

Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

5
1
2
3
4

5

(Continued)

570

_HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-1
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

EXTENDED

3

1
2
3

Op Code Address
Op Code Address + 1
Op Code Address + 2

1
1
1

Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

4

1
2
3
4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand

1
1
1
1

Op Code
Address of Operand (H igh Order Byte)
Address of Operand (Low Order Byte)
Operand Data

STA

4

1
2
3
4

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address

1
1
1
0

Op Code
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumul ator

LOS
LOX
LDD

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
1
1

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

STS
STX
STD

5

1
2
3
4
5

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1

1
1
1
0
0

Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low

(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)

6

1
2
3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus F F F F
Address of Operand

1
1
1
1
1
0

Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

CPX
SUBD
ADDD

6

1
2
3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

JSR

6

1
2
3
4
5
6

Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1
0
0

Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

JMP

ADC
ADD
AND
BIT
CMP

ASL
ASR
CLR
COM
DEC
INC

EOR
LOA
ORA
SBC
SUB

LSR
NEG
ROL
ROR
TST*

• In the TST instruction, the line condition of the sixth cycle does the following: R/W = "High", AB

= FFFF, DB = Low Byte of Reset Vector,
(Continued)

•

HITACHI

571

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M O - l - - - - - - - - - - - - - - - Table 14 Cycle by CYcle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

INDEXED

3

JMP

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

4

3
4
4

STA

1
2

1
2

3
4

LOS
LOX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST *

6

1
2

3
4

5
6

CPX
SUBD
ADDD

6

JSR

6

1
2

3
4
5
6
1
2

3
4
5
6

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Offset
Low Byte of Restart Vector

Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset

1
1

,

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset

0

Op Code
Offset
Low Byte of Restart Vector
Operand Data

Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

,
,
,
1
1
1
1

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Op Code Add re~s
Op Code Address + 1
Address Bus F F F F
Index Register Plus Offset
Index Register Plus Offset + 1
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Register + Offset
Index Register + Offset + 1
,
Address Bus FFFF
Op Code Address
Op Code Address + ,
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1

1

1

1
1
1

0
0
1
1
1
1
1

0
1
1
1
1

,
1

,,
1

1

0
0

Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)

• In the TST instruction, the line condition of the sixth cycle does the following: R/Vil = "High", AB

= FFFF, DB = Low Byte of Reset

Vector.

(Continued)

572

_HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-l
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions

Data Bus

Address Bus

IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
ABX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

2

1
2

Op Code Address
Op Code Address + 1

1
1

Op Code
Op Code of Next Instruction

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

1
2
3
1
2
3
1
2
3
1
2
3
1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Irrelevant
Low Byte
Op Code
Irrelevant
Low Byte

Op Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer

1
1
1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

1
1
0
1
1
1

Op Code
Op Code of Next Instruction
Accumulator Data

Data
of Restart Vector

ASLD
LSRD

3

DES
INS

3

INX
DEX

3

PSHA
PSHB

3

TSX

3

TXS

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Op Code of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

Op Code
Irrelevant Data
Index Register (Low Order Byte I
Index RegIster (High Order Byte)

PULX

5

1
2
3
4

RTS

5

1
2
3
4

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
0
0
1
1
1
1
1
1
1
1
1

5

Stack Pointer + 2

1

5

Data
of Restart Vector

Op Code
Op Code of Next Instruction
Irrelevant Data

Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
OpCode
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(H igh Order Byte)
Address of Next Instruction
(Low Order Byte)
(Continued)

eHITACHI

573

HD68P01V07. HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M 0 - 1 - - - - - - - - - - - - - - - Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction
WAI

.*

Cycles
9

Cycle

Address Bus

RIW
Line

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Sta~k Pointer - 4
Stack Pointer - 5
Stack Pointer - 6

1
1
0
0
0
0
0
0
0

OpCode
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register

Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Op,Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

5

Stack Pointer + 2

1

6

Stack Pointer + 3

1

7

Stack Pointer + 4

1

8

Stack Pointer + 5

1

9

Stack Pointer + 6

1

10

Stack Pointer + 7

1

10
11

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer - 7
Vector Address FFFA (Hex)

1
1
0
0
0
0
0
0
0
1
1

12

Vector Address FFFB (Hell)

1

Dp Code
Irrelevant Data
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Op Code
Irrelevant Data
Irrelevant Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (Low Order Byte)
Op Code
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)

#

1
2
3
4
5
6
7

8
9

MUL

10

1
2
3
4
5
6
7

8
9

RTI

SWI

10

12

10
1
2
3
4

1

2
3
4
5
6
7

8
9

Data Bus

•• While the MCU is in the 'Wait" state, its bus state will appear as a .erie. of the MCU reads of an address which i. seven locations
lass then the original contents of the Stack Pointer. Co~trary to the HD6800, none of the ports are driven to the high impedence
state by a WAI instruction.

(Continued)

574

•

HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-l
Table 14 Cycle by Cycle Operation (Continued)
Address Mode &
Instruction

Address Bus

Data Bus

RELATIVE
BCC BHT BNE
BCS BLE BPL
BEQ BLS BRA BRN
BGE BLT BVC
BGT BMT BVS
BSR

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus F F F F

1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4
5

Op Code Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1

1
1
1
1

Op Code
Br anch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

6

0
0

When the op codes (4E. 5E) are used to execute. the MeV
continues to increase the program counter and it will not stop
until the Reset signal enters. These op codes are used to test the

•

SUMMARY OF UNDEFINED INSTRUCTIONS OPERATION
The MeV has 36 undefined instructions. When these arc
carried out. the contents of Register and Memory in MeV

LSI.

change at random.
Table 15 Op Codes Map
HD68POI MICROCOMPUTER INSTRUCTIONS
OP
CODE

ACC
A

ACC
B

IND

EXT

0100
4

0101

0110

0111

5

6

7

ACCA orSP

ACC80rX

IMM I OIR liND I EXT
1000 11001 11010 11011

0011

3

/

BLS PULB 1+1)

0100

4

LSRD (+1)

,../'

BCC

DES

0101

5

ASLD (+1)

,/""" BCS

TXS

0110

6

---TAP

TAB

BNE

PSHA

ROR

0111

7

TPA

TBA

BEQ

PSHB

ASR

1000

8

INX (+1)

,../'

BVC PUlX (+2)

1001

9

DEX (+1)

DAA

BVS

RTS (+2)

ROl

ADC

1010

A

ClV

/

BPl

ABX

DEC

ORA

1011

B

SEV

ABA

BMI

RTI (+7)

,../'

BGE PSHX (+1)

~
LO

0000

0

0001

1

0010

2

0000

0001 0010
1

2

3

SBA

BRA

TSX

CBA

BRN

INS

,../'

BHI PULA (+1)

0

NOP

0011

1100

C

ClC

1101

0

SEC

1110

E

Cli

V,../'

BGT

WAI (+6)

1111

F

SEI

,../'

BlE

SWI (+9)

112

112

213

113

BYTEICYClE

BlT MUl (+7)

--

8

1 9

1 A

·

LSR

I

SUBD (+2)

I EXT

C

1 OlE

1 F
0

CMP

1

SBC

2

1
AND

·

:

AD DO (+2)

5
6

LOA
,....,....- 1

STA

INC

·
·

BSR
(+4)

TST
JMP (-3)

ClR
216

316

I

I

CPX (+2)
JSR (+2)

I
I

lOS (+1)

• (+1)1

STS (+1)

212

I 213 I

214

I 314

;

7

STA

"'-----1
EOR

ADD

3
4

BIT

ASl

112

DIR liND

SUB

COM

112

I

1100 11101 11110 11111

1 8

NEG

_.. -

IMM

8
9
A

·
(+1~
·,
,

• (+111
212

B
lDD (+1)

C

STD (+1)

0

lOX (+1)

E

STX (+1)

F

I 213 I

214

I 314

c:2::J.

(NOTES) 1. Undefined Op codes are marked with
2. (
) indicate that the number in parenthesis must be added to the cvcla count for that instruction.
3. The instructions shown below are all 3 bvtes and are marked with ......
Immediate addressing mode of SUBD, CPX, lOS, ADDD, lDD and lOX instructions, and undefined op codas
(8F, CD, CF).
4. The Op code. (4E, 5E) are 1 by tel- cvcles instruction., and are marked with .......

_HITACHI

575

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M 0 - 1 - - - - - - - - - - - - - - - • PRECAUTIONS WHEN EMULATING
THE HD6801 FAMILY
The HD68POI series has 8k-byte EPROM space internally in
location $EOOO to $FFFF. Note the following when emulating
the HD6801S0 (2k-byte ROM on-chip) and the HD6801VO
(4k-byte ROM on-chip) with the HD68POI series.

(Note 1) In Tabl. 16, the following addr..... ar. ext.rnal like the ROM
on-chip typ.:
$FFFO to $FFFF in Mod. 1
$FFFE and $FFFF tres.t vector) ju.t aft.r r.leasing r..et in
Mode 0
(Note 2) In Mod. 0, data will not appear at Port 3 if acces.ing the
EPROM addr...... It i. different from the ROM on-chip type.

1) Mode 0, 1,6
Table 16 shows the address which may be used for the internal ROM space.

2) Mode 5, 7
,Table 18 shows the addresses which may be used for the
internal ROM space without any limitations.
Table 18

Table 16
HD6801SO
HD6801VO'

HD6801S0
HD6801VO

$F800 to $FFFF (2k bytes)
$FOOO to $FFFF (4k bytes)

Mode 0, 1 and 6 are expanded modes. When emulating the
HD6801S0 and the HD6801VO, the addresses shown in Table
17 should not be used externally because they are the internal
space in the EPROM on the package type. (See Fig. 26)

$F800 to $FFFF (2k bytes)
$FOOO to $FFFF (4k bytes)

3) Mode 2,3,4
In these modes, the internal ROM is disable. The EPROM
on the package type may be used equivalently as the ROM onchip type.

Table 17
HD6801S0
HD6801VO

$EOOO to $F7FF (6k bytes)
$EOOO to $EFFF (4k bytes)
(Example)

IROM On-chip Type I

EPROM on the Package Type

I

Memory

External
M.mory Space

®

4k-Byt. EPROM Spac.

Int.rnal
Addr.....

Figure 26

}

Memory Map Example when Emulating the HD6801S0
with the HD68POl MO and the 4k -Byte EPROM

Figure 26 shows an address map example when emulating the
HD6801S0 with the HD68POIMO and the 4k-byte EPROM in
mode 0, 1 and 6. In the emulation of expanded modes, the
addresses for memories and peripherals may be used externally
in space A, but not in space Band C which are internal ad-

576

Internal Addr•••es
Corresponding to the
ROM On-chip Typ.

•

dresses in the EPROM on the package type.
Figure 27 and 28 show the memory maps when emulating
the HD6801S0 and HD6801VO with the EPROM on the package type and the EPROM.

HITACHI

- - - - - - - - - - - - - - - - H D 6 8 P 0 1 V 0 7 , HD68P01V07-1, HD68P01MO, HD68P01MO-l
EPROM on the Package Type

HD68P01V07/-1

EPROM

HN482732A
Meu
Address

Memory Map

EPROM
Address

l~

External
Address

$EOOO,

,

HD68P01 MO/·1
HN482732A
Meu
Address

EPROM
Address

HN482764
Meu
Address

l

$EJOO[!J

EPROM
Address

!

®

I
I
I

I

:@
I

I

$17FF
$Fs:oolw'0l $1 800
Internal
ROM Address
$lFFF

Figure 27 Memory Map When Emulating the HD6801S0

EPROM on the Package Type

HN482732A

EPROM

Meu
Address

Memory Map
External
Address

.-

... --~
;
@
:
L.. ___ . J

r'HU©j:':
·""""'" 'I

}

HD68P01MO/·1

HD68P01V07/·1

EPROM
Address

~~

$EOOO,

I

I
I
I

I

I

Address

Meu
Address

EPROM
Address

$E;OO~

HN482764
Meu
Address

!

EPROM
Address

®

~

I

I

'

I

:@:

Unusable

HN482732A

I

I

I

I

I
I

I
I

I

I

I

I

@

Internal
ROM Address

Figure 28 Memory Map When Emulating the HD6801VO

•

HITACHI

577

HD68P01V07, HD68P01V07-1, HD68P01MO, H D 6 8 P 0 1 M 0 - 1 - - - - - - - - - - - - - - - •

PRECAUTION TO USE EPROM ON THE PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER

As this microcomputer takes a special packaging type with
pin sockets on its surface, pay attention to the followings;
(I) Do not apply higher electro-static voltage or serge voltage
etc. than maximum rating, or it may cause permanent
damage to the device.
(2) There are 28 pin sockets on its surface. When using 32k
Let the index-side four pins open.
When using 24 pin EPROM, match
its index and insert it into lower

24 pin sockets.

EPROM (24 pins), let the index-side four pins open.
(3) When assembling this LSI into user's system products as
well as the mask ROM type 8-bit single-chip microcompu,
ter, pay atte~tion to the followings to keep the good ohmic
contact between EPROM pins and pin sockets.
(a). When soldering on a printed circuit board, etc., keep its
condition under 250°C within 10 seconds. Over-time/
temperature may cause the bonding solder of socket
pins to meet and the sockets may drop.
(b) Keep out detergent or coater from the pin sockets at
aft-solder flux removal or board coating. The flux or
coater may make pin socket contactivity worse.
(c) Avoid the permanent use of this LSI under the evervibratory place and system.
(d) Repeating insertion/removal of EPROMs may damage
the contactivity of the pin sockets, so it is recommended to assemble new ones to your system products.
(4) In order to perform the normal operation at 1.25 MHz, it
is recommended to use the EPROM whose access time is
less than 300 ns.
Ask our sales agent about anything unclear.

578

•

HITACHI

HD68P05V07------------MCU (Microcomputer Unit)
The HD68P05V is the 8·bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, RAM, I/O and timer. It is
designed for the user who needs an economical microcomputer
with the proven capabilities of the HD6800-based instruction
set. Setting EPROM on the package, this MCU has the equiva·
lent function as the H06805U and HD6805V. HD68P05V07
uses HN482732A as EPROM. The fonowing are some of the hardware and software highlights of the MeU.
•
•
•
•
•
•
•
•
•
•
•

HARDWARE FEATURES
B-Bit Architecture
96 Bytes of RAM
Memory Mapped 1/0
Internal B-Bit Timer with 7·Bit Prescaler
Vectored Interrupts - External, Timer and Software
24 110 Ports + 8 Input Port
(8 Lines Directly Drive LEOs; 7 Bits Comparator Inputs)
On·Chip Clock Circuit
Master Reset
Complete Development System Support by Evaluation Kit
5 Vdc Single Supply

•
•
•
•
•
•
•
•
•
•
•
•
•
•

SOFTWARE FEATURES
Similar to H06800
Byte Efficient Instruction Set
Easy to Program
True Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/Flags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and 1/0
Compatible Instruction Set with H06805

HD68P05V07

(DC-40P)
• PIN ARRANGEMENT
HD68P05V07

o Vee
ONe
OADR,
OADRI
OADR.
OADR.
OADR3
OADR.
OADR,
OADRo
000
00,
00.
OVo.

VccO
Vee 0
Vee 0
ADR.O
ADR.O
ADRl1 0
VssO
ADR,oO
(;EO
0,0
0.0
0.0
O. 0
030

D. 20

(Top View)
Note) EPROM is not attached to the MCU.

•

HITACHI

579

-

- - - - - - ..

__ . - - - - - - -

HD68P05V07------------------------------------------------------------• BLOCK DIAGRAM

TIMER
Port B
110 Lines
Accumulator

PortA
110 Line.

A

8

CPU Control

Inde.
Register

X

Data
Dir
Reg

Port B
Reg

Condition

Port A
Reg

Data
Dir
Reg

5

Code
Register

cc

CPU

Port C
110 Lines

Stack
Pointer
'5

SP

Program

Counter
"High" PCH

Deta
Input Line.

o.
0,
0,
0,
0,-0,
0,
0,

8

ALU

Program
Counter
"Low" PCl

Deta
Input ~-~~-------1_-e~----_1~---~
Buffer

Addre ..
Output Lines
AOR o
ADR,

ADR,
ADR,
ADR,
ADR,

Addres.
Output~--~e_--------------~

Buffer

ADR.

ADR,

Address
Output Line.
ADR,
ADR,
ADRIII

ADR I •

a-

580

Address
Output
Buffer

•

HITACHI

Data Port C
Oir
Reg
Reg

Port 0
Input Lines

-------------------------------------------------------------HD68P05V07
• ABSOLUTE MAXIMUM RATINGS
Item
-----

Input Voltage (EXCEPT TIMER)
Input Voltage (TIMER)

.. -

- ----

Operating Temperature -_.
----Storage Temperature
•

.

-0.3- +7.0

V

Vin

-0.3 - +7.0
-0.3- +12.0

V

Top,

o -+70

V
·C

T stg

-55-+150

·C

Permanent LSI damage may occur .f maximum rattng'ii are exceeded. Normal operation should be under
recommen"ded operating conditions. If these conditions are exceeded. it could affect reliability of LSI.

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VCC=5.25V ± 0.5V. VSS=GND. Ta=O-+70·C. unless otherwise noted. I
Item
Input "High" Voltage

typ

max

-

Vee

V

3.0

Vee

V

Vee
0.8

V

0.8

V

II

2.0

RES

-0.3

-

INT

-0.3

-

All Other

XTAL (Crystal Mode)

V'H

V'L

-0.3

All Other
Power Dissipation

-0.3
Po
LVR

Low Voltage Recover
TIMER
Input Leak Current

min

-

INT

Input "Low" Voltage

-----

4.0

Test Condition

Symbol
RES

INT

I'L

-----

V,n=0.4V-V ee

XTAL (Crystal Model

•

Unit

Vee'

With respect to VSS (SYSTEM GNOI

(NOTE)

•
•

Value

Symbol

Supply Voltage

-20

Unit

V

0.6

V

0.8

V

-

700

mW

-

4.75

-

20

/JoA

V

-50

-

50

/JoA

-1200

-

0

/JoA

Unit

AC CHARACTERISTICS (Vcc=5.25V ± 0.5V. VSS=GND. Ta=0-+70·C. unless otherwise noted.1
min

typ

max

Clock Frequency

tel

0.4

-

4.0

MHz

Cycle Time

tcye

1.0

-

10

/Jos

friif Pulse Width

t'WL

t eve +
250

-

ns

RES Pulse Width

tRwL

tCYC

+

-

-

ns

TIMER Pulse Width

t TWL

tCYC

250

-

-

ns

Oscillation Start-up Time (Crystal Model

tose

-

-

100

ms

Delay Time Reset

tRHL

100

-

-

ms

35

pF

12.5

pF

Item

Input Capacitance

l
I

EXTAL
All Other

Symbol

Cin

•

Test Condition

-

250

CL =22pF±20%,
Rs=60n max.
External Cap. = 2.2/JoF
Vin=OV

HITACHI

-

+

581

HD68P05V07------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5 25V ± 0.5V, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)
typ
min
Symbol
Test Condition
max
Unit
Item
Port A
Output "High" Voltage

Port B

VOH

Port C
Port A and C
Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage

Port B
Port A, B,C,
and 0*
Port A

Input Leak Current

Input "High" Voltage
Input "Low" Voltage
Threshold Voltage
• Port 0 as digital Input
** Port 0 as analog input

..

Port B,C,
and 0
Port 0**
(Do - 0 6 )
Port 0**
(Do.. - 0 6 )
Port 0**(0,)

IOH = -loj./A

3.5

IOH = -100j./A

2.4

IOH = -200 j./A
IOH = -1 mA

2.4
1.5

IOH = -l00j./A

2.4

-

~_=1.6mA

~~3.2mA

VOL

IOL = 10 mA
VIH

2.0
-{).3

VIL

-500

Yin = O.BV
1---'-----Yin = 2V

IlL

-300

Yin =0_4V- V CC

VIH
----

V IL

--

VTH

- 20

-----------i-------=--

r--------+--i-

-

-

V
V
V
V
V

0.4

V

0.4

V

1.0

V

Vee

V

O.B

V
j./A

-

j./A

20

j./A

VTH+0.2

-

V

VTH-0.2

-

V

-

O.BXVce

V

TTL Equiv. (Port A and C)

TTL Equiv. (Port B)

Vee
2.4kl!

Ii = 3.2 mA

Ii = 1.6 mA

Test Pomt

Test Point

V,

Vi

40pF

(NOTE)

30pF

12 kn

24 kl!

1. Load capacitance includes the floating capacitance of tt.e probe and the jig etc.
2. All diodes are IS2074 ®or equivalent.

Figure 1 Bus Timing Test Loads
• SIGNAL DESCRIPTION

inputs.

The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.

• TIMER

• Vee and Vss
Power is supplied to the MCU using these two pins. Vee
is +5.25V ±O.5V. Vss is the ground connection.

This pin allows an external input to be used to decrement
the internal timer circuitry. Refer to TIMER for additional
information about the timer circuitry.

•

INT

This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS
for additional information.

•

• RES
This pin allows resetting of the MCU. Refer to RESETS
for additional information.

XTAL and EXTAL

These pins provide connections for the on·chip clock circuit.
A crystal (AT cut, 4 MHz maximum) can be.connected to these
pins to provide a system clock with various stability. Refer to
INTERNAL OSCILLATOR for recommendations about these

582

•

• NUM

This pin is not for user application and should be connected
to VSS.

HITACHI

---------------------------------------------------------------HD68P05V07
• Input/Output Lines (Ao - A" Bo - B" Co - C,)
These 24 lines are arranged into three 8-bit ports (A, Band
C). A1llines are programmable as either inputs or outputs under
software control of the Data Direction Register (DDR). Refer to
INPUT/OUTPUT for additional information.
• Input Lines (Do - 0,)
These are 8-bit input lines, which has two functions. Firstly,
these are TTL compatible inputs, in location $003. The other
function of them is 7 bits comparator in location $007. Refer to
INPUT for more detail.
• REGISTERS
The MCU has five registers available to the programmer.
They are shown in Figure 2 and are explained in the following
paragraphs.

I Accumulator

A.

o

11

I
----'I

Index Register

L....-------'o

L:-______P_c_ _ _ _

,
mIT

11

5 4

Program Counter

0

LI°:JI..;°.JI..;0.JI..;o_IL°..JI,-'LI_'LI_ _5:.."_----'1
N

Z

S,,,k Po,",..

C

~

-

- -

-

--- -

•

Zero
NegatIVe

- - - Interrupt Mask

------~

Figure 2

Condition Code Register

Carry/Borrow

HaltCarry

Programming Model

Ac:c:umulator (A)

The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
• Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode. It contains an 8-bit address that may be added
to an offset value to create an effective address. The index
register can also be used for limited calculations and data
manipulations when using read/modify/write instructions. When
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed.

• Stack Pointer ISP)
The stack pointer is a l3-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set tQ location $007F and is decremented as data is being
pushed onto the stack and incremented as data is being pulled
from the stack. The six most significant bits of the stack pointer
are permanently set to 00000011. During an MCV reset or the
reset stack pointer (RSP) instruction, the stack pointer is set
to location $007F. Subroutines and interrupts may be nested
down to location $0061 which allows the programmer to use up
to IS levels of subroutine calls.
• Condition Code Register (CC)
The condition code register is a 5-bit register in which each
bit is used to indicate or flag the r~sults of the instruction just
executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained in the following
paragraphs.
Half Carry (H)
Used during arithmetic operations (ADD and ADC) to
indicate that a carry occurred between bits 3 and 4.
Interru pt (I)
This bit is set to mask the timer and external interrupt (iNT).
If an interrupt occurs while this bit is set it is latched and will be
processed as soon as the interrupt bit is reset.
Negative (N)
Used to indicate that the result of the last arithmetic, logical
or data manipulation was negative (bit 7 in result equal to a
logical one).
Zero IZ)
Used to indicate that the result of the last arithmetic, logical
or data rna nipula tion was zero.
Carry/Borrow IC)
Used 10 mdicate that a carry or borrow out of the arithmetic
logic unit (ALU) occurred during the last arithmetic operation.
This bit is also affected dunng bit test and branch instructions,
shifts, and rotates.
• TIMER
The MCV timer circuitry is shown in Figure 3. The 8-bil
counter, the Timer Data Register (TOR), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the timer reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register (TCR) is
set. The MCV responds to this in terrpt by saving the present
CPU state on tlie stack, fetching the timer interrupt vector from
locations $OFF8 and $OFF9 and executing the interrupt routine. The timer interrupt can be masked by setting the timer

TIMER Input Pin
TCR bit4
Timer Control Register

(TCR)

<1>, (Internal) - - - - . . . . . , - ,
TCR bit 5

Prescaler
) Address Bits
Clock Input

a·bit Counter
Timer Data Register (TOR)

Timer Interrupt Req.
Timer Interrupt Mask
) Clock Input
Source Option

Figure 3

Timer Block Diagram

•

HITACHI

583

HD68P05V07------------------------------------------------------------interrupt mask bit (bit 6) in the TCR. The interrupt bit (I bit) in
the Condition Code Register also prevents a timer interrupt
from being processed.
The clock input to the timer can be from an external source
applied to the TIMER input pin or it can be the internal t/l2
signal. When the t/l2 signal is used as the source, it can be gated
by an input applied to the TIMER input pin allowing the
user to easily perform pulse-width measurements. A prescaler
option can be applied to the clock input that extends the timing
interval up to a maximum of 128 counts before decrementing
the counter (TOR). The timer continues to count past zero,
falling through to $FF from zero and then continuing the
count. Thus, the counter (TOR) can be read at any time by
reading the TOR. This allows a program to determine the length
of time since a time interrupt has occurred and not disturb
the counting process.
The TOR is 8-bit read/write register in location $008. At
power-up or reset, the TOR and the prescaler are initialize with
all logical ones.
The timer interrupt request bit (bit 7 of the TCR) is set by
hardware when timer count reaches zero, and is cleared by program or by hardware reset. The bit 6 of the TCR is writable by
program. Both of those bits can be read by MPV.
The bit 5 and bit 4 of the TCR select a clock input source.
The selections are shown in Table I. Bit 3 is not used. Bit 2, bit
I and bit 0 are used to select the prescaler dividing ratio, shown
in Table 2. At reset, an internal clock by the TIMER input pin
is selected as clock source and "+ I mode" is selected as the
prescaler dividing ratio.
(NOTE) If the MCV Timer is not used, the TIMER input pin
must be grounded.

• RESETS

The MCV can be reset two ways; by initial power-up and
by the external reset input (RES), see Figure 4. All the I/O
ports are initialized to input mode (DORs are cleared) during
reset.
Ouring power-up, a minimum 100 milliseconds is needed
before allowing the RES inpu t to go "High".
This time allows the internal crystal oscillator to stabilize.
Connecting a capacitor to the RES input, as shown in Figure
5, typically provides sufficient delay.

RES Pm

Internal _ _ _ _ _ _ _ _ _ _....l
Reset

Figure4 PowerandFiETiming

2

Part of

HD68P05V

MCU

Figure 5 Power Up Reset Delay Circuit

Table 1 Selection of Clock Input Source
•

Timer Control
Register (TC R)

Clock Input Source

Bit 5

Bit 4

0

0

0

1

1

0

1

1

t/l2

(Internal Clock)

--------_¥'

(Note 2)

INTERNAL OSCILLATOR

The internal oscillator circuit is designed to require a minimum of external components. The use of a crystal (AT cut,
4 MHz max) is sufficient to drive the internal oscillator with
various stability. The different connection methods are shown
in Figure 6. Crystal specifications are given in Figure 7.

TIMER Input Pin

6 XTAL

(NOTE) 1. 0.0 and 1.0 are not usable In mask option of 6805

4~a~z c::J

2. The TI M ER input pin must be tied to V ce. for

uncontrolled C/J" clock.

5 EXTAL HD68P05V

MCU
22PF'20%T

Table 2 Selection of Prescaler Dividing Ratio
Timer Control
Register (TCR)

Prescaler Dividing Ratio
Crystal

Bit 2

Bit 1

Bit 0

0
0
0
0

0
0

0

Prescaler + 1

1

Prescaler .;. 2

1

0

Prescaler .;. 4

1

1

1

0

0

Prescaler .;. 8
Prescaler .;. 16

1

0

1

Prescaler + 32

1

1

0

Prescaler.;. 64

1

1

1

Prescaler .;. 1 28

6 XTAL
External

Clock

HD68P05V

MCU

External Clock

Figure 6

584

5 EXTAL

Input

•

HITACHI

Internal Oscillator

-------------------------------------------------------------HD68P05V07
only the pr<~gram counter (pCH, PeL) contents to be pushed
onto the stack. This interrupt bit (I) in the condition code register is set, the address of the interrupt routine is obtained from
the appropriate interrupt vector addrdss, and the interrupt routine is executed. The interrupt service routines normally end
with a return from interrupt (RTI) instruction which allows the
MCU to resume processing of the program prior to the interrupt.
Table 3 provides a listing of the interrupts, their priority, and
the vector address that contain the starting address of the
appropriate interrupt routine.
A flowchart of the interrupt processing sequence is given
in Fig. 9.

C,

XTAl~~EXTAl
6

~W

5

AT - Cut Parallel Resonance Crystal
Cn = 1 pF max.
1·4 MHz
As· 6011 max.

6

Figure 7 Crystal Parameters
n-4

• INTERRUPTS
The MCU can be interrupted three different ways: through
the external interrupt (INT) input pin, the internal timer interrupt request, and a software interrupt instruction (SWI). When
any interrupt occurs, processing is suspended, the present CPU
state is pushed onto the stack in the order shown in Fig. 8, the
interrupt bit (I) in the Condition Code Register is set, the address of the interrupt routine is obtained from the appropriate
interrupt vector address, and the interrupt routine is executed.
Since the stack pointer decrements during pushes, the low order
byte (PCL) of the program counter is stacked first; then the
high order five bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer increments
when it pulls data from the stack. A subroutine call will canse

1

5

4

, ,1

3

2

0

ConditiOn

Pull

n +1

Code Register

n-3

Accumulator

n+2

n-2

I ndex Register

n+3

n-'

,,,

,I

n+4

PCW

n+5

PCl"

Push
• For subroutine calls, only PCH and pel are stacked.

Figure 8 Interrupt Stacking Order
Table 3 Interrupt Priorities
Interru
RES
SWI
INT
TIMER

Priority
1

2
3
4

Vector Address
SOFFE and SOFFF
SOFFC and SOFFD
SOFFA and SOFFB
$OFF8 and $OFF9

1 ~I
7F -SP
O_COR's
CLR iNT Logic
FF _Timer

IF .... Presc.ler
7F _TeR

SWI

Figure 9 Interrupt Processing Flowchart

•

HITACHI

585

HD68P05V07------------------------------------------------------------• INPUT/OUTPUT

There are 24 input/output pins. All pins are programmable
as either inputs or outputs under software control of the cor·
responding Data Direction Register (DDR). When programmed
as outputs, the latched output data is readable as input data,
regardless of the logic levels at the output pin due to output

loading (see Fig. 10). When Port B is programmed for outputs,
it is capable of sinking lOrnA on each pin (VOL = IV max).
All input/output lines are TTL compatible as both inputs and
outputs. Port A is CMOS compatible as outputs, and Port Band
C are CMOS compatible as inputs. Figure I I provides some
examples of port connections.

Data
Direction

Output

Register

Data Sit

Output
State

Input to
MCU

0
1
3·State

Pin

Bit

1
1
0

0
1

,

0
1

Figure 10 Typical Port I/O Circuitry
B.

A,

o

•

o
o

Port A

Port B

o

o
o

•oo
o

A,

B,

Port B Programmed as output Is) , driving Darlington base directly.
Ib)

Port A Programmed as output Is). driving CMOS and TTL Load directly.
la)

+V

+V

R

R

c.

-

Port B

PortC

o
o
o
o

.

J - - - - -........ CMOS Inverter

o

10mAmax

C,

B,

Port C Programmed as output Is), driving CMOS loads, using external
resistors.
Id)

Port B Programmed as outputls), driving LED(s) directly".

PUll'UD

lei

Figure 11 Typical Port Connections

•

INPUT

Port D can be used as either 8 TTL compatible inputs or I
threshold input and 7 analog inputs pins. Fig. 12 (a) shows the
construction of port D. The Port D register at location $003
stores TTL compatible inputs, and those in location $007 store
the result of compariso!) Do to D6 inputs with D7 threshold
input. Port D has not only the conventional function as inputs
but also voltage-comparison function. Applying the latter, can
easily check that 7 analog input electric potential max. exceeds
the limit with the construction shown in Fig. 12 (b). Also, using
one output pin of MeV, after external capacity is discharged
at the preset state, charge the CR circuit of long enough time
eonstan t, apply the charging curve to the D7 pin. The construe·
tion described above is shown in Fig. 12 (c). The compared
result of Do to D6 is regularly monitored, which gives the
analog input electric potential applied to Do to D6 pins from
inverted time. This method enables 7 inputs to be converted
from analog to digital. Furthermore, combination of two functions gives 3 level voltages from Do to D6. Fig. 12 (d) provides

586

•

the example when VTH is set to 3.SV.
• BIT MANIPULATION
The MCV has the ability to set or clear any single random
access memory or input/output bit (except the data direction
registers) with a single instruction (BSET, BCLR). Any bit in
the page zero read only memory can be tested, using the BRSET
and BRCLR instructions, and the program branches as a result
of its state. This capability to work with any bit in RAM, ROM
or I/O allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in Figure 13
illustrates the usefulness of the bit manipUlation and test
instructions. Assume that bit 0 of port A is connecte-d to a zero
crossing detector circuit and that bit I of port A is connected to
the trigger of a TRIAC which power the controlled hardware.
This program, which uses only seven ROM locations, ,provides turn-on of the TRIAC within 14 microseconds of the zero
orossing. The timer could also be incorporated to provide turn·
on at some later time which would permit pulse·width modUla·
tion of the controlled power.

HITACHI

-------------------------------------------------------------HD68P05V07
$003 Read
Internal Bus

IBitO - Bit6)

$003 Read

Input Port 10,)

Internal Bus

IBit 7)
la) The logic configuration of Port 0

POrt

r----

c.

C

0,

Reference Level

O.

Analog Input 6

0, _ _ _ _ _ _._ _ _ _ _ _ _ _ _ _ _ _ _.....J

Port

0

Port

\
0,

o

O.

I-::---Analoq Illput 6

o.

r"::"'-'-- Analog Input 0

Analog Input 0

c,

~

o,~

Ic) Application to AID·convertor

(b) Seven analog inputs and a reference level input of Port 0

0,
VTH 1= 3.5V)

O.

3 Levels Input 6

Port

0

\
0,

1$007)
1$003)
\i'~!!10
0
0
-py - O.8V..
0
1
2.0V - 3.3V
-----------------r-.--1
1
3.7V- VcC

3 Levels Input 0

Id) Application to 3 levels input

Figure 12 Configuration and Appl ication of Port 0

•

587

HITACHI

- _.. _------

HD68P05V07-----------------------------------------------------------

SELF 1

··••
·•

BRClR 0, PORT A, SELF 1
BSET I, PORT A
BClR I, PORT A

··
·

Figure 13 Bit Manipulation Example
• ADDRESSING MODES
The MCU has ten addressing modes available for use by the
programmer. They are explained and illustrated briefly in the
following paragraphs.
• Immediate
Refer to Figure 14. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte following the
opcode.
• Direct
Refer to Figure IS. In direct addressing. the address of the
operand is contained in the second byte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of this
efficient memory addressing mode.
• Extended
Refer to Figure 16. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes following the opcode. Extended addressing instructions are three bytes long.
• Relative
Refer to Figure 17. The relative addressing mode applies only
to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA=(pc)+2+Rel. Rei is the contents
of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken Rel=O, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 of the present instruction. These
instructions are two bytes long.
• Indexed (No Offset)
Refer to Figure 18. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and'their EA is the contents of the index register.
• Indexed (S-bit Offset)
Refer to Figure 19. The EA is calculated by adding the
contents of the byte following the opcode to the contents of
the index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.
'
• Indexad (16-bit Offsetl
Refer to Figure 20. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are three
bytes long.

588

$

• Bit Set/Clear
Refer to Figure 21. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch
Refer to Figure 22. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($OO-$FF) and branch to any location relative to the PC. The
byte to be tested is addressed by the byte following the opcode.
The individual bit within that byte to be tested is addressed by
the lower three bits of the opcode. The third byte is the relative
address to be added to the program counter if the branch condition is met. These instructions are three bytes long. The value of
the bit tested is written to the carry bit in the condition code
register.
• Implied
Refer to Figure 23. The implied mode of addressing has no
EA. All the information necessary io execute an instruction is
contained in the opcode. Direct operations on the accumulator
and the index register are included in this mode of addressing.
In addition, control instructions such as SWI, RTI belbng to this
group. All implied addressing instructions are one byte long.
• INSTRUCTION SET
The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/modify/
write. branch, bit manipulation, and control. The following
paragraphs briefly explain each type. All the instructions within
a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand is
either the accumulator or the index register. The other operand
is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR)
instructions have no register operand. Refer to Table 4.
• Read/Modify/Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back
to memory or to the register. The test for negative or zero
(TST) instruction is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table
5.
• Branch Instructions
The branch instructions cause a branch from the program
when a certain condition is met. Refer to Table 6.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other group
performs the bit test and branch operations. Refer to Table 7.
• Control Instructions
The control instructions control the MCU operations during
program execution. Refer to Table 8.
• Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 9.
• Opcode Map
Table lOis an opcode map for the instructions used on the
MeU.

HITACHI

----------------------------------------------------------------HD68P05V07
lEA

I

Melorv
i

I

I

i

I
I

I

I

8
A6

05BF

F8

/

~

Adder

A
F8
IndrlliH

I

I

Stack Point

I
I

PROG LOA #$F8 05BE

I

t

I
I

I
I

I

I
Prog Count

I
I

05CO
CC

I
,

I

~
I

I

,I

Figure 14

t

lEA

Memory
I

I

I

I
I
I
I
I

I
I

I
I

CAT

FCB

32

Immediate Addressing Example

I

/

1
Adder

20

004B

I

004B

~
o!o

A
20

1

Index Reg

I

I

PROG

LOA

CAT

0520

B6

052E

4B

I
I

Stack Point

I
I

Prog Count

052F

I
I
I

CC

~
I

I

I

I

I

I

i

I

I

Figure 15 Direct Addressing Example

•

HITACHI

589

HD68P05V07-------------------------------------------------------------

+

Memory

0000
A
40
PROG

LOA

CAT

Index Reg

Stack Point

Prog Count
CAT

FCB

040C

64

CC

Figure 16 Extended Addressing Example

lEA
Memory

i

i

I

I

§

i

I
BEQ

PROG2

I

04A7

27

04A8

18

I

~

i
i

I

PROG

L

04Cl

/
I

Adder

i
OR

r

'"
I

oot

A

I
Index Reg

I
Stack Point

I

I
I
I

Prog Count

y

I

04Cl

JI

CC

I

§

I

i

Figure 17 Relative Addressing Example

590

z

J

i

.,HITACHI

I

-------------------------------------------------------------HD68P05V07
lEA

I

Melorv
i

i

I
I
I

i
I
I

/

I

I

TABL

t

i

I

~

Adder

A

.,

oJoo

4C

FCC I U 100BB

I

00B8

4C

49

I

Index Reg

B8

I

Stack Point

PROG

LOA

X
Prog Count

05F5
CC

Figure 18 Indexed (No Offset) Addressing Example

J

Memory
I

I

I

I

I

TABL

r

I

FCB

"BF

0089

BF

FCB

.. 86

008A

86

FC8

~

DB

008B

DB

FCB

"CF

008C

CF
I

/

1

EA

I

008C

t
Adder

~
J1\

I
I
I

I

A

"

CF
Index Reg

03

I
I

Stack Pomt

PROG

LOA

""":;:1 : 1

Prog Count

0750
CC

I

I

§
Figure 19 Indexed (8-Bit Offset) Addressing Example

•

HITACHI

591

HD68P05V07---------------------------------------------------------lEA

MeLv

,,

i
I

I

I

~
~

,
PROG

LOA TABL. X 0692
0693
0694

L

I

0780

t
Adder

I

""
I
I

IJ

7E

#BF

FCB

#86

077E
077F

86

FCB

#OB

0780

DB

FCB

#CF

07Bl

CF

DB

02

0695

I

EA
0001

Memory

EQU

BF

0001

A

Index Reg
PROG BCLR 6. PORT B

10

05BF

Stack POint

0~0~-----0-1----~

I
Prog Count
0591

I

CC

~
I
I

I
I

Figure 21

592

J

I
I
I

I
Prog Count

Figure 20 Indexed (16-Bit Offset) Addressing Example

PORTB

I

Index Reg

CC

I

BF

FCB

A

Stack Point

07

,
TABL

L

Bit Set/Clear Addressing Example

•

HITACHI

HD68P05V07

PORT C

Eau

0002

2

r-------i
FO

A

Index Reg

0000

Stack POint

PROG BRCLR 2. PORT C. PROG 2

r------~

0574
05
0575 r---"';;0=-2---1

Prog Count

0576t---~1=-D---Hr-----

0594
CC

I

~
I

Figure 22 B'It Test and Branch Add ressmg
. Example

EA
Memory

I
I
I

~

PROG

TAX

II

I

I

I

A

'~As

05BB
CC

I

I

~
I

I
I

I
I

I

I

!

I

Figure 23 Imp Iied Addressing Example

•

HITACHI

593

HD68P05V07------------------------------------------------------------Table 4 Register/Memory Instructions
Addressing Modes

1---""
Function

Mnemonic

Immediate

Extended

Direct

Op
Op
Op
#
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code Bytes

#
Cycles

Indexed

Indexed

Indexed

(NoOllse,)

(8"8i,Ollse')

(16"8i,Ollse')

Op
Op
#
Op
#
#
#
#
#
Code Bytes CVcles Code Bytes Cycles Code Bytes Cycles

Load A from Memory

LOA

A6

2

2

B6

2

4

C6

F6

1

4

E6

2

5

06

J

6

LOX

AE

2

2

BE

2

4

CE

J"
J

5

load X from Memory

5

FE

1

4

EE

2

5

DE

J

6

-

--

B7

"--

2

J

6

F7

1

5

E7

2

6

07

J

7

BF

2

t-~-

C7

5

CF

J

6

FF

1

5

EF

2

6

OF

J

7

BB

2

4

CB

J

5

FB

1

4

EB

2

5

DB

J

6

B9

2

4

C9

J

5

F9

1

4

E9

2

5

09

J

6

2

4

CO

J

5

FO

1

4

EO

2

5

DO

J

6

1

4

E2

2

5

02

3

6

1

4

E4

2

5

04

3

6

Store A

In

Memory

Store X

In

Memory

STA
t - - " - - r - ---STX

Add Memory to A

ADD

AB

2

2

Add Memory and
Carry to A

AOC

A9

2

2

Subtract Memory

SUB __

2

2

--

Subtract Memory from

SBC

A with Borrow
A~O

Memory to A

r-~
A2

AND

----- ~

-2

2

2

- " - - '-~-"

BO
B2

2

4

C2

J

5

F2

B4

2

4

C4

3

5

F4

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

OA

3

6

ECR

A8

2

2

BB

2

•

C8

3

5

F8

1

4

E8

2

5

08

3

6

CMP

Al

2

2

Bl

2

4

Cl

3

5

Fl

1

4

El

2

5

01

3

6

CPX

A3

2

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

03

3

6

BIt Test Memory with A
(Logical Compare)

BIT

A5

2

2

B5

2

4

C5

3

5

F5

1

4

E5

2

5

05

3

6

Jump UnCOnditional

JMP

-

2

3

CC

J

4

FC

1

3

EC

2

4

DC

J

5

JSR

-

8C

Jump to Subroutine

-

BO

2

7

CD

3

8

FO

1

7

ED

2

8

DO

J

9

OR Memory with A

Exclusive OR Memory
with A

Arithmetic Compare A
with Memory
ArithmetIC Compare X

with Memory

---

Table 5 Read/Modify/Write Instructions
-Function

---------Implied (A)

Mnemonic

-Op
Code

594

~-Addre"ing Mode,
.--~--~--~

#

Implied (XI

#

Op

Bytes Cycle, Code

Indexed
(No Offset)

Direct

Op
#
#
Byte, Cycle, Code

Op
#
#
Bytes Cycle, Code

Indexed
(S·Bit Offset)

Op
#
#
Bytes Cyc(e, Code

#

#

Bytes Cycle,

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

7

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

Negate
(2', Complement)

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

7

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

Logical Shift Right

LSR

44

1

4

54

1

4

34

2

6

74

1

6

64

2

7

Arithmetic Shift Right

ASR

47

1

4

57

1

4

37

2

6

77

1

6

67

2

7

Arithmetic Shift Left

ASL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

Test for Negative or
Z.o

TST

40

1

4

50

1

4

3D

2

6

70

1

6

60

2

7

•

HITACHI

-------------------------------------------------------------HD68P05V07
Table 6 Branch Instructions
Relative Addressing Mode
Function

Mnemonic

Op
Code

#

#

Bytes

Cycles

Branch Always

BRA

20

2

4

Branch Never

BRN

21

2

4

Branch IF Higher

BHI

22

2

4

Branch I F Lower or Same
Branch I F Carry Clear

BLS

23

2

4

BCC

24

2

4

(Branch IF Higher or Same)

(BHS)

24

2

4

Branch I F Carry Set

BCS

25

2

4

(Branch IF Lower)

(BLO)

25

2

4

Branch I F Not Equal

BNE

26

2

4

Branch I F Equal

BEQ

27

2

4

Branch I F Half Carry Clear

BHCC

28

2

Branch I F Half Carry Set

BHCS

29

2

Branch I F Plus

BPL

2A

2

Branch IF Minus

BMI

2B

2

Branch I F Interrupt Mask Bit is Clear

BMC

2C

2

Branch I F Interrupt Mask Bit is Set

BMS

20

2

Branch I F Interrupt Line is Low

BIL

2E

2

4
4
4
4
4
4
4

Branch IF Interrupt Line is High

BIH

2F

2

4

Branch to Subroutine

BSR

AD

2

8

Table 7 Bit Manipulation Instructions
Addressing Modes
Function

Bit Set/Clear

Mnemonic

Bit Test and Branch

#

#

Bytes

Cycles

-

-

Op
Code

Op
Code

#

#

Bytes

Cycles

-

2·n

3

10

-

01+2·n

3

10

-

-

-

Branch I F Bit n is set

BRSET n (n-O ..... 7)

Branch I F Bit n is clear

BRCLR n (n=O ..... 7)

Set Bit n

BSET n (n=O ..... 7)

10+2·n

2

7

Clear bit n

BCLR n (n=O ..... 7)

11+2·n

2

7

-

Table 8 Control Instructions
Implied
Function

Mnemonic

Op
Code

#

#

Bytes

Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

CLC

98

1

2
2

Set Interrupt Mask Bit

SEI

9B

1

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP

9C

1

2

No-Operation

NOP

90

1

2

•

HITACHI

595

HD68P05V07---------------------------------------------------------Table 9 Instruction Set

Mnemonic
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC

Imme·
Implied diate

Ex·
Direct tended

x
x

x

x

x
x
x

x
x

x
x
x

Addressi n9 Modes
Bit
Indexed Indexed
Re· Indexed
(No
Setl
lative Offset)
(8 Bits) (16 Bits) Clear
x
x
x
x
x
x
x
x
x
x
x
x

Condition Code
Bit
Test & H
Branch

..
.
• •
• •
N

z

C

/\

/\

/\

/\

/\

/\
/\

/\
/\
/\
/\

/\

/\

/\

/\
• • /\
•• •• •• •• ••

x

x

x
x
x
x

•
•
•

•
•
•

•
•
•

•
•
•

•
•
•

__~B~H~C~S___+-----,----_1----_1----~r__x--~-------r-----+------+----~-----+-.-+-.-+-.-+-·~r·~
___B_H_I_____+----_1~----r_----+_----_r--X-----+I------1_----_+-------r_----r_----_r.--r_·_+-·_+-·--r·-BHS
x
• • • • •
--------_+----_1----_1----_1----~I___---- I-------+----~------_+----+_----_+--r__+--r___+BIH
x
• • • • •
-----'::..:.:..:--t__---f------ ----- ;-------1--- ---- ---------- -----+-----+---+---+-=----+--=---~_+_=__t-=-Bil
x
• •• ~
BIT
x
x
x
---- -- ---x--- ---~--x
• • /\ i /\ •
BlO
BlS

x
x

~~----r---~---_+---~------~-~--------

-i

• • • i.

•

•

•

•

•

• • • •

------+----4------+_+_+~---~

•

•

--------_+----_1----_1---~----_+----+----+-----~r_----_r-----+-----~--r__r--r__+-

-----'B~M~C~_t__-~----_+_-~--_+_-x_+

BMI
--------t-----,;---BMS
BNE

------- ~--r----

--t-------t-------r--i-------'

x

:-I__:+-:_+-:--r:-•

----------r_----1_-----~----_+------r_--_1------_r-------r___-

• • • •

___B_P_l_____+----_1;------r_----+_----_r--x--~-------------- ~-------I__----r_----~-·--I__·+-·_+-·--r·-BRA
x
• • • • •

--~B~R-N-----t-----1~----t-----+------+--x---t------------r-------I------r-----~-.--I__.+-.-+-.--r.--

BRClR

x

I

BRSH

••••

/\

•

•

----t-- ---- t----I--------1r----+---x---+.--t---.-+-.+-.-+-/\--

BSET

I

--

----t-------+=

x

•

•

•

-----1 - - - --x-- - f-----f------+-------+----+--f--+--+--r_B~_~_______ 1----__ -- ---- -- --- ---- -- --------t-----+-----+----+----+.=--if--.=--t-'.=--t-'.'--j~.=-

__x___ ~----_+----+_----4_-----+_------- ___ ---_+------+_--_1------+-._+-.__+-._+-._1~0,-

ClC

~_I__-~-- _____ _

ClR
CMP
COM
CPX
DEC

x
x
x
x
x

______

x
x
x
x
x

______

__ _____

x
x
x
x
x

x
x

x
x
x
x
x

x
x

•

0

•

•
•
•
•
•

•
•
•
•
•

0 1
/\ /\
/\ /\
/\ /\
/\ /\

•

•

•
/\
1
/\
•

___E_O_R_____ t--______+-_x~_+--~x=-+--'x~-t----+---'x=-_+--~x=-+---'x=-_+----_+------t-._+-'.-+~/\___1~/\~~.-INC
x
x
x
x
• • /\ /\ •
JMP
x
x
x
x
x
• • • • •
JSR
x
x
x
x
x
• • • • •
x
x
x
x
x
x
• • /\ /\ •
lOA
lOX
x
x
x
x
x
x
• • /\ /\ •
(to be continued)
Condition Code Symbols:
H
I
N
Z

596

Half Carry (From Bit 31
Interrupt Mask
Negative (Sign Bid
Zero

C
/\
•

Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected

_HITACHI

-------------------------------------------------------------HD68P05V07
Table 9 Instruction Set
Addressing Modes
Mnemonic

Implied

Immediate

Direct

LSL

x

x

LSR

x

x

NEG

x

x

NOP

x

ORA
ROL

x

RTI

x
.. x
x
x

RTS

x

--

ROR
RSP

SEC

----

x
x

x
x

x
-- --

x

x
x

x
x
x

x

x

x

x

x

x

x
x

STX

x

SUB
TAX

x
x

TST

x

TXA

x

Bit
Test &
Branch

H

I

N

Z

•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
?
•
•
•
1
•
•
•
1
•
•
•

1\

1\

1\

0

1\

1\

1\

1\
1\

?

STA

SWI

x
x
x

Relative

Bit
Set!
Clear

•

x

SBC
SEI

---

Extended

Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x

----

Condition Code Symbols.
H
Hall Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

x
x
x

x
x

x
-.- f-x
x
x
x

x

x

-----

x

x

x

x
x

x

•
•

•
•
•
•
•
•
•
•
•

C

1\
•

?

•

C

• • •
1\ 1\ •
1\

1\

1\

1\

1\
1\

• • •
?
?
?
• • •
1\ 1\ 1\
• • 1
• • •
1\ 1\ •
1\ 1\ •
1\ 1\ 1\
• • •
• • •
1\ 1\ •
• • •

Carry/Borrow
Test and Set if True Cleared Otherwise
Not Affected
Load CC Register From Stack
I

HITACHI

597

HD68P05V07---------------------------------------------------------Table 10

0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F

Bit Manipulation
Branch
Test &
Setl
Rei
Branch
Clear
1
2
0
8RSETO 8SETO 8RA
BRClRO BClRO 8RN
BRSET1
8SET1
8HI
BRClRl BClRl 8lS
8RSET2 8SET2 BCC
8RClR2 BClR2 8CS
BRSET3 BSET3 BNE
BRClR3 8ClR3 BEQ
8RSET4 BSET4 BHCC
BRClR4 BClR4 BHCS
BRSET5 BSET5 BPl
BRClR5 BClR5 BMI
BRSET6 BSET6 BMC
BRClR6 BClR6 BMS
BRSET7 BSET7 Bil
8RClR7 BClR7 BIH
3/10
2/7
2/4

OIR

I

3

I

Opcode Map
Control

Raad/Modifv!Write
A
4

I
I

X
5
NEG

I I
.Xl

I

I

6

)(0

IMP

IMP

7

8
RTI'
RTS'

9

-

-

-

2/6

I

1/4

I

1/4

I 2/7 I 1/6

A

I

I

C

I

-

-

TXA

-

11'

1/2

2/2

I

- I
BSR'I

-

I
I

)(2
0
SUB
CMP

I

)(1

I

.XO

I

E

I

F

S8C
CPX
AND
81T
lOA
STA(+I)
EOR
AOC
ORA
ADD
JMP(-I)
JSR(-3)

TAX
ClC
SEC
Cli
SEI
RSP
NOP

-

ClR

I

B

-

-

INC
TST

EXT

-

-

-

I

-

-

ROR
ASR
lSl/ASl
ROl
DEC

OIR

-

SWI'

-

I

-

-

COM
lSR

Register/Memory
IMM

lOX
STX(+I)

2/4

I

3/5

I

3/6

I

-

HIGH
0
1
2
3 l
4 o
5 W
6
7
B
9
A
B
C
0
E
F

2/5

I 1/4

(NOTE) 1. Undefined opcodes are marked with "-".
2. The number at the bottom of each column denote the number of bytes and the number of cycles reQuired (Bytes/Cycles).
Mnemonics followed by a "." require a different number of cycles as follows:

RT!
9
RTS
6
SWill
BSR
B
3. (

indicate that the number in parenthesis must be added to the cycle count for that instruction.

• HD68P05V USED AS ROM·ON·CHIP HD6805U/V

When using the HD68P05V for the HD6805U (2k ROM)
or the HD6805V (4k ROM), take the memory configuration
shown in Figure 25 (a) or (b). "Not Used" or "Self Test"
($F80 $FF7) locations can be used in the HD68P05V. Note
that these locations cannot be used for a user program when
making the program mask ROM. The HD6805U or HD6805V
takes mask option method for internal osci11ation, I,?w voltage

inhibit circuit or timer. The HD68P05V takes crystal option
for osci11ation without low voltage inhibit circuits. The
HD68P05V should specify timer part by software, so it is reo
quired to set bit 0 to bit 5 of the Timer Control Register after
reset and select the prescaler dividing ratio and the clock input
source. Figure 24 shows a program example where external
clock is selected as an input source at 128 dividing ratio.

lOA #$77
STA TCR ($009)

••
•••
Figure 24 Example to initialize timer control register (TCR)

598

•

HITACHI

-------------------------------------------------------------HD68P05V07
o

7

000

Timer
RAM
(128 Bytes

127
128

765432

$000

110 Ports

$07F

S~O

ROM
(128 Bytes)

$OFF
$100

255

256
Not Used

$7FF
$800

2047
2048

o
$000

0

Port A

1

Port B

$001

2

Port C

$002

3

Port 0 (digital)

4

Port A DDR

$004'

5

Port BOOR

$005'

6

Port C DDR

$006'

7

Port 0 (analog)

8

Timer Data Reg

$008

9

Timer CTR L Reg

$009

10
ROM

31

(1920 Bytes)

\

$OO3*"

$007"

Not Used

$OOA

(22 Bytes)

$OlF

RAM (96 Bytes)

$020

Stack

$07F

127

3967
3968
4087
4088
4095

Self-Test
Interrupt Vectors

Write Only Register

$F7F
$F80
$FF7
$FF8
$FFF

"

Read Only Register

(a) HD6805U Configuration

o

7

000

76543210

$000

110 Ports
Timer

12 7
128

RAM
(128 Bytes)

$07F
$080

0

Port A

$000

1

Port B

$001

2

Port C

$002

3

Port 0 (digital)

$003"

4

Port A DDR

$004'

5

Port BOOR

$005'

6

Port C DDR

$006'

7

Port 0 (analog)

$O07*"

ROM

8

Timer Data Reg

$008

(3840 Bytes)

9

Timer CTR L Reg

$009

Not Used

$OOA

(22 Bytes)

$OlF

RAM (96 Bytes)
S,".ck

$020

10
31
3\
127

3967
3968
4087
4088
4095

Self-Test
Interrupt Vectors

$F7F
$F80
$FF7
$FF8
$FFF

$07F

Write Only Register

"

Read Only Register

(b) HD6805V ConfIguration

Figure 25 MCU Memory Configuration

~HITACHI

599

HD68P05V07'------------------------------------------------------------• PRECAUTION TO USE EPROM ON THE PACKAGE 8-8IT
SINGLE-CHIP MICROCOMPUTER

As this microcomputer takes a special packaging type with
pin sockets on its surface, pay attention to the followings;
(I) Do not apply higher electro-static voltage or serge voltage
etc. than maximum rating, or it may cause permanent
damage to the device.
(2) There are 28 pin sockets on its surface. When using 32k
Let the index-side four pins open.

When using 24 pin EPROM, match
its index and insert it into lower
24 pin sockets.

EPROM (24 pins), let the index-side four pins open.
(3) When assembling this LSI into user's system products as
well as the mask ROM type 8-bit single-chip microcomputer, pay attention to the followings to keep the good ohmic
contact between EPROM pins and pin sockets.
(a) When soldering on a printed circuit board, etc., keep its
condition under 250°C within 10 seconds. Over-time/
temperature may cause the bonding solder of socket
pins to meet and the sockets may drop.
(b) Keep out detergent or coater from the pin sockets at
aft-solder flux removal or board coating. The flux or
coater may make pin socket contactivity worse.
(c) Avoid the permanent use of this LSI under the evervibratory place and system.
(d) Repeating insertion/removal of EPROMs may damage
the contactivity of the pin sockets, so it is recommended to assemble new ones to your system products.
Ask our sales agent about anything unclear.

600

•

HITACHI

HD68P05WO------------MCU (Microcomputer
The HD68POSWO is the 8-bit Microcomputer Unit (MCU)
which contains a CPU, on-chip clock, RAM, an A/D converter,
I/O and two timers. It is designed for the user who needs an
economical microcomputer with the proven capabilities of the
HD6800-based instruction set. Setting EPROM on the package,
this MCU has the same function as the HD680SWI which has
on-chip ROM. It is useful not only for a means of debugging
and evaluating the HD680SWI but also for small-scale-production.
The following EPROMs are available.
4k byte: HN482732A
8k byte: HN482764

Unit)

-PRELIMINARY-

HD68P05WO

(DC40P)
• HARDWARE FEATURES
• 8-8it Architecture
• 96 8ytes of RAM
• Memory Mapped I/O
• Internal8-Bit Timer with 7-8it Prescaler
• Vectored interrupts: External, Timer and Software
• 23 I/O Ports + 6 Input Ports
(8 Lines Directly.Drive LEDs.)
• On-Chip Clock Generator
• On-Chip 8 bits A/D Converter
• Two Programmable Timers
• Master Reset
• 5 Vdc Single Supply
•
•
•
•
•
•
•
•
•
•
•
•
•
•

• PIN ARRANGEMENT

OVee
OA"
XTAL
OA7
NUM 7
OA.
TIMER
OA.
C.
OA.
C,l
OA3
C,
OA.
C,
OA,
C.
OA.
IC
00.
OC
00,
INT,
00.
AN.
OVss
AN,
AN,
AN,

SOFTWARE FEATURES
Similar to HD6800 Family
Byte Efficient Instruction Set
Easy to Program
Ture Bit Manipulation
Bit Test and Branch Instructions
Versatile Interrupt Handing
Powerful Indexed Addressing for Tables
Full Set of Conditional Branches
Memory Usable as Registers/F lags
Single Instruction Memory Examine/Change
10 Powerful Addressing Modes
All Addressing Modes Apply to ROM, RAM and I/O
Compatible Instructiop Set with HD6805

Vee 0
Vee 0
Vee 0
A. 0
3
A. 0
A" 0
1
VssO
A,oO
CEO
070
0.0 2
0.0
0.0
03 0

A.
B,
B.
B.
B.
B,

(Top View)

• TYPE OF PRODUCTS
Type No.

Bus Timing

HD68P05WO

1 MHz

EPROM Type No.
HN482732A-30
HN482764-3

(NOTE) EPROM is not attached to the MCU.

•

HITACHI

601

HD68P05WO~-----------------------------------------------------------

• BLOCK DIAGRAM

TIMER

7

a

Port B
1/0 line.

TlMER-2

a

Prescalsr Control
Register 2

a

Timer Data
Register 2

a

Output Compare
Register

A.

.~ ~

011:

II:
CD

~

0..

Condition Code
Register

CC

SP
"High"

PCH

AlU

a

L
oS
:g'!!
.. i
oCt:

Program Counter

"Low"

PCl

Port 0
Input lines
D. (lNT,)
0, (AN.)
D, (AN,)
D, (AN,)
D. (AN,)
D, (VRH)

(RAME) Vee Standby

,------ I
D.
0,

0,

0,
O.
O.
O.
0,

I
I
I
I

ADC lines
r-------AVee
r-----AVSS
(VRH)

1---"--1

ADR.
ADR,
ADR,
ADR,
ADR.
ADR.
ADR.
ADR,

1

ADR.
ADR,
ADR'·I
ADR"
ADRul

eel
I

(AN.)
(AN,)
(AN.)
(AN,)
AID Control
Status Register

a

._--+

Addreul-_ _ _ _ _ _ _ _ _
Output
Buffer

a
(NOTE)

Address
Output~----------~

Buffer

L _______ --1

602

Port C
1/0 lines
C.
C,
C,
C,
C.
C, (lC)
c. (OC)

r---,----,

A,
A,
A,
A.
A,
A.
A,

1
1
I

B.
B,
B,
B,
B.
B,
B.
B,

CPU

Program Counter

Timer Control

PortA
1/0 lines

.

'61

~·i
....

x

6

a Register

a Register 2

'il

Stack Point

I nput Capture

(lC)

CPU Control

a
5

Timer

(OC)

0

A
Index Register

a Status Register 2

~

c

Accumulator

a

7 Prosealer 2

eHITACHI

AID Result
Register

The contents of ( ) items can be changed by software.

----------------------------------------------------------HD68P05WO
• ABSOLUTE MAXIMUM RATINGS
Symbol

Item
Supply Voltage

Value

Vee

Input Voltage (EXCEPT TIMER)

Yin

Input Voltage (TIMER)

V

-0.3 -+7.0

V
V
·C
·C

Operating Temperature

Top,

-0.3-+12.0
0-+70

Storage Temperature

Tstg

-55 -+150

(NOTE)

Unit

-0.3-+7.0

This device has an input protection circuit for high quiescent voltage and field.liowever, be careful not
to impress a high input voltage than the insulation maximum value to the high input impedance circuit.
To insure normal operation, the following are recommended for Vi" and V out =
Vss ~ (Vin or Vout) ~ Vee

•

ELECTRICAL CHARACTERISTICS

•

DC CHARACTERISTICS (Vee = 5.25V ±0.5V, Vss = GND. Ta = 0 -+70·C. unless otherwise noted.)
Test Condition

Symbol

Item
RES
INT I.

Input "liigh" Voltage

fi'JT;

V IH

RES

iNT;, iNT2

V IL

EXTAL
All Others
Power Dissipation

•

-

-0.3
-0.3
-0.3

-1200

-

-

TIMER

-20

INTI.INT2

Standby Current

-0.3

-

Po
LVR

Low Voltage Recover

Standby Voltage

2.0

-

2.2

Timer

I nput Leak Current

typ

4.0
3.2

All Others

Input "Low" Voltage

min

IlL

Vin =O.4V-V ee

-50

max

Unit

Vee

V

Vee

V

Vee

V

Vee
0.8

V

0.8
0.6
0.8
750

V
V
V
mW

4.75
20

J.l.A

50

J.l.A

0

J.l.A

V

V

EXTAL
Nonoperation Mode

V SBB

4.0

-

Vee

Operation Mode

V SB

4.75

-

Nonoperation Mode

ISBB

-

Vee
3

min

typ

max

Unit

0.4

-

4.0

MHz

10

J.l.S

-

ns

100

ms

35

ms
pF

12.5

pF

VSBB=4.0V

-

V
mA

AC CHARACTERISTICS (Vee = 5.25V ±0.5V. Vss = GND. Ta = 0 -+70·C, unless otherwise noted.)
Item

Symbol

Clock Frequency

fel

Cycle Time

tcye

Test Condition

1.0

INT Pulse Width

tlWL

t Cyc+
250

RES Pulse Width

tRWL

10 e+
20

TIMER Pulse Width

tTWL

tcyc+
250

Oscillation Start-up Time (Crystal Mode)

tose

C L =22pF±20%
Rs=60n max.

tRHL

External Cap. = 2.2 J.l.F

Delay Time Reset
Input Capacitance

I
I

XTAL. VRH/Ds

Cin

All Others

•

5

V1n=OV

HITACHI

100

-

-

-

ns
ns

603

HD68P05WO------------------------------------------------------------• PORT ELECTRICAL CHARACTERISTICS (Vee = 5.25V ±0.5V. Vss = GND. Ta = 0 - +70°C. unless otherwise noted.)
Item

Symbol

Test Condition

min

typ

max

IOH =-10JlA

3.5

-

V

IOH = -l00JlA

2.4

-

V

IOH = -200 J1A

2.4

-

IOH = -1 rnA

1.5

V

PortC

IOH =-l00JlA

2.4

-

Po rts A a'nd C

IOL=1.6mA

-

0.5

V

-

0.5

V

1.0

V

2.0

-

Vee
0.8

V

-

J1A

20

J1A

Port A
Output "High" Voltage

Output "Low" Voltage
Input "High" Voltage
Input "Low" Voltage

IOL =3.2mA

VOL

Port B

IOL = lOrnA
V IH

Ports A. B. C
and D*

IlL
Ports B. C and D*

.. mput
* Port D as digital

-

-0.3

-

V in = 0.8V

-500

Vin= 2V
Vin = 0.4V-V ee

-300

-

V IL

Port A

I nput Leak Current

•

V OH

Port B

-20

Unit

V
V

V
J1A

AID CONVERTER ELECTRICAL CHARACTERISTICS (Vee = 5.25V±0.5V. Vss = AVss = GMD. Ta = 0 - +70°C. unless
otherwise noted.)
Item

min

typ

AVee

4.75

AV in

0

Symbol

Analog Power Supply
Voltage
Analog Input Voltage
Reference "High" Voltage

VRH

Test Condition

4.75V ~ V ee ~ 5.25V

4.0
4.0

5.25V < V ee ~ 5.75V

Analog Multiplexer Input
Capacitance
Resolution Power

-

Conversion Time

at4MHz

I nput Channels
Absolute Accuracy

Ta= 25°C

Off-channel Leak Current

AVin=5.0V. AVee =4.75V. Ta=25°C.
On-channel
AVln=OV

Off-channel Leak Current

AVin =OV. AVee =4.75V. Ta=25°C.
AVin =5V
On-channel

max

Unit

5.25

5.75

V

-

V RH

V
V

-

Vee
5.25

-

7.5

pF

-

8

-

76

76

76

Bit
teye

4

4

4

Channel

-

-

±1.5

LSB

10

100

nA

-100

-10

-

nA

TTL Equiv. (Ports A. C and D)

TTL Equiv. (Port B)

Vee

Vee
Ii = 3.2mA

l.4k!l

Vi
=r=40pF

(NOTE)

Vi

? 12 k!l

30pF

24 k!l

1. Load capacitance includes the floating capacitance of the probe and the jig etc.

2. All diod•• are IS2074(8j or equivalent.

Figure 1 Bus Timing Test Loads

604

Ii = 1.6mA

Test Point

--:;-

Test Point

V

•

HITACHI

2.4k!l

----------------------------------------------------------HD68P05WO
• SIGNAL DESCRIPTION
The input and output signals for the MCU, shown in PIN
ARRANGEMENT, are described in the following paragraphs.
• Vee and Vss
Voltage is supplied to the MCU using these two pins. Vee is
S.2SV to.SV. Vss is the ground connection.

disabled.
Vee Standby must remain above VS BB (min).
(2) Hardware
When RAME pin is "Low" before powerdown, the RAM is
disabled. Vee Standby must remain above VSBB (min).

Vee Standby

• INT J /INT 2
This pin provides the capability for asynchronously applying
an external interrupt to the MCU. Refer to INTERRUPTS for
additional information.
• XTAL and EXTAL
These pins provide connections for the on-chip clock circuit.
A crystal (AT cut, 4MHz maximum) or an external signal can be
connected to these pins to provide the internal oscillator with
varying degrees of stability. Refer to INTERNAL OSCILLATOR for recommendations about these inputs.
• TIMER
This pin allows an external input to be used to count for the
internal timer circuitry. Refer to TIMER I and TIMER 2 for
additional information about the timer circuitry.
• RES
This pin allows resetting of the MCU. Refer to RESETS for
additional information.
• NUM
This pin is not for user application and should be connected
toVss·
• I/O Lines (Ao - A,. Bo - B,. Co - C6 )
These 23 lines are arranged into three ports (A, B and C). All
lines are programmable as either inputs or outputs under software control of the Data Direction Registers. Refer to INPUT I
OUTPUT for additional information.
• Input Lines (Do - Os)
These are TTL compatible input lines, in location $0003.
These also allow analog inputs to be used for an AID converter.
Refer to INPUT for additional information.
• Vee Standby

Vee Standby provides power to the standby portion of the
RAM and the STBY PWR and RAME bits of the RAM Control
Register. Voltage requirements depend on whether the MCU
is in a powerup or powerdown state. In the powerup state, the
~er supply should provide Vee and must reach VSB before
RES .reaches 4.0V. During powerdown, Vee Standby must
remain above VSBB (min) to sustain the standby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB'
It is typical to power both Vee and Vee Standby from the
same source during nomal operation. A diode must be used
between them to prevent supplying power to Vee during powerdown operation shown Figure 2.
To sustllin the standby RAM during powerdown, the following software or hardware are needed.
(I) Software
When clearing the RAM Enable bit (RAME) which is bit 6
of the RAM Control Register at location $OOIF, the RAM is

•

T

Power Line

Figure 2 Battery Backup for Vee Standby
• RAME
This pin is used for the external control of the RAM. When
it is "Low" before powerdown, the RAM is disabled. If Vee
Standby remains above VSBB (min), the standby RAM is
sustained.
• AVee
This pin is used for the power supply of the AID converter.
When high accuracy is required, a different power source from
Vcc is impressed as
AVec =5.25 ±O.SV
Connect to Vee for all other cases.
• ANo -AN 3
These pins allow analog inputs to be used for an AID converter. These inputs are switched by the internal multiplexer
and selected by bit 0 and I of the AID Control Status Register
(ADCSR: $OOOE).
• VRH and AVss
The input terminal reference voltage for the AID converter is
"High" (VRH) or "Low" (AVss). AVss is fixed at OV.
• Input Capture (lC)
This pin is used for input of Timer2 control. in this case,
Port Cs should be configured as input. Refer to TIMER 2 for
more details.
• Output Compare (OC)
This pin is used for output of Timer2 when the Output
Compare Register is matched with the Timer Data Register 2.
In this case, Port C6 should be configured as an output. Refer to
TIMER 2 for more details.

HITACHI

605

HD68P05WOI------------------------------------------------------------•

REGISTERS

The CPU has five registers available to the programmer,
as shown in Figure 3 and explained below.

executed. These bits can be individually tested by a program
and specific action taken as a result of their state. Each individual condition code register bit is explained below.
Half Carry IH)

7

I

A

The half carry bit is used during arithmetic operations (ADD
or ADC) to indicate that a carry occurred between bits 3 and 4.

°

Interrupt (I)
This bit is set to mask everything. If an interrupt occurs
while this bit is set, it is latched and will be processed as soon as
the interrupt bit is reset.

7

I,-________. .1.

Index Register

X

I.....______________..JJ°
12

PC

'2

6 5

Program Counter

Negative IN)

°

The negative bit is used to indicate that the result of the last
arithmetic, logical or data manipulation was negative (bit 7 in
a result equal to a logical one).

l....o....I_0..LI_o.....I_0..LI_o.....l_o.....I_,.....I __s_p_--I1 Stack Pointer
Condition Code

Zero IZ)

Register

Zero is used to indicate that the result of the last arithmetic,
logical or data manipulation was zero.

Carry/Borrow

Zero

Carry/Borrow IC)

Negative

Carry/borrow is used to indicate that a carry or borrow out
of the arithmetic logic unit (ALU) occurred during the last
arithmetic operation. This bit is also affected during bit test and
branch instructions, shifts and rotates.

Interrupt Mask

~------ Half Carry

Figure 3 Programming Model

• TIMER 1
• Accumulator (A)

The accumulator is a general purpose 8-bit register used to
hold operands and results of arithmetic calculations or data
manipulations.
•

I ndex Register I X)

The index register is an 8-bit register used for the indexed
addressing mode and contains an 8-bit address that may be
added to an offset value to create an effective address. The
index register can also be used for limited calculations or data
manipulations when using read/modify/write instructions. When.
not required by a code sequence being executed, the index
register can be used as a temporary storage area.
• Program Counter IPC)

The program counter is a 13-bit register that contains the
address of the next instruction to be executed.
• Stack Pointer ISP)

The stack pointer is a 13-bit register that contains the address
of the next free location on the stack. Initially, the stack pointer is set to location $007F and is decremented as data is being
pushed onto the stack and incremented while data is being
pulled from the stack. The seven most Significant bits of the
stack pointer are permanently set to 000000 I. During an MCU
reset or reset stack pointer (RSP) instruction, the stack pointer
is set to location $007F. Subroutines and interrupts may be
nested down to location $0041 which allows the programmer to
use up to 31 levels of subroutine calls.

The MCU timer circuitry is shown in Figure 4. The 8-bit
counter, Timer Data Register I (TORI), is loaded under program control and counts down toward zero as soon as the clock
input is applied. When the TORI reaches zero, the timer interrupt request bit (bit 7) in the Timer Control Register I (TCRI)
is set. The MCU responds to this interrupt by saving the present
CPU state in the stack, fetching the timer I interrupt vector
from locations $OFF8 and $OFF9 and executing the interrupt
routine. The timer 1 interrupt can be masked by setting the
timer interrupt mask bit (bit 6) in the TCR 1. The interrupt bit
(1 bit) in the Condition Code Register also prevents a timer I
interrupt from being processed.
The clock input to the timer I can be from an external
source applied to the TIMER input pin or it can be the internal
¢2 signal. When ¢2 is used as the source, it can be gated by an
input applied to the TIMER input pin allowing the user to
easily perform pulse-width measurements. The timer 1 continues to count past zero, falling through to $FF from zero and
then continuing the count. Thus, the counter (TORI) can be
read at any time by reading the TORI. This allows a program
to determine the length of time since a timer interrupt has
occurred and not disturb the counting process.
At power-up or reset, the prescaler and counter are initialized
with all logical ones; the timer I interrupt request bit (bit 7) is
cleared and the timer 1 interrupt mask bit (bit 6) is set. In
order to release the timer I interrupt, bit 7 of the TCR 1 must
be cleared by software.

• Condition Code Register ICC)

The condition code register is a 5-bit register in which each
bit is used to indicate or flag the results of the instruction just

606

•

HITACHI

----------------------------------------------------------HD68P05WO

3

TimeOut

Write

Read

Figure 4 Timer Clock

• Timer Control Register 1 ITCR1: $0009)
The Timer Control Register I (TCRI: $0009) can control
selection of clock input source and prescaler dividing ratio and
timer interrupt.
Timer Control Register 1 (TCR1: $0009)
7

6

5

4

ll-

3

2

0

Table 1 Selection of Clock Input Source
TCR1
Bit5
0
0
1
1

Bit 4
0
1
0
1

Clock Input Source
Internal Clock tP2 *

tP2 Controlled by TIMER Input
Event Input From TIMER

• The TIMER Input pm must be tIed to Vee. for uncontrolled ~
clock input.

~

Table 2 Selection of Prescaler Dividing Ratio
Lprescaler Dividing Ratio

~CIOCk Input Source
Timer Interrupt Mask

L - - - - - - - - - - T i m e r Interrupt Request Flag

As shown in Table I, the selection of the clock input source
is ISO and lSI in the TCRI (bit 4 and bit 5) and 3 kinds of
input are selectable. At reset, internal clock tP2 controlled by
the TIMER input (bit 4 = 1, bit 5 = 0) is selected.
The prescaler dividing ratio is selected by MSO, MSl, and
MS2 in the TCRI (bit 0, bit 1, bit 2) as shown in Table 2. The
dividing ratio is selectable from eight ways (+ 1, +2, +4, +8, +16,
+32, +64, +128). At reset, +1 mode is selected. The prescaler
is initialized by writing in the TDRI.
Timer 1 interrupt mask bit (TIM) allows the Timer 1 into
interrupt at "0" and masks at "1". Timer 1 interrupt causes
Timer 1 interrupt request bit (TIF) to be set. TIF must be
cleared by software.
(NOTE) If the MCV Timer! and Timer2 are not used, the
TIMER input pin must be grounded.

•

Bit 2
0
0
0
0
1
1
1
1

HITACHI

TCR1
Bit 1
0
0
1
1
0
0
1
1

BitO
0
1
Q

1
0
1
0
1

Prescaler Dividing Ratio
+1
+2
+4
+8
+16
+32
+64
+ 128

607

HD68P05WOI-----------------------------------------------------------• TIMER 2

The HD68POSWO includes an 8-bit programmable timer
(Timer 2) which can not only measure the input waveform
but also generate the output waveform. The pulse width for
both input and output waveform can be varied from several
microseconds to several seconds.
(NOTE) If the MCU Timerl and Timer2 are not used, the
TIMER input pin must be grounded.
Timer 2 hardware consists of the followings.

• 8-bit Control Register 2
• 8-bit Status Register 2
• 8-bit Timer Data Register 2
• 8-bit Output Compare Register
• 8-bit Input Capture Register
• 5 -bit Prescaler Control Register
• 7-bit Prescaler 2
Block Diagram of Timer 2 is shown in Fig. S.

3
Timer Data Register 2 (TDR2: $001 C)

Output Compare Register
(OCR: $00101

8

8 bit Register
' - - - - - - - ' ReadIWrite
Input Capture Register (lCR: $001 E)
8 bit Register

8

Reed

Timer Control Register 2

(TCR2:S001BI

ICI

OCI TOI

Internal Interrupts Request Signal

Figure 5 Block Diagram of Timer 2

•

Timer Data Register 2 (TDR2; $OO1C)

The main part of the Timer 2 is the 8-bit Timer Data Register
2 (TDR2) as free-running counter, which is driven by internal
clock ¢2 or the TIMER input and increments the value. The
values in the counter is always readable by software.
The Timer Data Register 2 is Read/Write register and is
cleared at reset.

output level bit (OLVL) in the TCR2 is transferred to Port C6
(OC).
If Port C6 's Data Direction Register (DDR) is "I" (output),
this value will appear at Port C6 (OC). Then the values of OCF
and OLVL can be changed for the next compare. The OCR is
set to $FF at reset.
•

•

Output Compare Register (OCR; $0010)

The Output Compare Register (OCR) is an 8-bit read/write
register used to control an output waveform. The contents of
this register are always compared with those of the TDR2.
When these two contents conform to each other, the flag (OCF)
in the Timer Status Register 2 (TSR2) is set and the value of the

608

•

Input Capture Register (tCR; $001E)

The Input Capture Register (ICR) is an 8-bit read-only
register used to store the value of the TDR2 when Port Cs
(IC) input transition occurs as defined by the input edge bit
(IEDG) of the TCR2.
In order to apply Port C s (IC) input to the edge detect
circuit, the DDR of Port Cs should be cleared ("0").*

HITACHI

----------------------------------------------------------HD68P05WO
To ensure an input capture under all condition, Port C.
(IC) input pulse width should be 2 Enable-cycles at least.
·The edge detect circuit always senses Port C, (IC) even if the DDR
is set with Port C, output.

Bit 5 TOF Timer Overflow Flag
This read-only bit is set when the TDR2 contains $00. It
is cleared by reading the TSR2 followed by reading of the
TDR2 .

• Timer Control Register 2 (TCR2; $OOIB)
The Timer Control Register 2 (TCR2) consists of an 5-bit
register of which all bits can be read and written.

Bit 6 OCF Output Compare Flag
This read-only bit is set when a match is found between the
OCR and the TDR2. It is cleared by reading the TSR2 and then
writing to the OCR.

Timer Control Register 2 (TCR2: $001 B)

Bit 7 ICF Input Capture Flag
This read-only bit is set to indicate a proper level transition
and cleared by reading the TSR2 and then reading the TCR2.

76543210

1 / V 1 / 1 I C I M 1 OCIM 1 TOIM IIEDG 1 OLVL 1

Bit 0 OLVL Output Level
This bit will appear at Port C6 when the value in the TDR2
equals the value in the OCR, if the DDR of Port C6 is set. It
is cleared by reset.
Bit 1 IEDG Input Edge
This bit determines which level transition of Port Cs (IC)
input will trigger a data store to ICR from the TDR2. When
this function is used, it is necessary to clear DDR of Port Cs .
When !EDG = 0, the negative edge triggers ("High" to "Low"
transition). When IEDG = I, the positive edge triggers ("Low"
to "High" transition). It is cleared by reset.

User can write into port C6 by software.
Accordingly, after port C6 has output -by hardware and is
immediately write into by software, simultaneous cyclic pulse
control with a short width is easy .
• Prescaler Control Register 2 (PCR2: $0019)
The selections of clock input source and prescaler dividing
ratio are performed by the Prescaler Control Register 2 (PCR2:
$0019).

Prescaler Control Register 2 (PCR2: $0019)
6

071

5

4

1S1

ISO

3

0

~---Y'--~

Bit 2 TOIM Timer Overflow Interrupt Mask
When this bit is cleared, internal interrupt (TOI) is enabled
by TOF interrupt but when set, interrupt is inhibited.

1

• Timer Status Register 2 (TSR2: $OOIA)
The Timer Status Register 2 (TSR2) is an 8-bit read-only
register which indicates that:
(i) A proper leveltransition has been detected on the input
pin with a subsequent transfer of the TDR2 value to the
ICR (ICF).
(2) A match has been found between the TDR2 and the OCR
(OCF).
(3) The TDR2 is zero (TOF).
Each of the event can generate 3 kinds of internal interrupt
request and is controlled by an individual inhibit bits in the
TCR2. If the I bit in the Condition Code Register is cleared,
priority vectors are generated in response to clearing each
interrupt mask bit. Each bit is described below.

ICF

6

OCF

5

4

3

MS1

MSO

Prescaler OLding Ratio
Input Source

The selection of clock input source is performed in three
different ways by bit 4 and bit 5 of the PCR2, as shown in
Table 3. At reset, internal clock tP2 controlled by the TIMER
input (bit 4 = 1, bit 5 = 0) is selected.
The prescaler dividing ratio is selected by three bits in the
PCR2 (bits 0, 1, 2), as shown in Table 4. The dividing ratio
can be selected in 8 ways (+1, +2, +4, +8, +16, +32, +64,
+128). At reset, + 1 (bit 0 =bit 1 =bit 2 =0) is selected.
When writing into the PCR2, or when writing into the TDR2,
prescaler is initialized to $FF.
Table 3 Selection of Clock Input Source
PCR2
Bit 5
0
0
1
1

Bit4
0
1
0
1

Clock Input Source
Internal Clock tP2 *
tP2 Controlled by TIMER Input
Event Input from TIMER

• The TIMER input pin must be tied to Vee. for uncontroUed ,

Timer Status Register 2 (TSR2: $001 A)
7

MS2

'----v--------'

~CIOCk

Bit 3 OCIM Output Compare Interrupt Mask
When this bit is cleared, internal interrupt (OCI) by OCF
interrupt occurs. When set, interrupt is inhibited.
Bit 4 ICIM Input Capture Interrupt Mask
When this bit is cleared, internal interrupt (ICI) by ICF
interrupt occurs. When set, interrupt is inhibited.

o

2

2

clock.

0

TOF 1 / 1 / 1 7 1 / 1 2 1

•

HITACHI

609

HD68P05WO----------------------------------------------------------(4) Branch Instruction

Table 4 Selection of Prescaler Dividing Ratio

Bit2
0
0
0
0
1
1
1
1

PCR2
Bit 1
0
0
1
1
0
0
1
1

BitO
0
1
0
1
0
1
0
1

+1
+2
+4
+8
+ 16
+32
+64
+ 128

CAUTION
(1) Don't program branch instructions shown in Table 5-(1),
(4) at address $117 to $IIC.
(2) Don't use the instructions shown in Table 5-(1), (2), (3)
for read/write/test operation of the TSR2 flags.
When these instructions are executing the TSR2, two flags
(TOF and ICF) of the TSR2 will sometimes cleared.
Cause:

These instructions have some dummy read cycles so
the TSR2 be read when executing the instructions.

Table 5 Instruction Inhibited to Operate the TSR2
(1) Bit Test and Branch Instruction
Mnemonic
BRSET n (n=0-7)
BRCLR n (n=0-7)

OpCode
2·n
01+2· n

# Bytes
3
3

#Cycles
10
10

# Bytes
2
2

# Cycles
7
7

(2) Bit Set/Clear Instruction
Mnemonic
BSET n (n=0-7)
BCLRn (n=0-7)

OpCode
10+2· n
11+2· n

OpCode
20
21
22
23
24
24
25
25
26
27
28
29
2A
2B
2C
20
2E
2F
AD

Mnemonic
BRA
BRN
BHI
BLS
BCC
(BHS)
BCS
(BLO)
BNE
BEQ

Prescaler Dividing Ratio

BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
BSR

# Bytes
2
2
2
2
2
2
2
2
2
2
:2
2
2
2
2
2
2
2
2

# Cycles
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8

• RESETS
The MCU can be reset two ways; by initial power-up and by
the external reset input (RES), see Figure 6. All the I/O ports
are initialized to input mode (DDRs are cleared) during reset.
During power-up, a minimum 100 milliseconds is needed
before allowing the llliS' input to go "High". This time allows
the internal crystal oscillator to stabilize. Connecting a capacitor to the IffiS input, as shown in Figure 7, typically provides
sufficient delay.

(3) Read/ModifylWrite Instruction
Mnemonic
INC
DEC
CLR
COM
NEG
ROL
ROR
LSL
LSR
ASR
ASL
TST

OpCode
3C
3A
3F
33
30
39
36
38
34
37
38
3D

# Bytes
2
2
2
2
2
2
2
2
2
2
2
2

#Cycles
6
6
6
6
6
6
6
6
6
6
6
6

R'ES'/RAME Pin _ _ _ _ _ _~~

Internal
Re~t

_________

~

Figure 6 Power Up and Reset Timing

2

Part of
HD68P05WO

MCU

Figure 7 Power Up Reset Delay Circuit

610

_HITACHI

-------------------------------------------------------------HD68P05WO
•

INTERNAL OSCILLATOR

The internal oscillator circuit is designed to interface with a
crystal (AT cut, 4 MHz max.) which is sufficient to drive it
with various stability. As shown in Figure 8, a 22 pF capacitor

is required from EXTAL to ground. Crystal specifications are
given in Figure 9. Alternatively, EXTAL may be driven with
a duty cycle of 50% with XT AL connected to ground.

6 XTAl
4 MHz c:::J
max

5 EXTAL

6 XTAL
HD68P05WO
MCU

External

5 EXTAL

Clock
Input

22PF±20%~

HD68P05WO
MCU

Crystal
External Clock

Figure 8 Internal Oscillator Options

Table 6 Interrupt Priorities

C,

Interrupt

1
2
3
4
5
6

SWI
INT,
TimerllNT,
ICI
OCI
OFI

4k bytes
type
AT - Cut Parallel Resonance Crystal

Co = 7 pF max.

1=4 MHz (C, =22pF±20%1
AS= 60n max.

7

Priority
1
2
3
4
5

Interrupt

RES

Figure 9 Crystal parameters

SWI
INT,
TimerllNT,
ICI
OCI
OFI

8k bytes
type

• INTERRUPTS

The MCU can be interrupted in seven different ways: through
external interrupt input pin (fliI'F, and INT 2)' internal timer
interrupt request (Timer I, ICI, OCI and OFI) and a software
interrupt instruction (SWI). tNT2 and Timer I are generated
by the same vector address. When interrupt occurs, processing
of the program is suspended, the present CPU state is pushed
onto the stack. Figure 10 shows interrupt stacking order.
Moreover, the interrupt mask bit (I) of the Condition Code
Register is set and the external routine priority address is
achieved from the special external vector address. After that,
the external interrupt routine is executed. The interrupt
service routines normally end with a return from interrupt
(RTO instruction which allows the CPU to resume processing
of the program prior to the interrupt. The priority interrupts
are shown in Table 6 with the vector address that contains
the starting address of the appropriate interrupt routine. The
interrupt sequence is shown as a flowchart in Figure 11.
Note that the Vector Address when using the 8k byte type
EPROM is different from the 4k byte type EPROM.

6
n-4

1

5
1

11

Vector Address
$OFFE. $OFFF
$OFFC. $OFFD
$OFFA. $OFF8
$OFF8. $OFF9
$OFF6. $OFF7
$OFF4. $OFF5
$OFF2. $OFF3

Priority

RES"

Vector Address
$1 FFE. $IFFF
$1 FFC. $1 FFD
$1 FFA. $1 FF8
$1 FF8. $1 FF9
:);1 FF6. $1 FF7
$1 FF4. $1 FF5
$1 FF2. $1 FF3

6
7

4

3
ConditIon

Code Register

0

Pu II
"+1

"-3

Accumu latar

"+2

"-2

Index Register

"+3

"-1

1

1

11

PCH*
PCl'

"+4

0+5

Push
* For subroutine calls. only PCH and

pel are stacked.

Figure 10 Interrupt Stacking Order

eHITACHI

611

HD68P05WO'------------------------------------------------------------

y

INT,

Y

ilii'F,

Clear
y TIMER 1

1 .... 1
7F .... SP
O .... OOR·s
CLR INT Logic
7F .... MR
FF .... TDRI
OO .... TOR2
7 F .... Presealer 1
7 F .... Prescaler 2
50 .... TCRI
lC .... TCR2
OO .... TSR2
10 .... PCR2

Y

ICI

Y

OCI

Fetch Instruction

N

y

Stack PC. X. CC. A
Execute Instruction

Type
SWI
INT,
TIMER

Tiiii;'
ICI
OCI

OFI

4k bytes
$OFFC. $OFFO
$OFFA. $OFFB
$OFF8.$OFF9
$OFFS.$OFF9
$OFF6. $OFF7
$OFF4.$OFF5
$OFF2.$OFF3

8k bytes
$1 FFC. $1 FFO
$IFFA. $IFFB
$IFFS.$IFF9
$IFF8.$IFF9
I $1 FF6. $1 FF7
I $IFF4.$IFF5
I $IFF2.$IFF3

I
I
I
I

Figure 11 Interrupt Flowchart

• Miscellaneous Register (MR: $OOOA)
The vector address generated by the external interrupt
(mT2 ) is the same as that of TIMER I as shown in Table 6.
The miscellaneous register (MR) controls the lNT2 interrupt.

Miscellaneous Register (MR: $OOOA)
7
IRF

6
1M

5

4

3

2

k1Z121Zl21ZI

L....._ _ _ _ _

INT, Interrupt Mask

L - - - - - - - - - - I N T , Interrupt Request Flag

612

_HITACHI

0

-------------------------------------------------------------HD68P05WO
Bit 7 (lRF) of the MR is used as an mT2 interrupt request
flag. lNT"2 interrupt occurs at the INT2 negative edge, and
IRF is set. INT2 interrupt or not can be proved by checking
IRF by software in the interrupt routine of the vector address
($FF8, $FF9). IRF should be reset by software (BCLR instruction).
Bit 6 (1M) of the MR is an INT2 interrupt mask bit. When
1M is set, IN'f; interrupt is disabled. 1NT2 interrupt is also
disabled by bit (I) of the Condition Code Register (CC) like
other interrupts.
IRF is available for both read and write. However, IRF is
not writable by software. Therefore, 1lil'f2 interrupt cannot
be requested by software. At reset, IRF is cleared and 1M is
set.
•

INPUT/OUTPUT

There are 23 input/output pins. All pins are controlled by
the Data Direction Register and both input and output are
programmable. When programmed as output, the latched
output data is readable as input data, regardless of the logic

levels at the output pin due to output loading (See Figure 12.)
When Port B is programmed for output, it is capable of sinking
10 rnA on each pin (VOL max. = IV). Furthermore, Port A is
CMOS compatible as output. Ports Band C are CMOS compatible as inputs. Some examples of the Port connections are
shown in Figure 13.
Port C5 and C6 are also used for Timer 2.
When Port C5 is used as Timer 2 Input Capture (IC), Port
C5 's DDR should be cleared (port C5 as input) and bit 4 (ICIM)
in the Timer Control Register 2 (TCR2) should be cleared too.
The Input Capture Register (lCR) stores the TDR2 when a
Port C5 input transition occures as defined by bit 1 (IDEG) of
the TCR2.
When Port C6 is used as Timer 2 Output Compare (OC), Port
C6 's DDR should be set (Port C6 as output). When the Output
Compare Register (OCR) matches the TDR2, bit 0 (OLVL) in
the TCR2 is set and OLVL will appear at Port C6 . Port C6 is
writable by software. But the writing by software is unavailable
when a match between the TDR2 and the OCR is found at the
same time.

Data
Direction
Register

Output
Data Bit

Output
State

Input to

0
1
3-State

0
1

MCU

Bit
1
1
0

0
1

x

Pin

Figure 12 Typical Port 1/0 Circuitry

•

HITACHI

613

HD68P05WO---------------------------------------------------------B,

···•
·

A,

Port A

··
··••

Port B

/

_ _ _ _.., Ie· hFE' 18

B,

A,

Port B Programmed as output(s), driving Darlington base directly.

Port A Programmed as output(s), driving CMOS and TTL Load directly.

(b)

(a)

+v

+v

R

C,
PortC

Port B

··••
··•

CMOS Inverter

C,

Port C Programmed as output(s), driving CMOS load(s), using external
pull·up resistors.
(d)

Port B Programmed as output(s), driving LED(s) directly.
(e)

Figure 13 Typical Port Connections

• INPUT
Port D is usable as either TTL compatible inputs or a 4'channel input for an AID converter. Fig. 14 shows port D logic
configuration.
The Port D register at location $003 stores TTL compatible
inputs. When using as analog inputs for an AID converter,
refer to "AID CONVERTER"

(ANo to AN 3 ), the Result Register (ADRR) and the Control
Status Register (ADCSR).
CAUTION
The MCV has circuitry to protect the inputs against damage
due to high static voltages or electric field; however, the design
of the input circuitry for the AID converter, ANo - AN3, VRH
and AVec, does not offer the same level of protection. Precautions should be taken to avoid applications of any voltage
higher than maximum-rated voltage or handled in any environment producing high-static voltages.

• AID CONVERTER
The HD68P05WO has an internal 8 bit AID converter. The
AID converter, shown in Figure 15, includes 4 analog inputs

$0003 Read

Internal Bus

OIA

Port 0

1-....- - - - ( 0 . to Os)

4

AV.. - - - - -

Anl'09lnput

r------,

AN,
AN,
AN,

StllCt MUX

AN,

Figure 14 Port D

AVccC>O----

'v

881t Regl,.r IAORR: SOOOF)
AID Control Statllf Rigiiter

AID Retult Reg/Iter IAORR: SOOOF I

IADCSR: $ODOE)

Figure 15 AID Converter Block Diagram

614

•

HITACHI

------------------------------------------------------------HD68P05WO
• Analog Input (ANo to AN31
Analog inputs ANo to AN3 accept analog voltages of OV
to 5V. The resolution is 8 bits (256 divisions) with a conversion
time of 76 J1S at I MHz. Analog conversion starts selecting
analog inputs by bit 0 and bit I of the ADCSR analog input.
Since the CPU is not required during conversion, other user
programs can be executed.

• RAM Control Register (RCR: $001 FI
This register at location $01 F gives the status information
about the RAM. When RAM Enable bit (RAME) is "0", the
RAM is disabled. When Vee Standby is greater than VSBB,
Standby Power bit (STBY PWR) is set and the standby RAM is
sustained during powerdown.

Table 7 Analog Input Selection

RAM Control Register IRCR: $001 FI

ADCSR
Bit 1
0
0
1
1

Analog Input Signal

Bit 0

ci

$001 F

ANo
ANI
AN2
AN3

1
0
1

AID Control Status Register (ADCSR: $OOOEI
The Control Status Register (ADCSR) is used to select
analog input pin and confirm A/D conversion termination.
An analog input pin is selected by bit 0 and bit I as shown in
Table 7.
A/D conversion begins when the data is written into bit 0
and bit I of the ADCSR. When A/D conversion ends, bit 7
(CEND) is set. Bit 7 is reset after the ADRR is read. Even if
bit 7 is set, A/D conversion execution still continues. To end
the A/D conversion, the A/D Result Register (ADRR) stores the
most current value. During A/D conversion execution, new
data is written into the ADCSR selecting the input channel and
the A/D conversion execution at that time is suspended. CEND
is reset and new A/D conversion begins.

•

• AID Result Register (ADRR: $OOOFI
When the A/D conversion ends, the result is set in the AID
Result Register ($OOOF). When CEND of the ADCSR is set,
converted result is obtained by reading the ADRR. Furthermore, CEND is cleared.
• STANDBY RAM
The portion from $020 to $027 of the RAM can be used for
the standby RAM.
When using the standby RAM, Vee Standby should remain
above VSBB (min) during powerdown. Consequently, power is
provided only to the standby RAM and STBY PWR bit of the
RAM Control Register. 8 byte RAM is sustained with small
power dissipation. The RAM including the standby RAM is
controlled by the RAM Control Register (RCR) or RAME pin.

I
.

6
STBY

PWA

AAME

;'";db;Y==:;_;;;;;;;_-.!:4!L.I'-.IL..JL..IL..

4

3

2

0

l/1/1/1/VV1

Bit 6 RAM Enable
RAME bit is set or cleared by either software or hardware.
When the MCU is reset, RAME bit is set and the RAM is enabled. If RAME bit is cleared, the user can neither read nor write
the RAM.
When the RAM is disabled (logic "0"), the RAM address is
invalid.
Bit 7 Standby Power
STBY PWR bit is cleared whenever Vee standby decreases
below VSBB (min). This bit is a read/write status bit that the
user can read. When this bit is set, it indicates that the standby
power is applied and data in the standby RAM is valid.
• RAME Signal
RAME bit in the RCR can be cleared when RAME pin goes
"Low" by hardware (RAM is disabled). To make standby mode
by hardware, set RAME pin "Low" during Vee Standby remains above VSBB (min) and powerdown sequence should be as
shown in Fig. 17.
When RAME pin gets "Low" in the powerup state, RAME
bit of the RCR is cleared and the RAM is disabled. During
powerdown, RAME bit is sustained by Vee Standby. When
RAME pin gets "High" in the powerup state, RAME bit of the
RCR is set and the RAM is enabled.
RAME pin can be used to control the RAM externally without software.
Vee

\
RAME

~v~e~e;..

5

RAM CTRL

Reg. I$OOIFI

RAM Enable

Standby RAM
(sa)

Vee

Vee OFF

/

t-"MD;'~"r

Figure 17 RAM Control Signal (RAMEl
RAM

(96B)

1-_ _ _ _

$OO7F

Figure 16 Standby RAM

• BIT MANIPULATION
The MCU has the ability to set or clear any single RAM or
input/output port (except the data direction registers) with a
single instruction (BSET and BCLR). Any bit in the page zero
read only memory can be tested by using the BRSET and

~HITACHI

615

HD68P05WO-----------------------------------------------------------BRCLR instructions, and the program branches as a result of
its state. This capability to work with any bit in RAM, ROM or
I/O allows the user to have individual flags in RAM or to handle
single I/O bits as control lines. The example in Figure 18 shows
the usefulness of the bit manipulation and test instructions.
Assume that bit 0 of port A is connected to a zero crossing
detector circuit and that bit 1 of port A is connected to the
trigger of a TRIAC which powers the controlled hardware.
This program, which uses only seven bytes of ROM provides tum-on of the TRIAC within 14 microseconds of the zero
crossing. The timer is also incorporated to provide tum-on at
some later time which permits pulse-width modulation of the
•
controlled power.

SELF 1

···••

•

Indexed (No Offset)

Refer to Figure 23. This mode of addressing accesses the
lowest 256 bytes of memory. These instructions are one byte
long and their EA is the contents of the index register.
•

Indexed (8-bit Offset)

Refer to Figure 24. The EA is calculated by adding the contents of the byte following the opcode to the contents of the
index register. In this mode, 511 low memory locations are
accessable. These instructions occupy two bytes.

BRCLRO, PORTA, SELF 1
BSET I, PORTA
BCLR I, PORTA

··
·

•

Indexed l16-bit Offset)

Refer to Figure 25. This addressing mode calculates the EA
by adding the contents of the two bytes following the opcode
to the index register. Thus, the entire memory space may be
accessed. Instructions which use this addressing mode are
three bytes long.

Figure 18 Bit Manipulation Example

• ADDRESSING MODES
The MCU has ten addressing modes available for use by the
programmer. These modes are explained and iIlustrated briefly
in the following paragraphs.
•

to the branch instructions. In this mode the contents of the
byte following the opcode is added to the program counter
when the branch is taken. EA = (PC) +2 + ReI. Rei is the contents of the location following the instruction opcode with bit 7
being the sign bit. If the branch is not taken, Rei = 0, when a
branch takes place, the program goes to somewhere within the
range of +129 bytes to -127 bytes of the present instruction.
These instructions are two bytes long.

Immediate

Refer to Figure 19. The immediate addressing mode accesses
constants which do not change during program execution. Such
instructions are two bytes long. The effective address (EA) is
the PC and the operand is fetched from the byte follOWing the
opcode.

• Bit Set/Clear

Refer to Figure 26. This mode of addressing applies to
instructions which can set or clear any bit on page zero. The
lower three bits in the opcode specify the bit to be set or
cleared while the byte following the opcode specifies the
address in page zero.
• Bit Test and Branch

Refer to Figure 20. In direct addressing, the address of the
operand is contained in the secondbyte of the instruction.
Direct addressing allows the user to directly address the lowest
256 bytes in memory. All RAM space, I/O registers and 128
bytes of ROM are located in page zero to take advantage of
this efficient memory addressing mode.

Refer to Figure 27. This mode of addressing applies to
instructions which can test any bit in the first 256 locations
($0000 through $OOFF) and branch to any location relative to
the PC. The byte to be tested is addressed by the byte following
the opcode. The individual bit within that byte to be tested
is addressed by the lower three bits of the opcode. The third
byte is the relative address to be added to the program counter
if the branch condition is met. These instructions are three
bytes long. The value of the bit to be tested is written to the
carry bit in the condition code register.

• Extended

•

• Direct

Refer to Figure 21. Extended addressing is used to reference
any location in memory space. The EA is the contents of the
two bytes follOWing the opcode, Extended addressing instructions are three bytes long.
•

Relative

Refer to Figure 22. The relative addressing mode applies only

616

•

Implied

Refer to Figure 28. The implied mode of addressing has
no EA. All of the information necessary to execute an instruction is contained in the opcode. Direct operations on the
accumulator and the index register are included in this mode
of addressing. In addition, control instructions such as SWI
and RTI belong to this group. All implied addressing instructions are one byte long.

HITACHI

---------------------------------------------------------------HD68P05WO
lEA
i
i
i
i

Melorv

I
i
i

I
I

PROG LOA #$F8 05BE

A6

05BF

F8

I

t

/

I

8

I

Adder

,
I

""

A
F8
Index

I

e9

I

Stack Point

I
I

I

I
Prog Count

I
I

05CO
CC

I
I

§

I

i

I
I
I
I

Figure 19 Immediate Addressing Example

lEA
Melorv
i

I

I
I

i
i
i
i
i

i

I
i

CAT

FCB

32

I

L

t
Adder

20

004B

I

004B

~

A

ooto

20

I

Index Reg

PROG

LOA

CAT

I

I

I

0520

86

052E

48

Stack Point

I

I
Prog Count

I

052F

I
I
I

CC

~

I

i
i

i

I

Figure 20 Direct Addressing Example

@HITACHI

617

HD68P05VVO------------------------------------------------------------

0000
A

40
PROG

LOA

CAT

Index Reg

Stack Point

Prog Count
CAT

FCB

64

06E5~--~4~0~--~r_------------------------~

040C
CC

Figure 21 Extended Addressing Example

lEA
Memory

I
I

i

I
I
I

I

S
I

PROG

BEQ

PROG2

04A7

27

04AB

18

I

I

I

04Cl

/
I

+
Adder

t
OR

I-

oot

I

'"

Index Reg

I
Stack Point

I

I

1
z

I

I

I,

•

HITACHI

I
I

Prog Count

i rcc

Figure 22 Relative Addressing Example

618

I

04Cl

~
I,

I

A

I

------------------------------------------------------------HD68P05WO
lEA
Melorv

i

,

I
I
I

I
I
I

OOBB

,

I

/

Adder

ooto

4C

FCC I LII 00B8

49

I

PROG

LOA

X

I

t

I

I

TABL

I

'"

A
i

I

4C
Index Reg

I

BB

,

Stack Point

~"~

Prog Count

05F5
CC

§
I
I

Figure 23 Indexed (No Offset) Addressing Example

lEA
Melorv
I
I

I
I
I

I

TABL

FCB

#BF

00B9

BF

FCB

#86

OOBA

B6

FCB

#OB

OOBB

DB

FCB

#CF

OOBC

CF

LOA

TABL. X 075B

E6

075C

89

I

OOBC

f

/

Adder

I
,I

I
I

PROG

I

'"

CF

1

Index Reg

r

03

1

Stack Point

I

I

I

Prog Count

I
I

A
i

0750
CC

I

I

§
I,

I,

Figure 24 Indexed (S-Bit Offset) Addressing Example

•

HITACHI

619

HD68P05WO-----------------------------------------------------------lEA
I
I
I

Meiorv

I

~
~

I
PROG

lDA TABl. X 0692
0693
0694

/'

Adder

t

I

'"

A
DB

02

I
I

IJ

I
Prog Count

0695
CC

I

FCB

#BF

077E

BF

FCB

#86

077F

86

FCB

#DB

0780

DB

FCB

#CF

0781

CF

I

Figure 25 Indexed (l6-Bit Offset) Addressing Example

EA
0001

Memory

PORTB EaU

0001

BF
A
0000

I
Index Reg

PROG BClR 6. PORT B 05BF

lD

0590

01

Stack Point

Prog Count
0591
I
I

I
I

CC

~
I

I

I
I

Figure 26 Bit Set/Clear Addressing Example

620

I

Index Reg

I

Stack Point

07

7E

I
TABl

0780

I

I

I

I

•

HITACHI

I
I
I

------------------------------------------------------------HD68P05WO
lEA
Memtrv
i
i
i
i

PORT C

EQU

0002

2

i
I
I

FO

I

I

0002

t

/

Adder

~

Bit

2
010

A

I

Index Reg

I
I

I
I

Stack Point
I
I

i

I

PROG 6RCLR 2. PORT C. PROG 2

0574

05

0575

02

0576

10

I

I

Prog Count

1

rl

0 00

I)

H
I

OR

I

~

I

~

J

0594
CC

I

I

C

J

~
Adder

I

/

I

Figure 27 Bit Test and Branch Addressing Example

Memory
I

I
I
I

~

E5
Index Reg

I

I

PROG

TAX

E5

I
I

_A~

Prog Count
0566
CC

I

I

I

I

~
Figure 28 Implied Addressing Example

•

HITACHI

621

HD68P05WO------------------------------------------------------------• INSTRUCTION SET
The MeU has a set of 59 basic instructions. These instructions can be divided into five different types; register/memory,
read/modify/write, branch, bit manipulation and control. Each
instruction is briefly explained below. All of the instructions
within a given type are presented in individual tables.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either the accumulator or the index register. The other
operand is obtained from memory by using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to
Table 8.
• Read/Modify/Write Instructions
These instructions read a memory location or a register,
modify or test its contents and write the modified value back
to the memory or register. The TST instruction for test of
negative or zero is an exception to the read/modify/write
instructions since it does not perform the write. Refer to Table

• Branch Instructions
The branch instructions cause a branch from a program
when a certain condition is met. Refer to Table 10.
• Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes
of the memory. One group either sets or clears. The other
group performs the bit test and branch operations. Refer to
Table II.
• Control Instructions
The control iQstructions control the MeU operations during
program execution. Refer to Table 12.
• Alphabetical Listing
The complete instruction set is given in alphabetical order
in Table 13.
• Opcode Map
Table 14 is an opcode map for the instructions used on the
MeU.

9.

622

•

HITACHI

Table 8 Register/Memory Instructions

Addressing Modes
Function

Mnemonic

Immediate

Indexed
(No Offset)

Extended

Direct

Op
Op
Op
#
#
#
#
Code Bytes Cycles Code Bytes Cycles Code

Op
#
#
Bytes Cycles Code

Indexed
(8-Bit Offset)

Op
#
#
Bytes Cycles Code

Indexed
(t 6-Bit Offset)

Op
#
#
Bytes Cycles Code

#

#

Bytes Cycles

Load A from Memory

LOA

A6

2

2

B6

2

4

C6

3

5

F6

1

4

E6

2

5

06

3

6

Load X from Memory

LOX

AE

2

2

BE

2

4

CE

3

5

FE

1

4

EE

2

5

DE

3

6

Store A in Memory

STA

-

-

-

B7

2

5

C7

3

6

F7

1

5

E7

2

6

07

3

7

Store X in Memory

STX

-

-

-

BF

2

5

CF

3

6

FF

1

5

EF

2

6

OF

3

7

Add Memory to A

ADD

AB

2

2

BB

2

4

CB

3

5

FB

1

4

EB

2

5

DB

3

6

Add Memory and
Carry to A

ADC

A9

2

2

B9

2

4

C9

3

5

F9

1

4

E9

2

5

09

3

6

:I

Subtract Memory

SUB

AO

2

2

BO

2

4

CO

3

5

FO

1

4

EO

2

5

DO

3

6

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

4

C2

3

5

F2

1

4

E2

2

5

02

3

6

()

•
~

!

AND Memory to A

AND

A4

2

2

B4

2

4

C4

3

5

F4

1

4

E4

2

5

04

3

6

OR Memory with A

ORA

AA

2

2

BA

2

4

CA

3

5

FA

1

4

EA

2

5

DA

3

6

Exclusive OR Memory
with A

EOR

A8

2

2

B8

2

4

C8

3

5

F8

1

4

E8

2

5

08

3

6

Arithmetic Compare A
with Memory

CMP

A1

2

2

B1

2

4

C1

3

5

F1

1

4

E1

2

5

01

3

6

Arithmetic Compare X
with Memory

CPX

A3

2

2

B3

2

4

C3

3

5

F3

1

4

E3

2

5

03

3

6

Bit Test Memory with A
(Logical Compare)

BIT

A5

2

2

B5

2

4

C5

3

5

F5

1

4

E5

2

5

05

3

6

Jump Unconditional

JMP

-

2

3

CC

3

4

FC

1

3

EC

2

4

OC

3

5

JSR

-

-

BC

Jump to Subroutine

-

2

7

CD

3

8

FO

1

7

ED

2

8

DO

3

9

Symbols:
Op: Operation Abbreviation

# : Instruction Statement

~

W

BO

L.

::I:

o

O'l

00

-0

o

U1

~

:J:
C

0)
I\)

.".

0)

00

."

o

(11

~
Table 9

Read/ModifylWrite Instructions

Addressing Modes
Function

Implied (A)

Mnemonic

Op
Code

Implied (X)

Op
#
#
Bytes Cycles Code

Indexed
(No Offset)

Direct

Op
#
#
Bytes Cycles Code

Op
#
#
Bytes Cycles Code

Indexed
(8-Bit Offset)

Op
#
#
Bytes Cycles Code

#

#

Bytes Cycles

Increment

INC

4C

1

4

5C

1

4

3C

2

6

7C

1

6

6C

2

7

Decrement

DEC

4A

1

4

5A

1

4

3A

2

6

7A

1

6

6A

2

7

Clear

CLR

4F

1

4

5F

1

4

3F

2

6

7F

1

6

6F

2

7

Complement

COM

43

1

4

53

1

4

33

2

6

73

1

6

63

2

7

~
()

Negate
(2's Complement)

NEG

40

1

4

50

1

4

30

2

6

70

1

6

60

2

7

Rotate Left Thru Carry

ROL

49

1

4

59

1

4

39

2

6

79

1

6

69

2

7

%

Rotate Right Thru Carry

ROR

46

1

4

56

1

4

36

2

6

76

1

6

66

2

7

Logical Shift Left

LSL

48

1

4

58

1

4

38

2

6

78

1

6

68

2

7

1

4

34

2

6

74

1

6

64

2

7

1

4

37

2

6

77

1

6

67

2

7

1

4

38

2

6

78

1

6

68

2

7

4

3D

2

6

70

1

6

6D

2

7

•
x

-

Logical Shift Right

LSR

44

1

4

54

Arithmetic Shift Right

ASR

47

1

4

57

Arithmetic Shift Left

ASL

48

1

4

TST

4~L

4

Test for Negative or
Zero

-- --

Svmbols:
Op: Operation Abbreviation

# : Instruction Statement

-----

58
50
-

-

-

1
-----

L- _____

------------------------------------------------------------HD68P05WO
Table 10 Branch Instructions
Relative Addressing Mode
Mnemonic

Function

#

#

Bytes

Cycles
4

Branch Always

BRA

Op
Code
20

Branch Never

BRN

21

2
2

Branch IF Higher

BHI

22

2

Branch IF lower or Same

BlS

23

2

Branch IF Carry Clear

BCC

24

2

(Branch IF Higher or Same)

(BHS)

24

2

Branch I F Carry Set

BCS

25

2

(Branch IF lower)

(BLO)

25

2

Branch I F Not Equal

26

2

Branch I F Equal

BNE
BEQ

27

2

Branch I F Half Carry Clear

BHCC

28

2
2

Branch IF Half Carry Set

BHCS

29

Branch I F Plus

BPl

2A

2

Branch I F Minus

BMI

2B

2

Branch IF Interrupt Mask Bit is Clear

BMC

2C

2

Branch IF Interrupt Mask Bit is Set

BMS

20

2

Branch I F Interrupt Line is low

Bil

2E

2

Branch IF Interrupt Line is High

BIH

2F

2

Branch to Subroutine

BSR

AD

2

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

4
8

..

Symbols: Op: OperatIon AbbrevIatIon #: Instruction Statement

Table 11

Bit Manipulation Instructions
Addressing Modes

Function

Bit Set/Clear

Mnemonic

Bit Test and Branch
Op
#
#
Cycles
Code
Bytes

Op
Code

#

#

Bytes

Cycles

-

-

-

2'n

-

01+2'n

Branch I F Bit n is set

BRSET n (n=O ..... 7)

Branch IF Bit n is clear

BRClR n (n=O ..... 7)

Set Bit n

BSET n (n=O ..... 7)

10+2'n

2

7

-

Clear bit n

BClR n (n=O ..... 7)

11+2'n

2

7

-

3
3

10
10

-

-

Symbols: Op: Operation AbbreviatIon #: InstructIon Statement

Table 12 Control Instructions
Implied
Function

Mnemonic

Op
Code

#

#

Bytes

Cycles

Transfer A to X

TAX

97

1

2

Transfer X to A

TXA

9F

1

2

Set Carry Bit

SEC

99

1

2

Clear Carry Bit

ClC

98

1

2

Set Interrupt Mask Bit

SEI

9B

1

2

Clear Interrupt Mask Bit

CLI

9A

1

2

Software Interrupt

SWI

83

1

11

Return from Subroutine

RTS

81

1

6

Return from Interrupt

RTI

80

1

9

Reset Stack Pointer

RSP

9C

1

2

No-Operation

NOP

90

1

2

..

Symbols: Op: Operation AbbreViation

#: Instruction Statement

•

HITACHI

625

HD68P05WO----------------------------------------__________________
Table 13 Instruction Set
Mnemonic
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
ClC
Cli
ClR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX

Implied Immediate
x
x
x

x
x

x
)(

x

Relative

x
x
x

Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x

x
x

x
x

x

x
x
x

Condition Code
Bit
Set/
Clear

Bit
Test &
Branch

x
x
x
x

x
x

x
x
x
x

x

x

x

x

x

x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x

x
x
x
x

x
x
x

x

x
x

x

x
x

x

x

x

x
x

x

x
x

x

x
x

x
x
x

x
x
x
C

1\
•

•

x
x

x

x
x

x

x
x

x

x
x

x

x

x
x

x

x

x
x

x
x

Carry Borrow
Test and Set if True. Cleared Otherwise
Not Affected

HITACHI

H

I

N

Z

C

1\
1\

•

1\
1\
1\
1\
1\

1\
1\
1\
1\
1\

1\
1\

•
•
•
•
•
•
•
•
•
•
1\
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•

•

• •

x

x

Condition Code Symbols:
H
Half Carry (From Bit 3)
I
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

626

ExDirect tended

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•

•
•
•

1\

•

•

1\
1\

•

••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•1\

•
•
•
•
•
•
•
•
•
• 1\
• •
• •
• 0
• •
1 •

0
1\ 1\ 1\
1\ 1\ 1
1\ 1\ 1\
1\ 1\
1\ 1\
1\ 1\

•
•
•
• • •
• • •
1\ 1\ •
1\ 1\ •

(to be continued)

---------------------------------------------------------------HD68P05WO
Table 13 Instruction Set
Addressing Modes
Mnemonic

Immediate

Implied

Direct

x
x
x
x

LSL
LSR
NEQ
NOP

x

RSP
RTI
RTS

x

x

x
x
x
x
x
x

ROR

Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)

Relative

x
x

ORA
ROL

Extended

x
x

x
x
x

x
x
x

x
x
x

x
x
x

Bit
Setl
Clear

Bit
Test &
Branch

H

x

x

x

x

x

x

x

SEI

x
x

x
x

x

x
x
x

x

x

x
x
x

x
x
x

x

x

STA
STX
SUB
TAX

x
x

TST

x

TXA

x

SWI

x

Z

C

?

?

?

?

• • • • •

• • 1\ 1\ 1\
• • • • 1
• 1 • • •
• • 1\ 1\ •

x
x

SEC

N

• • 1\ 1\ 1\
• • 0 1\ 1\
• • 1\ 1\ 1\
• • • • •
• • 1\ 1\ •
• • 1\ 1\ 1\
• • 1\ 1\ 1\
• • • • •
?

SBC

I

•
•
•
•
•
•

• 1\ 1\ •
• 1\ 1\ 1\
1 • • •
• • • •
• 1\ 1\ •
• • • •

Condition Code Svmbols:
H
I
N
Z

Half Carry (From Bit 3)
I nterrupt Mask
Negative (Sign Bit)
Zero

Carry IBorrow
Test and Sat if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

C

1\
•

?

cable 14 Opcode Map
Bit Manipulation

Test &
Branch

0
0 BRSETO
1 BRClRO
2 BRSEn
3

BRCLR1

4 BRSET2
5 BRClR2
6 BRSET3
7 BRClR3
B BRSET4
9 BRClR4
A BRSET5
B BRCLR5
C BRSET6
0 BRCLR6
E BRSET7
F BRCLR7

Control

Read/ModifvNVrite

OIR

I

1

2

3

I

BSETO

BRA

BClRO

BRN

BSEn
BClRl

BHI

-

BLS

COM

A

I

4

I

x

I

)(1

I

,XO

6

I

7

5
I
NEQ

IMP

8
RT'RTS·

-

BCC

lSR

BCS
BNE
BEQ

ROR
ASR

-

BSET4

BHCC

lSl/ASL

-

BClR4
BSET5

BHCS
BPl

ROl
DEC

BClR5
BSET6

BMI
BMC

INC

BClR6

BMS

TST

BSET7

Bil

BClR7

BIH

2/4

-

-

-

-

-

ClR

2/6

I

1/4

I

1/4

I 2n I

(NOTE) 1. Undefined opcodes are marked with "-".

1/6

IMM

1

9

A

I

Register/Memory

oiR

I

EXT

I

B

I

C

I

)(2

1)(1

0
I
SUB
CMP

-

SBC
CPX

-

BIT
lOA
STA(+l1

-

SWI'

BSET2

IMP

-

-

BCLR2
BSET3
BClR3

2/7

3/10

8rnch

Rei

Setl
Clear

TAX

I

,XO

I

F

-

I

EOR

A
B

CLI
SEI
RSP

- I

JMPHI

NQP

BSR'I

JSR(-31

C
0
E

lOX

TXA

-

II'

1/2

2/2

I
I

F

STX(+lI

2/4

I

3/5

I

3/6

HIGH

8
9

AOC
ORA
ADD

-

~

0
1
2
3 l
4 o
5 w
B
7

AND

ClC
SEC

-

E

I

2/5

I

1/4

,-

2. The number at the bottom of each column denotes the number of bytes and the number of cycles required (Bytes/Cycles).
Mnemonics followed bV 8 ..... require a different number of cvcles as follows:
RTI
9
RTS
6
SWill

3. t

BSR

8_

) indicates that the number in parenthesis must be added to the cycle count for that instruction .

•

HITACHI

627

HD68P05WO---------------------------------------------------------•

HD68P05WO USED FOR HD6805W1

The HD6805Wl provides mask option of the internal oscillator and low voltage inhibit, while the HD68P05WO provides
only crystal option and without low voltage inhibit function.
The address from $OF? A to $OFFI cannot be used for user
program because the self test program of the HD6805Wl (on-

''''''''''

...RA.,

."

'"

".

127

SOD"

II""'"

-

00000
porte

$000'
$0002

..... 0.

$0003"

'0004'

....,.'
"""".

SOD"

ROM

"""OJ

s0007

TI,"..

D~.R.g

chip ROM version) is located at these addresses.
In order to be pin compatible with the HD6805Wl, the
address of the HD68P05WO's ROM must be located at $0080 $OFFF. Memory addresses $1000 to $IFFF should not be
usable.
r-------------~«oooww.-------~~~~--------~«ooo

..'",
".'"

....

r-----;=:----------1:::;
r---:~'=:_-------1 :::-

.....

000"

T'mer CTRL Reg ,

00"""

M,scelieneoulRIII

IO.OA

..:r'II'IItrCTRLRIIII 1

R.M
180501

SOOO.
SOOOC
....0

....,

AID CTRL 5111uaRag

SOOOf"

AIDR.,;ultReg

$001,

~14

000"

---------------

SOF7A

$OFF1
SOFF2

.aa2

OOO'C
000'0
$(Kne"

RAM Control Reg

$001 F

..

r-----;::':::.=~-=:;,=:w:':,:=:::'::=-__---1 :::••
!------;::=.'7'=""':':O:::.:....=R"::;;:..,=-__--I :~~

::::.7'------1 :~:..

\I----:':A;::'~;-;·:=::"::;,

r---------~-----j~ro

ISelfTml
4(81

TomerD81aRog.2

r---======~-----isoo~

S.... dbyRAM18IW··
j
__________________ $0027

Stlndby AAM 18 81'"

)

AAMi96!1

' -___________'L-__-, soo"
' -____________--'SOF ..

";,,'

~

' -__________.L...
l __-' SOD"

·W.. IeReg
"RHdReg

·W"gAq.
··A.IdA....

"'Stlndby RAM uaes f.rst 8 bVIe$ 01 RAM

···S'lndbvRAt./Iu. . f"I,llIVlRofAAM

Figure 29 MCU Memory Structure (For 32k bytes)

8'91

L....____________---' SlFFF

Figure 30 MCU Memory Structure (For 64k bytes)
-CAUTION This 64k bytes type should not be used debugging
on-chip ROM of the HD6805Wl .

628

s6027

- - - - - - - - - - - - - - - - - - 10028

~"

"r'

SOOOF··

~==~~~.~~~.,~,,~"~,R~~,~===1 :::

SOD"
000"
$OC'A"
SOO18

'nputCaptu"Aeg

SOOOE

AID A....1t All!!

r----------------1 :::
000'.
r----------------1 $0017

000"

SOO'.

T.merCTRLRIIIl2

AID CTRL Stetus R,g

~===============~ :::

000"
~13

T ......'51.tUllRII!I 2

$0009

r-__.~'.=.='""=~=W=R..~____-1:::
r----------------1 ::~
r----------------1 :~~

SOO10

Prescalo.CTRLRog 2

~==:::=:::::::::::=======~ ::::

r-----;T"._-=""-:-.-=R-.."":"'-------1 : :

SOOO8

,

•

HITACHI

------------------------------------------------------------HD68P05WO
•

PRECAUTION TO USE EPROM ON THE PACKAGE 8-BIT
SINGLE-CHIP MICROCOMPUTER

As this microcomputer takes a special packaging type with
pin sockets on its surface, pay attention to the followings;
(1) Do not apply higher electro-static voltage or serge voltage
etc. than maximum rating, or it may cause permanent
damage to the device.
(2) There are 28 pin sockets on its surface. When using 32k

Let the index-side four pins open.
When using 24 pin EPROM. match
its index and insert it into lower
24 pin sockets.

EPROM (24 pins),let the index-side four pins open.
(3) When assembling this LSI into user's system products as
well as the mask ROM type 8-bit single-chip microcomputer, pay attention to the followings to keep the good ohmic
contact between EPROM pins and pin sockets.
(a) When soldering on a printed circuit board, etc., keep its
condition under 2S0·C within 10 seconds. Over-time/
temperature may cause the bonding solder of socket
pins to meet and the sockets may drop.
(b) Keep out detergent or coater from the pin sockets at
aft-solder flux removal or board coating. The flux or
coater may make pin socket contactivity worse.
(c) Avoid the permanent use of this LSI under the evervibratory place and system.
(d) Repeating insertion/removal of EPROMs may damage
the contactivity of the pin sockets, so it is recommended to assemble new ones to your system products.
Ask our sales agent about anything unclear.

•

HITACHI

629

HD63P01 M1 ,HD63PA01 M1,HD63PB01 M1
CMOS MCU (Microcomputer Unit)
The HD63POIMI is an 8-bit single chip Microcomputer Unit
(MeU) which has 4096 bytes or 8192 byles of EPROM on
the package. It is pin and function (except ROM) compatible
with the HD6301Vl. The HD63POIMI can be used to emulate
the HD6301 VI for software development or it can be used in
production to allow for easy finnware changes with minimum
delay.
• FEATURES
• Pin Compatible with HD6301 V1
• On Chip Function Compatible with HD6301t'1
• 12B Bytes of RAM
• 29 Parallel I/O
·16 Bit Programmable Timer
• Serial Communication Interface
• Low Power Consumption Mode
Sleep Mode, Standby Mode
• Minimum Instruction Cycle Time
1ps (f = 1MHzl. 0.67ps (f = 1.5MHz),
0.5p5 (f = 2MHz)
• Bit Manipulation, Bit Test Instruction
• Protection from System Upset
Address Trap, Op-Code Trap
• Up to 65k Words Address Space
• Applicable to 4k or 8k Bytes of EPROM
4096 Bytes: HN482732A
8192 Bytes: HN4B2764, HN27C64

- The specifications for HD63PA01Ml and HD63PB01Ml are preliminary.-

HD63P01M1, HD63PA01M1,
HD63PB01M1

• PIN ARRANGEMENT
HD63P01M1, HD63PA01Ml, HD63PB01Ml

o
OVcc
OAn
OA,
OA.
OA,
OA.
OA3
OA"
OA,
OA.
00.
00,
00,
OVss

• TVPE OF PRODUCTS
Type No.
HD63P01M1
HD63PA01Ml'
HD63PB01M1'

Bus Timing
1MHz
1.5MHz
2MHz

EPROM Type No.
HN482732A·30, HN482764-3, HN27C64-30
HN482732A-30, HN482764-3, HN27C64-30
HN482732A-25, HN482764, HN27C64-25

* Preliminary

A"
Vss
A,.
CE

0
0
0
0

'0,
O.

0
0

o.

0

03

0

o.

0

(Top View)
(NOTE)

630

•

HITACHI

EPROM is not included •

- - - - - - - - - - - - - - - - - - - - - - H D 6 3 P 0 1 M 1,HD63PA01 M 1 ,HD63PB01 M 1
•

BLOCK DIAGRAM

On Package

, - - - - - - - - - - - --I
I

I

I

Ao I
AI I
A,I

All

A·I
All
A.I

A, ,
EPROM

A.I
A,I
AlOl

HN482732Al
[ HN482764
HN27C64

All'
Au'

,,
,,
001
011
0"

"OC 1

03,
O. '
0, :

,1

0 ...

Input

00,
0"

L __________

,

--l

•

HITACHI

631

HD63P01 M 1,HD63PA01 M 1)HD63PB01 M 1 - - - - - - - - - - - - - - - - - - - - •

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Supply Voltage
Input Voltage
Operating Temperature

Top.
Tstg

Storage Temperature
(NOTE)

Value

Vee
V ln

Unit

-0.3 -+7.0

V

-0.3 - V ee +O.3
0- +70

V
°c

-55 -+150

°c

This product has protection circuits in input terminal from high static electricity wltage and high electric field.
But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection
circuits. To assure the normal operation. we recommend V in, V out : VSS :;;; (V in or V out) ;:;; V ce.

• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee .. 5.0V±10%, Vss ~ OV, Ta = O-+70oC, unless otherwise noted.)
Item

Symbol

Test Condition

RE,STBY
Input "High" Voltage

EXTAL

min
Vee-0.5
V ee xO,7

V IH

Other Inputs

2.0

typ

max

Unit

-

Vee
to.3

V

-

Input "Low" Voltage

All Inputs

V IL

-0.3

-

O.B

Input Leakage Current

NMI, IRO I , RES, STBY

Illn I

Vi~ =0.5-V ee -0.5V

-

1.0

V
jJA

Three State (off·state)
Leakage Current

PIO-P17, P20 -P24 ,
P30 -P 37 , P40 -P47 , TS3

II Ts, 1

V in =0.5-V ec -0.5V

-

1.0

jJA

Output "High" Voltage

All Outputs

V OH

-

V
V

Output "Low" Voltage

All OutpuU

VOL

0.55

V

Input Capacitance

All Inputs

Cin

-

12.5

pF

Standby Current

Non Operation

Icc

IOH = -200jJA
IOH --10jJA

Current Dissipation·

Ice

RAM Stand·By Voltage

V RAM

*.

• V1H,min

-

IOL = 1.6mA
Vln=OV, f= 1.0MHz,
Ta = 25°C

-

2.0

15.0

jJA

Operating (f=l MHz··)

-

6.0

Sleeping (f=l MHz··)

-

1.0

10.0
2.0

mA

2.0

-

-

= vce-l.OV, VIL max = O.BV, lee of EPROM is not included.

Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typo or max,
values about Current Dissipations at f = x MHz operation are, decided according to the following formula;
typo value (f = x MHz) = typo value If = 1MHz) x x
max. value (f = x MHz) = max. value (f = 1 MHz) x x
(both the sleeping and operating)

632

2.4
Vee- 0.7

•

HITACHI

V

- - - - - - - - - - - - - - - - · - - - - - H D 6 3 P O l Ml,HD63PAOl Ml,HD63PBOl M 1
•

AC CHARACTERISTICS (Vee

=5.0V±10%, Vss =OV, Ta =O-+70°C, unless otherwise noted.1

BUS TIMING
Item

Symbol

Test
Con
dition

HD63P01Ml
min

Cycle Time
Address Strobe Pulse Width
"High"

toyc

Address Strobe Rise Time
Address Strobe Fall Time
Address Strobe Delay Time

tASr
tASf
tASD

Enable Rise Time
Enable Fall Time

tEr
tEf

-

Enable Pulse Width "High" Level

PWEH

450

Enable Pulse Width "Low" Level
Address Strobe to Enable Delay
Time

PWEL

450

t ASED

60

PWASH

~

Address Delay Time
Address Delay Time for Latch
Write
Read

Data Set-up Time

Write
Address Set-up Time for Latch
Address Hold Time for Latch
Address Hold Time
Ao - A7 Set-up Time Before E
P
eripheral Read
Access 1'i me

60

-

tAD2

Fig. 1

tADL
tosw

Fig. 2

0

tHW

20

tASL
tAHL
tAH
tASM

60
30
20
200

IBus
Non-Multiplexed
(tACCNI
I Multiplexed Bus

Oscillator stabilization Time
Processor Control Set-up Time

230
80

tOSR
tHR

Read

Data Hold Time

1
220

-

(tACCM
Fig. 10 20
tRC
Fig_ 11 200
tpcs

typ

-

HD63PA01Ml HD63PB01Ml
Unit
max min typ max min typ max
10 0.66lI

20
20

-

-

250
250

-

250

-

-

-

-

20
20

-

-

-

650
650

-

-

-

-

20

-

-

-

-

10 0.5

- - 20
- 20
40 - - 20
- - 20
300 300 40 - - 190
- - 190
- - 190
150 60 0 20 40 20 20 110 - - 395
- - 395
20 200 150

110

-

20

220
220

0
20
20
20
20
60

20
200

20
20

- - 20

-

- 100
50

10

20

160
160
160

- - - - - - - - -

-

J.IS

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

270

ns

270

ns
ms
ns

~

-

PERIPHERAL PORT TIMING
Item

Symbol

Test
Condition

HD63PB01Ml
HD63PA01Ml
HD63P01Ml
Unit
min typ max min typ max min typ max

tpDSU

Fig.3

200

Fig. 3

200

Peripheral Data.
Set-up Time

Port 1, 2, 3, 4

Peripheral Data
Hold Time

Port 1,2,3,4 tpDH

- - -

-

200

200

-

-

200

200

-

-

Delay Time, Enable Positive
Transition to 0"S3 Negative
Transition

toSDl

Fig. 5

- -

300

-

-

300

- - - 300

Delay Time, Enable Positive
Transition to 0S3 Positive
Transition

tOSD2

Fig. 5

-

300

-

-

300

- -

Delay Time, Enable Nega-I Port 1
tive Transition to Peri2" 3
tpWD
pheral Data Valid
' ,

4

Input Strobe Pulse Width
Input Data Hold Time
Input Data Setup Time

I

I

Port 3
Port 3

tpWIS
tlH
tiS

Fig. 4
Fig. 6
Fig. 6
Fig. 6

-

300

- - 300 - - 300 - - 300
200 - 200 - - 200 - 150 - 150 - - 150 - 0 0 0 -

ns
ns
ns

ns

ns
ns
ns
ns

• Except P21

•

HITACHI

633

HD63P01M1,HD63PA01M1,HD63PB01M1-----------------------------------------TIMER, SCI TIMING
Item

Test
Symbol Condition

HD63P01M1

HD63PA01M1

HD63PB01M1

min

typ

max min

typ

max min

typ

tPWT

2.0

-

2.0

-

-

2.0

-

-

toyc

400

-

-

400

-

-

400

ns

-

2.0

2.0

-

-

tcyc

0.4

-

-

0.6

0.6

0.4

-

0.6

tSCYc

max

Unit

Delay Time, Enable Positive
Transition to Timer Out

t TOD

SCI Input Clock Cycle

t ScyC

2.0

-

SCI Input Clock Pulse Width

tpWSCK

0.4

-

Test
Symbol Condition

HD63P01M1

HD63PA01M1

HD63PB01M1

min

typ

typ

max min

typ

max

RES "Low" Pulse Width

PW RSTL

3

-

tCYC

-

150

-

-

tMPs
tMPH

-

3

Mode Programming Set-up Time

-

t.yc
ns

Timer Input Pulse Width

Fig. 7

-

MODE PROGRAMMING
Item

Mode Programming Hold Time

Address Suobe

Fig. 8

2
150

max min

-

3

-

150

2

-

2

2.4V

lAS I

I't------ PWE H - - - - - l \
Enable

lEI

A,W .Ar-A.

ISei (Po,.4)

MCU Wnte

Oo-O,.A.-A,
(POfl ))

MCU Read

0.-0,. A.-A,
(POrt 3)

~ NotVahd

Figure 1 Expanded Multiplexed Bus Timing

634

•

HITACHI

Unit

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1

teye

A.-A,IPort41

RM

ISC,.

RJ!

(SC.I

MCUWnte
0,-0,
(Por131

----!-----+----~

M~~~:.d------+-~------------------~
(Pori 3)

A.-A, (Port

2AV

A.-A" !PoI'14'

O.IV

rllllA

Not Valid

Figure 2 Expanded Non·Multiplexed Bus Timing

r

rMCUR ••d

MCUWflte

~
Pl0 .....

1-'...

Pp

PJO - PH

p." . . . p.,

2.DV

08V

All Oata
2.4V .Oata Valki
Port Outputs ____________-.J £0",.8:.,._ __

Inputs

Pp

20V

Inputs'

o.sv

P30 .....

Note) Port 2: Except P1 I

Figure 4 Port Data Delay Times
(MCU Write)

'Port 3 Non·Latched Operation

Figure 3 Port Data Set·up and Hold Times
(MCU Read)

Add' ... - - - -.....

au.

0.-1

r-1r----',...-!---P,o-P St 20V

OS3----------0~I~V~~_-I-O-S-O-'---J~

'npull

• AcOiSI match .. Output Strobe Select lOSS· 0, a r.ad;
OSS' ',. writel

..::O::.8::V".1-;;...____...1If""'o;.l~~_ __
Figure 6 Port 3 Latch Timing
(Single Chip Mode)

Figure 5 Port 3 Output Strobe Timing
(Single Chip Mode)

•

HITACHI

635

HD63P01M1.HD63PA01M1.HD63PB01M1---------------------

1.4V

t MPH

rimer

-J '--i==;::"'-J ' -___

Counter _ _ _ _

-

.J<:,..-------:.i... 20V

Mode Inputs

tPID.PI'.PI2'-----:..;;;~

o BY

P"
Output

,..'------"'1"" .
Data Valid

1>-0:".:""--

Figure 8 Mode Programming Timing
Figure 7 Timer Output Timing

C =90pF for Pm-Pli. P40-P4i. SCI.

se z

=3OpF for PIU-P I ;, P20-P~4
=40pF for E
R =12kQ for Pitt-PH. P2D-PU • P.m-PI7. P40-P47. E, SCI. Sel

Figure 9 Bus Timing Test Loads (TTL Load)

Interrupt

Test

Internal

Address Bus _ _J\.. ._"__..,.._ _"-_..J'-_-" _ _"-_..J'-_J\._......
SP
SP-2
SP-3
SP-'

"__..,.._~"'-

Internal

_

_ J ' _ _ " " '_ _ _"_ _

_"....

Vector

Vet.:tor New PC
MSB
LSB
Address
Address Address

NMI, IRQ,. IRQ2

--V--..r-"""....-V-"'"'\,--V--V"-"'"'\,--V--..r-"""....-V-"'"'\,-v---...r-.r

Oa~B~ _ _- "_ _~~~~~~~-J~--"~~~~-J~~..,..~~~~~~~~r_=~~~~~~~~~"­

Internal

Read
Internal
Write

Op Code pE!;r8nd Irrelevant peoCode Data
PC 7

PC PC'S

IXOIX7

IX8IX15

ACCA

ACCB

CCR

'---

I
Figure 10 Interrupt Sequence

AM~Ji'llIt.ijlliji.rimtii.i.'r--.>-------------~:~~i

~~~)'ml.ijMlNill
..I.'.m.lMmal.I."~------------~,~J~--~------Figure 11

636

$

Reset Timing

HITACHI

-------------------------------------------HD63P01Ml,HD63PA01Ml,HD63PB01Ml
• FUNCTIONAL PIN DESCRIPTION

(I) I/O Port 2 bits, 2,1,0 are latched into bits PC2, PCI, PCO of

• Vee, Vss
These two pins are used for power supply and GND. Recommended power supply voltage is 5V ± 10%. If the operating
voltage of the EPROM is 5V ±5%, 5V±5% should be used.

• XTAL, EXTAL
These two pins are connected with parallel resonant fundamental crystal, AT cut. For instance, in order to obtain the
system clock 1MHz, a 4MHz resonant fundamental crystal is
used because the devide by 4 circuitry is included. EXTAL
accepts an external clock input of duty 50% (±1 0%) to drive,
then internal clock is a quarter the frequency of an external
clock. External driving frequency will be less than 4 times as
maximum internal clock. For external driving, XTAL pin
should be open. An example of connection circuit is shown in
Fig. 12.
A T Cut Parallel Resonance Crystal
Co'" 7 pF max
Rs == 60.n max
XTAl~--~-----'

C u = C l2 -10-22pF , 20%

CJ

EXTAl

~-

(a) Crystal Interface
XTAL

• Enable IE)
This output pin supplies system clock. Output is a singlephase, TTL compatible and 1/4 of the crystal oscillation frequency. It will drive two LS TTL load and 40pF.
• Non maskable Interrupt (NMI)
When the falling edge of the input signal of this pin is recognized, NMI sequence starts. The current instruction is continued to complete, even if NMI signal is detected. Interrupt
mask bit in Condition Code Register has no effect on NMI
detection. In response to NMI interrupt, the information of
Program Counter, Index Register, Accumulators, and Condition
Code Register are stored on the stack. On completion of this
sequence, vectoring address $FFFC and $FFFD are generated
to load the contents to the program counter. Then the CPU
branch to a non maskable interrupt service routine.
• Interrupt Request II ROd
This level sensitive input requests maskable interrupt sequence. When IRQ! goes to "Low", the CPU waits until it
completes the current instruction that is being executed. Then,
if the interrupt mask bit in Condition Code Register is not set,
CPU begins interrupt sequence; otherwise, interrupt request is
neglected.
Once the sequence has started, the information of Program
Counter, Index Register, Accumulators, Condition Code Register are stored on the stack. Then the CPU sets the interrupt
mask bit so that no further maskable interrupts may be responded.

(32-SMHz)

__-,

EXTAL

program con trol register.
(2) The contents of the two Start Addresses, $FFFE, $FFFF
are brought to the program counter, from which program
starts (see Table I).
(3) The interrupt mask bit is set. In order to have the CPU
recognize the maskable interrupts IRQ! and IRQ1, clear
it before those are used.

N.C.
External Clock

Table 1

(b) External Clock

Interrupt Vectoring memory map
Vector

Highest
Priority

Figure 12 Connection Circuit
• Standby (STBY)
This pin is used to place the MCU in the Standby mode.
If this goes to ,"Low" level, the oscillation stops, the internal
clock is tied to V ss or Vee and the MCU is reset. In order to
retain information in RAM during standby, write "0" into RAM
enable bit (RAME). RAME is bit 6 of the RAM Control Register
at address $0014. This disables the RAM, so the contents of
RAM is guaranteed. For details of the standby mode, see the
Standby section.
• Reset ("ifES)
This input is used to reset the MCU. RES must be held
"Low" for at least 20ms when the power starts up. It should be
noted that, before clock generator stabilize, the internal state
and I/O ports are uncertain, because MCU can not be reset
without' clock. To reset the MCU during system operation, it
must be held "Low" for at least 3 system clock cycles. From
the third cycle, all address buses become "High-impedance"
and it continues while RES'is "Low". If RES goes to "High",
CPU does the following.

•

Lowest
Priority

Interrupt

MS8

Lsa

FFFE

FFFF

1m

FFEE

FFEF

TRAP

FFFC

FFFO

FFFA

FFFI

NM'
SofftWre Interrupt ($WI!

iFilI.

FFFa

FFFI

FFFI

FFF7

leF (Tuner Input c.tuf4I1

FF'4

FFF5

aCF (T lmef OutpUt Com~'.)

FFF2

FFF3

TOF (Til'''''' Overflow)

FFFO

FFF1

SCI (RORF + OAFE + TOAE)

(or 1$3)

At the end of the cycle, the CPU generates 16 bit vectoring
addresses indicating memory addresses $FFF8 and $FFF9, and
load the contents to the Program Counter, then branch to an
interrupt service routine.
The Internal Interrupt will generate signal (IRQ2) which is
qUite the same as IRQ! except that it will use the vector address
$FFFO to $FFF7.
When IRQi and IRQl are generated at the same time, the
former precede the latter. Interrupt Mask Bit in the condition
code register, if being set, will keep the both interrupts off.
IRQ! has no internal latch. Therefore, if IRQ! is removed
during suspension, that JR(JI is ignored.

HITACHI

637

HD63P01M1,HD63PA01M1,HD63PB01M1----------------------------------------On occurrence of Address error or Op-code error, TRAP
interrupt is invoked. This interrupt has priority next to RES.
Regardless of the Interrupt Mask Bit condition, the CPU wiII
start an interrupt sequence. The vector for this interrupt will be
$FFEE, SFFEF.

Table 2 Port and Data Direction Register Addresses
Ports

Port Address

1/0 Port 1

$0002
$0003
$0006
$0007

I/O Port 2
I/O Port 3
I/O Port 4

Oat8 Direction
Register Address
$0000
$0001
$000.
$0005

The following pins are available only in single chip mode.

•

Input Strobe (113) (SCI)
.
This Signal controls IS3 interrupt and the latch of Port 3.
When the falling edge of this signal is detected, the flag of
Port 3 Control Status Register is set.
For detailed explanation of Port 3 Control Status Register,
see the I/O PORT 3 CONTROL STATUS REGISTER section.

•

Output Strobe (OS3) (SC2 )
This signal is used to send a strobe to an external device,
indicating effective data is on the I/O pins. The timing chart for
Output Strobe are shown in Figure 5.

• I/O Port 1
This is an 8-bit port, each bit being defined individually as
input or outputs by associated Data Direction Register. The
8-bit output buffers have three-state capability, maintaining in
high impedance state when they are used for input. In order to
be read accurately, the voltage on the input lines must be more
than 2.0V for logic "I" and less than 0.8 V for logic "0".
These are TTL compatible. After the MCU has been reset, all
I/O lines of Port I are configured as inputs in all modes except
mode I. In all modes except expanded non multiplexed mode
(Mode I), Port I is always parallel I/O. In mode I, Port I will be
output line for lower order address lines (Ao to A7).

The following pins are available for Expanded Modes.

• Read/Write (R/W) (SC2)
This TTL compatible output signal indicates peripheral and
memory devices whether CPU is in Read ("High"), or in Write
("Low"). The normal stand-by state is Read ("High"). Its
output wiII drive one TTL load and 90pF.
• I/O Strobe (iOS) (SCI)
In expanded non multiplexed mode 5 of operation, lOS
goes to "Low" onll' when A9 through AI5 are "0" and A8 is
"I" . This allows external access up to 256 addresses from
$0100 to $OIFF in memory. The timing chart is shown in
Figure 2.
• Address Strobe (AS) (SCI)
In the expanded multiplexed mode, address strobe signal
appears at this pin. It is used to latch the lower 8 bits addresses
multiplexed with data at Port 3. The 8-bit latch is controlled
by address strobe as shown in Figure 18. Thereby, I/O Port 3
can become data bus during E pulse. The timing chart of this
signal is shown in Figure I.
Address Strobe (AS) is sent out even if the internal address
area is accessed.
• PORTS
There are four I/O Ports on HD63POIMI MCU (three 8-bit
ports and one 5-bit port). 2 control pins are connected to one
of the 8-bit port. Each port has an independent write-only data
direction register to program individual I/O pins for input or
output.*
When the bit of associated Data Direction Register is "I".
I/O pin is programmed for output, if "0", then programmed for
an input.
There are four ports: Port I, Port 2, Port 3, and Port 4.
Addresses of each port and associated Data Direction Registers
are shown in Table 2.
• Only one exception is bit I of Port 2 which becomes either a
data input or a timer output. It cannot be used as an output
port.
~ does not affect I/O port Data Register. Therefore, just
after RES, Data Register is uncertain. Data Direction Registers
are reset.

638

•

• I/O Port 2
This port has five lines, whose I/O direction depends on its
data direction register. The S-bit output buffers have three-state
capability, going high impedance state when used as inputs. In
order to be read accurately, the voltage on the input lines must
be more than 2.0V for logic "I" and less than 0.8V for logic
"0". After the MCU has been reset, I/O lines are configured as
inputs. These pins on Port 2 (pins 10,9,8 of the chip) are used
to program the mode of operation during reset. The values of
these three pins during reset are latched into the upper 3 bits
(bit 7, 6 and 5) of Port 2 Data Register, which is explained in
the MODE SELECTION section.
In all modes, Port 2 can be configured as I/O lines. This port
also provides access to the Serial I/O and the Timer. However,
note that bit J (P21) is the only pin restricted to data input or
Timer output.
• I/O Port 3
This is an 8-bit port which can be configured as I/O lines, a
data bus, or an address bus multiplexed with data bus. Its
function depends on hardware operation mode programmed by
the user using 3 bits of Port 2 during Reset. Port 3 as a data bus
is bi-directional. For an input from peripherals, regular TTL
level must be supplied, that is greater than 2.0V for a logic" I"
and less than 0.8V for a logic "0". This TTL compatible threestate buffer can drive one TTL load and 90pF. In the expanded
Modes, data direction register will be inhibited after Reset and
data direction will depend on the state of the R/W line. Function of Port 3 is shown below.
Single Chip Mode (Mode 7)
Parallel Inputs/Outputs as programmed by its corresponding
Data Direction Register.
There are two control lines associated with this port in this
mode, an input strobe (IS3) and an output strobe (053), both
being used for handshaking. They are controlled by I/O Port 3
Control/Status Register. Function of these two control lines of
Port 3 are summarized as follows:
(I) Port 3 input data can be latched using IS3 (SCI) as a
input strobe signal.
(2) ITSj can be generated by CPU read or write to Port 3 's
data register.
(3) IRQI interrupt can be generated by an IS3 falling
edge .

HITACHI

- - - - - - - - - - - - - - - - - - - - - - H D 6 3 P 0 1 M 1,HD63PA01 M1,HD63PB01 M1
Port 3 strobe and latch timing is shown in Figs. 5 and 6
respectively.
I/O Port 3 Control/Status Register is explained as follows:
I/O Port 3 Control/Status Register

Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
Bit 3 LATCH ENABLE.
Bit 3 is used to control the input latch of Port 3. If the bit is
set at "I", the input data on Port 3 is latched by the falling edge
of IS3. The latch is released by the MCV read to Port 3; now
new data can be latched again by IS3 falling edge. Bit 3 is
cleared by a reset. If this bit is "0", IS3 does not affect I/O
Port 3 latch operation.
Bit 4 OSS (Output Strobe Select)
This bit identifies the cause of output strobe generation: a
write operation or read operation to I/O Port 3. When the bit is
cleared, the strobe will be generated by a read operation to Port
3. When the bit is not cleared, the strobe will be generated by a
write operation. Bit 4 is cleared by a reset.
Bit 5 Not used.
Bit6 IS3IRQI ENABLE.
If this bit is set, IRQI interrupt by IS3 Flag is enabled.
Otherwise the interrupt is disabled. The bit is cleared by a
reset.
Bit 7 IS3 FLAG.
Bit 7 is a read-only bit which is set by the falling edge of IS3
(SCI). It is cleared by a read of the Control/Status Register followed by a read/write of I/O Port 3. The bit is cleared by reset.
Expanded Non Multiplexed Mode (mode 1, 5)
In this mode, Port 3 becomes data bus. (Do - D7)
Expanded Multiplexed Mode (mode 0, 2, 4, 6)
Port 3 becomes both the data bus (Do - D7) and lower bits
of the address bus (Ao - A 7). An address strobe output is "High"
while the address is on the port.
• I/O Port 4
This is an 8-bit port that becomes either I/O or address
outputs depending on the selected operation mode. In order
to be read accurately, the voltage at the input lines must be
greater than 2.0V for a logic" I", and less than 0.8V for a logic
"0". For outputs, each line is TTL compatible and can drive one
TTL load and 90pF. Function of Port 4 for each mode is
explained below.
Single Chip Mode (Mode 7): Parallel Inputs/Outputs as programmed by its associated data direction register.
Expanded Non Multiplexed Mode (Mode 5): In this mode,
Port 4 becomes the lower address lines (Ao to A 7) by writing
"I"s on the data direction register. After reset, this port
becomes inputs. In order to use these pins as addresses, they
should be programmed as outputs.
When all of the eight bits are not required as addresses, the
remaining lines can be used as I/O lines (Inputs only).
Expanded Non Multiplexed Mode (Mode 1): In this mode, Port
4 becomes output for upper order address lines (A8 to AlS)
regard,less of the value of the direction register.
Expanded Multiplexed Mode (Mode 6): In this mode, Port 4
becomes the upper address lines (A8 to Au). After reset, this

•

port becomes inpu ts. In order to use these pins as addresses,
they should be programmed as outputs. When all of the eight
bits are not required, the remaining lines can be used as I/O
lines (input only).
Expanded Multiplexed Mode (Mode 0, 2, 4): In this mode, Port
4 becomes output for upper order address lines (As to Au)
regardless of the value of data direction register.
The relation between each mode and I/O Port I to 4 is
summarized in Table 3.
• MODE SELECTION
The operation mode after the reset must be determined by
the user wiring the 10, 9, and 8th pins externally. These three
pins are lower order bits; I/O 0, I/O I, I/O 2 of Port 2. They are
latched into the control bits PCO,PCI,PC2 ofl/OPort 2 register
when reset goes "High". I/O Port 2 Register is shown below.
Port 2 DATA REGISTER
•
$00031

pc21

PC.

I

PCO

a

1"0.1"031"021'/0 1"0
1

0

I

An example of external hardware used for Mode Selection is
shown in Fig. 13. The HDI4053B is used to separate the peripheral device from the MCV during reset. It is necessary if
the data may conflict between peripheral device and Mode
generation circuit.
No mode can be changed through software because the bits
5, 6, and 7 of Port 2 Data Register are read-only. The mode
selection of the HD63POIMI is shown in Table 4.
The HD63PO 1M1 operates in three basic modes: (I) Single
Chip Mode; (2) Expanded Multiplexed Mode (compatible with
the HMCS6800 peripheral family), (3) Expanded Non Multiplexed Mode (compatible with HMCS6800 peripheral family).
• Single Chip Mode (Mode 7)
In the Single Chip Mode, all ports will become I/O. This is
shown in Figure 15. In this mode, SCI, SC2 pins are configured
for control lines of Port 3 and can be used as input strobe (IS3)
and output strobe (~) for data handshaking.
• Expanded Multiplexed Mode (Mode 0, 2, 4, 6)
In this mode, Port 4 is configured for I/O (inputs only) or
address lines. The data bus and the lower order address bus are
multiplexed in Port 3 and can be separated by the Address
Strobe.
Port 2 is configured for 5 parallel I/O or Serial I/O, or Timer,
or any combination thereof. Port 1 is configured for 8 parallel
I/O. In this mode, HD63POIMI is expandable up to 65k words
(See Fig. 16).
• Expanded Non Multiplexed Mode (Mode 1,5)
In this mode, the HD63POIMI can directly address HMCS6800
peripherals with no external logic. In mode 5, Port 3 becomes a
data bus. Port 4 becomes Ao to A7 address bus or partial
address bus and I/O (inputs only). Port 2 is configured for a
parallel I/O, Serial I/O, Timer or any combination thereof.
Port I is configured as a paranel I/O only.
In this mode, HD63POIMI is expandable to 256 locations.
In mode 1, Port 3 becomes a data bus and Port 1 becomes
Ao to A7 address bus, and Port 4 becomes A8 to Als address
bus .

HITACHI

639

HD63P01 M1,HD63PA01 M 1,HD63PB01 M 1 - - - - - - - - - - - - - - - - - - - - In this mode, the HD63POlMl is expandable to 65k words
with no extemallogic. (See Fig. 17)
•

Lower Order Address Bus Latch

address bus in Port 3 in the expanded multiplexed mode,
address bits must be latched. It requires the 74LS373 Trans·
parent octal Ootype to latch the LSB. Latch connection of
the HD63POIMI is shown in Figure 18.

Because the data bus is multiplexed with the lower order
Vee

II

....--

RI R, II,

RES

T TT
ABC

HD63P01
Ml

X,

PJO (PCO)

Y,

X

~z,

y

P J1 (PClI

X,

Z

Pu IPC2J

Y,
2,
In"

HOl40S3B

??? ~n"ol

C

I

~

Note 1) Figure 01 Mode 7
2) RC"Reset Constant

i---

Mode

3) R,=10kn

Swll,"

Figure 13 Recommended Circuit for Mode Selection

Truth Table

,SP-I- sP

37

Pull 0 ...

PSHB
PULA

1 B - Msp,SP -1-SP
1 SP+ 1-SP,MIP-A

4
4
32 3
3
33

PULB

Aotate Lift

ROL

611

6

2 79

49

59

ROLB
Rotate Right

ROR
RORA
RORB

66 6 2 76

6

=} '91''57 I Ii I I 1,;1
&0

1 1
•
1 1

3
46

56

Notel Condition Code Register will be explained in Note of Table 11.

•

1 SP+l-SP,MIP-B

6 3

ROLA

I
I

I
I
I
I

I
I
I

1 1 A-A
1 1 B -B
oo-M-M

INep•• '

V C

··
· ··
·
·
·· ·· ··
·· · ··
··
·· ·
··· ···
·· ··
·· ··
·· ··
·· ··
·· ·.' ·•
·· ··
·•• ·· •
·· ··· ··
·· ·· • · ·
··• ·· • • · ·•
·• ··•• ······ ·•• ·•
··• ·
·
,1:1 • ·
·• ·•

53

43

COMB
NEG

1 0

I N Z

A:B+M:M+l-A:B

5 3
lB

3 2 A9 4

3 2

H

5 4

HITACHI

1 1
1

1

:} Cfi1!
•

b7

I I I I I

fiG

I
I
I
I
: I
I I
I I
I I
I
• J
I I
S
• R
S
• R
S
• R
I I
I I

I
I
I
I
I
I

I
I
I
I
I
I

R
R
R
R

R R
R R
R R

I
I

I
I

I

I

I

I

I
I
I
I
I
I

I R S
I R S
I R S
I (j)~
I 0000
I (j)~

I

I

I
I
I
I
I
I
I
I
I
I

I @ •
I @ •
I ®.
I R
I R
I @.
I @.
I @ •
I R
I R

I

I

R

I
I

I
I

R
R •

I
I
I
I
I
I

I
I
I
I
I
I

ill I
ill I

I @

• I[j)

@ I

@
@ I
@ I

Ito be continuedl

651

HD63POl Ml ,HD63PAOl Ml ,HD63PBOl M l - - - - - - - - - - - - - - - - - - - - Table 8 Accumulator, Memory Manipulation Instructions
Condition Code

Addressing Modes

Operations

Mnemonic

IMMED
OP

Shift Left
Arithmetic

ASL

-"

DIRECT
OP -

INDEX

" OP
68

-

EXTEND
"

OP -

6 2 7S

#OP

6 3

ASLA
ASLS

Double Shift
Left. Arithmetic

ASLD

Shift Right
Arithmetic

ASR
ASRA

67

6

2

77

6

Shift Right

Logical

1 1 ~

74

6

3
44

1 1

64

1 1

04

1 1

LSRD
STAA

97

STAS

07 3 2 E7

STD

00.4 2 ED 5 2 FD 5

Subtract

SU8A

SO

Double Subtract

SUSS
SUSO

00
S3

Accumulators

S8A

Subtract
With Carry

SSCA

Transfer
Accumulators

TAS
T8A

Test Zet'oor
Minus

TST

SSCS

4

2 F7

3 2 AO 4 2 SO
2 2 DO 3 2 EO 4 2 FO
3 3 93 4 2 A3 5 2 83
2 2 90

2 2 92 3 2 A2 4 2 S2
2 2 02 3 2 E2 4 2 F2

Ace N Ate. 1-0

:J en IJTjj I r9
8

br

M\
A O~
B

bl

°i,

A-M_A
8-M_S
A:8-M:M+1-A:B
1 1 A-S-A

A-M-C-A

4 3
4 3

S-M-C-S

TSTA

40

1

1 A -00

50

1

1 8 - 00

And Immediate

TST8
AIM

OR Immediate

DIM

EOR Immediate
Test Immediate

ElM
TIM

3
72 6 3
75 6 3
78 4 3
71

6

3

3
62 7 3
65 7 3
88 5 3
61

IO~

A_M
B _ M+1

3

4 3
4 3
5 3

70 4

-

bO

ACCMAl li CC 8

1 1 A-S
1 1 8_A
M-OO

2

bO

_
IIIIIIII~

16
17
60 4

eo

AO 87

8_M

4 3

10
S2
C2

bO

A_M

3 2 A7 4 2 S1 4 3

Store Double
Accumulator

bl

Al

LSRS

Store

Subtract

05

LSRA

Double Shift
Right Logical
Accumulator

6 2

M\ 1?111lililt-o
.-

1 1
1 1

M·IMM~M

7

5 4
H

#

1 1 A
1 1 8

57

64

Arithnwtic Operation

48
68

47

LSR

-

3

ASRS

Boolean/

IMPLIED

M+IMM~M

MEBIMM~M

M·IMM

Regi.t.,
3 2 1 0

I N Z V C

·· ·
··
··• ··•
····
·· ·· ·
·· ·· ••
••
••
••
·· ··
••
·•• •• ••
··• ···• •
••
•
•
••
•
•

I

I@ I
I I!ID I
I I~ I
I

I~

I

I
I I
I
I I
I I
I
R I
I
R I 6 I
R I
I

R

I~

I

I R
I I R

I

I I R

I I I I
I I I I
I I I I
I I I

••
••

I

I
I
I
I
I
1
1

I I
I I I
1 R
1 R
1 R R
1 R R

t
t
t
t

t R
t R
t R
t R •

I

I. R R

•

NOle) Condition Code Register will be explained in Not. of Table 11.

•

New Instructions
In addition to the HD6801 Instruction Set, the HD63POIMI
has the following new instructions:
AIM---·(M)· (IMM)-+(M)
Evaluates the AND of the immediate data and the
memory, places the result in the memory.
OIM---· (M) + QMM) -+ (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory.
EIM----(M)(±) QMM)-+(M)
Evaluates the EOR of the immediate data and the
contents of memory, places the result in memory .

652

•

TIIIII---·(M)· QMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the rust is op-code, the
second is immediate data, the third is address modifier.
XGDX--(ACCD)" QX)
Exchanges the contents of accumulator and the index
register.
SLP----The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.

HITACHI

---------------------HD63P01Ml,HD63PA01Ml,HD63PB01Ml
Table 9 Index Register, Stack Manipulation Instructions
AddreSSing Modes
Pointer Operation,

Compare

'"dell Reg

Mnemonic

CPX

Decrement Index Reg

DEX

DIRECT

IMMED.

- " oP2 AC 5

OP
OP 3 3 9C 4

"

8C

EXTEND

INDEX

IMPLIED

- " -•

Booleanl
ArithmetiC Operation

OP

" OP
2 BC

5 3

09

1

Decre"."t Stack Pntr

DES

34

1 1 SP-l-SP

INX

1

1 X+, ..... X

Increment Stack Pntr

INS

08
31

1

1 SP+l-SP

Load Index Reg

lOX

CE

3

3 DE 4

lOS

8E

3

3 9E

5 3

M ...... X H • (M+1)- XL

5 3

M- sPH. CM+1)-SPL

OF 4

2 EE 5 2 FE
2 AE 5 2 BE
2 EF 5 2 FF

Store Index Reg

STX

5 3

XH ..... M. XL ...... (M + 11

Store Stack Pntr

STS

9F

2 AF 5

5 3

Index Reg ..... Stack Pntr

TXS

35

Stack Pntr""" Index Reg

TSX

Add
Push Data

ABX

30 1 1 sP+1-X
3A 1 1 8+X ..... X

PSHX

3C

5

1 X L -M... SP-l-SP
XH- MIP . SP -1- SP

Pull Data

PUlX

38

4

1 SP

4

2 8F

1

SPH - M. SP L - 1M + II
1 X-l-SP

+, . . . SP.M

tP ...... XH

SP + 1- SP.M.. - XL

Exchange

XGDX

18

2

I
I

I

I

I

Loed Stack Pntr

4

·• ·· • • · ·
·· ·• ·· ·· ··
·· ·· · · · ··
·· · ··
·· · · · · ··
··• ·· ·· ·• ··• ··
··· ·
·• ·• ·• ·• ·• ·•
I

'X-M:M+l
1 X-1 ..... X

Increment Index Reg

Condition Code
Register

5 4 3 2 1 0
H I N Z V C

1 ACCD-IX

• (1) I

R

I
I

R

.(]) I

R

(])
(])

R

Note) Condition Code Register will be explained in Note of Table 11.

Table 10 Jump, Branch Instruction
Condition Code
Register

Addressing Modes
Operation,

Mnemonic

RELATIve

DIRECT

-

INDEX

-

EXTEND

IMPLIED

OP

OP

-"

- "

Sranch Test

Branch Always

BRA

Branch Never
Branch If Carry CI.r

BRN

OP - " OP
20 3 2
21 3 2

BCC

24

3 2

CoO

Branch If Carry Set

BCS

C=1

BEO

25
27

3

Branch If • Zero

> Zero
> Zero

8GE

2C
2E

3

3 2

Z + IN GJ VI- 0

3 2

C+Z-O

BlE

22
2F

3 2

Z + IN GJ VI - 1

BlS

23

3 2

C+Z-1

BlT
BMI

20
2B

3 2
3 2

NGJV-l
N -I

Branch If Not Equal
Zero

BNE

26

3 2

ZoO

Branch If Overflow
Clear

BVC

28

3 2

Branch If Overflow Set

BVS

29

3

2

V-I

Branch If Plul

8PL

2A

3 2

N-O

Branch To Subroutine

80

5

Branch If
Branch If

Branch If Higher
Branch If

< Zero

Branch If Lower Or
Some
Branch If

< Zero

Branch If Minus

BGT
BHI

"

OP

"

None

2

3 2

Z'1
NGJV-O

2

,

V-O

Jump

BSR
JMP

Jump To Subroutine

JSR

No Operattan

NOP

RltUm From Interrupt

RTI

3B 10 1

Rltum From
Subroutine

RTS

39

Softwdr. Interrupt

SWI

3F 12 1

Wait for Intlrrupt-

WAI
SlP

3E 9
lA 4

Slnp

None

2
90 5

6E 3 2 7E 3 3
2 AD 5 2 BD 6 3
01

1 1

Advances Prog. Cntr.
Only

5 1

1
1

Note) ·WAI· put. RIW high; Address Bus goes to FFFF; Data Bus goes to the three state.
Condition Code Register will be explained in Note of Table 11.

@HITACHI

5 4 3 2 1 0
H I N Z V C

·· ·· ·· ·· ·· ··
··· ··· ······ ··· ···
·· ·· ·· ·· ·· ··
··· ··· ··· ······ ···
·· ·· ·· ·· ·· ··
· ···

··
·· ·· ·· ···· ··
·· ·· ·· ·· ·· ··
··· ··• ··· ······ ···
·· · ·· ·· ·· ··
• ••·
•·
•·
•
-@-

S

• @.

653

HD63P01M1,HD63PA01M1,HD63PB01M1----------------------------------------Table 11 Condition Code Register Manipulation Instructions
~dd_"gMode!

Accumulator A ... CCR

CCR ... Accumulator A

[NOTE 1]

-

CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA

C_C-V
elM, 'nterrupt Me.k
C_OWrf_
Set Carry
Set Interrupt Me.k
$e.O..rflow

Condition Code
(f)
(Bi. V)
@
(Bit C)
@
(Bit C)
@
(Bit V)
@
(Bit V)
@
(Bit V)
(f)
(Bit N)
® (All Bit)
l~
{Bit IJ

Condition Code Register

5

Boolean OperatIOn

IMPLIED
OP
#
1
1
OC
OE
1
1
1
OA
1
1
00
1
OF
1
1
1
OB
1
1
06
1
1
07
1

Mnemonic

Operations

H

3

2

N

Z

1
V

0
C
R

··• ·• ·· ·· ·· ·
·· · ··· ··· ·· ··
···· ·
··

O~C

R

0-1

R

O~V

S

l-C

S

1~1

S

I~V

A~

4
I

@

CCR

•J •

CCR-A

• I•

Register Notes: (Bit set if test is true and cleared otherwise)
Test: Result = 100000007
Test: Result'" OOOOOOOO?
Test: BCD Character of high-order byte greater than 97 (Not cleared if previously set)
Test: Operand = 10000000 prior to execution 7
Test: Operand=01111111 priortoexecution?
Test: Set equal to Nee=1 after the execution of instructions
Test: Result less than zero? (Bit 15=1)
load Condition Code Register from Stack.
Set when interrupt occurs. If previouslV set, a Non-Maskable Interrupt is required to exit the wait

state.

@I

(All Bit) Set according to the contents of Accumulator A.
(Bit C)
Result of Multiplicetion Bi. 7=1 of ACCB?
Cli instructions and interrupt.
__
If interrupt mask·bit is set (1="1") and interrupt is requested (IRa, = "0" or IRa, = "0") •.

®

[NOTE

21

and then

eLi

instruction is executed, the CPU responds as follows.

1

the next instruction of CLI is one-machine cycle instruction.
Subsequent two instructions are executed before the interrupt is responded.
That is, the next and the next of the next instruction are executed.
2 the next instruction of CLI is two-machine cycle (or more) instruction.
Only the next instruction is executed and then the CPU jump to the interrupt routine.
Even if TAP instruction is used, instead of Cll, the same thing occurs.

Table 12 OP-Code Map
OP
CODE

~
lO

00lI0
0

00lI0 0 ..-/
0lI01 1 NOP
0010 2 ..-/
0011 3 /
0100 4 lSRD
0101 5 ASLO
0110 6 TAP
0111 7 TPA
10lI0 8 INX
1001 9 DEX
1010 A ClV
1011 B SEV
1100 C ClC
1101 0 SEC
1110 E Cli
1111 F SEI
0

ACC
A

ACC
B

IND

0lI01

0010

0011

0100

0101

0110

I

2

3
TSX

4

5

6

SBA
CBA

BRA
BRN

..-/
/
..-/
..-/

BHI
BlS
BCC
BCS
TAB
BNE
TBA
BEQ
XGDX BVC
OM
BVS
SlP
BPl
ABA

/
/
..-/
..-/
1

BMI
BGE
BlT
BGT
BlE

2

INS
PULA
PUlB
DES
TXS
PSHA
PSHB
PUlX
ATS
ABX
ATI
PSHX
MUl
WAI
SWI

S

---

1

1

5

IMM

0111
7

1000

8

1'DIR liND 1 EXT
1 1101 1 1110 1 1111
1 0 1 ElF
0
I

SBC

2

1

SUBO

COM
lSR

ADDD

3

AND
BIT

ElM

1

IMM

1100
C
SUB
CMP

4

5

lOA

ROR
ASR
ASL
ROl

6

,,-/1

STA

/1

STA

7

EOR

DEC
TIM
INC

6

ADC

9

QRA
ADD

A

B

CPX

TST

BSR

1

6

7

,,-/1
8 1

$

HITACHI

/1

JSR
lOS
STS

JMP

ClR

UNDEFINED OP CODE ~
• Only for Instructions of AIM. OIM, ElM, TIM

654

ACCB or X

1 DIR liND 1 EXT
! 1001 1 1010 1 1011
1 9 1 A 1 B

AIM
OIM

...·..........1..-/
4

ACCA or SP

IR

NEG

--J

--

fo

9

1

A

1

.............. 1
B

C

1

lDD
STD
lOX
STX
DIE

C
0
E
F

1

F

- - - - - - - - - - - - - - - - - - - - - H D 6 3 P O l Ml.HD63PAOl Ml.HD63PBOl Ml
•

I nstruction Execution Cycles

In the HMCS6800 series, the execution cycle of each instruction is the number of cycles between the start of the current
instruction fetch and just before the start of the subsequent
instruction fetch.
The HD63P01Ml uses a mechanism of the pipeline control for the instruction fetch and the subsequent instruction
fetch is performed during the current instruction being exe-

cuted.
Therefore, the method to count instruction cycles used in
the HMCS6800 series cannot be applied to the instruction cycles such as MULT,PULL, DAA andXGDXin the HD63POIMl.
Table 13 provides the information about the relrilionship
among each data on the Address Bus, Data Bus, and R/W status
in cycle-by-cycle basis during the execution of each instruction.

Table 13 Cycle-by-Cycle Operation
Address Mode &
Instructions
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
ADDD CPX
LOS
LDD
LOX
SUBD
DIRECT
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

Address Bus

CPX
LOS
SUBD

STD
STX

STS

1
2

Op Code Address+ 1
Op Code Address+2

1
1

Operand Data
Next Op Code

1
2
3

Op Code Address+ 1
Op Code Address + 2
Op Code Address+3

1
1
1

Operand Data (MSB)
Operand Data (LSB)
Next Op Code

1
2
3

Op Code Address+ 1
Address of Operand
Op Code Address+2

1
1
1

Address of Operand (LSB)
Operand Data
Next Op Code

1
2
3
1
2
3

Op Code Address + 1
Destination Address
Op Code Address+2
Op Code Address+ 1
Address of Operand
Address of Operand + 1
Op Code Address+2
Op Code Address+ 1
Destination Address
Destination Address + 1
Op Code Address+2
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-l
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3

1

Destination Address
Accumulator Data
Next Op Code
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code

2

3

3

3
ADDD
LDD
LOX

4

4
4

1
2
3

4
JSR

5

1
2
3

4
5
TIM

4

1
2
3

4
AIM
OIM

Data Bus

ElM

6

1
2
3

4
5
6

0
1
1
1
1
1
1
0

0
1
1
1

0
0
1
1
1
1
1
1
1
1
1

0
1

- Continued -

•

HITACHI

655

HD63P01 M1 ,HD63PA01 M1 ,HD63PB01 M 1 - - - - - - - - - - - - - - - - - - - - Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &.
Instructions

Address Bus

Data Bus

INDEXED
JMP

1
2

3

3
ADC
AND
CMP
LOA
SBC
TST
STA

ADD
BIT
EOR
ORA
SUB

1
2
3
4

4

1

2

4
ADDD
CPX
LOS
SUBD
STD
STX

LDD
LOX

5

STS

5

JSR

5

ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

6

TIM

5

CLR

5

AIM
OIM

ElM

7

I

3
4
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
6
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
6

7

656

Op Code Address+ 1
FFFF
Jump Address
Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2

1
1
1
1
1
1
1

Offset
Restart Address (LSB)
First Op Code of Jump Routine
Offset
Restart Address (LSB)
Operand Data
Next Op Code

Op Code Address+ 1
FFFF
IX + Offset
Op Code Address+2
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address+2
Op Code Address + 1
FFFF
IX + Offset
IX +Offset+ 1
Op Code Address+2
Op Code Address + 1
FFFF
Stack Pointer
Stack Pointer-1
IX+Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 1
Op Code Address + 1
Op Code Address+2
FFFF
IX + Offset
Op Code Address+3
Op Code Address+ 1
FFFF
IX+Offset
IX + Offset
Op Code Address+2
Op Code Address + 1
Op Code Address+2
FFFF
IX + Offset
FFFF
IX + Offset
OP Code Address+3

1
1

Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Oparand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data

•

HITACHI

0
1
1
1
1
1
1
1
1

0
0
1
1
1

0
0
1
1
1
1
1

0
1
1
1
1
1
1
1
1
1

0

00

1
1

Next Op Code
Immediate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
-Contmued -

1
1
1
1

0
1

- - - - - - - - - - - - - - - - - - - - - H D 6 3 P 0 1 M1 ,HD63PA01 M1 ,HD63PB01 M1

Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

EXTEND
JMP

1
2
3
1
2
3

3
ADC
AND
CMP
LOA
SBC
STA

ADD
BIT
EOR
ORA
SUB

TST

4

4
1
2
3

4

4
ADDD
CPX
LOS
SUBD
STD
STX

LDD
LOX

I

1
2
3

5

4
5
1
2
3

STS

5

4
5
1
2
3

JSR

6

ASL
COM
INC
NEG
ROR

ASR
DEC
LSR
ROL

4
5
6
1
2
3

6

4
5
6
1
2
3

CLR

5

I

4
5

Data Bus

Op Code Address + 1
Op Code Address+2
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
Op Code Address+3

1
1
1
1
1
1
1

Jump Address (MSB)
Jump Address (LSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Next Op Code

Op Code Address + 1
Op Code Address+2
Destination Address
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand + 1
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Destination Address
Destination Address + 1
Op Code Address+3
Op Code Address+ 1
Op Code Address+2
FFFF
Stack Pointer
Stack Pointer-1
Jump Address
Op Code Address + 1
Op Code Address+2
Address of Operand
FFFF
Address of Operand
Op Code Address+3
Op Code Address + 1
Op Code Address+2
Address of Operand
Address of Operand
0):> Code Address+3

1
1

Destination Address (MSB)
Destination Address (LSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Destination Address (MSB)
Destination Address (LSB)
Register Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data

0
1
1
1
1
1
1
1
1

0
0
1
1
1
1

0
0
1
1
1
1
1

0
1
1
1
1

0

00

1

Next Op Code
- Continued -

•

HITACHI

657

HD63P01 M1.HD63PA01 M1.HD63PB01 M 1 - - - - - - - - - - - - - - - - - - - - -

Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

IMPLIED
ABA
ASl
ASR
ClC
ClR
COM
DES
INC
INX
lSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
DAA
PULA

ABX
ASlD
CBA
Cli
ClV
DEC
DEX
INS
lSR
ROl
NOP
SEC
SEV
TAP
TPA
TSX
XGDX

Address Bus

1

Op Code Address + 1

1

Next Op Code

1
2
1
2

Op Code Address+ 1
FFFF
Op Code Address + 1
FFFF
Stack Pointer + 1
Op Code Address + 1
FFFF
Stack Pointer
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer+ 1
Stack Pointer + 2
Op Code Address+1
FFFF
Stack Pointer
Stack Pointer-1
Op Code Address+ 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address+ 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF

1
1
1
1
1
1
1

Next Op Code
Restart Address (lSB)
Next Op Code
Restart Address (lSB)
Data from Stack
Next Op Code
Restart Address (lSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (lSB)
Data from Stack (MSB)
Data from Stack (lSB)
Next Op Code
Restart Address (lSB)
Index Register (lSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (lSB)
Return Address (MSB)
Return Address (lSB)
First Op Code of Return Routine
Next Op Code
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
- Continued -

1

2

PUlB

3

3
PSHA

PSHB

4
PUlX

4
PSHX

1
2

3
4
1
2

3
4
1
2

5

3
4

5
RTS

1
2
5

3
4

5
MUl

1
2

7

3
4

5
6
7

658

Data Bus

•

HITACHI

0
1
1
1
1
1
1
1

0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

- - - - - - - - - - - - - - - - - - - - - H D 6 3 P 0 1 M 1,HD63PA01 M 1,HD63PB01 M 1

Table 13 Cycle-by-Cycle Operation I(Continued)
Address Mode 8.
Instructions

Address Bus

IMPLIED
WAI

9

1
2
3
4
5
6
7

8
9
RTI

10

1
2
3
4
5
6
7

8
9
SWI

12

10
1
2
3
4
5
6
7

8
9
10
11
12
1
2

SlP

4

r
1

I

Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer-4
Stack Pointer-5
Stack Pointer - 6
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7
Return Address
Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
FFFF

Sleep
3
4

FFFF
Op Code Address+ 1

Data Bus

1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1

Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (lSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index Register (lSB)
Return Address (MSB)
Return Address (lSB)
First Op Code of Return Routine
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (lSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (lSB)
High Impedance-Non MPX Mod e
Address Bus -MPX Mode

1

Restart Address (lSB)
Next Op Code
- Continued -

•

HITACHI

659

HD63P01M1.HD63PA01M1.HD63PB01M1-------------------------------------------

Table 13 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions

Address Bus

Data Bus

RELATIVE
BCC
BEQ
BGT
BlE
BlT
BNE
BRA
BVC
BSR

BCS
BGE
BHI
BlS
BMT
BPl
BRN
BVS

1

3

2
3

1

5

2
3
4

5

Op Code Address+ 1
FFFF
{ Branch Address······Test=·.,.
Op Code Address+ 1,,·Test=·O"

1
1

Op Code Address+ 1
FFFF
Stack Pointer
Stack Pointer-1
Branch Address

1

• LOW POWER CONSUMPTION MODE
The HD63POIMI has two low power consumption modes;
sleep and standby mode.
• SleepMode
On execution of SLP instruction, the MCU is brought to the
sleep mode. In the sleep mode, the CPU sleeps (the CPU clock
becomes inactive), but the contents of the registers in the CPU
are retained. In this mode, the peripherals of CPU will remain
active. So the operations such as transmit and receive of the
SCI data and counter may keep in operation. In this mode,
the power consumption is reduced to about 1/6 the value of
a normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The IffiS resets the MCU and the STBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, in such a case that the timer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the

1

1

0
0
1

Branch Offset
Restart Address (lSB)
First Op Code of Branch Routin e
Next Op Code

Offset
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Op Code of Subroutine

CPU.
This sleep mode is available to reduce an average power
consumption in the applications of the HD63PO I M I which may
not be always running .
Standby Mode
Bringing "STBY "Low", the CPU becomes reset and all
clocks of the HD63POIMI become inactive. It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD63POIMI.
In the standby mode, if the HD63POIMI is continuously
supplied with power, the contents of RAM is retained. The
standby mode should escape by the reset start. The following
is the typical application of this mode.
First, NMl routine stacks the MCU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the Standby bit, and then goes into the standby
mode. If the Standby bit keeps set on reset start, it means
that the power has been kept during standby mode and the
contents of RAM is normally guaranteed. The system recovery
may be possible by returning SP and bringing into the condition
before the standby mode has started. The timing relation for
each line in this application is shown in Figure 24.
•

Veo

(DNMi
HD63POl M1 'J' iii

my

~------~I~I----~r-

Figure 24 Standby Mode Timing

660

_HITACHI

- - - - - - - - - - - - - - - - - - - - - H D 6 3 P O l Ml ,HD63PAOl Ml ,HD63PBOl Ml
• ERROR PROCESSING
When the HD63P01M1 fetches an undefined instruction or
fetches an instruction from unusable memory area, it generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.

Table 14 Address Error
Mode

• Op-Code Error

I

Fetching an undefined op.code,the HD63P01M1 will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP (SFFEE, SFFEF), that has a second highest priority
(RES is the highest).
•

2,4
7
5
6
0
1
S_ S_ S_ $_ S_ $_
I

I

I

I

I

Address SGOIF SGOIF SGOIF SG07F SGOIF SG07F

S0200

SOIOO

I

I

$EFFF

SEFFF

System Flow chart ofHD63POlM1 is shown in Fig. 25.

Add ..... Error

When an instruction is fetched from other than a resident
ROM, RAM, or an external memory area, the CPU starts the
same interrupt as op·code error. In the case which the instruc·
tion is fetched from external memory area and that area is not
usable, the address error cannot be detected.
The addresses which cause address error in particular mode
are shown in Table 14.
nus feature is applicable only to the instruction fetch, not to
normal read/write of data accessing.

•

Transitions among the active mode, sleep mode, standby
mode and reset are shown in Fig. 26.
Figures 27, 28, 29 and 30 shows a system configuration.

HITACHI

661

HD63P01M1,HD63PA01M1,HD63PB01M1-----------------------------------------

A

V CT R
F F .FFF

PCL~MSP
PCH~MSP-1
IXL~MSP-2
IXH~MSP-3

ACCA ... MSP·4

Acce --MSP-5
CCR~MSP-6

Figure 25 HD63P01M1 System Flow Chart

662

•

HITACHI

- - - - - - - - - - - - - - - - - · - - - - - H D 6 3 P O l M l,HD63PAOl M l,HD63PBOl M 1

Figure 26 Transitions among Active Mode, Standby Mode,
Sleep Mode, and Reset

vee

Vee

Enable

Enable

c:::::J

NMI

NMI

IRQ,

mlr,

Port 3

8 Transfer
Lines

RES
Port 1

Port 1
81/0 Lines

81/0
Lmes

Port 2

Po,t4
81/0 lines

51/0 L,ne.
SCI

Port 4

Port 2
51/0 Lines
SCI

8110 Lines

vss

VSS

Figure 27 HD63P01Ml MCU Single-Chip Dual Processor Configuration

$

HITACHI

663

HD63POl Ml ,HD63PAOl Ml ,HD63PBOl M l - - - - - - - - - - - - - - - - - - - - -

HD63P01Ml

MCU

B

Address

Bus

Data
Address Bus

Bus

Figure 28 HD63P01Ml MCU Expanded Non-Multiplexed Mode
(Mode 5)

Data Bus

Figure 29 HD63POl M 1 MCU Expanded Multiplexed Mode
(Modes 2, 4 and 6)

HD63P01Ml MCU

8

16

Add,... BUI

Olta Bus

Figure 30 HD63P01Ml MCU Expanded Non-Multiplexed Mode (Mode 1)

664

•

HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1
• PRECAUTION TO THE BOARD DESIGN OF OSCILLATION CIRCUIT

• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State

At. shown in Fig. 31, there is a case that the cross talk disturbs the normal oscillation if signal lines are put near the
oscillation circuit. When designing a board, pay attention to
this. Crystal and CL must be put as near the HD63POIMI
as possible.

The conditions of power supply pins (pins 1 and 21), clock
pins (pins 2 and 3), input pins (pins 4, 5, 6 and 7) and E clock
pin (pin 40) are the same as those of operation. Refer to Table
15 for the other pin conditions. Both address (Ao - AI.) and
chip enable (CE) for the EPROM are in "1" state.
• Standby State

Only power supply pins (pins 1 and 21) and STBY pin (pin 7)
are active. As for the clock pin EXTAL(pin3), its input is fIXed
internally so the MCV is not influenced by the pin conditions.
XTAL (pin 2) is in "1" output. All the other pins are in high
impedance. Both address (Ao - AI.) and chip enable (CE) for
the EPROM are in "1" output.

H H - H 3 (EXTALI
HD63P01M1

Do not use this kind of print board design.
Figure 31 Precaution to the boad design of
oscillation circuit
Table 15 Pin Condition in Sleep Mode

~e

0

Pin

Port 1
PIO-P17
Port 2
P20"""P14

Port 3
P30- P31

Port 4
P40 -P47

2,4

1

Function

1/0 Port

Lower Address Bus

110 Port

Condition

Keep the cond ition
just before sleep

Output "1"

Keep the condition

Function

I/O Port

Condition

Keep the condition

just before sleep

5

6

7

+-

+-

++-

+-

+-

+-

+-

+-

+-

+-

+-

<-

+-

+-

+-

just before sleep

Function

E: Lower Address
Bus
E: Data Bus

Data Bus

E: Lower Address
Bus
E: Data Bus

Data Bus

E: Lower Address
Bus
E: Data Bus

Condition

E: Output "1"
E: High Impedance

High Impedance

E: Output "1"
E: High Impedance

High Impedance

Keep the condition
E: Output "1"
E: High Impedance just before sleep

Function

Upper Address

+-

<-

Condition

Output "1"

+-

+-

SC,

Output "1"
(Read Condition)

+-

+-

SC,

Output Address
Strobe

+-

+-

Lower Address Bus
or I "put Port

Upper Address Bus
or I nput Port

110 Port

1/0 Port

Address Bus: Out-

$

HITACHI

put "1"
Port: Keep the condition just before
sleep
+-

Output "1"

+-

Keep the condition
just before sleep

<-

Output "1"

Output Address
Strobe

Input Pin

665

HD63P01M1,HD63PA01M1,HD63PB01M1--------------------Table 16 Pin Condition during RESET

~e
Pin

0,2,4,6

1

5

7

Port 1
PIO - PI7

high impedance (input)

..

..

.

Port 2
P20 - P:14

high impedance (input)

.

..

Port 3
P30 - P37

E: "1" output
E: high impedance

Port 4
P40 - P47

high impedance (input)

..

.
..
.

"1" output (Read)

.

1:": "1" output

..

SC2
(R/W)
SCI
(AS)

high impedance

E: "0" output

..
..
..

"1" output
"1" output

• PRECAUTION TO EMULATE THE HD6301Vl BY
HD63P01Ml

The internal EPROM of the HD63POIMI provides 8k bytes
address space located from $0000 through $FFFF. The followings should be noted to emulate the HD630 I VI (4k bytes
internal ROM) with the HD63POIMI.
I. Mode 5 (Expanded Non·multiplexed Mode) and Mode 7
(Single Chip Mode)
Use 4k bytes of EPROM address space located from $FooO
through $FFFF.

high impedance (input)

2. Mode 6 (Expanded Multiplexed Mode)
Use 4k bytes of EPROM address space located from $FOOO
througil $FFFF. But do not use 4k bytes from $0000
througil $EFFF because these addresses are intemal for the
HD63POIMl, while these are external for the HD6301Vl.
3. Mode 1,2,4
No need to be careful, since ROM address is external in
these cases.

HD63P01Ml

HD6301Vl

$EOOO
External Addre••
}

Internal
Addre••
(EPROM)

Internal Addre••

$FFFF

Figure 32 Address Map of Mode 6

666

•

HITACHI

---------------------HD63P01M1,HD63PA01M1,HD63PB01M1
• PRECAUTION TO USE THE EPROM ON·PACKAGE
8 BIT SINGLE CHIP MICROCOMPUTER
Please pay attention to the followings, since this MeV has

special structure with pin socket on the package.
(1) Don't apply high static voltage or surge voltage over MAX·
IMUM RATINGS to the socket pins as well as the LSI pins.
If not, that may cause permanent damage to the device.
(2) When using 32k EPROM (24 pin), insert it on the mark side
and let the four above pins open.

(b) Note that the detergent or coating will not get in the
socket during flux washing or board coating after
soldering, because that may cause bad effect on socket
contact.
(c) Avoid permanent application of this under the condi·
tion of VIbratory place and system.
(d) The socket, inserted and pulled repeatedly loses its
contactability. It is recommended to use new one
when applied in production.

4 Pins (On index side) open.

24 Pin EPROM should be inserted
on the mark side with 4 above open.

(3) When using this in production like mask ROM type single
chip microcomputer, pay attention to the followingS to
keep the good contact between the EPROM pins and socket
pins.
(a) When soldering the LSI on a print circuit board, the
recommended condition is
Temperature: lower than 250·C
Time
: within 10 sec.

•

HITACHI

667

HD63P05YO,HD63PA05YO,-HD63PB05YO
CMOS MCU (Microcomputer Unit)
-ADVANCE INFORMATIONHD63POSYO is an 8-bit CMOS single-chip
unit which has 4k bytes or 8k bytes of EPROM
It is compatible with the HD630SYO except
HD63POSYO can be used to emulate the
HD630SYO for software. developmentor, or it
small-scale production.

microcomputer
on the package.
for ROM. The
HD630SXO or
can be used in

• FEATURES
• Pin compatible with HD6305XO and HD6305YO
• 256·byte of RAM
• A total of 55 terminals, including 32 110's, 7 inputs and 16
outputs.
• Twotimers
- 8·bit timer with a 7-bit prescaler (programmable prescaler;
event counter)
- 15-bit timer (commonly used with the SCI clock divider)
• On-chip serial interface circuit (synchronized with clock)
• Six interrupts (two external, two timer, one serial and one
software)
• Low power dissipation modes - Wait, Stop and Standby
Mode
• Minimum instruction cycle time
HD63P05YO ...... 1 [..Is (f = 1 MHz)
HD63PA05YO .... 0.67 [..IS (f = 1.5 MHz)
H D63P805YO ..... 0.5 [..IS (f = 2 MHz)
• Similar to HD6800 instruction set
• Bit manipulation
• Bit test and branch
• Versatile interrupt handling
• Full set of conditional branches
• New instructions - STOP, WAIT, DAA
• Applicable to 4k or 8k bytes of EPROM
4k bytes; HN482732A
8k bytes; HN482764, HN27C64

HD63P05YO, HD63PA05YO,
HD63PB05YO

•

(DC-64SP)
• PIN ARRANGEMENT

• TYPE OF PRODUCTS
Type No.
HD63P05YO

Bus Timing

EPROM Type No.

1 MHz

HN482732A-30, HN482764-3, HN27C64-30

HD63PA05YO

1.5 MHz

HN482732A-30, HN482764-3, HN27C64-30

HD63PB05YO

2 MHz

HN482732A-25, HN482764, HN27C64-25

(Note) EPROM is not attached to the MCU.

B2

o Vee
o All

Vee 0

OA,

Vee 0

Vee 0

OA.

A.O

OA,

A. 0

OA.

A110

OA3

VssO

OA2

A100

OA,

CEO

OAo

0,0

000

0.0

00,

0.0

002

O. 0

OVss

030

E,
E2

0,
D./1m2
37 04

3

03
502
0,
Vee

(Top View)

668

•

HITACHI

----------------------HD63P05YO,HD63PA05YO,HD63PB05YO
•

BLOCK DIAGRAM

XTAL

EXT.A.l

RES

NUM

i"N'T

STBY

TIMER

Accumulator
B

A

Index
Register

Port A

I/O
Terminals

CPU
ContrOl

x

0,
DUINT2

0,
D.

Condition Code
Register cc

0,
0,
0,

CPU

Port 0
Input

Terminals

Stack
Pointer

Sp

Program
Counter
"High" PCH
Program
Counter

Port 8
1/0

Terminals

"Low" pel

Port C
1/0
Terminals

E,
E,
E,
E,
E.
E,
E,
E,

F,
F,
F,
F,
F.
F,

__

CJEK:~~~!l ~~~J

CfI/AlI:

C,/Tx

ALU

Port E

Output
Terminals

Port F
Output
Terminals

F.

F,

Go
G,
G,
0,

Register

a.

G,
G.
G,

On Package

r-----------,

Port G
I/O
Terminals

I

Aol
A,l

A'i

EPROM

A,
A,I
A,I

Address

Aol

Output

~I

A, I
Alol
HN482732A]
[ HN482764
HN27C64

Alii
AUI

TIEl
I

I
I

0'1
0,1
0,1
0"

Data
Input

0.'
0,'
I

LI _____ _

0,1
0"

,

_~

_ _~

_...J

~HITACHI

669

HD63701XO,-------------CMOS MCU (Microcomputer

Unit)

-ADVANCE INFORMATIONThe HD63701XO is an 8-bit CMOS single-chip microcomputer
which contains a CPU compatible with the HD630IXO, 4k byte
EPROM, 192 byte RAM, 53 Input/Output lines, a Serial Communication Interface and 2 Timers. Besides powerful peripheral
functions, Halt function and Memory Ready function are available for Bus interface in expanded mode.
•
•
•

•
•
•
•

•

•
•

FEATURES
Object Code Compatible with the HD6301XO/HD6301V1
Abundant On-Chip Functions;
4k Byte EPROM, 192 Byte RAM, 531/0 Lines, 16-bit Timer,
S-bit Timer, Serial Communication Interface
Interrupt - 3 External Lines and 7 Internal Lines
MR Input for Use with Slow Memory
Halt Function for Direct Memory Access
Operation Mode
Mode 1 - Expanded Mode (On-Chip ROM disable)
Mode 2 - Expanded Mode (On-Chip ROM enable)
Mode 3 - Single Chip Mode
EPROM ProgramlVerify Mode
The same programming specification as standard 2732;
V pp =21V±0.5V, tpw =50 msec.
Low Power Consumption Mode; Sleep Mode, Standby Mode
Minimum Instruction Cycle Time; 0.5115 (f =2.0MHz)

HD63701XO

(DC-64S)

• PIN ARRANGEMENT

P"

P"

Pn
P"
PM

HD63701XO
P"
P"
Pu '

P"
p..

P"
p..

Po.

Vsrl"pp
p..
p..

P"
p..

P.,

Vee

(Top View)

670

•

HITACHI

----------------------------------------------------------------HD63701XO
• BLOCK DIAGRAM

Vcc---"
Vss - - . . .

o

P,o{Tln}

~
o

I~

P" (Tout 1 )

~

"
"

t01111llllli
;!
x

a::

PllIRx)

N

P,.{Tx)

It

r!--

t

I

!"

lIE I~ I~I§;;;

;!
~

,--

CPU

~I~ ~~~

og

P,lISCLK)

M

1l

r

P,ol
Pl1i

~

~

P,,(Tout2)

"

Pl6 lTout3)

P,,/
P,,/L

P,.jB A

I---

P,,{TCLK)

cfg
l!!

L--

L-.

r---

t--

I + - - P " I O olEO"
I - - - - - P " I DilEO,

~

~

&
,:::

~

'--

-

r-~

~P,"/A olEAn

~P"/A ,lEA,
~P"/A ,lEA,

<:'

r----+P"/A )!EAJ

~

0

i=

~

,-P" (iRQ'; )

r - - - P " / A ,lEA,

~,-

r - - - P " I A6fEA6
r - - - P " I A,/EA,

~

P" (i'R'O;)

~

"'

t---------

r---:-

~

P"
p..

eEl

~

~

(MR)

'--

J

h

rV

P,,p .. p.. -

~

11
RAM

192 Bvtes

~

.
EPROM
4k Bytes.

~P•• I A"/EA,,
t - - - - - P " I A"

t-----

P.,;

I--------P"I
I--------P"I A"

p.. -

P,,P,,P,,-

p .. 1A,/EA,

I - - - - p " 1A./EA.

t--------- P" 1A,o/EA,o

b

P"

r----+P"/A ./EA.

L-

'---

P"

~P"I D./EO.
~P"/D,/EO,

~P"IO./E0 6
~P"/D ,lEO,

'---

HAC'f)

I - - - - - P " I O,/EO,
~P"I D)/EO,

'----

~lVpp

p.. -

@HITACHI

671

INTRODUCTION OF
RELATED
DEVICES
• 8/16-bit Multi-chip Microcomputers
• 4-bit Single-chip Microcomputer
H MCS400 Series
• 4-bit Single-chip Microcomputer
H MCS40 Series
• LCD Driver Series
• IC Memories
• Gate Array
• LSI for Speech Synthesizer System
• CODEC/Filter Combo LSI

Preliminary data sheets herein contain information on new products. Specifications and information are subject to change without notice.
Advance Information data sheets herein contain information on products

under development. Hitachi reserves the right to change or discontinue these
products without notice.

674

8/16-BIT MULTI-CHIP MICROCOMPUTERS

•

S-SIT MULTI-CHIP MICROCOMPUTERS
Type No.

Division

.-----1 Process
Old Type No.

IF,:CIOC~,rk·v

1D63003R

HTsf¥s-r2.O

IH08303Y"

i-Jl!--

'=~..
~1=~I""A·30=-R3R-+--~lcMOS

~~~~~I I¥::r.~~~u;;
5.0

0 . +10

5.0

0- +10

Function

Compatibility

Packaget

,+1280V'''o'

01'-'10

~.:

IMC. . .3

Mlcroprocltllor +128 Bytes of RAM

CG-40
Microprocessor +192 Bytes of RAM

:!,!::,.,-i~f--

I

MPU

__tl CM
~ .••
I-Po-OS_

~

ICMOS

D83B05Y2'

CMOS

~:~~~::,,~80a:!'!;;;-O--f~=~""'OO;-~-1NMOS
.06802
08802W
.08809

12:0

Ht=

F

INMOS

D48802

~:=~=:'--+

nu&.

1.0
1.0

INMOS
-tNMOS
CMOS

IH08309"

0 - +10

;~~;.

Microprocessor +256 Bvtes of RAM

5.0

0 - +10

~;.:S

Microprocessor +128 Bytes of RAM

5.0

0-+70

:~;!:S

Microprocessor +256 Bytes of RAM

6.0

-20-+76 0p-'IO

15.0
15.0

-20 - +76 OP·40

~
;-

___

5.0

1

Uy..... RAM

5.0

-20 ... +75

OP-40

High·EndS·O" Mic"",,,,,,,,_,

~5.0

-20"" +76

OP-40

High-End 8.Bit

~5.0

-20 ... +76

OP40

High.End B·Bit Mlcroprocenor
(Extern.1 Clock Typel

;--

,"OS

[3.ij"-

6.0

~;~==+!~;.~.,~ NMOS

.1?--~

5.0

-20 .... +75 DP-40

5.0

-20- +75

IH08309E"
I HD6821

I HD46821

IH068B21

IHD48SB2

,HD83B21

CMOS

~i~~~~::~~-+----

NMOS

IPTM

iFOC

IH06843

:~::~:.:.
I HD48603S

IMC68AOO
IMC68BOO

MicroprOClluor

~

t.!==

F

20- +76

0'-40

~

Microp~or

IMC680RE
IMC68A09E

IMC. . . . .E

High-End 8·Bit Microprocessor

IExt.rnal Clock Typa)
Peripheral Interface Adapter

~

IMC68B21

~;!

Peripheral Interface Adapte,

Programmable Timer Module

5.0

CMOS I
5.0
INMOS f*---I 5.0

-20 - +75 OP·2B
0-+75

IOP.40

-20'" +76

DP-4Q

-20"" +75

OP"",O

IMC68A40

Programmable Timer Module

I Flop.V Ol,k Con',oll.,
IMC6844

p"H~'[D684~~5c=i:~:'~~04865~50055~RR.2);:: NMOS
Vi ICRTC

~

j

:~:::.':

IH08BA45S
:OMS( IH08B46

IHD48505S
IH048505S.
IHD48848

NMOS

~ 5.0
15.0

:~~::

CMOS

ISSOA

IHD88A52~=2

INMOS

ATC

IHD48~Ao.:-.-+---~NMOS
IHoI_18

IMC68844
5.0

INMOS

IACIA

AOU

Ri=
,.0

ICMOS

it-'--

-20"" +75

5.0

f3.0MHz High-1P88d Display)

IMC88A~

IMC88...

CRT Controller
(3.1MHz High.speed Oispl-vl

r-

I Combination ROM I/O Tim.,

IMC6846

-20 - +75 IOP.24

Iln",face Ada... ,

IMC88A50

Asynchronous Communications
Interface Adapter

0_0"'_
Ad....
_'----1p*=="--2

-20 . +75 I0I'_.24--i1i-Svnch_,"nou_,,:
S8_d.'1
-20'" +75

6.0
1.0

OP-40

I MCBII4.

CRT Controll.r

-20- +75 IOP·40

-20'" +75 OP·24

f¥s--15.0

I

Direct Memory Acetin Controller

DP-40

.5.0

Analog Oata Acquisition Unit

Rul Time Clock Plu. RAM
• +75 IOP.24

MCI48816

R.o! .

• Preliminary·· Under development ••• Wide Temperature Range (-40"" +85"C) version i, .veilible.

tOP; PI_ttc DIP. FP; PI_tic Flat Pack• . CG: GI ....Hled Ceramic LHCl!_ Chip Carrier

•

HITACHI

675

8/l6-BIT MULTI-CHIP M I C R O C O M P U T E R S , - - - - - - - - - - - - - - - - - - - - - - - - -

•

16-BIT MULTI-CHIP MICROCOMPUTERS
LSI Characteristics
Division

MPU

Type No.

Process

e
"

MC6S000L4

HD68000.a
HD6S000-10

S
10

HD6S000-12

12.5

HD68000Y4

4

HD68000Y6

6

HD68000YS

NMOS

S

HD6S000Y10

10

HD68000Y12
HD68000Z4'

12.5

HD68000Z6'

6

MC68000L10
MC6S000L12

f-

MC6S000R4
MC6S000R6

0-+70

5.0

PGA-6S

Microprocessor

MC6S000RS
MC68000R10
MC6S000R12

r----

MC6S000Z4
MC6S000Z6

HD6BOOOZS'

S

HD6BOOOZ10'

10

MC6S000Z10

HD6BOOOZ12'

12.5
4

MC6S000Z12
MC68450L4

HD68450.a

6
S

HD68450·10*

10

HD68450·12**
HD68450Y4

NMOS

12.5
4

HD68450Y6

6

HD68450YS

S
10
12.5

HD63463-6**

HD63484-6**

MC6S000ZS

CG-6S*

MC68450L6
MC68450LB

DC-64

MC68450L10
0-+70

5.0

!---

Direct Memory
Access Controller

6

-

5.0

-20 - +75

DC-48

Hard Disk Controller

5.0

-20 - +75

DC-64

Advanced CRT Controller

S
4
CMOS

HD63484-S**

** Under development

6

-

PGA-6S*

4
CMOS

HD63463.a**
HD63484-4**

676

DC-64

4

HD68450Y10*

* Preliminary

Compatibility

MC68000L6
MC6S000LS

HD68450Y12**
--- ----HD63463-4**

ACRTC

Function

4

.c

HOC

t
Package

6

...i

.9

Operating
Temp'erature
(OC)

HD68000-4

HD68450-6

~

Supply
Voltage
(V)

1'1068000-6

HD68450-4

DMAC

Clock
Frequency
(MHz)

-

S
DC; Ceramic DIP, PGA; Pin Grid Array,
CG; Glass-sealed Ceramic Leadl ••s Chip Carrier

$

HITACHI

14-BIT SINGLE-CHIP MICROCOMPUTER HMCS400 SERIES
The new CMOS 4-bit HMCS400 microcomputer series is
designed to satisfy the growing need for microcomputer
systems with large program capacity and for advanced applications. The HMCS400 series strengthens the proven capabilities
of the HMCS40 series, offering advanced software productive
architecture, enhanced peripheral functions, and high speed
instruction execution.
•
•

•
•

•
•
•

FEATURES
Architecturally Compatible with the HMCS40 Series for Convenient Replacement
One Cycle per Instruction Execution Utilizing 10-bit per
Instruction
Powerful ROM and RAM Addressing Capability

•
•

16 Subroutine Stack Levels
98 Instructions Including Logic Arithmetic and BCD Arithmetic Operating Instructions, and Pattern Generating
Instruction
Five Interrupt Levels (External: 2, TimelCounter. 2, Serial
Interface: 1)
8-bit Serial Interface (Clock Synchronous Type)
Two Timer/Counters: 8-bit Free Running Timer and 8-bit
Reload TimerlEvent Counter
58 1/0 Lines (26 High Voltage 40V 1/0 Lines)
High Speed Instruction Execution: 2"satV.. 5V, High Speed
Version (1.3 "s) Available
EPROM-on-Package Type Available for System Emuletion

•
•
•

-HMCS400 SERIES PRODUCT CHARACTERISTICS
HMCS404CL'

Family Name

:~S
u

~

-=

U

in
..J

Power Dissipation

Max. 1/0 Terminal Voltage
Operating Temperature Range
Packaga
ROM
I
Memory
RAM
Registers
Subroutine Stack Levels

(V)
(n.ax.) (mW)
(V)
(oC)
(bits)
(bits)

2.5 - 6.0
9
VCC -40
-20 - +75
FP-64, DP-64S
4096 x 10
256 x 4

~-

4-Bit Input
~

c

4·Bit Output

I/O Ports

0

.~

c

..."
Interrupts

r-------

HMCS404C'
CMOS
4-6

CMOS

Process Technology
Supply Voltaga

58

External

2
2
2
2
1
1
99
99
4
2
Built-in (External drive is possible)

Number of Instructions

Cycle Time (I's)
Clock Pulse Generator
Others
EPROM on the Package Typo

7
16
4xl
2xl
4x4
4x5
1 x 16

-20 - +75
FP·64, DP·64S
4096 x 10
256 x4
7
16
4xl
2 xl
4x4
58
4x5
1 x 16

4-Bit Input/Output
l-Bit InputlOutput

Timer/Counter
Interface
-_ ..Serial
_-----_
.. -

Instruction

18
- - VCC- 4O

HMCS404AC'
CMOS
4.5-5.5
27
VCC -40
-20 - +75
FP-64, DP-64S
4096 x 10
256 x 4
7
16
4xl
2xl
4x4
58
4x5
1 x 16
2
2
1
99
1.33

----

Power Saving Mode (Stop mode, Stand-by mode)
HD614POBOS'

·Prellmlnary

eHITACHI

677

4-BIT SINGLE-CHIP MICROCOMPUTER HMCS40 SERIES

The HMCS40 Series are high performance. low cost 4-Bit
Single-Chip Microcomputers designed for dedicated applications.
The HMCS40 Series Instruction Set provides convenient chip

selection and system expansion.
LCD-III/IV are LCD driver on chip microcomputers designed
for applications which need an LCD display device.

FEATURES
• Full Line-Up:

•

•
•
•

CMOS
2 - 4k Words ROM
160 - 256 Words RAM
32 - 44 I/O Lines
All Instructions (except Pattern Generation Instruction)
are Single cycle.
Pattern Generation Instruction (Table Reference Capability).
Powerful Interrupt Function.

•
•
•
•
•
•

3 Interrupt Sources .r2 External Interrupt Line
L.:J Timer/Counter
Low Power Dissipation (2mW): CMOS.
Low Operating Voltage Version (3V): CMOS.
Built-in Clock Pulse Generator (Resistor or Ceramic Filter).
Built-in Power-on Reset Circuitry.
I/O Options (User Selectable at Each Pin).
CMOS: Pull up Resistor/Open Drain/CMOS Output
Built-in LCD drive circuit: LCD-III/IV.

• HMCS40 SERIES PRODUCT CHARACTERISTICS
HMCS44CL
IHD44808)
HMCS44C
IHD44800)

Family Name

(Type Name)

"

.~

."l!l
~

~

U

Cii

..J

HMCS47CL
IHD44868)
HMCS47C
IHD44860)

HMCS46CL
IHD44848)
HMCS46C
IHD44840l

LCD·III .,
IHD44795,
HD44790)

LCD·IV
IHD61390

CMOS

CMOS

CMOS

CMOS

CMOS

Supply Voltage IVCC)

IV)

3/5

3/5

3/5

3/5

3/5

3/5

Power Dissipation ITyp.)

ImW)

0.32/2

0.32/2

0.32/4

0.32/4

0.36/2.4

0.9/5.0

Max. I/O Terminal Voltage

IV)

VCC + 0.3

VCC +0.3

VCC + 0.3

VCC + 0.3

VCC + 0.3

VCC + O.~

Operating Temperature Range * I

I'C)

-20 - +75

-20 - +75

-20 - +75

-20 - +75

-20 - +75

-20 - +7!

Process Technology

DP-42, DP·42S

FP-54,DP-64S

DP-42, DP·42S

FP·54, DP-64S

Fp·80

FP·80

(bit,)

2,048 x 10
128x 10"

2,048 x 10
128 x 10"

4,096 x 10

4,096 x 10

2,048 x 10
128x 10"

4,096 x

RAM

Ibits)

160 x4

160 x 4

256 x 4

256 x4

160 x4

256 x4

8

6

8

6

6

6

4

4

4

4

4

4

Registers
Stack Registers

Discrete Output

-

4·Bit Data Input/Output

4x4

4·Bit Data Input

Discrete Input
I/O Ports

"g"
0

""

4·Bit Data Output

32

Interrupts

External

Instruc-

Number of Instructions

tions

Cycle Time
Built-in Clock Pulse Generator

44

II'S)

4xl

-

32

4x6

-

44

4 xl

4xl

4 xl

32

-

-

32

4x2

1 x 16

1 x 16

1(

~

-

4x6

4x4

1 x 16

-

1 x 16

2
1

2
1

2
1

2
1

71

71

71

71

71

71

20/10

20/10

20/5

20/5

20/10

20/5

2
1

Timer/Counter

-

-

1 x 16

Discrete Input/Output

I.L

CMOS

ROM

Package
Memory

~

HMCS45CL
IHD44828)
HMCS45C
IHD44820)

4x"
-

-4x
-1 x

2
1

Power on Reset

No/Ves

No/Ves

No/Ves

No/Ves

Ves

No

Battery Back.up

Halt

Halt

Halt

Halt

Halt

Halt

HD44850E
HD44857E

HD44850E
HD44857E

HD44857E

HD44857E

HD44797E

HD447971

Evaluation Chip

*'

Wide Temperature Range (-40 - +85°C) version is available.
*2 Pattern Memory

*3 LCD DRIVE FUNCTION
LCD
Drive

Common

4

Segment

32

Duty

Bias
Display Capabil ity

Static, 1/2,1/3, 1/4
1/2,1/3
4x32 Matrix 11/4 Duty)

Expandable using the LCD Driver HD44100H .

678

•

HITACHI

LCD DRIVER SERIES
• LCD DRIVER SERIES CHARACTERISTICS
General

Type
Type Number

I

:1

Procell
Supply Voltage

-"
u

Operating Temperature
Package

.

iii
...J

--

Power Dissipation

(VI
(oCI
(mWI

.

I/O

CMOS
5"
-20 - +75
FP-l00
5.0

C~O_S_____

5. '
-20 - +75
FP-60
5.0

-

(bitsl

-

Interface (Driver Ie)

(External ROM, RAMI

u. Number of Instruction

Common
LCD Driver

CMOS

(bitsl

Interface

0

'ilc

HD81B02

RAM
Interface (CPU I
~

HD61100

ROM
Memory

Segment

Duly
Display Capability

Segment Display

HD44100H

8

8
2

2

-

-

-

-

40

80

Fr•• (N)

Free (N)

N x40

N x80

Matrix

(lIN Duty)

Matrix
(lIN Duty)

SR type

SR type

3- 5*1

-20- +76
FP-80
0.5 (5VI

HDBI803
t-S-",pS
3-5*1
-20 - +76
FP-60
0.5 (5VI

-

-

51 x4

84 x 1

14

10

-

-

4
4
51
St.tic, 1/2,
1/3,114
204

4
1
84

Segment
(1/4 Duty)

Static

HD44780
(~CD-III

CMOS
5. '
-2Q - +75"
FP-80
1.75
7200
(CGI"
80x 8/64
x 8(CGI"
11
4

11
16
40

--

1/8,1/11,

1/16
16 Digits

64 Segment

(6 x7 DolS
1/16 Duty)
Expandable

Comment

'1: Exc.pt Power Supply for LCD.
'2: -40 - +8SoC (Special Aequest). Pl.... contact Hitachi Agents.
'3: CG; Character G.nerator.

680

eHITACHI

--

to 80 Digits

using
HD44100H

- - - - - - - - - - - - - - - - - - - - - - - - - - - - L C D DRIVER SERIES

Character Display

HD44101H
~MOS
5"

-20 - +75

~O

------

Graphic Display

HD43160AH

HD44102CH

HD44103CH

HD44105H

HD61830

HD61102

HD61103

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

5"
-20-+75

5"

5"

5"

5"

-20 - +75
FP-60

5"
-20- +75

5"

-20 - +75
FP-80

-20 - +75

-20 - +75

FP·60

FP-60

FP·l00

-20 - +75
Fp·l00

FP·54

1.75

10.0

2.5

4.0

4.0

30.0

3.0

5.0

6720
ICG)"

6240
ICG)"

-

-

-

7360
ICG)"

-

-

32 x 8

80x8

200 x 8

-

-

("(ternal
65536 x 8)

512 x 8

-

12

21

21

6

6

13

21

6

4

5

-

5

5

9

18

-

6

6

-

33

8

12

7

15

-

-

-

5

-

-

20

-

32

50

1/8,1/12,
1'16

1/8,1/12,1/16,
1/24,1/32

1/8,1/12,1/16,
1/24,1/32

40
1/7,1/14
160i9it.
15x 7 Dots
1/14 Duty)
Expandable
to 32 Digits

using
HD44100H

-

32 x 50
Dots

11/32 Duty)

-

1/8,1/12,1/16,1/24,
1/32,1/48,1/64

-

Display to

80 Digits
using
HD44100H

-

-

Segment

Common

Oriver

Driver

Common
Driver

eHITACHI

,

64

-

64

-

Static,

-1/64

1/48,1/64
1/96,1/128

64.64
Dots
11/64 duty)

-

111 - 1/128

Display to
524288
Dots using
HD44100H

Segment
Driver

Common
Driver

681

[iC

MEMORIES

• MOSRAM
Mode

Static

Total
Bit

16k·bit

64k·bit

682

Type No.

Process

HM6116·2
HM6116·3
HM6116·4
HM6116L·2
HM6116L·3
HM6116L4
HM6116A-12
HM6116A·15
HM6116A·20
HM6116AL·12
HM6116AL·15
HM6116AL·20
HM6117-3 HM61174
HM6117L·3
HM6117L4
HM6168H45
HM6168H·55
CMOS
HM6168H-70
HM6168HL45
HM6168HL·55
HM6168HL-70
HM6167
HM6167-6
HM6167·8
HM6167L
HM6167L-6
HM6167L-8
HM6167H45
HM6167H·55
HM6167HL45
HM6167HL·55
HM6267·35
HM626745
HM6264-10
HM6264-12
HM6264-15
HM6264L-l0
HM6264L·12
HM6264L-15

Organiza~

Access

Cycle

ticn
(word x bit)

Time

Time

(ns) max
120
150
200
120
150
200
120
150
200
120
150
200
150
200
150
200
45
55
70
45
55
70
70
85
100
70
85
100
45
55
45
55
35
45
100
120
150
100
120
150

(ns) min
120
150
200
120
150
200
120
150
200
120
150
200
150
200
150
200
45
55
70
45
55
70
70
85
100
70
85
100
45
55
45
55
35
45
100
120
150
100
120
150

2048 x 8

4096 x 4

16384 xl

8192 x 8

eHITACHI

Supply
Voltage
(V)

Power
Dissipation
(W)

Package t
Pin No.

0.lm/0.2
0.lm/0.18
201lA/0.18
201lA/0.16

CG

G

• •
•• ••
•
•
•

P

0.lm/15m
24
5,,/10m

•

0.lm/0.2
10,,/0.18

+5

0.lm/0.25
20

•
•
•

FP SP

•
••
•
••

•
•
•••
•
•
•
•
•

5,,/0.25
5,,/0.25

•
•
•

0.lm/0.15

5,,/0.15
0.lm/0.2

20

• •
• •

5,,/0.2
0.lm/0.25
0.lm/0.2
28
10,,/0.2

•
••
• •
•• •
• •
• •
(Continued)

------------------------------IC
Total
Bit

Mode

Type No.

64k-bit

Dynamic

256k·bit

Process

HM48416A·12
HM48416A·15
HM48416A·20
HM41lt;4·2
HM4864·3
HM4864A·12
HM4864A·15
HM4864A·20
HM50256·12
HM50256·15
HM50256·20
HM50257·12
HM50257·15
HM50257·20

Organiza-

Access

Cycle

Supply

Power

tion

Time

Time

(ns) max
120
150
200
150
200
120
150
200
120
150
200
120
150
200

(ns) min
230
260
330
270
335
220
260
330
220
260
330
220
260
330

Voltage
(V)

Dissipation

(word x bit)
16384 x 4

65536 xl
NMOS

262144 x 1

(W)

20m/0.3

Package t
Pin No.

CG

P

G

20m/0.25
16

•
•
• •
• ••
•
•

•
••

20m/0.35

•
•

20m/0.36

FP

•
•
•
•
•
•
•
•
•
•
•
•
•
•

18

20m/0.33
+5

MEMORIES

SP

II HM6116LP/LFP Series: 10 IlW
t The package codes of eG, G, P, FP and SP are applied to the package materials as follows.
CG: Glass·sealed Ceramic Leadless Chip Carrier, G: Cerdip, P: Plastic DIP, FP: Plastic Flat Package (SOP), SP: Skinny Type Plastic DIP

• MOS ROM

Mode

Total
Bit
64k·bit

Mask

128k·blt
256k·bit
lM·bit
32k·bit

U.V. Erasable
& Electrically

64k-bit

128k·bit

256k-bit
On Time

64k-bit

Electrically

128k-bit

Electrically
Erasable &

64k·bit

Programmable

Type No.
HN61364
HN61365
HN61366
HN613128

Process

H N4827128-30'
HN58064·25
HN58064·30
HN580614-45

(word x bit)
8192 x 8

CMOS

HN61256
HN613256
HN62301 •
HN482732A·20
HN482732A·25
HN482732A-30
HN482764
HN482764·2
HN482764·3
HN27C64·15
HN27C64-20
HN27C64·25
HN27C64·30
HN4827128-25
HN4827128-30
HN4827128-45
HN27256·20
HN27256·25
HN27256-30
HN482764-3

Organization

16384 x 8
32768x8 or
65536 x 4
32768 x 8
131072 x 8

Access
Time
(ns) max
250
250
250
250

51t/50m
+5

51l/50m
2m/75m

8192 x 8

16384 x 8
NMOS
32768 x 8
8192 x 8
16348 x 8
8192 x 8

300
250
300
450

* Preliminary
t The package codes of C, G, P and FP are applied to the package material as follows.
C: Side·brazed Ceramic DIP, G: Cerdip, P: Plastic DIP, FP: Plastic Flat Package

~HITACHI

24

51t/50m
51t/7.5m

CMOS

C

G

28

250
350
200
250
300
250
200
300
150
200
250
300
250
300
450
200
250
300
300

4096 x 8

NMOS

(V)

Package

Power
Dissipation
(W)
Pin No.

3500

NMOS

NMOS

Supply
Voltage

0.18/0.8

28

24

0.18/0.55
+5
0.55m/0.l

28

t
P

FP

• •
•

•
• •
•• ••
•
•
•
•
•
•
•
•
•
•
•
•
•

0.18/0.53

••
•

0.22/0_55
+5

+5

0.18/0.55

28

0.18/0.53
0.22/0.55

28

·

••
•
•
•

683

Ie MEMORIES-----------------------------------------------------------•

BIPOLAR RAM

level

Total
Bit
256

1k

ECl
10k
4k

16k

1k

Eel
100k

4k

16k

Type No.
HM10414
HM10414-1
HM2110
HM2110-1
HM2112
HM2112-1
HM10422
HM10422-7
HM10470
HM10470-1
HM10470-25
HM2142
HM10474
HM 10474-8*
HM10474-10*
HM10480
HM10480-15*
HM10480-20*
HM10484-15*
HM10484-20*
HM100415
HM100422
HM100470
HM100474
HM100480
HM100480-15*
HM100480-20*
HM100484-15*
H M 100484-20 *

Organization
(word x bit)

Output

Access
Supply
Time
Voltage
(V)
(ns) max

256 x 1

1024 x 1

256 x4

4096 x 1

1024 x 4
- - - --

16384 x 1

Open
Emitter

4096 x 4
1024 x 1
256x 4
4096 x 1
1024 x 4
16384 x 1
4096 x 4

10
8
35
25
10
8
10
7
25
15
25
10
25
8
10
25
15
20
15
20
10
10
25
25
25
15
20
15
20

* Under development
t The package codes of F, G, P and CC are applied to the package materials as follows.

F: Flat Package, G: Cerdip, P: Plastic DIP, CC: Ceramic Leadless Chip Carrier .

684

•

HITACHI

Power
Package t
Dissipation
tmW/bit) Pin No. F
P
G
2.8
0.5

16

0.8

-5.2

0.8
1.0

24

0.2

18

0.3
0.2

20

0.3

24

0.05
0.06

-4.5

20

0.06

28

0.6
0.8
0.2
0.2
0.05

16
24
18
24

0.06
0.06

20
28

•
•
•
•••
•• ••
•
•
•
•
•
•
• •
••
••
•
• •
•
•• •
••
•
•
•

CC

.'

••

•

/GATE ARRAY
CMOS Gate Array HD61J/HD61K/HD61L/HD61MM Series
•
•

FEATURES
Fast operation
Internal gate (2-input NAND, FO=3, AL=3mm) .. 3.5ns typ
Input buffer (FO=3, AL =.3mm) ..••.•....... 9ns typ
Output buffer (Cl =50pF). . . . . . . . . . . . . . . .• 20ns typ
Memory access time (HD61MM) ...........•... 60ns typ
• Low power dissipation
At 10MHz operation (Internal gate) ...... 13~W/gate typ
• Abundant input and output configuration
Allocation of all pins except power supply pins to input/
output/input-output
Output can be CMOS/open drain/3-state

•

•
•

•

•
•

Memory on-chip (HD61MM)
Flexibility of memory capacity and word organization
Selection of single port/dual port memory
Wide operation temperature range
-20 to +75'C
Wide package selection
Especially plastic packages with high pin
count •...••.... DILP64/FPP100
Powerful design support
User-Defined-Macro
Test pattern evaluation with fault simulator
Design support at local Design Center
Quick turn around time and reasonable development cost

LINE UP
Gate count
I/O pin count
RAM on chip

Package

HD61J
504
50

HD61K
1080
68

HD61L
1584
68

a

a

-

HD61MM*
2496
104
available

0

0
0

0
0
0

0

0

-

-

0

0

-

-

DP28
DP42
DP64
FP54
FP80
FP100
DC28
DC40
PGA72
PGA120

-

-

-

-

0
0

0
0

0
0

0*
0
0

-

-

-

0*

-

-

Power supply pin

4

a

4

8*

... Preliminary

Bi-CMOS Gate Array HD27K/HD27L/HD27P/HD27Q Series
• FEATURES
• High speed with super low power dissipation _ ..•..•....
• Internal gate: 4.0ns (Fan out=3)
@0.05mW
• Input buffer: 5.0ns (Fan out=3)
@2.6mW
• Output buffer: 8.0ns (Cl =15pF)
@2.6mW
• LS TTL compatible input/output ........•....•.....
• Selectable totem-pole/3-state/open collector output
• IOl =8mA: Capable of driving 20 LS TTL's

•
•

•

•

•

•

Output buffer can construct logic functions.
• Saves gate stages.
A variety of macrocell library
• Internal gate: 44
• Output buffer: 9
A variety of reliable package
• Plastic 01 P 16 to 64 pins
• Plastic FP 60 to 100 pins (under development)
A variety of DA'system support
• Only logic diagrams and test patterns needed as an interface
with the user.
Short development time

HITACHI

685

GATEARRAY----------------------------------------------------------Number of gates

Number
of Vee
and GND
pins

Package

Input
buffer

Output
buffer

HD27K

200

18

18

2

16,20,28,
42 pins

HD27L

528

30

30

4

28,42,64
pins

60,80 pins

HD27P

966

40

40

4

28,42,64
pins

60,80,100
pins

HD27Q

1530

50

50

4

28,42,64
pins

60,80,100
pins

*Under development

686

•

HITACHI

DIP
(Plastic)

Fp·

I nternal gate
(2-input NAND)

(Plastic)

-

LSI FOR SPEECH SYNTHESIZER SYSTEM
PMOS 3-chip System
• OUTLINE OF BASIC DEVICE
Type name

Function

HD388808

Speech
synthesizer

HD38884P

Explanation of function

Outline

Synthesizes speech by reading out a prescribed c~aracteristic parameter
from the ROM chip according to the command from the microcomputer.

DC-28
DP-28

128k-bit
ROM

Analyzes the speech which should be synthesized in advance and stores the
extracted characteristic parameter.

DP-28

HD38882P

EPROM
interface

Capable of 1M-bit connection when using EPROM.

DP-42

HMCS40'
Series

Controller

Performs overall control to synthesize special speech under suitable
conditions.

.

*See 4..tJit microcomputer item.

•

System Features

•

High speech quality
Since a PAR COR system is employed and the bit rate can be
taken up to 2400-9600 bits/sec, excellent tone quality is
made possible.
Synthesizing woman's voice
In addition to a man's voice, synthesizing woman's voice is
possible with the adoption of the vocal tract loss effect.
Variation of speaking speed
Speech can be spoken slowly or rapidly by microcomputer
control.
Vocalization with accurate scale
By producing voice pitch through external synchronization,
accurately scaled singing is possible.

•

•

•

•

•

Long-period voice cepecity
A maximum of 16 ROMs can be connected without an interface circuit. Vocal sound of 50-100 seconds (2400 bit/sec)
can be synthesized with 1 ROM.
Speaker direct drive
The speaker is directly driven by the built-in D/A converter and
speaker driving circuit. Excellent tone quality and power is
possible by providing an external 0/A converter and speaker
driving circuit utilizing the digital output.

• BASIC SYSTEM COMPOSITION EXAMPLES
• Case of using mask ROM

• Case of using EPROM

Ceramic
OICIII8tor

Ceramic
Oscillator
ZL .. 1QOn

AI\ItOO Output

'\

~===:Q]))I.

HMCS40Sllrles
{Controller!

HMCS4Q

Se,'"

IControlierl

HD38884
U28k bit AOMI

HN482764

x 16 mex

AMP

JC16maM

I'

•

HITACHI

687

LSI FOR SPEECH SYNTHESIZER S Y S T E M - - - - - - - - - - - - - - - - - - - - - • SYSTEM SPECIFICATIONS
Item

Content

System

PARCOR system

Voice channel model

8th stage/10th stage digital filter .............................. Selectable
Vocal tract loss effect (existence/non-existence) , ................. Selectable

Voice source model

Voice sound ...... Rectangular wave/triangle wave
Voiceless sound
White noise

...

Sampling frequency

.............

Selectable

8 kHz

Bit rate (b/s)
Frame period (ms)

2400

4800

9600

20

10/20

10

Variable speaking speed

Variation of frame period is possible from -30"A> to +60% by 1O"A> steps.

Pitch

I ntegral times of 125 /ls/External synchronization

Speaking time

50-100 sec/ROM (2400 b/s)

............. .. . Selectable

CMOS 1-chip System
• OUTLINE OF BASIC DEVICE
Type No.

Function

HD61885

Speech

HD61887

Synthesizer

(HD44881)

128k-bit ROM

Explanation of function
Synthesizes speech by reading out a prescribed characteristic parameter from the internal or external ROM according to the command
from the microcomputer or key switch.
(Expanding ROM)
Performs overall control to synthesize special speech under suitable
conditions .

•

SYSTEM FEATURES

•

1-chip system
Including synthesizer, 32k-bit ROM and interface circuit.
High speech quality
Since a PARCOR system is employed and the bit rate can be
taken to 1250--9900 bitl sec, excellenttone quality is possible.

•

•

•

688

Content
PARCOR system
10th stage digital filter
10 kHz
1,250 - 9,900
10/20
-25%, 0, +25%
10-20sec (internal ROM)
5V single (3.6 - 5.5V operation)

•

DP-28
FP-54
DP-28

Long-period voice capecity
A maximum 16 ROMs can be connected without an interface
circuit. Vocal sound of 50-100 seconds can be synthesized
with 1 ROM.
Low power dissipation (Standby mode)

• SYSTEM SPECIFICATIONS
Item
System
Voice channel model
Sampling frequency
Bit rate (b/s)
Frame period (ms)
Variable speaking speed
Speaking time
Supply Voltage

Outline

HITACHI

- - - - - - - - - - - - - - - - - - - - - L S I FOR SPEECH SYNTHESIZER SYSTEM
• BASIC SYSTEM COMPOSITION EXAMPLES
-Code Input

- Key Input

Ceramic

Oscillator

r-- -- -

---,

,-- ---

I

I
I
I

I
I

I
I

I
H044881

1128k-bl1 ROM

16max'

I

I

I

I

I
I
I
I

:
JI

I
I

I

I

I

:

--,

I
I

I

I
I
I

:

I

IL _____._____________ JI

I
I

H044881

I

I
I

I
I
I

:

1

~-----------------~

_ Microcomputer Control

Vee

HMCS40 Seriel
(Controllerl

r---

-- -

I
I

I

I
I
I

I

u

I
I
I

I
I

I
I
I

:

---,
I
I

:

I
I
HD44881

I

I
I

!

IL _____________________ JI

•

HITACHI

689

ICODEC/F I LTER

COMBO LSI

• LINE UP
Clock

Seri ..

TYPINo.

Compo

Law

H044210

HD44211A
H044212A

H044220

H044222

,.
,.

H044231B

A

H044232B
H044233B

A

H044230

H044234B
H044235
H044236
H044237
H044238
H044231C
H044232C
H044233C

H044230C

H044240C

H044234C
H044235C
H044236C
H044237C
H044238C
H044240C

A

,.

,.
,.
,.
,.
,.
A
,.

Power

CR

Voltage

(mWI

Filter

Reference

150

-

-

40

-

External

Dissipation

Sync.1
Async.

Internal

Clock
External

128 kHz req.

PLL

60

0

0

Divider

64 - 204BkHz

-

DC·24

Both

64 - 2048kHz

Decoder Shift

DC·16

1536/1544/2048kHz

-

Both

Sync.
50

0

0

PLL

f---

64 - 2048kHz

Bo.h

Decoder Shift

Decoder Shift

DG·16

Sync.

Divider

A

-

1536/1544/2048kHz

-

Both

60

0

0

-

Sync.

PLL

A

)---

,.

64- 2048kHz

Both

60

0

0

PLL

A-law; Europe" International Telephone.
,.·Iaw ; U.S.A., Canada" Japan

690

Package

Both

)---

A

,.

Signaling

Sync.

A
A

PCM Bit
Clock Required

•

HITACHI

Both

Decoder Shift

Decoder Sh ift

64 - 2048kHz

AlB D.'a 110

DG·20

HITACHI AMERICA, LTD.
SEMICONDUCTOR AND IC SALES & SERVICE DIVISION
HEADQUARTERS
Hitachi, Ltd.
Nippon Bldg., 6-2, 2-chome
Ohtemachi, Chiyoda~ku, Tokyo, 100, Japan
Tel: 212-1111
Telex: J22395, J22432

REGIONAL OFFICES
~ORTHEAST

REGION
Hitachi America, Ltd.
5 Burlington Woods Dr.
Burlington, MA 01803
617/229-2150

SOUTHERN REGION
Hitachi America, Ltd.
Two Lincoln Centre, Suite 865
5420 LBJ Freeway
Dallas, TX 75240
214/991-4510
NORTH CENTRAL REGION
Hitachi America, Ltd.
500 Park Blvd., Suite 415
Itasca, IL 60143
3121773-4864
NORTHWEST REGION
Hitachi America, Ltd.
2099 Gateway Place, Suite 550
San Jose, CA 95110
408/277-0712
SOUTHWEST REGION
Hitachi America, Ltd.
Warner Center Plaza One
21600 Oxnard St., Suite 600
Woodland Hills, CA 91367
8181704-6500

692

U.S. SALES OFFICE
Hitachi America, Ltd.
Semiconductor and IC Sales & Service Division
1800 Bering Drive
San Jose, CA 95112
Tel: 408/292-6404
Telex: 17-1581
Twx: 910-338-2103
Fax: 408-2922133
Fax: 408-2949618

DISTRICT OFFICES
•

Hitachi America, Ltd.
1700 Galloping Hill Rd.
Kenilworth, NJ 07033
201/245-6400

•

Hitachi America, Ltd.
3500 W. 80th Street, Suite 175
Bloomington, MN 55431
612/831-0408

•

Hitachi America, Ltd.
80 Washington St., Suite 101
Poughkeepsie, NY 12601
914/485-3400

•

Hitachi America, Ltd.
1 Parkland Blvd., #1222E
Dearborn, MI 48126
313/271-4410

•

Hitachi America, Ltd.
6200 Savoy Dr., Suite 850
Houston, TX 77036
713/974-0534

•

Hitachi America, Ltd.
5775 Peachtree Dunwoody Rd.
Suite 270-C
Atlanta, GA 30342
404/843-3445

•

Hitachi America, Ltd.
4901 N.W. 17th Way
Fort Lauderdale, FL 33309
305/491-6154

•

Hitachi America, Ltd.
18004 Skypark Circle, Suite 200
Irvine, CA 92714
714/261-9034



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