1986_IDT_High Performance_CMOS_Data_Book 1986 IDT High Performance CMOS Data Book
User Manual: 1986_IDT_High-Performance_CMOS_Data_Book
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Integrated
Device
Technology
MICROSLlCE~
II
II
II
Digital Signal Processing (DSP)
III
Logic
II
Technology/Capabilities
Static RAM
Data Conversion
Subsystems Modules
General Product Infonnation
II
fI
II
Integrated Device Technology, Inc.
HIGH-SPEED CMOS
DATA BOOK
3236 Scott Boulevard, Santa Clara, California 95054
Telephone: (408) 727-6116. TWX: 910-338-2070. FAX: (408) 988-3029
Printed in U.S.A. 8/86
@ 1986 Integrated Device Technology, Inc.
CONTENTS OVERVIEW
This book has been organized into sections by product families, with
additional sections providing numerous aids to assist in a better understanding
of our high-performance CMOS devices. These include descriptions of lDT's
commitment to providing the highest levels of technology, quality and service in
the industry; our CEMOS™ and surface mount technologies; facilities and
capabilities; product selector guides; article reprints; application and technical
notes; quality flows and testing; package-related data and ordering information.
Two separate indexes have also been provided to ensure ease of use of this data
book. One is organized by product line and function within the product line; the
other is a numerical index. As a further aid, industry cross reference guides are
provided by product family.
Three different types of data sheets are contained in this book:
ADVANCE INFORMATION - Contain initial descriptions for products that are
in development, including features, pinouts and block diagrams.
PRELIMINARY - Contain minimum and maximum limits, based upon initial
device characterization, which are subject to change upon full characterization
over the specified supply and temperature range.
FINAL - Contain minimum and maximum limits specified over the complete
supply and temperature range for full production devices.
New products, product performance enhancements, additional package types
and new product families are being introduced frequently. Please contact your
10caiiDT sales representative or call our factory at 1-80Q-IDT-CMOS to determine
latest device specifications, package types and product availability.
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in
order to improve design or performance and to supply the best possible product. lOT does not assume any responsibility for use of
any circuitry described other than the circuitry embodied in an lOT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent, patent rights, or other rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
I ntegrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a
specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of lOT.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
CEMOS, MICROSLlCE, SPC, and SYSTEM-SLICE are trademarks of Integrated Device Technology, Inc.
SPC (Special Protocol Channel) has a patent pending.
FAST is a trademark of Fairchild Semiconductor Co.
TABLE OF CONTENTS
CONTENTS
PAGE
Contents Overview
Disclaimer
Life Support Policy
Table of Contents
Alphanumeric Listing by Product Line ............................................................... ii
Numerical Index ....•........................................................................•.... vi
Product Selector Guides ............................................................................. x
Cross Reference Guides
Static RAM .......•..................••.....................•........................•............ xix
MICROSLICE™ .....................................................•.................•..•..•..... xxii
DSP .•...............•........................................................................... xxiii
Technology/Capabilities
IDT... Leading the CMOS Future .....................................................................
IDT Leading Edge CEMOS Technology .............................................................•..
Radiation Hardened Technology •..•................................................................
Surface Mount Technology ...........................•...............................•.............
State-of-the-Art Facilities and Capabilities ......•.....................................................
Superior Quality and Reliability ....•................................................................
1-1
1-2
1-5
1-5
1-6
1-7
Static RAMs
IDT6116A
16K (2Kx8) Static RAM ...................................................... .
IDT6167A
16K (16Kx1) Static RAM .........................................•............
IDT6168A
16K (4Kx4) Static RAM .............................................•........•
IDT71256
256K (32Kx8) Static RAM .................................................... .
IDT71257
256K (256Kx1) Static RAM ................................................... .
IDT71258
256K (64Kx4) Static RAM ........................................•........•...
IDT7130/40
8K (1 Kx8) Dual-Port Static RAM .............................................. .
IDT7132/42
16K (2Kx8) Dual-Port Static RAM .....................................•..•.....
IDT71322
16K (2Kx8) Dual-Port Static RAM ............................................. .
IDT7133/43
32K (2Kx16 & 4Kx8) Dual-Port Static RAM ..................................... .
IDT7134
32K (4Kx8) Dual-Port Static RAM .....................................•........
IDT71341
32K (4Kx8) Dual-Port Static RAM ............................................. .
IDT7164
64K (8Kx8) Static RAM ..............................................•........
IDT7165
64K (8Kx8) Static RAM ...................................................... .
I DT71681A/82A
16K (4Kx4) Static RAM ...........................•..•...........•..•....•...•
IDT7174
64K (8Kx8) Static RAM ...................................................... .
IDT7187
64K (64Kx1) Static RAM ..................................................... .
IDT7188
64K (16Kx4) Static RAM ..........................•........•.•......•.........
IDT7198
64K (16Kx4) Static RAM ..............•................•...•..................
IDT71981/82
64K (16Kx4) Static RAM .....•.........•....................•.................
Ordering Information ....•.................................•.........................................
2-1
2-8
2-15
2-23
2-25
2-27
2-29
2-41
2-51
2-53
2-55
2-57
2-59
2-67
2-73
2-82
2-89
2-95
2-101
2-108
2-115
MICROSLICETII (Bit-Slice Microprocessors)
IDT39C01C/D/E
IDT39C02A
IDT39C03A/B
IDT39C09A/B
IDT39C10B/C
IDT39C11NB
4-Bit Microprocessor Slice .......•..•..•.....•................................
Carry Lookahead Generator .......................................•..........
4-Bit Microprocessor Slice ..........•.........................................
4-Bit Sequencer ..............•..............................................
12-Bit Sequencer .............•..............................•...•.•..••.•..•
4-Bit Sequencer ............................................................ .
II
3-1
3-12
3-15
3-47
3-61
3-47
TABLE OF CONTENTS (CONT'D)
CONTENTS
MICROSLICET• (Cont'd.)
PAGE
IDT39C203/A
4-Bit Microprocessor Slice ....................................................
IDT39C60
16-Bit Cascadeable E.D.C .....................................................
IDT39C705A/B
16x4 Register File Extension ..................................................
IDT39C707/A
16x4 Register File Extension ..................................................
IDT49C25
Microcycle Length Controller .................................................
IDT49C401/A
16-Bit Microprocessor Slice ...................................................
IDT49C402/A
16-Bit Microprocessor Slice ...................................................
IDT49C403/A
16-Bit Microprocessor Slice ...................................................
IDT49C404
32-Bit Microprocessor Slice ...................................................
IDT49C410/A
16-Bit Sequencer ............................................................
IDT49C460/A
32-Bit Cascadeable E.D.C .....................................................
Ordering Information ............................................................................... .
3-71
3-73
3-99
3-99
3-101
3-103
3-113
3-124
3-126
3-128
3-138
3-157
Digital Signal Processing (DSP)
IDT7201A/02A
512x9 & 1024x9 Half-Full Flag FIFO ........................................... .
IDT7201102
512x9 & 1024x9 Parallel In-Out FIFO .......................................... .
IDT7203/04
2Kx9 & 4Kx9 Parallel In-Out FIFO ............................................ .
IDT72064/65
64-Bit Floating Point ........................................................ .
IDT7209
12x12 Parallel Multiplier-Accumulator ......................................... .
IDT721 0/43
16x16 Parallel Multiplier-Accumulator ......................................... .
IDT72103/04
2Kx9 & 4Kx9 Half-Full Flag FIFO ............................................. .
IDT7212113
12x12 Parallel Multiplier ..................................................... .
IDT7216/17
16x16 Parallel Multiplier ..................................................... .
IDT72264/65
64-Bit Floating Point ........................................................ .
IDT72401/02/03/04
64x4 & 64x5 Parallel In-Out FIFO ............................................. .
IDT72413
Parallel 64x5 FIFO .......................................................... .
Ordering Information ............................................................................... .
Logic
IDT39C821
10-Bit Non-inverting Register .................................................
10-Bit Inverting Register ......................................................
IDT39C822
IDT39C823
9-Bit Non-inverting Register ..................................................
IDT39C824
9-Bit Inverting Register .......................................................
IDT39C825
8-Bit Non-inverting Register ..................................................
8-Bit Inverting Register .......................................................
IDT39C826
IDT39C841
10-Bit Non-inverting Latch ....................................................
IDT39C842
10-Bit Inverting Latch ....................................................... .
IDT39C843
9-Bit Non-inverting Latch .................................................... .
IDT39C844
9-Bit Inverting Latch ........................................................ ,
8-Bit Non-inverting Latch .................................................... .
IDT39C845
IDT39C846
8-Bit Inverting Latch ........................................................ .
IDT39C861
10-Bit Non-inverting Transceiver .............................................. .
IDT39C862
1Q-Bit Inverting Transceiver ............•......................................
IDT39C863
9-Bit Non-inverting Transceiver ............................................... .
IDT39C864
9-Bit Inverting Transceiver ................................................... .
IDT49C818
Octal Register with SPC'· ............................................•........
IDT54/74AHCT138
1-of-8 Decoder ............................................................. .
I DT54/74AHCT139
Dual 1-of-4 Decoder ........................................................ .
IDT54/74AHCT1611163 Synchronous Binary Counter ................................................ .
IDT54174AHCT182
Carry Lookahead Generator ................................................. .
Up/Down Binary Counter .................................................... .
IDT54/74AHCT191
Up/Down Binary Counter ............................................•........
I DT54/74AHCT193
IDT54174AHCT240
Octal Buffer ................................................................ .
I DT54174AHCT244
Octal Buffer ................................................................ .
iii
4-1
4-11
4-21
4-31
4-35
4-42
4-50
4-52
4-61
4-71
4-75
4-77
4-78
5-1
5-1
5-1
5-1
5-1
5-1
5-7
5-7
5-7
5-7
5-7
5-7
5-13
5-13
5-13
5-13
5-18
5-20
5-24
5-27
5-31
5-35
5-39
5-43
5-47
TABLE OF CONTENTS (CONT'D)
CONTENTS
Logic (CONT'D.)
PAGE
IDT54174AHCT245
IDT54/74AHCT273
IDT54174AHCT299
IDT54174AHCT373
IDT54174AHCT374
IDT54174AHCT377
IDT54174AHCT521
IDT54174AHCT533
IDT54174AHCT534
IDT54/74AHCT573
IDT54/74AHCT574
IDT54/74AHCT640
IDT54/74AHCT645
IDT54/74FCT138/A
IDT54174FCT139/A
Octal Bidirectional Transceiver ................................................
Octal D Flip-Flop ..............................................••............
Universal Shift Register ................................•.....••...............
Octal Transparent Latch ......................................................
Octal D Flip-Flop .....................•......................................
Octal D Flip-Flop ......•...•....•.........•.....................•.....•......
8-Bit Comparator ........................................................••..
Octal Transparent Latch ......................................................
Octal D Flip-Flop ..•...................•.........................•....•......
Octal Transparent Latch ......................................................
Octal D Register .............................................................
Octal Bidirectional Transceiver ................................................
Octal Bidirectional Transceiver ................................................
1-of-8 Decoder ..............................................................
DuaI1-of-4 Decoder ..............................•.......•..................
IDT54/74FCT161/163/A Synchronous Binary Counter .................................................
IDT54174FCT182/A
Carry Lookahead Generator ..................................................
IDT54/74FCT191/A
Up/Down Binary Counter .....................................................
IDT54174FCT193/A
Up/Down Binary Counter .....................................................
IDT54/74FCT240/A
Octal Buffer ...............•.................................................
IDT54174FCT244/A
Octal Buffer .................................................................
IDT54174FCT245/A
Octal Bidirectional Transceiver ................................................
IDT54174FCT273/A
Octal D Flip-Flop ........•.............................•...............•.....
IDT54174FCT299/A
Octal Universal Shift Register ..........................•.....................•
IDT54174FCT373/A
Octal Transparent Latch ......................................................
IDT54174FCT374/A
Octal D Flip-Flop ........................•...........•.......................
IDT54/74FCT377/A
Octal D Flip-Flop ...•....•..........••.................••.........•..........
IDT54174FCT521/A
8-Bit Comparator ••.•.......•.•••........•.....................•.............
IDT54174FCT533/A
Octal Transparent Latch .....•.......................................•........
IDT54174FCT534/A
Octal D Flip-Flop ............•.........•••..•..•....•.......•.•..............
IDT54174FCT573/A
Octal Transparent Latch ................................••.........•..........
IDT54174FCT574/A
Octal D Register ..••...................................•.......•......•...•.•
IDT54174FCT640/A
Octal Bidirectional Transceiver ................................................
IDT54174FCT645/A
Octal Bidirectional Transceiver ................................................
IDT54/74FCT821B
10-Bit Non-inverting Register ........••.............•................•........
IDT54174FCT822B
1Q-Bit Inverting Register •....•...............................•.............•..
IDT54174FCT823B
9-Bit Non-inverting Register .............................•..........•.........
IDT54174FCT824B
9-Bit Inverting Register •......•.........•............•........................
IDT54/74FCT825B
8-Bit Non-inverting Register ........•••.......................................
IDT54174FCT826B
8-Bit Inverting Register •..•••.......•.........................................
IDT54174FCT841B
1O-Bit Non-inverting Latch ...........••.............•............••.....••....
IDT54174FCT842B
10-Bit Inverting Latch ............................................•......•....
IDT54174FCT843B
9-Bit Non-inverting Latch ................•.....•.....•........................
IDT54174FCT844B
9-Bit Inverting Latch .........................................................
IDT54174FCT845B
8-Bit Non-inverting Latch. . . . . . . • • • • . . . . . . • • . • . . . . . . . . . • • . . . . . . . . . . . . . • . . . . . • ..
IDT54/74FCT846B
8-Bit Inverting Latch ..............•.........•...............•••......••......
IDT54174FCT861 B
1Q-Bit Non-inverting Transceiver.. .. . . . . . • .. .. . . . . . . . . . . .. .. . . . . . . . . . . .. . . . . . ..
IDT54/74FCT862B
1Q-Bit Inverting Transceiver ...................................................
IDT54174FCT863B
9-Bit Non-inverting Transceiver ................................................
IDT54174FCT864B
9-Bit Inverting Transceiver •. , .................................................
IDT54/74AHCT/FCT Family Test Circuits and Waveforms ........•...........••......•.....•.......•.....
Ordering Information ..................................................................••............
Iv
5-50
5-53
5-57
5-61
5-65
5-69
5-73
5-76
5-80
5-84
5-88
5-92
5-95
5-98
5-102
5-105
5-109
5-113
5-117
5-121
5-125
5-129
5-133
5-137
5-141
5-145
5-149
5-153
5-156
5-160
5-164
5-168
5-172
5-176
5-180
5-180
5-180
5-180
5-180
5-180
5-186
5-186
5-186
5-186
5-186
5-186
5-192
5-192
5-192
5-192
5-197
5-198
TABLE OF CONTENTS (CONT'D)
CONTENTS
Data Conversion
PAGE
IDT75C18/28
8-Bit 125MHz Video DAC ..................................................... 6-1
Ordering Information ................................................................................ 6-3
Subsystems Modules
IDTlMP624
IDTlM134/135
IDTlM136/137
IDTlM144/145
IDTlM203/204
IDTlM205/206
IDTlM624
IDTlM656
IDTlM812/912
IDTlM824
IDTlM856
I DTlM864/8M864
IDT8MP624/612
IDT8MP656/628
IDT8MP824
IDT8M624/612
IDT8M656/628
IDT8M824
IDT8M856
Ordering Information
1 Megabit (64Kx16, 128Kx8 or 256Kx4) Plastic Static RAM Module ............... .
64K (8Kx8) & 128K (16Kx8) Dual-Port RAM Module ............................ .
128K (16Kx8) & 256K (32Kx8) Dual-Port RAM Module .......................... .
64K (8Kx8) & 128K (16Kx8) Slave Dual-Port RAM Module ....................... .
2Kx9 & 4Kx9 Parallel In-Out FIFO ............................................ .
8Kx9 & 16Kx9 Parallel In-Out FIFO ........................................... .
1 Megabit (64Kx16, 128Kx8 or 256Kx4) Static RAM Module ...................... .
256K (16Kx16, 32Kx8 or 64Kx4) Static RAM Module ............................ .
512K (64Kx8 or 64Kx9) Static RAM Module .................................... .
1 Megabit (128Kx8) Static RAM Module ....................................... .
256K (32Kx8) Static RAM Module ............................................ .
64K (8Kx8) Static RAM Module ............................................... .
512K (32Kx16) Plastic Static RAM Module ..................................... .
256K (16Kx16) & 128K (8Kx16) Plastic Static RAM Module ....................... .
1 Megabit (128Kx8) Plastic Static RAM Module ................................. .
1 Megabit (64Kx16) & 512K (32Kx16) Static RAM Module ........................ .
256K (16Kx16) & 128K (8Kx16) Static RAM Module ............................. .
1 Megabit (128Kx8) Static RAM Module ....................................... .
256K (32Kx8) Static RAM Module ............................................ .
7-1
7-3
7-13
7-15
7-18
7-28
7-29
7-35
7-41
7-46
7-49
7-55
7-60
7-62
7-64
7-66
7-68
7-75
7-77
7-83
General Product Information
Application Notes
AN-01
Understanding the IDTl201/02 FIFO ....................................................
AN-02
Dual-Port RAMs Simplify Communication in Computer Systems. . . . . . . . . . . . . . . . . . . . . . . . . ..
AN-03
Trust Your Data with a High-Speed CMOS 16-, 32- or 64-Bit EDC ..........................
AN-04
High-Speed CMOS TTL-Compatible Number-Crunching Elements for Fixed and
Floating Point Arithmetic ............................................................
AN-05
Separate 1/0 RAMs Increase Speed and Reduce Part Count ...............................
AN-06
16-Bit CMOS Slices--New Building Blocks Maintain Microcode Compatibility
Yet Increase Performance ...........................................................
AN-07
Cache Tag RAM Chips Simplify Cache Memory Design ...................................
Tech Note
Using Two Chip Selects on the IDT7198 .................................................
8-1
8-9
8-19
8-27
8-33
8-38
8-44
8-53
Article Reprints
CMOS Logic with Bipolar-enhanced 1/0 Rivals Fast TTL Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-density Modules Suit Military Applications ......................................................
High-speed FIFOs Contend with Widely Differing Data Rates ...........................................
16x16-Bit Multipliers Fabricated in CMOS Rival the Speed of Bipolars ...................................
8-55
8-61
8-67
8-71
Quality Conformance Program
Commitment to Quality ............................................................................
Summary Plastic Processing Flow ................................................................
Summary of Monolithic Hermetic Product Processing Flow ..........................................
Improved Tolerance of Integrated Device Technology Products for High-Radiation Environments ...........
System Considerations in the Testing of Fast CMOS Devices ...........................................
Thermal Performance Data of Integrated Device Technology Packages ............. . . . . . . . . . . . . . . . . . . . ..
8-76
8-77
8-83
8-90
8-92
8-93
Package Diagram Outlines ........................................................................... 8-95
General Ordering Information ........................................................................ 8-113
Factory Direct Offices, Domestic and International Representatives, Authorized Distributors ................. 8-114
v
NUMERIC TABLE OF CONTENTS
PART #
39C01C/D/E
39C02A
39C03A/B
39C09A1B
39C10B/C
39C11A/B
39C203/A
39C60
39C705A/B
39C707/A
39C821
39C822
39C823
39C824
39C825
39C826
39C841
39C842
39C843
39C844
39C845
39C846
39C861
39C862
39C863
39C864
49C25
49C401/A
49C402/A
49C403/A
49C404
49C410/A
49C460/A
49C818
54/74AHCT138
54174AHCT139
54174AHCT161
54174AHCT163
54/74AHCT182
54/74AHCT191
54/74AHCT193
54/74AHCT240
54/74AHCT244
54/74AHCT245
54/74AHCT273
54/74AHCT299
54/74AHCT373
54174AHCT374
54/74AHCT377
54174AHCT521
54/74AHCT533
54/74AHCT534
54/74AHCT573
PAGE
4-Bit Microprocessor Slice ........................................................
Carry Lookahead Generator ......................................................
4-Bit Microprocessor Slice ........................................................
4-Bit Sequencer .................................................................
12-Bit Sequencer ............................................•...................
4-Bit Sequencer ................................................•.........•......
4-Bit Microprocessor Slice ........................................................
16-Bit Cascadeable E.D.C. ........................................................
16x4 Register File Extension ......................................................
16x4 Register File Extension ......................................................
10-Bit Non-inverting Register ......................................................
10-Bit Inverting Register ..........................................................
9-Bit Non-inverting Register .......................................................
9-Bit Inverting Register ...........................................................
8-Bit Non-inverting Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-Bit I nverting Register ...........................................................
10-Bit Non-inverting Latch ........................................•.....•.........
10-Bit Inverting Latch .............................................................
9-Bit Non-inverting Latch .........................................................
9-Bit Inverting Latch •............................................................
8-Bit Non-inverting Latch ...............•.........................................
8-Bit Inverting Latch ..•......•...................................................
10-Bit Non-inverting Transceiver ...................................................
10-Bit Inverting Transceiver .......................................................
9-Bit Non-inverting Transceiver ....................................................
9-Bit Inverting Transceiver ........................................................
Microcycle Length Controller .....................................................
16-Bit Microprocessor Slice .......................................................
16-Bit Microprocessor Slice .......................................................
16-Bit Microprocessor Slice .......................................................
32-Bit Microprocessor Slice .......................................................
16-Bit Sequencer ............•.........•.........................................
32-Bit Cascadeable E.D.C ........................................••....••.........
Octal Register with SPCT..........................................................
1-of-8 Decoder ..............•...................................................
Dual 1-of-4 Decoder .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Binary Counter ....................................•................
Synchronous Binary Counter .•...................................................
Carry Lookahead Generator ......................................................
Up/Down Binary Counter .........................................................
Up/Down Binary Counter .....•...................................................
Octal Buffer ......•..............................................................
Octal Buffer ....................................................•................
Octal Bidirectional Transceiver ....................................................
Octal D Flip-Flop ...........................................••................•..
Universal Shift Register .......•....•.........•............•.................•.....
Octal Transparent Latch .............•......................•.....................
Octal D Flip-Flop ................................................................
Octal D Flip-Flop .................................................•..............
8-Bit Comparator ..........................................•........•............
Octal Transparent Latch .........................................•............... ,
Octal D Flip-Flop .....................•..........................................
Octal Transparent Latch ................................•.........................
vi
3-1
3-12
3-15
3-47
3-61
3-47
3-71
3-73
3-99
3-99
5-1
5-1
5-1
5-1
5-1
5-1
5-7
5-7
5-7
5-7
5-7
5-7
5-13
5-13
5-13
5-13
3-101
3-103
3-113
3-124
3-126
3-128
3-138
5-18
5-20
5-24
5-27
5-27
5-31
5-35
5-39
5-43
5-47
5-50
5-53
5-57
5-61
5-65
5-69
5-73
5-76
5-80
5-84
NUMERIC TABLE OF CONTENTS (CONT'D)
PART #
54/7 4AHCT574
54/74AHCT640
54/74AHCT645
54/74FCT138/A
54/74FCT139/A
54/74FCT161/A
54/74FCT163/A
54/74FCT182/A
54/7 4FCT191 IA
54/74FCT193/A
5417 4FCT240/A
54/74FCT244/A
54/74FCT245/A
54/74FCT273/A
54/74FCT299/A
5417 4FCT373/A
54/7 4FCT37 4/A
54/74FCT377/A
54/74FCT521/A
54/74FCT533/A
54174FCT534/A
54/74FCT573/A
54174FCT574/A
54/74FCT640/A
54174FCT645/A
54/74FCT821 B
54/74FCT822B
54/74FCT823B
54/74FCT824B
54/74FCT825B
54/74FCT826B
54/74FCT841 B
54/74FCT842B
54/74FCT843B
54/74FCT844B
54/74FCT845B
54/74FCT846B
54/74FCT861 B
54/74FCT862B
5417 4FCT863B
54/74FCT864B
6116A
6167A
6168A
7130
7132
7133
7134
7140
7142
7143
7164
7165
PAGE
Octal D Register .................................................................
Octal Bidirectional Transceiver ....................................................
Octal Bidirectional Transceiver ....................................................
1-of-8 Decoder ..................................................................
DuaI1-of-4 Decoder .............................................................
Synchronous Binary Counter .....................................................
Synchronous Binary Counter .....................................................
Carry Lookahead Generator ......................................................
Up/Down Binary Counter .........................................................
Up/Down Binary Counter .........................................................
Octal Buffer .....................................................................
Octal Buffer .....................................................................
Octal Bidirectional Transceiver ....................................................
Octal D Flip-Flop ................................................................
Octal Universal Shift Register .....................................................
Octal Transparent Latch ..........................................................
Octal D Flip-Flop ................................................................
Octal D Flip-Flop ................................................................
8-Bit Comparator ................................................................
Octal Transparent Latch ..........................................................
Octal D Flip-Flop ................................................................
Octal Transparent Latch ..........................................................
Octal D Register .................................................................
Octal Bidirectional Transceiver ....................................................
Octal Bidirectional Transceiver ....................................................
10-Bit Non-inverting Register ......................................................
10-Bit Inverting Register ..........................................................
9-Bit Non-inverting Register .......................................................
9-Bit Inverting Register ...........................................................
8-Bit Non-inverting Register .......................................................
8-Bit Inverting Register ................. .........................................
10-Bit Non-inverting Latch ........................................................
10-Bit Inverting Latch ............................................................
9-Bit Non-inverting Latch .........................................................
9-Bit Inverting Latch .............................................................
8-Bit Non-inverting Latch .........................................................
8-Bit I nverting Latch .............................................................
10-Bit Non-inverting Transceiver ...................................................
1D-Bit Inverting Transceiver .......................................................
9-Bit Non-inverting Transceiver ....................................................
9-Bit I nverting Transceiver ........................................................
16K (2Kx8) Static RAM ...........................................................
16K (16Kx1) Static RAM ..........................................................
16K (4Kx4) Static RAM ...........................................................
8K (1 Kx8) Dual-Port Static RAM ...................................................
16K (2Kx8) Dual-Port Static RAM ..................................................
32K 2Kx16 Dual-Port Static RAM ..................................................
32K (4Kx8) Dual-Port Static RAM ..................................................
8K (1 Kx8) Slave Dual-Port Static RAM .............................................
16K (2Kx8) Slave Dual-Port Static RAM ............................................
32K 2Kx16 Slave Dual-Port Static RAM .............................................
64K (8Kx8) Static RAM ...........................................................
64K (8Kx8) Static RAM ...........................................................
vii
5-88
5-92
5-95
5-98
5-102
5-105
5-105
5-109
5-113
5-117
5-121
5-125
5-129
5-133
5-137
5-141
5-145
5-149
5-153
5-156
5-160
5-164
5-168
5-172
5-176
5-180
5-180
5-180
5-180
5-180
5-180
5-186
5-186
5-186
5-186
5-186
5-186
5-192
5-192
5-192
5-192
2-1
2-8
2-15
2-29
2-41
2-53
2-55
2-29
2-41
2-53
2-59
2-67
NUMERIC TABLE OF CONTENTS (CONT'D)
PART #
7174
7187
7188
7198
7201
7201A
7202
7202A
7203
7204
7209
7210
7212
7213
7216
7217
7243
71256
71257
71258
71322
71341
71681A
716S2A
719S1
719S2
72064
72065
72103
72104
72264
72265
72401
72402
72403
72404
72413
75C1S
75C2S
7MP624
7M134
7M135
7M136
7M137
7M144
7M145
7M203
7M204
7M205
7M206
7M624
7M656
7MS12
7MS24
PAGE
64K (SKxS) Static RAM .•..............••...............................••...•....
64K (64Kx1) Static RAM .................................................•.•.•....
64K (16Kx4) Static RAM ................•..................•...........•......•...
64K (16Kx4) Static RAM ........................•..........................•......
512x9 Parallel In-Out FIFO ......•........................................•........
512x9 Half-Full Flag FIFO ...................•.........................•..........•
1024x9 Parallel In-Out FIFO ........................................••.............
1024x9 Half-Full Flag FIFO ..................................•......•.••...........
204SKx9 Parallel In-Out FIFO ..............•...••.••.•......................•.•...
4096Kx9 Parallel In-Out FIFO .......•....•..................................•..•..
12x12 Parallel Multiplier-Accumulator .•..........•..................•..••..........
16x16 Parallel Multiplier-Accumulator ..................•.........•..........•......
12x12 Parallel Multiplier ..........................................................
12x12 Parallel Multiplier ......•.•......................•...................•.•....
16x16 Parallel Multiplier ..................................•..............•........
16x16 Parallel Multiplier ........•.....................•....................•......
16x16 Parallel Multiplier-Accumulator .....•...............................•........
256K (32KxS) Static RAM ...........•...............................•.•..........•
256K (256Kx1) Static RAM .......•.•......•.•..•••..............•.••..............
256K (64Kx4) Static RAM ......................••...............•..•..•...........
16K (2KxS) Dual-Port Static RAM .........•.••.......••..........•........•........
32K (4KxS) Dual-Port Static RAM .........•....................•..........•........
16K (4Kx4) Static RAM .....................•..••.....••..........•...•..........•
16K (4Kx4) Static RAM .....•.................................................•...
64K (16Kx4) Static RAM ...•...........••.........•.........................•••...
64K (16Kx4) Static RAM ...•..........••.•........•...............................
64-Bit Floating Point Multiplier .................••..................••.•.........•.
64-Bit Floating Point ALU ....................•..•..••.............................
2084Kx9 Half-Full Flag FIFO ........•.........................•.............••..••
4096Kx9 Half-Full Flag FIFO ...........•................................•.........
64-Bit Floating Point Multiplier ................................................••..
64-Bit Floating Point ALU .........................................................
64x4 Parallel In-Out FIFO ..•••.........••••.......•.........................•••...
64x5 Parallel In-Out FIFO ••.................................•.........••....••....
64x4 Parallel In-Out FIFO .......................•.....................•........•..
64x5 Parallel In-Out FIFO ......••....................•...................•.•......
Parallel 64x5 FIFO ..•...................................••..............•••......
8-Bit 125MHz Video DAC ......•..........................•............. '..........
8-Bit 125MHz Video DAC .........................................................
1 Megabit (64Kx16, 12SKxS or 256Kx4) Plastic Static RAM Module ..............•••...
64K (SKxS) Dual-Port RAM Module ...................................•.•....••••..
12SK (16KxS) Dual-Port RAM Module .......•.••......•••••..............•.•.......
12SK (16KxS) Dual-Port RAM Module ..................•..................•...••...
256K (32KxS) Dual-Port RAM Module ..................................•.....•••...
64K (SKxS) Slave Dual-Port RAM Module .....................................••....
12SK (16KxS) Slave Dual-Port RAM Module .........................•.•••..... , ..••.
2Kx9-Bit Parallel In-Out FIFO •........••..........•...............................
4Kx9-Bit Parallel In-Out FIFO ............................•••...........•••.••.•...
SKx9-Bit Parallel In-Out FIFO ...•.••.........•.........•..............•........•..
16Kx9-Bit Parallel In-Out FIFO •...•...............................................
1 Megabit (64Kx16, 12SKxS or 256Kx4) Static HAM Module .....................•••.•.
256K (16Kx16, 32KxS or 64Kx4) Static RAM Module ...........•.......•.....•.•.....
512K 64KxS Static RAM Module ......•...........•..............•........••.......
1 Megabit (12SKxS) Static RAM Module ............................•••.••....••....
viii
2-S2
2-S9
2-95
2-101
4-11
4-1
4-11
4-1
4-21
4-21
4-35
4-42
4-52
4-52
4-61
4-61
4-42
2-23
2-25
2-27
2-51
2-57
2-73
2-73
2-10S
2-10S
4-31
4-31
4-50
4-50
4-71
4-71
4-75
4-75
4-75
4-75
4-77
6-1
6-1
7-1
7-3
7-3
7-13
7-13
7-15
7-15
7-1S
7-1S
7-2S
7-2S
7-29
7-35
7-41
7-46
NUMERIC TABLE OF CONTENTS (CONT'D)
PART #
7M856
7M864
7M912
8MP612
8M612
8MP624
8M624
8MP628
8M628
8MP656
8M656
8MP824
8M824
8M856
8M864
PAGE
256K (32Kx8) Static RAM Module .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K (8Kx8) Static RAM Module ....................................................
512K (64Kx8 or 64Kx9) Static RAM Module .........................................
512K (32Kx16) Plastic Static RAM Module ..........................................
512K (32Kx16) Static RAM Module .................................................
1 Megabit (64Kx16) Plastic Static RAM Module ......................................
1 Megabit (64Kx16) Static RAM Module ............................................
128K (8Kx16) Plastic Static RAM Module ...........................................
128K (8Kx16) Static RAM Module ..................................................
256K (16Kx16) Plastic Static RAM Module ..........................................
256K (16Kx16) Static RAM Module .................................................
1 Megabit (128Kx8) Plastic Static RAM Module ................... " . '" .............
1 Megabit (128Kx8) Static RAM Module ............................................
256K (32Kx8) Static RAM Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64K (8Kx8) Static RAM Module ....................................................
Ix
7-49
7-55
7-41
7-60
7-66
7-60
7-66
7-62
7-68
7-62
7-68
7-64
7-75
7-77
7-55
High-Speed CItfOS ItfICROSLICE Products
TII
• CMOS microprogrammable bit-slice microprocessor
family
·
•
•
Meets or exceeds bipolar speeds and output drive at a
small fraction of the power consumption
IDT49COOO products offer dramatically improved system
performance through new innovative architectures
• Available in military and commercial temperature ranges
• Sequential letter suffix designates 20%-40% speed
upgrade
•
IDT39COOO products are pin-compatible, performanceenhanced 2900 family replacements
·
Instruction set/operation codes functionally identical to
2900 family
Produced with advanced CEMOSTM high-performance
technology
Oper. Power (max)
(mW)
Com'l. Mil.
Availability
Page
No.
Part Number
Description
Replaces
IDT39C01C
IDT39C01D
IDT39C01E
4-Bit IJP Slice
Am2901B,C; Am29C01C;
IDM2901A.-2; SFC2901B,C;
CY7C901
105
165
NOW
3-1
IDT39C03A
IDT39C03B
4-Bit IJP Slice
Am2903, SFC2903
265
330
NOW
3-15
IDT39C203
IDT39C203A
4·Bit JlP Slice
Am29203
265
330
NOW
3-71
IDT49C40 1
IDT49C401A
16-Bit IJP Slice
IMI4X2901B
660
825
NOW
3-103
IDT49C402
IDT49C402A
16·Bit JlP Slice, Quad 2901
with 8 additional destination
functions and a 64 x 16 dualport memory capacity
UNIQUE
660
825
NOW
3-113
IDT49C403
IDT49C403A
16-Bit IJP Slice, Quad 2903/
29203 with 64 x 16 register
file, 4 Q·registers, word/BYTE
control, BYTE swap,
cascadeable
UNIQUE
660
825
NOW
3-124
IDT49C404
IDT49C404A
32-Bit JlP Slice, 3·port device
with 32-Bit ALU, 64 x 32
register file, cascadeable
funnel shifter, priority
encoder, merge logic and
mask generator
UNIQUE
3500
4000
Q4 '86
3-126
IDT39C09A
IDT39C09B
4-Bit Sequencer
Am2909A; CY7C909;
SFC2909; LM2909
130
165
NOW
3-47
IDT39C1OB
IDT39C10C
12-Bit Sequencer with
33-Deep Stack
Am2910A; CY7C910;
SFC2910; IDM2910
395
495
NOW
3-61
IDT39C11A
IDT39C11B
4-Bit Sequencer
Am2911A; CY7C911;
SFC2911A; IDM2911A
130
165
NOW
3-47
IDT49C410
IDT49C410A
16-Bit Sequencer with
33-Deep Stack
UNIQUE
395
495
NOW
3-128
UI
IDT39C705A
IDT39C705B
16 X 4 Register File Extension
Am29705A
105
165
NOW
3-99
a:
w
IDT39C707
IDT39C707A
16 X 4 Register File Extension
Am29707
105
165
NOW
3-99
w
a:
c;
IDT49C470
IDT49C470A
64x 16 Register File
UNIQUE
16-Bit Cascadeable Error
Detection Correction Unit
Am2960-1,A; N2960
450
550
NOW
3-73
0
IDT39C60
IDT39C60-1
IDT39C60A
IDT49C460
IDT49C460A
32-Bit Cascadeable Error
Detection Correction Unit
UNIQUE
500
690
NOW
3-138
UI
a:
0
UI
UI
w
0
0
a:
A-
0
a:
0
i
UI
a:
w
0
zw
:::)
0
w
UI
...ii:w
Iii
CI
w
Q4 '86
a:
w
IDT39C02A
Carry Lookahead Generator
Am2902A
30
30
NOW
3-12
I-
IDT49C25
Clock Generator
Am2925
30
30
NOW
3-101
:J:
0
*Contact Factory
X
High·Speed CMOS Static RAMs
··
·
2V data retention battery backup on all low-power
devices
•
Three-state outputs
.
.
Extremely fast access times
Low power consumption
'M' type ceramic RAM modules are built with IDT
monolithic RAMs in Lee packages surface mounted onto
multi-layered, co-fired ceramic substrates using IDrs
high-reliability vapor phase reflow soldering process
'MP' type commercial plastic modules are built using
IDT monolithic RAMs in SMD plastic packages, surface
mounted onto epoxy laminate (FR4) substrates
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
(fl W )
Page
No.
Part Number
Description
IDT6116A
16K (2K x 8)
35
30
250
IDT6120
16K (2K x 8) with high-speed chip
select (chip select access time)
20
18
200
IDT6167A
16K{16Kx 1)
20
15
200
10
NOW
2-8
IDT6168A
16K (4K x 4)
25
20
225
10
NOW
2-15
IDT6169
16K (4K x 4) with high-speed chip
select (chip select access time)
15
12
225
IDT71681A
16K (4K x 4) with separate data
inputs and outputs; outputs track
inputs during write mode
25
20
225
10
NOW
2-73
IDT71682A
16K (4K x 4) with separate data
inputs and outputs; outputs in high
impedance state during write mode
25
20
225
10
NOW
2-73
IDT7164
64K (8Kx8)
45
30
300
30
NOW
2-59
IDT7165
64K (8K x 8) with asynchronous
clear and high-speed chip select
45
30
300
30
NOW
2-67
IDT7174
64K (8K x 8) with cache address
comparator, asynchronous clear
and high-speed chip select
45
35
300
NOW
2-82
2-89
30
Availability
NOW
2-1
Q4 '86
Q4 '86
IDT7187
64K (64Kx 1)
30
25
250
30
NOW
IDT7188
64K{16KX4)
30
25
300
30
NOW
2-95
IDT7198
64K (16K x 4) output enable tOE)
and second chip select (eS,) for
added system flexibility and
memory control
30
25
300
30
NOW
2-101
IDT71981
64K (16K x 4) with separate data
inputs and outputs; outputs track
inputs during write mode
30
25
300
30
NOW
2-108
IDT71982
64K (16K x 4) with separate data
inputs and outputs; outputs in high
impedance state during write mode
30
25
300
30
NOW
2-108
IDT71256
256K (32K x 8)
55
45
350
100
Q4 '86
2-23
IDT71257
256K (256K xl)
45
35
350
100
Q1 '87
2-25
IDT71258
256K (64K x 4)
45
35
350
100
Ql '87
2-27
IDT7M864
64K (8K x 8) RAM module with
static RAM pinout
75
65
325
80
NOW
7-55
IDT8M864
64K (8K x 8) RAM module with
EPROM pinout
75
65
325
80
NOW
7-55
IDT8M628
128K (8K x 16) RAM module with
monolithic pinout
60
50
750
750
Q4 '86
7-68
IDT8MP628
128K (8K x 16) plastic SI PRAM
module
50
750
750
NOW
7-62
IDT7M656
256K (16K x 16, 32K x 8, 64K x 4)
RAM module - customer
configurable organization
25
2000
1500
NOW
7-35
35
*Contact Factory
CONTINUED
xi
High·Speed CMOS Static RAMs (continued)
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
(j.tW)
Availability
Page
No.
1000
NOW
7-49
350
500
NOW
7-77
50
1000
1000
04 '86
7-68
50
1000
1000
NOW
7-62
55
45
1800
900
NOW
7-41
512K (64K x 9) RAM module offering maximum addressable memory
required by 8-bit MPs
55
45
1800
900
NOW
7-41
IDT8M612
512K (32K x 16) RAM module with
monolithic pinout
75
60
1000
300
01 '87
7-66
IDT8MP612
512K (32K x 16) plastic SI PRAM
module
60
1000
300
04 '86
7-60
IDT7M624
1 Megabit (64K x 16, 128K x 8,
256K x 4) RAM module - customer
configurable organization
30
2000
1600
NOW
7-29
IDT7MP624
1 Megabit (64K x 16, 128K x 8,
256K x 4) plastic RAM module customer configurable organization
30
2000
1600
04 '86
7-1
IDT8M824
1 Megabit (128K x 8) RAM module
with monolithic pinout
60
500
150
01 '87
7-75
IDT8MP824
1 Megabit (128K
RAM module
60
500
150
04 '86
7-64
IDT7M824
1 Megabit (128K x 8) RAM module
with registered buffered/latched
addresses and I/Os
75
65
950
1600
NOW
7-46
IDT8M624
1 Megabit (64K x 16) RAM module
with monolithic pinout
75
60
1000
300
01 '87
7-66
IDT8MP624
1 Megabit (64K
RAM module
60
1000
300
04 '86
7-66
Part Number
Description
IDT7M856
256K (32K X 8) RAM module with
monolithic pinout
55
50
950
IDT8M856
256K (32K x 8) RAM module with
monolithic pinout (low-power)
55
50
IDT8M656
256K (16K X 16) RAM module with
monolithic pinout
60
IDT8MP656
256K (16K X 16) plastic SI PRAM
module
IDT7M812
512K (64K x 8) RAM module offering maximum addressable memory
required by 8-bit MPs
IDT7M912
40
75
x 8) plastic SIP
x 16) plastic SIP
xII
High-Speed CIIIIOS Dual-Port RAlllls
··
··
·•
··
·
High-speed, low-power
Independent read or write access to any memory
location from either port
Each port has separate controls, address and 1/0
On-chip port arbitration logic
Fully asynchronous operation from either port
TNTand BUSY flags (BUSY only in
Automatic power-down feature controlled byCE
2V data retention battery back-up on all low-power
devices
Dual-port RAM modules built with IDT monolithic dualport RAMs in LCC packages, surface mounted to multilayered, co-fired ceramic substrates using IDT's highreliability vapor phase reflow soldering process
IDT713217142)
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
(mW)
Page
No.
Part Number
Description
IDTl130
8K (1 K X 8) replaces Synertek
SY2130
70
55
55
45
325
NOW
Q4 '86
2-29
IDT7132
16K (2K x 8) largest monolithic dualport static RAM available in the
industry
70
55
55
45
325
NOW
Q4 '86
2-41
IDT7140
8K (1 K X 8) functions as slave with
IDT7130 to provide 16-bit words or
wider; pin compatible with IDT7130
70
55
55
45
325
NOW
Q4 '86
2-29
IDT7142
16K (2K x 8) functions as slave with
IDT7132 to provide 16-bit words or
wider; pin compatible with IDT7132
70
55
55
45
325
NOW
Q4 '86
2-41
IDT71322
16K (2K x 8) with Semaphore
55
45
325
Ql '87
2-51
IDT7133
32K (2Kx 16)
90
70
325
Q4 '86
2-53
IDT7134
32K (4K x 8) high-speed operation
in system where on-chip arbitration
is not needed
55
45
325
Ql '87
2-55
IDT71341
32K (4K X 8) with Semaphore
55
45
325
Ql '87
2-57
IDT7143
32K (2K x 16) functions as slave
with IDTl133 to provide 32-bit
words or wider
90
70
325
Q4 '86
2-53
IDTlM134
64K (8K x 8) dual-port RAM module
90
70
950
20
NOW
7-3
IDTlM135
128K (16K x 8) dual-port RAM
module
90
70
1600
50
NOW
7-3
IDTlM136
128K (16K x 8) functions in system
where on-chip arbitration is not
needed
80
60
1000
30
Ql'87
7-13
IDT7MI37
256K (32K x 8) dual-port RAM
module whf,re on-chip arbitration is
not needed
80
60
1800
60
Ql'87
7-13
IDT7MI44
64K (8K x 8) functions as slave with
IDT7MI34 to provide 16-bit words
or wider; pin compatible with
IDT7MI34
90
70
950
20
NOW
7-15
IDT7MI45
128K (16K x 8) functions as slave
with IDT7MI35 to provide 16-bit
words or wider; pin compatible with
IDT7M135
90
70
1600
50
NOW
7-15
xiii
Availability
High-Speed CMOS FIFOs
•
·
·
•
•
Extremely fast access and cycle times
Low-power consumption
• Asynchronous and simultaneous read and write
Master/slave multiprocessing applications
Bidirectional and rate buffer applications
• Auto retransmit capability
·
Fully expandable by both word depth and/or bit width
• Single read/write line operation
• Empty, full and half-full flags indicate status
FIFO modules are built with IDT monolithic FIFOs in LCC
packages, surface mounted to multi-layered, co-fired
ceramic substrates using IDT's high-reliability vapor
phase reflow soldering process
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
(mW)
Description
IDT7201
512 X 9 replaces Mostek MK4501
40
35
250
25
NOW
4-11
IDT7202
1024 x 9 largest monolithic FIFO
available in the industry
40
35
250
25
NOW
4-11
IDT7201A
512
40
35
250
25
NOW
4-1
IDT7202A
1024 x 9 half-full flag
40
35
250
25
NOW
4-1
IDT7203
2K X 9 half-full flag
50
50
600
100
04 '86
4-21
IDT7204
4K X 9 half-full flag
50
50
600
100
04 '86
4-21
IDT72103
2K x 9 serial input. Half-full, almostfull, almost-empty flags
50
50
600
100
04 '86
4-50
IDT72104
4K X 9 serial input. Half-full, almostfull, almost-empty flags
50
50
600
100
04 '86
4-50
x 9 half-full flag
Availability
Page
No,
Part Number
IDT72401
64 x 4 replace MMI 67401
60
50
200
20
01'87
4-75
IDT72402
64 x 5 replace MMI 67402
60
50
200
20
01'87
4-75
IDT72403
64 x 4 output enable
60
50
200
20
01'87
4-75
IDT72404
64 X 5 output enable
60
50
200
20
01'87
4-75
1DT72413
64 x 5 replace MM I 67413 output
enable
50
30
200
20
01'87
4-77
IDT7M203
2K x 9 FIFO module using four
IDT7201s
50
40
630
100
NOW
7-18
IDT7M204
4K X 9 FIFO module using four
I[)T7202s
50
40
630
100
NOW
7-18
IDT7M205
8K X 9 FIFO module using four
IDT7203s
65
60
1400
400
04'86
7-28
IDT7M206
16K X 9 FIFO module using four
IDT7204s
65
60
1400
400
04'86
7-28
High-Speed CMOS Parallel Multiplier-Accumulators
•
High-speed, low-power
•
Parallel multiplier-accumulators with selectable
accumulation, rounding and preloading
·
Preload function allows output register to be preset
•
Inputs and outputs directly TTL-compatible
• All devices perform subtraction and double precision
addition and multiplication
• Extended product output for multiple accumulations
Max, Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
(jAmW)
Availability
Page
No,
500
NOW
4-35
200
500
NOW
4-42
200
500
NOW
4-42
Part Number
Description
IDT7209
12 X 12-pin and functionally
compatible with TRW TDC1009J
40
30
200
IDT7210
16 X 16-with 35-bit output; pin and
functionally compatible with TRW
TDC1010J
40
35
IDT7243
16 X 16-with 19-bit output; pin and
functionally compatible with TRW
TDC1043
40
35
xiv
High·Speed CMOS Parallel Multipliers
•
··
·
High-speed, low-power
• Configured for easy array expansion
•
User-controlled option for transparent output register
mode
Round control for rounding the MSP
Inputs and outputs directly TTL-compatible
Three-state output controls and separate register enables
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Standby
Oper.
(mW)
(j;W)
Availability
Page
No.
500
NOW
4-52
150
500
NOW
4-52
35
150
500
NOW
4-61
35
150
500
NOW
4-61
Part Number
Description
IDT7212
12 X 12-pin and functionally
compatible with TRW MPY012H
40
30
150
IDT7213
12 x 12-with single clock
architecture
40
30
IDT7216
16 x 16-pin and functionally
compatible with TRW MPY016H/K
and AMD Am29516
40
IDT7217
16 x 16-with single clock
architecture; pin and functionally
compatible with AMD Am29517
40
High·Speed CMOS Floating Point Products
··
·
• Advanced CEMOS technology
•
Full IEEE standard 754 conformance
• Single 5V supply
Full 32-bit and 64-bit multiply and ALU operations
144·Pin Grid Array
Low-power
750mW per device
Power (typical)
Oper.(mW)
Description
Max. Speed (ns)
IDT72064
64-Bit Multiplier·pin and functionally
compatible with Weitek WTL 1064
Single precision
5 MFLOPS (200)
Double precision
2.5 MFLOPS (400)
750
04 '86
4-31
IDT72065
54· Bit ALU·pin and functionally
compatible with Weitek WTL 1065
Single precision
10 MFLOPS (100)
Double precision
10 MFLOPS (100)
750
04 '86
4-31
IDT72264
64-Bit Multiplier-pin and functionally
compatible with Weitek WTL 1264
Single precision
10 MFLOPS (100)
Double precision
5 MFLOPS (200)
750
04 '86
4-71
IDT72265
64·Bit ALU-pin and functionally
compatible with Weitek WTL 1265
Single precision
10 MFLOPS (100)
Double precision
10 MFLOPS (100)
750
04 '86
4-71
xv
Availability
Page
No.
Part Number
High-Speed CMOS Logic Products
•
FCTXXXA devices 35%-50% faster than FAST™ with
equivalent output drive but at dramatically lower CMOS
power over full temperature and voltage supply extremes
•
FCT devices same speed and output drive as FAST™,
but at dramatically lower CMOS power
• AHCT devices same speed and output drive as ALS, but
at dramatically lower CMOS power
•
·
·
·
Substantially lower input current levels than FAST™ or
ALS (5"A max.)
•
JEDEC standard pinout for DIP and LCC
•
Pin-compatible with industry standard MSI logic
Both CMOS and TTL output compatible (eliminates need
for pull-up resistors when driving CMOS static RAMs)
39C8XX devices same speed and output drive as 29800,
but at dramatically lower CMOS power
54/74 FCT8XXB devices 32%-38% faster than 29800
with equivalent output drive, but at dramatically lower
CMOS power
Part Number
Description
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
().tW)
Availability
Page
No.
5-98
IDT54/7 4FCT138A
1-of-8 Decoder
7.8
5.8
10.0
5.0
NOW
IDT54/74FCT139A
DuaI1-of-4 Decoder
7.8
5.9
10.0
5.0
NOW
5-102
IDT54/74FCT161A
Synchronous Binary Counter
7.5
7.2
10.0
5.0
04 '86
5-105
IDT54/74FCT163A
Synchronous Binary Counter
7.5
7.2
10.0
5.0
04 '86
5-105
IDT54/74FCT182A
Carry Lookahead Generator
10.0
5.0
04 '86
5-109
IDT54/74FCT191A
Up/Down Binary Counter
10.5
7.8
10.0
5.0
04 '86
5-113
IDT54/74FCT193A
Up/Down Binary Counter
6.9
6.5
10.0
5.0
04 '86
5-117
IDT54/7 4FCT240A
Octal Buffer
5.1
4.8
10.0
5.0
NOW
5-121
IDT54/74FCT244A
Octal Buffer
4.6
4.3
10.0
5.0
NOW
5-125
IDT54/74FCT245A
Octal Bidirectional Transceiver
4.9
4.6
10.0
5.0
NOW
5-129
IDT54/74FCT273A
Octal 0 Flip-Flop
8.3
7.2
10.0
5.0
NOW
5-133
IDT54/74FCT299A
Octal Universal Shift Register
9.5
7.2
10.0
5.0
NOW
5-137
IDT54/7 4FCT373A
Octal Transparent Latch
5.6
5.2
10.0
5.0
NOW
5-141
IDT54/74FCT374A
Octal 0 Flip-Flop
7.2
6.5
10.0
5.0
NOW
5-145
IDT54/74FCT377A
Octal 0 Flip-Flop
8.3
7.2
10.0
5.0
NOW
5-149
IDT54/74FCT521A
8-Bit Comparator
9.5
7.2
10.0
5.0
NOW
5-153
IDT54/74FCT533A
Octal Transparent Latch
5.6
5.2
10.0
5.0
NOW
5-156
IDT54/74FCT534A
Octal 0 Flip-Flop
7.2
6.5
10.0
5.0
NOW
5-160
IDT54/74FCT573A
Octal Transparent Latch
5.6
5.2
10.0
5.0
NOW
5-164
IDT54/7 4FCT57 4A
Octal 0 Register
7.2
6.5
10.0
5.0
NOW
5-168
IDT54/74FCT640A
Octal Bidirectional Transceiver
5.3
5.0
10.0
5.0
NOW
5-172
IDT54/74FCT645A
Octal Bidirectional Transceiver
4.9
4.6
10.0
5.0
NOW
5-176
IDT54/74FCT138
1-of-8 Decoder
12.0
9.0
10.0
5.0
NOW
5-98
IDT54/74FCT139
DuaI1-of-4 Decoder
12.0
9.0
10.0
5.0
NOW
5-102
IDT54/74FCT161
Synchronous Binary Counter
11.5
11.0
10.0
5.0
04 '86
5-105
IDT54/74FCT163
Synchronous Binary Counter
11.5
11.0
10.0
5.0
04 '86
5-105
IDT54/74FCT182
Carry Lookahead Generator
11.5
9.0
10.0
5.0
NOW
5-109
IDT54/74FCT191
Up/Down Binary Counter
16.0
12.0
10.0
5.0
04 '86
5-113
IDT54/74FCT193
Up/Down Binary Counter
10.5
10.0
10.0
5.0
04 '86
5-117
IDT54/74FCT240
Octal Buffer
9.0
8.0
10.0
5.0
NOW
5-121
IDT54/74FCT244
Octal Buffer
7.0
6.5
10.0
5.0
NOW
5-125
IDT54/74FCT245
Octal Bidirectional Transceiver
7.5
7.0
10.0
5.0
NOW
5-129
IDT54/74FCT273
Octal 0 Flip-Flop
15.0
13.0
10.0
5.0
NOW
5-133
IDT54/74FCT299
Octal Universal Shift Register
16.0
10.0
10.0
5.0
NOW
5-137
xvi
CONTINUED
High·Speed CMOS Logic Products (continued)
Part Number
Description
Max. Speed (ns)
Com' I.
Mil.
Power (typical)
Oper.
Standby
(mW)
(jIW)
Availability
Page
No.
IDT54/7 4 FCT373
Octal Transparent Latch
8.5
8.0
10.0
5.0
NOW
5-141
IDT54/74FCT374
Octal D Flip-Flop
11.0
10.0
10.0
5.0
NOW
5-145
IDT54/7 4 FCT377
Octal D Flip-Flop
15.0
13.0
10.0
5.0
NOW
5-149
IDT54/7 4 FCT521
8-Bit Comparator
15.0
11.0
10.0
5.0
NOW
5-153
IDT54/74FCT533
Octal Transparent Latch
12.0
10.0
10.0
5.0
NOW
5-156
11.0
10.0
10.0
5.0
NOW
5-160
8.5
8.0
10.0
5.0
NOW
5-164
5-168
IDT54/74FCT534
Octal D Flip-Flop
IDT54/7 4 FCT573
Octal Transparent Latch
IDT54/74FCT574
Octal D Register
11.0
10.0
10.0
5.0
NOW
IDT54/74FCT640
Octal Bidirectional Transceiver
8.0
7.0
10.0
5.0
NOW
5-172
IDT54/7 4 FCT645
Octal Bidirectional Transceiver
11.0
9.5
10.0
5.0
NOW
5-176
IDT54/7 4AHCT138
1-of-8 Decoder
27.0
22.0
3.5
5.0
NOW
5-20
IDT54/74AHCT139
DuaI1-of-4 Decoder
25.0
20.0
3.5
5.0
NOW
5-24
5-27
IDT54/74AHCT161
Synchronous Binary Counter
20.0
17.0
3.5
5.0
04 '86
IDT54/74AHCT163
Synchronous Binary Counter
20.0
17.0
3.5
5.0
04 '86
5-27
I DT54/7 4AHCT182
Carry Lookahead Generator
15.0
12.0
3.5
5.0
NOW
5-31
IDT54/74AHCT191
Up/Down Binary Counter
22.0
18.0
3.5
5.0
04 '86
5-35
IDT54/74AHCT193
Up/Down Binary Counter
19.0
16.0
3.5
5.0
04 '86
5-39
IDT54/74AHCT240
Octal Buffer
12.0
9.0
3.5
5.0
NOW
5-43
IDT54/74AHCT244
Octal Buffer
13.0
10.0
3.5
5.0
NOW
5-47
IDT54/7 4AHCT245
Octal Bidirectional Transceiver
15.0
10.0
3.5
5.0
NOW
5-50
IDT54/7 4AHCT273
Octal D Flip-Flop
17.0
15.0
3.5
5.0
NOW
5-53
IDT54/7 4AHCT299
Universal Shift Register
20.0
14.0
3.5
5.0
NOW
5-57
IDT54/74AHCT373
Octal Transparent Latch
19.0
16.0
3.5
5.0
NOW
5-61
IDT54/7 4AHCT374
Octal D Flip-Flop
18.0
16.0
3.5
5.0
NOW
5-65
IDT54/74AHCT377
Octal D Flip-Flop
18.0
16.0
3.5
5.0
NOW
5-69
IDT54/74AHCT521
8-Bit Comparator
18.0
14.0
3.5
5.0
NOW
5-73
IDT54/74AHCT533
Octal Transparent Latch
24.0
19.0
3.5
5.0
NOW
5-76
IDT54/7 4AHCT534
Octal D Flip-Flop
18.0
16.0
3.5
5.0
NOW
5-80
IDT54/74AHCT573
Octal Transparent Latch
15.0
14.0
3.5
5.0
NOW
5-84
IDT54/7 4AHCT574
Octal D Register
15.0
14.0
3.5
5.0
NOW
5-88
IDT54/7 4AHCT640
Octal Bidirectional Transceiver
14.0
11.0
3.5
5.0
NOW
5-92
IDT54/74AHCT645
Octal Bidirectional Transceiver
15.0
10.0
3.5
5.0
NOW
5-95
5-1
IDT39C821
10-Bit Non-inverting Register
12.0
12.0
10.0
5.0
NOW
IDT39C822
10-Bit Inverting Register
12.0
12.0
10.0
5.0
04 '86
5-1
IDT39C823
9-Bit Non-inverting Register
12.0
12.0
10.0
5.0
NOW
5-1
IOT39C824
9-Bit Inverting Register
12.0
12.0
10.0
5.0
NOW
5-1
IDT39C825
8-Bit Non-inverting Register
12.0
12.0
10.0
5.0
NOW
5-1
IDT39C826
8-Bit Inverting Register
12.0
12.0
10.0
5.0
04 '86
5-1
IDT39C827
10-Bit Non-inverting Buffer
10.0
8.0
10.0
5.0
NOW
IDT39C828
10-Bit Inverting Buffer
10.0
8.0
10.0
5.0
NOW
IDT39C841
10-Bit Non-inverting Latch
11.0
9.5
10.0
5.0
NOW
IDT39C842
10-Bit Inverting Latch
11.0
9.5
10.0
5.0
04 '86
5-7
5-7
IDT39C843
9-Bit Non-inverting Latch
11.0
9.5
10.0
5.0
NOW
5-7
IDT39C844
9-Bi! Inverting Latch
11.0
9.5
10.0
5.0
NOW
5-7
·Contact Factory
xvii
CONTINUED
High-Speed CMOS Logic Products (continued}
Max. Speed (ns)
Mil.
Com'l.
Power (typical)
Oper.
Standby
(mW)
(,.tW)
Availability
Page
No.
Part Number
Description
IDT39C845
8-Bit Non-inverting Latch
11.0
9.5
10.0
5.0
NOW
5-7
IDT39C846
8-Bit Inverting Latch
11.0
9.5
10.0
5.0
04 '86
5-7
IDT39C861
10-Bit Non-inverting Transceiver
10.0
8.0
10.0
5.0
NOW
5-13
IDT39C862
10-Bit Inverting Transceiver
10.0
8.0
10.0
5.0
04 '86
5-13
IDT39C863
9-Bit Non-inverting Transceiver
10.0
8.0
10.0
5.0
NOW
5-13
IDT39C864
9-Bit Inverting Transceiver
10.0
8.0
10.0
5.0
NOW
5-13
IDT54/74FCT821 B
10-Bit Non-inverting Register
8.5
7.5
10.0
5.0
NOW
5-180
IDT54/74FCT822B
10-Bit Inverting Register
8.5
7.5
10.0
5.0
04 '86
5-180
IDT54/74FCT823B
9-Bit Non-inverting Register
8.5
7.5
10.0
5.0
NOW
5-180
IDT54/74FCT824B
9-Bit Inverting Register
8.5
7.5
10.0
5.0
NOW
5-180
IDT54/74FCT825B
8-Bit Non-inverting Register
8.5
7.5
10.0
5.0
NOW
5-180
IDT54/74FCT826B
8-Bit Inverting Register
8.5
7.5
10.0
5.0
04 '86
5-180
IDT54/74FCT827B
10-Bit Non-inverting Buffer
6.5
5.0
10.0
5.0
NOW
IDT54/74FCT828B
10-Bit Inverting Buffer
6.5
5.0
10.0
5.0
NOW
IDT54/74FCT841 B
10-Bit Non-inverting Latch
7.5
6.5
10.0
5.0
NOW
5-186
IDT54/74FCT842B
10-Bit Inverting Latch
7.5
6.5
10.0
5.0
04 '86
5-186
IDT54/74FCT843B
9-Bit Non-inverting Latch
7.5
6.5
10.0
5.0
NOW
5-186
IDT54/74FCT844B
9-Bit Inverting Latch
7.5
6.5
10.0
5.0
NOW
5-186
IDT54/74FCT845B
8-Bit Non-inverting Latch
7.5
6.5
10.0
5.0
NOW
5-186
IDT54/74FCT846B
8-Bit Inverting Latch
7.5
6.5
10.0
5.0
04 '86
5-186
IDT54/74FCT861 B
10-Bit Non-inverting Transceiver
6.5
5.0
10.0
5.0
NOW
5-192
IDT54/74FCT862B
10-Bit Inverting Transceiver
6.5
5.0
10.0
5.0
04 '86
5-192
IDT54/74FCT863B
9-Bit Non-inverting Transceiver
6.5
5.0
10.0
5.0
NOW
5-192
IDT54/74FCT864B
9-Bit Inverting Transceiver
6.5
5.0
10.0
5.0
NOW
5-192
*Contact Factory
xvIII
AMO
lOT
Am2167-35C
Am2167-45C
Am2167-55C
Am2167-55BRA
Am2167-70C
Am2167-70BRA
IOT6167-35
IOT6167-45
IOT6167-55
IOT6167-855B
IOT6167-70
IOT6167-870B
Am2168-35C
Am2168-45C
Am2168-55C
Am2168-55M
Am2168-70C
Am2168-90M
IOT6168-35
IOT6168-45
IOT6168-55
IOT6168-55B
IOT6168-70
IOT6168-70B
Am9128-70C
Am9128-70M
Am9128-90M
Am9128-100C
Am9128-100M
Am9128-120M
IDT6116-70
IOT6116-70B
IOT6116-90B
IOT6116-90
IOT6116-90B
IOT6116-120B
Am99C68-45C
Am99C68-55C
Am99C68-55M
Am99C68-70C
Am99C68-70M
IOT61688-45
IOT61688-55
IOT61688-55B
IDT61688-70
I DT61688-70B
Am99C68L-45C
Am99C68L-55C
Am99C68L-55M
Am99C68L-70C
Am99C68L-70M
IOT6168L-45
IDT6168L-55
IOT6168L-55B
IOT6168L-70
IOT6168L-70B
Am99C88-70C
Am99C88-100C
Am99C88-100M
Am99C88-120C
Am99C88-120M
Am99C88-150C
Am99C88-150M
IOT71648-70
10T71648-70
10T7164S-85B
10T71648-70
IOT7164S-85B
10T7164S-70
IOT7164S-85B
Am99C88L-70C
Am99C88L-100C
10T7164L-70
10T7164L-70
Am213D-70C
Am2130-90C
Am213D-90M
Am2130-100C
Am2130-100M
10T713D-70
10T713D-90
10T713D-90B
IOT7130-100
IOT713D-100B
CYPRESS
lOT
CYPRESS
lOT
CY7C128-35C
CY7C128-45C
CY7C128-45M
CY7C128-55C
CY7C128-55M
IOT6116-35
IOT6116-45
IOT6116-45B
IOT6116-55
IOT6116-55B
CY7C172-25C
CY7C172-35C
CY7C172-35M
CY7C172-45C
CY7C172-45M
IOT71682-25
IOT71682-35
10T71682-35B
IOT71682-45
IOT71682-45B
CY7C13D-55C
CY7C130-70C
CY7C13D-70M
CY7C130-90C
CY7C13D-90M
IOT713D-55
IOT713D-70
IOT713D-70B
IOT713D-00
IOT713D-90B
CY7C185-35C
CY7C185-45C
CY7C185-45M
CY7C185-55C
CY7C185-55M
IOT7164-35
10T7164-45C
IOT7164-45B
IOT7164-55C
IOT7164-55B
CY7C161-25C
CY7C161-35C
CY7C161-35M
CY7C161-45C
CY7C161-45M
10T71981-25
IOT71981-35
10T71981-35B
IOT71981-45
10T71981-45B
CY7C186-35C
CY7C186-45C
CY7C186-45M
CY7C186-55C
CY7C186-55M
IOT7164-35
10T7164-45
IOT7164-45B
10T7164-55
IOT7164-55B
CY7C162-25C
CY7C162-35C
CY7C162-35M
CY7C162-45C
CY7C162-45M
IOT71982-25
IOT71982-35
IOT71982-35B
10T71982-45
IOT71982-45B
CY7C164-25C
CY7C164-35C
CY7C164-35M
CY7C164-45C
CY7C164-45M
CY7C164-55C
CY7C164-55M
IOT7188-25
IOT7188-35
10T7188-35B
10T7188-45
10T7188-45B
IOT7188-55
10T7188-55B
CY7C187-25C
CY7C187-35C
CY7C187-35M
CY7C187-45C
CY7C187-45M
CY7C187-55C
CY7C187-55M
IOT7187-25
IOT7187-35
10T7187-35B
IOT7187-45
IOT7187-45B
IOT7187-55
IOT7187-55B
CY7C166-25C
CY7C166-35C
CY7C166-35M
CY7C166-45C
CY7C166-45M
CY7C166-55C
CY7C166-55M
10T7198-25
10T7198-35
10T7198-35B
10T7198-45
10T7198-45B
10T7198-55
IOT7198-55B
CY7C167-25C
CY7C167-35C
CY7C167-35M
CY7C167-45C
CY7C167-45M
IOT6167-25
IOT6167-35
IOT6167-35B
IOT6167-45
IOT6167-45B
CY7C168-25C
CY7C168-35C
CY7C168-35M
IOT6168-25
IOT6168-35
IOT6168-35B
CY7C171-25C
CY7C171-35C
CY7C171-35M
CY7C171-45C
CY7C171-45M
IOT71681-25
IOT71681-35
IOT71681-350
IOT71681-45
IOT71681-450
xix
FUJITSU
lOT
MB81C67-35
MB81C67-45
MB81C67-55
IOT6167-35
IOT6167-45
IOT6167-55
MB8416-120
MB8416-150
MB8416-200
IOT6116-120
IOT6116-120
IOT6116-120
MB81C68-35
MB81C68-45
MB81C68-55
IOT6168-35
IOT6168-45
IOT6168-55
MB81C75-35
MB81C75-45
MB81C75-55
10T7198-35
IOT7198-45
IOT7198-55
MB81C71-35
MB81C71-45
MB81C71-55
IOT7187-35
IOT7187-45
10T7187-55
MB81C78-45
MB81C78-55
MB81C78-70
IOT7164-45
IOT7164-55
IOT7164-70
FAIRCHILO
lOT
F160D-C45
F160D-C55
F16OD-M55
F160D-C70
F16OD-M70
IDT7187-45
IDT7187-55
1DT7187-55B
IDT7187-70
IDT7187-70B
F1601-C45
F1601-C55
F1601-M55
F1601-C70
F1601-M70
IDT7187-45
IDT7187-55
IDT7187-55B
IDT7187-70
IDT7187-70B
HARRIS
lOT
HM65262B-8
HM65262S-9
HM65262B-9
HM65262-9
HM65262-8
HM65262C-9
IDT6167-70B
IDT6167-55B
IDT6167-70B
IDT6167-70B
IDT6167-70B
IDT6167-70B
HM65162B-2
HM65162-2
HM65162C-2
HM65162S-9
HM65162B-9
HM65162-9
HM65162C-9
HM65162S-5
HM65162B-5
HM65162-5
IDT6116-70B
IDT6116-70B
IDT6116-70B
IDT6116-55B
IDT6116-70B
IDT6116-70B
IDT6116-70B
IDT6116-55
IDT6116-70
IDT6116-90
HITACHI
lOT
HM6267-35
HM6267-45
IDT6167-35
IDT6167-45
HM6116-120
HM6116-150
HM6116-200
IDT6116-55
IDT6116-55
IDT6116-55
HM6168-45
HM6168-55
HM6168-70
IDT6168-45
IDT6168-55
IDT6168-55
HM6287-45
HM6287-55
HM6287-70
IDT7187-45
IDT7187-55
IDT7187-55
HITACHI
lOT
HM6787-25
IDT7187-25
HM6264-100
HM6264-120
HM6264-150
IDT7164-70
IDT7164-70
IDT7164-70
lOT
INMOS
I MS140D-35
IMS14OD-45
I MS1400-45M
IMS14OD-55
IMS140D-55M
IDT6167-35
IDT6167-45
IDT6167-45B
IDT6167-55
IDT6167-55B
IMS1400L-70
IMS1400L-100
IDT6167L-55
IDT6167L-55
IMS1403-35
I MS1403-45
I MS1403-45M
I MS1403-55
IMS1403-55M
IDT6167-35
IDT6167-45
IDT6167-45B
IDT6167-55
IDT6167-55B
I MS142D-45
I MS142D-55
IMS142D-55M
I MS1420-70
I MS142D-70M
IDT6168-45
IDT6168-55
IDT6168-55B
IDT6168-70
IDT6168-70B
IMS1420L-70
IMS1420L-100
IDT6168L-55
IDT6168L-55
IMS1423-25
I MS1423-35
I MS1423-35M
IMS1423-45
IMS1423-45M
IDT6168-25
IDT6168-35
IDT6168-35B
IDT6168-45
IDT6168-45B
I MS160D-45
I MS160D-55
IMS160D-55M
I MS160D-70
I MS160D-70M
IDT7187-45
IDT7187-55
IDT7187-55B
IDT7187-70
IDT7187-70B
xx
INMOS
lOT
IMS162D-45
IMS162D-55
IMS162D-55M
IMS162D-70
IMS162D-70M
IDT7188-45
IDT7188-55
IDT7188-55B
IDT7188-70
IDT7188-70B
I MS1624-45
IMS1624-55
I MS1624-55M
IMS1624-70
I MS1624-70M
IDT7198-45
IDT7198-55
IDT7198-55B
IDT7198-70
IDT7198-70B
MATRA-HARRIS
lOT
HM65263-45
HM65263-55
IDT6167-45
IDT6167-55
HM65163-45
HM65163-55
IDT6116-45
IDT6116-55
HM65682-45
HM65682-55
HM65682-70
IDT6168-45
IDT6168-55
IDT6168-70
HM62641-70
HM62641-90
IDT7164-70
IDT7164-70
LATTICE
lOT
SR16K8-35
SR16K8-45
SR16K8-45M
SR16K8-55
SR16K8-55M
IDT6116-35
IDT6116-45
IDT6116-45B
IDT6116-55
IDT6116-55B
SR16K4-35
SR16K4-45
SR16K4-45M
SR16K4-55
SR16K4-55M
IDT6168-35
IDT6168-45
IDT6168-45B
IDT6168-55
IDT6168-55B
SR64K4-35
SR64K4-45
SR64K4-45M
SR64K4-55
SR64K4-55M
IDT7188-35
IDT7188-45
I DT7188-45B
IDT7188-55
IDT7188-55B
SR64E4-35
SR64E4-45
SR64E4-45M
SR64E4-55
SR64E4-55M
IDT7198-35
IDT7198-45
IDT7198-45B
IDT7198-55
IDT7198-55B
LATTICE
lOT
SR64K1-35
SR64K1-45
SR64K1-45M
SR64K1-55
SR64K1-55M
IDT7187-35
IDT7187-45
IDT7187-45B
IDT7187-55
IDT7187-55B
SR64K8-35
SR64K8-45
SR64K8-45M
SR64K8-55
SR64K8-55M
IDT7164-35
IDT7164-45
IDT7164-45B
IDT7164-55
IDT7164-55B
NEC
lOT
!-'PD4362-45
!-'PD4362-55
!-,PD4362-70
IDT7188-45
IDT7188-55
IDT7188-70
!-'PD4361-40
!-'PD4361-45
!-'PD4361-55
!-'PD4361-70
IDT7187-35
IDT7187-45
IDT7187-55
IDT7187-70
!-'PD4464-XXX
IDT7164-70
TOSHIBA
MOTOROLA
lOT
MCM2167-45
MCM2167-55
MCM2167-70
IDT6167-45
IDT6167-55
IDT6167-70
MCM2016-45
MCM2016-55
MCM2016-70
IDT6116-45
IDT6116-55
IDT6116-70
MCM6168-35
MCM6168-45
MCM6168-55
MCM6168-70
IDT6168-35
IDT6168-45
IDT6168-55
IDT6168-70
MCM6268-35
MCM6268-45
MCM6268-55
IDT7188-35
IDT7188-45
IDT7188-55
MCM6287-35
MCM6287-45
MCM6287-55
IDT7187-35
IDT7187-45
IDT7187-55
MCM6164-45
MCM6164-55
MCM6164-70
IDT7164-45
IDT7164-55
IDT7164-70
NEC
lOT
!-,PD4311-35
!-'PD4311-45
!-'PD4311-55
IDT6167-35
IDT6167-45
IDT6167-55
!-,PD446
IDT6116-70
!-,PD4314-35
!-'PD4314-45
!-,PD4314-55
IDT6168-35
IDT6168-45
IDT6168-55
lOT
TC2018-35
TC2018-45
TC2018-55
IDT6116-35
IDT6116-45
IDT6116-55
TC2068-35
TC2068-45
TC2068-55
IDT6168-35
IDT6168-45
IDT6168-55
TC5562-35
TC5562-45
TC5562-55
IDT7187-35
IDT7187-45
IDT7187-55
TC2064-XXX
IDT7164-70
VITELIC
lOT
V61C67-35
V61C67-45
V61C67-55
IDT6167-35
IDT6167-45
IDT6167-55
V61C16-35
V61C16-45
V61C16-55
IDT6116-35
IDT6116-45
IDT6116-55
V61C68-35
V61C68-45
V61C68-55
IDT6168-35
IDT6168-45
IDT6168-55
V61C62-45
V61C62-55
V61C62-70
IDT6188-45
IDT6188-55
IDT6188-70
V61C64-45
VC1C64-55
VC1C64-70
IDT7165-45
IDT7165-55
IDT7165-70
xxi
VITELIC
V61C32-70
V61C32-90
VTI
lOT
IDT7132-70
IDT7132-90
lOT
VT64KS4-35
VT64KS4-45
VT64KS4-55
IDT7188-35
IDT7188-45
IDT7188-55
VT16H4-35
VT16H4-45
VT16H4-55
IDT71981-35
IDT71981-45
IDT71981-55
IDT39COOO SERIES
COMPETITORS
PIN
DESCRIPTION
AMD
THOMPSON
CSF
NSC
lOT SPECIAL FEATURES
CYPRESS
IDT39C01C
IDT39C01D
IDT39C01E
4-Bit Slice
Am2901B
Am2901C
IDM2901A
IDM2901A-2
SFC2901B
SFC2901C
IDT39C02A
Carry Lookahead
Generator
Am2902
Am2902A
IDM2902
SFC2902
SFC2902A
• High-Speed CMOS
IDT39C03A
IDT39C03B
4-Bit Slice
Am2903
Am2903A
LM2903
SFC2903
• 1/4 The Bipolar Power
• "B" Version 20% Faster Than "A"
IDT39COOA
IDT39COOB
4-Bit Sequencer
Am2909
Am2909A
LM2909A
SFC2909
SFC2909A
CY7C909
• High-Speed CMOS
• "B" Version 20% Faster than "A"
• 1/3 The Bipolar Power
IDT39Cl0B
IDT39C1OC
12-Bit Sequencer
Am291 0
Am2910A
IDM2910A
SFC2910
CY7C910
• 33-Deep Stack
• "C" Version 20% Faster Than "B"
IDT39CllA
IDT39CllB
4-Bit Sequencer
Am2911
Am2911A
IDM2911A
SFC2911A
CY7C911
• High-Speed CMOS
• "B" Version 20% Faster Than "/>:'
IDT39C203
IDT39C203A
4-Bit Slice
Ain29203
• 1/4 The Bipolar Power
• "/>:' Version 20% Faster
IDT39C60
IDT39C60-1
IDT39C60A
16-Bit E.D.C.
Am2960
Am296Q-l
Am2960A
• ''A'' Version World's Fastest
16-Bit E.D.C.
• 1/4 The Bipolar Power
IDT39C705A
IDT39C705B
16 X 4 Register File
Am29705
Am29705A
IDT39C707
IDT39C707A
16 X 4 Register File
Am29707
• High-Speed CMOS
• "A" Version 20% Faster
IDT49C25
Clock Generator
Am2925
• 1/4 The Bipolar Power
CY7C901
IDM29705
IDM29705A
• 115 The Bipolar Power
• "0" Version 25% Faster Than "C"
• "E" Version 25% Faster Than "0"
• High-Speed CMOS
• "B" Version 20% Faster than "A"
IDT49COOO SERIES
PIN
IDT49C401
I DT49C401 A
IDT49C402
IDT49C402A
DESCRIPTION
16-Bit Slice
16-Bit Slice
lOT SPECIAL FEATURES
PACKAGE
64-Pin Dip
• Speed Enhanced, Pin Compatible to
IM14X2901
• High-Speed CMOS
• 2901 Instruction Set Compatible
68-Pin Dip, PGA, LCC
• Quad 2901 With 2902
• High-Speed CMOS ("A" Version 40%
Faster than four 2901 CS and 2902A)
• 64 Registers
• 8 Additional Destination Functions
• 2901 Instruction Set Compatible
High-Speed CMOS
Quad 2903A/29203 With 2902A
Binary/BCD Arithmetic
64 Registers
Four Q-Reglsters
Additional ALU Functions
BytelWord Capability
2903A129203 Instruction Set Compatible
IDT49C403
16-Bit Slice
lOB-Pin PGA
•
•
•
•
•
•
•
•
1DT49C410
IDT49C410A
16-Bit Sequencer
48-Pin Dip, LCC
52-Pin PLCC
• High-Speed CMOS
• 33-Deep Stack
• 2910 Instruction Set Compatible
IDT49C460
IDT49C460A
32-Bit E.D.C.
68-Pin Dip, PGA, LCC,
PLCC
• Replaces Two Cascaded 16-Bit
E.D.C. Chips
• "A" Version World's Fastest 32-Bit E.D.C.
• Compatible To IDT39c.sos
xxii
lOT MULTIPLIER AND MULTIPLIER/ACCUMULATOR PRODUCTS
All lOT Fixed Point Multiplier/MACs feature:
o Low-power dissipation-less than 500mW typical
o Full complement of packages:
-Ceramic DIP
-SHRINKDIP
-Fiatpack (Contact Factory)
-PLCC
-Pin Grid Array
-LCC
o Competitively priced
o Full conformance to MIL-STD-883, Class B
o Highest CMOS speeds in the industry
CROSS REFERENCE
PART
NUMBER
DESCRIPTION
AMD
WEITEK
ANALOG
DEVICES
TRW
ADSP1016
MPY016
lOT SPECIAL FEATURES
Speed to 35n5 One-sixth
bipolar power.
IDT7216
16 x 16 Mul1iplier
Am29516A
WTL1516
IDT7217
16x 16 Multiplier with Single Clock
Am29517A
WTL1517
IDT7212
12 x 12 Multiplier
-
-
ADSP1012
MPY012
IDT7213
12 x 12 Multiplier with Single Clock
-
-
-
-
IDT7210
16 x 16 Multiplier/Accumulator
Am29510
WTL1010
ADSP1010
TDC2010
One-sixth bipolar power.
Speeds to 35n5.
IDT7243
16 x 16 Multiplier/Accumulator
-
WTL2044
-
TDC1043
One-sixth bipolar power.
Speeds to 35n5.
IDT7209
12 x 12 Multiplier/Accumulator
Am29509
-
TDC1009
Speeds to 30ns.
-
-
ADSP1009
Single clock option. Speed to 35n5.
Speeds to 30ns.
Single clock microprogrammed
version.
lOT FIFO PRODUCTS:
All lOT FIFOs feature:
o Auto retransmit capability zeros read pOinter
o Dual-ported RAM pOinter architecture
o Zero fall-through time
o Advanced 1.2 micron CEMOS'· II technology
o Full military temperature range operation
o Fully asynchronous and simultaneous read/write
o Th ree-state buffered output
o Fully expandable in word depth and/or width
o Processed to MIL-STD-883, Class B
PART
NUMBER
SPEED
(ACCESS TIME)
(ns)
SIZE
DEPTH X WIDTH
PACKAGE
IDT7201
35
512 x 9-Bit
o 28-Pin DIP
IDT7202
35
1024 x 9-Bit
IDT7201A
35
512 x 9-Bit
• 32-Pin Ceramic Leaded
Chip Carrier (LCC)
IDT7202A
35
1024 x 9-Bit
• 28-Pin Plastic J-Bend
Leaded Chip Carrier
IDT7203
50
2048 x 9-Bit
o 28-Pin Flatpack
1DT7204
50
4096 x 9-Bit
IDT721 03
50
2048 x 9-Bit
IDT72104
4096 x 9-Bit
50
o 4Q-Pin DIP
• 44-Pin Ceramic LCe
• 44-Pin Plastic J-Bend
Leaded Chip Carrier
SPECIAL IDT FEATURES
Speeds to 35n5 access time.
Mostek MK4501 compatible
Half-Full flag. Flow-through mode for first
data byte.
Half-Full flag. Flow-through mode for first
data byte.
Half-Full, Almost-Full and Almost-Empty
flags. Serial input and output. Fully
cascadable in word width and depth.
lOT FLOATING POINT PRODUCTS:
o Advanced CEMOS II 1.2 micron technology
• Full 32-bit and 64-bit multiply and arithmetic operations
o Full IEEE Standard 754 conformance
o 144-pin grid array
o Single 5 Volt supply operation
• Low-power (less than 750mW typical) per device
SINGLE PRECISION OPERATIONS
(32-BIT)
DOUBLE PRECISION OPERATIONS
(64-BIT)
FEATURES
IDT72064 64-Bit Multiplier
5 megaflops (200ns pipelined)
2.5 megaflops (400ns pipelined)
o Weitek WTL1064 equivalent
IDT72065 64-Bit ALU
10 megaflops (100ns pipelined)
10 megaflops (100ns pipelined)
o Weitek WTL 1065 equivalent
IDT72264 64-Bit Multiplier
10 megaflops (100ns pipelined)
5 megaflops (200ns pipelined)
o Weitek WTL 1264 equivalent
IDT72265 64-Bit ALU
10 megaflops (100ns pipelined)
10 megaflops (100ns pipelined)
o Weitek WTL 1265 equivalent
PART TYPE
xxiii
Integrated
Device
Technology
Technology/Capabilities
TECHNOLOGY/CAPABILITIES
TABLE OF CONTENTS
CONTENTS
PAGE
Technology/Capabilities
lOT. .. Leading the CMOS Future .....................................................................
lOT Leading Edge CEMOS Technology ................................................................
Radiation Hardened Technology ....................................................................
Surface Mount Technology .........................................................................
State-of-the-Art Facilities and Capabilities ............................................................
Superior Quality and Reliability .....................................................................
1-1
1-2
1-5
1-5
1-6
1-7
lOT... LEADING THE CMOS FUTURE
A major revolution is taking place in the semiconductor
industry today. A new technology is rapidly displacing older
NMOS and bipolar technologies as the workhorse of the 80's
and beyond. That technology is high-speed CMOS. Integrated
Device Technology, a company totally predicated on and dedicated to implementing high-performance CMOS products, is on
the leading edge of this dramatic change.
Beginning with the introduction of the industry's fastest CMOS
2K x 8 static RAM, IDT has grown into a company with multiple
divisions producing a wide range of high-speed CMOS circuits
that are, in almost every case, the fastest available. These advanced products are produced with lDT's proprietary CEMOS"
technology, a twin-well dry-etched, stepper-aligned process utilizing progressively smaller dimensions.
From inception, our product strategy has been to apply the
advantages of our extremely fast CEMOS technology to produce
the integrated circuit elements required to implement highperformance digital systems. IDT's goal is to provide the circuits
necessary to create systems which are far superior to previous
generations in performance, reliability, cost, weight and size.
Many of our innovative product designs offer higher levels of
integration, advanced architectures, higher density packaging
and system enhancement features that are establishing tomorrow's industry standards. The company is committed to providing its customers with an ever-expanding series of these
high-speed, low-power IC solutions to system design needs.
IDT's commitment, however, extends beyond state-of-the-art
technology and advanced products to providing the highest level
of customer service and satisfaction in the industry. Producing
products to exacting quality standards that provide excellent,
long-term reliability is given the same level of importance and
priority as device performance. IDT is also dedicated to delivering
these high-quality advanced products on time. The company
would like to be known not only for its technological capabilities,
but also for providing its customers with quick, responsive and
courteous service.
IDT's product families are available in both commercial and
military grades. As a bonus, commercial customers obtain the
benefits of military processing disciplines, established to meet
or exceed the stringent criteria of the applicable military specifications.
IDT is the leading U.S. supplier of high-speed CMOS circuits.
The company's high-performance static RAMs, logic, DSp'
MICROSLICE'" bit-slice microprocessor products, data conversion devices, and modular subsystem assemblies complement
each other to provide high-speed CMOS solutions to a wide
range of applications and systems.
Dedicated to maintaining its leadership position as a state-ofthe-art IC manufacturer, IDT will continue to focus on maintaining its technology edge as well as developing a broader range of
innovative products. New products and speed enhancements are
continuously being added to each of the existing product families and additional product lines will be introduced. Contact your
IDT field representative or factory marketing at 1-800-IDT-CMOS
to determine the latest product offerings. If you're building
state-of-the-art equipment, IDT may be able to solve some of
your design problems.
1-1
IDT LEADING EDGE CEMOS TECHNOLOGY
HIGH-PERFORMANCE CEMOS
DUAL-WELL STRUCTURES
CEMOS (the "E" stands for enhanced) is a state-of-the-art
proprietary CMOS technology initially developed and continually
refined by lOT to be at the leading-edge of new high-speed
CMOS processes. It incorporates the best characteristics of
traditional CMOS, including low-power, high-noise immunity
and wide operating temperature range; it also aChieves speed
and output drive equal or superior to bipolar Schottky TTL.
The company has been producing CEMOS products in large
volume for over five years. During this time, CEMOS technology
has been re-engineered and refined from the original 2.5 micron
CEMOS I to the present CEMOS III direct step-on-wafer, dryetch process providing gate lengths as small as sub-micron.
Continual advancement of CEMOS technology allows lOT to
implement progressively higher levels of integration and achieve
increasingly faster speeds maintaining the company's established position as the leader in high-speed CMOS integrated
circuits.
CEMOS is a technology designed to optimize both speed and
power capabilities of advanced architecture VLSI products. It
achieves industry-leading speeds yet consumes very low operating power. Unlike many other competitive "CMOS" circuits, lOT
products can power down to a full CMOS standby mode with
extremely low micro-watt power levels or, in the case of memories, maintain memory contents in a battery backup data
retention mode. Many competing "CMOS" technologies employ
techniques aimed at obtaining fast performance, such as substrate bias generators or charge pumps, that consume higher
levels of operating and standby power and preclude full CMOS
level standby or battery backup operation.
CEMOS is constructed using an advanced dual-well, or twinwell process architecture to optimize the overall characteristics
of a high-performance CMOS process. CMOS processes, using
only "P-wells", resulted in inferior P (or N) channel transistors
or compromised PIN channels. This compromise is largely
eliminated by utilizing both a deep underlying main "well" (in
this case a "P-well") and by altering the doping profile nearer
the surface of the P-channel transistor regions. The latter region
becomes the "N-well" of the dual- or twin-well process. This
technique allows the fabrication of high-performance transistors
in both polarities.
The industry now recognizes that the best combination of
balanced capabilities is achieved using this "dual-well" approach.
This construction technique suppresses punch-through, minimizes junction capacitance and transistor body effects, and
allows extremely fast speeds. In addition, it virtually eliminates
soft errors in fine line geometry memory products induced by
high-energy alpha particles.
BUILT-IN ALPHA PARTICLE IMMUNITY
Random alpha particles can cause memory cells to temporarily lose their contents or suffer a "soft error." Travelling with
high energy levels, alpha particles penetrate deep into an integrated circuit chip. As they burrow into the silicon, they leave a
trail of free electron-hole pairs in their wake. In typical NMOS or
"N-well" CMOS processes, the free electrons are attracted by
the N+ memory cells and cause soft errors by entering them.
To protect the cells from this hazardous occurrence, manufacturers using these technologies apply a liquid die coating of
IDTCEMOS
Built-In High Alpha Particle Immunity
IDTCEMOS
Device Cross Section
-3V
+5V
NMOS
CEMOS'· I
P-Well Barrier
• Deep burrowing alpha particles penetrate over 20l'm
beneath the surface
• Leaves trail of electron-hole pairs in its wake
• CEMOS" I potential barrier repels electrons-then swept
away to ground
• No need for protective surface coatings (i.e. organic
polyimide)
1-2
polyimide, an organic compound that becomes a jelly-like substance as a result of package sealing temperatures. These
compounds may themselves have limitations. Often the sealing
temperatures cause bubbles in the die coating which still allow
alpha particles to reach the die. Also, the compounds are
organic and may lead to future reliability problems (military
standards preclude their use in package cavities unless a waiver
is obtained).
In an IDT product, the P-well potential barrier of the dual-well
structure repels the free electrons, preventing them from reaching the memory cells. Electrons then re-combine with the free
holes or are swept away to the substrate contact. IDT dual-well
memories are virtually immune to alpha particle soft errors and
do not require organic die coatings with their related difficulties.
ELECTROSTATIC
DISCHARGE (ESD) PROTECTION
Another traditional limitation associated with many MOS and
bipolar products is electrostatic discharge induced failures. This
problem has also been solved by a combination of IDT's CEMOS
process and proper circuit design. All I DT products incorporate
proprietary ESD protection circuitry on all inputs and outputs to
ensure that they are insensitive to repeated applications of ESD
stress and do not exhibit the degradation found in other other
MOS or bipolar products which can eventually result in product
failure.
CEMOS VARIATIONS
Variations of IDT CEMOS technology employ single- and
dual-layer metalization as well as single and double poly layers
to optimize memory or logic product performance. In addition,
bipolar devices are utilized selectively, along with the N- and
P-channel CMOS structures, to enhance performance and output drives.
LATCHUP IMMUNITY
A combination of careful design layout, selective use of guard
rings and proprietary techniques have resulted in virtual elimination of latchup problems often associated with older CMOS
processes. The use of NPN and N-channel I/O devices eliminates hole injection latchup. Double guard ring structures are
utilized on all input and output circuits to absorb injected
electrons. These effectively cut off the current paths into the
internal circuits to essentially isolate I/O circuits. Compared to
older CMOS processes which exhibit latchup characteristics
with trigger currents from 1O-20mA, IDT products inhibit latchup
at trigger currents substantially greater than 700mA.
MAINTAINING LEADING EDGE TECHNOLOGY
IDT maintains a constant research and development program
to continue to enhance the capabilities of its CEMOS technology.
CEMOS III, I DT's next generation process, is cu rrently being
refined to achieve aggressive submicron minimum feature size
geometries to allow the implementation of significantly faster
speeds as well as higher levels of integration.
These continued advancements in process development and
manufacturing, coupled with customer-proven deliveries, quality
and reliability, have established the company as a leader in
high-speed CMOS integrated circuits. Committed to maintaining
superior performance, IDT will continue to drive the technology
to lead the CMOS future.
This chart-showing our evolution from the company's original CEMOS I technology to CEMOS II and CEMOS 111depicts the continuous research and development efforts that
we expend to maintain our technological leadership in highspeed CMOS.
IDTCEMOS
Latchup Suppression
-
\
- n-Substrate
-
0
.
-
~
1,\
~
CEMOS
TECHNOLOGY
MINIMUM(1)
FEATURE
SIZE
(MICRONS)
I
IIA
liB
IIC
IliA
IIIB
2.5
2.0
1.5
1.2
1.0
SUBMICRON
0
0
(a)
01
234567
(b) Collector Supply Voltage Vee (V)
• Double guard rings on I/O circuits
• npn and n-channel I/O devices eliminate hole injection
latchup
• Latchup trigger current substantially greater than 500mA
FASTEST
SPEED
PRODUCT
16K x 1 RAM
AVAILABILITY
COM'L. ACCESS
TIME (ns)
45
35(2)
30
15
SUB15
T.BD.
Since 1982
1983
1984
NOW
FUTURE
FUTURE
NOTES:
1. There are many claims and counter claims in this area of minimum feature
size. We are using here a conservative approach, Le. the gate length as
physically measured on a scanning electron microscope.
2. Estimate - not manufactured in CEMOS IIA. Our 16K x 1 static RAM is
used as a typical product to illustrate the figures of merit of this constant
drive for ever higher performance standards.
1-3
RADIATION HARDENED TECHNOLOGY
ability used both in process development and testing of deliverable product. lOT also has a separate group within the company
concentrate on supplying products for radiation hardened applications and to continue research and development of process
and products to further improve radiation handling capabilities
(See "Improved Tolerance of Integrated Device Technology
Products for High-Radiation Environments" in Section 8).
lOT has developed and supplied several levels of radiation
hardened products for military/aerospace applications to perform
at various levels of dose rate, total dose, single event upset
(SEU), upset and latchup. lOT products maintain nearly their
same high-performance levels built-in these to special process
requirements. The company has in-house radiation testing cap-
SURFACE MOUNT TECHNOLOGY
SUBSYSTEM MODULAR ASSEMBLIES
To take full advantage of the low-power aspect of CMOS, and
obtain two to three times the space savings, CMOS products
should be used as SMDs (surface mount devices). However,
most integrated circuits sold today are still packaged in the
traditional DIP (dual in-line package) configuration, and there is
a tremendous support industry to handle thru-board assembly.
Determined to utilize CMOS advantages, lOT re-invented the
DIP. This was accomplished by developing multilayered substrates (either co-fired ceramic or glass filled epoxy FR-4) with
dual in-line (DIP) or single in-line (SIP) pins. An advanced vapor
phase reflow surface mount technology was also developed
after exhaustive evaluation proved vapor phase reflow to be the
most efficient method of heat transfer and to produce the most
reliable solder connections available.
Products that are to be interconnected to form larger electronic elements are electrically tested, environmentally screened,
performance selected and then thermally matched to the appropriate ceramic or glass filled epoxy substrates. After modular
assembly, the finished product is 100% re-tested to ensure that
it completely performs to the specifications required.
As a result, lOT produces extraordinarily dense, high-speed
combinations of monolithic ICs as complex subsystem modular
assemblies. These modules convert SMDs to user-friendly DIPs/
SIPs providing customers with the density advantages of surface
mount in a format compatible with their extensive, thru-board,
assembly expertise.
1-5
STATE-OF-THE-ART FACILITIES AND CAPABILITIES
Integrated Device Technology is headquartered in Santa Clara,
California - the heart of the "Silicon Valley." The company's
operations are housed in five facilities totaling close to 300,000
square feet. These facilities incorporate all aspects of business
from research and development to design, wafer fabrication,
assembly, environmental screening, test and administration. Inhouse capabilities incorporate scanning electron microscope
(SEM) evaluation, particle impact noise detection (PIND), burnin, life test and a full complement of environmental screening
equipment.
IDT's 54,000 square foot Corporate Headquarters houses technology and product research and development. Teams equipped
with state-of-the-art computerized design and analytical tools
conduct the continuous R&D required to push CEMOS technology forward and to create future product lines. This facility
contains a 10,000 square foot Class 10 (no more than 10
particles larger than 0.2 micron per cubic foot) wafer fabrication
clean room used to produce the MICROSLlCE, DSP and logic
product families as well as support R&D.
Located adjacent to the headquarters facility, forming an IDT
corporate campus, is a 100,000 square foot two-building complex that houses the DSP Division and MICROSLICE product
line. Design and product teams, along with administrative functions, are situated in these buildings.
A second small wafer fabrication area, used for research and
development, is also located at this site. This facility houses its
own design tools, laboratories, test and burn-in facilities. Construction of an in-house plastic assembly area is also underway
in this facility.
IDT's Subsystems Division is housed in a third Santa Clara
location, only a few blocks away from the other sites. This
37,000 square foot facility contains the development and product
teams that produce IDT's FCT, AHCT and IDT39C800 logic
families and modular assemblies. Included at this facility are a
quick turnaround hermetic package assembly line and an advanced vapor phase reflow surface mounting module assembly
area.
I DT's largest facility is located in Salinas, California, about an
hour away from Santa Clara. This is the Static RAM Division's
headquarters, a 100,000 square foot facility located on a 14-acre
site. Constructed in 1985, this facility houses an ultra-modern
25,000 square foot high-volume production wafer fabrication
area measured at Class 2-to-Class 3 clean room conditions (a
maximum of 2 to 3 particles per cubic foot of 0.2 micron or
larger). Careful design and construction created a clean room
environment far beyond the average of U.S. fab areas (Class
100), capable of producing large volumes of very high-density,
submicron geometry, fast static RAMs. This facility also houses
the product development areas, laboratories, test, burn-in and
shipping areas for IDT's leadership family of CMOS static
RAMs. This site has future expansion capabilities to accomodate
a 250,000 square foot complex.
I DT's facilities now total nearly 300,000 square feet of floor
space and house three wafer fabrication clean rooms, three
domestic assembly lines, four test and three burn-in areas. All
of these facilities are aimed at increasing our manufacturing
productivity to supply ever larger volumes of high-performance,
cost-effective leadership CMOS products.
1-6
SUPERIOR QUALITY AND RELIABILITY
For module assemblies, additional screening of the fully
assembled substrates is performed to assure package integrity
and mechanical reliability. Finally, 100% electrical tests are
performed on the finished module to ensure compliance with
the defined "subsystem" specifications.
By maintaining these high standards and rigid controls
throughout every step of the manufacturing process, IDT ensures
that commercial, industrial, and military grade products consistently meet customer requirements for quality, reliability and
performance.
Maintaining the highest standards of quality in the industry
on all products is the basis of Integrated Device Technology's
manufacturing systems and procedures. From inception, quality
and reliability are built into all of IDT's products. Quality is
"designed in" at every stage of manufacturing - as opposed to
being "tested-in" later - in order to ensure impeccable performance.
Dedicated commitment to fine workmanship, along with development of rigid controls throughout wafer fab, device assembly
and electrical test, create inherently reliable products. Incoming
materials and chemicals are subjected to careful inspections.
Quality monitors, or inspections, are performed throughout the
manufacturing flow.
IDT's commercial grade products are required to meet stringent criteria.
Product flow and test procedures for all monolithic hermetic
military grade products are in accordance with the latest revision
and notice of MIL-STD-883. State-of-the-art production techniques and computer-based test procedures are coupled with
tight controls and inspections to ensure that products meet the
requirements for 100% screening. Routine quality conformance
lot testing is performed as defined in MIL-STD-883, Methods
5004 and 5005.
IDT military grade monolithic hermetic products are designed
to meet or exceed the demanding Class B reliability levels of
MIL-STD-883 and MIL-M-38510. As per MIL-HDBK-217, products screened to Class B requirements result in failure rates
thirty (30) times better than those not subjected to stress
screening. Parts processed to these reliability levels are generally
used in applications where product reliability is vital.
SPECIAL PROGRAMS
Class S. IDT also has all manufacturing, screening and test
capabilities in-house (except X-ray and some Group D tests) to
perform complete Class S processing per MIL-STD-883 on all
IDT products and has supplied Class S products on several
programs.
Radiation Hardened. IDT has developed and supplied several
levels of radiation hardened products for military/aerospace
applications to perform at various levels of dose rate, total
dose, single event upset (SEU), upset and latchup. IDT products maintain nearly their same high-performance levels built
to these special process requirements. The company has inhouse radiation testing capability used both in process development and testing of deliverable product. IDT also has a separate
group within the company dedicated to supplying products for
radiation hardened applications and to continue research and
development of process and products to further improve radiation hardening capabilities.
1-7
Integrated
Device
Technology
Static RAM
STATIC RAM PRODUCTS
TABLE OF CONTENTS
PAGE
CONTENTS
Static RAMs
IDT6116A
IDT6167A
IDT6168A
IDT71256
IDT71257
IDT71258
IDT7130/40
IDT7132142
IDT71322
IDT7133/43
IDT7134
IDT71341
IDT7164
IDT7165
IDT71681Al82A
IDT7174
IDT7187
IDT7188
IDT7198
IDT71981/82
Ordering Information
16K (2Kx8) Static RAM ...•..••...........•....................•••....••......
16K (16Kx1) Static RAM ..•.......••••...........••....•.••...................
16K (4Kx4) Static RAM ••...................•.....••••..................•.••..
256K (32Kx8) Static RAM •............••.......••.•.........................••
256K (256Kx1) Static RAM ............•........•.......•.....•.....•.....••..•
256K (64Kx4) Static RAM ..........................................••.....•...
8K (1 Kx8) Dual-Port Static RAM .......•......................••..........••••.
16K (2Kx8) Dual-Port Static RAM ..........•..................•••.••..•.•......
16K (2Kx8) Dual-Port Static RAM ...•••...........•••......••.•................
32K (2Kx16 & 4Kx8) Dual-Port Static RAM ............••...........•............
32K (4Kx8) Dual-Port Static RAM ......•........••••.......•...................
32K (4Kx8) Dual-Port Static RAM ...................•••........................
64K (8Kx8) Static RAM .....................•.......••.......•....•.......•...
64K (8Kx8) Static RAM ••.......•.....••.......••........•....................
16K (4Kx4) Static RAM .........••....•........•.........•...•................
64K (8Kx8) Static RAM ...••..••..........................•.•.................
64K (64Kx1) Static RAM ...•..•...................•.........•.................
64K (16Kx4) Static RAM .........••.•.•.•........•..•..•••••••..••...•••......
64K (16Kx4) Static RAM ..••............••....................................
64K (16Kx4) Static RAM ..••..................................................
2-1
2-8
2-15
2-23
2-25
2-27
2-29
2-41
2-51
2-53
2-55
2-57
2-59
2-67
2-73
2-82
2-89
2-95
2-101
2-108
2-115
FEATURES:
DESCRIPTION:
• High-speed
-Military - 35/45/55170/90/120/150ns (max.)
-Commercial- 30/35/45/55170/90ns (max.)
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as2K x8. It is fabricated using I DT's high-performance,
high-reliability technology - CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques,
provides a cost-effective alternative to bipolar and fast NMOS
memories.
Access times as fast as 30ns are available with maximum
power consumption of only 495mW. The circuit also offers a
reduced power standby mode. When CS goes high, the circuit
will automatically go to, and remain in, a standby power mode as
long as CS remains high. In the standby mode, the low-power
device consumes less than 20"W typically. This capability
provides significant system level power and cooling savings.
The low-power (L) version also offers a battery backup data
retention capability where the circuit typically consumes only
1!'W to 4"W operating off of a 2V battery.
All inputs and outputs ofthe IDT6116SA/LA are TTL-compatible
and operation is from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used, requiring no
clocks or refreshing for operation, providing equal access and
cycle times for ease of use.
The IDT6116SA/LA is packaged in either a24-pin, 600 and 300
mil DIPs or 32- and 28-pin leadless chip carriers, providing high
board-level packing densities.
The IDT6116SA/LA Military RAM is 100% processed in compliance to the test methods of MIL-STD-883, Method 5004,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
• Low-power operation
-IDT6116SA
Active: 180mW (typ.)
Standby: 100!'W (typ.)
-IDT6116LA
Active: 160mW (typ.)
Standby: 20"W (typ.)
• Battery backup operation - 2V data retention voltage (LA
version only)
• Produced with advanced CEMOS'· high-performance
technology
• CEMOS process virtually eliminates alpha particle
soft-error rates (with no organic die coatings)
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Standard 24-pin DIP, 24-pin THINDIP or plastic DIP, 28- and
32-pin LCC, or 24-Lead Flatpack
• Military product available 100% screened to MIL-STD-883,
Class B
PIN CONFIGURATIONS
AS
WE
Ao-A10
AS
1/01-1/08 DATA INPUT/OUTPUT OE
A"
CS
WE
A3
Vcc
A10
cs
A'
ADDRESS
vee
CHIP SELECT
POWER
WRITE ENABLE
OUTPUT ENABLE
GND GROUND
FUNCTIONAL BLOCK DIAGRAM
1108
1/07
1106
1/05
1104
28-PIN LCC
TOP VIEW
SR06116SAlLA·002
24-PIN SIDEBRAZE
TOP VIEW
c~~~~~~
SRD6116SA/LA·001
LOGIC SYMBOL
Ao
A,
A2
A3
""
As
.....
At;
A7
lID,
1/02
liD,
1104
1105
I/0e
1/07
lID,
A4 :::'
.2 ::J.
A3 ::].
A1 ::1'0
Ao ::1"
.. ::: A'0
».0_
n:::
He :],.
lID,
::J~i f51 ;.;
rl r'; ['1 t!~:'
CS
IlOa
1/07
gg~~ggg
A10CSWEOE
32-PINLCC
TOP VIEW
SRD6116SA/LA-003
SRD6116SA/LA-004
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
2-1
JULY 1986
Printed in U.S.A.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6116SAIIDT6116LA CMOS STATIC RAMS 16K (2K xII-Bin
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
VALUE
UNIT
-0.5 to +7.0
V
RATING
Terminal Voltage
with Respect 10 GND
VTERM
GRADE
Military
TA
Operating Temperature
MIL.
COM'L.
-5510 +125
Oto +70
°C
TBIAS
Temperature
Under Bias
MIL.
COM'L.
-65 to +135
-10to +85
°C
Storage Temperalure
MIL.
COM'L.
-65 to +150
-55 to +125
°C
TSTG
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
rnA
AMBIENT
TEMPERATURE
GND
Vee
-55°C to +125°C
OV
5.0V±10%
O°Cto +70°C
OV
5.0V±10%
Commercial
RECOMMENDED DC OPERATING CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
a
a
a
V
V,H
Input High Voltage
2.2
3.5
6.0
V
V,L
I n put Low Voltage
-1.0(1)
-
0.8
V
CL
Output Load
-
-
30
pF
SYMBOL
NOTE:
1.' Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
PARAMETER
NOTE:
indicated in the operational sections of this specification is not Implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
1. V1L =-3.0V for pulse widths less than 20n5.
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 10%, VLe = 0.2V, VHe = Vee - 0.2V
SYMBOL
PARAMETER
IDT6116SA
IDT6116LA
MIN. TYP.(1) MAX. MIN. TYP'(1) MAX.
TEST CONDITIONS
-
-
10
5
-
-
10
5
IILlI
Input Leakage Current
Vee = Max.; Y,N = GND to Vee
MIL.
COM'L.
IILol
Output Leakage Current
Vee = Max.
CS = V,H, VOUT = GND to Vec
MIL.
COM'L.
VOL
Output Low Voltage
IOL = 8mA, Vee = Min.
-
VOH
Output High Voltage
IOH = -4mA, Vee = Min.
2.4
-
-
0.4
-
-
2.4
UNIT
-
-
5
2
itA
-
5
2
itA
-
0.4
V
-
-
V
NOTE:
1. Typical limits are at Vec = 5.0V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS(1)
Vee = 5.0V
SYMBOL
± 10%, Vt.e = 0.2V, \/tie = Vee PARAMETER
POWER
0.2V
3On.
MIL
eOM'L.
ICCI
ICC2
ISB
Operating Power
Supply Current
CS=V,L,
Output Open,
Vcc=Max.,f=O
Dyn. Op. Current
CS=V,L,
Output Open,
Vcc = Max.,
f=fMax.
Standby Power
Supply Current
i!IL Level)
CS 2:V,H,
Vcc = Max.,
Output Open
Full Stdby. Power
Supply Current
C 2: VHC,
Vcc= Max.,
V,N2: VHC or
Y,N:>; VLC
MIL
45n.
COM'L. MIL.
55n.
COM'L. MIL
70ns
COM'L. MIL.
IOn.
COWL. MIL.
SA
80
-
80
90
80
90
80
90
80
90
80
90
LA
75
~
75
85
75
85
75
85
75
85
75
85
SA
110S
100
115
100
100
100
100
100
100
90
LA
105:t-
95
105
90
95
80
90
80
90
SA
asf·
25
35
25
25
25
25
25
11-
25
30
20
20
20
20
It -
2
10
2
10
2
-
0.1
0.9
0.1
0.9
0.1
120n.(3)
COM'L.
MIL.
-
90
UNIT
rnA
LA
SA
~MOSLeVel)
ISBI
35n.(2)
COM'L.
LA
;;;;;;:
~
0.1
100
-
100
75
85
-
85
25
20
25
-
25
15
20
15
15
-
15
10
2
10
2
10
-
10
0.9
0.1
0.9
0.1
0.9
-
0.9
85
rnA
rnA
rnA
NOTE:
1. All values are maximum guaranteed values.
2. O.ta is pre!lmlnary for Military devices.
3. Also available: 15On. Military device.
2-2
IDT6116SAlIDT6116LA CMOS STATIC RAMS 16K (2K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLc
=O.2V, VHC =Vcc -
O.2V
TYPJ1}
SYMBOL
PARAMETER
TEST CONDITION
MIN.
-
VOR
Vcc for Data Retention
ICCOR
Data Retention Current
tCOR (3 )
t R(3 )
Chip Deselect to Data Retention Time
Ilu1 (3)
Input Leakage Current
I COM'L.
MIL.
Operation Recovery Time
UNIT
Vcc @
2.0V
3.0V
2.0
-
-
-
-
V
-
0.5
0.5
1.5
1.5
200
20
300
30
I'A
-
CS ",VHC
V'N '" VHC or ,; VLC
MAX.
Vcc @
2.0V
3.0V
-
-
ns
t Rc (2)
-
-
2
I'A
0
ns
NOTES:
1. TA = +25°C.
2. t RC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
1:r-.--:~--.
r--DATA RETENTION MODE--*j
Vee
eI
---t--~.....,j~
'Olllfv.. \
v"~w
VDR
I
v'''"r\\\\\\'
SRD6116SA/LA~006
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
+5V
GNDt03.0V
5ns
4-
1.5V
DOUT---.-----1
4"""
DOUT-~---i
1.5V
See Figures 1 & 2
5pP
SRD6167~006
Figure 1. Output Load
SRD6167·007
Figure 2. Output Load
(for toLz, tCLl' toHZ'
t WHZ' tCHZ' and tow)
*Including scope and jig.
2-3
IDT6116SAlIDT6116LA CMOS STATIC RAMS 18K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vee = 5V ± 10%. All Temperature Ranges)
SYMBOL
PARAMETER
8118SA3O(1)
6116LA30(1)
MIN. MAX.
6116SA35/4S(4)
6116LA35/4S(4)
MAX.
MIN.
6116SA55
8116LA55
MIN. MAX.
6116SA70
6118LA70
MIN. MAX.
6116SA90
6116LA90
MIN. MAX.
6116SA120(2)
6116LA120(2)
MAX.
MIN.
UNIT
READ CYCLE
70
-
90
-
ns
70
9.0
120
ns
50
65
-
-
-
-
90
-
120
ns
5
-
5
-
5
-
5
-
ns
20/25
-
40
-
50
-
85
-
80
ns
5
-
5
-
5
-
5
-
5
-
ns
-
20/25
-
30
-
35
-
40
-
40
ns
-
20/25
-
30
-
35
-
40
-
40
ns
5
-
5
-
5
-
5
-
5
-
ns
tRC
Read Cycle Time
30
-
35/45
-
55
-
tAA
Address Access Time
-
30
-
35/45
-
55
lAcs
Chip Select Access Time
-
30
-
35/45
-
tClZ
Chip Select to
Output In Low Z(3)
5
-
5
-
tOE
Output Enable to
Output Valid
-
18
-
tOll
Output Enable to
Output in Low Z(3)
5
-
tCHZ
Chip Deselect to
Output In High Z(3)
-
tOHZ
Output Disable to
Output in High Z(3)
-
tOH
Output Hold from
Address Change
5
,»;
i,
~~!-
120
i0:'.
WRITE CYCLE
-,
twc
Write Cycle Time
30*'';: -
35/45
-
55
-
70
-
90
-
120
-
ns
tcw
Chip Select to
End of Write
25/30
-
40
-
40
-
55
-
70
-
ns
tAW
Address Valid to
End of Write
2~J ~", -
25/30
-
45
-
85
-
80
0
5
-
15
-
15
-
ns
Address Setup Time
-
105
tAS
twp
Write Pulse Width
40
-
40
-
55
-
70
ns
tWR
Write Recovery Time
5
-
5
-
5
-
5
-
ns
~:'
.Ill
20/25
0
-
0
-
tOHZ
Output Disable to
Output In High Z(3)
-
18
-
20/25
-
30
-
35
-
40
-
40
tWHZ
Write to Output
in High Z(3)
-
18
-
20/25
-
30
-
35
-
40
-
40
tow
Data to Write
Time Overlap
15
-
15/20
-
25
-
30
-
30
-
35
-
ns
tOH
Data Hold from
Write Time
0
-
0
-
5
-
5
-
5
-
5
-
ns
tow
Output Active from
End of Write(3)
0
-
0
-
0
-
0
-
0
-
0
-
ns
1~g
NOTES:
1. O°C to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. This parameter guaranteed but not tested.
4. Data is preliminary for military devices only.
2-4
20
ns
ns
ns
IDT6116SA/IDT6116LA CMOS STATIC RAMS 16K (2K x 8-BIT)
TIMING WAVEFORMS OF READ CYCLE NO.
ADDRESS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
READ CYCLE
1(1)
2(1,2,4)
-----'I~===.:===~--'I\..-SR06116SA/LA-008
READ CYCLE
3(1,3,4)
OOUT - - - - - - - - - - - - {
SRD6116SA/LA-007
SRD6116SA/LA-009
NOTES:
WE IS High for Read Cycle
2. Device is continuously selected, CS -= VIL
3. Address valid prior to or coincident with CS transition low.
4. OE: = VIL.
5. Transition is measured ±50QmV from steady state with 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
TIMING WAVEFORMS OF WRITE CYCLE 1(1)
(WE CONTROLLED)
TIMING WAVEFORMS OF WRITE CYCLE
(CS CONTROLLED)
2(1)
iwc-----_
ADDRESS
_JIL_ _ _ _ _ _ _ _'IL_ ____
SRD6116SAlLA-Ol1
SRD6116SA/LA-01Q
NOTES:
1.
WE
must be high during all address transitions.
2. A write occurs during the overlap (t wp ) of a low CS and a low WE.
3.
tWA
is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the
6.
5E
CS low transition
occurs simultaneously with the
WE
low transitions or after the
WE
transition, outputs remain in a high impedance state.
is continuously low (OE = V1L ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CS is low during this period, 1/0 pins are
In
the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
2-5
IDT6116SA1IDT6116LA CMOS STATIC RAMS 16K (2K x Il-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
ICC VB. Supply Voltege
ICC VB.
Temperature
I
TA =25 oe
1.2
1.6
Jl
1.0
" 1.1
/
V
\
-"
1.0
ee
\
\ '\
1.2
1.0
"-
.......
-80
Isa1 VB.
Vee=5.0V
Temperature
50
A
Vee=5.0V
1.2
10
\.
1.0
_i
.....
0.9
0.8
o
-80
""
1.0
V
'--
~" ~
)
4
SR06116SAlLA"()16
ICCOR VS.
t AA• tACS VB. Supply Voltage
TA=25 0
10.0
/
Jl
\
)
1.0
6
-80
/
SRD8118SA/lA-018
/
1.1
'"'"
J 1.0
}
!
0.9
0.8
140
SRD6116$AlLA-019
2-6
6
1.2
Veeo.=2.0V
10
o
SRD6116SA/LA-017
Temperatura
100.0
Vee= 6.0V r--
I!
140
-80
8
5
Vee(VI
/
J
/
/
V
o
0.8
140
TA =2JO e
\
6
0.5
Isa1 VS. V IN
I.
_i
/
SRD6116SA/LA-015
o
SA06116SA/LA-014
SRD6116SAJLA-013
T=2Le
_II
10'
8
4
Isa, VB. Supply Voltege
18mpereture
\
10'
'"
V
0.0
140
~
1.1
/
-=
SRD6116SA/LA..()12
ISB VB.
TA=26o e
2.0
o
8
4
I
vlov
0.9
0.6
Isa VB. Supply Voltage
o
4
8
SRD6116SA/LA-020
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6116SA/IDT6116LA CMOS STATIC RAMS 16K (2K x a-BIT)
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
t AA • tACS VS. Output Loading
t AA • tACS VS. Temperature
V CC=5.0V
1.2
Vcc=5.0V
)
/
1.1
J
TA =25°C
1.5
/V
1.0
0.9
V
/
/
/
1.0
/'
./
V
/
/
O.B
0.5
-60
o
140
300
SRD6116SAllA-022
SRD6116SA/LA-Q21
TRUTH TABLE
CAPACITANCE
1/0 OPERATION
MODE
CS
OE
WE
Standby
H
X
X
High Z
Read
Read
L
L
L
DOUT
H
H
H
High Z
Write
L
X
L
DIN
400
TYp.
UNIT
C IN
Input Capacitance
VIN
=OV
6
pF
ClIO
Input/Output
Capacitance
VI/a = OV
8
pF
SYMBOL
PARAMETER(1)
CONDITIONS
NOTE:
1. This parameter is sampled and not 100% tested.
PINOUT CONFIGURATION
16K CMOS SRAM
IDT6116 (2K x 8)
FUNCTION
LOGIC
SYMBOL
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Address Line
Input/Output
Input/Output
Input/Output
Power Ground
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Chip Select/
Data Retention
Address Line
Output Enable
Write Enable
Address Une
Address Line
Power Supply
A,
A6
As
A.
Aa
A,
A,
AD
I/O 1
1/02
1/03
1
2
3
4
5
6
7
8
9
10
GND
24 DIP
PIN NUMBER
28LCC
32LCC
1/06
1/07
1/08
12
13
14
15
16
17
1
2
3
4
5
6
9
10
11
12
13
14
15
16
17
18
19
4
5
6
7
8
9
10
11
13
14
15
16
18
19
20
21
22
CS
18
20
23
~
19
20
21
22
23
24
23
24
25
26
27
28
24
25
26
28
29
32
1/04
1105
WE
Ag
As
Vcc
11
2-7
&I
(TA = +25°C. f = 100M Hz)
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle time)
-Military - 25/35/45/55/70/85/100ns (max.)
-Commercial - 15/20/25/35/45/55ns (max.)
• Low-power consumption
-IDT6167SA
Active: 200mW (typ.)
Standby: 100!'W (typ.)
-IDT6167LA
Active: 150mW (typ.)
Standby: 10!'W (typ.)
• Battery backup operation-2V data retention voltage
(IDT6167LA only)
• High-density 20-pin DIP, 2D-pin plastic DIP and 20-pin
leadless chip carriers
• Produced with advanced CEMOS'· high-performance
technology
The IDT6167 is a 16,384-bit high-speed static RAM organized as
16K x 1. It is fabricated using IDT's high-performance, high-reliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective alternative to bipolar and fast NMOS memories.
Access times as fast as 15ns are available with maximum power
consumption of only 550mW. The circuit also offers a reduced
power standby mode. When CS goes high, the circuit will automatically go to, and remain in, a standby mode as long as CS
remains high. In the standby mode, the device consumes less than
10!'W, typically. This capability provides significant system-level
power and cooling savings. The low-power (LA) version also
offers a battery backup data retention capability where the circuit
typically consumes only l!'W operating off a 2V battery.
All inputs and the output of the IDT6167 are TTL-compatible
and operate from a single 5V supply, thus simplifying system
designs. Fully static asynchronous circuitry is used, which
requires no clocks or refreshing for operation, and provides equal
access and cycle times for ease of use.
The IDT6167 is packaged in either a space-saving 2D-pin, 300
mil DIP or 2D-pin lead less chip carrier, providing high board-level
packing densities.
The IDT6167 Military RAM is 100% processed in compliance to
the test methods of MIL-STD-883, Method 5004, making it ideally
suited to military temperature applications demanding the highest
level of performance and reliability.
• CEMOS process virtually eliminates alpha particle soft-error
rates (with no organic die coatings)
• Separate data input and output
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product available 100% screened to MIL-STD-883,
Class B
PIN CONFIGURATIONS
LOGIC SYMBOL
A.
DOUT
A3
A4
SR06167-003
AS
FUNCTIONAL BLOCK DIAGRAM
AO
DOUT
Ao
Vee
Al
DIP
LCC
TOP VIEW
TOP VIEW
SAD6167-001
.....---GND
A.
Row
A3
Select
SR06167-002
128x 128
Memory Array
A4
PIN NAMES
Al'
A13
Ao-A13
ADDRESS INPUTS
DIN
DATA IN
CS
CHIP SELECT
Dour
DATA OUT
co
WE
WRITE ENABLE
GND
GROUND
D'N
Vee
POWER
__+ __-C~+__-;o:Co='u",m"=n':;::/O,::-_ _-+-C_ DOUT
CEMOS is a trademark of Integrated Device Technology, Inc.
SAD6167·004
MILITARY AND COMMERCIAL TEMPERATURE RANGES
o 1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SAlIDT6167LA CMOS STATIC RAMS 16K (16K x 1-BIT)
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
TA
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
Terminal Voltage with
Respect to GND
-0.5 to +7.0
Operating Temperature
-55 to +125
SYMBOL
UNIT
V
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
-
6.0
V
V,L
Input Low Voltage
-0.511)
-
0.8
V
'c
'c
'c
NOTE:
1. V1L min:::: -3.0V for pulse width less than 20n5.
TSIAS
Temperature Under Bias
-65 to +135
TSTG
Storage Temperature
-65 to +150
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
AMBIENT
TEMPERATURE
GND
-55'C to +125'C
OV
5.0V ± 10%
O'C to +70'C
OV
5.0V± 10%
Commercial
Vee
DC ELECTRICAL CHARACTERISTICS
± 10%, 'tc = 0.2V, VHC = VCC - 0.2V
Vcc = S.OV
SYMBOL
PARAMETER
IDT6167SA
IDT6167LA
MIN. TYP.(') MAX. MIN. TYP.(') MAX.
TEST CONDITIONS
Input Leakage Current
Vee = Max.; V,N = GND to Vee
MIL.
COM'L.
-
liLeI
Output Leakage Current
Vee = Max.
CS = V,H. VOUT = GND to Vee
MIL.
COM'L.
-
-
-
VOL
Output Low Voltage
lOL - 12mA, Vee - Min.
VOH
Output High Voltage
IOH = -4mA, Vee = Min.
/lui
-
UNIT
10
5
-
-
-
5
2
p.A
-
-
-
10
5
-
-
5
2
p.A
-
-
0.4
-
-
0.4
V
2.4
-
-
2.4
-
-
V
-
NOTE:
1. Typical limits are at Vee = S.OV, +25 Q C ambient.
DC ELECTRICAL CHARACTERISTICS(1)
Vcc = S.OV ± 10%, VLC = O.2V, VHC = Vcc - 0.2V
SYMBOL
PARAMETER
15ns
POWER
lee1
Ice2
ISB
ISB1
Operating Power
Supply Current
CS = V ,L,
Output Open,
V ce" Max., f = 0
Dyn. Op. Current
CS = V IL,
Output Open,
Vce" Max.,
f= f Max.
Standby Power
Supply Current
(TTL Level)
CS 2':V ,H ,
Vec=Max.,
Output Open
Full Stdby. Power
Supply Current
(CMOS Level)
CS 2': V HC'
Vee" Max.,
V 1N 2::: V HC or
20ns
MIL.
COM'l.
COM'l.
25ns
MIl.
35no
45n.
70n.(2)
55ns
COM'l.
MIl.
COM'l.
MIl.
COM'L.
MIl.
COM'l.
MIl.
COM'l.
MIl.
SA
90
-
90
-
90
90
90
90
90
90
90
90
-
90
LA
-
ce&
55
-
55
60
55
60
55
60
55
60
-
60
SA
100
100
-
100
100
100
100
100
100
100
100
-
100
LA
-
-
80
-
70
75
65
70
60
65
55
60
-
60
-
35
-
35
35
35
35
35
35
35
35
-
35
"-
30
-
25
25
20
20
15
20
15
20
-
15
-
5
-
5
10
5
10
5
10
5
10
-
10
-
0.05
-
0.05
0.9
0.05
0.9
0.05
0.9
0.05
0.9
-
0.9
UNIT
mA
"
.....
. ';
w
mA
~,
SA
35'
LA
t-i
SA
"
,':'~
,
mA
mA
LA
-
VIN~VI!.C
NOTE:
1. All values are maximum guaranteed values.
2. Also available: 85 and 1DOns Military devices.
2-9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT6167SAlIDT6167LA CMOS STATIC RAMS 16K (16K x I-BIT)
DATA RETENTION CHARACTERISTICS
(L Version Only) VLC =O.2V,VHc
SYMBOL
=Vcc - O.2V
PARAMETER
TEST CONDITION
MIN.
TYP'(1)
MAX.
Vcc @
Vcc @
3.OV
2.0V
VOR
-
Vcc for Data Retention
ICCOR
Data Retention Current
tCOR
Chip Deselect to Data
Retention Time
i R(3)
Operation Recovery Time
II Ll I(3)
Input Leakage Current
I
MIL.
COM'L.
CS~VHC
Y'N ~ VHC or ,,; VLC
2.0V
UNIT
3.OV
2.0
-
-
-
-
-
0.5
0.5
1.0
1.0
200
20
300
30
0
-
t RC(2)
-
-
V
I'A
-
ns
2
I'A
ns
NOTES:
1. TA = +25°C.
2.
t RC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
Vee
~
DATA RETEN110N MODE_t
4.5Y
4.5V
VDR"2:2V
tA-j
~
Ci
'070~v..'
VDA
I
VIH\\\\\\'
SR06167-005
+5V
.5V
48O''
::"*
I''ki'
45no
COM·L. MIL.
55no
COM·L. MIL.
70n5(2)
COM'L.
MIL.
MIL.
100
90
100
90
100
90
100
-
100
80
70
80
70
80
70
80
80
110
120
100
110
100
110
100
110
-
110
90
100
80
90
70
80
70
80
-
80
UNIT
mA
mA
35
45
30
35
30
35
30
35
-
35
-
25
30
20
25
20
25
20
20
-
20
-
2
10
2
10
2
10
2
10
-
10
-
0.05
0.3
0.05
0.3
0.05
0.3
0.05
0.3
-
0.3
.,
-I
35no
COM'L.
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. Also available: 85 and 100ns military devices.
2-16
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)
DATA RETENTION CHARACTERISTICS
SYMBOL
VDR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(L Version Only)
PARAMETER
TEST CONDITIONS
MIN.
Vee for Retention Data
MIL.
leeDR
CS '" Vee - 0.2V
V'N'" Vee - 0.2V
or:s 0.2V
Data Retention Current
I
t e OR(5)
tR(5)
COM'L.
Chip Deselect to Data Retention Time
IDT76168SAlLA
TYP.(')
UNIT
MAX.
2.0
-
-
V
-
0.5(2)
1.0(3)
100(2)
150(3)
p.A
0.5(2)
1.0(3)
20(2)
30(3)
p.A
0
-
-
ns
t Re (4)
Operation Recovery Time
ns
NOTES:
1. TA = 25°C.
2.
3.
at Vee = 2V
at Vee = 3V
4. t RC = Read Cycle Time
5. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
~Data RelantionMode_
Vee
C.SY
r
cs
tCDR
f\..
I
VDR;;,2V
'--_---=.:=~-..1
4.SV
II
-
'Z07lfVIH '
VD.
58D6168-005
Input Pulse Levels
Input Riseand Fall Times
InputTimlng Reference Levels
Output Reference Levels
Output Load
+5V
+5V
AC TEST CONDITIONS
4IOQ
GNDt03.0V
DOUT'-~--~
5ns
1.5V
DoUT---?'---1
3OpF*
5pF*
860616&006
5506168-007
1.5V
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Output Load
(for t HZ' t LZ' twz. and tow)
·Including scope and Jig.
2·17
IDT6168SAlIDT6168LA CMOS STATIC RAM 16K (4k X 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vee = 5V ± 10%, All Temperature Ranges)
SYMBOL
PARAMETER
6168SA20(1 )
6168LA20 (1 )
MIN.
MAX.
6168SA25
6168LA25
MIN. MAX.
6168SA35
6168LA35
MIN. MAX.
6168SA45
6168LA45
MIN. MAX.
6168SA55
6168LA55
MIN.
MAX.
6168SA 701')
6168LA701')
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
20
-
25
-
35
-
45
-
55
-
70
-
ns
tAA
Address Access Time
-
20
-
25
-
35
-
45
-
55
-
70
ns
t ACS
Chip Select Access Time
-
20
-
25
-
35
-
45
-
55
-
70
ns
tOH
Output Hold from
Address Change
5
-
5
-
5
-
5
-
5
-
5
-
ns
tLZ
Chip Selection to
Output in Low Z13)
5
5
-
5
-
5
-
5
-
5
-
ns
tHZ
Chip Deselect to
Output in High Z13)
-
-
10
-
15
-
15
-
25
-
30
ns
tpu
Chip Select to
Power Up Time (3)
0
0
-
0
-
0
-
0
-
0
-
ns
tpo
Chip Select to
Power Down Time(3)
-
-
25
-
35
-
40
-
50
-
60
ns
t RCS
Read Command
Set-Up Time
-
-5
-
-5
-
-5
-
-5
-
-5
-
ns
tRCH
Read Command
Hold Time'
·«44.: -
-5
-
-5
-
-5
-
-5
-
-5
-
ns
-
20
-
30
-
40
-
50
-
60
-
ns
-
20
-
30
-
40
-
50
-
60
-
ns
WRITE CYCLE
twc
Write Cycle Time
tcw
Chip Select to
End of Write
tAW
Address Valid to End
of Write
tAS
Address Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
4.'>
-!i
~
M
-5
jn~<
l
-
20
-
30
-
50
-
60
-
ns
0
-
a
-
40
-
a
a
-
a
-
ns
20
-
20
-
30
-
40
50
-
60
-
0
-
a
-
a
a
0
Data Valid to End of Write
13
-
13
-
17
-
20
20
-
-
ns
a
25
-
ns
tOH
Data Hold Time
3
-
3
-
3
-
3
-
3
-
3
-
ns
twz
Write Enable to
Output in High ZIS)
-
7
-
7
-
13
-
20
-
25
-
30
ns
tow
Output Active from
End of Write IS)
a
-
0
-
a
-
a
-
a
-
a
-
ns
NOTES:
1. Available over DOC to + 700 e temperature range only.
2. Available over -55°C to +125°C temperature range only. Also available: 85 and 100ns military devices.
3. This parameter is guaranteed but not tested.
2-18
ns
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K 14K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2)
't
Address
======,,::::'.e·~:I_
L-
-='"1~
Data Dul
i X X J:)K_ _
"""'au. Data Valid
Data Valid
1;'~-,Re·--------lt
------------------t~'~K..-*
tHz'1l1--:=~
TIMING WAVEFORM OF READ CYCLE NO. 2(1,3)
~
----------------
D.,.Ou' Icc
-------~----tP-D.
1
~=¥.....L.-1--=
.
vccc~=:
.I--r--
DataV.Ii.
~tpu'''L
~
IS8
-:...-.l-_.RCHt_
es_ _ _
8806168-009
NOTES: 1.
2.
3.
4.
WE is high for READ cycle.
CS is low for READ cycle.
Address valid prior to or coincident with CS tranSition low.
Transition is measured ±200mV from steady state Yoltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
5. All READ cycle timings are referenced the last valid address to the first transitioning address.
6. This parameter is sampled and not 100% tested.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
.
'we
Add....
~
--I
I
'ew
,\ ~\\
.:\\\\' .\\\\
twR-
'AW
'WP
~ ..._.~~S
D.tal.
D... Out
I--'ow~I ~. _.
~-----,r=----------.;..._~
!--IDH-
Oata V.H.
I-Iwz'j
DataUndetlnacl
r--tow.'~....--
_
HIgh Impedance
....._ __
8806168-010
2-19
IDT6168SAlIDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
1 _ - - - - - - -t wc 3- - - - - - -. .1
Address
I----tcw-----I
Data In
Data Undefined
Data Out
High Impedance
8506168-011
NOTES: 1. CS or WE must be high during address transitions.
2. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured ± 200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
TRUTH TABLE
CAPACITANCE (TA = +25°C, f
MODE
CS
WE
OUTPUT
POWER
Standby
H
X
High Z
Standby
Read
L
H
DOut
Active
Write
L
L
HlghZ
Active
= 1.0MHz)
PARAMETER(1)
CONDITIONS
TYP.
C 'N
Input Capacitance
Y,N = OV
5
pF
C OUT
Output Capacitance
VOUT = OV
7
pF
SYMBOL
UNIT
NOTE:
1. This parameter is sampled and not 100% tested.
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
ICC vs. Supply Voltage
I
V cc=5.0V
T =21S0C
A
1.5
1.0
.5
4.0
ISB vs. Supply Voltage
ICC vs. Temperature
TJ5 C
0
A
1.5
1.5
/
V
1.0
~ .........
1.0
~
6.0
.5
-60
~
140
2-20
.5
4.0
/
/
6.0
IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL DC AN D AC CHARACTERISTICS
158 vs. Temperature
ISBl vs. Supply Voltage
ISBl vs. Temperature
I
Vcc =5.0V
TA
100.0
0
'~~J
1.2
1.5
1.0
=J5 C
"" '"
.
...........
1.0
5
-60
/
/
r--
10.0
1.0
140
V
./
o
0.8
4.0
6.0
-60
ICCDR vs. Temperature
100.000
100.0
V CC -5V
1\
10.000
II
~
1.000
1\
10.0
\
100
IceDR
1.0
10.0
1.0
J
o
5
2
o
V
/
TAIOJI
1.2
t AA • t ACS
V
.8
4.0
140
t AA • t ACS vs. Temperature
VCC=5V
V
cc
TA=25
1.2
/
.8
-60
V
//
1.2
/
t AA. tACS
1.0
.8
140
2-21
/
/
V
/
o
~
6.0
t AA • t ACS vs. Output Loading
V '=5V
1.0
""
1.0
./
·60
6
140
tAA t ACS vs. Supply Voltage
'~""V
TA =25°
v
200
FEATURES:
DESCRIPTION:
• High-speed address/chip select access time
-Military: 55/70/85ns (max.)
- Commercial: 45/55/70ns (max.)
The IDT71256 is a 262,144-bit high-speed static RAM organized
as 32K x 8. It is fabricated using IDT's high-performance, highreliability CEMOS technology.
Address access times as fast as 45ns are available with
typical power consumption of only 300mW. The circuit also
offers a reduced power standby mode. When CS goes high, the
circuit will automatically go to, and remain in, a low-power
standby mode. In the full standby mode, the low-power device
consumes less than 50/lW, typically. The low-power version (L)
offers a battery backup data retention capability where the circuit
typically consumes only 20/lW operating off a 2V battery.
All inputs and outputs of the IDT71256 are TTL-compatible
and operation is from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used, requiring no
clocks or refreshing for operation.
The IDT71256is packaged in eithera28-pin 400 mil THINDIp, a
28-pin 600 mil DIP or 32-pin lead less chip carrier, providing high
board-level packing densities.
The 1DT71256 Military RAM is 100% processed in compliance
to the test methods of MIL-STD-883, Method 5004, making it
ideally suited to military temperature applications demanding
the highest level of performances and reliability.
• Low-power operation
-IDT71256S
Active: 300mW (typ.)
Standby: 200/lW (typ.))
-IDT71256L
Active: 250mW (typ.)
Standby: 50/lW (typ.)
• Battery backup operation -
2V data retention
• Produced with advanced high-performance CEMOS'·
technology
• Single 5V (±10%) power supply
• Input and output directly TTL compatible
• Th ree-state output
• Static operation: no clocks or refresh required
• Standard 28-pin DIP (600 mil), 28-pin THINDIP (400 mil)
and 32-pin LCC
• Pin compatible with standard 256K static RAM and EPROM
• Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
AO
----0 vee
----OGND
ROW
DECODER
512 x 512
MEMORY ARRAY
As
1/01
INPUT
DATA
CIRCUIT
I/0s
CS
OE
CONTROL
CIRCUIT
WE
SRD71256.()Q1
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 1986
Printed in U.S.A.
01986 Integrated Oevice Technology, Inc.
2-23
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT71256S/IDT71256L CMOS STATIC RAMS 256K (32K x a-BIT)
PIN CONFIGURATIONS
Vee
WE
A'4
A'2
A7
At;
A13
As
As
At;
A9
A4
A3
A"
OE
A2
A,
C5
Ao
1/0,
I/0s
1102
1/03
1/06
1/05
GND
1/04
A2
A,
An
J11
23[
NC
J12
22[
~
A3
A,o
1/07
A.
J6
J'
J.
J.
JlO
As
2S[
As
27[
A11
NC
26[
2S[
OE
24[
A,.
CS
1/0,
.. '" cz 0
z
00
~;;:;::"
DIP
TOP VIEW
1/0.
1/0,
g" g g
on
LCC
TOP VIEW
SAD71256-003
SRD71256-002
LOGIC SYMBOL
PIN NAMES
AO_14
1/0,
1/02
1/03
1/04
1/05
1/06
1/07
I/0s
SRD71256-004
2-24
Addresses
1/01-8
Data Inpul/Output
CS
Chip Select
WE
Write Enable
OE
Output Enable
GND
Ground
Vee
Power
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle times)
-Military - 45/55/70/85ns max.
-Commercial - 35/45/55/70ns max.
The IDT71257, a 262, 144-bit high-speed static RAM organized
as 256K x 1, is fabricated using IDT's high-performance, highreliability technology - CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost effective approach for memory intensive applications.
Access times as fast as 45ns are available, with typical power
consumption of only 400mW. The IDT71257 offers a reduced
power standby mode, IS81' which enables the designer to greatly
reduce device power requirements. This capability significantly
decreases system power and cooling levels, while greatly enhancing system reliability. The low-power (L) version also offers
a battery backup data retention capability where the circuit
typically consumes only 80p.W when operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a
single 5 volt supply. Fully static asynchronous circuitry, along
with matching access and cycle times, favor the simplified system design approach.
The IDT71257 is packaged in a 24-pin, 300 mil DIP providing
excellent board-level packi ng densities.
The IDT71257 military RAM is 100% processed in compliance
to the test methods of MIL-STD-883, Method 5004, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
• Low-power operation
-IDT 71257S
Active: 400mW (typ.)
Standby: 400l'W (typ.)
-IDT 71257L
Active: 350mW (typ.)
Standby: 100l'W (typ.)
• Battery backup operation - 2V data retention
(L version only)
• High-density industry standard 24-pin, 300 mil DIP
• Produced with advanced CEMOS" technology
• Separate data input and output
• Single 5V (±10%) power supply
• Inputs/outputs TTL-compatible
• Three state outputs
• Static operation - no clocks or refresh required
• Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
Vee
GND
C
ROW
ADDRESSES
m
o
oC
262,144-BIT
MEMORY ARRAY
m
:D
COLUMN I/O
DoUT
CEMOS is a trademark 01 Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
.1986 Integrated Device Technology. Inc.
2-25
IDT71257S/IDT71257L CMOS STATIC RAMS 256K (256K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN NAMES
PIN CONFIGURATION
AD-17
Address Inputs
Ao
Vee
D'N
Data In
Al
An
DOUT
Data Out
~
A3
A16
CS
Chip Select
WE
Write Enable
A,
Al "
-'1.
-'13
A12
A11
As
-'10
A..
As
As
As
DOUT
WE
D'N
CS
Vss
DIP
TOP VIEW
SRD712S7-002
LOGIC SYMBOL
SRD71257-0oa
2-26
Vee
Power
GND
Ground
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle times)
-Military - 45/55/70/85ns max.
-Commercial - 35/45/55nOns max.
The IDT71258, a 262,144-bit high-speed static RAM organized
as 64K x 4, is fabricated using IDT's high-performance, highreliability technology - CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques,
provides a cost effective approach for memory intensive
applications.
Access times as fast as 35ns are available, with typical power
consumption of only 4oomW. The IDT71258 offers a reduced
power standby mode, 18B1' which enables the designer to greatly
reduce device power requirements. This capability significantly
decreases system power and cooling levels, while greatly enhancing system reliability. The low-power (L) version also offers
a battery backup data retention capability where the circuit
typically consumes only 80J.!W when operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a
single 5 volt supply. Fully static asynchronous circuitry, along
with matching access and cycle times, favor the simplified
system design approach.
The 1DT71258 is packaged in a 24-pin, 300 mil DIP providing
excellent board-level packing densities.
The IDT71258 military RAM is 100% processed in compliance
to the test methods of MIL-STD-883, Method 5004, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
• Low-power operation
-IDT71258S
Active: 400mW (typ.)
Standby: 400J.!W (typ.)
-IDT71258L
Active: 350mW (typ.)
Standby: 100J.!W (typ.)
• Battery backup operation - 2V data retention
(L version only)
•
•
•
•
•
•
•
•
High-density industry standard 24-pin, 300 mil DIP
Produced with advanced CEMOS'· technology
Bidirectional data inputs and outputs
Single 5V (±10%) power supply
Inputs/outputs TTL-compatible
Three state outputs
Static operation - no clocks or refresh required
Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
ADDRESSES
•
•
SELECT.
Vee
GND
262,144-BIT
MEMORY ARRAY
• • • ••
COLUMN 1/0
WEJ-JL~--------------------~
SR071258-OQ1
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
CI 1986 Integrated Device Technology, Inc.
2-27
IDT71258S/IDT71258L CMOS STATIC RAMS 256K (64K.x 4oBIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PIN NAMES
As
Vee
AI
~
~
"-Is
AI.
A13
As
Au
As
A"
AID
110.
1103
As
A,
Ae
Ae
es
110.
1101
Vss
WE
DIP
TOP VIEW
SRD71258-Q02
LOGIC SYMBOL
SR071258-003
2-28
AG-15
Address Inputs
1101-4
Data InpuVOutput
CS
Chip Select
WE
Write Enable
Vee
Power
GND
Ground
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 70/90/100/120ns (max.)
-Commercial: 55170/90/1oons (max.)
• Low-power operation
-IDT7130/40S
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT7130/40L
Active: 325mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7130 easily expands data bus width to
16-or-more bits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 only)
• BUSY output flag on IDT7130; BUSY input on IDT7140
• INT flag for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation - 2V data retention
• TTL compatible, single 5V ± 10% power supply
• Military product 100% screened to MIL-STD-883, Class B
The IDT7130/IDT7140 are high-speed 1K x 8 dual-port static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM together with
the IDT7140 "SLAVE" dual-port in 16-bit-or-more word width
systems. Using the lOT MASTER/SLAVE dual-port RAM
approach in 16-or-more-bit memory system applications results
in full-speed, error-free operation withoutthe need for additional
discrete logic.
Both devices provide two independent ports with separate
control, address and 1/0 pins that permit independent, asynchronous access for reads or writes to any location in memory. An
automatic power down feature, controlled by CE, permits the
on-chip circuitry of each port to enter a very low standby power
mode.
Fabricated using lOT's CEMOS'· high-performance technology, these devices typically operate on only 325mW of power
at maximum access times as fast as 55ns. Low-power (L) versions offer battery backup data retention capability, with each
dual-port typically consuming 2OO!-'W from a 2V battery.
The IDT713017140 devices are packaged in 48-pin sidebraze,
plastic DIP, 48- or52-pin LCC and 52-pin PLCC, with the military
devices available 100% processed in compliance to the test
methods of MIL-STD-883, Method 5004.
R/WR
R/WL
CER
DER
CiiL
eEL
All
A,.
A,.
A'L
I/OOL
I/OOA
I/00L
II07R
AuL
Ago
AuL
A..
---------.....J
INTLI2I ...
'------------.INTft(1)
SRD7130-002
NOTES:
1. IDT7130 (master): BUSY is open drain output and requires pullup resistor.
IDT7140 (slave): BUSY Is Input.
2. Open drain output: requires pull up resistor.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-29
&I
IDT7130S/l AND IDT7140S/l
CMOS DUAL-PORT RAMS 8K 11K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
~
~ ~ ~I~ ~ ~
CEL
Vee
RIWL
CER
BUSYl
INTL
OEL
AOL
All
A2L
A3L
I!_Z
~
~ ~I~ ~ ~
"Ii!'
"I!Z
m IUW >ulwli!'
0
m _ low
U
~
~
6 .." .. " Lol L.I I. .. II ................ 1,,1 .... 43
:: 7
5 4 3 2
48 47 46 4S 44 42 t:
U
AOR
1
A1R
RtWR
A1l
BUSYR
A2L
INTR
A3l
DER
:]8
::19
A4L
:::::10
A3R
ASL
~A
A7l
::J11
::! 12
::: 13
A8L
:::: 14
A7R
A'L
A'L
1/001..
AOR
A••
A,.
A,.
A,.
A,.
A,.
A7.
As.
A9R
I/01L
I/0 7R
A'L
A5L
A6L
A7L
c0lw
0
lIOn
I/06R
I/03L
1I0SR
I/04L
I/04R
I/OSL
II03R
1/06L
I/02R
I/07L
GND
I/01R
A6L
A9L
A2A
ASR
ASR
J 15
ASR
~~
J~
I/O lL.
::J 17
32:::
I/07R
~
1/02L
:::: 18 20 21 22 23 24 25 26 27 28 29 311:
19" r, n n n n " " " " r'l "30
I/OaR
SRD7130-0Q4
48-PIN lee
TOP VIEW
IIOOR
SA07130-003
DIP
TOP VIEW
52-PIN lee & PlCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VrERM
TA
TBIAS
TSTG
PT
lOUT
NOTE.
RATING
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
SYMBOL
MIN.
TYP.
MAX.
UNIT
-0.5 to +7.0
V
Vee
Supply Voltage
4.5
5.0
5.5
V
-55 to +125
-65 to +135
-65 to +150
1.0
50
°C
°C
°C
GND
Supply Voltage
0
0
o·
V
Input High Voltage
2.2
-
6.0
V
Input Low Voltage
-0.5(1)
-
0.8
V
V,H
V'L
NOTE:
W
mA
PARAMETER
1. V1L = -3.0V for pulse width less than 20ns.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
2-30
AMBIENT
TEMPERATURE
GND
Vec
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
IDT7130S/L AND IDT1140S/L
CMOS DUAL-PORT RAMS 8K (lK x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
PARAMETER
SYMBOL
(Vee = S.OV
± 10%)
IDT1130S
IDT1140S
MIN.
MAX.
TEST CONDITIONS
IDT1130L
IDT7140L
MIN.
MAX.
UNIT
!Ill I
Input Leakage Current
Vee = 5.5V. V'N = OV to Vee
-
10
-
5
Jl.A
IILOI
Output Leakage Current
CE = V'H' VOUT = OV to Vee
-
10
-
5
Jl.A
V'H
Input High Voltage
2.2
6.0
2.2
6.0
V
V,"
Input Low Voltage
-1.0'"
0.8
-1.0")
0.8
V
-
0.4
-
0.4
V
-
0.5
-
0.5
V
2.4
-
2.4
-
V
1--_ VOL
Output Low Voltage (1/0 0 - 110,)
Open Drain Output Low
10l
=4.0mA
=16mA
Val
Voltage (BUSY, INT)
10l
VOH
Output High Voltage
10H = -4mA
NOTES:
1. V1L min. ". -3.5V for pulse width less than 30ns.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
SYMBOL
Icc
ISB1
ISB2
ISB3
ISB'
PARAMETER
TEST CONDITION
VERSION
(Vee = S.OV ± 10%)
7130x55(2)
7140x55
7130x70
7140x70
7130x90/l00
7140x90/l00
7130x120(3)
7140x120
MIL.
S
L
-
-
65
65
225
180
65
65
185
150
65
65
185
150
COML.
S
L
65
65
170
120
65
65
170
120
65
65
170
120
-
-
MIL.
S
L
-
-
25
25
65
55
25
25
65
45
25
25
45
COML.
S
L
25
25
65
45
25
25
60
25
25
50
30
-
-
40
CEl or CE R 2> V'H
Active Port Outputs
Open
MIL.
S
L
-
-
40
40
135
110
40
40
125
100
40
40
125
100
COM·L.
S
L
40
40
115
85
40
40
110
85
40
40
110
75
-
-
Full Standby Current
(Both Ports-All
CMOS Level
Inputs)
Both Ports CEl and
CE R ? Vee - 0.2V
V'N 2> Vee - 0.2V or
V'N:5 0.2V
MIL.
S
L
-
-
-
-
1
0.2
30
10
1
0.2
30
10
1
0.2
30
10
COM·L.
S
L
1
0.2
15
4
1
0.2
15
4
1
0.2
15
4
-
-
-
Full Standby Current
(One Port-All
CMOS Level
Inputs)
One Port CEl or
CE R 2> Vee - 0.2V
V'N 2> Vee - 0.2V or
V'N:5 0.2V
Active Port Outputs
Open
MIL.
S
L
-
-
-
40
35
110
80
40
35
110
80
40
35
110
80
COM·L.
S
L
40
35
90
70
40
35
90
70
40
35
90
-
-
Dynamic Operating
Current (Both Ports
Active)
CE = V,"
Outputs Open
Standby Current
(Both Ports-TTL
Level Inputs)
CEl and CE R 2> V'H
Standby Current
(One Port-TTL
Level Inputs)
NOTES:
1. X in part numbers represents versions (8 or L).
2. Available in Commercial
aoe to +70°C temperature range only.
3. Available in Military -55°C to +125°C temperature range only.
4. Vcc = 5V. TA = +25°e.
2-31
UNITS
TYP(') MAX TYP(4) MAX TYP(') MAX TYP(') MAX
mA
65
mA
-
mA
-
mA
mA
65
IDT7130S/L AND IDm40S/L
CMOS DUAL-PORT RAMS 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (L Version Only)
SYMBOL
VCR
Vee for Retention Data
leecR
Data Retention Current
tecR(3)
Chip Deselect to Data Retention Time
t R(3)
IDm30LlIDT7140L
TYP'(I)
MIN.
MAX.
TEST CONDITIONS
PARAMETER
Vee = 2.0V, CE '" Vee - 0.2V
Y'N '" Vce -0.2V or Y'N '" 0.2V
Operation Recovery Time
I MIL
I COM'L.
-
-
V
-
100
4000
p.A
100
1500
p.A
0
-
-
ns
t Rc l»
-
-
ns
NOTES:
1. Vee = 2V, TA = +25°C.
2. t RC = Read Cycle Time.
3. This paralT!eter is guaranteed but not tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDA 2:2V
YD.
YIHts\\\\'
SAD7130-020
AC TEST CONDITIONS
GNDt03.0V
5ns
1.5V
1.5V
See Figures 1, 2, and 3
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5Y
+5Y
1250n
DOUT-.....- - 4
nsn
+5Y
12500
DOUT-~--""
lOOp.·
non
SpF.
SRD7130-0Q6
SRD7130-005
Figure 1.
Output Load
Figure 2.
Output Load
(for tHz, t LZ' twz, and tow)
"Including scope and Jig.
2-32
UNIT
2.0
SRD7130-007
Figure 3.
BUSYandlNT
Output Load
(IDT7130 only)
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS aK (1K
x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
IDT7130S/LSS(2)
IDT714OS/LSS(2)
MIN.
MAX.
IDT7130S/L70
IDT714OS/L70
MIN.
MAX.
IDT713OS/L90 IDT7130S/L100 IDT7130S/L 120(3)
IDT7140S/L90 IDT7140S/L100 IDT7140S/L 120(3)
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT
READ CYCLE
t RC
Read Cycle Time
55
-
70
-
90
-
100
-
120
-
tM
Address Access Time
-
55
-
70
-
90
-
100
120
ns
t ACE
Chip Enable Access Time
-
55
-
70
-
90
-
100
120
ns
tAOE
Output Enable Access Time
-
35
-
40
-
40
-
40
-
60
ns
tOH
Output Hold From Address Change
0
-
0
-
10
-
10
10
-
ns
ns
tLZ
Output Low Z Time(1,,)
5
-
5
-
5
-
5
-
5
-
ns
tHz
Output High Z Time n .. )
-
30
-
35
-
40
-
40
-
40
ns
tpu
Chip Enable to Power Up Time(4)
0
-
0
-
0
-
0
-
0
-
ns
tpo
Chip Disable to Power Down Time(4)
-
50
-
50
-
50
-
50
-
50
ns
120
-
ns
100
-
ns
100
-
ns
.
WRITE CYCLE
twc
Write Cycle Time(10)
55
-
70
-
100
Chip Enable to End of Write
40
-
50
-
90
tEW
85
-
90
tAw
Address Valid to End of Write
40
-
50
-
85
-
90
-
0
50
t AS
Address Setup Time
0
twp
Write Pulse Width
40
tWR
Write Recovery Time
0
-
tow
Data Valid to End of Write
20
-
30
-
tHz
Output High Z Time(1,,)
-
30
-
35
tOH
Data Hold Time
0
-
0
twz
Write Enabled to Output in High Z(1.4)
-
30
tow
Output Active From End of Write(1")
0
0
-
0
-
0
-
ns
60
-
60
70
-
ns
0
-
0
0
-
ns
40
-
40
-
40
-
ns
40
-
40
-
40
ns
-
a
-
0
-
0
-
ns
-
35
0
40
0
40
0
50
ns
-
0
-
0
-
0
-
0
-
ns
0
BUSY TIMING
tWB
Write to BUSY (5,8)
-10
-
-10
-
-10
-
-10
-
ns
Write Hold After BUSy(9)
20
-
20
-
20
-
-10
tWH
20
-
20
-
ns
tSAA
BUSY Access Time to Address
-
45
-
45
-
45
-
50
-
60
ns
tBDA
BUSY Disable Time to Address
-
40
-
40
-
45
-
50
-
60
ns
t SAC
BUSY Access Time to Chip Enable
-
35
-
35
-
45
-
50
-
60
ns
tsoc
BUSY Disable time to Chip Enable
-
30
-
30
-
45
-
50
-
60
ns
tWDD
Write Pulse to Data Delay(6)
-
80
-
90
-
100
-
120
-
140
ns
tODD
Write Data Valid to
Read Data Delay(6)
-
55
-
70
-
90
-
100
-
120
ns
tAPS
Arbitration Priority Set Up Time
5
-
5
-
5
-
5
-
5
-
tsoo
BUSY Disable to Valid Data(7)
-
Note 7
-
Note 7
-
Note 7
-
Note 7
-
Note 7
ns
-
-
ns
-
ns
70
ns
60
a
a
-
70
ns
ns
INTERRUPT TIMING
t AS
Address Set Up Time
0
-
0
-
a
a
-
Write Recovery Time
a
a
-
tWR
tiNS
Interrupt Set Time
-
45
-
50
-
55
a
a
-
t'NR
Interrupt Reset Time
-
45
-
50
-
55
-
NOTES:
-
60
6. Port to port delay through RAM cells from writing port to reading port.
1. Transition is measured ±50QmV from low or high impedance voltage with
load (Figures 1, 2 & 3).
7. t sDo is a calculated parameter and is the greater of 0, twoo - twp (actual)
2. Available over O°C to +70°C temperature range only.
8. To ensure that the write cycle is inhibited during contention.
or tODD - tow (actual).
9. To ensure that a write cycle is completed after contention.
3. Available over -55°C to +125°C temperature range only.
4. This parameter guaranteed but not tested.
10. For MASTER/SLAVE combination, twc = tBAA + tWA + t wp ·
5. For Slave part (IDT7140) only.
2-33
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS 8K
11 K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 EITHER SIDE(1,2,6)
~-
fL, ~---+I'RC-----Il,~_
r-------------------------~
D~AO~ ____P_R_EV_'D_U_S_D_AT_A_V_AL_'__
D ~~~~I'-----------D-A-T-A-VA-L_'D__________- J
SRD7130~008
TIMING WAVEFORM OF READ CYCLE NO.2 EITHER SIDEll,3)
lACE
-}-
I+--"OE-
'!--'HZ-
I--'.Z ---+j
if f
~_\. \.
..I
DATAouT
I.
~Ipu
ICC
CURREr:
::::::l
I.Z
~
VALID DATA
---"
---------------J"" so_.
SAD713G-009
TIMING WAVEFORM OF READ
WITH BUSY
ADD. ~
TIMING WAVEFORM OF WRITE
WITH BUSY
MATCH
VALID
X.....
1
BUSY.
\.. -\
---t=:==JrI.'WH-j
R~
_ ~lw.J-I
X
BUSY,
MATCH
tBDA_
~BDD"
i-
SAD7130-024
!woo
VALl o
DOUTL
--'000-
CAPACITANCE (TA =+25°C, f = 1.0MHz)
SRD7130..Q23
PARAMETER(1)
CONDITIONS
TYP.
UNIT
C 'N
Input Capacitance
Output Capacitance
10
10
pF
C OUT
=OV
VOUT =OV
SYMBOL
Y,N
NOTE:
1. This parameter is sampled and not 100% tested.
2-34
pF
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 EITHER SIDE(4,7)
Iwe
ADDRESS
~
---'
L
lEW
I' t\
II III
J'AW
i--'WR-
Iwp
lAS
\\\
RM
•
lOW
f-\c
DATAIN
10H
DATA VALID
I
\ \ \'
LLL,HZHI GH I MPEDANCE
DATAOUT
SR07130-010
TIMING WAVEFORM OF WRITE CYCLE NO.2 EITHER SIDE(4,7)
Iwe
ADDRESS
----..
---J
'EW
.1
\ \ \ \~
//1
'AW
lAS
RM
I
Iwp-
-'k'
I:'
~
DATAOllT
DATA,. :1)3)E)EE):1:):1)3)~)EE):1:):z)3)~)EE)
/
/
/
/
I
~IWR-
I+'OH.
DATA VALID
~,OW
ti~H~IGH~IM~PED~ANC~E=14:~x~xaXBX~)
~twz---"
SAD7130-011
2-35
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS 8K (1K
x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1 CE ARBITRATION
CEl VALID FIRST:
ADOR
LANDR
-A
--v____________________
ADDRESSES MATCH
~
~A_
::4-=1 [,-~~
--f
l\
BUSYR
SRD7130-013
CER VALID FIRST
ADDR
LANDR
::::x- - - - - - - - - - - - " ~
ADDRESSES MATCH
CER~
r
~~=1 i=~~._
~
BUSVL
~
SRD7130-012
TIMING WAVEFORM OF CONTENTION CYCLE NO.2 ADDRESS VALID ARBITRATION(5)
LEFT ADDRESS VALID FIRST:
IRC OR twe
ADDRSL.
~
--'
lAPS
ADDRESSES MATCH
ADDRESSES 00 NOT MATCH
1--+
x::=
AODRSR
!---tB..
..
tBDA
SRD7130-0J.1
2-36
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS 8K (1K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RIGHT ADDRESS VALID FIRST:
.
ADDRSR
-
tAPS
IRe OR twc
--
ADDRESSES MATCH
~tBAA
ADDRESSES DO NOT MATCH
......-..---teoA
SRD7130-015
TIMING WAVEFORM OF INTERRUPT MODE(S,B)
LEFT SIDE SETS INTR:
Iwe
ADDRL
RIWL
=t'"1-
INTR
WRITE 3FF
IIN51
>C
J'tx
SRD7130-016
RIGHT SIDE CLEARS INTR:
~
..,......,.....~~~._~_'Re_1~
ADORR
~
READ3FF
L
~\\-,-\.....\~\.\\~\-,-\->-\~\
...
.\\
. . ......\-,-\.>...,,;\.......\ ........
\\
.....\.....\.>......l\'-f'L----:------'/
______________~__'INR1-----SRD7130-017
2-37
IDm30S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RIGHT SIDE SETS TATL.;
1"~
~1
Iwe
ADDRR
RiW"
I'
INTL
)C
WRtTE3FE
N8
SA07130-01B
LEFT SIDE CLEARS INTL:
ADDRL
RlWL
\.......\ .......
\ ......
\ ........
\\
.......\.......\~\......
\ ........
\\
.......\.......\~\......
\ ........
\\
.......\.......\ .......\ ......
\...p."k_ _ _--i!
______________________________1==
___I'N_")------------
SRD7130-019
NOTES:
1. Riw is high for Read Cycles.
2. Device is continuously enabled. CE = VIL.
3. Addresses valid prior to or coincident with CE transition low.
4. If CE gOBS high simultaneously with R/W high, the outputs remain in the high impedance state.
5. GEL = GER = V'L·
6. ~=VIL.
7. R/W =VIH during address transition.
S. INTR and INTL are reset (high) during power up.
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEM
LEFT
RIGHT
IDT
Rlii 7130 Rlii
MASTER
BUSY
BUSY
~+5V
Rlii
Rlii
+5V~
IDT
7140 Rfii
SLAVE(l)
~ BUSY
BUSY
NOTE:
1. Noa,bit,ation in IDT7140 (SLAVE). BUSY-IN inhibils w,ite in IDT7140 (SLAVE).
2-38
-
SRD713().025
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS 8K 11K
x 8-BIT)
FUNCTIONAL DESCRIPTION:
The IDT7130/40 provides two ports with separate control,
address and I/O pins that permit independent access for reads
or writes to any location in memory. The IDT7130/40 has an
automatic power-down feature controlled by CEo The CE
controls on-chip power-down circuitry that permits the respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire memory
array is permitted. Each port has its own Output Enable control
(OE). In the read mode, the port's OE turns on the output
drivers when set LOW. Non-contention READ/WRITE conditions
are illustrated in Table I.
The interrupt flag (INT) permits communication between
ports or systems. If the user chooses to use the interrupt
function, a memory location (mail box or message center)
is assigned to each port. The left port interrupt flag (INTLl
is set when the right port writes to memory location 3FE
(HEX). The left port clears the interrupt by reading address
location 3FE. Likewise, the right port interrupt flag (INTR) is set
when the left port writes to memory location 3FF (HEX) and to
clear the interrupt flag (INTR), the right port must read the
memory location 3FF. The message (a-bits) at 3FE or 3FF is
user-defined. If the interrupt function is not used, address
locations 3FE and 3FF are not used as mail boxes but as part
of the random access memory. Refer to Table II for the
interrupt operation.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
set LOW. The delayed port will have access when BUSY
goes inactive.
Contention occurs when both left and right ports are active
and both addresses match. When this situation occurs, the onchip arbitration logic determines access. Two modes of
arbitration are provided: (1) if the addresses match and are
valid before CE, on-chip control logic arbitrates between CE l
and CER for access; or (2) if the CEs are low before an address
match, on-chip control logic arbitrates between the left and right
addresses for access (refer to Table III). In either mode of arbitration, the delayed port's BUSY flag is set and will reset when the
port granted access completes its operation.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to sixteen-or-more-bits in a
dual-port RAM system implies that several chips will be active at
the same time. If each chip includes a hardware arbitrator, and
the addresses for each chip arrive at the same time, it is possible
that one will activate its L BUSY while another activates its R BUSY
signal. Both sides are now busy and the CPUs will wait indefinitely
for their port to become free.
To avoid this "Busy Lock-Out" problem, lOT has developed a
MASTER/SLAVE approach where only one hardware arbitrator,
in the MASTER, is used. The SLAVE has BUSY inputs which
allow an interface to the MASTER with no external components
and with a speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, the write pulse must
extend a hold time past BUSY to ensure that a write cycle takes
place after the contention is resolved. This timing is inherent in all
dual-port memory systems where more than one chip is active at
the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a contention
occurs, the write to the SLAVE will be inhibited due to BUSY from
the MASTER.
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip
enable match down to 5ns minimum and determine which port
has access. In all cases, an active BUSY flag will be set for the
delayed port.
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location. When
this situation OCGurs, on-chip arbitration logic will determine
which port has access and sets the delayed port's BUSY flag.
BUSY is set at speeds that permit the processor to hold the
operation and its respective address and data. It is important
to note that the operation is invalid for the port that has BUSY
2-39
IDT7130S/L AND IDT7140S/L
CMOS DUAL-PORT RAMS aK (1K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I - NON-CONTENTION
READIWRITE CONTROL
LEFT OR RIGHT PORT!I)
FUNCTION
RIW
CE
OE
D0-7
X
H
X
Z
Port Disabled and in Power Down
Mode, ISBI or ISBO
X
H
X
Z
CE R = CE l = H, Power Down Mode,
ISBI or ISB3
L
L
X
DATA'N
H
L
L
DATAoUT
Data on Port Written Into Memory(2)
Data in Memory Output on Port(3)
H
L
H
Z
High I mpedance Outputs
-
-
-
-
Data in Memory Output
on Right Port
NOTES:
1. Aol - A91;t ADR - ABR
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see twoo and tooo timing.
H = HIGH, L = LOW, X = DON'T CARE, Z
=HIGH IMPEDANCE
TABLE" - INTERRUPT FLAG(1)
LEFTPORT
R/W l
RIGHT PORT
CE l
OE l
A ol-A 9l
INTl
R/W R
CE R
OE R
FUNCTION
L
L
X
3FF
X
X
X
X
X
INTR
Ll2)
X
X
X
X
X
X
L
L
3FF
H(3)
X
X
X
X
Ll3)
L
L
X
3FE
X
Set Left I NT l Flag
X
L
L
3FE
H(2)
X
X
X
X
X
Reset Left I NT l Flag
AOl-AR
Set Right INT R Flag
Reset Right INT R Flag
NOTES:
1. Assumes BUSYL = BUSY R = H.
3. If BUSY R = L, then NC.
2. If BUSYL = L, then NC.
H = HIGH, L = LOW, X = DON'T CARE, NC = NO CHANGE
TABLE'" - ARBITRATION
LEFTPORT
CEl
FLAGS!I)
RIGHT PORT
FUNCTION
AQL-A ...
CER
AOR""A9R
BUSYL
BUSYR
H
X
H
X
H
H
No Contention
L
Any
H
X
H
H
No Contention
H
X
L
Any
H
H
No Contention
L
;tAmrA 9R
L
;t A Ol-A 9l
H
H
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
LV5R
L
LV5R
H
L
L-Port Wins
L
RV5L
L
LV5R
L
H
R-Port Wins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R
= AOR - A9R
LL5R
= AOL - A9L
H
L
L-PortWins
RL5L
= AOR - A9R
RL5R
= AOl - A9l
L
H
R-Port Wins
LW5R
= AOR - A9R
LW5R
= AOL - A9L
H
L
Arbitration Resolved
LW5R
= AOR - A9R
LW5R
= ADL - AgL
L
H
Arbitration Resolved
NOTE:
Same = Left and Right Addresses match within 5ns of each other.
1. I NT Flags Don't Care.
X
=DON'T CARE, L = LOW, H =HIGH
LV5R
=
LL5R
RV5R = Right Address Valid
~
=Left CE =LOW;" 5ns before Right CEo
RL5L = Right CE = LOW;" 5ns before Left CEo
Left Address Valid;::-: 5ns before right address.
LW5R = Left and Right CE = LOW within 5ns of each other.
5ns before left address.
2-40
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 70/S0/100/120ns (max.)
-Commercial: 55/70/S0/100ns (max.)
The IDT7132/IDT7142 are high-speed 2K x 8 dual-port static
RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM together with
the IDT7142 "SLAVE" dual-port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE dual-port RAM approach
in 16-or-more-bit memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power down feature controlled by CE permits the
on-Chip circuitry of each port to enter a very low standby power
mode.
Fabricated using IDT's CEMOS'· high-performance technology, these devices typically operate on only 325mW of power
at maximum access times as fast as 55ns. Low-power (L)
versions offer battery backup data retention capability with each
port typically consuming 200JJ.W from a 2V battery.
The IDT7132/7142 devices are packaged in either a 48-pin
sidebraze or plastic DI P, or 48- or 52-pin LCC and 52-pin PLCC,
with the military devices available 100% processed in compliance
to the test methods of MIL-STD-883, Method 5004.
• Low-power operation
-IDT7132/42S
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT7132/42L
Active: 325mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7132 easily expands data bus width to
16-or-more bits using SLAVE IDT7142
• On-chip port arbitration logic (1DT7132 only)
• BUSY output flag on IDT7132; BUSY input on 1DT7142
• Fully asynchronous operation from either port
• Battery backup operation -
2V data retention
• TTL compatible, single 5V
± 10% power supply
• Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
R/WL
CEL
=:;::J==::::J::::::f----,
OEL~~
Al0L
An
IIOOL
---f-!--r-l-f"---"'oJ
1/07L---~__I
H
1--~---I/07R
BiJSVL(l) 0-0. . .- - - . - - - - - "
"'--------,r--_--oiiiJSv'R(l)
A6L----h..
k-+----A'R
AoL----H~
~+----AOR
SRD7132-OO1
NOTE:
B'iJSv is open drain output and requires pullup resistor.
BuSY is input.
1. IOT7132 (master):
IDT7142 (slave):
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
01986 Integrated Device Technology. Inc.
2-41
IDT7132S/L AND IDT7142S/L
CMOS DUAL-PORT RAMS 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CEl
Vee
RIWL
CER
I
;! ~
~I:
61tiJ ! rg I~ ItiJ g l.ff 1;1 rg 11.ff
coclDa::u>uQ:m:co
RiWR
BUSYR
BUSYL
A10L
OEl
A10R
AOI.
OER
A__
A"
AOR
A'R
A'R
A'R
A"
A"
A5L
A"
ASA
A6R
A"
An.
AOL
A..
I/01L
A'R
A'R
AOR
110m
I/02L
I/OGR
IIOOl
I/03l
I/OSR
I/04L
I/04R
I/OOl
I/06L
I/02R
I/01L
GND
I/0 1R
A9R
I/07R
I/06ft
19"" "n" n" "n r, "'''30
~~~~~~~~~~~~
I/03R
1I0SL
32:::
20 21 22 23 24 25 26 27 28 29 31:::
SAD7132-003
48-PINLCC
TOP VIEW
IIOOR
SRD7132-002
DIP
TOP VIEW
52-PIN LCC & PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
TA
TSIAS
TSTG
PT
lOUT
RATING
Temiinal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
VALUE
UNIT
-0.5 to +7.0
V
-55 to +125
-65 to +135
-65 to +150
1.0
50
°C
°C
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
GND
-55°C to +125°C
OV
5.0V
DoC to +70°C
OV
5.0V
Vee
± 10%
± 10%
W
mA
RECOMMENDED DC OPERATING CONDITIONS
NOTE.
1. Stresses greater than those fisted under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
Indicated in the operational sections of this specifIcation is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
-
6.0
V
0.8
V
SYMBOL
PARAMETER
V,H
Input High Voltage
2.2
V,L
Input Low Voltage
-0.5 (1 )
NOTE:
1. V1L = -3.0V for pulse width less than 20ns.
2-42
IDT7132S/L AND IDT7142S/L
CMOS DUAL·PORT RAMS 16K (2K x a·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL
PARAMETER
jill I
--
IILOI
.-_ .. - - . - -
V'H -V'L
VOL
_._--
VOL
VOH
--
(Vee = S.OV
± 10%)
IDT7132S
IDT7142S
MIN.
MAX.
TEST CONDITIONS
IDT7132L
IDT7142L
MIN.
MAX.
UNIT
Input Leakage Current
Vee = 5.5V. V'N = OV to Vee
-
10
-
5
p.A
Output Leakage Current
CE = V'H' Vour = OV to Vee
-
10
-
5
p.A
Input High Voltage
2.2
6.0
2.2
6.0
V
Input Low Voltage
-1.0111
O.S
V
Output Low Voltage (110 0 - 1/0 7)
-_.
r-__I()L = 6mA
-
-1.0(11
O.S
-0.4
IOL = SmA
-
0.5
-
IOL = 16mA
-
0.5
-
0.5
V
IOH = -4mA
2.4
-
2.4
-
V
-----
Open Drain Output Low
Voltage (BUSY, INT)
. Output High Voltage
0.4
-~
V
NOTES:
1. V1L min ... -·3.5V for pulse width less than 30ns.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
SYMBOL
Icc
PARAMETER
Dynamic Operating
Current (Both Ports
Active)
TEST CONDITION
CE = V(L
Outputs Open
Standby Current
(Both Ports-TTL
Level Inputs)
ISB2
ISB3
Standby Current
(One Port-TTL
Level Inputs)
GEL or CE R 2 V,H
Active Port Outputs
Open
Full Standby Current
(Both Ports-All
CMOS Level
Inputs)
Both Ports CE L and
CE R 2 Vee - 0.2V
V,N 2 Vee - 0.2V or
V,N=O 0.2V
Full Standby Current
(One Port-All
CMOS Level
Inputs)
One Port CE L or
CE R 2 Vee - 0.2V
V,N 2 Vee - 0.2V or
V,N=O 0.2V
Active Port Outputs
Open
VER·
SION
s.ov ± 10%)
7132x70
7142x70
7132x90/100
7142x90/1oo
7132x120(3)
7142x120
f-----+----+-----f------\
-
-
65225
65
180
65
65
185
150
COM'L.
S
L
65
65
170
120
65
65
170
120
65
65
170
120
MIL.
S
L
-
-
25
25
65
55
25
25
65
45
COM'L.
S
L
25
25
65
45
25
25
60
40
25
25
50
30
65
65
185
150
25
25
65
45
MIL.
S
L
-
-
40
40
135
110
40
40
125
100
40
125
100
S
L
40
115
65
40
40
110
~
110
65
~
~
S
-
-
1
W
1
W
1
L
-
-
0.2
10
0.2
10
0.2
30
10
COM'L.
S
L
1
0.2
15
4
1
0.2
15
4
1
0.2
15
4
MIL.
S
40
35
110
80
40
35
110
80
40
35
110
80
COM'L.
S
~
90
70
40
35
90
65
~
I----+--:::--+--:--,-.,-::--t-....,,----,-:-:-t-...,..,----:-:-t-------I
COM'L.
MIL.
UNITS
TYP(') MAX TYP(') MAX TYP(') MAX TYP(') MAX
MIL.
S
L
~
L
mA
mA
mA
mA
mA
L
NOTES:
1. X in part numbers represents versions (S or L).
2. Available in Commercial
(Vee =
7132x55(2)
7142x55
aoc to +70°C temperature range only.
3. Available in Military -55°C to +125°C temperature range only.
4. Vee = 5V, TA = +25°C.
2·43
40
35
90
70
35
II
IDm32S/L AND IDT7142S/L
CMOS DUAL-PORT RAMS 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (L Version Only)
SYMBOL
PARAMETER
VOR
IDm30LlIDT7140L
TYP'(I)
MAX.
MIN.
TEST CONDITIONS
-
-
V
-
100
4000
I'A
100
1500
i
I.... f.A
t:!"IBo"'"
3-
SA07130-024
twoo
VALl D
L
1 - - -1000------'
TIMING WAVEFORM OF WRITE CYCLE NO.1 EITHER SIDE(4.7)
'we
ADDRESS
---r ti
'EW
ll--''AW
'AS
'WP
\\\
RiW
..
I
1
LLf-'HZ~
'ow
LLL
~'WR-
.OH-l
DATAVAUD
~'
HIGH IMPEDANCE
SA07130-010
2-46
IDT7132S/L AND IDT7142S/L
CMOS DUAL-PORT RAMS 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2 EITHER SIDE(4,7)
ADDRESS
twe
-
--i
tEW
.1
LL-,- L L LL.l
\ \ \ \-\
tAS
tAW
twp- ~tWR_
I
\\
RiW
I~ 14t
DH.
DATA VALID
r---
DATAOUT
I--tow
3)~)EE)f):1:)3)3)~)EE):1:)3)3)~)E£):ti_H~tGH~tM~PED~AN~CE=1--f~X~X8X6X!e)
twz----'
SRD7130-011
II
TIMING WAVEFORM OF CONTENTION CYCLE NO.1 CE ARBITRATION
CEl VALID FIRST:
LANDA --V __________________________"-VADDR
--,\~
ADDRESSES MATCH
t
~-t.AC==:I~---+-~-t.-DC~~,~~~=
~~
CER
---7f
~
BUSVR
SAD7130-013
CER VALID FIRST
LANDR
______________________________________
"-ADDR --V
ADDRESSES MATCH
V--"~
~: ~-t9~[-t.De=1======
SA07130-012
2-47
IDT7132S/L AND IDT7142S/L
CMOS DUAL-PORT RAMS 16K (2K
x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.2 ADDRESS VALID ARBITRATION(S)
LEFT ADDRESS VALID FIRST:
lAC OR 'we
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
'''' 1--+
ADDASR
.
1+---'."
~
'.""
9--1
SA07130-014
RIGHT ADDRESS VALID FIRST:
tRCORtwc
ADDRS"
~
--'
......
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
1--+
x=
_ _ 1aoA
~,."
9------)
BUSYL
NOTES:
1. RlW is high for Read Cycles.
2. Device is continuously enabled, CE = VIL.
3. Addresses valid prior to or coincident with
4. If CE goes high simultaneously with
5. eEL = eER = V,L·
6.
SRD7130-015
CE transition low.
Riw high, the outputs remain in the high impedance state.
Cit= V,L·
7. R/W
=VIH during address transition.
16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEM
RIGHT
LEFT
Rfii
RNi
IDT
7132 RtW
MASTER
BUSY
~+5V
'-f---+
R1W
Rfii
iUfi
+5V~
IDT
7142 RM
SLAVE(1)
~ BUSY
BUSY
I-SRD7130-025
NOTE:
1. No arbitration in IDT7142 (SLAVE). BUSY-IN inhibits write in IDT7142 (SLAVE).
2-48
X
I DT7132S/L AND I DT7142S/L
CMOS DUAL-PORT RAMS 16K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
The IDT7132/42 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. These devices have an automatic power-down feature controlled by CE. The CE controls
on-chip power-down circuitry that permits the respective port to
go into a standby mode when not selected (CE high). When a
port is enabled, access to the entire memory array is permitted.
Each port has its own Output Enable control (OE). In the read
mode, the port's OE turns on the output drivers when set LOW.
Non-contention READ/WRITE conditions are illustrated in
Table I.
CEl and CER for access; or (2) if the CEs are low before an
address match, on-chip control logic arbitrates between the left
and right addresses for access (refer to Table II). In either mode
of arbitration, the delayed port's BUSY flag is set and will reset
when the port granted access completes its operation.
DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
The BUSY flags are provided for the situation when both
ports simultaneously access the same memory location. When
this Situation occurs, on-chip arbitration logic will determine
which port has access and sets the delayed port's BUSY flag.
BUSY is set at speeds that permit the processor to hold the
operation and its respective address and data. It is important
to note that the operation is invalid for the port that has BUSY
set LOW. The delayed port will have access when BUSY
goes inactive.
Contention occurs when both left and right ports are active
and both addresses match. When this situation occurs, the
on-chip arbitration logic determines access. Two modes of
arbitration are provided: (1) if the addresses match and are
valid before CE, on-chip control logic arbitrates between
Expanding the data bus width to sixteen-or-more-bits in a
dual-port RAM system implies that several chips will be active at
the same time. If each chip includes a hardware arbitrator, and
the addresses for each chip arrive at the same time, it is possible
that one will activate its L BUSY while another activates its R BUSY
signal. Both sides are now busy and the CPUs will wait indefinitely
for their port to become free.
To avoid this "Busy Lock-Out" problem, IDT has developed a
MASTER/SLAVE approach where only one hardware arbitrator,
in the MASTER, is used. The SLAVE has BUSY inputs which
allow an interface to the MASTER with no external components
and with a speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has
settled. Otherwise, the SLAVE chip may begin a write cycle
during a contention situation. Conversely, the write pulse must
extend a hold time past BUSY to ensure that a write cycle takes
place after the contention is resolved. This timing is inherent in all
dual-port memory systems where more than one chip is active at
the same time.
The write pulse to the SLAVE should be delayed by the
maximum arbitration time of the MASTER. If, then, a contention
occurs, the write tothe SLAVE will be inhibited dueto BUSY from
the MASTER.
TRUTH TABLES
CAPACITANCE (TA = +25°C, f = 1.0MHz)
ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip
enable match down to 5ns minimum and determine' which port
has access. In all cases, an active BUSYflag will be setforthe delayed port.
SYMBOL
TABLE I - NON-CONTENTION
READIWRITE CONTROL
LEFT OR RIGHT PORT(1)
RIW
CE
OE
H
X
Z
X
H
X
Z
L
L
X
H
L
L
DATA'N
DATAoUT
H
r--'
-
L
H
Z
High Impedance Outputs
-
-
Data in Memory Output
on Right Port
COUT
Output Capacitance
CONDITIONS
TYP.
UNIT
Y'N =OV
VOUT =OV
10
pF
10
pF
1. This parameter is sampled and not 100% tested.
Port Disabled and in Power Down
Mode, ISBl or ISB4
CE R = CEl = H, Power Down Mode,
ISBl or ISB3
Data on Port Written Into Memory(2)
Data in Memory Output on Port( 3)
-
Input CapaCitance
NOTE:
FUNCTION
D0-7
X
PARAMETER(1)
C'N
NOTES:
1. AOl - A1OL"I AOR - A 10A
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t WOD and tODD timing.
H = HIGH, l = lOW, X = DON'T CARE, Z = HIGH IMPEDANCE
2-49
IDm32S/L AND IDm42S/L
CMOS DUAL-PORT RAMS 18K (2K x a-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE II - ARBITRATION
LEFTPORT
eEL
FLAGS(')
RIGHT PORT
AOI..-A'OL
CER
AOR-A,OR
BUSYL
BUSYR
FUNCTION
H
X
H
X
H
H
L
Any
H
X
H
H
No Contention
H
X
L
Any
H
H
No Contention
L
t- AOR"AIOA
L
t- ADL-A'DL
H
H
No Contention
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
LV5R
L
LV5R
H
L
L-Port Wins
L
RV5L
L
LV5R
L
H
R-Port Wins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
=ADL -A'DL
=ADL -A,ol
=ADL - A,oL
=ADL - AIOL
H
L
L-PortWins
L
H
R-PortWins
H
L
Arbitration Resolved
L
H
Arbitration Resolved
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R
RL5L
LW5R
LW5R
=ADR -A'DR
=ADA - A'DR
=AOA - A'DR
=ADR - A'DR
LL5R
RL5L
LW5R
LW5R
NOTE:
1. INT Flags Don't Care
X = DON'T CARE, L = LOW, H = HIGH
LV5R = Left Address Valid
~
RV5L = Right Address Valid
Sns before right address.
~
Sns before left address.
Same = left and Right Addresses match within 5ns of each other.
LL5R = Left CE=LOW " 5ns before Right CEo
RL5L = Right CE=LOW " 5ns before Left CEo
LW5R = Left and Right CE=LOW within 5ns of each other.
2-50
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 55/70/90/100ns (max.)
-Commercial: 45/55170/90ns (max.)
• Low-power operation
-IDT71322S
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT71322L
Active: 325mW (typ.)
Standby: 1mW (typ.)
The IDT71322 is an extremely high-speed 2K x 8 dual-port
static RAM with full on-chip hardware support of semaphore
signalling between the two ports.
the IDT71322 provides two independent ports with separate
control, address and 1/0 pins that permit independent, asynchronous access for reads and writes to any 10Gation in memory. It is
the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports.
To assist in arbitrating between ports, a fully independent
semaphore logic block is provided. An automatic power down
feature controlled by CE and SEM permits the on-chip circuitry
of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS'· high-performance technology, this device typically operates on only 325mW of power at
maximum access times as fast as 45ns. Low-power (L) versions
offer battery backup data retention capability with each port
typically consuming 200/lW from a 2V battery.
The IDT71322 is packaged in either a 48-pin sidebraze or
plastic DIPor'52-pin LCC, with the military devices available 100%
processed in compliance to the test methods of MIL-STD-883,
Method 5004.
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation - 2V data retention
• TTL compatible, single 5V ± 10% power supply
• Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
r--~f----- A10R
A10l - - - - H - - - ,
.--++-------- A7R
A7l------~t-~
I/OOl
----I--Lr""lf-rl.----'~
t-4-+-------- I/OOR
L-____~HL___t--+.------1I07R
I/07L --------+.-1
A6l ---------,~
k:---------
Aol----+i
.....' - - - - - - AOR
A6R
I/OOR-7R
I/O Ol-7l
AOR-2R
AOl-2l
CE l - - - -___-tSEMAPHORE . . - - - - CE R
SEMl
LOGIC..
SEMR
OEl
..
R/Vh
OER
RiWR
SRD71322-OO1
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1988 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-51
IDT71322S/L CMOS DUAL-PORT
RAMS 16K (2K x a-BIT) WITH SEMAPHORE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LCC
TOP VIEW
SRD7132NXl2
DIP
TOP VIEW
2-52
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 90/100/120ns (max.)
-Commercial: 70/90/100ns (max.)
The 1DT7133/10T7143 are high-speed 2K x 16 dual-port static
RAMs. The IOT7133 is designed to be used as a stand-alone
16-bit dual-port RAM or as a "MASTER" dual-port RAM together
with the IDT7143 "SLAVE" dual-port in 32-bit-or-more word
width systems. Using the IDT MASTER/SLAVE dual-port RAM
approach in 32-or-more-bit memory system applications results
in fulI'.:speed, error-free operation without the need for additional
discrete logic.
Both devices provide two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by CE, permits the
on-chip circuitry of each port to enter a very low standby power
mode.
Fabricated using lOT's CEMOS'· high-performance technology, these devices typically operate on only 32SmW of power
at maximum access times as fast as 70ns. Low-power (L)
versions offer battery backup data retention capability with each
port typically consuming 200p.W from a 2V battery.
Both the IDT7133/7143 2K x 16 devices have identical pinouts.
Each are packaged in either a 68-pin PGA, sidebraze or plastic
DIP or LCC, with the military devices available 100% processed in
compliance to the test methods of MIL-STD-883, Method S004.
• Low-power operation
-IDT7133/43S
Active: 32SmW (typ.)
Standby: SmW (typ.)
-IDT7133/43L
Active: 32SmW (typ.)
Standby: 1mW (typ.)
• Versatile control for write: separate write control for lower
and upper byte of each port
• MASTER IDT7133 easily expands data bus width to
32-or-more bits using SLAVE I DT7143
•
•
•
•
•
•
•
On-chip port arbitration logic (IDT7133 only)
BUSY output flag on IOT7133; BUSY input on IOT7143
Fully asynchronous operation from either port
Battery backup operation - 2V data retention
TIL compatible, single SV (±10%) power supply
Available in 68-pin PGA, OIP (600 mil, 70 mil centers), LCC
Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
RtWLUBTr=="C)-___---,
'+i,--...,-.. . .
+--7"'--I/OSR -I/0 15A
L _ _J-L_j---+-~~I/OOfl-I/07R
"'------~r---... BUSyR(l)
1-4o-+---A"
",---+-+1
..-+---AOR
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pullup resistor.
IDT7143 (SLAVE): BUSY is input.
SRD7133-002
2. LB = LOWER BYTE
UB = UPPER BYTE
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
=1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-53
II
IDT7133SIL AND IDT7143S/L
CMOS DUAL·PORT RAMS 32K (2K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
~~~rl.~~~€€ ~;IWo" ecce
II 01
---------~~~
all:!
m~~Q~vMN~~~ffi~~~~w
1/09L 10
I/O 'OL 11
I/0 nL 12
1/0, 21. 13
1/0'aL ,.
1/0'4L 15
I/O'SL 16
VCC2 17
VSS2 18
I/OOR 19
I/O'R 20
1/02R 21
I/0 aR 22
I/O.A 23
1/05R 24
I/O SR 25
1/07R . 26
60 ASL
59 A5L
58
57
56
55
~L
A3L
A2L
A'L
~~L
52
51
50
CEL
CE
BU
h
48 A'A
47 A2R
48 A3R
45 A'R
44 ASA
LCC
TOP VIEW
6R07133-004
SA07133-003
DIP
TOP VIEW
UB = UPPER BYTE
LB = LOWER BYTE
PGA
TOP VIEW
2·54
A
49 AOA
SRD713:H)05
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 55170/90/100ns (max.)
-Commercial: 45/55/70/90ns (max.)
The IDT7134 is an extremely high-speed 4K x 8 dual-port static
RAM designed to be used in systems where on-chip hardware
port arbitration is not needed.
The IDT7134 provides two independent ports with separate
control, address and liD pins that perm;t independent, asynchronous access for reads or writes to any location in memory. It
is the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports.
An automatic power down feature, controlled by CE, permits the
on-chip circuitry of each port to enter a very low standby power
mode.
Fabricated using IDT's CEMOS'· high-performance technology, these dual ports typically operate on only 325mW of
power at maximum access times as fast as 45ns. low power (l)
versions offer battery backup data retention capability with each
port typically consuming 200p.W from a 2V battery.
The IDT7134 is packaged in either a 48-pin sidebraze or plastic
DIP or lCC, with the military devices available 100% processed in
compliance to the test methods of Mll-5TD-883, Method 5004.
• low-power operation
-IDT7134S
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT7134l
Active: 325mW (typ.)
Standby: 1mW (typ.)
•
•
•
•
Fully asynchronous operation from either port
Battery backup operation - 2V data retention
TTL compatible, single +5V (±10%) power supply
Military product 100% screened to Mll-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
R/WL
R/WA
CEL
CEA
OEL
OEA
Al1L
A7L
AlIA
A7A
I/OUL
··
I/07L
I/OUA
I/07A
AGL
A6A
AuL
AOR
SDR7134-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
Cl 1986 Integrated Device Technology, Inc.
2-55
2
IDT7134S/IDT7134L CMOS DUAL-PORT RAMS 32K (4K
x B-Bln
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
....
............ "" ....
II:
~II:II:II:
..11111 ~ ;:1<::1111 (J "'1111
.joo(o(a:(JZ~(J
;: ~IIII
o(o(q~
10
11
12
13
,.
,
15
16
:J
17
~
~
/iA
J/,':"
18
r
".~, 'S..'
35 ..
J;'~t 2~":'23 24 25 26 27 28 29 30 31 32 34 t:
~,f~}"
r1
" n n n r, " " " "
,,33
SDA7134-003
LCC
TOP VIEW
DIP
TOP VIEW
SDR7134-002
2-56
FEATURES:
DESCRIPTION:
• High-speed access
-Military: 55170/901100ns (max.)
-Commercial: 45/55/70/90ns (max.)
The IDT71341 is an extremely high-speed 4K x 8 dual-port
static RAM with full on-chip hardware support of semaphore
signalling between the two ports.
The IDT71341 provides two independent ports with separate
cootrol, address and 1/0 pins that permit independent, asynchronous access for reads and writes to any location in memory. It is
the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports.
To assist in arbitrating between ports, a fully independent semaphore logic block is provided. An automatic power down feature,
controlled by CE and SEM, permits the on-chip circuitry of each
port to enter a very low standby power mode (both CE and SEM
high).
Fabricated using IDT's CEMOS·· high-performance technology, this device typically operates on only 325mW of power at
maximum access times as fast as 45ns. Low-power (L) versions
offer battery backup data retention capability with each port
typically consuming 200!-'W from a 2V battery.
The IDT71341 military devices are available 100% processed in
compliance to the test methods of MIL-STD-883, Class B,
Method 5004.
• Low-power operation
-IDT71341S
Active: 325mW (typ.)
Standby: 5mW (typ.)
-IDT71341L
Active: 325mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation - 2V data retention
• TTL compatible, single 5V (±10%) power supply
• Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
RlWL
eEL
==l~8-I--1
I/OOL -1/07 L ~--..,--++-~
AOL-A11 L ------I~
....H-I-.....- -. .
L Side
Address
Decode
Logic
R Side
Address
Decode
Logic
IlOO R- V07 R
AOR-AllR
SRD71341-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
"1986 Integrated Device Technology, Inc.
2-57
fI
FEATURES:
DESCRIPTION:
• High-speed address/chip select access time
Military - 35/45/55/70/85/1 00/120/150/200ns (max.)
Commercial - 30135/45/55/70ns (max.)
The IDT7164 is a 65,536 bit high-speed static RAM organized
as 8K x 8. It is fabricated using IDT's high-performance, highreliability CEMOS technology.
Address access times as fast as 30ns are available with
typical power consumption of only 250mW. The circuit also
offers a reduced power standby mode. When CS, goes high or
CS2 goes low, the circuit will automatically go to, and remain
in, a low power standby mode. In the full standby mode, the
low power device consumes less than 3o,.W typically. The
low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 10j.LW
operating off a 2V battery.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation.
The IDT7164 is packaged in either a 28-pin, 400 mil THINDIP; a
28-pin, 600 mil DIP or 32-pin lead less chip carrier, providing high
board-level packing densities.
The IDT7164 Military RAM is 100% processed in compliance to
the test methods of MIL-STD-883, Method 5004, making it ideally
suited to military temperature applications demanding the highest
level of performance and reliability.
• Low-power operation
-IDT7164S
Active: 300mW (typ.)
Standby: 100j.LW (typ.)
-IDT7164L
Active: 250mW (typ.)
Standby: 30j.LW (typ.)
• Battery Backup operation - 2V data retention voltage
(L Version only)
• Produced with advanced CEMOS'· high-performance
technology
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Standard 28-pin DIP (600 mil), 28-pin THINDIP (400 mil) and
32-pin LCC
• Pin compatible with standard 64K static RAM and EPROM
• Military product available 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
AO
-+---0
Vee
-+---OGND
ROW
DECODER
•
1/01
256 x 256
MEMORY ARRAY
COLUMN 1/0
INPUT
DATA
CIRCUIT
I/OS
CS1
CONTROL~________________________~__~
CS2
CIRCUIT
OE
WE ~-"L-_ _-I
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-59
II
IDT7164SfIDT7164L CMOS STATIC RAMS 64K (BK x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
NC
Vee
WE
A12
A7
CS2
A6
As
As
As
A4
Aa
A11
OE
A2
Al
Al0
~1
Ao
1I0a
1101
1102
1103
1I0a
As
At
All
NC
OE
Al0
CSl
VOa
1107
V07
1105
1104
GND
NI
""I
Q
0
..
1ft
CD
gg~zggg
SDR7164-003
SDR7164-002
LCC
TOP VIEW
DIP
TOP VIEW
LOGIC SYMBOL
PIN NAMES
SOR7164-004
2-60
Ao-A'2
110,-110 8
ADDRESS
WE
DATA I NPUTf OUTPUT
OE
WRITE ENABLE
OUTPUT ENABLE
CS,
CHIP SELECT
GND
GROUND
CS 2
CHIP SELECT
Vee
POWER
IDT7164S/IDT7164L CMOS STATIC RAMS 64K (8K x 8-BIT)
MILITARY AND CDMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
RATING
Terminal Voltage with
Respect to GND
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
-0.5 to +7.0
V
TA
Operating Temperature
-55 to +125
°C
TS1AS
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
-65 to +150
SYMBOL
°C
PARAMETER
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
-
6.0
V
V'L
Input Low Voltage
-0.51')
-
O.S
V
UNIT
NOTE:
PT
Power Dissi pation
1.0
W
lOUT
DC Output Current
50
mA
1. V,L min = -3.0V lor pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
AMBIENT
TEMPERATURE
GND
-55°C to +125°C
OV
5.0V
O°C to +70°C
OV
5.0V
Commercial
Vee
± 10%
± 10%
DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ± 10%, VLC = 0.2V, VHC = Vcc - 0.2V
SYMBOL
PARAMETER
IDT7164S
IDT7164L
MIN. TYP'(I) MAX. MIN. TYP.(') MAX.
TEST CONDITIONS
IOL = lOmA, Vee = Min.
-
0.5
-
IOL = SmA, Vec = Min.
-
-
0.4
-
10H = -4mA, Vee = Min.
2.4
-
-
2.4
!lui
Input Leakage Current
Vee = Max.; V,N = GND to Vee
MIL.
COM'L.
IILOI
Output Leakage Current
Vee = Max.
CS, = V,H , VOUT = GND to Vee
MIL.
COM'L.
VOL
Output Low Voltage
VOH
Output High Voltage
-
10
5
-
-
-
10
5
-
-
-
-
UNIT
5
2
p.A
5
2
p.A
0.5
V
0.4
V
-
V
NOTE:
1. Typical limits are at Vee = 5.0V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS(1)
=5.0V ± 10%, VLC =0.2V, VHC = Vcc - 0.2V
Vcc
SYMBOL
PARAMETER
Icc,
Operating Power Supply Current
CS, = V'L' Output Open, CS2 = V,H
Vee = Max., I = 0
Icc2
IS8
I S8 ,
Dynamic Operating Current
CS, =V'L' Output Open, CS 2 =V,H
Vec = Max., I = I Max.
Standby Power Supply Current
illL Level)
CS, 2" V,H, or CS 2 '; V'L
Vec = Max., Output Open
Full Standby Power Supply
Current (CMOS Level)
1. CS, 2" VHe and CS 2 2" VHC
2. CS 2,; VLC' Vce = Max.
POWER
30n$
.'t.
COM'L.
S
90
L
SO
<
~
35no
COM'L.
45n5
MIL.
COM'L.
55no
MIL.
85no(2)
70no
COM'L
MIL
COM'L.
MIL.
COM'L.
MIL.
-
100
90
~~
90
100
90
100
90
100
90
100
-
SO
90
SO
90
SO
90
SO
90
-
150
160
UNIT
mA
:~
S
160,~¥;C
150
160
150
160
150
160
-
160
L
140\,' ;"-
130
140
120
130
115
125
110
120
-
120
S
20
-
20
20
20
20
20
20
20
20
-
20
mA
,,'
mA
L
3,
-
3
5
3
5
3
5
3
5
-
5
S
15
-
15
20
15
20
15
20
15
20
-
20
L
0.2
-
0.2
1.0
0.2
1.0
0.2
1.0
0.2
1.0
-
1.0
mA
NOTES:
1. All values are maximum guaranteed values.
2. Also available: 100, 120, 150 and 200ns military devices.
2-in
PI
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7164S/IDT7164L CMOS STATIC RAMS 64K (8K x B-BIT)
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLc
=O.2V, VHC =Vcc - O.2V
TYP.(1)
SYMBOL
PARAMETER
TEST CONDITION
-
MIN.
VDR
Vcc for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention Time
1.' CS,", V HC' & CS 2 ", V HC
tR
Operation Recovery Time
2. CS 2 "V lC
Ilul (3)
Input Leakage Current
I MIL.
COM'L.
MAX.
Vcc @
2.0V
3.OV
UNIT
Vcc @
2.0V
3.0V
2.0
-
-
-
-
10
10
15
15
200
-
V
300
90
60
p.A
-
ns
t RC (2)
-
-
-
2
p.A
0
ns
NOTES:
1. TA = +25"C.
2. IRC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION
MODE
Vee
--------:1..
4.5V VDR"' 2V 4.5V
SDR7164-005
AC TEST CONDITIONS
I nput Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
+5V
GND to3.0V
5ns
1.5V
1.5V
See Figs. 1 and 2
4800
4800
30pF
5pF"
DO!JT-~r--_--1
2550
SDR71~
Figure 1. Output Load
SDR7164-007
Figure 2. Output Load
(lor t CLZ1." 10LZ' I CHZ1,2' 10Hz,
low,lwHZ)
"Including scope and jig
2-62
IDT7164S/IDT7164L CMOS STATIC RAMS 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS Vee = 5V ± 10%, All Temperature Ranges)
SYMBOL
7164S30(1,7)
7164L30(1,7)
MIN. MAX.
PARAMETER
7164S35(5)
7164L35(5)
MIN. MAX.
7164S45
7164L45
MIN. MAX.
7164S55
7164L55
MIN. MAX.
7164S70
7164L70
MIN. MAX.
7164S85(2)
7164L85(2)
MIN. MAX.
UNITS
READ CYCLE
t AC
Read Cycle Time
30
-
45
-
55
-
70
-
85
-
ns
Address Access Time
-
30
35
-
-
tM
35
-
45
-
55
-
70
-
85
ns
t ACS1 ,2
Chip Select-1,2
Access Time( 3)
-
35(7)
-
40( 5)
-
45
-
55
-
70
-
85
ns
t CLZ1 ,2
Chip Select-1 ,2 to
Output in low Z(4)
5
-
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to
Output Valid
-
15
-
20
-
25
-
30
-
35
-
40
ns
tOLZ
Output Enable to
Output in low Z(4)
0
-
0
-
0
-
0
-
0
-
0
-
ns
t CHZ1 ,2
Chip Select-1 ,2 to
Output in High Z(4)
-
15
-
15
-
20
-
25
-
30
-
35
ns
tOHZ
Chip Select-1 ,2 to
Output in High Z(4)
-
15
-
15
-
20
-
25
-
30
-
35
ns
tOH
Output Hold from
Address Change
5
5
-
5
-
5
-
5
-
5
-
ns
tpu
Chip Select to
Power Up Time( 4 )
0
0
-
0
-
0
-
0
-
0
-
ns
-
35
-
45
-
55
-
70
-
85
ns
35
-
45
-
55
-
70
-
85
-
ns
-
40
-
50
-
60
-
75
-
ns
ns
,h
'"'
Chip Select to
Power Down Time( 4)
tpo
~,
",'" 30
"""
WRITE CYCLE
..... ,-'
twc
Write Cycle Time
39
"
t CW1 ,2
Chi p Select to
End of Write
tAW
Address Valid to
End of Write
tAS
Address Setup Time
twp
-
2s
-
30
25
-
30
-
40
-
50
-
60
-
75
-
0
-
0
0
-
0
-
0
-
ns
25
-
30
40
-
50
-
0
Write Pulse Width
-
60
-
75
-
ns
tWR1
Write Recovery Time
(CS"WE)
0
-
0
-
0
-
0
-
0
-
0
-
ns
tWA'
Write Recovery Time
(CS 2 )
5
-
5
-
5
-
5
-
5
-
5
-
ns
tWHZ
Write Enable to
Output High Z(4)
-
12
-
15
-
20
-
25
-
30
-
35
ns
tow
Data to Write
Time Overlap
13
-
15
-
20
-
25
-
30
-
35
-
ns
tOH
Data Hold from
Write Time(6)
3/5
-
3/5
-
3/5
-
3/5
-
3/5
-
3/5
-
ns
tow
Output Active from
End of Write( 4)
5
-
5
-
5
-
5
-
5
-
5
-
ns
"
r
NOTES:
1.
aoc to 70 e product only.
0
2. -55°C to +125°C product only. Also available: 100, 120. 150 and 200n5 military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter guaranteed but not tested.
5. t ACS1 = 35n5, t ACS2 = 40n5.
6. With respect to CS 1
=30n5, CS 2 = 5ns.
7. t ACS1 = 30n5, t ACS2 = 35n5.
2-63
IDT7164SIIDT7164L CMOS STATIC RAMS 64K (BK
x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1(1)
ADDRESS
__
JI~
________________
~~
_____
DOUT---------------------{
SDR7164-008
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS--t===~ tRC--=~
_ _
DOUT
-t,,,-9XJ
T=~l
SDR7184-009
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
DOUT--------------~~~========================~
SDR7164-010
NOTES:
1.
WE is High for Read Cycle.
2. Device is continuously selected,
68 1 = V1L• CS 2 = V 1H.
Cs, transition low and CS 2 transition high.
3. Address valid prior to or COincident with
DE = V'L
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
4.
IDT7164SIIDT7164L CMOS STATIC RAMS 64K (8K X 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
I-------twc------.j
ADDRESS
DOUT
DIN
--------_&DAiTA.::twiUc~'if9.'W
SDR71~11
TIMING WAVEFORM OF WRITE CYCLE NO. 2(1,6)
I~-----twc-----~
SOR7164-012
NOTES:
1.
WE must be high during all address transitions.
2. A write occurs during the overlap (t wp) of a low CS, and a high CS2 .
3. t WR1 .2 is measured from the earlier of CS, or WE going high or CSz going low to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CS 1 low transition or CS z high transition occurs simultaneously with the WE low transitions or after the WE transition. outputs remain in a high impedance state.
6. OE is continuously low
(Oe = V,L).
7. DOUT is the same phase of write data of this write cycle.
8. If CS, is low and CS 2 is high during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied tothem.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
2-65
IDT7164S1IDT7164L CMOS STATIC RAMS 14K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA =+25°C, f =1.0MHz)
SYMBOL
PARAMETER(1)
C IN
Input CapaCitance
C OUT
Output Capacitance
TRUTH TABLE (VLC = O.2V, VHC = vcc - O.2V)
CONDITIONS
TYP.
UNIT
WE
CS,
CS z
OE
1/0
VIN = OV
5
pF
X
H
X
X
HIGHZ
Standby (Iss)
VOUT = OV
7
pF
X
X
l
X
HIGHZ
Standby (Iss)
X
VHC
VHCor
VLC
X
HIGHZ
Standby (ISS1)
X
X
VLC
X
HIGHZ
Standby (ISS1)
H
L
H
H
HIGHZ
Output disable
H
l
H
L
D OUT
Read
L
L
H
X
DIN
Write
NOTES:
1. This parameter is sampled and not 100% tested.
MODE
NOTE:
1. CS2 will power-down
2-66
CS 1• but CS 1 will not power-down CS 2.
FEATURES:
DESCRIPTION
• High-speed address access time
-Military: 35/45/55ns (max.)
-Commercial: 30/35/45/55ns (max.)
• High-speed chip select (CS1) time
-Military: 20/25/30/35ns (max.)
-Commercial: 15/20/25/30ns (max.)
• Low-power operation
-IDT7165S
Active: 300mW (typ.)
Standby: 100!'W (typ.)
-IDT7165L
Active: 250mW (typ.)
Standby: 30!'W (typ.)
• Battery backup operation - 2V data retention voltage
(IDT7165L only)
• Produced with advanced CEMOS·· high-performance
technology
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Standard 28-pin DIP (600 and 400 mil) and 32-pin LCC
• Asynchronous clear on Pin 1
• Military product 100% screened to MIL-STD-883, Class B
The IDT7165 is a high-speed 65,536-bit static RAM, organized
8K x 8, with reset function. It also provides a single RAM clear
control which clears all words in the internal RAM to zero when
activated. This allows the memory bits for all locations to be
cleared at power-on or system reset.
This product is fabricated using IDT's high-performance, highreliability CEMOS··technology. Address access time of 30ns and
chip select (CS 1) time of 15ns are available with maximum power
consumption of only 770mW. This circuit also offers a reduced
power standby mode. When CS 2 goes low, the circuit will
automatically go to and remain in low-power standby mode. In
the full standby mode, the low-power device consumes less than
30!'W typically. The low-power (L) version offers a battery
backup data retention capability where the circuit typically
consumes only 10!'W operating off a 2V battery.
All inputs and outputs of the IDT7165 are TTL-compatible and
the device operates from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used so no clocks
or refreshing for operation is required.
The IDT7165 is packaged in a 28-pin 600 mil or 400 mil DIP or
32-pin lead less chip carrier, providing high board level densities.
This resettable military RAM is 100% processed in compliance
to the test methods of MIL-STD-883, Method 5004 making it
ideally suited to the military temperature applications demanding
the highest level of performance and reliability.
•
:
RESET
256 X 256
...... Vee
MEMORY ARRAY _GND
ROW
DECODER
----~4~--------~
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
@1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
2·67
IDT7165S1IDT7165L CMOS STATIC RAMS 64K (6K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
I
N
.... ~UlO(JW(/)
0( 0( a:
CJ
z ~ 1;=
A6
Aa
As
A4
As
As
NC
A2
OE
A1
A'0
CS,
All
Ao
Ne
I/0a
1/01
1/07
DIP
TOP VIEW
SRD7165-002
Lee
TOP VIEW
LOGIC SYMBOL
SRD7165-003
PIN NAMES
1/0,
1/02
V0 3
1/0.
1/05
1/06
Ao-'2
Address
WE
Write Enable
1/0,_8
Data Input/Output
OE
Output Enable
CS,. CS 2
Chip Select
GND
Ground
RESET
Memory Reset
Vee
Power
1/07
1/0.
RESET
CS,
CS2
OE
WE
SRD716S-004
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
TA
Operating Temperature
-55 to +125
·C
TBIAS
Temperature Under Bias
-65 to +135
·C
TSTG
Storage Temperature
-65 to +150
·C
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
mA
VTEAM
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
6.0
V
V,L
Input Low Voltage
-0.5(')
-
0.8
V
SYMBOL
NOTE:
1. V1L min = -3.0V for pulse width less than 20n5.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
Commercial
2-68
AMBIENT
TEMPERATURE
GND
Vcc
-55·C to +125·C
OV
5.0V±10%
O·C to +70·C
OV
5.0V±10%
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7165S/IDT7165L CMOS STATIC RAMS 64K (8K x 8-BIT)
DC ELECTRICAL CHARACTERISTICS
vce
=5.0V ± 10%, VLC =0.2V, VHC = VCC -0.2V
SYMBOL
Ilul
PARAMETER
Input Leakage Current
IlLOI
Output Leakage Current
VOL
Output Low Voltage
VOH
Output High Voltage
IDT7165S
IDT7165L
MIN. TYP'(1) MAX. MIN. TYP'(1) MAX.
TEST CONDITIONS
Vee
= Max.; V,N = GND to Vee
= Max.
CS = V,H. Vour = GND to Vee
10L = lomA, Vee = Min.
Vee
10L =BmA, Vee
10H
UNIT
MIL.
COM'L.
-
-
10
5
-
-
5
2
p.A
MIL.
COM'L.
-
-
-
-
-
10
5
-
5
2
p.A
-
-
0.5
-
-
0.5
V
-
0.4
-
-
0.4
V
2.4
-
-
2.4
-
-
V
=Min.
= -4mA, Vee = Min.
-
NOTE:
1. Typical limits are at Vee = S.OV, +25 0 C ambient.
DC ELECTRICAL CHARACTERISTICS(1)
Vec
=5.0V ± 10%, VLC =0.2V, VHe =Vce -
SYMBOL
lee1 (2)
lee2(2)
ISB
ISBl
0.2V
30n.
PARAMETER
POWER
Operating Power Supply Current
Output Open,
Vee = Max., f = 0
S
90
L
BO
Dynamic Operating Current
Output Open,
Vee = Max., f = f Max.
S
160
L
140
S
20,;';;~\
L
3'
Standby Power Supply Current
(TTL Level), CS, ~ V ,H ,
CS 2 :5 V,L , and RESET ~ V,H
Vee = Max., Output Open
Full Standby Power Supply
Current (CMOS Level)
CS 2 :5 VLe and RESET;;, VHe ,
Vee = Max.
35n.
45n.
55no
COM·L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
-~"
90
100
90
100
90
100
.:...
BO
90
BO
90
BO
90
\.~
150
160
150
160
150
160
}:-
130
140
120
130
115
125
-
20
20
20
20
20
20
-
3
5
3
5
3
5
-
15
20
15
20
15
20
-
0.2
1
0.2
1
0.2
1
MIL.
COM'L.
UNIT
mA
mA
mA
,..,
S
L
~
,0
1S
mA
,,0.2
NOTES:
1, All values are maximum guaranteed values.
2. CS,= V,H
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2\1, VHC = VCC - 0.2V
TYP,(1)
SYMBOL
PARAMETER
VDR
Vee for Data Retention
IceDR
Data Retention Current
teDR(3)
t R(3)
Chip Deselect to Data Retention Time
Ilul (3)
Input Leakage Current
Operation Recovery Time
TEST CONDITION
-
I MIL.
COM'L.
CS 2 :5 VLC and
RESET ~ VHe
MIN.
MAX.
Vcc @
2.0V
3.0V
-
-
-
-
V
-
10
10
15
15
200
60
300
90
p.A
0
-
-
ns
t Re (2)
-
-
2
p.A
NOTES:
2. t RC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION
MODE
-------o::L 4.5V
VOR
~ 2V
4.5V
SRD7165-005
2-69
UNIT
2.0
1. TA = +25°C.
Vee
VCC @
2.0V
3.0V
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7165SIIDT7165L CMOS STATIC RAMS 64K (8K x 8-BIT)
Input Pulse Levels
I nput Rise/Fall Times
I nput Timing Reference Levels
Output Reference Levels
Output Load
+5V
+5V
AC TEST CONDITIONS
GNDto 3.0V
5ns
1.5V
1.5V
See Figs. 1 and 2
4800
4800
DOUT-~~--i
DOUT-~r----1
2550
30pF
2550
5pF*
SRD7165-006
Figure 1. Output Load
*Includlng scope and jig
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vee
SRD7165wOO7
Figure 2. Output Load
(for tCLZ1• 20 tOLZ' t CHZ1•20 tOHZ'
tow> twHZl
=5V ± 10%. All Temperature Ranges)
IDT7165S30(1)
IDT7165L30(1)
MIN.
MAX.
IDT7165S35(5)
IDT7165L35(5)
MIN.
MAX.
IDT7165S45
IDT7165L45
MIN.
MAX.
IDT7165S55
IDT7165L55
MIN.
MAX.
UNITS
READ CYCLE
t RC
Read Cycle Time
30
-
35
-
45
-
55
-
ns
tAA
Address Access Ti me
-
30
35
-
45
ns
Chip Select-l Access Time(2)
20
-
25
30
ns
Chip Select-2 Access Time(2)
-
-
55
tACS'
t ACS2
35
-
40
-
45
-
55
ns
t CLZ '
IcLZ2
Chip Select-l to Output in Low Z(3)
0
-
0
0
-
0
-
ns
Chip Select-2 to Output in Low Z(3)
5
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
-
20
-
25
-
30
ns
tOLZ
Output Enable to Output in Low Z(3)
0
0
-
0
-
0
-
ns
Chip Select-l to Output in High Z(3)
-
-
15
-
20
-
25
ns
15
20
-
25
ns
15
-
20
-
25
ns
5
5
-
5
-
5
-
ns
35
-
45
55
-
ns
30
-
ns
50
-
ns
50
-
ns
0
-
ns
50
5
-
ns
5
-
ns
t CHZ '
tCHZ2
Chip Select-2 to Output in High Z(3)
tOHZ
Output Disable to Output in High Z(3)
Output Hold from Address Change
tOH
WRITE CYCLE
15
twc
Write Cycle Time
tcw,
Chip Select-l to End of Write
tCW2
Chip Select-2 to End of Write
tAW
t AS
Address Valid to End of Write
twp
Write Pulse Width
-
tWR'
Write Recovery Time (CS, • WE)
-
0
tWR2
Write Recovery Time (eS2)
-
5
12
-
15
-
20
-
25
15
-
20
-
25
-
-
100
20.
30
25
Address Setup Time
.0"",
20
30
30
0
30
25
40
40
0
40
0
tWHZ
Write Enable to Output in High Z(3)
tow
Data to Write Time Overlap
13
t OH '
tOH2
Data Hold From Write Time (CS,)
3
Data Hold From Write Time (CS 2)
5
-
Output Active from End of Write(3)
tow
RESET(')
5
-
5
55
-
65
-
80
5
-
10
t RSPW
Reset Pulse Width
t RSR
Reset High to WE Low
5
3
5
NOTES:
1. O°C to +70°C temperature range only.
2. Both chip selects must be active for the device to be selected.
3. This parameter guaranteed but not tested.
4. Maximum 10% duty cycle applies.
5. Data is preliminary for military devices only.
2-70
3
5
5
0
3
5
5
10
-
ns
ns
ns
ns
ns
ns
ns
ns
IDT7165S/IDT7165L CMOS STATIC RAMS 64K (8K
x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO_ 1(1)
ADDRESS
DOUT----------------------1\~~----------~~~
SRD7165-00B
TIMING WAVEFORM OF READ CYCLE NO.
2(1,2,4)
ADDRESS-t==~IRC_=~
DOUT
-t~"?1XXX1
'[''"1
SRD7165-009
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
DOUT--------------~~~======================~
SDR7164-010
RESET TIMING
f
RSPW
I
xxxxxxxxxXXXXXxxxy
~
=I }.r--
NOTES:
1. WE is High for Read Cycle.
CS1 = V1L . CS 2 = V1H .
3. Address valid prior to or coincident with CS 1 transition low and CS 2 transition high.
2. Device is continuously selected,
4.
OE = V,L
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
2-71
I RSRC
IDT7165SIIDT7165L CMOS STATIC RAMS 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
i-+------twc------+j
ADDRESS
____
-JI~
__________________
r--~,------
CS,
DOUT
DIN
-------------------;&-;;:u.:ilDA:;:;;~VVW
SRD7165-011
TIMING WAVEFORM OF WRITE CYCLE NO. 2(1,6)
~-----------twc------~~
ADDRESS
DOUT
DIN
::~~~~~t:~~~~~~~~--~~~~~=======
tDW tDH~8)
~~L1D
--------------------1
1,'
DATAI7XXxx
NOTES:
1.
WE must be high during all address tranSitions.
2. A write occurs during the overlap (twp) of a low CS, and a high C8 2.
3. tWR1.2 is measured from the earlier of CS, or WE gOing high or CS 2 going low to the end of write cycle.
4. During this period, liD pins are in the output state 50 that the input signals of opposite phase to the outputs must not be applied.
5. If the CS 1 10w transition or CS 2 high transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
6. OE is continuously low
(DE = VtL).
7. DOUT is the same phase of write data of this write cycle.
8. If CS 1 is low and CS 2 is high during this period, 110 pins are in the output state. Then the data input signals of opposite phase tothe outputs must not be applied tothem.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
2-72
IDT7165SIIDT7165L CMOS STATIC RAMS 64K (8K x 8-BIT) .
CAPACITANCE
SYMBOL
(TA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
=+25°C, f =1.0MHz)
TRUTH TABLE
PARAMETER!')
CONDITIONS
TYP.
UNIT
WE
CS,
CS 2
OE
RESET
C 'N
Input Capacitance
V,N = OV
5
pF
X
X
X
X
L
-
Resets all bits to low
C OUT
Output Capacitance
7
pF
X
H
X
X
H
Z
Deselect chip
X
X
L
X
H
Z
Deselect power down
X
VHC
X
X
H
Z
Deselect chip
VOUT
=OV
NOTES:
1. This parameter is sampled and not 100% tested.
FUNCTION
I/O
X
X
VLC
X
VHC
Z
CMOS deselect
power down
H
L
H
H
H
Z
Output disable
H
L
L
L
H
H
L
X
H
H
DOUT
D'N
Read
Write
NOTE:
1. CS2 will power-down CS" but CS 1 will not power-down CS 2.
2-73
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT71681/IDT71682 are 16,384-bit high-speed static RAMs
organized as 4K x 4. They are fabricated using IDT's highperformance, high-reliability technology-CEMOS. This stateof-the-art technology, combined with innovative circuit design
techniques, provides a cost effective alternative to bipolar and
fast NMOS memories
Access times as fast as 20ns are available with maximum
power consumption of only 550mW. These circuits also offer a
reduced power standby mode (IS8)' When CS goes high, the
circuit will automatically go to, and remain in, this standby mode
as long as CS remains high. In the ultra low power standby mode
(lS81), the devices consume less than 10"W, typically. This
capability provides significant system-level power and cooling
savings. The low power (L) versions also offer a battery backup
data retention capability where the circuit typically consumes
only 1"W operating off a 2V battery.
All inputs and outputs of the IDT71681/IDT71682 are TTLcompatible and operate from a single 5V supply, thus simplifying
system designs. Fully static asynchronous circuitry is used,
which requires no clocks or refreshing for operation, and
provides equal access and cycle times for ease of use.
The IDT71681/IDT71682 are packaged in either space-saving
24-pin, 300 mil DIPs or 28-pin leadless chip carriers, providing
high board-level packing densities.
The IDT7168111DT71682 Military RAMs are 100% processed in
compliance to the test methods of MIL-STD-883, Method 5004,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Separate data inputs and outputs
I DT71681 SAlLA: outputs track inputs during write mode
IDT71682SA/LA: high impedance outputs during write mode
High-speed (equal access and cycle time)
-Military - 25/35/45/55/70/85/100ns (max.)
-Commercial- 20/25/35/45/55ns (max.)
• Low-power consumption
- I DT7168112SA
Active: 225mW (typ.)
Standby: 100"W (typ.)
-IDT71681/2LA
Active: 225mW (typ.)
Standby: 10"W (typ.)
• Battery backup operation - 2V data retention
(L version only)
• High-density 24-pin 30D-mil DIPs and 28-pin lead less
chip carriers
• Produced with advanced CEMOS'· high-performanc,e
technology
• CEMOS process virtually eliminates alpha particle softerror rates (with no organic die coatings)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product available 100% screened to MIL-STD-883,
Class 8
PIN CONFIGURATIONS
A, A. A, A. Vee An
Vee
A"
LOGIC SYMBOL
A"
FUNCTIONAL BLOCK DIAGRAM
: I
A"
A.
A,
A,
A,
A,
A,
N.C.
O.
O.
N.C.
N.C.
A,
A,
A,
N.C.
A.
0,
Y.
0,
Y,
0,
Y.
Y,
Y,
Dz CsGNDWEY,
WE
V,
y~
A,
128·128
Memory Array
Y.
Y,
A,
A,
A,
A,
Y,
Y,
A,
A"
A"
LCC
TOP VIEW
DIP
TOP VIEW
Cs
We
PIN NAMES
A.-A"
ADDRESS INPUTS
D,-D,
DATA IN
CS
CHIP SELECT
Y,-Y,
DATA OUT
WE
WRITE ENABLE
GND
GROUND
Vcc
POWER
r------- -----
1
ID171682 ONLY
__ __
-r1
WE~¢=~c~~_~Q
__-__~__
,-----------
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
01986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-74
IDTn681SAlLA AND IDTn682SA/LA
CMOS STATIC RAMS 16K 14K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
RECOMMENDED DC OPERATING CONDITIONS
VALUE
RATING
Terminal Voltage with
Respect to GND
-0.5 to +7.0
TA
Operating Temperature
-55 to +125
·C
TBIAS
Temperature Under Bias
-65 to +135
·C
TSTG
Storage Temperature
-65 to +150
·C
VTERM
SYMBOL
UNIT
V
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
mA
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
-
6.0
V
V,l
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. V1L min = -3.0V for pulse width less than 20n5.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
AMBIENT
TEMPERATURE
GND
Vee
-55·C to +125·C
OV
5.0V± 10%
O·C to +70·C
OV
5.0V± 10%
Commercial
DC ELECTRICAL CHARACTERISTICS
= 5.0V ± 10%, VLC = 0.2V, VHC =VCC - 0.2V
Vcc
SYMBOL
Ilul
IlLOI
Input Leakage Current
Output Leakage Current
Val
Output Low Voltage
VOH
Output High Voltage
IDT71681SA
IDT71681LA
IDT71682SA
IDT71682LA
MIN. Typ.(1) MAX. MIN. TYP'(1) MAX.
TEST CONDITIONS
PARAMETER
Vee = Max.; V,N
=GND to Vee
Vee = Max.
CS =V,H. VOUT = GND to Vee
MIL.
COM'L.
MIL.
COM'L.
10l = 10mA, Vee = Min.
IOl = 8mA, Vee
=Min.
IOH = -4mA, Vee = Min.
-
-
2.4
10
5
-
-
-
-
10
5
-
0.5
-
0.4
-
-
-
2.4
-
UNIT
5
2
p.A
-
5
2
p.A
-
0.5
V
-
0.4
V
-
-
V
-
NOTE:
1. Typical limits are at Vee
= 5.0V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS(1)
Vcc = 5.0V ± 10%, VLC = 0.2V, VHC = Vcc - 0.2V
SYMBOL
PARAMETER
20n.
POWER
25n.
35n8
45n.
70ns(2)
55n.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL
COM'L.
MIL.
COY'L.
MIL.
100
110
80
-
80
30
35
-
35
20
20
-
20
SA
90
~
90
100
90
100
90
100
90
100
ICC1
LA
70
.,
70
80
70
80
70
80
70
80
Qlnamic Operating Current
CS = V Il' Output Open,
Vee = Max.,f = f Max.
SA
120
"'
110
120
100
110
100
110
100
lee2
100
80
90
70
80
70
45
30
35
30
35
25
20
25
ISB
1581
Standby Power Supply Current
fITL Level)
CS2:V,H,
Vee = Max., Output Open
Full Standby Power Supply
Current (CMOS Level)
CS 2" V He, Vee = Max.,
V tN :::: V HC or V tN ::; V LC
.-
100 .... -
90
SA
45", , -
35
MIL.
-
Operating Power Supply Current
CS = V Il' Output Open,
Vee = Max., f = 0
LA
COM'L.
mA
80
110
mA
mA
~
LA
30., -
UNIT
25
30
20
,.
SA
20
-
2
10
2
10
2
10
2
10
-
10
LA
'2
-
0.05
0.3
0.05
0.3
0.05
0.3
0.05
0.3
-
0.3
NOTES:
1. All values are maximum guaranteed values.
2. Also available: 85ns and 100ns Military devices.
2-75
mA
IDT71681SAlLA AND IDT71682SA/LA
CMOS STATIC RAMS 16K (4K x 4-BIn
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS (L Version
SYMBOL
VDA
leeDA
tCDA
t R (6)
PARAMETER
Only)
IDT71681SAlLA - IDT71682SA/LA
MIN.
TYR
MAX.
TEST CONDITIONS
Vee for Retention Data
CS 2: Vee - 0.2V
Y,N 2: Vec - 0.2V
or $ 0.2V
Data Retention Current
MIL.
COM'L.
Chip Deselect to Data Retention Time
Operation Recovery Time
UNIT
2.0
-
-
V
-
0.5(2)
to(3)
100(2)
150(3)
p.A
0.5(2)
to(3)
20(2)
30(3)
p.A
0
t RC (4)
-
-
ns
ns
NOTES:
1. TA = 2S·C
2. at Vee = 2V
3. at Vee =3V
4. t AC =Read Cycle Time
5. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
~Dala RetenlionMode_
Vee
4.5V
r
os
ICDA
1\
J 4.5V
~____~VD~._.2_V____--I1
'_1
1-1
-
7777l!vIH '
VD.
, VIH\\\\\\'
AC TEST CONDITIONS
+5V
+5V
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDt03.0V
Sns
48DC
DOUT-~---i
DOUT-~---i
1.SV
1.SV
5pF'"
3OpF"
See Figures 1 and 2
Figure 1. Output Load
Figure 2, Output Load
(for t HZ• tLz. t wz• and tow)
·Including scope and jig.
2-76
IDT71681SAlLA AND IDT71682SA/LA
CMOS STATIC RAMS 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(4) (Vee
SYMBOL
71681X20 (1 )
71682X20(1 )
MIN.
MAX.
PARAMETER
= 5V
± 10%, All Temperature Ranges.)
71681 X25 (5 )
71682X25 IS)
MIN.
MAX.
71681X35
71682X35
MIN.
MAX.
71681X45
71682X45
MIN.
MAX.
71681X55
71682X55
MIN. MAX.
71681 X70 (2)
71682X70 (2)
MIN.
MAX.
UNIT
READ CYCLE
tRC
Read Cycle Time
20
-
25
-
35
-
45
-
55
-
70
-
ns
tAA
Add ress Access Ti me
-
20
-
25
-
35
45
-
55
ns
Chip Select Access Time
-
20
-
25
-
35
45
-
55
-
70
tACS
-
70
ns
tOH
Output Hold from
Address Change
5
-
5
-
5
-
5
-
5
-
5
-
ns
tLZ
Chip Selection to
Output in Low l(3)
5
-
5
-
5
-
5
-
5
-
5
-
ns
tHZ
Chip Deselect to
Output in High l(3)
-
10
-
10
-
15
-
20
-
25
-
30
ns
tpu
Chip Select to
Power Up Time (3 )
0
-
0
-
0
-
0
-
0
-
0
-
ns
tpD
Chip Select to
Power Down Time(3)
-
20
-
25
-
35
-
40
-
50
-
60
ns
tRCS
Read Command
Set-UpTime
-5
-
-5
-
-5
-
-5
-
-5
-
-5
-
ns
tRCH
Read Command
Hold Time
-5 .
-
-5
-
-5
-
-5
-
-5
-
-5
-
ns
WRITE CYCLE
twc
Write Cycle Time
:,(t:
-
20
-
30
-
40
-
50
-
60
-
ns
tcw
Chip Select to
End of Write
~()
-
20
-
30
-
40
-
50
-
60
-
ns
~O
-
20
-
30
-
50
-
60
-
ns
-
0
0
0
-
0
-
0
-
ns
20
-
20
-
25
30
-
35
-
40
-
ns
0
-
0
-
0
0
-
0
-
0
-
ns
13
13
-
17
-
40
0
20
20
-
ns
-
3
-
3
3
-
25
3
-
3
-
ns
tAW
Address Valid to End
of Write
tAS
Address Setup Time
'.
twp
Write Pulse Width
tWA
Write Recovery Time
tDW
Data Valid to End of Write
tDH
Data Hold Time
3
-
t,V
Data Valid to Output
Valid (71681 only)13)
-
20
-
25
-
30
-
35
-
35
-
40
ns
twv
Write Enable to Output
Valid (71681 only)13)
-
20
-
25
-
30
-
35
-
35
-
40
ns
twz
Write Enable to Output
in High l (71682 only)13)
-
7
-
7
-
13
-
20
-
25
-
30
ns
tow
Output Active from End
of Write (71682 only) (3)
0
-
0
-
0
-
0
-
0
-
0
-
ns
NOTES:
1. DoC to +70°C temperature range and standard power only.
2. -55 D C to +125°C temperature range only.
3. This parameter guaranteed but not tested.
4. X in part numbers represents SA or LA.
2-77
IDT71681SAlLA AND IDT71682SAlLA
CMOS STATIC RAMS 16K (41< x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2)
Ad _ _
D... Out
t=~~·tR~C'~t::
====~~~_'~~~
___tOH__~~m-tM~~~1:
i X X )I<_____________
......... Doto Valid
Da.. Valid
TIMING WAVEFORM OF READ CYCLE NO. 2(1,3)
_: i;1---;~.-~u__
tRC·-l-li"-j
!5.c_
Current 1.1
V.. Supply
~,--__--,)K
I t~!)
J-_
_
Da..
~lI-~H~"=h:=I_=::O::"~
V.11d
1_ -tPD~{
r-.
I
I
~
'--_ __
~~I~----~_~--------------------~----~--~~--------
NOTES: 1. WE Is high for READ cycle.
2. CS is low for READ cycle.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.
6. This parameter is sampled and not 100% tested.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
Address
--'
tew
tAW
I.
,\ \\\
j~\\\\' ,\\\\
'0
.
twp
-t.. -t\~
Data
-
twe
~
r-----...;.------,r=
low _____ - - - I D H - - '
Data Valid
I-\Y~I
DataOut!51
Data Undellned
•
Data Valkt
k_
I- twz.~~
DIItaOut(8J
______--
I+(:
Dala Undefined
IWR _ _
~
I--tow · · -
t----~~~~---o(.
H... '..........
' - -_ __
2-78
IDT71681SAlLA AND IDT71682SA/LA
CMOS STATIC RAMS 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
WE
----------*
I-----+--- -_. low - - - - - - . .
Data In
NOTES: 1.
2.
3.
4.
5.
6.
I
D.t, V,'ld
l-tWY->k~--
Oata Dul(S)
--------------------I_twz'_~
Data DutlS)
Data Undefined
Data Undefined
,
Data Valid
JIr------~-:-_:_-----High Impedance
Cs or WE must
be high dunng address transitions.
If CS goes high simultaneously with WE high, the output remains In a high impedallce state.
All wnte cycle timings are referenced from the last valid address to the first transltlonlng address
Transition is measured ± 200mV from steady state voltage with specified loading In Figure 2. This parameter is sampled and not 100% tested.
For IOT71681 only.
For IOT71682 only.
TRUTH TABLE
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
MODE
CS
WE
OUTPUT
POWER
Standby
H
X
High Z
Standby
C 'N
Input Capacitance
Read
L
H
DOUT
Active
C OUT
Output Capacitance
Write(1)
L
L
Active
NOTE:
Write!')
L
L
D'N
High Z
Active
1. This parameter is sampled and not 100% tested.
SYMBOL
NOTES:
1. For IDT71681 only.
2. For IDT71682 only.
2-79
PARAMETER(1)
CONDITIONS
V,N
0
OV
VOUT - OV
TYP.
UNIT
5
pF
7
pF
IDT7I681SAlLA AND IDT7I682SAlLA
CMOS STATIC RAMS 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
vs.
ICC
ICC
Supply Voltage
vs.
Temperature
I
=16 C
TA
Vcc=5.0V
0
1.5
1.5
1.0
/
V
1.0
.6
4.0
vs.
... ~
140
IS8 vs. Temperature
Supply Voltage
I
TA=!5 C
Vcc=5.0V
0
1.5
1.5
IS.
1.0
I'-.....
.5
-60
&.0
IS8
'"
r--...
v
/
1.0
.5
4.0
vs.
Supply Voltage
~
--140
IS81
=J5 C
TA
"'-
5
-60
&.0
IS81
~
ISB
vs.
Temperature
100.01---+--+---1---11
0
1.2
1.0
0.8
4.0
V
10.01---+--+---1'r/----1
V
1.0
O~~_L
&.0
-60
2-80
____
~
_ _ _ L_ _
~
140
IDT71681SAlLA AND IDT71682SAlLA
CMOS STATIC RAMS 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
ICCDR vs. Temperature
100.000
TA =25°
I\.
10.000
II
~
1.000
100
\
10.0
\
'CCDR
10.0
1.0
"-I
100.0
Vcc-5V
1.0
}
o
5
/
o
6
V
/
V
-60
140
tAA t ACS vs. Temperature
tAA t ACS vs. Supply Voltage
I
Vcc=5V
TA(oJ)
1.2
1.2
""
1.0
.8
4.0
1.0
"'-.....
/
.8
-60
6.0
tAA t ACS vs. Output Loading
Vcc=5V
V
TA =25
1.2
1.0
.8
/
V
~
V
o
200
2-81
/V
V
V
140
FEATURES:
DESCRIPTION:
• High-speed address/access time
-Military: 45/55ns (max.)
-Commercial: 35/45ns (max.)
• High-speed chip select access time
-Military: 25/30ns (max.)
-Commercial: 20/25ns (max.)
• High-speed comparison time
-Military: 45/55ns (max.)
-Commercial: 37/45ns (max.)
• Low-power operation
-IDT7174S
Active: 300mW (typ.)
• Produced with advanced CEMOS'· high-performance
technology
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Standard 28-pin DIP (600 mil), 28-pin THINDIP (400 mil)
and 32-pin LCC
• High-speed asynchronous RAM Clear on Pin 1
(Reset Cycle Time = 2 x TAAl
(Note: Some duty cycle limitations may apply)
The IDT7174 is a high-speed cache address comparator
subsystem consisting of a 65,536 bit static RAM organized as
8K x 8 and an 8-bit comparator. The IDT7174 can also be used
as an 8K x 8 high-speed static RAM. A single IDT7174 can
provide address comparison for 8K cache words as 21 bits of
address organized as 13 word cache address bits and 8 upper
address bits. Two IDT7174s can be combined to provide 29 bits
of address comparison, etc. The IDT7174 also provides a single
RAM clear control, which clears all words in the internal RAM
to zero when activated. This allows the tag bits for all locations
to be cleared at power-on or system reset, a requirement for
cache comparator systems.
The IDT7174 is fabricated using IDT's high-performance,
high-reliability technology - CEMOS. Address access times as
fast as 35ns, chip select times of 20ns and comparison times of
37ns are available with maximum power consumption of 825mW.
All inputs and outputs of the IDT7174 are TTL-compatible
and the device operates from a single 5V supply. Fully static
asynchronous circuitry is used, requiring no clocks or refreshing for operation.
The IDT7174 is packaged in either a 28-pin, 600 mil DIP; Ii
28-pin, 400 mil THINDIP, or a 32-pin lead less chip carrier,
providing high board level packing densities.
The IDT7174 Military grade Cache Comparator is 100% processed in compliance to the test methods of MIL-STD-883,
Method 5004, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
• Match Output on Pin 26
• Military product 100% screened to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
A
•••
•
256 x 256
MEMORY ARRAY
-Vee
-GND
I/O...,...---7---1>-_ _-+__<~
J-:.,,,.,..,.=-c====='
WE
MATCH'
("OPEN DRAIN)
SRD7174-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
C1986 Integrated Device Technology, Inc.
2-82
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7174S CMOS STATIC RAMS 64K (8K x 8-BIT) CACHE-TAG RAM
PIN CONFIGURATIONS
RESET
A'2
A7
A.
A.
A.
Aa
A2
A,
A.
110,
1/0 2
I/0 a
GND
Vee
WE
MATCH
'LJ LJ U
As J
A.
Ag
A"
OE
A,.
CS
110.
1/0 7
110.
110.
I/0.
5
3
2
I I LJ
LJ
LJ LJ30
32 ,31
1
[
A.
C
A.
A.
J6
A.
J7
27 [
A3
J8
26
A2
A,
J.
25 [
OE
J
10
24 [
A,o
J11
23 [
CS
J
22 [
110.
As
NC
28
12
A"
C NC
1/07
I/O,
N
MOO"
ggi3
z
CD
g gg
1ft
SRD7174-003
SAD7174-002
LCC
TOP VIEW
DIP
TOP VIEW
PIN NAMES
LOGIC SYMBOL
A.
A,
AO-12
Address
WE
Write Enable
11O,
1/0 , _8
Data Input/Output
OE
Output Enable
A2
1/0 2
CS
Chip Select
GND
Ground
Aa
I/0 a
RESET
Memory Reset
Vce
Power
A.
110.
DatalMemory Match (Open Drain)
A.
110.
MATCH
A.
A7
110.
1/0 7
A.
Ag
110.
MATCH
A,.
A"
A'2
SR07174~004
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
TA
Operating Temperature
-55 to +125
°C
TB1AS
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
-65 to +150
°C
Pr
Power Dissipation
1.0
W
lour
DC Output Current
50
mA
VrEAM
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
a
0
0
V
V,H
Input High Voltage
2.2
-
6.0
V
V'L
Input Low Voltage
-0.5(1)
-
0.8
V
SYMBOL
V
PARAMETER
NOTE:
1. V1L min::: -3.0V for pulse width less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation 01 the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
Commercial
2-83
AMBIENT
TEMPERATURE
GND
Vee
-55°C to +125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ± 10%
IDT7174S CMOS STATIC RAMS 64K (8K x B-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
=5.0V ± 10%, VLe = 0.2V, VHe =Vee -o.2V
Vee
SYMBOL
PARAMETER
1IL11
Input Leakage Current
IILol
Output Leakage Current(2)
VOH
MIN.
MIL.
COM'L.
=Max.; Y,N = GND to Vee
Vee =Max.
CS =V,H. VO UT =GND to Vee
IOL =ISmA MATCH
IOL =22mA MATCH
IOL =lOrnA. Vee =Min.
IOL =SmA, Vee =Min.
IOH =-4mA, Vee =Min.
Vee
Output Low Voltage
VOL
IDT7174S
TEST CONDITIONS
Output High Voltage
MIL.
COM'L.
MIL.
COM'L.
(Except Match)
TYP'(l)
-
-
2.4
UNIT
MAX.
10
5
p.A
10
5
p.A
0.5
V
0.5
V
0.5
V
-
0.4
V
-
-
V
NOTES:
1. Typical limits are at Vee = S.OV, +25 D C ambient.
2. Data and match.
DC ELECTRICAL CHARACTERISTICS(1,2)
Vee = 5.0V ± 10%, VLe = 0.2V, VHe = Vee - 0.2V
SYMBOL
PARAMETER
POWER
35ns
COM·L.
MIL.
45n&
MIL.
COM'L.
55n&
COM'L.
MIL.
UNIT
lee1
Operating Power Supply Current
Output Open, Vee =Max., I =0
S
110
-
110
125
-
125
rnA
lee2
Dynamic Operating Current
Output Open, Vee =Max., I =I Max.
S
150
-
140
150
-
145
rnA
NOTES:
1. All values are maximum guaranteed values.
2. This device has no power down mode.
AC TEST CONDITIONS
Input Pulse Levels
I nput Rise/Fall Times
Input Timing Relerenee Levels
Output Relerence Levels
Output Load-
GND to 3.0V
5ns
1.5V
1.5V
See Figs. I, 2, and 3
+5V
+5V
+5V
4800
4800
30pF
5pF·
SRD7174-005
SRD7174-006
DOUT ----,---i
2550
Figure I, Output Load
·Includlng scope and Jig
Figure 2. Output Load
(lor tCLZ toLZ' tCHZ t OHZ'
tow, tWHzl
2-84
..=-1"'
I
30PF
SRD7165-007
RL = 2000 (COM'L.)
= 2700 (MIL.)
Figure 3, Output Load lor Match
IDT7174S CMOS STATIC RAMS 64K (8K
x 8-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vee = 5V ± 10%, All Temperature Ranges)
SYMBOL
PARAMETER
IDT7174S35(1)
MIN.
MAX.
IDT7174S45
MAX.
MIN.
IDT7174S55(4)
MIN.
MAX.
UNITS
READ CYCLE
t AC
Read Cycle Time
35
-
45
-
55
-
ns
tAA
Address Access Time
-
35
-
45
-
55
ns
t ACS
Chip Select Access Time
-
20
-
25
-
30
ns
tClZ
Chip Select to Output in Low Z
0
-
0
-
0
-
ns
tOE
Output Enable to Output Valid
-
20
-
25
-
30
ns
tOLZ
Output Enable to Output in Low Z(2)
0
-
0
-
0
-
ns
tCHZ
Chip Select to Output in High Z(2)
-
15
-
20
-
25
ns
tOHZ
Output Disable to Output in High Z (2)
-
15
-
20
-
25
ns
tOH
Output Hold from Address Change
5
-
5
-
5
-
ns
tpu
Chip Select to Power Up Time(2)
0
-
0
-
0
-
ns
tpD
Chip Deselect to Power Down Time(2)
-
35
-
45
-
55
ns
twc
Write Cycle Time
35
-
45
-
55
-
ns
tcw
Chip Select to End of Write
20
-
25
-
30
-
ns
tAw
Address Valid to End of Write
30
-
40
-
50
-
ns
WRITE CYCLE
t AS
Address Setup Time
0
-
0
-
0
-
ns
twp
Write Pulse Width
30
-
40
-
50
ns
tWA
Write Recovery Time (CS, WE)
a
-
-
tWHZ
Write Enable to Output in High Z(2)
-
15
a
-
20
a
-
25
ns
tow
Data to Write Time Overlap
15
-
20
-
25
-
ns
tOH
Data Hold From Write Time
2
-
2
-
2
-
ns
tow
Output Active from End of Write(2)
5
-
5
-
5
-
ns
t AOM
Addresss to Match Valid
-
37
-
45
-
55
ns
tCSM
Chip Select to Match Valid
-
20
25
-
30
ns
tCSMHI
Chip Deselect to Match High
-
20
-
25
-
30
ns
tOAM
Data Input to Match Valid
-
28
-
35
45
ns
tOEMHI
OE Low to Match High
-
25
-
35
-
45
ns
tOEM
OE High to Match Valid
-
25
-
35
45
ns
tWEMH!
WE Low to Match High
-
25
-
35
45
ns
tWEM
WE High to Match Valid
-
25
-
35
45
ns
tRSMHI
RESET Low to Match High
-
25
-
35
-
ns
MATCH
45
tMHA
Match Valid Hold From Address
5
-
5
-
ns
Match Valid Hold From Data
5
-
5
-
5
tMHD
5
-
ns
t RSPW
RESET Pulse Width (3)
65
-
100
-
ns
RESET High to WE Low
-
80
t ASAC
10
-
10
-
ns
RESET
5
NOTES:
1.
aoe to +70°C temperature range only.
2. This parameter guaranteed but not tested.
3. Recommended duty cycle 10% maximum.
4. -55°C to +125°C temperature range only.
2-85
IDT7174S CMOS STATIC RAMS 64K (8K
x B-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS __
~
________________
-JI~
_____
CS
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS-t==_tRC-=~
D~ 1:=""?3iJ 1~"1
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
cs
tCHZ (5)
DOUT--------------{
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected.
CS
= V1L .
3. Address valid prior to or coincident with
4.
Cs
transition low.
BE = VIL
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
ADDRESS
CS
DOUT
~3El3~3E~~----------------1-------------
DIN
----------Ar-;rumto::--.'ihi~rq
2-86
IDT7174S CMOS STATIC RAMS 64K (8K x 8-BIT) CACHE-TAG RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2(1,6)
.
twc
ADDRESS
CS
\\
\
\
\
\~5)
JIIIIII
lAw
~-IWp(2)
--
•
__
\\\\
lAs
I-
- 4 - I WR (')
~tOH"'"
I---- -tWHZ(4,9) ___ tOW(9)_
(7)
DOUT
(8)
tOW. -tOH
-
RESET TIMING
~t----._I_RSPW----I~
XXXXXXXXXXXXXXXXXY
~'-t
MATCH TIMING
~
ADDRESS
~
-t~!::====t;;;.;IADM~=~:;j"".!-'\:=~'"==t,,;;IMH;;;-:A--j=:::::rCS \ \ \ \ \
\ \ \ t-- ~CSM
--'--'~>-'>""~-"--'+.--"-It>-------+-------'l--lcSMH' --+I
r
1IIIIIIC'
I
-----I
1lllllllllT
I
\
OEM
-[.- IWEM
----I
j.;iOEMH,-l
\
!+==IWEMH' ,
J IRSMH ,
I/Os "_ _ _ _VALID
_ _ _READ
_ _ DOUT
~~
_ __ _ J
MATCH-----------------------~--~Ir_--------------------~
NOTES:
1. WE must be high during aU address transitions.
2. A write occurs during the overlap (t wp) or a low es.
3. tWA is measured from the earlier of Cs or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
6. OE is continuously low (DE = V1L).
7. Dour is the same phase of write data of this write cycle.
8. If CS is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition Is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
2-87
IDT7174S CMOS STATIC RAMS 14K (8K x 8-BIT) CACHE-TAG RAM
CAPACITANCE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
(TA = +25°C, f = 1.0MHz)
PARAMETER(')
CONDITIONS
TYP.
UNIT
WE
CS
OE
C 'N
Input Capacitance
Y'N = OV
5
pF
X
X
X
C OUT
Output Capacitance
VOUT = OV
7
pF
SYMBOL
RESET MATCH
110
FUNCTION
L
H
-
Reset all bits to low
X
H
X
H
H
High Z
NOTE:
H
L
H
H
L
D,N
1. This parameter is sampled and not 100% tested.
H
L
H
H
H
D'N
Match
H
L
L
H
H
DOUT
Read
L
L
X
H
H
D,N
Write
2-88
Deselect chip
No Match
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle time)
-Military: 25/30/35/45/55/70/85ns (max.)
-Commercial: 25/30/35/45/55/70ns (max.)
The IDT7187 is a 64K x 1-bit high-speed static RAM fabricated using IDT's high-performance, high-reliability technology,
CEMOS. Access times as fast as 25n5 are available with maximum
power consumption of 550mW.
Both the standard (S) and low-power (L) versions of the
IDT7187 provide two standby modes-l s8 and IS81.IS8 provides
~ra low-power operation (192.5mW max.); IS81 provides lowpower operation (5mW max.). The low-power (L) version also
provides the capability for data retention using battery backup.
When using a 2V battery, the circuit typically consumes only
• Low-power consumption
-IOT7187S
Active: 300mW (typ.)
Standby: 100/tW (typ.)
-IDT7187L
Active: 250mW (typ.)
Standby: 30/tW (typ.)
• Battery backup operation - 2V data retention
(IDT7187L version only)
20/tW.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation, along with matching access and cycle
times. The device is packaged in an industry standard 22-pin, 300
mil DIP or 22- and 28-pin lead less chip carriers.
The IDT7187 Military RAM version is 100% processed to the
test methods of MIL-STD-883, Class B, Methods 5004 and 5005,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
• JEDEC standard high-density 22-pin DIP, 22-pin plastic
DIP, 22-pin and 28-pin leadless chip carrier
• Produced with advanced CEMOS ,. high-performance
technology
• Separate data input and output
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product available 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
A
Vcc
A
A
A
A
ROW
SELECT
A
A
•
•
•
•
•
GND
65,536-BIT
MEMORY ARRAY
•
•
A
CS
• • • • • •
DIN
DOUT
WE .....- - - - L . J
SRD7187-004
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
2-89
Ell
IDT7187S/IDT1187L CMOS STATIC RAMS 64K (64K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
As
Vee
A,
Au
A>
AM
A>
A13
A<
LOGIC SYMBOL
A11
As
AlO
A7
As
lUU
3 ... JLJIIL..ILol2
Au
As
zz>HC\!!
"
"'
4.c~cf
A2
A,.
A.
A,.
A.
A'2
Al1
As
A.
AI
A2
A3
A4
NC
As
As
A7
DOUT
A'D
Ag
A7
DOUT
As
WE
DIN
GND
Ci
As
19 ::
f1 q
22-PINLCC
TOP VIEW
28-PIN LeC
TOP VIEW
D,N
Ao
A,
A,
A>
A.
As
As
A7
DOUT
As
NC
As
n r'11
I~ CI
~ ~1l3 ~
C!I
DIP
TOP VIEW
J 11
:: 1214151618 ::
J
~ ~t
SRD7187-001
AM
A'3
AI2
All
NC
AIO
Ae
13r1
As
DOUT
:l4 2 t~2826 t.
:::5
1
25 r.
::6
J7
::: 8
22 r:
J 9
21 ~
J 10
20 :::
A10
Al1
Au
A13
AM
A_
SRD7187-002
SRD7187-003
PIN NAMES
Ao-AIS
~
WE
Vee
ADDRESS INPUTS
CHIP SELECT
WRITE ENABLE
POWER
DATA IN
DATA OUT
GROUND
DIN
DOUT
GND
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
TA
Operating Temperature
-55 to +125
°C
T B1AS
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
-65 to +150
°C
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
rnA
MIN.
TYP.
MAX.
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
-
6.0
V
O.B
V
SYMBOL
PARAMETER
V1H
Input High Voltage
2.2
V1l
Input Low Voltage
-0.5(')
UNIT
NOTE:
1. V1L min = -3.0V for pulse width less than 20n8.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation ofthedevice at these or any other conditions above those
Indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
AMBIENT
TEMPERATURE
GND
Vee
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 10%
Commercial
DC ELECTRICAL CHARACTERISTICS
Vec = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V
SYMBOL
PARAMETER
IDT7187S
IDT1187L
MIN. TYR(I) MAX. MIN. TYR(II MAX.
TEST CONDITIONS
lIul
Input Leakage Current
Vee = Max.; V,N = GND to Vee
MIL.
COM'L.
IILOI
Output Leakage Current
Vee = Max.
CS = V1H. VOUT = GND to Vee
MIL.
COM'L.
VOL
Output Low Voltage
VOH
Output High Voltage
-
IOl = lOrnA, Vee = Min.
-
10l = BmA, Vee = Min.
-
IOH = -4mA, Vee = Min.
2.4
NOTE:
I. Typical limits are at Vee = 5.0V, +25°C ambient.
2-90
-
0.5
-
0.4
-
-
2.4
10
5
10
5
-
UNIT
5
2
p.A
5
2
p.A
0.5
V
0.4
V
-
V
IDT7187S/IDT7187L CMOS STATIC RAMS 64K (64K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (for each speed)
VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V
SYMBOL
ICC1
ICC2
ISB
ISB1
PARAMETER
25ns
POWER
Operating Power
Supply Current
CS =V 'b
Output Open,
Vcc=Max.,f=O
Dyn. Op. Current
CS = V ,b
Output Open,
Vcc = Max.,
f=fMax.
Standby Power
Supply Current
(TTL Level)
CS;:"V ,H,
Vcc = Max.,
Output Open
Full Stdby. Power
Supply Current
(CMOS Level)
CS;:" V HC,
Vcc = Max.,
V,N ;:" VHCor
V,N'" VLC
3On8
35n8
45n8
55ns
70ns
85ns
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
S
90
105
90
105
90
105
90
105
90
105
90
105
90
105
L
70
a~
70
85
70
85
70
85
70
85
70
85
70
85
S
120
130
110
120
110
120
110
120
110
120
110
120
110
120
L
100 '"110
95
110
90
100
85
95
85
95
80
90
80
90
S
55;:
' 55
45
50
45
50
45
50
45
50
45
50
45
50
L
45
,
50
40
45
35
40
30
35
25
30
25
28
25
28
S
15
20
15
20
15
20
15
20
15
20
15
20
15
20
L
0.3
1.5
0.3
1.5
0.3
1.5
0.3
1.5
0.3
1.5
0.3
1.5
0.3
1.5
UNIT
mA
mA
mA
mA
NOTE:
1. All values are maximum guaranteed values.
DATA RETENTION CHARACTERISTICS
(L Version Only) VLC = 0.2V,vHC = Vcc - 0.2V
SYMBOL
PARAMETER
MIN,
TEST CONDITION
TYP.(')
MAX.
Vcc @
Vcc @
2.0V
VDR
-
Operation Recovery Time
ICCDR
Data Retention Current
tCDR(3)
Chip Deselect to Data
Retention Time
tR (3 )
Operation Recovery Time
II Ll I(3)
Input Leakage Current
I
MIL.
COM'L.
CS ;:"VHC
Y'N ;:" VHC or '" VLC
3.0V
-
-
-
-
V
-
10
10
15
15
600
900
150
225
I'A
0
-
-
ns
t Rc(2 )
-
-
ns
2
p.A
-
1. TA = +25°C.
2. IRC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
- - - DATA RETENTION MODE---
4.SV
VOR?' 2Y
4.SY
SRD7187-()()5
2-91
UNIT
3.0V
2.0
NOTES:
vee
2.0V
fI
IDT7187S/IDT7187L CMOS STATIC RAMS 64K (64K xl-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
+5V
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
+5V
GNDto3.0V
4802
5ns
1.5V
Output Reference Levels
480<>
DOUT---,----i
DOUT---,----i
1.5V
See Figures 1 and 2
Output Load
5pF"
SR07167-006
SRD7187-007
Figure 1. Output Load
Figure 2. Output Load
(for tHz, t lZ, t wz , and tow)
"Including scope and jig.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vee = 5V ± 10%, All Temperature Ranges)
7187S85(2)
7187S30
7187S35
7187S45
7187S55
7187S70
7187S25
7187L85(2) UNITS
7187L45
7187L55
7187L30
7187L70
7187L35
7187L25
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE
t RC
Read Cycle Time
25
-
30
-
35
-
45
-
55
-
70
-
85
-
ns
tAA
Address Access Time
25
-
30
-
35
-
45
-
55
-
70
ns
Chip Select Access Time
25
-
30
-
35
-
45
-
55
-
70
-
85
t ACS
-
85
ns
tOH
Output Hold from
Address Change
5
-
5
-
5
-
5
-
5
-
5
-
ns
tLZ
Chip Select to Output
in Low Z(3)
5
-
5
-
5
-
5
-
5
-
5
-
ns
tHZ
Chip Deselect to Output
in High Z(3)
-
25
-
25
-
30
-
30
-
30
-
40
ns
tpu
Chip Select to Power Up
Time(3)
0
-
0
-
0
-
0
-
0
-
0
-
ns
tpo
Chip Deselect to Power
Down Time(3)
-
30
-
30
-
35
-
35
-
35
-
40
ns
WRITE CYCLE
5
t>::
~~
t
.''''''''~
30
-
35
-
45
-
55
-
70
-
85
-
ns
25
-
30
-
40
-
50
-
55
-
65
-
ns
tAW
Address Valid to End
of Write
25
-
50
-
55
-
65
-
ns
0
-
40
Address Setup Time
0
-
0
-
0
-
ns
Write Pulse Width
20
25
-
30
-
35
40
-
45
-
ns
tWR
Write Recovery Time
0
0
-
0
-
0
-
0
twp
-
30
t AS
0
-
0
-
ns
tow
Data Valid to
End o/Write
20
-
20
-
25
-
25
-
30
-
35
-
ns
tOH
Data Hold Time
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
twz
Write Enable to Output
in High Z(3)
0
20
0
25
0
25
0
30
0
30
0
30
0
40
ns
tow
Output Active from End
ofWrite(3)
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
twc
Write Cycle Time
tcw
Chip Select to End
of Write
2'o::t0i<'%
0
NOTES:
1. OOC to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. This parameter guaranteed but not tested.
2-92
IDT7187SIIDT7187L CMOS STATIC RAMS 64K (64K x 1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2)
C
F::::::::::::::::_'R_c(_51::::::::::::::.::::
ADDRESS
------"~'OHPREVIOUS DATA VALID
DATAoUT
DATA VALID
SRD71B7-0OB
TIMING WAVEFORM OF READ CYCLE NO. (1,3)
,
,
IRe{S)
~
,
lACS
_ _ _ t LZ (4)
DATAOUT
)K
I'
r-1~1
-----
f--'Hz(4)~
~I
--.~
DATA VALID
'1
HIGH IMPEDANCE
ICC
Vee SUPPLY
CURRENT Iss
SRD7187-009
NOTES;
1.
2.
3.
4.
5.
cycle.
WE is high for READ
CS is low for READ cycle.
Address valid prior to or COincident with CS tranSition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
,
'we
ADDRESS
~
-
....J
I,
,
'ew
.\ \\\
'AW
\\
:\\\\ .\\\\
'w.
tDW --------.
DATAIN _ _ _ _ _ _ _ _-'-_ _ _ _
[--DATAOUT
0
.Jt=
-'A5-1
twR-
0
---IDH ___
DATA,. VALID
twz (4)------.
DATA UNDEFINED
HIGH IMPEDANCE
SRD71B7-010
NOTES;
1. CS or WE must be high during address transitions
2. It CS goes tllgh simultaneously with WE high. the output remains in a high Impedance state.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
2-93
IDm87SIlDm87L CMOS STATIC RAMS 14K (64K 1I1-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
--------tWC(3)---------i~1
ADDRESS
I_--~~::~::::::::::~.I ~tWA--'
X-·
-+___
.D_
_
W
__
_
-_
DH
~
DATAIN VAUD
DATA UNDEFINED
DATAOUT
HIGH IMPEDANCE
SRD7187-011
NOTES:
1. CS or WE must be high during address transitions.
2. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
TRUTH TABLE
CAPACITANCE
MODE
CS
WE
OUTPUT
POWER
Standby
H
X
High Z
Standby
Read
L
H
DOut
Active
Write
L
L
High Z
Active
SYMBOL
C'N
C OUT
(TA = +25 0 C. f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYR
UNIT
Input Capacitance
V'N=OV
5
pF
VOUT=OV
7
pF
Output Capacitance
NOTE:
1. This parameter i. sampled and not100'1l0 tested.
2-94
FEATURES:
DESCRIPTION:
• High-speed (equal access and cycle times)
-Military - 30/35/45/55/70/85ns (max.)
-Commercial - 25/30/35/45/55/70ns (max.)
The I DT7188 is a 65,536-bit high-speed static RAM organized
as 16K x4. It is fabricated using IDT's high-performance, highreliability technology - CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques, providesa cost effective approach for memory intensive applications.
Access times as fast as 25ns are available, with maximum
power consumption of only 740mW. The IDT7188 offers a
reduced power standby mode, IS81' which enables the designer
to greatly reduce device power requirements. This capability
significantly decreases system power and cooling levels, while
greatly enhancing system reliability. The low-power (l) version
also offers a battery backup data retention capability where the
circuit typically consumes only 20"W when operating from a 2V
battery.
All inputs and outputs are TTL-compatible and operate from a
single 5 volt supply. Fully static asynchronous circuitry, along
with matching access and cycle times, favor the simplified
system design approach.
The IDT7188 is packaged in a 22-pin, 300 mil DIP providing
excellent board-level packing densities.
The I DT7188 military RAM is 100% processed in compliance to
the test methods of Mll-STD-883, Method 5004, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
• low-power operation
-IDT7188S
Active: 350mW (typ.)
Standby: 100"W (typ.)
-IDT7188l
Active: 300mW (typ.)
Standby: 30"W (typ.)
• Battery backup operation - 2V data retention
(l version only)
• Available in high-density industry standard 22-pin, 300 mil
ceramic and plastic DIPs
• Produced with advanced CEMOS'· technology
• Single +5V (±10%) power supply
• Inputs/outputs TTL-compatible
• Three state outputs
• Static operation - no clocks or refresh required
•
Military product 100% screened to MIL-STD-883, Class B
PIN CONFIGURATION
A.
Vee
A,
A"
.,
An
A,
..
....
..
A"
A,
A,
A,
1/02
1/01
GND
WE
1/03
A"
A"
An
A"
1/03
Os
1/02
.
A,
1/04
A,
lID,
A,
A,
A,
A,
A,
A"
A,
FUNCTIONAL BLOCK DIAGRAM
LOGIC SYMBOL
lID"
WE
OS
5607188-001
6807188-002
DIP
CS
TOP VIEW
WE
PIN NAMES
Ao-A13
CS
WE
ADDRESS INPUTS
CHIP SELECT
WRITE ENABLE
SSD7188-003
1/0,-1/04
Vee
GND
DATA I/O
POWER
GROUND
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1986 Integrated Device Technology, Inc.
2-95
JULY 1986
Printed in U.S.A.
II
IDT718BS/IDT7188L 64K (16K x 4-BIT) CMOS STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
TA
Operating Temperature
-55 to +125
°C
T BIAS
Temperature Under Bias
-65 to +135
°C
TSTG
Storage Temperature
-65 to +150
°C
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
rnA
VTERM
SYMBOL
MIN.
TYP.
. MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
6.0
V
V,L
Input Low Voltage
-0.511)
-
0.8
V
NOTE:
1. V1l min = -3.0V for pulse width less than 20n5.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
GRADE
indicated in the operational sections of this specification is not implied,
Military
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Commercial
AMBIENT
TEMPERATURE
GND
Vee
-55°C to +125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V± 10%
DC ELECTRICAL CHARACTERISTICS
± 10%, VLC = 0.2V, VHC = VCC - 0.2V
Vcc = 5.0V
SYMBOL
PARAMETER
Input Leakage Current
IILlI
IILol
Output Leakage Current
VOL
Output Low Voltage
VOH
Output H ig h Voltage
IDT7188S
IDT7188L
MIN. TYP.C') MAX. MIN. TYP'C') MAX.
TEST CONDITIONS
Vee = Max.; V,N ' GND to Vee
MIL.
COM'L.
-
Vee' Max.
CS • V,H, VOUT ' GND to Vee
MIL.
COM'L.
-
-
-
10L' lOrnA, Vee' Min.
-
IOL' 8mA, Vee' Min.
-
IOH • -4mA, Vee' Min.
2.4
--
-
10
5
10
5
-
-
UNIT
5
2
p.A
5
2
p.A
0.5
-
-
0.5
V
0.4
-
-
0.4
V
-
2.4
-
-
V
NOTE:
1. Typical limits are at Vee' 5.0V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS
± 10%, VLC • 0.2V, VHC = VCC - 0.2V
VCC • 5.0V
SYMBOL
PARAMETER
POWER
25n8
COM'L.
leel
lec..2
ISB
ISBI
Operating Power
~ply Current
CS 'V ,Lo
Output Open,
Vee' Max., f • 0
Dyn. Op. Current
CS'V ,Lo
Output Open,
Vee' Max.,
f 'fMax.
Standby Power
Supply Current
(TTL Level)
CS;::V ,H ,
Vee' Max.,
Output Open
Full Stdby. Power
Supply Current
(CMOS Level)
CS 2: V He,
Vee' Max.,
V ,N ;:: V He or
V,N"V le
MIL.
30nl
MIL.
COM'L.
35ns
MIL.
COM'L.
45n.
MIL.
COM'L.
55ns
70ns
COM'L.
MIL.
COM'L.
MIL.
85n.
COM·L. MIL.
100
110
100
110
100
110
100
110
100
110
-
110
85
95
85
95
85
95
85
95
85
95
-
95
125
140
125
140
125
140
125
140
125
140
'-
140
115
125
105
115
100
110
100
110
95
110
-
105
551!-
50
55
45
50
45
50
45
50
45
50
-
50
f/-
40
45
35
40
30
35
30
35
30
35
-
35
-
S
100
L
85
S
135 :
L
125
S
L
UNIT
rnA
;~
i!!!-
rnA
rnA
S
Q~
-
15
20
15
20
15
20
15
20
15
20
-
20
L
0.5
-
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
-
1.5
rnA
NOTE:
1. All values are maximum guaranteed values.
2-96
IDT7188SIIDT718BL 14K (16K x 4-BIT) CMOS STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC : O.2V, VHC : Vcc - O.2V
TYP.!')
SYMBOL
VOR
PARAMETER
MIN,
TEST CONDITION
-
Vcc for Data Retention
ICCOR
Data Retention Current
t COR (3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
lIul (3)
Input Leakage Current
I
MIL.
COM'L.
CS;>: VHC
Y'N ;>: VHC or ,,; VLC
MAX.
Vcc @
2.0V
3.0V
Vcc @
2.0V
3.0V
2.0
-
-
-
-
-
10
10
15
15
600
150
900
225
UNIT
V
p.A
0
-
-
t RC (2)
-
-
ns
-
-
2
p.A
ns
NOTES:
1. TA = +25°C.
2. t Re = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
I--- DATA RETENTION MODE-----.-.a
Vee
4.5V
I\,-__Y;.::D::..'::..~2V~ _ _.J1
-.tleDO'"
OS 7////7fV.H \
YDO
4.5V
I- I'-j
I
Y'H\\\\\\'
S807188-004
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDt03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
8507188-005
Figure 1. Oulput Load
55D7188-006
Figure 2. Output Load
(lor tHZ' tLz, tWZ. and tow)
"Including scope and JIg.
2-97
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7188S/IDT7188L 64K (16K x 4-BIT) CMOS STATIC RAMS
AC ELECTRICAL CHARACTERISTICS (Vee = 5V ± 10%, All Temperature Ranges)
SYMBOL
7188525(1)
7188S30(4)
7188S85(2)
7188S35
7188S45
7188S55
7188S70
7188L25(1)
7188L85 (2) UNITS
7188L45
7188L55
7188L30
7188L70
7188L35
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
PARAMETER
REAl:! CYCLE
t RC
Read Cycle Time
25
-
30
-
35
-
45
-
55
-
70
-
85
-
ns
tAA
Address Access Time
-
25
-
30
-
35
-
45
-
55
-
70
-
85
ns
tAGS
Chip Select Access Time
-
25
-
30
-
35
-
45
-
55
-
70
-
85
ns
tOH
Output Hold from
Address Change
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tLZ
Chip Select to Output
in Low Z13)
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tHZ
Chip Deselect to Output
in High Z13)
-
-
15
-
15
-
20
-
25
-
30
ns
t pu
Chip Select to Power
Up Timel 3)
0
t pD
Chip Deselect to Power
Down Time(3)
-~
!'w
.;,
-
13
0
-
0
-
0
-
0
-
0
-
0
-
ns
-
30
-
35
-
45
-
55
-
70
-
85
ns
ZZ,;
WRITE CYCLE
twe
Write Cycle Time
2q~t; -
25
30
-
40
-
50
-
60
-
75
-
ns
tew
2,;~!
-
-
Chip Select to End
of Write
25
-
30
-
35
-
50
-
60
-
75
-
ns
tAW
Address Valid to End
of Write
i7
-
25
-
25
-
35
-
50
-
60
-
75
-
ns
-
0
-
0
-
0
-
0
-
0
-
ns
-
25
-
25
-
35
50
60
0
-
0
0
-
0
-
ns
-
-
75
0
-
-
0
20
!a
t AS
Address Setup Time
twe
Write Pulse Width
tWA
Write Recovery Time
0
-
tDW
Data Valid to End
of Write
13
-
15
-
15
-
20
-
25
-
30
-
35
tDH
Data Hold Time
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
twz
Write Enable to
Output in High Z(3)
-
7
-
10
-
10
-
15
-
25
-
30
-
40
ns
tow
Output Active from
End of Write(3)
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
NOTES:
1. OOC to +70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. This parameter guaranteed but not tested.
4. Preliminary data only for military devices.
TIMING WAVEFORM OF READ CYCLE
ADDRESS
DATA OUT
NO. 1(1,2)
f=
-----"~-\OH
\"'-------C=~
-
-
DATA VALID
PREVIOUS DATA VALID
SSD7188-007
2-98
0
ns
ns
IDT7188S/IDT7188L 64K (16K x 4-BIT) CMOS STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1,3)
1-------IRC5-------I,~-------
_____ n---------------~---·D~
S807188-oo8
NOTES:
1. WE is high for READ cycle.
2. C§ is low for READ cycle.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
ADDRESS
DATA IN
DATA OUT
------------DATA UNDEFINED
HIGH IMPEDANCE
SSD718&{)09
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
1 - - - - - - - I I W C3 - - - - - - - I
ADDRESS
NOTES:
1. C§ or WE must be high during address transitions.
2. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid addr~ to the first transitioning address.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
2-99
IDT7188SIlDT7188L 64K (18K
x 4-BIT) CMOS STATIC RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA =+25°C, f
TRUTH TABLE
MODE
Standby
Read
Write
e!l
WI!
H
L
L
X
H
L
110
High Z
DOUT
D'N
POWER
Standby
Active
Active
SYMBOL
PARAMETER(1)
C 'N
Input Capacitance
C OUT
Output Capacitance
=1.0MHz)
CONDITIONS
V,N
= OV
VOUT = OV
NOTE:
1. This parameter is sampled and not 100% tested.
2-100
TYP.
UNIT
5
pF
7
pF
FEATURES:
•
•
Output Enable (OE) pin available for added system flexibility
Multiple Chip Selects (CS 1, CS 2) simplify system design and
operation
•
High-speed (equal access and cycle times)
-Military: 30/35/45/55/70/85ns (max.)
-Commercial: 25/30/35/45/55/70ns (max.)
• Low-power operation
-IDT7198S
Active: 350mW (typ.)
Standby: 100!'W (typ.)
-IDT7198L
Active: 300mW (typ.)
Standby: 30!'W (typ.)
•
Battery back-up operation - 2V data retention
(L version only)
•
24-pin THINDIp, 24-pin plastic DIP and high-density 28-pin
lead less chip carrier
Produced with advanced CEMOS'· technology
Bidirectional data inputs and outputs
Inputs/Outputs TTL-compatible
•
•
•
The dual chip select feature (CS1, CS2) now brings the
convenience of improved system speeds to the large memory
deSigner by reducing the external logic required to perform
decoding. Since external decoding logic is reduced, board space
Is saved, system speed is enhanced by approximately 10-20ns
and system reliability improves as a result of lower part count.
Both chip selects, chip select 1 (CS1) and chip select 2 (CS2),
must be in the active-low state to select the memory. If either chip
select is pulled high, the memory will be deselected and remain in
the standby mode.
The output enable function (OE) is also a highly desirable
feature of the IDT7198 high-speed common I/O static RAM. This
function is designed to eliminate problems associated with data
bus contention by allowing the data outputs to be controlled
independent of either chip select.
These added memory control features provide improved
system design flexibility, along with overall system speed
performance enhancements.
DESCRIPTION:
The IDT7198 is a 65,536 bit high-speed static RAM organized
as 16K x 4. It is fabricated using IDT's high-performance, highreliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective approach for memory intensive applications.
• Three state outputs
• Military product 100% screened to MIL-STD-883, Class B
MEMORY CONTROL:
The IDT7198 64K high-speed CEMOS static RAM Incorporates
two additional memory control features (an extra chip select and
an output enable pin) which offer additional benefits in many
system memory applications.
PIN CONFIGURATION
Ao
vee
A,
Au
A,
A"
A,
An
A.
A"
A,
A,
A,
CS2
.
M
1/04
1/0 3
CS,
1102
DE
liD,
GND
WE
The IDT7198 features three memory control functions: chip
select 1 (CS1), chip select 2 (CS2) and output enable (OE). These
three functions greatly enhance the IDT7198's overall flexibility in
(Con't on next page)
high-speed memory applications.
FUNCTIONAL BLOCK DIAGRAM
LOGIC SYMBOL
00 U
Z Z
0:(
Ne
A,
A,
A.
A,
A,
A,
..
cs,
Au
J5
OS
07
JB
09
A"
Au
20 r;
:::: 10
::::11
19 ::::
:::: 1214151618 C
13""" n "17
I~ ~1:31;
A"
A,
1/0 4
I/Os
1102
SRD7198-002
Vee
GND
..
..
A.
A,
65.536~BIT
1/02
MEMORY ARRAY
A,
A,
1/03
A"
Au
A"
Au
1/04
g-
Lee
DIP
liD,
AO
A,
A,
A,
l:l u
> z
I/O
I/O
CS,CS20EWE
TOP VIEW
SRD7198-003
TOP VIEW
I/O
I/O
PIN NAMES
Ao-A13 ADDRESS INPUTS
CSI
CHIP SELECT 1
CS2
CHIP SELECT 2
WE
WRITE ENABLE
OE
1/01-1/04
Vee
GND
OUTPUT ENABLE
DATA I/O
POWER
GROUND
~~
WE
~
I--------------------------~
SRD7198-004
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
@19661ntegrated Device TeChnOlogy, Inc.
2-101
IDT7198S/IDT7198L CMOS STATIC RAMS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Con't)
Access times as fast as 25ns are available, with maximum
power consumption of only 740mW. The IDT7198 offers a
reduced power standby mode, ISB1' which enables the designer
to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels,
while greatly enhancing system reliability. The low-power version
(Ll also offers a battery backup data retention capability where
the circuit typically consumes only 20j.lW when operating from a
2V battery.
All inputs and outputs are TTL-compatible and operate from a
single 5 volt supply. Fully static asynchronous circuitry, along
with matching access and cycle times, favor the simplified
system design approach.
The IDT7198 is packaged in either a 24-pin DIP, 24-pin plastic
DIP or 28-pin leadless chip carrier, providing improved boardlevel packing densities.
The IDT7198 military RAM is 100% processed in compliance to
the test methods of M I L-STD-883, Method 5004, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
TA
Operating Temperature
-55 to +125
·C
TBIAS
Temperature Under Bias
-65 to +135
·C
TSTG
Storage Temperature
-65 to +150
·C
VTERM
RATING
PT
Power Dissipation
1.0
W
lOUT
DC Output Current
50
mA
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
-
6.0
V
V,l
Input Low Voltage
-0.5(1)
-
O.B
V
SYMBOL
NOTE:
1. V1L min = -3.0V for pulse width less than
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2005.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
GND
Vee
-55·C to +125OC
OV
5.0V± 10%
OOCto +70OC
OV
5.0V± 10%
DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ±10%, VLC = O.2V, VHC = VCC - O.2V
SYMBOL
PARAMETER
IDT7198S
IDT7198L
MIN. TYR(1) MAX. MIN. TYP'(1) MAX.
TEST CONDITIONS
IOl = BmA. Vee = Min.
-
IOH = -4mA, Vee = Min.
2.4
Ilul
Input Leakage Current
Vec = Max.; V,N = GND to Vee
MIL.
COM'L.
IILOI
Output Leakage Current
Vee = Max.
CS = V,H. VOUT = GND to Vee
COM'L.
VOL
Output Low Voltage
VOH
Output High Voltage
10l = 10mA, Vee = Min.
NOTE:
1. Typical limits are at Vec = 5.0V, +25·C ambient.
2·102
MIL.
-
10
5
-
-
10
0.4
-
-
2.4
-
-
5
-
0.5
-
-
-
-
-
UNIT
5
2
p.A
5
2
p.A
0.5
V
0.4
V
-
V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAMS 64K (16K x 4-BIT)
DC ELECTRICAL CHARACTERISTICS(l)
= 5.0V ± 10%, VLC = 0.2V, '4ic =VCC - 0.2V
vcc
SYMBOL
PARAMETER
POWER
25n.
COM'L
Operating Power
Supply Current
CS =V ,L.
Output Open,
Vcc = Max., 1= 0
Icc1
Dyn. Op. Current
CS = V ,L,
Output Open.
Vcc = Max.,
I = I Max.'
ICC2
ISB
ISB1
35no
45no
70no
55no
85no
COM'l.
MIl.
COM'L.
MIl.
COM'L.
MIl.
CQM'l.
MIL
COM'L.
MIl.
COM'l.
UNIT
MIl.
S
100
-
100
110
100
110
100
110
100
110
100
110
-
110
L
85
-
85
95
85
95
85
95
85
95
85
95
-
95
135
-
125
140
125
140
125
140
125
140
125
140
-
140
mA
S
--~---
Standby Power
Supply Current
(TTL Level)
CS2>V ,H ,
Vce = Max.,
Output Open
30no
MIl.
- - - - - _ .. _--
--
mA
L
125
-
115
125
105
115
100
110
100
110
95
110
-
105
S
55
-
50
55
45
50
45
50
45
50
45
50
-
50
L
45
-
40
45
35
40
30
35
30
35
30
35
-
35
S
15
-
15
20
15
20
15
20
15
20
15
20
-
20
L
0.5
-
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
-
1.5
mA
Full Stdby. Power
Supply Current
(CMOS Level)
CS;O:V HC '
Vce = Max.,
V 1N 2: V HC or
V1N :::; V LC
mA
NOTE:
1. All values are maximum guaranteed values.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
MAX.
TYP'<')
SYMBOL
VOR
PARAMETER
TEST CONDITION
-
Vee lor Data Retenlion
ICCOR
Data Retention Current
tCOR(3)
Chip Deselect to Data Retention Time
t R(3)
Operation Recovery Time
IILlI (3)
Input Leakage Current
I
MIN.
MIL.
COM'l.
V 1N ~ V HC
2.0
-
-
-
-
-
10
10
15
15
600
150
900
225
-
a
CS;O:VHC
or:5
V LC
Vcc @
3.0V
2.0V
Vcc @
2.0V
3.0V
t Rc (2)
-
-
UNIT
V
-
p.A
ns
-
ns
2
p.A
NOTES:
1. TA = +2SoC.
2. t AC = Read Cycle Time.
3. This parameter is guaranteed but not tested.
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee
VO,,;:::2V
....t
OS
'CD
'i///M"
'
V:'\\\\\'
VD.
I
-Ej
SAD7198-Q05
'5V
..V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Relerence Levels
Output Relerence Levels
Output Load
GND t03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
DDUT
255n
480n
__
SRD7198-007
SA0719S-OOS
Figure 1. Output Load
'Including scope and jig
2-103
Figure 2. Output Load
(for
tCLZ1,21 tOLZ' t CHZ1 ,2t t OHZ'
low and I WHZ )
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7198S/IDT7198L CMOS STATIC RAMS 64K (16K x 4-BIT)
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vee = 5V ± 10%, All Temperature Ranges)
7198S85(2)
7198S30(5)
7198S25(1)
7198S45
7198S55
7198S70
7198S35
7198L85(2) UNITS
7198L25(1)
7198L30(5)
7198L55
7198L70
7198L35
7198L45
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE
t AC
Read Cycle Time
25
-
30
-
35
-
45
-
55
-
70
-
85
-
ns
tM
Address Access Time
-
25
-
30
-
35
-
45
-
55
-
70
-
85
ns
t ACS1,2
Chip Select-I, 2
Access Time( 3)
-
25
-
30
-
35
-
45
-
55
-
70
-
85
ns
tClZl,2(4)
Chip Select-I, 2 to
Output in Low Z
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to
Output Valid
-
15
-
20
-
25
-
30
-
35
-
45
-
55
ns
t olz (4)
Output Enable to
Output in Low Z
5
-
5
~~:0J:
5
-
5
-
5
-
5
-
5
-
ns
tCHZ1,2(4)
Chip Select-I, 2 to
Output in High Z
-
10
.J:~~3
-
15
-
15
-
20
-
25
-
30
ns
t oHz (4)
Output Disable to
Output in High Z
-
-
15
-
15
-
20
-
25
-
30
ns
tOH
Output Hold from
Address Change
5
5
-
5
-
5
-
5
-
5
-
ns
tpu (4 )
Chip Select to
Power Up Time
a
-
a
-
a
-
a
-
a
-
a
-
ns
t pD (4 )
Chip Deselect to
Power Down Time
30
-
35
-
45
-
55
-
70
-
85
ns
25
-
30
-
40
-
50
-
60
-
75
-
ns
25
-
30
-
35
-
50
-
60
-
75
-
ns
25
-
25
-
35
-
50
-
60
-
75
-
ns
WRITE CYCLE
twe
Write Cycle Time
tCW1,2
Chip Select to
End of Write (3)
tAW
Address Valid to
End of Write
tAS
Address Setup Time
twp
Write Pulse Width
-
:i:
-;~i~'4l
-"}'.
0
2l>;q. -
~
20
20
-
a
-
a
-
a
-
a
-
a
-
a
-
ns
25
-
25
-
35
50
-
60
-
75
-
ns
t WA1 , 2
Write Recovery Time
a
-
a
-
a
-
a
-
a
-
0
-
0
-
ns
t WHz (4)
Write Enable to
Output in High Z
-
7
-
10
-
10
-
15
-
25
-
30
-
40
ns
tDW
Data Valid to
End of Write
13
-
15
-
15
-
20
-
25
-
30
-
35
-
ns
tDH
Data Hold Time
a
0
-
a
-
a
-
0
5
-
5
5
-
5
-
ns
-
-
0
Output Active from
End afWrite
-
a
t ow (4)
-
5
5
NOTES:
1.
aoc to +70°C temperature range only.
2. -55D C to +125°C temperature range only.
3. Both chip selects must be active tow for the device to be selected.
4. This parameter guaranteed but not tested.
5. Preliminary data only for military devices.
2-104
5
ns
IDT7198S/IDT7198L CMOS STATIC RAMS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. W)
ADDRESS
DOUT - - -_ _ _ _ _ _ _ _ _ _ _ _- (
SRD7198-008
TIMING WAVEFORM OF READ CYCLE NO.
=1
2(1,2,4)
>---------,.c-----------<1="'I
ADD••S.
I:~-
10"=1
D= ______~~~-_=~-_=~-_=~Io_"~~=-~_-==_-=-~----~··_____________~--~SRD7198-009
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
SRD7198-010
NOTES:
1. WE is High lor Read Cycle.
2. Device is continuously selected, CSt = V,L, CS2 = V,L.
3. Address valid prior to or coincident with CSt and or CS 2 transition low.
4. OE'= V,L.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
2-105
II
IDT7198S/IDT7198L CMOS STATIC RAMS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(l)
~-----------------I~----------------~
~-------ICW
----------I
1--------------- 1. . ---------------+1
I-------Iw,''''----------i~
D,.
------7
SAD7198-006
Figure 1. Output Load
Figure 2. Output Load
(for 'CLZ1,2' t OLZ ' t CHZ1 ,2! 10HZ'
tow and t wHZ)
-Including scope and jig
AC TEST CONDITIONS
I nput Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto 3.0V
5ns
1.5V
1.5V
See Figs. 1 and 2
2-110
IDT71981/IDT71982 CMOS STATIC RAMS 64K (16K
AC ELECTRICAL CHARACTERISTICS
x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vee = 5V ± 10%, All Temperature Ranges)
7198112530 71981/2535 71981/2545 71981/2555 71981/2570 71981/2585(1)
71981/2L2S(6) 71981/2L30 71981/2L35 71981/2L45 71981/2L55 71981/2L70 71981/2L8S(I) UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
71981/2525(6)
SYMBOL
PARAMETER
READ CYCLE
t Re
Read Cycle Time
25
-
30
-
35
-
45
-
55
-
70
-
85
-
ns
tAA
Address Access Time
-
25
-
30
-
35
-
45
-
55
-
70
-
85
ns
t ACS1 ,2
Chip Select-I, 2
Access Ti me (2)
-
25
-
30
-
35
-
45
-
55
-
70
-
85
ns
t elzl ,2
Chip Select-I, 2 to
Output in Low l(3)
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to
Output Valid
-
15
-
20
-
25
-
30
-
35
-
45
-
55
ns
tOLZ
Output Enable to
Output in Low l(3)
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
t CHZ1 ,2
Chip Select-I. 2 to
Output in High l(3)
-
10
-
13
-
15
-
15
-
20
-
25
-
30
ns
tOHZ
Output Disable to
Output in High l(3)
-
15
~.
15
-
15
-
15
-
20
-
25
-
30
ns
tOH
Output Hold from
Address Change
5
-
'5
-
5
-
5
-
5
-
5
-
5
-
ns
tpu
Chip Select to Power
Up Time(3)
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
tpo
Chip Deselect to Power
Down Time (3 )
-
25
30
-
35
-
45
-
55
-
70
-
85
ns
r>"':
",'
WRITE CYCLE
i,'
twe
Write Cycle Time
20
25
-
30
-
40
-
50
-
60
-
75
-
ns
t CW1 . 2
Chip Select 10 End of
Write
-
20
-
25
-
30
-
35
-
50
-
60
-
75
-
ns
-
25
25
-
50
-
60
-
75
0
-
0
-
0
0
35
-
50
-
60
-
75
0
-
35
0
-
0
-
0
-
0
-
0
-
-
10
-
10
-
15
-
25
-
30
-
40
ns
-
20
-
25
-
30
-
35
-
ns
"
tAW
Address Valid to End
of Write
20
t AS
Address Setup Time
0," < ........
twp
Write Pulse Width
20' ,
t WR1 ,2
Write Recovery Time
~·O ~
tWHZ
Write Enable to Output
High l13. 5)
-
tow
Data Valid to End of
Write
13
-
15
-
15
-
"
7
0
25
0
25
ns
ns
ns
ns
tOH
Data Hold Time
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
tow
Output Active from End
of Writel3. 5)
5
-
5
-
5
-
5
-
5
-
5
-
5
-
ns
ttY
Data Valid to Output
Valid (4)
-
20
-
30
-
30
-
35
-
40
-
45
-
50
ns
tWY
Write Enable to Output
Valid( 4 )
-
20
-
30
-
30
-
35
-
40
-
45
-
50
ns
NOTES:
1, -55°C to +125°C temperature range only,
2, Both chip selects must be active low for the device to be selected.
3. This parameter guaranteed but not tested.
4. For IDT71981S/L only.
5. For IDT71982S/L only.
6. DoC to +70°C temperature range only.
2-111
I
IDT71981/1DT71982 CMOS STATIC RAMS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. W)
i-------tRc------i
ADDRESS __
~
________________
-J~
_____
i 4 - - - - - t A A - - -........
DATAOUT-------------~~~----------~~~
SRD71981-008
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
~I-----~
_ _ _- _ _
_IRC==1--
)
-'b~~?~
__'_t___
~
toH
_d,,.....
DATAOUT
SRD71981-009
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
-I
Vce Icc-----
SUPPLY
CURRENT
I
tt
I-tPD(61
PU (81
=L
IS8 ---...:...SRD71981-010
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS, = V1l • 05 2 = V1L.
3. Address valid prior to or coincident with CS,. and or Cs 2 transition low.
4. OE = V,L.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
6. This parameter is sampled and not 100% tested.
2-112
IDT71981/1DT71982 CMOS STATIC RAMS 64K (16K x 4-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1<1)
..o - - - - - - - I w c - - - - - - I
I~
ADDRESS
DATAIN
-------+----IJ'.---+--.lfloI~\,QoO'
DATAOUT
:t3Et1~3Et3~------------------SRD71981-011
TIMING WAVEFORM OF WRITE CYCLE NO.
2(1,6)
I-------Iwc-----~
ADDRESS
DATAIN
_____________
I
~~'I~~------JI~----
II
DATAOUy(10)
DATA UNDEFINED
t-
I I Y , t : _ - - - : -_ _
I
DATA VALID
DATAOUy(11)----D-AT.-A-U-N-D-E-F-IN-E-D---~ --------------{~
..
SRD71981..()12
2-113
IDT71981/1DT71982 CMOS STATIC RAMS 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 3(1.6)
twe
----,.
ADDRESS
\
_tWR1,2(3)
.I:;--tew-
\
\
\ \ \ \-,It
/ IIIIII
tAW
_twp(2)_
\".".\
tASf.-j
DATAIN
L
*
'I
DATAOUr(10)
lOW
I
IOH.1:=.
II
DATA VALID
_tw~
X
DATA UNDEFINED
DATA VALID
\
twHZ(4,9);
DATAOUr(11)
.1
DATA UNDEFINED
SRD719S1-013
NOTES:
1. WE must be high during all address transitions.
2. A write occurs during the overlap (t wp) of a low CS, and a low CS 2.
3. tWR is measured from the earlier of CS, or
CS 2 or WE going high to the end of write cycle.
4. During this period, liD pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the Cs, and or CS 2 'ow transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
6. DE is continuously low (OE = V1l).
7. DOUT is the same phase of write data of this write cycle.
8. If Cs 1 and Cs 2 are low during this period, 110 pins are in the output state. Then the data input signals of opposite phaseto the outputs must not be applied to them.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
10. For 10T71981 only.
11. For IOT71982 only.
TRUTH TABLE
CAPACITANCE
MODE
CS,
CS 2
WE
OE
OUTPUT
POWER
Standby
H
X
X
X
HighZ
Standby
Standby
X
H
X
X
HighZ
Standby
Read
L
L
H
L
DOUT
Active
Write(1)
L
L
L
L
D'N
Active
Write(1)
L
L
L
H
HighZ
Active
Write(2)
L
L
L
X
HighZ
Active
Read
L
L
H
H
HighZ
Active
(TA = +25°C, f = 1,OMHz)
PARAMETER(1)
CONDITIONS
TYp.
C 'N
Input Capacitance
5
pF
C OUT
Output Capacitance
=OV
VOUT =OV
7
pF
SYMBOL
Y'N
NOTES:
1. This parameter is sampled and not 100% tested.
NOTES:
1. For IOT71981 only.
2. For IOT719B2 only.
2-114
UNIT
OROER PART
NUMBER
IOT6116LA30P
SPEED
(n8)
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
ORDER PART
NUMBER
30
75
P24-1, P24-2
Com'l.
IOT6116SA450B
IOT6116LA300
SPEED
(n8)
Icc (MAX.)
(mA)
45
90
PACKAGE
TYPE
OPER.
TEMP.
024-1
Mil.
024-1
IOT6116SA45TB
024-2
IOT6116LA30T
024-2
IOT6116SA45LB
L28-1 , L32
IOT6116LA30L
L28-1 , L32
IOT6116SA45FB
IOT6116LA30F
F24
IOT6116LA55P
P24-1, P24-2
IOT6116LA550
IOT6116SA300
024-1
IOT6116LA55T
024-2
IOT6116SA30T
024-2
IOT6116LA55L
L28-1 , L32
IOT6116SA30L
L28-1 , L32
IOT6116LA55F
IOT6116SA30F
F24
IOT6116SA30P
IOT6116LA35P
80
35
75
P24-1, P24-2
Com'l.
IOT6116LA55LB
IOT6116LA55FB
IOT6116LA35L
L28-1, L32
IOT6116SA55P
IOT6116LA35F
F24
IOT6116SA550
Mil.
024-1
L28-1, L32
024-1
P24-1, P24-2
IOT6116SA55T
024-2
IOT6116SA55L
L28-1, L32
IOT6116LA35LB
L28-1, L32
IDT6116SA55F
IOT6116LA35FB
F24
P24-1, P24-2
L28-1, L32
024-1
IDT6116SA55LB
024-2
IOT6116SA55FB
IOT6116SA35L
L28-1, L32
IDT6116LA70P
IOT6116SA35F
F24
IOT6116LA700
024-1
Mil.
024-1
024-2
IOT6116SA35T
90
90
IDT6116SA55TB
IOT6116SA350
IOT6116SA350B
F24
IOT6116SA550B
Com'l.
75
P24-1, P24-2
IOT6116LA70T
024-2
IOT6116LA70L
L28-1 , L32
IOT6116SA35LB
L28-1 , L32
IOT6116LA70F
IOT6116SA35FB
F24
75
P24-1, P24-2
024-1
024-2
L28-1, L32
024-1
IOT6116LA70LB
IOT6116LA45T
024-2
IOT6116LA70FB
IOT6116LA45L
L28-1 , L32
IOT6116SA70P
IOT6116LA45F
F24
IDT6116SA700
Mil.
85
IOT6116LA70TB
IOT6116LA450
IOT6116LA450B
F24
IOT6116LA700B
Com'l.
P24-1, P24-2
IOT6116SA70T
024-2
IOT6116SA70L
L28-1 , L32
IOT6116LA45LB
L28-1, L32
IOT6116SA70F
IOT6116LA45FB
F24
IOT6116SA45P
80
P24-1, P24-2
F24
IDT6116SA700B
Com'l.
024-1
024-2
L28-1, L32
024-1
IDT6116SA70LB
IOT6116SA45T
024-2
IDT6116SA70FB
IOT6116SA45L
L28-1 , L32
IOT6116LA90P
IOT6116SA45F
F24
IOT6116LA900
2-115
90
IOT6116SA70TB
IOT6116SA450
Com'l.
024-1
024-2
024-1
Mil.
F24
80
IOT6116LA45TB
85
Com'l.
024-1
024-2
45
Mil.
F24
70
IOT6116SA35TB
IOT6116LA45P
Com'l.
024-1
024-2
80
Mil.
F24
80
IOT6116LA35TB
IOT6116SA35P
Com'l.
F24
85
024-2
024-2
024-1
P24-1, P24-2
IOT6116LA55TB
IOT6116LA35T
85
75
024-1
IOT6116LA550B
IOT6116LA350
IOT6116LA350B
F24
55
Mil.
F24
90
75
P24-1, P24-2
024-1
IOT6116LA90T
024-2
IOT6116LA90L
L28-1, L32
IOT6116LA90F
F24
Com'l.
ORDER PART
NUMBER
IDT6116LA90DB
SPEED
(ns)
Icc!MAX.)
(rnA)
90
85
PACKAGE
TYPE
OPER.
TEMP.
D24-1
Mil.
ORDER PART
NUMBER
IDT6167SA25P
SPEED
(ns)
Icc (MAX.)
(rnA)
25
90
PACKAGE
TYPE
OPER.
TEMP.
P20
Com' I.
IDT6116LA90TB
D24-2
IDT6167SA25D
D20
IDT6116LA90LB
L28-1, L32
IDT6167SA25L
L2Q-1
IDT6116LA90FB
F24
IDT6167SA25F
F20
IDT6167SA25DB
D20
IDT6167SA25LB
L2Q-1
I DT6116SA90P
80
IDT6116SA90D
P24-1, P24-2
Com'l.
D24-1
IDT6116SA90T
D24-2
IDT6116SA90L
L28-1, L32
IDT6167LA35P
IDT6116SA90F
F24
IDT6167LA35D
D20
IDT6167LA35L
L20-1
IDT6116SA90DB
90
D24-1
IDT6167SA25FB
Mil.
IDT6116SA90TB
D24-2
I DT6116SA90LB
L28-1, L32
IDT6167LA35DB
IDT6116SA90FB
F24
IDT6167LA35LB
IDT6116LA120DB
120
85
D24-1
F20
35
55
IDT6167LA35F
Mil.
P20
D20
IDT6167LA35FB
F20
IDT6167SA35P
IDT6116LA120LB
L28-1, L32
I DT6167SA35D
D20
L2Q-1
90
P20
F24
IDT6167SA35L
D24-1
IDT6167SA35F
F20
IDT6116SA120TB
D24-2
IDT6167SA35DB
D20
IDT6116SA120LB
L28-1, L32
IDT6167SA35LB
L2Q-1
90
IDT6116SA120FB
IDT6116LA150DB
F24
150
85
D24-1
IDT6167SA35FB
IDT6167LA45P
Mil. '
55
P20
D24-2
IDT6167LA45D
D20
IDT6116LA150LB
L28-1, L32
IDT6167LA45L
L2Q-1
IDT6116LA150FB
F24
IDT6167LA45F
90
D24-1
Mil.
D24-2
IDT6167LA45LB
IDT6116SA150LB
L28-1, L32
IDT6167LA45FB
IDT6116SA150FB
F24
IDT6167SA15P
15
90
P20
IDT6167SA15D
D20
IDT61,67SA15L
IDT6167SA15F
IDT6167LA20P
20
55
D20
P20
IDT6167SA45D
D20
IDT6167SA45L
L2Q-1
F20
L20-1
IDT6167SA45DB
D20
F20
IDT6167SA45LB
L2Q-1
Com'l.
IDT6167SA45FB
D20
IDT6167LA55P
IDT6167LA20L
L20-1
IDT6167LA55D
D20
L2Q-1
F20
IDT6167LA55L
P20
IDT8167LA55F
IDT6167SA20D
D20
IDT6167LA55DB
IDT6167SA20L
L20-1
IDT6167LA55LB
IDT6167SA20P
90
IDT6167SA20F
IDT6167LA25P
F20
25
55
P20
IDT6167LA25D
D20
IDT6167LA25L
IDT6167LA25F
IDT6167LA25DB
60
55
55
IDT6167SA55P
P20
D20
P20
L20-1
IDT6167SA55L
L20-1
F20
IDT6167SA55F
F20
IDT6167SA55DB
D20
IDT6167LA25LB
L2Q-1
IDT6167SA55LB
L2Q-1
IDT6167LA25FB
F20
IDT6167SA55FB
F20
2-116
Mil.
F20
90
D20
Mil.
Com' I.
L2Q-1
IDT6167SA55D
D20
Mil.
F20
60
IDT6167LA55FB
Com'l.
Com'l.
F20
IDT6167LA20D
IDT6167LA20F
Mil.
F20
90
IDT6167SA45F
P20
Com' I.
L2Q-1
IDT6167SA45P
Com' I.
Mil.
F20
60
IDT6167LA45DB
IDT6116SA150TB
Com'l.
F20
45
IDT6116LA150TB
IDT6116SA150DB
Mil.
L20-1
D24-2
IDT6116SA120DB
Com'l.
F20
60
IDT6116LA120TB
IDT6116LA 120FB
Mil.
Com'l.
Mil.
ORDER PART
NUMBER
IDT6167LA70DB
SPEED
(ns)
Icc (MAX.)
(mA)
70
60
IDT6167LA70LB
PACKAGE
TYPE
OPER.
TEMP.
D20
Mil.
ORDER PART
NUMBER
IDT6168SA35P
L2o-1
IDT6167LA70FB
F20
IDT6167SA70DB
90
D20
Mil.
P20
Com'l.
L2o-1
F20
IDT6168SA35LB
F20
100
D20
F20
IDT6167LA85LB
L2o-1
IDT6168LA45P
IDT6167LA85FB
F20
IDT6168LA45D
D20
L20-1
IDT6167SA85DB
D20
IDT6168LA45L
IDT6167SA85LB
L2o-1
IDT6168LA45F
IDT6167SA85FB
F20
I DT6167LA 1OODB
90
100
60
D20
45
70
P20
80
D20
IDT6167LA100LB
L20-1
F20
IDT6168SA45P
D20
IDT6168SA45D
D20
L2D-1
90
IDT6168LA45FB
IDT6167SA 1OOLB
L20-1
IDT6168SA45L
I DT6167SA1 OOFB
F20
IDT6168SA45F
F20
90
20
70
P20
IDT6168SA45LB
Com 'I.
P20
D20
D20
IDT6168LA20L
L2o-1
IDT6168LA55P
IDT6168LA20F
F20
IDT6168LA55D
D20
L20-1
IDT6168SA45FB
P20
I DT6168LA55L
IDT6168SA20D
D20
IDT6168LA55F
IDT6168SA20L
L20-1
IDT6168LA55DB
IDT6168SA20F
F20
IDT6168LA55LB
I DT6168LA25P
90
25
70
P20
F20
55
70
P20
D20
F20
D20
IDT6168SA55P
IDT6168LA25L
L2o-1
IDT6168SA55D
D20
IDT6168SA55L
L2o-1
F20
IDT6168LA25DB
80
D20
IDT6168LA25LB
L20-1
IDT6168SA55DB
IDT6168LA25FB
F20
IDT6168SA55LB
IDT6168SA25P
90
P20
Com'l.
D20
IDT6168LA70DB
IDT6168SA25L
L2o-1
IDT6168LA70LB
F20
IDT6168SA25DB
100
D20
L2o-1
IDT6168SA70LB
I DT6168SA25FB
F20
IDT6168SA70FB
IDT6168LA35P
35
70
P20
Com' I.
IDT6168LA85DB
IDT6168LA35D
D20
IDT6168LA85LB
I DT6168LA35L
L20-1
IDT6168LA85FB
IDT6168LA35F
F20
IDT6168SA85DB
IDT6168LA35DB
80
D20
IDT6168LA35LB
L2o-1
IDT6168LA35FB
F20
Mil.
2-117
D20
Mil.
F20
70
80
D20
Mil.
L2o-1
F20
IDT6168LA70FB
IDT6168SA25LB
Com' I.
L2o-1
IDT6168SA70DB
Mil.
P20
F20
100
IDT6168SA55FB
IDT6168SA25D
IDT6168SA25F
90
IDT6168SA55F
Mil.
Mil.
L2D-1
IDT6168LA25D
IDT6168LA25F
Com'l.
F20
80
I DT6168LA55FB
Com'l.
Mil.
L20-1
IDT6168LA20D
IDT6168SA20P
Com'l.
F20
100
IDT6168SA45DB
IDT6168LA20P
Mil.
L2o-1
IDT6168LA45LB
IDT6167LA100FB
IDT6167SA 1OODB
Com'l.
F20
IDT6168LA45DB
Mil.
Mil.
L20-1
IDT6168SA35FB
Mil.
OPER.
TEMP.
IDT6168SA35L
IDT6167SA70FB
D20
90
IDT6168SA35F
IDT6168SA35DB
60
35
PACKAGE
TYPE
D20
L2o-1
85
ICC (MAX.)
(mA)
IDT6168SA35D
IDT6167SA70LB
IDT6167LA85DB
SPEED
(ns)
100
D20
L2o-1
F20
85
80
D20
L2o-1
F20
100
D20
IDT6168SA85LB
L2o-1
IDT6168SA85FB
F20
Mil.
ORDER PART
NUMBER
IOT6168LA1000B
SPEED
(n8)
Icc (MAX.)
(mA)
100
80
IOT6168LA100LB
PACKAGE
TYPE
OPER.
TEMR
020
Mil.
ORDER PART
NUMBER
10T71257L55T
IOT6168LA100FB
100
Icc!MAX.)
(mA)
PACKAGE
TYPE
55
-
024-2
F20
1DT71257S55T
I Com'l.
020
IDT71257S55TB
L2Q-1
IOT6168SA100FB
F20
IOT71257L70T
~
70
-
024-2
1DT71257L70TB
-
028-1
10T71256L45T
028-2
10T71257L85TB
10T71256L45L
L32
10T71257S85TB
10T71256S45D
028-1
1DT71256S45T
028-2
IDT71258L35T
10T71256S45L
L32
10T71258S35T
10T71256L550
55
-
10T71256L55T
028-1
IOT71258L45T
028-1
IOT71256L55TB
028-2
IDT71256L55LB
L32
10T71256S550
028-1
10T71256S55T
028-2
10T71256S55L
L32
10T71256S550B
028-1
IOT71256S55TB
028-2
10T71256S55LB
L32
70
-
10T71256L70T
-
024-2
Mil.
35
-
024-2
Com'l.
45
-
024-2
--;:.w:-
IDT71258S45TB
IOT71258L55T
55
-
024-2
10T71258L55TB
Mil.
-
024-2
IOT71258L70TB
IOT71258L85TB
Com'l.
85
-
024-2
Mil.
55
120
P48
Com' I.
IOT71258S85TB
L32
IOT71256L700B
028-1
10T71256L70TB
028-2
Mil.
10T7130L55P
10T7130L55J
J52
IOT7130L55C
048-1
10T7130L55L
L48, L52
IDT71256L70LB
L32
IDT71256S700
028-1
10T71256S70T
028-2
1DT713OS55P
IOT71256S70L
L32
IOT7130S55J
J52
1DT7130S55C
048-1
Com'l.
IDT71256S700B
028-1
IOT71256S70TB
028-2
IOT7130S55L
IOT71256S70LB
L32
10T7130L70P
10T71256L850B
85
-
Mil.
028-1
Mil.
170
P48
L48, L52
70
120
IOT7130L7OJ
P48
IOT71256L85TB
028-2
IOT7130L70C
048-1
L32
IOT7130L70L
L48, L52
IOT71256S850B
028-1
IOT7130L70CB
10T71256S85TB
028-2
IDT7130L70LB
10T71256S85LB
L32
IDT7130S70P
180
35
-
024-2
Com'l.
IOT71257L45T
1DT71257L45TB
10T71257S45T
IDT71257S45TB
45
-
024-2
-
170
048-1
L48, L52
10T713OS70CB
IOT7130S70LB
2-118
Mil.
Com'l.
J52
1DT7130S70C
Mil.
Com'l.
P48
10T713OS70L
Com'l.
--;:.w:-
048-1
L48, L52
IOT713OS7OJ
IOT71257S35T
Com'l.
J52
10T71256L85LB
IDT71257L35T
Com'l.
~
~
IOT71258S70TB
Com'l.
Mil.
--;:.w:70
IOT71258S70T
028-1
Com'l.
Com'l.
IOT71258S55TB
IOT71258L70T
-
,---
IDT71258S55T
Com'l.
Com'l.
--;:.w:~
IOT71258S45T
Mil.
028-2
10T71256L70L
85
IOT71258L45TB
L32
10T71256L550B
1DT71256L700
Com'l.
028-2
10T71256L55L
Com'l.
~
IOT71257S70TB
Com'l.
Com'l.
~
I---
10T71257S70T
45
Com'l.
~
IOT6168SA100LB
10T71256L450
OPER.
TEMR
1DT71257L55TB
L2Q-1
IDT6168SA1000B
SPEED
(ns)
225
048-1
L48, L52
Mil.
--ORDER PART
NUMBER
IOT7130L90P
--
SPEED
(ns)
Icc (MAX.)
(rnA)
90
120
IOT7130L90J
PACKAGE
TYPE
OPER.
TEMP.
P48
Com 'I.
ORDER PART
NUMBER
IOT7132L90P
SPEED
(ns)
'cc!MAX.)
(rnA)
PACKAGE
TYPE
OPER.
TEMP.
90
120
P48
Com'l.
J52
10T7132L90J
10T7130L90C
048-1
10T7132L90C
048-1
10T7130L90L
L48, L52
10T7132L90L
L48, L52
IOT7130L90CB
150
10T7130L90LB
048-1
10T7132L90CB
Mil.
L48, L52
IOT7130S90P
170
10T7130S90J
P48
J52
150
10T7132L90LB
Com'l.
048-1
IOT7132S90P
170
P48
---_.-
J52
IOT7132S90J
10T7130S90C
048-1
IOT7132S90C
048-1
IOT7130S90L
L48, L52
IOT7132S90L
L48, L52
IOT7130S90CB
185
10T7130S90LB
IOT7130L 100P
048-1
100
120
10T7130L 100J
P48
185
10T7132L 100P
048-1
100
120
P48
J52
10T7132L 100J
10T7130L 100C
048-1
10T7132L100C
048-1
IOT7130L 100L
L48, L52
10T7132L100L
L48, L52
10T7130L 100CB
150
IOT7130L 100LB
048-1
IOT7130S100P
170
I OT7130S 100J
P48
150
10T7132L 100LB
Com'l.
048-1
10T7132S1OOP
170
P48
IOT7132S100J
IOT7130S100C
048-1
10T7132S1OOC
048-1
10T7130S1OOL
L48, L52
10T7132S1ooL
L48, L52
185
IDT7130S1ooLB
iOT7130L 120CB
120
150
I OT7130L 120L B
Mil.
048-1
iOT7132S1ooCB
IOT7132L 120CB
Mil.
185
IDT7130S120LB
55
120
IOT7132L55J
048-1
IOT7132S120CB
IDT7132S120LB
P48
185
Com'l.
IOT71322L45P
048-1
120
150
048-1
185
048-1
L48, L52
45
-
P48
10T71322L45C
10T7132L55C
048-1
10T71322L45L
L52
IDT7132L55L
L48, L52
10T71322S45P
P48
048-1
10T7132S55P
170
P48
IOT71322S45C
J52
10T71322S45L
10T7132S55C
048-1
10T71322L55P
10T7132S55L
L48, L52
IOT71322L55C
IOT7132L70P
70
120
P48
Com'l.
L52
55
-
IOT71322L55L
P48
~s:::1
10T71322L55CB
048-1
1DT7132L70C
048-1
10T71322L55LB
L52
L48, L52
180
I 0T7132L 70LB
IDT7132S70P
048-1
Mil.
L48, L52
170
IOT7132S70J
P48
10T71322S55P
P48
10T71322S55C
048-1
IOT71322S55L
Com'l.
J52
048-1
10T71322S55LB
L52
IOT7132S70C
048-1
IOT71322L70P
L48, L52
IOT71322L70C
10T7132S70CB
IOT7132S70LB
225
048-1
10T71322L70L
Mil.
L48, L52
2-119
Mil.
Com'l.
L52
IOT71322S55CB
1DT7132S70L
Com' I.
L52
J52
IOT7132L70L
Com'l.
048-1
10T7132L70J
IDT7132L70CB
Mil.
L48, L52
J52
1DT7132S55J
Mil.
L48, L52
10T7132L 120LB
L48, L52
Com'l.
J52
IOT7132S100LB
L48, L52
10T7130S120CB
10T7132L55P
048-1
L48, L52
Mil.
L48, L52
J52
10T7130S100CB
Com'l.
J52
10T7132L 100CB
Mil.
L48, L52
Mil.
L48, L52
10T7132S90LB
Com'l.
Com'l.
J52
10T7132S90CB
Mil.
L48, L52
Mil.
L48, L52
70
-
P48
Mil.
Com'l.
048-1
L52
IOT71322L70CB
048-1
IOT71322L70LB
L52
Mil.
ORDER PART
NUMBER
10T71322S70P
SPEED
(ns)
70
Icc (MAX.)
(rnA)
-
OPER.
TEMP.
P48
Com·1.
ORDER PART
NUMBER
10T7134L45P
048-1
1DT71322S70C
10T71322S70L
048-1
10T71322S70LB
-
P48
45
IcclMAX.)
(rnA)
-
PACKAGE
TYPE
OPER.
TEMP.
P48
Com'l.
048-1
10T7134L45L
L48
Mil.
10T7134S45P
P48
IOT7134S45C
048-1
Com'l.
IOT7134S45L
L52
90
SPEED
(ns)
IOT7134L45C
L52
IOT71322S70CB
10T71322L90P
PACKAGE
TYPE
IOT71322L90C
048-1
10T7134L55P
IOT71322L90L
L52
10T7134L55C
-
P48
048-1
IOT71322L90LB
L52
10T71322S90P
P48
IOT71322S90C
048-1
IOT7134S55P
P48
10T71322S90L
L52
IOT7134S55C
048-1
048-1
IOT71322S90LB
L52
10T71322L 100CB
100
-
048-1
10T7134L55L
Com'l.
Mil.
048-1
10T7134L55LB
L48
048-1
IOT7134S55LB
L48
10T71322L 100LB
L52
10T7134L70P
048-1
10T7134L70C
10T71322S100LB
L52
10T7134L70L
70
-
P68
Com'l.
70
-
P48
048-1
IOT7134L70LB
L48
068
IOT7134S70P
P48
L68
10T7134S70C
048-1
IOT7133S70P
P68
IOT7134S70L
10T7133S70XC
068
10T7134S70CB
048-1
10T7133S70L
L68
IOT7134S70LB
L48
90
-
P68
10T7133L90L
L68
10T7133L90XCB
068
IOT7133L90LB
L68
IOT7133S90P
P68
10T7133S90XC
068
IOT7133S90L
L68
10T7133S90XCB
068
10T7133S90LB
L68
I OT7133L 100P
100
-
IOT7133L 100XC
10T7134L90P
P68
IOT7133L 100L
L68
068
IOT7133L 100LB
L68
10T7133S100P
P68
10T7133S100XC
068
I 0T7133S 1OOL
L68
10T7133S100XCB
068
10T7133S100LB
Com'l.
-
068
10T7133L 120LB
L68
IOT7133S120XCB
068
IOT7133S120LB
L68
-
Com'l.
Mil.
Com'l.
P48
048-1
10T7134L90LB
L48
IOT7134S90P
P48
IOT7134S90C
048-1
048-1
IOT7134S90LB
L48
100
-
048-1
IOT7134L l00LB
L48
I OT7134S 1OOC B
048-1
IOT7134S100LB
L48
10T71341
Com'l.
Mil.
Com'l.
Mil.
Mil.
Consult Factory
55
120
P48
Mil.
10T7140L55J
10T7140L55C
048-1
Mil.
10T7140L55L
L48, L52
2-120
Mil.
L48
10T7134S90CB
I 0T7140L55 P
Com'l.
L48
10T7134L90CB
IOT7134L 100CB
Mil.
048-1
10T7134S90L
Mil.
L68
120
90
10T7134L90L
Mil.
Com'l.
L48
IOT7134L90C
068
IOT7133L 100XCB
10T7133L 120XCB
Com' I.
068
Mil.
L48
IOT7134L70CB
IOT7133L70XC
IOT7133L90P
Com'l.
048-1
10T7133L70L
IDT7133L90XC
Mil.
L48
10T7134S55CB
10T71322S100CB
10T7133L70P
L48
10T7134L55CB
IOT7134S55L
Mil.
Com'l.
048-1
IOT71322L90CB
10T71322S90CB
Mil.
L48
55
J52
Com'l.
ORDER PART
NUMBER
10T7140S55P
SPEED
(ns)
'cc(MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
55
170
P48
Com' I.
10T7140S55J
ORDER PART
NUMBER
IDT7142S55P
SPEED
(ns)
'cc(MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
55
170
P48
Com'l.
J52
I DT7142S55J
10T7140S55C
048-1
I DT7142S55C
D48-1
IOT7140S55L
L48, L52
IDT7142S55L
L48, L52
I OT7140L 70P
70
120
10T7140L70J
P48
Com'l.
IOT7142L70P
J52
70
120
P48
J52
IDT7142L70J
I 0T7140L 70C
048-1
IDT7142L70C
048-1
IOT7140L70L
L48, L52
IDT7142L70L
L48, L52
I 0T7140L 70CB
180
I 0T7140L 70LB
048-1
Mil.
IOT7140S70P
170
P48
10T7142L70CB
180
IDT7142L70LB
L48, L52
Com'l.
048-1
170
10T7142S70P
P48
IOT7140S70C
D48-1
IDT7142S70C
048-1
I DT7140S70L
L48, L52
IDT7142S70L
L48, L52
225
IDT7140S70LB
IDT7140L90P
D48-1
Mil.
90
120
I DT7140L90J
P48
225
IOT7142S70CB
IDT7142S70LB
L48, L52
Com'l.
10T7142L90P
D48-1
90
120
P48
IDT7142L90J
1DT7140L90C
D48-1
1DT7142L90C
048-1
IOT7140L90L
L48, L52
IDT7142L90L
L48, L52
150
IDT7140L90LB
048-1
Mil.
L48, L52
IOT7140S90P
170
P48
1DT7142L90CB
150
048-1
170
IDT7142S90P
P48
IDT7140S90C
048-1
10T7142S90C
048-1
10T7140S90L
L48, L52
10T7142S90L
L48, L52
185
10T7140S90LB
10T7140L 100P
048-1
Mil.
100
120
10T7140L100J
P48
185
IDT7142S90CB
10T7142S90LB
L48, L52
Com'l.
10T7142L 100P
048-1
100
120
P48
IDT7142L 100J
10T7140L100C
D48-1
IDT7142L1ooC
048-1
1DT7140L100L
L48, L52
IDT7142L100L
L48, L52
150
D48-1
Mil.
10T7140S100P
170
1DT7140S100J
P48
Com'l.
150
IDT7142L 100CB
048-1
I DT7142S 1OOP
170
P48
IDT7142S100J
1DT7140S100C
048-1
IOT7142S100C
048-1
IOT714OS1ooL
L48, L52
IDT7142S100L
L48, L52
IOT7140S1ooCB
185
IDT7140L120CB
120
150
1DT7140L120LB
IDT7140S120CB
IOT7142L55J
Mil.
D48-1
Mil.
185
55
120
IDT7142S100CB
IDT7142L 120CB
D48-1
IDT7142S120CB
1DT7142S120LB
P48
J52
IOT7142L55C
048-1
10T7142L55L
L48, L52
185
Com' I.
IDT7143L70P
048-1
120
150
048-1
Mil.
L48, L52
185
048-1
L48, L52
70
-
P68
IDT7143L70XC
068
IDT7143L70L
L68
2-121
Mil.
L48, L52
IOT7142L 120LB
L48, L52
Com' I.
J52
IDT7142S100LB
L48, L52
1DT7140S120LB
IDT7142L55P
D48-1
L48, L52
Mil.
L48, L52
J52
10T7140S100LB
Com' I.
J52
IDT7142L 100LB
L48, L52
IDT7140L 100LB
Mil.
L48, L52
J52
10T7140L 100CB
Com'l.
J52
I DT7142S90J
10T7140S90CB
Mil.
L48, L52
IDT7142L90LB
Com'l.
Com'l.
J52
J52
IDT7140S90J
Mil.
L48, L52
J52
IDT7140L90CB
Com'l.
J52
IOT7142S70J
IDT7140S70CB
Mil.
L48, L52
J52
10T714OS70J
Com'l.
J52
Com'!.
ORDER PART
NUMBER
10T7143S70P
SPEED
Icc (MAX.)
(na)
(mA)
70
-
IOT7143S70XC
OPER.
TEMP.
P68
Com' I.
ORDER PART
NUMBER
10T7164L45P
068
IOT7143S70L
IOT7143L90P
PACKAGE
TYPE
L68
90
-
P6B
SO
10T7164L45TB
10T7143L90XCB
068
10T7143L90LB
L6B
10T7143S90P
P6B
Com' I.
Com'l.
L32
90
028-1
L32
P28
IOT7164S450
028-1
028-2
068
10T7164S45T
L68
IOT7164S45L
10T7143S90XCB
068
10T7143S90LB
L6B
100
IOT7164S45TB
028-1
10T7164S45LB
L32
10T7164L55P
IOT7143L100L
L68
IOT7164L55D
028-1
IDT7164L55T
028-2
068
L68
10T7143S100P
P68
10T7143S1OOXC
068
10T7143S100L
L68
IOT7143S1ooXCB
068
10T7143S100LB
L68
IOT7143L 120XCB
120
-
068
Mil.
55
80
IOT7164L55L
Com'l.
90
L32
IOT7164S55P
P28
10T7164S550
028-1
10T7164S55T
028-2
L68
10T7164S55L
10T7143S120XCB
068
IOT7164S550B
10T7143S120LB
L68
10T7164S55TB
30
80
P28
IDT7164L 70P
Com'l.
028-1
SO
P28
10T7164L700
028-1
10T7164L30T
028-2
1DT7164L70T
028-2
10T7164L30L
L32
IOT7164L70L
P28
10T7164L700B
10T7164S300
028-1
1DT7164L70TB
10T7164S30T
028-2
10T7164L70LB
L32
10T7164S30L
L32
10T7164S70P
P28
IOT7164S700
028-1
028-2
IOT7164L35P
35
80
P28
Com' I.
10T7164L350
028-1
IOT7164S70T
IOT7164L35T
028-2
1DT7164S70L
10T7164L35L
L32
IOT7164L350B
90
028-1
028-2
1DT7164S70LB
10T7164L35LB
L32
10T7164L850B
IOT7164S35P
P28
IOT7164S350
028-1
IOT7164L85LB
IOT7164S35T
028-2
10T7164S850B
10T7164S35L
1DT7164S350B
L32
100
028-1
10T7164S35TB
028-2
IOT7164S35LB
L32
Mil.
2-122
Mil.
Com'l.
L32
100
028-1
Mil.
028-2
L32
85
90
028-1
028-2
10T7164L85TB
Com' I.
028-1
028-2
10T7164S70TB
IOT7164L35TB
Com'l.
L32
90
IOT7164S700B
Mil.
Mil.
L32
70
028-1
90
Com'l.
028-2
IOT7164L300
10T7164S30P
Mil.
L32
100
10T7164S55LB
10T7164L30P
028-1
10T7164L55LB
10T7143L 120LS
Com'l.
028-2
IOT7164L55TB
Mil.
P28
L32
10T7164L550B
Mil.
Mil.
028-2
068
10T7143L 100XCB
Com'l.
L32
IOT7164S450B
10T7143L 100XC
10T7143L100LB
Mil.
028-2
10T7164L45LB
10T7143S90XC
Com'l.
P28
IDT7164S45P
10T7143S90L
Mil.
OPER.
TEMP.
028-2
L6B
Mil.
PACKAGE
TYPE
10T7164L45T
10T7143L90L
P68
45
10T7164L45L
Com' I.
IOT7164L450B
-
(mA)
028-1
068
100
Icc (MAX.)
(na)
10T7164L450
10T7143L90XC
IOT7143L100P
SPEED
L32
100
028-1
IDT7164S85TB
028-2
10T7164S85LB
L32
Mil.
ORDER PART
NUMBER
IDT7164L 100DB
SPEED
(ns)
Icc (MAX.)
(mA)
100
90
IDT7164L 100TB
IDT7164L 100LB
PACKAGE
TYPE
OPER.
TEMP.
D28-1
Mil.
ORDER PART
NUMBER
IDT7165L45P
80
OPER.
TEMP.
P28
Com' I.
D28-1
D28-2
IDT7165L45T
IDT7165L45L
IDT7164S 100TB
D28-2
IDT7165L45DB
IDT7164S100LB
L32
IDT7165L45TB
IDT7164L 120DB
45
PACKAGE
TYPE
IDT7165L45D
L32
100
IcclMAX.)
(mA)
D28-2
D28-1
IDT7164S100DB
SPEED
(ns)
IDT7165L45LB
L32
IDT7165S45P
P28
IDT7164L 120LB
L32
I DT7165S45D
D28-1
D28-2
IDT7164S120DB
D28-1
IDT7165S45T
IDT7164S120TB
D28-2
I DT7165S45L
IDT7164S120LB
L32
IDT7164L 150DB
100
150
90
D28-1
D28-1
D28-2
IDT7164L 150LB
L32
IDT7165L55P
D28-1
IDT7165L55D
D28-1
IDT7164S150TB
D28-2
IDT7165L55T
D28-2
IDT7164S150LB
L32
IDT7165L55L
IDT7164L2ooDB
100
200
90
D28-1
IDT7165S45LB
Mil.
L32
55
80
P28
90
D28-1
IDT7165L55TB
L32
IDT7165L55LB
L32
D28-1
IDT7165S55P
P28
IDT7164S200TB
D28-2
IDT7165S55D
D28-1
IDT7164S200LB
L32
I DT7165S55T
D28-2
IDT7165S55L
IDT7165L30P
30
80
P28
Com'l.
100
D28-1
D28-1
IDT7165S55TB
D28-2
IDT7165L30T
D28-2
IDT7165S55LB
L32
IDT7165L30L
L32
P28
I DT71681 LA20P
IDT7165S30D
D28-1
IDT71681 LA20C
I DT7165S30T
D28-2
I DT71681 LA20L
IDT7165S30L
L32
I DT71681SA20P
IDT7165L35P
90
35
80
P28
Com'l.
D28-1
I DT71681SA20L
IDT7165L35T
D28-2
IDT71681 LA25P
IDT7165L35L
L32
IDT71681LA25C
IDT7165L35DB
90
D28-1
Mil.
D28-2
IDT71681LA25CB
IDT7165L35LB
L32
IDT71681 LA25LB
IDT7165S35P
P28
D28-1
I DT7165S35T
D28-2
IDT7165S35L
L32
IDT7165S35DB
100
D28-1
70
Com'l.
P20
D24-2
L28-1
25
70
P20
Com' I.
D24-2
L28-1
80
D24-2
Mil.
L28-1
90
P20
Com'l.
D24-2
I DT71681SA25C
IDT71681SA25L
L28-1
IDT71681SA25CB
100
IDT71681SA25LB
D24-2
Mil.
L28-1
IDT7165S35TB
D28-2
IDT71681 LA35P
IDT7165S35LB
L32
IDT71681 LA35C
D24-2
IDT71681 LA35L
L28-1
2-123
Com'l.
L28-1
90
IDT71681SA25P
Mil.
P20
Mil.
D24-2
IDT71681LA25L
IDT7165L35TB
IDT7165S35D
20
IDT71681SA20C
I DT7165L35D
Com'l.
L32
IDT7165S55DB
IDT7165L30D
IDT7165S30P
Mil.
D28-2
D28-2
IDT7164L2ooLB
100
Com'l.
L32
IDT7165L55DB
IDT7164L2ooTB
IDT7164S200DB
Mil.
D28-2
IDT7165S45TB
IDT7164L 150TB
IDT7164S150DB
Coml
L32
100
IDT7165S45DB
Mil.
Mil.
D28-2
D28-2
90
Mil.
D28-1
IDT7164L 120TB
120
D28-1
L32
90
35
70
P20
Com' I.
PI
ORDER PART
NUMBER
SPEED
(ns)
Icc!MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
ORDER PART
NUMBER
SPEED
(ns)
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
1DT71681 LA35CB
35
80
D24-2
Mil.
IDT71682LA25CB
25
80
D24-2
Mil.
IDT71681 LA35LB
IDT71681SA35P
90
I DT71681 SA35C
100
IDT71681SA35LB
45
70
IDT71681LA45L
D24-2
90
IDT716B1 SA45C
P20
I DT71681 SA45L
100
IDT716B1SA45LB
D24-2
55
70
I DT716B1 LA55C
P20
IDT71682LA45P
BO
IDT71681LA55LB
D24-2
90
I DT71681 SA55C
P20
100
IDT71681SA55LB
D24-2
70
80
IDT71681 SA70CB
100
I DT71681SA70LB
85
IDT716B2LA55P
Mil.
L2B-1
I DT71682LA55C
D24-2
IDT716B2LA55L
L28-1
IDT716B2LA55CB
D24-2
L28-1
1DT71682SA55P
100
D24-2
1DT716B2SA55C
BO
D24-2
I DT71681 SA85LB
IDT71681 LA100LB
Mil.
IDT71681SA1OOCB
100
IDT716B2LA70CB
L28-1
1DT716B2LA70LB
20
70
P20
Com'l.
D24-2
IDT716B2LA85CB
IDT71682LA20L
L28-1
I DT716B2LA85LB
IDT716B2SA20P
P20
IDT71682SA85CB
IDT716B2SA20C
D24-2
IDT71682SA85LB
I DT71682SA20L
L28-1
IDT71682LA1ooCB
I DT71682LA25P
90
25
70
P20
90
IDT716B2LA25C
D24-2
IDT716B2SA1OOCB
I DT716B2LA25L
L2B-1
IDT716B2SA1ooLB
2-124
D24-2
Mil.
P20
Com'l.
D24-2
Mil.
P20
Com' I.
D24-2
L28-1
100
D24-2
Mil.
L28-1
70
80
D24-2
Mil.
L28-1
100
D24-2
80
D24-2
L28-1
85
Mil.
L28-1
100
D24-2
80
D24-2
L28-1
100
IDT71682LA100LB
Com'l.
Com' I.
L28-1
I DT716B2SA70LB
I DT71682LA20C
P20
L2B-1
80
1DT716B2SA70CB
IDT71682LA20P
70
I DT716B2SA55LB
D24-2
Mil.
D24-2
IDT716B2SA55CB
L28-1
IDT71681SA1ooLB
55
I DT716B2SA55L
L28-1
100
D24-2
L28-1
IDT716B2LA55LB
Mil.
Com'l.
L28-1
100
IDT71682SA45LB
BO
I DT71681 LA85LB
IDT71681SA85CB
D24-2
P20
D24-2
I DT71682SA45L
L28-1
IDT71681LA70LB
90
1DT71682SA45CB
Mil.
Mil.
L28-1
IDT716B2SA45C
L2B-1
IDT71681SA55CB
D24-2
L28-1
80
IDT716B2SA45P
Com'l.
Com'l.
D24-2
IDT71682LA45LB
D24-2
I DT71681SA55L
70
IDT71682LA45L
L28-1
IDT71681SA55P
45
IDT716B2LA45CB
Mil.
P20
L28-1
IDT71682LA45C
L28-1
IDT71681 LA55CB
Mil.
L28-1
100
IDT716B2SA35LB
Com'\.
D24-2
D24-2
IDT716B2SA35CB
D24-2
IDT71681 LA55L
90
IDT71682SA35L
L28-1
Com'l.
L2B-1
IDT716B2SA35C
Mil.
P20
L28-1
BO
IDT716B2SA35P
Com'l.
L28-1
IDT71681SA45CB
70
IDT716B2LA35LB
D24-2
Mil.
D24-2
IDT71682LA35CB
L28-1
IDT71681 SA45P
35
IDT716B2LA35L
Mil.
D24-2
L28-1
IDT716B2LA35C
L28-1
80
IDT71681 LA45LB
IDT716B1LA100CB
IDT716B2SA25LB
IDT71682LA35P
Com·I.
L2B-1
100
IDT716B2SA25CB
Com'l.
P20
D24-2
IDT716B2SA25L
Mil.
D24-2
IDT71681 LA45CB
IDT71681 LA85CB
P20
90
IDT71682SA25C
L28-1
I DT71681 LA45C
IDT716B1 LA70CB
D24-2
L2B-1
IDT716B2SA25P
Com'l.
L28-1
IDT71681SA35CB
IDT71681 LA55P
P20
D24-2
IDT716B1SA35L
IDT71681LA45P
I DT716B2LA25LB
L28-1
L28-1
100
D24-2
L28-1
Mil.
ORDER PART
NUMBER
IDT7174L35P
SPEED
(ns)
Icc (MAX.)
(mA)
35
100
PACII.~GE
TYPE
OPER.
TEMP.
P28
Coml
ORDER PART
NUMBER
IDT7187S30P
IDT7174L35D
D28-1
I DT7187S30C
IDT7174L35T
D28-2
I DT7187S30L
IDT7174L35L
L32
IDT7174L35DB
115
D28-1
D28-2
IDT7187L35P
L32
I DT7187L35C
P28
Coml
D28-1
IDT7187L35CB
I DT7174S35T
D28-2
I DT7187L35LB
L32
IDT7174S35DB
125
D28-1
I DT7174S35TB
D28-2
IDT7174S35LB
L32
IDT7174L45P
45
100
P28
I DT7187L45P
I DT7187L45C
L32
115
IDT7174L45TB
D28-1
IDT7174L45LB
P28
D28-1
I DT7187S45L
D28-2
IDT7187S45CB
I DT7174S45L
L32
IDT7187S45LB
125
IDT7174S45LB
IDT7174L55DB
D28-1
Mil.
1DT7187L55P
D28-2
IDT7174S45TB
115
IDT7174L55TB
D28-1
IDT7174L55LB
L32
IDT7187S55P
IDT7187S55C
I DT7174S55TB
D28-2
I DT7187S55L
IDT7174S55LB
L32
125
70
25
70
IDT7187L25C
IDT7187L25L
85
IDT7187L25LB
90
IDT7187S25C
90
D22
P22
55
70
105
IDT7187S25LB
D22
30
70
1DT7187L30C
90
P22
IDT7187L30L
D22
70
70
L22, L28-2
IDT7187L85LB
2-125
P22
Com'l.
D22
Mil.
P22
Com'l.
D22
Mil.
P22
Com'l.
L22, L28-2
85
D22
Mil.
L22, L28-2
90
P22
Com' I.
D22
L22, L28-2
105
D22
Mil.
L22, L28-2
85
70
P22
Com'l.
D22
L22, L28-2
IDT7187L85L
IDT7187L85CB
Mil.
Mil.
D22
1DT7187L85C
L22, L28-2
85
D22
L22, L28-2
IDT7187S70LB
IDT7187L85P
Com'l.
L22, L28-2
105
IDT7187S70L
Com'l.
P22
D22
IDT7187S70CB
D22
Mil.
L22, L28-2
IDT7187S70C
L22, L28-2
D22
L22, L28-2
85
IDT7187S70P
Mil.
Com'l.
D22
IDT7187L70LB
L22, L28-2
IDT7187S25CB
P22
L22, L28-2
IDT7187L70CB
Com'l.
Mil.
L22, L28-2
105
IDT7187L70L
Mil.
D22
D22
IDT7187L70C
D22
I DT7187S25L
IDT7187L30LB
IDT7187L70P
L22, L28-2
IDT7187S25P
IDT7187L30CB
Com'l.
L22, L28-2
IDT7187L25CB
IDT7187L30P
P22
Coml
L22, L28-2
I DT7187S55CB
D22
P22
L22, L28-2
85
I DT7187S55LB
IDT7187L25P
Mil.
D22
1DT7187L55LB
D28-1
IDT7174S55DB
45
IDT7187L55CB
D28-2
D22
L22, L28-2
IDT7187L55L
Mil.
Com'l.
L22, L28-2
105
IDT7187L55C
L32
55
P22
D22
IDT7187S45P
IDT7174S45T
IDT7174S45DB
90
IDT7187S45C
1DT7174S45 D
Mil.
L22, L28-2
IDT7187L45LB
Com'l.
D22
L22, L28-2
85
IDT7187L45L
L32
110
Com'l.
D22
I DT7187L45CB
Mil.
D28-2
IDT7174S45P
70
IDT7187S35LB
D28-1
IDT7174L45L
35
I DT7187S35CB
D28-2
P22
L22, L28-2
I DT7187S35L
IDT7174L45D
OPER.
TEMP.
L22, L28-2
105
I DT7187S35C
Com'l.
PACKAGE
TYPE
D22
IDT7187S35P
Mil.
IDT7174L45T
1DT7174L45DB
90
IDT7187L35L
IDT7174S35D
IDT7174S35L
30
I DT7187S30LB
Mil.
IDT7174L35LB
110
Icc (MAX.)
(mA)
IDT7187S30CB
IDT7174L35TB
IDT7174S35P
SPEED
(ns)
85
D22
L22, L28-2
Mil.
ORDER PART
NUMBER
10T7187S85P
SPEED
(ns)
Icc (MAX.)
(rnA)
85
90
10T7187S85C
PACKAGE
TYPE
OPER.
TEMP.
P22
Com' I.
ORDER PART
NUMBER
IOT7198L30P
IOT7187S85L
L22, L28-2
105
IDT7187S85LB
022
Icc (MAX.)
(rnA)
30
85
IOT7198L30C
022
10T7187S85CB
SPEED
(ns)
IOT7198L30L
25
85
IOT7188L25C
IOT7188S25P
100
1DT7188S25C
10T7188L30P
30
85
10T7188L30C
P22
Com'l.
10T7198S30L
P22
IOT7198S30CB
022
IOT7198S30LB
P22
Com·1.
10T7188L30CB
95
022
Mil.
100
P22
Com'l.
1DT7188S30CB
35
022
Mil.
IOT7198S35P
P22
Com'l.
IOT7198S35C
IOT7188L35C
95
022
Mil.
IOT7198S35CB
1DT7188S35P
100
P22
Com'l.
IOT7198S35LB
022
Mil.
10T7198L45C
P22
Com' I.
IDT7198L45L
1DT7188L45P
110
45
85
IOT7188L45C
95
10T7188S45P
100
1DT7188S45C
022
Mil.
P22
Com'l.
10T7188S45CB
55
022
Mil.
85
P22
Com'l.
10T7188L55C
95
022
Mil.
1DT7198L55P
P22
Com' I.
IDT7198L55C
IOT7188S55C
1DT7188L70P
70
022
Mil.
IOT7198L55CB
85
P22
Com'l.
1DT7198L55LB
10T7188L70C
95
10T7188S70P
100
10T7188S70C
Mil.
85
10T7188S85CB
P22
Com' I.
Mil.
IOT7198S55LB
Mil.
IOT7198L70P
95
022
022
85
P24-2
100
25
1DT7198L25C
IDT7198L25L
IOT7198L70CB
024-2
10T7198L70LB
L28-2
IDT7198S70P
P24-2
IOT7198S70C
10T7198S25C
024-2
IDT7198S70L
10T7198S25L
L28-2
IOT7198S70CB
10T7198S25P
100
10T7198S70LB
2-126
Mil.
P24-2
Com'l.
024-2
Mil.
P24-2
Com'l.
L28-2
110
024-2
Mil.
L28-2
55
85
P24-2
Com'l.
024-2
L28-2
95
024-2
Mil.
L28-2
100
P24-2
Com'l.
024-2
L28-2
110
024-2
Mil.
L28-2
70
85
IOT7198L70C
Com'l.
024-2
024-2
P24-2
Com'l.
024-2
IOT7198L70L
10T7198L25P
Com'l.
L28-2
IOT7198S55L
022
P24-2
L28-2
95
IOT7198S55CB
110
110
85
10T7198S55C
022
IOT7188S70CB
1DT7188L85CB
022
Mil.
024-2
1DT7198S55P
022
IDT7188L70CB
45
IOT7198L55L
022
110
024-2
L28-2
1DT7198S45LB
100
Com'l.
L28-2
110
IDT7198S45CB
10T7188S55P
P24-2
024-2
IDT7198S45L
10T7188L55CB
10T7188S55CB
100
IOT7198S45P
022
Mil.
L28-2
IOT7198S45C
110
024-2
L28-2
95
1DT7198L45LB
022
Com'l.
024-2
IOT7198L45CB
022
10T7188L45CB
IOT7188L55P
IOT7198L45P
022
IOT7188S35CB
85
IOT7198S35L
022
10T7188L35CB
10T7188S35C
35
IOT7198L35LB
85
P24-2
L28-2
IOT7198L35CB
110
Mil.
L28-2
110
IOT7198L35L
022
024-2
024-2
10T7198L35C
IDT7188S30P
10T7188L35P
IOT7198L35P
022
10T7188S30C
100
IOT7198S3OC
022
Com'l.
L28-2
10T7198S30P
10T7188L25P
P24-2
L28-2
95
IOT7198L30LB
L22, L28-2
OPER.
TEMP.
024-2
1DT7198L30CB
Mil.
PACKAGE
TYPE
L28-2
95
024-2
Mil.
L28-2
100
P24-2
Com'l.
024-2
L28-2
110
024-2
L28-2
Mil.
ORDER PART
NUMBER
10T7198L85CB
SPEED
(ns)
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
85
95
024-2
Mil.
IOT7198L85LB
10T7198S85CB
110
10T7198S85LB
I 0T71981 L25C
25
85
I OT71981 L25L
I 0T71981 S25C
100
I 0T71981 S25L
IOT71981L30C
30
85
I 0T71981 L30L
IOT71981L30CB
95
100
IDT71981 S30L
110
I 0T71981 S30LB
35
85
10T71982L25C
10T71982L25L
028-2
10T71982S25C
L28-2
IOT71982S25L
028-2
028-2
028-2
028-2
028-2
028-2
100
028-2
I 0T71981 S35L
Com'l.
10T71982L30C
IOT71981S35CB
110
028-2
45
85
028-2
95
10T71981L45LB
028-2
Com'l.
I OT71981 S45C
100
028-2
10T71981S45CB
110
028-2
55
85
028-2
95
I OT71981 L55LB
028-2
Com'l.
I OT71981 S55C
100
028-2
10T71982L35C
110
I OT71981 S55LB
028-2
70
85
028-2
95
028-2
IDT71982L45C
100
028-2
028-2
028-2
85
028-2
95
100
110
35
85
028-2
100
028-2
110
45
85
95
100
110
55
85
95
100
10T71982S70CB
IOT71982S70LB
2-127
028-2
Mil.
028-2
Com'l.
028-2
Mil.
028-2
Com'l.
028-2
Mil.
028-2
Com'l.
L28-2
110
028-2
Mil.
L28-2
70
85
028-2
Com'l.
L28-2
95
028-2
Mil.
L28-2
100
IOT71982S70L
Mil.
Com'l.
L28-2
IDT71982L70LB
L28-2
028-2
L28-2
I OT71982L 70L
IOT71982S70C
Mil.
L28-2
IOT71982S55LB
Com'l.
028-2
L28-2
10T71982S55CB
10T71982L7OCB
Com'l.
L28-2
IOT71982S55L
Mil.
Mil.
L28-2
IDT71982S55C
10T71982L70C
Com'l.
L28-2
10T71982L55CB
Com'l.
Mil.
L28-2
IOT71982L55LB
Mil.
028-2
95
10T71982L55L
Com'l.
028-2
L28-2
IOT71982S45CB
Mil.
Com'l.
L28-2
10T71982S45LB
IOT71982L55C
028-2
L28-2
IOT71982S45C
Com'l.
Mil.
L28-2
10T71982S45L
Mil.
028-2
L28-2
IOT71982L45LB
Com'l.
Com'l.
L28-2
10T71982L45CB
L28-2
110
100
IDT71982L45L
Mil.
Com'l.
L28-2
30
IOT71982S35CB
Com'l.
028-2
L28-2
IOT71982S35LB
L28-2
10T71981S70L
85
10T71982S35L
L28-2
IDT71981L70LB
25
IDT71982S35C
Mil.
028-2
L28-2
IOT71982L35LB
Com'l.
L28-2
10T71981 L70L
110
10T71982L35CB
Mil.
L28-2
10T71981S55CB
Mil.
L28-2
10T71982L35L
L28-2
10T71981S55L
028-2
10T71982S30LB
L28-2
10T71981L55CB
95
IOT71982S30CB
Mil.
L28-2
I OT71981 L55L
85
10T71982S30L
L28-2
1DT71981S45LB
OPER.
TEMP.
10T71982S30C
L28-2
10T71981S45L
PACKAGE
TYPE
10T71982L30LB
L28-2
10T71981L45CB
ICC (MAX.)
(mA)
10T71982L30CB
Mil.
L28-2
10T71981 L45L
SPEED
(ns)
10T71982L30L
L28-2
10T71981S35LB
IOT71981S70CB
Com'l.
L28-2
L28-2
I OT71981S35C
IDT71981S70LB
028-2
95
10T71981L35LB
I OT71981S70C
I OT71981 S85LB
L28-2
10T71981L35CB
10T71981L70CB
10T71981S85CB
L28-2
L28-2
IOT71981L35L
10T71981L70C
024-2
L28-2
I OT71981 S30CB
I OT71981 L55C
10T71981 L85LB
L28-2
10T71981 S30C
IOT71981L45C
10T71981 L8SCB
L28-2
L28-2
10T71981L30LB
10T71981 L35C
ORDER PART
NUMBER
028-2
Com'l.
L28-2
110
028-2
L28-2
Mil.
II
ORDER PART
NUMBER
1DT71982L85CB
SPEED
(ns)
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
85
95
028-2
Mil.
10T71982L85LB
IOT71982S85CB
IOT71982S85LB
L28-2
110
028-2
L28-2
2-128
Integrated
Device
Technology
MICROSLICE™
MICROSLICE PRODUCTS
TABLE OF CONTENTS
CONTENTS
PAGE
MICROSLICE™ (Bit-Slice Microprocessors)
IDT39C01 C/D/E
4-Bit Microprocessor Slice ...........................•................•.••.... 3-1
IDT39C02A
Carry Lookahead 'Generator ................................•.•...............
IDT39C03A1B
4-Bit Microprocessor Slipe , ..•................................................
IDT39C09A1B
4-Bit Sequencer ........•..•.••..••.......•..................................
IDT39C10B/C
12-Bit Sequencer ......•.•••••.....•.....•......................••...........
IDT39C11A1B
4-Bit Sequencer ..........................•.•......•..•...........•.•...•....
IDT39C203/A
4-Bit Microprocessor Slice ................................................... .
IDT39C60
16-Bit Cascadeable E.D.C. . ..........•........................................
IDT39C705A/B
16x4 Register File Extension ............................................•.....
IDT39C707/A
16x4 Register File Extension ..•••.........................••..................
IDT49C25
Microcycle Length Controller •.........................•••..........•••.......
IDT49C401lA
16-Bit Microprocessor Slice .................................•...........•.....
IDT49C402/A
16-Bit Microprocessor Slice .................................................. .
IDT49C403/A
16-Bit Microprocessor Slice •.•.••........•......................••.•.•........
IDT49C404
32-Bit Microprocessor Slice ...............•....•...................•..•.......
IDT49C410/A
16-Bit Sequencer ...•......................................••........•..••...
IDT49C460/A
32-Bit Cascadeable E.D.C .......•.............•............•..................
Ordering Information ................................................................................
3-12
3-15
3-47
3-61
3-47
3-71
3-73
3-99
3-99
3-101
3-103
3-113
3-124
3-126
3-128
3-138
3-157
MICROSLICETM PRODUCT
FEATURES:
DESCRIPTION:
• Low-power
-Icc {max.}
Military - 35mA
Commercial - 30mA
The IDT39COI Cs are high-speed, cascadable ALUs which can
be used to implement CPUs, peripheral controllers and programmable microprocessors. The IDT39C01's microinstruction flexibility allows for easy emulation of most digital computers.
This extremely low-power yet high-speed ALU consists of a
16-word by 4-bit dual-port RAM, a high-speed ALU, and the
required shifting, decoding and multiplexing logic. It is expandable in 4-bit increments, contains a flag output along with threestate data outputs, and can easily use either a ripple carry or full
lookahead carry. The nine-bit microinstruction word is organized
into three groups of three bits each and selects the ALU destination register, ALU source operands and the ALU function.
The IDT39COIC is fabricated using CEMOS'·, a single poly,
double metal CMOS technology deSigned for high-performance
and high-reliability.
The IDT39COIC is a pin-compatible, performance-enhanced,
functional replacement for all versions of the 2901.
• Fast
-IDT39COIC - meets 2901C speeds
-IDT39COID - 20% speed upgrade
-IDT39COI E - 40% speed upgrade
• Eight-function ALU
-Performs addition, two subtraction operations and five
logic functions on two source operands
• Expandable
-Longer word lengths achieved through cascading any
number of IDT39COls
• Four status flags
-Carry, overflow, negative and zero
• Pin compatible and functionally equivalent to the 2901 A,B,C
• Military product available 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
RAMo
CLOCK~~~~~b=~~='
BDATA'N
READ ADDRESS
READIWRITE ADDRESS
A ADDRESS
16 ADDRESSABLE
REGISTERS
B ADDRESS
DIRECT DATA'N _ _...........
g
CARRY IN
P
B-FUNCTION ALU
Cn+4
F3 (SIGN)
OVERFLOW
F = 0000
OUTPUT ENABLE
DATAOUT
IDT39C01C-001
MICROSLICE and CEMOS are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986 Integrated Device Technology, Inc.
3-1
JUNE 1986
Printed
In
U.S.A.
MILITARV AND COMMERCIAL TEMPERATURE RANGES
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
OE
V3
V2
V,
Vo
A3
A2
A,
AO
16
18
17
RAM3
RAMo
Vee
p-
OVR
Cn +4
G
F3
GND
Cn
14
15
13
Do
D,
D2
D3
00
F~O
10
h
12
CP
03
BO
B,
B2
B3
DIP
TOP VIEW
~ .. ~~~egl.:;:N"':::O<
NC
Ia
17
RAM3
RAMo
Vee
P
OVR
2...+4
G
F3
GND
Cn
14
15
13
F~O
10
h
12
CP
NC
FLATPACK
(Consult Factory)
OIllIllIllIllOCCCCZ
NWQCoJ~ .... o
0
I»O ....
IOT39C01C-002
LCC
TOP VIEW
IDT39C01C-003
PIN DESCRIPTIONS
PIN NAME
I/O
Ao-A3
I
Four address inputs to the register file which selects one register and displays its contents through the A-port.
DESCRIPTION
Bo-B3
I
Four address inputs to the register file which selects one of the registers in the file, the contents of which is
displayed through the B-port. It also selects the location into which new data can be written when the clock
goes LOW.
10-1.
I
Nine instruction control lines which determine what data source will be applied to the ALU 10• 1• 20 what function
the ALU will perform 13. 4. 50 and what data is to be deposited in the Q Register or the register file 1.,7, ..
0 0-0 3
I
Four-bit direct data inputs which are the ALU data source for entering external data into the device. Do is the
LSB.
VO-V3
0
Four three-state output lines which, when enabled, display either the four outputs of the ALU or the data on
the A-port of the register stack. This is determined by the destination code 1•. 7..'
F3
0
Most significant ALU output bit (sign-bit).
F~O
0
Open drain output which goes HIGH if the Fo-F3 ALU outputs are all LOW. This indicates that the result of an
ALU operation is zero (positive logic).
Cn
I
Carry-in to the internal ALU.
C n+4
0
Carry-out of the internal ALU.
Q3
RAM3
I/O
Bidirectional lines controlled by 16.7..' Both are three-state output drivers connected to the TTL-compatible
CMOS inputs. When the destination code on 1.,7.. indicates an up shift, the three-state outputs are enabled
and the MSB of the Q Register is available on the Q3 pin and the MSB of the ALU output is available on the
RAM3 pin. When the destination code indicates a down shift, the pins are the data inputs to the MSB of the
Q Register and the MSB of the RAM.
Qo
RAMo
I/O
Both bidirectional lines function identically to Q 3 and RAM3 lines except they are the LSB of the Q Register
and RAM.
OE
I
Output enable which, when pulled HIGH, the V outputs are OFF (high impedance). When pulled LOW, the V
outputs are enabled.
G,P
0
Carry generate and carry propagate output of the ALU. These are used to perform a carry-Iookahead
operation.
OVR
0
Overflow. This pin is logically the Exclusive-OR of the carry-in and carry-out of the MSB of the ALU. At the
most significant end of the word, this pin indicates that the result of an arithmetic two's complement operation
has overflowed into the sign-bit.
CP
I
Clock input. LOW-to-HIGH clock transitions will change the Q Register and the register file outputs. Clock
LOW time is internally the write enable time for the 16x4 RAM which compromises the master latches of the
register file. While the clock is LOW, the slave latches on the RAM outputs are closed, storing the data previously on the RAM outputs. Synchronous MASTER-SLAVE operation of the register file is achieved
by this.
3-2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
DEVICE ARCHITECTURE:
The IDT39C01 CMOS bit-slice microprocessor is configured
four bits wide and is cascadable to any numberof bits (4,8,12,16,
etc.). Key elements which make up this four-bit-slice microprocessor are: (1) the register file (16x4 dual-port RAM) with
shifter, (2) ALU, and (3) 0 Register and shifter.
REGISTER FILE-RAM data is read from the A-port as
controlled by the 4-bit A address field input. Data, as defined by
the B address field input, can be simultaneously read from the
B-port of the RAM. This same code can be appl ied to the A select
and B select field with the identical data appearing at both the
RAM A-port and B-port outputs simultaneously. New data is
written into the file (word) defined by the B address field of the
RAM when activated by the RAM write enable. The RAM data
input field is driven by a 3-input multiplexer that is used to shift
the ALU output data (F). It is capable of shifting the data up one
position, down one position, or no shift at all. The other inputs to
the multiplexer are from the RAM 3 and RAMo 1/0 pins. For a shift
up operation, the RAM3 output buffer is enabled and the RAMo
multiplexer input is enabled. During a shift down operation the
RAMo output buffer is enabled and the RAM3 multiplexer input is
enabled. Four-bit latches hold the RAM data while the clock is
LOW with the A-port output and B-port output each driving
separate latches. The data to be written into the RAM is applied
from the ALU F output.
ALU-The ALU can perform three binary arithmetic and five
logic operations on the two 4-bit input words Sand R. The S input
field is driven from a 3-input multiplexer and the R input field is
driven from a 2-input multiplexer with both having an inhibit
capability. Both multiplexers are controlled by the 10 1, 12 inputs.
This multiplexer configuration enables the user to s~le~t various
pairs of the A, B, D, 0, and "0" inputs as source operands to the
ALU. Microinstruction inputs (13.14.15) are used to select the ALU
function. This high-speed ALU also incorporates a carry-in (C n)
input, carry propagate (P) output, carry generate (<3) output and
carry-out (C n+4) all aimed at accelerating arithmetic operations
by the use of carry-Iookahead logic. The overflow output pin
(OVR) will be HIGH when arithmetic operations exceed the two's
complement number range. The ALU data outputs (Fo. F,. F2. F3)
are routed to the RAM 0 Register inputs and the Y outputs under
control of the 16.17. Iscontrol signal inputs. The MSB of the ALU is
output as F3 so the user can examine the sign-bit without enabling the three-state outputs. An open drain output, F=O, is HIGH
when Fo= F, = F2 = F3 = Oso thatthe user can determine when the
ALU output is zero by wire-ORing these outputs together.
Q REGISTER-The 0 Register is a separate 4-bit file intended
for multiplication and division routines and can also be used as
an accumulator or holding register for other types of applications. It is driven from a 3-input multiplexer. In the no-shift mode,
the multiplexer enters the ALU data into the 0 Register. In either
the shift-up or shift-down mode, the multiplexer selects the 0
Register data appropriately shifted up or down. The 0 shifter has
two ports, 0 0 and 03, which operate comparably to the RAM
shifter. They are controlled by the 16 17 Is inputs.
The clock input of the IDT39C01 c;ntrols the RAM, 0 Register
and A and B data latches. When enabled, the data is clocked into
the 0 Registeron the LOW-to-HIGH transition. When the clock is
HIGH, the A and B latches are open and pass data that is present
at the RAM outputs. When the clock is LOW, the latches are
closed and retain the last data entered. When the clock is LOW
and RAM EN is enabled, new data will be written into the RAM file
defined by the B address field.
ALU SOURCE OPERAND CONTROL
ALU FUNCTION CONTROL
MICROCODE
MNEMONIC
AQ
AB
ZQ
ZB
ZA
DA
DQ
DZ
MICROCODE
ALU SOURCE
OPERANDS
12
I,
I.
OCTAL
CODE
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
R
S
A
A
0
0
0
D
D
D
Q
B
Q
B
A
A
Q
0
MNEMONIC
ADD
SUBR
SUBS
OR
AND
NOTAS
EXOR
EXNOR
3-3
I.
I.
13
OCTAL
CODE
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
ALU
FUNCTION
SYMBOL
R Plus S
S Minus R
R Minus S
ROR S
RAND S
RAND S
REX-OR S
REX-NOR S
R+S
S-R
R-S
R VS
RIIS
RIIS
RIIS
RIIS
IDT39C01C/D/E
FOUR~BIT
CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ALU DESTINATION CONTROL
RAM
FUNCTION
MICROCODE
MNEMONIC
I,
17
Q REGISTER
FUNCTION
I.
OCTAL
CODE
SHIFT
LOAD
SHIFT
LOAD
Y
OUTPUT
Q
RAM
SHIFTER
SHIFTER
RAMo
RAM3
Qo
Q3
QREG
L
L
L
0
X
NONE
NONE
F-Q
F
X
X
X
X
NOP
L
L
H
1
X
NONE
X
NONE
F
X
X
X
X
RAM A
L
H
L
2
NONE
F-B
X
NONE
A
X
X
X
X
RAMF
L
H
H
3
NONE
F-B
X
NONE
F
X
X
X
X
RAMQO
H
L
L
4
DOWN
F/2-B
DOWN
Q/2-0
F
Fa
IN3
Qo
IN3
RAMO
H
L
H
5
DOWN
F/2- B
X
NONE
F
Fa
IN3
Qo
X
RAMQU
H
H
L
6
UP
2F-B
UP
2Q-Q
F
INa
F3
INa
Q3
RAMU
H
H
H
7
UP
2F-B
X
NONE
F
INa
F3
X
Q3
x = Don't Care. Electrically, the shift pin is a TTL input internally connected to a three-state output which is in the high-impedance st.l1lte.
B = Registe, Addressed by B Inputs.
UP is toward MSB; DOWN is toward LSB.
SOURCE OPERAND AND ALU FUNCTION MATRIX
12,1,0 OCTAL
OCTAL
15,0,3
ALU
FUNCTION
0
1
2
3
4
5
6
7
ALU SOURCE
A,a
A,B
0,0
O,B
O,A
D,A
D,a
D,O
A+O
A+B
0
B
A
O+A
O+Q
0
0
Cn = L
R PluaS
Cn = H
A+Q+1
A+B+1
Q+1
B+1
A+1
o +A+ 1
o +Q + 1
0+1
Q-A-1
B-A-1
Q-1
B-1
A-1
A - 0-1
Q - 0-1
-0 -1
1
Cn = L
S Minus R
Cn = H
Q-A
B-A
Q
B
A
A-O
Q-O
-D
A- Q-1
A- B-1
-Q -1
-B -1
-A-1
0- A-1
o -Q-1
0-1
2
Cn=L
R Minus S
Cn = H
A-Q
A-B
-Q
-B
-A
O-A
O-Q
0
3
RORS
AVQ
AVB
Q
B
A
OVA
OVQ
0
4
RANDS
AAQ
AAB
0
0
0
OAA
OAQ
0
5
RANDS
AAQ
AAB
Q
B
A
OAA
OAQ
0
6
REX-OR S
AVQ
AVB
Q
B
A
OVA
OVQ
0
7
R EX-NORS
AVQ
AVB
Q
B
A
OVA
OVQ
0
+ = PLUS; - = MINUS; A = AND; v = EX-OR; V = OR
3-4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
ALU LOGIC MODE FUNCTIONS
OCTAL
GROUP
1....3.12,1,0
4
4
4
4
ALU ARITHMETIC MODE FUNCTIONS
AND
A 1'10
AI'IB
DI'IA
DI'IO
3 0
3 1
3 5
3 6
OA
AVO
AVB
DVA
DVO
6 0
6 1
6 5
6 6
EX-OA
AVO
AVB
DVA
DVO
7
7
7
7
0
1
5
6
EX-NOA
AVO
AVB
DVA
DVO
7
7
7
7
2
3
4
7
INVEAT
6
6
6
6
2
3
4
7
PASS
0
B
A
D
3
3
3
3
2
3
4
7
PASS
0
B
A
D
4
4
4
4
2
3
"ZEAO"
0
0
0
0
5
5
5
5
0
1
5
6
MASK
AIIO
AIIB
OIlA
OliO
0
1
5
6
15,,,3. 12,,,0
FUNCTION
GROUP
FUNCTION
0 0
0 1
0 5
0 6
ADD
A+O
A+B
D+A
D+O
ADD
plus one
A+O+ 1
A+B+1
D +A+ 1
D+0+1
0 2
0 3
0 4
0 7
PASS
0
B
A
D
Increment
0+ 1
B+1
A+1
D+1
Decrement
0-1
B-1
A-1
D-1
PASS
0
B
A
D
1's Compo
-0 -1
-B -1
-A -1
-D -1
2's Compo
(Negate)
-0
-B
-A
-D
Subtract
(1's Comp.)
o -A-1
B - A-1
A- D-1
O-D -1
A-0-1
A - B-1
D - A-1
D -0-1
Subtract
(2's Comp.)
O-A
B-A
A-D
O-D
A-O
A-B
D-A
D-O
2
3
4
7
2 2
2 3
2 4
1 7
1
1
1
1
2
2
2
2
8
A
0
Cn = H
GROUP
1
1
1
2
0
4
7
Cn = L
OCTAL
FUNCTION
0
1
5
6
0
1
5
6
DEFINITIONS
Po=Ao+S o
P, = A, + S,
P2 = A2 + S2
P, = A, + S,
Go = AoSo
G, = A,S,
G 2 = A,82
G, =A,S,
C, = G, + P,G 2 + P,P 2G, + P,P 2P,G O + P 3P2P,P OC n
C 3 = G 2 + P2G, + P2P,G O + P2P,PoCn
+ = OA
LOGIC FUNCTIONS FOR
G, P, C n+4t AND OVR
I
1....3
0
FUNCTION
P
G
A+S
P3P2P,PO
G 3 + P3G 2 + P3P2G, + P3P2P,G O
1
S-A
2
A-S
3
AVS
LOW
P3P2P,P O
4
AilS
LOW
G 3 + G 2 + G, + Go
5
AilS
LOW
6
AVS
7
AVS
I
Cn + 4
C,
L
OVR
I
C 3VC,
Same as A + S equations, but substitute A; for A; in definitions
Same as A + S equations, but substitute S; for S; in definitions
I
I
P3P2P,P O + C n
G 3 + G 2 + G, + Go + C n
I
I
P3P2P,P O + C n
G 3 + G 2 + G, + Go + C n
Same as All S equations, but substitute A; for A; in definitions
Same as A I7S equations, but substitute A; for A; in definitions
G 3 + G 2 + G, + Go
G 3 + P,G 2 + P3P2G, + P,P 2P,P O
NOTES:
I
,. + = OR
2. [1'2 + G2P, + G2G,PO + G2G,G oC nlV[P3 + G3P2 + G3G2P, + G3G2G,PO + G3G2G,G oC nl
3-5
G a + PaG~ + P,P 2G,
+ P3P2P,P O (Go + ~n)
I
See Note 2
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
VALUE
UNIT
-0.5(3) to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
-55 to +125
°C
TBIAS
Temperature
Under Bias
-65 to +135
°C
TSTG
Storage
Temperature
-65 to +150
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
PT
Power Dissipation (2)
1.0
W
lOUT
DC Output Current
into Outputs
30
mA
AMBIENT
TEMPERATURE
GND
Vee
-55°C to +125°C
OV
5.0V±10%
O°C to +70°C
OV
5.0V±5%
Commercial
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections 01 this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. PT maximum can only be achieved by excessive IOl or 'OH'
3. V ,L Min. = -3.0V for pulse width less than 20ns.
DC ELECTRICAL CHARACTERISTICS
TA =O·C to +70"C
TA = -55°C to +12S·C
VLe =+O.2V
VHe = Vee - O.2V
SYMBOL
Vee =+S.OV ± S%
Vee = +S.OV ± 10%
PARAMETER
I'H
Vee = Max.
Y,N = Vee
I'L
Input Low Current
(All Inputs)
Vee = Max.
Y'N = GND
VOL
Output High Voltage
Output Low Voltage
Max. =+S.2SV (Commercial)
Max. = +S.SOV (Military)
TEST CONDITIONS
Output Short Circuit Current
(All Inputs)
VOH
Min. = +4.7SV
Min. = +4.S0V
Vee = Min.
10H = -1.0mA (MIL.)
Y,N = V,H = or V,L
10H
Vee =Min.
10L
Y,N =V,H =or V'L
10L
= -1.6mA (COM'L.)
= 16mA (MIL.)
= 20mA (COM'L.)
MIN.
TYP'(31
MAX.
UNITS
-
0.1
5
/,A
-
-0.1
-5
/'A
2.4
4.3
-
4.3
-
V
2.4
-
0.3
0.5
-
0.3
0.5
2.0
-
-
V
-
0.8
V
V
V,H
Input High Voltage
(1)
V'L
Input Low Voltage
(1)
loz
Output Leakage Current
Vee = Max.
VOUT = HIGH Z
-40
-
40
/'A
Output Short Circuit Current
Vee = Max.
VOUT = OV(2)
-30
-
-130
mA
los
NOTES:
1. These input levels provide ze'ro noise Immunity and should only be static tested in a noise-free environment.
2. Not more than one output should be shorted at a time. Duration of the short circuit test shall not exceed one second.
3. Vee = +5.0V@TA+25°e.
3-6
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
VCC = +5.0V ± 5%
Vcc = +5.0V ± 10%
SYMBOL
PARAMETER
MIN.
TEST CONDITIONS
ICCOH
Quiescent Power Supply Current
CP = H (CMOS Inputs)
Vcc = Max.
VHC $ V1N • V1N :::; VLC
fcp= 0, CP = H
ICCOl
Quiescent Power Supply Current
CP = L (CMOS Inputs)
VHC ::; V1N • V1N ::; VLC
ICCT
Quiescent Input Power Supply(4)
Current (per Input @ TTL High)
Vcc = Max., Y'N = 3.4V, fcp = 0
ICCD
Dynamic Power Supply Current
Vcc= Max.
VHC <; Y'N' Y'N <; VlC
Outputs Open, OE = L
TYp.131
MAX.
UNITS
-
-
-
mA
-
-
-
mA
-
-
-
Input
-
-
COM'L.
-
-
-
-
Vcc = Max.
fcp= 0, CP = L
MIL.
Vcc = Max.,
Outputs Open, OE = L
CP = 50% Duty cycle
VHC <; Y,N' Y'N <; VlC
IDT39C01C
fcp= 10MHz
MIL.
-
COM'L.
-
IDT39C01 D
fcp = 15MHz
MIL
-
-
-
COM'L.
-
-
-
IDT39C01E
fcp = 17.5MHz
MIL.
-
-
-
COM'L.
-
-
-
IDT39C01C
fcp= 10MHz
MIL.
-
COM'L.
-
35
30
IDT39C01D
fcp = 15MHz
MIL.
-
-
40
COM'L.
-
-
35
IDT39C01E
fcp = 17.5MHz
MIL.
-
-
45
COM'L.
-
-
40
Total Power Supply Current(5)
Icc
Max. = +5.25V (Commercial)
Max. = +5.50V (Military)
Min. = +4.75V
Min. = +4.50V
TA = O°C to +70°C
TA = -55°C to +125°C
VLC = +0.2V
VHC = VCC - 0.2V
Vcc = Max.,
Outputs Open, OE = L
C P = 50% Duty cycle
Y'N = 3.4V, Y'N = 0
-
mAl
mAl
MHz
mA
NOTES:
'44. ICCQT is derived by measuring the total current with all the inputs tied tagetherat 3.4V, subtracting I CCQH ' then dividing by the total number of inputs.
5. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (ateither CMOS orTTL input levels). For all conditions, the Total Supply Current can
be calculated by using the following equation:
Icc
= I CCOH (CD H) + ICCOl (1
- CD Hi + leCT (NT x D H) + ICCD (f cp)
CD H :::: Clock duty cycle high period.
D H :::: Data duty cycle TTL high period (V'N = 3.4V).
NT::: Number of dynamic inputs driven at TTL levels.
fcp = Clock Input Frequency.
3-7
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CYCLE TIME ANP CLOCK CHARACTERISTICS
IDT39C01C
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
The tables" below specify the guarante!3d performance of the
IDT39C01 C over the -55·C to +125·C and OOC to +70·C temperature ranges. Vee is specified at 5V ± 10%. All times are in
nanoseconds and are measured between the 1.5V signal level.
The input switch between OV and 3V with signallransition rates of
1V per nanosecond. All outputs have maximum DC current
loads.
COMBINATIONAL PROPAGATION DELAYS(1) (C l
Maximum Clock Frequency to
s~ift
Q (50% duty qycle, 1=432 or 632)
MIL.
COM'L.
UNITS
32
31
ns
31
32
MHz
Mini'l'um Clock LOW Time
15
15
ns
Minimum Clock HIGH Time
15
15
ns
Minimum Clock Period
32
31
ns
= 50pF)
TO OUTPUT
Y
FROM INPUT
Fa
~IL.
MIL. COM'L.
G,P
C n+4
F=O
48
40
48
0
37
30
37
Cn
25
22
25
22
21
20
-
-
28
25
10• 1• 2
40
35
40
35
40
35
44
37
44
37
13,4,5
40
35
40
35
40
35
40
35
40
38
40
35
16• 7,8
A Bypass
ALU (1=2XX)
29
25
-
-
-"
-
-
-
-
-
40
35
-
-
-
-
-
-
-
-
-
--.r
40
35
O.
Oa
UNIT
COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. ~IL. COM'L. MIL. COM'L.
40
48
40
48
40
40
48
40
44
37
48
-
A,B Address
Clock
RAM.
RAM a
OVR
40
30
37
35
30
40
34
35
40
40
30
40
35
35
30
-
28
25
-
40
35
30
37
25
22
40
35
37
38
40
-
ns
.ns
n~
40
35
-
-
~s
29
26
29
26
ns
-
-
-
-
-
ns
35
40
35
33
28
ns
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
I
\
CP:
SET-UPTIME
BEFORE H-L
INPUT
HOLD TIME
AFTER H-L
MIL.
COM'L.
MIL.
A,B Source Address
15
15
2
B Destination Address
15
15
0
_(1)
-
Cn
-
-
10,1.2
-
13,4,5
COM'L.
1(3)
HOLD TIME
AFTERL-H
SET-UPTIME
BEFqREL-H
COM'L.
MIL.
30, 15+TPWL (4)
UNIT
MIL.
COM'L.
2
1
2
1
ns
25
0
0
ns
Do not change (2)
ns
-
20
20
0
9
ns
-
-
-
30
30
0
0
ns
-
-
-
-
30
30
0
ns
16,7,8
10
10
0
0
0
RAM O,,.QO,3
-
-
0
0
ns
-
25
Do not change (2)
-
-
12
12
ns
OUTPUT ENABLE/DISABLE TIMES
(C L = 5pF, measured to 0.5V change of VOUT in nanoseconds)
INPUT
MIL.
OE
Y
DISABLE
ENABLE
OUTPUT
25
"I COM'L.
I 23
MIL.
25
I
I
COM'L
23
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during t~e entire clock LOW time ~void erroneou~ operation.
3. Source addresses must be stable prior to the H-L transition to allow timeto access the source data before the latches close. The A address may then be changed. The
B address could be chang~d if it is not a destination; i.e., if dl4ta Is not being writte~ back into the RAM. Normally A a~d B are not changed during the clock ~OWtlme.
to
4. The setwup time prior to the clock I:--H transition is to allow time for data to be accessed, passed through the ALU, and returnttd to the RAM. It includes aU the ti~e from
stable A and 8 addresses to the clopk L-H transition, regardless of when the ~-L transition QCc~rs.
3-8
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C01D
AC ELECTRICAL CHARACTERISTICS
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
MIL.
COM'L.
UNITS
27
23
ns
o (50% duty cycle, 1=432 or 632)
37
43
MHz
Minimum Clock LOW Time
13
11
ns
Minimum Clock HIGH Time
13
11
ns
Minimum Clock Period
27
23
ns
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
The tables below specify the guaranteed performance of the
IDT39C01D over the -55°C to +125°C and O°C to +70°C temperature ranges. Vee is specified at 5V ± 10%. All times are in
nanoseconds and are measured between the 1.5V signal level.
The input switch between OV and 3V with signal transition rates of
1V per nanosecond. All outputs have maximum DC current
loads.
Maximum Clock Frequency to shift
COMBINATIONAL PROPAGATION DELAYS(1) (CL = 50pF)
TO OUTPUT
Y
FROM INPUT
F3
G,P
Cn+4
F=O
Qo
Q3
RAMo
RAM3
OVR
UNIT
MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
-
ns
-
ns
-
ns
21
ns
-
-
ns
20
19
ns
A,B Address
33
30
33
30
33
30
33
28
33
30
33
30
33
30
-
D
24
21
23
20
23
20
21
20
25
24
24
21
25
22
Cn
18
17
17
16
14
14
-
-
19
18
17
16
19
18
10,1,2
28
26
27
25
26
24
28
24
29
25
27
24
27
25
13,4,5
27
26
27
24
26
24
26
24
27
26
26
24
27
26
-
16• 7• 8
A Bypass
ALU (1=2XX)
18
16
-
-
-
-
-
-
21
21
21
24
-
-
-
-
-
-
-
26
-
-
-
-
-
-
Clock~
27
24
26
23
26
23
25
23
27
24
26
24
27
24
ns
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
I
\
CP:
SET-UPTIME
BEFOREH-L
INPUT
HOLD TIME
AFTER H-L
MIL.
COM'L.
MIL.
COM'L.
A,B Source Address
11
10
0
0 (3 )
B Destination Address
11
10
D
_(1)
-
Cn
-
-
10•1•2
-
-
13•4.5
-
-
16.7.8
7
7
RAM o.3,OO.3
-
-
SET-UPTIME
BEFOREL-H
MIL.
COM'L.
24,
21,
11+TPWL(4) 10+TPWL(4)
COM'L.
2
1
ns
2
1
ns
16
16
0
0
ns
-
13
13
0
0
ns
-
19
19
0
0
ns
-
19
19
0
0
ns
0
0
ns
0
0
ns
Do not change (2)
-
-
UNIT
MIL.
-
Do not change (2)
-
HOLD TIME
AFTERL-H
9
9
OUTPUT ENABLE/DISABLE TIMES
(C L =5pF, measured to O.5V change of VO UT )
INPUT
MIL.
OE
y
DISABLE
ENABLE
OUTPUT
16
I
I
COM'L.
MIL.
14
18
I
I
COM'L
16
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneou~ operation.
3. Source addresses must be stable prior to the H-L transition to allow timeto access the source data before the latches close. The A address may then be changed. The
B address CQuid be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed during the clock LOWtime.
4. The set~up time prior to the clock L-H transition is to allow time for data to be accessed. passed through the ALU, and returned to the RAM. It includes all the time from
stable A and B addresses to the clock L-H transition, regardless of when the H-L transition occurs.
3-9
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C01E
AC ELECTRICAL CHARACTERISTICS
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
MIL.
COM'L.
UNITS
21
20
ns
46
50
MHz
Minimum Clock LOW Time
10
8
ns
Minimum Clock HIGH Time
10
8
ns
Minimum Clock Period
21
20
ns
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
The tables below specify the guaranteed performance of the
IDT39C01E over the -55·C to +125·C and O·C to +70·C temperature ranges. Vee is specified at 5V ± 10%. All times are in
nanoseconds and are measured between the 1.5V signal level.
The input switch between OV and 3V with signal transition rates of
1V per nanosecond. All outputs have maximum DC current
loads.
Maximum Clock Frequency to shift
Q (50% duty cycle, 1=432 or 632)
COMBINATIONAL PROPAGATION DELAYS(1) (CL = 50pF)
TO OUTPUT
Y
FROM INPUT
F3
G,P
C n+4
O.
F=O
03
A,B Address
26
22
26
22
26
22
26
21
0
18
16
17
15
17
15
16
15
Cn
13
13
13
12
10
10
'0,1,2
21
20
20
19
19
18
13. 4. 5
20
20
20
18
19
18
16. 7. 8
A Bypass
ALU (1=2XX)
13
12
19
18
Clock ~
20
18
UNIT
'L. MIL. COM'L.
MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL.
ns
26
ns
21
13
ns
19
ns
ns
20
16
16
16
16
ns
20
18
15
15
ns
ns
19
18
17
HOLD TIME
AFTER H-L
B Destination Address
18
SET-UPTIME
BEFOREL-H
HOLD TIME
AFTER L-H
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.
MIL.
8
7
0
0(31
18,8
+TPWL(41
15,
7 + TPWL! 41
2
iv,\
A, B Source Addres§"
19
Do not change(21
UNIT
COM'L.
ns
2
1
12
12
0
0
ns
Cn
10
10
0
0
ns
10 ,1.2
14
14
0
0
ns
13.4.5
14
14
0
0
ns
0
0
ns
0
0
ns
8
_(11
0
5
16.7.8
Do not change(21
5
7
RAM o.3,Qo.3
ns
OUTPUT ENABLE/DISABLE TIMES
(C l =5pF. measured to 0.5V change of VOUT )
INPUT
ENABLE
OUTPUT
MIL.
OE
Y
14
I
I
DISABLE
COM'L.
MIL.
10
12
I
I
COM'L
12
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H--L transition to allow time to access the sourcedata before the latches close. The A address may then be changed. The
B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally Aand B are not changed during the clock LOW time.
4. The set-up time priorto the clock L-H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It Includes all the time from
stable A and B addresses to the clock L -H transition, regardless of when the H-L transition occurs.
3-10
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C01C/D/E FOUR-BIT CMOS MICROPROCESSOR SLICE
CAPACITANCE (TA +25°C, f
AC TEST CONDITIONS
0
r-'
Input Pulse Levels
Input Rise/Fal1 Times
Input Timing Reference Levels
Wins
G'N
C OUT
1.5V
1.SV
See Figs. 1, 2
Output Reference Levels
Output Load
PARAMETER(1)
SYMBOL
GND to3.0V
Input Capacitance
Output Capacitance
0
1 OM Hz)
CONDITIONS
V,N
0
TYP.
UNIT
5
pF
7
pF
OV
VOUT = OV
NOTE:
1. This parameter is sampled and not 100% tested
Vee
Your
Fr
CL
1194fl
50pF
~
160fl
I DT39C01 C-D06
Figure 1. All Outputs
(Except I 0)
Figure 2. Open Drain Output
(1
0
0
0)
INPUT/OUTPUT INTERFACE CIRCUITRY
_
4
Vee
-
INPUTS <>--~M~+-(>~
OUTPUTS
(IoL
'OH
I"
IOT39C01C-007
Figure 1. Input Structure (All Inputs)
Figure 2. Output Structure
(All Outputs Except F = 0)
3-11
IDT39C01C-008
I DT39C01C-009
Figure 3. Output Structure
(F = 0 Only)
FEATURES:
DESCRIPTION:
• Provides lookahead carries across any number of 4-bit
microprocessor ALUs
The IDT39C02A is a high-speed carry lookahead generator
built using advanced CEMOS'" II, a dual metal 1.5p.m CMOS
technology. The IDT39C02A is generally used with an arithmetic
logic unit to provide high-speed lookahead over larger word
lengths.
The IDT39C02A is a pin-compatible, performance enhanced,
functional replacement for all versions of the 2902.
• Very high-speed and output drive over full temperature and
voltage supply extremes
• 6ns typical propagation delay
•
•
•
•
10L = 32m A over full military temperature range
CMOS power levels (5p.W typo static)
80th CMOS and TTL output compatible
Substantially lower input current levels than bipolar
(5p.A max.)
• 100% product assurance screening to MIL-STD-883,
Class 8 available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
I,)
Z
G,
Vcc
P,
P2
G2
Cn
Go
Po
G3
P3
LJ LJ
Go
Po
G3
P3
cn+x
Cn+y
P
NC
G
3
2
I I
I I
LJ
LJ LJ
20
NC
1
:] 4
:J 5
G2
:J 6
Cn
-, 7
Cn+x
Cn+y
_.1
:J 8 9
r,
I
cn+z
GND
"
Ie[ lci" ~ I~
I
III.
SSDFCT18NX)1
10
", I
a
Z
~
DIP
11
r,
12
r,
I I
I I
i:
I~
I,)
r,
,
I
I,)
Z
SSDFCT182-002
TOP VIEW
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
G3P3
SSOFCTI82-003
MICROSLICE and CEMOS are trademarks of Integrated Device Technology, Incorporated.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1986
Printed in the U.S.A.
01985 Integrated Device Technology, Incorporated.
3-12
IDT39C02A CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
'C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vee =5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(')
MAX.
UNIT
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
O.B
V
I'H
Input HIGH Current
Vcc = Max., Y'N = Vcc
5
I'A
I'L
Input LOW Current
Vcc = Max., Y'N = GND
-
-
-5
I'A
Isc
Short Circuit Current
Vcc = Max. (3)
-60
-120
-
rnA
VHC
Vcc
-
Output HIGH Voltage
V = Min.
Y'N = V,H or V,L
10H = -3001'A
VOH
10H = -12mA MIL
2.4
4.3
10H = -15mA COM
2.4
4.3
-
VOL
PARAMETER
Output LOW Voltage
Vcc = Min.
Y'N = V,H or V,L
MIN.
TYP'(2)
V,H
10L = 3OOl'A
-
GND
VLC
IOL = 32m A MIL
-
0.3
0.5
IOL = 4BmA COM
-
0.3
0.5
V
V
Iccoc
Quiescent Power Supply Current
(CMOS Inputs)
Vcc = Max.
VHC '; Y'N ,; VLC
f =a
-
0.001
2.0
rnA
ICCQT
Quiescent Power Supply Current
(TTL Inputs)
Vcc = Max.
Y,N = 3.4v(4)
-
0.5
2.5
rnA
Iceo
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
One InputToggling
50% Duty Cycle
VHC '; Y,N ,; VLC
-
0.15
-
Vcc = Max.
f=10MHz
Outputs Open
50% Duty Cycle
One InputToggling
All Inputs
VHC '; Y'N ,; VLC
-
1.5
-
Icc
Total Power Supply(5)
Current
Y'N = 3.4v(4)
-
2.0
-
rnA
Y'N - 3.4V(4)
16.0
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Per TTL driven input (V,N
::=
3AV); all other inputs at Vee or GND.
5. Ice::: 'eeoc + (Ieeor )( NT) + (lceo)( f )( N) + (leeoT )( D )( No)
N ::: Total number of inputs toggling.
f = Frequency in MHz.
D = Percent high duty cycle.
NT = Number of TTL statically driven inputs (V,N = 3.4V)
No = Number of TTL dynamically driven inputs (V,N ::= 3.4V)
3-13
mAl
MHz
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C02A CMOS CARRY LOOKAHEAD GENERATOR
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
Cn
Carry
Carry
Carry
Carry
Carry
Carry
Go. 13;. G2• G3
PO: p,. P2. rs;Cn+x-Cn + z
G
P
Input
Generate Inputs (Active LOW)
Propagate I nputs (Active LOW)
Outputs
Generate Output (Active LOW)
Propagate Output (Active LOW)
TRUTH TABLE
INPUTS
Cn
Go
Po
X
H
X
H
H
L
H
X
L
X
X
X
X
H
H
H
L
L
X
X
X
L
H
X
L
X
X
X
X
H
H
H
X
X
X
X
X
L
X
X
X
X
H
X
L
L
P,
OUTPUTS
G2
P2
G3
P3
Cn + x C n +'1
Cn + z
G
P
L
L
H
H
X
X
X
X
X
X
X
X
G,
H
H
H
L
H
X
X
L
L
X
X
H
H
H
H
L
X
X
X
X
X
X
L
L
X
X
X
X
H
X
X
X
X
X
X
X
H
H
H
X
X
L
X
L
L
L
L
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
L
H
X
X
X
L
L
L
X
X
H
H
H
H
L
X
X
X
X
X
X
L
L
X
L
L
L
L
H
H
H
H
X
X
X
X
H
X
X
X
X
H
X
X
H
L
L
L
X
X
X
H
H
H
H
L
H
X
X
X
L
L
L
H
H
H
H
L
L
L
L
X
X
X
X
H
H
H
H
L
X
X
X
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COMMERCIAL
SYMBOL
PARAMETER
tplH
t pHl
Propagation Delay
CN to CN+ X• C N+y• C N+Z
Propagation Delay
Po. p,. or P2• to
C N+ X• C N +y. C N+ Z
tplH
tpHl
tplH
tpHl
Propagation Delay
G", G,. or G 2 • to
C N+ X• C N+ y , C N+ Z
CONDITION
C l = 50 pf
Rl = 500n
TYPICAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
6.0
3.0
14.0
3.0
16.5
ns
6.0
2.0
9.0
2.0
11.5
ns
6.0
2.0
9.5
2.0
11.5
ns
tpHl
Propagation Delay
p,. P2• or P3. to G
7.0
3.0
12.0
3.0
16.5
ns
tplH
tpHl
Propagation Delay
GNtoG
7.5
3.0
12.0
3.0
16.5
ns
tplH
tpHl
Propagation Delay
PNto P
6.0
2.5
11.0
2.5
12.5
ns
tpLH
3-14
MICROSLICE™ PRODUCT
FEATURES:
DESCRIPTION:
• Fast
-IDT39C03A matches 2903A speeds
-IDT39C03B 20% speed upgrade
The IDT39C03s are four-bit expandable CMOS microprocessor slices. While executing the identical functions associated
with the high-speed IDT39C01 series of 4-bit slices, the IDT39C03s
also provide additional enhancements for use in arithmeticoriented processors.
This extremely low-power yet high-s~eed microprocessor
consists of a 16-word-by-4-bit dual-port RAM, a multidirectional
three-port architecture, 16 logic operation ALU and the necessary shifting, decoding and multiplexing logic. Compatible
2903A arithmetic and logic instructions, including the special
multiplication, division and normalization instructions, are available on the I DT39C03s. Both are easily expandable in 4-bit
increments.
Both devices are pin-compatible, functional-replacements for
the 2903A. The fastest version, the IDT39C03B, is a 20% speed
upgrade from the normal 2903A device. The IDT39C03A meets
the 2903A speeds.
The IDT39C03s are fabricated using CEMOS'", a single poly
double metal CMOS technology designed for high-performance
and high-reliability.
Military product is 100% screened to MIL-STD-883, Class B,
making them ideally suited to military temperature applications.
• Low-power CMOS
-50mA commercial (max.)
-60mA (military) (max.)
• Pin-compatible, performance-enhanced functional
replacement for the 2903A
• Cascadable to 8, 12, 16, etc. bits
• Expandable Register File
• On-chip Parity Generation and Sign Extension Logic
-Provides parity across the entire ALU output and sign
extension at any slice boundary
• On-chip Normalization Logic
-Floating point mantissa and exponent easily develgped
using single microcycle per shift
• On-chip Multiplication and Division Logic
-Executes unsigned and two's complement multiplication
along with last cycle of two's complement multiplication
• Packaged in 48-pin plastic and ceramic DIPs and 52-pin LCC
• Military product available 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
A...
c>------l--+~---<~=:J~~=:=J~----+~----<:::J Bo~
v-~--------_C~WE
cp
DEB
DA~3C>---~-----_.
r-~===~=====;~-g:21
080 . 3
Ell C > - - - f - - - - - - I
SI03
1'>..2'1----t--------1
0103 K : ; ' I - - - - t - - - - - - - - - + - - - - - - '
OEYC>----------~
IO~~.•
LSS
TOPLA
PLA.
Ii/iii'fEIMSS
lEN
z
MSD39C03·001
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
CI 1986 Integrated Device Technology, Inc.
3-15
&I
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
,,~
oZQQQQwOOllllllllllll(J
c ttl.; .lIC Q Q
oG.
\"I
N
...
I.
I.
I.
Cn
Cn + 4
R'OVR
GND
GiN
OEy
Yo
Y,
Y.
NC
MSD39C03~003
LCC
TOP VIEW
MSD39C03-002
DIP
TOP VIEW
3-16
IDT39C03A!IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
1/0
DESCRIPTION
AQ-3
I
RAM A Address Inputs (TTL Input) - Four RAM address inputs which contain the address of the RAM word appearing at
the RAM A output port.
BQ-3
I
RAM B Address Inputs (TTL Input) - Four RAM address inputs which contain the address of the RAM word appearing at
the RAM B output port and into which new data is written when the WE input and the CP input are LOW.
WE
I
Write Enable Input (TTL Input) - The RAM write enable input. If WE is LOW, data at the Y I/O port is written into the RAM
when the CP input is LOW. When WE is HIGH, writing data into the RAM is inhibited.
DAQ-3
I
External Data Inputs (TTL Input) - A four-bit external data input which can be selected as one of the IDT39C03 ALU
operand sources; DAo is the least significant bit.
EA
I
Control Input (TTL Input) - A control input which, when HIGH, selects DAQ-3as the ALU R operand, and, when LOW,
selects RAM output A as the ALU R operand and the DAQ-3 output data.
PIN NAME
DBQ-3
I/O
OE B
I
Control Input (TTL Input) - A control input which, when LOW, enables RAM output B onto the DBQ-3lines and, when
HIGH, disables the RAM output B tri-state buffers.
Cn
I
Carry-In Input (TTL Input) - The carry-in input to the IDT39C03 ALU.
10-8
I
Instruction Inputs (TTL Input) - The nine instruction inputs used to select the IDT39C03 operation to be performed.
lEN
I
Instruction Enable Input (TTL Input) - The instruction enable input which, when LOW, allows the 0 Register and the Sign
Compare flip-fl~o be written. When lEN is HIGH, the 0 Register and Sign Compare flip-flop are in the hold mode. On
the IDT39C03, lEN also controls WRITE.
C n+4
0
Carry-out Output (TTL Output) - This output generally indicates the carry- OVR (MSS)
Z = 0 0 (LSS)
Two's Complement Multiply Last Cycle
SF 6: F = S + Cn if Z = 0
F =S + R + Cn ifZ =1
Y = Log. F/2
0= Log. 0/2
Y3 = OVR E> (MSS)
Z = 0 0 (LSS)
3-27
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SF A/SF C, SF E)
TO
FROM
A, BAddr
DA,DB
Cn
1.-0
CP
SLICE
Y
Cn + 4
G,P
Z
N
OVR
DB
WR
QIOo,a
MSS
@
72/@
-
78/-
68
67
@
-
IS
@
@
@
@/-
-
@
@
@
@/-
-
@
LSS
-
@
-
-
MSS
@
66/@
-
66/-
55
58
-
-
IS
@
@
@
@/-
-
-
LSS
@
@
@
@/-
-
@
37/@
41/-
31
29
IS
@
@
-
@/-
-
LSS
@
@
@/-
-
-
MSS
72/96
89179
-
-
-
-
MSS
-
-
-
80/33
71191
69/91
-
-
SIO o
71
@
@
61
-
@
-
@
36
-
-
-
@
76/98'
-
@
75/96'
@
@
75198'
81193
-
@
@
IS
72/96
69179
56/79
80/-
-
-
LSS
72/96
69179
56/79
80/-
-
-
-
MSS
@/91
51174
-
67/28
55174
58174
@
-
@
IS
@
@
@
@/-
-
-
@
-
@
@
LSS
@
@
@
@/-
-
-
@
-
@
@
-
-
-
-
-
-
-/65
-
-
-/65
-
-
-
Z
IS
-/63
-/46
-/46
-
-
LSS
-/63
-/46
-/46
SIO o,SI0 3
Any
@
-
-
-
-
MSS
-
-
-
-
-
NOTES:
1.
An "-" means the delay path does not exist.
2.
An II." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an u." is the delay to correct data on an enabled
output. An ,,'" shown without a number means the output is disabled by the Input or It Is enabled but the delay to correct data Is determined by something el.e.
3.
An "@" means the delay is the same as In the Standard Functions and Increment by One or Two Instructions Table.
4.
If two delays are given, the first is for 1st divide and normalization: the second is for two's complement divide and two's complement divide correction.
Double Length Normalize and First Divide Op
SF A: F= S + Cn
Y= Log.2F
0= Log. 20
SI0 3 = F3 e R. (MSS)
Cn
= F3 F2 (MSS)
OVR = ~ ~ F.1 ("-1i'!.Sl. __
Z = OOQ,0203FOF,FoF3
+,
e
Two's Complement Divide
SF C: F = R + S + Cn if Z = 0
F = S - R -1 + Cn If Z = 1
Y= Log. 2F
0= Log. 20
SIOs = F. Ell Rs (MSS)
Z = F3 Ell R3 (MSS) from
previous cycle
3-28
Two's Complement Divide Correction and Remainder
SF E: F= R +S+Cn IIZ=O
F=S-R-1 +CnifZ=1
Y=F
0= Log. 20
Z = Fs e Rs (MSS) from previous cycle
IDT39CD3A1IDT39CD3B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SF 5)
TO
FROM
A. BAddr
DA.DB
Cn
I~
CP
WRITE/
MSS
SLICE
Y
Cn +4
G,P
Z
N
OVR
DB
MSS
97
81
-
42
89
89
@
IS
@
@
@
-
-
@
-
LSS
@
@
@
-
-
-
@
-
MSS
94
76
-
37
84
IS
@
@
@
@
@
@
-
84
-
LSS
-
-
MSS
33
@
-
-
32
27
IS
@
@
@
@
-
-
LSS
-
-
MSS
85
67
-
28
82
73
-
@
88"
@
@
88"
@
97
IS
85
67
63
LSS
85
67
63
-
-
-
-
MSS
94
76
-
37
84
84
@
IS
@
@
@
-
-
-
@
LSS
@
@
@
-
-
-
@
-
-
-
-
-
-
-
-
-
-
-
-
-
MSS
-
-
-
Z
IS
57
39
35
LSS
57
39
35
SIO o. SI0 3
Any
@
-
-
QIO o••
SIO.
-
102
@
88"
@
@
97
@
@
@
@
@
@
@
@
@
-
-
-
60
60
-
NOTES:
1.
An "-" means the delay path does not exist.
2.
An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an " .. " is the delay to correct data on an enabled
output. An ..... shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determined by something elsB.
3.
An "@" means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
SF 5: F = S + Cn if Z = 0
F=S+CnifZ=1
Y, =S,61 F3 (MSS)
Z = S,(MSS)
Q=Q
N=F,ifZ=O
N = F, 6l S3 if Z = 1
3-29
II
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SF 8)
TO
FROM
A, B Addr
DA,DB
Cn
18-0
CK
Z
SIOo, SI03
SLICE
Y
en + 4
G,P
Z
N
OVR
DB
@
MSS
@
-
-
-
-
IS
@
@
@
-
LSS
@
@
@
MSS
@
-
-
-
IS
@
@
@
LSS
@
@
@
MSS
@
-
-
IS
@
@
-
-
-
WRITE!
MSS
-
@
-
@
-
-
-
LSS
@
@
-
-
MSS
64
37
-
29
24
24
-
IS
64
64
50
29
LSS
64
64
50
29
-
-
MSS
@
29
-
26
26
29
@
IS
@
@
@
26
-
-
@
LSS
@
@
@
26
-
-
@
MSS
-
-
-
LSS
-
-
IS
-
Any
@
-
-
-
-
-
-
-
010 0,3
SI0 3
-
@
-
@
@
@
@
@
-
-
@
-
-
@
-
-
@
@
62'
@
62'
@
@
62'
-
@
@
@
@
-
-
@
@
-
-
-
NOTES:
1.
An "_" means the delay path does not exist.
2.
An " .. " means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct data on an enabled
output. An "." shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determined by something else.
3.
An "@" means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
SF 8: F = S + Cn
N = 0 3 (MSS)
Y=F
C n . , = 0 3 Ell Q, (MSS)
OVR
Z=QOQ,Q,Q 3
0= LOG. 20
3-30
=0, Ell Q,
(MSS)
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED
MILITARY RANGE PERFORMANCE
TABLE 10.
ENABLE/DISABLE TIMES ALL FUNCTIONS
The tables below specify the guaranteed performance of the
IDT39C03A over the military operating range of -55°C to +125°C
with Vcc from 4.5 to 5.5V. All data are in nanoseconds, with inputs
switching between 0 and 3V at 1Vlnsand measurements made at
1.5V. All outputs have maximum DC load.
FROM
TO
ENABLE
DISABLE
OEy
Y
25
21
OEe
DB
25
21
EA
DA
25
21
18
SIO
25
21
TABLE 9.
CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time
30n8
Minimum Clock High Time
30n8
Minimum Time CP and WE both Low to Write
30n8
18
010
38
38
18.7,6.5
010
38
38
14.3.2.1.0
LSS
010
38
35
WR
30
25
NOTE:
C L = S.OpF for output disable tests. Measurement is made to a O.5V change on the
output.
TABLE 11.
SETUP AND HOLD TIMES ALL FUNCTIONS
HIGH-TO-LOW
LOW-TO-HIGH
TPWL
FROM
WITH RESPECT TO
SET-UP
HOLD
Y
CP
Don't Care
Don't Care
WE HIGH
CP
15
WE LOW
CP
Don't Care
Don't Care
A, B Source
CP
20
3
B Destination
CP
6
010 0. 3
CP
Don't Care
Don't Care
18.7.6.5
lEN HIGH
CP
12
-
CP
24
lEN LOW
CP
Don't Care
Don't Care
CP
18
-
14.3.2.1.0
NOTES:
I
SET-UP
HOLD
14
3
TpWL
I
I
COMMENTS
Store Yin RAM/O(1)
0
Prevent Writing
15
0
Write into RAM
Don't Care
Don't Care
Latch Data from RAM Out
3
Write Data into B Address
TpwL
I
I
I
I
a
17
3
Shift
20
0
Write into 0(21
0
Prevent Writing into
21
0
Write into
32
0
Write into 0(21
a
a
1.
The internal V-bus to RAM setup condition will be met 5ns after valid Y output (OE y = 0).
2.
The setup time with respect to CP falling edge is to prevent writing. The setup time with respect to CP rising edge is to enable writing.
3.
Forall other setup conditions not specified in this table, the setup time should be the delay to stable Y output plus the Vtc RAM internal setup time. Even if the RAM is
not being loaded, this setup condition ensures valid writing into the register and sign compare flip-flop.
4.
WE controls writing into the RAM. lEN controls writing into Q and, indirectly, controls WE through the WRITElMSS output. To prevent writing, lEN and WE must go
HIGH during the entire clock LOW time. They may go LOW a!terthe clock has gone LOW to cause a write, provided the WE LOW and lEN LOW setup times are met.
Having gone LOW. they should not be returned HIGH until after the clock has gone HIGH.
a
5.
A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6.
Writing occurs when CP and WE are both LOW. The B address should be stable during this entire period.
7.
Because '8,7,6,5 controls the writing or not writing of data into RAM and a. they should be stable during the entire clock LOW time unless lEN is HIGH, which prevents
writing.
8.
The setup time priorto the clock LOW-TO-HIGH transition occurs in parallel with the setup time prior to the clock HIGH-TO-LOW transition and the clock LOW lime.
The actual setup time requirement on ' 4,3,2,1,0 relative tothe clock LOW-TO-HIGH transition is the longer of (1) the setup time priorto clock L - Hand (2) the sum ofthe
setup time prior to clock H - L and the clock LOW time,
3-31
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A1IDT39C03B FOUR·BIT CMOS MICROPROCESSOR SLICE
IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF 4)
TO
FROM
Y
en +.
G,P
A. BAddr
70
58
52
78
DA.DB
60
52
40
66
Cn
35
19
-
41
31
29
Z
OVR
DB
WRITE!
MSS
68
67
28
-
55
58
N
18-<1
72
69
56
80
71
69
-
CP
60
42
43
67
55
58
22
SIO o.SI0 3
26
-
-
29
-
-
MSS
44
-
44
44
44
44
Y
-
-
-
-
-
17
lEN
-
-
-
EA
60
52
40
66
55
58
-
SI0 3
SIO.
PARITY
47
71
84
35
61
74
23
33
40
26'
58'
75'
89'
25
41
61
66
-
-
29
19
44
44
44
-
-
-
-
-
35
61
74
010 •• 3
SIO.
-
-
-
-
36
-
20
-
NOTES:
1.
A "-" means the delay path does not exist.
2.
An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an enabled
output. An "." shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determined by somethin~ else.
Standard Functions: See Ta;ble 2
Increment SF 4: F = 5 + 1 + Cn
MULTIPLY INSTRUCTIONS (SF 0, SF 2, SF 6)
TO
FROM
A. B Addr
DA.DB
Cn
18-<1
CP
Z
SIO o• SI0 3
Z
N
OVR
DB
WRITE!
MSS
010 0•3
SIO.
@
@
@
-
-
@
-
-
@
-
-
-
@
-
@
-
-
@
@
-
@
@
@
-
-
-
LSS
@
@
@
-
-
-
-
@
MSS
40
@
IS
@
@
-
-
-
-
-
@
@
-
SLICE
Y
en + 4
MSS
72
@
-
IS
@
@
@
LSS
@
@
MSS
62
IS
G,P
-
@
@
@
@
@
-
-
-
@
-
-
@
98
-
-
-
98
-
@
@
LSS
@
@
-
MSS
108
84
-
IS
108
84
80
-
LSS
108
84
80
33
-
-
MSS
62
@
-
@
@
@
-
@
IS
@
@
@
-
-
@
@
104
80
74
29
-
@
LSS
-
@
-
@
77
-
48
-
48
MSS
75
51
-
-
65
65
-
IS
75
51
47
-
-
-
-
LSS
-
Any
@
-
-
-
-
-
-
-
-
@
@
81'
@
81'
@
81'
-
NOTES:
1.
An "-" means the delay path does not exist.
2.
An "." means the output is enabled or disabled by the input. See enaple and disable times. A number shown with an "." is the delay to correct data on an enabled
output. An "." shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determined by something else.
3.
An "@" means the delay is the same as in the Standard FUnctions and Increment by One or Two Instructions Table.
Unsigned Multiply
SF 0: F = S + Cn if Z = 0
F = 5 + R + Cn if Z
V = Log. F/2
a = Log. 0/2
V3 =C;. 4 (MSS)
Z =0 0 (LSS)
=1
Two's Complement Multiply
SF 2: F = S + Cn if Z = 0
F=R+S+CnifZ=1
V = Log. F/2
=Log. 0/2
V3 = F3 e OVR (MSS)
Z = 0 0 (LSS)
Two's Complement Multiply Last Cycle
SF 6: F = S + Cn if Z = 0
F = S - R • 1 + Cn if Z = 1
V = Log. F/2
= Log. 0/2
V3 = OVR e F3 (MSS)
Z =0 0 (LSS)
a
a
3-32
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SF A/SF C, SF E)
TO
FROM
A. B Addr
DA. DB
Cn
18-0
CP
Z
SIO o• SI0 3
SLICE
Y
Cn + 4
MSS
@
72/@
IS
@
LSS
Z
N
OVR
DB
WR
-
78/-
68
67
@
-
@
@
@/-
-
-
@
-
-
@
@
@
@/-
-
-
@
-
-
@
MSS
@
66/@
-
66/-
55
58
-
-
-
61
@
G,P
010 0 •3
-
SIO O
71
@
IS
@
@
@
@/-
-
-
-
-
-
LSS
@
@
@
@/-
-
-
-
-
-
@
MSS
@
37/@
-
41/-
31
29
-
-
-
36
@
IS
@
@
-
@/-
-
-
-
-
-
LSS
@
@
-
@/-
-
-
-
-
-
@
MSS
72/96
89/79
-
80/33
71/91
69/91
-
-
@
76/98'
IS
72/96
69/79
56/79
80/-
-
-
-
-
@
75/98'
LSS
72/96
69/79
56/79
80/-
-
-
-
@
@
75/98'
MSS
@/91
51/74
-
67/28
55/74
58/74
@
-
@
61/93
IS
@
@
@
@/-
-
-
@
-
@
@
LSS
@
@
@
@/-
-
-
@
-
@
@
MSS
-
-
-
-
-
-
-
-
-
-
IS
-/63
-/46
-/46
-
-
-
-
-
-
-/65
LSS
-/63
-/46
-/46
-
-
-
-
-
-
-/65
Any
@
-
-
-
-
-
-
-
-
-
NOTES:
1,
An "-" means the delay path does not exist.
2,
An "." means the output is enabled or dIsabled by the mput. See enable and disable times. A number shown with an "*" is the delay to correct data on an enabled
output. An "." shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determmed by something else.
3.
An "@" means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table,
If two delays are given, the first is for 1 st divide and normalization; the second is for two's complement divide and two's complement divide correctron.
Double Length Normalize and First Divide Op
SF A: F = S + Cn
Y = Log. 2F
0= Log. 20
SI0 3 = F3 Ell R3 (MSSI
C n >4=F 3 E1lF,(MSS)
OVR = F, Ell F, (MSS)
Z =Qo~
0 2 0'3 F;;F;F;F;
Two's Complement Divide
SF C: F =R + S + Cn if Z =0
F = S - R -1 + Cn If Z = 1
Y = Log. 2F
0= Log. 20
SI0 3 = F3 Ell R3 (MSS)
Z = F3 Ell R3 (MSSI from
previous cycle
3-33
Two's Complement Divide Correction and Remainder
SF E: F =R + S + Cn if Z = 0
F = S - R - 1 + en if Z = 1
Y=F
0= Log. 20
Z = F3 ffi R3 (MSS) from previous cycle
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SF 5)
TO
FROM
A, BAddr
DA,DB
Cn
18-<)
CP
Z
SLICE
Y
Cn +4
MSS
G,P
Z
N
OVR
DB
114
95
-
49
106
106
@
IS
@
@
@
@
@
@
-
-
@
LSS
-
MSS
108
89
-
43
101
WRITE!
MSS
QIO.,3
SI0 3
125
109"
@
-
101
-
-
-
-
-
-
@
IS
@
@
@
LSS
@
@
@
-
-
MSS
36
@
-
-
-
35
29
IS
@
@
-
-
-
LSS
@
@
-
-
-
-
-
MSS
98
79
-
33
97
88
-
@
@
119
@
@
@
@
@
IS
98
79
73
-
-
-
-
@
109"
LSS
98
79
73
-
-
-
-
-
@
@
109"
MSS
108
89
-
43
101
101
@
@
119
@
@
@
-
-
IS
-
-
@
-
@
@
LSS
@
@
@
@
@
-
-
-
-
-
-
@
MSS
-
-
-
-
IS
65
46
40
-
-
-
-
LSS
65
46
40
-
-
-
-
-
Any
-
-
-
-
-
-
-
-
-
76
-
76
-
-
EN
SIO o, SI0 3
NOTES:
1.
An "-" means the delay path does not exist.
2.
An """ means the output is enabled or disabled by the Input. See enable and disable times. A number shown with an "." is the delay to correct data on an enabled
output. An ...... shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determined by something else.
3.
An "@" means the delay Is the same as in the Standard Functions and Increment by One or Two Instructions Table.
5F 5: F= 5 + Cn ifZ = 0
F = 5 + Cn if Z = 1
Y3=5 3 EB F 3 (M55)
Z = 53 (MSS)
Y=F
Q =Q
N = F3 if Z = 0
N=F3 EBS 3 ifZ=1
3-34
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SF 8)
TO
FROM
A, B Addr
DA, DB
Cn
18-0
CK
Z
SIO o, SI0 3
SLICE
Y
Cn + 4
G,P
Z
N
OVR
DB
WRITEI
MSS
MSS
@
-
-
-
@
-
-
@
IS
@
@
@
@
-
-
@
LSS
@
@
@
@
-
-
@
MSS
@
-
-
-
-
@
-
-
-
-
-
-
-
@
-
-
@
010 0 ,3
510.
IS
@
@
@
-
LSS
@
@
@
-
-
MSS
@
-
-
-
-
IS
@
@
-
-
-
-
LSS
@
@
-
-
-
-
-
MSS
72
47
-
33
27
27
75"
72
69
56
33
-
-
-
@
IS
@
75"
LSS
72
69
56
33
-
-
-
@
@
75"
MSS
@
31
-
28
26
31
@
@
@
IS
@
@
@
28
-
@
@
@
LSS
@
@
@
28
-
LSS
-
Any
@
-
-
IS
-
-
@
MSS
-
-
-
-
-
-
-
-
-
-
-
-
-
@
@
@
@
@
-
-
-
-
NOTES:
1.
An "_" means the delay path does not exist.
2.
An co." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct data on an enabled
output. An "*" shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is d~termined by something else.
3.
An "@" means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
SF 8: F =S + Cn
N = O.(MSS)
Y=F
0= LOG. 20
C n . . = 9,~
92l MSS)
OVR = 0 2 $ 0, (MSS)
Z = 0 00,0 20,
3-35
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
IDT39C03B GUARANTEED COMMERCIAL
RANGE PERFORMANCE
TABLE 13.
ENABLE/DISABLE TIMES ALL FUNCTIONS
The tables below specify the guaranteed performance of the
IDT39C03A over the commercial operating range of 0 to +70°C
with Vee from 4.75 to 5.25V. All data are in nanoseconds, with
inputs switching between 0 and 3V at lV/ns and measurements
made at 1.5V. All outputs have maximum DC load.
FROM
TO
ENABLE
DISABLE
DEy
Y
-
DEB
DB
EA
DA
-
18
SIO
18
QIO
18.7•6•5
QIO
14.3.2.1.0
LSS
QIO
TABLE 12.
CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time
Minimum Clock High Time
WR
-
-
-
NOTE:
Minimum Time CP and WE both Low to Write
is made to a O.5V change on the
TABLE 14.
SETUP AND HOLD TIMES ALL FUNCTIONS
HIGH-TO-LOW
From
Y
Hold
With Respect To
Comments
Store Y in RAM/Q(')
CP
WE HIGH
Prevent Writing
WE LOW
Write into RAM
A. B Source
Latch Data from RAM Out
B Destination
Write Data into B Address
QIO O• 3
ShiflQ
18.7•6•5
lEN HIGH
Write into Q(2)
lEN LOW
WriteintoQ
14.3.2.1.0
Write into Q(2)
Prevent Writing into Q
NOTES:
1. The internal V-bus to RAM setup condition will be met 5ns after valid Y output (OE y = 0).
2.
The setup time with respect to CP falling edge is to prevent writing. The setup time with respect to CP rising edge is to enable writing.
3.
For all other setup conditions not specified in this table, the setup time should be the delay to stable Y output plus the Y to RAM internal setup time. Even if the RAM is
not being loaded, this setup condition ensures valid writing into the register and sign compare flip-flop.
4.
WE controls writing into the RAM. WE controls writing into 0 and, indirectly, controls WE through the WRITEJMSS output. To prevent writing, lEN and WE must go
HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided theWE LOW and lEN LOW setup times are met.
Having gone LOW. they should not be returned HIGH until after the clock has gone HIGH.
5.
A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
a
6.
Writing occurs when CP and WE are both LOW. The B address should be stable during this entire period.
7.
Because I s.7 ,6,5 controls the writing or not writing of data into RAM and Q, they should be stable during the entire clock LOW time unless lEN is HIGH, which
prevents writing.
8.
The setup time prior to the clock LOW-TO-HIGH tranSition occurs in parallel with the setup time prior to the clock HIGH-TO-lOW transition and the clock LOW time.
The actual setup time requirement on 14 ,3.2,1,0 relative to the clock LOW-TO-HIGH transition is the longerof (1) the setup time prior to clock L - Hand (2) the sum of the
setup time prior to clock H - L and the clock LOW time.
3-36
1DT39C03A/IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03B GUARANTEED COMMERCIAL RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF 4)
TO
FROM
Y
G,P
z
N
OVR
DB
WRITEI
MSS
SI0 3
010 0,3
SIO o
PARITY
A, B Addr
DA, DB
Cn
CP
MSS
Y
lEN
EA
NOTES:
1.
A "-" means the delay path does not exist.
2.
An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown wtth an " .. " is the delay to correct data on an enabled
output. An "*" shown without a number means the output is disabled by the input or it is enabled but the defay to correct data is determined by something else.
Standard Functions: See Table 2
Increment SF 4: F::: S + 1 + Cn
MULTIPLY INSTRUCTIONS (SF 0, SF 2, SF 6)
TO
FROM
SLICE
Y
Cn + 4
z
G,P
N
OVR
WRITEI
MSS
DB
010 0,3
SIO O
MSS
A, B Addr
IS
LSS
MSS
DA,DB
IS
LSS
MSS
Co
IS
LSS
MSS
18-0
IS
LSS
MSS
CP
IS
I
LSS
MSS
Z
IS
I
LSS
SIO o, SI0 3
Any
NOTES:
1.
An ,,_It means the delay path does not exist.
2.
An "*,, means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an enabled
output. An "*" shown without a number means the output is disabled by the input or it is enabled but the delay to correct data rs determined by something else.
3.
An "@" means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
Unsigned Multiply
SF 0: F =S + Cn if Z =0
F ::: S + A + Cn if Z = 1
Y =Log. F/2
0= Log. 0/2
Y3 =C O ' 4 (MSS)
Z =0 0 (LSS)
Two's Complement Multiply
SF 2: F = S + Cn if Z = 0
F=R+S+CnifZ=l
Y = Log. F/2
0= Log. 0/2
Y3 = F3 t~~
-
__-L______L-____- L______L-____-L____~~____~
>").-)«1>.
1.
2.
SF 5: F = 5 + Cn if Z = 0
F = S + Cn if Z = 1
,~
), %r
W~".
';' 'Gt
. S~·it1~je and disable times. A number shown with an ..... is the delay to correct data on an enabled
'~6Ied by the input or it is enabled but the delay to correct data is determined by something else.
tions and Increment by One or Two Instructions Table.
.:s; e F3 (M5S)
dm
a=a
~ 53 (MSS)
N=F3 ifZ =D
S3 if Z
N =F3
e
" \ :I" ~
t~~
3-39
=1
IDT39C03A/IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03B GUARANTEED COMMERCIAL RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SF 8)
TO
z
G,P
J--------l---+---+-"
N
OVR
DB
WRITEI
MSS
QIOO,3
fr"",
>i";,:",,....
v':'; c/'
1.
An "_" means the delay path does not ex;ist.
2.
An ,,,.,, means the output is enabled or dis
output. An ,,* .. shown without a numb
3.
An "@" means the
SF 8: F = S + Cn
N = 0, (MSS)
Y=F
0= LOG. 20
d~lay
is the
,v /fo
:.,., ~'r'
e:.nable and disable times. A number shown with an "." is the delay to correct data on an enabled
is~bled by the input or it is enabled but the delay to correct data is determined by something else.
sa~"
ions and Increment by One or Two In!;:itructions Table.
OVR = 0, Ell 0, (MSS)
0, Ell 0, (MSS)
-p,Op,
3-40
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03A1IDT39C03B FOUR-BIT CMOS MICROPROCESSOR SLICE
IDT3903B GUARANTEED
MILITARY RANGE PERFORMANCE
TABLE 16.
ENABLE/DISABLE TIMES ALL FUNCTIONS
The tables below specify the guaranteed performance of the
I DT39C03B over the military operating range of -55°C to +125°C
with Vee from 4.5 to S.SV. All data are in nanoseconds, with inputs
switching between 0 and 3V at 1V1nsand measurements made at
1.SV. All outputs have maximum DC load.
FROM
TO
OEy
y
-
-
OE B
DB
-
-
EA
DA
-
-
I,
SID
-
-
I.
010
-
-
la.7.6,5
010
-
-
14,3,2,1,0
010
-
-
LSS
WR
-
-
TABLE 15.
CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time
-
Minimum Clock High Time
-
Minimum Time CP and WE both Low to Write
-
ENABLE
DISABLE
NOTE:
C L = 5.0pF for output disable tests. Measurement is made to a O.SV change on the
output.
TABLE 17.
SETUP AND HOLD TIMES ALL FUNCTIONS
HIGH-TO-LOW
LOW-TO·HIGH
TpWL
SET-UP
HOLD
WITH RESPECT TO
SET-UP
HOLD
y
CP
-
-
-
-
Store Yin RAMIO 111
WEHIGH
CP
-
-
-
-
Prevent Writing
WE LOW
CP
-
-
Write into RAM
-
-
-
Latch Data from RAM Out
B Destination
CP
CP
-
-
-
A, B Source
-
-
Write Data into B Address
010 0 . 3
OP
-
-
-
-
ShiltO
18 ,7,6,5
CP
-
-
-
-
Write into 0(21
lEN HIGH
CP
-
-
-
-
Prevent Writing into 0
lEN LOW
CP
-
-
-
-
Write into 0
14,3,2,1,0
CP
-
-
-
-
Write into 0(21
FROM
COMMENTS
NOTES:
The internal V-bus to RAM setup condition will be met 5ns after valid Y output (OE y = 0).
2.
The setup time with respect to CP falling edge is to prevent writing. The setup time with respect to CP rising edge is to enable writing.
3.
Forall other setup conditions not specified in this table, the setup time should be the delay tastable Y output plus the Y to RAM internal setup time. Even if the RAM is
not Jeing loaded, this setup conditiQn ensures valid writing into the Q register and sign compare flip-flop.
4.
WE controls writing
into the RAM. lEN controls writing into Q and, indirectly, controls WE through the WRITElMSS output. To prevent writing, lEN and WE must go
HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE LOW and lEN LOW setup times are met.
Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
5.
A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6.
Writing occurs when CP and WE are both LOW. The B address should be stable during this entire period.
7.
Because 18765 controls the writing or not writing of data into RAM and Q, they should be stable during the entire clock LOW time unless lEN is HIGH, which prevents
.,.
writing.
8.
The setup time prior to the clock LOW-TO-HIGH transition occurs in parallel with the setup time prior to the clock HIGH-TO-LOW transition and the clock LOW time.
The actual setup time requirement on 14 3210 relative to the clock LOW-TO-HIGH transition is the longer of (1) the setup time priortoclock L -- Hand (2) the sum of the
setup time prior to clock H --- L and the clock LOW time.
3-41
IDT39C03A1IDT39C03B FOUR·BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C03B GUARANTEED MILITARY RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF 4)
TO
FROM
G,P
Y
z
N
OVR
DB
WRITE!
MSi
010 0,3
SIO
PARI~
SIOo
A, B Addr
DA,DB
Cn
CP
MSS
Y
lEN
EA
NOTES:
1.
A "-" means the delay path does not exist.
2.
An "~,, means the output is enabled or disabled by the input. See enable and disable times. A number shown with an"
output. An ... shown without a number means the output is disabled by the input or it is enabled but the delay to
ct data on an enabled
by something else.
11
Standard Functions: See Table 2
Increment SF 4: F = S + 1 + en
MULTIPLY INSTRUCTIONS (SF 0, SF 2, SF 6)
FROM
SLICE
Y
Cn+4
G,P
DB
WRITE!
MSS
010 0,3
SIO o
MSS
A, BAddr
IS
LSS
... "$~;-
MSS
DA,DB
IS
.....
Cn
MSS
la-a
IS
LSS
MSS
CP
IS
LSS
MSS
Z
IS
SIO o, SI0 3
Any
LSS
NOTES:
1.
An "_" means the delay path does not exist.
2.
An "." means the output is enabled or disabled'by the input. See enable and disable times. A number shown with an " .. " isthe delay to correct data on an enabled
output. An ..... shown without a number means the output is disabled by the input or it is enabled but the delay to correct data is determined by something else.
3.
An "@" means the delay is the same as In the Standard Functions and Increment by One or Two Instructions Table.
Unsigned Multiply
SFO: F = S + Cn iIZ=O
F = S + R + Cn il Z = 1
Y = Log. F/2
0= Log. 0/2
Y,=Cn .. (MSS)
Z = 0 0 (LSS)
Two's Complement Multiply
SF2:F=S+CnifZ=O
F=R+S+CnifZ=1
Y = Log. F/2
0= Log. 0/2
Y, = F, 0hL
IOT49C41~
IOT49C410-007
'Flgure 2. Output Structure (All Outputs)
Figure 1. Input Structure (All Inputs)
AC TEST CONDITIONS
Input Pulse Levels
Input RiselFail Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
Wins
1.5V·
1.5V
~OUTPUT
--I:>-11~L
See Fig. 4
MSD39C03-008
SWITCHING WAVEFORMS
Figure 3. Open Drain Structure
3.0Y----~
INPUTS
OY - - - - - - "
3.0Y
TEST LOAD CIRCUITS
CLOCK
OY
Yee
14m
OUTPUTS
~UT-~~------t
750
MSD39C03-009
Figure 4. Switching Test Circuit
(alt outputs)
3-46
FEATURES:
• Low-power CMOS
-Commercial - 45mA (max.)
-Military - 55mA (max.)
The IDT39C09/11 devices are high-speed, 4-bit address
sequencers intended for controlling the sequence of microinstructions located in the microprogram memory. They are fully
cascadable and can be expanded to any increment of 4 bits.
The IDT39C09s can select an address from any four sources:
1) external direct inputs (D); 2) external data from the R inputs,
stored in an internal register; 3) a 9-word deep push-pop stack; or
4) a program counter register. Also included in the stack are
additional control functions which efficiently execute nested
subroutine linkage. Each output can be ORed with an external
input for conditional skip or branch instructions. A ZERO input
line forces the outputs to all zeroes. All outputs are three-state
and are controlled by the OE (Output Enable) pin.
The IDT39C11s operate identically to the IDT39C09s except
the four OR outputs are removed and the D and R inputs are tied
together. They are fabricated using CEMOS", a single poly,
double metal CMOS technology designed for high-performance
and high-reliability. Military product is 100% screened to MILSTD-883, Class 8, making them ideally suited to military temperature applications demanding the highest level of performance
and reliability.
• Fast
-A versions meet standard speeds
-8 versions are 20% speed upgrades
• 9-Deep stack
-Accommodates nested loops and subroutines
• Cascadable
-Infinitely expandable in 4-bit increments
• Available in 28-pin DIP/LCC (IDT39C09) and 20-pin
DIP/LCC (IDT39C11)
• Pin-compatible, functional enhancement for all versions of
the 2909/2911
• Military product available 100% screened to MIL-STD-883,
Class 8
:= _~(~:!:~CO! ~~!l_J
FUNCTIONAL BLOCK DIAGRAM
FE
PUP
r---I
iiE--iI,----<. .
I
I
f(NOTE 1)
4
I
t----o<}----t---
So
S,
rTD{T~~1:9-~O~N~LY~-Li::e:::~::t:~~
I
I
CP
MICROPROGRAM
COUNTER
REGISTER
ORa~--~--+-~~~
OR,~--~-+-.
I ORo _----!-,
---1
1______
4
Yo Y, Y
Y
a
3
Cn
Nole 1: D and R connecled on IDT39C11 only.
C.,..
MSD39C09-0[:l1
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
C1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
3-47
II
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARV AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT39C09
IDT39C09
r£ rE rll~
~o
...
...
'I " ,
II
II
II
.
Vee
CP
pUP
FE
Ro
OR 3
03
Cn+4
Cn
aE
OR_
V3
L.JLJ ,0 I I LJ L.J LJ
-, 4
3 2 I , 28 27 26rLJ
2s L 1
FE
:J6
24[:
C n +4
:J 7
23[-=.
Cn
:J8
:J9
22[-:"
OE
21[:
20[:
Va
V_
-"5
v_
0_
V,
OR,
:JlO
0,
-,11
Vo
S,
So
ZERO
-~
fl fl rl
f~
ri rl rr--
C §]
I~
t3
0:0
o
DIP
TOP VIEW
II
u ... ::J
19r-
,,~
V,
en ~
LCC
TOP VIEW
MSD39C09-003
IDT39C11
IDT39C11
CP
III!
PUP
FE
Vee
RE
u
... ::J......
~ u
LJ LJ I' I,
~J
I~
LJ
03
Cn+4
Cn
03
D_
OE
D_
Cn
0,
Va
V_
V,
0,
OE
Do
V3
Do
GND
ZERO
LJ
20
CO'o
1
GND
Vo
S,
So
2
r,
'a r,
r
'
, I
11
I I
12
V_
,r,, ,r,,
"
I~
DIP
TOP VIEW
MSD39C09-004
t3
rn~>
LCC
TOP VIEW
MSD39C09..oos
PIN DESCRIPTION
NAME
I/O
DESCRIPTION
S,. So
I
Control lines for address source selection.
FE, PUP
I
Control lines for push/pop stack.
RE
I
Enable line for internal address register.
OR,
I
Logic OR inputs on each address output line.
(IDT39C09 ONLY)
ZERO
I
Logic AND input on the output lines.
OE
I
Output Enable. When OE is HIGH, the Youtputs
are OFF (high impedance).
Cn
I
Carry-in to the incrementer.
R,
I
Inputs to the internal address register.
(IDT39C09 ONLY)
D,
I
Direct inputs to the multiplexer.
CP
I
Clock input to the AR and "PC register and
Push-Pop stack.
Y,
0
Address outputs from IDT39C09/11. (Address
inputs to control memory.)
Cn + 4
0
Carry out from the incrementer
3-48
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MICROPROGRAM SEQUENCER
ARCHITECTURE
The IOT39C09/11's architecture consists of the following
segments:
-Multiplexer
-Direct Inputs
-Address Register
-Microprogram Counter
-Stack
MULTIPLEXER
The multiplexer is controlled by the So and 5, inputs to select
the address source. The two inputs control the selection of the
address register, direct inputs, microprogram counter or stack as
the source of the next microinstruction address.
DIRECT INPUTS
This 4-bit field of inputs (OJ) allows addresses from an external
source to be output on the Y outputs. On the IOT39C11s, these
inputs are also used as inputs to the register.
ADDRESS REGISTER
The Address Register (AR) consists of 4 O-type, edgetriggered flip-flops which are controlled by the Register Enable
(RE) input. With the address register enable LOW, new data will
be entered into the register on the clock LOW-to-HIGH transition.
The address register is also available as the next microinstruction
address to the multiplexer.
MICROPROGRAM COUNTER
Both devices contain a microprogram counter "(/lPC), which
consists of a 4-bit incrementer followed by a 4-bit register. The
incrementer has Carry-In (C n) and Carry-Out (C n+4) for easy and
simple cascading.
When the least significant carry-in to the incrementer is HIGH,
the microprogram register is loaded on the next clock cycle with
the current V output word plus one (V + 1 - /lPG). If the least
significant C n is LOW, the incrementer passes the V output word
unmodified and the microprogram register is loaded with the
same Y word on the next clock cycle (V - /lPC).
STACK
The 9-deep stack, which stores return addresses when executing microinstructions, is an input to the multiplexer. It contains a
stack pointer which always points to the last word written. The
added stack depth of 9 on the IOT39C09/11 allows for additional
microinstruction nesting.
The stack pointer is an up/down counter controlled by File
Enable (FE) and Push/Pop (PUP) inputs. When the FE input is
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOWand Ihe PUP input is HIGH, the PUSH operation is enabled.
The stack pointer will then increment and the memory array is
written with the microinstruction address following the subroutine jump that initiated the PUSH. A POP operation is initialed at
the end of a microsubroutine to obtain the return address. A POP
will occur when FE and PUP are both LOW, implying a return
from a subroutine. The next LOW-to-HIGH clock transition
causes the stack pointerto decrement. Ifthe FE input is HIGH, no
action is taken by the stack pointer regardless of any other input.
The ZERO is used to force the four outputs to the binary zero
state. When LOW, all V outputs are LOW regardless of any other
inputs (except OE). Each Y output bit also has a separate OR
input such that a conditional logic one can be forced at each V
output (IOT39C09 only). This allows jumping to different microinstructions on programmed conditions.
The Output Enable (OE) input controls the V outputs. When
HIGH, the outputs are programmed to a high impedance
condition.
OPERATION OF THE IDT39C09/11
Figure 1 lists the select codes for the multiplexer. The two bits
applied from the microword register (and additional combinationallogic for branching) determine which data source contains
the address for the next microinstruction. The contents of the
selected source will appear on the Y outputs. Also in Figure 1 is
the truth table for the output control and the push/pop stack
control. So. 5" FE and PUP operation is explained in Figure 2. All
four define the address appearing on the V outputs and the state
of the internal registers following a clock LOW-to-HIGH
transition.
The columns on the left explain the sequence of microinstructions to be executed. At address J + 2, the sequence control
portion of the microinstruction contains the command "Jump to
subroutine at A". Atthetime T2, this instruction is in the /lWR and
the IDT39C09 inputs are set up to execute the jump and save the
return address. The subroutine address A is applied to the 0
inputs from the /lWR and appears on the V outputs. The first
instruction olthe subroutine, I(A) is accessed and is at the inputs
of the /lWR. On the next clock transition, I(A) is loaded into the
/lWR for execution and the return address J + 3 is pushed onto
the stack. The return instruction is executed at T5. Figure 4 is a
similar timing chart showing one subroutine linking to a second,
the latter consisting of only one microinstruction.
Figures 3 and 4 are examples of subroutine execution. The
instruction being executed at any given time is the one contained
in the microword register (/lWR). The contents of the /lWR also
controls the four signals SO,S" FE and PUP. The starting address
of the subroutine is applied to the 0 inputs of the IOT39C09 at
the correct time.
3-49
3
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARV AND COMMERCIAL TEMPERATURE RANGES
ADDRESS SELECTION
OUTPUT CONTROL
5,
So
SOURCE FOR V OUTPUTS
SYMBOL
OR,
ZERO
OE
V,
L
L
H
H
L
H
L
H
Microprogram Counter
Address/Holding Register
Push-Pop stack
Direct inputs
"PC
AR
STKO
X
X
H
L
X
L
H
H
H
L
L
L
Z
L
H
Source selected by So S,
OJ
Z = High Impedance
SYNCHRONOUS STACK CONTROL
FE
PUP
H
X
PUSH-POP STACK CHANGE
No change
L
H
Increment stack pOinter, then push current PC
onto STKO
L
L
Pop stack (decrement stack pointer)
H = High
L= Low
X = Don't Care
Figure 1.
CYCLE
So, 5" FE, PUP
"PC
REG
VOUT
N
N+1
L L L L
J
J +1
K
K
J
-
N
N+1
L L L H
J
J+1
K
K
-
N
N+1
L L H X
J
J +1
K
K
-
N
N+1
L H L L
J
K+1
K
K
-
N
N+1
L H L H
J
K+1
K
K
-
Push "PC: Jump to Address in AR
JSRAR
N
N+1
LHHX
J
K+ 1
K
K
K
-
Jump to Address in AA
JMPAR
N
N+1
H L L L
J
Ra + 1
K
K
Aa
N
N+1
H L L H
J
Ra + 1
K
K
Ra
-
Jump to Address in STKO: Push "PC
N
N+1
H L H X
J
Ra + 1
K
K
Ra
-
Jump to Address in STKO
N
N+1
H H L L
J
0+1
K
K
-
N
N+1
H H L H
J
0+1
K
K
0
-
N
N +1
H H H X
J
0+1
K
K
0
-
-
-
-
J
J
K
K
-
0
-
COMMENT
Pop Stack
End Loop
Push "PC
Set-up Loop
Continue
Continue
Pop Stack: Use AR for Address
End Loop
Jump to Address in STKO: Pop Stack
RTS
Stack Ref (Loop)
Pop Stack: Jump to Address on 0
End Loop
Jump to Address on D: Push "PC
JSR D
Jump to Address on 0
JMPD
x = Don't care, 0 = LOW, 1 = HIGH, Assume eN = HIGH
Figure 2. Output and Internal Next-Cycle Register States lor IDT39C09111
3-50
PRINCIPAL USE
IDT39C09A1B AND IDT39CllA1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONTROL MEMORY
In the columns on pages 5 and 6, the sequence of microinstructions to be executed are shown. At address J+2, the
command "Jump to Subroutine at A" is contained in the
sequence control portion of the microinstruction. At time T2,
this instruction is in the p.WR, and the IDT39C09 inputs are set
up to execute the jump and save the return address. The
subroutine address A is applied to the D inputs from the p.WR
and appears on the Y outputs. The first instruction of the
subroutine, I (A). is accessed and is at the inputs of the p.WR.
On the next clock transition, I(A) is loaded into the p.WR for
execution and the return address J+3 is pushed onto the stack.
The return instruction is executed at Ts. Figure 4 shows a
similar timing chart of one subroutine linking to a second, the
latter consisting of only one microinstruction.
MICROPROGRAM
EXECUTE
CYCLE ADDRESS SEQUENCER
INSTRUCTION
To
T,
T2
T6
T7
-
J-l
J
J +1
J+2
J+3
J+4
JSR A
-
-
T3
T,
T5
-
A
A+ 1
A+2
I(A)
RTS
-
-
-
-
-
-
-
-
-
EXECUTIVE CYCLE
CLOCK
SIGNALS
IDT3SCOS/11
Inputs
(from!,WR)
Internal
Registers
To
T1
I LrL
.-
T2
T3
T,
Ts
T.
T7
3
0
H
0
H
2
0
H
0
H
X
X
X
n- ILI Ln-~I LL-
S~o
FE
0
H
0
H
PUP
D
X
X
X
L
H
X
A
X
X
X
L
L
X
!,PC
STKO
STK1
STK2
STK3
J+1
J+2
J+3
-
-
A+ 1
J+3
A+2
J+3
A+3
J+3
-
Ta
-
-
-
-
-
X
X
J+4
J+5
-
-
-
IDT3SCOS/11
Output
Y
J +1
J+2
A
A+ 1
A+2
J+3
J+4
J+5
ROM Output
(V)
I(J + 1)
JSR A
I(A)
I(A+ 1)
RTS
I(J + 3)
I(J +4)
I(J + 5)
Contents of !'WR
(Instruction
being executed)
!'WR
I(J)
I(J + 1)
JSRA
I(A)
I(A+ 1)
RTS
I(J +3)
I(J + 4)
Figure 3. Subroutine Execution.
3-51
T.
L
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONTROL MEMORY
MICROPROGRAM
EXECUTE
CYCLE ADDRESS SEQUENCER
INSTRUCTION
-
J-1
J
J+1
J+2
J+3
To
T,
T2
Tg
-
JSRA
-
-
T3
T.
Ts
T7
Ta
-
-
-
A
A+ 1
A+2
A+3
A+4
JSR 8
8
RTS
-
RTS
-
T6
-
-
-
EXECUTIVE CYCLE
To
T,
T2
T3
T.
To
T.
S~o
0
H
X
X
0
H
X
X
3
L
H
A
0
H
X
X
0
H
X
X
3
L
H
8
2
L
L
X
0
H
X
X
2
L
L
X
0
H
X
X
I'PC
STKO
STK1
STK2
STK3
J +1
J+2
J+3
A+1
J+3
A+2
J+3
A+3
J+3
8+1
A+3
J+3
A+4
J+3
A+5
J+3
J+4
IDT39C09/11
Output
Y
ROM Output
Contents of I'WR
(Instruction
being executed)
CLOCK
SIGNALS
IDT39C09/11
Inputs
(IromI'WR)
Internal
Registers
- n-I Ln- I LILn- IL
FE
PUP
D
-
-
-
-
J +1
J+2
(Y)
I(J + 1)
I'WR
I(J)
-
-
-
A
A+1
A+2
JSRA
I(A)
I(A+1)
I(J + 1)
JSRA
I(A)
-
Ta
L
L L
-
-
8
A+3
A+4
J+3
J+4
JSR 8
RTS
I(A+3)
RTS
I(J + 3)
I(J + 4)
I(A+ 1)
JSR 8
RTS
I(A+3)
RTS
I(J + 3)
Figure 4. lWo Nested Subroutines. Routine B Is Only One Instruction.
-
T.
-
C n ; High
3-52
T7
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ID,T39C09/11 APPLICATIONS
CONTROL UNIT ARCHITECTURE
The IDT39CCi9 and IDT39C11 are four-bit-slice sequencers
which are cascaded to form a microprogram memory address
generator. Both products make available to the user several
lines which are used to directly control the internal holding
register, multiplexer and stack. By appropriate control of these
lines, the user can implement any desired set of sequence
control functions; by cascading parts he can generate any
desired address length. These two qualities set the IDT39C09
and IDT39C11 apart from the IDT39C10, which is architecturally
similar, but is fixed at 12 bits in length and has a fixed set of 16
sequence control instructions. The I DT39C09 or I DT39C11
should be selected instead of the IDT39C10 under the following
conditions: (1) address less than 8 bits and not likely to be
expanded; (2) address longer than 12 bits; (3) more complex
instruction set needed than is available on IDT39C10.
The recommended architecture using the IDT39C09 or
IDT39C11 is shown in Figure 5. The path from the pipeline
register output through the next address logic, multiplexer and
microprogram memory is all combinational. The pipeline register contains the current microinstruction being executed. A
portion of that microinstruction consists of a sequence control
command such as "continue", "loop", "return from subroutine",
etc. The bits representing this sequence command are logically
combined with bits representing such things as test conditions
and system state to generate the required control signals to the
I DT39C09 or I DT39C 11.
I
FE,PUP
I
I
I
I
I
I
OTHER BRANCH
ADDRES1 SOURCE
2~
-8
----
-7
VARIOUS
TEST
CONDITIONS
6
'"0",
S
z'"
0
....
4
INTERRUPT
Qa:
0)( I-
j::!!:
-!::i
Q:;)
3
~:;;
2
0
/~
L
NEXT ADDRESS
CONTROL LOGIC
I
~
I
II ANDSUBROUTINE
LOOP STACK
j
I,
MICROPROGRAM
COUNTER REGISTER
~
So
S,
PC
D
R
F
NEXT ADDRESS
MULTIPLEXER
~
i
I
INCREMENTER
i
L-----r·--ADDRESS
MICROPROGRAM MEMORY
BRANCH NEXT ADDRESS
OTHER
ADDRESS
SELECT
I!:f--:;)
r
STACK POINTER
REGISTER
I
:;)
0
I
+
SYSTEM STATE
{' 12 BITS TYP f S BITS Typf 40 BITS TYP
CLOCK
PIPELINE REGISTER
•
/3-SBITS
~
JTOIDT~
C.
OTHER
MSD39C09-Q08
Figure S. Recommended Computer Control Unit Architecture Using the IDT39C09A/B and IDT39C11A/B.
3-53
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C09/11 EXPANSION
Figure 6 shows the interconnection of three IDT39C11s to
form a 12-bit sequencer. Note that the only interconnection
between packages, other than the common clock and control
lines, is the ripple carry between !,PC Incrementors. This carry
path is not in the critical speed path if the IDT39C11 Youtputs
drive the microprogram memory, because the ripple carry
occurs in parallel with the memory access time. If, on the other
hand, a microaddress register is placed at the IDT39C11 output,
then the carry may lie in the critical speed path, since the last
carry-in must be stable for a setup time prior to the clock.
SELECTING BETWEEN THE
IDT39C09 AND IDT39C11
The difference between the IDT39C09 and the IDT39C11
involves two signals: the data inputs to the holding register and
the OR inputs. In the IDT39C09, separate four-bit fields are
provided for the holding register and the direct branch inputs
to the multiplexer. In the IDT39C11, these fields are internally
tied together. This may affect the design of the branch add~ess
system, as shown in Figure 7. Using the IDT39C09, the register
inputs may be connected directly to the microprogram memory;
the internal register replaces part of the pipeline register. The
direct (D) inputs may be tied to the mapping logic which
translates instruction op codes into microprogram addresses.
While the same technique might be used with the IDT39C11,
it is more common to connect the IDT39C11's D inputs to
a branch address bus onto which various sources may be
enabled. Shown in Figure 7 is a pipeline register and a mapping
ROM. Other sources might also be applied to the same bus.
The internal register is used only for temporary storage of
some previous branch address.
BRANCH
ADDRESS
IN
c,"
MICROINSTRUCTION
Figure 6. Twelve Bit Sequencer.
INSTRUCTION REG.
IDT3tc11
MS039C09-11
MSOO9C09-0010
Figure 7. Branch Address Structures.
3-54
IDT39C09A1B AND IDT39CllA1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The second difference between the IDT39C09 and IDT39C11
is that the IDT39C09 has OR inputs available on each address
output line. These pins can be used to generate mUlti-way
single-cycle branches by simply typing several test conditions
into the OR lines (see Figure 8). Typically, a branch is taken to
an address with zeroes in the least significant bits. These bits
are replaced with 1s or Os by test conditions applied to the OR
lines. In Figure 8, the states of the two test conditions X and Y
result in a branch to 1100, 1101, 1110 or 1111.
m- ~---+---,
How to Perform Common Functions
with the IDT39C09/11
1. CONTINUE
L
FE
PUP
H
x
FE
PUP
H
x
Contents of PC placed on Y outputs; PC incremented.
2. BRANCH
H
H
H
Feed data on 0 inputs straight through to memory address lines.
Increment address and place in PC.
Y
3. JUMP TO SUBROUTINE
H
FE
PUP
L
H
xI
Figure 8, Use of OR Input. to Obtain 4-Way Branch.
Subroutine address fed from 0 inputs to memory address. Current PC
is pushed onto stack, where it is saved for the return.
4. RETURN FROM SUBROUTINE
L
FE
PUP
L
L
The address at the top of the stack is applied to the microprogram
memory, and is incremented for PC on the next cycle. The stack is
popped to remove the return address.
3-55
IDT39C09AfB AND IDT39C11AfB
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
V TERM
RATING
Terminal Voltage
with Respect
toGND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
VALUE
UNIT
-0.5(3) to +7.0
V
Military
TA
Operating
Temperature
-55 to +125
°C
TS1AS
Temperature
Under Bias
-65 to +135
°C
TSTG
Storage
Temperature
-65 to +150
°C
PT
lOUT
GRADE
Power Dissipation (2 )
1.0
DC Output Current
into 0 utputs
GND
Vee
-55°C to +125°C
OV
5.0V ± 10%
O°C to +70°C
OV
5.0V ±5%
Commercial
CAPACITANCE
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
CONDITIONS
TYP.
UNIT
=OV
VOUT =OV
5
pF
7
pF
Input Capacitance
C'N
C OUT
mA
(TA = +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
W
30
AMBIENT
TEMPERATURE
Y'N
Output Capacitance
NOTE:
1. This parameter is sampled and not 100% tested.
2. PT maximum can only be achieved by excessive IOL or IOH'
3. V1l Min. = -3.0V for pulse width less than 20n5.
DC ELECTRICAL CHARACTERISTICS
TA = O°C to +70°C
TA = -55°C to +125°C
VLe = 0.2V
VHe = Vee - 0.2V
Min. = 4.75V
Min. = 4.50V
Vee = 5.0V ± 5%
Vee = 5.0V ± 10%
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level (4)
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level (4 )
-
-
0.8
V
I'H
Input HIGH Current
Vec
-
0.1
5
p.A
I'L
Input LOW Current
Vee = Max.,
-
p.A
SYMBOL
TEST CONDITIONS(1)
PARAMETER
= Max.,
= Vcc
Y,N = GND
Y,N
-0.1
-5
= -300p.A
VHe
Vcc
-
IOH = -12mA MIL.
2.4
4.3
-
IOH = -15mA COM'L.
2.4
4.3
-
IOL = 300p.A
-
GND
=20m A MIL.
IOL = 24mA COM'L.
Vo = OV
Vo = Vcc
-
0.3
0.5
-
0.3
0.5
-
-
-40
-
-
40
-30
-
-130
IOH
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Vcc = Min.
Y'N = V,H or V,L
Vee = Min.
Y'N = V,H or V,L
loz
Off State (High Impedance)
Output Current
Vcc
los
Output Short Circuit Current
Vcc = Max., VOUT
10L
= Max.
=OVI3)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee
=S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
3-56
V
VLe
V
p.A
mA
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (CONT'D)
TA =O°C to +70°C
Vcc =5.0V ± 5%
TA = -55°C to +125°C
VLC = 0.2V
VHC = VCC - 0.2V
SYMBOL
ICCQH
leGaL
TEST CONDITIONS(1)
PARAMETER
Quiescent Power Supply Current
CP ~ H
Quiescent Power Supply Current
CP~L
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
Min. = 4.75V
Min. = 4.50V
Vcc = 5.0V ± 10%
MIN.
Vcc = Max.
VHC <: V'N' V'N <: VlC
TYP.(')
MAX.
UNIT
-
-
-
mA
Vcc ~ Max.
VHC ~ V1N , V1N :5 VLC
Icp~O, CP ~L
-
-
-
mA
-
-
-
Icp~O,CP~H
ICCT
Quiescent Input Power Supply(51
Current (per Input @ TTL High)
Vcc ~ Max. V'N ~ 304V, Icp ~ 0
Vcc ~ Max.
VHC <: V'N, V'N <: VlC
Outputs Open, OE ~ L
-
-
-
Dynamic Power Supply Current
MIL.
ICCD
COM'L.
-
-
-
Vcc ~ Max., Icp ~ 10MHz
Outputs Open, OE ~ L
CP ~ 50% Duty cycle
VHC :5 V,N , V1N :5 VLC
MIL.
-
-
-
COM'L.
-
-
-
Vcc ~ Max., Icp ~ 10MHz
Outputs Open, OE ~ L
CP ~ 50% Duty cycle
V'H ~ 304\1, V'l ~ Oo4V
MIL.
-
-
55
COM'L.
-
-
45
Icc
Total Power Supply Currentl 6}
mAl
Input
mAl
MHz
mA
NOTES:
5. feeT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out I CCQH ' then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply Current
can be calculated by using the following equation:
Icc ~ ICCOH(CDHI + ICCOl (1 - CDHI + ICCT (NT' DHI + ICCD (fcpl
CD H = Clock duty cycle high period.
DH =Data duty cycle TTL high period (V'N =3.4VI.
NT'" Number of dynamic inputs driven at TTL levels.
fcp = Clock Input frequency.
3-57
IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C09A1IDT39C11A SWITCHING
CHARACTERISTICS OVER OPERATING RANGE
TABLE III
GUARANTEED SET-UP AND HOLD TIMES(1)
Table I, II and III below define the timing characteristics of the
IDT39C09A/11A over the operating voltage and temperature
range. The tables are divided into three types of parameters: clock
characteristics, combinational delays from inputs to outputs, and
set-up and hold time requirements. The latter table defines the
time prior to the end of the cycle (i.e., clock LOW-to-HIGH transition) that each input must be stable to guarantee that the correct
data is written into one of the internal registers.
Measurements are made at 1.5V with VIL =OV and VIH =3.0V. For
three-state disable tests, C L = 5.0pF and measurement is to O.5V
change on output voltage level. All outputs have maximum DC
loading.
TIME
COMMERCIAL
MILITARY
20
20
Minimum Clock HIGH Time
20
20
SET-UP
TIME
HOLD
TIME
SET-UP
TIME
HOLD
TIME
19
4
19
5
ns
R(2)
10
4
12
5
ns
PUP
25
4
27
5
ns
FE
25
4
27
5
ns
Cn
18
4
18
5
ns
DI
25
0
25
0
ns
OR;
25
0
25
0
ns
80> 8,
25
0
29
0
ns
ZERO
25
0
29
0
ns
NOTES
1. All times relative to clock LOW-ta-HIGH transition.
2. On IDT39C11, Ri and D j are internally connected together and labeled
Use R! set-up and hold times when D inputs are used to load register.
TABLE II
MAXIMUM COMBINATIONAL
PROPAGATION DELAYS
C L = 50pF (except output disable test)
COMMERCIAL
FROM INPUT
Y
MILITARY
Y
Cn + 4
Cn + 4
UNITS
D;
17
22
20
25
ns
8 0,8,
29
34
29
34
ns
OR;
17
22
20
25
ns
Cn
-
14
-
16
ns
ZERO
29
34
30
35
ns
OE LOW (enable)
25
-
25
-
ns
OE HIGH (disable)I')
25
-
25
-
ns
t 8,8 0 = LH
Clock t 8,8 0 = LL
Clock t 8,8 0 = HL
39
44
45
50
ns
39
44
45
50
ns
44
49
53
58
ns
Clock
NOTE:
1. CL =5pF
r(T~BtE 1)1
~\TO'CLOCKH\~
L OCCURS
i--(T1Bfe 1)-1
~
CP
I ,-
I
ALL INPUTS
(EXCEPTOE)
fr----
ANYTIME
HE~
I-
(TABLE III)
I~
I
I CLOCK TO Y OR Cn+4Ii-= (TABLEI II)
YOUT
Cn+4
________
UNITS
RE
I
TABLE I
CYCLE TIME AND CLOCK CHARACTERISTICS
Minimum Clock LOW Time
MILITARY
COMMERCIAL
FROM INPUT
I
• -
3.0V
1.5V
OV
•
hTAB~E III)
m:~:
:
INPUTS TO Y OR Cn+4
- .
(TABLE II)
~------------ ~~~
VOL
~~~~~~~~~~~LK~______________________
MSD39C09-OO7
3-58
°
1_
IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEOUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C09B/IDT39C11B SWITCHING
CHARACTERISTICS OVER OPERATING RANGE
TABLE III
GUARANTEED SET-UP AND HOLD TIMES(1)
Table I, II and III below define the timing characteristics of the
IDT39C09B/11 B over the operating voltage and temperature
range. The tables are divided into three types of parameters: clock
characteristics, combinational delays from inputs to outputs, and
set-up and hold time requirements. The latter table defines the
time prior to the end of the cycle (i.e., clock LOW-to-HIGH transition) that each input must be stable to guarantee that the correct
data is written into one of the internal registers.
Measurements are made at 1.5V with V,L ~ OV and V,H ~ 3.0V. For
three-state disable tests, C L ~ 5.0pF and measurement is to O.5V
change on output voltage level. All outputs have maximum DC
loading.
COMMERCIAL
FROM INPUT
TABLE I
CYCLE TIME AND CLOCK CHARACTERISTICS
TIME
COMMERCIAL
-
-
Minimum Clock HIGH Time
-
-
MILITARY
HOLD
TIME
SET-UP
TIME
~
-
-
-
-
ns
-
-
-
-
ns
PUP
-
-
-
-
ns
FE
-
-
-
-
ns
Co
-
-
-
-
ns
D,
-
-
-
-
ns
OR;
-
-
-
-
ns
5 0 ,5,
-
-
-
-
ns
ZERO
-
-
-
-
ns
1. All times relative to clock lOW-te-HIGH transition
2. On IDT39C11, RI and 01 are il)ternally connected together and labeled 0 ,_
Use AI set-up and hold times when 0 inputs are used to load register.
50pF (except output disable test)
COMMERCIAL
FROM INPUT
Y
D;
-
-
5 0,5,
-
-
OR;
-
-
Co
-
-
ZERO
-
OE LOW (enable)
OE HIGH (disable}I')
Clock
Clock
Clock
I 5,5 0 ~ LH
I 5,5 0 = LL
I 5,5 0 = HL
MILITARY
Cn + 4
Y
-
UNITS
Cn + 4
-
ns
-
ns
-
ns
.-
-
ns
~
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
-
-
-
-
ns
NOTE:
1. C L = 5pF
I:=(T~'B~ 1)-1
1
ALL INPUTS
(EXCEPTOE)
____
r(T~B~E 1)1
~1.~J~~
cPJ
14
I~
~
~LL~UU~LL~~
I
CLOCK TO Y, OR
(TABLE II)
j.=
cn+.I" .
UNITS
RE
R;12)
TABLE II
MAXIMUM COMBINATIONAL
PROPAGATION DELAYS
CL
HOLD
TIME
NOTES:
MILITARY
Minimum Clock LOW Time
SET-UP
TIME
(TABLE III)
Iflr---- :~~
• • • hTABrE III)
________________
'AmJ...
<00<»'_ 10~V::
~~~
:- I. INPUTS(TABLE
TO Y OR C +.
II)
n
YOUT
VOH
_ _- - - - - - - - - - - 1 . 5 V
________ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
VOL
~~UL~~UL~~UL~~UL~_______________________
3-59
IDT39C09A1B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
TEST LOAD CIRCUIT
GND to 3.0V
1V/ns
1.SV
1.SV
See Figure 1
Vee
1470
....
VOUT ---<~----
SWITCHING WAVEFORMS
750
3.0V----_""
INPUTS
OV _ _ _ _ _UJ
3.0V
CLOCK
OV
Figure 1. Swllchlng Test Circuit
(all oulputs)
OUTPUTS
INPUT/OUTPUT INTERFACE CIRCUITRY
Vee
--
INPUTS o-~""'~""'-i>O-
OUTPUTS
IoL
IDT49C41D-007
IOT49C41Q.OOa
Figure 1. Input Structure (AI/Inputs)
Figure 2. Output Structure (All Outputs)
3-60
MICROSLlCpM PRODUCT
FEATURES:
program sequencers are intended for use in controlling the
sequence of microinstructions executed in the microprogram
memory. The IDT39C10s provide several conditional branch
instructions that allow branching to any microinstruction within
the4K microword address space. A 33-deep last-in, first-out stack
provides for a very powerful microprogram subroutine return
linkage and looping capability. With this depth of a microprogram return stack, the microprogrammer has maximum flexibility in nesting subroutines and loops. The counter contained in
the IDT39C10s provides for microinstruction loop counts of up to
4096, in terms of total count length.
The IDT39C10s provide a 12-bit address to the microprogram
memory. This microprogram sequencer selects one of four
sources for the address: these are (1) the microprogram address
register, (2) external direct input, (3) internal register counter, and
(4) the 33-deep LIFO stack. The microprogram counter usually
contains an address that is one greater than the microinstruction
currently being executed in the microprogram pipeline register.
The IDT39C10s are fabricated using CEMOS, a single-poly
double metal CMOS technology designed for high-performance
and high-reliability. The devices are pin-compatible, performanceenhanced, functional replacements for the 2910A.
• Low-power CEMOS'·
-Icc (max.)
Military - 90mA
Commercial - 75mA
• Fast
-IDT39C10B matches 2910A speeds
-IDT39C10C 30% speed upgrade
• 33-Deep stack
-Accommodates highly nested loops and subroutines
microcode
•
•
•
•
•
•
12-bit address width
12-bit internal loop counter
16 powerful microinstructions
3 enables control branch address sources
Available in 40-pin DIP and 44-pin LCC
Military product available 100% screened to MIL-STD-883,
Class B
DESCRIPTION:
The IDT39C10 microprogram sequencers are designed for use
in high-performance microprogram state machines. These micro-
FUNCTIONAL BLOCK DIAGRAM
0,
RLD
CP
0--------1
FUll
DECREMENTI
HDLD/LOAD
R=O
CC
CCEN
L-r--.....c,
0Ec=>----~-~-~----~
Pi:
MAP
VECT
v,
IDT39C10B-001
MICROSLICE and CEMOS are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~ 1986 Integrated
JUNE 1986
Printed In U.S.A.
Device Technology, Inc.
3-61
II
IDT38C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
D4
Y4
D3
Y3
D2
VE§f
~~
Ys
p[
ir.iP
13
12
p[
~
;.ms
Do
YO
13
12
11
10
CCiN
CC
iiLD
PUll.
D,
Y,
Dr
11
---'.I!
CCEN
CC
RLD
NC
Y,
De
Y,
Yr --"""-_ _~DIP
TOP VIEW
De
IDT39C10B-003
LCC
TOP VIEW
IOT39C1OB-002
PIN FUNCTIONS
PIN NAME
Yo
NC
CI
CP
GND
NC
OE
Y11
D11
Vee
CI
CP
GND
OE
Y11
D11
Y10
D10
VCe
Y1
Do
DESCRIPTION
FUNCTION
01
Direct Input Bit i
Direct input to register/counter
and multiplexer Do is LSB.
Ii
Instruction Bit I
Selects one-ol-sixteen
instructions.
CC
Condition Code
Used as test criterion. Pass test is
a LOW on CC.
CCEN
Condition Code
Enable
Whenever the Signal is HIGH, CC
Is ignored and the part operates
as though CC were true (LOW).
CI
Carry-In
Low order carry input to incrementer lor microprogram counter.
RLD
Register Load
When LOW lorces loading 01
register/counter regardless 01
Instruction or condition.
OE
Output Enable
Three-state control 01 Vi outputs.
CP
Clock Pulse
Triggers all internal state changes
at LOW-to-HIGH edge.
Vee
5 Volts
GND
Ground
VI
Microprogram
Address Bit i
Address to microprogram
memory. Vo is LSB, V'1 Is MSB.
FULL
Full
Indicates that 33 items are on the
stack.
PL
Pipeline Address
Enable
Can select #1 source (usually
Pipeline Register) as direct input
source.
MAP
Map Address
Enable
Can select #2 source (usually
Mapping PROM or PLA) as direct
input source.
VECT
Vector Address
Enable
Can select #3 source (lor exampie, Interrupt Starting Address) as
direct input source.
3-62
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
PRODUCT DESCRIPTION
The I DT39C1 Os are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed microprogrammable microprocessor applications. The sequencers
allow for direct control of up to 4K words of microprogram.
The heart of the microprogram sequencers is a 4-input multiplexer that is used to select one of four address sources to select
the next microprogram address. These address sources include
the register/counter, the direct input, the microprogram counter
or the stack as the source for the address of the next microinstruction.
The register/counter consists oltwelve D-typeflip-flops which
can contain either an address or a count. These edge-triggered
flip-flops are under the control of a common clock enable as well
as the four microinstruction control inputs. When the load control (RLD) is LOW, the data at the D-inputs is loaded into this
register on the LOW-to-HIGH transition of the clock. The output
olthe register/counter is available at the multiplexer as a possible
next address source for the microcode. Also, the terminal count
output associated with the register/counter is available at the
internal instruction PLA to be used as a condition code input for
some of the microinstructions. The IDT39C10s contain a microprogram counter that usually contains the address of the next
microinstruction compared to that currently being executed. The
microprogram counter actually consists of a 12-bit incrementer
followed by a 12-bit register. The microprogram counter will
increment the address coming out of the sequencer going to the
microprogram memory if the carry-in input to this counter is
HIGH; otherwise, this address will be loaded into the microprogram counter. Normally, this carry-in input is set to the logic
HIGH state so that the incrementer will be active. Should the
carry-in input be set LOW, the same address is loaded into the
microprogram counter. This is a technique that can be used to
allow execution of the same microinstruction several times.
There are twelve D-inputs on the I DT39C1 Os that go directly to
the address multiplexer. These inputs are used to provide a
branch address that can come directly from the microcode or
some other external source. The fourth input available to the
multiplexer for next address control is the 33-deep, 12-bit wide
LIFO stack. The LIFO stack provides return address linkage for
subroutines and loops. The IDT39C10s contain a built-in stack
pointer that always points to the last stack location written. This
allows for stack reference operations, usually called loops, to be
performed without popping the stack.
The stack pointer internal to the IDT39C10s is actually an
up/down counter. During the execution of microinstructions
one, four and five, the PUSH operation may occur depending on
the state of the condition code input. This causes the stack
pointer to be incremented by one and the stack to be written with
the required return linkage (the value contained in the microprogram counter). On the microprogram cycle fOllowing the
PUSH, this new return linkage data that was in the microprogram
counter is now at the new location pointed to by the stack pointer.
Thus, any time the multiplexer looks at the stack, it will see this
data on the top of the stack.
During five different microinstructions, a pop operation associated with the stack may occur. If the pop occurs, the stack
pointer is decremented althe next LOW-to-HIGH transition olthe
clock. A pop decrements the stack pointer which is the equivalent of removing the old information from the top of the stack.
The I DT39C1Os are designed so that the stack pointer linkage
allows any sequence of pushes, pops or stack references to be
used. The depth of the stack can grow to a full 33 locations. After
a depth of 33 is reached, the FULL output goes LOW. If further
PUSHes are attempted when the stack is full, the stack information at the top of the stack will be destroyed but the stack pointer
will not end around. It is necessary to initialize the stack pointer
when power is first turned on. This is performed by executing a
RESET instruction (Instruction 0). This sets the stack pointer to
the stack empty position-the equivalent depth of O. Similarly, a
pop from an empty stack may place unknown data on the Y
outputs, but the stack pointer is designed so as not to end
around. Thus, the stack pointer will remain at the 0 or stack
empty location if a pop is executed while the stack is already
empty.
The IDT39C10s' internal 12-bit register/counter is used during
microinstructions eight, nine and fifteen. During these instructions, the 12-bit counter acts as a down counter and the terminal
count (count = 0) is used by the internal instruction PLA as an
input to control the microinstruction branch test capability. The
design of the internal counter is such that if it is preloaded with a
number N, and then this counter is used in a microprogram loop,
the actual sequence in the loop will be executed N + 1 times.
Thus, it is possible to load the counter with a count of 0 and this
will result in the microcode being executed one time. The 3-way
branch microinstruction, Instruction 15, uses both the loop counter and the external condition code input to control the final
source address from the Y outputs of the microprogram
sequencer. This 3-way branch may result in the next address
coming from the D inputs, the stack or the microprogram
counter.
The IDT39C10s provide a 12-bit address at the Y outputs that
are under control olthe OE input. Thus, the outputs can be put in
the three-state mode, allowing the writeable control store to be
loaded or certain types of external diagnostics to be executed.
In summary, the IDT39C10s are the most powerful microprogram sequencers currently available. They provide the deepest
stack, the highest performance, and the lowest power dissipation
for today's microprogrammed machine design.
3-63
I
IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIGURE 1. IDT39C10B FLOW DIAGRAMS
o Jump Zero (JZ)
1 Cond JSB PL (CJS)
2 Jump Map (JMAP)
66
65f:1
~
67
68
69
70
3 Cond Jump PL (CJP)
4 Pu.h/Cond LD CNTR (PUSH)
6 Cond Jump Vector (CJV)
~
66
67
68
69
32
33
34
66
65h
72
42
43
44
67
68
35
36
69
65
30I/70~40
31
71
41
7 Cond JUMP R/PL (JRP)
5
~~
5 Cond JSB R/PL (JSRP)
66 t < : : 8 STACK
67
68
REGISTER/
N COUNTER
25
26
"
*-;86
65
65h
66
67
68
69
E!
STACK
40
41
42
43
20
21
8 Repeat Loop, CNTR "" 0 (RFCT)
T 30
T31
9 Repea! PL, CNTR .;. 0 (RPCT)
10 Cond Retum (CRTN)
STACK
(PUSH)
65
REGISTER/
COUNTER
66
67
68
69
65
66
67
68
~
N
COUNTER
(LDCT)
66
67
68
69
70
70
11 Cond Jump PL & POP (CJPP)
12 LD CNTR & Continue (LDCT)
(t)-+----.. 40
68
69
41
42
65 ~COUNTER
66
67
68
14 Continue (CO NT)
15 Three-Way Branch (TWB)
t
65~7
67
68
32
33
34
37
66
67
70
71
30
31
35
36
STACK
(PUSH)
65
66
65
65
66
67
68
69
STACK
(PUSH)
REGISTER/
N COUNTER
72
73
3-64
13 Test End Loop (LOOP)
65
66
67
68
69
70
71
72
STACK
(PUSH)
IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 OPERATION
The IDT39C10s are CMOS pin-compatible implementations of
the Am2910 & 2910A microprogram sequencers. The IDT39C10s'
microprogram is functionally identical except that it provides a
33-deep stack to give the microprogrammer more capability in
terms of microprogram subroutines and microprogram loops.
The definition of each microprogram instruction is shown in the
table of instructions. This table shows the results of each instruction in terms of controlling the multiplexer which determines the
Y outputs, and in controlling the signals that can be used to
enable various branch address sources (PL, MAP, VECT). The
operation of the register/counter and the 33-deep stack after the
next LOW-to-HIGH transition of the clock are also shown. The
internal multiplexer is used to select which olthe internal sources
is used to drive the Y outputs. The actual value loaded into the
microprogram counter is either identical to the Y output or the Y
output value is incremented by 1 and placed in the microprogram
counter. This function is under the control of the carry input. For
each of the microinstruction inputs, only one of the three outputs
(PL, MAP or VECT) will be Law. Note that this function is not
determined by any of the possible condition code inputs. These
outputs can be used to control the three-state selection of one of
the sources for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the conditional instructions. These are fully defined in the table of instructions. The RLD input can be used to load the internal register/
counter at any time. When this input is LOW, the data at the 0
inputs will be loaded into this register/counter on the LOW-toHIGH transition of the clock. Thus, the RLD input overrides the
internal hold or decrement operations specified by the various
microinstructions. The OE input is normally LOW and is used as
the three-state enable for the Y outputs. The internal stack in the
IDT39C10s is a last-in, first-out memory that is 12-bits in width
and 33 words deep. It has a stack pointer that addresses the stack
and always points to the value currently on the top of the stack.
When instruction 0 (RESET) is executed, the stack pointer is
initialized to the top of the stack which is, by definition, the stack
empty condition. Thus, the contents of the top of the stack are
undefined until the forced PUSH occurs. A pop performed while
the stack is empty will not change the stack pointer in any way;
however, it will result in unknown data at the Y outputs.
By definition, the stack is full any time 33 more PUSHes than
pops have occurred since the stack was last empty. When this
happens, the FULL flag will go LOW. This signal first goes LOW
on the microcycle after the 33 pushes occur. When this signal is
LOW, no additional pushes should be attempted or the information on the top of the stack will be lost.
nal instruction PLA uses the four instruction inputs as well as the
CC, CCEN and the internal counter = 0 line for controlling the
sequencer. This internal instruction PLA provides all of the
necessary internal control signals to control each particular part
of the microprogram sequencer. The next address at the Y outputs of the IDT39C10s can be from one of four sources. These
include the internal microprogram counter, the last-in first-out
stack, the register/ counter and the direct inputs.
The following paragraphs will describe each instruction associated with the IDT39C10s. As a part of the discussion, an example
of each instruction is shown in Figure 1. The purpose of the
examples is to show microprogram flow. Thus, in each example
the microinstruction currently being executed has a circle
around it. That is, this microinstruction is assumed to be the
contents of the pipeline register at the output of the microprogram memory. In these drawings, each of the dots refers to the
time that the contents of the microprogram memory word would
be in the pipeline register and currently being executed.
INSTRUCTION 0JUMP 0 (JZ)
This instruction is used at power-up time or at any restart
sequence when the need is to reset the stack pointer and jump to
the very first address in microprogram memory. The jump 0
instruction does not change the contents of the register/counter.
INSTRUCTION 1CONDITIONAL JUMP TO SUBROUTINE (CJS)
The conditional jumpto subroutine instruction is the one used
to call microprogram subroutines. The subroutine address will
be contained in the pipeline register and presented at the 0
inputs. If the condition code test is passed, a branch is taken to
the subroutine. Referring to the flow diagram for the IDT39C10s
shown in Figure 1, we see that the contents of the micrQProgram
counter is 68. This value is pushed onto the stack and the top of
stack pointer is incremented. If the test is failed, then this conditional jump to subroutine instruction behaves as a simple continue. That is, the contents of microinstruction address 68 is
executed next.
INSTRUCTION 2JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction
opcode. This is typically accomplished by using a mapping
PROM as an input to the 0 inputs on the microprogram
sequencer. The JMAP instruction branches to the address
appearing on the 0 inputs. In the flow diagram shown in Figure 1,
we see thatthe branch actually will be to the contents of microinstruction 85 and this instruction will be executed next.
THE IDT39C10 INSTRUCTION SET
This data sheet contains a block diagram of the IDT39C10
microprogram sequencers. As can be seen, the devices are controlled by a 4-bit micrOinstruction word (13-10), Normally, this
word is supplied from one 4-bit field of the microinstruction word
associated with the entire state machine system. These four bits
provide for the selection of one of the sixteen powerful instructions associated with selecting the address of the next microinstruction. Unused Y outputs can be left open; however, the corresponding most significant 0 inputs should be tied to ground for
smaller microwords. This is necessary to make sure the internal
operation of the counter is proper should less than 4K of microcode be implemented. As shown in the block diagram, the inter-
INSTRUCTION 3CONDITIONAL JUMP PIPELINE (CJP)
The simplest branching control available in the IDT39C10
microprogram sequencers is that of conditional jump to address.
In this instruction, the jump address is usually contained in the
microinstruction pipeline register and presented to the 0 inputs.
If the test is passed, the jump is taken while, if the test fails, this
instruction executes as a simple continue. In the example shown
in the flow diagrams of Figure 1, we see that if the test is passed,
the next microinstruction to be executed is the contents of
address 25. If the test is failed, the microcode simply continues to
the contents of the next instruction.
3-65
I
IDT39C10B!C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 INSTRUCTION OPERATIONAL SUMMARY
13-10
MNEMONIC
CC
COUNTER
TEST
STACK
ADDRESS
SOURCE
REGISTER!
COUNTER
ENABLE
SELECT
0
JZ
X
X
CLEAR
0
NC
PL
1
CJS
PASS
FAIL
X
X
PUSH
NC
D
PC
NC
NC
PL
PL
2
JMAP
X
X
NC
D
NC
MAP
3
CJP
PASS
FAIL
X
X
NC
NC
D
PC
NC
NC
PL
PL
4
PUSH
PASS
FAIL
X
X
PUSH
PUSH
PC
PC
LOAD
NC
PL
PL
5
JSRP
PASS
FAIL
X
X
PUSH
PUSH
D
R
NC
NC
PL
PL
6
CJV
PASS
FAIL
X
X
NC
NC
D
PC
NC
NC
VECT
VECT
7
JRP
PASS
FAIL
X
X
NC
NC
D
R
NC
NC
PL
PL
8
RFCT
X
X
=0
NOT =0
POP
NC
PC
STACK
NC
DEC
PL
PL
9
RPCT
X
X
=0
NOT =0
NC
NC
PC
D
NC
DEC
PL
PL
10
CRTN
PASS
FAIL
X
X
POP
NC
STACK
PC
NC
NC
PL
PL
11
CJPP
PASS
FAIL
X
X
POP
NC
D
PC
NC
NC
PL
PL
12
LDCT
X
X
NC
PC
LOAD
PL
13
LOOP
PASS
FAIL
X
X
POP
NC
PC
STACK
NC
NC
PL
PL
14
CO NT
X
X
NC
PC
NC
PL
TWB
PASS
PASS
FAIL
FAIL
=0
NOT = 0
=0
NOT= 0
POP
POP
POP
NC
PC
PC
D
STACK
NC
DEC
NC
DEC
PL
PL
PL
PL
15
NC = no change; DEC = decrement
INSTRUCTION 4PUSH/CONDITIONAL LOAD COUNTER (PUSH)
address Is taken from the internal register/counter. An example
of this is shown in the flow diagram of Figure 1.
With this instruction, the counter can be conditionally loaded
during the same instruction that pushes the current value of the
microprogram counter on to the stack. Under any condition
independent of the conditional testing, the microprogram
counter is pushed on to the stack. If the conditional test is
passed, the counter will be loaded with the value on the D inputs
to the sequencer. If the test fails, the contents of the counter will
not change. The PUSH/conditional load counter instruction is
used in conjunction with the loop instruction (Instruction 13),
the repeat file based on the counter instruction (I nstruction 9) or
the 3-way branch instruction (Instruction 15).
INSTRUCTION 6CONDITIONAL JUMP VECTOR (CJV)
The conditional jump vector instruction is similar to the jump
map instruction in that it allows a branch operation to a microinstruction as defined from some external source. This instruction
is similar to the jump map instruction except that it is conditional.
The jump map instruction is unconditional. If the conditional test
is passed, the branch is taken to the new address on the D inputs.
If the conditional test is failed, no branch is taken but rather the
microcode simply continues to the next sequential microinstruction. When this instruction is executed, the VECT output is LOW
unconditionally. Thus, an external 12-bit field can be enabled on
to the D inputs of the microprogram sequencer.
INSTRUCTION 5CONDITIONAL JUMP TO SUBROUTINE R/PL (JSRP)
INSTRUCTION 7CONDITIONAL JUMP RlPL (JRP)
Subroutines may be called by a conditional jump subroutine
from the internal register orfrom the external pipeline register. In
this instruction the contents of the microprogram counter are
pushed on the stack and the branch adddress for the SUbroutine
call will be taken from either the internal register/counter or the
external pipeline register presented to the D inputs. If the conditional test is passed, the subroutine address will be taken from
the pipeline register. If the conditional test fails, the branch
The conditional jump register/counter or external pipeline register always causes a branch in microcode. This jump will be to
one of two different locations in the microcode address space. If
the test is passed, the jump will be to the address presented on
the D inputs to the microprogram sequencer. If the conditional
test fails, the branch will be to the address contained in the
internal register/counter.
3-66
IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INSTRUCTION 8REPEAT LOOP COUNTER NOT EQUAL TO 0 (RFCT)
INSTRUCTION 13TEST END OF LOOP (LOOP)
This instruction utilizes the loop counter and the stack to
implement microprogrammed loops. The start address for the
loop would be initialized by using the PUSH/conditional load
counter instruction. Then, when the repeat loop instruction is
executed, if the counter is not equal to 0, the next microword
address will be taken from the stack. This will cause a loop to be
executed as shown in the Figure 1 flow diagram. Each time the
microcode sequence goes around the loop, the counter is
decremented. When the counter reaches 0, the stack will be
popped and the microinstruction address will be taken from the
microprogram counter. This instruction performs a timed wait or
allows a single sequence to be executed the desired number of
times. Remember, the actual number of loops performed is
equal to the value in the counter plus 1.
The test end of loop instruction is used as a last instruction in a
loop associated with the stack. During this instruction, if the
conditional test input is failed, the loop branch address will be
that on the stack. Since we may go around the loop a number of
times, the stack is not popped. If the conditional test input is
passed, then the loop is terminated and the stack is popped.
Notice that the loop instruction requires a PUSH to be performed
at the instruction immediately prior to the loop return address.
This is necessary so as to have the correct address on the stack
before the loop operation. It is for this reason that the stack
pointer always points to the last thing written on the stack.
INSTRUCTION 9REPEAT PIPELINE COUNTER NOT EQUAL TO 0 (RPCT)
The continue instruction is a simple instruction whereby the
address forthe microinstruction is taken from the microprogram
counter. This instruction simply causes sequential program flow
to the next microinstruction in microcode memory.
INSTRUCTION 14CONTINUE (CO NT)
This instruction is another technique for implementing a loop
using the counter. Here, the branch address for the loop is contained in the pipeline register. This instruction does not use the
stack in any way as a part of its implementation. As long as the
counter is not equal to 0, the next microword address will be
taken from the D inputs of the microprogram sequencer. When
the counter reaches 0, the internal multiplexer will select the
address source from the microprogram counter, thus causing the
microcode to continue on and leave the loop.
INSTRUCTION 15THREE WAY BRANCH (TWB)
The three-way branch instruction is used for looping while
waiting for a conditional event to come true. If the event does not
come true after some number of microinstructions, then a branch
is taken to another microprogram sequence. This is depicted in
Figure 1 showing the IDT39Cl0s' flow diagrams and is also
described in full detail in the IDT39Cl0s' instruction operational
summary. Operation of the instruction is such that any time the
external conditional test input is passed, the next microinstruction will be that associated with the program counter and the loop
will be left. The stack is also popped. Thus, the external test input
overrides the other possibilities. Should the external conditional
test input not be true, then the rest of the operation is controlled
by the internal counter. Ifthe counter is not equal toO, the loop is
taken by selecting the address on the top of the stack as the
address out of the Y outputs of the IDT39Cl0s. In addition, the
counter is decremented. Should the external conditional test
input be failed and the counter also have counted to 0, then this
instruction "times out." The result is that the stack is popped and
a branch is taken to the address presented to the D inputs of the
IDT39Cl0 microprogram sequencers. This address is usually
provided by the external pipeline register.
INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The conditional return instruction is used for terminating subroutines. The fact that it is conditional allows the subroutine
either to be ended orto continue. If the conditional test is passed,
the address of the next microinstruction will be taken from the
stack and it will be popped. If the conditional test fails, the next
microinstruction address will come from the internal microprogram counter. This is depicted in the flow diagram of Figure 1.
It is important to remember that every subroutine call must
somewhere be followed by a return from subroutine call in order
to have an equal number of pushes and pops on the stack.
INSTRUCTION 11CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The conditional jump pipeline and pop instruction is a technique for exiting a loop from within the middle of the loop. This is
depicted fully in the flowdiagramsforthe I DT39Cl0s as shown in
Figure 1. The conditional test inputforthis instruction results in a
branch being taken if the test is passed. The address selected will
be that on the D inputs to the microprogram sequencer and since
the loop is being terminated, the stack will be popped. Should the
test be failed on the conditional test inputs, the microprogram
will simply continue to the next address as taken from the microprogram counter. The stack will not be affected if the conditional
test input is failed.
CONDITIONAL TEST
Throughout this discussion we have talked about microcode
passing the conditional test. There are actually two inputs associated with the conditional test input. These include the CCEN
and the CC inputs. The CCEN input is a condition code enable.
Whenever the CCEN input is HIGH, the CC input is ignored and
the device operates as though the CC input were true (LOW).
Thus, a fail of the external test condition can be defined as CCEN
equals LOW and CC equals HIGH. A pass condition is defined as
a CCEN equal to HIGH or a CC equal to LOW. It is important to
recognize the full function of the condition code enable and the
condition code inputs in order to understand when the test is
passed or failed.
INSTRUCTION 12LOAD COUNTER AND CONTINUE (LDCT)
The load counter and continue instruction is used to place a
value on the D inputs in the register/counter and continue to the
next microinstruction.
3-67
&I
IDT39C10B!C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10 INSTRUCTIONS
1,-1 0
MNEMONIC
REG!
CNTR
CCEN
CONY
TENTS
NAME
PASS
FAIL
=LOW and CC =HIGH
CCEN
STACK
= HIGH or CC =LOW
Y
STACK
REG!
CNTR
ENABLE
PL
0
JZ
Jump Zero
X
0
CLEAR
0
CLEAR
HOLD
1
CJS
Cond JSB PL
X
PC
HOLD
0
PUSH
HOLD
PL
2
JMAP
Jump Map
X
0
HOLD
0
HOLD
HOLD
MAP
3
CJP
Cond Jump PL
X
PC
HOLD
0
HOLD
HOLD
PL
4
PUSH
PUSH/Cond Ld Cntr
X
PC
PUSH
PC
PUSH
Note 1
PL
5
JSRP
Cond JSB R/PL
X
R
PUSH
0
PUSH
HOLD
PL
6
CJV
Cond Jump Vector
X
PC
HOLD
0
HOLD
HOLD
VECT
7
JRP
Cond Jump R/PL
X
R
HOLD
0
HOLD
HOLD
PL
'"'0
=0
F
HOLD
F
HOLD
DEC
PL
PC
RFCT
8
Repeat Loop, CNTR '"' 0
a
POP
PC
POP
HOLD
PL
'"'0
=0
0
HOLD
0
HOLD
DEC
PL
PC
HOLD
PC
HOLD
HOLD
PL
9
RPCT
Repeat PL, CNTR '"'
10
CRTN
Cond RTN
X
PC
HOLD
F
POP
HOLD
PL
11
CJPP
Cond Jump PL & POP
X
PC
HOLD
0
POP
HOLD
PL
12
LDCT
LD Contr & Continue
X
PC
HOLD
PC
HOLD
LOAD
PL
13
LOOP
Test End Loop
X
F
HOLD
PC
POP
HOLD
PL
14
CONT
Continue
X
PC
HOLD
PC
HOLD
HOLD
PL
'"'0
=0
F
HOLD
PC
POP
DEC
PL
0
POP
PC
POP
HOLD
PL
15
TWB
NOTE: 1.1f CCEN
Three Way Branch
=LOW and CC =HIGH, hold; else load.
X =Don't Care.
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect
toGND
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
VALUE
UNIT
-0.5131 to +7.0
V
GRADE
Military
TA
Operating
Temperature
-55 to +125
·C
TBIAS
Temperature
Under Bias
-65 to +135
·C
TSTG
Storage
Temperature
-65 to +150
·C
Commercial
Power Dissipation (2)
1.0
W
lOUT
DC Output Current
into Outputs
30
rnA
GND
Vee
-55·C to +125·C
OV
5.0V ± 10%
O·C to +70·C
OV
S.OV±S%
CAPACITANCE
(TA = +2S0C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYp.
C IN
Input Capacitance
VIN = OV
5
pF
C OUT
Output Capacitance
VOUT= OV
7
pF
SYMBOL
PT
AMBIENT
TEMPERATURE
NOTE:
1. This parameter is sampled and not 100% tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other cond itions above those
indicated in the operational sections of this specification Is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. PT maximum can only be achieved by excessive IOl or IOH
3. VIL Min. = -3.0V for pulse width less than 20no.
3-68
UNIT
IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
TA = O°C to 'lO°C
VCC = +5.0V ± 5%
TA = -55°C to +125°C
Vcc = +5.0V ± 10%
Min. = +4.l5V
Min. = +4.50V
Max. = +5.25V (Commercial)
Max. = +5.50V (Military)
VLC = +0.2V
VHC = Vcc - 0.2V
TYP.(2)
MAX.
UNIT
V ,H
Input HIGH Level
Guaranteed Logic High Level(4)
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level!')
-
-
0.8
V
I'H
Input HIGH Current
Vce = Max .. Y'N = Vcc
0.1
5
p.A
I,L
Input LOW Current
Vce = Max., Y'N = GND
-
-0.1
-5
p.A
10H = -300p.A
VHC
Vcc
-
10H = -12rnA MIL.
2.4
4.3
-
10H = -15rnA COM'L.
2.4
4.3
-
SYMBOL
VOH
VOL
TEST CONDITIONS(1)
PARAMETER
Vec = Min.
Y'N = V,H or V,L
Output HIGH Voltage
Vce = Min.
Y'N = V,H or V,L
Output LOW Voltage
MIN.
10L = 300p.A
-
GND
10L = 20rnA MIL.
0.3
0.5
0.3
0.5
Vo= OV
-
-
-40
Vo = Vec
-
-
40
10L = 24rnA COM'L.
loz
los
011 State (High I rnpedance)
Output Current
Vce = Max.
Output Short Circuit Current
Vcc = Max., VOUT = OV(3)
leeoH
Quiescent Power Supply Current
CP = H
ICCOL
Quiescent Power Supply Current
CP=L
ICCOT
Quiescent Input Power Supply(5)
Current (per Input @ TTL High)
ICCD
Dynamic Power Supply Current
VHC "" VIN' VIN "" VLC
Icp = 0, CP = H
Vcc = Max.
VHC "" Y'N' VIN "" VLC
Icp=O,CP=L
Vcc = Max. VIN = 3.4V, I CP = 0
Total Power(6) Supply Current
-
VLC
-
-
-
rnA
-
-
-
rnA
-
-
-
MIL.
-
-
COM'L.
-
MIL.
-
-
-
COM'L.
-
-
-
MIL.
-
55
90
COM'L.
-
55
75
Vcc = Max., Fc = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VIH = 3.4\1, VIL = O.4V
p.A
rnA
VHC "" VIN' VIN "" VLC
Outputs Open, OE = L
VHC "" VIN' VIN "" VLC
V
-130
Vcc = Max.
Vce = Max., Fc = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
Icc
-30
Vcc = Max.
V
mAl
Input
mAl
MHz
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be statiC tested in a noise-free environment.
5. ICCQT is derived by measuring the total current with all the inputs tied together @3.4V. subtracting out ICCOH' then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply Current
can be calculated by using the following equation:
Icc = 'CCOH(CDH) + 'CCOL (1 - CDH) + 'CCT (NT
x
DH) + 'CCD (fcp)
CD H = Clock duty cycle high period.
DH
=Data duty cycle TTL high period (V ,N = 3.4V).
NT = Number of dynamic inputs driven at TTL levels.
f ep = Clock Input frequency.
3-69
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER
c L =50pF, TA =-55·C to +125·C (Military), O·C to +70·C (Commercial)
IDT39C10C AC ELECTRICAL CHARACTERISTICS
C L =50pF, TA = -55·C to +125·C (Military), O·C to +70·C (Commercial)
I. SET-UP AND HOLD TIMES
I. SET-UP AND HOLD TIMES
IDT39C10B AC ELECTRICAL CHARACTERISTICS
1(1)
INPUTS
COM'L.
I(h)
MIL.
COM'L.
MIL.
UNITS
1(1)
INPUTS
COM'L.
I(h)
MIL.
COM'L.
MIL.
UNITS
D,-R
16
16
0
0
ns
Dj-R
6
7
0
0
D,-PC
30
30
0
0
ns
OJ-PC
13
15
0
0
ns
10-3
35
38
0
0
ns
10 ••
23
25
0
0
ns
CC
24
35
0
0
ns
CC
15
18
0
0
ns
CCEN
24
35
0
0
ns
CCEN
15
18
0
0
ns
CI
18
18
0
0
ns
CI
6
7
0
0
ns
RLD
19
20
0
0
ns
RLD
11
12
0
0
ns
PL, VECT, MAP
FULL
II. COMBINATIONAL DELAYS
INPUTS
Y
COM'L.
MIL.
COM'L.
MIL.
ns
II. COMBINATIONAL DELAYS
COM'L.
MIL.
INPUTS
UNITS
PL, VECT, MAP
Y
COM'L.
MIL.
COM'L.
FULL
UNITS
MIL.
COM'L.
MIL,
-
ns
-
ns
-
ns
-
ns
Do."
20
25
-
-
-
-
ns
Do·"
12
15
-
-
10 ••
35
40
30
35
10 ••
20
25
13
15
30
36
-
ns
CC
16
20
-
-
CCEN
30
36
-
ns
CCEN
16
20
-
-
-
CP
40
46
-
31
35
ns
CP
28
33
-
-
22
25
ns
25/27
25/30
-
-
ns
CC
-
-
-
-
ns
10/10
13/13
-
-
-
-
ns
OElt)
OElt)
NOTE:
NOTE:
1. Enable/Disable. Disable times measuretoO.5V change on output voltage level
with C L = 5pF.
1. Enable/Disable. Disable times measure to O.5V change on output voltage level
with CL = 5pF.
III. CLOCK REQUIREMENTS
III. CLOCK REQUIREMENTS
COM'L.
MIL.
UNITS
COM'L.
MIL.
UNITS
Minimum clock LOW time
20
25
ns
Minimum clock LOW time
18
20
ns
Minimum clock HIGH time
20
25
ns
Minimum clock HIGH time
17
20
ns
Minimum clock period
50
51
ns
Minimum clock period
35
40
ns
AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDt03.0V
1V/ns
1.5V
1.5V
See Fig. 3
IDT39C10B INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
VCC~
INPUTS
-
0-----''''''''--1>--1>-hL
4
1470
VOUT
fIoL
IDT39Cl0B-007
---<~-----+
OUTPUTS
CL
I
sOp_
750
IDT39C10B-008
MS039C60-013
Figure 1. Inpul Siruciure (All Inputs)
Figure 2, Oulpul Siructure (All Oulpuls)
3-70
Figure 3. Oulpul Load Circuli
FEATURES:
DESCRIPTION:
• Fast
-I DT39C203 matches 29203 speeds
-IDT39C203A 20% speed upgrade
The IDT39C203s are four-bit expandable, high-performance
CMOS microprocessor slices. Along with the standard features
associated with the IDT39COls and IDT39C03s, the IDT39C203s
also incorporate additional enhancements for arithmeticoriented processors.
These extremely low-power yet high-speed three-port threeaddress architectured microprocessors consist of a 16-word by
4-bit dual-port RAM with latches on both outputs, highperformance ALU and shifter, a flexible Q Register with shifter
input, and nine-bit instruction decoder. Additionally, special
instructions which allow the easy implementation of multiplication, division, normalization, BCD arithmetic and conversion
are standard on the IDT39C203s. Both devices are easily
expandable in 4-bit increments.
They are pin-compatible, functional replacements for all
versions of the 29203. The fastest version, the IDT39C203A, is a
20% speed upgrade from the normal 29203 device. The
IDT39C203 meets the 29203 speeds.
The IDT39C203s are fabricated using CEMOS~, a single-poly,
double metal CMOS technology designed for high-performance
and high-reliability.
Military product is 100% screened to MIL-STD-883, Class B,
making them ideally suited to military temperature applications.
•
•
•
•
•
Low-power CMOS
-Commercial - 60mA (max.)
-Military -70mA (max.)
Pin-compatible, performance-enhanced functional
replacement for the 29203
Cascadable to 8,12,16, etc. bits
Infinitely expandable register file
Improved I/O capability
-DA, DB and Y ports are bidirectional
•
Performs BCD arithmetic
-Features automatic BCD add, subtract and
conversion between binary and BCD
• On-chip parity generation and sign extension logic
- Provides parity across the entire ALU output and sign
extension at any slice boundary
• On-chip normalization logic
-Floating point mantissa and exponent easily developed
using single microcycle per shift
• On-chip multiplication and division logic
•
•
•
Two bidirectional data lines
Packaged in 48-pin DIP and 52-pin LCC
Military product available 100% screened to MIL-STD-883,
Class B
PIN CONFIGURATIONS
QI~
EA
a ..
c.r.;: .eIC 2 2 .... ~ aD.
zCCCCWOOlDlDlDlDU
DAo
DA,
DA2
DA3
U
7 L.I L.I 1..1 U L.I
12
13
I.
Cn
654
~ ..
32
I I U
&...... lui L.I
U 5251504948
,
'''4
46::
12
13
I.
Cn
Cn + 4
_C n + 4
P/OYR
I¥OYR
GND
GND
'C'/N
GIN
OEY
OEY
YO
Y,
Y2
Yo
Y,
Y2
NC
Y3
SIO o
SI0 3
Z
DBo
DB,
LCC
TOPYIEW
DIP
TOP VIEW
CEMOS and MICROSllCE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.1986 Integrated Device Technology. Inc.
MSD39C203--002
JULY 1986
Printed in U.S.A.
3-71
I
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C203I1DT39C203A 4-BIT CMOS MICROPROCESSOR SLICE
FUNCTIONAL BLOCK DIAGRAM
4
A._.
7
,4
o
B._.
WE
lEN
OEB
DB._.
4
EA
DA._.
Cn + 4
Cn
G/N
P/OVR
SIO.
SIO.
QIO.
010.
OEY~>---------------~----~
1.-8~.
PLA.
WRITE/MSS
t·
TOPLA
LSS
lEN Z
3-72
MICROSLlCFM PRODUCT
FEATURES:
DESCRIPTION:
• Low Power CEMOS
- Military - 100mA (max.)
- Commercial - 85mA (max.)
The IDT39C60 family are high-speed, low-power, 16-bit Error
Detection and Correction Units which generate check bits on a
16-bit data field according to a modified Hamming Code and
COfrect the data word when check bits are supplied. When performing a read operation from memory, the IDT39C60s will
correct 100% of all single bit errors, will detect all double bit errors
and some tri pie bit errors.
The IDT39C60s are easily cascadable from 16 bits up to 64 bits.
Sixteen-bit systems use 6 check bits, 32-bit systems use 7 check
bits and 64-bit systems use 8 check bits. For all three configurations, the error syndrome is made available.
All incorporate 2 built-in diagnostic modes. Both simplify testing by allowing for diagnostic data to be entered into the device
and to execute system diagnostic functions.
The IDT39C60s are pin-compatible, performance-enhanced
functional replacements for all versions of the 2960. They are
fabricated using CEMOS'", a single poly, double metal CMOS
technology designed for high-performance and high-reliability.
The devices are packaged in either 48-pin DIPs or 48-pin and
52-pin LCCs. Military product is 100% screened to MIL-STD-883,
Class B, making them ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
• Fast
- Data in to error detect
IDT39C60A - 20ns (max.), IDT39C60-1 - 25ns (max.)
IDT39C60 - 32ns (max.)
- Data in to corrected data out
IDT39C60A - 30ns (max.). IDT39C60-1 - 52ns (max.)
IDT39C60 - 65ns (max.)
• Improves system memory reliability
- Corrects all single-bit errors, detects all double and some
triple-bit errors
• Cascadable
- Data words up to 64-bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Available in 48-pin DIP, 52-pin LCC, as well as space-efficient
48-pin SHRINK-DIP (70 mil pin centers) and 48-pin LCC
• Pin-compatible, functional equivalent to all versions of the 2960
• Military product available 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
LEOUTC>------------,
0..------,
OE BYTE 0
CBO-6
DATAo_7
D'+~------.___+--------------------------___,
~~l-.......ro;;;;:;(tjiTl
DATAs_15 ICI-(H't4.~~::.J
OE BYTE 1 O>--H-t------'
MULTERROR
LEOIAG
CODEID
DIAG MODE
PASS THRU
~4;f==:r==~,
C
D~'----o-l
0------0-1
GENERATEl::l~----<~
CORRECT
MSD39C60-001
O---IL__J
CEMOS and MICROSUCE are trademarks of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
JULY 1986
Printed in U.S.A.
1986 Integrated Device Technology, Inc.
3-73
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
CORRECT
DATA1S
DATA14
DATA13
DATA12
LEIN
LE D1AG
OEBYTE1
DATA11
DATA10
DATAg
DATAa
GND
DATA7
DATA6
DATAs
DATA4
OE BYTEO
LEOUT
DATA3
DATA2
DATA1
DATAO
SC1
PASSTHRU
DIAGMODE1
DIAG MODEO
CODEID2
CODE ID1
CODE IDo
GENERATE
CB6
CBO
CBs
CB4
CB3
Vee
CB2
CB1
MULTERROR
ERROR
OEse
SCo
SCs
SC3
SC2
SC4
SC6
GENERATE
CB6
CBO
CBs
CB4
CB3
Vee
CB2
CB1
MULTERROR
ERROR
OEse
LEOIAG
OE BYTE1
DATA11
DATA10
DATAg
DATAa
GND
DATA7
DATA6
DATAs
DATA4
OE BYTEo
MS039C6o-003
LCC
TOP VIEW
(560 mil x 650 mil)
MSD39C60...(J02
DIP
TOP VIEW
(600 mil x 100 mil CENTERS)
(400 mil x 70 mil CENTERS)
NC
GENERATE
CB6
CBO
CBs
CB4
CB3
Vee
CB2
CB1
MULTERROR
ERROR
OEse
LEOIAG
OE BYTE1
DATA11
DATA10
DATAg
DATAa
GND
DATA7
DATA6
DATAS
DATA4
OE BYTEO
NC
MSD39C60-004
LCC
TOP VIEW
(750 mil x 750 mil)
3-74
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
PIN DESCRIPTIONS
PIN NAME
----_.
I/O
I/O
DATA D_'5
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION
16 bidirectional data lines. They provide input to the. Data Input Latch, and receive output from the Data Output
Latch. DATAo is the least significant bit; DATA 15 the most significant.
CB D_6
1-:------ --
I
-~-.
-_._-
Seven check bit input lines. The check bit lines are used to input check bits for error detection. Also used to input
syndrome bits for error correction in 32- and 64-bit configurations.
--
-----------
LE'N
I
Latch Enable - Data Input Latch. Controls latching of the input data. When HIGH, the Data Input Latch and Check
Bit Input Latch follow the input data and input check bits. When LOW, the Data Input Latch and Check Bit Input
GENERATE
I
Generate Check Bits input. When this input is LOW, the EDC is in the Check Bit Generate mode. When HIGH, the
EDC is in the Detect mode or Correct mode. In the Generate mode the circuit generates the check bits or partial
check bits specific to the data in the Data Input Latch. The generated check bits are placed on the SC outputs. In the
Detect or Correct modes the EDC detects single and multiple errors, and generates syndrome bits based upon the
contents of the Data Input Latch and Check Bit Input Latch. In Correct mode, single-bit errors are also automatically
corrected -corrected data is placed at the inputs of the Data Output Latch. The syndrome result is placed on the SC
SC D_6
0
Syndrome/Check Bit outputs. These seven lines hold the check/partial-check bits when the EDC is in Generate
mode, and will hold the syndrome/partial syndrome bits when the device is in Detect or Correct Modes. These are 3state outputs.
OEsc
I
Output Enable - Syndrome/Check Bits. When LOW, the 3-state output lines SC D_6 are enabled. When HIGH, the SC
Latch are latched to their previous state.
_._----_._---------
outputs and indicates, in a coded form, the number of errors and the bit-in-error.
outputs are in the high impedance state.
ERROR
0
Error Detected output. When the EDC is in Detect or Correct Mode, this output will go LOW if one or more
syndrome bits are asserted, meaning there are one or more bit errors in the data or check bits. If no syndrome bits
are asserted, there are no errors detected and the output will be HIGH. In Generate mode, ERROR is forced HIGH.
(In a 64-bit configuration, ERROR must be implemented externally.)
MULT ERROR
0
Multiple Errors Detected output. When the EDC is in Detect or Correct mode, this output if LOW indicates that there
are two or more bit errors that have been detected. If HIGH, this indicates that either one or no errors have been
detected. In Generate mode, MULT ERROR is forced HIGH. (In a 64-bit configuration, MULT ERROR must be
implemented externally.)
CORRECT
I
Correct input. When HIGH, this signal allows the correction network to correct any single-bit error in the Data Input
Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the EDC will
drive data directly from the Data Input Latch to the Data Output Latch without correction.
LEoUT
I
Latch Enable - Data Output Latch. Controls the latching of the Data Output Latch. When LOW, the Data Output
Latch is latched to its previous state. When HIGH, the Data Output Latch follows the output of the Data Input Latch
as modified by the correction logic network. In Correct mode, single-bit errors are corrected by the network before
loading into the Data Output Latch. In Detect mode, the contents of the Data Input Latch are passed through the
correction network unchanged into the Data Output Latch. The inputs to the Data Output Latch are disabled with its
contents unchanged if the EDC is in Generate mode.
OE BYTE D
OE BYTE,
I
Output Enable - Bytes 0 and 1, Data Output Latch. These lines control the 3-state outputs for each of the two bytes
of the Data Output Latch. When LOW, these lines enable the Data Output Latch, and when HIGH these lines force
the Data Output Latch into the high impedance state. The two enable lines can be separately activated to enable
only one byte of the Data Output Latch at a time.
PASS THRU
I
Pass Thru input. This line when HIGH forces the contents of the Check Bit Input Latch onto the Syndrome/Check
Bit outputs (SC D_6) and the unmodified contents of the Data Input Latch onto the inputs of the Data Output Latch.
DIAG MODE D_,
I
Diagnostic Mode Select. These two lines control the initialization and diagnostic operation of the EDC.
CODE 10 0 _2
I
Code Identification inputs. These three bits identify the size of the total data word to be processed and which 16-bit
slice of larger data words a particular EDC is processing. The three allowable data word sizes are 16-, 32- and 64-bits
and their respective modified Hamming codes are deSignated 16/22, 32/39 and 64/72. Special CODE 10 input 001
(10 2, 10" 10 0) is also used to instruct the EDC that the signals CODE 100 _2, DIAG MODE D_" CORRECT and PASS
THRU are to be taken from the diagnostic latch rather than the control lines.
LE DIAG
I
Latch Enable - Diagnostic Latch. The Diagnostic Latch follows the 16-bit data on the input lines when HIGH. When
LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch holds diagnostic
check bits and internal control signals for CODE 10 0 _2, DIAG MODE D_" CORRECT and PASS THRU.
3-75
IDT39C60/-l/A l6-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT DESCRIPTION
CHECK BIT GENERATION LOGIC
The IDT39C60 EDC Unit is a powerful 16-bit cascadable
slice used for check bit generation, error detection, error
correction and diagnostics. As shown in the Functional Block
Diagram, the device consists of the following:
This block of combinational logic generates 7 check bits
using a modified Hamming code from the 16 bits of data input
froni the Data Input Latch.
SYNDROME GENERATION LOGIC
Data I nput Latch
Data Output Latch
Diagnostic Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Control Logic
DATA INPUT/OUTPUT/DIAGNOSTIC LATCHES
The LE IN , Latch Enable input, controls the Data Input Latch
which can load 16-bits of data from the bidirectional DATA lines.
The input data is used for either check bit generation or error
detection/correction.
The 16 bits of data from the DATA lines can be loaded into the
Diagnostic Latch under control of the Diagnostic Latch Enable,
LE DIAG, giving check bit information in one byte and control
information in the other byte. The Diagnostic Latch is used when
in Internal Control mode or in one of the Diagnostic modes.
The Data Output Latch is split into 2 bytes and enabled onto
the DATA lines through separate byte control lines. The Data
Output Latch stores the result of an error correction operation
or is loaded directly from the Data Input Latch under control of
the Latch Enable Out (LEOUT). The PASS THRU control input
determines which data is loaded.
This logic compares the check bits generated through the
Check Bit Generator with either the check bits in the Check Bit
Input Latch or 7 bits assigned in the Diagnostic Latch.
Syndrome bits are produced by an exclusive-OR of the two
sets of bits. A match indicates no errors. If errors occur, the
syndrome bits can be decoded to indicate the bit in error,
whether 2 errors were detected or 3 or more errors.
ERROR DETECTION/CORRECTION LOGIC
The syndrome bits generated by the Syndrome Logic are
decoded and used to control the ERROR and MULT ERROR
outputs. If one or more errors are detected, ERROR goes low. Iftwo
or more errors are detected, both ERROR and MULT ERROR go
low. Both outputs remain high when there are no errors detected.
For single bit errors, the correction logic will complement
(correct) the bit in error, which can then be loaded into the
Data Out Latches under the LEoUT control. If check bit errors
need to be corrected, then the device must be operated in the
Generate mode.
CONTROL LOGIC
The control logic determines the specific mode of operation,
usually from external control signals. However, the Internal
Control mode allows these signals to be provided from the
Diagnostic Latch.
3-76
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
DETAILED PRODUCT DESCRIPTION
The IDT39C60 EDC Unil contains the logic necessary to
generate check bits on a 16-bit data input according to a
modified Hamming code. The EDC can compare internally
generated check bits against those read with the 16-bit data to
allow correction of any single bit data error and detection of all
double and some triple bit errors. The IDT39C60 can be used
for 16-bit data words (6 check bits). 32-bit data words (7 check
bits), or 64-bit data words.
CODE AND BYTE SELECTION
The 3 code identification pins, ID 2.(}, are used to determine
the data word size from 16-, 32- or 64-bits and the byte position
of each 16-bit IDT39C60 EDC device.
Code 16/22 refers to a 16-bit data field with 6 check bits.
Code 32/39 refers to a 32-bit data field with 7 check bits.
Code 64/72 refers to a 64-bit data field with a check bits.
The ID2'(} of 001 is used to place the device in the Internal
Control Mode as described later in this section.
Table 1 defines all possible identification codes.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Detect mode provides an indication of errors or multiple
errors on the outputs ~ and MULT ERROR. Single bit
errors are not corrected in this mode. The syndrome bits are
provided on the outputs SC O-6. For the Diagnostic Detect
mode, the syndrome bits are generated by comparing the
internally generated check bits from the Data In Latch with
check bits stored in the diagnostic latch rather than with the
check bit latch contents.
Correct mode is similar to the Detect mode except that
single bit errors will be complemented (corrected) and made
available as input to the Data Out Latch. Again, the Diagnostic
Correct mode will correct single bit errors as determined by
syndrome bits generllted from the Data Input and contents of
the Diagnostic Latch.
The Initialize' mode provides check bits for all zero bit data.
Data In Latch is set and latched to a logic zero, and made
available as input to the Data Out Latch.
The Internal mode disables the external control pins
DIAG MODE,.(}, CORRECT, PASS THRU and CODE 10 to be
defined by the Diagnostic Latch. When in the internal mode,
the diagnostic latch should have the CODE 10 different from
001 as this would represent an invalid operation.
CHECK AND SYNDROME BITS
The IDT39C60 provides either check bits or syndrome bits
on the three state output pins SCO_B. Check bits are generated
from a combination of the Data Input bits, while syndrome bits
are an Exclusive-OR of the check bits generated from read data
with the read check bits stored with the data. Syndrome bits
can be decoded to determine the single bit in error or that a
double error was detected. Some triple-bit errors are also
detected. The check bits are labeled:
CX, CO, C1, C2, C4
for the a-bit configuration
CX, CO, C1, C2, C4, ca
for the 16-bit configuration
for the 32-bit configuration
CX, CO, C1, C2, C4, ca, C16
CX, CO, C1, C2, C4, CB, C16, C32 for the 64-bit configuration
Syndrome bits are similarly labeled SX through S32.
TABLE 1.
HAMMING CODE AND SLICE IDENTIFICATION
CODE
ID.
CODE
ID,
COPE
IDo
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HAMMING CODE
AND SLICE SELECTED
Code 16/22
Internal Control Mode
Code 32/39, Bytes 0 and
Code 32/39, Bytes 2 and
Code 64172, Bytes 0 and
Code 64172, Bytes 2 and
Code 64172, Bytes 4 and
Code 64/72, Bytes 6 and
1
3
1
3
5
7
TABLE 2.
DIAGNOSTIC MODE CONTROL
CONTROL MODE SELECTION
Tables 2 and 3 describe the 9 operating modes of the
IDT39C60. The Diagnostic mode pins, DIAG MODE,.(}, define
4 basic areas of operation, with GENERATE, CORRECT, and
PASS THRU further dividing operation into a functions with the
ID 2.(} defining the ninth mode as the Internal mode.
Generate mode is used to display the check bits on the
outputs SCO_B. The Diagnostic Generate mode displays check
bits as stored in the Diagnostic Latch.
3-77
DIAG
MODE,
DIAG
MODEo
0
0
Non-diagnostic mode. The EDC functions
normally in all modes.
0
1
Diagnostic Generate. The contents of the
Diagnostic Latch are substituted for the
normally generated check bits when in the
Generate mode. The EDC functions
normally in the Detect or Correct modes.
1
0
Diagnostic Detect/Correct. I n the Detect or
Correct mode, the contents of the
Diagnostic Latch are substituted for the
check bits normally read from the Check Bit
Input Latch. The EDC functions normally in
the Generate mode.
1
1
Initialize. The outputs of the Data Input
Latch are forced to zeroes and the check
bits generated correspond to the all zero
data. The latch is not reset, a functional
difference from the Am2960.
DIAGNOSTIC MODE SELECTED
IDT39C80/-l/A l8-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 3. IDT39C60 OPERATING MODES
OPERATING
MODE
DMl
DMO GENERATE CORRECT PASSTHRU
Generate
0
1
0
0
0
X
0
Detect
0
0
0
1
1
0
0
Correct
0
0
0
1
1
1
Pass Thru
0
0
1
0
1
0
X
Diagnostic Generate
0
1
0
DATA OUT LATCH
(LE oUT ; HIGH)
-
SCo-a
(OEsC;LOW)
Check Bits Generated
from Data In Latch
ERROR
MULTERROR
-
Data I n Latch
Syndrome Bits
Data In/Check Bit Latch
Error(')
Dep
0
Data I n Latch with
Single Bit Correction
Syndrome Bits
Data In/Check Bit Latch
Error
Dep
X
1
Data I n Latch
Check Bit Latch
High
X
0
-
Check Bits from Diagnostic
Latch
-
Diagnostic Detect
1
0
1
0
0
Data I n Latch
Syndrome Bits
Data I n/Diagnostic Latch
Diagnostic Correct
1
0
1
1
0
Data In Latch with
Single Bit Correction
Syndrome Bits
Data I n/Diagnostic Latch
Error
Dep
Initialization Mode
1
1
X
X
X
Data I n Latch
SettoOOOO
Check Bits Generated
from Data In Latch (0000)
-
Internal Mode
ID 2-A$STHRU
LEoUT
22
0
CODE 10,-0
LEoUT
25
0
LE'N
LEOUT
28
0
DATAO-'5
LE olAG
5
3
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with C L = 5pF and measured
to O.5V change of output voltage level.
22
OUTPUT
ENABLE
DISABLE
OE BYTEo,
OE BYTE,
OATAo-'5
24
21
OEsc
SCo-s
24
INPUT
25
,
..
21
MINIMUM PULSE WIDTHS
I
12
LE,N, LEoUT' LE OIAG
NOTE:
1. DATAIN (or LE 1N ) to Correct Data Out measurement requires timing as
shown In Figure 12 below.
CORRECT DATA
OUTPUT
DATAO-1S
LEIN
OE BYTEO& 1
Figure 12.
3-93
MSD39C60-014
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60A over the military operating range of -SsoC to
+12SoC, with Vcc from 4.SV to S.SV. All data are in nanoseconds, with inputs switching between OV and 3V at 1V per
nanosecond and measurements made at 1.SV. All outputs have
maximum DC load. Vee equal to S.OV ± 10%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
CL = SOpF
TO
(LATCHING
FROM INPUT
SET-UP
TIME
UP DATA)
CORRECT
(Not Internal
Control Mode)
DIAG MODE
(Not Internal
Control Mode)
HOLD
TIME
25
25
28
21
24
PASSTHRU
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with CL = SpF and measured
to O.SV change of output voltage level.
LE DIAG
(From latched to
transparenl; Not
Internal Control
Mode)
37
29
26
OUTPUT
ENABLE
DISABLE
~BYTEo,
INPUT
DATAo.'5
28
25
OEsc
SCO-jl
28
25
E BYTE,
Internal Control
Mode: LE olAG
(From latched
to transparenl)
30
43
32
35
Internal Control
Mode: DATAo.'5
(Via Diagnostic
Latch)
30
43
32
35
MINIMUM PULSE WIDTHS
12
NOTE:
1. DATAIN (or LE 1N ) to Correct Data Out measurement requires timing as
shown in Figure 13 below.
VALID
INPUT DATA
CORRECT DATA
r--';;';:;';':';'=~m '-_ _,IIr-_O_U_T_P_U_T
DATAO.15
OEBYTEO&l
MS039C60~014
Flgur.13.
3-94
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C6G-1 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39CSQ-1 over the commercial operating range of O°C to
+70°C, with Vee from 4.75V to 5. 25V. All data are in nanoseconds, with inputs switching between OV and 3V at 1V per
nanosecond and measurements made at 1.5V. All outputs have
maximum DC load. Vee equal to 5.0V ± 5%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L : 50pF
TO OUTPUT
FROM INPUT
SCo..
ERROR
MULTERROR
25
50
DATA o·'5
28
DATAo.' 5
52
CB O•6
(CODE 102-0000,011)
23
50
23
47
CB O•6
(CODE ID 2-O 010,100,
101,110,111)
28
34
29
34
GENERATE
35
63
36
55
CORRECT
(Not Internal
Control Mode)
-
45
-
DIAG MODE
(Not Internal
Control Mode)
50
78
59
PASSTHRU
(Not Internal
Control Mode)
36
CODE ID 2.0
61
90
60
80
LE'N
(From latched
to transparent)
39
72 (1 )
39
59
LEoUT
(From latched
to transparent)
-
31
-
-
LE olAG
(From latched to
transparent; Not
Internal Control
Mode)
45
Internal Control
Mode: LE DIAG
(From latched
to transparent)
67
96
66
86
I nternal Control
Mode: DATA o.' 5
(Via Diagnostic
Latch)
67
96
66
86
44
29
TO
(LATCHING
UP DATA)
FROM INPUT
SET-UP
TIME
HOLD
TIME
DATAa· '5
LE'N
6
7
CB a_6
LE'N
5
6
DATAa· '5
LEoUT
34
5
CB o..
(CODE ID)
000,011)
LEoUT
35
0
-
CB O•6
(CODE ID
100,101,110,111)
LEoUT
27
0
GENERATE
LEoUT
42
0
75
CORRECT
LEoUT
26
1
DIAG MODE
LEoUT
69
0
46
PASSTHRU
LEoUT
26
0
CODE 102.0
LEoUT
81
0
LE'N
LEoUT
51
5
DATA O·' 5
LE olAG
6
8
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with CL : 5pF and measured
to O.5V change of output voltage level.
78
45
65
OUTPUT
ENABLE
DISABLE
p-E BYTEa,
pE BYTE ,
INPUT
DATAa. '5
30
30
pE se
SC o..
30
30
MINIMUM PULSE WIDTHS
15
NOTE:
1. OATA 1N (or LE 1N ) to Correct Data Out measurement requires timing as
shown in Figure 14 below.
CORRECT DATA
OUTPUT
VALID
INPUT DATA
DATAo-15
LEIN
OE BYTEo&1
MSD39C60-014
Figure 14.
3-95
&I
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39CSG-1 AC ELECTRICAL CHARACTERIST,CS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
I DT39CSD-1 over the military operating range of -SS"C to
+12S"C, with Vee from 4.SV to S.SV. All data are in nanoseconds, with inputs switching between OV and 3V at 1V per
nanosecond and measurements made at 1.SV. All outputs have
.
maximum DC load. Vee equal to S.OV ± 10%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = SOpF
TO
(LATCHING
UP DATA)
TO OUTPUT
FROM INPUT
SET-UP
TIME
HOLD
TIME
LE'N
7
7
LE'N
5
7
DATAo· '5
LEoUT
39
5
CB O·6
(CODE ID)
000.011)
LEoUT
38
0
CB o-6
(CODE ID
100,101,110.111)
LEoUT
30
0
GENERATE
LEoUT
46
0
CORRECT
LEoUT
28
1
DIAG MODE
LEoUT
84
0
PASSTHRU
LEoUT
30
0
CODE ID 2. 0
LEoUT
89
0
LE'N
LEoUT
59
5
DATA o· '5
LE olAG
7
9
FROM INPUT
SCo••
DATAo•15
ERROR
MULTERROR
DATAo·'5
31
59
28
56
DATAo·15
CB O-6
(CODE ID 2-oOOO,011)
25
55
25
50
CBO- 010,100,
101,110,111)
28
45
29
34
GENERATE
35
63
36
55
CORRECT
(Not Internal
Control Mode)
-
45
-
-
CB •.•
(CODE ID
100,101,110,111)
LEoUT
27
0
DIAG MODE
(Not Internal
Control Mode)
GENERATE
LEoUT
42
0
50
78
59
75
CORRECT
LEoUT
26
1
DIAG MODE
LEoUT
69
0
PASS THRU
(Not Internal
Control Mode)
36
CODE
ID2~
61
44
29
90
60
46
80
LE'N
(From latched
to transparent)
39
72(1)
39
59
LEoUT
(From latched
to transparent)
-
31
-
-
LE D1AG
(From latched to
transparent; Not
Internal Control
Mode)
45
Internal Control
Mode: LE D1AG
(From latched
to transparent)
67
96
66
86
67
96
66
86
Internal Control
Mode: DATA•.,.
(Via Diagnostic
Latch)
PASS THRU
LEoUT
26
0
CODE ID 2.•
LEoUT
81
0
LE'N
LEoUT
51
5
DATA.·,s
LE olAG
6
8
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with CL = SpF and measured
to O.SV change of output voltage level.
45
78
65
OUTPUT
ENABLE
DISABLE
p-E BYTE.,
OE BYTE,
INPUT
DATA •. ,s
30
30
OEsc
SC D••
30
30
MINIMUM PULSE WIDTHS
15
NOTE:
1. DATAIN (or LE 1N ) to Correct Data Out measurement requires timing as
shown in Figure 16 below.
CORRECT DATA
OUTPUT
VALID
INPUT DATA
DATAo-15
LEIN
OE BYTEO& 1
MSD39caD-014
Flgura1&.
3-97
IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C60 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60 over the military operating range of -55°C to +125°C,
with Vee from 4.5V to 5.5V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.5V. All outputs have maximum DC
load. Vee equal to 5.0V ± 10%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
CL = 50pF
TO
(LATCHING
UP DATA)
TO OUTPUT
FROM INPUT
FROM INPUT
SC....
DATA••,.
ERROR
MULTERROR
DATA."5
35
73<'1
36
56
DATAO_'5
CB O-6
(CODE ID 2_0 OOO,011)
30
61
31
50
CB O-6
DATAO_'5
CB O_6
(CODE ID)
000,011)
CB O_6
(CODE 1D2_0 010,100,
101,110,111)
30
50
31
37
GENERATE
38
69
41
62
CORRECT
(Not Internal
Control Mode)
-
49
-
-
DIAG MODE
(Not Internal
Control Mode)
58
89
65
90
PASS THRU
(Not Internal
Control Mode)
39
CODE ID 2-<)
69
34
51
100
68
54
90
LE'N
(From latched
to transparent)
44
82(11
43
66
LEoUT
(From latched
to transparent)
-
33
-
-
LE D1AG
(From latched to
transparent; Not
I nternal Control
Mode)
50
I nternal Control
Mode: LE D1AG
(From latched
to transparent)
75
106
74
96
75
106
74
96
I nternal Control
Mode: DATAo_'5
(Via Diagnostic
Latch)
CB O_6
(CODE ID
100,101,110,111)
SET-UP
TIME
HOLD
TIME
LE'N
7
7
LE'N
5
7
LEOUT
50
5
LEoUT
38
0
LEoUT
30
0
0
GENERATE
LEOUT
46
CORRECT
LEoUT
28
1
DIAGMODE
LEoUT
84
0
PASSTHRU
LEoUT
30
0
CODE ID2_0
LEoUT
89
0
LE'N
LEoUT
59
5
DATA o_'5
LE D1AG
7
9
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with CL = 5pF and measured
to 0.5V change of output voltage level.
49
88
72
OUTPUT
ENABLE
DISABLE
Q:E BYTE o,
OE BYTE,
INPUT
DATA o_'5
35
35
OEsc
SC O_6
35
35
MINIMUM PULSE WIDTHS
15
NOTE:
1. DATAIN (or LE 1N ) to Correct Data Out measurement requires timing as
shown in Figure 17 below.
CORRECT DATA
OUTPUT
VALID
INPUT DATA
DATAO-1S
LEIN
OE BYTEO& 1
Figure 1l
3-98
MSD39C60-014
FEATURES:
selected by the B address. The D inputs are used to load new data
into the device.
Featured are two separate output ports which allow any two
4-bit words to be read from these outputs simultaneously. Also
featured is a 4-bit latch for each of the two output ports with a
common Latch Enable (LE) input being used to control all eight
latches. Two Write Enable (WE) inputs are designed such that
Write Enable 1 (WE1) and Latch Enable (LE) inputs can be
connected to the RAM to operate in an edge-triggered mode. The
Write Enable inputs control the writing of new data into the RAM.
Data is written into the B address field when both Write Enables
are LOW. If either of the Write Enables are HIGH, no data is
written into the RAM.
Three-state outputs allow several devices to be easily cascaded
for increased memory size. When OEA input is HIGH, the A
output port is in the high impedance mode. The same respective
operation occurs for the OE B input.
The IDT39C707s function identically to the IDT39C705s,
except each output port has a separate Latch Enable (LE) input.
Also, an extra Write Enable (WE) may be connected directly to
the lEN of the IDT39C203/A for improved cycle times when
compared to the IDT39C705s. The WEIBLE input can then be
connected directly to the system clock.
These performance-enhanced, pin-compatible replacements
for all respective versions ofthe 29705s and 29707s are fabricated
using IDTs high-speed, high-reliability CEMOS technology.
Military product is 100% screened to MIL-STD-883, Class B,
making them ideally suited to military temperature applications.
• Fast
-Available in either industry-standard speed or 20% speed
upgraded versions
• Low-power CEMOS'·
-Military - 50mA (max.)
-Commercial - 40mA (max.)
• 16-word x 4-bit, dual-port CMOS RAM
• Non-inverting data output with respect to data input
• Easily cascadable with separate Chip Select and
Write Enable
• Separate 4-bit latches with enables for each output port
(IDT39C707/A has separate output control)
• IDT39C705A/B pin-compatible to all versions of the 29705
• IDT39C707/A pin-compatible to all versions of the 29707
• Available in 28-pin DIP and LCC
• Military product 100% screened to MIL-STD-883, Class B
DESCRIPTION:
The IDT39C705s are high-performance 16-word by 4-bit, dualport RAMs. Addressing any of the 16-words is performed via the
4-bit A address field with the data appearing on the A output port.
The same respective operation holds true for the B address
input/output port and can happen simultaneously with the A-port
operation. New incoming data is written into the 4-bit RAM word
FUNCTIONAL BLOCK DIAGRAM
IDT39C70SAlB
O2
0,
·· 1
•
-
A,
-
~
A
ADDRESS
DECODER
.....
....
........
ALa
FORCE A
ZERO
OE A
I
·•
~
DUAL-PORT
RAM
,.w
•• " ..
"
A
ADDRESS
WE,
Da
(
B
ADDRESS
•
f-- Ba
B
ADDRESS f-- B2
DECODER
f-- B,
r--
r--A-PORT
WE
B-PORT
I
-
J
-t>
A-DATA
4-BIT
LATCH
....
....
I
I
I
I
B-DATA
4-BIT
LATCH
J
ALE
A-DATA
4-BIT
LATCH
to..
....
I
I
I
B-DATA
4-BIT
LATCH
I
I
I
I
.A
......
I
YBo YB, YB. YB.
YA" YA, YA. YA.
MSDC705-002
PIN CONFIGURATIONS
IDT39C705AIB
D,
Do
WE,
Bo
B,
B.
B.
IDT39C707/A
Vee
D.
D.
WE.
Ao
A,
A.
A.
OEA
ALO
LE
YBo
YAo
YB,
YA,
GND
DIP
TOP VIEW
OEs
YA.
YB.
YA.
YB.
D,
Do
WE,
Bo
B,
B.
B.
ALE
WEIBLE
YBo
YA"
YB,
YA,
GND
Vee
D.
D.
WE.
A"
A,
A.
A.
OE...
OE.
YA.
YB.
YA.
YB.
MSOC705-003
0luJ
0
...
U
N
,"2 ,i ."28
II
MSDC705-004
clw
IPJ
III!=CC-§CC
, , ,U ,
U
B, :J: 3
B. :J6
B~
, I
I
I
I
I,
,
U
rl rl ",. 15, , ,16, , , ", ,
, I
....... Q
17
r, r,
n
N
('III
U
WE.
24[: Ao
23[: A,
22[-:' A.
21[: A3
20[: OEA
25'--
:J 7
:J8
LE :J9
YBo :JlO
-,11
YA o
-~
I
u LJ
27 26,..-
ALo
f')
19r18'--
0
H
...
N
C"J
III!=CC>'CC
, I
LCC
TOP VIEW
OE s
B,
B.
B.
ALE
WEIBLE
YB o
YA"
,, I ,I
:J:
U
3
u
2
:J6
,
.J LJ
"U
28
26,..2SL-
27
24(:
:J 7
23[:
:J8
:J9
:JlO
22[-:'
21
19r-
-.., 11
_oJ
12
C:
20[:
13 1. 15 16
18L...-
17
,r', ri ," , ,r,, ,r,, ,r,, ", ,
...... Q
C"J
~~t3~~~~
"
"U
"
II
II
N
N
C"J
WE.
Ao
A,
A.
A.
OEA
OEs
COl
~~t3~~~~
MSDC705-0OS
MSDC705-006
3-100
MICROSLICE™ PRODUCT
FEATURES:
DESCRIPTION:
•
Similar function to AMD's Am2925 bipolar controller with
improved speeds and output drive over full temperature and
voltage supply extremes
•
Four microcode-controlled clock outputs allow clock cycle
length control for 15 to 30% increase in system throughput.
Microcode selects one of eight clock patterns from 3 to 10
oscillator cycles in length
•
System controls for RUN/HALT and Single Step
-Switch-debounced inputs provide flexible halt controls
•
Low input/output capacitance
-6pF inputs (typ.)
-8pF outputs (typ.)
•
CMOS power levels
Available in 300 mil 24-pin THIN DIP package
The IDT49C25 is a single-chip general purpose clock generator/driver built using advanced CEMOS'·, a dual metal CMOS
technology. It has microprogram mabie clock cycle length to
provide significant speed-up over fixed clock cycle approaches
and meets a variety of system speed requirements.
The IDT49C25 generates four different simultaneous clock
output waveforms tailored to meet the needs of the IDT39COOO
CMOS family and other MOS and bipolar microprocessor-based
systems. One-of-eight cycle lengths may be generated under
microprogram control using the Cycle Length inputs L" L2
and L 3.
A buffered oscillator output, F0, is provided for external system
timing in addition to the four microcode controlled clock outputs
C" C2, C 3 and C 4·
System control functions include RUN, HALT, Single-Step,
Initialize and Ready/Wait controls. In addition, the FIRST/LAST
input determines where a halt occurs and the C x input determines
the end point timing of wait cycles. WAITACK indicates that the
IDT49C25 is in a wait state.
•
Both CMOS and TTL output compatible
•
Substantially lower input current levels than AMD's bipolar
Am2900 series (5JlA max.)
•
100% product assurance screening to MIL-STD-883, Class
B is available
FUNCTIONAL BLOCK DIAGRAM
OSC
,-,,-
L3
....
V
MICROCYCLE
CONTROL
LATCH
I--
f--..
CONTROL
STATE
DECODER
f--
t
t
EN
---------
+
CLOCK
GENERATOR
REGISTER
....
....
V
~
.....
C.
C3
C
~-..... C,
2
1 ...
I
''--
FIRST/LAST - +
HALT
RUNl SSNC
SSNO
INIT
RUN/HALT
AND
SINGLE STEP
CONTROL
f
WAIT
CONTROL
I---
1
WAITREQ
I
READY
Cx
MSD49C25-001
CEMOS is a trademark of Integrated Device Technology, Inc,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A
©1986 Integrated Device Technology, Inc
3-101
IDT49C25 HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
u
z..r
Vee
GND
IIDDY
Cx
I
I
I. .
zQ
,,-
CJJU!
II
II
II II
II
II
LJ lJ
L..I
I I L.I
L.J
LJ
Ll
liiIlT
L2
~:[:
NC
~
L,
C1
C2
WAITREQ
L3 :J6
24[:
WAITREQ
WAi"i'ACK
ImI
C1
:J 7
23[:
WAiTACK
C2
:]8
22[:
RUN
C4
::]10
20[:
FIRST/LAST
OSC
HALT
FIRSTJi:AST
OSC
C3
C4
SSNC
NC
3
2
l1J
28 27
-.,11
19r-..I 12 13 14 15
16 17 18"'-
nrlr1rlflrlrl
NC
SSNO
GND
':J 54
Fo
Vee
LCC
TOP VIEW
DIP
TOP VIEW
MSD49C25-002
MSD49C25~003
3-102
MICROSLICET. PRODUCT
FEATURES:
of four 2901s and a 2902. with additional control features aimed at
enhancing the performance of bit-slice microprocessor designs.
The IDT49C401s include all of the normal functions associated
with standard 2901 bit-slice operation: (a) a 3-bit instruction field
(10.11.12) which controls the source operand selection forthe ALU;
(b) a 3-bit microinstruction field (13.14015) used to control the eight
possible functions of the ALU. and; (c) sixteen destination control
functions which are selected by the microcode inputs (lsh,Ia.lg).
Eight of the sixteen destination control functions reflect the
standard 2901 operation. while the other eight additional destination control functions allow for shifting the Q Register up and
down. loading the RAM or Q Register directly from the D inputs
without going through the ALU. and new combinations of
destination functions with the RAM A-port output available at the
Y output pins of the device. Also featured is an on-chip dual-port
RAM that contains 16 words by 16 bits.
The IDT49C401s are fabricated using CEMOS. a single poly.
double metal CMOS technology designed for high-performance
and high-reliability. These performance enhanced devices feature
both bipolar speed and bipolar output drive capabilities while
maintaining exceptional microinstruction speeds at greatly
reduced CMOS power levels.
• Fast
-30% faster than four 2901Cs and one 2902A
• Low-power CEMOS'·
-Military - 150mA (max.)
-Commercial-125mA (max.)
• Functionally equivalent to four 2901s and on 2902
• Pin-compatible. performance-enhanced replacement
for IMI4X29018
• Independent. simultaneous access to two 16-word x 16-bit
register files
• Expanded destination functions with eight new operations
allowing Direct Data to be loaded directly into the dual-port
RAM and Q Register
• Cascadable
• Available in a 64-pin DIP
• Military product 100% screened to MIL-STD-883. Class 8
DESCRIPTION:
The IDT49C401sare high-speed. fully cascadable 16-bit CMOS
microprocessor slice units which combine the standard functions
FUNCTIONAL BLOCK DIAGRAM
.t;.
0
1
2
10-19
3
4
5
UJ
ALU
SOURCE
0
UJ
0
t=
U
;:)
a:
Ul
Z
DESTINATION
CONTROL
5a:
U
RAM SHIFT
RAM15
{y--
V
B DATAIN
U
C
Z
ALU
FUNCTION
H
C
I-
6
7
8
9
RAMaCLOCK-
READ ADDRESS
II
1:
READIWRITE ADDRESS
II
y
CP
18 ADDRESSABLE
REGISTERS
A ADDRESS
A
B
BADDRESS DATA DATA
OUT OUT
DIRECT DATAIN
~
J
~
00 o SHIFT
4cp
{J.
7'
015
1
o REGISTER
7U[iju=
D
A
B
0
0
ALU DATA SOURCE SELECTOR
R
S
{J.
~J.
R
S
CARRY IN8-FUNCTION ALU
I-- C n + 16
MSS-
~F=O
{7
.J.
OUTPUT ENABLE
~G/N
I--P/OVR
OUTPUT DATA SELECTOR
.u-
DATAOUT
I
MSD49C402-001
CEMOS and MICROSLICE are trademarks of Integrated Oevice Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
01986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
3-103
I
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
PIN CONFIGURATION
DIP
TOP VIEW
DEVICE ARCHITECTURE
The IDT49C401 CMOS Bit-Slice Microprocessors are configured sixteen bits wide and are cascadableto any number of bits
(16, 32, 48, 64). Key elements which make up these sixteen-bit
slice microprocessors are the (1) register file (16 x 16 dual-port
RAM) with shifter, (2) ALU, and (3) 0 Register and shifter.
REGISTER FILE-A 16-bil data word from one of the 16 RAM
registers can be read from the A-port as selected by the 4-bit A
address field. Simultaneously, the same data word or any other
word from the 16 RAM registers can be read from the B-port as
selected by the 4-bit B address field. New data is written into the
RAM register location selected by the B address field during the
clock (CP) LOW time. Two sixteen-bit latches hold the RAM Aport and 8-port data during the clock (CP) LOW time, eliminating
any data races. During clock HIGH these latches are transparent,
reading the data selected by the A and B addresses. The RAM data
input field is driven from a four-input multiplexer that selects the
ALU output or the 0 inputs. The ALU output can be shifted up one
position, down one position or not shifted. Shifting data operations involve the RAM 15 and RAMo I/O pins. For a shift up
operation, the RAM shifter MSB is connected to an enabled
RAM 15 I/O output while the RAMo I/O input is selected as the
input to the LSB. During a shift down operation, the RAM shifter
LSB is connected to an enabled RAMo I/O output while the
RAM15 I/O input is selected as the input to the MSB.
ALU-The ALU can perform three binary arithmetic and five
logic operations on the two 16-bit input words Sand R. The S
input field is driven from a 3-input multiplexer and the R input field
is driven from a 2-input multiplexer, with both having a zero source
operand. Both multiplexers are controlled by the I (0,1,2) inputs.
This multiplexer configuration enables the user to select various
pairs of the A, B, 0, 0 and "0" inputs as source operands to the
ALU. Microinstruction inputs 1(3,4,5) are used to select the ALU
function. This high-speed ALU cascades to any word length,
providing carry-in (C n), carry-out (C n+1s) and an open-drain (F = 0)
output. When all bits of the ALU are zero, the pull-down device of
F = 0 is off, allowing a wire-OR olthis pin over all cascaded devices.
Multipurpose pins G/F15 and P/OVR are aimed at accelerating
3-104
arithmetic operations. For intermediate and least-significant slices,
the MSS pin is programmed LOW selecting the carry-generate (G)
and carry-propagate (P) output functions to be used by carrylookahead logic. For the most-significant slice, MSS is programmed high, selecting the sign-bit (F 1sl and the two's complement overflow (OVR) output functions. The sign-bit (F 1sl allows
the ALU sign-bit to be monitored without enabling the three-state
ALU outputs. The overflow (OVR) output is high when the two's
complement arithmetic operation has overflowed into the signbit, as logically determined from the Exclusive-OR of the carry-in
and carry-out of the most-significant bit of the ALU. For all 16-bit
applications, the MSS pin on the IDT49C401s is tied high or not
connected since only one device is needed. With MSS open or
tied high, internal circuitry will direct pins 33 and 34 to function as
F15 and OVR, respectively. It is in this 16-bit operating mode that
the IDT49C401s function identically to the IMI4X2901 B. The ALU
data outputs are available at the three-state outputs Y(0-15), or as
inputs to the RAM register file and 0 Register under control olthe
I (S.7.8.9) instruction inputs.
Q REGISTER-The 0 Register is a separate 16-bit register
intended for multiplication and division routines, and can also be
used as an accumulator or holding register for other types of
applications. It is drivlln from a 4-input multiplexer. In the no-shift
mode, the multiplexer enters the ALU F output or Direct Data into
the 0 Register. In either the shift-up or shift-down mode, the
multiplexer selects the 0 Register data appropriately shifted up or
down. The 0 shifter has two ports, 0 0 and 0 150 which operate
comparably to the flAM shifter. They are controlled by the 1(6.7.8,9)
inputs.
The clock input of the IDT49C401 controls the RAM, 0 Register
and A and B data latches. When enabled, the data is clocked into
the 0 Register on the LOW-to-HIGH transition. When the clock is
HIGH, the A and B latches are open and pass data that is present
at the RAM outputs. When the clock is LOW, the latches are closed
and retain the last data entered. When the clock is LOW and
I (6.7.8,9) define the RAM as the destination, new data will be written
into the RAM file defined by the B address field.
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
PIN NAME
1/0
Ao-A3
I
Four address inputs to the register file which selects one register and displays its contents through the A-port.
Bo-B3
I
Four address inputs to the register file which selects one of the registers in the file, the contents of which are
displayed through the B port. It also selects the location into which new data can be written when the clock goes
LOW.
10-19
I
Ten instruction control lines which determine what data source will be applied to the ALU 1(0",2)' what function the
ALU will perform 1(3,4,5), and what data is to be deposited in the Register or the register file 1(6,7,8,9)' Original 2901
destinations are selected if 19 is disconnected. In this mode, proper 19 bias is controlled by an internal pullup resistor
to Vce.
Do-D'5
I
Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU,
RAM. Do is the LSB,
YO-Y'5
0
Sixteen three-state output lines which, when enabled, display either the sixteen outputs of the ALU or the data on
the A-port of the register stack, This is determined by the destination code 1(6,7,8,9)'
G/F'5
0
A multipurpose pin which indicates the carry generate, G, function at the least significant and intermediate slices, or as
F'5' the most si(1!1ificant ALU output (sign bit). G/F'5 selection is controlled by MSS pin. If MSS = HIGH, F'5 is enabled.
If MSS = LOW, G is enabled.
F=O
0
Open drain output which goes HIGH if the Fo-F'5 ALU outputs are all LOW. This indicates that the result of an ALU
operation is zero (positive logic).
Cn
I
Carry-in to the internal ALU.
C n+16
0
0'5
RAM'5
I/O
00
RAMo
DESCRIPTION
a
a Register or
Carry-out of the internal ALU.
Bidirectional lines controlled by 1(6,7,8,9)' Both are three-state output drivers connected to the TTL-compatible
inputs. When the destination code on I (6,7,8,9) indicates an up shift, the three-state outputs are enabled and the MSB
of the Register is available on the 0'5 pin and the MSB of the ALU output is available on the RAM'5 pin. When the
destination code indicates a down shift, the pins are the data inputs to the MSB of the Register and the MSB
of the RAM.
a
I/O
a
Both bidirectional lines function identically to 0'5 and RAM'51ines except they are the LSB of the
RAM,
a Register and
OE
I
Output enable. When pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y outputs are
enabled.
P/OVR
0
A multipurpose pin which indicates the carry propagate (P) output for performing a carry-Iookahead operation or
overflow (OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MSB. OVR, at the most significant end of
!!:Ie word, indicates that the result of an arithmetic two's complement operation has overflowed..,into the sign bit.
P/OVR selection is controlled by the MSS pin. If MSS = HIGH, OVR is enabled. If MSS = LOW, P is enabled,
CP
I
The clock input. LOW-to-HIGH clock transitions will change the Register and the register file outputs. Clock LOW
time is internally the write enable time for the 64x16 RAM which compromises the master latches of the register file.
While the clock is LOW, the slave latches on the RAM outputs are closed, storing the data previously on the RAM
outputs. Synchronous MASTER-SLAVE operation of the register file is achieved by this.
MSS
I
When HIGH, enables OVR and F,. on the P/OVR and G/F'5 pins. When LOW, enables G and P on these pins. If left
open, internal pullup resistor to Vee provides declaration that the device is the most significant slice and will define
pins as OVR and F'5'
a
ALU SOURCE OPERAND CONTROL
MNEMONIC
AO
AB
ZO
ZB
ZA
DA
DO
DZ
12
I,
I.
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
ALU FUNCTION CONTROL
ALUSOURCE
OPERANDS
MICROCODE
OCTAL
CODE
0
1
2
3
4
5
6
7
R
S
A
A
a
B
a
0
0
0
D
D
D
MICROCODE
MNEMONIC
ADD
SUBR
SUBS
OR
AND
NOTRS
EXOR
EXNOR
B
A
A
a
0
3-105
I.
I.
I.
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
OCTAL
CODE
0
1
2
3
4
5
6
7
ALU
FUNCTION
R Plus S
S Minus R
R Minus S
RORS
RANDS
RANDS
REX-OR S
R EX-NORS
SYMBOL
R+S
S-R
R-S
R VS
R liS
R liS
i"iV'S
RVS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
ALU LOGIC MODE FUNCTIONS
ALU ARITHMETIC MODE FUNCTIONS
Cn = L
OCTAL
OCTAL
Cn=H
15,4,,. 12,1,0
GROUP
FUNCTION
GROUP
FUNCTION
0 0
0 1
0 5
0 6
ADD
A+O
A+B
D+A
D+O
ADD
Plus One
A+ 0 + 1
A+B+l
D +A+ 1
D+ 0 + 1
0 2
0 3
0 4
0 7
PASS
0
B
A
D
Increment
0+1
B+ 1
A+ 1
D+ 1
Decrement
0-1
B-1
A-I
D-l
PASS
0
B
A
D
l's Compo
-0 -1
-B -1
-A -1
-D -1
2's Compo
(Negate)
-0
-B
-A
-D
Subtract
(l's Comp.)
O-A-l
B -A-l
A-D-l
0- D-l
A-O -1
A-B-l
D -A-l
D -0-1
Subtract
(2's Comp.)
O-A
B-A
A-D
O-D
A-O
A-B
D-A
D-O
1
1
1
2
2
3
4
7
2
2
2
1
2
3
4
7
1
1
1
1
2
2
2
2
0
1
5
6
0
1
5
6
G~OUP
FUNCTION
15,4,,. 12,1,0
4
4
4
4
0
1
5
6
AND
AIIO
AIIB
DIIA
DIIO
3
3
3
3
0
1
5
6
OR
AVO
AVB
DVA
DVO
EX-OR
AVO
AVB
DVA
DVO
0
1
5
6
EX-NOR
AVO
AVB
DVA
DVO
7 2
7 3
7 4
7 7
INVERT
0
B
A
D
6 2
6 3
6 4
6 7
PASS
0
B
A
D
3 2
3 3
3 4
3 7
PASS
0
B
A
D
6 0
6 1
6 5
6 6
7
7
7
7
3-106
4
4
4
4
2
3
4
7
"ZERO"
0
0
0
0
5
5
5
5
0
1
5
6
MASK
AIIO
AIIB
"BIIA
5110
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SOURCE OPERAND AND ALU FUNCTION MATRIX
12",0 OCTAL
1
2
4
3
6
7
D,A
0,0
0,0
D+A
D+Q
D
OCTAL
Is,.,.
ALU
FUNCTION
0
5
A,a
A,B
0,0
O,B
O,A
A+Q
A+8
Q
8
A
0
C n =L
R Plus S
C n =H
A +Q +1
A+8 +1
Q+1
8 +1
A+1
D+A+1
D+Q+1
D+ 1
Q -A-l
8 - A-I
Q -1
8 -1
A-I
A - D-1
Q- D-1
-D -1
1
C n =L
S Minus R
C n =H
Q-A
8-A
Q
8
A
A-D
Q-D
-D
A - Q-l
A - 8-1
-Q -1
-8 -1
-A -1
D -A-l
D-Q-l
D -1
2
C n =L
R Minus S
C n =H
A-Q
A-8
-Q
-8
-A
D-A
D-Q
D
3
RORS
AVQ
AV8
Q
8
A
DVA
DVQ
D
4
RANDS
AI\Q
A 1\8
0
0
0
DI\A
DI\Q
0
5
RANDS
AI\Q
AI\8
Q
8
A
D I\A
DI\Q
0
6
R EX-ORS
AVQ
AV8
Q
8
A
DVA
DVQ
D
7
REX-NOR S
AVQ
AV8
Q
8
A
DVA
DVQ
D
ALU SOURCE
+ ::: Plus; -::: MinUS; A::: AND; V ::: EX-OR; V::: OR
ALU DESTINATION CONTROL
RAM
FUNCTION
MICROCODE
MNEMONIC
a REGISTER
FUNCTION
Y
OUTPUT
RAM
SHIFTER
a
SHIFTER
I.
I.
17
I.
HEX
CODE
SHIFT
LOAD
SHIFT
LOAD
RAMo
RAM,s
00
OREG
H
L
L
L
B
X
NONE
NONE
F-Q
F
X
X
X
X
NOP
H
L
L
H
9
X
NONE
X
NONE
F
X
X
X
X
RAMA
H
L
H
L
A
NONE
F- 8
X
NONE
A
X
X
X
X
RAMF
H
L
H
H
8
NONE
F-8
X
NONE
F
X
X
X
X
RAMQD
H
H
L
L
C
DOWN
F/2 - 8
DOWN
Q/2-Q
F
Fa
IN'5
Qo
IN'5
a,s
RAMD
H
H
L
H
D
DOWN
F/2 - 8
X
NONE
F
Fa
IN'5
Qo
X
RAMQU
H
H
H
L
E
UP
2F- 8
UP
2Q-Q
F
INa
F'5
INa
Q'5
RAMU
H
H
H
H
F
UP
2F- 8
X
NONE
F
INa
L
L
L
L
0
NONE
D-8
NONE
F-Q
F
X
F'5
X
X
DFF
X
Q'5
X
DFA
L
L
L
H
1
NONE
D-B
NONE
F-Q
A
X
X
X
X
FDF
L
L
H
L
2
NONE
F-B
NONE
D-Q
F
X
X
X
X
FDA
L
L
H
H
3
NONE
F-B
NONE
D-Q
A
X
X
X
X
XQDF
L
H
L
L
4
X
NONE
DOWN
Q/2-Q
F
X
X
Qo
IN'5
DXF
L
H
L
H
5
NONE
D-B
X
NONE
F
X
X
Qo
X
XQUF
L
H
H
L
6
X
NONE
UP
2Q-Q
F
X
X
INa
Q'5
XDF
L
H
H
H
7
X
NONE
NONE
D-Q
F
X
X
X
Q'5
X::: D"Jn't Care. Electrically, the shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.
S ::: Register Addressed by B inputs.
UP is toward MSB; DOWN is toward LSB.
3-107
Existing 2901
Functions
New Added
IDT49C401
Functions
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect
toGND
VALUE
UNIT
-0.5(3) to +7.0
V
Operating
Temperature
-55 to +125
·C
TelAs
Temperature
Under Bias
-65 to +135
·C
TSTG
Storage
Temperature
-65 to +150
·C
Power
lOUT
DC Output Current
into Outputs
GRADE
Military
T,
PT
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Dissipation (2 )
1.0
W
30
mA
Commercial
AMBIENT
TEMPERATURE
GND
Vcc
-55·C to +125·C
OV
5.0V± 10%
O·C to +70·C
OV
5.0V±S%
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAX)MUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions tor extended periods may affect
reliability.
2. PT maximum can only be achieved by excessive IOL or 'OH3. V 1L Min. = -3.0V for pulse width less than 20n5.
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 5%
Vee = 5.0V ± 10%
TA = O·C to +70·C
TA = -55·C to +125·C
VLe = 0.2V
VHe = Vee - 0.2V
Min. =4.75V
Min. =4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
VIH
Input HIGH Level
Guaranteed Logic High Level (4)
2.0
-
-
VIL
Input LOW Level
Guaranteed Logic Low Level (4)
-
-
0.8
V
IIH
Input HIGH Current
Vce
-
1.0
S
p.A
IlL
Input LOW Current
=Max., VIN =Vee
Vee = Max., VIN = GND
p.A
SYMBOL
VOH
TEST CONDITIONS!')
PARAMETER
Output HIGH Voltage
Vee = Min.
VIN = VIH or VIL
-
-1.0
-S
)OH = -300p.A
VHe
Vee
-
10H = -12mA MIL.
2.4
4.3
-
2.4
4.3
VLe
10H
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
loz
Off State (High Impedance)
Output Current
Vee
los
Output Short Circuit Current
Vee = Max., VOUT = OV(3)
= Max.
=-ISmA COM'L.
-
GND
=20mA MIL.
-
0.3
O.S
10L = 24mA COM'L.
-
0.3
0.5
Vo=OV
-
-
-
-40
Vo = Vee
10L = 300p.A
10L
-30
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
3-108
MAX.
40
-135
UNIT
V
V
V
p.A
mA
IDT49C4D1/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
VCC = 5.0V ± 5%
Vcc = 5.0V ± 10%
SYMBOL
ICCQH
ICCQL
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
Min. = 4.75V
Min. = 4.50V
TA = O°C to +70°C
TA = -55°C to +125°C
VLC = 0.2V
VHC = VCC - 0.2V
TEST CONDITIONS(')
PARAMETER
Quiescent Power Supply Current
CP = H
Quiescent Power Supply Current
CP=L
Vcc = Max.
VHC ::; V'N' V,N ::; VLC
MIN.
TYP.(')
-
-
-
rnA
-
-
-
rnA
-
-
-
MAX.
fcp = 0, CP = H
Vcc = Max.
VHC :::; V'N' V,N :::; VLC
fcp = 0, CP = L
mAl
ICCT
Quiescent Input Power Supply(S)
Current (per Input @ TTL High)
Vcc = Max. V,N = 3.4V, fcp = 0
-
-
-
Dynamic Power Supply Current
Vcc = Max.
VHC :5 V,N• V,N :::; VLC
Outputs Open, OE = L
MIL.
ICCD
COM'L.
-
-
-
Vcc = Max., fcp = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
MIL.
-
-
-
COM'L.
-
-
-
MIL.
-
70
150
COM'L.
-
70
125
VHC :5 V,N • V,N ::; VLC
Total Power Supply Current(6)
Icc
UNIT
Input
mAl
MHz
rnA
Vcc = Max., fcp = IOMHz
Outputs Open, OE = L
CP = 50% Duty cycle
V ,H = 3.4V, V,L = O.4V
NOTES:
5. leeT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out 'CCQH' then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply Current
can be calculated by using the following equation:
Icc
=ICCOH(CDH)
+ ICCOL (1 - CD H) + ICCT (NT' DH) + Iceo (fcp)
CD H = Clock duty cycle high period.
DH = Data duty cycle TTL high period (V rN ::: 3.4V).
NT::: Number of dynamic inputs driven at TTL levels.
f GP ::: Clock Input frequency.
IDT49C401A
AC ELECTRICAL CHARACTERISTICS
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of the
IDT49C401 A over the -55°C to +125°C and O°Cto +70°C temperature ranges. All times are in nanoseconds and are measured
between the 1.5V signal level. The inputs switch between OV and
3V with signal transition rates of 1V per nanosecond. All outputs
have maximum DC current loads.
MIL.
COM'L.
UNITS
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
28
24
ns
Maximum Clock Frequency to shift
Q (50% duty cycle, I=C32 or E32)
35
41
MHz
Minimum Clock LOW Time
13
11
ns
Minimum Clock HIGH Time
13
11
ns
Minimum Clack Period
36
31
ns
COMBINATIONAL PROPAGATION DELAYS(1) (CL = 50pF)
TO OUTPUT
FROM INPUT
(MSS = L)
G,P
Y
(MSS= H)
Qo
RAMo
RAM ••
F=O
C n+16
OVR
F ••
Q ••
UNIT
MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
A, B Address
41
37
39
35
41
37
41
37
37
34
41
37
40
36
-
-
ns
D
32
29
29
26
29
26
31
28
27
25
32
29
28
26
-
-
ns
Cn
29
26
-
-
26
24
25
23
20
18
29
26
23
21
-
-
ns
10,1.2
35
32
30
27
35
32
34
31
29
26
35
32
30
27
-
-
ns
13.4,5
35
32
28
26
34
31
34
31
27
25
35
32
28
26
-
-
ns
16,7,8,9
25
23
-
-
-
-
~
-
-
-
-
-
20
18
20
18
ns
A Bypass
ALU (I = AXX,
lXX,3XX)
30
27
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
34
31
31
28
33
30
34
31
30
27
34
31
34
31
25
23
ns
Clock
-
3-109
I
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES.
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
~
CP:
~
SET-UPTIME
BEFOREH-L
INPUT
MIL.
SET-UPTIME
BEFOREL-H
HOLD TIME
AFTERH-L
COM'L.
A,B Source Address
11
10
B Destination Address
10
0
11
_(1)
Cn
-
la,1,2
-
13,4,5
-
-
16,7,8,9
11
10
RAMa,15> Q a,15
-
-
COM'L.
0(3)
MIL.
0(3)
MIL.
24 (4)
HOLD TIME
AFTER L-H
COM'L.
COM'L.
0
0
ns
0
0
ns
21 (4)
Do not change (2 )
-
-
12/22(5)
10/20(5)
0
0
ns
17
15
0
0
ns
28
25
0
0
ns
28
25
0
0
ns
0
0
ns
0
0
ns
Do not change(2)
-
UNIT
MIL.
-
11
12
NOTES:
1.
A dash indicates a propagation delay or set-up time constraint does not exist.
2.
Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3.
Source addresses must be stable prior to the H-L transition to allow time to access the source data before the latches close. The A address may then be changed.
The B address CQuid be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed during the clock
LOW time.
4.
The set-up time prior to the clock L-H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all the time
from stable A and B addresses to the clock L-H transition. regardless of when the clock H-L transition occurs.
5.
First value is direct path (DATA'N - RAM/O Register). Second value is indirect path (DATA'N - ALU - RAM/O Register).
IDT49C401
AC ELECTRICAL CHARACTERISTICS
CYCLE TIME AND CLOCK CHARACTERISTICS
(Military and Commercial Temperature Ranges)
MIL.
COM'L.
UNITS
50
48
ns
Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)
The tables below specify the guaranteed performance of the
IDT49C401 over the -55°C to +125°C and O°C to +70°C temperature ranges. All times are in nanoseconds and are measured
between the 1.5V signal level. The inputs switch between OVand
3V with signal transition rates of 1V per nanosecond. All outputs
have maximum DC current loads.
Maximum Clock Frequency to shift
Q (50% duty cycle, I=C32 or E32)
20
21
MHz
Minimum ·Clock LOW Time
30
30
ns
Minimum Clock HIGH Time
20
20
ns
Minimum Clock Period
50
48
ns
COMBINATIONAL PROPAGATION DELAYS(1) (CL = 50pF)
TO OUTPUT
FROM INPUT
(MSS=L)
G,P
(MSS=H)
RAMo
00
F=O
Cn+18
OVR
RAM,.
0,.
Fi5
UNIT
MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
Y
A, B Address
52
47
47
42
52
47
47
42
38
34
52
47
44
40
0
35
32
34
31
35
32
34
31
27
25
35
32
28
26
Cn
29
26
-
-
29
26
27
25
20
18
29
26
23
21
1a,1,2
41
37
30
27
41
37
38
35
29
26
41
37
30
27
13,4,5
40
36
28
.26
40
36
37
34
27
25
40
36
28
26
-
16,7,8,9
26
24
-
-
-
-
-
-
-
-
-
-
20
18
A Bypass
ALU (I = AXX,
lXX,3XX)
30
27
-
-
-
-
-
-
-
-
-
-
-
42
38
41
37
42
38
41
37
30
27
42
38
41
Clock
-
3-110
-
ns
-
ns
-
ns
-
ns
20
18
ns
-
-
-
ns
37
25
23
ns
ns
IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)
~
CP:
-
~I(.
~
SET-UPTIME
BEFORE H-L
INPUT
MIL.
HOLD TIME
AFTER H-L
COM'L.
A,B Source Address
20
18
B Destination Address
18
D
20
_(1)
Cn
-
-
10,1.2
-
13,4,5
I
I
MIL.
0(3)
SET-UPTIME
BEFOREL-H
COM'L.
0(3)
COM'L.
MIL.
HOLD TIME
AFTER L-H
MIL.
46(4)
50(4)
Do not change(2)
-
UNIT
COM'L.
ns
0
0
0
0
ns
-
30/40(5)
26/36(5)
0
0
ns
-
35
32
0
0
ns
-
-
-
45
41
0
0
ns
-
-
-
-
45
41
0
0
ns
16,7,8,9
12
11
0
0
ns
RAM o.15,QO,15
-
-
0
0
ns
Do not change(2)
-
-
11
12
NOTES:
1.
A dash indicates a propagation delay or set-up time constraint does not exist.
2.
Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3.
Source addresses must be stable prior to the H-L transition to allow time to access the source data before the latches close. The A address may then be changed.
The B address could be changed if it is not a destination; Le., if data is not being written back into the RAM. Normally A and B are not changed during the clock
LOW time.
4.
The set-up time prior to the clock L -H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all the time
from stable A and B addresses to the clock l-H transition, regardless of when the clock H-l transition occurs.
5.
First value is direct path (DATA 'N - RAM/Q REGISTER). Second value is indirect path (DATA 'N - ALU - RAM/Q REGISTER).
IDT49C401
OUTPUT ENABLE/DISABLE TIMES
CAPACITANCE
(C L = 5pF, measured to 0.5V change of VOUT in nanoseconds)
INPUT
OUTPUT
OE
Y
DISABLE
ENABLE
MIL.
25
I COM'L.
I 23
SYMBOL
MIL.
25
(TA = +25°C, f = 1,OMHz)
PARAMETER(!)
I COM'L.
C 'N
Input Capacitance
I
C OUT
Output Capacitance
23
CONDITIONS
Y,N
=OV
VOUT = OV
TYP.
UNIT
5
pF
7
pF
NOTE:
1. This parameter is sampled and not 100% tested.
I DT49C401 A
OUTPUT ENABLE/DISABLE TIMES
(C L = 5pF, measured to 0.5V change of VOUT in nanoseconds).
INPUT
OUTPUT
OE
Y
ENABLE
MIL.
22
input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DISABLE
I COM'L.
I
AC TEST CONDITIONS
20
MIL.
20
I COM'L.
I
18
TEST LOAD CIRCUITS
Vee
14711
VOUT
---~~~~~~~~Ja~.~
m~~~~_~N~~~~~:~~~
Os 17
Dg 18
11
12
Vee
OE
D~
Bo
D13
Bl
D14
B2
DIS
B3
YIS
B4
Y14
BS
Y13
16
Y12
17
Yll
Is
Yl0
Ig
Yg
MSS
F=O
RAMIS
G/FIS
QIS
P/OVR~:...:-_ _ _~~_ C n +16
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
02 10
03 11
0412
Ds 13
06 14
07 15
GNO 16
01019
D1120
012 21
01322
D1423
01524
YIS 25
Y1426
A3
A2
Al
Ao
13
14
15
10
11
12
Vee
OE
BO
Bl
B2
45 B3
44 B4
~~~~~~~~~~~=~~~~~
~~~~~~~~~~~=~~~~~
... -
0
c0::IE::IE
It, Iii: U
::
MSD49C402-002
MSD49C402-003
LCC
TOP VIEW
OIP
TOP VIEW
o
~~~~~~2~~~~lm~~J~~
A3
As
17
Is
Ig
MSS
RAMIS
QIS
Cn +16
P/OVR
G/FIS
F=O
Yg
Yl0
Yl1
Y12
Y13
Y14
A4
QO
RAMo
CP
Cn
Y7
Ys
Ys
Y6
Y3
Y4
Yl
Y2
Yo
PGA
TOP VIEW
3-114
MSD49C402-004
IDT49C402lA 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
PIN NAME
1/0
Ao-A5
I
Six address inputs to the register file which selects one register and displays its contents through the A-port.
Bo-B5
I
Six address inputs to the register file which selects one of the registers in the file, the contents of which are
displayed through the B port. It also selects the location into which new data can be written when the clock goes
Law.
10-19
I
Ten instruction control lines which determine what data source will be applied to the ALU 1(0.'.2); what function the
ALU will perform 1\3.4.5); and what data is to be deposited in the a Register or the register file 1(6.7,8.9)' Original 2901
destinations are se ected if 19 is disconnected. In this mode, proper 19 bias is controlled by an internal pull up resistor
to Vcc.
0 0-0'5
I
Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU,
YO-Y'5
a
Sixteen three-state output lines which, when enabled, display either the sixteen outputs of the ALU or the data on
the A-port of the register stack. This is determined by the destination code 1(6.7.8.9)'
G/F'5
a
A multipurpose pin which indicates the carry g~erate. G, function at the least significant and intermediate slices. or as
F'5' the most sil!!'ificant ALU output (sign bit). G/F'5 selection is controlled by MSS pin. If MSS ; HIGH, F'5 is enabled.
If MSS ; LOW, G is enabled.
F;O
a
Open drain output which goes HIGH if the Fo-F'5 ALU outputs are all LOW. This indicates that the result of an ALU
operation is zero (positive logic).
Cn
I
Carry-in to the internal ALU.
C n+16
a
Carry-out of the internal ALU.
DESCRIPTION
a Register or
RAM. Do is the LSB.
0,5
RAM'5
1/0
Bidirectional lines controlled by 1(6.7,8.9)' Both are three-state output drivers connected to the TTL-compatible
inputs. When the destination code on I (6.7,8.9) indicates an up shift, the three-state outputs are enabled and the MSB
of the a Register is available on the 0'5 pin and the MSB of the ALU output is available on the RAM'5 pin. When the
destination code indicates a down shift, the pins are the data inputs to the MSB of the a Register and the MSB
of the RAM.
00
RAMo
I/O
Both bidirectional lines function identically to 0'5 and RAM'5lines except they are the LSB of the
RAM.
a Register and
OE
I
Output enable. When pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y outputs are
enabled.
PIOVR
a
A multipurpose pin which indicates the carry propagate (P) output for performing a carry-Iookahead operation or
overflow (OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MSB. OVR, at the most significant end of
!.he word, indicates that the result of an arithmetic two's complement operation has overfloweO-
4
OUTPUTS
flo<
IoL
MS039C01C-007
Figure 2. Input Structure
(All Inputs)
MSD39C~1 C-008
Figure 3. Output Structure
(All Outputs Except F = 0)
3-122
MSD39COl C-009
Figure 4. Output Structure
(F= Only)
IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CRITICAL SPEED PATH ANALYSIS
Critical speed paths for the IDT49C402A vs the equivalent
bipolar circuit implementation using four 2901Cs and one 2902A
is shown below.
The lOT49C402A operates faster than the theoretically achievable values of the discrete bipolar implementation. Actual speed
values for the discrete bipolar circuit will increase due to onchip/off-chip circuit board delays.
TIMING COMPARISON IDT49C402A vs 2901C w/2902A
DATA PATH
(MIL.)
DATA PATH
(COM'L.)
16-BIT
UNITS
~PSYSTEM
AB ADDR- F=O
Four 2901Cs +
2902A
2:
AB ADDR - RAMo,15
71
2:
71
AB ADDR -.. F = 0
2:
AB ADDR - RAMo,15
83.5
2:
83.5
ns
IDT49C402A
37
36
41
40
ns
Speed SavIngs
34
35
42.5
43.5
ns
TIMING COMPARISON IDT49C402 vs 2901C w/2902A
DATA PATH
(COM'L.)
16-BIT
~P SYSTEM
AB ADDR - F= 0
Four 2901 Cs +
2902A
2:
71
DATA PATH
(MIL.)
AB ADDR - RAMo,15
2:
71
ABADDR - F=O
2:
83.5
UNITS
AB ADDR - RAMo,15
2:
83.5
ns
IDT49C402
47
40
52
44
ns
Speed SavIngs
24
31
31.5
39.5
ns
3-123
MICROSLICET• PRODUCT
FEATURES:
DESCRIPTION:
• Monolithic 16-bit CMOS I'P slice
• Replaces four 2903As/29203s and a 2902A
The IDT49C403/A are high-speed, fully cascadable 16-bit
CEMOS'· microprocessor slices. They combine the standard
functions of four 2903s/29203s and one 2902, with additional
control features aimed at enhancing the performance of all bitslice microprocessor designs.
Included in these extremely low-power, yet fast, IDT49C403
devices are: 3 bidirectional data buses, 64 word x 16-bit dual-port
expandable RAM, 4 word x 16-bit Q Register file, parity generation, sign extension, multiplication/division and normalization
logic. Additionally, the IDT49C403s offer the special feature of
enhanced byte support through both Word/BYTE control and
BYTE swap control.
The lOT49C403s easily support fast 100ns microcycles and will
enhance the speed of all existing quad 2903Af29203 systems by
20%. Being specified at an extremely low 150mA maximum
(commercial), the lOT devices offer an immediate system power
savings and improved reliability.
The devices are packaged in either 108-pin PGAs or 144-pin
leaded chip carriers. Military product is 100% screened to MILSTD-883, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
• Fast
-20% faster than four 2903As/29203s and a 2902A
• Low-power CMOS
-Commercial - 150mA (max.)
-Military - 200mA (max.)
• Performs binary and BCD arithmetic
• Expandable two-address architecture with independent,
simultaneous access to internal 64 x 16 register file
•
•
•
•
Word/BYTE control
Expanded 4 word x 16-bit Q Register
Performs BYTE swap operation
Fully cascadable without the need for additional
carry-Iookahead
• Incorporates three 16-bit bidirectional buses
• High output drive
-Commercial - 24mA (max.)
-Military - 20m A (max.)
• Available in 108-pin grid array and 144-pin leaded chip carrier
• Military product 100% screened to MIL-STD-883, Class B
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
01986 Integrated Device Technology,
Inc.
JULY 1986
Printed in U.S.A.
3-124
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE
FUNCTIONAL BLOCK DIAGRAM
A
DATA'N
B
AI>-. >----+-----_.1 ADDRESS
ADDRESS
64 x 16 RAM
CJ Bo_.
I....W~E~---------<:IWE
I.........:>--CP
u>_--------------<
EAL->----~------~~
10Es
t--;:===========;--JS:;>jDB O-'.
DAI>-'.
Cn+15 C::J-------l------...::s;::RR:I>-=,.:-' 1'~S;:_::;4-------------l-~ClCn
GIN <-J-----j-------~
SIO o
~OVR<=r-----~------------~--~==~~--------~
alO o
SIO,.
alo,.~~---_+--~====~--~:::r::~--~
ao_,
a
4 x 16
REGISTERS
OE y
10-8~
LSS
MSS
WRITE
INST.
DECODE
Yo_,s
I--_--K">I Z
C]---I
WID . - - - - - '
MSD49C403~001
3-125
MICROSLICE T• PRODUCT
FEATURES:
DESCRIPTION
• High-speed
-Supports 8O-100ns microcycles
The IOT49C404 "SYSTEM-SLICE" is an expandable, microprogrammable, high-speed microprocessor slice. This monolithic three-port device consists of a powerful 32-bit ALU, 64-word
x~2-bit RAM, cascadable funnel shifter, priority encoder, merge
logic and mask generator.
This monolithic device has been optimized, both architecturally
and instruction set-wise, for use in ultra-high-speed controllers,
high-speed graphic engines, as well as high-speed communication disk controllers and special purpose mini-computers.
The IOT49C404 is fabricated using CEMOS", lOT's advanced
CMOS technology designed for high-performance and highreliability. It will be packaged in a 196-pin PGA and a 1XX-pin
surface mount package.
• Low-power CMOS
-700mA typo (dynamic)
-450mA typo (quiescent)
• 32-bit ALU cascadable to 64 bits
• 64-word x 32-bit RAM
- Easily expandable
• Three bidirectional 32-bit data I/O ports
-OA, DB, Y
•
•
•
•
•
•
•
•
•
Powerful, yet simple, instruction set
Cascadable funnel shifter
Powerful mask generator
Versatile merge logic
Built-In multiplication/division
Counter function
Priority encoder
Single 5V supply
Available in 196-pin PGA and surface mount package
CEMOS. MICROSLICE and SYSTEM-SLICE are trademarks of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
c 1988 Integrated Device Technology, Inc.
3-126
JULY 1986
Printed in U.S.A.
FEATURES:
DESCRIPTION:
• 16-bit wide address path
-Address up to 65,536 words of microprogram memory
The I DT49C410s are architecture and function code compatible
to the 2910A with an expanded 16-bit address path, thus allowing
for programs up to 65,536 words in length. They are microprogram
address sequencers intended for controlling the sequence of
execution of microinstructions stored in microprogram memory.
Besides the capability of sequential access, they provide conditional branching to any microinstruction within their 65,536
microword range.
The 33-deep stack provides microsubroutine return linkage and
looping capability. The deep stack can be used for highly nested
microcode applications. Microinstruction loop count control is
provided with a count capacity of 65,536.
During each microinstruction, the microprogram controller
provides a 16-bit address from one of four sources: 1) the
microprogram address register (I'PC), which usually contains an
address one greater than the previous address; 2) an external
(direct) input (D); 3) a register/counter (R) retaining data loaded
during a previous microinstruction; or 4) a last-in, first-out stack
• 16-bit loop counter
-Pre-setlable down-counter for counting loop
iterations and repeating instructions
• Low-power CEMOS"
-ICC (max.)
Military - 90mA
Commercial - 75mA
• Fast
-IDT49C410 meets 2910A speeds
-IDT49C410A 30% speed upgrade
• 33-deep stack
-Accomodates highly nested microcode
• 16 powerful microinstructions
-Executes 16 sequence control instructions
(F).
• Available in 48-pin DIP (600 mil),
(400 mil x 70 mil centers), 48-pin LCC and 52-pin PLCC
•
•
•
•
The IDT49C410s are fabricated using CEMOS, a single-poly
double-metal CMOS technology designed for high-performance
and high-reliability.
The IDT49C410s are pin-compatible, performance-enhanced,
easily upgradable versions of the 2910A.
The IDT49C410s are available in 48-pin DIPs (600 mil x 100 mil
centers or space-saving 400 mil x 70 mil centers), 48-pin LCCs
and 52-pin PLCCs.
Three enables control branch address sources
Four address sources
2910A instruction compatiblity
Military product available 100% screened to
MIL-STO-883, Class B
FUNCTIONAL BLOCK DIAGRAM
D,
cp
MSD49C410-001
MICROSLICE and CEMOS are trademarks of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL T~MPERATURE RANGES
111986 Integrated Device Technology, Printedlnc.
JULY 1986
i"U.S.A.
3-128
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
Y13
013
YS
012
Y12
03
Y3
02
Os
V2
VECT
MAP
PL
01
VI
00
13
p[
MAP
13
12
Vo
Vee
37::
----.!o
35::
Y4
04
VECT
CI
CP
GNO
12
Vee
II
II
VII
CC
lffi)
32::
011
Y10
CC
011
FULL
:: 18 20 21 22 23 24 25 26 27 28 29 31:::
010
FULL
Vl0
010
06
YB
07
Vg
Og
Y7
Os
VIS
01S
19r1 r1 n r, r1 " r, " " " n r,3O
Vs
MSD49C410-003
LCC
TOP VIEW
(560 mil x 560 mil)
MSD49C410-002
IDT49C410 PIN FUNCTIONS
DESCRIPTION
D,
Direct Input Bit i
I,
Instruction Bit i
CC
Condition Code
CCEN
Condition Code
Enable
FUNCTION
Direct input to register/counter
and multiplexer, Do is LSB.
Selects one-of-sixteen
instructions.
Carry-In
Used as test criterion. Pass test
is a LOW on CC.
Whenever the signal is HIGH,
CC is ignored and the part
operates as though CC were
true (LOW).
Low order carry input to
incrementer for microprogram
counter.
RLD
Register Load
OE
Output Enable
PL
CI
CP
GNO
OE
VII
DIP
FULL
Yo
38::
CCEN
TOP VIEW
(600 mil x 100 mil centers)
(400 mil x 70 mil centers)
Vee
GND
Y,
391:
CCEN
YI4_~__________~
CP
VI
00
OE
014
CI
40::
10
lffi)
PIN NAME
01
Clock Pulse
When LOW forces loading of
register/counter regardless of
instruction or condition.
Three-state control of 'Ii
outputs.
Triggers all internal state
changes at LOW-to-HIGH edge.
5 Volts
Ground
Microprogram
Address Bit i
Full
Pipeline Address
Enable
MAP
Map Address
Enable
VECT
Vector Address
Enable
Address to microprogram
memory. Yo is LSB, Y'5 is MSB.
Indicates that 33 items are on
the stack.
Can select #1 source (usually
Pipeline Register) as direct
input source.
Can select #2 source (usually
Mapping PROM or PLA) as
direct input source.
Can select #3 source (for
example, Interrupt Starting
Address) as direct input source.
3-129
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT DESCRIPTION
The IDT49C410s are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed microprogrammable microprocessor applications. The sequencers
allow for direct control of up to 64K-words of microprogram.
The heart of the microprogram sequencer is a 4-input multiplexer that is used to select one of four address sources to select
the next microprogram address. These address sources include
the register/counter, the direct input, the microprogram counter,
or the stack as the source for the address of the next microinstruction.
The register/counter consists of sixteen D-type flip-flops which
can contain either an address or a count. These edge-triggered
flip-flops are under the control of a common clock enable as well
as the four microinstruction control inputs. When the load control
(RLD) is LOW, the data at the D-inputs is loaded into this register
on the LOW-to-HIGH transition of the clock. The output of the
register/counter is available at the multiplexer as a possible next
address source for the microcode. Also, the terminal count output
associated with the register/counter is available at the internal
instruction PLA to be used as a condition code input for some of
the microinstructions. The IDT49C410s contain a microprogram
counter that usually contains the address of the next microinstruction compared to that currently being executed. The
microprogram counter actually consists of a 16-bil incrementer
followed by a 16-bit register. The microprogram counter will
increment the address coming out of the sequencer going to the
microprogram memory if the carry-in input to this counter is
HIGH; otherwise, this address will be loaded into the microprogram counter. Normally, this carry-in input is set to the logic
HI G H state so that the incrementer will be active. Should the carry
input be set LOW, the same address is loaded into the microprogram counter. This is a technique that can be used to allow
execution of the same microinstruction several times.
There are sixteen D-inputs on the IDT49C41 Os that go directly
to the address multiplexer. These inputs are used to provide a
branch address that can come directly from the microcode or
some other external source. The fourth input available to the
multiplexer for next address control is the 33-deep, 16-bit wide
LIFO stack. The LIFO stack provides return address linkage for
subroutines and loops. The IDT49C410s contain a built-in stack
pointer that always points to the last stack location written. This
allows for stack reference operations, usually called loops, to be
performed without popping the stack.
The stack pointer internal to the IDT49C410s is actually an
up/down counter. During the execution of microinstructions one,
four and five, the PUSH operation may occur depending on the
state of the condition code input. This causes the stack pointer to
be incremented by one and the stack to be written with the
3-130
required return linkage (the value contained in the microprogram
counter). On the microprogram cycle following the PUSH, this
new return linkage data that was in the microprogram counter is
now althe new location pointed to by the stack pointer. Thus, any
time the multiplexer looks at the stack, it will see this data on the
top of the stack.
During five different microinstructions, a pop operation associated with the stack may occur. If the pop occurs, the stack
pointer is decremented althe next LOW-to-HIGH transition of the
clock. A pop decrements the stack pointer which is the equivalent
of removing the old information from the top of the stack.
The IDT49C410s are designed so that the stack pointer linkage
allows any sequence of pushes, pops or stack references to be
used. The depth of the stack can grow to a full 33 locations. After a
depth of 33 is reached, the FULL output goes LOW. If further
PUSHes are attempted when the stack is full, the stack information at the top of the stack will be destroyed but the stack
pointer will not end around. It is necessary to initialize the stack
pointer when power is first turned on. This is performed by
executing a RESET instruction (instruction 0). This sets the stack
pointer to the stack empty position-the equivalent depth of O.
Similarly, a pop from an empty stack may place unknown data on
the Y outputs, but the stack pointer is designed so as not to end
around. Thus, the stack pointer will remain at the 0 or stack empty
location if a pop is executed while the stack is already empty.
The IDT49C41 Os' internal 16-bit register/counter is used during
microinstructions eight, nine, and fifteen. During these instructions, the 16-bit counter acts as a down counter and the terminal
count (count = 0) is used by the internal instruction PLA as an
input to control the microinstruction branch test capability. The
design of the internal counter is such that, if it is preloaded with a
number N and then this counter is used in a microprogram loop,
the actual sequence in the loop will be executed N + 1 times. Thus,
it is possible to load the counter with a count of 0 and this will
result in the microcode being executed one time. The 3-way
branch microinstruction, instruction 15, uses both the loop
counter and the external condition code input to control the final
source address from the Y outputs of the microprogram
sequencer. This 3-way branch may result in the next adresss
coming from the 0 inputs, the stack or the microprogram counter.
The IDT49C410s provide a 16-bit address at the Y outputs that
are under control of the OE input. Thus, the outputs can be put in
the three-state mode, allowing the writeable control store to be
loaded or certain types of external diagnostics to be executed.
In summary, the IDT49C410s are the most powerful microprogram sequencers currently available. They provides the
deepest stack, the highest performance, and the lowest power
dissipation for today's microprogrammed machine design.
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FIGURE 1. IDT49C410 FLOW DIAGRAMS
o Jump Zero (JZ)
1 Cond JSB PL (CJS)
65
66
67
68
69
70
3 Cond Jump PL (CJP)
2 Jump Map (JMAP)
H
4 Push/Cond LD CNTR (PUSH)
66
~ ~86
t ~
68 STACK
40
41
42
43
S Cond JSB R/PL (JSRP)
6
5h
67
65
66 t < : 8 STACK
65
68
69
67
68
66
67
68
69
25
26
REGISTERI
COUNTER
N
6 Cond Jump Vactor (CJV)
30V70~40
71
41
7 Cond JUMP R/PL (JRP)
A
31
32
33
34
5
66
67
68
20
21
8 Repeat Loop, CNTR '" 0 (RFCT)
72
42
43
44
T 30
T 31
9 Repast PL, CNTR .. 0 (RPCT)
10 Cond Raturn (CRTN)
STACK
(PUSH)
65
66
REGISTER/
COUNTER
67
68
69
70
67
68
11 Cond Jump PL " POP (CJPP)
65
66
67
68
69
70
71
~
N
COUNTER
(LDCT)
65
66
67
68
69
70
12 LD CNTR " Continue (LDCT)
STACK
(PUSH)
\IJ--+---.....
14 Continue (CO NT)
66
65
67
68
65
66
t
40
41
42
:~ ~COUNTER
30
31
32
33
34
35
36
37
13 Test End Loop jLOOP)
67
68
1S Three-Way Branch (TWB)
65~7
~
67
68
69
N
STACK
(PUSH)
REG~n~
COUNTER
72
73
3-131
65
66
67
68
69
70
71
72
STACK
(PUSH)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
IDT49C410 OPERATION
necessary internal control signals to control each particular part
of the microprogram sequencer. The next address at the Y outputs
olthe IOT49C410s can be from one offoursources. These include
the internal microprogram counter; the last-in, first-out stack; the
register/counter and the direct inputs.
The following paragraphs will describe each instruction associated with the IOT49C410s. As a part olthe discussion, an exam~e
of each instruction is shown in Figure 1. The purpose of the
examples is to show microprogram flow. Thus, in each example
the microinstruction currently being executed has a circle around
it. That is, this microinstruction is assumed to be the contents of
the pipeline register althe output olthe microprogram memory. In
these drawings, each of the dots refers to the time that the
contents of the microprogram memory word would be in the
pipeline register and currently being executed.
The lOT49C41OS are CMOS pin-compatible implementations of
the Am2910 & 2910A microprogram sequencers. The IOT49C410
sequencers are functionally identical except that they are 16 bits
wide and provide a 33-deep stack to give the microprogrammer
more capability in terms of microprogram subroutines and microprogram loops. The definition of each microprogram instruction
is shown in the table of instructions. This table shows the results of
each instruction in terms of controlling the multiplexer which
determines the Y outputs, and in controlling the signals that can
be used to enable various branch address sources (PL, MAp,
VECT). The operation of the register/counter and the 33-deep
stack after the next LOW-to-HIGH transition of the clock are also
shown. The internal multiplexer is used to select which of the
internal sources is used to drive the Y outputs. The actual value
loaded into the microprogram counter is either identical to the Y
output or the Y output value is incremented by 1 and placed in the
microprogram counter. This function is under the control of the
carry input. For each of the microinstruction inputs, only one of
the three outputs (PL, MAP or VECT) will be LOW. Note that this
function is not determined by any of the possible condition code
inputs. These outputs can be used to control the three-state
selection of one of the sources for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the
conditional instructions. These are fully defined in the table of
instructions. The RLO input can be used to load the internal
register/counter at any time. When this input is LOW, the data at
the 0 inputs will be loaded into this register/counter on the LOWto-HIGH transition of the clock. Thus, the RLO input overrides the
internal hold or decrement operations specified by the various
microinstructions. The OE input is normally LOW and is used as
the three-state enable for the Y Ol!tputs. The internal stack in the
IOT49C410s is a last-in, first-out memory that is 16 bits in width
and 33 words deep. It has a stack pOinter that addresses the stack
and always pOints to the value currently on the top of the stack.
When instruction 0 (RESET) is executed, the stack pOinter is
initialized to the top of the stack which is, by definition, the stack
empty condition. Thus, the contents of the top of the stack are
undefined until the forced PUSH occurs. A pop performed while
the stack is empty will not change the stack pointer in any way,
however it will result in unknown data at the Y outputs.
By definition, the stack is full any time 33 more PUSHes than
pops have occurred since the stack was last empty. When this
happens, the FULL flag will go LOW. This signal first goes LOW on
the microcycle after the 33 pushes occur. When this signal is LOW,
no additional pushes should be attempted or the information on
the top of the stack will be lost.
INSTRUCTION 0JUMP 0 (JZ)
This instruction is used at power-up time or at any restart
sequence when the need is to reset the stack pointer and jump to
the very first address in microprogram memory. The jump 0
instruction does not change the contents of the register/counter.
INSTRUCTION 1CONDITIONAL JUMP TO SUBROUTINE (CJS)
The conditional jump to subroutine instruction is the one used
to call microprogram subroutines. The subroutine address will be
contained in the pipeline register and presented at the 0 inputs. If
the condition code test is passed, a branch is taken to the
subroutine. Referring to the flow diagram for the IOT49C410s
shown in Figure 1, we see that the content of the microprogram
counter is 68. This value is pushed onto the stack and the top of
stack pointer is incremented. If the test is failed, then this
conditional jump to subroutine instruction behaves as a simple
continue. That is, the contents of microinstruction address 68 is
executed next.
INSTRUCTION 2JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction opcode.
This is typically accomplished by using a mapping PROM as an
input to the 0 inputs on the microprogram sequencer. The JMAP
instruction branches to the address appearing on the 0 inputs. In
the flow diagram shown in Figure 1, we see that the branch
actually will be to the contents of microinstruction 85 and this
instruction will be executed next.
INSTRUCTION 3CONDITIONAL JUMP PIPELINE (CJP)
THE IDT49C410 INSTRUCTION SET
This data sheet contains a block diagram of the IOT49C410
microprogram sequencers. As can be seen, the devices are
controlled by a 4-bit microinstruction word (I:rlo). Normally, this
word is supplied from one 4-bit field of the microinstruction word
associated with the entire state machine system. These four bits
provide forthe selection of one olthe sixteen powerful instructions
associated with selecting the addressolthe next microinstruction.
Unused Y outputs can be left open; however, the corresponding
most significant 0 inputs should be tied to ground for smaller
microwords. This is necessary to make sure the internal operation
of the counter is proper should less than 64K of microcode be
implemented. As shown in the block diagram, the internal
instruction PLA uses the four instruction inputs as well as the CC,
CCEN and the internal counter : 0 line for controlling the
sequencer. This internal instruction PLA provides all of the
3-132
The Simplest branching control available in the IOT49C410
microprogram sequencers is that of conditional jump to address.
In this instruction, the jump address is usually contained in the
microinstruction pipeline register and presented to the 0 inputs. If
the test is passed, the jump is taken while, if the test fails, this
instruction executes as a simple continue. In the example shown
in the flow diagrams of Figure 1, we see that ilthe test is passed the
next micrOinstruction to be executed is the contents of address
25. If the test is failed, the microcode simply continues to the
contents of the next instruction.
INSTRUCTION 4PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally loaded
during the same instruction that pushes the current value of the
microprogram counter on to the stack. Under any condition
independent olthe conditional testing, the microprogram counter
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410 INSTRUCTION OPERATIONAL SUMMARY
ADDRESS
SOURCE
REGISTERI
COUNTER
ENABLE
SELECT
CLEAR
0
NC
PL
PUSH
NC
D
PC
NC
NC
PL
PL
X
NC
D
NC
MAP
X
X
NC
NC
D
PC
NC
NC
PL
PL
X
X
PUSH
PUSH
PC
PC
LOAD
NC
PL
PL
PASS
FAIL
X
X
PUSH
PUSH
D
R
NC
NC
PL
PL
CJV
PASS
FAIL
X
X
NC
NC
D
PC
NC
NC
VECT
VECT
7
JRP
PASS
FAIL
X
X
NC
NC
D
R
NC
NC
PL
PL
8
RFCT
X
X
=0
NOT=O
POP
NC
PC
STACK
NC
DEC
PL
PL
9
RPCT
X
X
=0
NOT =0
NC
NC
PC
D
NC
DEC
PL
PL
10
CRTN
PASS
FAIL
X
X
POP
NC
STACK
PC
NC
NC
PL
PL
11
CJPP
PASS
FAIL
X
X
POP
NC
D
PC
NC
NC
PL
PL
COUNTER
TEST
STACK
X
X
PASS
FAIL
X
X
X
PASS
FAIL
PASS
FAIL
JSRP
6
13-10
MNEMONIC
0
JZ
1
CJS
2
JMAP
3
CJP
4
PUSH
5
CC
12
LDCT
X
X
NC
PC
LOAD
PL
13
LOOP
PASS
FAIL
X
X
POP
NC
PC
STACK
NC
NC
PL
PL
14
CONT
X
X
NC
PC
NC
PL
TWB
PASS
PASS
FAIL
FAIL
=0
NOT =0
=0
NOT=O
POP
POP
POP
NC
PC
PC
D
STACK
NC
DEC
NC
DEC
PL
PL
PL
PL
15
NC = no change; DEC = decrement
is pushed on to the stack. II the conditional test is passed, the
counter will be loaded with the value on the D inputs to the
sequencer. II the test lails, the contents 01 the counter will not
change. The PUSH/conditional load counter instruction is used
in conjunction with the loop instruction (Instruction 13), the
repeat lile based on the counter instruction (Instruction 9) orthe
3-way branch instruction (Instruction 15).
conditional test is passed, the branch is taken to the new address
on the D inputs. lithe conditional test is failed, no branch is taken
but rather the microcode simply continues to the next sequential
microinstruction. When this instruction is executed, the VECT
output is LOW unconditionallY. Thus, an external 16-bit field can
be enabled on to the 0 inputs of the microprogram sequencer.
INSTRUCTION 7CONDITIONAL JUMP R/PL (JRP)
INSTRUCTION 5CONDITIONAL JUMP TO SUBROUTINE RJPL (JSRP)
The conditional jump register/counter or external pipeline
register always causes a branch in microcode. This jump will be
to one oftwo different locations in the microcode address space.
If the test is passed, the jump will be to the address presented on
the 0 inputs to the microprogram sequencer. If the conditional
test fails, the branch will be to the address contained in the
internal register/counter.
Subroutines may be called by a conditional jump subroutine
Irom the internal register or Irom the external pipeline register. In
this instruction, the contents of the microprogram counter are
pushed on the stack and the branch adddress for the subroutine
call will be taken Irom either the internal register/counter or the
external pipeline register presented to the D inputs. If the
conditional test is passed, the subroutine address will be taken
from the pipeline register. If the conditional test fails, the branch
address is taken from the internal register/counter. An example of
this is shown in the flow diagram of Figure 1.
INSTRUCTION 8REPEAT LOOP COUNTER NOT EQUAL TO 0 (RFCT)
This instruction utilizes the loop counter and the stack to
implement microprogrammed loops. The start address for the
loop would be initialized by using the PUSH/conditional load
counter instruction. Then, when the repeat loop instruction is
executed, il the counter is not equal to 0, the next microword
address will be taken Irom the stack. This will cause a loop to be
executed as shown in the Figure 1 flow diagram. Each time the
microcode sequence goes around the loop, the' counter is
decremented. When the counter reaches 0, the stack will be
popped and the microinstruction address will be taken from the
INSTRUCTION 6CONDITIONAL JUMP VECTOR (CJV)
The conditional jump vector instruction is similar to the jump
map instruction in that it allows a branch operation to a
microinstruction as defined from some external source. This
instruction is similar to the jump map instruction except that it is
conditional. The jump map instruction is unconditional. If the
3-133
IDT49C410/A 18-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
microprogram counter. This instruction performs a timed wait or
allows a single sequence to be executed the desired number of
times. Remember, the actual number of loops performed is equal
to the value in the counter plus 1.
INSTRUCTION 9REPEAT PIPELINE, COUNTER NOT EQUAL TO 0 (RPCT)
This instruction is another technique for implementing a loop
using the 90unter. Here, the branch address for the loop is
contained in the pipeline register. This instruction does not use
the stack in any way as a part of its implementation. As long as the
counter is not equal to 0, the next microword address will be
taken from the D inputs of the microprogram sequencer. When
the counter reaches 0, the internal multiplexer will select the
address source from the microprogram counter, thus causing the
microcode to continue on and leave the loop.
INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The conditional return instruction is used for terminating
subroutines. The fact that it is conditional allows the subroutine
either to be ended orto continue.lfthe conditional test is passed,
the address of the next microinstruction will be taken from the
stack and it will be popped. If the conditional test fails, the next
microinstruction address will come from the internal microprogram counter. This is depicted in the flow diagram of Figure 1.
It is important to remember that every subroutine call must
somewhere be followed by a return from subroutine call in order
to have an equal number of pushes and pops on the stack.
INSTRUCTION 11CONDITIONAL JUMP PIPELINE AND POP (CJPP)
The conditional jump pipeline and pop instruction is a technique
for exiting a loop from within the middle of the loop. This is
depicted fully in the flow diagrams for the IDT49C410s as shown
in Figure 1. The conditional testinput for this instruction results
in a branch being taken ifthetest is passed. The address selected
will be that on the D inputs to the microprogram sequencer and
since the loop is being terminated, the stack will be popped.
Should the test be failed on the conditional test inputs, the
microprogram will simply continue to the next address as taken
from the microprogram counter. The stack will not be affected if
the conditional test input is failed.
INSTRUCTION 12LOAD COUNTER AND CONTINUE (LDCT)
The load counter and continue instruction is used to place a
value on the D inputs in the register/counter and continue to the
next microinstruction.
INSTRUCTION 13TEST END OF LOOP (LOOP)
The test end of loop instruction is used as a last instruction in a
loop associated with the stack. During this instruction, if the
conditional test Input is failed, the loop branch address will be
3-134
that on the stack. Since we may go around the loop a number of
times, the stack is not popped. If the conditional test input is
passed, then the loop is terminated and the stack is popped.
Notice thatthe loop instruction requires a PUSH to be performed
at the instruction immediately prior to the loop return address.
This is necessary so as to have the correct address on the stack
before the loop operation. It is for this reason that the stack
pointer always points to the last thing written on the stack.
INSTRUCTION 14CONTINUE (CONT)
The continue instruction is a simple instruction whereby the
address for the microinstruction is taken from the microprogram
counter. This instruction simply causes sequential program flow
to the next microinstruction in microcode memory.
INSTRUCTION 15THREE WAY BRANCH (TWB)
The three way branch instruction is used for looping while
waiting for a conditional event to come true. If the event does not
come true after some number of microinstructions, then a branch
is taken to another microprogram sequence. This is depicted in
Figure 1 showing the IDT49C410 flow diagrams and is also
described in full detail inthe IDT49C410s' instruction operational
summary. Operation of the instruction is such that any time the
external conditional test input is passed, the next microinstruction
will be that associated with the program counter and the loop will
be left. The stack is also poppecj. Thus, the external test input
overrides the other possibilities. Should the external conditional
test input not be true, then the rest of the operation is controlled
by the internal counter. If the counter is not equal to 0, the loop is
taken by selecting the address on the top of the stack as the
address out of the Y outputs olthe IDT49C410s.ln addition, the
counter is decremented. Should the external conditional test
input be failed and the counter also have counted to 0, then this
instruction "times out:' The result is that the stack is popped and
a branch is taken to the address presented to the D inputs of the
IDT49C410 microprogram sequencers. This address is usually
provided by the external pipeline register.
CONDITIONAL TEST
Throughout this discussion we have talked about microcode
passing the conditional test. There are actually two inputs
associated with the conditional test input. These include the
CCEN and the CC inputs. The CCEN input is a condition code
enable. Whenever the CCEN input is HIGH, the CC input is
ignored and the device operates as though the CC input were
true (LOW). Thus, a fail of the external test condition can be
defined as CCEN equals LOW and CC equals HIGH. A pass
condition is defined as a CCEN equal to HIGH or a CC equal to
LOW. It is important to recognize the full function of the condition
code enable and the condition code inputs in order to understand when the test is passed or failed.
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
VTERM
VALUE
UNIT
-0.5(3) to +7.0
V
-55 to +125
°C
-65 to +135
°C
-65 to +150
°C
1.0
W
RATING
Terminal Voltage
with Respect
toGND
Operating
TA
Temperature
T BIAS
Temperature
Under Bias
TSTG
Storage
Temperature
PT
Power Dissipation l ')
lOUT
DC Output Cu rrent
into Outputs
GRADE
Military
Commercial
GND
-55°C to +125°C
OV
5.0V± 10%
O°C to +70°C
OV
5.0V± 5%
Vee
CAPACITANCE (TA = +25° C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYP.
UNIT
C 'N
Input Capacitance
V,N = OV
5
pF
C OUT
Output Capacitance
VOUT = OV
7
pF
SYMBOL
mA
30
AMBIENT
TEMPERATURE
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
NOTE:
1. This parameter is sampled and not 100% tested.
2. P T maximum can only be achieved by excessive IOl or 'OH'
3. V 1L Min. = -3.0V for pulse width less than 20n5.
DC ELECTRICAL CHARACTERISTICS
Vcc = +5.0V ± 5%
Vcc = +5.0V ± 10%
Min. = +4.75V
Min. = +4.50V
TA = O°C to +70°C
TA = -55°C to +125°C
VLC = +0.2V
VHC = Vcc - 0.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
Max. = +5.25V (Commercial)
Max. = +5.50V (Military)
MIN.
TYP.(')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Levell')
2.0
-
-
V'L
Input LOW Level
Guaranteed Logic Low Levell')
-
-
0.8
V
I'H
Input HIGH Current
Vee
5
p.A
I nput LOW Current
-
0.1
I,L
= Max., V,N = Vce
Vec = Max., V,N = GND
-0.1
-5
p.A
VHe
Vee
-
2.4
4.3
-
2.4
4.3
-
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Vee = Min.
V,N = V,H or V'L
Vcc = Min.
V 1N ::;: V 1H or V 1L
loz
Off State (High Impedance)
Output Current
Vee
los
Output Short Circuit Current
Vee
=-3OOIlA
10H =-12mA MIL
10H =-15mA COM'L
10L =300ilA
10L =20mA MIL
10L =24mA COM'L
10H
-
GND
V Le
-
0.3
0.5
-
0.3
0.5
-
-
-40
-
-
40
-30
-
-130
Vo = OV
= Max.
Vo
=Vcc
= Max., VOUT =OV(3)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25 D C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
3-135
V
V
V
I'A
mA
IDT49C4101A 16-BIT CMOS MICROPROGRAM SEQUENCER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
=
Vcc =+5.0V ± 5%
Vcc = +5.0V ± 10%
Min. = +4.75V
Min. = +4.50V
TA O·C to +70°C
TA = -55°C to +125°C
VLc = +O.2V
VHC = Vcc - O.2V
SYMBOL
Max. = +5.25V (Commercial)
Max. = +5.50V (Military)
TEST CONDITIONS(1)
PARAMETER
MIN.
TYR(2)
MAX.
UNIT
-
-
-
mA
ICCOH
Quiescent Power Supply Current
CP = H (CMOS Inputs)
VCC= Max.
VHC OS; Y'N' Y,N OS; VlC
Fc=O,CP=H
ICCOl
Quiescent Power Supply Current
CP = L (CMOS Inputs)
Vcc = Max.
VHC OS; Y,N' Y,N OS; VlC
Fc=O,CP=L
-
-
-
mA
ICCT
Quiescent Input Power Supply
Current (per Input @ TTL High)(S)
Vcc = Max. Y,N = 3.4V, fcp = 0
-
-
-
Input
Dynamic Power Supply Current
VCC= Max.
VHC OS; Y,N' Y'N OS; VlC
Outputs Open, OE = L
MIL.
-
-
-
Icco
COM'L.
-
-
-
MIL.
-
50
90
COM'L.
-
50
75
Icc
Vce = Max., fcp = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC OS; Y,N' Y'N OS; VlC
Total Power Supply Current(6}
Vec = Max., fcp = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
V,H = 3.4V, V,l = 0.4V
MIL.
COM'L.
mAl
mAl
MHz
-
mA
NOTES:
5. teeT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCQH,then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions. the Total Supply Current
can be calculated by using the following equation:
Icc
=ICCOH(CDH) + ICCOl (1
- CD H) + ICCT (NT x D H) +
'cco (fcp)
CD H =Clock duty cycle high period.
DH = Data duty cycle TTL high period (V 1N = 3.4V).
NT = Number of dynamic inputs driven at TTL levels.
fcp = Clock Input frequency.
IDT49C410 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
OUTPUTS
--
INPUTS o--wl<--+-D......hL
I0T49C41~
IDT49C41O-00a
Figure 1. Input Structure (All Inputs)
Figure 2. Output Structure (All Outpull)
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
(nput Timing Reference Levels
Output Reference Levels
Output Load
GNDto3.0V
WIns
1.5V
1.5V
See Fig. 3
3-136
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C410/A 16-BIT CMOS MICROPROGRAM SEQUENCER
IDT49C410A
AC ELECTRICAL CHARACTERISTICS
Commercial: 5.0V ± 5%, TA = O°C to +70°C
Military: 5.0V ± 10%, TA = -55°C to +125°C
IDT49C410
AC ELECTRICAL CHARACTERISTICS
Commercial: 5.0V ± 5%, TA = O°C to +70°C
CL = 50pF
Military: 5.0V ± 10%, TA = -55°C to +125°C
CL = 50pF
I. SET-UP AND HOLD TIMES
I. SET-UP AND HOLD TIMES
INPUTS
1(0)
II")
COM'L.
MIL.
COM'L.
Dj-R
6
7
0
OJ-PC
13
15
0
10 •3
23
25
CC
15
CCEN
15
CI
RLD
MIL.
UNITS
INPUTS
COM'L.
MIL.
UNITS
0
Dj-R
16
16
0
0
0
ns
OJ-PC
30
30
0
0
ns
0
0
ns
10 •3
35
38
0
0
ns
18
0
0
ns
CC
24
35
0
0
ns
18
0
0
ns
CCEN
24
35
0
0
ns
6
7
0
0
ns
CI
18
18
0
0
ns
11
12
0
0
ns
RLD
19
20
0
0
ns
PL, VECT, MAP
FULL
Y
COM'L.
MIL.
COM'L.
0 0 . 11
12
15
-
-
20
25
13
15
CC
16
20
-
CCEN
16
20
-
CP
28
33
-
10/10
13/13
-
-
ns
II. COMBINATIONAL DELAYS
MIL.
10-3
OEI')
II")
MIL.
ns
II. COMBINATIONAL DELAYS
INPUTS
liS)
COM'L.
COM'L.
-
22
-
MIL.
UNITS
Y
INPUTS
COM'L.
PL, VECT, MAP
MIL.
COM'L.
MIL.
FULL
COM'L.
MIL.
UNITS
-
ns
0 0 •11
20
25
-
-
-
-
ns
-
ns
10-3
35
40
30
35
-
-
ns
-
ns
CC
30
36
-
-
-
ns
-
ns
CCEN
30
36
-
-
-
-
ns
25
ns
40
46
-
-
31
ns
25/27
25/30
-
-
-
35
-
ns
-
CP
OE(1)
ns
NOTE:
NOTE:
1. Enable/Disable. Disable times measure to O.SV change on output voltage level
with C L = 5pF.
1. Enable/Disable. Disable times measure to O.SV change on output voltage level
wjth C L = 5pF.
III. CLOCK REQUIREMENTS
III. CLOCK REQUIREMENTS
COM'L.
MIL.
UNITS
COM'L.
MIL.
Minimum Clock LOW Time
18
20
ns
Minimum Clock LOW Time
20
25
ns
Minimum Clock HIGH Time
17
20
ns
Minimum Clock HIGH Time
20
25
ns
Minimum Clock Period
35
40
ns
Minimum Clock Period
50
51
ns
UNITS
SWITCHING WAVEFORMS
TEST LOAD CIRCUITS
3.0V----~
Vee
INPUTS
OV - - - - - "
147fl
3.0V
CLOCK
VaUT -
------+
OV
....
75n
OUTPUTS
_ _ _ _----"2lII
MSD49C410-004
MSD49C410-005
Figure 3. Swllchlng Tesl Circuit
(aU oulputs)
3-137
I
MICROSLICE™ PRODUCT
FEATURES:
DESCRIPTION:
• Fast
- Error detect
IDT49C460A - 30ns (max.), IDT49C460 - 40ns (max.)
- Error correct
IDT49C460A - 36ns (max.), IDT49C460 - 49ns (max.)
The IDT49C460s are high-speed, low-power, 32-bit Error Detection and Correction Units which generate check bits on a 32-bit
data field according to a modified Hamming Code and correct the
data word when check bits are supplied. The IDT49C460s are
performance-enhanced functional replacements for 32-bit versions of the 2960. When performing a read operation from
memory, the IDT49C460s will correct 100% of all single bit errors,
will detect all double bit errors and some triple bit errors.
The IDT49C460s are easily cascadable to 64-bits. Thirty-two-bit
systems use 7 check bits and 64-bit systems use 8 check bits. For
both configurations, the error syndrome is made available.
The IDT49C460s incorporate two built-in diagnostic modes.
Both simplify testing by allowing for diagnostic data to be entered
into the device and to execute system diagnostic functions.
They are fabricated using CEMOS", a single poly, double metal
CMOS technology designed for high-performance and highreliability. The devices are packaged in a 68-pin PGA, DIP (600 mil
centers) and LCC (25 mil and 50 mil centers). Military product is
100% screened to MIL-STD-883, Class B, making them ideally
suited to military temperature applications demanding the highest
level of performance and reliability.
• Low-Power CMOS
- Commercial - 95mA (max.)
- Military - 125mA (max.)
• Improves system memory reliability
- Corrects all single bit errors, detects all double and some
triple-bit errors
• Cascadable
- Data words up to 64-bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Functional replacement for 32- and 64-bit configurations
of the 2960
• Available in 68-pin PGA, DIP (600 mil, 70 mil centers),
LCC (25 and 50 mil centers)
• Military product available 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
LEOUT/GENERATE
OE BYTED-3
D---;4;------,
D'-a-*---,
32
CB~7 ~~~==::J5it~~~~r;;;~~~~;,~~~l:J
DATAo-3t
MULTERROR
~~~=:r==::"'l
LEDIAG
CODE ID (
2
DIAG MODE D...:2~_....
LEoUT/GENERATE w~-........~
CORRECT D----I-I
MS049C460-001
CEMOS and MICROSLICE are trademarks of Integratad Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
01986 Integrated Device Technology. Inc.
JULY 1986
Printed In U.S.A.
3-138
IOT49C460/A 32-BIT CMOS
ERROR OETECTION ANO CORRECTION UNIT
MILITARY ANO COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE3
COOEo
COOEl
OIAG MOOEo
OIAG MOOEl
LEIN
OEo
031
030
029
028
027
026
025
GNO
00
01
02
03
04
05
06
07
08
016
09
010
011
012
013
014
015
OQ
OE 1
CB7
CB6
CBs
CB4
CB3
CB2
CBl
__________~
12
60 024
59 023
58 D22
13
57 021
10
0211
D3
04
05
06
07
08
017
Vee
GNO
CBO~
Vee
024
023
022
021
020
019
018
Vee
56 020
55 019
54 018
53 017
14
15
16
17
52
GNO 18
LEOUT/GENERATE
CORRECT
LEDIAG
ERROR
MULT ERROR
GNO
OEse
SC7
SC6
SCs
SC4
SC3
SC2
SCl
SCo
09
010
011
012
013
014
015
23
24
25
OEl
26
Vee
51 016
19
50 OE2
49 LEOUT/GENERATE
48 CORRECT
47 LEDIAG
20
21
22
46
ERROR
45
MULT ERROR
GNO
44
~re~g(ry~~~~~:;~~~~~~
~~~~MN~OO~N~~~~~O
mmmmmmmmUUUUUUUU0
UUUUUUUU~~~~~~~~~
MSD49C460-003
LCC
TOP VIEW
MSD49C460-002
OIP
TOP VIEW
OEse
SC7
SC6
SCs
SC4
SC3
SC2
SCl
SCo
CBo
CBl
CB2
CB3
CB4
CBs
CB6
025
027
026
029
028
031
030
COOEO
OE3
OIAG MOOEO
COOEl
LEIN
OIAG MOOEl
00
OEO
01
•
MSD49C460-004
PGA
TOP VIEW
3-139
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
PIN NAME
DATAo_3'
1/0
I/O
DESCRIPTION
32 bidirectional data lines. They provide input to the Data Input Latch and Diagnostic Latch and also receive output
from the Data Output Latch. DATAo is the LSB; DATA 3, is the MSB.
CB o_7
I
Eight check bit input lines. Used to input check bits for error detection and also used to input syndrome bits for error
correction in 64-bit applications.
LEIN
I
Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input
Latch are latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input Latch follow the input data and input check bits.
LEoUTI
GENERATE
I
A multifunction pin which, when LOW, is in the Check Bit Generate mode. In this mode, the device generates the
check bits or partial check bits specific to the data in the Data Input Latch. The generated Check Bits are placed on
the SC outputs. Also when LOW, the Data Out Latch is latched to its previous state.
When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple errors,
and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch. In the
Correct Mode, single bit errors are also automatically corrected, with the corrected data placed at the inputs of the
Data Output Latch. The syndrome result is placed on the SC outputs and indicates in a coded form the number of
errors and the specific bit-in-error. When HIGH, the Data Output Latch follows the output of the Data Input Latch as
modified by the correction logic network. In Correct Mode, single bit errors are corrected by the network before
being loaded into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch are passed through
the correction network unchanged into the Data Output Latch. The Data Output Latch is disabled, with its contents
unchanged, if the EDC is in the Generate Mode.
SC O_7
0
Syndrome Check Bit outputs. Eight outputs which hold the check and partial check bits when the EDC is in the
Generate Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct modes.
All are 3-state outputs.
OEsc
I
Output Enable - Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state.
When LOW, all SC output lines are enabled.
ERROR
0
In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When
HIGH, no errors have been detected. This pin is forced HIGH in the Generate Mode.
MULT ERROR
0
In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level
indicates that either one or no errors have been detected. This pin is forced HIGH in the Generate Mode.
CORRECT
I
The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input
Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will
drive data directly from the Data Input Latch to the Data Output Latch without correction.
OE BYTEO-3
I
Output Enable - Bytes 0, 1, 2, 3. Data Output Latch. Control the three-state output buffers for each of the four bytes
of the Data Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH, they
force the Data Output Latch buffer into the high impedance mode. One byte of the Data Output Latch is easily activated by separately selecting the four enable lines.
DIAG MODEo.,
I
Selects the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC.
CODE 100.,
I
These two code identification inputs identify the size of the total data word to be processed. The two allowable data
word sizes are 32- and 64-bits and their respective modified Hamming Codes are deSignated 32139 and 64/72. Special
CODE 10 input 01 is also used to instruct the EDC that the Signals CODE 100", DIAG MODE o., and CORRECT
are to be taken from the Diagnostic Latch rather than from the input control lines.
LE 01AG
I
This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the
input lines. When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch
holds diagnostic check bits and internal control signals for CODE 100 .1, DIAG MODE o., and CORRECT.
3-140
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
EDC ARCHITECTURE SUMMARY
ERROR DETECTION LOGIC:
The IDT49C460N460are high-performance cascadable EDCs
used for check bit generation, error detection, error correction
and diagnostics. The function blocks for this 32-bit device consists of the following:
This part of the device decodes the syndrome bits generated
by the Syndrome Generation Logic. With no errors in either the
input data or check bits, both the ERROR and MULT ERROR
outputs are HIGH. ERROR will go low if one error is detected.
MULT ERROR and ERROR will both go low if two or more errors
are detected.
•
•
•
•
•
•
•
•
•
Data Input Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Data Output Latch
Diagnostics Latch
Control Logic
ERROR CORRECTION LOGIC:
In single error cases, this logic complements (corrects) the
single data bit-in-error. This corrected data is loaded into the
Data Output Latch, which can then be read onto the bidirectional
data lines. If the error is resulting from one of the check bits, the
correction logic does not place corrected check bits on the
syndrome/check bit outputs. If the corrected check bits are
needed, the EDC must be switched to the Generate Mode.
DATA INPUT/OUTPUT LATCH:
The Latch Enable Input, LEIN, controls the loading of 32 bits
of data to the Data In Latch. The 32 bits of data from the DATA
lines can be loaded in the Diagnostic Latch under control of the
Diagnostic Latch Enable, LEDIAG, giving check bit information
in one byte and control information in the other byte. The Diagnostic Latch is used in the Internal Control mode or in one of the
Diagnostic modes. The Data Output Latch has buffers that place
data on the DATA lines. These buffers are split into four 8-bit
buffers, each having their own output enable controls. This feature facilitates byte read and byte modify operations.
The Data Output Latch is used for storing the result of an error
correction operation. The latch is loaded from the correction
logic under control of the Data Output Latch Enable, LEoUTThe Data Output Latch may also be directly loaded from the Data
Input Latch under control of the PASS THRU control input. The
Data Output Latch buffer is split into 4 individual buffers which
can be enabled by OEo-3 separately for reading onto the bidirectional data lines.
CHECK BIT INPUT LATCH:
DIAGNOSTIC LATCH:
Eight check bits are loaded under control of LEINo Check bits
are used in the Error Detection and Error Correction modes.
A 32-bit latch is loadable, under control of the Diagnostic Latch
Enable, LE DIAG , from the bidirectional data lines. Check bit
information is contained in one byte while the other byte contains
the control information. The Diagnostic Latch is used for driving
the device when in the Internal Control Mode, or for supplying
check bits when in one of the Diagnostic Modes.
DATA OUTPUT LATCH AND OUTPUT BUFFERS:
CHECK BIT GENERATION LOGIC:
This generates the appropriate check bits for the 32 bits of
data in the Data Input Latch. The modified Hamming Code is the
basis for generating the proper check bits.
CONTROL LOGIC:
Specifies what mode the device will be operating in. Normal
operation is when the control logic is driven by external control
inputs. In the Internal Control Mode, the control signals are read
from the Diagnostic Latch. Since the LEoUT and GENERATE
are controlled by the same pin, the latching action, LEoUT from
high to low, of the data output latch causes the EDC to go into the
generate mode.
SYNDROME GENERATION LOGIC:
In both the Detect and Correct modes, this logic does a
comparison on the check bits read from memory against the
newly generated set of check bits produced for the data read in
from memory. Matching sets of check bits means no error was
detected. If there is a mismatch, then one or more of the data or
check bits is in error. Syndrome bits are produced by an
exclusive-OR of the two sets of check bits. Identical sets of check
bits means the syndrome bits will be all zeroes. If an error results,
the syndrome bits can be decoded to determine the number of
errors and the specific bit-in-error.
3-141
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED PRODUCT DESCRIPTION
TABLE 2.
DIAGNOSTIC MODE CONTROL
The IOT49C460/A EOC unlt contains the logic necessary to
generate check bits on 32 bits of data input according to a modified Hamming Code. The EOC can compare internally generated
check bits against those read with the 32-bit data to allow correction of any single bit data error and detection of all double and
some tri pie bit errors. The lOT49C4601A can be used for32-bit data
words (7 check bits) and 64-bit (a check bits) data words.
CORRECT
DIAG
MODE,
DIAG
MODE.
X
0
0
Non-diagnostic mode. Normal
EDC function in this mode.
1
Diagnostic Generate. The
contents of the Diagnostic Latch
are substituted for the normally
generated check bits when in the
Generate Mode. The EDC functions normally in the Detect or
Correct Modes.
Diagnostic Detect/Correct. In
either mode, the contents of the
Diagnostic Latch are substituted
for the check bits normally read
from the Check Bit Input Latch.
The EDC functions normally in
the Generate Mode.
CODE AND BYTE SELECTION
X
0
The 2 code identification pins, 100., are used to determine
the data word size that is 32- or 64-bits. Table 4 defines all
possible slice identification codes.
CHECK AND SYNDROME BITS
The IOT49C460/A provides either check bits or syndrome bits on
the three-state output pins, SCO-7• Check bits are generated from
a combination of the Data Input bits, while syndrome bits are an
exclusive-OR of the check bits generated from read data with the
read check bit sorted with the data. Syndrome bits can be
decoded to determine the single bit in error, or that a double
(some triple) error was detected. The check bits are labeled:
CX, CO, Cl, C2, C4,
CX, CO, Cl, C2, C4,
ca, C16
ca, C16, C32
for the 32-bit configuration
for the 64-bit configuration
DIAGNOSTIC MODE SELECTED
X
1
0
1
1
1
Initialize. The Data Input Latch
outputs are forced to zeroes (and
latched upon removal of Initialize
Mode) and the check bits generated corresponding to the all zero
data.
0
1
1
Pass Thru.
Syndrome bits are similarly labeled SX through S32.
TABLE 3.
IDT49C460 OPERATING MODES
OPERATING
MODE
DM!
DM.
GENERATE
CORRECT
DATA OUT LATCH
_ SC._?
(OEsc= LOW)
ERROR
MULTERROR
Generate
0
1
0
0
0
X
LEoUT = LOW(!)
Check Bits Generated from
Data In Latch
-
Detect
0
0
0
1
1
0
Data In Latch
Syndrome Bits Data Inl
Check Bit Latch
Error Dep(2)
0
Syndrome Bits Data Inl
Check Bit Latch
Error Dep
HIGH
0
0
1
1
1
Data In Latch wi
Single Bit Correction
Pass Thru
1
1
1
0
Data In Latch
Check Bit Latch
Diagnostic Generate
0
1
0
X
-
Check Bits from Diagnostic Latch
-
Diagnostic Detect
1
0
Data In Latch
Syndrome Bits Data Inl
Diagnostic Latch
Error Dep
1
Data In Latch wI
Single Bit Correction
Syndrome Bits Data Inl
Diagnostic Latch
Error Dep
1
Data In Latch
set to 0000
Check Bit Data generated
from Data In Latch
-
Correct
Diagnostic Correct
Initialization Mode
Internal Mode
1
1
0
0
1
CODE 100•1 = 01
1
1
1
Control Signals 100•1, DIAG MODE o.!, and CORRECT are taken from Diagnostic Latch.
NOTES:
1. In Generate Mode, data is read in to the EOC unit and the check bits are generated. The same data is written to memory along with the check bits. Since the Data Out
Latch is not used in the Generate Mode, LEoUT ' being LOW (since it is tied to Generate), does not affect the writing of check bits.
2. Error Dep (Error Dependent): ERROR will be low for Single or multiple errors, with MULT ERROR low for double or multiple errors. Both signals are high for noerrors.
3-142
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONTROL MODE SELECTION
Tables 2 and 3 describe the 9 operating modes of the
IDT49C460/A. The Diagnostic Mode pins, DIAG MODEo.1, define
four basic areas of operation, with GENERATE and CORRECT
further dividing operation into 8 functions with the IDo.1 defining
the ninth mode as the Internal Mode.
Generate Mode is used to display the check bits on the outputs
SCo-7. The Diagnostic Generate mode displays check bits as
stored in the Diagnostic Latch.
Detect mode provides an indication of errors or multiple errors
on the outputs ERROR and MULT ERROR. Single bit errors are
not corrected in this mode. The syndrome bits are provided on
the outputs SC(}-7' Forthe Diagnostic Detect Mode, the syndrome
bits are generated by comparing the internally generated check
bits from the Data In Latch with check bits stored in the
DATAo-31 HIGH C16 C8 C4 C2 C1
diagnostic latch rather than with the check bit latch contents.
Correct Mode is similar to the Delect Mode except that single
bit errors will be complemented (corrected) and made available
as input to the Data Out Latches. Again. the Diagnostic Correct
Mode will correct single bit errors as determined by syndrome
bits generated from the data input and contents olthe diagnostic
latches.
The Initialize Mode provides check bits for all zero bit data.
Data Input Latches are set and latched to a logic zero, and made
available as input to the Data Out Latches.
The Internal Mode disables the external control pins DIAG
MODE o.1 and CORRECT to be defined by the Diagnostic Latch.
Even ID,.o although externally set to the 01 code, can be
redefined from the Diagnostic Latch data.
DATA INPUT
CO CX
CHECK-BIT INPUTS
DATA32_63
CODE ID
IDT49C460/A
8
0,0
DATA
32
S16/C16 S4/C4
S1/C1
CB..7
IDT49C460/A
(LOWER 32 BITS)
CODE ID, •o
SC"7
Sx/CX
8
CBO_7
IDT49C460/A
OEsc ....-----I----'
(UPPER 32 BITS)
1,1
CODE ID,•o
Figure 1. 32-BII Conllguratlon
SC"7
8
SYNDROMEI
CHECK BITS
Figure 2. 64-Blt Conllgurallon
DATA
CHECK BITS
Figure 3. 32-Blt Data Format
CHECK BITS
Figure 4. 64-Blt Data Format
3-143
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
32-BIT DATA WORD CONFIGURATION
A single IDT49C460/A EOC unit, connected as shown in
Figure 1, provides all the logic needed for single bit error
correction and double bit error detection of a 32-bit data field.
The identification code indicates 7 check bits are required. The
CB 7 pin is therefore a "Don't Care" and 10 1 0 = 00.
Figure 3 indicates the 39-bit data format ior two bytes of data
and 7 check bits. Table 3 describes the operating mode available.
The output pin, SC 7, is forced HIGH for either syndrome or check
bits since only 7 check bits are used for the 32-bit mode.
Table 6 indicates the data bits participating in the check bit
generation. For example, check bit CO is the exclusive-OR function of the 16 data input bits marked with an X. Check bits are
generated and output in the Generate and Initialization Mode.
Check bits from the respective latch are passed, unchanged, in
the Pass Thru or Diagnostic Generate Mode.
Syndrome bits are generated by an exclusive-OR or the generated check bits with the read check bits. For example, SX is the
XOR of check bits CX from those read with those generated.
Table 7 indicates the decoding of the seven syndrome bits to
identify the bit-in-error for a single bit error or whether a double
or triple bit error was detected. The all zero case indicates no
errors detected.
In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or
mUltiple error detection, the data available as input to the Data
Out Latch is not defined.
Table 4 defines the bit definition for the Diagnostic Latch. As
defined in Table 3, several modes will use the Diagnostic check
bits to determine syndrome bits or to pass as check bits to the
SCo- 7 outputs. The Internal mode substitutes the indicated bit
position for the external control signals.
TABLE 4.
32-BIT DIAGNOSTIC
LATCH CODING FORMAT
TABLE 5. SLICE IDENTIFICATION
BITO
BITl
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BITB
BIT9
BIT 10
BIT11
BIT 12
BIT 13-31
CBo DIAGNOSTIC
CB, DIAGNOSTIC
CB. DIAGNOSTIC
CB 3 DIAGNOSTIC
CB. DIAGNOSTIC
CB 5 DIAGNOSTIC
CBs DIAGNOSTIC
CB 7 DIAGNOSTIC
CODE 100
CODE 10,
DIAG MODE o
DIAGMODE,
CORRECT
DON'T CARE
CODEID,
CODEIDo
SLICE SELECTED
0
0
1
1
0
1
0
1
32-Bil
Inlernal Control Mode
64-Bil, Lower 32-Bil (0-31)
64-Bil, Upper 32-Bil (32-63)
TABLE 6. 32-BIT MODIFIDED HAMMING CODE-CHECK BIT ENCODE CHARt
GENERATED
CHECK BITS
PARITY
CX
Even (XOR)
PARTICIPATING DATA BITS
0
CO
Even (XOR)
X
Odd (XNOR)
X
C2
Odd (XNOR)
X
C4
Even (XOR)
CB
Even (XOR)
C16
Even (XOR)
GENERATED
PARITY
2
3
X
Cl
CHECK BITS
1
X
X
X
4
6
7
8
9
X
X
X
X
X
X
X
X
X
X
X
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
17
18
19
20
21
X
X
X
X
X
X
11
12
13
X
15
X
X
X
X
X
14
X
X
X
X
X
10
X
X
X
X
X
X
X
X
X
X
26
27
30
31
X
PARTICIPATING DATA BITS
CX
Even (XOR)
CO
Even (XOR)
X
C1
Odd (XNOR)
X
C2
Odd (XNOR)
X
X
X
22
23
24
25
X
X
X
X
X
X
X
X
X
X
X
X
X
28
29
X
X
X
X
X
X
X
X
X
X
X
C4
Even (XOR)
X
X
C8
Even (XOR)
X
X
X
X
X
X
X
X
C16
Even (XOR)
X
X
X
X
X
X
X
X
X
X
X
3-144
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
54-BIT DATA WORD CONFIGURATION
TABLE l
SYNDROME DECODE TO BIT-IN-ERROR
SYNDROME
BITS
S16
S8
S4
1
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
SX
SO
S1
S2
0
0
0
0
0
0
0
1
T
C4
T
T
30
C2
T
T
27
T
5
M
T
0
0
1
0
C1
T
T
25
T
3
15
T
0
0
1
1
T
M
13
T
23
T
T
M
0
1
0
0
CO
T
T
24
T
2
M
T
0
1
0
1
T
1
12
T
22
T
T
M
0
1
1
0
T
M
10
T
20
T
T
M
0
1
1
1
16
T
T
M
T
M
M
T
1
0
0
0
CX
T
T
M
T
M
14
T
1
0
0
1
T
M
11
T
21
T
T
M
31
C16 C8
*
1
0
1
0
T
M
9
T
19
T
T
1
0
1
1
M
T
T
29
T
7
M
T
1
1
0
0
T
M
8
T
18
T
T
M
1
1
0
1
17
T
T
28
T
6
M
T
1
1
1
0
M
T
T
26
T
4
M
T
1
1
1
1
T
0
M
T
M
T
T
M
NOTES:
* - no errors detected
Number - number of the single bit-in-error
T - two errors detected
M - three or more errors detected
TABLES.
64-BIT DIAGNOSTIC LATCH
- CODING FORMAT
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13-31
32-39
40
41
42
43
44
45-63
INTERNAL FUNCTION
CBo DIAGNOSTIC
CB, DIAGNOSTIC
C6 2 DIAGNOSTIC
CB 3 DIAGNOSTIC
CB, DIAGNOSTIC
CBs DIAGNOSTIC
CB B DIAGNOSTIC
CB 7 DIAGNOSTIC
CODEo LOWER 32-BIT
CODE, LOWER 32-BIT
DIAG MOD Eo LOWER 32-61T
DIAG MODE, LOWER 32-BIT
CORRECT LOWER 32-BIT
DON'T CARE
DON'T CARE
CODE 10 0 UPPER 32-BIT
CODE 10, UPPER 32-BIT
DIAG MODE o UPPER 32-BIT
DIAG MODE, UPPER 32-BIT
CORRECT UPPER 32-BIT
DON'T CARE
Two IDT49C460/A EDC units, connected as shown in Figure2,
provide all the logic needed for single bit error correction and
double bit error detection of a 64-bit data field. Table 5 gives the
I D, 0 values needed for distinguishing the upper 32 bits from the
low'er 32 bits. Valid syndrome, check bits and the ERROR and
MULT ERROR signals come from the IC with the CODE ID = 11.
Control signals not indicated are connected to both units in
parallel. The EDC with the CODE ID = 10 has the OEscgrounded.
The OEscselects the syndrome bits from the EDC with CODE ID
= 11 and also controls the check bit buffers from memory.
Data In bits 0 through 31 are connected to the same numbered
inputs of the EDC unit with CODE ID = 10 while Data In bits 32
through 63 are connected to Data Inputs Oto 31, respectively, for
the EDC unit with CODE ID = 11.
Figure 4 indicates the 72-bit data format of 8 bytes of data and 8
check bits. Check bits are inputto the EDC unit with CODE ID = 10
through a three-state buffer unit such as the IDT74FCT244.
Correction of single bit errors of the 64-bit configuration requires
a feedback of syndrome bits from the lower EDC unitto the upper
EDC units. The MUX shown on the functional block diagram is
used to select the CBo-7 pins as the syndrome bits rather than
internally generated syndrome bits.
Table 3 describes the operating mode available for the 64/72
configuration.
Table 11 indicates the data bits partiCipating in the check bit
generation. For example, check bit CO is the exclusive-OR
function or the 32 data input bits marked with an X. Check bits are
generated and output in the Generate and Initialization Mode.
Check bits are passed as stored in the Pass Thru or Diagnostic
Generate Mode.
Syndrome bits are generated by an exclusive-OR ofthegenerated check bits with the read check bits. For example, SX is the
XOR of check bits CX from those read with those generated.
Table 9 indicates the decoding of the 7 syndrome bits to determine the bit in error for a single bit error or whether a double or
triple bit error was detected. The all zero case indicates no errors
detected.
In the Correct Mode, the syndrome bits are used to complement
(correct) single bit errors in the data bits. For double or multiple
error detection, the data available as input to the Data Out Latch
is not defined.
Table 8 defines the bit definition for the Diagnostic Latch. As
defined in Table 3, several modes will use the Diagnostic Check
Bits to determine syndrome bits or to pass as check bits to the
SCo- 7 outputs. The Internal Mode substitutes the indicated bit
position for the external control signals.
Performance data is provided in Table 10 in relating a single
IDT49C460/A EDC with the two cascaded units of Figure 2. As
indicated, a summation of propagation delays is required from
the cascading arrangement of EDC units.
3-145
IDT49C460/A 32·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 9. SYNDROME DECODE TO BIT-IN-ERROR
S32
S16
S8
S4
SYNDROME
BITS
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
SX
SO
S1
S2
0
0
0
0
.
C32
C16
T
C8
T
T
M
C4
T
T
M
T
46
62
T
0
0
0
1
C2
T
T
M
T
43
59
T
T
53
37
T
M
T
T
M
0
0
1
0
C1
T
T
M
T
41
57
T
T
51
35
T
15
T
T
31
0
0
1
1
T
M
M
T
13
T
T
29
23
T
T
7
T
M
M
T
0
1
0
0
CO
T
T
M
T
40
56
T
T
50
34
T
M
T
T
M
0
1
0
1
T
49
33
T
12
T
T
28
22
T
T
6
T
M
M
T
0
1
1
0
T
M
M
T
10
T
T
26
20
T
T
4
T
M
M
T
0
1
1
1
16
T
T
0
T
M
M
T
T
M
M
T
M
T
T
M
1
0
0
0
CX
T
T
M
T
M
M
T
T
M
M
T
14
T
T
30
1
0
0
1
T
M
M
T
11
T
T
27
21
T
T
5
T
M
M
T
1
0
1
0
T
M
M
T
9
T
T
25
19
T
T
3
T
47
63
T
1
0
1
1
M
T
T
M
T
45
61
T
T
55
39
T
M
T
T
M
1
1
0
0
T
M
M
T
8
T
T
24
18
T
T
2
T
M
M
T
1
1
0
1
17
T
T
1
T
44
60
T
T
54
38
T
M
T
T
M
1
1
1
0
M
T
T
M
T
42
58
T
T
52
36
T
M
T
T
M
1
1
1
1
T
46
32
T
M
T
T
M
M
T
T
M
T
M
M
T
NOTES:
* =No errors detected
Number = The number of the single bit-in-error
T = Two errors detected
M =Three or more errors detected
TABLE 10.
KEY AC CALCULATIONS FOR THE 64-BIT CONFIGURATION
64·BIT
PROPAGATION DELAY
COMPONENT DELAY FOR IDT49C460/A AC SPECIFICATIONS
FROM
TO
DATA
Check Bits Out
DATA
Corrected DATA Out
(DATA TO SC) + (CB TO SC, CODE ID 11) + (CB TO DATA, CODE ID 10)
DATA
Syndromes Out
(DATA TO SC) + (CB TO SC, CODE ID 11)
DATA
ERROR for 32-Bits
(DATA TO SC) + (CBTO ERROR, CODE ID 11)
DATA
MULT ERROR for 32-Bits
(DATA TO SC) + (CB TO MULT ERROR, CODE ID 11)
(DATA TO SC) + (CB TO SC, CODE ID 11)
3-146
IDT49C460/A 32·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE 11. 64-BIT MODIFIED HAMMING CODE - CHECK BIT ENCODING
GENERATED
CHECK BITS
CX
PARITY
PARTICIPATING DATA BITS
0
Even (XOR)
CO
Even (XOR)
X
Cl
Odd (XNOR)
X
C2
Odd (XNOR)
X
1
2
3
X
X
X
X
X
4
5
7
X
X
X
6
X
X
X
X
X
X
X
X
X
X
C4
Even (XOR)
Even (XOR)
C16
Even (XOR)
X
X
X
X
X
X
X
X
C32
Even (XOR)
X
X
X
X
X
X
X
X
16
17
18
19
20
21
X
X
X
X
X
GENERATED
CHECK BITS
CX
PARITY
X
X
9
X
X
C8
X
8
X
11
X
12
13
X
X
X
X
10
14
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
27
28
29
30
31
PARTICIPATING DATA BITS
Even (XOR)
CO
Even (XOR)
X
Cl
Odd (XNOR)
X
C2
Odd (XNOR)
X
X
X
22
23
X
X
X
X
24
25
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C4
Even (XOR)
C8
Even (XOR)
X
X
X
X
X
X
X
X
C16
Even (XOR)
X
X
X
X
X
X
X
X
C32
Even (XOR)
X
X
X
X
X
X
X
X
42
43
46
47
GENERATED
CHECK BITS
PARITY
X
Even (XOR)
X
CO
Even (XOR)
X
Cl
Odd (X NOR)
X
C2
Odd (XNOR)
X
C4
Even (XOR)
Even (XOR)
C16
Even (XOR)
C32
Even (XOR)
GENERATED
CHECK BITS
PARITY
X
X
CO
Even (XOR)
X
Cl
Odd (X NOR)
X
C2
Odd (XNOR)
X
Even (XOR)
Even (XOR)
C16
Even (XOR)
C32
Even (XOR)
X
X
X
34
35
X
X
38
39
X
X
X
X
X
36
X
X
X
X
X
X
37
X
X
40
X
X
X
X
X
X
X
X
X
X
X
41
44
45
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
58
59
62
63
X
PARTICIPATING DATA BITS
48
Even (XOR)
C4
33
X
CX
C8
X
PARTICIPATING DATA BITS
32
CX
C8
X
49
X
50
X
X
52
54
55
X
X
X
X
X
X
X
X
X
53
X
X
X
X
51
X
X
X
X
X
X
X
X
X
X
X
57
X
X
NOTE: The check bit IS generated as either an XOR or XNOR of the 32 data bits noted by an "X" in the table.
3·147
56
X
60
61
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IDT49C480/A 32·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SCOUTPUTS
The tables below indicate how the SCQ-7 outputs are generated
in each control mode for various CODE IDs (internal control
mode not applicable).
CODE ID, -o
CODE ID,-o
00
10
11
CORRECTI
DETECT
00
10
11
SCo~
PHO
PH1
PH2 e CBo
SCo~
PHO e CO
PH1 e CO
PH2 e CBo
SC,~
PA
PA
PA e CB,
SC,~
PA e C1
PA e C1
PA e CB,
SC2~
PB
PB
PB e CB 2
SC2~
PB e C2
PB e C2
PB e CB 2
SC3~
PC
PC
PC e CB3
SC3~
PC e C3
PC e C3
PC e CB3
SC4~
PO
PO
PO e CB 4
SC4~
PO e C4
PO e C4
PC e CB4
SC.~
PE
PE
PE e CB 5
SC5~
PE e C5
PE e C5
PE e CB 5
SCa~
PF
PF
PF e CBa
SCa~
PF e C6
PF e C6
PF e CBa
SC7~
1
PF
PG e CB 7
SC7~
1
PF e C7
PG e CB7
DIAGNOSTIC
READ
00
10
11
DIAGNOSTIC
WRITE
00
PHO e OLO
PH1 e OLO
10
PH2 e CBo
11
SCo~
OLO
OLO
CBo
SC,~
OL1
OL1
CB,
SC2~
OL2
OL2
CB 2
GENERATE
SCo~
CODE ID, -o
SC,~
PA e OL1
PAeOL1
PA e CB,
SC2~
PB e OL2
PB e OL2
PB e CB 2
SC3~
PC e OL3
PC e OL3
PC e CB3
SC4~
PO e OL4
PO e OL4
PO e CB4
SC5~
PE e OL5
PE e OL5
PE e CB 5
SCa~
PF e OL6
PF e OL6
PF e CBa
SC7~
1
PF e OL7
PG e CB 7
PASS
THRU
SCo~
CODE ID, -o
SC3~
OL3
OL3
CB 3
SC4~
OL4
OL4
CB 4
CB 5
SC5~
OL5
OL5
SC6~
OL6
OL6
CBa
SC7~
1
OL7
CB 7
CODEID, -o
00
10
11
CO
CO
CBo
SC,~
C1
C1
CB,
SC2~
C2
C2
CB 2
SC3~
C3
C3
CB3
SC4~
C4
C4
CB 4
SC5~
C5
C5
CB 5
SCa~
C6
C6
CBa
SC7~
1
C7
CB7
3·148
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA CORRECTION
FUNCTIONAL EQUATIONS
The tables below indicate which data output bits are corrected
depending upon the syndromes and the COOE 10 position. The
syndromes that determine data correction are, in some cases,
syndromes input externally via the CB inputs and, in some cases,
syndromes input externally by that EOC (Si are the internal
syndromes and are the same as the value ofthe SCi output of that
EOC if enabled).
The equations below describe the IOT49C460 output values
as defined by the value of the inputs and internal states.
32-BIT CONFIGURATION
CODE 101 ,0 =00
SYNDROME
BITS
516
sa
54
0
0
0
1
0
0
0
1
0
-
-
SX
SO
51
52
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
-
-
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
-
-
-
27
-
-
-
30
5
-
-
25
-
-
3
15
13
-
-
23
2
-
-
-
-
24
-
1
12
-
22
-
-
10
20
-
-
14
-
-
-
-
9
-
-
-
-
-
-
31
-
29
-
7
-
8
-
18
-
-
-
-
-
-
0
1
1
1
16
-
1
0
0
1
1
0
0
1
-
1
0
1
0
-
1
0
1
1
1
1
0
0
-
-
28
-
6
26
-
4
-
-
-
-
-
-
-
1
1
0
1
17
1
1
1
0
-
-
1
1
1
1
-
9
11
21
19
DEFINITIONS(1)
PA = 00 Ell 01 Ell 02 Ell 04 Ell 06 Ell 08 Ell 010 Ell 012 Ell 016 Ell
017 Ell 018 Ell 020 Ell 022 Ell 024 Ell 026 Ell 028
PB = 00 Ell 03 Ell 04 Ell 07 Ell 09 Ell 010 Ell 013 Ell 015 Ell 016 Ell
019 Ell 020 Ell 023 Ell 025 Ell 026 Ell 029 Ell 031
PC = 00 Ell 01 Ell 05 Ell 06 Ell 07 Ell 011 Ell 012 Ell 013 Ell
016 Ell 017 Ell 021 Ell 022 Ell 023 Ell 027 Ell 028 Ell 029
PO = 02 Ell 03 Ell 04 Ell 05 Ell 06 Ell 07 Ell 014 Ell 015 Ell
018 Ell 019 Ell 020 Ell 021 Ell 022 Ell 023 Ell 030 Ell 031
PE = 08 Ell 09 Ell 010 Ell 011 Ell 012 Ell 013 Ell 014 Ell
015 Ell 024 Ell 025 Ell 026 Ell 027 Ell 028 Ell 029 Ell 030 Ell 031
PF = 00 Ell 01 Ell 02 Ell 03 Ell D4 Ell 05 Ell 06 Ell 07 Ell
024 Ell 025 Ell 026 Ell 027 Ell 028 Ell 029 Ell 030 Ell 031
PG = 08 Ell 09 Ell 010 Ell 011 Ell 012 Ell 013 Ell 014 Ell
015 Ell 016 Ell 017 Ell 018 Ell 019 Ell 020 Ell 021 Ell 022 Ell 023
PHO = 00 Ell 04 Ell 06 Ell 07 Ell 08 Ell 09 Ell 011 Ell 014 Ell
017 Ell 018 Ell 019 Ell 021 Ell 026 Ell 028 Ell 029 Ell 031
PH1 = 01 Ell 02 Ell 03 Ell 05 Ell 08 Ell 09 Ell 011 Ell 014 Ell
017 Ell 018 Ell 019 Ell 021 Ell 024 Ell 025 Ell 027 Ell 030
PH2 = 00 Ell 04 Ell 06 Ell 07 Ell 010 Ell 012 Ell 013 Ell 015 Ell
016 Ell 020 Ell 022 Ell 023 Ell 026 Ell 028 Ell 029 Ell 031
NOTE:
1. 532 = 1 in CODE,.o = 00
64-BIT (UPPER-BIT) CONFIGURATION
CODE 101-0 =11(1)
64-BIT (LOWER 32-BIT) CONFIGURATION
CODE 101-0 = 10
SYNDROME
BITS
CB32
CB16
CBB
CB4
CBX CBO CB1 CB2
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
15
31
7
-
-
0
0
0
1
-
0
0
1
0
-
0
0
1
1
0
1
0
0
0
1
0
1
-
0
1
1
0
-
0
1
1
1
16
0
1
0
0
0
0
-
-
-
-
-
13
29
23
-
-
-
-
-
-
-
-
12
28
22
6
-
-
10
26
20
4
0
-
-
-
-
-
-
14
30
5
0
0
-
-
-
11
27
-
-
21
9
25
19
3
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
-
-
-
-
-
-
-
-
-
-
-
8
24
18
2
-
-
-
1
1
0
1
17
1
1
1
1
1
-
-
-
-
-
SYNDROME
BITS
3-149
532
516
SB
54
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
SX
SO
51
52
0
0
0
0
-
-
46
62
0
1
-
-
0
-
-
0
43
59
53
37
0
0
1
0
-
-
41
57
51
35
-
0
0
1
1
-
-
-
-
-
1
0
0
-
-
-
0
40
56
50
34
0
1
0
1
49
33
0
1
1
0
1
1
1
0
0
1
-
-
-
-
1
0
0
1
-
-
-
1
-
-
0
-
-
0
1
0
-
-
1
-
-
-
1
0
1
1
45
61
55
39
1
1
0
0
-
-
-
1
1
0
1
1
1
1
0
1
1
1
1
-
-
-
44
60
54
-
-
42
58
52
36
48
32
-
-
-
-
-
-
-
-
47
63
-
-
38
-
-
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect
toGND
VALUE
UNIT
-0.5(3) to +7.0
V
Operating
Temperature
-55 to +125
·C
TBIAS
Temperature
Under Bias
-65 to +135
·C
TSTG
Storage
Temperature
-65 to +150
·C
Disslpatlon (2 )
Power
lOUT
DC Output Current
Into Outputs
GRADE
Military
TA
PT
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
1.0
W
30
rnA
Commercial
AMBIENT
TEMPERATURE
GND
Vee
-55·C to +125·C
OV
5.0V± 10%
O·C to +70·C
OV
5.0V±5%
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated In the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. Pr maximum can only be achieved by exceSsive IOL or 'OH'
3. VIL Min. = -3.0V for pulse width I... than 20ns.
DC ELECTRICAL CHARACTERISTICS
TA = O°C to +70°C
Vee = 5.0V ± 5%
TA = -55°C to +125°C
VLe = 0.2V
VHe = Vee - 0.2V
Vee = S.OV
Min. =4.75V
Min. =4.50V
± 10%
Max. = S.25V (Commercial)
Max. = S.SOV (Military)
MIN.
TYP.II)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Levell')
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic Low Levell')
-
-
0.8
V
IIH
Input HIGH Current
Vec = Max., VIN = Vee
-
0.1
5
p.A
IlL
Input LOW Current
Vee = Max., VIN = GND
-
-0.1
-5
p.A
SYMBOL
VOH
VOL
TEST CONDITIONS(1)
PARAMETER
Output HIGH Voltage
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
Vee = Min.
VIN = VIH or VIL
loz
Off State (High Impedance)
Output Current
Vee = Max.
los
Output Short Circuit Current
Vee = Max., VOUT = OV(3)
10H = -300p.A
VHe
Vee
-
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
10L = 3OQp.A
-
GND
VLe
10L = 20mA MIL.
0.3
0.5
10L = 24mA COM'L.
-
0.3
0.5
Vo =OV
-
-
-40
Vo = Vee
-30
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee
=5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
3-150
40
-130
V
V
p.A
rnA
IDT49C460/A 32-BIT CM06
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd)
Vee = 5.0V ± 5%
Vee = 5.0V ± 10%
TA = O°C to +70°C
TA = -55°C to +125°C
VLe = O.2V
VHe = Vee - O.2V
SYMBOL
TEST CONDITIONS(')
PARAMETER
ICCQ
Quiescent Power Supply Current
(CMOS Inputs)
Vcc= Max.
VHC " V'N' V'N" VlC
fop= 0
ICCT
Quiescent Input Power Supply!S)
Current (per Input @TTL High)
Vcc = Max. V'N = 3.4V, fop = 0
ICCD
Dynamic Power Supply Current
Total Power Supply Current!S)
MIN.
UNIT
-
-
rnA
-
-
-
mAl
Input
MIL.
-
-
-
COM'L.
-
-
-
MIL.
-
70
125
COM'L.
-
70
95
MIL.
VHC " V'N' V'N " VlC
Outputs Open, OE = L
COM'L.
VHC " V'N' V'N" VlC
Vcc= Max., fop: 10MHz
Outputs Open, OE = L
50% Duty cycle
V'H = 3.4V, V'l = O.4V
TYP'(2)
MAX.
Vcc= Max.
Vcc: Max., fop: 10MHz
Outputs Open, OE = L
50% Duty cycle
Icc
Max. : 5.25V (Commercial)
Max. : 5.50V (Military)
Min. =4.75V
Min. =4.50V
-
mAl
MHz
rnA
NOTES:
5. 'eeT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out 'ceQ then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions. the Total Supply Current
can be calculated by using the following equation:
Icc= Icca+lccT(NTx D H) + ICCD(top)
DH = Data duty cycle TTL high period (V'N = 3.4V).
NT = Number of dynamic inputs driven at TTL levels.
fop= Operating frequency.
3-151
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460A over the O·C to +70·C commercial temperature
range. All times are In nanoseconds and are measured between
the 1.SV signallevei. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC load. Vee equal to +S.OV ± S%.
COMBINATIONAL PROPAGATION DELAYS
SET-UP AND HOLD TIMES
RELATiVE TO LATCH ENABLES
CL = SOpF
TO OUTPUT
FROM INPUT
SCo.7
TO
DATA0-31
ERROR
MULTERROR
FROM INPUT
(LATCHING
UP DATA)
SET-UP
TIME
HOLD
TIME
4
DATA().31
27
36
30
33
DAT~l
LEIN
5
C80-7
(CODE 1000. 11)
16
34
19
23
C80-7
LEIN
5
4
DATA0-31
LEoUT
23
0
C80-7
(CODE 10)
LEoUT
15
0
LEoUT
15
0
C80-7
(CODE 1010)
16
20
19
21
GENERATE
21
23
15
15
CORRECT
(Not Internal
Control Mode)
-
23
-
-
C80-7
(CODE 10 10)
DIAGMODE
(Not Internal
Control Mode)
CORRECT
LEoUT
11
0
17
26
20
24
DIAGMODE
LEoUT
17
0
CODE 100•1
LEoUT
17
0
LEIN
LEoUT
25
0
DATA0-31
LEOIAG
5
3
CODE 100•1
18
26
21
26
LEIN
(From latched
to transparent)
27
38 11)
30
33
LEoUT
(From latched
to transparent)
-
12
-
-
LEOIAG
(From latched to
transparent; Not
Internal Control
Mode)
15
29
19
22
Internal Control
Mode: LEOIAG
(From latched
to transparent)
16
Internal Control
Mode: DATA0-31
(Via Diagnostic
Latch)
16
19
32
00.11)
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with C L = SpF and measured
to O.SV change of output voltage level.
INPUT
OUTPUT
ENABLE
MIN.
MAX.
DISABLE
MIN. MAX.
OE 8YTEO-3
DATAO-31
10
23
10
19
OEsc
SC0-7
10
24
10
20
24
MINIMUM PULSE WIDTHS
I
32
20
LEIN• LEoUT' LEOIAG
25
NOTE:
1. OATA1N (or LE 1N) to Correct Data Out measurement requires timing
as shown in Figure 5 below.
CORRECT DATA
OUTPUT
LEIN
OE BYTEo.3
Figure 5.
3-152
9
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460A over the -SsoC to +12SoC military temperature
range. All times are in nanoseconds and are measured between
the 1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC load. Vee equal to +S.OV ±10%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
CL = SOpF
TO OUTPUT
FROM INPUT
SC0-7
DATA 0-31
ERROR
MULTERROR
DATA()'3'
30
39
33
36
CB()'7
(CODE 10 00,11)
19
37
22
26
CB()'7
(CODE 10 10)
19
23
22
24
GENERATE
24
26
18
18
CORRECT
(Not Internal
Control Mode)
-
26
-
-
DIAG MODE
(Not Internal
Control Mode)
CODE 10 0 .,
20
21
29
23
29
24
27
29
LE'N
(From latched
to transparent)
30
41
33
36
LEoUT
(From latched
to transparent)
-
15
-
-
LE D1AG
(From latched to
transparent; Not
Internal Control
Mode)
18
Internal Control
Mode: LE OIAG
(From latched
to transparent)
19
Internal Control
Mode: DATA o_3,
(Via Diagnostic
Latch)
19
22
35
22
23
LE'N
5
LE'N
5
4
DATA()'3'
LEoUT
27
0
CBo-7
(CODE 10 00,11)
LEoUT
18
0
CB()'7
(CODE 10 10)
LEoUT
18
0
CORRECT
LEoUT
14
0
DIAG MODE
LEoUT
20
0
CODE 10 0.,
LEOUT
20
0
LE'N
LEOUT
28
0
DATA()'3'
LE DIAG
5
3
to O.SV change of output voltage level.
OUTPUT
ENABLE
MAX.
MIN.
DISABLE
MIN.
MAX.
OE BYTEo_3
DATA o_31
10
25
10
21
OEsc
SC O_7
10
27
10
22
MINIMUM PULSE WIDTHS
DIAG
28
NOTE:
1. DATAIN (or LE 1N ) to Correct Data Out measurement requires timing
as shown in Figure 6 below.
VALID
INPUT DATA
4
DATAo-3'
I LE,N, LEOUT' LE
35
HOLD
TIME
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with C L = SpF and measured
25
27
SET-UP
TIME
CBo-7
INPUT
32
TO
(LATCHING
UP DATA)
FROM INPUT
,------rTTn
DATA0-31
LEIN
OE BYTE0-3
Figure 6.
3-153
CORRECT DATA
OUTPUT
12
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460 over the O°C to +70°C commercial temperature
range. All times are in nanoseconds and are measured between
the 1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC load. Vee equal to +S.OV ± S%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = SOpF
TO OUTPUT
FROM INPUT
TO
(LATCHING
UP DATA)
FROM INPUT
SET-UP
TIME
HOLD
TIME
SCo-7
DATAo-31
ERROR
MULTERROR
DATA0-31
37
49
40
45
DATA0-31
LEIN
6
4
CS0-7
(CODE ID 00,11)
22
46
26
31
CS0-7
LEIN
5
4
CS0-7
(CODE ID 10)
22
30
26
29
DATA0-31
LEoUT
30
0
GENERATE
29
31
21
21
CS0- 7
(CODE ID)
00,11)
LEoUT
20
0
CORRECT
(Not Internal
Control Mode)
-
31
-
-
CS0- 7
(CODE ID 10)
LEoUT
20
0
CORRECT
LEoUT
16
0
DIAGMODE
LEoUT
23
0
CODEID o.1
LEoUT
23
0
LEIN
LEoUT
31
0
DATAO-31
LE olAG
6
3
DIAGMODE
(Not Internal
Control Mode)
23
CODE ID o,1
25
LEIN
(From latched
to transparent)
35
27
33
35
29
35
37
51
41
45
LEoUT
(From latched
to transparent)
-
17
-
-
LE DIAG
(From latched to
transparent; Not
Internal Control
Mode)
21
38
26
30
Internal Control
Mode: LE 01AG
(From latched
to transparent)
22
Internal Control
Mode: DATA0-31
(Via Diagnostic
Latch)
22
42
26
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with C L = SpF and measured
to O.SV change of output voltage level.
INPUT
OUTPUT
ENABLE
MIN.
MAX.
DISABLE
MIN. MAX.
OE SYTE O-3
DATAO-31
10
27
10
23
OEse
SC0-7
10
28
10
24
33
MINIMUM PULSE WIDTHS
12
42
27
34
NOTE:
1. DATAIN (or LE 1N) to Correct Data Out measurement requires timing
as shown in Figure 7 below ..
CORRECT DATA
OUTPUT
VALID
INPUT DATA
DATAo-31
LEIN
OE BYTE0-3
Figure 7.
3-154
IDT49C460/A 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT49C460 over the -55°C to +125°C military temperature range.
All times are in nanoseconds and are measured between the
1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have
maximum DC load. Vee equal to +5.0V ± 10%.
SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES
COMBINATIONAL PROPAGATION DELAYS
C L = 50pF
TO OUTPUT
FROM INPUT
TO
SET-UP
TIME
HOLD
TIME
LE'N
6
4
LE'N
5
4
DATA(}'31
LEoUT
36
0
CB(}.7
(CODE ID)
00.11)
LEoUT
24
0
CB(}'7
(CODE ID 10)
LEoUT
24
0
CORRECT
LEoUT
20
0
DIAGMODE
LEoUT
28
0
CODEID o.1
LEoUT
28
0
LE'N
LEoUT
37
0
DATA(}'31
LE DIAG
6
3
DATA....,
ERROR
MULTERROR
52
44
48
DATA(}'31
25
49
29
34
CB(}.7
CB(}.7
(CODE ID 10)
25
33
29
32
GENERATE
32
34
24
24
CORRECT
(Not Internal
Control Mode)
-
34
-
-
DATA(}'31
CB(}'7
(CODE ID 00.11)
DIAG MODE
(Not Internal
Control Mode)
26
CODE ID o.1
28
38
30
38
32
36
38
LE'N
(From latched
to transparent)
40
54
44
48
LEoUT
(From latched
to transparent)
-
20
-
-
LE OIAG
(From latched to
transparent; Not
Internal Control
Mode)
24
42
29
33
Internal Control
Mode: LE DIAG
(From latched
to transparent)
25
Internal Control
Mode: DATA(}'31
(Via Diagnostic
Latch)
25
47
29
(LATCHING
UP DATA)
FROM INPUT
SC"'7
40
OUTPUT ENABLE/DISABLE TIMES
Output disable tests performed with C L = 5pF and measured
to 0.5V change of output voltage level.
INPUT
OUTPUT
ENABLE
MIN. MAX.
DISABLE
MIN.
MAX.
OE BYTE o_3
DATA O_31
10
29
10
25
OEsc
SCM
10
30
10
26
36
MINIMUM PULSE WIDTHS
I
47
30
LE,N• LE oUT' LE OIAG
37
NOTE:
1. DATA'N (or LE ,N ) to Correct Data Out measurement requires timing
as shown in Figure 8 below.
VALID
INPUT DATA
CORRECT DATA
OUTPUT
DATA ....,
LEIN
OEBYTE ....
Figure 8.
3-155
15
IDT49C460/A 32·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUT/OUTPUT INTERFACE CIRCUIT
Vee
4
-
INPUTS o----'M~+-_{>IlL
MS039C60~011
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Vee
1470
~UT----~---------+
r
750
SOpF
MSD39C60-013
Figure 11. Output Load Circuit
CAPACITANCE (TA = +25°C. f = 1.0MHz)
PARAMETER(1)
C IN
Input Capacitance
C OUT
Output Capacitance
MSD39C60-D12
AC TEST CONDITIONS
TEST LOAD CIRCUITS
SYMBOL
10H
Figure 10. Output Structure
Figure 9. Input Structure (All tnputs)
CL
OUTPUTS
(IoL
CONDITIONS
TYPo
UNIT
=OV
VOUT =OV
5
pF
7
pF
VIN
NOTE:
1. This parameter Is sampled and not 100% tested.
3·156
GNDto3.0V
10ns
1.5V
1.5V
See Fig. 11
ORDER PART
NUMBER
IOT39C01CP
SPEED
C
PACKAGE
TYPE
OPER.
TEMP.
P40
Com·1.
ORDER PART
NUMBER
IOT39C09AP
IOT39C01CO
040-2
IOT39C09AO
SPEED
A
PACKAGE
TYPE
OPER.
TEMP.
P28
Com'l.
028-1
I OT39C01CC
040-1
IOT39C09AL
L28-3
IOT39C01CL
L44
IDT39C09AOB
028-1
IOT39C01CF
F42
I OT39C09ALB
L28-3
I OT39C01 COB
040-2
I OT39C01CCB
040-1
IOT39C09BO
IOT39C01CLB
L44
IOT39C09BL
L28-3
I OT39C01CFB
F42
IOT39C09BOB
028-1
IOT39C09BLB
L28-3
IOT39C01DP
0
P40
Mil.
IOT39C09BP
Com'l.
A
P28
040-2
IOT39C01DC
040-1
IOT39C10BP
IOT39C01DL
L44
IOT39C10BO
040-1
IOT39C10BC
040-2
IOT39C01DF
F42
040-2
IOT39C01DCB
040-1
Mil.
B
P40
IOT39C10BL
L44
IOT39C10BF
F42
IOT39C01DLB
L44
IOT39C10BOB
040-1
IOT39C01DFB
F42
IOT39C10BCB
040-2
IOT39C01EP
IOT39C10BLB
L44
IOT39C01EO
040-2
IOT39C10BFB
F42
IOT39C01EC
040-1
IOT39C1OCP
IDT39C01EL
L44
IOT39C10CO
040-1
IOT39C1OCC
040-2
E
I OT39C01EF
P40
Com'l.
F42
I OT39C01EOB
040-2
IOT39C01ECB
040-1
Mil.
B
P40
IOT39C1OCL
L44
IOT39C1OCF
F42
IDT39C01 ELB
L44
IOT39C10COB
040-1
IOT39C01EFB
F42
IOT39C10CCB
040-2
IOT39C02AO
A
IDT39C02AL
016
016
IOT39C02ALB
L20-2
IOT39C03AP
A
P48
.-
L52
IOT39C03ACB
048
IOT39C03ALB
IOT39C03BC
Mil.
L44
F42
IOT39C11AP
Com'l.
048
IOT39C03AL
IOT39C03BP
IOT39C1OCLB
IOT39C10CFB
Mil.
Com'!.
Mil.
Com'l.
Mil.
L20-2
IOT39C02AOB
IOT39C03AC
Com'l.
Com'l.
028-1
IOT39C01D0
IOT39C0100B
Mil.
L52
B
P48
Com'l.
048
IOT39C03BL
L52
IOT39C03BCB
048
IOT39C03BLB
L52
Mil.
IOT39C11AL
L20-2
IDT39C11AOB
020
IOT39C11ALB
L20-2
B
P20
IOT39C11BO
020
IOT39C11BL
L20-2
IOT39C11BOB
020
IOT39C11BLB
L20-2
IOT39C203C
IOT39C203L
3-157
P20
020
IOT39C11BP
Mil.
A
IOT39C11AO
-
048-1
Com'l.
Mil.
Com'l.
Mil.
Com'l.
L52
IOT39C203CB
048-1
IDT39C203LB
L52
Mil.
ORDER PART
NUMBER
IDT39C203AC
SPEED
PACKAGE
TYPE
OPER.
TEMP.
A
D48-1
Com'l.
I DT39C203AL
ORDER PART
NUMBER
IDT39C707ADB
L52
IDT39C203ACB
D48-1
IDT39C203ALB
L52
Mil.
SPEED
A
-
P48
L28-1
048-1
IDT49C401C
I DT49C401CB
L48, L52
1DT49C401AC
D48-1
D48-2
IDT39CSOLB
IDT39CSOAP
Mil.
P48
-
DS4
IDT49C402XC
Com'l.
Mil.
Mil.
-
D68
IDT49C402G
G68
IDT39CSOAC
D48-1
IDT49C402L
L68-1
IDT39CSOAXC
D48-2
IDT49C402XL
L68-2
IDT39CSOAL
L48, L52
IDT39CSOACB
D48-1
IDT39CSOAXCB
D48-2
IDT39CSOALB
IDT39C60-1P
L48, L52
-1
IDT39CSD-1C
IDT39CSO-1XC
IDT39CSD-1L
P48
Com'l.
IDT49C402AXC
L68-1
L68-2
IDT49C402AXCB
D68
D48-2
IDT49C402AGB
G68
L48, L52
IDT49C402ALB
L68-1
IDT49C402AXLB
L68-2
D28-1
D28-3
L28-1
IDT39C705ADB
D28-1
IDT39C705ACB
D28-3
Mil.
IDT49C403/A
Consult Factory
IDT49C404
Consult Factory
I DT49C41 OJ
L28-1
D28-1
Com'l.
D48-2
IDT49C410XC
L28-1
IDT49C410L
IDT39C705BDB
D28-1
IDT39C705BCB
IDT39C705BLB
D48-1
D28-3
IDT49C410XCB
D48-2
L28-1
I DT49C41OLB
D28-1
Com'l.
D48-2
D28-3
I DT49C41OAXC
L28-1
I DT49C41OAL
IDT39C707DB
D28-1
IDT39C707CB
D28-3
Mil.
L28-1
D28-1
IDT39C707AC
D28-3
IDT39C707AL
L28-1
3-158
Com'l.
Mil.
Com' I.
L48
I DT49C41OACB
D48-1
lOT 49C41 OAXCB
D48-2
IDT49C410ALB
Com'l.
J52
D48-1
IDT39C707L
A
Mil.
L48
A
IDT49C410AC
IDT39C707C
IDT39C707AD
Com'l.
L48
IDT49C410CB
IDT49C41 OAJ
IDT39C707LB
J52
D48-1
D28-3
Mil.
-
I DT49C41OC
IDT39C705BL
-
Mil.
Com'l.
IDT39C705BC
IDT39C707D
D68
IDT49C402AXL
Mil.
Com'l.
L68-2
A
IDT49C402AL
IDT39C705AC
B
L68-1
D48-2
IDT39C705AL
IDT39C705BD
IDT49C402LB
G68
IDT39CSD-1XCB
IDT39C705ALB
G68
IDT49C402AG
048-1
A
D68
IDT49C402GB
IDT49C402XLB
L48, L52
IDT39CSD-1 LB
IDT49C402XCB
D48-1
IDT39CSD-1CB
IDT39C705AD
Mil.
Com'l
Com'l.
A
I DT49C401ACB
L48, L52
A
Consult Factory
Com'l.
D48-2
IDT39CSOCB
Mil.
IDT39C707ALB
IDT39CSOC
IDT39CSOXCB
D28-1
D28-3
IDT39CSOXC
IDT39CSOL
OPER.
TEMP.
IDT39C707ACB
IDT49C25
IDT39CSOP
PACKAGE
TYPE
L48
Mil.
ORDER PART
NUMBER
IDT49C460XC
SPEED
-
1DT49C4S0G
PACKAGE
TYPE
OPER.
TEMP.
DSB
Com'l.
G6B
IDT49C4S0L
LSB-1
IDT49C4S0XL
LSB-2
IDT49C4S0XCB
D6B
IDT49C4S0GB
GSB
IDT49C4S0LB
LSB-1
IDT49C4S0XLB
L6B-2
IDT49C460AXC
A
DS8
IDT49C4S0AG
G6B
lOT49C460AL
L68-1
IDT49C4S0AXL
LSB-2
IDT49C460AXCB
D68
IDT49C460AGB
G68
IDT49C4S0ALB
L6B-1
IDT49C460AXLB
LS8-2
Mil.
Com'l.
Mil.
3-159
Integrated
Device
Technology
Digital Signal Processing (DSP)
I
DIGITAL SIGNAL PROCESSING PRODUCTS
TABLE OF CONTENTS
CONTENTS
Digital Signal Processing (OSP)
IDT7201N02A
512x9 & 1024x9 Half-Full Flag FIFO ......•.......................••............
IDT7201/02
512x9 & 1024x9 Parallel In-Out FIFO .....•••..•.......••.................•.....
IDT7203/04
2Kx9 & 4Kx9 Parallel In-Out FIFO ..................••..........••.............
IDT72064/65
54-Bit Floating Point ••..........•..........•............•...........•........
IDT7209
12x12 Parallel Multiplier-Accumulator ......................................... .
IDT721 0/43
16x16 Parallel Multiplier-Accumulator •....................•....................
IDT72103/04
2Kx9 & 4Kx9 Half-Full Flag FIFO .....................•..•...........•.........
IDT7212113
12x12 Parallel Multiplier ................•............••.........•.............
IDT7216/17
16x16 Parallel Multiplier •.....................•...............................
IDT72264165
64-Bit Floating Point ........................................................ .
IDT72401/02/03/04
54x4 & 64x5 Parallel In-Out FIFO •........................•....................
IDT72413
Parallel 64x5 FIFO ....................•.............•..•.........•...........
Ordering Information
PAGE
4-1
4-11
4-21
4-31
4-35
4-42
4-50
4-52
4-61
4-71
4-75
4-77
4-78
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
•
The IDT7201A17202A is a dual port memory that utilizes a
special First-In, First-Out algorithm that loads and empties data
on a first-in, first-out basis. The device uses full and empty flags
to prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the use
of ring pOinters, with no address information required to load and
unload data. Data is toggled in and out of the device through the
use of the WRITE (W) and READ (A) pins. The device has a
read/write cycle time of 45ns (22MHz).
The device utilizes a 9-bit wide data array to allow for control
and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking. It
also featues a RETRANSM IT (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed low to
allow for retransmission from the beginning of data. A half-full
flag is available in the single device mode and width expansion
modes.
The IDT7201A17202A is fabricated using the high speed
CEMOS II, 1.2 micron technology and is available in DIPs and
LCCs screened to MIL-STD-883, Method 5004. It is designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications. The
1024 x 9 organization of the IDT7202A allows a 1024 deep word
structure without the need for expansion.
•
•
•
•
•
•
•
•
•
First-In, First-Out dual port memory
512 x 9 organization (IDT7201A)
1024 x 9 organization (IDT7202A)
Low power consumption
Ultra high speed - 45ns cycle time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
IDT7201A pin and functionally compatible with Mostek
MK4501 but with half-full flag capability
IDT7202A allows for deep word structure (1024) without
expansion
Half-full flag capability in single device mode
Master/slave multiprocessing applications
Bidirectional and rate buffer applications
Empty and full warning flags
Auto retransmit capability
High-performance 1.2 micron CEMOS'· II technology
Available in Plastic DIP, CERDIP and LCC
Military product available 100% screened to MIL-STD-883,
Class B
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(DO-DO)
Vi
8 I!I~ ~ ~ ~ ~
Vee
DO
D.
D3
DS
D2
D6
D1
D7
AAif
RS
OF
DO
Xi
FF
XO/HF
QO
Q1
Q7
Q2
Q6
Q3
QS
QO
Q.
R
GND
DSP7201-001
DIP
4 ....
D2
L.I
3
JS
Vi
U II L.I L..I "'30
2lj 3231 29::
1
D1
D6
D7
DO
NC
Xi
FF
FLIRT
RS
OF
QO
Q1
XO/H'F
NC
Q7
Q2
Q6
8
~ ~ ~Ia: ~
8
R
is
Z
~
TOP VIEW
DSP7201-002
PLCC& LCC
TOP VIEW
ifI----'1.~~~.r------- XO/HF
DSP7201-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
01986 Integrated Device Technology, Inc.
4-1
II
IDT7201A17202A CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
VTERM
Terminal Voltage
with Respect
toGND
TA
RECOMMENDED DC OPERATING CONDITIONS
COMMERCIAL
UNIT
MILITARY
-0.5 to +7.0
-0.5 to +7.0
V
Operating
Temperature
o to +70
-55 to +125
·C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
fUnctional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ± 10%, TA = O·C to +70°C;
SYMBOL
PARAMETER
MIN.
TYP.
III
Input Leakage Current
(Any Input)
-1
-
1
ILO
Output Leakage Current
-10
-
10
VOH
Output Logic "1" Voltage
10H = -2mA
2.4
-
VOL
Output Logic "0" Voltage
10l = BmA
-
ICCl
Average Vcc
Power Supply Current
4.5
5.0
5.5
V
-
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
-
GND
Supply Voltage
0
0
0
V
-
V,H
Input High
Voltage
Commercial
2.0
-
-
V
-
V,H
Input High
Voltage
Military
2.2
-
-
V
-
V,l
Input Low
Voltage
Commercial
& Military
-
-
O.B
V
1
± 10%. TA = -55°C to
IDT7201SAlLA
IDT7202SA/LA
MILITARY
TA = 40n.
+125°C)
IDT7201SAlLA
IDT7201SAlLA
IDT7202SA/LA
IDT7202SA/LA
COMMERCIAL
MILITARY
TA = 50, 65,
TA = 50, 65,
80, 120n.
8O,120n.
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
NOTES
TYP.
MAX.
-10
-
10
-1
-
1
-10
-
10
pA
1
-10
-
10
-10
-
10
-10
-
10
p.A
2
-
2.4
-
-
2.4
-
-
2.4
-
-
V
-
-
0.4
-
-
0.4
-
-
0.4
-
-
0.4
V
-
-
-
100
-
-
120
-
50
BO
-
70
100
mA
3
StandEY Current
(R = W = RS = FLIRT = V,H )
-
-
15
-
-
20
-
5
B
-
B
15
mA
3
IcdL)
Power Down Cu rrent
(All Input = Vcc -0.2V)
-
-
500
-
-
900
-
-
500
-
-
900
p.A
3
I CC3 (S)
Power Down Current
(All Input = Vcc -0.2V)
-
-
5
-
-
9
-
-
5
-
-
9
mA
3
ICC2
A~er~e
MAX. MIN.
MIN. TYP. MAX. UNIT NOTES
Military
Supply Voltage
NOTE:
1. 1.SV undershoots are allowed for 10ns once per cycle.
Military: Vee = 5V
IDT7201SA/LA
IDT7202SAlLA
COMMERCIAL
TA = 35n.
PARAMETER
Vcc
NOTES:
1. ~easurements with 0.4:5 V1N :5 Vee.
2. A ~ V1H • 0.4 :5 VOUT :5 Vee.
3. Icc measurements are made with outputs open.
4-2
IDT7201A/7202A CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee =5V ± 10%, TA =O°C to +70°C;
Military: Vee
COM'L
SYMBOL
PARAMETER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
=5V ± 10%, TA =-55°C to +125°C)
MILITARY
MILITARY AND COMMERCIAL
7201A/2A-35 7201A/2A-40 7201A12A-50 7201A/2A-85 7201A/2A-BO 7201A12A-120
UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
t AC
Read Cycle Time
45
-
50
-
65
-
80
-
100
-
140
-
ns
tA
Aceess Time
-
35
-
40
-
50
-
65
-
80
-
120
ns
10
-
20
-
20
80
-
120
-
ns
10
-
10
-
ns
20
-
20
-
ns
IAA
Read Recovery Ti me
10
15
35
40
-
-
Read Pulse Width(2)
-
15
tAPW
50
-
65
tALZ
Read Pulse Low
to Data Bus at Low
Z(3)
5
-
5
-
10
-
10
twLZ
Write Pulse High
to Data Bus at Low
Z (3. 4)
10
-
10
-
15
-
15
ns
tDV
Data Valid from Read Pulse High
5
-
5
-
5
-
5
-
5
-
5
-
ns
tAHZ
Read Pulse High
to Data Bus at High
-
20
-
25
-
30
-
30
-
30
-
35
ns
50
-
80
-
140
80
-
120
15
-
20
20
30
-
40
10
-
10
-
80
100
-
140
65
-
80
120
15
-
20
-
80
-
100
-
-
ns
65
-
100
50
10
-
65
40
80
Z(3)
twe
Write Cycle Time
45
t wpw
Write Pulse Width(2)
35
tWA
Write Recovery Time
10
-
t DS
Data Setup Time
18
-
20
-
30
tDH
Data Hold Time
0
0
Reset Cycle Time
45
t AS
Reset Pulse Width(2)
35
t ASA
Reset Recovery Time
10
tATe
Retransmit Cycle Time
45
50
-
5
t Ase
-
tAT
Retransmit Pulse Width(2)
35
-
40
-
50
tATA
Retransmit Recovery Time
10
-
10
-
15
tEFL
Reset to Empty Flag Low
45
-
50
tHFH.FFH
Reset to Half & Full Flag High
-
45
-
50
tAEF
Read Low to Empty Flag Low
-
30
-
35
tAFF
Read High to Full Flag High
-
30
-
35
-
tWEF
Write High to Empty Flag High
-
30
-
35
-
45
tWFF
Write Low to Full Flag Low
30
-
35
45
45
-
50
45
-
50
-
tWHF
Write Low to Half-Full Flag Low
-
tAHF
Read High to Half-Full Flag High
-
50
40
10
15
65
50
15
65
65
65
45
45
65
65
65
15
-
40
10
20
140
ns
ns
ns
ns
ns
ns
ns
ns
-
120
100
-
140
ns
80
-
140
ns
60
-
60
60
ns
60
-
60
60
ns
60
-
60
ns
60
-
60
ns
100
-
140
ns
100
-
140
ns
60
60
80
80
80
20
20
100
ns
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
5V
3. Values guaranteed by design. not currently tested.
4. Only applies to read data flow through mode.
1.1k
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
SYMBOL
TO OUTPUT
PIN 0--.......- - - - - - .
GNDt03.0V
5ns
1.5V
1.5V
See Figure 1
680n
=F 30pP
(TA = +25°C, f = 1.0MHz)
PARAMETER")
C IN
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYPo
UNIT
VIN = OV
5
pF
VOUT = OV
7
DSP7201-004
-Includes jig and scope capacitances.
pF
Figure 1. Output Load.
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
Generating R'!WSignals - When using these high-speed FIFO devices. it is necessary to have clean inputs on the RandWsignals.lt is important to not have glitches, spikes
or ringing on the A, W(that violate the V 1L• V1H requirements); although the minimum pulse width lowforthe RandWare specified in tens of nanosecond, a glitch of5nscan
affect the read or write pOinter and cause it to increment.
4-3
IDT7201A17202A CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
then begin. When the FIFO is empty, the internal read pointer is
blocked from R, so external changes in R will not affect the FIFO
when it is empty.
INPUTS:
DATA IN (00-08)
.
Data inputs for 9-bit wide data.
FIRST LOAOIRETRANSMIT (FLIRT)
This is a dual purpose input. In the Depth Expansion Mode, this
pin is grounded to indicate that it is the first loaded. (See Operating Modes.) In the Single Device Mode, this pin acts as the
retransmit input. The Single Device Mode is initiated by grounding the EXPANSION IN (Xi).
The IDT7201A12A can be made to retransmit data when the
RETRANSMIT ENABLE CONTROL (RT) input is pulsed low. A
retransmit operation will set the internal read pointer to the fi!!t
location and will not affect the write pointer. READ ENABLE (R)
and WRITE ENABLE (IN) must be in the high state during
retransmit. This feature is useful when less than 51211024 writes
are performed between resets. The retransmit feature is not cornpatible with Depth Expansion Mode and will affect HALF-FULL
FLAG (HF) depending on the relative locations of the read and
write pOinters.
CONTROLS:
RESET (RS)
_
Reset ill accomplished whenever the RESET (RS) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
READ ENABLE (R) and WRITE ENABLE (iN) inputs must be in
the high state during the window shown in Figure 2; i.e., tRPW or
twpw before the rising edge of RS, and should not change until
tRS R after the rising edge of RS. HALF-FULL FLAG (HF) will be
reset to high after master RESET (RS).
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the
FULL FLAG (FF) is not set. Data setup and hold times must be
adhered to with respect to the rising edge of the WRITE ENABLE
(W). Data is stored in the RAM array sequentially and independently of any ongoing read operation.
After half of the memory is filled, and at the falling edge of the
next write operation, the HALF-FULL FLAG (HF) will be setto low
and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The HALF-FULL FLAG (HF) is then reset
by the rising edge of the read operation.
_
To prevent data overflow, the FULL FLAG (FF) will go low,
inhibiting further write operations. Upon the completion of a valid
read operation, the FULL FLAG (FF) will go high after tRFF,
allowing a valid write to begin. When the FIFO is full, the internal
write pointer is blocked from Iii, so external changes in Iii will not
affect the FIFO when it is full.
EXPANSION IN ( X i ) .
.
This input is a dual purpose pm. EXPANSION IN (XI) IS
grounded to indicate an operation in the single device mode.
EXPANSION IN (XI) is connected to EXPANSION OUT (XO) of
the previous device in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (FF) _
The FULL FLAT (FF) will go low, inhibiting further write operation, when the write pointer is one location from the read pointer,
indicating that the device is full. if the read pointer is not moved
after RESET (RS), the FULL FLAG (FF) will go low after 512 writes
for the IDT7201A and 1024 writes for the IDT7202A.
EXPANSION OUT/HALF-FULL FLAG (Xo/HF)
This is a dual purpose output. In the single device mode, when
EXPANSION IN (Xi) is grounded, this output acts as an indication
of a half-full memory.
After half of the memory is filled, and at the failing edge of the
next write operation, the HALF-FULL FLAG (HF) will be set to low
and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The HALF-FULL FLAG (HF) is then reset
by the rising edge of the read operation.
_
I n the Depth Expansion Mode, EXPANSION IN (XI) is connected
to EXPANSION OUT (XO) of the previous device. Thisoutputacts
as a Signal to the next device in the Daisy Chain by providing a
pulse to the next device when the previous device reaches the last
location of memory.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the READ
ENABLE (R) provided the EMPTY FLAG (EF) is not set. The data
is accessed on a First-In, First-Out basis independent of any
ongoing write operations. After READ ENABLE (Ai goes high, the
Data Outputs (CO through C8) will return to a high impedance
condition until the next READ operation. When all the data has
been read from the FIFO, the EMPTY FLAG (EF) will go low,
allowing the "final" read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance
state. Once a valid write operation has been accomplished, the
EMPTY FLAG (EF) will go high after tWEF, and a valid READ can
los
iii
~[-
f-
7
1\
~
R,W'////// / / / / / / / /
/ /
/ / / / / /~
r
'EFL
'.ow
-
Iwpw
1---'... EF
NOTES:
1. tRse =t RS + t RSR2, Wand R = V'H around the rising edge of RS,
!\
~Ir
1\
Figure 2. Reaet
4-4
DSP7201-005
IDT7201A/7202A CMOS
PARALLEL FIRST·IN/FIRST·OUT FIFO 512 x 9·BIT & 1024 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
f-,.-------IRe------t----IRPW
'RR
b
'RL
IDV=j
Q:::o-::;;Q:::8=--------00<--D"-~-..-O-U-T-V-ALI0
IRHZ-I
'm}(-DA-;rA-OU-T-~-"-Ll-D"''tlJ------
Iwe
'wpw
w
,
' WR -
~
/
1\
"
-i~--DA-~-..-I-N-~.-.L-,D-- )~I-----~<:r--DA-~-..-,N-~-.-L-,D---.)~---.
t"H
'DS
_OO-_D8_______
DSP7201~OO6
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
ADDITIONAL
FIRST READ
FIRST WRITE
READS
\.....--.JI'-
R
w
1'------'
1 - 'wFF
-
-
IAFF
-
F
DSP7201-007
Figure 4. Full Flag From Last Write 10 First Read
LAST READ
FIRST WRITE
ADDITIONAL
FIRST
WRITES
READ
EF
OSP7201-Q08
Figure 5. Empty Flag From Last Read to First Write
4·5
IDT7201An202A C~OS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.",.
FLiRT
j
1\
R,W
f---'RTRDSP7201-009
NOTES:
1. tATe = tAT + t ATR .
2.
er, HF and FF may change state during retransmit as a result of the offset of the read and write pOinters, but flags will be valid at tATeFigure 6. Retransmit
tRPE: EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH
w----_
IWEF
u
------------------------+---'
NOTE:
DSP7201-01Q
1. (I APE = IAPwl.
Figure 7. Empty Flag Timing
.WPF: EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH
ii----_
~-----------------------~--J
tWPF
DSP7201-011
NOTE:
1. (Iwp > = Iwpwl.
Figure 8. Full Flag Timing
,,
HALF fULL OR LESS
~ .. MORE THAN HALF-FULL
HALF FULL OR LESS
i
-:
tRHF
r--
...., f-
--
tWHF
-
-.r
~r-
D5P72Ql-012
Figure 9. Half-Full Flag Timing
4-6
IDT7201AJ7202A CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 • 9-BIT & 1024 .9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEPTH EXPANSION (DAISY CHAIN) MODE
DATA OUTPUTS (QO-Q8)
Data outputs for 9-bit wide data. This output is in a high impedance condition whenever READ (R) is in a high state.
The IDT7201A/2A can easily be adapted to applications when
the requirements are for greater than 51211024 words. Figure 12
demonstrates Depth Expansion using three IDT7201A/2As. Any
depth can be attained by adding additional IDT7201A/2As. The
IDT7201A/2A operates in the Depth Expansion configuration
when the following conditions are met:
OPERATING MODES:
SINGLE DEVICE MODE
A single IDT7201A/2A may be used when the application
requirements are for 51211024 words or less. The IDT7201A/2A is
in a Single Device Configuration when the EXPANSION IN (XI)
control input is grounded. (See Figure 10.) In this mode the
HALF-FULL FLAG (HF), which is an active low output, is shared
with EXPANSION OUT (XO).
(HALF.FULL FLAG)
1. The first device must be designed by grounding the FIRST
LOAD (FL) control input.
2. All other devices must have FL in the high state.
3. The EXPANSION OUT (XO) pin of each device must be tied to
the EXPANSION IN (XI) pin of the next device. See Figure 12.
4. External logic is needed to generate a composite FULL FLAG
(FF) and EMPTY FLAG (EF). This requires the ORing of all EFs
and ORing of all FFs (i.e. all must be set to generate the correct
composite FF or EF). See Figure 12.
HF
t
WRITE
(R)
(W)
~
9
DATA IN
/
(FF)'
FULL FlAG
RESET
~
9
(D)
5. The RETRANSMIT (RT) function and HALF-FULL FLAG (HF)
are not available in the Depth Expansion Mode.
READ
(0) /
:>
DATA OUT
COMPOUND EXPANSION MODE
IDT7201A12A
(RS)
EXPANSION IN (ii)
(ff)
EMPTY FLAG'
(RT)
RETRANSMIT
The two expansion techniques described above can be applied
together in a straightforward mannerto achieve large FIFO arrays.
(See Figure 13.)
BIDIRECTIONAL MODE
i
Applications which require data buffering between two systems
(each system capable of READ and WRITE operations) can be
achieved by pairing IDT7201N2As as is shown in Figure 14. Care
must be taken to assure that the appropriate flag is monitored by
each system; (i.e. FF is monitored on the device where Wis used;
EF is monitored on the device where R is used). Both Depth
Expansion and Width Expansion may be used in this mode.
DSP720,-013
Figure 10. Block Diagram 01 Single 512x9/1024.9 FIFO
DATA FLOW-THROUGH MODES
DATA
INCD)
WRITE
---"''-----*
FULL flAG
RESET
Two types of flow-through modes are permitted, a read flowthrough and write flow-through mode. For the read flow-through
mode (Figure 15), the FIFO permits a reading of a single word
after writing one word of data into an empty FIFO. The data is
enabled on the bus in (tWEF + tA)ns after the rising edge of IN,
called the first write edge, and it remains on the bus until the R
line is raised from low-to-high, after which the bus would go
into a three-state mode after tRHZns. The EF line would have a
pulse showing temporary de-assertion and then would be
asserted. In the interval of time that R was low, more words can
be written to the FI FO (the subsequent writes after the first write
edge would de-assert the empty flag); however, the same word
(written on the first write edge), presented to the output bus as
the read pointer, would not be incremented when R is low. On
toggling R, the other words that were written to the FIFO will
appear on the output bus as in the read cycle timings.
In the write flow-through mode (Figure 16), the FIFO permits
the writing of a single word of data immediately after reading
one word of data from a full FIFO. The R line causes the FF to
be de-asserted but the W line being low causes it to be asserted
again in anticipation of a new data word. On the rising edge of
IN, the new word is loaded in the FIFO. The VIi line must be
toggled when FF is not asserted to write new data in the FIFO
and to increment the write pointer.
<"R) READ
(FF)
(EF) EMPTY FLAG
_---"(R"'S)'------;*""
DSP7201-014
NOTES:
IT
HF
Flag detection is accomplished by monitoring the FF.
and the
signals on
either (any) device used in the width expansion configuration. Do not connect
any output control signals together.
Figure 11. Block Diagram 01 512x1811024x18 FIFO Memory
Used in Width Expansion Mode
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Staius
flags (EF, FF and HF) can be detected from anyone device.
Figure 11 demonstrates an 18-bit word width by using two
I DT7201N2As. Any word width can be attained by adding
additional I DT7201 N2As.
4-7
I
IDT7201A17202A CMOS
PARALLEL. FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I - RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INPUTS
MODE
OUTPUTS
INTERNAL STATUS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
1
HF
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
Read/Write
1
1
0
Increment l11
IncrementPI
X
X
X
NOTE:
1. Pointer will increment if flag is high.
TABLE II - RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE
OUTPUTS
INTERNAL STATUS
INPUTS
MODE
RS
FL
XI
Read Pointer
WrIte Pointer
EF
FF
Reset-First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
Read/Write
1
X
(1)
X
X
X
X
NOTES:
1. Xi is connected to XO of previous device. See Figure 12.
M = Reset Input. FLIRT = First Load/Retransmit. EF = Empty Flag Output.
FF = Full Flag Output. Xi = Expansion Input. HF = Half-Full Flag Output.
FF
: -_ _ _~9f_-_rL.-_-1.t_-_-_-_-_-_-:..l9~:~j~ """"".
~:::::::t::::JL.-..r....
D
I----
/
L
EF
__
';9,...._ _ _"...
/
Q
~~~~
'v
cc
Xi
-
~~------------1-i
---
r-~------~~
KG
~---I"'-'- f4fF
~
..........:,9~,..~""110T72D1A12A_
/
r
FL
Xi
Figure 12. Block Diagram of 1536x9/3072x9 FIFO Memory (Depth Expansion)
4-8
DSP7201·015
IDT7201A17202A CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
•••
09-017
aO-08
---..,
Q(N-B)-ON
09-017
OO-OB
O(N-B)-ON
R,w,RS
D(N-B)-DN
D(N-B)-DN
DSP7201-016
NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 12.
2. For Flag detection see WIDTH EXPANSION Section and Figure 11.
Figure 13_ Compound FIFO Expansion
"-
\VA
We
FF;
HF.
~
DAO-B
IDT72D1A/2A
,
0 8 0-8
A
~
SYSTEM A
SYSTEM B
~
.A
'(
Q AO-8
R.
1\
IDT7201AJ2A
°8°-8
"1
We
HF.
EF;
FF;;
DSP7201-017
Figure 14, Bidirectional FIFO Mode
4-9
IDT7201A17202A CMOS
PARALLEL FIRST·IN/FIRST·OUT FIFO 512
x 9·BIT & 1024 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OATAIN
3V
Vi
R
ov
ov
EF
DATA OUT
--~~---------------------+~
NOTE:
1. (tRPE = tRPwl
Figure 15. Read Data Flow Through Mode
DSP7201-018
3V
ov
w---t----------------+--------t-----------JI
ov
~ --~--------------------r_-------J
DATA,.
--~----------------------------------~
'~I
~TAOUT
DATAOUT - - - - - - - -...
VALID
)@_-----------------
NOTE:
1. (tWPF = twpwl
DSP7201-019
Figure 16. Write Data Flow Through Mode
4-10
FEATURES:
DESCRIPTION:
• First-In. First-Out dual port memory
The IDT720117202 is a dual port memory that utilizes a special
First-In. First-Out algorithm that loads and empties data on a
first-in. first-out basis. The device uses full and empty flags
to prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the use
of ring pointers. with no address information required to load and
unload data. Data is toggled in and out of the device through the
use of the WRITE (W) and READ (R) pins. The device has a
read/write cycle time of 45ns (22M Hz).
The device utilizes a 9-bit wide data array to allow for control
and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking. It
alsofeatues a RETRANSMIT (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed low to
allow for retransmission from the beginning of data.
The 1DT720117202 is fabricated using IDT's high-speed
CEMOS technology and is available in DIPs and LCCs screened
to MIL-STD-883. Method 5004. It is designed for those applications requiring asynchronous and simultaneous read/writes in
multiprocessing and rate buffer applications. The 1024 x 9 organization olthe IDT7202 allows a 1024 deep word structure without
the need for expansion.
• 512 x 9 organization (IDT7201)
• 1024 x 9 organization (IDT7202)
• Low power consumption
• Ultra high speed - 45ns cycle time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• IDT7201 pin and functionally compatible with Mostek
MK4501
• IDT7202 allows for deep word structure (1024) without
expansion
• Master/slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and full warning flags
• Auto retransmit capability
• High-performance CEMOS'· technology
• Available in Plastic DIP, CERDIP and LCC
• Military product available 100% screened to MIL-STD-883.
Class B
NOTE: No Half-Full Flag on these devices. For Haif-Full Flag
see IDT7201SAlLA and IDT7202SAlLA data sheet.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(00-08)
W
Vee
08
D.
OS
D.
06
01
DO
07
fliRT
Xi
FF
EF
a ~I:r=
DO
As
QO
ro
Q1
Q7
Q'
Q6
QS
Q'
Q8
QO
"
GND
DSP7201-001
DIP
TDPVlEW
4L.I Loll U
•
D.
01
DO
~ ~~
II
U
£g
Vi
l.l L.l30
2lj 3231 29[:
1
2S::::
~7
06
07
Ne
Xi
FF
~8
~9
FLIRT
AS
QO
:]10
EF
Q1
::11
:]12
Ne
Q'
ro
22l:
Q7
::13151617181921[
14" "
,,~
Q6
r, " " "
a 8 ~ ~Ia: ~ 8
ii
C
Z
~
DSP7201-Q02
PLCC& LCC
TOP VIEW
1----+--. EF
L..::;:.::..J----j--i'F
j(j---~1L~~_1------ro
DSP72Q1-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
4-11
JULY 1986
Printed in U.S.A.
II
IDT7201/7202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT
a 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
RECOMMENDED DC OPERATING CONDITIONS
COMMERCIAL
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
UNIT
MILITARY
-0.5 to +7.0
V
TA
Oparating
Temperature
Oto +70
-55 to +125
'c
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
'c
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'c
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
mA
PARAMETER
SYMBOL
Military
Supply Voltage
4.5
5.0
5.5
V
-
Vcc
Commercial
Supply Voltage
4.5
5.0
5.5
V
-
GND
Supply Voltage
0
0
0
V
-
V1H
Input High
Voltage
Commercial
2.0
-
-
V
-
V1H
Input High
Voltage
Military
2.2
-
-
V
-
V1L
Input Low
Voltage
Commercial
& Military
-
-
0.8
V
1
NOTE:
I. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = SV ± 10%. TA = O'C to +70'C;
SYMBOL
PARAMETER
MIN.
III
Input Leakage Current
(Any Input)
ILO
NOTE:
1. 1.SV undershoots are allowed for 100s once per cycle.
Military: Vee = SV
IDT7201SIL
IDT7202S/L
COMMERCIAL
TA = 35n.
-
Output Leakage Current
-10
VOH
Output Logic "I" Voltage
IOH= -2mA
2.4
VOL
Output Logic "0" Voltage
IOL =8mA
ICCl
± 10%. TA = -SS'C to +12S'C)
IDT7201S1L
IDT7201S1L
IDT7202S/L
IDT7202S/L
COMMERCIAL
MILITARY
TA = 50,65,
TA = 50, 65.
8O,120n.
80, 120n.
TYR MAX. MIN. TYP. MAX. MIN. TYP. MAX.
IDT7201SIL
IDT7202S/L
MILITARY
TA = 4On.
TYR MAX. MIN.
-1
1
-10
-
-
10
-10
-
-
2.4
-
-
0.4
Average Vcc
Power Supply Current
-
-
A"yer~e ~nd~
Current
(R = W = RS = FLIRT = V1H)
-
I cc3(L)
Power Down Current
(All Input = Vcc -0.2V)
I cc3(S)
Power Down Current
(All Input = Vcc -o.2V)
-
Icc2
UNIT
NOTES
1
1
-10
-
10
~
10
-10
-
10
I'A
2
2.4
-
-
2.4
-
-
V
-
0.4
-
-
0.4
-
-
0.4
V
-
-
120
-
50
80
-
70
100
mA
3
-
-
20
-
5
8
-
8
15
mA
3
500
-
-
900
-
-
500
-
-
900
I'A
3
5
-
-
9
-
-
5
-
-
9
mA
3
10
-1
-
10
-10
-
-
-
-
100
-
-
15
-
NOTES:
1. Measurements with 0.4 S V1N S Vee.
2.
MIN. TYP. MAX. UNIT NOTES
Vcc
Ii;;, V1H• 0.4'; VOUT '; Vcc.
3. lee measurements are made with outputs open.
4-12
IDT7201/7202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT " 1024 x 9-BIT
AC ELECTRICAL CHARACTERISTICS
(Commercial: Vec = 5V ± 10%. TA = O°C to +70°C;
SYMBOL
PARAMETER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Military: Vee = 5V
± 10%. TA = -55°C to +125°C)
COM'L.
MILITARY
7201/2-35
7201/2-40
MILITARY AND COMMERCIAL
7201/2-50
7201/2-65
7201/2-80
7201/2-120
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNITS
t RC
Read Cycle Time
45
-
50
-
65
-
80
-
100
-
140
-
tA
Access Time
-
35
-
40
-
50
-
65
-
80
-
120
ns
tRR
·Read Recovery Time
10
-
10
-
15
15
-
40
-
50
65
80
120
-
ns
35
-
20
Read Pulse Width(')
-
20
t RPW
-
tRlZ
Read Pulse Low
to Data Bus at Low
Z(3)
5
-
5
-
10
-
10
-
10
-
10
-
ns
tWLZ
Write Pulse High
to Data Bus at Low
Z(3. 4)
10
-
10
-
15
-
15
-
20
-
20
-
ns
tDV
Data Valid from Read Pulse High
5
-
5
-
5
-
5
-
5
-
5
-
ns
ns
ns
tRHZ
Read Pulse High
to Data Bus at High
-
20
-
25
-
30
-
30
-
30
-
35
ns
twc
Write Cycle Time
45
-
50
-
65
80
-
40
-
50
65
tWR
Write Recovery Time
10
10
-
15
15
-
20
t DS
Data Setup Time
18
-
20
30
-
30
-
40
tDH
Data Hold Time
0
5
45
50
65
80
140
t RS
Reset Pulse Width (')
35
40
-
50
120
ns
Reset Recovery Time
10
10
15
15
20
Retransmit Cycle Time
45
65
-
80
100
tRT
Retransmit Pulse Width (')
35
50
-
65
-
80
-
120
tRTA
Retransmit Recovery Time
10
10
-
-
ns
t RTC
-
-
-
t RSR
-
-
10
Reset Cycle Time
-
10
t RSC
-
-
ns
35
-
140
Write Pulse Width(')
-
100
t wpw
-
15
-
15
-
20
-
20
-
ns
tEFl
Reset to Empty Flag Low
-
45
-
50
-
65
-
80
-
100
140
ns
tREF
Read Low to Empty Flag Low
-
30
-
35
-
60
60
ns
30
-
35
60
-
60
tWEF
Write High to Empty Flag High
30
35
-
45
60
Write Low to Full Flag Low
35
-
45
-
60
tWFF
-
-
60
Read High to Full Flag High
-
45
tAFF
-
Z(3)
-
-
30
0
50
40
45
65
60
80
100
80
20
120
20
40
10
140
60
ns
ns
ns
ns
ns
ns
ns
60
ns
60
ns
60
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5V
AC TEST CONDITIONS
1.1k
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CAPACITANCE
SYMBOL
GNDt03.0V
5ns
1.5V
1.5V
See Figure 1
TO OUTPUT
PIN 0--.----;
680Cl
30pF'
(TA = +25°C. f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYP.
UNIT
V,N=OV
5
pF
VOUT = OV
7
pF
DSP7201-004
C 'N
Input Capacitance
C OUT
Output Capacitance
*Includes jig and scope capacitances.
NOTE:
Figure 1. Output Load.
1. This parameter is sampled and not 100% tested.
NOTE:
Generating Fiiw signals - When using these high·speed FIFO devices, it is necessary to have clean inputs on the Rand Wsignals. It is important to not have glitches, spikes
or ringing on the RW (that Yiolate the V 1L, VIH requirements), although the minimum pulse width low forthe R andW are specified in tens of nanosecond, a glitch of 5nscan
affect the read or write pointer and cause It to increment.
4-13
IDT7201n202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512
x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (DG-D8)
Data inputs for 9-bit wide data.
FIRST LOAD/RETRANSMIT (FURT)
This is a dual purpose input. In the Depth Expansion Mode, this
pin is grounded to indicate that it is the first device loaded. (See
Operating Modes.) In the Single Device Mode, this pin acts as the
retransmit input. TheSingle Device Mode is initiated bygrounding
the EXPANSION IN (Xi).
The IDT7201 II DT7202 can be made to retransrriit data when the
RETRANSMIT ENABLE CONTROL (RT) input is pulsed low. A
retransmit operation will set the internal read pointer to the first
location and will not affect the write pointer. READ ENABLE (R)
and WRITE ENABLE (iN) must be in the high state during
retransmit. This feature is useful when less than 51211024 writes
are performed between resets.
CONTROLS:
RESET (RS)
_
Reset is accomplished whenever the RESET (RS) input is taken
to a low state. During reset, both internal read and write pointers
are set to the first location. A reset is required after power up
before a write operation can take place. Both the READ ENABLE
(Fi) and WRITE ENABLE (IN) inputs must be in the high state
during the window shown in Figure 2; i.e., tRPw or twpw before
the rising edge of RS, and should not change until tRSR after the
rising edge of RS.
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the
FULL FLAG (FF) is not set. Data setup and hold times must be
adhered to with respect to the rising edge of the WRITE ENABLE
(iN). Data is stored in the RAM array sequentially and independently of any ongoirig read operation.
To prevent data overflow, the FULL FLAG (FF) will go low,
inhibiting further write operations. Upon the completion of a valid
read operation, the FULL FLAG (FF) will go high after tRFF, allowing a valid write to begin. When the FIFO is full, the internal write
pointer is blocked from W, so external changes in iNwili not affect
the FIFO when it is full.
EXPANSION IN (XI)
This input is a dual purpose pin. EXPANSION IN (Xi) is
grounded to indicate an operation in the single device mode.
EXPANSION IN (xi) is connected to EXPANSION OUT (XO) of
the previous deviCe in the Depth Expansion or Daisy Chain Mode.
OUTPUTS:
FULL FLAG (FF) _
The FULL FLAG (FF) will go low, inhibiting further write operation, when the write pointer is one location from the read pointer,
iridicating that the device is full. If the read pointer is not moved
after RESET (RS), the FULL FLAG (FF) will go low after 512 writes
for the IDT7201 and 1024 writes for the 1DT7202.
READ ENABLE CA)
A read cycle is initiated on the falling edge of the READ
ENABLE (R) provided the EMPTY FLAG (8=) is not set. The data
is accessed on a First-In, First-Out basis independent of any
ongoing write operations. After READ ENABLE (R"j goes high, the
Data Outputs (00 through 08) will return to a high impedance
condition until the next READ operation. When all the data has
been read from the FIFO, the EMPTY FLAG (EF) will go low,
allowing the "final" read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance
state. Once a valid write operation has been accomplished, the
EMPTY FLAG (EF) will go high after tWEF, and a valid READ can
then begin. When the FIFO is empty, the internal read pOinter is
blocked from R, so external changes in R will not affect the FIFO
when it is empty.
EXPANSION OUT (XO)
_
In the Depth Expansion Mode, EXPANSION IN (XI) is connected
to EXPANSION OUT (XO) of the previous device. This output
acts as aSignal tothe next device in the Daisy Chain by providing
a pulse to the next device when the previous device reaches the
last location of memory.
DATA OUTPUTS (0G-08)
Data outputs for 9-bit wide data. This output is in a high
impedance condition whenever READ (Ai is in a high state.
"s
RS
~k-
I
i\
ii.w / / / / / / / / / / / ' / / / / / / ' / / / /
'EFL
EF
NOTES:
1. tRse = t RS + tRSRo
2. Wand R = V'H around the rising edge of RS.
/1-
hlPW
I
lwow
~r
\.
Figure 2. Reset
4-14
'-
-.....-'
~
DSP7201-005
IDT7201n202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I - - - - - - - I o c - - - - - - - I - - - -I O P W - - - -
IA- - -
IA- - -
1-
10L
'O)00-----"Z-I
loV==::j
'1:&:}(
OO\--DA-~-A-O-U-T-V-ALID
QO=;;;.-.;:;Q8;;....-----......
DATA OUT VALID
IWC
IWpw
IWO-
~
iii
It
'\
1\
_~_D_._______~I(r--D-A-~-A-IN-V-A-L-,O----lOS
»I--___-1<:r--DA-~-A-IN-VA-L-,O----)~-------
loH
DSP7201-006
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
ADDITIONAL
READS
FIRST READ
FIRST WRITE
~
R
W
-
tWFF
-- -
-
tRFF
F
DSP7201-007
Figure 4. Full Flag From Last Write to First Read
LAST READ
ADDITIONAL
WRITES
FIRST WRITE
FIRST
READ
-t_____t-__________
IWE,ir_ _
EF
DSP7201-00B
Figure 5. Empty Flag From Last Read to First Write
4-15
IDT7201/7202 CMOS
PARAllEL FIRST-IN/FIRST-OUT FIFO 512
x 9-BIT 10 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
'AT
FlIRT
R,W
1\
I--'ATRDSP7201·Q09
NOTES:
1. t RTC = tAT + t RTA .
2. EF and FF may change state during retransmit as a result of the offset of the read and write pOinters, but flags ~ill be valid at t RTC -
Figure 6. Retransmit
t RPE: EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH
w----_
~
------------------------------------------------r-----'
NOTE:
1. (t RPE
DSP7201-010
=t RPW ),
Figure 7. Empty Flag Timing
tWPF: EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH
lI----_
~------------------------------------------------+_----J
DSP7201-011
NOTE:
1. (t WPF =
t wpw).
Figure 8. Full Flag Timing
4-16
IDT7201/7202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODES:
SINGLE DEVICE MODE
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7201lIDT7202 can easily be adapted to applications
when the requirements are for greater than 512/1024 words.
Figure 11 demonstrates Depth Expansion using three IDT72011
IDT7202s. Any depth can be attained by adding additional
IDT7201lIDT7202s. The IDT7201l1DT7202 operates in the Depth
Expansion configuration when the fOllowing conditions are met:
A single 1DT7201I1DT7202 may be used when the application
requirements are for 512/1 024 words or less. The IDT720111DT7202
is in a Single Device Configuration when the EXPANSION IN (xi)
control input is grounded. (See Figure 9).
1. The first device must be designed by grounding the FIRST
LOAD (FL) control input.
2. All other devices must have f[ in the high state.
WRITE
~
9
DATA IN
/
(ff) ,
RESET
(0) /
4. External logic is needed to generate a composite FULL FLAG
(FF) and EMPTY FLAG (EF). This requires the ORing of all EFs
and ORing of all FFs (i.e. all must be set to generate the correct
composite FF or EF). See Figure 11.
~
9
(0)
FULL FLAG
READ
(A)
(W)
3. The EXPANSION OUT (XO) pin of each device must be tied to
the EXPANSION IN (XI) pin of the next device. See Figure 11.
OATA OUT
)
IOT72D1/2
(EF)
(iff)
(RS)
EXPANSION IN (Xi)
EMPTY FLAG '
5. The RETRANSMIT (RT) function is not available in the Depth
Expansion Mode.
RETRANSMIT
i
COMPOUND EXPANSION MODE
Thetwo expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays.
(See Figure 12.)
DSP7201-013
Figure 9. Block Diagram of Single 512x9/1024x9 FIFO
BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of READ and WRITE operations) can be
achieved by pairing IDT7201l1DT7202s as is shown in Figure 13.
Care must be taken to assure that the appropriate flag is
monitored by each system; (i.e. FF is monitored on the device
where iii is used; EF is monitored on the device where R is used).
Both Depth Expansion and Width Expansion may be used in this
mode.
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the corresponding input control signals of mUltiple devices. Status flags
(EF and FF) can be detected from anyone device. Figure 10
demonstrates an 18-bit word width by using two IDT72011
IDT7202s. Any word width can be attained by adding additional
IDT7201/IDT7202s.
DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted - a read
flow-through and a write flow-through mode. For the read flowthrough mode (Figure 14), the FIFO permits a reading of asingle
word after writing one word of data into an empty FI FO. The data
is enabled on the bus in (tWEF + tA)ns after the rising edge of iii,
called the first write edge, and it remains on the bus until the R
line is raised from low-to-high, after which the bus would go into
a three-state mode after tRHZns. The EF line would have a pulse
showing temporary de-assertion and then would be asserted. In
the interval of time that R was low, more words can be written to
the FIFO (the subsequent writes after the first write edge would
de-assert the empty flag); however, the same word (written on the
first write edge). presented to the output bus as the read pointer,
would not be incremented when R is low. On toggling R, the other
words that were written to the FI FO will appear on the output bus
as in the read cycle timings.
In a write flow-through mode (Figure15), the FIFO permits the
writing of a single word of data immediately after reading one
word of data from a full FIFO. The R line causes the FF to be
de-asserted, but the W line being low causes it to be asserted
again in anticipation of a new data word. On the rising edge
of IN, a new word is loaded into the FIFO. TheIN line must be
toggled when FF is not asserted to write new data into the
FIFO and increment tlie write pointer.
DATA
IN (0)
WRITE
--""'-----'i+
(ii)
FULL FLAG
IFF)
~EAD
(EF) EMPTY FLAG
+
RESET - - ( ".'.
" ' , -.....
DSP7201-014
NOTES:
Flag detection is accomplished by monitoring the
and
signals on either
(any) device used in the width expansion configuration. Do not connect any
output control signals together.
FF
EF.
Figure 10. Block Diagram of 512x1811024x18 FIFO Memory
Used in Width Expansion Mode
4-17
II
~
IDT720117202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I - RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
OUTPUTS
INTERNAL STATUS
INPUTS
MODE
RS
RT
XI
READ POINTER
WRITE POINTER
EF
Reset
0
X
0
Location Zero
Location Zero
0
FF
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
Read/Write
1
1
0
I ncrement l1 )
I ncrement l1 )
X
X
NOTE:
1. Pointer will increment If flag is high.
TABLE II - RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE
OUTPUTS
INTERNAL STATUS
INPUTS
MODE
RS
FL
XI
READ POINTER
WRITE POINTER
EF
Reset-First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
Read/Write
1
X
(1)
X
X
X
X
NOTES:
1. Xi is connected to
2.
Xc5 of previous device. See Figure 11.
AS = Reset Input, "FLiFIT = First Load/Retransmit, EF = Empty Flag Output. FF = Full Flag Output, XI = Expansion
Input.
jffi
R
Vi
EF
Fe
D
9
9
/
L
IOT7201/2
----=
~
9
~
/
a)
~ v"
.-£':
~,....-
Xi
---
x.
-.--..
-
-
FULL
FF
L
-
IDT720112-
~
-
~
EF
9'"
---:~
-
-rXi
x.
-'-'---
9
7
Rs
I--=EF
FF
... IDT720112
f--
r-~
r:
'--r-Xi
-::-
DSP7201-015
Figure 11. Block Diagram 01 1536x9/3072x9 FIFO Memory (Depth Expansion)
4-18
FF
IDT7201n202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512 x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
09-017
00-08
~
...
~
;
Q(N-8)-ON
09-017
00-08
O(N-B)-ON
R,W,RS
IDT7201/2
DEPTH EXPANSION
BLOCK
I---
IDT7201/2,
DEPTH EXPANSION
BLOCK
"'" ;:...
- •••
"'" ;:...
00-08
-
09-017
'"--09-DN
018-0N
•••
IDT7201/2
DEPTH EXPANSION
BLOCK
"'"
;:...
DIN-8)-DN
DIN-B)-ON
NOTES:
1, For depth expansion block see DEPTH EXPANSION Section and Figure 11,
2, For detection see WIDTH EXPANSION Section and Figure 10,
DSP72Ql-016
Figure 12. Compound FIFO Expansion
II
Ai
ViA
FF.;
EF;
.A
DAD-8
IDT7201/2
°eO-8
,-
...
A
SYSTEM A
SYSTEM B
'i
A .
QA°..a
10T7201/2
R.
,
0 8 0-8
~
we
FFa
DSP7201-017
Figure 13. Bidirectional FIFO Mode
4-19
IDT7201n202 CMOS
PARALLEL FIRST-IN/FIRST-OUT FIFO 512
x 9-BIT & 1024 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA IN
IV
w-+---,.
av
R-~----------------~------~--------JI
av
~--_+--------------------_+-------J
DA~o~
--_+--------------------_+-{
NOTE:
DSP720'-01a
1. (tAPE =tApwl
Figure 14. Read Data Flow Through Mode
Ii
3Y
ov ________________
w---+
~-------+-----------JI
ov
"_+
_________+-____- J
DATA,.
--+---------------------------------<
DATAO~ ----_~
DATAOUT VAllO
)@_---------------
NOTE:
DSP7201-019
1. (tWPf = 'wpwl
Figure 15. Write Data Flow Through Mode
4-20
FEATURES:
DESCRIPTION:
• First-In, First-Out dual port memory
The IDT720317204 is a dual port memory that utilizes a special
First-In, First-Out algorithm that loads and empties data on a
first-in, first-out basis. The device uses full and empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the use
of ring pointers, with no address information required to load and
unload data. Data is toggled in and out of the device through the
use of the WRITE (VII) and READ (R) pins. The device has a
read/write cycle time of 6Sns (1SMHz).
The device utilizes a 9-bit wide data array to allow for control
and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking. It
also featu res a RETRANSM IT (RT) capabi lity that allows for reset
of the read pointer to its initial position when RT is pulsed low to
allow for retransmission from the beginning of data. A half-full
flag is available in the single device mode and width expansion
modes.
The IDT7203/7204 is fabricated using the high-speed
CEMOS'"II, 1.S micron technology and is available in DIP and
LCC screened to MIL-STD-883, Method S004.lt is designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
The 4096 x 9 organization for the IDT7204 allows a 4096 deep
word structure without the need for expansion.
• 2048 x 9 organization (IDT7203)
• 4096 x 9 organization (IDT7204)
• Low power consumption
-Active: 660mW (max.)
-Power down: 66mW (max.)
•
•
•
•
•
•
•
•
•
•
•
•
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Pin and functionally compatible with IDT7201/02
IDT7204 allows 4096 word structure without expansion
Half-full flag capability in single device mode
Master/slave multiprocessing applications
Bidirectional and rate buffer applications
Empty and full warning flags
Auto retransmit capability
High-performance CEMOS'" II technology
Available in DIP and LCC
Military product available 100% screened to MIL-STD-883,
Class B
PIN CONFIGURATIONS
Vi
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(00-08)
Vee
D.
08
03
OS
D.
01
06
07
DO
FLIRT
Xi
FF
liS
Eo'
XO/HF
DO
01
07
06
D.
03
08
OS
D.
R
GND
02
01
4 .... L.I L.I II ...I ...I L.l30
::::5 3 2lj 3231 29;:
1
28[
DQ
27:::
Xi
FF
26 :::
25[
24[
23 t
DO
01
NC
02
D6
07
AS
EF
XotHF
221:
Q7
:::13151617181921:::
Q6
14" "
"
"
"
"
Vi
He
FLiFrr
"20
a a ~ ~Ia: t; 8
DSP7201-001
DIP
TOP VIEW
c
it
DSP7201-002
Lee
TOP VIEW
Xi ----i.~~=_j_------ XO/HF
DSP7203-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FEBRUARY 1986
Printed In U.S.A.
Cl1986 Integrated Device Technology, Inc.Printed in U.S.A.
4-21
II
•
IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAX.IMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
'C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
PT
Power Dissipation
1.0
1.0
W
lOUT
DC Output Current
50
50
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTES
VCCM
Military
Supply Voltage
4.5
5.0
5.5
V
-
VCCC
Commercial
Supply Voltage
4.5
5.0
5.5
V
-
GND
Su pply Voltage
0
0
0
V
-
V,H
Input High
Voltage
Commercial
2.0
-
-
V
-
V,H
Input High
Voltage
Military
2.2
-
-
V
-
V,L
Input Low
Voltage
Commercial
& Military
-
-
0.8
V
1
NOTE:
1. 1.5V undershoots are allowed for 10ns once pet cycle.
DC ELECTRICAL CHARACTERISTICS (CommerCial: Vee =5V ± 10%. TA =O°C to +70°C;
Military: Vee = 5V ± 10%, TA = -55°C to +125°C)
SYMBOL
PARAMETER
MIN.
IDT7203S/L
IDT7204S/L
MILITARY
TYP.
MAX.
UNIT
NOTES
"A
p.A
1
V
-
I'L
Input Leakage Current (Any Input)
-1
-
1
-10
-
10
10L
Output Leakage Current
-10
-
10
-10
-
10
VOH
Output Logic "1" Voltage lOUT = -2mA
2.4
-
2.4
-
-
VOL
Output Logic "0" Voltage lOUT = 8mA
-
-
0.4
V
-
Average VCC Power Supply Current
-
75
120
-
0.4
Icc.
100
150
rnA
3
12
-
12
25
rnA
3
A~er~e
-
2
StandbLC.!!!!'ent
(R = W = RST = FLIRT =V, H)
-
8
I cc3 (L)
Power Down Current
(All Input =Vcc -0.2V)
-
-
2
-
-
4
rnA
3
I cc3 (S)
Power Down Current
(All Input =Vcc -0.2V)
-
-
8
-
-
12
rnA
3
Icc2
NOTES:
1: Measurements with 0.4
2.
IDT7203S/L
IDT7204S/L
COMMERCIAL
TYP.
MIN.
MAX.
~
V1N :5. Vour "
R ~ V1H • 0.4:S VOUT :5. Vee
3. Icc measurements are made with outputs open.
4-22
IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 X 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Commercial: Vee = 5V ± 10%, T A = O°C to +70°C;
Military: Vee =5V ± 10%, TA =-55°C to +125°C)
SYMBOL
IDT7203/4-50
MAX.
MIN.
PARAMETERS
IDT7203/4-65
MAX.
MIN.
IDT7203/4-80
MIN.
MAX.
t AC
Read Cycle Ti me
65
-
80
-
100
-
tA
Access Time
-
50
-
65
-
80
IDT7203/4-120
MIN.
MAX.
UNITS
NOTES
-
ns
-
-
120
ns
-
140
tAA
Read Recovery Time
15
-
15
-
20
-
20
-
ns
t RPW
Read Pulse Width
50
-
65
-
80
-
120
-
ns
2
tALZ
Read Pulse Low to Data Bus at Low Z
10
-
10
-
10
-
10
-
ns
3
tWLZ
Write Pulse High to Data Bus at Low Z
15
-
15
-
20
-
20
-
ns
3
tDV
Data Valid from Read Pulse High
5
-
5
-
5
-
5
-
ns
-
-
30
-
tAHZ
Read Pulse High to Data Bus at High Z
-
30
-
30
35
ns
3
twc
Write Cycle Ti me
65
-
80
-
100
-
140
-
ns
-
t wpw
Write Pulse Width
50
-
65
-
80
-
120
-
ns
2
tWA
Write Recovery Time
15
-
15
-
20
-
20
-
ns
-
t DS
Data Setup Time
30
-
30
-
40
-
40
-
ns
-
tOH
Data Hold Time
5
-
10
-
10
-
10
-
ns
-
t RsC
Reset Cycle Time
65
-
80
-
100
-
140
-
ns
-
t AS
Reset Pu Ise Width
50
-
65
-
80
-
120
-
ns
2
t RSR
Reset Recovery Time
15
-
15
-
20
-
20
-
ns
-
t ATC
Retransmit Cycle Time
65
-
80
-
140
-
ns
-
Retransmit Pulse Width
50
-
65
-
100
tAT
80
-
120
-
ns
2
tRTR
Retransmit Recovery Time
15
-
15
-
20
-
20
-
ns
-
tEFl
Reset to Empty Flag Low
-
65
-
80
-
100
-
140
ns
tREF
Read Low to Empty Flag Low
-
45
-
60
-
70
-
110
ns
-
tRFF
Read High to Full Flag High
-
45
-
60
70
-
110
ns
-
tWEF
Write High to Empty Flag High
-
45
-
60
-
70
-
110
ns
-
tWFF
Write Low to Full Flag Low
-
45
-
60
-
70
-
110
ns
-
tWHF
Write Low to Half Full Flag Low
-
65
-
80
-
100
-
140
ns
-
tRHF
Read High to Half Full Flag High
-
65
-
80
-
100
-
140
ns
-
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
AC TEST CONDITIONS
5V
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
UK
1.5V
See Figure 1
D.U.T. - -......- - - - - 1
6BOH
CAPACITANCE
SYMBOL
C IN
C OUT
(TA
ITEM
CONDITIONS
MAX.
UNIT
NOTES
Input
Capacitance
VIN = OV
7
pF
3
Output
Capacitance
3OpF*
=+25°C, f = 1.0MHz)(1)
VOUT = OV
12
pF
DSP7201-004
"Includes jig and scope capacitances.
2,3
Figure 1. Output Load.
NOTES:
1 This parameter is sampled and not 100% tested.
2 With output deselected
Characterized values, not currently tested.
4-23
II
IDT7203/IDT7204 CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 2048 x 9-BIT & 4096 x 9·BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS:
loaded. (See Operating Modes.) In the Single Device
Mode, this pin acts as the retransmit input. The Single
Device Mode is initiated by grounding the EXPANSION IN
(XI).
The IDT7203/4 can be made to retransmit data when the
RETRANSMIT ENABLE CONTROL (RT) input is pulsed
low. A retransmit operation will set the internal read pointer
to the first location and will not affect the write pointer.
READ ENABLE (R) and WRITE ENABLE (W) must be in the
high state during retransmit. This feature is useful when
less than 2048/4096 writes are performed between resets.
The retransmit feature is not compatible with Depth
Expansion Mode and will affect HALF FULL FLAG (HF)
depending on the relative locations of the read and write
pointers.
INPUTS:
DATA IN (DO • 08)
Data inputs for 9·bit wide data.
CONTROLS:
RESET (RS)
_
Reset is accomplished whenever the RESET (RS) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
READ ENABLE (R) and WRITE ENABLE (W) inputs must be
in the high state during reset. HALF FULL FLAG (HF) will be
reset to high after master RESET (RS).
EXPANSION IN (Xi)
WRITE ENABLE (Vi)
_
This input is a dual purpose pin. EXPANSION IN (XI) is
grounded to indicate an operation in the single device mode.
EXPANSION IN (Xi) is connected to EXPANSION OUT (XO)
ofthe previous device in the Depth Expansion or Daisy Chain
Mode.
A write cycle is initiated on the falling edge of this input if
the FULL FLAG (FF) is not set. Data setup and hold times
must be adhered to with respect to the rising edge of the
WRITE ENABLE (W). Data is stored in the RAM array
sequentially and independently of any ongoing read
operation.
After half of the memory is filled, and at the falling edge of
the next write operation, the HALF FULL FLAG (HF) will be
set to low and will remain set until the difference between the
write pointer and read pointer is less than or equal to one half
ofthe total memory ofthe device. The HALF FULL FLAG (HF)
is then reset by the rising edge of the read op~ation.
To prevent data overflow, the FULL FLAG (FF) will go low,
inhibiting further write operations. Upon the completion of a
valid read operation, the FULL FLAG (FF) will go high after
tRFF, allowing a valid write to begin.
OUTPUTS:
FULL FLAG
(FF)
The FULL FLAG (FF) will go low, inhibiting further write
operation, when the write pointer is one location from the
read pointer, indicating that the device is full. If the read
pointer is not moved after RESET (RS), the FULL FLAG
(FF) will go low after 2048 writes for the I DT7203 and 4096
writes for the IDT7204.
EXPANSION OUT/HALF FULL FLAG (XO/HF)
This is a dual purpose output. In the single deviceJllode,
when EXPANSION IN (Xi) is grounded, this output acts as an
indication of a half full memory.
After half of the memory is filled, and at the falling edge of
the next write operation, the HALF FULL FLAG (HF) will be
set to low and will remain set until the difference between the
write pointer and read pointer is less than or equal to one half
ofthe total memory ofthe device. The HALF FULL FLAG (HF)
is then reset by the rising edge of the read operation.
In the Multiple Device Mode, EXPANSION IN (Xi) is
connected to EXPANSION OUT (XO) of the previous device.
This output acts as a signal to the next device in the Daisy
Chain by providing a pulse to the next device when the
previous device reaches the last location of memory.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the READ
ENABLE (R) provided the EMPTY FLAG (EF) is not set. The
data is accessed on a First·ln, First·Out basis independent of
any ongoing write operations. After READ ENABLE (R) goes
high, the Data Outputs (00 through 08) will return to a high
impedance condition until the next READ operation. When
all the data has been read from the FIFO, the EMPTY FLAG
(EF) will go low, inhibiting further read operations with the
data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the EMPTY
FLAG (EF) will go high aftertwEF, and a valid READ can then
begin.
FIRST LOAD/RETRANSMIT (f[/RT)
DATA OUTPUTS (00 • 08)
This is a dual purpose output. In the Multiple Device Mode,
this pin is grounded to indicate that it is the first device
Data outputs for 9-bit wide data. This output is in a high
impedance condition whenever READ (R) is in a high state.
Io.
Iii
~
j
\.
w
I
I
EF
NOTES:
1. tRSC = t AS + tASR .
2. Wand R =V'H
during RESET.
"FL
.....
-
~'----~
I
j--'RSR-
Figure 2. Reset
4·24
DSP7201-005
IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 " 9-BIT .. 4096 " 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I-------.Re------I----.RPW
'.
b
~=J
'm)(
=QO-=Q::.·-----.......~--[)jI-;r.-1I-0-U-T-VA-LlD
~Hz-I
DATA OUT VALID
)(l;). . .----
'we
'Wf'W
'WR-
~
Vi
I
1\
1\
~l::~--[)jI-~-A-.N-V-A-L-.D- »I------1<:~--[)jI-~-A-.N-VA-L-,D----:>~--------'DS
_D_o-_D_·_______
'DH
DSP7201·006
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
ADDITIONAL
FIRST READ
FIRST WRITE
READS
'L-.J
R
/
w
1- ..... I--
-
~FF
r-
F
DSP7201-007
Figure 4. Full Flag From Last Write to Fir.t Read
LASTREAO
FIRST WRITE
ADDITIONAL
FIRST
WRITES
READ
ii
•
WEF
V-____-1______+-______________
I.
DATA OUT
DSP7201-00B
Figure 5. Empty Flag From La.t Read to First Write
4-25
IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4098
x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
'RT
R,W
1 -..... DSP7201-009
NOTES:
1. tATe = tRT + t ATA .
2.
EF, RF and FF may change state during retransmit as a result of the offset of the read and write pointers,
but flags will be valid at tATe-
Figure 6. Retransmit
tRPE: EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH
w----_
~
------------------------------------------------r-----'
"'PE
NOTE:
1. (I APE
DSP7201-010
=I APW).
Figure 7. Empty Flag Timing
'WPF: EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH
ff------------------------r----
J
OSP7201-011
NOTE:
1. (I WPF = Iwpw>,
Figure 8. Full Flag Timing
HALF-FULL + 1
HALF-FULL
-'~
HALF-FULL
-
I--
IRHF
...., ~
Ii
-
'WHF
-
..,r-
~,
j
DSP7201-012
Figure 9. Half Full Flag Timing
4-26
IDT7203/1DT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODES:
SINGLE DEVICE MODE
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7203/4 can easily be adapted to applications when the
requirements are for greater than 2048/4906 words. Figure 12
demonstrates Depth Expansion using three IDT7203/4s. Any
depth can be attained by adding additional IDT7203/4s. The
IDT7203/4 operates in the Depth Expansion configuration when
the following conditions are met:
A single IDT7203/4 may be used when the application requirements are for 2048/4096 words or less. The IDT7203/4 is in a
Single Device Configuration when the EXPANSION IN (Xl) control input is grounded. (See Figure 10.) In this mode the HALF
FULL FLAG (HF), which is an active low output, is shared with
EXPANSION OUT (XO).
1. The first device must be designed by grounding the FIRST
LOAD (FL) control input.
2. All other device must have
(HALF FULL FLAG)
HF
t
WRITE
(W)
/
(FF) ,
FULL FLAG
REseT
~
9
(D)
(Q) /
4. External logic is needed to generate a composite FULL FLAG
(FF) and EMPTY FLAG (EF). This requires the ORing of all EFs
and ORing of all FFs. (I.e. all must besetto generate the correct
composite FF or EF). See Figure 12.
READ
IR)
~
9
DATA IN
DATA OUT
5. The RETRANSMIT (RT) function and HALF FULL FLAG (HF)
are not available in the Depth Expansion Mode.
IDT7203/04
(fF)
(RS)
FL in the high state.
3. The EXPANSION OUT (XO) pin of each device must be tied to
the EXPANSION IN (XI) pin of the next device. See Figure 12.
(AT)
EMPTY FLAG'
RETRANSMIT
COMPOUND EXPANSION MODE
EXPANSION IN (xi)
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FI FO arrays.
(See Figure 13.)
~
DSP7203-003
Figure 10. Block Diagram of Single 2048 x 9/4096 x 9 FIFO
BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of READ and WRITE operations) can be
achieved by pairing IDT7203/4s as is shown in Figure 14. Care
must be taken to assure that the appropriate flag is monitored by
each system. (I.e. FF is monitored on the device where VIi is used;
EF is monitored on the device wher y R is used.) Both Depth
Expansion and Width Expansion may be used in this mode.
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags
(EF, FF and HF) can be detected from anyone device. Figure 11
demonstrates an 18-bitword width by using two IDT7203/4s. Any
word width can be attained by adding additional IDT7203/4s.
DATA FLOW THRU MODES
Two types of flow through modes are permitted with the
I DT7203!7204. A read flow through and write flow through mode.
For the read flow through mode (Figure 15), the FIFO permits a
reading of a single word of data immediately after writing one
word of data into the completely empty FIFO.
In the write flow through mode (Figure16), the FIFO permits a
writing of a single word of data immediately after reading one
word of data from a completely full FIFO.
DATA
IN (0)
WRITE
---"'''----1-
RESET
--"""---1-
DSP72Q3-004
NOTES:
Flag detection is accomplished by monitoring the ff, IT, and the HF signals on
either (any) device used in the width expansion configuration. Do not connect
any output control signals together.
Figure 11. Block Diagram of 2048 x 18/4096 x 18 FIFO Memory
Used in Width Expansion Mode
4-27
III
•
IDT7203I1DT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT • 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I -- RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
INTERNAL STATUS
INPUTS
MODE
OUTPUTS
RS
RT
XI
Read Pointer
Write Pointer
EF
FF
Reset
0
X
0
Location Zero
Location Zero
0
t
HF
1
Retransmit
1
0
0
Location Zero
Unchanged
X
X
X
ReadIWrite
t
1
0
I ncrement(1)
Increment(1)
X
X
X
NOTE.
1. Pointer will increment if flag is high.
TABLE" -- RESET AND FIRST LOAD TRUTH TABLE -DEPTH EXPANSION/COMPOUND EXPANSION MODE
OUTPUTS
INTERNAL STATUS
INPUTS
MODE
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset-First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
ReadlWrite
1
X
(1)
X
X
X
X
NOTES.
1. Xi is connected to X6 of previous device. See Figure 12.
AS = Reset Input. FL/RT = First Load/Retransmit. EF = Empty Flag Output.
W~______________~r-
o
FF = Full Flag Output. Xi = Expansion Input, Hi' = Half Full Flag Output.
1
R
______~~
~.-----~-------f--------------~
L
/
Q>
,
Vee
----
~~----------~-i
KG
I-+---l~r-I.FF
L-I....:;9,..-'\I
..
lOT
720314
--=EF
-
_
/
FL
1.-:--
DSP7203·005
Figure 12. Block Diagram 01 6,144 x 9/12,288 x 9 FIFO Memory (Depth Expansion)
4-28
IDT7203/1DT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT .. 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
... ------,
00-08
O(N-B)-ON
DO-DB
O(N-B)-ON
R,W,AS
DSP7203-006
NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 12.
2. For Flag detection see WIDTH EXPANSION Section and Figure 11.
Figure 13. Compound FIFO Expansion
iiii
ViA
EFa
FFA
,
~
D.o-B
II
HFa
IDT7203/4
°a°-8
,,J.
SYSTEM B
SYSTEM A
A
°-8
QA
liA
IDT72D3/4
,
°8°-8
Wjj
HF.
FF;;
EFA
0
Figure 14. Bidirectional FIFO Mode
4-29
IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY ANP COMMERCIAL TEMPERATURE RANGES
DATA IN
3V
;;.;--+--~
R __
ov
~
__________________
~
______
~
__________J
OV
u---+--------__----------~-----J
OATAOUT
----~--------------------~-{
DSP7201·018
Figure 15; Read Data Flow-Through Mode
3V
ov -+________--,______+ ______--+__________-'1
; .; __
ov
"-~-------+-----'I
DATAIN
DATAOUT
---4-----------------------------------<14 OAT::.~
.~,
---------<
ill:
~~~~~~~~~~~~~~>~d
•• ~ •••
nN~m~~~~~~~
CLKX
59 X"
X,D
57 Xg
56 Xs
55 X
7
54
Xe
53 X5
52
~
51 X3
50 X2
49 X1
48 Xo
47 ACC
48 SUB
45 RND
44 TSL
TSX 10
P26
p..
p..
P23
p..
P21
POD
P19
P1S
P17
P'6
P15
P14
P13
P12
TSM
60
"
12
13
14
15
16
58
17
16
19
20
21
22
23
24
25
26
~rereg~~~~~~~~~~~~~
~~~l~~~~~~~~~~~~~
lEd
CI
CICI
DSP7209-003
LCC
TOP VIEW
4-36
IDT7209L 12 x 12 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
'C
PT
Power Dissipation
1.6
1.6
W
lOUT
DC Output Current
50
50
rnA
-0.5 to +7.0
-0.5 to +7.0
SYMBOL
V
MIN. TYP. MAX. UNIT
PARAMETER
VeeM
Military Supply Voltage
4.5
5.0
5.5
V
Vce
Commercial Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V'H
Input High Voltage
2.0
-
V
V'L
Input Low Voltage
-
-
O.B
V
'C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation afthe device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vee =5V ± 10%, TA =O'C to +70°C, Military Vee =5V ± 10%, TA = -55°C to +125°C)
for Commercial clocked multiply times of 30,45.55,65ns or Military, 40.55.65,75ns
SYMBOL
PARAMETER
TEST CONDITIONS
Ilul
Input Leakage Current
Vce = Max., V'N = 0 to Vce
IILOI
Output Leakage Current
Hi Z, Vee = Max., VOUT
=0 to Vee
COMMERCIAL
MIN. TYP.!') MAX.
-
-
10
-
10
MILITARY
MIN. TYP.!') MAX.
-
UNIT
-
20
p.A
-
20
p.A
lec(2)
Operating Power Supply Current
Outputs Open Measured at 10MHz(2)
-
40
BO
-
40
100
rnA
IceQ'
Quiescent Power Supply Current
V'N ;, V'H, V'N " V'L
-
20
50
20
50
rnA
ICeQ2
Quiescent Power Supply Current
V'N;' Vee - 0.2V. V'N " 0.2V
-
4
20
-
4
25
I c d f (2.3)
I ncrease in Power
Supply Current/MHz
Vce = Max., f > 10MHz
-
-
6
-
-
B
VOH
Output High Voltage
Vcc = Min., 10H = -2.0mA
2.4
-
-
2.4
-
-
V
VOL
Output Low Voltage
Vec = Min .• 10L
-
-
0.4
-
-
0.4
V
=BmA
rnA
mAl
MHz
NOTES:
1. Typical implies Vee = 5V and TA = +25°C.
2. Icc is measured at 10MHz and V 1N = TTL voltages. Forfrequencies greater than 10MHz, the following equation is usedforthecommercial range: Icc =80 +6(f-10} rnA,
where f = operating frequency in MHz. For the military range, Icc = 100 + 8(f - 10) where f = operating frequency in MHz.
3. For frequencies greater than 10MHz.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vee =5V ± 10%, TA =DoC to +70'C. Military Vee =5V ± 10%, TA = -55°C to +125°C)
for Commercial clocked multiply times of 100,135ns or Military, 120,170ns
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
MIN. TYP.!') MAX.
lecQ'
Quiescent Power Supply Current
V'N;' V'H, V'N " V'L
-
10
30
ICCQ2
Quiescent Power Supply Current
V'N;' Vcc - 0.2V, V'N" 0.2V
-
0.1
1.0
I cc/f(2.3)
Increase in Power
Supply Current/MHz
Vce = Max., f> 10MHz
-
-
5
-
-
7
mAl
MHz
VOH
Output High Voltage
Vee = Min., 10H = -2.0mA
2.4
-
-
2.4
V
Output Low Voltage
Vee = Min., IOL = BmA
-
-
0.4
-
-
-
VOL
0.4
V
Vec = Max .• V'N = 0 to Vec
IILol
Output Leakage Current
Hi Z. Vcc = Max .• VOUT = 0 to Vce
Icc(2)
Operating Power Supply Current
Outputs Open Measured at 10MHz(2)
-
30
60
UNIT
-
lIul
Input Leakage Current
2
MILITARY
MIN. TYP.!') MAX.
2
-
10
-
10
p.A
30
BO
rnA
10
30
rnA
0.1
2.0
rnA
p.A
NOTES:
1. Typical implies Vee = 5V and TA = +25°C.
2. Icc is measured at 1 OMHz and V 1N = TTL voltages. For frequencies greater than 10M Hz, the following equation is used lor the commercial range: Icc = 60 + 5(1 -1 0) rnA,
where f = operating frequency in MHz. For the military range, Icc = 80 + 7(f - 10) where f = operating frequency in MHz.
3. For frequencies greater than 10MHz.
4-37
IDT7209L 12 x 12 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Vee
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
810n
OUTPUTo---~--~--,
OUTPUT~
1
.-l
-y~
PIN
SYMBOL
PARAMETER!11
C 'N
Input CapaCitance
C our
Output Capacitance
PIN .n_I:
1.lK
40pF
CAPACITANCE (TA = +25°C, f = 1.DMHz)
UNIT
CONDITIONS
TYP.
Y'N = OV
10
pF
Your = OV
12
pF
500n
TO
TO
DSP7216-010
DSP7216-009
NOTE:
1. This parameter is sampled and not 100% tested.
Figure 2. Output Three State
Delay Load
(V. = OV or 2.6V)
Figure 1. AC Output Test Load
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (Vee =5V ± 10%, TA =DOC to +7DOC)
SYMBOL
PARAMETER
IDT7209L-30
MIN.
MAX.
IDT7209L-45
MIN.
MAX.
IDT7209L-65
MIN.
MAX.
-
30
-
45
25
25
3-State Output Disable Delay(1)
-
25
-
25
-
Input Register Setup Time
12
15
-
25
3
-
3
-
15
-
25
-
tMA
Multiply-Accumulate Time
to
Output Delay
tENA
3-State Output Enable Delay(1)
tOiS
ts
25
tH
Input Register Hold Time
3
-
tpw
Clock Pulse Width
10
-
25
IDT7209L-l00 IDT7209L-l35
MIN.
MAX.
MIN.
MAX.
UNITS
TEST
LOAD
FIG.
1
-
100
ns
35
-
135
35
40
ns
1
30
-
35
-
40
ns
2
:10
-
35
-
40
ns
2
-
25
25
-
0
-
ns
0
-
ns
-
25
-
25
-
ns
-
UNITS
TEST
LOAD
FIG.
65
AC ELECTRICAL CHARACTERISTICS MILITARY (Vee = 5V ± 1D%, TA = DOC to +125°C)
SYMBOL
PARAMETER
IDT7209L-40
MAX,
MIN.
tENA
3-State Output Enable Delay(1)
t OIS
3-State Output Disable Delay(1)
-
ts
Input Regi~er Setup Time
15
tMA
Multiply-Accumulate Time
to
Output Delay
IDT7209L-55
MIN.
MAX.
IDT7209L-75
MIN.
MAlt
40
-
55
25
-
30
25
-
30
25
30
-
-
20
-
25
tH
Input Register Hold Time
3
-
3
-
3
tpw
Clock Pulse Width
15
-
20
-
30
NOTE:
1, Transition is measured ±5QOmV from steady state with loading specified in Fig. 2.
4-38
IDT7209L-120
MIN.
MAX.
IDT7209L-l70
MIN.
MAX.
120
-
170
ns
1
40
ns
1
40
-
45
35
-
45
ns
2
35
-
40
-
45
ns
2
-
30
30
-
ns
-
0
-
0
-
ns
30
-
30
-
ns
-
75
35
IDT7209L 12 x 12 PARALLEL CMOS MULTIPLIER·ACCUMULATOR
DATA
INPUT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
THREE~
CONS;:6~
lOIS
~rNI/JIL 3V
~~:V
tS~IH
f
CLOCK
INPUT
----.
lENA
OUTPUT----;*---:-:-==;~~~
THREE
~~y
O~
STATE _ _ _- '
HIGH IMPEDANCE
DSP7209-007
DSP7209-Q06
Figure 4. Three State Control Timing Diagram
Figure 3. Set Up and Hold Time
INPUT
INPUT
CLOCK
OUTPUT
CLOCK
PRELOAD
THREE-STATE
CONTROL
OUTPUT
DSP7209-00B
Figure 5. Timing Diagram
I
SIGNAL DESCRIPTIONS:
INPUTS:
high and SUB is low, an addition instead of a subtraction is
performed. Like the ACC signal, the SUB signal is loaded into
the SUB register at the rising edge of either CLKX or CLKY
and must be valid over the same period as the input data is
valid. When the ACC is low, SUB acts as a "don't care" input.
X,N (X11-XO>
Multiplicand Data Inputs
Y,N (Y11-YO>
Multiplier Data Inputs
TC (Two's Complement)
INPUT CLOCKS:
When the TC Control is HIGH, it makes both the X and Y
input, two's complement inputs. When the TC Control is
LOW, it makes both inputs, X and Y, unsigned magnitude
inputs.
CLKX,CLKY
Input data is loaded on the rising edge of these clocks.
CONTROLS:
ACC (Accumulate)
RND (Round)
When ACC is high, the contents of the XTP, MSP and LSP
registers are added to or subtracted from the multiplier
output. When ACC is low, the device acts as a simple
multiplier with no accumulation being performed and the
next product generated will be stored directly into the output
registers. The ACC signal is loaded on the rising edge of
the CLKX or CLKY and must be valid forthe duration of the
data input.
A high level at this input adds a "1" to the most significant
bit of the LSP to round up the XTP and MSP data. RND, like
ACC and SUB, is loaded on the rising edge of either CLKX or
CLKY and must be valid for the duration of the input data.
PREL (Preload)
When the PREL input is high, the output is driven to a high
impedance state. When the TSX, TSL and TSM inputs are
also high, the contents of the output register can be preset to
the preload data applied to the output pins at the rising of
CLKP. The PREL, TSM TSL and TSX inputs must all be valid
over the same period that the preload input is valid.
SUB (Subtract)
When the ACC and SUB signals are both high, the contents
of the output register are subtracted from the next product
generated and the difference is stored back into the output
registers at the rising edge of the next CLKP. When ACC is
4·39
IDT7209l 12 x 12 PARAllEL CMOS MUlTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TSX, TSL, TSM (Three State Output Controls)
case when multiplying -1 x -1. With the additional bits that are
available in this multiplier, the -1 x -1 is valid operation that
yields a +1 product.
3. In operations that require the accumulation of single products or sum of products, there is no change in format. To allow
for a valid summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are
provided. This is the same as if the product was accumulated
off-chip in a separate 27-bit wide adder. Taking the sign at the
most significant bit position will guarantee that the largest number field will be used. When the accumulated sum only occupies
the right hand portion of the accumulator, the sign will be
extended into the lesser significant bit positions.
The XTp, MSP and LSP registers are controlled by direct
non-registered control signals. These output drivers are at
high impedance (disabled) when control signals TSX, TSM
and TSL are high and are enabled when TSX, TSM and TSL
are low.
OUTPUT CLOCK:
CLKP
Output data is loaded into the output register on the rising
edge of this clock.
OUTPUTS:
XTP (P26-P24)
Extended Product Output (3-bits)
PRELOAD TRUTH TABLE
MSP (P:wP1V
Most Significant Product
LSP (P11-PO)
Least Significant Product
NOTES ON TWO'S COMPLEMENT FORMATS:
1. In two's complement notation, the location of the binary point
that signifies the separation of the fractional and integer fields is
just after the sign, between the sign bit (_2 0 ) and the next significant bit for the multiplier inputs. This same format is carried
over to the output format, except that the extended significance
of the integer field is provided to extend the utility of the accumulator. In the case of the output notation, the output binary
point is located between the 20 and 2- 1 bit positions. The location of the binary point is arbitrary, as long as there is consistency with both the input and output formats. The number field
can be considered entirely integer with the binary point just to
the right of the least significant bit for the input, product and the
accumulated sum.
2. When in the non-accumulating mode, the first four bits (P 26
through P23) will all indicate the sign olthe product. Additionally,
the P22 term will also indicate the sign except for one exceptional
PREl
TSX
TSM
TSl
XTP
MSP
lSP
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q
Q
Q
Q
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
PL
PL
PL
PL
Q
Q
HiZ
HiZ
Q
Q
HiZ
HiZ
HiZ
HiZ
PL
PL
HiZ
HiZ
PL
PL
Q
HiZ
Q
HiZ
Q
HiZ
Q
HiZ
HiZ
PL
HiZ
PL
HiZ
PL
HiZ
PL
NOTES:
Hi Z = Output buffers at high impedance (output disabled).
Q = Output buffers at low impedance. Contents of output register will
be transferred to output pins.
PL = Output buffers at high impedance, or output disabled. Preload
data supplied externally at output pins will be loaded into the
output register at the rising edge of CLKP.
•
BINARV POINT
"
"
Pol '3 '11 "
'0
SIGNAL
LB.
DSP7209-009
Figure 6. FractionallWo's Complement Notation
4-40
IDT7209L 12 x 12 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BINARY POINT
DSP7209~010
Figure 7. Fractional Unsigned Magnitude Notation
BINARY POINT
SIGNAL
f=;;P,;t'=:;tc:;t.::;1Por:;r:;+c:;t.::;1P'P'C1 DIGIT VALUE
r;;P';r:*:':+-';1p.p.!+'*:;t~P.P.C1 SIGNAL
L-.L--'---'---'---"'-'-'--'---'-'-L---''-.L....-j DIGIT VALUE
DSP7209-011
Figure 8. Integer Two's Complement Notation
SIGNAL
Rct=;:;r:;t=;.t"::;-P.+:;.r::;t::;t..::;.t--=O+:;-t DIGIT VALUE
P.:E:!+,*~..:.;.~t..:,~*.:;.t"::-p'+";-tSIGNAL
L.:.....I.-'.--'-':....L---'_'--",-,,-'-:....L;;....l":""'--'--i DIGIT VALUE
Figure 9. Integer Unsigned· Magnitude Notation
4-41
DSP7209-012
II
FEATURES:
DESCRIPTION:
• 16 x 16 parallel multiplier/accumulator with selectable
accumulation and subtraction
• High-speed - 35ns multiply/accumulate time
• I DT721 0 features selectable accumulation, subtraction and
rounding and preloading with 35-bit result
• IDT7243 features selectable accumulation, subtraction and
rounding with 19-bit result
• IDT7210 is pin and functionally compatible with the
TRW TDC1010J
• IDT7243 is pin and functionally compatible with the
TRWTDC1043
The IDT7210/IDT7243 are high-speed, low-power 16 x 16
parallel multiplier/accumulators that are ideally suited for realtime digital signal processing applications. Fabricated using
CEMOS silicon gate technology, these devices offer a very lowpower alternative to existing bipolar and NMOS counterparts,
with only 117 to 1/10the power dissipation and exceptional speed
(35ns maximum) performance.
Pin and functional replacements for TRW's TDC1010JITOC1043, the IDT721017243 operate from a single 5 volt supply and
are compatible with standard TTL logic levels. The architecture
ofthe I DT721 017243 is farily straightforward, featuring individual
input and output registers with clocked D-type flip-flops, a preload capability (IDT7210 only) which enables input data to be
preloaded into the output registers, individual three-state output
ports for the extended product (XTP) and most significant
product (MSP), and a least significant product output (LSP)
whic\:l is multiplexed with the Y input. Unlike the IDT7210, the
1DT7243 does not have either a preload capability or a least
significant product (LSP) output accessible externally.
The XIN and YIN data input registers may be specified through
the use of the two's complement input (TC) as either two's
complement or an unsigned magnitude, yielding a full-precision
32-bit result that may be accumulated to a full 35-bit result. The
• Both devices perform subtraction and double precision
addition and multiplication
• Produced using advanced CEMOS'· high-performance
technology
• Low-power consumption (less than 250mW typical) - less
than 1110 the power of compatible bipolar and 117 the power
of NMOS designs
• Input and output directly TTL-compatible
• Single 5V supply
• Available in topbraze DIP, SHRINK-DIp, plastic DIP, LCC,
Fine-Pitch LCC, PLCC and Flatpack
• Military product available 100% screened to MIL-STD-883,
Class B
Continued on Page 2
FUNCTIONAL BLOCK DIAGRAMS
CLKV
CLKX X'H(X,!> - Xo)
YIN (Y15 - YolP15 - PO)
Ace, SUB,
RND, TC
CLKY VIN(V1S - Vol
TSX
XTPOUT
(P34 ·P32)
TSM
3
XTPOUT
(P34-P32)
MSPOUT
(P31.P16)
DSP721 0-001
DSP721 0-002
IDT7243
IDT7210
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
101986 Integrated Device Technology, Inc.
4-42
JULY 1986
Printed in U.S.A.
IDT7210L/IDT7243L 16 x 16
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (CONT'D)
three output registers-extended product (XTP), most significant product (MSP) and least significant product (LSP)-are
controlled by the respective TSX, TSM and TSL input lines.
The LSP output can be routed through YIN ports in the IDT7210.
The accumulate input (ACC) enables the device to perform
either a multiply or a multiply-accumulate function. In the multiply-accumulate mode, output data can be added to or subtracted from subsequent results. When the subtraction (SUB)
input is active simultaneously with an active ACC, a subtraction
can be performed. The double precision accumulated result is
rounded down to either a single precision or single precision plus
3-bit extended result. In the multiply mode, the extended product
output (XTP) is sign extended in the two's complement mode, or
set to zero in the unsigned mode. The ROUND (RND) control
rounds up the most significant product (MSP) and the 3-bit
extended product (XTP) outputs. When pre-load input (PREL) is
active, all the output buffers are forced into a high-impedance
state (see PRELOAD truth table) and external data can be loaded
into the output register by using the TSX, TSL and TSM signals as
input controls.
PIN CONFIGURATIONS
IDT7210
x,
x,
x,
x,
x,
x,
XIO
X2
x"
x"
x"
x"
x"
x,
Xo
Po. Yo
Pl. V,
IDT721 0
IDT7243
x,
x,
x,
x,
x,
x,
x,
X2
x"
x"
x"
x"
x"
x,
Xo
Vo
V,
V,
NC
RNO
Ps, Y5
Ps, Y6
CLKX
V,
V,
V,
P7. Y7
elKY
v,
elKY
Vee
TC
TSX
GNO
TSM
CLKP
Pa, V3
P4, Y4
V,
GNO
Vee
GNO
Pa. Va
Pg, Vg
TC
TSX
V,
V,
SUB
ACC
CLKX
PHI. Vl0
PREL
VIO
Pll. V11
TSM
CLKP
V"
P"
P"
P"
P31
P30
P"
P"
P"
P"
P,.
V"
V"
V"
P16
P17
P18
P19
P"
P2I
P"
P,.
P"
P2I
P"
P"
P"
P"
P"
P"
P"
P"
P"
P"
Pl20 Y12
Pl3. V13
P14. Y14
P1S. V1S
P16
P17
P18
V"
gcnco"," co
>nLl)Lnan
5!;:
~
~;! ~
~~~~£f££l£l
;1;~:n;::n5iC':~~~3
P"Y,61
43 P17
Po.Vo 62
42 P1B
Xo 63
X,64
X2 65
X,66
. . 67
41
40
39
38
37
Xs 68
x,
x,
x,
x,
XIO
x"
x"
x"
x"
9
P19
P"
P2I
P"
P23
36 P24
1
35 P25
34 P"
2
3
4
5
33 P27
32
31
30
29
P28
P"
P30
P3l
28 P32
'0 P"
Sl;:~~':!~~t::=~~N~
~~~
:Eo. X
,,>co.
~~~i~;;~~~~~~ ......
00
0
DSP721 0-005
LCC, PLCC & FINE-PITCH LeC
TOP VIEW
P"
P31
P30
P"
P,.
DSP7210-004
DSP721G-003
DIP
TOP VIEW
t>l~"";oi
XIO
TSL
RNO
SUB
ACC
P2> Y2
».:~.:
D.Q.Q.Q.Q.
DIP
TOP VIEW
IDT7243
DD
>~~~~~~~~;;;~;~~~
g~~~~~~~~~~~~~~~3
V,
VO
Xo
Xl
43
42
41
40
39
38
P17
P18
P19
P,.
P2I
P"
37p"
36 P"
35 P"
34 P"
33 P21
32 P"
31 P"
30 P30
29 P31
29 P",
'0 p ..
61
62
63
64
X2 65
X,66
X467
Xs 68
X,
X,
X,
x.
1
2
3
4
X"
X"
X"
X"
X"
~~~~~~~~'~~N~~~~~
~~~~~;;~~~~ee~~;l
00
0
DSP721Q-006
LCC, PLCC & FINE-PITCH LeC
TOP VIEW
4-43
I
IDT7210LIIDm43L 18 x 18
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont'd)
IDT7243
IDT7210
.x,
x.
x.
x,.
x"
x,.
x,.
x,.
x,.
x,
X,
x.
x..
x"
x,.
X,
x,
x,
x.
liz
x,
Xu
',1,Y11
P'20 Y12
X13
X14
X16
N/C
TSl
RND
SUB
ACC
CLKX
CLKV
Vee
Vee
TC
TSX
GND
TSM
ClKP
P'31 V,3
P,. V,4
P,. V,5
POI
NlC
p~Yo
P,. Y,
N/C
TSl
RND
SUB
ACC
CLK X
ClK V
Vee
Vee
TC
TSX
PREL
TSM
ClKP
P .. V.
P3J Va
P..,Y.
'SlY,
p. V,
PJl Y7
GND
GND
P .. Y.
p .. Y.
PUlr V,0
p..
p ..
p..
p..
p..
p..
p..
P,.
p..
p..
p..
p..
p..
P 27
p..
p..
p..
p..
x.
x,
liz
Xu
N/C
V.
V,
V.
V.
V,
V.
V.
V,
GND
GND
Y,
Y.
Y..
Y"
Y,.
Y,.
Y14
Y15
P"
P 17
p..
p..
P"
P 17
P 27
X,
X,
X,
p..
P"
p..
p..
p..
p..
P.,
p..
p..
P.,
p..
p..
SHRINK-DIP
TDPVIEW
SHRINK-DIP
TDPVlEW
IDT7210
IDT1243
»fIJ~>-.>-IIt';)!:Q )!'~J';';~.J';
~ iii A .;.
if
,..t,Z
Io" • ;: fI
~
!
Q
~~~~~)!')!"l5~~';-;i"';":.J';
j
~~~~~~~~~~~~~~~~
:~~~$~~~~~~~~~~~
.
."
PQo Yo 1
X. '
X,3
45
X. '
x••
x,.
44
43
42
X. '
x,
'
X, •
41
P"
P 17
P"
P"
P,.
P.,
p..
p..
p..
p..
p..
X10 12
p..
p..
X,3 '5
34
P,.
X M 16
33
p..
X,2 '4
X,3 '5
X14 16
41
Xe
40
39
38
37
36
35
34
33
10
x, "
X,1
'3
~~~gN~~~~~~i~~~~
~~~~~~~~~re~re~~M~
I!!;;tQIIIU>C> 8(.)(0:10. aal
_~QmOM>oOM~~~x=A
K=li~~~~~=i=~~~~
1.)1.)
45
44
43
42
x, •
P 27
X,10
X.'1
47
x,.
40
39
38
37
36
35
X,0 ' 2
X11 13
X,2 '4
.
..
Y. '
Xu'
X,3
X.4
X.5
X••
X.7
)( .... ~iil!ol!5!5,.. .... ~~~!5 .........
1.)1.)
I.)
FLATPACK
TDPVIEW
FLATPACK
TDPVlEW
4-44
I.)
P"
P"
P"
p,.
p..
P.,
p..
p..
p ..
p..
p..
P 27
p.
p..
P,.
P.,
IDT7210L/IDT7243L 16 x 16
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
COMMERCIAL
Terminal Voltage
with Respect
toGND
-0.5 to +7.0
MILITARY
UNIT
-0.5 to +7.0
Operating
Temperature
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
'C
oto +70
PT
Power Dissipation
1.6
lOUT
DC Output Current
50
VCCM
Military Supply Voltage
4.5
5.0
5.5
V
Vee
Commercial Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.0
-
-
V
V,L
Input Low Voltage
-
-
O.A
V
V
TA
-55 to +125
'C
1.6
W
50
mA
MIN. TYP. MAX. UNIT
PARAMETER
SYMBOL
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause pern'anent damage to the device. This is a stress rating only and
functional opera~ion of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vee = 5V ± 10%, TA = O°C to +70°C, Military Vee = 5V ± 10%, TA = -55°C to +125°C
for Commercial clocked multiply times of 35,45,55,65ns or Military 40,55,65,75ns
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
MIN. TYP.(1) MAX.
-
-
10
-
-
Outputs Open Measured at 10MHz(2)
-
Quiescent Power Supply Current
V,N '" V,H, V'N ,; V,L
Quiescent Power Supply Current
V'N'" Vee - 0.2V, V'N ,; 0.2V
ledI12.3 )
Increase in Power
Supply Current/MHz
Vee
VOH
Output High Voltage
Vee
VOL
Output Low Voltage
Vee = Min., 10L = SmA
MILITARY
MIN. TYP.(1) MAX.
UNIT
-
20
10
-
-
20
45
90
-
45
110
-
20
50
-
20
50
-
4
20
-
4
25
=Max., I> 10MHz
-
-
6
-
-
=Min.,
2.4
-
-
2.4
-
-
-
-
0.4
-
-
0.4~
Ilul
Input Leakage Current
Vee = Max., V'N = 0 to Vee
IILOI
Output Leakage Current
Hi Z, Vee = Max., VOUT
lee (2)
Operating Power Supply Current
leeo,
lee02
10H
=0 to Vee
= -2.0mA
/LA
/LA
-
mA
mA
I
mA
6I~
MHz
",
i
V
NOTES:
1. Typical implies \Icc
=5V and TA = +25
D
C.
2. Icc is measureo at 1OMHz and V1N = TTL voltages. For frequencies greater than 1OMHz, the following equation is used forthe commercial range: Icc =90 1 5(1 -1 0) rnA,
where f = operating frequency in MHz. For the military range, Icc = 110 + 8(1 -10) where f =operating frequency in MHz.
3. For frequencies. greater than lOMHz.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vee = 10V ± 10%, TA = O°C to +70°C, Military Vee = 10V ± 10%, TA ~ -55'C to +125°C
for Commercial clocked multiply times of 1oo,165ns or Military 120/200ns.
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
MIN. TYP.(1) MAX.
MILITARY
MIN. TYP.(1) MAX.
UNIT
-
Ilul
Input Leakage Current
Vee
10
-
2
-
-
Hi Z, Vee
-
2
Output Leakage Current
=Max., V,N = 0 to Vee
=Max., VOUT =0 to Vee
-
IILOI
-
10
/LA
lee(2)
Operating Power Supply Current
Outputs Open Measured al 10MHz(2)
-
35
70
-
35
90
mA
/LA
leeo,
Quiescent Power Supply Current
V,N ;' V'H' V,N '; V,L
30
-
10
30
mA
Quiescent Power Supply Current
V'N'" Vee - 0.2V, V'N ,; 0.2V
-
10
lee02
0.1
1.0
-
0.1
2.0
mA
lee/fI2.3)
Increase in Power
Supply Current/MHz
Vee
=Max., I > 10MHz
-
-
5
-
-
7
VOH
Output High Voltage
Vee
=Min.,
2.4
2.4
V
Vee = Min., 10L = SmA
0.4
-
-
-
Output Low Voltage
-
-
VOL
0.4
V
10H
=-2.0mA
-
mAl
MHz
NOTES:
1. Typical implies Vee = 5V and TA
=+25°C.
2. Icc is measured at lOMHz and V1N = TTL voltages. For frequencies greater than lOMHz, the following equation is used forthecommercial range: Icc =70 + 5(t -10) rnA,
where f = operating frequency In MHz. For the military range, Icc = 90 + 7(1 - 10) where f = operating frequency in MHz.
3. For frequencies greater than 10MHz.
4-45
II
IDT7210L/IDT7243L 16 x 16
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
CAPACITANCE
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
(TA
=+25°C, f =1.0MHz)
PARAMETER!')
SYMBOL
C 'N
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
Y'N = OV
10
pF
VOUT = OV
12
pF
NOTE:
1. This parameter is sampled and not 100% tested.
AC ELECTRICAL CHARACTERISTICS COMMERCIAL
SYMBOL
.1\
PARAMETER
(Vee
=5V ± 10%, TA =O°C to +70°C)
7210L75
7210L100
721OL165
TEST
7210L35
7210L45
7210L55
7210L65
7243L75
7243L100
7243L165 UNITS LOAD
7243L35
7243L45
7243L55
7243L65
FIG.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tMA
Multiply'Accumulate Time
-
35
-
45
-
55
-
65
-
75
-
100
-
165
ns
1
tD
Output Delay
-
25
-
25
-
30
-
35
-
35
-
35
-
40
ns
1
tENA
Three-State Output
Enable Delay!')
-
25
-
25
-
30
-
30
-
35
-
35
-
40
ns
2
t DiS
Three-State Output
Disable Delay!')
-
25
-
25
-
30
-
30
-
35
-
35
-
40
ns
2
ts
Input Register
Setup Time
12
-
15
-
20
-
25
-
25
-
25
-
30
-
ns
-
tH
Input Register
Hold Time
3
-
3
-
3
-
3
-
3
-
0
-
0
-
ns
-
tpw
Clock Pulse Width
10
-
15
-
20
-
25
-
25
-
25
-
25
-
ns
-
AC ELECTRICAL CHARACTERISTICS MILITARY
SYMBOL
PARAMETER
(Vee
=5V ± 10%, TA = -55°C to +125°C)
7210L55
7210L65
7210L75
7210L65
7210L120
7210L200
TEST
7210L40
7243L75
7243L85
7243L120
7243L200 UNITS LOAD
7243L55
7243L65
7243L40
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
FIG.
MIN. MAX.
tMA
MultiplyAccumulate Time
-
40
-
55
-
65
-
75
-
85
-
120
-
200
ns
1
tD
Output Delay
-
25
-
30
-
35
-
35
-
35
-
40
-
45
ns
1
tENA
Three-State Output
Enable Delay!')
-
25
-
30
-
30
-
35
-
35
-
40
-
45
ns
2
t Dis
Three-State Output
Disable Delay!')
-
25
-
30
-
30
-
30
-
35
-
40
-
45
ns
2
ts
Input Register
Setup Time
15
-
20
-
25
-
25
25
-
30
-
30
-
ns
-
tH
Input Register
Hold Time
3
-
3
-
3
-
3
-
3
-
0
-
0
-
ns
-
t pw
Clock Pulse Width
15
-
20
-
25
-
25
-
30
-
30
-
30
-
ns
-
~
NOTE:
1. Transition is measured ±500mV from steady state with loading specified in Fig. 2.
Vee
TO
50011
OUTPUT~
8100
TO
PIN
OUTPUTo---~--~--~
40pF
~ft_ l
..
.1
@~LIV'
PIN
UK
Yx;OOR2.6V
DSP8210"008
DSP7216-009
Figure 2. Output Three
Figure 1. AC Output Teat Load
SlBte Delay Load
4-46
IDT7210L/IDT7243L 16 x 16
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
DATA
INPUT
-NIIfJ
---
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~ 3V
THREE~
cONSJ:6~
tOIS
~ ~:V
IS n t H
CLOCK
INPUT
f
~~v
----.
----I'-----o~
THREE
OUTPUT
STATE
lENA
====)*--;;;;;;:;iMP~~;~
HIGH IMPEDANCE
DSP7201-010
DSP7210-009
Figure 4. Three State Control Timing Diagram
Figure 3. Set Up and Hold Time
INPUT
INPUT
CLOCK
OUTPUT
CLOCK
PRELOAD
THREE-STATE
CONTROL
OUTPUT
Figure 5. Timing Diagram
SIGNAL DESCRIPTIONS:
RND (Round)
INPUTS:
XIN (X15 -XO)
Multiplicand Data Inputs
VIN (V 1S-V 0)
Multiplier Data Inputs
A high level at this input adds a "1" to the most significant
bit of the LSP to round up the XTP and MSP data. RND, like
ACC and SUB, is loaded on the rising edge of either CLKX or
CLKY and must be valid for the duration of the input data.
PREL (Preload) (IDT7210 only)
When the PREL input is high, the output is driven to a high
impedance state. When the TSX, TSL and TSM inputs are
also high, the contents of the output register can be preset to
the preload data applied to the output pins at the rising of
CLKP. The PREL, TSM, TSL and TSX inputs must all be valid
over the same period that the preload input is valid.
INPUT CLOCKS:
CLKX,CLKV
Input data is loaded on the rising edge of these clocks.
CONTROLS:
VIN/LSP Output -
(LSP output, IDT7210 only)
Shares functions between 16-bit data input (YIN) and the
least significant product output (LSP).
ACC (Accumulate)
When ACC is high, the contents of the XTP, MSP and LSP
registers are added to or subtracted from the multiplier
output. When ACC is low, the device acts as a simple
multiplier with no accumulation being performed and the
next product generated will be stored directly into the output
registers. The ACC signal is loaded on the rising edge of
the CLKX or CLKY and must be valid for the duration of the
data input.
TSX, TSL, TSM (Three State Output Controls)
The XTp, MSP and LSP registers are controlled by direct
non-registered control signals. These output drivers are at
high impedance (disabled) when control signals TSX, TSM
and TSL are high and are enabled when TSX, TSM and TSL
are low.
SUB (Subtract)
When the ACC and SUB signals are both high, the contents
of the output register are subtracted from the next product
generated and the difference is stored back into the output
registers at the rising edge of the next CLKP. When ACC is
high and SUB is low, an addition instead of a subtraction is
performed. Like the ACC signal, the SUB signal is loaded into
the SUB register at the rising edge of either CLKX or CLKY
and must be valid over the same period as the input data is
valid. When the ACC is low, SUB acts as a "don't care" input.
OUTPUT CLOCK:
CLKP
Output data is loaded into the output register on the rising
edge of this clock.
OUTPUTS:
XTP (P34-P3V
Extended Product Output (3-bits)
MSP (P31-P1s)
Most Significant Product
TC (Two's Complement)
LSP (P1S -Po)
When the TC Control is HIGH, it makes both the X and Y
inputs, two's complement inputs. When the TC control is LOW,
it makes both inputs, X and Y, unsigned magnitude inputs.
Least Significant Product (IDT7210 only), shared with YIN
input.
4-47
IDT7210LIIDT7243L 16 x 16
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRELOAD TRUTH TABLE (IDT7210 only)
NOTES ON TWO'S COMPLEMENT FORMATS:
1. In two's complement notation, the location of the binary point
that signifies the separation of the fractional and integer fields is
just after the sign, between the sign bit (_2 0 ) and the next significant bit for the multiplier inputs. This same format is carried
over to the output format, except that the extended significance
of the integer field is provided to extend the utility of the accumulator. In the case of the output notation, the output binary
point is located between the 20 and 2-1 bit positions. The location of the binary point is arbitrary, as long as there is consistency with both the input and output formats. The number field
can be considered entirely integer with the binary point just to
the right of the least significant bit for the input, product and the
accumulated sum.
2. When in the non-accumulating mode, the first four bits (P34
to P31) will all indicate the sign of the product. Additionally, the
P30 term will also indicate the sign except for one exceptional
case when multiplying -1 x -1. With the additional bits that are
available in this multiplier, the -1 x -1 is a valid operation that
yields a +1 product.
PREL
TSX
TSM
TSL
XTP
MSP
LSP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
Q
Q
Q
Q
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
PL
PL
PL
PL
Q
Q
HiZ
HiZ
Q
Q
HiZ
HiZ
HiZ
HIZ
PL
PL
HiZ
HiZ
PL
PL
Q
HiZ
Q
HiZ
Q
HiZ
Q
HiZ
HiZ
PL
HiZ
PL
HiZ
PL
HiZ
PL
1
1
1
1
1
1
1
0
0
1
0
1
1
1
0
0
0
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
NOTES:
Hi Z = Output buffers at high impedance (output disabled).
Q = Output buffers at low impedance. Contents of output register will
be transferred to output pins.
Pl = Output buffers at high impedance. or output disabled. Preload
data supplied externally at output pins will be loaded into the
output register at the rising edge of ClK P.
3. In operations that require the accumulation of single products or sum of products, there is no change in format. To allow
for a valid summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are
provided. This is the same as if the product was accumulated
off-chip in a separate 35-bit wide adder. Taking the sign at the
most significant bit position will guarantee that the largest number field will be used. When the accumulated sum only occupies
the right hand portion of the accumulator, the sign will be
extended into the lesser significant bit positions.
Figure 6. FractionallWo's Complement Notation
BINARY POINT
SIGNAL
~~~~~~~~~~~~~~~~~~~~~~7.r~~~~~~~~=r7.T~~~r=~~
L..:....L..::....l.=--!''':''''.L..::....L::....L::.....I'::''''J..::......L::....L::....J'::''''J..::......L::....L::....J=--L.:......l::....J:'--l=--L:......J::.....J::....J=--L:......J::......L:-..I.:--L:......J::......L:--'':......J,,-.1;:.....l::......J DIGIT
4-48
VALUE
IDT7210L/IDT7243L 16 x 16
PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 7. Fractional Unsigned Magnitude Notation
BINARY POINT
Figure 8. Integer 'TWo's Complement Notation
BINARY POINT
Xo
SIGNAL
20 DIGIT VALUE
Yo
SIGNAL
20 DIGIT VALUE
Po
SIGNAL
20 DIGIT VALUE
Figure 9. Integer Unsigned Magnitude Notation
BINARY POINT
Xo
SIGNAL
20 DIGIT VALUE
Yo
SIGNAL
20 DIGIT VALUE
Po
SIGNAL
20 DIGIT VALUE
4-49
II
FEATURES:
DESCRIPTION:
• 20MHz parallel port access time
• 40MHz serial inpuVoutput port clock cycle
• Serial-to-Parallel, Parallel-ta-Serial, Serial-to-Serial and
Parallel-to-Parallel operations
• Easily expandable in depth and width
• Programmable word lengths from 3-bits to any bit width
using Flexishift'· without using any additional components
• Multiple status flags: Full, Almost-Full (1/8 from full), FullMinus-One, Empty, Almost-Empty (1/8 from empty), EmptyPlus-One, and Half-Full
• Asynchronous and simultaneous read and write operations
• Dual-ported zero fall-through time architecture with 50ns
access time
The 1DT72103/IDT72104 are high-speed Parallel Serial FIFOs
that are ideally suited for serial communications, high-density
media storage and local area networks.
The devices have four ports: Two of these are 9-bit parallel
ports and the other two are for serial input and serial output. A
variety of operations can be performed: Serial-ta-Parallel,
P'lirallel-to-Serial, Serial-to-Serial, and Parallel-to-Parallel. The
Parallel-Serial FI FOs can expand in depth or width for any of
these modes.
A unique feature that enhances the bandwidth is the handling
of serial wordlengths that are not a multiple of9. The I DT721 03/
IDT72104 can be configured to handle serial wordlengths of 3 to
9 bits, up to words of any length, using multiple devices. This
feature is provided without using any additionallCs. For example, a user can configurea4K x24 FIFO by using three devices to
generate internal increments to the read/write pointers every 24
cycles rather than every 27 cycles, thereby maintaining a high
bandwidth.
A number of flags are provided to monitor the status of the
FIFO. These include Full, Almost-Full (when the FIFO is more
than 7/8 full), Full-Minus-One (when the FIFO has one or zero
locations left), Empty, Almost-Empty (when the FIFO is less than
1/8 full), Empty-Plus-One (when there is only one or zero samples left in the FIFO), and a Half-Full Flag.
Read and Write controls are provided to permit asynchronous
and simultaneous operations. An Output Enable control is provided on the parallel port, and this is an additional control to the
Read input that also controls the parallel port.
Expansion controls XO and Xi are provided to allow cascading
for deeper FI FOs.
The IDT72103/IDT72104 are manufactured in advanced
CEMOS technology and fully conform to the requirements of
MIL-STD-883, Class B.
•
•
•
•
•
Output enable control provided for parallel port
Retransmit capability in single device mode
High-performance CEMOS'· technology
Available in DIP, LCC, and J-Leaded PLCC
Military product available 100% screened to MIL-STD-883,
Class B
APPLICATIONS:
•
•
•
•
•
•
•
•
High-Speed Data Acquisition Systems
Local Area Network Buffers
Remote Telemetry Buffers
Serial Link Buffers
High-Speed Parallel Bus-to-Bus Serial Communications
Magnetic Media Controllers
Single Chip Video Frame Buffers
FAx/Printer Buffers
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(Do- Dal
FULL-1
EMPTY + 1
FULL
EMPTY
SI/PI
ALMOST EMPTY/FULL
so/po
HALF FULL
FD;=:1:==~g=~=~C=T::::;
Xi
-----.J EXPANSION L XO
!
LOGIC!
OUTPUT ENABLE
(OE)
- - -....... SERIAL OUTPUT
REGISTER
DATA OUTPUTS
(Qo- Qal
SERIAL
OUTPUT
DSP72103-001
CEMOS and Flexishift are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
4-50
IDT72103/1DT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
W
D.
Vee
D.
D3
D2
Dl
D.
D7
D8
~
XI
SO/PO
SOX
SOCP
SO
AEF
FF-1
~L/R'f
AS
SI
SICP
SIX
iii/PI
OE
EF+1
FF
EF
xo/HF
Q.
Q1
Q8
Q2
Q3
Q.
GND
Q7
Q.
.9.
---"L"'-_ _..::.;.Jr-
DIP
TOP VIEW
R
DSP72103-OO2
II
4-51
FEATURES:
DESCRIPTION:
• 12 x 12 parallel multiplier with double precision product
• High-speed - 30ns maximum clock to multiply time
• Low-power consumption - 150mW typical, less than 1/10th
the power of compatible bipolar parts
• Produced with advanced CEMOS" high-performance
technology
• IDT7212L is pin and functionally compatible with
TRW MPY012H
• IDT7213L requires only a single clock with register enables
• Configured for easy array expansion
• User-controlled option for transparent output register mode
• Round control for rounding the MSP
• Single 5V power supply
• Input and output directly TTL-compatible
• Three-state output
• Available in DIP, SHRINK-DIp, plastic DIp, LCC or Flatpack
• Military product available 100% screened to MIL-STD-883,
Class B
The I DT721211 DT7213 are high-speed, low power12x 12 multipliers ideal for fast, real-time digital signal processing applications. Utilization of a modified Booths algorithm and IDT's highperformance, high-reliability technology, CEMOS, has achieved
speeds (30ns max.) exceeding bipolar at 1!1Oth the power
consumption.
The IDT7212/IDT7213 are ideal for applications requiring highspeed multiplications such as fast Fourier transform analysis,
digital filtering, graphic display systems, speech synthesis and
recognition, and in any system requirement where multiplication
speeds of a mini/micro computer are inadequate.
All input registers, as well as LSP and MSP output registers,
use the same positive edge triggered D-type flip-flop. With the
IDT7212, there are independent clocks (CLKX, CLKY, CLKM,
CLKL) associated with each of these registers. The I DT7213 has
only a single clock input (CLK) and three register enables. ENX
and ENY control the two input registers, while ENP controls the
entire product.
The IDT7212/IDT7213 offer additional flexibility with the FA
control. T.he FA control formats the output for 2's complement by
shifting the MSP up one bit and then repeating the sign bit in the
MSB of the LSP.
The 1DT7212/IDT7213 Multipliers are 100% processed in
compliance to the test methods of MIL-STD-883, Method 5004,
making them ideally suited to applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAMS
RND
RND
--++------'
CLK-~~~t-----~++---~
CLKY--t--t--.-.......
CLKX
m ---+---+--.:~~>~
.;:$!"ID"'ID~~tlll)"'MN .... CI
)0)0»»»»>>->->->->-
1~~~i~~~I~~~~~~t
Zg~~i~~~~~~~~~~t
(MSB)P"
P"
P21
P20
p,.
v,
+Vcc
+Vcc
P"
OEl
OEM
GNO
GNO
V.
V,o
FT
X"
ENX
ENV
RNO
XM
Vo
V,
V,
V,
V,
48 XM
47
46
45
44
5
RND
CLKV
CLKX
X11
P1a 6
P17 7
43 X'O
P"
8
41 X8
P15 9
40 X,
39 X,
38 X,
42 Xg
P141Q
P1311
P1212
(MSB)P"
P22
P"
P,o
P"
P18
P"
P"
P15
FA 15
FT 16
48 XM
47 RND
4600
45 ENX
44 Xl1
43 X,o
6
42 Xg
41 X8
40 X,
39 X,
9
P1410
38 Xs
37
P13 11
37 X4
CLKM 13
CLKL 14
1
2
3
x.
P1212
ENP 13
36 X,
35 X,
34 X,
elK 14
FA 15
36 X,
35 X,
34 X,
33 Xo
FT 16
33 Xo
~~'2~~~~~~~~~~~R
a a
1:11...1 ;:
<:)
CI>
00
'""
\I)
III
...
M
C'II
...
co
~~~~~~~~~~~~~~~~
~
DSP7212-005
TOP VIEW
DSP7212-007
TOP VIEW
4-53
IDT7212L/IDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7213
58-PIN SHRINK-DIP
IDT7212
58-PIN SHRINK-DIP
x.
Xg
x,o
x"
CLKX
CLKY
RND
XM
-.!n
ENX
ENY
RND
XM
N/C
N/C
N/C
Yo
Y,
Y2
Y.
Y.
Y.
Vee
vee
Vee
Y6
Y7
Y.
Y.
Y,o
Y"
YM
Po
P,
P2
OEM
GND
GND
Yo
Y,
Y2
Y.
Y.
Y.
Vee
vee
vee
Y6
Y7
Y.
Y.
Y,o
Y"
YM
El
OEM
GND
GND
N/C
N/C
N/C
N/C
P2•
P22
P21
P20
FT
FA
ClK
ENP
P'2
p.
p.
p.
p.
P7
p.
p.
P,o
~
P23
P22
P21
P20
FT
FA
ClKL
ClKM
P'2
p,.
p,.
Ne
ClKM
ClKl
FA
FT
5
•
7
•
9
p,.
p,.
p,.
TOPYIEW
IDT7213
68-PIN Lee
z»»»»»»»»
U~~~m~~G~gg~_~N~C
~~;;~~>~~~~>~~~>~
i~~~=~~~~~~"~'~3
imm~=~~~~~~'i~~~3
~
~
P21 .3
P'2
~
IDT7212
P,. 62
2
3
4
P,o
68-PIN Lee
(MSB)P" 61
P'4
P'3
p.
p.
p.
P7
p.
p.
P'7
P'6
TOPYIEW
64
65
N/C
Po
P,
P2
P3
p,.
p,.
p,.
p,.
p,.
P'7
P'6
P20
P'9
~'8
P17
P,e
P'5
x7
X6
X.
x.
x.
x2
X,
Xo
x.
X.
X,o
X7
X6
X.
X.
X.
X2
X,
Xo
~
66
43
.2
41
40
6'
XM
RNO
CLKY
ClKX
P21 63
P20
P'9
P1a
P17
39 X,1
38 X'D
37 Xg
67
68
1
35 X,
~
~-------
27
4' ENV
40 ENX
39 X,1
64
65
66
67
x,o
38
37 Xs
36 Xa
35 X7
P'668
P'5 1
P'4 2
36 X,
34
33
32
31
30
29
28
43 XM
42 RNO
(MSB) P"
P22 62
X,
X,
X.
X3
X,
X,
P13
3
P'2
4
34
33
32
NC
ENP
ClK
FA
FT
x.
NC
31
x,
x,
x.
x,
30 x,
29 x,
28 x.
27 NC
~~~~,~~~~~~~~~~~~
~~I~I~~ll~~~~~~~~~~
CD
"00 0
~
DSP7212-Q06
DSP7212-00B
TOP VIEW
TOPYIEW
4-54
IDT7212LIIDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
1.4
1.4
W
lOUT
DC Output Current
50
50
rnA
-0.5 to +7.0
-0.5 to +7.0
SYMBOL
V
PARAMETER
MIN. TYP. MAX. UNIT
VeeM
Military Supply Voltage
4.5
5.0
5.5
Vee
Commercial Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V
V,H
Input High Voltage
2.0
-
-
V
V,L
Input Low Voltage
-
-
0.8
V
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vee = 5V ± 10%, TA = O°C to +70°C,
Military Vee = 5V ± 10%, TA = -55°C to +125°C)
for Commercial clocked multiply times of 30,45,70ns br Military, 40,55,90ns
SYMBOL
PARAMETER
COMMERCIAL
MIN. TYP.(') MAX.
TEST CONDITIONS
= Max., V,N = 0 to Vee
= Max., VOUT = 0 to
lIu l
Input Leakage Current
Vce
IlLO I
Output Leakage Cu rrent
Hi Z, Vee
lee l2 )
Operating Power Supply Current
Outputs Open Measured at 10MHz(2)
IceQ1
Quiescent Power Supply Current
V1N
IceQ2
Quiescent Power Supply Current
V,N ? Vec - 0.2V, V,N oS O.2V
lee/I12.3)
Increase in Power
~
V1H , V1N
-:s;
V1L
Vee
= Max.,
I > 10MHz
VOH
Output High Voltage
Vee
10H
VOL
Output Low Voltage
Vee
= Min.,
= Min.,
Supply Current/MHz
Vee
= -2.0mA
10L = 8mA
MILITARY
MIN. TYP.(') MAX.
UNIT
-
-
10
-
-
20
-
-
10
-
-
20
I'A
-
30
65
-
30
85
rnA
-
20
50
-
20
50
rnA
-
4
20
-
4
25
rnA
mAl
MHz
I'A
-
-
6
-
-
8
2.4
-
-
2.4
-
-
V
-
-
0.4
-
-
0.4
V
NOTES:
1. Typical implies Vee::: 5V and TA ::: +25°C.
2. Icc is measured at 10MHz and V1N :::TTL voltages. Forlrequencies greater than 10MHz. the following equation is used forthe commercial range: Icc::: 65 + 6(1 -10) rnA,
where 1::: operating frequency in MHz. For the military range, Icc::: 85 + 8(f - 10) where 1 = operating frequency in MHz.
3. For frequencies greater than 10MHz.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vee = 5V ± 10%, TA = DoC to +70°C,
Military Vee = 5V
for Commercial clocked multiply times of 115ns or Military, 140ns
SYMBOL
PARAMETER
± 10%,
TA = -55°C to +125°C)
COMMERCIAL
MIN. TYP.(') MAX.
TEST CONDITIONS
lIu l
Input Leakage Current
Vee = Max., V,N
IILO I
Output Leakage Current
Hi Z, Vee
lee l2 )
Operating Power Supply Current
Outputs Open Measured at 10MHz12)
-
leCQl
Quiescent Power Supply Current
V1N ::::: V'H' V1N ::::: V1L
-
leeQ2
Quiescent Power Supply Current
V1N ::::: Vee
-
Increase in Power
= 0 to Vec
= Max., VOUT = 0 to
0.2V, V,N oS 0.2V
Vee
= Max.,
I> 10MHz
VOH
Output High Voltage
Vee
= Min.,
10H
VOL
Output Low Voltage
Vec = Min., IOL = SmA
lee/I12.3)
Supply Current/MHz
= -2.0mA
Vee
MILITARY
MIN. TYP.(') MAX.
UNIT
-
2
-
-
10
-
2
-
-
10
I'A
25
55
-
25
75
rnA
10
30
-
10
30
rnA
0.1
1.0
-
0.1
2.0
rnA
mAl
MHz
I'A
-
-
5
-
-
7
2.4
-
-
2.4
-
-
V
-
-
0.4
-
-
0.4
V
NOTES:
1. Typical implies Vec = 5V and TA = +25°C.
2. Icc is measured at 10MHz and V1N = TTL voltages. Forlrequencies greater than 10MHz, the following equation is used forthe commercial range: Icc::: 55 + 5(f -10) rnA,
where f = operating frequency in MHz. For the military range, Icc = 75 + 7(f - 10) where f ::: operating frequency in MHz.
3. For frequencies greater than 10MHz.
4-55
II
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7212L/IDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
AC ELECTRICAL CHARACTERISTICS COMMERCIAL
SYMBOL
(Vee = 5V ± 10%, TA = O°C to +70°C)
IDT7212L30
IDT7213L30
MAX.
MIN.
PARAMETER
-
t MUC
Unclocked Multiply Time
tMc
Clocked Mulliply Time
Is
X,
tH
X, Y, RND Hold Time
3
tPWH
Clock Pulse Width High
tPWL
IDT7212L45
IDT7213L45
MIN.
MAX.
-
65
30
-
20
50
45
IDT7212L70
IDT7213L70
MIN.
MAX.
IDT7212L 115
IDT7213L115
MIN.
MAX.
UNITS
TEST
LOAD
FIG.
-
105
-
155
ns
1
70
115
ns
1
20
-
25
-
ns
1
2
0
ns
1
25
-
ns
1
ns
1
3
15
-
-
20
-
20
-
Clock Pulse Width Low
15
-
20
-
20
-
25
-
tpop
Output Clock to P
ns
1
35
40
ns
2
lOIS
3 Slate Disable Time(2)
25
25
-
40
30
-
30
25
-
25
3 Stale Enable Time(2)
-
25
tENA
35
ns
2
ts
Clock Enable Setput Time (IDT7213 only)
15
-
20
-
25
ns
1
tH
Clock Enable Hold Time (IDT7213 only)
3
3
-
3
ns
1
tHCL
Clock Low Hold Time CLKXY Relative to
CLKML(1) (IDT7212 only)
0
-
0
-
0
-
ns
1
UNITS
TEST
LOAD
FIG.
V. RND Set-Up Time
15
AC ELECTRICAL CHARACTERISTICS MILITARY
SYMBOL
(Vee = 5V
IDT7212L40
IDT7213L40
MAX.
MIN.
PARAMETER
30
-
25
0
0
± 10%, TA = -55°C to +125°C)
IDT7212L55
IDT7213L55
MIN.
MAX.
IDT7212L90
IDT7213L90
MIN.
MAX.
t MUC
Unclocked Multiply Time
-
60
Clocked Multiply Time
-
40
-
55
-
130
tMc
ts
X,
20
-
20
-
25
tH
V. RND Set-Up Time
X, V. RND Hold Time
3
-
3
2
tPWH
Clock Pulse Width High
20
-
25
-
-
75
90
30
tPWL
Clock Pulse Width Low
20
-
25
-
30
t pop
Output Clock to P
25
-
30
25
-
30
25
-
25
-
IDT7212L140
IDT7213L140
MIN.
MAX.
-
185
ns
1
140
ns
1
30
ns
1
0
-
30
ns
1
-
ns
1
30
-
ns
1
45
ns
1
45
ns
2
40
-
45
ns
2
tENA
3 State Enable Time(2)
t OIS
3 State Disable Time(2)
-
ts
Clock Enable Setput Time (1DT7213 only)
20
-
25
-
30
-
30
-
ns
1
tH
Clock Enable Hold Time (IDT7213 only)
3
-
3
-
2
-
0
-
ns
1
tHCL
Clock Low Hold Time CLKXY Relative to
CLKML(1) (IDT7212 only)
0
-
0
-
0
-
0
-
ns
1
35
40
NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked.
2. Transition is measured ±500mV from steady state voltage with loading specified in Fig. 2.
vee
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDt03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
810n
soon
TO
TO
OUTPUT~
OUWUTo---~--~--~
PIN
PIN •___
40pF
CAPACITANCE
(TA
=+25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS
TYp.
UNIT
C 'N
Input Capacitance
10
pF
COUT
Output CapaCitance
=OV
VOUT =OV
12
pF
SYMBOL
IN3062
Y,N
DSP7212-009
Figure 1. AC Output Test Load
NOTE:
1. This parameter is sampled and not 100% tested.
4-56
1
~
-LI"
OSP7212-010
Figure 2. Output Three State
Delay Load
(V. = OV or 2.6V)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7212L/IDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
DATA
INPUT
- f0-1
1-1
CLOCK
INPUT
I
3V
1.SV
OV
THREE
STATE
CONTROL
- tDlS
...... tH ........
3V
1.SV
OV
OUTPUT
HIGH IMPEDANCE
THREE
STATE
NOTE:
Diagram shown for HIGH data only. Output transition
may be opposite sense.
DSP7212-012
DSP7212-011
Figure 4. Three-Slate Control Timing Diagram
Figure 3. Set-Up And Hold Time
CLKX
CLKY _ _ _-,-_ _---1
~L~~ -------------r---------------------------~
OUTPUTP
DSP7212-013
Figure 5. IDT7212 Timing Diagram
l-tPWH-1
DSP7212-014
Figure 6. I DT7213 Timing Diagram
4-57
II
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7212L1IDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
elK _ _ _ _...I
-I 1-
tHCL (IDT7212)
O l - - - - - - - - - I G - - ..!'=~!':..M~':..O!!;.S!: --I
DATA INPUT
DATA OUTPUT
R~S~S
TR'l,:~E'i:
DSP7212-015
Figure 7. Simplified Timing Diagram-Typical Application
SIGNAL DESCRIPTIONS:
FA (RS)(1)
INPUTS:
When the format adjust control is HIGH, a full 24-bit
product is selected. When this control is LOW, a left-shifted
23-bit product is selected with the sign bit replicated in the
Least Significant Product (LSP). This control is normally
HIGH except for certain fractional two's complement
applications. (See Multiplier Input/Output Formats.)
X'N (X11 through Xo)
Twelve Multiplicand Dala Inputs
Y,N (Y11 through Yo)
Twelve Multiplier Data Inputs
INPUT CLOCKS (IDT7212 ONLY):
FT
When this control is HIGH, both the Most Significant
Product (MSP) and Least Significant Product (LSP) registers
are bypassed.
ClKX
The rising edge of this clock loads the X11 - Xo data input
register along with the two's complement and round
registers.
OEl
ClKY
Three-state enable for LSP output.
The rising edge of this clock loads the Y11 - Yo data input
register along with the two's complement and round
registers.
OEP
Three-state enable for MSP output.
RND
ClKM
Round control for the rounding of the Most Significant
Product (MSP). When this control is HIGH, a one is added to
the Most Significant Bit (MSB) of the Least Significant
Prod\.lct (LSP). Note that this bit depends on the state of the
Format Adjust (FA) control. If FA is LOW when RND is HIGH,
a one will be added to the P 10. If FA is HIGH when RND is
HIGH, aonewill beaddedtotheP 11 .ln either case, theLSP
output will reflect this addition when RND is HIGH. Note also
the rounding always occurs in the positive direction which
may introduce asystematic bias. The RND input is registered
and clocked in at the rising edge of the logical OR of both
CLKX and CLKY.
The rising edge of this clock loads the Most Significant
Product (MSP) register.
ClKl
The rising edge of this clock loads the Least Significant
Product (LSP) register.
INPUT CLOCKS (IDT7213 ONLY):
ClK
The rising edge of this clock loads all registers.
ENX
Register enable for the X11 - Xo data input register along
with the two's complement and round registers.
OUTPUTS:
ENY
MSP (P23 through P12l
Register enable for the Y11 - Yo data input register along
with the two's complement and round registers.
Most Significant Product Output
E"NP
lSP (P11 through PO>
Register enable for the Most Significant Product (MSP)
and Least Significant Product (LSP).
Least Significant Product Output
CONTROLS:
XM, YM (TCX, TCy)(1)
Mode control inpuls for each data word. A low input
designates unsigned data input with a high input used for
two's complement.
NOTE:
1. TRW MPY012H/K pin designation
4-58
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7212L/IDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
BINARY POINT
Figure 8. Fractional Two's Complement Notation
DSP7212·016
BINARY POINT
i-='!-I~"::;+~~:!..f-=~;.pP::Rf.=!!:l
SIGNAL
DIGIT VALUE
SIGNAL
~~~~~~~~~~-Y~~
!-"--'-"--'-':...J-=-.L::..-L:c....L"-L.::....l.:.....L:'--I"-l.:.......J DIGIT VALUE
Figure 9. Fractional Unsigned Magnitude Notation
II
DSP7212·017
BINARY POINT
SIGNAL
1-':t--':l-"'-'!:-lr.+'--:t-:..:+-'-':-~:t-'4.:.::1-'+.P.::f (UNSIGNED MAGNITUDE)
f-=-.J...:.....L.::.....L-=--J..:..J..:....J..:...JI.:-..L:....l.:---l=-l:...-.I DIGIT VALUE
Figure 10. Fractional Mixed Mode Notation
DSP7212-018
* In this format an overflow occurs in the attempted multiplication of the two's complement number 10000 ... 0 with 1000 ... 00 yielding an
erroneous product of -1 in the fraction case and -222 in the integer case.
4-59
IDT7212L/IDT7213L 12 x 12 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BINARY POINT
~~~~~+-~~~~~~~~y-X~o SIGNAL
L..:....L::...J..::...JL...:....L.:-L::...J.L...:...J...:....L:....J.-=--L..:.....L..:2'-j· DIGIT VALUE
Y.
SIGNAL
2·
DIGIT VALUE
p. SIGNAL
2·
DIGIT VALUE ! FA = 0 !
p. SIGNAL
2·
DIGIT VALUE ! FA = • !
DSP7212-019
Figure 11. Integer lINo's Complement Notation
BINARY POINT
SIGNAL
R:F::+:.::-i-"':t":+.::t-'7I-":;r:::+.:.::1p.-t"!.'-l DIGIT VALUE
~~~~~~~~~~~~~~
SIGNAL
L::...J..:....J..::...JL...:...J..:....L:....J.-=--L.:....L..::...J.::...JL...:....L:'-j DIGIT VALUE
SIGNAL
~~=t~~~~~~~~~~~~~~~~~~~~;r:7t~~~7t~~DIGITVALUE
!FA=.!
MANDATORY
DSP7212-020
Figure 12. Integer Unsigned Magnitude Notation
BINARY POINT
f-:''I-!:+~~+-~~~~~~~~Y-Y~.rJ~:~NED MAGNITUDE)
L.:....L::...J..::...JL...:....L.:-L::...J.-=--L.:....L:....J.-=--L..:...L:2"'-j DIGIT VALUE
Figure 13. Integer Mixed Mode Notation
DSP7212-021
* In this format an overflow occurs in the attempted multiplication of the two's complement number 10000 ... 0 with 1000 ... 00 yielding an
erroneous product of -1 in the fraction case and -222 in the integer case.
4-60
FEATURES:
applications. Utilization of a mOdified Booths algorithm and
IDT's high-performance, high-reliability technology, CEMOS,
has achieved speeds comparableto bipolar, (35ns max.) at 1I10th
the power consumption.
The IDT7216/IDT7217 are ideal for applications requiring highspeed multiplications such as fast Fourier transform analysis,
digital filtering, graphic display systems, speech synthesis and
recognition, and in any system requirement where multiplication
speeds of a mini/micro computer are inadequate.
All input registers, as well as LSP and MSP output registers,
use the same positive edge triggered D-type flip-flop. In the
IDT7216, there are independent clocks (CLKX, CLKY, CLKM,
CLKL) associated with each of these registers. The IDT7217 has
only a single clock input (CLK) and three register enables. ENX
and ENY control the two input registers, while.ENP controls the
entire product.
The IDT7216/IDT7217 offer additional flexibility with the FA
control and MSPSEL functions. The FA control formats the
output for 2's complement by shifting the MSP up one bit and
then repeating the sign bit in the MSB of the LSP. The MSPSEL
low selects the MSP to be available at the product output port,
while a high selects the LSP to be available. Keeping this pin low
will ensure compatibility with the TRW MPY016H.
The IDT7216/IDT7217 Multipliers are 100% processed in compliance to the test methods of MIL-STD-883, Method 5004,
making them ideally suited to applications demanding the
highest level of performance and reliability.
• 16 x 16 parallel multiplier with double precision product
• High-speed 35ns clocked multiply time
• Low-power consumption - 200mW typical, less than 1/1Oth
the power of compatible bipolar parts
• Produced with advanced CEMOS'· high-performance
technology
• IDT7216L is pin and functionally compatible with TRW
MPY016H/K and AMD Am29516
• IDT7217L requires only single clock with register enables
making it pin and functionally compatible with AMD
Am29517
• Configured for easy array expansion
• User-controlled option for transparent output register mode
•
•
•
•
•
Round control for rounding the MSP
Single 5V power supply
Input and output directly TTL compatible
Th ree-state output
Available in SHRINK-DIP. Plastic DIP, LCC, Flatpack,
Fine-Pitch LCC, Pin Grid Array and Plastic LCC
• Military product available 100% screened to Class B
DESCRIPTION:
The IDT7216/IDT7217 are high-speed, low-power 16 x 16
multipliers, ideal for fast, real time digital signal processing
FUNCTIONAL BLOCK DIAGRAMS
RND
CLKY
--+-+-..---+--+----'
......+-+-r'"
CLK
ENX
CLKX -
OEL
ENY
MULTIPLIER
ARRAY
MULTIPLIER
ARRAY
:====~
FA
FT
16
CLKM - - - - - - - - - '
CLKL
----------i---'
ENP
MSPSEl - - - - - - - - ;
OEP
MSPlli
---------~~
OEP
PRODUCT
MSPOUT (P31 - P16)
IDT7216
MSPOUT (P31 - P16)
DSP721S-001
IDT7217
DSP7216-002
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
C19S6 Integrated Device Technology, Inc.
4-61
JULY 1986
Printed in U.S.A.
I
IDT7216L/IDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT7216
64-PIN DIP
IDT7217
64-PIN DIP
IDT7216/1DT7217
68-PIN SHRINKDIP
".X3
x,
x.
x,
X,
x,
x,
x,
X3
x,
x,
x,
x,
x,
x,
x.
x,
x,
x.
OEI
X10
QE[
X10
CLKL
x"
elK
ENY
x"
X12
X13
eLKY
Po Yo
P, Y,
X12
X'3
Po va
x"
x"
P, Y,
P2 V2
p& Va
X15
elKX
RND
XM
YM
P7 Y7
+Vcc
P7 Y7
P8 Va
+Vcc
Pa Va
+Ycc
+Vcc
P'OY,0
GND
GND
P9 V,
P'OY,0
GND
GND
P,1Y,1
MsPSEr
P,1 Y,1
P'2V,2
P,3Y,3
P,4 Y,4
FT
FA
MiPsE[
FT
FA
P2 V2
P3 V3
P4 Y4
P5 Y5
P9 V9
X15
ENi
RND
XM
YM
P3 V3
P4 Y4
Ps Y5
P6 Va
P,2Y,2
P,3Y,3
P,4Y,4
OEP
OEP
P'SV,5
Po P'6
P, P17
CLKM
P,SY,5
ENP
P,&P31
Po P'6
P, P17
P'SP 31
P2 P'8
P3 P'9
P'3P29
P2 P'8
P3 P'9
P'3P29
P'4P30
P14P 30
P4 P20
P5,P21
P'2P28
P11 P27
P4 P20
P'2P28
P"P27
PtuPa
Ps P21
P'0P26
P6 P22
P9 P25
p& P22
P9 P25
P7 P23
P8 P24
P7 P23
P8 P24
DSP7216-003
DSP7216-0Q4
TOP VIEW
x,
Xa
x7
xB
X.
x10
x.
X3
X2
X1
Xo
OEL
X11
X12
N/C
)(13
X1•
X1•
'(ENX)/CLKK
RND
XM
YM
+Vee
+Vee
GND
GNLJ
GNO
MSPSt:l
FT
FA
OEP
'(ENP)/CLKM
N/C
P1.. P31
P14• P30
P13• Pzg
P1z, P2B
pu. P27
P10. P2B
P", Pzs
CLKL/~)'
CLKY/(ENY)'
N/C
Do. Yo
P1.Y1
Pz, Y2
P", Y3
p... Y.
P50 Y.
p. Ya
~Y7
p. YB
P", Y.
P10. Y10
PU.Yu
P1z, Y12
P13• Y13
P1... Y1•
P1f;. Y1S
Po. P1a
P1• P17
Pz, P1B
P30 P1•
p... P20
P50 P21
p. P22
23
""
P24
p.. Y
TOPYIEW
TOP VIEW
X11
X.
X10
X7
X.
Xs
Xa
X3
IDT7216/1DT7217
68-PIN PGA
X.
X1
~
Xo
CLKY/(ENYj*
CLKL/(CLK)'
NC
•
~~~~~~~~~~~~~~~£u~
~-t--t'-t'>;;>iiI~-t-~>t
IS ~ Ii. A .& t1\Z ~
»
» » a;
PGA
TOP VIEW
'PIN DESIGNATION IN PARENTHESES INDICATES IDT7217 PIN NAME
4-62
05P7216-026
IDT7216L/IDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I0T7216
64-LEAD FLATPACK
IDT7217
64-LEAD FLATPACK
48
P1SP 31
P14P ao
P13P 29
Pl~28
)(12
P1SP 31
P14P 30
47 Xl1
46 X1D
45 X9
3
4
PU P 27
P1DP 26
43 "
42 "
41
P9P25
"
PaP24
9
P6P22 10
PSP21 11
P'20 12
40 )(4
39 X3
38 X2
P3P19
P2P18
P1 P 17
POP16
36 Xo
P7P 23
37 X,
13
14
15
16
48
47
46
45
P,:2P28
44 X,
P11 P 27
P,oP26
1
P13P 29
35 OEl
34 CLKL
33 CLKY
44 "
43 "
6
42 X6
41 Xs
PgP25
PaP24
P7P 23
P6P22
PsP21
P4P20
P3P19
P2P18
.. "
9
10
11
12
13
14
P,P17 15
PoP16 16
39 X3
38 X2
37 X,
36 '0
35 OEl
34 elK
33 ENY
DSP7216-005
DSP7216-007
TOP VIEW
TOP VIEW
IDT7216
LCC, PLCC
FINE-PITCH LCC
~:::~~~
IDT7217
LCC,PLCC
FINE-PITCH LCC
•• ~~~~.~aa
~>
~ ~~~;: ~><>< >2';' >:'-2 ~ ~I~ dI~
2~~~~~~~~~~~'~:~3
~m~~~~~~~~~"~~~3
_A.ftftAft,..
43 N/e
)(13 61
)(13 61
62
X14 62
42 PaVo
)(14
)(15 63
41 PlY'
)(15 63
CLKX
PND
XM
YM
Vee
64
65
66
67
68
+Vcc
GND
GND
1
2
3
MSPSEL
FT
FA
OEP
CLKM
N/C
40
39
38
37
36
35
34
33
P2Y2
PaY3
P4Y4
PsYs
PsYs
P7Y7
PaYs
PgYg
32
31
30
29
28
27
Pl0V10
P11V11
P12V12
P13V13
P14Y,4
P,SY,S
ENX
RNO
XM
YM
Vee
43
4:.:
41
40
64
65
66
67
68
+Vcc
1
GNO
GND
MSPSEL
FT
FA
OEP
2
3
ENP
N/C
39
38
37
36
35
34
33
32
31
30
29
28
"D
?/
~_
N/e
PoYo
P,Y,
P2Y2
P3Y3
P4Y4
PsYs
P6Y6
P7Y7
P,V,
PgY,
P,0Y,0
P"V"
P12V12
P,3Y,3
P14Vt4
P,SY1S
~~~~~~~~~~~N~~~~~
~~~~~~~~~~~~~~~~~
DSP7216-006
DSP7216-008
TOP VIEW
TOP VIEW
4-63
X12
Xl1
XlO
X9
IDT7216L/IDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
RECOMMENDED DC OPERATING CONDITIONS
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
T elAs
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
·C
PT
Power Dissipation
1.2
1.2
W
lOUT
DC Output Current
50
50
mA
-0.5 to +7.0
-0.5 to +7.0
SYMBOL
V
MIN. TYP. MAX. UNIT
PARAMETER
VCCM
Military Supply Voltage
4.5
5.0
5.5
Vcc
Commercial Supply Voltage
4.5
5.0
5.5
V
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.0
-
-
V
VIL
Input Low Voltage
-
-
O.S
V
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This Is a stress rating only and
functional operation oftha device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
=
=
=
=
(Commercial Vcc 5V ± 10%, TA O·C to 70·C, Military Vcc 5V ± 10%, TA -55·C to 125·C)
for Commercial clocked multiply times of 35,45,55,65ns or Military, 40,55,65,75ns.
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
MIN. TYP'(I) MAX.
MILITARY
MIN. TYP'(I) MAX.
Ilul
Input Leakage Current
Vee = Max., VIN = 0 to Vee
-
IILOI
Output Leakage Current
Hi Z, Vee = Max., VOUT = 0 to Vee
lee(2)
Operating Power Supply Current
Outputs Open Measured at 10MHz(2)
leeol
Quiescent Power Supply Current
VIN ~ VIH, VIN :5 VIL
20
40
leeo2
Quiescent Power Supply Current
VIN ~ Vec - 0.2V, VIN :5 0.2V
-
-
4
20
-
ledf (2.3)
Increase in Power
Supply Current/MHz
Vee = Max., f > 10MHz
-
-
6
-
VOH
Output High Voltage
Vee = Min., 10H = -2.0mA
2.4
-
2.4
VOL
Output Low Voltage
Vee = Min., 10L = SmA
-
-
0.4
-
10
-
-
-
40
80
10
UNIT
-
20
-
20
p.A
40
100
mA
20
50
mA
4
25
-
S
p.A
mA
mAl
MHz
-
V
0.4
V
NOTES:
1. Typical implies Vee = 5V and TA = +25C1 C.
2. Icc is measured at 10MHz and VIN = TTL voltages. Forlrequencies greater than 10MHz, the lollowing equation is used lorthe commercial range: Icc = 80 +6(I-l0)mA,
where I = operating lrequency in MHz. For the military range, Icc = 100 + 8(1 - 10) where I = operating frequency in MHz.
3. For frequencies greater than 10MHz.
DC ELECTRICAL CHARACTERISTICS
(Commercial Vcc = 5V ± 10%, TA = O·C to 70·C, Military Vcc = 5V ± 10%, TA = -55·C to 125·C)
for Commercial clocked multiply times of 75,95,140n5 or Military, 90,120,165n5.
SYMBOL
PARAMETER
TEST CONDITIONS
COMMERCIAL
MIN. TYP'(I) MAX.
Ilul
Input Leakage Current
Vee = Max., VIN = 0 to Vee
-
IILOI
Output Leakage Current
Hi Z, Vee = Max., VOUT = 0 to Vee
lee(2)
Operating Power Supply Current
Outputs Open Measured at 10MHz(2)
-
leeOl
Quiescent Power Supply Current
VIN ~ VIH , VIN :5 VIL
-
10
lee02
Quiescent Power Supply Current
VIN '" Vee - 0.2V, VIN :5 0.2V
-
0.1
MILITARY
MIN. TYP.(I) MAX.
UNIT
-
2
-
-
10
2
-
-
10
p.A
30
60
30
80
mA
30
-
10
30
mA
1.0
-
0.1
2.0
mA
p.A
ledf (2.3)
Increase in Power
Supply Current/MHz
Vee = Max., f> 10MHz
-
-
5
-
-
7
mAl
MHz
VOH
Output High Voltage
Vee = Min., 10H = -2.0mA
2.4
-
-
2.4
-
-
V
VOL
Output Low Voltage
Vee = Min., IOL
-
-
0.4
-
-
0.4
V
NOTES:
1. Typical implies Vcc
= SmA
=SV and TA =+2SoC.
2. Icc is measured at 1OMHz and V1N = TTL voltages. Forfrequencies greater than 10M Hz. the following equation is used for the commercial range: Icc = 60 + 5(1 -10) rnA,
where f =operating frequency in MHz. For the military range, Icc = 80 + 7(1 - 10) where f :;: operating frequency in MHz.
3. For frequencies greater than 10M Hz.
4·64
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7216L/1DT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
CAPACITANCE
SYMBOL
(TA = +25°C, f = tOM Hz)
PARAMETER(1)
C 'N
Input Capacitance
C OUT
Output Capacitance
Vee
CONDITIONS
TYP.
UNIT
Y,N = OV
10
pF
VOUT = OV
12
pF
810n
TO
TO
OUTPUT 0---.----'------,
PIN
NOTE:
1. This parameter is sampled and not 100% tested.
PIN
1.1K
40pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATA
INPUT
- 1-
CLOCK
INPUT
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
15
-1
- tH-
.n_"
1-
1
"'Lf
OSP7216-010
DSP7216-009
Figure 1. AC Output Test Load
Figure 2. Output Three State
Delay Load (V, = OV or 2.6V)
3V
THREE
1.5V
STATE
-lOIS
CONTROL
OV
1
f
500n
OUTPUT~
3V
OUTPUT
1.5V
HIGH IMPEDANCE
THREE
STATE _ _ _ _ _ _ __
OV
DSP7216-012
DSP7216-011
NOTE:
Diagram shown for HIGH data only. Output transition
may be opposite sense.
AC ELECTRICAL CHARACTERISTICS MILITARy(3)
SYMBOL
PARAMETER
I
Figure 4. Three-State Control Timing Diagram
Figure 3. Set-Up And Hold Time
(Vee = 5V
± 10%, TA = -55°C to +125°C)
IDT7216L-40 IDT7216L-55 IDT7216L-65 IDT7216L-75 IDT7216L-90 IDT7216L-120 IDT7216L-I85
IDT7217L-40 IDT7217L-55 IDT7217L-65 IDT7217L-75 IDT7217L-90 IDT7217L-120 IDT7217L-I85
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
t MUC
Unciocked Multiply Time
-
60
-
75
-
85
--
95
-
125
-
160
t MC
Clocked Multiply Time
-
40
-
55
-
65
-
75
-
90
-
120
ts
X, Y, RND Setup Time
15
-
20
-
25
-
30
3
-
3
3
-
3
-
2
-
30
X, Y, RND Hold Time
-
25
tH
tpWH
Clock Pulse Width High
15
-
15
-
15
-
15
-
25
-
30
tpWL
Clock Pulse Width Low
15
-
15
-
15
-
15
-
25
tpDSEL
MSPSEL to Product Out
-
25
-
30
-
35
35
-
-
-
UNITS
230
ns
185
ns
30
-
ns
0
-
ns
-
30
-
ns
30
-
30
-
ns
40
-
40
-
45
ns
ns
0
t pDP
Output Clock to P
-
25
-
30
-
30
-
35
-
40
-
40
-
45
t pDy
Output Clock to Y
-
25
-
30
-
30
-
35
-
40
-
40
-
45
ns
tENA
3 State Enable Time(2)
-
25
-
25
-
35
-
40
-
40
-
40
-
45
ns
t OIS
3 State Disable Time(2)
-
25
-
25
-
25
-
25
-
40
-
40
-
45
ns
ts
Clock Enable Setup Time
(IDT7217 only)
12
-
15
-
15
-
15
-
30
-
30
-
30
-
ns
tH
Clock Enable Hold Time
(IDT7217 only)
3
-
3
-
3
-
3
-
3
-
3
-
3
-
ns
t HCL
Clock Low Hold Time
CLKXY Relative to
CLKMLI') (IDT7216 only)
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked.
2. Transition is measured ±500mV form steady state voltage with loading specified in Figure 2.
3. For Test Load, see Fig ure 1.
4-65
IDT1216LIIDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL(1)
SYMBOL
PARAMETER
(Vee
=5V ± 10%, TA =O·C to +70·C)
1DT1216L-35 IDT1216L-45 IDT1216L-55 IDT1216L-55 IDT1216-75 IDT1216L-90 IDT1216L-140
IDT7217L-35 1DT1217L-45 IDT1217L-55 IDT1217L-55 IDT1217L-75 IDT1217L-90 IDT1217L-140
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
I MUC
Unclocked Multiply Time
I MC
Clocked Multiply Time
-
35
-
-
55
-
75
45
65
55
65
-
100
65
-
75
-
125
-
160
ns
90
-
140
ns
-
25
-
25
-
ns
0
ns
25
-
25
-
ns
30
35
-
40
ns
35
40
ns
40
ns
20
-
25
3
-
2
15
-
20
20
-
20
-
30
30
35
-
-
30
-
30
35
-
35
-
25
-
30
35
35
-
35
-
40
ns
22
-
25
-
25
-
30
-
30
-
40
ns
10
-
10
-
25
-
25
-
25
-
ns
3
-
3
-
3
-
3
-
3
-
ns
0
-
0
-
0
-
0
-
0
-
ns
Is
X, Y, RND Setup Time
12
15
-
20
IH
X, Y, RND Hold Time
3
-
3
-
3
IpwH
Clock Pulse Width High
10
-
15
-
15
-
tPWL
Clock Pulse Widlh Low
10
-
15
-
20
-
IpOSEL
MSPSEL to Producl Out
25
-
25
Output Clock to P
-
25
tpop
25
-
IpOY
Output Clock 10 Y
-
25
-
25
lENA
3 Stele Enable Tlme(2)
25
-
lOIS
3 Siale Disable Time (2)
-
22
-
ts
Clock Enable Setup Time
(IDT7217 Only)
10
tH
Clock Enable Hold Time
(IDT1217 Only)
3
-
I HCL
Clock Low Hold Time CLKXY
Relative to CLKMl(1)
(IDT1216 Only)
0
-
3
-
0
-
10
-
25
30
0
20
20
NOTE:
1. For Test Load, see Figure 1.
CLKX
CLKY _ _ _-:-_ _- '
INPUT
XI,YI,
RND
-+_____________--J
CLKL _ _ _ _ _ _
~~~
UNITS
______-+____________
~--J
Figure 5. IDT7216 Timing Diagram
4-66
DSP7216-013
ns
IDT7216L!IDT7217L16 x 16 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
I-'PWH-I
elK
l-tPWL-
X,
y,.
RND
OUTPUT Y
OUTPUT P
OSP7216-014
Figure 6. IDT7217 Timing Diagram
----·MC---elK
Of----------{D- - _R!:.e.5~"_M,,:;.': ~R_l~P__ -f
DATA
DATA OUTPUT
TO X, Y
REGISTERS
TO MSP, LSP
REGISTERS
-I 1-
t HCL (IDT7216)
O - - - - - - - - - [ ] - - .!'=':!:'~':..M~':"O~ ~s!: --I
DATA INPUT
TO X, y
REGISTERS
DATA OUTPUT
TO MSP, LSP
REGISTERS
DSP7216-015
Figure 7. Simplified Timing Diagram - Typical Application
4-67
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7216LIIDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
SIGNAL D.ESCRIPTIONS:
INPUTS:
FA (RS)(l)
XIN (X15 through XO>
When the format adjust control is HIGH. a full 32-bit product is
selected. When this control is LOW. a left-shifted 31-bit product is
selected with the sign bit replicated in the Least Significant
Product (LSP). This control is normally HIGH except for certain
fractional two's complement applications. (See Multiplier Input!
Output Formats.)
Sixteen Multiplicand Data Inputs.
YIN (Y15 through yo>
Sixteen Multiplier Data Inputs. (This is also an output port
for P 15-0.)
INPUT CLOCKS (IDT7216 ONLY):
ClKX
FT
When this control is HIGH. both the Most Significant Product
(MSP) and Least Significant Product (LSP) registers are
transparent.
The rising edge of this clock loads the X15-0 data input
register along with the X mode and round registers.
ClKY
The rising edge of this clock loads the Y15-0 data input
register along with the Y mode and round registers.
OEl
ClKM
OEP
Three-state enable for routing LSP through YIN/LSPOUT port.
The rising edge of this clock loads the Most Significant
Product (MSP) register.
Three-state enable for the product output port.
RND
Round control for the rounding olthe Most Significant Product
(MSP). When this control is HIGH. a one is added to the Most
Significant Bit (MSB) of the Least Significant Product (LSP).
Note that this bit depends on the state of the format adjust (FA)
control. If FA is LOW when RND is HIGH. a one will be added to
the 2-t6..bit (P14)' If FA is HIGH when RND is HIGH. a one will be
added to the 2-15_bit (P15)' In either case. the LSP output will
reflect this addition when RND is HIGH. Note also that rounding
always occurs in the positive direction which may introduce a
systematic bias. The RND input is registered and clocked in at
the rising edge of the logical OR of both CLKX and CLKY
ClKl
The rising edge of this clock loads the Least Significant
Product (LSP) register.
INPUT CLOCKS (IDT7217 ONLY):
ClK
The rising edge of this clock loads all registers.
ENX
Register enable for the X15-0 data input register along with
the X mode and round registers.
ENY
Register enable for the Y15-0 data input register along with the
Y mode and round registers.
MSPSEl
When the MSPSEL is LOW. the Most Significant Product (MSP)
is selected. When HIGH. the Least Significant Product (LSP) is
available at the product output port.
ENP
Register enable for the Most Significant Product (MSP) and
Least Significant Product (LSP).
OUTPUTS:
CONTROLS:
MSP (P 3l through Pl&l
Most Significant Product Output.
XM• YM (TCX. TCy)(l)
Mode control inputs for each data word. A LOW input designates unsigned data input and a HIGH input designates two's
complement.
lSP (P15 through Po)
Least Significant Product Output.
Yls-oilSPOUT (Y15 through Yo or P15 through Po)
NOTE:
_
Least Significant Product (LSP) Output available when OEL is
LOW. This is also an output port for Y15 -(}
1. TRW MPY016HJK pin designation.
4-68
IDT7216L/IDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BINARY POINT
DSP7216-016
Figure 8. Fractional Two'. Complement Nolation
BINARY POINT
DSP7216-017
Figure 9. Fractional Unsigned Magnllude Notation
BINARY POINT
I
DSP7216-018
Figure 10. Fractional Mixed Mode Notation
BINARY POINT
SIGNAL
pp.;t:.=t7.t"'7.r-:;t-:-:t-'=t..:.:-t-:';'P,;t-:*-7I...:.:-1p.+c;.J DIGIT VALUE
Figure 11. Integer Two's Complement Notation
OSP7216-019
* In this format an overflow occurs in the attempted multiplication of the two's complement number 1000 ... 0 with 1000.00 yielding an erroneous
product of -1 in the fraction case and _2 30 in the integer case.
4-69
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7216L/IDT7217L 16 x 16 BIT PARALLEL CMOS MULTIPLIER
BINARY POINT
1--"'+-'''+-''''+'"'''1I-''+-'''+--''+-'!.f-'7I-''f-''''+--'+-''-l--7+-,,+-X7-jO SIGNAL
L.:....L::.....L::.....L::...JL.:-J.::.....L..::...L:...J."::""L.:....L.::...L:....L.::...J--=--L.:.....J....:2'--l0 DIGIT VALUE
1--"'+'-"'+'''''+~p+-'''+--''+.:..!..f-'7I-'~''+--'+-''"l--'-'-f--,'+-Y7-jO SIGNAL
L.:....L::.....L::.....L::...JL.:-J.::.....L..::...L:...J."::""L.:....L.::...L:....L.::...J--=--L.:.....J....:2'--l' DIGIT VALUE
Figure 12. Integer Unsigned Magnitude Notation
BINARY POINT
(~~~~L
1-"'+'-"+-""+-"1f-.!.!+-'''+--''+-'!.f--:-I-'+-''+--'+-''-l--7+-,,+-X7-j'
COMPLEMENT)
L..:....L::.....L::.....L::...JL.:-J.::.....L..::...L:...J."::""L.:....L.::...L:....L.::...J--=--L.:.....J....:2'--l0 DIGIT VALUE
~~~~~NED
1--"'+'-"+-""+-"1f-.!.!+-'''+--''+-'!.f--:-I-'+-''+--'+-''-l--7+-,,+-Y7-j'
MAGNITUDE)
L.:....L::.....L::.....L::...J"::""J.::.....L..::...L:...J."::""L.:....L.::...L:....L.::...J--=--L.:.....J....:2'--l' DIGIT VALUE
~~~=+~~~~~~~~~~=+~~~~~~~~~~~~~~~~~~~~~~~~P~o SIGNAL
L--'-....L..--'-----'_'--.L._-'::=---''--.L..;.....L:.-1.::.......I-=-1..C....J..::.+'-L:....J-=--.L:......L:.-1.::.......I'--'-'':c~....L..::...l..:....J-=-L:...L.--'-;..J.-2'--' DIGIT VALUE
I
I
FA = 1
MANDATORY
DSP7216-021
Figure 13. Integer Mixed Mode Notation
4-70
FEATURES:
the result can be used bj another device) of 400ns for single
precision and 500ns for double precision multiplications. This
ultra-high speed performance is achieved by combining both
state-of-the-art CEMOS technology and advanced circuit design
techniques.
For signal processing applications, where higher throughput
speeds are required, operations including the function specification can be pipelined. For single precision multiplications, new
operands can be loaded and a product unloaded every 100ns
while double precision multiplies can be accomplished ata 200ns
rate. The IDT72265 ALU executes all operations at a 100ns
pipelined throughput. All operations including the function specification are pipelined so there is no penalty for i nterleavi ng various
functions. The on-chip pipeline is automatically advanced using
internal timers, so explicit pipeline flushing is not required.
This flexible two-chip set operates in full conformance with the
requirements of IEEE standard 754 revision 10.0. It performs
operations on single (32-bit) and double (64-bit) precision operands as well as conversion to 32-bit two's complement integers
(lDT72265 only). The IDT72264/265 accommodates all rounding
modes, infinity and reserved operand representations, and the
treatment of exceptions, such as overflow, underflow, invalid and
inexact operations. Exact conformance to the standards ensures
complete software portability between prototype development
and final application. A "FAST" mode eliminates the time penalty
for denormalized numbers by substituting zero for a denormalized
number.
The flexible inpuVoutput architecture of these devices allows
them to be used in systems with one, two, or three 32-bit buses, or
one 64-bit bus. Fully registered inputs and outputs, separately
controlled, are loaded on each positive-going transition of the
clock.
A 6-bitfunction control determines the arithmetic function to be
performed while a 4-bit status output flags arithmetic exceptions
and conditions. Both the function inputs and status outputs
propagate along with the data to ease system design timing.
• Pin and functionally compatible with Weitek 1264/1265
• Low-power (750mW typical per device) operation
• Single 5 volt supply - no need for two supplies
• Advanced CEMOS" 111.5 micron technology
• Fully conforms to the requirements of IEEE Standard 754,
version 10.0 for full 32-bit and 64-bit multiply and arithmetic
operations.
• Very high-speed operation
-10 megaflops (100ns) pipelined ALU operation
(add/subtracVconverVcompare)
-10 megaflops (100ns) pipelined 32-bit (single precision)
multiplications
-5 megaflops (200ns) pipelined 64-bit (double precision)
multiplications
• Full floating point function arithmetic logic unit including:
-Add
-Subtract
-Absolute Value
-Compare
-Conversion to and from two's complement integer
• Flexible system design
- Three 32-bit ports allow two data inputs and one
result output every 50ns
-One, two, or three port architectures supported
-Single phase, edge-triggered clock interface, with fully
registered TTL compatible inputs and outputs
• Standard 144-pin grid array package
DESCRIPTION:
The IDT72264 floating-point multiplier and the IDT72265
floating-point ALU provide high-speed 32-bit and 64-bit floatingpoint processing capability.
The IDT72264/265 are fabricated using IDT's advanced
CEMOS II 1.5 micron technology and are capable of a total
multiply latency (time required from the input of the operand until
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MARCH 1986
Printed in U.S.A.
""1986 Integrated Oevice Technology, Inc.
4-71
IDT72264/265 64-BIT IEEE FLOATING POINT MULTIPLIER AND ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
IDT72264 FLOATING POINT MULTIPLIER
3
MUXAM
MUXAL
MUXBM
MUXBL
32
FREG
32
AREG
32
BREG
LOAD
PIPE
PIPELINED DATA PATH
STAGE 1
(USED 1 X FOR 32-BIT, 2 X FOR 64-BIT)
LOAD
ACCUMULATOR
PIPE 1
PIPELINED DATA PATH
STAGE 2
4
~
~
DSP72265~OO2
4-72
IDT72264/265 64-BIT IEEE FLOATING POINT MULTIPLIER AND ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
IDT72265 FLOATING POINT ALU
3
MUXAM
MUXAL
MUXBM
MUXBL
6
IilEG
32
32
32
AREG
4
BREG
PIPELINED DATA PATH STAGE 1
LOAD
PIPE
PIPE 1
I
PIPELINED DATA PATH STAGE 2
PIPE 2
PIPELINED DATA PATH STAGE 3
PIPE 3
STREG
4
~
~
4-73
DSP72265-001
IDT72264/265 64-BIT IEEE FLOATING POINT MULTIPLIER AND ALU
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
GND
Z3'
Z,.
Z'3'
Z27
Z,o
Z25
Z2.
Z7
Z22
Z20
Z,.
Z3
Z,
GND
S3
NC
Vee
Z,.
Z ••
Z'2
Zl1
Z.
Z.
Z2'
Z.
Z,.
Z17
Vee
Yo
GND
S2
NC
NC
Z30
Z2S
Z2.
Zs
Z23
Z.
Z2
Z'6
Zo
GND
Y17
TEN
So
NC
NC
Y,.
Y,.
U.
CSU
S,
Y,
Y2
Y.
NC
Uo
U,
Y3
Y,.
Y2,
NC
CLK
NC
Y.
Y.o
Y.
F.
F.
Vss
Y23
Y2•
Y7
F3
Fo
F,
Ys
Y2•
Y2•
F.
NC
L.
Y••
Y,o
Y.
NC
L.
Lo
Y2•
Y27
Vl1
L3
NC
NC
Y,.
Y'3
Y'2
L,
GND
X3,
X,.
X••
X2•
Xs
X23
X.
X3
X,
NC
Y3,
Y,.
Y.s
CSL
NC
X,.
X'3
X27
X'D
X2•
X22
X.O
X,.
X2
X,.
NC
NC
Y30
GND
X30
X2S
X,.
Xl1
X.
X••
X7
Xs
X.,
X.
X'S
X17
Xo
Vss
144-PIN PGA
(PIN GRID ARRAY)
TOP VIEW
4-74
DSP72265-003
FEATURES:
performance First-In, First-Out memories organized 64 words
by 5 bits. The IDT72403 and 1DT72404 also have an Output
Enable (OE) pin. The FIFOs accept 4-bit or 5-bit data at the data
input (D Ir D 3,4)' The stored data stack up on a first-in, first-out
basis.
It Shift Out (SO) signal causes the data at the next to last
word to shift to the output and all other data shifts down one
location in the stack. The Input Ready (IR) signal acts like a flag
to indicate when the input is ready for new data (IR = HIGH), or
to signal when the FIFO is full (IR = LOW). The Input Ready
signal can also be used to cascade multiple devices together.
The Output Ready (OR) signal is a flag to indicate that the
output contains valid data (OR = HIGH), or to indicate that the
FIFO is empty (OR = LOW). The Output Ready signal can also
be used to cascade multiple devices together.
Width expansion is accomplished by logically AND-ing the
Input Ready (IR) and Output Ready (OR) signals to form
composite signals.
Depth expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The Input
Ready pin of the receiving device is connected to the Shift Out
pin of the sending device, and the Output Ready pin of the
sending device is connected to the Shift In pin of the receiving
device.
Reading and writing operations are completely asynchronous, allowing tre FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
25MHz speed makes these FI FOs ideal for high-speed communication and controller applications.
• First-In, First-Out dual-port memory
• 64 x 4 organization (IDT72401/IDT72403)
64 x 5 organization (IDT72402/IDT72404)
• Low-power consumption
-Commercial - Active: 375mW
-Military - Active: 450mW
• Maximum shift rate
-15MHz (IDT72401/IDT72402)
-25MHz (IDT72403/IDT72404)
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• IDT72401/02 pin and functionally compatible with
MMI67401/02
•
•
•
•
•
IDT72403/04 have Output Enable pin to enable output data
High-speed data communications applications
High-performance CEMOS'· technology
Available in DIP and LCC
Military product available 100% screened to MIL-STD-883,
Class B
DESCRIPTION:
The IDT72401 and IDT72403 are asynchronous, high-performance First-In, First-Out memories organized 64 words by 4
bits, The IDT72402 and IDT72404 are asynchronous, high-
FUNCTIONAL BLOCK DIAGRAM
SI
WRITE POINTER
IR
WRITE MULTIPLEXER
OUTPUT
ENABLE
(OE) (IDT72403 AND
IDT72404)
0 ..3
MEMORY
ARRAY
D_
(IDT72402
AND IDT72404)
DATAOUT
Q_ (IDT72402 AND
IDT72404)
MASTER
RESET
READ MULTIPLEXER
READ POINTER
SO
OR
DSP72401-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
4-75
II
CMOS PARALLEL FIRST-IN/FIRST-OUT FIFO (64 x 4-BIT AND 64 x 5-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT72401
IDT72403
IDT72402
IDT72404
NC/OE(2)
NC/OEI')
Vee
so
IR
IR
SI
Do
SI
OR
Do
aD
a,
a2
a3
a.
0,
0,
O2
03
O2
0
3
D.
GND
GND
MIl
DSP72401-002
DSP72401-()()3
DIP
TOP VIEW
DIP
TOP VIEW
~
z $zJl~
~
~$~Jl~
UUIIULJ
2 L,J 20 ~:[:
0
II I I
LJ L.J
,LJ,
II II
I I LJ
U 20
NC
SI
::Jl
17(:
OR
Do
:J5
0,
16C:
:J6
16[:
15[:
14 r -
aD
a,
a2
0,
O2
NC
O2
:]7
-,8
15[":'
SI
':Jl
Do
:J5
_0
9
10 11 12
13L..-
03
rlf1r1r1fl
Q§lld'~
_0
,
2
19 r 1S L -
1
17(:
14,--
9
10 11 12
13'--
I
fl/
r, r,
II
I
r,
r'"'
11'1
QW§lId'~
CJ
CJ
DSP72401-Q04
DSP72401-005
LCC
TOP VIEW
LCC
TOP VIEW
NOTE:
,. Pin': NC - No Connection IDT72401
OE - IDT72403
2.
Pin 1: NC -
OR
ao
a,
a2
a.
No Connection IDT72402
OE - IDT72404
4-76
FEATURES:
DESCRIPTION:
• First-In, First-Out dual-port memory
The IDT72413 is a 64 x 5, high-speed First-In, First-Out (FIFO)
that loads and empties data on a first-in, first-out basis. It is
cascadable in both word depth and/or bit width.
The FIFO has a Half-full flag, which signals when it has 32 or
more words in memory. The Almost Full/Empty flag is active
when there are 56 or more words in memory, or when there are 8
or less words in memory.
The IDT72413 is pin and functionally compatible to the
MM167413. It operates at a shift rate of 35M Hz. This makes it ideal
for use in high-speed data buffering applications. The IDT72413
can be used as a rate buffer, between two digital systems of
varying data rates, in high-speed tape drivers, hard disk
controllers, data communications controllers and graphics
controllers.
The IDT72413 is fabricated using IDT's high-performance
CEMOS process. This process maintains the speed and high
output drive capability of TTL circuits in low-power CMOS.
• 64 x 5 organization
• Low-power consumption
-Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through
time-35MHz
•
•
•
•
•
•
•
•
•
Asynchronous and simultaneous read and write
Cascadable by both word depth and/or bit width
Half-full and Almost-full/Empty status flags
1DT72413 is pin and functionally compatible with MMI67413
High-speed data communications applications
Bidirectional and rate buffer applications
High-performance CEMOS'· technology
Available in DIP and LCC
Military product available, 100% screened to MIL-STD-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
OE
II
Vee
AF/E
HF
IR
OR
81
Do
80
.0 0
0,
0,
D_
O_
03
03
D.
GND
O.
MR
DSP72413-002
DIP
TOP VIEW
DSP72413-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986lntegrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
4-77
ORDER PART
NUMBER
IOT7201lA35P
SPEED
(ns)
ICC (MAX.)
35
100
(rnA)
PACKAGE
TYPE
OPER.
TEMP.
P28
Com'l.
I0T7201 lA35J
J32
IOT7201 lA350
IOT7201 lA35l
10T7201 lA400B
40
120
I0T7201 lA40lB
I0T7201 lA50P
10T7201SA65P
80
80
P28
Com'l.
IOT7201SA650
028-1
028-1
P28
l32
10T7201SA650B
Mil.
100
I0T7201SA56lB
Com'l.
IOT7201SA80P
028-1
80
80
P28
J32
028-1
1DT7201SA800
028-1
l32
10T7201 SA80l
028-1
P28
100
10T7201SA80LB
Com'l.
10T7201SA120P
028-1
120
80
P28
J32
10T7201SA120J
J32
10T7201 lA650
028-1
10T7201 SA 1200
028-1
IOT7201 lA65l
l32
I0T7201 SA120L
100
I0T7201 lA65lB
1DT7201 lA80P
028-1
80
80
P28
J32
IOT7201 lA800
I0T7201 lA80l
I0T7201 lA800B
100
I0T7201 lA80lB
10T7201 L35P
80
028-1
35
100
P28
J32
028-1
10T7201 L350
028-1
l32
10T7201l35L
028-1
Mil.
1DT7201 l400B
P28
10T7201 l50P
120
028-1
50
80
P28
J32
1DT7201 L50J
J32
10T7201lA1200
028-1
1DT7201 l500
028-1
I0T7201 lA 120l
l32
1DT7201 L50l
100
10T7201 LA 120lB
IOT7201 SA35P
028-1
Mil.
35
100
P28
100
10T7201L65P
028-1
65
80
P28
10T7201SA35J
J32
IOT7201 l65J
J32
I0T7201 SA350
028-1
IOT7201l650
028-1
I0T7201 SA35l
l32
I0T7201 l65l
I0T7201 SA400B
40
120
I0T7201SA40lB
IDT7201 SA50P
028-1
50
80
P28
j32
I0T7201 SA500
IOT7201 SA50l
IDT7201 SA50lB
100
100
IOT7201l65lB
Com' I.
I0T7201 L80P
028-1
80
80
P28
J32
02~-1
IOT7201L800
028-1
L32
10T7201 L80L
Mil.
IDT7201l800B
L32
10T7201 l80LB
4-78
Mil.
l32
10T7201l8OJ
028-1
Com' I.
l32
10T7201l650B
l32
I0T7201 SA50J
10T7201 SA500B
Mil.
Mil.
l32
IOT7201 l50LB
Com'l.
Com'l.
L32
10T7201L500B
l32
Mil.
l32
IOT7201lA120J
I0T7201LA1200B
Com'l.
L32
40
1DT7201 l40lB
Com'l.
Mil.
l32
I0T7201 l35J
l32
120
100
10T7201SA120LB
Com'l.
Com'l.
l32
1DT7201SA1200B
l32
1DT7201 lA80J
10T7201lA120P
Mil.
Mil.
l32
IOT7201 lA65J
1DT7201 lA650B
Com' I.
l32
IOT7201SA800B
Mil.
Mil.
l32
1DT7201 SA80J
l32
65
OPER.
TEMP.
10T7201SA65l
IOT7201 lA50l
I0T7201 lA50lB
80
PACKAGE
TYPE
l32
I0T7201 lA500
100
65
(rnA)
028-1
J32
IDT7201 lA500B
Icc (MAX.)
J32
l32
50
SPEED
(ns)
IOT720i SA65J
I0T7201 lA50J
I0T7201 lA65P
ORDER PART
NUMBER
Com'l.
L32
100
028-1
l32
Mil.
ORDER PART
NUMBER
I 0T7201 L 120P
SPEED
(ns)
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
120
80
P28
Com'l.
ORDER PART
NUMBER
I DT7202LA65P
SPEED
(ns)
IcclMAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
65
80
P28
Com'l.
10T7201 L 120J
J32
I DT7202LA65J
J32
IOT7201 L 1200
028-1
I DT7202LA65D
D28-1
I 0T7201 L 120L
L32
I DT7202LA65L
I OT7201 L 1200B
100
I OT7201 L 120LB
IOT7201S35P
028-1
35
100
P28
J32
I 0T7201 S350
I OT7201 S35L
40
120
I OT7201 S40LB
I OT7201 S50P
I DT7202LA65LB
IDT7202LA80P
Com'l.
80
D28-1
80
80
P28
J32
028-1
IDT7202LA80D
D28-1
L32
IDT7202LA80L
028-1
P28
100
I DT7202LA 120P
D28-1
120
80
P28
I OT7201 S50J
J32
I 0T7202LA 120J
J32
I 0T7201S500
028-1
I DT7202LA 120D
D28-1
I OT7201 S50L
L32
I DT7202LA 120L
I OT7201 S500B
100
I OT7201 S50LB
10T7201S65P
028-1
65
80
P28
IDT7202LA120LB
I 0T7201 S65LB
80
100
P28
IDT7202SA35D
D28-1
L32
IDT7202SA35L
028-1
1DT7202SA40DB
Mil.
P28
IDT7202SA50P
Com'l.
120
D28-1
50
80
P28
J32
IDT7202SA50J
J32
I 0T7201S800
028-1
IDT7202SA50D
D28-1
100
I DT7201 S80LB
I DT7201 S 120P
028-1
I DT7202SA50LB
L32
120
80
P28
100
IDT7202SA50DB
Mil.
I DT7202SA65P
Com'l.
D28-1
65
80
P28
J32
I DT7202SA65J
J32
IDT7201S120D
028-1
IDT7202SA65D
D28-1
IDT7201S120L
L32
I DT7202SA65L
100
IDT7201S120LB
028-1
I DT7202SA80P
I DT7202LA35P
35
100
P28
Com'l.
IDT7202SA80D
I DT7202SA80L
I DT7202LA35L
L32
120
D28-1
50
80
P28
I DT7202LA40LB
IDT7202LA50P
I DT7202SA 120P
Com'l.
IDT7202SA120D
IDT7202SA120L
IDT7202LA50L
L32
I DT7202LA50LB
IDT7202SA120DB
IDT7202SA 120LB
L32
4-79
120
80
P28
D28-1
J32
Com'l.
Mil.
L32
J32
D28-1
Mil.
D28-1
I DT7202SA 120J
IDT7202LA50D
D28-1
P28
L32
IDT7202SA80LB
Mil.
L32
100
80
100
I DT7202SA80DB
IDT7202LA50J
IDT7202LA50DB
80
D28-1
J32
D28-1
Mil.
L32
J32
I DT7202LA35D
40
D28-1
I DT7202SA80J
I DT7202LA35J
IDT7202LA40DB
100
I DT7202SA65LB
L32
Com'l.
L32
IDT7202SA65DB
Mil.
Mil.
L32
I DT7201 S 120J
IDT7201S120DB
Com'l.
L32
I DT7202SA50L
L32
I 0T7201 S800B
Mil.
L32
10T7201 S80J
I OT7201 S80L
Com'l.
L32
40
10T7202SA40LB
L32
80
35
028-1
IOT7201S650
100
IDT7202SA35P
Mil.
L32
J32
10T7201S65L
IOT7201S650B
Com'l.
028-1
I DT7202SA35J
J32
Com'l.
L32
100
IDT7202LA120DB
L32
IOT7201 S65J
I 0T7201 S80P
Mil.
Mil.
L32
I DT7202LA80LB
Com'l.
Com'l.
L32
10T7202LA80DB
Mil.
Mil.
L32
IDT7202LA80J
L32
50
L32
100
IDT7202LA65DB
L32
I OT7201 S35J
I OT7201 S400B
Mil.
Com'l.
L32
100
D28-1
L32
Mil.
II
ORDER PART
NUMBER
IOT7202L35P
SPEED
(n8)
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
35
100
P28
Com'l.
IOT7202L35J
J32
IOT7202L350
IOT7202L35L
IOT7202L400B
40
120
IOT7202L40LB
IOT7202L50P
NUMBER
10T7202S80P
80
80
80
P28
Com'l.
IOT7202S800
028-1
028-1
Mil.
P28
L32
1DT7202S800B
100
1DT7202S80LB
Com'l.
10T7202S120P
028-1
120
80
P28
J32
028-1
I OT7202S 1200
026-1
L32
I OT7202S 120L
028-1
Mil.
P26
100
I OT7202S 120LB
028-1
Com'l.
10T7203L50P
10T7202L650
028-1
10T7203L500
028-1
IOT7203L50C
028-3
L32
100
1DT7202L65LB
10T7202L60P
028-1
Mil.
80
P26
50
120
10T7203L50L
L32
80
150
10T7203L50CB
028-1
J32
028-1
1DT7203L65P
10T7202L80L
L32
10T7203L650
028-1
10T7203L65C
028-3
100
I 0T7202L 120P
028-1
120
80
P28
10T7202L 120J
J32
10T7202L 1200
028-1
10T7202L120L
L32
IDT7202L1200B
100
028-1
100
P28
1DT7202L120LB
1DT7202S35P
10T7203L50LB
Mil.
L32
Mil.
Com' I.
L32
1DT7202S40LB
IOT7202S50P
1DT7203L120P
L32
50
60
P28
Com'l.
10T7203L1200B
IOT7202S50L
L32
10T7203L120CB
100
IOT7202S50LB
10T7202S65P
028-1
1DT7203L 120L
80
P28
10T7203S50P
Com'l.
10T7203S50C
IOT7203S50L
IOT7202S65L
L32
10T7202S65LB
028-1
IOT7203S500B
Mil.
L32
4-80
Mil.
L32
50
120
P28
028-3
J32
028-1
Com'l.
028-3
028-1
IOT7202S650
100
028-1
10T7203S500
10T7202S65J
10T7202S650B
P28
L32
150
10T7203L120LB
Mil.
L32
65
120
028-3
028-1
Mil.
L32
120
10T7203L120C
IOT7202S500
Com'l.
028-3
028-1
J32
IOT7202S500B
028-1
1DT7203L 1200
1DT7202S5OJ
Mil.
L32
150
1DT7203L80LB
Mil.
P28
028-3
IDT7203L80L
10T7203L80CB
028-1
120
IDT7203L80C
028-1
Com'l.
L32
80
028-1
1DT7202S350
120
028-1
10T7203L800
1DT7203L800B
40
P28
028-3
IOT7203L65LB
IOT7203L80P
J32
IOT7202S400B
150
10T7203L65CB
1DT7202S35J
10T7202S35L
120
L32
IOT7203L650B
L32
35
L32
65
10T7203L65L
Com'l.
Mil.
028-3
IOT7202L600
10T7202L80LB
Com'l.
L32
IDT7203L500B
Com'l.
P28
10T7202L6OJ
IOT7202L600B
Mil.
L32
J32
10T7202L65L
Com'l.
L32
IOT7202S1200B
10T7202L65J
10T7202L650B
Mil.
L32
10T7202S120J
L32
65
80
1DT7202S80L
1DT7202L50L
10T7202L50LB
OPER.
TEMP.
L32
1DT7202L500
100
PACKAGE
TYPE
028-1
J32
IOT7202L500B
Icc!MAX.)
(mA)
J32
L32
50
SPEED
(ns)
IOT7202S80J
10T7202L5OJ
10T7202L65P
ORDER PART
Com'l.
L32
150
028-1
IOT7203S50CB
028-3
10T7203S50LB
L32
Mil.
ORDER PART
NUMBER
10T7203S65P
SPEED
(ns)
Icc (MAX.)
(rnA)
65
120
PACKAGE
TYPE
OPER.
TEMP.
P28
Com'l.
ORDER PART
NUMBER
1DT7204S50P
SPEED
(ns)
IcC (MAX.)
(rnA)
50
120
PACKAGE
TYPE
OPER.
TEMP.
P28
Com'l.
IOT7203S650
028-1
IOT7204S500
028-1
10T7203S65C
028·3
10T7204S50C
028-3
10T7203S65L
L32
10T7204S50L
IOT7203S650B
150
Mil.
IOT7203S65LB
10T7204S50CB
L32
80
120
P28
L32
150
IOT7204S500B
028-3
IOT7203S65CB
IOT7203S80P
028-1
028-1
10T7204S50LB
Com'l.
10T7204S65P
L32
65
120
P28
IOT7203S800
028-1
IOT7204S650
028-1
10T7203S80C
028-3
10T7204S65C
028-3
10T7203S80L
L32
10T7204S65L
10T7203S800B
150
IOT7203S80CB
Mil.
120
P28
150
10T7204S65CB
028-1
Com'l.
IOT7204S80P
L32
80
120
P28
10T7203S1200
028-1
10T7204S800
028-1
IDT7203S 120C
028-3
IOT7204S80C
028-3
I OT7203S 120L
L32
IOT7204S80L
10T7203S1200B
150
028-1
Mil.
028-3
10T7204S80CB
I 0T7203S 120LB
L32
10T7204S80LB
IOT7204S120P
IOT7204L50P
50
120
P28
Com'l.
10T7204S120C
IDT7204S120L
10T7204L50L
L32
028-1
IDT7204L50C B
028-3
10T7204L50LB
L32
10T7204L65P
65
120
P28
10T7204L650
028-1
IDT7204L65C
028-3
IDT7204L65L
L32
IOT7204L650B
150
028-1
IOT7204L65CB
028-3
1DT7204L65LB
L32
IOT7204L80P
80
120
P28
IDT7204L800
028-1
IOT7204L80C
028-3
10T7204L80L
150
028·1
10T7204L80CB
028-3
IDT7204L80LB
L32
I OT7204L 120P
120
120
P28
IOT7204L 1200
028-1
I 0T7204L 120C
028-3
I OT7204L 120L
I 0T7204L 1200B
Com'l.
Mil.
028-1
IDT7204L 120CB
028-3
I OT7204L 120LB
L32
L32
IOT72064
Consult Factory
10T72065
Consult Factory
SPEED
30
10T7209L40CB
40
IOT7209L55LB
4-81
064
Mil.
P64
Com'l.
064
068
L68-2
10T7209L45L
I 0T7209L55C B
Com'l
L68-1
45
10T7209L45XC
10T7209L55XCB
P64
068
10T7209L45C
Mil.
OPER.
TEMP.
068
10T7209L40LB
Com'l.
PACKAGE
TYPE
L68-1
IOT7209L40XCB
10T7209L45P
Mil.
064
10T7209L30XC
L32
150
IOT7204S120LB
10T7209L30L
Mil.
028-1
028-3
IOT7209L30P
Com'l.
L32
150
10T7209L30C
Com'!.
P28
120
IOT7204S120CB
ORDER PART
NUMBER
L32
1DT7204L800B
L32
120
IOT7204S1200B
Mil.
Mil.
028-3
028-3
028-1
028-3
150
028-1
028-1
IOT7204L500
10T7204L500B
150
I OT7204S 1200
10T7204L50C
Com'l.
L32
10T7204S800B
IOT7203S12CB
Mil.
028-3
10T7204S65LB
L32
120
Com'l.
L32
IOT7204S650B
028-3
IOT7203S80LB
10T7203S120P
028-1
Mil.
028-3
55
064
068
L68-2
Mil.
ORDER PART
NUMBER
I DT7209L65P
SPEED
45
I DT7209L65C
1DT7209L65XC
IDT7209L65L
I DT7209L75CB
OPER.
TEMP.
P64
Com'l.
ORDER PART
NUMBER
IDT7210L55CB
75
IDT7209L75LB
100
SPEED
55
PACKAGE
TYPE
OPER.
TEMP.
D64
Mil.
D64
IDT7210L55XCB
D68
IDT7210L55LB
L6B-1
IDT7210L55XLB
L6B-2
L6B-2
IDT7209L75XCB
I DT7209L 1OOP
PACKAGE
TYPE
D64
Mil.
D68
IDT7210L55FB
F64
D68
IDT7210L65P
L68-2
I DT721 OL65J
J68
I DT721OL65C
D64
P64
Com'l.
65
P64
I DT7209L1 OOC
D64
I DT721 OL65XC
IDT7209L 100XC
D68
1DT7210L65L
L6B-1
I DT721 OL65XL
L68-2
IDT7209L 100L
IDT7209L 120CB
L68-2
120
IDT7209L 120XCB
Mil.
D68
IDT7209L 120LB
IDT7209L 135P
D64
L68-2
D68
I DT721OL65F
F64
I DT721 OL65CB
D64
1DT7210L65XCB
D6B
I DT721 OL65LB
L68-1
IDT7209L 135C
D64
I DT721 OL65XLB
L6B-2
IDT7209L 135XC
D68
I DT721 OL65FB
135
I DT7209L 135L
1DT7209L 170CB
Com'l.
L68-2
170
IDT7209L 170XCB
D64
I DT721 OL 75P
L68-2
35
P64
Com'l.
P64
IDT7210L75C
D64
IDT7210L75XC
D6B
I DT721 OL 75L
L6B-1
I DT721 OL 75XL
L6B-2
J68
IDT7210L75F
F64
IDT7210L35C
D64
IDT7210L75CB
D64
IDT7210L35XC
D68
IDT7210L75XCB
D6B
I DT721 OL35F
IDT7210L40CB
L68-1
IDT7210L75LB
L6B-1
L6B-2
IDT7210L75XLB
L68-2
--
IDT7210L35XL
F64
40
IDT7210L40XCB
D64
IDT7210LB5CB
B5
IDT7210LB5XCB
D68
D64
I DT721 OL40LB
L68-1
I DT721 OL85LB
L68-1
L68-2
IDT7210L85XLB
L6B-2
I DT721 OL45P
45
P64
F64
IDT7210L85FB
F64
I DT721OL 100P
Com'l.
100
P64
I DT721 OL45J
J68
IDT7210L 100J
J68
IDT7210L45C
D64
1DT7210L 100c
D64
I DT721 OL45XC
D68
IDT7210L100XC
L68-1
I DT721OL 100L
L6B-1
IDT7210L45XL
L6B-2
1DT721 OL 1OOXL
L6B-2
IDT7210L55P
I DT721OL 100F
F64
55
P64
IDT7210L 120CB
Com'l.
F64
120
D64
I DT721 OL55J
J68
IDT721 OL55C
D64
I DT721OL 120LB
L6B-1
IDT7210L55XC
D68
IDT721 OL 120XLB
L6B-2
IDT7210L55L
L68-1
IDT7210L55XL
L68-2
I DT721 OL55F
IDT7210L 120XCB
I DT721 OL 120FB
F64
4-82
Com' I.
D68
I DT721 OL45L
I DT721OL45F
Mil.
D68
IDT7210L40XLB
IDT7210L40FB
Mil.
F64
1DT7210L75FB
Mil.
Com'l.
J6B
I DT721 OL35J
IDT7210L35L
Mil.
F64
75
I DT721OL75J
Mil.
D68
I DT7209L 170LB
IDT7210L35P
P64
Com'l.
D68
F64
Mil.
ORDER PART
NUMBER
IDT7210L 165P
SPEED
165
PACKAGE
TYPE
OPER,
TEMP.
P64
Com' I.
ORDER PART
NUMBER
IDT7212L 140CB
SPEED
PACKAGE
TYPE
OPER,
TEMP.
140
D64
Mil.
IDT7210L 165J
J68
IDT7212L 140XCB
IDT7210L 165C
D64
I DT7212L 140LB
L68-1
I DT721 OL 165XC
D68
I DT7212L140FB
F64
IDT721 OL 165L
L68-1
IDT7210L 165XL
L68-2
I DT7213L30P
F64
IDT7213L30C
IDT7210L 165F
IDT7210L200CB
200
D64
Mil.
D68
30
P64
Com'l.
D64
IDT7213L30XC
D68
----~
IDT7210L200XCB
D68
I DT 7213L30L
IDT7210L200LB
L68-1
IDT7213L30F
IDT7210L200XLB
L68-2
IDT7213L40CB
I DT721 OL200FB
F64
L68-1
F64
40
IDT7213L40XCB
Consult Factory
IDT721 04
L68-1
IDT7213L40FB
IDT7213L45P
Consult Factory
F64
45
I DT7213L45C
30
P64
Com'l.
D64
IDT7213L45F
I DT7212L30XC
D68
IDT7213L55CB
I DT7212L30L
L68-1
I DT7212L30F
I DT7212L40CB
IDT7212L40XCB
IDT7212L40LB
IDT7212L40FB
IDT7212L45P
I DT7212L45XC
I DT7212L45L
I DT7213L 70P
L68-1
IDT7213L70C
I DT7212L55LB
IDT7212L55FB
F64
D68
IOT7213L90CB
L68-1
IDT7213L115C
IDT7213L 115F
D68
I DT7213L 140CB
L68-1
IDT7212L90XCB
D64
Mil.
D64
Mil.
D68
L68-1
F64
D68
L68-1
IOT7216L35P
F64
10T7216L35J
I DT7212L 115XC
F64
140
IDT7213L140FB
I DT7212L90FB
IDT7212L 115P
D68
IDT7213L 140LB
I DT7212L90LB
IDT7212L 115C
Com'l.
L68-1
IDT7213L 140XCB
F64
90
P64
D64
IDT7213L 115L
D64
I DT7212L90CB
F64
115
I DT7213L 115XC
Com'l.
Mil.
L68-1
I DT7213L90FB
IDT7213L 115P
064
068
IDT7213L90LB
Mil.
D68
P64
90
IDT7213L90XCB
I DT7212L 70XC
I DT7212L 70F
D68
IDT7213L70F
D64
Com'!.
D64
D64
IDT7212L70C
I DT7212L 70L
P64
L68-1
F64
70
F64
70
IDT7213L70XC
Com'l.
Mil.
L68-1
IDT7213L70L
P64
F64
55
I DT7212L55XCB
IDT7212L70P
D68
D64
D68
IDT7213L55FB
L68-1
I DT7212L45F
F64
55
IDT7213L55LB
Mil.
F64
45
I DT7212L45C
I DT7212L55CB
D64
D68
IDT7213L55XCB
F64
40
Com'l.
L68-1
I DT7213L45L
IDT7212L30C
P64
D64
I DT7213L45XC
IDT7212L30P
Mil.
D68
I DT7213L40LB
IDT72103
D64
115
P64
Com'l.
35
P64
J68
IDT7216L35C
D64
D64
I DT7216L35XC
D68
D68
I DT7216L35G
G68
IDT7212L 115L
L68-1
I DT7216L35L
L68-1
IDT7212L 115F
F64
I DT7216L35XL
L68-2
IDT7216L35F
4-83
F64
Com'l.
II
ORDER PART
NUMBER
I DT7216L40CB
SPEED
PACKAGE
TYPE
OPER.
TEMP.
40
D64
Mil.
IDT7216L40XCB
ORDER PART
NUMBER
IDT7216L75CB
SPEED
PACKAGE
TYPE
OPER.
TEMP.
75
D64
Mil.
068
068
IDT7216L75XCB
1DT7216L40G B
G68
IDT7216L75GB
G68
IDT7216L40LB
L68-1
IDT7216L75LB
L68-1
IDT7216L40XLB
L68-2
IDT7216L75XLB
L68-2
IDT7216L40FB
IDT7216L45P
F64
45
P64
F64
IDT7216L75FB
IDT7216L90P
Com' I.
90
P64
IDT7216L45J
J68
IDT7216L90J
J68
IDT7216L45C
064
IDT7216L90C
064
IDT7216L45XC
068
IDT7216L90XC
068
IDT7216L45G
G68
IDT7216L90G
G68
IDT7216L45L
L68-1
IDT7216L90L
L68-1
IDT7216L45XL
L68-2
IDT7216L90XL
L68-2
IDT7216L90F
F64
I DT7216L90CB
D64
J68
I DT7216L90XCB
068
IDT7216L55C
064
IDT7216L90GB
G68
IDT7216L55XC
D68
IDT7216L90LB
L68-1
IDT7216L90XLB
L68-2
I DT7216L45F
I DT7216L55P
F64
55
I DT7216L55J
P64
Com'l.
IDT7216L55G
G68
IDT7216L55L
L68-1
1DT7216L90FB
IDT7216L55XL
L68-2
IDT7216L120CB
IDT7216L120XCB
064
IDT7216L55CB
064
IDT7216L 120GB
G68
IDT7216L55XCB
068
IDT7216L120LB
L68-1
IDT7216L55GB
G68
IDT7216L120XLB
L68-2
I DT7216L55LB
L68-1
I DT7216L 120FB
IDT7216L55XLB
L68-2
I DT7216L 140P
F64
I DT7216L 140J
J68
IDT7216L140C
064
IDT7216L65P
65
P64
Com'l.
F64
140
P64
IDT7216L65J
J68
IDT7216L140XC
068
IDT7216L65C
064
IDT7216L140G
G68
IDT7216L65XC
068
IDT7216L140L
L68-1
IDT7216L65G
G68
1DT7216L 140XL
L68-2
I DT7216L65L
L68-1
IDT7216L 140F
I DT7216L65XL
L68-2
IDT7216L 185CB
IDT7216L65F
F64
IDT7216L65CB
064
IDT7216L65XCB
068
IDT7216L65GB
G68
IDT7216L65LB
L68-1
IDT7216L65XLB
L68-2
I DT7216L65FB
IDT7216L75P
P64
1DT7216L 185GB
G68
IDT7216L 185LB
L68-1
IDT7216L185XLB
L68-2
IDT7217L35P
Com'l.
064
F64
35
P64
IDT7217L35J
J68
D64
IDT7216L75J
J68
IDT7217L35C
IDT7216L75C
064
IDT7217L35XC
068
IDT7216L75XC
068
I DT7217L35G
G68
IDT7216L75G
G68
I DT7217L35L
L68-1
IDT7216L75L
L68-1
IDT7217L35XL
L68-2
IDT7216L75XL
L68-2
IDT7217L35F
IDT7216L75F
F64
4-84
Mil.
068
1DT7216L185FB
F64
75
Com'l.
F64
185
IDT7216L 185XCB
Mil.
Mil.
068
F64
IDT7216L55FB
Mil.
F64
120
IDT7216L55F
Mil.
Com' I.
F64
Com'l.
ORDER PART
NUMBER
IDT7217L40CB
SPEED
PACKAGE
TYPE
OPER.
TEMP.
40
D64
Mil.
IDT7217L40XCB
ORDER PART
NUMBER
D68
PACKAGE
TYPE
OPER.
TEMP.
I DT7217L 75CB
D64
Mil.
IDT7217L 75XCB
D68
SPEED
IDT7217L40GB
G68
IDT7217L75GB
G68
IDT7217L40LB
L68-1
IDT7217L 75LB
L68-1
IDT7217L40XLB
L68-2
I DT7217L 75XLB
L68-2
I DT7217L40FB
I DT7217L45P
IDT7217L 75FB
F64
45
P64
Com'l.
I DT7217L90P
F64
90
IDT7217L45J
J68
IDT7217L45C
D64
I DT7217L90C
D64
IDT7217L45XC
D68
IDT7217L90XC
D68
IDT7217L45G
G68
IDT7217L90G
G68
I DT7217L45L
L68-1
IDT7217L90L
L68-1
IDT7217L45XL
L68-2
IDT7217L90XL
L68-2
IDT7217L45F
1DT7217L90J
P64
IDT7217L90F
F64
IDT7217L90CB
D64
J68
IDT7217L90XCB
D68
IDT7217L55C
D64
IDT7217L90GB
G68
IDT7217L55XC
D68
IDT7217L90LB
L68-1
IDT7217L55G
G68
IDT7217L90XLB
L68-2
I DT7217L55L
L68-1
IDT7217L90FB
I DT7217L55XL
L68-2
IDT7217L120CB
IDT7217L55P
F64
55
I DT7217L55J
P64
Com'l.
D64
F64
I DT7217L55CB
D64
IDT7217L 120GB
G68
IDT7217L55XCB
D68
IDT7217L 120LB
L68-1
1DT7217L55GB
G68
1DT7217L 120XLB
L68-2
I DT7217L55LB
L68-1
IDT7217L 120FB
IDT7217L55XLB
L68-2
I DT7217L 140P
F64
IDT7217L 140J
J68
IDT7217L 140C
D64
1DT7217L55FB
IDT7217L65P
65
P64
F64
140
P64
IDT7217L65J
J68
IDT7217L 140XC
D68
IDT7217L65C
D64
IDT7217L 140G
G68
IDT7217L65XC
D68
IDT7217L 140L
L68-1
1DT7217L65G
G68
IDT7217L 140XL
L68-2
1DT7217L65L
L68-1
1DT7217L 140F
1DT7217L65XL
L68-2
IDT7217L 185CB
IDT7217L65F
F64
IDT7217L 185XCB
D64
D68
D64
IDT7217L 185GB
G68
IDT7217L65XCB
D68
IDT7217L185LB
L68-1
IDT7217L65GB
G68
I DT7217L 185XLB
L68-2
IDT7217L65LB
L68-1
I DT7217L65XLB
L68-2
IDT7217L65FB
IDT7217L75P
F64
75
P64
IDT7217L75J
J68
IDT7217L75C
D64
IDT7217L75XC
D68
IDT7217L75G
G68
IDT7217L75L
L68-1
IDT7217L75XL
L68-2
IDT7217L75F
I DT7217L 185FB
F64
IDT72264
Consult Factory
IDT72265
Consult Factory
IDT72401
Consult Factory
IDT72402
Consult Factory
IDT72403
Consult Factory
Com' I.
F64
4-85
Com'l.
F64
185
I DT7217L65CB
Mil.
Mil.
D68
IDT7217L 120XCB
Com'l.
Mil.
F64
120
I DT7217L55F
Mil.
Com·1.
J68
Mil.
ORDER PART
NUMBER
SPEED
IDT72404
PACKAGE
TYPE
ORDER PART
NUMBER
OPER,
TEMP.
Consult Factory
I DT7243L 75P
SPEED
PACKAGE
TYPE
OPER,
TEMP.
75
P64
Com'l.
I DT7243L 75J
IDT72413
IDT7243L35P
Consult Factory
J68
I DT7243L 75C
064
I DT7243L 75XC
068
I DT7243L 75L
L68-1
IDT7243L35J
J68
IDT7243L75XL
L68-2
IDT7243L35C
064
I DT7243L 75F
F64
IDT7243L35XC
D68
I DT7243L 75CB
D64
068
35
P64
Com'l.
IDT7243L35L
L68-1
I DT7243L 75XCB
IDT7243L35XL
L68-2
I DT7243L 75LB
L68-1
I DT7243L 75XLB
L68-2
IDT7243L35F
IDT7243L40CB
F64
40
IDT7243L40XCB
064
Mil.
IDT7243L75FB
IDT7243L85CB
068
F64
85
L68-1
IDT7243L85XCB
IDT7243L40XLB
L68-2
IDT7243L85LB
L68-1
IDT7243L85XLB
L68-2
IDT7243L45P
F64
45
P64
Com'l.
068
F64
IDT7243L85FB
IDT7243L45J
J68
IDT7243L 100P
IDT7243L45C
064
IDT7243L 100J
J68
068
I DT7243L 100C
064
IDT7243L45XC
100
L68-1
I DT7243L 1OOXC
IDT7243L45XL
L68-2
I DT7243L 1OOL
L68-1
IDT7243L 100XL
L68-2
I DT7243L55P
F64
55
P64
Com'l.
068
I DT7243L 1OOF
IDT7243L55J
J68
I DT7243L 120CB
IDT7243L55C
064
I DT7243L 120XCB
068
F64
120
068
I DT7243L 120LB
L68-1
L68-1
I DT7243L 120XLB
L68-2
IDT7243L55XL
L68-2
I DT7243L 120FB
IDT7243L55F
IDT7243L55CB
I DT7243L 165P
F64
55
IDT7243L55XCB
064
Mil.
068
F64
165
IDT7243L 165J
J68
IDT7243L 165C
064
068
L68-1
I DT7243L 165XC
IDT7243L55XLB
L68-2
IDT7243L 165L
L68-1
IDT7243L165XL
L68-2
IDT7243L65P
F64
65
P64
Com'l.
IDT7243L65J
J68
IDT7243L200CB
064
IDT7243L200XCB
068
200
064
068
IDT7243L200LB
L68-1
1DT7243L65L
L68-1
IDT7243L200XLB
L68-2
IDT7243L65XL
L68-2
IDT7243L200FB
1DT7243L65XC
IDT7243L65F
F64
IDT7243L65CB
064
IDT7243L65XCB
068
IDT7243L65LB
L68-1
IDT7243L65XLB
L68-2
IDT7243L65FB
Mil.
F64
4-86
,
F64
I DT7243L 165F
IDT7243L65C
Com'l.
P64
1DT7243L55LB
I DT7243L55FB
Mil.
064
IDT7243L55L
IDT7243L55XC
Com' I.
P64
IDT7243L45L
IDT7243L45F
Mil.
064
IDT7243L40LB
IDT7243L40FB
Mil.
F64
Mil.
Integrated
Device
Technology
Logic
LOGIC PRODUCTS
TABLE OF CONTENTS
PAGE
CONTENTS
Logic
IDT39C821
IDT39C822
IDT39C823
IDT39C824
IDT39C825
IDT39C826
IDT39C841
IDT39C842
IDT39C843
IDT39C844
IDT39C845
IDT39C846
IDT39C861
IDT39C862
IDT39C863
IDT39C864
IDT49C818
IDT54/74AHCT138
IDT54/74AHCT139
IDT54J74AHCT161/163
IDT54J74AHCT182
IDT54/74AHCT191
IDT54/74AHCT193
IDT54J74AHCT240
IDT54/74AHCT244
IDT54/74AHCT245
IDT54/74AHCT273
IDT54/74AHCT299
IDT54/74AHCT373
IDT54/74AHCT374
IDT54/74AHCT377
IDT54/74AHCT521
IDT54/74AHCT533
IDT54/74AHCT534
IDT54/74AHCT573
IDT54J74AHCT574
IDT54/74AHCT640
IDT54/74AHCT645
IDT54/74FCT138/A
IDT54J74FCT139/A
IDT54/74FCT161/163/A
IDT54J74FCT182/A
IDT54/74FCT1911A
IDT54/74FCT193/A
IDT54/74FCT240/A
IDT54J74FCT244/A
IDT54/74FCT245/A
IDT54/74FCT273/A
IDT54/74FCT299/A
10-Bit Non-inverting Register .................................................
1D-Bit Inverting Register ......................................................
9-Bit Non-inverting Register ..................................................
9-Bit Inverting Register .......................................................
8-Bit Non-inverting Register ..................................................
8-Bit Inverting Register .......................................................
10-Bit Non-inverting Latch ....................................................
10-Bit Inverting Latch ........................................................
9-Bit Non-inverting Latch .....................................................
9-Bit Inverting Latch .........................................................
8-Bit Non-inverting Latch .....................................................
8-Bit Inverting Latch .........................................................
10-Bit Non-inverting Transceiver ................ , ..............................
10-Bit Inverting Transceiver ...................................................
9-Bit Non-inverting Transceiver ................... , ............................
9-Bit Inverting Transceiver ....................................................
Octal Register with SPCTM ...... , ..............................................
1-of-8 Decoder ..............................................................
Dual 1-of-4 Decoder .........................................................
Synchronous Binary Counter .................................................
Carry Lookahead Generator ..................................................
Up/Down Binary Counter .....................................................
Up/Down Binary Counter .....................................................
Octal Buffer .................................................................
Octal Buffer .................................................................
Octal Bidirectional Transceiver ................................................
Octal D Flip-Flop ............................................................
Universal Shift Register .......................................................
Octal Transparent Latch ......................................................
Octal D Flip-Flop ............................................................
Octal D Flip-Flop ............................................................
8-Bit Comparator ............................................................
Octal Transparent Latch ......................................................
Octal D Flip-Flop ............................................................
Octal Transparent Latch ......................................................
Octal D Register ............................................. , ...............
Octal Bidirectional Transceiver ................................................
Octal Bidirectional Transceiver ................................................
1-of-8 Decoder ..............................................................
Dual 1-of-4 Decoder .........................................................
Synchronous Binary Counter .................................................
Carry Lookahead Generator ..................................................
Up/Down Binary Counter .....................................................
Up/Down Binary Counter .....................................................
Octal Buffer .................................................................
Octal Buffer .................................................................
Octal Bidirectional Transceiver ................................................
Octal D Flip-Flop ............................................................
Octal Universal Shift Register .................................................
5-1
5-1
5-1
5-1
5-1
5-1
5-7
5-7
5-7
5-7
5-7
5-7
5-13
5-13
5-13
5-13
5-18
5-20
5-24
5-27
5-31
5-35
5-39
5-43
5-47
5-50
5-53
5-57
5-61
5-65
5-69
5-73
5-76
5-80
5-84
5-88
5-92
5-95
5-98
5-102
5-105
5-109
5-113
5-117
5-121
5-125
5-129
5-133
5-137
LOGIC PRODUCTS
TABLE OF CONTENTS (CONT'D)
CONTENTS
Logic (CONT'D.)
IDT54/74FCT373/A
Octal Transparent Latch ......................................................
IDT54/74FCT374/A
Octal D Flip-Flop ............................................................
IDT54/74FCT377/A
Octal D Flip-Flop ............................................................
IDT54/74FCT521/A
8-Bit Comparator ............................................................
IDT54/74FCT533/A
Octal Transparent Latch ......................................................
IDT54/74FCT534/A
Octal D Flip-Flop ............................................................
IDT54/74FCT573/A
Octal Transparent Latch ......................................................
IDT54174FCT574/A
Octal D Register .............................................................
IDT54/74FCT640/A
Octal Bidirectional Transceiver ................................................
IDT54/74FCT645/A
Octal Bidirectional Transceiver ................................................
IDT54/74FCT821 B
10-Bit Non-inverting Register .................................................
IDT54/74FCT822B
10-Bit Inverting Register ......................................................
9-Bit Non-inverting Register ..................................................
IDT54/74FCT823B
IDT54/74FCT824B
9-Bit Inverting Register .......................................................
IDT54/74FCT825B
8-Bit Non-inverting Register ..................................................
IDT54/74FCT826B
8-Bit Inverting Register .......................................................
IDT54/74FCT841B
10-Bit Non-inverting Latch ....................................................
IDT54/74FCT842B
1D-Bit Inverting Latch ........................................................
IDT54/74FCT843B
9-Bit Non-inverting Latch .....................................................
IDT54174FCT844B
9-Bit Inverting Latch .........................................................
IDT54/74FCT845B
B-Bit Non-inverting Latch .....................................................
IDT54/74FCT846B
8-Bit Inverting Latch .........................................................
IDT54/74FCT861B
10-Bit Non-inverting Transceiver ...............................................
IDT54/74FCT862B
10-Bit Inverting Transceiver ...................................................
IDT54/74FCT863B
9-Bit Non-inverting Transceiver ................................................
IDT54/74FCT864B
9-Bit Inverting Transceiver ....................................................
IDT54/74AHCT/FCT Family Test Circuits and Waveforms ................................................
Ordering Information .................................................................•..............
PAGE
5-141
5-145
5-149
5-153
5-156
5-160
5-164
5-168
5-172
5-176
5-180
5-180
5-180
5-180
5-180
5-180
5-186
5-186
5-186
5-186
5-186
5-186
5-192
5-192
5-192
5-192
5-197
5-198
FEATURES:
DESCRIPTION:
• Equivalent to AM D's Am29821-26 Bipolar Registers in
pinouVfunction, speeds and output drive over full
temperature and voltage supply extremes
• High-speed parallel registers with positive edge-triggered
D-type flip-flops
-Non-inverting Cp-y tpD ~ 7.5ns typo
-Inverting CP-Y tpD ~ 7.5ns typo
The IDT39C800 Series is built using advanced CEMOS··, a
dual metal CMOS technology.
The IDT39C820 Series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers
and provide extra data width for wider address/data paths or
bu!!es carrying parity. The IDT39C821 and IDT39C822 are
buffered, 10-bit wide versions of the popular '374/'534 functions.
The I DT39C823 and I DT39C824 are 9-bit wide buffered registers
with Clock Enable (EN) and Clear (ClR) - ideal for parity bus
interfacing in high-performance microprogrammed systems.
The IDT39C825 and I DT39C826 are 8-bit buffered registers with
all the '823/4 controls plus multiple enables (OE" OE2, OE3 ) to
allow multiuser control of the interface, e.g., CS, DMA, and
RD/WR. They are ideal for use as an output port requiring high
10l/loH ·
cAli of the IDT39C800 high-performance interface family are
designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes, and all outputs are designed for lowcapacitance bus loading in the high impedance state.
• Buffered common Clock Enable (EN) and asynchronous
Clear input (ClR)
• 48mA commerciallQL, 32mA military 10l
• 200mV (typ.) hysteresis on clock INPUT
• Clamp diodes on all inputs for ringing suppression
• ESD protection 5000V (typ.) - Mll-STD-883 Category B
• low inpuVoutput capacitance
-6pF inputs (typ.)
-8pF outputs (typ.)
• CMOS power levels (5iJ.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AMD's Bipolar
Am29800 series (5iJ.A max.)
• 100% product assurance screening to Mll-STD-883, Class B
is available.
FUNCTIONAL BLOCK DIAGRAM
CLOCK
ENABLE
Do
05
ON-l
CE
CLEAR
CDR~~----+---~--~+---~---+4---~---++---~--~+---~--~+---~
CLOCK
CP -('*----~------~--------~------_4~------~~------~
OUTPUT
ENABLE
OE
__________
______
______
______
______
______..
~~
~~
~-+
~-+
~~
~~
Vs
Vo
Vn -l
Vn
SSD39C621-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Cl19861ntegrated Device Technology, Inc.
Printed in the U.S.A.
5-1
10T39C821-26 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTIi:RS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN COI'IIFIGURATIONS
IDT39C821/IDT39C82~
OE
LOGIC SYMBOL$
10-BIT REGISTERS
u
o8~~:!;1~>
Vee
do
Vo
01
V1
02
V2
03
V3
04
V4
Os
Vs
06
V6
07
Y7
Oa
Va
Vg
09
GNO
,
"
LJ LJ
02
:J;
3
tj!!~~J~~r_
L,J
25'"'-,
03
24[:
V2
V3
04
NC
V4
NC
Ps
06
V6
07
O~O
Vs
-..1
19r--
12 13 14 15 16 17 181.,,.,
,., ,., ,., r, ,., ,..,
II
CD
CP
Q
II
II
II
II
II
Y7
I
Q
CP
10
V
I
I
CP
OE
II
"'CUlL ~.p
Z Z U
Q
"
DIP
TOP VIEW
LCC
TQPVIEW
SSD39C821-005
SSD39C821·002
SSD39C82HX)6
IDT39C823/IDT39C824 9-BIT REGISTERS
OE
Vee
Do
Vo
01
V1
02
V2
03
04
V3
Os
Vs
06
Y7
Va
CLR
II
2
3
IIII
II
II
I I 28 27 26 ... L,J
25""-
Y:!
24[:
V3
:J6
04 :J7
NC :J8
05 :J9
07
-,11
_..I
12
o +0
V4
22[: NC
23[:
06 :JlO
13 14 15 16 17
rlnr1r1r1rl
EN
CP
GNO
-, 4
-"5
03
Vs
Oa
,
"
LJ l.J LJ I I L .. LJ LJ
02
V4
07
u
Q8~~:!;1*,>
Sls~~tsli5
CP
21[:
Vs
20[:
Vs
CP
19,-
Y7
EN
rr--
EN CLRQ
9
v
r
CUi
~
OE
U"
DIP
TOP VIEW
LCC
TOP VIEW
SS039C821-007
SSD39C821-003
SS039C821·008
IDT39C82S/IDT39C826 8-BIT REGISTERS
OE1
Vee
OE2
OE3
0
I
DO
Vo
01
V1
01
02
V2
02 :]8
03
Va
04
V4
Os
Vs
06
V6
07
CLR
Y7
GNO
Vo
II
V1
24C: Y:!
03 :J7
NC :J8
~3[:
Ya
CP
NC
EN
CLR
04 :J9
21[:
V4
20[:
Vs
13 14 15 16 17
~:[:
Vs
II
II
II
r, ,., ,., r, ,., r:'1
0IS
u
II
II
U
~ Z
Q
II
II
CLR
22(.:
[Is :JlO
De :J~~
,.,
EN
28r-
251.,-
0
Q
LJ LJ
27
8
8
V
0E1
OE2
0Ea
uILIZ
I:
w
LCC
TOP VIEW
DIP
TOP VIEW
SSD39C821-010
SSD39C821-009
5-2
SSD39C821-004
IDT39C821-26 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
PIN DESCRIPTION
NAME
PRODUCT SELECTOR GUIDE
I
CLR
I
DEVICE
DESCRIPTION
I/O
Dj
10-BIT
9-BIT
8-BIT
IDT39C821
IDT39C823
IDT39C825
IDT39C822
IDT39C824
IDT39C826
The D flip-flop data inputs.
I Noninverting
For both inverting and noninverti!!lLregisters,
when the clear input is LOW and OE is LOW, the
Q j outputs are Law. When the clear input is
HIGH, data can be entered into the register.
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Vi. Vi
a
The register three-state outputs.
EN
I
Clock Enable. When the clock enable is LOW,
data on the D j input is transferred to the Q j
output on the LOW-to-HIGH clock transition.
When the clock enable is HIGH, the Q j outputs
do not change state, regardless of the data or
clock input transitions.
OE
I
Output Control. When the OE input is HIGH, the
Vj 0'!!euts are in the high impedance state. When
the OE input is LOW, the TRUE register data is
present at the Vj outputs.
I Inverting
FUNCTION TABLES
IDT39C821/23/25
INPUTS
IDT39C822/24/26
INTERNAL OUTPUTS
OE CLR EN 0, CP
0,
INTERNAL OUTPUTS
INPUTS
FUNCTION
OE CLR EN 0, CP
FUNCTION
0,
V,
Hi-Z
H
H
X
X
L
L
L
H
I
I
H
L
Z
Z
Hi-Z
Clear
H
L
L
L
X
X
X
X
X
X
L
L
Z
L
Clear
Z
NC
Hold
H
L
H
H
H
H
X
X
X
X
NC
NC
Z
NC
Hold
Z
Z
L
H
Load
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
I
I
I
I
H
L
H
L
Z
Z
H
L
Load
V,
H
H
X
X
L
L
L
H
I
I
L
H
Z
Z
H
L
L
L
X
X
X
X
X
X
L
L
Z
L
H
L
H
H
H
H
X
X
X
X
NC
NC
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
I
I
I
I
L
H
L
H
H; HIGH
L ; LOW
X ; Don't Care
MILITARV AND COMMERCIAL TEMPERATURE RANGES
H; HIGH
L ; LOW
X ; Don't Care
NC ; No Change
I
; LOW-to-HIGH Transition
Z ; High Impedance
5-3
NC ; No Change
I
; LOW-to-HIGH Transition
Z ; High Impedance
IDT39CB21-26 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect
toGND
CAPACITANCE
COMMERCIAL
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MILITARY
UNIT
-0.5 to +7.0
V
(TA = +25°C, f = 1.0MHz)
PARAMETER(1)
SYMBOL
C 'N
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TVP.
UNIT
Y,N = OV
6
pF
VOUT = OV
8
pF
UNIT
NOTE:
TA
Operating
Temperature
oto +70
-55 to +125
°C
TalAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
100
100
mA
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vee =5.0V ± 5%
Min.
TA =-55°C to +125°C
Vee =5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
I'H
Input HIGH Current
Vee = Max., Y,N = Vee
-
I,L
Input LOW Current
Vee = Max., Y'N = GND
V,
Clamp Diode Voltage
Vee
loz
Off State (High Impedance)
Output Current
Vee = Max.
Vo = O.4V
-
-
Vo = 2.4V
Ise
Short Circuit Current
Vee
SYMBOL
TEST CONDITIONS(1)
PARAMETER
=Min., IN =-18mA
=Max. (3)
Output HIGH Voltage
Vce = Min.
Y'N = V,H or V,L
VH
Input Hysteresis on Clock Only
Vee =Min.
Y'N = V,H or V,L
10
2.0
3.5
-
-
GND
VLC
IOL = 300"A
-
GND
V Le
IOL = 32mA MIL.
-
0.5
IOL = 4BmA COM.
-
200
-
Vee
10H = - 25OI'A
VHe
Vec
10H = -15mA MIL.
2.4
4.0
=-24mA COM.
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. "TYpical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-4
V
-
-120
10H
Output LOW Voltage
I'A
-1.2
-10
-75
Vee =3V, Y'N = VLe or VHe , IOL = 300l'A
VOL
I'A
-
VHe
Vce = 3V, Y,N = VLe or VHe, IOH=-32~
VOH
-().7
5
-5
I'A
mA
V
V
0.5
mV
IDT39C821-26 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC ~ 0.2V: v HC ~ vcc - 0.2V
SYMBOL
MIN.
TYp'12,
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V,N 2VHC
V,N $ VLC
-
0.15
0.25
mAl
MHz
V,N 2VHC
V,N $ VLC
(FCT)
-
1.5
4.0
-
2.0
5.6
-
3.75
I8
-
6.0
15.0
TEST CONDITIONS I"
PARAMETER
VCC~
ICCQ
Quiescent Power Supply Current
Max.
V,N 2: VHC; V,N :5 VLC
Icp~ I; ~ 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc ~ Max.
V,N ~ 3.4V I3'
Dynamic Power Supply
Current
Vcc ~ Max.
Outputs Open
OE~ GND
One Bit Toggling
50% Duty Cycle
ICCD
Icc
Vcc ~ Max.
Outputs Open
Icp ~ 10MHz
50% Duty Cycle
OE ~GND
One Bit Toggling
at Ii ~ 5MHz
50% Duty Cycle
Total Power Supply l 4'
Current
VCC~ Max.
Outputs Open
Icp ~ 10MHz
50% Duty Cycle
OE ~GND
Eight Bits Toggling
at Ii ~ 2.5MHz
50% Duty Cycle
V,N ~ 3.4V
or
V'N~GND
rnA
V ,N 2 VHC
V,N $ VLC
(FCT)
V,N
~
3.4V
or
V,N ~ GND
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input {V,N = 3.4V}; all other inputs at Vee or GNO.
4.
Icc = 'QUIESCENT + 'INPUTS + 'OYNAMIC
Icc = ICCQ + IccrDHNr + IceD (fcp/2 + fjNj)
ICCQ =
IceT
~
Quiescent Current
Power Supply Current for a TTL High Input (V,N
=3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at 0H
IceD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj = Number of Inputs at fj
All currents are in milliamps and all frequencies are in megahertz.
5-5
IDT39C821-26 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COMMERCIAL
PARAMETERS
IpLH
IpHL
IpLH
IpHL
Is
TEST CONDITIONS(1)
DESCRIPTION
Propagation Delay Clock 10 Vi (OE = LOW)
MIN.
MIN.
MAX.
-
12
-
20
C L = 50pF
RL = 500n
-
12
C L = 300pF
RL = 500n
-
20
Dala 10 CP Selup Time
MILITARY
MAX.
UNITS
ns
ns
4
4
ns
IH
Dala 10 CP Hold Time
2
2
ns
Is
Enable (EN ' - ) 10 CP Selup Time
4
4
ns
Is
Enable (EN S ) 10 CP Selup Time
4
4
ns
IH
Enable (EN) Hold Time
2
2
ns
C L = 50pF
RL = 500n
IpHL
Propagalion Delay, Clear 10 Vi
Is
Clear Recovery (ClR ' - ) Time
IPWH
I HIGH
I LOW
Clock Pulse Widlh
IpWL
IPWL
IZH
IZL
IZH
IZL
1HZ
ILZ
I HZ (2)
I LZ
Clear (CLR = LOW) Pulse Widlh
Oulpul Enable Time OE """L 10 Vi
Oulpul Disable Time OE S
10 Vi
20
20
ns
7
7
ns
7
7
ns
7
7
ns
7
7
ns
C L = 300pF
RL = 500n
23
25
ns
C L = 50pF
RL =500n
14
15
ns
C L = 50pF
RL = 500n
16
18
ns
C L = 5pF
RL = 500n
9
10
ns
NOTE:
1. See test circuit and waveforms.
2. This parameter guaranteed but not tested.
5-6
FEATURES:
DESCRIPTION:
• Equivalent to AM D's Am29841-46 Bipolar Registers in
pinout/function, speeds and output drive over full
temperature and voltage supply extremes
• High-speed parallel latches
-Noninverting transparent tpo = 5.5ns typo
-Inverting transparent tpo = 6.0ns typo
The IDT39C800 Series is built using advanced CEMOS'·, a
dual metal CMOS technology.
The I DT39C840 Series bus interface latches are designed to
eliminate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The IDT39C841 and IDT39C842 are buffered, 10-bit wide versions of the popular '373 function. The
IDT39C843 and IDT39C844 are 9-bit wide buffered latches with
Preset (PRE) and Clear (CLR) - ideal for parity bus interfacing in
high-performance systems. The IDT39C845 and IDT39C846 are
8-bit buffered latches with all the '843/4 controls plus multiple
enables (OE" OE 2, OE 3 ) to allow multiuser control of the interface, e.g., CS, DMA, and RDIWR. They are ideal for use as an
output port requiring high IOl/loH .
All of the IDT39C800 high-performance interface family are
designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. All
inputs have· clamp diodes, and all outputs are designed for lowcapacitance bus loading in the high impedance state.
• Buffered common latch enable, clear and preset input
• 48mA commercial IOl' 32mA military IOl
• 200mV (typ.) hysteresis on latch enable input
• Clamp diodes on all inputs for ringing supression
• ESD protection 5000V (typ.) - MIL-STD-883 Category B
• Low input/output capacitance
-6pF inputs (typ.)
-8pF outputs (typ.)
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AM D's Bipolar
Am29800 Series (5p.A max.)
• 100% product assurance screening to MIL-STD-883, Class B
is available
FUNCTIONAL BLOCK DIAGRAM
DSR39C841-001
PRODUCT SELECTOR GUIDE
DEVICE
10-BIT
9-BIT
a-BIT
I Noninverting
IDT39C841
IDT39C843
IDT39C845
I Inverting
IDT39C842
IDT39C844
IDT39C846
CEMOS is a trademark of I ntegrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in the U.S.A.
5-7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C841-46 HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
LOGIC SYMBOLS
IDT39C841/IDT39C842 10-BIT LATCHES
OE
Vee
Do
Yo
Dl
Yl
D2
Y2
D3
Y3
D4
Y4
Ds
Ys
Da
Ya
D7
Y7
Da
Dg
Ya
Yg
GND
u
U
r5 81~ z ~.p>
LJ l.J
-, 4 3 t2J ! ! ~~ 27 26rLJ
II
D3
-".
:J6
D4
:J 7
D2
II
II
II
LJ LJ
24::': Y3
23C: Y4
NC
:J8
Ds :J9
22[:
NC
21 [:
Ys
D&
:110
D7
19,-,11
-..I 12 13 14
16 17 181-1'"" "", r., r, r, r,
20::': Ya
.
II
0
LE
Y2
251--
1
II
II
co 0
"
II
I
U
w
....
Oz· Z
I
00
Y7
D~D
Q
LE
...
10
Y
to'!
I
LE
OE
"
00
~~
CI
LCC
TOP VIEW
DIP
TOP VIEW
DSR39C841-005
DSR39C841-006
DSR39C841-002
IDT39C843/1DT39C844 9-BIT LATCHES
OE
Vee
Do
Yo
Dl
Yl
D2
Y2
D3
Y3
D4
Y4
Ds
Ys
Da
Y&
D7
Y7
Da
II
D3
D4
NC
Ds
D&
D7
-".
-, 4
II
II II
I'll
Lt ILl: 28
3
~: ~~r-
2S L.-
Y2
24[:
Y3
23[:
Y4
:J6
:J7
:J8
:J9
:JlO
22[:
NC
21[:
Ys
20::': Ya
-,11
19r-..I 12
13 14 1. 16 17 18L..r., ,., r,
f"'
I
PRE
GND
II
L.Jl.J
D2
Ya
CUi
u
r5 81~ ~~~>
I
1'"'
II
II
0"I~
....
II
r,
00
II
Y7
"
D
-*D
LE
PRE CfJiQ
1
LE
PRE
..
9
"
Y
CLR
OE
00
0
zU
z UlI.i:l!"
U CI
II.
LE
DIP
TOP VIEW
LCC
TOP VIEW
DSR39C841-003
DSR39C841-008
DSR39CB41-007
IDT39C84S/lDT39C846 8-BIT LATCHES
OEl
Vee
0E2
OE3
81~~ ~
II
II
u ..
~I~ ~
t; ! ! ~i ~J ~tr-
2SL.-
Yl
24[:
Y2
Do
Yo
Dl
Yl
D2
Y2
D2
~J"
:J6
Y3
D3
:J7
23C: Y3
NC
Y4
D3
lJ LJ
Dl
3
L/
D4
Y4
NC
:J8
22[:
Ds
Ys
D4
:J9
21[:
20::': Ys
Ds :JlO
D&
Ya
D7
CLR
Y7
PRE
GND
LE
DIP
TOP VIEW
Da
-.,11
12
_.J
r'
II
D
13
1"""
I
I
19,..14 15 16 17 1SI--
Ya
r., ... , r, r, r,
I
I
II
II
II
D
8
Y
LE
PRE
CLR
OEl
II
orouj3Z ~I -t:
0
8
OE2
U
OE3
LCC
TOP VIEW
DSR39C841-01O
DSR39CB41-009
5-8
DSA39C841-004
IDT39C841-46 HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
NAME
DESCRIPTION
110
IDT39C841/43/45 (Non-inverting)
CLR
I
When CLR is low. the outputs are LOW if OE is
LOW. When CLR is HIGH. data can be entered
into the latch.
Dj
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data is
latched on the HIGH-to-LOW transition.
Yj
a
The 3-state latch outputs.
OE
I
The output enable control. When OE is LOW. the
outputs are enabled. When OE is HIGH. the
outputs Y, are in the high-impedance (off) state.
PRE
I
Preset li~~ When PRE is LOW. the o~s are
HIGH if OE is LOW. Preset overrides CLR.
IDT39C842/44/46 (Inverting)
CLR
I
When CLR is low. the outputs are LOW if OE is
LOW. When CLR is HIGH. data can be entered
into the latch.
Dj
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data is
latched on the HIGH-to-LOW transition.
Yj
a
The 3-state latch outputs.
OE
I
The output enable control. When OE is LOW. the
outputs are enabled. When OE is HIGH. the
outputs Yj are in the high-impedance (off) state.
PRE
I
Preset line. When PRE is LOW. the ou~s are
HIGH if OE is Law. Preset overrides CLR.
FUNCTION TABLES
IDT39C841/43/45
I DT39C842/44/46
INTERNAL
OUTPUTS
INPUTS
CLR
PRE
OE
H
H
H
H
H
LE
D;
Q,
Y,
H
X
X
X
Z
H
H
L
L
Z
H
H
H
H
H
H
H
H
L
X
H
H
L
H
H
H
L
H
H
H
L
INTERNAL
OUTPUTS
INPUTS
FUNCTION
LE
FUNCTION
CLR
PRE
OE
Hi-Z
H
H
H
Hi-Z
H
H
H
Z
Hi-Z
H
H
H
H
NC
Z
Latched
(Hi-Z)
H
H
H
L
X
NC
L
L
L
Transparent
H
H
L
H
H
L
H
H
H
H
Transparent
H
H
L
H
L
H
L
L
X
NC
NC
Latched
H
H
L
L
X
NC
NC
L
L
X
X
H
H
Preset
H
L
L
X
X
H
H
Preset
H
L
X
X
L
L
Clear
L
H
L
X
X
L
L
Clear
D;
Q;
Y;
X
X
X
Z
Hi-Z
H
H
L
Z
Hi-Z
L
H
Z
Hi-Z
Z
Latched
(Hi-Z)
L
Transparent
H
Transparent
Latched
L
L
L
X
X
H
H
Preset
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
Latched
(Hi-Z)
L
H
H
L
X
L
Z
Latched
(Hi-Z)
Z
Latched
(Hi-Z)
H
L
H
L
X
H
Z
Latched
(Hi-Z)
H
L
H
L
X
H
5-9
IDT39C841-46 HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
CAPACITANCE
MILITARY
UNIT
VTERM
Terminal Vollage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
100
100
mA
-0.5 to +7.0
MILITARY AND COMMERCIAL TEMPERATURE RANGES
-0.5 to +7.0
V
(TA: +25°C, f: l.DMHz)
PARAMETER(')
CONDITIONS
TYp.
UNIT
C 'N
Input Capacitance
V,N : OV
6
pF
C OUT
Output Capacitance
VOUT : OV
8
pF
MAX,
UNIT
SYMBOL
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Vee: 5.DV ± 5%
Min. : 4.75V
=
Vee =5.DV ± 10%
Min. =4.5DV
VLe = D.2V
VHe = Vee - D.2V
Max. = 5.25V (Commercial)
Max. = 5.5DV (Military)
TA: DOC to +7D oC
TA -55°C to +125°C
SYMBOL
TEST CONDITIONS(')
PARAMETER
MIN,
TYP'(2)
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V,L
Input LOW Level
Guaranteed Log ic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vee: Max., Y'N : Vee
-
-
5
I'A
I'L
I nput LOW Current
Vee: Max., Y'N : GND
I'A
loz
Off State (High Impedance)
Output Current
Vee; Max.
-
-
-5
Vo; O.4V
-
-
-10
Vo; 2.4V
-
-
10
-0.7
-1.2
V
-75
-120
mA
V,
Clamp Diode Voltage
Vee; Min., IN; -18mA
Ise
Short Circuit Current
Vee: Max. (3)
VHe
Vee
-
10H; - 25OI'A
VHe
Vce
-
10H; -15mA
2.4
4.0
10H ; -24mA COM'L.
2.0
3.5
-
-
GND
VLe
10L: 300l'A
-
GND
VLe
10L; 32mA MIL.
-
-
0.5
-
-
0.5
-
200
-
Vee; 3V, Y'N ; VLe or VHe, 10H; -321'A
VOH
Output HIGH Voltage
Vee: Min.
Y,N ; V,H or V'L
Vee: 3V, V,N ; VLe or VHe , 10L ; 300ilA
VOL
Output LOW Voltage
VH
I nput Hysteresis on LE
Vee; Min.
Y'N ; V,H or V,L
10L ; 48mA COM'L.
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-10
V
I'A
V
V
mV
IDT39C841-46 HIGH·PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = 0.2V: v HC = vcc - 0.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc = Max.
Y,N 2: VHC : Y'N ,;; VLC
Ii = 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc= Max.
Y'N = 3.4v(3)
Dynamic Power Supply
Current
Vcc= Max.
Outputs Open
OE = GND
LE = VCC
One Input Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply(4)
Current
MIN.
TVP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
Y'N 2: VHC
V,N ,;; VLC
-
0.15
0.25
mAl
MHz
Y,N 2: VHC
V,N';;V LC
(FCT)
-
1.5
4.0
Y'N = 3AV
V,N=GND
-
1.8
4.8
Y,N 2:VHC
Y,N';; V LC
(FCT)
-
3.0
6.5
Y'N = 3.4V
Y,N = GND
-
5.0
12.9
TEST CONDITIONS(1)
PARAMETER
Vcc = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE=GND
LE = VCC
One Bit Toggling
Vcc = Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
OE =GND
LE = Vcc
Eight Bits Toggling
mA
NOTES:
1. For conditions shown as max. or min .. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'QUIESCENT + 'INPUTS + 'OYNAMIC
Icc = IceQ + ICCTDHNT + IceD (fcp/2 + fjNj)
ICCQ = Quiescent Current
ICCT =Power Supply Current for a TTL High Input (V IN =3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
tep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-11
IDT39C841-46 HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COMMERCIAL
PARAMETERS
tpLH
(IDT39C841, 43, 4S)
tpHL
TEST CONDITIONS(1)
DESCRIPTION
C L = SOpF
RL = soon
Data (0,) to Output (V,) (LE = HIGH)
tpLH
tpHL
ts
Data to LE Setup Time
tH
Data to LE Hold Time
t pLH
(IDT39C842, 44, 46)
t pHL
Data (0,) to Output (V,) (LE = HIGH)
tpLH
tpHL
ts
Data to LE Setup Time
tH
Data to LE Hold Time
tpLH
tpHL
Latch Enable (LE) to V,
t pLH
tpHL
tpLH
Propagation Delay, Preset to Vi
ts
Preset Recovery (PRE S ) Time
tpHL
Propagation Delay, Clear to V,
Clear Recovery (CLR
tPWH
LE Pulse Width
HIGH
tPWL
Preset Pulse Width
LOW
tpwL
Clear Pulse Width
LOW
tZH
tZL
tHZ
tLZ
t HZ(2)
Output Enable Time OE
Output Disable Time
9.S
C L = 300pF
RL = soon
-
C L = SOpF
RL = soon
2.S
....r
OE S
to Vi
tLZ
NOTE:
1. See test circuit and waveforms,
2. This parameter guaranteed but not tested.
5-12
MAX.
UNITS
11
ns
13
-
1S
ns
-
2.S
ns
2.S
-
3
-
C L = SOpF
RL = soon
-
10
-
12
ns
C L = 300pF
RL = soon
-
13
-
1S
ns
C L = SOpF
RL = soon
2.S
-
2.S
2.S
3
-
ns
C L = SOpF
RL = soon
-
12
-
16
ns
C L = 300 pF
RL = soon
-
16
-
20
ns
-
12
-
14
ns
-
14
-
17
ns
-
13
-
1S
ns
17
ns
6
6
9
-
ns
8
-
8
-
9
-
ns
C L = 300pF
RL = soon
-
23
-
2S
ns
C L = SOpF
RL = soon
-
14
-
1S
ns
C L = SOpF
RL = soon
-
12
-
12
ns
C L = SpF
RL = soon
-
9
-
10
ns
C L = SOpF
RL = soon
to V,
MILITARY
MIN.
-
-1 ) Time
tZH
tZL
MAX.
-
C L = SOpF
RL = soon
ts
MIN.
14
ns
ns
ns
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am29861-64 Bipolar Registers in
pinout/function, speeds and output drive over full
temperature and voltage supply extremes
• High-speed symmetrical bidirectional transceivers
-Noninverting tpo 5.5ns typo
-Inverting tpo 6.0ns typo
The IDT39C800 Series is built using advanced CEMOS'·, a
dual metal CMOS technology.
The IDT39C860 Series bus transceivers provide high-performance bus interface buffering for wide data/address paths or
buses carryi ng parity. The I DT39C863/64 9-bit transceivers have
NOR-ed output enables for maximum control flexibility.
All of the IDT39C800 high-performance interface family are
designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes, and all outputs are designed for lowcapacitance bus loading in the high impedance state.
0
0
• 48mA commercial IOl' 32mA military IOl
• 200mV (typ.) hysteresis on T and R buses
• Clamp diodes on all inputs for ringing suppression
• ESD protection 5000V (typ.) -
MIL-STD-883 Category B
• Low input/output capacitance
• CMOS power levels (5/lW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AMD's Bipolar
Am29800 series (5/lA max.)
• 100% product assurance screening to MIL-STD-883, Class B
is available.
FUNCTIONAL BLOCK DIAGRAM
IDT39C861/1DT39C862 10-BIT TRANSCEIVERS
SS039C861-001
PRODUCT SELECTOR GUIDE
DEVICE
10-BIT
9-BIT
I Noninverting
IDT39C861
IDT39C863
I Inverting
IDT39C862
IDT39C864
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986lntegrated Device Technology, Inc
JULY 1986
Printed
5-13
In
USA
IDT39C861-64 HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
IDT39C863/1DT39C864 9-BIT TRANSCEIVERS
SSD39CB61-004
PIN CONFIGURATIONS
LOGIC SYMBOLS
IDT39C861/IDT39C862 10-BIT TRANSCEIVERS
IDT39C861
OER
Vee
Ro
To
Rl
Tl
R2
T2
R2
T2
R3
T3
R3
T3
R4
R4
T4
NC
T4
NC
Rs
Ts
Rs
Ts
R6
T6
R6
:J10
R7
T7
R7
-,'11
--'12
Ra
Rg
Ta
Tg
GND
13
14 15 16 17
20[:
T6
19,..lSL..-
T7
fl r1 fl rl fl rl rl
10
R
T
OER
CDCIIQOI~~~
a:a:zzw~~
OET
CI
DIP
TOP VIEW
0
SSD39C8610-002
LCC
TOP VIEW
SSD39C861-005
SSD39C861-006
IDT39C863/IDT39C864.9-BIT TRANSCEIVERS
IDT39C863
OERl
Vee
Ro
To
Rl
Tl
R2
R2
T2
R3
R3
T3
R4
T4
R4
NC
:]8
22[:
NC
Rs
Ts
Rs
:J9
21[':
R6
T6
R6
:J10
20[:
Ts
Te
R7
T7
R7
:J';~ 13 14 15 16 17
fl r1 rl r1 r1 r1 rl
;:C:
T7
Ra
OER2
Ta
OET2
GND
OETt
DIP
TOP VIEW
5SD39C861-007
23[:
T4
9
T
LCC
TOP VIEW
SSD39CB61-008
5-14
SSD39C661-003
IDT39C861-64 HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
NAME
1/0
DESCRIPTION
IDT39C861 162
6ER
I
When LOW in conjunction with OET HIGH
activates the RECEIVE mode.
6ET
I
When LOW in conjunction with OER HIGH
activates the TRANSMIT mode.
R,
I/O
10-bit RECEIVE input/output.
T,
I/O
10-bit TRANSMIT input/output.
IDT39C863/64
OER,
I
When LOW in conjunction with OET, HIGH
activates the RECEIVE mode.
OET,
I
When LOW in conjunction with OER, HIGH
activates the TRANSMIT mode.
R,
I/O
9-bit RECEIVE input/output.
T,
I/O
9-bit TRANSMIT input/output.
FUNCTION TABLES
IDT39C861/1DT39C863 (Noninverting)
IDT39C862/1DT39C864 (Inverting)
INPUTS
OET
OER
R,
OUTPUTS
T,
R,
T,
INPUTS
FUNCTION
OET
OER
R,
OUTPUTS
T,
R,
T,
FUNCTION
Transmitting
l
H
l
N/A
N/A
l
Transmitting
L
H
l
N/A
N/A
l
H
H
N/A
N/A
H
Transmitting
l
H
H
N/A
N/A
l
H
l
N/A
l
l
N/A
Receiving
H
l
N/A
l
H
N/A
Receiving
H
l
N/A
H
H
N/A
Receiving
H
l
N/A
H
l
N/A
Receiving
H
H
X
X
Z
Z
Hi-Z
H
H
X
X
Z
Z
H; HIGH
l;lOW
Z ; High Impedance
H; HIGH
l;lOW
Z ; High Impedance
X ; Don't Care
N/A ; Not Applicable
5-15
H
Transmitting
Hi-Z
X ; Don't Care
N/A; Not Applicable
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39C861-64 HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
CAPACITANCE
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
oto +70
-55 to +125
°C
TelAs
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
100
100
mA
-0.5 to +7.0
-0.5 to +7.0
V
(TA = +25°C, f = 100M Hz)
PARAMETER(1)
SYMBOL
C 'N
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
V,N =OV
6
pF
VOUT = OV
8
pF
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
VHe = Vee - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP.(')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V'L
Input LOW Level
Guaranteed Logie Low Level
-
0.8
V
I'H
Input HIGH Current
Vec = Max., V,N = Vec
-
-
5
p.A
I'L
V,
Input LOW Current
Vcc = Max., V,N = GND
-
-
-5
p.A
Clamp Diode Voltage
Vce = Min., IN = -18mA
-
-0.7
-1.2
V
Vee = MAX
Vo = 0.4V
-
-
-10
loz
Off State (High Impedance)
Output Current
Vo = 2.4V
-
-
10
Ise
Short Circuit Current
Vee = Max. (3)
SYMBOL
VOH
TEST CONDITIONS(1)
PARAMETER
Output HIGH Voltage
-75
-120
-
VHe
Vee
-
10H = -250p.A
VHe
Vee
-
10H = -15mA MIL.
2.4
4.0
-
Vec
= 3V, V,N = VLe or VHe,
Vee
= Min.
V 1N = V 1H or V IL
10H = -32p.A
2.0
3.5
-
-
GND
VLe
IOL
-
GND
VLe
10L
-
-
0.5
-
0.5
IOH
=-24mA COM.
Vee = 3V, V,N = VLe or VHe, 10L = 300p.A
VOL
Output LOW Voltage
VH
Input Hysteresis on Ri and Ti
=300p.A
=32mA MIL.
10L = 48mA COM.
Vee = Min.
V,N = V,H or V'L
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0\1, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-16
200
-
p.A
mA
V
V
mV
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT39CB61-64 HIGH·PERFORMANCE CMOS BUS TRANSCEIVERS
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; vHC = vcc - O.2V
SYMBOL
MIN.
TYR")
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N 2: VHC
V1N ::; VLC
-
0.15
0.25
Vcc = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
V,N 2: VHC
Y,N S VLC (FCT)
-
1.5
4.0
Y,N = 3.4V
Y'N = GND
-
1.8
4.8
Vce = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
V,N 2: VHC
V,N S VLC (FCT)
-
3.0
6.5
Y'N = 3.4V
V,N=GND
-
5.0
12.9
PARAMETER
TEST CONDITlONS")
ICCQ
Quiescent Power Supply Current
Vcc = Max.
Y,N 2: VHC: Y,N S VLC
f, = 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vce = Max.
V IN = 3.4V(3)
leeo
Dynamic Power Supply
Current
Vee = Max.
Outputs Open
O£.=GND
T/R = GND or Vee
One Input Toggling
50% Duty Cycle
Total Power Supply (4)
Current
Icc
mAl
MHz
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN :::: 3.4V); all other inputs at Vee or GND.
4.
Icc
= IQUIESCENT + IINPUTS +
I DYNAMIC
Icc = Icco + ICCTDHNT + ICCD (fcp/2 + fiNj)
Icco = Quiescent Current
ICCT
=Power Supply Current for a TTL High Input (V 1N =3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HlH or lHl)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
PARAMETERS
tpLH
t pHL
tpLH
t pHL
tpLH
tpHL
tpLH
DESCRIPTION
Propagation Delay from
Ai to Ti or Ti to Ai
IDT39C861/1DT39C863 (Noninverting)
Propagation Delay from
Ai to Ti or T j to Ai
IDT39C862/1DT39C864 (Inverting)
tpHL
tZH
tZL
tZH
tZL
t ZH (2)
tZL
tZH
tZL
Output Enable Time OET to
T, or OER to Rj
Output Enable Time OET to
T j or OER toH,
TEST CONDITIONS(1)
MILITARY
COMMERCIAL
MIN.
MAX.
UNITS
MIN.
MAX.
C L = 50pF
RL = soon
-
8
-
10
ns
C L = 300pF
RL = 500n
-
15
-
17
ns
C L = 50pF
RL =500n
-
7.5
-
9.5
ns
C L = 300pF
RL =500n
-
14
-
16
ns
C L = 50pF
RL = 500n
-
15
-
17
ns
C L = 300pF
RL = SOOn
-
20
-
22
ns
C L =5pF
RL = 500n
-
9
-
10
ns
C L = SOpF
RL = 500n
-
17
-
19
ns
NOTE:
1. See test circuit and waveforms.
2. This parameter guaranteed but not tested.
5·17
FEATURES:
DESCRIPTION:
The i OT49C818 is a high-speed, general-purpose octal register
• High-speed non-inverting 8-bit parallel register for any data
path, control path or pipelining application
• Pin-out similar to the Am29818 and 54/745818, but uses an
improved protocol for the serial interface
to New, unique command capability which allows for
multiplicity of diagnostic functions
• High-speed Serial Protocol Channel (SPC) which provides
access to octal data register using four pins
with a Serial Protocol Channel (SPC). The D-to-Y path of the
octal register provides a data path that is designed for normal
system operation wherever a high-speed clocked register is
required. The IDT49C818 is pin-out similar to the 29818 and
54/74S818, but uses the serial data, clock and mode pins as SPC
to communicate with the serial command and data registers.
The command and data registers are used to observe and
control the operation of the octal data registers. The serial
command and data registers can be accessed while the system is
performing normal system function. Diagnostic operations then
can be performed "on the fly", synchronous with the system
clock, or can be performed in the "single step" environment. The
SPC port utilizes serial data in (SDI) and data out (SDO) pins
which can participate in a serial scan loop throughoutthe system
where normal data, address, status and control registers are
replaced with the IDT49C818. The loop can be used to scan in a
complete test routine starting point (data, address, etc.). Then,
after a specified number of clock cycles, the data can be clocked
out and compared with expected results. An "oscilloscope mode"
can be achieved by loading data from theSPC serial data register
into the octal data register synchronous to the system clock
(PCLK) using a diagnostic command which transfers data
synchronously. When repeated every Nth clock, the repeating
states of the system can be observed on an oscilloscope. When
used as a pipeline register, WCS loading can be accomplished by
scanning in data through the SPC port and enabling the data
onto the D bus pins.
• Controllability
-Serial scan of new machine state
-Form temporary connections between D and Y buses
-Load new machine state "on the fly" synchronous
with PCLK
- Temporarily force Y output bus
- Temporarily force data out the D input bus (as in loading
Writeable Control Store - WCS)
• 0 bservabil ity
-Directly observe D and Y buses
-Serial scan out current machine state
-Capture machine state "on the fly" synchronous
with PCLK
-WCS pipeline register
-Load WCS from serial input
- Read WCS via serial scan
• Ideal for diagnostic scan testing
00.7
FUNCTIONAL BLOCK DIAGRAM
MUX
.-------~--------L>SDO
SOl
SCLK
SERIAL PROTOCOL
DATA AND CONTROL
REGISTERS
DATA REGISTI:R
PCLK
MUX
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.
Integrated Device Technology, Inc. has a patent pending on this ~evice.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
5-18
JULY 1986
Printed in U.S.A.
IDT49C818 FAST CMOS OCTAL REGISTER
WITH SPC (SPECIAL PROTOCOL CHANNEL)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOGIC SYMBOL
PIN CONFIGURATION
3
DE
Vee
SCLK
c/o
Do
Yo
D,
Y,
D.
Y.
Y3
D3
11
Ds
5
D7
SDI
9
10
PLCK
13
OE
23
22 21 20 19 18 17 16 15
SSD49C818-0Q3
PCLK
DIP
TOP VIEW
SS049C818~OO2
TYPICAL MICROPROGRAM APPLICATION
IR
(SPC REG)
DATA'N
(SPC REG)
IDT49C818
IDT49C818
IDT49C402
WCS
IDT71981
SPC
8
14
SDO
GND
7
SCLK
Y.
Y7
D.
6
SDI
Y.
Ys
D.
4
PIPELINE REG
(SPC REG)
DATAOUT
(SPCREG)
IDT49C818
IDT49C818
SSD49CB18-004
5-19
FEATURES:
DESCRIPTION:
• Equivalent to AlS speeds and output drive over full
temperature and voltage supply extremes
The IDT54174AHCT138 are 1-of-8 decoders built using
advanced CEMOS", a dual metal CMOS technology. The
IDT54/74AHCT138 accepts three binary weighed inputs (A o,
A" AiJ and, when enabled, provides eight mutually exclusive
aciive lOW outputs (0 0-0 7), The IDT54/74AHCT138 features
three enable inputs, two active lOW (f" E 2) and one active
HIGH (E3)' All outpus will be HIGH unless E, andE2 are lOW
and E3 is HIGH. This multiple enable function allows easy
parallel expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four IDT54/74AHCT138 devices and one
inverter.
• 11 ns typical address to output delay
•
•
•
•
•
•
IOl = 14mA over full military temperature range
CMOS power levels (5/lW typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than AlS (5/lA max.)
1-of-8 decoder with enables
100% product assurance screening to Mll-STD-883, Class B
is available
• JEDEC standard pinout for DIP and lCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Vee
00
0,
02
0,
O.
0,
0,
SSD54174AHCT13B-001
DIP
TOP VIEW
LJ LJ L J L J LJ
07
GND
::9 8
7
6
5
43:
A1
2::
Ao
:::10
SS054174AHCT138-003
SSD54174AHCT138-002
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in USA.
01986 Integrated Device Technology, Inc.
5-20
IDT54/74AHCT138 HIGH-SPEED CMOS 1-0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TerAs
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
VHe = Vee - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP.(')
MAX.
VrH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
Vrl
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
5
p.A
-5
p.A
-
mA
SYMBOL
TEST CONDITIONS(')
PARAMETER
IrH
Input HIGH Current
Vee = Max., V,N = Vee
-
I,L
Input LOW Current
Vee = Max., V,N = GND
-
-
Isc
Short Circuit Current
Vee = Max. (3)
-60
-100
Vee = 3V, V,N = Vle or VHe, 10H = -32p.A
VHe
Vee
10H = -150p.A
VHe
Vee
10H = -1.0mA MIL
2.4
4.3
10H = -2.6mA COM
2.4
4.3
-
GND
VLC
-
GND
Vle
-
0.4
-
0.5
VOH
Output HIGH Voltage
Vee = Min.
V ,N = V,H or V'l
Vee = 3V, V,N = V LC or VHe , 10l = 3OOl'A
VOL
Output LOW Voltage
10l = 300p.A
Vee = Min.
V,N = VrH or V'l
10L =14mA MIL
IOl =24mA COM
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at vee::: 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-21
UNIT
V
V
IDT54n4AHCT138 HIGH-SPEED CMOS 1-0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = vcc - O.2V
SYMBOL
Icca
Quiescent Power Supply Current
Vcc= Max.
VHC S Y,N; Y,N S VLC
'i =0
Iocr
Power Supply Current
TTL Inputs HIGH
Vcc= Max.
V IN = 3.4V(3)
ICCD
Dynamic Power
Supply Current
Vcc=Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Icc
Total Power
Supply Current (4)
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N---
~7
~7
C5 ~
~
II
~7
)U
1I
II
t)
r
I
Q 1/ :r
~
I
CLOCK
PRESET
CLEAR
Fie
TC
o
Q
1
L-
t)
1
I
L
I L
I
I
Y/
V
I
I
I
1
I
I
),
CJ
Q
~
V
0
~
V
0,
C)
1
),
J CLOCK K
PRESET
CLEAR
KIF
CLEAR
Q
Y
I
I
~IJPRESET
CLOCK
CLOCK K
PRESET
CLEAR
o
II
Q
~
V
0,
SSOFCT191-OO1
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5-35
JULY 1986
@1986 Integrated Device Technology, Printed In the U.S.A.
IDT54n4AHCT191
HIGH-SPEED CMOS UP/OOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATING(1)
II
_] L3.J
4
II
II
II
Li :L,J: ~~
RATING
COMMERCIAL
MILITARY
UNIT
VTERM
Terminal
Voltage with
Respect to GNO
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operation
Temperature
Oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
OCOutput
Current
120
120
mA
SSDFCT191...Q02
DIP
TOP VIEW
Qo -
SYMBOL
NOTE:
1. Stresses greeter than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other cond itions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
II
t~r-
18~- CP
Ce
17e:
NC
leL:. NC
UJD
TC
RC
SSDFCT19HXJ3
LCC
TOP VIEW
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP'(2)
MAX.
UNIT
-
-
V
0.8
V
-
5
p.A
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
VIL
Input LOW Level
Guaranteed Logic Low Level
-
IIH
Input HIGH Current
Vee = Max., VIN = Vce
-
IlL
Input LOW Current
Vee = Max., V,N = GNO
-
-
-5
p.A
Ise
Short Circuit Current
Vee = Max. (3)
-60
-100
mA
VHe
Vee
-
10H = -150p.A
VHe
Vee
-
10H = -1.0mA MIL.
2.4
4.3
-
10H = -2.6mA COM'L.
2.4
4.3
-
-
GNO
VLe
Vee = 3V, VIN = VLe or VHe , 10H = -32p.A
VOH
Output HIGH Voltage
Vee = Min.
V IN = V IH or VIL
Vee = 3V, VIN = VLe or VHe , 10L = 300p.A
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
10L = 300p.A
-
GNO
VLe
IOL = 14mA MIL.
-
0.4
IOL = 24mA COM'L.
-
-
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the. applicable device type.
2. Typical valUes are at Vee = 5.0V, +25Q C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-36
V
V
IDT54174AHCT191
HIGH-SPEED CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC
=O.2V; vHC =vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vee = Max.
Y'N e: VHC: V,N '; VLC
fcp=fi=O
ICCT
Power Supply Current
Per TTL Input HIGH
Vcc= Max.
Y'N = 3.4V(3)
Dynamic Power
Supply Current
Vcc= Max.
Outputs Open
Count Up or Down
CE = VLC
£,L = Po - P 3 = VHC
U/D = VHC or VLC
Total Power
Supply Current(')
Vcc= Max.
Outputs Open
fcp= 1.0MHz
50"10 Duty Cycle
Count Up or Down
CE = VLC
£,L = Po - P 3 = VHC
U/D = VHC or VLC
IceD
Icc
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.3
-
MHz
V'Ne: VHC
Y,N'; VLC
(AHCT)
-
0.3
-
Y'N = 3.4V
or
Y,N = GND
-
1.1
-
TEST CONDITIONS(1)
PARAMETER
V1N 2::VHC
Y,N'; VLC
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: 5.0V, +25°C ambient and maximum loading.
3. Not more than one output shold be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Per TTL driven input (VtN ::: 3.4V); all other inputs at Vee or GND.
5.
Icc::: 'QUIESCENT + 'INPUTS
+ I DYNAMIC
Icc::: Icca+ ICCTDHNT+ IceD (fcp+ fiNj)
'CGQ::: Quiescent Current
'ceT::: Power Supply Current for a TTL High Input (VIN = 3.4V)
DH =Duty Cycle for TTL Input High
NT'" Number of TTL Inputs at DH
I CCD
=Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Count Clock or Load Clock Frequency
fj = PO~3lnput Frequency (Load)
Nj = Number of P o_3 lnputs at f i (Load)
All currents are in milliamps and all frequencies are in megahertz.
5-37
mN
IDT54n4AHCT191
HIGH-SPEED CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
RC TRUTH TABLE
DESCRIPTION
INPUTS
Count Enable I nput (Active LOW)
Count Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Up/Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output (Active LOW)
Terminal Clock Output (Active HIGH)
CE
CP
PO-3
PL
U/D
QO-3
RC
TC
CE
TC(1I
L
H
H
X
L
X
OUTPUT
CP
RC
X
X
H
H
NOTES:
1. TC is generated internally.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
TRUTH TABLES
MODE SELECT TABLE
INPUTS
PL
CE
UfD
CP
H
H
L
H
L
L
L
H
I
I
X
X
X
X
X
H
MODE
Count Up
Count Down
Preset (Asynch.)
No Change (Hold)
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITION
TYPICAL
COMMERCIAL
MILITARY
MIN ••
MAX.
MIN.
MAX.
UNITS
tpLH
t pHL
Propagation Delay
CP to Q n
-
3.0
18.0
3.0
22.0
ns
tpLH
tpHL
Propagation Delay
CPtoTC
-
6.0
31.0
6.0
34.0
ns
tpLH
tpHL
Propagatio!l!>elay
CPto RC
-
5.0
20.0
4.0
24.0
ns
tpLH
t pHL
ProP.l!ll!'tio!l!>elay
CEto RC
-
4.0
18.0
4.0
21.0
ns
tpLH
tpHL
Pro~gatio'!.Qelay
tpLH
Pro~gation
-
6.0
25.0
6.0
30.0
ns
Delay
UlDtoTC
-
6.0
25.0
6.0
30.0
ns
Propagation Delay
Pn to Q n
-
4.0
21.0
4.0
25.0
ns
Prop~ation
-
6.0
30.0
6.0
34.0
ns
-
20.0
-
25.0
-
ns
-
5.0
-
5.0
-
ns
LOW
CEto CP
-
20.0
-
25.0
-
tH(L)
Hold Time LOW
CEtoCP
-
0
-
0
-
ts(H)
ts(L)
Setup Time
HIGH or LOW
U/DtoCP
-
20.0
-
20.0
-
ns
tH(H)
tH(L)
Hold Time
HIGH or LOW
U/DtoCP
-
0
-
0
-
ns
tpHL
tpLH
tpHl
tpLH
tpHL
UlD to RC
Delay
PL to Q n
ts(H)
ts(L)
Setup Time
HIGH or LOW
Pn to PL
tH(H)
tH(L)
Hold Time
HIGH or LOW
Pn to PL
ts(L)
Set~Time
C L = 50pF
RL = 500n
tw(L)
PL Pulse Width LOW
-
ns
15.0
-
25.0
CP Pulse Width LOW
-
20.0
tw(L)
20.0
-
ns
tREe
Recovery Time
PL to CP
-
15.0
-
20.0
-
ns
5-38
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT193 is an up/down module-16 binary
counter built using advanced CEMOS'·, a dual metal CMOS
technology. Separate Count-up and Count-down Clocks are used
and, in either counting mode, the circuits operate synchronously.
The outputs change state synchronously with the LOW-te-HIGH
transitions on the clock inputs. Separate Terminal Count-up and
Terminal Count-down outputs are provided that are used as the
clocks for subsequent stages without extra logic, thus si mplifying
multistage counter designs. Individual preset inputs allow the
circuit to be used as a programmable counter. Both the Parallel
Load (PL) and the Master Reset (MR) inputs asynchronously
override the clocks.
• IOL = 14mA over full military temperature range
• CMOS power levels (5J.'
V
'7
'7
0,
O2
03
L-
MR
y
~: CPos~r
SD
(BORROW)
~
~
:[
j
CD
(CARRY)
o
J'
So
0
r
~
L-
o
0
~
SSDAHCT193"()()1
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
01986 Integrated Device Technology, Inc.
Printed in the U.S.A.
5-39
IDT54n4AHCT193
HIGH-SPEED CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATING(1)
PI
Vee
Q1
Qo
Po
TCo
CPu
TCu
Pi
Q2
Q3
P2
P3
GND
DIP/SOIC
TOP VIEW
COMMERCIAL
MILITARY
UNIT
VTERM
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operation
Temperature
oto +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output
Current
120
120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
u
cfa.""~
~~
II II
II
_] L3.J
-
RATING
Terminal
Voltage with
Respect to GND
MR
CPo
Q2
SYMBOL
4
L2.J
II
I : ~o
~J
II
i~r18L.-
Pi
CPu
:J 5
17[: TCu
NC
:J6
16C: NC
CPD :J7
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability_
15[":' TCD
14 r -
QO
13L...-
," ,
MR
LCc/PLCC
TOPYIEW
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FOllowing Conditions Apply Unless Otherwise Specified:
TA =O·C to +70·C
Vee =5.0V ± 5%
Min. =4.75V
TA = -55·C to +125·C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = O.2V
VHe = Vee - O.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYp.(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
VIL
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
IIH
Input HIGH Current
Vee =Max., VIN
-
-
5
p.A
IlL
Input LOW Current
-
-5
p.A
Short Circuit Current
Vee = Max., VIN = GND
Vee = Max. 13)
-
Ise
-60
-100
mA
Vee = 3V, VIN = VLe or VHe, IOH = -32p.A
-
SYMBOL
VOH
TEST CONDITIONSII)
PARAMETER
Output HIGH Voltage
Vee = Min.
VIN = VIH or V IL
=Vec
VHe
Vee
IOH= -150p.A
VHe
Vee
-
IOH = -1.0mA MIL.
2.4
4.3
IOH = -2.6mA COM'L
2.4
4.3
-
GND
VLe
IOL = 3oop.A
-
GND
VLe
IOL = 14m A MIL.
-
0.4
IOL = 24mA COM'L.
-
-
Vee = 3V, VIN = V Le or VHe , IOL = 3oop.A
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or V IL
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-40
0.5
V
V
IDT54n4AHCT193
HIGH-SPEED CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; vHC = vcc - O.2V
SYMBOL
Icco
Quiescent Power Supply Current
Vee = Max.
V'N 2: VHC; V'N oS VLC
fcpu =f CPD = fi =0
ICCT
Power Supply Current Per
TTL Input HIGH
Vcc =Max.
V'N =3.4V(3)
IceD
Dynamic Power
Supply Current
Vcc =Max.
Outputs Open
Count Up or Down
PL=P o -P 3 =VHc
MR =VLC
Total Power
Supply Current")
Vcc =Max.
Outputs Open
fcp =1.0MHz
50% Duty Cycle
Count Up or Down
PL = Po - P3 =VHC
MR =VLC
Icc
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N 2: VHC
V'N oS VLC
-
0.3
-
mAl
MHz
V'N 2: VHC
V,N oS VLC
(AHCT)
-
0.3
-
TEST CONDITIONst')
PARAMETER
V'N
=3.4V
or
V'N=GND
mA
-
1.1
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (V1N ::: 3.4V); all other inputs at Vee or GNO.
4.
Icc::: IQUIESCENT + IINPUTS + IDYNAMIC
Icc::: leGQ + ICCTDHNT + ICGD (fcp + fiNj)
ICGQ:::
Quiescent Current
leCT = Power Supply Current for a TTL High Input (V1N ::: 3.4V)
DH = Duty Cycle for TTL Input High
NT::: Number of TTL Inputs at DH
IceD::: Dynamic Current caused by an Input Transition pair (HlH or LHL)
fcp::: Count Clock or Load Clock Frequency
fi ::: PO_3lnput Frequency (Load)
Ni ::: Number of PO_3lnputs at fj (load)
All currents are in milliamps and all frequencies are in megahertz.
I
5-41
IDT54n4AHCT193
HIGH-SPEED CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE
DEFINITION OF FUNCTIONAl- TERMS
PIN
NAMES
CPu
CPo
MR
PL
PO-3
0 0-3
TC o
TC u
DESCRIPTION
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset Input (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-Flop Outputs'
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
MR
PI-
CPu
CPo
H
L
L
L
L
X
L
H
H
H
X
X
H
I
X
X
H
H
H
I
MODE
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down
H " HIGH Voltage Level
L" LOW Voltage Level
X::: Immaterial
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITION
TYPICAL
COMMERCIAL
MILITARY
MIN ..
MAX.
MIN.
MAX.
UNITS
Propagation Delay
C£..u or CPo to
TCuorTC o
-
4.0
16.0
4.0
19.0
ns
t pHL
Propagation Delay
CPu or CPo to On
-
4.0
17.0
4.0
20.0
ns
tpLH
tpHL
Propagation Delay
PntoO n
-
4.0
17.0
4.0
20.0
ns
t pLH
t pHL
Propagation Delay
PL to On
-
6.0
28.0
6.0
31.0
ns
tpHL
Propagation Delay
MRtoO n
-
6.0
28.0
6.0
31.0
ns
-
6.0
28.0
6.0
31.0
ns
-
6.0
28.0
6.0
31.0
ns
-
6.0
28.0
6.0
31.0
ns
-
4.0
17.0
4.0
20.0
ns
-
20.0
-
25.0
-
ns
t pLH
tpHL
tpLH
tpLH
t pHL
Propagati~elay
MRtoTC u
Propagati~elay
MRtoTC o
tpLH
tpHL
Propagation Delay
PL to TC u or TC o
t pLH
tpHL
Propa9~ion
Delay
Pn to TC u or TC o
CL " SOpF
RL" soon
ts(H)
ts(L)
Setup Time,
HIGH or LOW
Pn to PL
tH(H)
tH(L)
Hold Time,
HIGH or LOW
Pn to PL
-
5.0
-
5.0
-
ns
twILl
PL Pulse Width,
LOW
-
20.0
-
25.0
-
ns
twILl
CPu or CPo
Pulse Width, LOW
-
15.0
-
20.0
-
ns
twILl
CPu or CPo
Pulse Width, LOW
(Change of Direction)
-
15.0
-
20.0
-
ns
tw(H)
MR Pulse Width,
HIGH
-
10.0
-
10.0
-
ns
Time
PL to CPu or CPo
-
15.0
-
20.0
-
ns
Recovery Time
MR to CPu or CPo
-
15.0
-
20.0
-
ns
tREC
tREC
~ecovery
5-42
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes
• 7ns typical data to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5fJW typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5fJA max.)
• Octal buffer/line driver with 3-state output
• 100% product assurance screening to MIL-STD-883, Class 8
is available
• JEDEC standard pinout for DIP and LCC
The IDT54174AHCT240 is an octal buffer/line driver built using
advanced CEMOS~, a dual metal CMOS technology. The device
is designed to be employed as a memory and address driver,
clock driver and bus-oriented transmitter/receiver which provides
improved board density.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
OEA
Vee
DA.
CEs
OS.
OAo
DA,
DB.
DB,
0A1
DA,
DB,
OB:z
0A:z
DA,
DB,
083
0A3
GND
DB,
OEA
SSDAHCT240-001
DA.
O'EB
DB.
OA.
DA,
DB.
DB,
OA,
DA,
DB,
082
CiA,
DA,
DB,
DB,
OA,
DIP
TOPYIEW
LJ LJLJ LJLJ
083
:9 8
7
6
5
43::
GND
::10
2::
083
::11
1~::
20.....
1t1 ~Ig
DB,
Vee
SSDAHCT24Q-003
!Ig
SSOAHCT24o-002
LCC
TOPYIEW
CEMOS is 8 trademark of Integrated Device Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
CI 1986 Integrated Device Technology, Inc.
Printed In the U.S.A.
5-43
IDT54/74AHCT240 HIGH-SPEED CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Term i nal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
'C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Vee ~ 5.0V ± 5%
Min. ~ 4.75V
Vee ~ 5.0V ± 10%
Min. = 4.50V
TA ~ O'C to +70°C
TA ~ -55°C to +125°C
VLe = 0.2V
VHe
~
Max.
Max.
5.25V (Commercial)
5.50V (Military)
~
~
Vee - 0.2V
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vee
0
Max .. V,N
~
Vee
-
-
5
p.A
I'L
Input LOW Current
Vee
0
Max., V,N
0
GND
-
Ise
Short Circuit Current
Vee
~
Max. (3)
Vee
~
3V, V,N
VOH
Output HIGH Voltage
SYMBOL
TEST CONDITIONS(1)
PARAMETER
Output LOW Voltage
~
3V, V,N
0
-5
p.A
-100
-
mA
VHe
Vee
-
10H
~
-150p.A
VHe
Vee
-
10H
~
-12mA MIL
2.4
4.3
-
VLe or VHe , I OH
Vee ~ Min.
V1N = V1H or V1L
Vee
VOL
0
-60
~
-32p.A
10H ~ -15mA COM
4.3
-
GND
VLe
10L
~
300p.A
-
GND
V Le
10L
~
14mA MIL
-
-
0.4
10L
~
24mA COM
-
-
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second
5-44
-
2.4
VLe or VHe , 10L ~ 300p.A
Vee ~ Min.
V,N ~ V,H or V'L
V
V
IDT54/74AHCT240 HIGH-SPEED CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC
=O.2V; VHC =vcc - O.2V
SYMBOL
Vee
leca
Quiescent Power Supply Current
TYP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
mAl
MHz
-
0.15
1.8
-
004
2.6
V,N 2 VHc:
V,N :5 VLe (AHCT)
-
0.3
2.0
=3.4Vor
=GND
-
2.3
8.4
TEST CONDITIONS(1)
PARAMETER
=Max.
V1N ;;:: VH6 V1N :::; VLC
=0
Vec =Max.
Y,N =3.4V(3)
Vee =Max.
Outputs Open
OE A =OEs =GND
MIN.
'i
ICCT
Power Supply Current
TTL Inputs HIGH
IceD
Dynamic Power Supply
Current
lee
Total Power Supply(4)
Current
One Input Toggling
50% Duty Cycle
Vec =Max.
Outputs Open
'i =1.0MHz
50% DlJ.!Y.Cyele
OE A =OEs =GND
One Bit Toggling
Vee =Max.
Outputs Open
'i =250KHz
50% DlJ.!Y.Cycle
OE A =OEs =GND
Eight Bits Toggling
V,N 2VHc;
V1N $ VLC
V,N 2VHe;
V,N :5 VLe (AHCT)
Y,N =3AV or
V ,N
=GND
mA
Y'N
Y'N
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV. +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc
= IQUIESCENT +
IINPUTS + [DYNAMIC
Icc = ICGQ + IccrDHNr + ICGD (fcp/2 + fiNi)
ICGQ = Quiescent Current
leeT = Power Supply Current for a TTL High Input (V 1N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT
=Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni
=Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-45
IDT54I74AHCT240 HIGH-SPEED CMOS OCTAL BUFFERILINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
OEA,OE B
Dxx
Oxx
3-State Output Enable Input (Active LOW)
Inputs
Outputs
INPUTS
OUTPUT
OE", OE.
D
L
L
H
L
H
X
H
L
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
tpHL
Propagatio!! Delay
ONto ON
tZH
tZL
Output Enable
Time
tHz
tLz
Output Disable
Time
CONDITION
C L = 50pf
RL = 5000
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
7.0
2.0
9.0
2.0
12.0
ns
15.0
5.0
18.0
5.0
20.0
ns
10.0
2.0
12.0
2.0
18.0
ns
5-46
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54174AHCT244 are octal buffer/line drivers built using
advanced CEMOS'·, a dual metal CMOS technology. The
devices are designed to be employed as memory and address
drivers, clock drivers and bus-oriented transmitters/receivers
which provide improved board density.
• 7ns typical data to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5/LW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5/LA max.)
• Octal buffer/line driver with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
ilEA
Vee
DA.
OEB
DB.
OA.
DA,
DB.
DB,
OA,
DA,
DB,
DB,
OA,
DA,
DB,
DB,
DA,
GND
DB,
OEA
SSD54fl4AHCT244-001
DIP
TOP VIEW
LJ LJ L J
L J LJ
OB3
::::9 8
43::
OBo
GND
::10
2:::
DAo
O~3
::::12
20:::
Vee
DB2
::1~4
7
6
5
DA.
OEB
DB.
OA.
DA,
DB.
DB,
OA,
DA,
DB,
DB,
OA,
DA,
DB,
DB,
OA,
DB,
,
15 16 17
r1 r1
n
1~9::
SS054/74AHGT244-0oc,
DEB
rl r1 /
SSD54/74AHCT244-002
Lee
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tel
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
5-47
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74AHCT244 HIGH-SPEED CMOS OCTAL BUFFER/LINE DRIVER
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
mA
120
NOTE:
I.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
V Le = 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
VHe = Vee - 0.2V
MIN.
TYP.(')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
I'H
Input HIGH Current
Vec
-
-
-60
-100
SYMBOL
I'L
Input LOW Current
Ise
Short Circuit Current
VOH
TEST CONDITIONS(')
PARAMETER
Output HIGH Voltage
=Max.• Y,N =Vee
Vee =Max., V,N = GND
Vee =Max. (31
Vee =3V, V,N = VLe or VHe,
Vee
=Min.
Y,N = V,H or V'L
Vee
VOL
Output LOW Voltage
10H = -32"A
=-150"A
10H =-12mA MIL
10H =-15mA COM
10H
=3V, V,N = VLe or VHe,
Vee =Min.
V ,N =V,H or V,L
10L
10L = 300"A
=300"A
10L =14mA MIL
10L =24mA COM
V
5
"A
-5
"A
mA
VHe
Vee
VHe
Vee
-
2.4
4.3
-
2.4
4.3
-
-
GND
VLe
GND
VLe
-
0.4
-
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-48
0.8
V
V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74AHCT244 HIGH-SPEED CMOS OCTAL BUFFER/LINE DRIVER
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
Icco
Quiescent Power Supply Current
Vcc = Max.
V,N ", VHC ; V,N :5 VLC
Ii =0
ICCT
Power Supply Current
Per TTL Inputs HIGH
Vcc = Max.
Y,N = 3.4V(3)
Icco
Icc
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V,N'" VHC
V,N :5 VLC
-
0.15
0.25
mAl
MHz
V,N'" VHC
V,N:5 VLC (AHCT)
-
0.15
1.8
Y,N = 3.4V or
V,N = GND
-
0.4
2.6
V,N'" VHC
V,N :5 VLC (AHCT)
-
0.3
2.0
Y,N = 3.4Vor
V'N=GND
-
2.3
8.4
TEST CONDITIONS(1)
PARAMETER
Vcc = Max.
Outputs Open
OE A = OE B = GND
One I nput Toggling
50% Duty Cycle
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
Ii = 1.0MHz
50% DLJ!Y.Cycle
OE A = OE B = GND
One Bit Toggling
Total Power Supply l 4)
Current
Vcc = Max.
Outputs Open
Ii = 250kHz
50% Duty Cycle
OE A = OE B = GND
Eight Bits Toggling
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCG = 5.0V. +25 0 C ambient and maximum loading.
3. Per TTL driven input (VIN
4.
=3.4V); all other inputs at Vee or GND.
+ 'INPUTS + 'DYNAMIC
Icc =IceQ + ICCTDHNT + IceD (fcp/2 + fjNj)
Icc = 'QUIESCENT
ICGQ
=Quiescent Current
teeT = Power Supply Current for a TTL High Input (V 1N
=3.4V)
DH = Duty Cycle for TTL Inputs High
NT
ICGD
=Number of TTL Inputs at DH
=Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OEA.OE B
Dxx
Oxx
INPUTS
DESCRIPTION
3-State Output Enable I nput (Active LOW)
Inputs
Outputs
OUTPUT
OEA.OE B
D
L
L
L
H
X
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpHL
Propagation Delay
DNtO ON
tZH
tZL
Output Enable
Time
tHz
tLZ
Output Disable
Time
tpLH
CONDITION
C L = 50pl
RL = 500n
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
7.0
3.0
10.0
3.0
13.0
ns
16.0
7.0
20.0
7.0
25.0
ns
10.0
2.0
13.0
2.0
18.0
ns
5-49
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 8ns typical data to output
The IDT54174AHCT245 are 8-bit non-inverting, bidirectional
buffers built using advanced CEMOS'·, a dual metal CMOS
technology. This bidirectional buffer has 3-state outputs and is
intended for bus-oriented applications. The Transmit/Receive
(T/R) input determines the direction of data flow through the
bidirectional transceiver. Transmit (active HIGH) enables data
from A ports to 8 ports. Receive (active LOW) enables data from
8 ports to A ports. The Output Enable input, when HIGH,
disables both A and 8 ports by placing them in High Z condition .
• IOL = 14mA over full military temperature range
• CMOS power levels (5pW typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5pA'max.)
• Non-inverting, buffer transceiver
• 100% product assurance screening to MIL-STD-883, Class 8
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
TiR
T/R -'(.::.')~r-...
Vee
OE
L----+-r-----+~-OE
·0
.,.,
Ao
.,.4
.,.5
A,
A,
A,
GND
SSDS4/74AHCT24S-001
A4
A~,
A,
As A5 A4 A3 A2
A,
LJ lJ LJ LJ L.J
A,
.,.,.5
7
:9 8
6
5
43:::
A,
:11
2:::
1:::::
T/R
:12
20:::::
Vee
:10
::1~4
"
8
4
19:
15 16 17 18
rl
(3)
(4)
(5)
(6)
·0
.,
.,
.,
.4
DIP
TOP VIEW
GND
(2)
(7)
(8)
(9)
·5
.,
.,
Ao
SSD54174AHCT24S-003
OE
r1 n r1
B3 82 B1 Bo
SSD54/74AHCT245-002
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
5-50
JULY 1986
Printed in U.S.A.
IDT54/74AHCT245 HIGH-SPEED CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
oto +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification Is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vee =5.0V ± 5%
Min.
TA =-55°C to +125°C
Vee =5.0V ± 10%
Min.
V Le = 0.2V
VHe = Vee - 0.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYp'I')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic LOW Level
V
I'H
Vec = Max., V,N = Vee
-
0.8
Input HIGH Current
(Except I/O Pins)
-
5
,..A
I,L
Input LOW Current
(Except I/O Pins)
Vee = Max., V,N = GND
-
-
-5
,..A
Ise
Short Circuit Current
Vee = Max. (3)
-60
-100
mA
VOH
Output HIGH Voltage
PortA and B
SYMBOL
TEST CONDITIONSI')
PARAMETER
VHe
Vee
10H =-150,..A
VHe
Vee
-
10H =-12mA MIL
2.4
4.3
-
10H =-15mA COM
2.4
4.3
-
-
GND
VLe
Vee = 3V, V,N = VLe or VHe, 10H = -32,..A
Vee = Min.
V,N = V,H or V,L
Vee = 3V, V,N = VLe or VHe , 10L = 300,..A
VOL
Output LOW Voltage
Port A and B
10L = 300,..A
Vee = Min.
V,N =V,H or V,L
10L =14mA MIL
10L = 24mA COM
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-51
-
GND
VLe
-
0.4
-
0.5
V
V
II
IDT54/74AHCT245 HIGH-SPEED CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vcc - O.2V
VLC = O.2V; VHC =
SYMBOL
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N ", VHc
V,N :5 VLC
-
0.15
0.25
Vcc = Max.
Outputs Open
Ii = 1.0MHz
50% Duty Cycle
OE= GND
One Bit Toggling
V,N ", VHC
V,N :5 VLC (AHCT)
-
0.15
1.8
V,N = 3.4Vor
V,N = GND
-
0.4
2.6
Vcc= Max.
Outputs Open
Ii = 250kHz
50% Duty Cycle
OE= GND
Eight Bits Toggling
V,N ", VHc
V,N :5 VLc (AHCT)
-
0.3
2.0
V,N = 3.4V or
V,N=GND
-
2.3
8.4
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc = Max.
V,N ", VHC ; V,N :5 VLC
Ii =0
ICCT
Power Supply Current
Per TTL Input HIGH
Vcc= Max.
V ,N = 3.4V(3)
Dynamic Power Supply Current
Vcc= Max.
Outputs Open
OE= GND
TiR" = GND or Vcc
One Input Toggling
50% Duty Cycle
Icco
Icc
Total Power Supply Current(4)
mAl
MHz
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc
= IOUlESCENT + I INPUTS + IDYNAMIC
Icc = ICCQ + IccTDHNr + ICCD (fcp/2 + fjNj)
Icco =Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V ,N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
f Cp
=Clock Frequency for Register Devices (Zero for Non·Register Devices)
fi = Input Frequency
Ni
=Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OE
TtR
Ao-A7
Bo-B7
TRUTH TABLE
INPUTS
DESCRIPTION
OE
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or
3-State Outputs
Side B Inputs or
3-State Outputs
L
L
H
OUTPUT
TIR
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
High Z State
H = HIGH Voltage Level
L ~ LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
tpHL
Propagation Delay
AtoB
BtoB
tZH
tZL
Output Enable
Time
tHZ
tLz
Output Disable
Time
tOLH
tOHL
Proe.agatlon Delay
TIR toAor B'
CONDITION
C L = 50 pI
RL = soon
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
8.0
3.0
10.0
3.0
15.0
ns
15.0
5.0
20.0
5.0
25.0
ns
11.0
2.0
15.0
2.0
18.0
ns
14.0
-
-
-
-
ns
*Guaranteed by Design
5-52
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes
The IDT54/74AHCT273 are octal D flip-flops built using
advanced CEMOS'·, a dual metal CMOS technology. The
IDT54/74AHCT273 has eight edge-triggered D-type flip-flops
with individual D inputs and 0 outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear)
all flip-flops simultaneously.
Ihe register is fully edge-triggered. The state of each D input,
one setup time before the LOW-to-HIGH clock transition, is
transferred to the corresponding flip-flop's 0 output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is
useful for applications where the true output only is required and
the Clock and Master Reset are common to all storage elements.
•
•
•
•
•
10ns typical clock to output
IOL = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
• Octal D flip-flop with clear
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
Mil
Vee
00
07
03
Do
07
GND
Cp
LJ lJ LJ LJ LJ
0,
0,
0,
o.
o.
Os
0,
0,
0,
D.
0,
D.
GND
CP
:::9 8
7
6
5
43:
Do
2'-
00
::10
iiR
vee
07
SSD54/74AHCT273-0D2
LCC
TOP VIEW
SSDS4174AHCT273-001
DIP
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
0,
0,
DO
0,
0,
CP--I>~~------~------~~-----'+-----~H-------~------~-------,
o
o
Q
00
o
Q
0,
o
0
o
Q
0,
0,
Q
o
o
Q
0,
o
Q
Q
0,
SSD54174AHCT273-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
5-53
JULY 1986
Printed in the U.S.A.
IDT54174AHCT273 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
T SIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
rnA
NOTE:
I. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
allect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
O·C to +70°C
Vcc = 5.0V ± 5%
Min. = 4.75V
TA = -55·C to +125°C
Vcc = 5.0V ± 10%
Min. = 4.50V
VLC = 0.2V
VHC =Vce - 0.2V
TA =
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2}
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
I'H
Input HIGH Current
Vee = Max .•
-
-
5
p.A
-5
p.A
-80
-100
-
rnA
SYMBOL
TEST CONDITIONS('}
PARAMETER
I'L
Input LOW Current
Y,N = VCC
VCC = Max .• Y,N = GND
Isc
Short Circuit Current
Vcc = Max. (3}
Vcc = 3V.
VOH
Output HIGH Voltage
Vcc= Min.
Y,N = V,H or V,L
Vcc = 3V.
VOL
Output LOW Voltage
Vcc
VHC
Vcc
10H = -1.0mA MIL
2.4
4.3
10H = -2.6mA COM
2.4
4.3
-
GND
VLC
10L = 300p.A
-
GND
VLC
10L = 14mA MIL
-
-
0.4
Y,N = VLC or VHC • 10L = 300p.A
Vcc = Min.
Y,N = V,H or V,L
10L = 24mA COM
NOTES:
1. For conditions shown 85 max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-54
-
VHC
10H = -150p.A
Y'N = VLC or VHC• 10H = -32p.A
-
V
-
0.5
V
IDT54174AHCT273 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; VHC = vcc - O.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc = Max.
V,N 2 VHC: V,N '" VLC
Icp=li =0
ICCT
Power Supply Current
Per TTL Inputs HIGH
Vcc = Max.
V,N = 3.4V (3 )
Dynamic Power Supply
Current
VCC = Max.
Outputs Open
MR = Vcc
One Bit Toggling
50% Duty Cycle
Iceo
Icc
Total Power Supply Current ")
V,N 2o VHC
V,N '" VLC
MIN.
TYP.(Z)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
-
0.15
0.25
mAl
MHz
-
0.15
1.8
-
0.65
3.4
Vcc = Max.
Outputs Open
Icp= 1.0MHz
50% Duty Cycle
MR = Vcc
One Bit Toggling
at Ii = 500kHz
50% Duty Cycle
V,N 2o VHc
Vcc = Max.
Outputs Open
Icp= 1.0MHz
50% Duty Cycle
MR= Vcc
Eight Bits Toggling
Ii = 250kHz
50% Duty Cycle
V,N 2o VHc
V,N '" VLc
(AHCT)
-
0.63
2.2
V,N = 3.4V
or
V,N = GND
-
2.88
9.4
V,N '" VLC
(AHCT)
V,N = 3.4V
or
V,N = GND
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (V 1N = 3.4V); all other inputs at Vee or GND.
4. Icc
= 'QUIESCENT
+ 'INPUTS + 'DYNAMIC
Icc = 'ceQ + ICCTDHNT + ICGD (fcp/2 + fjNj)
ICGQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V,N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-55
IDT54n4AHCT273 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINJnON OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
~D7
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
MR
CP
0 0-0 7
TRUTH TABLE
OUTPUT
INPUTS
OPERATING MODE
MR
CP
DN
Reset (Clear)
L
X
X
L
Load '1'
H
f
h
H
Load '0'
H
f
I
L
ON
H = HIGH Voltage steady state
h = HIGH Voltage Level one setup time prior to the LOW-toHIGH clock transition
L = LOW Voltage Level steady state
I =LOW Voltage Level one setup time prior to the LOW-toHIGH clock transition
X =Don't Care
I = LDW-to-HIGH clock transition
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
tpHL
Propagation Delay
CPtoO N
tpLH
tpHL
Propagation Delay
MR to Output
ts
Set UpTime
High or Low
Data toCP
CONDITION
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN_
MAX.
MIN.
MAX.
10.0
3.0
15.0
3.0
17.0
ns
12.0
4.0
18.0
4.0
21.0
ns
3.0
10.0
-
10.0
-
ns
0.6
1.0
-
1.0
-
ns
C L =50pf
RL = 500n
tH
Hold Time
High or Low
DatatoCP
tw
Clock Pulse Width
High or Low
10.0
16.0
-
16.0
-
ns
t REc
Recovery Time
MRtoCP
5.0
15.0
-
15.0
-
ns
5-56
FEATURES:
DESCRIPTION:
• Equivalentto ALS speeds and output drive overfull temperature
and voltage supply extremes
The IDT54174AHCT299 is an 8-bit universal shift register
built using advanced CEMOS'", a dual metal CMOS technology.
The IDT54174AHCT299 is an 8-bit universal shift/storage register with 3-state outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel
load inputs and flip-flop outputs are multiplexed to reduce the
total number of package pins. Additional outputs are provided
for flip-flops 0 0-07 to allow easy serial cascading. A separate
active LOW Master Reset is used to reset the register.
•
•
•
•
•
•
•
9ns typical clock to output
IOL = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
8-input universal shift register
100% product assu rance screening to MIL-STD-883, Class B is
available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
S.
Vee
0E1
S,
0E2
os,
1,0,
0,
1,0.
110,
I/o,
110,
I/O.
110,
D.
110,
Mii
CP
l J LJ L J L J LJ
Mn
7
6
5
43:::
GND
OS.
CP
1/01
OS.
GND
:::::9 8
S,
II
SSDFCT299-002
LCC
TOP VIEW
SSDFCT299-001
DIP
TOPYIEW
FUNCTIONAL BLOCK DIAGRAM
SSDFCT299-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CI 1986 Integrated Device Technology. Inc.
5-57
JULY 1986
Printed in U.SA
IDT54174AHCT299
HIGH-SPEED CMOS a-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
VTERM
Terminal
Voltage with
Respect to GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operation
Temperature
Oto +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output
Current
120
120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied,
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O·C to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(1)
PARAMETER
TYP'(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed LogiC Low Level
V
Input HIGH Current
Vee =Max., VIN ; Vee
5
p.A
IlL
Input LOW Current
Vee =Max., VIN ; GND
-
0.8
IIH
-
-5
p.A
Ise
Short Circuit Current
Vee; Max. (3)
-60
-100
-
mA
Vee; 3V, VIN ; VLe or VHO 10H; -32p.A
VOH
Output HIGH Voltage
Vee =Min.
V IN ; V IH or VIL
MIN.
VHe
Vee
10H; -200p.A
VHe
Vee
10H; -lOmA MIL
2.4
4.3
IOH ; -2.6mA COM'L
2.4
4.3
-
GND
VLe
GND
VLe
-
0.4
-
-10
-
10
Vee; 3V, VIN = VLe or VHe , IOL = 3oop.A
VOL
Output LOW Voltage
loz
Off State (High Impedance)
Output Current
IOL; 300p.A
Vee; Min.
VIN = VIH or VIL
Vee; Max.
IOL = 14mA MIL.
IOL = 24mA COM'L
Vo = OAV
Vo= 2.4V
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-58
V
V
0.5
p.A
IDT54174AHCT299
HIGH-SPEED CMOS B-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC =O.2V; VHC =vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
MIN.
TYP.(')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
mAl
MHz
VIN" VHC
VIN:'O VLC (AHCT)
-
0.15
1.8
VIN ~ 3.4V
orVIN~ GND
-
0.65
3.4
TEST CONDITIONS(')
PARAMETER
Vcc ~ Max.
VIN " VHC; VIN:'O VLC
Icp~li ~O
ICCT
ICCD
Icc
Power Supply Current
Per TTL Input HIGH
Vcc ~ Max.
V IN ~ 3.4V(3)
Dynamic Power Supply
Current
Vcc ~ Max.
Outputs Open
OE, ~ DE2 ~ GND
MR ~ Vcc
So ~ S, ~ Vcc
DS o ~ DS, ~ GND
One Bit Toggling
50% Duty Cycle
Total Power Supply Current(4)
Vcc ~ Max.
Outputs Open
Icp~ 1.0MHz
50% Dilly Cycle
OE, ~ OE 2 ~ GND
MR ~ Vcc
So~ S, ~ Vcc
DS o ~ DS 7 ~ GND
One Bit Toggling
at Ii ~ 500kHz
50% Duty Cycle
Vcc ~ Max.
Outputs Open
Icp ~ 1.0MHz
50% D.t!!Y. Cycle
DE, ~ DE2 ~ GND
MR ~ Vcc
80~ 8, ~ Vcc
D80~D8,~GND
Eight Bits Toggling
at Ii ~ 250kHz
50% Duty Cycle
VIN " VHC
V'NS; VLC
mA
VIN" VHC
VIN:'O VLC (AHCT)
-
0.63
2.2
VIN ~
VIN~
-
2.88
9.4
3.4V
GND
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc
= 'aUIESCENT + ',NPUTS + 'OYNAMIC
Icc = Icea + ICCTDHNT + ICCD (fcp/2 + fjNj)
ICGQ = Quiescent Current
teeT = Power Supply Current for a TTL High Input (V ,N = 3.4V)
DH
~
Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni
=Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-59
IDT54n4AHCT299
HIGH-SPEED CMOS a-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
CP
DS o
DS 7
So. S,
MR
OE,. OE,
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable I nputs (Active LOW)
Parallel Data I nputs or 3-State Parallel Outputs
Serial Outputs
110 0-1/0 7
0 0• 0 7
INPUTS
RESPONSE
MR
S,
S.
CP
L
H
H
H
H
X
H
L
H
L
X
H
H
L
L
X
I
I
I
X
Asynchronous Reset; 0 0-0 7 = LOW
Parallel Load; liON - ON
Shift Right; DS o - 0 0• 0 0 etc.
Shift Left; DS 7 0 7 - 0 6• etc.
Hold
a"
a,.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COMMERCIAL
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Delay
CP to Ooor 0 7
tpLH
tpHL
tpHL
tpHL
CONDITION
TYPICAL
MILITARY
UNITS
MIN
MAX
MIN
MAX
9.0
3.5
13.0
-
17.0
ns
Propagation Delay
CPto liON
8.0
4.0
15.0
-
15.0
ns
Pr:Qe.agation Delay
MRtoOoor0 7
9.0
4.5
13.0
-
15.0
ns
9.0
6.5
15.0
-
15.0
ns
10.0
3.5
14.0
-
18.0
ns
7.5
2.0
10.0
-
12.0
ns
Pro~ation
Delay
MRto lION
tZH
tZL
Outp.!!LEnable Time
OEto lION
tHZ
tLZ
Outp.!!!...Disable Time
OEto lION
ts
Setup Time HIGH or LOW
Soor S, to CP
4.0
8.5
-
8.5
-
ns
tH
Hold Time HIGH or LOW
Soor S, to CP
1.0
1.0
-
1.0
-
ns
ts
Setup Time HIGH or LOW
liON. DSoor DS 7 to CP
1.5
5.5
-
5.5
-
ns
tH
Hold Time HIGH or LOW
liON. DSoor DS 7 to CP
0
3.0
-
4.0
-
ns
tw
CP Pulse Width HIGH or LOW
8.0
8.0
-
ns
MR Pulse Width Low
8.0
8.0
8.0
-
ns
t REC
Recovery Time MR to CP
8.0
8.0
-
8.0
tw
8.0
-
ns
C L = 50 pf
RL = 500 n
5·60
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT373 are 8-bit latches built using advanced
CEMOS'", a dual metal CMOS technology. This octal latch has
3-state output and is intended for bus-oriented applications. The
flip-flops appear transparent to the data when Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE)
is LOW. When bE is HIGH, the bus output is in the high
impedance state.
• 10ns typical data to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5p.A max.)
• Octal transparent latch with enable
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
De
v"
00
0,
Do
0,
0,
0,
0,
0,
0,
0,
0,
GND
::10
LE
::11
0,
::12
0,
0,
0,
D.
0,
O.
GND
lE
03 D2 020, D1
LJ LJ LJ LJLJ
0,
::::9 8
~13
~
I.
7
5
6
Do
2:::
00
1~::
20::::
De
1~9::
0,
15 16 17
nr1n
43::::
r1
v"
r1
05 Os 0& 08 07
SSD54174AHCT373-001
SSOS4174AHCT373-002
DIP
LCC
TOPYIEW
TOPYIEW
FUNCTIONAL BLOCK DIAGRAM
DO
LE
0,
0,
0,
0,
0,
07
--~~~--~----+---~~---4----~----~----~----~---4~---+----~----+---~~---4----~
De --~~----~----+---~~---4----~----~----~----~---4~---+----~----+---~~---4----~
00
0,
0,
0,
0,
o.
0,
SSD54174AHCT373-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986 Integrated Device Technology,
rnc.
5-61
JULY 1986
Printed in U.S.A.
IDT54/74AHCT373 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
oto +70
-55 to +125
·C
TelAs
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stressesgreaterthanthose listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
VHe = Vee - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYp'I')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
V
V,L
Input LOW Level
Guaranteed Logic LOW Level
I'H
I,L
Input HIGH Current
Vce = Max., Y,N = Vec
Input LOW Current
Vcc = Max., Y'N = GND
-
-
-5
p.A
Ise
Short Circuit Current
Vce = Max. (3)
-60
-100
-
mA
VOH
Output HIGH Voltage
-
V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
VHC
Vee
10H = -150p.A
VHe
Vee
10H = -1.0mA MIL
2.4
4.3
10H = -2.6mA COM
2.4
4.3
-
GND
Vee = 3V, Y'N = VLe or VHe, 10H = -321'A
Vec= Min.
Y,N = V,H or V,L
Vec = 3V, Y,N = VLe or VHe , 10L = 300pA
VOL
Output LOW Voltage
10L = 300p.A
Vee = Min.
Y,N = V,H or V,L
10L = 14mA MIL
10L = 24mA COM
=
5.0V. +25°C ambient and maximum loading.
5-62
pA
VLe
VLC
-
0.4
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
V
5
GND
NOTES:
2. Typical values are at Vee
0.8
0.5
V
IDT54/74AHCT373 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =O.2V; vHC =vcc - O.2V
SYMBOL
leeQ
Quiescent Power Supply Current
Vee = Max.
V'N 2 VHe: V'N:5 VLe
Ii =0
leeT
Power Supply Current
Per TTL Inputs HIGH
Vee = Max.
V'N = 3.4V(3)
leCD
Dynamic Power Supply Current
Vee = Max.
Outputs Open
OE= GND
LE = Vee
One Input Toggling
50% Duty Cycle
Vee = Max.
Outputs Open
1,= 1.0MHz
50% Duty Cycle
OE=GND
LE = Vee
One Bit Toggling
Icc
Total Power Supply Current (4 )
TYP.(')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
mAl
MHz
-
0.15
1.8
V,N = 3.4V
or
V,N = GND
-
0.4
2.6
V'N2 VHe
V'N:5 VLe (AHCT)
-
0.3
2.0
-
2.3
8.4
TEST CONDITIONS(1)
PARAMETER
Vee - Max.
Outputs Open
Ii o 250kHz
50% Duty Cycle
OE = GND
LE 0 Vce
Eight Bits Toggling
V'N2 VHe
V1Ns:: VLC
V'N2 VHe
V'N:5 VLe (AHCT)
MIN.
mA
V'N
3.4V
or
V'N = GND
0
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25 D C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'QUIESCENT + 'INPUTS + 'OYNAMIC
Icc = 'CGQ + ICCTDHNT + ICGD (fcp/2 + fjNj)
ICGQ =
Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V,N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current caused
by an Input Transition pair (HLH or LHL)
fcp:: Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi :: Input Frequency
Ni :: Number of Inputs at fi
All currents are in mitliamps and all frequencies are in megahertz.
5-63
IDT54174AHCT373 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
0 0-0 7
LE
OE
Data Inputs
Latch Enables Input (Active HIGH)
Output Enables Input (Active LOW)
3-State Latch Outputs
0 0-0 7
TRUTH TABLE
INPUTS
OUTPUTS
D.
LE
OE
0.
H
L
H
H
X
X
L
L
H
H
L
Z
H = HIGH Voltage Level
l = LOW Voltage level
X = Don't Care
Z = HIGH Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Delay
ONto ON
tZH
tZL
Output Enable
Time
tHZ
tLZ
Output Disable
Time
tpLH
tpHL
Propagation Delay
LEto ON
ts
Set-up Time
HIGH or LOW
ONto LE
tH
tw
CONDITION
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
10.0
2.0
16.0
2.0
19.0
ns
15.0
5.0
20.0
5.0
24.0
ns
9.0
2.0
12.0
2.0
16.0
ns
20.0
6.0
23.0
6.0
27.0
ns
4.0
10.0
-
10.0
-
ns
Hold Time
HIGH or LOW
ONto LE
3.0
7.0
-
7.0
-
ns
LE Pulse Width
HIGH or LOW
7.0
10.0
-
10.0
-
ns
C L " 50 pf
RL" soon
5-64
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT374 are 8-bit registers built using advanced
CEMOS'", a dual metal CMOS technology. This register consists
of eight D-type flip-flops with a buffered common clock and
bu~ered three-state output control. When the output enable (OE)
inp~t is LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the three-state conditions.
Input data meeting the set-up and hold time requirements of
the D inputs is transferred to the 0 outputs on the LOW-to-HIGH
transition of the clock input.
•
•
•
•
•
•
•
10ns typical address to output delay
IOL = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
Octal D register (3-state)
100% product assurance screening to MIL-STD-833, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
Vee
00
07
00
07
01
06
01
06
02
Os
Os
02
03
04
03
04
GNO
CP
88~~o
01
01
02
02
03
l J LJ I ILJ l J
20 1918 :::
~43 2
U
:::5
1
17~
16~
:::6
:::7
1S:::
07
06
06
OS
Os
SSD54!74AHCT374~()()1
SSD54174AHCT374-002
OIP
TOP VIEW
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
Os
00
06
CP
CLOCK
OE
OUTPUT~I~~~~--~~~----~+-----+-+-----~~----~-+----~~----~
ENABLE
Os
00
06
07
SSOS4/74AHCT374-0D3
CEMOS is a trademark of I ntegrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
@19861ntegrated Device Technology, Inc.
Printed in the U.S.A.
5-65
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54174 AHCT374 HIGH-SPEED CMOS OCTAl 0 REGISTER (3-STATE)
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +1-0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
'Operating
Temperature
o to +70
-55 to +125
'C
T BIAS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
lOUT
DC Output Current
120
120
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vee =5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
= 4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
I'H
Input HIGH Current
Vcc
= Max., Y'N =Vcc
Vcc = Max., Y'N = GND
Vcc = Max. (3)
Vcc = 3V, Y,N = VLC or VHC,
-
-
5
p.A
SYMBOL
I,L
Input LOW Current
Isc
Short Circuit Current
VOH
TEST CONDITIONS(')
PARAMETER
Output HIGH Voltage
Vcc
Y'N
VOL
Output LOW Voltage
=Min.
=V,H or V,L
-5
p.A
-
rnA
10H = -32p.A
= -150p.A
VHC
Vcc
VHC
Vcc
-
10H
=-1.0mA MIL.
2.4
4.3
-
10H = -2.6mA COM'L
= 3V, Y,N =V LC or VHC ' 10L =300p.A
Vce
= Min.
10L
=V,H or V,L
-120
10H
Vcc
Y'N
-60
=300p.A
= 14mA MIL.
10L = 24mA COM'L.
IOL
2.4
4.3
-
-
GND
V LC
-
GND
V LC
-
-
0.4
-
-
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-66
V
V
IDT54174 AHCT374 HIGH-SPEED CMOS OCTAL D REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC =O.2V; VHC =vcc - O.2V
SYMBOL
TEST CONDITIONS!')
PARAMETER
Icco
Quiescent Power Supply Current
Vee ° Max.
V,N '" VHC ; V,N S VLC
Icpo/ioO
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc ° Max.
V,N ° 3.4V(3)
Dynamic Power Supply
Current
Vcc ° Max.
Outputs Open
OE ° GND
One Bit Toggling
50% Duty Cycle
Icco
Icc
Total Power Supply(4)
Current
Vcc = Max.
Outputs Open
Icp = 1.0MHz
50% Duty Cycle
OE = GND
One Bit Toggling
at Ii ° 500kHz
50% Duty Cycle
Vce ° Max.
Outputs Open
Icp ° 1.0MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
at Ii ° 250kHz
50% Duty Cycle
MIN.
TYP.!')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
0.15
0.25
V1N 2: VHC
V,NS VLC
V,N '" VHC
V,N S VLC
(AHCT)
-
0.15
1.8
V,N = 3.4V
or
V,N ° GND
-
0.65
3.4
V,N '" VHC
V,NS VLC
(AHCT)
-
0.63
2.2
V,N ° 3.4V
or
V,N ° GND
-
2.88
9.4
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (V1N = 3.4V); all other inputs at Vee or GND.
4.
Icc = lQUIESCENT + 'INPUTS + IDYNAMIC
Icc = ICGQ + ICCTDHNT + ICGD (fcp/2 + fiN;)
ICGQ
=
Quiescent Current
lecT::: Power Supply Current for a TTL High Input (V1N = 3.4V)
DH ° Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
f Cp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fj
=
Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-67
mAl
MHz
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54174 AHCT374 HIGH-SPEED CMOS OCTAL D REGISTER (3-STATE)
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0,
CP
0,
OE
DESCRIPTION
FUNCTION
The 0 flip-flop data inputs.
Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.
The register three-state outputs.
Output Control. An active-LOW three-state
control used to enable the outputs. A HIGH level
input forces the outputs to the high impedance
(off) state.
INPUTS
OUTPUTS
INTERNAL
OE
CLOCK
0,
0,
Q,
Hi-Z
H
H
L
H
X
X
Z
Z
NC
NC
LOAD
REGISTER
L
L
H
H
-..r
-..r
-..r
-..r
L
H
L
H
L
H
L
H
L
H
Z
Z
H =HIGH
L = LOW
X
=
Don't Care
Z = High Impedance
= LOW-la-HIGH Iransilion
NO =No Change
J
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITION
TYPICAL
MILITARY
COMMERCIAL
UNITS
MIN.
MAX.
MIN.
MAX.
tplH
tpHl
Propagation Delay
CPtoO N
10.0
3.0
16.0
3.0
18.0
ns
tZH
tZl
Output Enable Time
11.0
5.0
18.0
5.0
20.0
ns
tHZ
tlZ
Output Disable Time
9.0
2.0
18.0
2.0
24.0
ns
ts
Setup Time HIGH or LOW
ONto CP
2.0
10.0
-
10.0
-
ns
tH
Hold Time HIGH or LOW
°NtoCP
0.5
3.0
-
4.0
-
ns
tw
CP Pulse Width HIGH or LOW
10.0
14.0
-
16.5
-
ns
C l = 50 pi
Rl = 500 n
5-68
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT377 is an octal D flip-flop built using
advanced CEMOS'", a dual metal CMOS technology. The
I DT54174AHCT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and 0 outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously when the
Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop's
o output. The CE input must be stable only one setup time priorto
the LOW-to-HIGH clock transition for predictable operation.
•
•
•
•
•
•
•
10ns typical clock to output
IOL = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
Octal D flip-flop with clock enable
100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
03 0 2020101
CE
Vee
00
0,
Do
0,
lJ lJ L J LJ L j
0,
:::9 8
GND
:::10
0,
0,
CP
:::11
0,
0,
0,
:::12
0,
0,
0,
0,
0,
0,
0,
0,
0,
GND
CP
7
6
5
43::
Do
2:
00
1:==
CE
20;:::
Vee
19:::::
0,
Os 05060601
SSD54174FCT377-002
Lee
I
TOP VIEW
SSD54174FC1377-001
DIP
TOPYIEW
FUNCTIONAL BLOCK DIAGRAM
DO
0,
0,
0,
o
ep--~~~----~--------~---------~~------~+-------
00
0,
0,
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986lntegrated Device Technology, Inc.
0,
o.
0,
SSD54/74FCT377-003
CEMOS is a trademark of Integrated Device Technology, Inc.
5-69
JULY 1986
Printed in U.S.A.
IDT54174AHCT377 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
mA
NOTE:
I. Stresses greater than those /istedunder ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Vee: 5.0V ± 5%
Min. : 4.75V
Vec = 5.0V ± 10%
Min. : 4.50V
Max. =5.25V (Commercial)
Max. : 5.50V (Military)
TA: O°C to +70°C
TA : -55°C to +125°C
VLC: 0.2V
VHC : VCC - 0.2V
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
V
Input HIGH Current
Vee: Max., V,N : Vee
-
O.B
I'H
-
5
p.A
I,L
Input LOW Current
Vee: Max., V,N
Ise
Short Circuit Current
Vee: Max. (3)
SYMBOL
TEST CONDITIONS(!)
PARAMETER
Vee: 3V, V,N
VOH
Output HIGH Voltage
Output LOW Voltage
=-32p.A
-
-
-5
p.A
-60
-100
-
rnA
VHe
Vee
10H: -150p.A
VHe
Vee
10H = -1.0rnA MIL.
2.4
4.3
VLe or VHC' 10H
Vee = Min.
V,N : V,H or V'L
Vee: 3V, V,N
VOL
:
= GND
10H = -2.6rnA COM'L.
= VLe or VHe , 10L : 300p.A
10L = 300p.A
Vee: Min.
V ,N : V,H or V'L
10L: 14rnA MIL.
10L = 24rnA COM'L.
2.4
4.3
-
GND
VLe
GND
VLe
-
0.4
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-70
-
0.5
V
V
IDT54174AHCT377 HIGH·SPEED
CMOS OCTAL D FLlp·FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = 0.2V: v HC = vcc - 0.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc = Max.
V,N 2 VHC : V,N oS VLC
fcp = fi = 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V,N = 3AV(3)
ICCD
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
CE =GND
One Bit Toggling
50% Duty Cycle
Icc
Total Power Supply!')
Current
MIN.
TYP.!')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V ,N 2 VHC
V,N oS VLC
-
0.15
0.25
V,N 2 VHC
V,N '" VLC
(AHCT)
-
0.15
1.8
V,N = 3AV
or
V,N =GND
-
0.65
3.4
TEST CONDITIONS(1)
PARAMETER
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
CE =GND
One Bit Toggling
at fi = 500KHz
50% Duty Cycle
VCC = Max.
Outputs Open
Fcp = 1.0MHz
50% Duty Cycle
CE =GND
Eight Bits Toggling
at fi = 250KHz
50% Duty Cycle
mA
V,N 2 VHC
V,N '" VLC
(AHCT)
-
0.63
2.2
V,N = 3AV
or
V1N=GND
-
2.88
904
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN
4.
:::
3.4V); all other inputs at Vee or GNO.
Icc = 'QUIESCENT + 'INPUTS + 'DYNAMIC
Icc == 'CCQ + 'CCTOHNT + ICCD (fcp/2 + fiNj)
'cea = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V,N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5·71
mAl
MHz
IDT54174AHCT377 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
00-0 7
CE
00-0 7
CP
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DESCRIPTION
INPUTS
OPERATING MODE
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
OUTPUTS
CP
CE
Load "1"
t
I
DN
h
Load "0"
t
I
I
L
Hold (Do Nothing)
t
h
H
X
X
No Change
No Change
X
ON
H
=
H HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
L =LOW Voltage Level
I = LOW Voltage Level one setup time priortothe LOW-te-HIGH ClockTransition
X = Immaterial
I = LOW-to-HIGH Clock Transition
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
t pLH
IpHL
Propagalion Delay
CPIoO N
Is
Sel UpTime
HIGH or LOW
0Nlo CP
IH
Hold Time
HIGH or LOW
ONlo CP
CONDITION
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
10.0
4.0
18.0
4.0
20.0
s.o
6.0
-
6.0
-
ns
2.0
3.0
-
4.0
-
ns
3.0
S.O
-
5.0
-
ns
C L = SOp!
RL = soon
ns
Is
Sel UpTime
HIGH or LOW
CElo CP
IH
Hold Time
HIGH or LOW
CEloCP
2.0
6.0
-
8.0
-
ns
tw
Clock Pulse
Widlh. LOW
7.0
10.0
-
10.0
-
ns
5-72
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes
The IDT54174AHCT521 is an 8-bit identity comparator built
using advanced CEMOS", a dual metal CMOS technology. The
device compares two words of up to eight bits each and provides
a LOW output when the two words match bit for bit. The
expansion input I A =8 also serves as an active LOW enable input.
•
•
•
•
•
•
•
9ns typical propagation delay
IOl = 14mA over full military temperature range
CMOS power levels (5Jl.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5Jl.A max.)
8-bit identity comparator
100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
Vee
TA=B
Ao
OA=B
Bo
B7
A1
A7
B1
B6
A2
A6
B2
Bs
A3
As
B3
GND
B4
A4
SSDAHCT521-001
DIP
TOP VIEW
A3 B2 A2B1 A1
SSDAHCT521-003
LJ lJ lJ LJ LJ
B3
:9 8
7
6
5
43:
Bo
2;:: Au
GND
:10
A4
B4
As
:11
1:::=
:12
20 ::
TA=B
Vee
OA=B
Bs A6Ba A7B7
SSDAHCT521-002
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
c 1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
5-73
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDTS4/74AHCT521 HIGH-SPEED CMOS 8-BIT IDENTITYCOMPARATOR
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FOllowing Conditions Apply Unless Otherwise Specified:
TA =O·C to +70·C
Vee =5.0V ± 5%
Min.
TA =-55·C to +125·C
Vee =5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN,
TYP.("
MAX,
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
V
Input HIGH Current
Vee: Max., V,N : Vee
5
/LA
I'L
Input LOW Current
Vee: Max .• V,N : GND
-
0.8
I'H
-
-5
/LA
Ise
Short Circuit Current
Vee: Max. (3)
-60
-120
mA
VOH
Output HIGH Voltage
SYMBOL
TEST CONDITIONS(l)
PARAMETER
Vee
VHe
Vee
10H: -300/LA
VHe
Vee
-
10H: -12mA MIL.
2.4
4.3
-
I OH : -15mA COM'L.
2.4
4.3
-
-
GND
VLe
GND
VLe
-
0.4
-
0.5
=3V, V,N : VLe or VHe• 10H: -32/LA
Vee: Min.
V,N : V,H or V'L
Vee: 3V, V,N : VLe or VHe • 10L : 300/LA
VOL
Output LOW Voltage
10L: 300/LA
=
Vee Min.
V,N : V,H or V'L
10L
=14mA MIL.
10L: 24mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-74
V
V
IDT54/74AHCT521 HIGH-SPEED CMOS 8-BIT IDENTITYCOMPARATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
MIN.
TYP.!·)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V'N" VHC
V'N'; VLC
-
0.15
0.25
mAl
MHz
V'N" VHC
V'N'; VLC (AHCT)
-
0.15
1.8
V'N = 3.4V or
V'N = GND
-
0.4
2.6
TEST CONDITIONS!')
PARAMETER
ICCQ
Quiescent Power Supply Current
VCC = Max.
V'N" VHC: V'N ,; VLC
'i =0
ICCT
Power Supply Current
Per TTL Inputs HIGH
Vcc = Max.
V'N = 3.4V (3)
ICCD
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Icc
Total Power Supply (4)
Current
Vcc = Max.
Outputs Open
Ii = 1.0MHz
50% Duty Cycle
mA
NOTES:
1. For conditions shown as max. or min .. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at vee::: 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN
4.
:::
3.4V); all other inputs at Vee or GND.
+ 'INPUTS + 'DYNAMIC
Icc::: IceQ + IccTDHNr + ICGD (fcpl2 + fjNj)
ICGQ::: Quiescent Current
Icc::: 'QUIESCENT
'ceT::: Power Supply Current for a TTL High Input (V IN ::: 3.4V)
D H ::: Duty Cycle for TTL Inputs High
NT::: Number of TTL Inputs at DH
I CGD ::: Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Oevices (Zero for Non-Register Devices)
fi = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Ao-A7
~O-S7
IA .B
°A.B
TRUTH TABLE
INPUTS
DESCRIPTION
Word A inputs
Word S inputs
Expansion or Enable Input (Active LOW)
Identity Output (Active Low)
OUTPUT
IA • B
A,B
°A'B
L
L
H
H
A = S'
A"'S
A = S'
A"'S
L
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
• Ao ::: Bo. A,
=
B,. A2
=
B2. etc.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
t pHL
Propagation Qelay
AN or SN to 0 A • B
tpLH
tpHL
Pr~pagati~
Delay
IA • B to 0A. B
CONDITION
C L = 50 pI
RL =500n
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
9.0
-
13.0
-
17.0
ns
5.0
-
12.0
-
11.0
ns
5-75
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 11 ns typical clock to output
• IOL = 14mA over full military temperature range
• CMOS power levels (5/lW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5/l max.)
• Octal transparent latch with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
The IDT54/74AHCT533 are octal transparent latches built
using advanced CEMOS··, a dual metal CMOS technology. The
IDT54n4AHCT533 consist of eight latches with 3-state outputs
for bus organized system applications. The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH. When
LE is LOW, the data that meets the setup times is latched. Data
apJ'ears on the bus when the Output Enable (OE) is LOW. When
OE is HIGH, the bus output is in the high impedance state.
PIN CONFIGURATIONS
OE
Vee
o.
0,
D.
0,
0,
D.
0,
0,
o.
0,
Os
GND
:::10
0,
Os
0,
D.
0,
0,
GND
LE
D3 D2 02
'Of D1
LJ lJLJ LJLJ
~98
7
6
5
43::
D.
2::
LE
:11
1:::::
O.
OE
0,
:::12
20:::
Vee
D.
::1~4 15 16 17 1:9 :::
r1 n r1 n r1
0,
"-
Os 050606 D1
SSD54174FCT533~()()1
SSD54174FCT533-002
LCC
DIP
TOP VIEW
TOPYIEW
FUNCTIONAL BLOCK DIAGRAM
D.
0,
0,
0,
Os
D.
0,
LE --~~>---4----~~--~----~----4-----~--~----~----4-----~--~----~----4-----~--~
0,
0,
0,
Os
O.
0,
SSDAHCT533-003
CEMOS is a trademark of Integrated Oevice Technology. Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
c 1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
5-76
IDT54174AHCT533 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Termi nal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
Storage
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
= 4.75V
= 4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP.(')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V,l
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vee
= Max., V,N = Vee
Vec = Max., V,N =GND
Vee = Max. (3)
Vee =3V, V,N = Vle or VHe•
-
-
5
p.A
I'l
Input LOW Current
Ise
Short Circuit Current
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
10H
=-32p.A
10H = -150p.A
Vee = Min.
V1N '!': V tH or VtL
=-1.0mA MIL
10H = -2.6mA COM
Vee = 3V. V,N = Vle or VHe . 10l =300p.A
10L = 300l'A
Vee = Min.
10L = 14mA MIL
V,N = V,H or V,L
10L = 24mA COM
10H
-
-
-5
p.A
-60
-100
-
mA
-
VHe
Vee
VHe
Vee
-
2.4
4.3
2.4
4.3
-
-
GND
VLe
-
GND
VLe
-
-
0.4
-
-
0.5
NOTES:
1. For conditions shown 85 max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-77
V
V
V
IDT54174AHCT533 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc= Max.
V1N :2: VHC; VIN:5 VLC
Ii = 0
lecT
Power Supply Current
Per TTL Input HIGH
Vcc= Max.
V1N = 3.4V(3)
IceD
DynamiC Power Supply Current
Vcc= Max.
Outputs Open
OE=GND
LE = Vec
One Input Toggling
50% Duty Cycle
Vcc= Max.
Outputs Open
Ii = 1.0MHz
50% Duty Cycle
OE = GND
LE = Vce
One Bit Toggling
Icc
Total Power Supply Current(')
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
VIN:2:VHC
V1N:5 VLc
-
0.15
0.25
mAl
MHz
V1N :2:VHC
V1N :5 VLC (AHCT)
-
0.15
1.8
V1N = 3.4V
or
V1N=GND
-
0.4
2.6
V1N :2:VHC
V1N :5 VLC (AHCT)
-
0.3
2.0
V1N = 3.4V
or
V1N=GND
-
2.3
8.4
TEST CONDITIONS(!)
PARAMETER
Vcc= Max.
Outputs Open
Ii = 250KHz
50% Duty Cycle
OE =GND
LE = Vee
Eight Bits Toggling
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GNO.
4.
Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc:;:: ICCQ + IccrDHNr + IceD (fcp/2 + fjNj)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V1N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at 0H
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Oevices (Zero for Non-Register Oevices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-78
IDT54174AHCT533 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable I nput (Active LOW)
Complementary 3-State Outputs
Do-D7
LE
OE
0 0-0 7
TRUTH TABLE
INPUTS
OUTPUTS
ON
LE
OE
ON
H
L
X
H
H
X
L
L
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
Propagatio!:, Delay
DNto ON
tZH
tZl
Output Enable
Time
tHZ
tlZ
Output Disable
Time
tpLH
Propagatio!:, Delay
LE to ON
tpHL
CONDITION
C l " 50pf
R l " 500n
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
11.0
4.0
19.0
4.0
24.0
ns
15.0
4.0
18.0
4.0
20.0
ns
11.0
2.0
16.0
2.0
22.0
ns
23.0
4.0
28.0
ns
15.0
4.0
ts
Set Up Time
HIGH or LOW
DN to LE
7.0
15.0
-
15.0
-
ns
tH
Hold Time
HIGH or LOW
DN to LE
5.0
7.0
-
7.0
-
ns
tw
LE Pulse Width
HIGH or LOW
7.0
15.0
-
15.0
-
ns
tpHL
5-79
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT534 are octal D flip-flops built using
advanced CEMOS'·, a dual metal CMOS technology. The
IDT54174FCT534 are high-speed, low-power octal D-type flipflops featuring separate D-type inputs for each flip-flop and
3-state outputs for bus-oriented applications. A buffered Clock
(CP) and Output Enable (OE) are common to all flip-flops.
•
•
•
•
•
•
•
10ns typical clock to output
IOL = 14mA over full military temperature range
CMOS power levels (5/lW typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5/lA max.)
Octal D flip-flop with 3-state output
100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
a-
Vec
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
43::
Do
GND
:::10
2:::
0,
0,
0,
CP
:::11
1~::
0,
D.
O.
:::12
20::
0,
O.
GNO
CP
LJ lJLJ LJLJ
ih
::::9 8
7
6
5
aVee
05 Os 06 De D7
SSD54174FCT534-002
SSOS4174FCT534-001
LCC
DIP
TOP VIEW
TOPYIEW
FUNCTIONAL BLOCK DIAGRAM
0,
0,
0,
0,
0,
0,
CP--I>o---'-~----~-+----~~r-----~~----~-1------'-~-----'-+------'
0,
0,
0,
0,
o.
0,
0,
SSDFCT534-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
" 1986 Integrated Device Technology, Inc.
5-80
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74AHCT534 HIGH·SPEED CMOS OCTAL D FLlp·FLOP (3·STATE)
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TB1AS
Temperature
Under Bias
-55.to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee =5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee =5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP.!·)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
-
IIH
Input HIGH Current
Vcc =Max., V,N
-
-
-5
p.A
-60
-120
-
mA
-
SYMBOL
I,L
Input LOW Current
Ise
Short Circuit Current
VOH
TEST CONDITIONS(1)
PARAMETER
Output HIGH Voltage
=Vee
Vee =Max., V,N =GND
Vee =Max. (3)
Vee =3V, V,N = VLe or VHe,
Vee =Min.
V,N =V,H or V,L
10H =-32p.A
Output LOW Voltage
p.A
VHe
Vee
VHe
Vee
-
10H =-1.OmA MIL.
2.4
4.3
-
10H =-2.6mA COM'L.
=VLe or VHe, 10L =300p.A
10L =300p.A
Vee =Min.
10L =14mA MIL.
V,N =V,H or V,L
10L =24mA COM'L.
2.4
4.3
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
V
-
-
GND
VLe
-
GND
VLe
-
0.4
-
-
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
5·81
V
5
10H =-150p.A
Vee =3V, V,N
VOL
0.8
V
IDT54174AHCT534 HIGH-SPEED CMOS OCTAL D FLIP-FLOP (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc = Max.
Y'N 2: VHC; V,N ,; VLC
Icp=li=O
ICCT
Power Supply Current
TTL Inputs HIGH
Vcc= Max.
Y,N = 3.4V(4)
Icco
Dynamic Power Supply Current
VCC = Max.
Outputs Open
OE =GND
One Bit Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
Icp= 1.0MHz
50% Duty Cycle
OE = GND
One Bit Toggling
at I; = 500KHz
50% Duty Cycle
Icc
Total Power Supply Current (4 )
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V,N 2: VHC
Y,N'; VLC
-
0.15
0.25
mAl
MHz
V,N 2: VHc
V,N '; VLC (AHCT)
-
0.15
1.8
Y,N = 3.4V
or
V,N = GND
-
0.65
3.4
V,N 2: VHc
V,N '; VLc (AHCT)
-
0.63
2.2
Y,N = 3.4V
or
V,N=GND
-
2.88
9.4
TEST CONDITIONS(1)
PARAMETER
Vcc = Max.
Outputs Open
Icp = 1.0MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
at I; = 250KHz
50% Duty Cycle
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25 D C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4.
Icc = IQUIESCENT
Icc
+ 'INPUTS + 'DYNAMIC
=Icca + iccrOHNT + IceD (fcp/2 + fjNj)
ICCQ = Quiescent Current
'CCT = Power Supply Current for a TTL High Input (V,N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi
Nj
=Input Frequency
=Number of Inputs at fj
All currents are in milliamps and all frequencies are in megahertz.
5-82
IDT54174AHCT534 HIGH-SPEED CMOS OCTAL 0 FLIP-FLOP (S-STATE)
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0-07
CP
OE
0 0-07
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DESCRIPTION
INPUTS
FUNCTION
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-State Output Enable Input (Active LOW)
Complementary 3-State Outputs
OUTPUTS
INTERNAL
X
X
ON
Z
Z
NC
NC
L
H
L
H
H
L
Z
Z
H
L
H
L
OE
CP
0,
Hi-Z
H
H
L
H
LOAD
REGISTER
L
L
H
H
-'
-'
-'
I
-'
a,
H
L
X
Z
= H'GH
= LOW
= Don't Care
= High Impedance
f =LOW-to-HIGH transition
NC = No Change
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tplH
tpHl
Propagatio!!. Delay
CPtoO N
tZH
tZl
Output Enable
Time
tHZ
tlZ
Output Disable
Time
CONDITION
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
10.0
3.0
16.0
3.0
18.0
ns
11.0
5.0
18.0
5.0
20.0
ns
11.0
2.0
14.0
2.0
16.0
ns
2.0
10.0
-
10.0
-
ns
C l = 50 pI
ts
Set UpTime
HIGH or LOW
DNtoCP
tH
Hold Time
HIGH or LOW
ONto CP
0.5
3.0
-
4.0
-
ns
tw
CP Pulse Width
HIGH or LOW
7.0
14.0
-
16.0
-
ns
Rl = 500n
5-83
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT573 are 8-bit latches built using advanced
CEMOS'·, a dual metal CMOS technology. This octal latch has
3-state outputs and is intended for bus-oriented applications.
The flip-flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the bus output is in the
high impedance state.
• 1Ons typical data to output delay
• IOL = 14mA over full military temperature range
•
•
•
•
•
CMOS power levels (5/lW typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5J1.A max.)
Octal transparent latch with enable
100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
Vce
Do
0,
00
0,
O2
O2
03
D.
03
O.
Os
Os
06
0,
.GND
06
0,
CCO"'QQ
LJ LJ LJ LJLJ
0,
GND
:9 8
7
•
5
43:
:10
LE
LE
0,
2:: Do
Of
0,
Vee
O.
00
00000
DIP
LCC
TOP VIEW
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
Do
0,
0,
0,
D.
05
06
0,
LE ---i~>---~----t---~~---1----~-----r----~----r---~~---t----~----t---~~---1----~
OE ---q~----~----t---~~---1----~-----r----~----r---~~---t----~----+---~~--~----~
00
0,
0,
0,
0,
0,
0,
SSD54/74AHCT373-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.SA
5-84
IDT54174AHCT573 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stressesgreaterthan those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O·C to +70·C
Vee = 5.0V ± 5%
Min.
TA = -55·C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MAX.
UNIT
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current
=Max., VIN =Vee
Vee =Max., VIN =GND
Vee =Max. (3)
Vee =3V, V'N =VLe or VHe,
-
0.8
IIH
-
5
p.A
VHe
Vee
10H
VHe
Vee
2.4
4.3
PARAMETER
IlL
Input LOW Current
Ise
Short Circuit Current
VOH
VOL
TEST CONDITIONSI')
TYp'I')
VIH
Output HIGH Voltage
Output LOW Voltage
Vee
10H =-32p.A
=-150p.A
Vee =Min.
10H =-1.0mA MIL
V IN =VIH or VIL
10H =-2.6mA COM
Vee =3V, V'N =VLe or VHe , 10L =300p.A
10L =3OOl'A
Vee =Min.
10L =14mA MIL
V'N =V'H or VIL
10L =24mA COM
MIN.
-60
-100
p.A
mA
2.4
4.3
-
-
GND
VLe
-
GND
VLC
-
0.4
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-B5
-5
-
0.5
V
V
IDT54174AHCT573 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =O.2V; VHC =vcc - O.2V
SYMBOL
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
VIN"VHC
VIN :5 VLC
-
0.15
0.25
Vcc= Max.
Outputs Open
1;= 1.0MHz
50% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling
VIN"VHC
VIN :5 VLC (AHCT)
-
0.15
1.8
VIN = 3.4V
or
VIN=GND
-
0.4
2.6
Vcc = Max.
Outputs Open
I; = 250KHz
50% Duty Cycle
OE = GND
LE = Vee
Eight Bits Toggling
VIN" VHC
VIN :5 VLC (AHCT)
-
0.3
2.0
VIN = 3.4V
or
VIN = GND
-
2.3
8.4
TEST CONDITIONS(1)
PARAMETER
I ceo
Quiescent Power Supply Current
Vcc= Max.
VIN " VHC; VIN :5 VLC
Ii =
ICCT
Power Supply Current
TTL Inputs HIGH
Vcc= Max.
VIN = 3.4V(3)
ICCD
Icc
Dynamic Power Supply Current
a
Vcc= Max.
Outputs Open
OE =GND
LE = Vcc
One Input Toggling
50% Duty Cycle
Total Power Supply Current(4)
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25 0 C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4.
='OUIESCENT + 'INPUTS + 'DYNAMIC
=ICGQ + ICCTDHNT + ICGD (fcp/2 + fjNj)
'CGQ =Quiescent Current
Icc
Icc
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT
ICGD
=Number of TTL Inputs at DH
=Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Oevices (Zero for Non-Register Devices)
fi
Ni
mN
MHz
=Input Frequency
=Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-86
IDT54174AHCT573 HIGH-SPEED CMOS OCTAL TRANSPARENT LATCH
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0 -0 7
LE
OE
0 0 -0 7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DESCRIPTION
INPUTS
Data Inputs
Latch Enables Input (Active HIGH)
Output Enables Input (Active LOW)
3-State Latch Outputs
H =HIGH Voltage Level
L =LOW Voltage Level
X = Don't Care
Z = HIGH Impedance
OUTPUTS
On
LE
OE
On
H
L
X
H
H
X
L
L
H
H
L
Z
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITION
TYPICAL
COMMERCIAL
MILITARY
MIN.
MAX.
MIN.
MAX.
UNITS
tplH
t pHl
Propagation Delay
ON to ON
10.0
2.0
14.0
2.0
15.0
ns
tZH
tZl
Output Enable
Time
15.0
4.0
18.0
4.0
21.0
ns
tHZ
tlz
Output Disable
Time
9.0
2.0
13.0
2.0
15.0
ns
tplH
t pHl
Propagation Delay
LE to ON
20.0
8.0
20.0
8.0
27.0
ns
4.0
10.0
-
10.0
-
ns
C l = 50 pi
Rl = soon
ts
Set-up Time
HIGH or LOW
ON to LE
tH
Hold Time
HIGH or LOW
ON to LE
3.0
7.0
-
7.0
-
ns
tw
LE Pulse Width
HIGH orLOW
7.0
10.0
-
10.0
-
ns
5-87
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54174AHCT574 are 8,bit registers built using advanced
CEMOS'", a dual metal CMOS technology. This register consists
of eight D,type flip,flops with a buffered common clock and
buffered thre9"state output control. When the output enable (OE)
input is LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the thre9"state conditions.
Input data meeting the set,up and hold time requirements of
the D inputs is transferred to the 0 outputs on the LOW,to,HIGH
transition of the clock input.
•
•
•
•
•
•
•
10ns typical address to output delay
IOL = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
Octal D register (3,state)
100% product assurance screening to MIL,STD,833, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
Do
D,
D2
D3
D.
Ds
D8
D7
GND
Vee
00
0,
Q cl~
O2
03
O.
D2
D3 ::5
D. ::6
05 ::7
14'0 6 ""8
- 9 10 11 12 13 ~
05
08
07
::fo
0,
O2
03
O.
05
r1 r1 rlr1 rl
c~fjoo
CP
CI
DIP
LCC
TOP VIEW
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
DO
05
06
07
CP
CLOCK~~~~-+""""""""~-+""""""""~-+""""""""~-r""""""""~-r""""""""~-r""""""""~-r"""""""",
OE
OUTPUT~I~~~r-""""""""~+-""""""""*-+-""""""""1-~""""""""~-r""""""""~~""""""""~~r-""""~
ENABLE
00
05
06
SS054/74AHCT374-003
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
@1986 Integrated Device Technology. Inc.
Printed in the U.S.A.
5--88
IDT54/74AHCT574 HIGH-SPEED CMOS OCTAL D REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
'C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
lOUT
DC Output Current
120
120
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vcc = 5.0V ± 5%
Min. = 4.75V
TA = -55'C to +125°C
Vce = 5.0V ± 10%
Min. = 4.50V
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS!11
PARAMETER
MIN.
TYP'!2j
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V'l
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vce
=Max., V,N =Vee
Vee =Max., V,N =GND
Vee =Max. (3)
Vee =3V, V,N =Vle or VHe,
-
-
5
I'A
-60
-120
I'l
Input LOW Current
Ise
Short Circuit Current
VOH
Output HIGH Voltage
Vee =Min.
V,N =V,H or V'l
Output LOW Voltage
VHC
Vce
VHe
Vee
10H =-1.0mA MIL.
2.4
4.3
-
10H =-2.6mA COM'L.
2.4
4.3
-
=3V, V,N =Vle or VHe , 10l =3OOl'A
10l =300l'A
Vee =Min.
10l = 14mA MIL.
V,N =V,H or V'l
10l =24mA COM'L.
-
GND
Vle
-
GND
Vle
-
-
0.4
-
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Not more than one outlfut should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-89
I'A
rnA
10H =-1501'A
Vee
VOL
-5
-
10H =-321'A
V
V
V
II
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54n4AHCT574 HIGH-SPEED CMOS OCTAL D REGISTER (3-STATE)
POWER SUPPLY CHARACTERISTICS
VLC
=O.2V; VHC =Vec - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc= Max.
V'N 2 VHc: V'N '" VLC
Icp= Ii = 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V'N = 3.4V(3)
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
OE =GND
One Bit Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply(4)
Current
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V'N 2V HC
V'N'" VLC
-
0.15
0.25
V,N2VHC
V'N '" VLC
(AHCT)
-
0.15
1.8
V'N = 3.4V
or
V'N=GND
-
0.65
3.4
V'N2 VHC
V'N'" VLC
(AHCT)
-
0.63
2.2
V'N = 3.4V
or
V'N= GND
-
2.88
9.4
TEST CONDITIONS(1)
PARAMETER
Vcc = Max.
Outputs Open
Icp= 1.0MHz
50% Duty Cycle
OE =GND
One Bit Toggling
at Ii = 500kHz
50% Duty Cycle
Vcc = Max.
Outputs Open
Icp= 1.0MHz
50% Duty Cycle
OE =GND
Eight Bits Toggling
at Ii = 250kHz
50% Duty Cycle
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.Ov, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'QUIESCENT + 'INPUTS + 'DYNAMIC
Icc = ICGQ + IccTDHNr + ICGD (fcp/2 + fjNj)
Iceo = Quiescent Current
ICCT = Power Supp'y Current for a TTL High Input (V'N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-90
mAl
MHz
IDT54174AHCT574 HIGH-SPEED CMOS OCTAL D REGISTER (3-STATE)
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0,
CP
01
OE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DESCRIPTION
FUNCTION
The 0 flip-flop data inputs.
Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.
The register three-state outputs.
Output Control. An active-LOW three-state
control used to enable the outputs. A HIGH level
input forces the outputs to the high impedance
(off) state.
OUTPUTS
INPUTS
INTERNAL
OE
CLOCK
D,
0,
0,
Hi-Z
H
H
L
H
X
X
Z
Z
NC
NC
LOAD
REGISTER
L
L
H
H
....r
....r
....r
....r
L
H
L
H
L
H
Z
Z
L
H
L
H
H
L
X
Z
=HIGH
= LOW
=Don't Care
=
High Impedance
J = lOW-ta-HIGH transition
NC = No Change
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
CONDITION
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
tpL.H
tpHl
Propagation Delay
CP to ON
10.0
4.0
14.0
4.0
15.0
ns
tZH
tZl
Output Enable Time
11.0
4.0
lB.O
4.0
21.0
ns
tHZ
tlZ
Output Disable Time
9.0
2.0
12.0
2.0
15.0
ns
ts
Setup Time HIGH or LOW
ON to CP
2.0
15.0
-
15.0
-
ns
tH
Hold Time HIGH or LOW
ONto CP
0.5
4.0
-
4.0
-
ns
tw
CP Pulse Width HIGH or LOW
10.0
14.0
-
16.5
-
ns
C l ' 50 pf
R l '50011
5-91
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
The IDT54/74AHCT640 are 8-bit inverting buffer transceivers
built using advanced CEMOS'", a dual metal CMOS technology.
These octal bus transceivers are designed for asynchronous
two-way communication between data buses. The devices
transmit data from the A bus to the 8 bus or from the 8 bus to the
A bus depending upon the level at the direction control (TiR)
input. The enable input (OE) can be used to disable the device so
the buses are effectively isolated.
•
•
•
•
•
10ns data to output
IOl = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
80th CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
• Inverting buffer transceiver
• 100% product assurance screening to MIL-STD-883, Class 8
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
TtR
Vee
AD
DE
A,
Bo
A,
B,
T/R
'----++--....,.=-DE
AD
A,
B,
A,
B,
As
B,
A,
Bs
A,
B,
GND
B,
(1)
(2)
Bo
A,
(3)
B,
A,
(4)
B,
A,
(5)
B,
SSD54174AHCT64()-'OO1
A,
(6)
DIP
B,
TOP VIEW
As
(7)
Bs
A,
(8)
B,
LJLJLJLJLJ
AT
GND
:9 8
7
6
5 43:
A,
2:::
Ao
::10
A,
(9)
B,
SSD54/74AHCT640-003
SSD54174AHCT64()-'002
LCC
TOPYIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
5-92
JULY 1986
Printed In U.S.A.
IDT54174AHCT640 HIGH-SPEED CMOS
OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
-55 to +125
-65 to +155
·C
120
120
rnA
TSTG
lOUT
Storage
Temperature
DC Output Current
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
V Le = 0.2V
VHe = Vee - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP.(")
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
lice = Max., Y,N = Vee
-
5
!lA
I'L
Input LOW Current
Vee = Max" Y,N = GND
-
-
-5
!,A
Ise
Short Circuit Current
Vee = Max. (3)
-80
-100
-
rnA
SYMBOL
TEST CONDITIONS(')
PARAMETER
VHe
Vee
IOH = -150!,A
VHe
Vee
-
10H = -12mA MIL
2.4
4.3
-
10H = -15mA COM
2.4
4.3
-
-
GND
VLe
10L = 300!,A
-
GND
VLe
10L = 14mA MIL
-
-
0.4
10L = 24mA COM
-
-
0.5
Vee = 3V, Y,N = VLe or VHO IOH = -32!,A
VOH
Output HIGH Voltage
Vee = Min.
Y,N = V,H or V'L
Vee = 3V, Y,N = VLe or VHe , 10L = 3oo!lA
VOL
Output LOW Voltage
Vee = Min.
Y,N = V,H or V,L
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-93
V
V
IDT54/74AHCT640 HIGH-SPEED CMOS
OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; VHC = vcc - O.2V
SYMBOL
I ceo
Quiescent Power Supply Current
Vcc= Max.
VIN 20 VHC ; VIN $ VLC
Ii =0
ICCT
Power Supply Current
Per TTL Input HIGH
Vcc= Max.
V IN = 3.4V(3)
Dynamic Power Supply Current
Vcc= Max.
Outputs Open
OE=GND
T/R = GND or Vcc
One Input Toggling
50% Duty Cycle
Icco
Icc
MIN.
TYP.!')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
VIN? VHC
VIN$VLC
-
0.15
0.25
mAl
MHz
VIN? VHC
VIN $ VLC (AHCT)
-
0.15
1.8
VIN = 3.4V or
VIN = GND
-
0.4
2.6
VIN? VHC
VIN $ VLC (AHCT)
-
0.3
2.0
VIN = 3.4V or
VIN = GND
-
2.3
8.4
TEST CONDITIONS!')
PARAMETER
Total Power Supply Current!')
Vcc= Max.
Outputs Open
Ii = 1.0MHz
50% Duty Cycle
OE =GND
One Bit Toggling
Vcc = Max.
Outputs Open
Ii = 250kHz
50% Duty Cycle
OE =GND
Eight Bits Toggling
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vce or GND.
4.
Icc::= 'QUIESCENT + 'INPUTS + 'DYNAMIC
Icc == ICCQ + IccrDHNr + ICCD Cfcp/2 + fjNj)
'CCQ::= Quiescent Current
ICCT = Power Supply CUrrent for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT == Number of TTL Inputs at DH
ICCD == Dynamic Current caused by an Input Transition pair (HLH or lHL)
fcp == Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi == Input Frequency
Ni == Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DE
T/R
Ao-A7
Bo-B7
FUNCTION TABLE
INPUTS
DESCRIPTION
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or
3-State Outputs
Side B Inputs or
3-State Outputs
OE
L
L
H
OPERATION
TtR
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
Isolation
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
PARAMETER
tpLH
tpHL
Propagation Delay
AtoBor
BtoA
tZH
tZL
Output Enable
Time
tHz
tLZ
Output Disable
Time
CONDITION
C L = 50 pI
RL = 500 n
TYPICAL
COMMERCIAL
MILITARY
UNITS
MIN.
MAX.
MIN.
MAX.
10.0
2.0
11.0
2.0
14.0
ns
15.0
5.0
24.0
5.0
27.0
ns
12.0
2.0
15.0
2.0
20.0
ns
5-94
FEATURES:
DESCRIPTION:
• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 8ns typical data to output delay
The IDT54174AHCT645 are 8-bit non-inverting buffer transceivers built using advanced CEMOS'·, a dual metal CMOS
technology. These non-inverting buffer transceivers are designed
for asynchronous two-way communication between data buses.
The devices transmit data from the A bus to the 8 bus or from the
8 bus to the A bus, depending upon the level at the direction
control (TiFi) input. The enable input (OE) can be used to disable
the device so the buses are effectively isolated.
•
•
•
•
IOL = 14mA over full military temperature range
CMOS power levels (5p.W typo static)
80th CMOS and TTL output compatible
Substantially lower input current levels than ALS (5p.A max.)
• Non-inverting buffer transceiver
• 100% product assurance screening to MIL-STD-883, Class 8
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
T/R
T/R
Vee
(1)
liE
AD
(19)
.,.,
.0
A,
A,
AD
.,.,
.,.,
A,
A,
As
A,
(18)
A,
·s
A,
GND
(3)
(17)
A,
.0
.,
(4)
(16)
A,
DE
(2)
a
B,
(5)
(15)
B,
SSD54174AHCT645-001
A,
(6)
(14)
A,
B,
(7)
(13)
·s
A,
A6 As A4 A3 A2
LJ LJ LJ
A,
.,.,
:::9 8
7
6
(8)
(12)
LJLJ
5
43::
2:::
A,
A,
AD
GND
:::10
B,
:11
1::::::
T/R
:::12
20::::
Vee
.,
(0)
(11)
B,
SSD54n4AHCT645-003
liE
SSD54fl4AHCT645-002
LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in the U.S.A.
5-95
IDT54/74AHCT645 HIGH-SPEED CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
VHe = Vee - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP.!')
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
-
0.8
V
IIH
Input HIGH Current
(Except I/O Pins)
Vce = Max .• VIN = Vee
-
-
5
I'A
IlL
Input LOW Current
(Except I/O Pins)
Vce = Max .• VIN = GND
-
-
-5
I'A
Isc
Short Circuit Current
Vec = Max. (3)
-60
-100
-
rnA
-
SYMBOL
TEST CONDITIONS!')
PARAMETER
VHC
Vce
10H = - 15OI'A
VHC
Vee
10H = -12mA MIL
2.4
4.3
10H = -15mA COM
2.4
4.3
-
GND
VLC
GND
VLC
-
0.4
Vcc = 3V. VIN = VLC or VHC• 10H = -321'A
VOH
Output HIGH Voltage
Vce= Min.
VIN = VIH or VIL
Vec = 3V. VIN = VLe or VHC• 10L =300l'A
VOL
Output LOW Voltage
Vce =Min.
VIN = VIH or VIL
10L =300l'A
10L =14mA MIL
10L =24mA COM
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-96
-
0.5
V
V
IDT54174AHCT645 HIGH-SPEED CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =O.2V; VHC =vcc - O.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc= Max.
V,N ", VHO Y,N " VLC
Ii = 0
ICCT
Power Supply Current
Per TTL Input HIGH
Vcc = Max.
V IN = 3.4V(3)
ICCD
Dynamic Power
Supply Current
Vcc = Max.
Outputs Open
OE = GND
TiR' = GND or Vcc
One Input Toggling
50% Duty Cycle
Icc
VCC = Max.
Outputs Open
Ii = 1.0MHz
50% Duty Cycle
OE =GND
One Bit Toggling
Total Power Supply(')
Current
Vcc = Max.
Outputs Open
Ii = 250kHz
50% Duty Cycle
OE =GND
Eight Bits Toggling
MIN.
TYP'(2)
MAlt
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N",VHC
V,N" VLC
-
0.15
0.25
V,N",VHC
V,N " VLC (AHCT)
-
0.15
1.8
Y,N = 3.4V
orV,N = GND
-
0.4
2.6
V,N",VHC
V,N " VLC (AHCT)
-
0.3
2.0
Y'N = 3.4V
orV,N=GND
-
2.3
8.4
mAl
MHz
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
Icc = 'QUIESCENT
4.
+ 'INPUTS + 'DYNAMIC
Icc = ICGQ + ICCTDHNT + ICGD (fCp/2 + fjNj)
ICGQ =
leeT
Quiescent Current
=Power Supply Current for a TTL High Input (VtN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fj
AU currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OE
T/R
Ao-A7
Bo-B7
FUNCTION TABLE
DESCRIPTION
INPUTS
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or
3-State Outputs
Side B Inputs or
3-State Outputs
OE
L
L
H
TIR
L
H
X
OPERATION
Bus B Data to Bus A
Bus A Data to Bus B
Isolation
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
tpLH
tpHL
PARAMETER
Propagation Delay
AtoB
B toA
tZH
tZL
Output Enable
Time
tHZ
tLZ
Output Disable
Time
Propagation Delay
tOLH
T/RtoAorB'
tOHL
Guaranteed by DeSign
.
CONDITION
C L = 50 pI
RL =500n
TYPICAL
MILITARY
COMMERCIAL
UNITS
MIN.
MAX.
MIN.
MAX.
8.0
3.0
10.0
3.0
15.0
ns
15.0
5.0
20.0
5.0
25.0
ns
11.0
2.0
15.0
2.0
18.0
ns
15.0
-
5-97
-
-
-
ns
FEATURES:
DESCRIPTION:
• IDT54174FCT138 equivalent to FAST~ speed;
IDT54174FCT138A 35% faster than FAST'·
• Equivalent to FAST'· output drive over full
temperature and voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FAST'·
(5p.A max.)
• 1-of-8 decoder with enables
• 100% product assurance screening to MIL-STD-883, Class B
is available
The IDT54174FCT138 and IDT54174FCT138A are 1-of-8
decoders built using advanced CEMOS'·, a dual metal CMOS
technology. The IDT54174FCT138 and IDT54174FCT138A accept
three binary weighed inputs (Ao, A 1, A2l and, when enabled,
provide eight mutually exclusive active LOW outputs (00-07).
The IDT54174FCT138 and IDT54174FCT138A feature three
enable inputs, two active LOW iE1' E 2) and one active HIGH
(Ea). All outpus will be HIGH unless E1 andE2 are LOW and Es
is HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder
with just four IDT54174FCT138 or IDT54174FCT138A devices
and one inverter.
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
AO
A1
A2
E1
E2
Ea
07
GND
SSD54n4FCT138-001
DIP/SOIC
TOP VIEW
Ea E2NCE1 A2
LJ lJ LJ LJ LJ
<>?
GND
NC
0&
05
:9 8
7
6
5
43:
:10
2~
:11
1~::
::12
20 :::
::1~4
19:::
15 16 17 18
nr1r1f1r1
A1
Ao
NC
Vee
00
SSD54174FCT138-003
040aNC0201
SSD54/74FCT138-002
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
CI 1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
5-98
IDT54/74FCT13B/A FAST CMOS 1-0F-B DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
Oto +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
120
120
DC Output Current
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O·C to +70·C
Vee =5.0V ± 5%
Min.
TA =-55·C to +125·C
Vee =5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
= 4.75V
= 4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
V'L
Input LOW Level
Guaranteed Logic Low Level
I'H
Input HIGH Current
Vcc
-
-
SYMBOL
I'L
Input LOW Current
Isc
Short Circuit Current
VOH
TEST CONDITIONS(1)
PARAMETER
Output HIGH Voltage
=Max .• V,N =Vec
Vee =Max., V,N =GND
Vec =Max. (3)
Vee =3V, V,N =VLe or VHe,
Vee =Min.
V,N =V,H or V'L
-
Output LOW Voltage
V
"A
-5
"A
mA
-
VHe
Vee
VHe
Vee
-
10H =-12mA MIL.
2.4
4.3
-
4.3
-
-
GND
VLe
-
GND
V Le
-
0.3
0.5
-
0.3
0.5
2.4
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
V
5
IOH =-300"A
10H =-32"A
UNIT
0.8
-120
IOH =-15mA COM'L.
=3V, V,N =VLe or VHC, IOL =300"A
IOL =300"A
Vee =Min.
IOL =32mA MIL.
V,N =V,H or V'L
IOL =48mA COM'L.
5-99
-
-60
Vce
VOL
MAX.
V
V
IDT54n4FCT138/A FAST CMOS 1-0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; VHC = vcc - O.2V
SYMBOL
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V'N<'=VHC
V'N"'VLC
-
0.15
0.3
VCC= Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
One Input Toggling
V'N<'= VHC
V'N'" VLC (FCT)
-
1.5
4.5
V'N = 3.4V
V'N=GND
-
1.8
5.3
Vcc= Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
V'N<'= VHC
V'N'" VLC (FCT)
-
0.38
2.3
V'N = 3.4V
V'N=GND
-
0.63
3.1
TEST CONDITIONS(1)
PARAMETER
Icco
Quiescent Power Supply Current
Vee = Max.
V'N <'= VHO V'N'" VLC
Ii =0
ICCT
Power Supply Current
TTL Inputs HIGH
Vcc=Max.
V'N = 3.4V(3)
ICCD
Dynamic Power Supply
Current
VCC= Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Icc
Total Power Supply(')
Current
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'aUIESCENT + 'INPUTS + 'DYNAMIC
Icc = Icco + ICCTDHNT + 'CCD (fcp/2 + fiN,)
IceQ = Quiescent Current
ICCT =Power Supply Current for a TTL High Input (V'N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fj = Input Frequency
Nj = Number of Inputs at fj
All currents are in milliamps and all frequencies are In megahertz.
5-100
mAl
MHz
ID"'S4/74FCT138/A FAST CMOS 1-0F-8 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
P.O-P.2
E" E2
9_
0 0 -0 7
DESCRIPTION
INPUTS
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs (Active LOW)
OUTPUTS
O2 0 3 O. 0 5 0 6 0 7
E,
E2
E3
AD
A,
A2
00
0,
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT138A
IDT54/74FCT138
SYMBOL
PARAMETER
tpHL
PropagatioJ:! Delay
Aoto ON
t pLH
t pHL
Prgpaga.ti0n ~Iay
E, or E,to ON
tpLH
ProP'!9ati"" Delay
E3to ON
tpLH
tpHL
CONDITION
TYP.
7.0
COM'L.
MIL.
MIN.
MAX.
MIN.
MAX.
3.5
9.0
3.5
12.0
TYP.
4.5
COM'L.
MIL.
MIN.
MAX.
MIN.
1.5
5.8
1.5
UNITS
MAX.
7,8
ns
I"
C L = 50pF
RL = 500n
6.0
3.0
9.0
3.0
12.5
4.5
1.5
5.9
1.5
8.0
ns
6.0
3.5
9.0
3.5
12.5
4.5
1.5
5.9
1.5
8.0
ns
I
5-101
FEATURES:
DESCRIPTION:
• IDT54174FCT139 equivalent to FASr" speed;
IDT54174FCT139A 35% faster than FAST'"
• Equivalent to FASr" output drive over full
temperature and voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FASr"
(5p.A max.)
The IDT54/74FCT139 and IDT54174FCT139A are dual 1-01-4
decoders built using advanced CEMOS'·, a dual metal CMOS
technology. The devices have two independent decoders, each
01 which accept two binary weighed inputs (Ao-A1) and provide
lour mutually exclusive active LOW outputs (00-03). Each
decoder has an active LOW enable (E). When E is HIGH, all
outputs are forced HIGH.
• Dual 1-of-4 decoder with enable
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout lor DIP and LCC
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
SSD54174FCT139-001
DIP/SOIC
TOP VIEW
:I
,:! 0
c!I :!
SSD54174FCT139-003
IOIOZIOC
LJ
038
:::9 8
t J LJ LJ LJ
7
6
5
43:
GND
::::10
2:::
NC
:::11
::12
1~::
20::::
03b
02b
19::::
Aoa
E.
NC
Vee
Eb
SSD54174FCT139-002
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in the U.S.A.
5-102
IDT54174FCT139/A FAST CMOS DUAL 1-0F-4 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
Oto +70
-55 to +125
'C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
lOUT
DC Output Current
120
mA
120
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
VHe = Vee - 0.2V
TA = O°C to +70°C
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYR(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
VIL
I nput LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
IIH
Input HIGH Current
Vee = Max., VIN = Vee
-
-
5
p.A
IlL
I nput LOW Current
Vee = Max., VIN = GND
-
-
-5
p.A
Ise
Short Circuit Current
Vee = Max. (3)
-60
-120
mA
SYMBOL
TEST CONDITIONS(1)
PARAMETER
VHe
Vee
-
10H = -300p.A
VHe
Vee
-
10H = -12mA MIL.
2.4
4.3
-
10H = -15mA COM'L.
2.4
Vee = 3V, VIN = VLC or VHe• 10H = -32p.A
VOH
Output HIGH Voltage
Vee = Min.
VIN = VIH or VIL
4.3
-
-
GND
VLe
10L = 300p.A
-
GND
VLe
10L = 32mA MIL.
-
0.3
0.5
IOL = 48mA COM'L.
-
0.3
0.5
Vee = 3V, VIN = VLe or VHe , 10L = 300p.A
VOL
Output LOW Voltage
Vee = Min.
VIN = VIH or VIL
NOTES:
1. For conditions shown 85 max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-103
V
V
IDT54/74FCT139/A FAST CMOS DUAL 1-0F-4 DECODER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC : O.2V; VHC :
vcc - O.2V
SYMBOL
Icca
Quiescent Power Supply Current
Vec" Max.
V'N 2 VHc; V'N " VLC
Ii "0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc" Max.
V'N : 3.4V(3)
ICCD
Dynamic Power Supply
Current
Vcc" Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Vce" Max.
Outputs Open
Ii" 10MHz
50% Duty Cycle
One Input Toggling
Total Power Supply(4)
Current
Icc
TYP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V'N 2 VHC
V'N" VLC
-
0.15
0.3
mAl
MHz
V'N 2 VHC
V'N" VLC (FCT)
-
1.5
4.5
V'N: 3.4V
V'N"GND
-
1.8
5.3
V,N2VHC
V'N " VLC (FCT)
-
3.0
7.5
V'N" 3.4V
V'N = GND
-
3.5
9.1
TEST CONDITIONS(')
PARAMETER
Vce" Max.
Outputs Open
Ii" 10MHz
50% Duty Cycle
One Input Toggling
on Each Decoder
MIN.
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GNO.
4.
Icc = laUIEsCENT + IINPUTS + IDYNAMIC
Icc
=ICGQ + ICCTDHNT + IceD (fcp/2 + fiNj)
ICGQ =
leeT
Quiescent Current
=Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT
=Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi
Nj
=Input Frequency
=Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
TRUTH TABLE
INPUTS
DEFINITION OF FUNCTIONAL TERMS
OUTPUTS
DESCRIPTION
PIN NAMES
E
Ao
A,
00
0,
O2
03
H
L
L
L
L
X
L
H
L
H
X
L
L
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
!'-O, A,
E
0 0 -0 3
Address Inputs
Enable Inpuls (Active LOW)
Outputs (Active LOW)
H =HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT139A
IDT54/74FCT139
SYMBOL
tpLH
tpHL
t pLH
t pHL
PARAMETER
Propagation ~Iay
AoorA,toO n
ProP'!llatiQD Delay
Eta On
CONDITION
C L = 50p!
RL = 500n
TYP.
6.0
5.5
COM'L.
MIL.
TYP.
MIN.
MAX.
MIN.
MAX.
3.0
9.0
2.5
12.0
3.0
8.0
5-104
2.5
9.0
COM'L.
MIN.
4.5
s;b::'
't)~
\>/;
1.5
MAX.
~
""I
<~~~t; ~'5
5.5
1.5
UNITS
•
7.8
ns
7.2
ns
FEATURES:
DESCRIPTION:
• IDT54174FCT161/163 equivalent to FASr" speed;
IDT54/74FCT161A/163A 35% faster than FAST'"
The IDT54/74FCT161/163 and IDT54174FCT161A1163A are
high-speed synchronous modul0-16 binary counters built using
advanced CEMOS'", a dual metal CMOS technology. They are
synchronously presettable for application in programmable
dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The IDT54/74FCT161/163 and IDT54/74FCT161 AI
163A have asynchronous Master Reset inputs that override all
other inputs and force the outputs LOW. The IDT54174FCT161/163
and IDT54174FCT161A/163A have Synchronous Reset inputs
that override counting and parallel loading and allow the outputs
to be simultaneously reset on the rising edge of the clock.
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5/JW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FASr"
(5/JA max.)
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
P,
PE--t-~~fl~------------+-~-------------++----------.~-------------.
'161
I"'-'
.,f' \., '163
CEP--~~~~~
:-
l=LJ
______~~-+-+
__________-.-++-______
~~~
______-,
CET---Ti~1~63~~------------~I--~~-------------+~~---------+-T+----------T-----T~
:~
~
r::,: ~---~~-11lf11r====IfT1~~===i,===m=P-I
...)c>--t-.
CP
CP ---i---{...
1
IONLY'
1_'
: i~ H' D CPa aD
,:
II
I
1-"
00
'----- ~
I
t---o:-a
.....
1
T
TC
DETAIL A
DETAIL A
DETAIL A
a,
a2
a3
o
L_________ !!~~~_~
I
I
I
I
SR ('163)
Co
I'"
,I
MR (,161)
~
......
SSOFCT163-001
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl 1986 Integrated Devfce TeChnology. Inc.
JULY 1986
Printed in U.S.A.
5-105
IDT54/74FCT161/A & IDT54/74FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATING(l)
'-R
Vee
TC
CP
p.
P,
P2
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
VTEAM
Terminal
Voltage with
Respect to GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operation
Temperature
o to +70
-55 to +125
'C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
lOUT
DC Output
Current
120
120
mA
Q.
Q,
Q2
Q3
P3
CEP
CET
PE
GND
SSDFCT163-002
DIP/SOIC
TOP VIEW
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
P3 P2 NC P, p.
,u , , ,
LJ u'
,
LJ
6
4
,-
CEP
::::J 9
GND
NC
:::'JlO
=:J11
1:::
NC
PE
:::J12
20~=
Vee
19 r -
TC
CET
8
:J13
14 15
, , ," ,
16
"
"
17
18
3 L_
CP
2[::::
'R
L_
, , ," ,
"'
Q 3 Q 2 NC Q, Q.
SSDFCT163-003
LCC/PLCC
TOP VIEW
'MR FOR '161
'SR FOR '163
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O'C to +70°C
Vcc = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vcc = 5.0V ± 10%
Min.
VLC = 0.2V
VHc = Vcc - 0.2V
SYMBOL
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(')
PARAMETER
MIN,
TYP'(2)
MAX.
UNIT
2.0
-
-
V
-
0.8
V
-
5
!,A
V,H
Input HIGH Level
Guaranteed Logic High Level
V,L
Input LOW Level
Guaranteed Logic Low Level
I'H
Input HIGH Current
=Max., V,N =Vee
Vce = Max., V,N =GND
Vee = Max.!3)
Vcc =3V, V,N =VLe or VHC,
-5
!,A
-60
-120
-
mA
VHe
Vee
-
IOH
VHC
Vee
2.4
4.3
2.4
4.3
-
I,L
Input LOW Current
Isc
Short Circuit Current
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
-
Vee
10H =-32!'A
=-300!,A
Vce = Min.
IOH = -12mA MIL.
V ,N =V ,H or V,L
10H =-15mA COM'L.
Vce =3V, V,N =VLe or VHe, 10L =300!,A
10L =300!,A
Vee = Min.
IOL" 32mA COM'L.
V ,N =V,H or V,L
IOL =48mA COM'L.
-
-
-
GND
VLC
-
GND
V Le
-
0.3
0.5
-
0.3
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration 01 the short circuit test should not exceed one second.
5-106
V
V
IDT54/74FCT161/A & IDT54174FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS (IDT54174FCT161/A)
VLC = O.2V; v HC = vcc - O.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP'(2)
MAX.
UNIT
Vee = Max.
ICCQ
Quiescent Power Supply Current
V1N ;:: VHC ; V1N :-:;; VLC
fcpof,oO
-
0.001
1.5
rnA
ICCT
Power Supply Current per
TTL Input HIGH
VCC 0 Max.
V,N 0 3.4V(3)
-
0.5
1.6
rnA
Dynamic Power Supply Current
Vcc 0 Max.
Outputs Open
Count Mode
P(}'3° VLC
CEP 0 CET 0 MR
PE 0 VHC
CP
V1N 2.': VHC
V,N :5 VLC (FCT)
-
0.3
-
CP
V,N:O VHC
V,N :5 VLC (FCT)
.-
3.0
-
CP
V,N
V,N
-
3.8
-
ICGD
0
Vcc 0 Max.
Outputs Open
fcpo 10MHz,
50% Duty Cycle
Count Mode
P O_3 ° VLC
CEP 0 CET 0 MR =
PE 0 VHC
Total Power Supply Current(4)
Icc
mAl
MHz
rnA
3.4V or
GND
0
0
POWER SUPPLY CHARACTERISTICS (IDT54/74FCT163/A)
VLC = O.2V; VHC = Vcc - O.2V
SYMBOL
Vcc
0
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
CP
V,N:O VHC
V,N :5 VLC (FCT)
-
0.3
-
CP
V,N:O VHC
V,N :5 VLC (FCT)
-
3.0
-
CP
V,N
V,N
-
3.8
-
MIN.
Max.
V1N :::: VHC ; V1N :::; VLC
Quiescent Power Supply Current
ICCQ
TYP'(2)
TEST CONDITIONS(1)
PARAMETER
fcpof,oO
ICCT
ICCD
Power Supply Current per
TTL Input HIGH
Vcc 0 Max.
V,N o3.4V(3)
Dynamic Power Supply Current
Vcc 0 Max.
Outputs Open
Count Mode
P(}'3° VLC
CEP 0 CET 0 SR
PE 0 VHC
Vcc 0 Max.
Outputs Open
fcp 0 10MHz,
50% Duty Cycle
Count Mode
P O_3 ° V LC
CEP 0 CET 0 SR
PE 0 VHC
Total Power Supply Current(4)
Icc
0
rnA
0
0
0
3.4V or
GND
NOTES:
1 For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for !he applicable device type.
2. Typical values are at Vee
co
5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V1N = 3.4V); all other inputs at Vee or GND.
4.
Icc:': IQUIESCENT + IINPUTS t IDYNAMIC
Icc::' ICGQ
t
ICCTDHNT + IceD (fep + fiNi)
Iceo =- Quiescent Current
lecT
~-
Power Supply Current for a TTL High Input (VIN
DH
==
Duty Cycle for TTL Inputs High
:::
3.4V)
NT::: Number of TTL Inputs at DH
ICGD =- Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp::: Count Clock or Load Clock Frequency
fj = PO_3lnput Frequency (Load)
Nj = Number of Po _3 lnputs at fj (Load)
All currents are in milliamps and all frequencies are in megahertz.
5-107
mAl
MHz
IDT54/74FCT161/A & IDT54114FCT163/A
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
CEP
CET
CP
MR (,161)
SR ('163)
PO-3
PE
Q0- 3
TC
TRUTH TABLE
DESCRIPTION
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
SR(1)
PE
CET
CEP
ACTION ON THE RISING
CLOCK EDGE (S )
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset (Clear)
Load (Po - Qo)
Count (Increment)
No Change (Hold)
No Change (Hold)
NOTES:
1. For FCT163/163A ONLY
H : HIGH Voltage Level
L : LOW Voltage Level
X :::: Immaterial
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161
IDT54/74FCT163
SYMBOL
tpLH
t pHl
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpHL
PARAMETER
CONDITION
TYP.
IDT54/74FCT161A
IDT54114FCT163A
MIL.
COM'L.
MIN.
MAX.
MIN.
MAX.
MIL.
TYP.
COM'L.
MIN.
MAX.
MIN.
MAX.
UNITS
Propagation Delay
_CPtoQn
(PE Input HIGH)
7.0
3.5
11.5
3.5
11.0
4.5
2.0
7.5
2.0
7.2
ns
Propagation Delay
_CPtoQo
(PE Input LOW)
7.0
4.0
10.0
4.0
9.5
4.5
2.0
6.5
2.0
6.2
ns
Propagation Delay
CPtoTC
10.0
5.0
16.5
5.0
15.0
6.5
2.0
10.8
2.0
9.8
ns
Propagation Delay
CETtoTC
4.5
2.5
9.0
2.5
8.5
3.0
1.5
5.9
1.5
5.5
ns
£'rQpagation Delay
MR to Q n (,F161A)
9.0
5.5
14.0
5.5
13.0
5.9
2.0
9.1
2.0
8.5
ns
Pro~tion
Delay
MR to TC
8.0
4.5
12.5
4.5
11.5
5.2
2.0
8.2
2.0
7.5
ns
ts(H)
ts(L)
Setup Time,
HIGH or LOW
Po to CP
5.0
5.5
-
5.0
-
4.0
4.5
-
4.0
-
ns
tN(H)
tN(L)
Hold Time,
HIGH or LOW
Po to CP
2.0
2.5
-
2.0
-
1.5
2.0
-
1.5
-
ns
ts(H)
ts(L)
Setup Time,
HIGH or LOW
PE or SR to CP
11.0
13.5
-
11.5
-
9.0
11.5
-
9.5
-
ns
tN(H)
tN(L)
Hold Time,
HIGH or LOW
PE or SR to CP
2.0
2.0
-
2.0
-
1.5
1.5
-
1.5
-
ns
ts(H)
ts(L)
Setup Time,
HIGH or LOW
CEP or CET to CP
11.0
13.0
-
11.5
-
9.0
11.0
-
9.5
-
ns
tN(H)
tN(L)
Hold Time,
HIGH or LOW
CEP or CET to CP
0
0
-
0
-
0
0
-
0
-
ns
tw(H)
tw(L)
Clock Pulse Width
(Load)
HIGH or LOW
5.0
5.0
-
5.0
-
4.0
4.0
-
4.0
-
ns
tw(H)
tw(L)
Clock Pulse Width
(Count)
HIGH or LOW
6.0
8.0
-
7.0
-
5.0
7.0
-
6.0
-
ns
tw(L)
MR Pulse Width,
LOW ('F161A)
5.0
5.0
-
5.0
-
4.0
4.0
-
4.0
-
ns
tREe
Recovery Time
MR to CP (,F161A)
6.0
6.0
-
6.0
-
5.0
5.0
-
5.0
-
ns
tpHL
C L = 50pf
RL = 500n
5-108
FEATURES:
DESCRIPTION:
• IDT54/74FCT182 equivalent to FASr" specs
The IDT54/74FCT182 and IDT54174FCT182A are high-speed
carry lookahead generators built using advanced CEMOS'", a
dual metal CMOS technology. The IDT54174FCT182 and IDT541
74FCT182A are generally used with a 4-bit arithmetic logic unitto
provide high-speed lookahead over word lengths of more than
four bits.
IDT54!74FCT182A 35% laster than FAST
• Equivalent to FASr" speeds and output drive over lull
temperature and voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FASr"
(5p.A max.)
• Carry lookahead generator
• 100% product assurance screening to MIL-STD-883, Class B
is avai lable
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
('I')
(I')
0
0
0
Ia.. 10 Z Ia.. 10
G,
Vee
P,
Go
Po
G3
P3
P
P2
G2
LJ
P
Cn
C n +x
Cn +y
G
Cn + l
GND
:9 8
7
•
LJ L J
4
5
':::
2~
:10
GND
NC
~11
Cn+z
~12
G
L J LJ
1:::::=
~1:;4 15
r1 n
,.
r1
P,
G,
20:
NC
Vee
1:1:::::
P2
17 18
r1 r l
eN
~ " 0 010
i: Z
C
0 0
SSDFCT182-0Q2
SSDFCT182-001
LCC
TOP VIEW
DIP/SOIC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
SSDFCT182-003
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
~
Printed
1986 Integrated Oevice Technology. Inc
5-109
In
the U.S.A.
IDT54/74FCT1821A
FAST CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
oto +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
120
120
mA
lOUT
NOTE:
DC Output Current
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections ofthls specification Is not Implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA O·C to +70·C
Vee 5.0V ± 5%
Min.
TA -55·C to +125·C
Vee 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
=
=
=
=
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High level
2.0
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
0.8
V
IIH
Input HIGH Current
Vee =Max., Y,N =Vee
-
5
"A
IlL
Input lOW Current
Vee
-
-
Ise
Short Circuit Cucrent
Vee =Max. (3)
"A
mA
SYMBOL
TEST CONDITIONS(1)
PARAMETER
Vee
VOH
Output HIGH Voltage
=Max., Y'N =GND
-5
-120
-
VHe
Vee
-
10H =-300"A
VHe
10H =-12mA MIL.
2.4
Vee
4.3
-
=3V, VIN =VLe or VHe,
Vee =Min.
Y,N =VIH or VIL
-
-60
10H =-32"A
10H =-15mA COM'l.
=3V, Y'N =VLe or VHe, 10L =300"A
10L =300"A
Vee =Min.
10L =32mA MIL.
VIN =V,H or VIL
10L =48mA COM'L.
Vee
VOL
Output LOW Voltage
2.4
4.3
-
-
GND
VLe
-
GND
VLe
-
0.3
0.5
0.3
0.5
NOTE8:
1. For conditions shown as max. or min., use appropriate value speeifled under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-110
V
V
IDT54174FCT1821A
FAST CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
MIN.
TYp'I')
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V'N2:VHC
V'N:5 VLC
-
0.15
0.3
mAl
MHz
V'N2:VHC
V'N:5 VLC (FCT)
-
1.5
4.5
V'N = 3.4V
V'N= GND
-
1.8
5.3
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc= Max.
V'N 2: VHC; V'N :5 VLC
Icp = Ii = 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
V'N = 3.4V(3)
ICCD
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Icc
Total Power Supply(4)
Current
Vcc = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
One Input Toggling
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V tN = 3.4V); all other inputs at Vee or GNO.
4.
Icc::: 'QUIESCENT
+ 'INPUTS +
'DYNAMIC
Icc::: ICCQ + ICCTDHNT + ICCD (fcp/2 + fjNj)
ICCQ :::
Quiescent Current
ICCT ::: Power Supply Current for a TTL High Input (V 1N ::: 3.4V)
DH = Duty Cycle for TTL Inputs High
NT
=Number of TTL Inputs at DH
IceD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep::: Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi ::: Input Frequency
Ni ::: Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Cn
G", G2
G,
G3
Po. P,
P2
P3
C n + x-Cn + z
G
P
DESCRIPTION
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Carry
Input
Generate I nputs (Active LOW)
Generate Input (Active LOW)
Generate I nput (Active LOW)
Propagate Inputs (Active LOW)
Propagate Input (Active LOW)
Propagate Input (Active LOW)
Outputs
Generate Output (Active LOW)
Propagate Output (Active LOW)
5-111
IDT54/74FCT182/A
FAST CMOS CARRY LOOKAHEAD GENERATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
OUTPUTS
INPUTS
Cn
Go
Po
X
L
X
H
H
H
L
X
H
X
X
L
X
X
L
X
X
H
X
H
H
X
L
X
X
H
X
X
X
L
H
H
H
L
X
X
H
X
X
X
L
L
X
X
X
L
X
X
X
H
X
X
H
H
X
X
L
X
X
X
H
X
X
X
X
L
X
H
H
H
X
L
X
X
X
H
X
X
X
X
L
L
H
H
H
H
L
X
X
X
H
X
X
X
X
L
L
L
X
X
H
H
X
X
L
X
X
X
H
X
X
X
X
L
X
H
H
H
X
L
X
X
X
H
X
X
X
X
L
L
G,
P,
G2
P2
G,
P,
Cn + x
C n+ y
G
C n+z
P
L
L
H
H
X
X
X
H
X
X
X
L
H
X
X
X
L
X
H
X
X
L
L
L
L
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
X
L
H
H
H
H
L
L
L
L
H
X
X
X
X
L
L
L
H
H
H
H
L
X
X
X
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT182
SYMBOL
PARAMETER
CONDITION
TYP.
COM'L,
MIN,
MAX,
IDT54174FCT182A
MIL
MIN,
TYP,
MAX,
COM'L
MIN,
MAX,
UNITS
MIL
MIN,
MAX,
~~--
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tp!....H
tpHL
tpLH
tpHL
tpLH
tpHl
Propagation Delay
C N to C N• X ,
6.0
3.0
10.0
3.0
16.5
4.0
2.0
6.5
2.0
10.7
ns
6.0
2.0
9.0
2.0
11 ~5
4.0
1.5
5.8
1 ~5
7.4
ns
6.0
2.0
9.5
2.0
11.5
4.0
1.5
6.0
1.5
7.4
1---:--
Propagation Delay
P P2 , P 3 to G
"
7.0
3.0
11 ~O
3.0
16~5
4.8
2.0
7.0
2.0
10.7
ns
Propagation Delay
GNtoG
7.5
3.0
11.5
3~0
16.5
5~0
2.0
7.4
2.0
10.7
ns
Propagation Delay
PNto P
6~0
2.5
8.5
2.5
12.5
4~0
1.5
5~5
1.5
7.4
ns
C N +y , C N +Z
Propagation Delay
Po, P,. P 2 , to
C N -+ X' C N + y , C N + Z
Prcpa[@tio-" Delay
Go, G G 2 , to
"
C N +X' C N +y , C N + Z
C L = 50 pi
RL = 500n
5-112
FEATURES:
DESCRIPTION:
• IDT54/74FCT191 equivalent to FASr" speed;
The IDT54/74FCT191 and IDT54/74FCT191A are reversible
modulo-16 binary counters, featuring synchronous counting and
asynchronous presetting, and built using advanced CEMOS'", a
dual metal CMOS technology. The preset feature allows the
IDT54174FCT191 and IDT54/74FCT191A to be used in programmable dividers. The Count Enable input, the Terminal Count
output and the Ripple Clock output make possible a variety of
methods of implementing multistage counters. In the counting
modes, state changes are initiated by the rising edge of the
clock.
IDT54174FCT191A 35% faster than FAST'"
• Equivalent to FAST'" output drive over full temperature and
voltage supply extremes
•
•
•
•
IOL = 32mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than FASr"
(5p.A max.)
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
CP
OlD
"7
~
P,
-
,,7
~
'i7-
If~
I
I
>0-
-J
'i7
)
11
I-
( )
1
(
J
(J
tf
I
l
I
J CLOCK K
PRESET
CLEAR
Q
1
RC
TC
I
I
Q
L--
Y
Qo
I
I
I
I
J CLOCK
Q
Q
I
I
Q
Q
L--..--
V
Y
Q,
I
I
ioPRESET
CLEAR
Q
I
I
J CLOCK K
1
J CLOCK K
'--<
PRESET
p...
CLEAR
Q
a
I
f
Q3
SSDFCT191-001
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
I
I
I
tJ
[)
K
PRESET
CLEAR
IV
I
j
JULY 1986
Printed in U.S.A.
1986 Integrated Device Technology, Inc.
5-113
1DT54174FCT1I11/A
FAST CMOS UPIDOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATING(1)
P,
Q,
Qo
Vec
Po
CE
RC
UtD
tc
Pi:
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
VTERM
Terminal
Voltage with
Respect to GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operation
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperalure
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output
Current
120
120
rnA
CP
Q2
P2
Q.
GND
p.
SSDFCT19HlO2
NOTE:
DIP/SOIC
TOP VIEW
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Ol~ ~I~d'
Q.
LJ LJ LJ LJ LJ"
:.8
7 "6
5 4 ~t
GND
2:::
NC
p.
1::::::
20:::
P2
""4151.,71.'-
-"3
1.....
~,
P,
NC
Vee
Po
r1r1f1r1r1
I~ ~ ~
If!! fj
sSD~CT1rf1-OOS
LCC/PLCC
TOP VIEW
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =OOC to +70·C
Vcc =S.OV ± 5%
Min. =4.75V
TA "-5S·C to +12S·C
Vcc = S.OV ± 10%
Min. = 4.S0V
VLC = O.2V
VHC = Vcc - O.2V
Max. = S.25V (Commercial)
Max. = S.SOV (Military)
MIN.
TYP'(2)
MAX.
UNIT
VIH
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
VIL
Input LOW Level
Guaranteed Logic Low Level
0.8
V
IIH
Input HIGH Current
Vcc = Max., VIN
-
-
-
5
p.A
SYMBOL
TEST CONDITIONS(')
PARAMETER
IlL
Input LOW Current
Isc
Short Circuit Current
VOH
Output HIGH Voltage
=Vcc
Vcc =Max., VIN =GND
Vcc =Max. (3)
Vcc =3V, VIN = VLe or VHC,
Vcc= Min.
VIN V'H or VIL
=
Vcc
VOL
Output LOW Voltage
-
-
-5
p.A
-60
-120
-
rnA
VHC
Vcc
10H = -300p.A
VHC
Vcc
10H = -12mA MIL.
2.4
4.3
IOH = -15mA COM'L.
2.4
4.3
-
-
GND
VLC
-
GND
VLc
-
0.3
0.5
0.3
0.5
IOH = -32p.A
=3V, VIN = VLC or VHC, 10L = 3OOp.A
IOL =300p.A
Vcc= Min.
VIN = VIH or VIL
10L = 32mA MIL.
IOL = 48mA COM'L.
NOTEI:
1. For conditions shown as rnax. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. "lYplcal values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not mare than one output should be shorted at one time. Duration of the short circuit test should not exceed one s""ond.
5-114
V
V
IDT54n4FCT191/A
FAST CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC =O.2V; VHC =vcc - O.2V
SYMBOL
Icco
Quiescent Power Supply Current
Vcc = Max.
V'N'" VHC; V'N~ VLC
fcp=fi=O
ICCT
Power Supply Current
TTL Input HIGH
Vcc= Max.
V'N = 3.4V(a)
Dynamic Power
Supply Current
Vcc= Max.
Outputs Open
Count Up or Down Mode
CE = VLC
fL=Po-Pa=VHc
u/D = VHC or VLC
Total Power
Supply Current (4)
Vcc= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
Count Up or Dawn Mode
PL = Po - Pa = VHc
£E =VLC
U/D = VHC or VLC
ICCD
Icc
MIN.
TYp.II)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V'N'" VHc
V'N~ VLc
-
0.3
-
mAl
MHz
V'N"'VHC
V'N ~ VLC (FCT)
-
3.0
-
V'N = 3.4V
or
V'N=GND
-
3.8
-
TEST CONDITIONS(1)
PARAMETER
mA
NOTES:
1. For conditions shown as max. or min .. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=5.0V. +25°C ambient and maximum loading.
3. Per TTL driven input (V1N ::: 3.4V); all other inputs at Vee or GND.
4.
Icc
='QUIESCENT + 'INPUTS + 'DVNAMIC
lee l =ICCQ + ICCTDHNT + IceD (fep + fjNj)
ICCQ = Quiescent Current
teeT = Power Supply Current for a TTL High Input (V1N
DH =Duty Cycle for TTL Input High
=3.4V)
NT = Number of TTL Inputs at DH
IceD
=DynamiC Current caused by an Input Transition pair (HLH or LHL)
fcp = Count Clock or Load Clock Frequency
fj = PO-3 Input Frequency (Load)
=Number of Po_3 lnputs at fi (Load)
All currents are in milliamps and all frequencies are in megahertz.
Ni
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
CE
CP
Po-a
PL
D/D
Qo-a
RC
TC
&I
TRUTH TABLES
MODE SELECT TABLE
DESCRIPTION
INPUTS
Count Enable Input (Active LOW)
Count Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Up/Dawn Count Control Input
Flip-Flap Outputs
Ripple Clack Output (Active LOW)
Terminal Clock Output (Active HIGH)
PL
CE
U/D
H
H
L
H
L
L
X
H
L
H
X
X
CP
--.r
--.r
X
X
MODE
Count Up
CountDown
Preset (Asynch.)
No Change (Hold)
RC TRUTH TABLE
CE
INPUTS
TCll)
CP
RC
L
H
X
H
X
L
"lJ"
X
X
"lJ"
H
H
NOTES:
1. TC Is generated Internally.
H = HIGH Voltage Level
L = LOW Voltage Level
X
5-115
=Immaterial
OUTPUT
IDT54/74FCT191/A
FAST CMOS UP/DOWN BINARY COUNTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT191A
IDT54n4FCT191
SYMBOL
PARAMETER
CONDITION
TYP.
COM·L.
MIL.
MIN.
MAX.
MIN.
MAX.
TYP.
COM·L.
MIL.
MIN.
MAX.
MIN.
MAX.
UNITS
tpLH
tpHL
Propagation Delay
CP to Q n
8.5
1.5
16.0
3.0
12.0
5.5
1.5
10.5
2.5
7.8
ns
tpLH
Propagation Delay
CPtoTC
10.0
4.5
16.0
5.0
14.0
6.5
2.0
10.5
3.0
9.1
ns
5.5
1.5
12.5
3.0
8.5
3.6
1.5
8.2
2.5
5.6
ns
t pHL
tpLH
tpHL
Propagatio~elay
t pLH
tpHL
Propagation Delay
CEto RC
5.5
3.0
8.5
3.0
8.0
3.6
2.0
5.6
2.0
5.2
ns
t pLH
tpHL
Prol'.!'gation Delay
u/D to RC
11.0
5.5
22.5
5.5
20.0
7.2
4.0
14.7
4.0
13.0
ns
tpLH
Prol'.!'gation Delay
U/D to TC
7.0
4.0
13.0
4.0
11.0
4.6
3.0
8.5
3.0
7.2
ns
t pHL
Propagation Delay
Pn to Q n
10.0
1.5
16.0
3.0
14.0
6.5
1.5
10.4
2.0
9.1
ns
tpLH
tpHL
Prop!!9..ation Delay
PL to Q n
9.0
5.0
14.0
5.0
13.0
5.9
3.0
9.1
3.0
8.5
ns
ts(H)
ts(L)
Setup Time,
HIGH or LOW
Pn to PL
4.5
6.0
-
5.0
-
4.0
5.0
-
4.0
-
ns
tH(H)
tH(L)
Hold Time,
HIGH or LOW
Pn to PL
2.0
2.0
-
2.0
-
1.5
1.5
-
1.5
-
ns
10.0
10.5
-
10.0
-
9.0
9.5
-
9.0
-
ns
tpHL
tpLH
ts(L)
CPto RC
Set~Time
LOW
CEto CP
C L ; 50pF
R L ; 5000
tH(L)
Hold Time LOW
CEto CP
0
0
-
0
-
0
0
-
0
-
ns
ts(H)
t.(L)
Setup Time,
HIGH or LOW
DID to CP
12.0
12.0
-
12.0
-
10.0
10.0
-
10.0
-
ns
tH(H)
tH(L)
Hold Time,
HIGH or LOW
DID to CP
0
0
-
0
-
0
0
-
0
-
ns
tw(L)
PL Pulse Width, LOW
6.0
8.5
-
6.0
-
5.5
8.0
5.0
7.0
-
5.0
-
4.0
6.0
4.0
-
ns
CP Pulse Width, LOW
-
5.5
tw(L)
t REC
Recovery Time
PL to CP
6.0
7.5
-
6.0
-
5.0
6.5
-
5.0
-
ns
5-116
ns
FEATURES:
DESCRIPTION:
• IDT54/74FCT193 equivalent to FAST'· speed;
IDT54n4FCT193A 35% faster than FAST'"
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
The IDT54/74FCT193 and IDT54/74FCT193A are up/down
modul0-16 binary counters built using advanced CEMOS'", a
dual metal CMOS technology. Separate Count-up and Countdown Clocks are used and, in either counting mode, the circuits
operate synchronously. The outputs change state synchronQusly with the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count-up and Terminal Count-down outputs
are provided that are used as the clocks for subsequent stage
without extra logic, thus simplifying multistage counter designs.
Individual preset inputs allow the circuit to be used as a
programmable counter. 80th the Parallel (PL) and the Master
Reset (MR) inputs asynchronously override the clocks.
•
•
•
•
IOL = 32mA over full military temperature range
CMOS power levels (5p.W typo static)
80th CMOS and TTL output compatible
Substantially lower input current levels than FAST'"
(5p.A max.)
• 100% product assurance screening to MIL-STD-883, Class 8
is available
FUNCTIONAL BLOCK DIAGRAM
P,
......
...
TC u
......
CPu
CPo
~
--I
TC o
rr
~
~
r ",+
j
KO
Co
......
So
(CARRY)
~
~
~:CPi1
L--
~7
~
XJ'f
~cKCD CP So
o
L--
0
~
~KCPl
CD
So
o
L--
~7
(BORROW)
~
0
L--
~7
0,
SSDFCT193-001
CEMOS is a trademark of Integrated Oevice Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in the U.S.A.
@1986lntegrated Device Technology, Inc.
5-117
IDT54174FCTI93/A FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
P,
VTERM
a,
a.
Terminal
Voltage with
Respect to GND
-0.5 to +7.0
-0.5 to +7.0
V
TA
Operation
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output
Current
120
120
mA
CPo
CPu
O2
03
GND
SSDFCT193-002
DIP/SOIC
TOP VIEW
NOTE:
,. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
fNr£orf
O()Z()O
CI
LJ LJLJ
LJLJ
43:
a,
GND
=10
2:
P,
NC
P3
::11
':::::=
NC
::12
20::::
Vce
P2
::::1~4
03
:::9 8
7
6
5
,J
9 ;:
15 16 17
rl rlr1
r1 r1
p.
I~I~ ~I~I~
SSDFCT193 w OO3
LCC/PLCC
TOP VIEW
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Vcc = 5.0V ± 5%
Min. = 4.75V
Vcc = 5.0V ± 10%
Min. = 4.50V
VLC = 0.2V
VHC = Vec - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TA = O°C to +70°C
TA = -55°C to +125°C
MIN.
TYP'(2)
MAX.
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
VIL
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
I'H
Input HIGH Current
Vee = Max .• Y'N = Vee
-
5
p.A
I'L
Input LOW Current
Vee = Max., Y,N = GND
-
-
Ise
Short Circuit Current
Vee = Max. 13)
-60
-120
SYMBOL
TEST CONDITIONS(')
PARAMETER
VOH
Output HIGH Voltage
Vcc = Min.
V1N = V1H or V'L
VOL
Vcc = Min.
Y,N = V,H or V,L
Vee
-
Vcc
-
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
-
GND
VLC
10L = 300p.A
-
GND
V LC
10L = 32mA MIL.
-
0.3
0.5
IOL = 48mA COM'L.
-
0.3
0.5
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
=
5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-118
mA
VHe
NOTES:
2. Typical values are at Vee
p.A
-
VHe
Vcc = 3V, Y,N = V LC or VHc , 10L = 3OOl'A
Output LOW Voltage
-5
10H = -300p.A
Vee = 3V, Y,N = VLe or VHe , 10H = -32p.A
UNIT
V
V
IDT54n4FCT193/A FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; vHC = vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc = Max.
V'N'" VHC; V'N =0 VLC
ICPu=lcPo=li =0
ICCT
Power Supply Current
TTL Input HIGH
VCC = Max.
V'N = 3.4V(4)
Icco
Dynamic Power
Supply Current
Vcc = Max.
Outputs Open
Count Up or Down
PL = Po - P 3 = VHC
MR = VLC
Total Power
Supply Current
Vcc = Max.
Outputs Open
Icp= 10MHz
50% Duty Cycle
Count Up or Down
PL=P o -P 3 =VHc
MR = VLC
Icc
TYP'(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V'N'" VHC
V'N=O VLC
-
0.3
-
mAl
MHz
V'N"'VHC
V'N=O VLC
(FCT)
-
3.0
-
V'N = 3.4V
or
V'N = GND
-
3.8
-
TEST CONDITIONS(1)
PARAMETER
MIN.
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: S.OV, +25°C ambient and maximum loading.
3. Not more than one output shold be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Per TTL driven input (V 1N ::: 3.4V); all other inputs at Vee or GND.
5.
Icc::: IQUIESCENT
+ 'INPUTS + 'DYNAMIC
Icc:::: ICGQ + ICCTDHNT + ICGD (fep + fjNj)
leGQ::: Quiescent Current
leeT::: Power Supply Current for a TTL High Input (V 1N = 3.4V)
DH = Duty Cycle for TTL Input High
NT = Number of TTL Inputs at DH
I eCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Count Clock or Load Clock Frequency
fi = PO_3lnput Frequency (Load)
Ni = Number of Po_3 lnputs at fi (Load)
All currents are in milliamps and all frequencies are in megahertz.
5-119
IDT54174FCTI93/A FAST CMOS UP/DOWN BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DESCRIPTION
MR
PL
CPu
CPo
MODE
CPu
CPo
MR
PL
P O-P 3
9D:-Q 3
TC o
TC u
Count Up Clock Input (Active Rising Edge)
Count Down Clock Input (Active Rising Edge)
Asynchronous Master Reset (Active HIGH)
Asynchronous Parallel Load Input (Active LOW)
Parallel Data Inputs
Flip-flop Outputs
Terminal Count Down (Borrow) Output (Active LOW)
Terminal Count Up (Carry) Output (Active LOW)
H
L
L
L
L
X
X
X
X
X
H
f
H
H
H
f
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down
L
H
H
H
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT193A
IDT54174FCT193
SYMBOL PARAMETER
CONDITION
TYP.
MIL.
COM'L.
MIN.
MAX.
MIN.
MAX.
TYP.
COM'L.
MIL.
MIN.
MAX.
MIN.
MAX.
UNITS
Propagation Delay
C.!:u or C~ to
TCuor TC o
7.0
3.5
10.5
3.5
10.5
4.6
2.0
6.9
2.0
6.5
ns
tpLH
tpHL
Propagation Delay
CPu or CPo to Q n
9.5
4.0
14.0
4.0
13.5
6.2
2.0
9.1
2.0
8.8
ns
tpLH
Propagation Delay
Pn to Q n
11.0
3.0
16.5
3.0
15.5
7.2
2.0
10.8
2.0
10.1
ns
Propagation Delay
PL to Q n
10.0
5.0
13.5
5.0
14.0
6.5
2.0
9.1
2.0
8.8
ns
t pHL
Propagation Delay
MR to Q n
11.0
6.5
16.0
6.5
15.5
7.0
3.0
10.4
3.0
10.1
ns
tpLH
PropagatioJ!..Pelay
MRtoTC u
10.5
6.0
15.0
6.0
14.5
6.5
3.0
9.8
3.0
9.4
ns
tpHL
Propagati'?!!Jlelay
MRtoTC o
11.5
7.0
16.0
7.0
15.5
7.5
3.0
10.4
3.0
10.1
ns
t pLH
Propa~on
12.0
7.0
18.5
7.0
16.5
8.0
3.0
12.0
3.0
10.8
ns
11.5
6.5
16.5
6.5
15.5
7.5
3.0
10.8
3.0
10.1
ns
4.5
6.0
-
5.0
-
4.0
5.0
-
4.0
-
ns
tpLH
tpHL
tpHL
tpLH
t pHL
tpHL
Delay
PL to TC u or TC o
tpLH
tpHL
Propagation Delay
Pn to TC u or TC o
ts(H)
ts(L)
Setup Time,
HIGH or LOW
Pn to PL
tH(H)
tH(L)
Hold Time,
HIGH or LOW
Pn to PL
2.0
2.0
-
2.0
-
1.5
1.5
-
1.5
-
ns
tw(L)
PL Pulse Width,
LOW
6.0
7.5
-
6.0
-
5.0
6.5
-
5.0
-
ns
tw(L)
CPu or CPo
Pulse Width, LOW
5.0
7.0
-
5.0
-
4.0
6.0
-
4.0
-
ns
tw(L)
CPu orCP o
Pulse Width, LOW
(Change of Direction)
10.0
12.0
-
10.0
-
8.0
10.0
-
8.0
-
ns
tw(H)
MR Pulse Width,
HIGH
6.0
6.0
-
6.0
-
5.0
5.0
-
5.0
-
ns
tREe
...J1ecovery Time
PL to CPu or CPo
6.0
8.0
-
6.0
-
5.0
7.0
-
5.0
-
ns
t REC
Recovery Time
MR to CPu or CPo
4.0
4.5
-
4.0
-
3.0
3.5
-
3.0
-
ns
C L =50pF
RL =
soon
5-120
FEATURES:
DESCRIPTION:
• IDT54174FCT240 equivalent to FASr" speed;
IDT54/74FCT240A 35% faster than FAST'"
The IDT54/74FCT240 and IDT54174FCT240A are octal buffer/
line drivers built using advanced CEMOS'", a dual metal CMOS
technology. The devices are designed to be employed as
memory and address drivers, clock drivers and bus-oriented
transmitters/receivers which provide improved board density.
• Equivalent to FASr" output drive over full
temperature and voltage supply extremes
•
•
•
•
IOl = 48mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than FASr"
(5p.A max.)
• Octal buffer/line driver with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
OEA
Vee
DA,
DEB
080
'CAo
DA,
DB,
OB1
0A1
DA,
DB,
082
0A2
DA,
DB,
0i3
0A3
OND
DB,
O"E A
SSDFCT240-001
DIP/SOIC
TOP VIEW
gl~ til~
g
DA,
OEB
080
CAo
DA,
DB,
i5i 1
0A1
DA,
DB,
082
0A2
DA.
DB,
083
CA3
LJ LJ L J LJ LJ
Oia
~9 8
GND
:::10
DB,
:11
CA,
7
::::12
6
5
43:::
08,
2:::
1::::::
OEA
20:'::::
DA,
DB.
SSDFCT240-003
Vee
DEB
DB,
SSDFCT240-002
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in the U.S.A.
5-121
IDT54/74FCT240/A FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
-55 to +125
-65 to +155
·C
120
120
mA
Storage
TSTG
Temperature
lOUT
DC Output Current
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = O.2V
VHe = Vee - O.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
I,L
Input HIGH Current
Vee = Max., Y'N = Vee
-
-
5
p.A
Input LOW Current
Vee = Max., V,N = GND
-
-
-5
p.A
Ise
Short Circuit Current
Vee = Max. (3)
-60
-120
-
mA
SYMBOL
TEST CONDITIONs(1)
PARAMETER
VHe
Vee
-
10H =-300p.A
VHe
-
10H = -12mA MIL.
2.4
Vee
4.3
10H =-15mA COM'L.
2.4
Vee = 3V, V,N = VLe or VHC , 10H = -32p.A
VOH
Output HIGH Voltage
Vee = Min.
V,N = V,H or V'L
Vee = 3V, V,N = VLe or VHe , 10L =300p.A
VOL
Output LOW Voltage
GND
=300p.A
-
GND
VLe
10L = 48mA MIL.
-
0.3
0.55
-
0.3
0.55
10L
=64mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-122
V
-
-
10L
Vee =Min.
V,N = V,H or V'L
4.3
-
VLe
V
IDT54/74FCT240/A FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vcc - O.2V
VLC ~ O.2V; VHC ~
SYMBOL
TVP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V1N :2':V HC
VIN ::; VLC
-
0.15
0.25
mAl
MHz
V,NOO> VHe
Y'N <; VLe
(FCT)
-
1.5
4.0
Y'N ~ 3.4V
Y'N ~ GND
-
1.8
4.8
Y'N <; VLe
(FCT)
-
3.0
6.5
Y'N ~ 3.4V
Y'N ~ GND
-
5.0
12.9
TEST CONDITIONS(1)
PARAMETER
MIN.
Vee ~ Max.
leeQ
Quiescent Power Supply Current
VIN ~ V HC ; VIN:S V LC
I;~ 0
leeT
Quiescent Power Supply Current
TTL Inputs HIGH
Vee ~ Max.
V IN ~ 3.4v(3)
IceD
Dynamic Power Supply
Current
~ Max.
Output~Open
Vee
Icc
Total Power Supply(')
Current
OE A ~ OE B ~ GND
One Input Toggling
50% Duty Cycle
Vee ~ Max.
Outputs Open
Ii ~ 10MHz
50% DLJI}'Cycie
OE A ~ OEs ~ GND
One Bit Toggling
Vee ~ Max.
Outputs Open
Ii ~ 2.5MHz
50% DLJI}'Cycie
OE A ~ OE B ~ GND
Eight Bits Toggling
mA
VIN ;:::: VHC
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V 1N = 3.4V); all other inputs at Vee or GND
4.
Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc::O Icea + IccrOHNr + ICGD (fcp/2 + fjNj)
leca = Quiescent Current
leeT = Power Supply Current for a TTL High Input (V 1N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT'" Number of TTL Inputs at DH
ICCD'" Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp
=Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj ::: Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-123
IDT54/74FCT240/A FAST CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
TRUTH TABLE
INPUTS
PIN NAMES
DESCRIPTION
OEA,OE s
Dxx
Oxx
3-State Output Enable Input (Active LOW)
Inputs
Outputs
OUTPUT
OEA,OE B
D
L
L
H
L
H
H
L
Z
X
H =HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z ::: High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT240
SYMBOL
tpLH
PARAMETER
CONDITION
Propagatio~ Delay
tpHl
ON to ON
tZH
tZl
Output Enable
Time
tHZ
tlZ
Output Disable
Time
TYP.
5.0
Cl
Rl
= 50p!
=500n
7.0
COM'L.
IDT54/74FCT240A
TYP.
MIL.
MIN.
MAX.
MIN.
MAX.
2.0
8.0
2.0
9.0
2.0
10.0
2.0
10.5
COM'L.
3.5
4.8
'.'
6.0
2.0
9.5
5-124
2.0
12.5
:~i;
MIN.
MAX.
1.5
4.8
MAX.
do/1.~
~~Jf
ns
1.5
6.5
ns
1.5
5.9
ns
,,"t5 {';.~:{i':~'
/ 1.5
5.6
UNITS
MIL.
MIN.
1'.
FEATURES:
DESCRIPTION:
• IDT54174FCT244 equivalent to FASr" speed;
IDT54174FCT244A 35% faster than FAST'"
The IDT54174FCT244 and IDT54/74FCT244A are octal buffer/
line drivers built using advanced CEMOS'", a dual metal CMOS
technology. The devices are designed to be employed as memory
and address drivers, clock drivers and bus-oriented transmitters/
receivers which provide improved PC and board density.
• Equivalent to FAST'" output drive over full
temperature and voltage supply extremes
IOL = 48mA over full military temperature range
CMOS power levels (5jLW typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than FASr"
(5jLA max.)
• Octal buffer/line driver with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is available
•
•
•
•
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
OEA
Vee
DA.
OEa
DB.
OA.
DA,
DB.
DB,
OA,
DA2
DB,
OB2
OA2
DA,
DB2
DB,
OA,
OND
DB,
OEA
SSD54174FCT244-001
DIP/SOIC
TOPYIEW
~
£
0
~
iij
0
i
DA,
DEe
DB,
OA,
DA,
DB,
DB,
OA,
DA,
DB,
DB,
OA,
DA,
DB,
DB,
OA,
&I
LJ LJ L J L J LJ
DB,
~98
OND
::::10
DB,
OA,
:11
:12
7
6
5
43:::
.:::
DB,
DB,
DA.
OEA
SSD54/74FCT244-003
Vee
OEa
DB,
SSD?4/74FCT244-002
LCC/PLCC
TOPYIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in the U.S.A.
5-125
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54174FCT244/A FAST CMOS OCTAL BUFFER/LINE DRIVER
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FOllowing Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = O.2V
VHe = Vee - O.2V
= 4.75V
= 4.50V
Max. = 5.25V (CommerCial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V'L
I nput LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vee
-
-
5
p.A
-
-
-5
p.A
-60
-120
-
mA
SYMBOL
TEST CONDITIONS(1)
PARAMETER
I'L
Input LOW Current
= Max., Y'N = Vee
Vee = Max., Y'N = GND
Ise
Short Circuit Current
Vee = Max. (3)
VOH
Output HIGH Voltage
Vee = Min.
Y'N = V,H or V'L
= -32p.A
VHe
Vee
-
10H = -300p.A
VHe
Vee
-
10H = -12mA MIL.
2.4
4.3
-
Vee = 3V, Y'N = VLe or VHCo 10H
10H
= -15mA COM'L.
=300p.A
VOL
Output LOW Voltage
Vee = Min.
V1N = VJH or V1L
Hysteresis
4.3
10L = 300p.A
-
GND
V Le
10L = 48mA MIL.
-
0.3
0.55
-
0.3
0.55
-
0.4
-
= 64mA COM'L.
On Data Inputs
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at
vee:: 5.0V,
+25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-126
-
GND
10L
V+- V-
2.4
-
Vee = 3V, Y'N = VLe or VHe , 10L
V
VLe
V
V
IDT54/74FCT244/A FAST CMOS OCTAL BUFFERILINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
Icco
Quiescent Power Supply Current
Vcc= Max.
V1N ;;, VHo V1N ';; VLC
Ii =0
ICCT
Power Supply Current
TTL Inputs H)GH
Vee = Max.
V 1N = 3.4V I3)
ICCD
Dynamic Power Supply
Current
Vcc= Max.
Outputs Open
OE A = OEe = GND
One Input Toggling
50% Duty Cycle
Icc
MIN.
TVP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V1N;;,VHC
V1N ,;; VLC
-
0.15
0.25
V1N;;'VHC
V1N ';; VLc (FCT)
-
1.5
4.0
V1N = 3.4V
V1N=GND
-
1.8
4.8
V1N;;'VHC
V1N ';; VLc (FCT)
-
3.0
6.5
V1N = 3.4V
V1N=GND
-
5.0
12.9
TEST CONDITIONS(1)
PARAMETER
Vcc= Max.
Outputs Open
Ii = 10MHz
50% Dl!!Y.Cycle
OE A = OEe = GND
One Bit Toggling
Total Power Supply!')
Current
Vcc= Max.
Outputs Open
Ii = 2.5MHz
50% Dl!!Y.Cycle
OE A = OEe = GND
Eight Bits Toggling
mA
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values Bfe at Vee
=S.OV. +25°C ambient and maximum loading.
3. Per TTL driven input (V 1N = 3.4V); all other inputs at Vcc or GND.
4. Icc = 'aUIESCENT + 'INPUTS + 'DYNAMIC
tcc = Icca + ICCTDHNT + ICCD (l cp /2 + flNi)
'ceQ = QUiescent Current
ICCT = Power Supply Current for a TTL High Input (V 1N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for
Non~Register
Devices)
Ii = Input Frequency
Nj = Number of Inputs at Ii
All currents are in milliamps and all frequencies are in megahertz.
5-127
mAl
MHz
IDT54/74FCT244/A FAST CMOS OCTAL BUFFERILINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OEA,OE e
Dxx
Oxx
TRUTH TABLE
DESCRIPTION
INPUTS
3-State Output Enable Input (Active LOW)
Inputs
Outputs
OUTPUT
OEA,OE s
D
L
L
L
L
H
H
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT244A
IDT54/74FCT244
SYMBOL
PARAMETER
CONDITION
Propagation Delay
DNtO ON
tZH
tZL
Output Enable
Time
Output Disable
Time
C L = SOp!
RL = soon
TYP.
COM'L,
MIL,
TYP.
MIN.
MAX.
MIN.
MAX.
4.S
2.S
6.5
2.0
7.0
6.0
2.0
8.0
2.0
8.S
MAX.
MIL.
MIN.
UNITS
M~I'
ns
3.1
¥~~k,,'~~~4
1.5
5.5
ns
1.5
1.5
4.9
ns
~--~~--4----+----+----t1Th0~~'
3.3
7.0
2.0
7.5
5.0
2.0
5-128
COM'L.
MIN.
4.6
FEATURES:
DESCRIPTION:
• IDT54/74FCT245 equivalent to FASr" speed;
IDT54174FCT245A 35% faster than FAST'"
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
The IDT54/74FCT245 and IDT54/74FCT245A are 8-bit noninverting, bidirectional buffers built using advanced CEMOS'", a
dual metal CMOS technology. These bidirectional buffers have
3-state outputs and are intended for bus-oriented applications.
The Transmit/Receive (TiR) input determines the direction of
data flow through the bidirectional transceiver. Transmit (active
HIGH) enables data from A ports to B ports. Receive (active
LOW) enables data from B ports to A ports. The Output Enable
(OE) input, when HIGH, disables both A and B ports by placing
them in High Z condition.
• IOL = 48mA port A, 48mA port B over full military
temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FASr"
(5p.A max.)
• Non-inverting buffer transceiver
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
T/R
Vee
Ao
DE
A,
Bo
A,
B,
A,
B,
A_
B,
A,
B_
A,
B,
A,
B,
GND
B,
DE
Ao
Bo
A,
B,
A,
B,
A,
B.
DIP/SDIC
TOP VIEW
A_
B.
SSD54/74FCT245-001
A,
B,
A,
B,
A,
LJ L J LJ LJ LJ
A7
GND
:::9 8
7
6
5
43:
A1
2~
Ao
:::10
:::11
B,
T/R
SSDS4174FCT24S-003
Vee
DE
LCC/PLCC
TOP VIEW
SSD54fl4FCT24S-002
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
JULY 1986
Printed in U.S.A.
1986 Integrated Oevice Technology, Inc.
5-129
IDT54174FCT245/A
FAST CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltl\ge
with Respect
toGND
Operating
TA
Temperat~rE!
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
oto +70
-55 to +125
·C
·C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output CUrrent
120
120
mA
NOTE:
I. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
Indicated in the operational sections of this specification js not Implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125·C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = O.2V
VHc = Vce - O.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TA = O°C to +70°C
MIN.
TYPo(2)
MAX.
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V,l
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
I'H
Input HIGH Current
(Except I/O Pins)
Vec = Max., Y,N = Vce
-
-
5
/LA
I'l
Input LOW Current
(Except I/O Pins)
Vce = Max., Y,N = GND
-
-
-5
/LA
Ise
Short Circuit Current
Vee = Max. (3)
-60
-120
-
mA
VOH
Output HIGH Voltage Ports A and B
SYMBOL
TEST CONDITIONS(1)
PARAMETER
VHC
VCC
-
10H= -300/LA
VHC
Vcc
IOH=-12mAMIL.
2.4
4.3
-
10H = -15mA COM'L.
2.4
4.3
-
-
GND
VlC
-
GND
VlC
0.3
0.55
0.3
0.55
Vee = 3V, Y'N = VlC or VHC' 10H = -3~A
Vee = Min.
Y,N = V,H or V,l
VCC = 3V, Y'N = VlC or VHC ' 10l = 300/LA
Val
Output LOW Voltage Port A
10l = 300/LA
Vec= Min.
Y'N = V,H or V,l
10l = 48mA MIL.
GND
VlC
10l = 300I'A
-
GND
Vle
10l = 48mA MIL.
-
0.3
0.55
lal = 64mA COM'L.
-
0.3
0.55
-
0.4
-
10l = 64mA COM'L.
Vcc = 3V, Y'N = VlC or VHC' 10l = 300/LA
VOL
Output LOW Voltage Port B
Vec= Min.
Y'N = V,H or V,l
V+-V-
Hysteresis
OnAi and Bi
NOTES:
1. For conditions shown as max. or min .• use appropriat~ value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV, +250 C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-130
UNIT
V
V
V
V
IDT54/74FCT245/A
FAST CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =O.2V; VHC = vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
VCC = Max.
V,N e: VHc: V,N '" VLC
Ii =0
ICCT
Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V ,N = 3.4V (3)
Dynamic Power Supply Current
Vcc = Max.
Outputs Open
OE= GND
T/R = GND or Vcc
One Input Toggling
50% Duty Cycle
ICCD
Total Power Supply Current(4)
Icc
MIN.
TYp.!')
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V,Ne: VHC;
V,N ", VLC
-
0.15
0.25
V,N ", VHC
V,N ", VLC (FCT)
-
1.5
4.0
V,N = 3.4Vor
V,N = GND
-
1.8
4.8
V,Ne: VLC
VCC "" VLC (FCT)
-
3.0
6.5
V,N = 3.4V or
V,N = GND
-
5.0
12.9
TEST CONDITIONS!')
PARAMETER
Vcc = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE= GND
One Bit Toggling
Vcc = Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
OE= GND
Eight Bits Toggling
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at vee::: 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven input (VIN ::: 3.4V); all other inputs at Vee or GND.
4. Icc:::
'QUIESCENT
+
'INPUTS + 'DYNAMIC
Icc::: 'CGQ + ICCTDHNT + 'CGD (fcp/2 + fjNj)
ICGQ ::: Quiescent Current
'eeT::: Power Supply Current for a TTL High Input (V IN ::: 3AV)
DH = Duty Cycle for TTL Inputs High
NT::: Number of TTL Inputs at DH
IceD::: Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp::: Clock Frequency for Register Devices (Zero for Non-Register Devices)
fj ::: Input Frequency
Ni ::: Number of Inputs at fj
All currents are in milliamps and all frequencies are in megahertz.
5-131
mAl
MHz
IDT54/74FCT245/A
FAST CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
OE
T/R
Ao-A,
Bo-Bo
INPUTS
DESCRIPTION
PIN NAMES
Output Enable I nput (Active LOW)
Transmit/Receive Input
Side A Inputs or
3-State Outputs
Side B Inputs or
3-State Outputs
OE
OUTPUT
T/R
L
H
L
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
High Z State
H = HIGH Voltage Level
L =LOW Voltage Level
X = Don't care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT245
SYMBOL
t pLH
t pHL
PARAMETER
Propagation Delay
AtoB
BtoA
tZH
tZL
Output Enable
Time
tHZ
tLZ
Output Disable
Time
tOLH
tOHL
CONDITION
Prol'.-agation Delay
T/R to A or B(1)
COM'L.
TYP.
5.0
IDT54174FCT245A
MIL.
COM'L.
TYP.
MIN.
MAX.
MIN.
MAX.
2.5
7.0
2.0
7.5
3.3
MIN.
MAX.
1.5
4.6
MIL.
MIN.
1.5
~+,
1,
C L =50 pF
RL = 500n
6.0
3.0
9.5
3.0
10.0
4.8
1.5
•• C'f'C
6.0
2.0
7.5
2.5
6.0
-
-
-
NOTE:
1. Guaranteed by design.
5-132
10.0
-
~~;;~ 1;:r:t'"
5.0
-
:,~~S0 r'l5
UNITS
MAX.
~
,4,4
ns
6.5
ns
~\
<
5.0
1.5
6.0
ns
-
-
-
ns
FEATURES:
DESCRIPTION:
• IDT54174FCT273 equivalent to FAST'" speed;
IDT54174FCT273A 35% faster than FAST'"
The IDT54174FCT273 and IDT54/74FCT273A are octal flipflops built using advanced CEMOS'", a dual metal CMOS technology. The IDT54!74FCT273 and IDT54174FCT273A have eight
edge-triggered D-type flip-flops with individual D inputs and 0
outputs. The common buffered Clock (CP) and Master Reset
(MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input,
one setup time before the LOW-to-HIGH clock transition, is
transferred to the corresponding flip-flop's 0 output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is
useful for applications where the true output only is required and
the Clock and Master Reset are common to all storage elements.
• Equivalent to FAST'" output drive over full temperature and
voltage supply extremes
• IOL
= 32mA over full military temperature range
• CMOS power levels (5p.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FAST'"
(5p.A max.)
• Octal D flip-flop with clear
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
Mil
Vee
00
0,
00
0,
0,
0,
0,
0,
03
0,
05
GND
Ll LJ LJ
0,
05
0,
0,
0,
0,
GNO
CP
:::9 8
7
LJ LJ
6
5
43:::
Do
2:::
00
:::10
SSDAHCT273-002
SSOAHCT273-001
LCC/PLCC
TOP VIEW
DIP/SOIC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
0,
00
0,
0,
05
0,
cP--C>o-~------~+-----~~------~~----~~------~~----~~------,
a
o
00
a
a
0,
o
a
0,
o
0,
a
o
a
o
05
a
o
0,
a
0,
SSDAHCT273-003
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U S,A
5-133
IDT54174FCT273/A CMOS OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections' 01 this specification is not Implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vcc =5.0V ± 5%
Min.
TA =-55°C to +125°C
Vcc =5.0V ± 10%
Min.
VLc = O.2V
VHC = Vee - O.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYp'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
-
0.8
V
I'H
Input HIGH Current
Vec = Max., V,N = Vee
-
-
5
",A
I'L
Input LOW Current
Vee
Ise
Short Circuit Current
Vee = Max. (3)
VOH
Output HIGH Voltage
SYMBOL
TEST CONDITIONS(1)
PARAMETER
-
-
-5
",A
-80
-120
-
rnA
=Max., V,N =GND
=
Vee Min.
V,N V,H or V,l
=
=-32",A
VHe
Vee
-
=-300",A
VHe
Vee
-
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
-
GND
Vle
GND
VLC
-
0.4
Vee = 3V, V,N = VLC or VHe, 10H
10H
=VLe or VHe, 10L =300",A
10L =300I'A
Vee =Min.
10l =32mA MIL.
V,N =V,H or V,l
Vee = 3V, V,N
VOL
Output LOW Voltage
10l = 48mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +2S Q C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-134
0.5
V
V
IDT54174FCT273/A CMOS OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; vHC = vcc - O.2V
SYMBOL
leeo
Quiescent Power Supply Current
Vee 0 Max.
V1N 2:: VHC ; V1N :::; VLC
fep 0 fi = 0
IceT
Quiescent Power Supply Current
TTL Inputs HIGH
Vee 0 Max.
V'N = 3.4V I3 )
Dynamic Power Supply
Current
Vee = Max.
Outputs Open
MR 0 Vee
One Bit Toggling
50% Duty Cycle
ICGD
Icc
Total Power Suppl y l 4)
Current
TYP'(2j
MAX.
UNIT
-
0001
1.5
rnA
-
0.5
1.6
rnA
V1N ::; VLC
-
0.15
0.25
V1N 2:: VHC
V1N :::;: VLC
(FCT)
-
1.5
4.0
V'N 0 3AV
or
V'N = GND
-
2.0
5.6
TEST CONDITIONS(l)
PARAMETER
Vee 0 Max.
Outputs Open
fep 0 10MHz
~Q~o Duty Cycle
MR 0 Vec
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
Vee = Max.
Outputs Open
Fep= 10MHz
~~o Duty Cycle
MR = Vee
Eight Bits Toggling
at Ii 0 2.5MHz
50% Duty Cycle
V1N 2: VH 6
MIN.
rnA
V1N :2:: VHC
V1N ::; VLC
(FCT)
-
3.75
7.8
V'N = 3AV
or
V'N = GND
-
6.0
15.0
NOTES:
1, For conditions shown as max. or min" use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee:::; 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven Input (V IN
4.
=
Icc::; 'QUIESCENT + IINPUTS
3.4V); all other inputs at Vee or GNO.
+
IOYNAMIC
Icc = ICGQ + ICCTDHNT + tceD (fcpf2 + fiNj)
I CGQ ;:; Quiescent Current
teeT = Power Supply Current for a TTL High Input (V IN ;:; 3.4V)
DH
;;:;
Duty Cycle for TTL Inputs High
NT
=
Number of TTL Inputs at DH
ICCD
=
Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep
=
Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl -;;; Input Frequency
Nj ::: Number of Inputs at fj
All currents are in milliamps and all frequencies are in megahertz.
5-135
mAl
MHz
IDT54174FCT273/A CMOS OCTAL D FLIP-FLOP WITH CLEAR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION
PIN NAMES
0 0-07
MR
CP
0 0-0 7
INPUTS
OPERATING MODE
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
OUTPUT
MR
CP
DN
Reset (Clear)
L
X
X
L
Load "t"
H
1
h
H
Load "0"
H
1
I
L
ON
H - HIGH Voltage Level steady state
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
L = LOW Voltage Level steady state
I = LOW Voltage Level one setup time prior to the LOW-ta-HIGH Clock Transition
X =DON'T CARE
t = LOW to HIGH clock transition
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
SYMBOL
PARAMETER
CONDITION
TYP.
COM'L.
IDT54n4FCT273A
MIL.
TYP.
MIN.
MAX.
MIN.
MAX.
COM'L.
MIL.
MAX.
MIN.
MAX.
8.3
ns
,8,.~
ns
t pLH
tpHL
Propagation Delay
Clock to Output
7.0
3.0
13.0
3.0
15.0
5.0
2.0
7.2
2.0
tpLH
PrQllllgation Delay
MR to Output
8.0
2.0
13.0
2.0
15.0
5.0
2.0
7.2
2.5
t pHL
ts
Set Up time
HIGH or LOW
Data to CP
C L =50 pf
RL =500n
3.0
3.0
-
3.5
-
1.0
2.0
J£
;!'~
Hold Time
HIGH or LOW
Data to CP
1.0
2.5
-
2.5
-
tw
Clock Pulse Width
HIGH or LOW
4.0
7.0
-
7.0
-
-
-
Recovery Time
MRtoCP
3.0
4.0
-
5.0
-
1.5
2.5
5-136
.~~: ~~.~i'
'2: i: .
tH
t REC
UNITS
MIN.
~"~'~
ns
"
1.5
-
ns
-
6.0
-
ns
-
3.0
-
ns
FEATURES:
DESCRIPTION:
• IDT54/74FCT299 equivalent to FAST'" speed;
IDT54174FCT299A 35% faster than FAST'·
The IDT54/74FCT299 and IDT54/74FCT299A are 8-bit universal shift registers built using advanced CEMOS'·, a dual metal
CMOS technology. The IDT54174FCT299 and IDT54174FCT299A
are 8-bit universal shift/storage registers with 3-state outputs.
Four modes of operation are possible: hold (store), shift left, shift
right and load data. The paralielload inputs and flip-flop outputs
are multiplexed to reduce the total number of package pins.
Additional outputs are provided for flip-flops Qa-Q 7 to allow easy
serial cascading. A separate active LOW Master Reset is used to
reset the register.
• Equivalent to FAST'· output drive over full
temperature and voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5J.1W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FAST'·
(5J.1A max.)
• 8-input universal shift register
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
s.
Vee
OEl
0E2
s,
os,
a g § g go
lJ LJ L J lJLJ
lID,
Q,
lID,
1/07
lID,
lIDs
lID.
1/0 3
CP
Q.
lID,
1/01
MR
CP
MR
::!9 8
GND
::10
os.
:::::11
:::::12
7
6
5
43:
2:::
1::::
20:::::
0E2
DE1
s.
Vee
s,
os.
GND
SSOS4174FCT299-002
SSD54174FCT299-001
DIP/SOIC
TOP VIEW
LCC/PLCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
s.
4---I----4Q7
lID.
lID,
I/Oa
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ell
lIDs
lID,
SSD54174FCT299-003
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
JULY 1986
Printed in the U.S.A.
1986 Integrated Device Technology, Inc.
5-137
IDT54n4FCT299/A FAST CMOS 8-INPUT UNIVI'RSAL SHIFT RI'GISTI'R
MILITARY AND COMMI'RCIAL Tl'MPI'RATURI' RANGI'S
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMI'RCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
T BIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation oftha d~vice at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA O°C to +70°C
Vcc 5.0V ± 5%
Min.
TA -55°C to +125°C
Vcc 5.0V ± 10%
Min.
VLC = 0.2V
VHC = VCC - 0.2V
=
=
=
=
SYMBOL
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TI'ST CONDITIONS(1)
PARAMI'TI'R
MIN.
TYP'(2)
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
V,L
Input LOW Level
Guaranteed Logic Low Level
I'H
Input HIGH Current
Vee = Max., Y'N = Vee
-
I'L
Input LOW Current
Vee = Max., Y'N = GND
-
-
Ise
Short Circuit Current
Vee = Max. (3)
-60
-120
Output HIGH Voltage
Vec= Min.
Y'N = V,H or V,L
Output LOW Voltage
loz
Off State (High Impedance)
Output Current
Vee = Min.
Y,N = V,H or V,L
Vec = Max.
V
5
p.A
-5
p.A
-
mA
VHe
Vee
Vee
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
GND
VLC
10L = 3OOp.A
-
GND
V LC
10L = 32mA MIL.
-
0.3
0.5
10L = 48mA COM'L.
-
0.3
0.5
Vo = O.4V
-
-40
Vo = 2.4V
-
-
40
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25 0 C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-138
V
0.8
VHe
Vee = 3V, Y,N = VLe or VHC , 10L = 300p.A
VOL
UNIT
-
10H = -300p.A
Vee = 3V. Y'N = VLc or VHe, 10H = -32p.A
VOH
MAX.
V
V
p.A
IDT54174FCT299/A FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC =O.2V; VHC =vcc - O.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc = Max.
Y'N ~ VHC ; Y,N :0: VLC
Icp=li =0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
Y,N = 3.4v(3)
Dynamic Power Supply
Current
VCC = Max.
Outputs Open
OE, = OE 2 = GND
MR = Vcc
So= S, = Vcc
DS o = OS, = GND
One Bit Toggling
50% Duty Cycle
Icco
Icc
Total Power Supply!')
Current
Vcc = Max.
Outputs Open
Icp = 10MHz
50% D.'!!Y Cycle
OE, = OE 2 = GND
MR = Vcc
So = S, = Vcc
DS o = DS 7 = GND
One Bit Toggling
at Ii = 5MHz
50% Duty Cycle
Vcc = Max.
Outputs Open
Icp = 10MHz
50% D.'!!Y Cycle
OE, = OE 2 = GND
MR = Vcc
So = S, = Vcc
DS o = OS, = GND
Eight Bits Toggling
at Ii = 2.5MHz
50% Duty Cycle
Y'N ~ VHC
V,N:O: VLC
Y'N ~ VHC
V1N :::; VLC
(FCT)
Y'N = 3.4V
Y'N =GND
MIN.
TYp'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
-
1.5
4.0
-
2.0
5.6
mA
Y,N ~ VHC
V,N:o: VLC
(FCT)
-
3.75
7.8
Y,N = 3.4V
Y,N = GND
-
6.0
15.0
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (V 1N = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'QUIESCENT + 'INPUTS + 'DYNAMIC
Icc = ICGQ + ICCTDHNT + ICGD (fcpf2 + fjNj)
ICGQ = Quiescent Current
leeT:: Power Supply Current for a TTL High Input (V 1N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
Ii = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-139
mAl
MHz
IDT54174FCT299/A FAST CMOS a-INPUT UNIVERSAL SHIFT REGISTER
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
CP
DS o
DS 7
So. S,
MR
OE,. OE 2
110 0-1/0 7
0 0• 0 7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
INPUTS
DESCRIPTION
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Inputs
Serial Outputs
RESPONSE
MR
Sl
So
CP
L
H
H
H
H
X
H
L
H
L
X
H
H
L
L
I
I
I
X
Asynchronous Reset; 0 0-0 7 = LOW
Parallel Load; lION - ON
Shift Right; DS o - 0 0. 0 0 etc.
Shift Left; DS 7 - 0 7• 0 7 - 0 6 • etc.
Hold
a,.
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT299
SYMBOL
t pLH
t pHL
tplH
tpHL
tpHL
tpHL
PARAMETER
TYP.
MIN.
MAX.
MIN.
MAX.
COM'L.
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
10.0
4.0
14.0
5.0
2.5
7.2
2.5
9.5
ns
Propagation Delay
CPto lION
6.0
4.0
12.0
3.5
12.0
5.0
2.5
7.2
2.5
9.5
ns
7.0
4.5
10.0
4.0
12.0
5.0
2.5
7.2
2.5
9.5
ns
7.0
6.5
15.0
7.0
15.0
6.0
2.5
6.7
2.5
11.5
ns
6.0
3.5
11.0
4.0
15.0
5.5
1.5
6.5
1.5
7.5
ns
5.5
2.0
7.0
3.0
9.0
4.0
1.5
5.5
1.5
6.5
ns
P~agation
Delay
MR to Ooor 0 7
Pro~ation
Delay
MR to lION
Outp~Disable
tH
IDT54174FCT299A
MIL.
3.5
t pHZ
ts
COM'L.
7.0
OutP-'!!...Enable Time
OEto liON
t plZ
TYP.
Propagation Delay
CPto 000r07
tpZL
tpZH
CONDITION
Time
OEto lION
Setup Time
HIGH or LOW
Soor S, to CP
Hold Time
HIGH or LOW
Soor S, to CP
::,;\
2.0
Cl
Rl
6.5
-
6.5
-
4.0
2.5
=50pF
=soon
-
5.~~
~
0
0
-
0
-
-1.5
~'.
',.
~~;,~
~.~i\i; \;
..
,r;
I"'"
ns
0
-
ns
%
ts
Setup Time HIGH
or LOW. liON.
DS o or DS 7 to CP
0.5
5.5
-
5.5
-
2.5
4.0
-
5.0
-
ns
ts
Hold Time HIGH
or LOW. lION.
DS o or DS 7 to CP
0
2.0
-
2.0
-
1.0
2.0
-
2.0
-
ns
tw
CP Pulse Width
HIGH or LOW
7.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
7.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
7.0
7.0
-
7.0
-
4.0
5.0
-
6.0
-
ns
tw
t REC
MR Pulse Width
LOW
Recovery Time
MRtoCP
5-140
FEATURES:
DESCRIPTION:
• IDT54174FCT373 equivalent to FAST'" speed;
IDT54/74FCT373A 35% faster than FAST'·
The IDT54/74FCT373 and IDT54/74FCT373A are 8-bit latches
built using advanced CEMOS'·, a dual metal CMOS technology.
These octal latches have 3-state outputs and are intended for
bus-oriented applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is HIGH. When LE is LOW, the
data that meets the setup times is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
• Equivalent to FAST'" output drive over full temperature and
voltage supply extremes.
• IOL = 32mA over full military temperature range
• CMOS power levels (5J.LW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FAST'·
(5J.LA max.)
• Octal transparent latch with enable
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
DE
v"
00
0,
Do
0,
0,
0,
0,
0,
0,
Os
0,
030202 01 0 1
lJ lJLJ lJLJ
0,
7
:!9 8
6
5
43:
Do
GND
::10
2:::
00
0,
LE
:::11
1::::
DE
0,
0,
0,
:::12
20::
v"
0,
0,
0,
GND
LE
0,
05
as as
II
06 D7
SSD54/74FCT373-001
SSD54/74FCT373<-OO2
DIP/SOle
TQPVIEW
LCC/PLCC
TQPVIEW
FUNCTIONAL BLOCK DIAGRAM
DO
0,
0,
0,
0,
0,
0,
LE --~.~D---~----+---~~---1----~----~----~----~--~~---+----~----+---~~---1----~
DE ---q:~----~----+---~~---1----~----~----~----~--~~---+----~----+---~~--~r---~
00
0,
0,
0,
0,
o.
07
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
SSD54174FCT373-003
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
@
1986 Integrated Device Technology, Inc.
Printed in U.S.A.
5-141
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT373/A FAST CMOS DCTAL TRANSPARENT LATCH
ABSOLUTE MAXIMUM RATING(1)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.510 +7.0
V
VTERM
Terminal Voltage
with Respect
10GND
TA
Operaling
Temperature
o to +70
-55 to +125
°C
T BIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
=O°C to +70°C
Vee =5.0V ± 5%
Min.
=-55°C to +125°C
Vee =5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
TA
TA
= 4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V,L
I n put LOW Level
Guaranteed Logic Low Level
I'H
Input HIGH Current
Vcc
-
-
SYMBOL
I,L
Input LOW Current
Ise
Short Circuit Current
VOH
VOL
TEST CONDITIONS(!)
PARAMETER
Output HIGH Voltage
Output LOW Voltage
=Max., V,N =Vee
Vee =Max., V,N =GND
Vee =Max.!")
Vee =3V, V,N =VLe or VHe,
VHe
Vee
10H
VHe
Vee
2.4
4.3
10H =-32p.A
=-300p.A
Vee =Min.
10H =-12mA MIL.
V,N =V,H or V,L
10H =-15mA COM'L.
Vee =3V, V,N =VLe or VHe , 10L =300p.A
10L =300p.A
Vee =Min.
10L =32mA MIL.
V,N =V,H or V,L
10L =48mA COM'L.
-60
-120
2. Typical values are at Vee
=
5.0V, +25°C ambient and maximum loading.
5-142
V
5
p.A
-5
p.A
-
mA
-
4.3
-
-
GND
VLe
-
GND
VLC
-
0.3
0.5
-
0.3
0.5
2.4
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
0.8
V
V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54174FCT373/A FAST CMOS OCTAL TRANSPARENT LATCH
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc = Max.
VIN 2 VH6 VIN " VLC
li=O
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V IN = 3.4V(3)
Iceo
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
OE = GND
LE = Vcc
One Input Toggling
50% Duty Cycle
Icc
Total Power Supply(')
Current
VIN 20VHC
V1N :$; VlC
MIN.
TYP.!')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
Vcc= Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE =GND
LE = Vcc
One Bit Toggling
V1N 2oVHC
V1N"VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
V1N=GND
-
1.8
5.6
Vcc = Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
OE =GND
LE = Vcc
Eight Bits Toggling
V 1N 2oVHC
V1N"VLC
(FCT)
-
3.0
6.5
VIN = 3.4V
VIN = GND
-
5.0
12.9
mA
NOTES:
1. For conditions shown as max. or min .. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc
= IQUIESCENT + IINPUTS + IDYNAMIC
Icc = Icca + ICCTDHNT + ICCD (fcp/2 + fjNj)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
=Number of TTL Inputs at DH
=Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp =Clock Frequency for Register Devices (Zero for Non-Register Devices)
fj =Input Frequency
NT
IceD
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-143
mAl
MHz
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT373/A FAST CMOS OCTAL TRANSPARENT LATCH
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0-0 7
LE
OE
0 0-0,
TRUTH TABLE
DESCRIPTION
INPUTS
Dala Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Latch Outputs
OUTPUTS
On
LE
OE
On
H
L
X
H
H
X
L
L
H
H
L
Z
H = HIGH Voltage Level
L =LOW Voltage Level
X = Don't Care
Z = High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT373A
ID.T54/74FCT373
SYMBOL
PARAMETER
CONDITION
TYP.
COM'L.
MIL.
MIN.
MAX.
MIN.
MAX.
TYP.
COM'L.
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
tpHL
Propagation Delay
On to On
5.0
2.0
8.0
2.0
8.5
4.0
1.5
5.2
1.5
5.6
ns
tZH
tZL
Output Enable
Time
7.0
2.0
12.0
2.0
13.5
5.5
1.5
6.5
1.5
7.5
ns
tHZ
tLZ
Output Disable
Time
6.0
2.0
7.5
2.0
10.0
4.0
1.5
5.5, .
tpLH
Propagation Delay
LE to On
tpLH
tpHL
C L =50pf
RL =5000
9.0
3.0
13.0
3.0
15.0
7.0
d*"'
ts
Set up Time
HIGH or LOW
On to LE
1.0
2.0
-
2.0
-
tH
Hold Time
HIGH or LOW
On to LE
1.0
3.0
-
3.0
-
tw
LE Pulse Width
HIGH or LOW
5.0
6.0
-
6.0
-
5-144
"('1'
':01.~t
I,tt:~f'~ lni~s
t ..
2.0
~'a~~
ns
9.8
ns
2.0
-
2.0
-
ns
1.0
1.8
-
1.8
-
ns
4.0
6.0
-
5.0
-
ns
FEATURES:
DESCRIPTION:
• IDT54174FCT374 equivalent to FASr" speed;
IDT54174FCT374A 35% laster than FAST'"
The IDT54/75FCT374 and IDT54174FCT374A are 8-bit registers built using advanced CEMOS~ a dual metal CMOS
technology. These registers consist of eight D-type flip-flops
with a buffered common clock and buffered three-state output
control. When the output enable (OE) input is LOW, the eight
outputs are enabled. When the OE input is HIGH, the outputs
are in the three-state conditions.
Input data meeting the setup and hold time requirements of
the D inputs is transferred the the 0 outputs on the LOW-toHIGH transition of the clock input.
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
•
•
•
•
IOL = 32m A over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than FASr"
(5p.A max.)
• Positive, edge-triggered masterlslave, D-type flip-flops
• Buffered common clock and buffered common three-state
control
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
881~~o
vcc
07
07
06
00
Do
0,
0,
0,
0,
02
02
03
06
05
02
03
05
04
03
04
GND
CP
02
lJ lJ IllJ lJ
3 2 ~J 20 1918~
~4
1
=.
=6
=7
17:::::
16:::
15:::::
~8
~
9
10
07
06
06
05
05
II
SSDAHCT374-002
LCC/PLCC
TOP VIEW
SSDAHCT374-001
DIP/SOIC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
Do
06
05
CLO~~--C>~--~+-----~-+----~~------~+-----~-+----~~~----~~-----'
OE
OUTPUT~~~~+-----~-r----~~----~~+-----~-r----~~------+-+-----~
ENABLE
00
05
06
SSDAHCT374·003
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in the U.S.A.
@1986 Integrated Device Technology, Inc.
5-145
IDT54n4FCT374/A FAST CMOS OCTAL D REGISTERS (:J.,STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOi..UTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-{l.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
oto +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
·C
lOUT
DC Output Current
120
120
mA
NOTE:
I. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This Is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O·C to +70·C
Vcc = 5.0V ± 5%
Min. = 4.75V
TA = -55·C to +125·C
Vcc = 5.0V ± 10%
Min. = 4.50V
VLc = 0.2V
VHC = Vce - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
I'H
Input HIGH Current
Vee
=Max., Y'N = Vee
Vee = Max., Y,N =GND
Vee =Max. (3)
Vee =3V, Y'N =VLe or VHe,
-
-
SYMBOL
I'L
Input LOW Current
Ise
Short Circuit Current
Output HIGH Voltage
VOH
VOL
TEST CONDITIONS(1)
PARAMETER
.
=Min.
Y,N =V,H or V,L
Vce
10H =-32p.A
-
-
-60
-120
VHe
Vee
10H =-300p.A
VHC
Vec
10H =-12mA MIL.
2.4
4.3
10H =-15mA COM'L.
=3V, Y'N =VLe or VHe , 10L =300p.A
10L =300p.A
Vee =Min.
10L =32mA MIL.
Y'N =V,H or V,L
10L =48mA COM'L.
Vee
Output LOW Voltage
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
5-146
V
5
pA
~5
p.A
-
mA
2.4
4.3
-
-
GND
V Le
GND
VU:;
0.3
0.5
0.3
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
0.8
V
V
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT374/A FAST CMOS OCTAL D REGISTERS (3-STATE)
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
Icca
Quiescent Power Supply Current
Vcc = Max.
V,N 2: VHC ; V,N S VLC
Icp=I,=O
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V,N = 3.4V(3)
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
OE= GND
One Bit Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply!')
Current
MIN.
TYp'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N 2: VHC
V1N ::; VLC
-
0.15
0.25
mAl
MHz
V,N 2: VHC
V,NS VLC
(FCT)
-
1.5
4.0
V,N = 3AV
or
V,N=GND
-
2.0
5.6
V,N 2: VHC
V,N '; VLC
(FCT)
-
3.75
7.8
V,N = 3AV
or
V,N=GND
-
6.0
15.0
TEST CONDITIONS I!)
PARAMETER
Vcc = Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
at Ii = 5MHz
50% Duty Cycle
Vcc = Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at Ii = 2.5MHz
50% Duty Cycle
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vee or GND.
4.
+ 'INPUTS + 'DYNAMIC
Icc = 'ceQ + ICCTDHNT + ICGD (fcp/2 + fiNi)
ICGQ = Quiescent Current
Icc = 'aUIESCENT
'eeT
=Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD = Dynamic Current caused by an Input Transition pair (HlH or lHl)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-147
IDT54174FCT374/A FAST CMOS OCTAL 0 REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0-0 7
CP
OE
0 0-0 7
TRUTH TABLE
DESCRIPTION
OUTPUTS
INPUTS
FUNCTION
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-State Output Enable Input (Active LOW)
Complementary 3-State Outputs
INTERNAL
OE
CP
01
ON
Hi-Z
H
H
L
H
X
X
Z
Z
NC
NC
LOAD
REGISTER
L
L
H
H
L
H
L
H
H
L
Z
Z
H
L
H
L
H
L
X
Z
J
NC
J
J
J
J
01
=HIGH
=LOW
:=
Don't Care
= High Impedance
= LOW-Io-HIGH Iransilion
=No Change
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT374
SYMBOL
PARAMETER
CONDITION
TYP.
COM'L.
MAX.
MIN.
MAX.
10.0
4.0
11.0
12.5
2.0
14.0
Propagation Delay
CP to ON
6.6
4.0
tZH
tZl
Output Enable
Time
9.0
2.0
tHZ
tlZ
Output Disable
Time
ts
Set Up Time
HIGH or LOW
ON to CP
tH
tw
C l = SOp!
Rl = soon
TYP.
MIN.
tplH
t pHL
6.0
IDT54174FCT374A
MIL.
2.0
I
COM'L.
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
4.5
2.0
6.5
2.0
7.2
5.5
1.5
6.5
1.5
ns
ns
7.5
" Y
8.0
2.0
8.0
4.0
1.0
2.0
-
2.5
-
Hold Time
HIGH or LOW
ONto CP
0.5
2.0
-
2.5
-
0.5
CP Pulse Width
HIGH or LOW
4.0
7.0
-
7.0
-
4.0
5-148
.~
1.5
:.';. i;2:~' .'
5.5
";'~ '~\
:'.';,.
,).s:",
"
~::<'
"
y. a;5~
ns
.
-
2.0
-
ns
1.5
-
1.5
-
ns
5.0
-
6.0
-
ns
FEATURES:
DESCRIPTION:
• IDT54/74FCT377 equivalent to FASr" speed;
IDT54174FCT377A 35% faster than FAST'·
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
The IDT54/74FCT377 and IDT54/74FCT377A are octal D flipflops built using advanced CEMOS'", a dual metal CMOS
technology. The IDT54174FCT377 and IDT54/74FCT377A have
eight edge-triggered, D-type flip-flops with individual D inputs
and 0 outputs. The common buffered Clock (CP) input loads all
flip-flops simultaneously when the Clock Enable (CEl is LOW.
The register is fully edge-triggered. The state of each D input,
one setup time before the LOW-to-HIGH clock transition, is
transferred to the corresponding flip-flop's 0 output. The CE
input must be stable only one setup time prior to the LOW-toHIGH clock transition for predictable operation.
•
•
•
•
IOL = 32mA over full military temperature range
CMOS power levels (5/lW typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than
FASr" (5/lA max.)
• Octal D flip-flop with clock enable
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
CE
Vee
00
0,
Do
0,
LJ lJ LJ lJLJ
03
GND
0,
D.
0,
D.
CP
0,
0,
D.
0,
0,
D.
0,
0,
0,
0,
GND
CP
:::9 8
7
6
5
:10
43::
Do
2::
00
SSD54174FCT377-002
LCC/PLCC
TOP VIEW
SSD54/74FCT377-001
DIP/SOIC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
DO
0,
0,
D,
D.
0,
0,
Q
cP--1D~----~--------~--------~~-------+~-------+~------~~--------~--------~
00
0,
0,
0,
D.
D.
0,
FAST is a trademark of Fairchild Semiconductor Co.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
5-149
IDT54174FCT377/A FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TSIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vcc = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vcc = 5.0V ± 10%
Min. = 4.50V
VLC = 0.2V
VHC = Vcc - 0.2V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V,L
Input LOW Level
Guaranteed Logic Low Level
-
I'H
Input HIGH Current
Vce = Max., V,N = Vee
I'L
Input LOW Current
Vee = Max., V,N = GND
-
-
Ise
Short Circuit Current
Vee = Max. (3)
-60
-120
SYMBOL
TEST CONDITIONS(1)
PARAMETER
Vee = 3\/, V,N = VLe or VHe, 10H = -32p.A
VOH
Output HIGH Voltage
Vee = Min.
V ,N = V,H or V'L
Vee = 3V, V,N
VOL
Output LOW Voltage
p.A
-5
p.A
-
rnA
VHe
Vee
VHe
Vee
10H = -12mA MIL.
2.4
4.3
10H = -15mA COM'L.
2.4
4.3
-
GND
VLe
GND
V Le
3.0
0.5
3.0
0.5
10L = 300p.A
10L = 32m A MIL.
10L = 48mA COM'L.
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-150
V
5
10H = -300p.A
= VLe or VHe , IOL = 300p.A
Vee = Min.
V ,N = V,H or V,L
0.8
V
V
IDT54174FCT377/A FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC ~ 0.2V; VHC ~ Vcc - 0.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP.(')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
-
1.5
4.0
-
2.0
5.6
Vee:: Max.
ICCQ
Quiescent Power Supply Current
VIN 2:: V HC; V IN :::; V LC
fcp~I,~O
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc ~ Max.
V'N ~ 3.4V(3)
Dynamic Power Supply
Current
Vcc ~ Max.
Outputs Open
CE ~ GND
One Bit Toggling
50% Duty Cycle
ICGD
Total Power Supply(4)
Current
Icc
Vcc ~ Max.
Outputs Open
fcp ~ 10MHz
50% Duty Cycle
CE ~ GND
One Bit Toggling
at Ii ~ 5MHz
50% Duty Cycle
Vcc ~ Max.
Outputs Open
fcp ~ 10MHz
50% Duty Cycle
CE ~ GND
Eight Bits Toggling
at Ii ~ 2.5MHz
50% Duty Cycle
V'N:> VHC
V,N:s VLC
V1N ;? VHC
V,N $ VLC
(FeT)
V'N ~ 3.4V
or
V'N ~ GND
mA
V'N:> VHC
VIN :5 VLC
(FCT)
V'N
~
3.4V
or
V'N ~ GND
-
3.75
7.8
-
6.0
15.0
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV. +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc = IQUIESCENT
+
IINPUTS + IDYNAMIC
Icc = ICGQ + ICCTDHNT + IceD (fcpf2 + fjNj)
ICGQ = Quiescent Current
lecT = Power Supply Current for a TTL High Input (V IN = 3AV)
D H ::: Duty Cycle for TTL Inputs High
NT::: Number of TTL Inputs at DH
I CCD
;::
Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp;:: Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi ;:: Input Frequency
Ni ;:: Number of Inputs at fj
All currents are in milliamps and all frequencies are in megahertz.
5-151
mAl
MHz
IDT54/74FCT377/A FAST CMOS OCTAL 0 FLIP-FLOP WITH CLOCK ENABLE
DEFINITION OF FUNCTIONAL TERMS
TRUTH TABLE
DESCRIPTION
PIN NAMES
0 0-0 7
CE
°0- 0 7
CP
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INPUTS
OPERATING MODE
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
OUTPUTS
CP
CE
ON
ON
Load "1"
I
I
h
H
Load "0"
I
I
I
L
Hold (Do Nothing)
I
X
h
H
X
X
No Change
No Change
H = HIGH Voltage Level
h :::: HIGH Voltage Level one setup time prior to the LOW-te-HIGH Clock
Transition
L :::: LOW Voltage Level
I :::: LOW Voltage Level one setup time prior to the LOW-te-HIGH Crock Transition
X :::: Don't care
I :::: LOW-ta-HIGH Clock Transition
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT377
SYMBOL
PARAMETER
CONDITION
TYP.
COM'L.
IDT54/74FCT377A
MIL.
COM'L.
TVP.
MIN.
MAX.
MIN.
MAX.
13.0
3.0
1S.0
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
S.O
2.0
7.2
2.0
8.3
ns
Propagation Delay
CPto ON
7.0
3.0
ts
Set Up Time
HIGH or LOW
ONto CP
1.0
2.S
-
3.0
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
ONto CP
1.0
2.0
-
2.S
-
1.0
1.S
-
1.S
-
ns
1.S
3.0
-
3.0
1.0
2.0
-
2.0
-
ns
t pLH
tpHl
C L = SOpt
RL = soon
ts
Set Up Time
HIGH or LOW
CE toCP
tH
Hold Time
HIGH or LOW
CEtoCP
3.0
4.0
-
S.O
-
1.0
2.0
-
2.0
-
ns
tw
Clock Pulse
Width. LOW
4.0
7.0
-
7.0
-
4.0
-
-
-
-
ns
5-152
FEATURES:
DESCRIPTION:
• IDT54174FCT521 7.0ns typical propagation delay;
IDT54174FCT521A 5.5n5 typical propagation delay
The IDT54/74FCT521 and IDT54174FCT521 A are 8-bit identity
comparators built using advanced CEMOS'·, a dual metal CMOS
technology. The devices compare two words of up to eight bits
each and provide a LOW output when the two words match bit for
bit. The expansion input IA=B also serves as an active LOW enable
input.
• Equivalent to FASr" output drive over full
temperature and voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5p.W typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than FASr"
(5p.A max.)
• a-bit identity comparator
• 100% product assurance screening to MIL-STD-883, Class 8
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Vee
TA=B
Ao
OA=B
Bo
B7
Al
A7
B6
Bl
A2
A6
B2
A3
Bs
B3
B4
A4
As
GND
SSDFCT521-001
DlP/SOIC
TOP VIEW
A3 B2 A2 Bl Al
LJ lJ LJ
B3
GND
A4
B4
As
:9 8
7
6
LJ LJ
5
43::
:::10
Bo
Ao
:11
TA=B
SSDFCT521-003
Vee
:12
"3
.... 14 1S 16
17 18
OA=B
r1r1r1nr1
Bs A6B6 A7B7
SSDFCT521-002
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Cl 1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
5-153
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT521/A FAST CMOS 8-BIT IDENTITY COMPARATOR
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
rnA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FOllowing Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
V He = Vee - 0.2V
SYMBOL
=4.75V
=4.50V
Max, = 5.25V (Commercial)
Max, = 5,50V (Military)
TEST CONDITIONS(1)
TYP'(2)
MAX.
UNIT
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
VIL
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vcc
= Max.,
-
-
5
"A
III
Input LOW Current
Vee
=Max"
-
-5
Ise
Short Circuit Current
Vee
= Max .i3)
"A
mA
Vee
=3V, V,N =VLC or VHe,
VOH
PARAMETER
MIN.
V,H
Output HIGH Voltage
= Vee
V,N = GND
Y'N
-
VIN
::=
V 1H
or
V 1L
Output LOW Voltage
Vee = Min,
V,N = V,H or VIL
-
VHe
Vee
-
Vee
-
IOH = -12mA MIL.
2.4
4.3
-
IOH = -15mA COM'L.
2.4
4.3
-
-
GND
VLe
10L = 3OOl'A
-
GND
VLe
10L = 32mA MIL.
-
0,3
0,5
10L = 48mA COM'L.
-
0.3
0.5
10H = -32"A
=-3001'A
Vee = 3V, V,N = VLe or VHe , 10L = 3OOl'A
VOL
-120
VHe
10H
Vee = Min.
-60
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second
5-154
V
V
IDT54/74FCT521/A FAST CMOS a-BIT IDENTITY COMPARATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = vcc - O.2V
SYMBOL
TYP.(')
MAX.
UNIT
-
0.001
1.S
mA
-
O.S
1.6
mA
-
0.1S
0.25
V'N'" VHC
V'N oS VLC (FCT)
-
1.5
4.0
V'N = 3.4V
V'N = GND
-
1.8
4.8
TEST CONDITIONS(1)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc = Max.
V1N 2: VHC ; V1N :s; VLC
1,=0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V'N = 3.4V I3 )
Iceo
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
One Input Toggling
SO% Duty Cycle
Icc
Total Power Supply!')
Current
Vcc = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
MIN.
VIN~VHC
mAl
MHz
V'N oS VLC
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: 5.DV, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN :: 3.4V); all other inputs at Vee or GNO.
4.
Icc::: 'QUIESCENT + IINPUTS + IDYNAMIC
Icc::: Icea + IccrDHNr
+
IceD (fepl2 + fjNj)
ICGQ :: Quiescent Current
leCT ::: Power Supply Current for a TTL High Input (V IN = 3.4V)
DH ::; Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD
=Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi
=Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Ao-A7
~O-B7
.!.A .B
°A.B
TRUTH TABLE
OUTPUT
INPUTS
DESCRIPTION
Word A inputs
Word S inputs
Expansion or Enable Input (Active LOW)
Identity Output (Active Low)
lAoS
A,B
°A.S
L
L
H
H
A = S'
A""S
A = S'
A""S
L
H
H
H
H=
L=
HIGH Voltage Level
LOW Voltage Level
*Ao"" 8 0, A1 ::: 8 1, A2 "" 8 2, etc.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT521A
IDT54/74FCT521
SYMBOL
PARAMETER
tpHL
Propagation Qelay
AN or SN to 0A.S
tpLh
Prppagati~
tpLH
tpHL
Delay
IA .. B to 0A" B
CONDITION
C L = SOpl
RL = soon
TYP.
ZO
COM'L.
MIL.
MIN.
MAX.
MIN.
MAX.
3.S
11.0
3.S
1S.0
TYP.
5.S
, -;..:~
••
s.o
3.0
10.0
5-155
3.0
9.0
COM'L.
~.4"
MIN.
i";.,
b;~,,:
1.5
.~J!.;;
.'
~~,;~
6.0
j
,,4t:.·
UNITS
)'Mm.'
MAX.
1.S
9.S
ns
1.S
Z8
ns
FEATURES:
DESCRIPTION:
• I DT54/74FCT533 6.0ns typical clock to output;
IDT54174FCT533A 4.0n5 typical clock to output
The IDT54174FCT533 and IDT54/74FCT533A are octal transparent latches built using advanced CEMOS'", a dual metal
CMOS technology. The IDT54/74FCT533 and IDT54174FCT533A
consist of eight latches with 3-state outputs for bus organized
system applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data that
m8ets the setup times is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
• Equivalent to FAST'" output drive over full temperature and
voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (5/lW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FAST'"
(5/lA max.)
• Octal transparent latch with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
v"
00
0,
Do
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
GND
LE
0302
'02 01
LJ lJLJ
0,
=:9 8
7
6
01
lJLJ
5
43:::::
Do
LE
00
0.
0,
V"
0,
0,
GND
Os AS
Os 06
D7
SSD54/74FCT533-002
SSD54/74FCT533-001
DIP/SOIC
TOP VIEW
LCC/PLCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
Do
0,
0,
0,
0,
0,
0,
0,
LE --~,~o---~-----~--~~--~----~-----+----~----~----~----~----~----+-----~----~--~
0.
---qI~----~----~----~----4-----------+---~~---4~--~~--~-----+-----+----~----~--~
00
0,
0,
0,
0,
0,
SSDAHCT533-003
CEMOS IS a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©
1986 Integrated Device Technology, Inc
JULY 1986
Printed in the U.S.A.
5-156
IDT54/74FCT533/A
FAST CMOS OCTAL TRANSPARENT LATCH (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBtAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
= DoC to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - O.2V
TA
SYMBOL
= 4.75V
= 4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(1)
PARAMETER
MIN.
TYP.!·)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V'L
I n put LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vee
= Max., V,N =Vee
Vee = Max., V,N = GND
Vee = Max. (3)
Vee = 3V, V,N =VLe or VHe ,
-
-
5
p.A
I'L
Input LOW Current
Ise
Short Circuit Current
VOH
Output HIGH Voltage
Vee
V ,N
= Min.
= V,H or V'L
Output LOW Voltage
-120
p.A
mA
10H = -32p.A
=-300p.A
VHe
Vee
VHe
Vee
-
10H
=-12mA MIL.
2.4
4.3
-
10H = -15mA COM'L.
= 3V, V,N =V Le or VHe , 10L =300p.A
10L = 300p.A
Vee = Min.
10L =32mA MIL.
V,N =V,H or V'L
10L = 48mA COM'L.
4.3
-
-
GND
V Le
-
GND
V Le
-
0.3
0.5
-
0.3
0.5
2.4
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-157
-5
-
10H
Vee
VOL
-60
V
V
V
IDT54n4FCT533/A
FAST CMOS OCTAL TRANSPARENT LATCH (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC =O.2V; VHC =vcc - O.2V
SYMBOL
TEST CONDITIONS(1)
PARAMETER
Icco
Quiescent Power Supply Current
Vcc= Max.
VIN '" VHC; VIN S VLC
1,= a
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc= Max.
VIN =3.4V (3)
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
OE = GND
LE =Vcc
One Input Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply (4)
Current
VCC = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE =GND
LE = Vcc
One Bit Toggling
Vcc = Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
OE =GND
LE = Vcc
Eight Bits Toggling
TYp'(2)
MAlt
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
VIN"'VHC
VINSVLC
-
0.15
0.25
VIN"'VHC
VINSVLC
(FCT)
-
1.5
4.0
VIN = 3.4V
VIN=GND
-
1.8
5.6
MIN.
mA
VIN",VHC
VINS VLC
(FCT)
-
3.0
6.5
VIN = 3.4V
VIN=GND
-
5.0
12.9
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4.
Icc = IQUIESCENT + I INPUTS + IDYNAMIC
Icc = ICGQ + IccrDHNT + IceD (fcp/2 + fiNj)
ICGQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at 0H
IceD
=
Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Nj
=
Number of Inputs at fj
All currents are In milliamps and all frequencies are in megahertz.
5-158
mAl
MHz
IDT54/74FCT533/A
FAST CMOS OCTAL TRANSPARENT LATCH (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0-0 7
TRUTH TABLE
DESCRIPTION
INPUTS
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary 3-State Outputs
LE
OE
0 0-07
H ::: HIGH Voltage Level
L " LOW Voltage Level
X ::: Don't Care
Z = HIGH Impedance
OUTPUTS
DN
LE
OE
ON
H
L
H
H
X
L
L
H
L
H
X
Z
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT533
SYMBOL
PARAMETER
Propagation Delay
ON to ON
tpLH
tpHL
tZH
tZL
tHZ
tLZ
!
,
I
Output Disable
Time
I
Propagatio!' Delay
LE to ON
tpLH
tpHL
Output Enable
Time
I
I
I
TYP.
CONDITION
COM'L.
IDT54174FCT533A
MIL.
TYP.
MIN.
MAX.
MIN.
MAX.
6.0
3.0
10.0
3.0
12.0
8.0
2.0
110
2.0
6.0
2.0
7.0
9.0
3.0
13.0
1.0
2.0
-
2.0
COM'L.
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
4.0
15
5.2
15
5.6
ns
12.5
5.5
15
6.5
15
7.5
ns
2.0
8.5
4.0
15
5.5
1.5
6.5
ns
3.0
14.0
7.0
2.0
8.5
2.0
9.8
ns
-
10
2.0
-
2.0
-
ns
I
I
C L 0 SOp!
RL 0 soon
I
I
,
ts
Set Up Time
HIGH or LOW
ON to LE
tH
Hold Time
HIGH or LOW
ON to LE
1.0
3.0
-
3.0
-
10
18
-
18
-
ns
tw
LE Pulse Width
HIGH or LOW
5.0
6.0
-
6.0
-
4.0
5.0
-
6.0
-
ns
I
II
5-159
FEATURES:
DESCRIPTION:
• IDT54174FCT534 6.5ns typical clock to output;
The IDT54174FCT534 and IDT54/74FCT534A are octal D flipflops built using advanced CEMOS'·, a dual metal CMOS technology. The IDT54/74FCT534 and IDT54/74FCT534A are highspeed, low-power octal D-type flip-flops featuring separate
D-type inputs for each flip-flop and 3-state outputs for busoriented applications. A buffered Clock (CP) and Output Enable
(OE) are common to all flip-flops.
IDT54174FCT534A 4.5ns typical clock to output
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
• IOL = 32mA over full military temperature range
• CMOS power levels (51'W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FAST'·
(51'A max.)
• Octal D flip-flop with 3-state output
• 100% product assurance screening to MIL-STD-883, Class B
is avai lable
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
a-
Ycc
0,
D,
D,
0,
OS
Ds
D,
0,
O.
D.
D,
0,
02
D2
D,
0,
GND
03 02620101
LJ L J L J LJ LJ
0,
~9 8
7
6
5
43:::
D.
:::10
2:::
O.
:::11
1~::
:::12
20~
,.
~13
~
15 16 17
aYee
1~9:: 0,
r1 r1 r1 r1 r1
CP
Os 050& Os 07
SSDFCT534-001
SSDFCT534-002
DIP/SOIC
TOP VIEW
LCC/PLCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
D.
D,
D2
D,
DS
D,
D,
cP~C>~~~~----~+-----~1-----~~----~-+----~r-~----~+-----.
a-~C>--~~~----~+-----+-+-----~~----~-+----~~------~+---~
O.
0,
02
0,
0,
Os
Os
0,
SSDFCT534-003
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CI
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
5-160
IDT54/74FCT534/A FAST CMOS OCTAL D FLIP-FLOP (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(l)
RATING
SYMBOL
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
V TEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA O°C to +70°C
Vee 5.0V ± 5%
Min.
TA -55°C to +125°C
Vee 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
=
=
=
=
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V,l
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vec = Max., V,N
-
-
5
p.A
SYMBOL
I'l
Input LOW Current
Isc
Short Circuit Current
VOH
VOL
TEST CONDITIONS(1)
PARAMETER
Output HIGH Voltage
Output LOW Voltage
= Vee
Vce = Max., V,N =GND
Vee = Max. (3)
Vee = 3V, V,N =VlC or VHe,
-
-
-5
p.A
-60
-120
-
mA
VHe
Vee
-
IOH
VHe
Vee
-
2.4
4.3
-
4.3
-
10H = -32p.A
= -300p.A
Vee =Min.
IOH = -12mA MIL.
V,N = V,H or V,l
IOH = -15mA COM'L.
Vee =3V, V,N =Vle or VHe , IOl = 300"A
IOl = 300"A
Vee = Min.
IOl =32mA MIL.
V,N
=V,H or V,L
IOl
= 48mA COM'L.
2.4
-
GND
Vle
-
GND
Vle
-
0.3
0.5
-
0.3
0.5
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0\1, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-161
V
V
IDT54/74FCT534/A FAST CMOS OCTAL D FLIP-FLOP (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = 0.2V; v HC = vcc -
0.2V .
SYMBOL
TEST CONDITIONS(!)
PARAMETER
ICCQ
Quiescent Power Supply Current
Vcc=Max.
VIN ~ VH6 VIN = '" VLC
fcp=f;=O
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc= Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
OE=GND
One Bit Toggling
50% Duty Cycle
Icc
Total Power Supply(4)
Current
VCC = Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE=GND
One Bit Toggling
at Ii = 5MHz
50% Duty Cycle
Vcc= Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
at Ii = 2.5M Hz
50% Duty Cycle
V1N~VHC
VIN '" VLC
VIN~VHC
VIN'" VLC
(FCT)
VIN = 3.4V
or
VIN = GND
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
mAl
MHz
-
1.5
4.0
-
2.0
5.6
-
3.75
7.8
-
6.0
15.0
mA
VIN~VHC
VIN"'VLC
(FCT)
VIN = 3.4V
or
VIN = GND
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven Input (V IN = 3.4V); all other inputs at Vee or GNO.
4.
Icc = laulESCENT + IINPUTS + IDYNAMIC
Icc = IccO + ICCTDHNT + ICCD (fcp/2 + fiNj)
Icco = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at 0H
ICCD = Dynamic Current caused by an Input Transition pair (HLH or lHl)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fj = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-162
IDT54/74FCT534/A FAST CMOS OCTAL 0 FLIP-FLOP (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0-0 7
CP
OE
0 0-0 7
TRUTH TABLE
DESCRIPTION
INPUTS
FUNCTION
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-State Output Enable Input (Active LOW)
Complementary 3-State Outputs
OUTPUTS
INTERNAL
OE
CP
0,
ON
0,
Hi-Z
H
H
L
H
X
X
Z
Z
NC
NC
LOAD
REGISTER
L
L
H
H
..r
..r
..r
..r
L
H
L
H
H
L
Z
Z
H
L
H
L
L
H
= H'GH
= LOW
X
"Don't Care
Z
= High Impedance
NC
=
f
: : LOW-to-HIGH transition
No Change
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54174FCT534A
IDT54174FCT534
SYMBOL
PARAMETER
t pHL
Propagation Delay
CPtoO N
tZH
tZl
Output Enable
Time
tpLH
CONDITION
TYPICAL
6.5
9.0
COMMERCIAL
MIN.
MAX.
4.0
10.0
2.0
12.5
MILITARY
MIN. MAX.
4.0
2.0
11.0
14.0
COMMERCIAL
TYPICAL
4.5
5.5
MIN.
MAX.
2.0
6.5
1.5
6.5
MILITARY
UNITS
MIN. MAX.
2.0
,,;t;$,
7.2
ns
7.5
ns
;
(-h'
tHZ
tlZ
Output Disable
Time
6.0
2.0
B.O
2.0
B.O
4.0
IS
Set Up Time
HIGH or LOW
ONto CP
1.0
2.0
-
2.5
-
1.0
tH
Hold Time
HIGH or LOW
ONto CP
0.5
2.0
-
2.5
-
1.0,..
tw
CP Pulse Width
HIGH or LOW
4.0
7.0
-
7.0
-
4.0
C l = SOp!
Rl = soon
5-163
1";/9~"
1.5
6.5
ns
-
2.0
-
ns
1.5
-
1.5
-
ns
5.0
-
6.0
-
ns
1.5
2.0 "
: c'
c' :::.
..
I
FEATURES:
DESCRIPTION:
• IDT54/74FCT573 equivalent to FAST'" speed;
IDT54/74FCT573A 35% faster than FAST'"
The IDT54174FCT573 and IDT54/74FCT573A are 8-bit latches
built using advanced CEMOS'", a dual metal CMOS technology.
These octal latches have 3-state outputs and are intended for
bus-oriented applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is HIGH. When LE is LOW, the
data that meets the setup times is latched. Data appears on the
bus when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes.
• IOL = 32mA over full military temperature range
• CMOS power levels (5JlW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than FASr"
(5JlA max.)
• Octal transparent latch with enable
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
Do
vee
0,
00
0,
O2
D.
D.
D.
O2
O.
O.
O.
06
07
o.
GND
LE
LJ lJLJ
07
GND
LE
07
07
O.
~9 8
7
6
LJ LJ
5
:'0
2::
::;"
'::==
=12
20;::::
::::1~4
'"
43::::
15 16 17 1J9;::::
r1 rl r1 f1
r, ,/
D1
Do
OE
Vee
00
0.0.0. O 2 0,
DIP
TOP VIEW
LCC
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
0,
0,
02
0,
0,
o.
0,
LE ---1~~--~----+---~~--~-----*----~----4-----~--~~---+----~----+---~~--~~--~
OE --~~----~----+---~~--~-----*----~----4-----~--~~---+----~----+---~~--~~--~
0,
0,
0,
02
0,
o.
0,
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
JULY 1986
Printed in U.S.A.
1986 Integrated Device Technology, Inc.
5-164
IDT54174FCT573/A FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
'C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Temperature
-55 to +125
-65 to +155
'C
120
120
mA
lOUT
NOTE:
Storage
DC Oulput Current
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Specified:
TA = O°C to +70°C
TA = -55°C to +125°C
SYMBOL
Vcc = 5.0V
Vce = 5.0V
± 5%
± 10%
Min. = 4.75V
Min. = 4.50V
Following Conditions Apply Unless Otherwise
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(1)
PARAMETER
MIN.
VLc = O.2V
V HC = Vcc - 0.2V
Typ.I')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V,L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current (Except 110 Pins)
Vee = Max., V,N = Vee
-
-
5
I"A
I'L
Input LOW Current (Except 110 Pins)
Vee = Max., V,N = GND
-
-
-5
I"A
Isc
Input Short Circuit Current
Vee = Max.!3)
-60
-120
-
mA
VHe
Vee
-
10H = -3001"A
VHC
Vee
-
10H = -12mA MIL
2.4
4.3
-
10H = -15mA COM
2.4
Vee - 3V, V,N - VLe or VHe , 10H - -321"A
VOH
Output HIGH Voltage
Vec = Min.
V1N ::;;: V 1H or V 1l
VOL
Output LOW Voltage
loz
Off State (High Impedance)
Output Current
Vee = Min.
V,N = V,H or V,L
Vee = Max.
4.3
GND
VLe
10L - 3OOl"A
-
GND
V Le
10L = 32mA MIL
-
0.3
0.5
10L = 48mA COM
-
0.3
0.5
Va = O.4V
-
-
-40
Va = 2.4V
-
-
40
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-165
V
-
-
Vee = 3V, V,N - VLe or VHC , 10L - 300l"A
V
V
I"A
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT573/A FAST CMOS OCTAL TRANSPARENT LATCH
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; vHC = vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc= Max.
V,N;" VH6 V,N" VLC
fcp=f,=O
ICCT
Power Supply Current
TTL Inputs HIGH
Vee = Max.
Y,N = 3.4V(3)
Dynamic Power Supply
Current
Vee = Max.
Outputs Open
OE=GND
LE=Vcc
One Input Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply(4)
Current
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N;"VHC
V,N"VLC
-
0.15
0.25
mN
MHz
V,N;" VHC
V,N " VLC
(FCT)
-
1.5
4.0
-
1.8
4.8
TEST CONDITIONS(1)
PARAMETER
Vcc= Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE=GND
LE = VCC
One Bit Toggling
VCC= Max.
Outputs Open
Ii =2.5MHz
50% Duty Cycle
OE=GND
LE = VCC
Eight Bits Toggling
=
V,N 3.4Vor
V,N=GND
mA
V,N ;" VHC
V,N" VLC
(FCT)
=
Y,N 3.4V or
V,N=GND
-
3.0
6.5
-
5.0
12.9
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0'1. +25°C ambient and maximum loading.
3. Per TIL driven input (V IN = 3.4V); all other Inputs at VccorGND.
4.
Icc = 'aUIESCENT+ 'INPUTS + 'DYNAMIC
Icc= 'cea + ICCTDHNT + ICCD (lce/2 + ~Ni)
IceQ= Quiescent Current
I CCT = Power Supply Currentfor a TTL High Input (V IN =3.4V)
DH =Duty Cycle lor TTL Inputs High
NT = Number 01 TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
Icp = Clock Frequency lor Register Devica. (Zero lor Non-Register Devices)
II = Input Frequency
Ni = Number 01 Inputs at II
All currents are in milliamps and all frequencies are in megahertz.
5-166
IDT54/74FCT573/A FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE
INPUTS
H
DEFINITION OF FUNCTIONAL TERMS
OUTPUTS
Dn
LE
OE
On
H
L
X
H
H
X
L
L
H
H
L
= HIGH
Voltage Level
PIN NAMES
0 0-0 7
LE
OE
~OO-07
Z
DESCRIPTION
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Latch Outputs
L = LOW Voltage Level
X :: Don't Care
Z :: High Impedance
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I
IDT54174FCT573
PARAMETER
SYMBOL
CONDITION
TYP.
---------- --
COM'l.
IDT54174FCT573A
MIL.
MIN.
MAX.
MIN.
MAX.
TYP.
COM'L.
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
Propagation Delay
DntoOn
5.0
2.0
8.0
2.0
8.5
4.0
1.5
5.2
1.5
5.6
ns
tZH
tZl
._----
Output Enable
Time
7.0
2.0
12.0
'2.0
13.5
5.5
l5
6.5
1.5
7.5
ns
tHZ
tLl
Output Disable
Time
6.0
2.0
7.5
2.0
10.0
4.0
l5
5.5
l5
6.5
ns
15.0
7.0
2.0
8.5
2.0
9.8
ns
tplH
tpHL
tpLH
Propagation Delay
LEto On
C l = SOp!
Rl = soon
9.0
3.0
13.0
3.0
ts
Set up Time
HIGH or LOW
On to LE
lO
2.0
-
2.0
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
On to LE
1.0
3.0
-
3.0
-
1.0
1.8
-
1.8
-
ns
tw
LE Pulse Width
HIGH or LOW
5.0
6.0
-
6.0
-
4.0
6.0
-
5.0
-
ns
tpHL
5-167
FEATURES:
DESCRIPTION:
• IDT54174FCT574 equivalent to FASr" speed;
IDT54174FCT574A 35% faster than FAST'"
• Equivalent to FASr" output drive over full temperature and
voltage supply extremes
The IDT54174FCT574 and IDT54174FCT574A are 8-bit registers built using advanced CEMOS'", a dual metal CMOS
technology. These registers consist of eight D-type flip-flops
with a buffered common clock and buffered three-state output
control. When the output enable (OE) input is LOW, the eight
outputs are enabled. When the OE input is HIGH, the outputs
are in the three-state conditions.
Input data meeting the setup and hold time requirements of
the D inputs is transferred the the 0 outputs on the LOW-toHIGH transition of the clock input.
•
•
•
•
•
•
IOL = 32mA over full military temperature range
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than FASr" (5p.A max.)
Positive, edge-triggered master/slave, D-type flip-flops
Buffered common clock and buffered common three-state
control
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
PIN CONFIGURATIONS
OE
QQI~ ~o
Vee
00
0,
Do
0,
O2
O2
0_
0_
°2
D_
D_
D.
0_
0.
0.
08
06
07
°7
GND
CP
LJ lJ ' l l J IJ
2 ~J 20 19 :
18
3
,
=4
=5
:6
:7
D.
De
-8
~
9 10 11 12
fl rl
0,
17=
°2
'6 =
0.
'5= O_
14 = Os
13
r l r l rl
Q~fioo
CI
LCC
TOP VIEW
DIP
TOP VIEW
FUNCTIONAL BLOCK DIAGRAM
00
06
05
CP
CLOCK--r.>~--'-+-----~-+----~~------~+-----~-+----~~~----~4------,
OE
OUTPUT-4C>~~~----~+-----~+-----+-+-----~~----~-+-----+-+----~
ENABLE
00
03
05
06
SSOAHCT374-003
FAST is a trademark of Fairchild Semiconductor Company.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
~1986
Integrated Device Technology, Inc.
5-168
JULY 1986
Printed In the U.SA
IDT54n4FCT574/A FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
VTEAM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
'C
TB1AS
Temperature
Under Bias
-55 to +125
-65 to +135
'C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
'C
lOUT
DC Output Current
120
120
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise
Specified:
TA = O°C to +70'C
TA = -55°C to +125°C
Vee = 5.0V ± 5%
Vee = 5.0V ± 10%
Min. = 4.75V
Min. =4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
VLe = 0.2V
VHe = Vee - 0.2V
MIN.
TYP.!')
MAX.
UNIT
V'H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
I'H
Input HIGH Current
Vec
-
-
SYMBOL
I'L
Input LOW Current
Ise
Short Circuit Current
VOH
TEST CONDITIONS(1)
PARAMETER
Output HIGH Voltage
VOL
Output LOW Voltage
loz
Off State (High Impedance)
Output Current
0.8
V
5
I'A
=Max., V'N =Vee
Vee = Max., V'N =GND
Vee = Max. (3)
Vee =3V, V'N =VLe or VHe,
-
-5
I'A
-60
-120
mA
VHe
Vee
10H
VHC
Vee
2.4
4.3
10H =-321'A
=
-3001'A
Vee = Min.
10H = -12mA MIL
V'N =V,H or V'L
IOH =-15mA COM
Vee =3V, V'N =VLe or VHe , IOL =300ilA
IOL =300ilA
Vee = Min.
IOL =32mA MIL
V 1N = V 1H or V1L
IOL =48mA COM
Va =O.4V
Vce = Max.
Va =2.4V
2.4
4.3
-
-
GND
VLe
-
GND
VLe
0.3
0.5
-
0.3
0.5
-
-
-40
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee'" 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-169
40
V
V
I'A
IDT54174FCT574/A FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc = Max.
V'N <': VHO V'N :5 VLC
Icp=lj=O
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
V'N = 3.4V(3)
Dynamic Power Supply
Current
Vcc = Max.
Outputs Open
OE =GND
One Bit Toggling
50% Duty Cycle
ICCD
Icc
Total Power Su pply(4)
Current
TYF!(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
-
0.15
0.25
-
1.5
4.0
V'N = 3.4V
or
V'N = GND
-
2.0
5.6
V'N <': VHC
V'N:5 VLC
(FCT)
-
3.75
7.8
V'N = 3.4V
or
V'N = GND
-
6.0
15.0
TEST CONDITIONSI')
PARAMETER
Vcc = Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE =GND
One Bit Toggling
at Ii = 5MHz
50% Duty Cycle
Vcc = Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
at Ii = 2.5MHz
50% Duty Cycle
V'N <,:VHC
MIN.
V'N:5 VLC
V'N<': VHC
V'N:5 VLC
(FCT)
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0\1, +25°C ambient and maximum loading.
3. Per TTL driven input (V1N = 3.4V); all other inputs at Vee or GND.
4.
Icc
=IQUIESCENT + IINPUTS + IDYNAMIC
Icc::: Icea + IccrDHNT + ICGD (fcp/2 + fjNj)
Icea = Quiescent Current
lecT::: Power Supply Current for a TTL High Input (V1N ::: 3.4V)
D H ::: Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICGD ::: Dynamic Current caused by an Input Transition pair (HLH or LHL)
fCp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-170
mAl
MHz
IDT54/74FCT574/A FAST CMOS OCTAL 0 REGISTERS (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
0 0-0 7
CP
OE
0 0-0 7
TRUTH TABLE
DESCRIPTION
INPUTS
FUNCTION
Data Inputs
Clock Pulse Input (Active Rising Edge)
3-State Output Enable Input (Active LOW)
Complementary 3-State Oulputs
OUTPUTS
INTERNAL
OE
CP
0,
ON
0,
Hi-Z
H
H
L
H
X
X
Z
Z
NC
NC
LOAD
REGISTER
L
L
H
H
..r
..r
..r
..r
L
H
L
H
H
L
Z
Z
H
L
H
L
=HIGH
= LOW
::: Don't Care
Z = High Impedance
J
::: LOW-ta-HIGH transition
NC ::: No Change
H
L
X
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT574A
IDT54/74FCT574
SYMBOL
PARAMETER
CONDITION
TYp.
COM'L.
MIL.
TYP.
MIN.
MAX.
MIN.
MAX.
COM'L.
UNITS
MIL.
MIN.
MAX.
MIN.
MAX.
tpHL
Propagation Delay
CPtoO N
6.6
4.0
10.0
4.0
11.0
4.S
2.0
6.S
2.0
7.2
ns
tZH
tZl
Output Enable
Time
9.0
2.0
12.S
2.0
14.0
S.5
1.5
6.5
1.5
7.5
ns
tHZ
tlZ
Output Disable
Time
6.0
2.0
8.0
2.0
8.0
4.0
1.5
5.$
1.5
6.5
ns
ts
Set Up Time
HIGH or LOW
ONto CP
1.0
2.0
-
2.S
-
1.0
2.0
-
2.0
-
ns
tH
Hold Time
HIGH or LOW
ON to CP
0.5
2.0
-
2.S
-
O.S
1.S
-
1.5
-
ns
tw
CP Pulse Width
HIGH or LOW
4.0
7.0
-
7.0
-
4.0
S.O
-
6.0
-
ns
tpLH
C l = 50pt
Rl = soon
5-171
FEATURES:
DESCRIPTION:
• IDT54174FCT640 6.0ns typical data to output;
The IDT54174FCT640 and IDT54/74FCT640A are 8-bit inverting buffer transceivers built using advanced CEMOS'·, a dual
metal CMOS technology. These octal bus transceivers are
designed for asynchronous two-way communication between
data busses. The devices transmit data from the A bus to the 8
bUs or from the 8 bus to the A bus, depending upon the level at
the direction control (T/R) input. The enable input (OE) can be
used to disable the device so the busses are effectively isolated.
IDT54174FCT640A 3.5n5 typical data to output
• Equivalent to FASr· output drive over full temperature and
voltage supply extremes.
•
•
•
•
IOL = 48mA over full military temperature range
CMOS power levels (5pW typo static)
80th CMOS and TTL output compatible
Substantially lower input current levels than FAST'·
(51'A max.)
• Inverting buffer transceiver
• 100% product assurance screening to MIL-STD-883, Class 8
is available
• JEDEC standard pinout for DIP and LCC
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
T/R
Vee
Ao
DE
A,
Bo
A,
B,
A,
B2
A_
B,
DE
Ao
Bo
A,
B,
A,
B_
At
B,
A,
B,
GND
B,
A,
SSD54/74FCT640-001
A_
A2
B2
(5)
B,
(6)
DIP/SOIC
B_
TOP VIEW
A,
(7)
B,
A,
(8)
B,
LJ LJ LJ LJLJ
A7
:9 8
7
6
5
43::
GND
:::10
2::
87
:::11
1[::
T/R
B6
::::12
20:::
Vee
85
::1~4
15 16 17
A,
Al
(9)
B,
Ao
SSD54174FCT640~OO3
1~9:: De
rlr1r1r1r1
SSD54174FCT640~OO2
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
5-172
JULY 1986
Printed in U.S.A.
IDT54174FCT640/A
FAST CMOS OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Ope rating
Tem perature
o to +70
-55 to +125
°c
Tem perature
Und er Bias
-10 to +85
-65 to +135
°c
Sto rage
Tem perature
-55 to +125
-65 to +150
°c
120
120
mA
Term inal Voltage
with Respect
to G NO
..
...
1----+
DC Output Current
NOTE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
Indicated in the operational sections of this specification IS not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
" DoC to +70°C
Vcc" 5.0V ± 5%
Min. = 4.75V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TA = -55°C to +125°C
Vcc = 5.0V ± 10%
Min. = 4.50V
V LC = 0.2V
V HC = Vcc - 0.2V
~-S-Y-M-B-O-L--~----·----P-A-R-AMET-ER---- ---·..,·----T-E-S-:;:-C-O-NDITioNS(l)
MIN.
TA
...
Input HIGH Level
Guaranteed Logic High Level
f - - - -... - - - -..- - - - - - - - j - - - - - - " - - . . : . . . . - - - . Input LOW L_e_v_e_1____
_ _ _ _--t_G_u_a_ra_n_t_eed Logic Low Level
----"!'_L__
_-
TYP.!')
I'L
-
Input LOW Current
Vcc" Max., V,N " GND
Short Circuit Current
Vee =' M~x. (3)
----~c·----r-·
V
~.---
Output LOW Voltage
.---~.-
HystereSIS
....
V
- - c----- f - - - 5
/J.A
.-----
-60
-5
-.-~
/J. A
r--~
-120
mA
----------------r---~----+_--~--.~
VHC
Vcc
_v.c.~_"_3'J. V,N " V,£,,, V-,-H"C.,__1'"0"H_"_-_3_2.c./J._A_ _+---'-'c:...+_.=_+
__---t
Output HIGH Voltage
v+ - V-
UNIT
0.8
_~'CI. _1--'-n~LJt_H_I_G_H_C..':'.rr_e_n_t_ _ _ _ _ _ _r_r_V.c.c.c.c-"-M-a-x-.-,_VI'-C.N_=_V-'c-'c_ _ _ _._ _ _ _-+__
__ ~~i?
MAX.
2.0
Vee = Min.
V 1N = V 1H or V 1L
10H" -300/J.A
VHC
Vcc
10H" -12mA MIL.
24
4.3
I OH " -15mA _C_O_M_'L_.+ -2.4
- - - t - 4.3
---+---f---Le ---1
Vce = 3V. V,N " VLe or _V_H.c.c_,.I..cOccL_"_3_0_0_/J._A_ _+ _ _--t_GND
_ _-+_V_
GND
V Le
IOL = 300/J.A
V
Vee = Min.
0.55
I, "48mA_M_I_L_.
j-. 0.3
V 1N = V 1H or V1L
0.3
0.55
IOL" 64mA C_O
__
M_·L_·r_f---+-----t-On Ai and Bi
0.4
V
_+-___
----.--.---.-----~--.-------
..- -..--- .. --- ... ---~-
--~--~---~-.-.-
NOTES:
1 For conditions shown as max or min., use appropriate value specified under Electncal Characteristics for the applicable device type
Typical values are at Vee
0-
V
5.0V, +25°C ambient and maximum loading
Not more than one output should be shorted at one time Duration of the short Clfcuit test should not exceed one second
5-173
II
IDT54174FCT640/A
FAST CMOS OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = vcc - O.2V
SYMBOL
ICCQ
Power Supply Current
Vcc = Max.
V,N ", VHC ; V,N:S VLC
I, = 0
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
Y'N = 3.4v(3)
Dynamic Power Supply Current
VCC = Max.
Outputs Open
OE=GND
TiR = GND or Vcc
One Input Toggling
50% Duty Cycle
Iceo
Icc
Total Power Supply(4) Current
MIN.
TYP.(')
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N'" VHC
V,N:S VLC
-
0.15
0.25
mAl
MHz
V,N'" VHC
V,N:S VLc (FCT)
-
1.5
4.0
Y'N = 3.4Vor
Y'N = GND
-
1.8
4.8
V,N'" VHC
Y'N :s VLC (FCT)
-
3.0
6.5
Y,N = 3.4V or
V ,N = GND
-
5.0
12.9
TEST CONDITIONS(')
PARAMETER
Vcc = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE=GND
One Bit Toggling
Vcc = Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee::: 5.0V, +2S Q C ambient and maximum loading.
3. Per TTL driven input (V IN ::: 3AV); all other inputs at Vee or GND.
4.
Icc::: IQUIESCENT + IINPUTS + IDYNAMIC
Icc::: ICGQ + ICCTDHNT + IceD (fcp/2 + fjNj)
ICGQ ::: Quiescent Current
teeT::: Power Supply Current for a TTL High Input (V IN ::: 3AV)
DH
=
Duty Cycle for TTL Inputs High
NT::: Number of TTL Inputs at DH
IceD::: Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp::: Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi ::: Input Frequency
Nj ::: Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-174
IDT54/74FCT640/A
FAST CMOS OCTAL INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE
DEFINITION OF FUNCTIONAL TERMS
INPUTS
OE
PIN NAMES
OPERATION
T/R
--
L
L
H
L
H
X
'----_.-._---
--
Bus B Data to Bus A
Bus A Data to Bus B
Isolation
DESCRIPTION
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or
3-State Outputs
Side B Inputs or
3-State Outputs
OE
T/R
AD-A,
Bo-B,
.--~-----
._.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54n4FCT640
SYMBOL
PARAMETER
t pLH
t pHL
Propagation Delay
tZH
tZl
Output Enable
Time
tHZ
tlZ
Output Disable
Time
tDlH
tDHL
CONDITION
A to B or B to A
Pro~agation
Delay
T/R to A or BI11
C l = SOpF
Rl = soon
TYP.
IDT54/74FCT640A
TYP.
MIL.
COM'L.
MIN.
MAX.
MIN.
MAX.
6.0
2.0
7.0
2.0
8.0
7.0
2.0
10.0
2.0
11.0
2.0
13.0
2.0
7.0
-
-
NOTE:
1. Guaranteed by design.
5-175
-
COM'L.
MIL.
UNITS
MIN.
MAX.
MIN.
MAX.
3.S
1.S
5.0
1.S
5.3
ns
12.0
4.S
1.5
5.0
1.S
6.0
ns
16.0
4.8
1.S
6.2
1.S
6.S
ns
5.0
-
-
-
-
ns
-
FEATURES:
DESCRIPTION:
• IDT54174FCT645 equivalent to FASr" speed;
IDT54174FCT645A 35% faster than FAST'"
• Equivalent to FAST'" output drive over full temperature and
voltage supply extremes
• IOL = 48mA over full military temperature range
• CMOS power levels (5/lW typo static)
• Substantially lower input current levels than FASr"
(5/lA max.)
• Non-inverting buffer transceiver
• 100% product assurance screening to MIL-STD-883, Class B
is available
• JEDEC standard pinout for DIP and LCC
The IDT54/74FCT645 and IDT54174FCT645A are 8-bit noninverting buffer transceivers built using advanced CEMOS'", a
dual metal CMOS technology. These non-inverting buffer
transceivers are designed for asynchronous two-way communication between data buses. The devices transmit data from the A
bus to the B bus or from the B bus to the A bus, depending upon
the level at the direction control (TiR) input. The enable input
(OE) can be used to disable the device so the buses are
effectively isolated.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
Vee
T/R
Ao
DE
A,
Bo
A,
(19)
B,
A,
B,
A,
B,
As
B,
As
B,
A,
B,
GND
B,
DE
Ao
(18)
Bo
A,
(17)
B,
A,
(16)
B,
A.
(15)
B,
SSD54174FCT645-001
A,
(14)
DIP/SOIC
TOP VIEW
B,
A,
(13)
B,
As
A6 As A4 A3 A2
(12)
LJ LJLJ lJLJ
A,
::::9 8
7
6
5
43:::
.:::
1::::
GND
B,
B,
20::::
Bs
A,
A,
(11)
Ao
T/R
Vee
B,
SSD54/74FCT645-003
DE
B,
SSD54174FCT645-002
LCC/PLCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
c 1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
5-176
I DT54/74FCT645/A
FAST CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(l)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +ZO
V
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
120
120
mA
NOTE:
1.Stressesgreaterthan those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = OOG to +70°C
Vee = 5.0V ± 5%
Min. = 4.75V
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min. = 4.50V
VLe = 0.2V
V He = Vee - 0.2V
SYMBOL
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS!')
PARAMETER
MIN.
TYP.!')
MAX.
UNIT
Guaranteed Logic High Level
2.0
-
-
V
V,L
I nput LOW Level
(Except 110 Pins)
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
(Except 110 Pins)
Vee = Max., Y,N = Vee
-
-
5
,..A
I'L
Input LOW Current
Vee
-
-5
,..A
Ise
Short Circuit Current
= Max., Y,N = GND
= Max.(31
Vee = 3V, Y,N =VLe or VHe'
-
Vee
mA
V,H
Input HIGH Level
VOH
Output HIGH Voltage
Vee = Min.
Y,N = V,H or V,L
Vee
VOL
V+- V
Output LOW Voltage
Hysteresis
-60
-120
VHe
Vee
-
10H = -300,..A
VHe
Vee
-
=-12mA MIL.
10H = -15mA COM'L.
2.4
4.3
-
10H = -32,..A
laH
4.3
-
-
GND
VLe
laL = 300,..A
-
GND
VLe
laL = 48mA MIL.
-
0.3
0.55
laL = 64mA COM'L.
-
0.3
0.55
-
0.4
-
=3V, Y'N = VLe or VHe, 10L = 300,..A
Vee = Min.
Y,N =V,H or V'L
On Ai and Bi
2.4
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee
=
5.0V, +25"C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-177
V
V
V
IDT54174FCT645/A
FAST CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
=O.2V; VHC =vcc - O.2V
VLC
SYMBOL
Icca
Quiescent Power Supply Current
Vcc= Max.
V,N " VHo V,N S VLC
Ii =0
ICCT
Power Supply Current
TTL Inputs HIGH
Vcc= Max.
V ,N = 3.4V(3)
Icco
Dynamic Power Supply
Current
Vce= Max.
Outputs Open
OE =GND
T/R = GND or Vcc
One Input Toggling
50% Duty Cycle
Icc
Total Power Supply(4)
Current
MIN.
TYR(2)
MAX.
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V,N " VHC
V,NS VLC
-
0.15
0.25
V,N " VHC
V,N S VLC (FCT)
-
1.5
4.0
V,N = 3.4V
V,N=GND
-
1.8
4.8
V,N " VHC
V,N S VLC (FCT)
-
3.0
6.5
V,N = 3.4V
V,N = GND
-
5.0
12.9
TEST CONDITIONS(!)
PARAMETER
Vcc= Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OE =GND
One Bit Toggling
Vcc= Max.
Outputs Open
Ii = 2.5MHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
rnA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25 D C ambient and maximum loading.
3. Per TTL driven input (V'N = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'aUIESCENT + 'INPuts + 'DYNAMIC
Icc = ICCQ + ICCTDHNT + ICCD (fcp/2 + fiNj)
ICCQ =
Quiescent Current
'CCT = Power Supply Current for a TTL High Input (V 1N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fop = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-178
mAl
MHz
IDT54/74FCT645/A
FAST CMOS NON-INVERTING BUFFER TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
FUNCTION TABLE
DESCRIPTION
OE
T/R
Ao-A7
INPUTS
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A I nputs or
3-State Outputs
Side B Inputs or
3-State Outputs
Bo-B7
OE
OPERATIONS
TIR
L
L
H
L
H
Bus B Data to Bus A
Bus A Data to Bus B
High Z State
X
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT645
SYMBOL
PARAMETER
IpHl
Propagation Delay
AtoBorBloA
tZH
tZl
Output Enable
Time
1HZ
tlZ
Output Disable
Time
t plH
tOLH
tOHl
Pro2-agation Delay
T/R to A or B(1)
CONDITION
Cl
Rl
=50pF
=soon
COM'L.
TYP.
IDT54174FCT645A
MIL.
MAX.
MIN.
MAX.
6.0
2.0
9.5
2.0
11.0
9.0
2.0
11.0
2.0
12.0
6.0
2.0
12.0
2.0
13.0
6.0
-
-
-
-
'.
MIL.
COM'L.
TYP.
MIN.
UNITS
MIN.
MAX.
MIN.
MAX.
3.3
1.5
4.6
1.5
,~.9,
ns
4.8
1.5
:; ~,f"t~ ~~J:' f5~.5
ns
. '\ , 1.5
4.$'
'"
5.0
-
5.0
1.5
6.0
ns
-
-
-
ns
NOTE:
1. Guaranteed by design.
III
5-179
FEATURES:
DESCRIPTION:
• 35% faster than AM D's Am29821-26 series
The IOTS4174FCT800B Series is built using advanced
CEMOS'", a dual metal CMOS technology.
The IOTS4174FCT800B Series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or busses carrying parity. The IOTS41
74FCT821B and IOTS4/74FCT822B are buffered, 10-bit wide
versions of the popular '374fS34 functions. The IDTS4/74FCT823B and IOTS4/74FCT824B are 9-bit wide buffered registers
with Clock Enable (EN) and Clear (CLR-ideal for parity bus
interfacing in high-performance microprogrammed systems.
The IOTS4/74FCT82SB and IOTS4/74FCT826B are8-bit buffered
registers with all the '823/4 controls plus multiple enables (OE1,
OE2, OE3) to allow multiuser control of the interface, e.g., CS,
OMA and RO/WR. They are ideal for use as an output port
requiring high IOL/loH.
All olthe IDTS4174FCT800B high-performance interface family
are designed for high capacitance load drive capability while
providing low capacitance bus loading at both inputs and
outputs. All inputs have clamp diodes, and all outputs are
designed for low capacitance bus loading in the high impedance
state.
• Equivalent to AMO's Am29821-26 bipolar registers in
pinout/function and output drive over full temperature and
voltage supply extremes
• High-speed parallel registers with positive edge-triggered
O-type flip-flops
-Non-inverting CP-Y tpD = S.Ons typo
-Inverting CP-Y tpD = S.Ons typo
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
•
•
•
•
48mA commercial IOL' 32mA military IOL
200mV (typ.) hysteresis on clock INPUT
Clamp diodes on all inputs for ringing suppression
ESO protection SOOOV (typ.) - MIL-STO-883 Category B
• Low input/output capacitance
-6pF inputs (typ.)
-8pF outputs (typ.)
• CMOS power levels (S}J.W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AMO's bipolar
Am29800 series (S}J.A max.)
• Military product available 100% screened to MIL-STO-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
CLOCK
ENABLE
DO
Os
CE
CLEAR
CLR-i:~----+---~--~+---~--~+---~---++---~--4-~--~--4-~--'-
CLOCK
CP -[~--~~-----4~------~~----~~------~~-----+~
OUTPUT
ENABLE
OE -i~----------~-+------~-+------~-+------~~------~4-------~
Ys
YO
Yn-l
Yn
SSD39C821-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Cl1986 Integrated Device Technology, Inc.
Prjnted in the U.S.A.
5-180
IOT54/74FCTB21-26B
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LOGIC SYMBOLS
IDT54n4FCT821BIIDT54/74FCT822B 10-BIT REGISTERS
OE
Vee
do
YO
01
Yl
02
Y2
03
Y3
04
Y4
05
Ys
06
Y6
07
Y7
Oa
Ya
0
Q 81~ u
Z ~~
II
Og
I,
LJ L.J
02
-, 4
5
,,
U
2
3
_J
O:i :J6
II
>=
,, ,,
II
I I L..J
I I 28
LJ
1
LJ
LJ
27 26,-2S L -
Y3
:J 7
Y4
NC
:J8
NC
05
:J9
Ys
04
06 :JlO
Yg
CP
0
07
16
00
o"'0
Z
Cl
DIP
TOP VIEW
19,181--
-,11
_-J
o
10
0
Y
CP
Y6
rl r~ r1 Fl rl fl ", ,
GNO
Y2
U
Q.
-1!
U
Z
CP-----'
OE ------------------'
~
LCC
TOP VIEW
SSD39C821-005
Y7
SSD39C821-002
SSD39C821-006
IDT54/74FCT823BIIDT54/74FCT824B 9-BIT REGISTERS
OE
Q81~fil~::=>=
Vee
Do
Yo
01
Yl
02
Y2
03
Y3
04
Y4
05
Ys
08
Ys
07
Y7
Oa
I
Ya
EN
GNO
CP
II
I
r ••
II
II
I I L.J 1...1 L..I
I I 28 27 26,.2S\""-
Y2
:J6
24[:
Y3
04
:J 7
23[:'
Y4
NC
:J8
:J9
22[-:'
NC
05
21[:
Ys
Os
:JlO
20[:
Ys
CP
07
-,11
19,lSL--
Y7
EN
_J
03
L..I
2
5
_oJ
CLR
r 11
L.J l.J
-, 4
3
02
rl t~
Ll
17
1415 16
r, r,
II
II
r,
1""
I
I
II
o ,a-': §! fil f> Iffi
u
00
," ,
0
9
0
CLRQ
9
Y
III
CLR
~
OE
Cl
DIP
TOP VIEW
LCC
TOP VIEW
SSD39C821-003
SSD39C821 -008
SSD39C821-Q07
IDT54n4FCT825BIIDT54n4FCT826B 8-BIT REGISTERS
OEl
Vce
OE2
OE3
01.n'IW
U
000 Z
II
DO
Yo
01
Yl
02
Y2
03
Y3
03
01
II
L.JU
-, 4
3
_J
5
o ..
~I~
U II U
2
I I 26
LJ
:e
II
II
1...1
L..I
0
27 261'"2S L
1
-
Y2
:J 7
23[:'
Y3
:J8
22[-:'
NC
04
Y4
NC
05
Ys
04
:J9
21[':
Y4
Os
Ys
05
:JlO
20[:
Ys
07
Y7
06
-,11
_oJ 12
rr--
Ys
CLR
EN
GNO
Yo
19r-
13
,.,
1""'
1"
I
0la:d
14
r,
I I
15
1""
II
16 17
r,
r,
I I I,'
I
U Q. Z
~ Z U w
0
0
Q
Yl
24:::
02 :J6
B
CLR
8
Y
CP
EN
CLR
OEl
OE2
OE3
-I:
LCC
TOP VIEW
DIP
TOP VIEW
SSQ39CB21-009
SSD39C821-01Q
5-181
SSD39C821-004
IDT54/74FCT821-26B
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
PIN DESCRIPTION
PRODUCT SELECTOR GUIDE
1/0
NAME
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION
DEVICE
Di
I
The D flip-flop data inputs.
CLR
I
For both inverting and noninverti~egisters,
when the clear input is LOW and OE is LOW, the
0, outputs are LOW. When the clear input is
HIGH, data can be entered into the register.
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Vi,Vi
EN
0
The register three-state outputs.
I
Clock Enable. When the clock enable is LOW,
data on the Di input is transferred to the 0i
output on the LOW-to-HIGH clock transition.
When the clock enable is HIGH, the 0i outputs
do not change state, regardless of the data or
clock input transitions.
OE
I
Output Control. When the OE input is HIGH, the
Vi o'!.!Quts are in the high impedance state. When
the OE input is LOW, the TRUE register data is
present at the Vi outputs.
1CJ..BIT
9-BIT
8-BIT
Non-inverting
IDT54174
FCT821B
IOT54174
FCT823B
IOT54174
FCT825B
Inverting
IDT54174
FCT822B
IOT54174
FCT824B
IOT54174
FCT826B
FUNCTION TABLES
IDT54174FCT822124/26B
IDT54174FCT821/23/25B
INPUTS
OE CLR EN 0, CP
Q,
V,
Z
Z
H
H
X
X
L
L
L
H
t
t
L
H
H
L
L
L
X
X
X
X
X
X
L
L
H
L
H
H
H
H
X
X
X
X
H
H
L
L
H
H
H
H
L
L
L
L
L
H
L
H
t
t
t
t
H =HIGH
L = LOW
X = Don't Care
INTERNAL OUTPUTS
INPUTS
INTERNAL OUTPUTS
FUNCTION
OE CLR EN 0, CP
V,
t
H
L
Z
Z
Hi-Z
X
X
L
L
Z
L
Clear
X
X
X
X
NC
NC
Z
NC
Hold
L
H
L
H
t
t
t
t
H
L
H
L
Z
Z
H
L
Load
Hi-Z
X
X
L
L
L
H
I
Z
L
Clear
H
L
L
L
X
X
X
X
NC
NC
Z
NC
Hold
H
L
H
H
H
H
L
H
L
H
Z
Z
L
H
Load
H
H
L
L
H
H
H
H
L
L
L
L
NC = No Change
t
= LOW-to-HIGH Transition
Z = High Impedance
H = HIGH
L = LOW
X = Don't Care
5-182
FUNCTION
Q,
H
H
NC = No Change
t
= LOW-to-HIGH Transition
= High Impedance
Z
IDT54/74FCT821-26B
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
CAPACITANCE
COMMERCIAL
MILITARY
UNIT
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
DC
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
100
100
mA
-0.5 to +ZO
-0.5 to +7.0
V
(TA = +25°C, f = 100M Hz)
PARAMETERI')
SYMBOL
C 'N
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
=OV
VOUT =OV
6
pF
8
pF
V,N
NOTE:
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA =O°C to +70°C
Vee = 5.0V ± 5%
Min.
TA = -55°C to +125°C
Vee = 5.0V ± 10%
Min.
VLe = 0.2V
VHe = Vee - 0.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYp'I')
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V'L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
=Max., V,N =Vcc
Vcc =Max., V,N =GND
Vcc =Min., IN =-18mA
-
-
5
p.A
-
-5
p.A
-
-0.7
-1.2
V
SYMBOL
PARAMETER
TEST CONDITIONSI')
Vcc
I'L
Input LOW Current
V,
Clamp Diode Voltage
loz
Off State (High Impedance)
Output Current
Vce
= MAX
Ise
Short Circuit Current
Vee
=Max. (3)
=3V, V,N =VLe or VHe,
Vee
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VH
Input Hysteresis on Clock Only
=O.4V
Vo =2.4V
Vo
-
-
-10
-
-
10
-75
-120
-
VHe
Vee
-
10H
VHe
Vee
-
10H
2.4
4.0
10H
=-32p.A
=-250p.A
=-15mA MIL.
10H =-24mA COM.
Vee =3V, V,N =VLe or VHe , 10L =300p.A
10L =300p.A
Vee =Min.
10L =32mA MIL.
V,N =V,H or V'L
10L =48mA COM.
Vee = Min.
V,N =V,H or V'L
-
3.5
-
-
GND
VLe
-
GND
VLe
2.0
-
-
0.5
-
-
0.5
-
200
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. DUration of the short circuit test should not exceed one second.
5-183
MAX.
UNIT
V
p.A
mA
V
V
mV
IDT54/74FCTB21-26B
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; v HC = vcc - 0.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc = Max.
VIN '" VHC; VIN :5 VLC
Icp=I;=O
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vee = Max.
VIN = 3.4V(3)
Dynamic Power Supply
Current
Vcc= Max.
Outputs Open
OE=GND
One Bit Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply(')
Current
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
VIN'" VHC
VIN :5 VLC
-
0.15
0.25
VIN'" VHC
VIN :5 VLC
(FCT)
-
1.5
4.0
VIN = 3.4V
or
VIN=GND
-
2.0
5.6
VIN'" VHC
VIN :5 VLC
(FCT)
-
3.75
7.8
VIN = 3.4V
or
VIN = GND
-
6.0
15.0
TEST CONDITIONS(1)
PARAMETER
Vcc= Max.
Outputs Open
Icp= 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
at Ii = 5MHz
50% Duty Cycle
Vcc= Max.
Outputs Open
Icp = 10MHz
50% Duty Cycle
OE =GND
Eight Bits Toggling
at Ii = 2.5M Hz
50% Duty Cycle
mA
NOTES:
1. For conditions shown as ;;'ax. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = 'aUIESCENT+ 'INPUTS + 'DVNAMIC
Icc = ICCQ + ICCTDHNT + ICCD (fcp/2 + fiNi)
'ceQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp ="Clock Frequency for Register Devices (Zero for Non-Register Devices)
1j = Input Frequency
Nj = Number of Inputs at 1j
All currents are in milliamps and all frequencies are in megahertz.
5-184
mAl
MHz
IDT54/74FCTB21-26B
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MILITARY
COMMERCIAL
PARAMETERS
IpLH
IpHL
IpLH
IpHL
TEST CONDITIONS(')
DESCRIPTION
Propagalion Delay Clock 10 Vi (OE " lOW)
UNITS
MIN
MAX
MIN
MAX
C L " 50pF
RL" 500n
-
7.5
3.5
8.5
ns
C L " 300pF
RL" 500n
-
7.5
3.5
8.5
ns
ts
Data to CP Setup Time
3.0
-
3.0
-
ns
tH
Dala 10 CP Hold Time
1.5
1.5
-
ns
L) 10 CP Selup Time
3.0
-
3.0
-
ns
) to CP Setup Time
3.0
-
3.0
-
ns
0
-
0
-
ns
Is
Enable (EN
Is
Enable (EN
IH
Enable (EN) Hold Time
tpHL
Propagation Delay, Clear to Vi
Is
Clear Recovery (ClR L)Time
t PWH
L
C L " 50pF
RL" 500n
IZH
tZL
IZH
IZL
tHZ
tLZ
t Hz (2)
tLZ
9.0
-
9.5
ns
-
6.0
ns
6.0
6.0
6.0
6.0
-
-
6.0
-
ns
C L " 300pF
RL" 500n
-
8.0
-
8.0
ns
C L " 50pF
RL" 500n
-
8.0
-
8.0
ns
C L " 50pF
RL" 500n
-
6.5
-
7.0
ns
C L " 5pF(2)
RL" 500n
-
6.5
-
7.0
ns
I HIGH
Clock Pulse Width
I lOW
tpWL
IPWL
6.0
6.0
Clear (ClR " lOW) Pulse Width
OUlpul Enable Time 6E """"L to Vi
Output Disable Time OE
~
to Vi
NOTES:
1. See test circuit and waveforms.
2. This parameter guaranteed but not tested.
5-185
ns
ns
FEATURES:
DESCRIPTION:
• 35% faster than AMO's Am29841-46 series
• Equivalent to AMO's Am29841-46 Bipolar Registers in
pinout/function, and output drive over full temperature and
voltage supply extremes
• High-speed parallel latches
-Non-inverting transparent tpD = 4.0ns typo
-Inverting transparent tpD = 4.5ns typo
• Buffered common latch enable, clear and preset input
The IOT54fl4FCT800 Series is built using advanced CEMOS'",
a dual metal CMOS technology.
The IOT54fl4FCT840B Series bus interface latches are
designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data
paths or buses carrying parity. The IOT54/74FCT841 Band
IOT54fl4FCT842B are buffered, 1O-bit wide versions of the popular '373 function. The I OT54fl4FCT843B and I OT54fl4FCT844B
are 9-bit wide buffered latches with Preset (PRE) and Clear
(ClR)-ideal for parity bus interfacing in high-performance
systems. The IOT54/74FCT845B and IOT54/74FCT846B are
8-bit buffered latches with all the '84314 controls plus multiple
enables (OE" OE 2, OEs) to allow multiuser control of the interface, e.g. CS, OMA and ROIWR. They are ideal for use as an
output port requiring high IOl/loH'
All of the IOT54fl4FCT800B high-performance interface
family are designed for high capacitance load drive capability
while providing low capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes, and all outputs are
designed for low capacitance bus loading in the high impedance state.
•
•
•
•
•
•
•
•
•
48mA commercial IOl' 32mA military IOl
200mV (typ.) hysteresis on latch enable input
Clamp diodes on all inputs for ringing suppression
ESO protection 5000V (typ.) - Mll-STO-883 Category B
low input/output capacitance
-6pF inputs (typ.)
-8pF outputs (typ.)
CMOS power levels (5p.W typo static)
Both CMOS and TTL output compatible
Substantially lower input current levels than AMO's bipolar
AM29800 Series (5p.A max.)
Military product available 100% screened to Mll-STO-883,
Class B
FUNCTIONAL BLOCK DIAGRAM
PRODUCT SELECTOR GUIDE
DSA39C841·001
DEVICE
1D-BIT
9-BIT
a-BIT
Non-inverting
IDT54174
FCT841B
IDT54174
FCT843B
IDT54174
FCT845B
Inverting
IDT54174
FCT842B
IDT54174
FCT844B
IDT54174
FCT846B
CEMOS is •
trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed in U.S.A.
CI 1986 Integrated Device Technology, Inc.
5-186
IDT54/74FCT841-46B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
LOGIC SYMBOLS
IDT54/74FCT841B/IDT54174FCT842B 10-BIT LATCHES
OE
Vee
Do
Yo
D1
Y1
D2
Y2
D3
Y3
D4
Y4
Ds
Ys
Ds
Ys
D7
Y7
. . 0lw
0
t I II
I
t I
II
LJ
LJ
27
26,..251--
Y2
24[::
Y3
23[:'
Y4
NC
22C..
NC
Ds
21::::
Ys
20[:
Ys
LE
19r--
Y7
OE
II
LJ LJ
3
D2
:Js'
D3
:J6
D4
:J 7
L2.J
~
I
:
t
I
~~
LJ
1
Ds
D7
Da
Ya
D9
Y9
LE
-,11
- ..... 12
r""
I
GND
0
ccoz~~>
c
II
II
II
16
1""'
rl rf--
C
Z
U
Z
UI
....I
of!~
14 15
13
,..,
1'1
co
0)
C
r., ,..,
D
~
D
LE
a
..,....
10
Y
I
C)
LCC
TOP VIEW
DIP
TOP VIEW
DSA39C841·005
DSR39C841-006
DSR39C841-002
IDT54174FCT843B/IDT54174FCT844B 9-BIT LATCHES
OE
Vee
Do
Yo
D1
Y1
D2
Y2
D3
Y3
D4
Y4
Ds
Ys
Ds
Ys
D7
Y7
Da
Ya
CLR
Q81~~~~>
II
LJ
D2
~J
II
l.J
3
2
:J6
D4 :J 7
D3
II U
I I 28
LJ
1
II
It
LJ
LJ
27
261""-
251--
Y2
24[:
Y3
23[:
Y4
NC
:]8
22[:
NC
Ds
:J9
21[:
Ys
Ds
::::JlO
20[:
Ys
D7
-,11
rr--
Y7
_..I
12 13 14 15 16 17
r., ,..,
,.., ,.., r, r1
II
PRE
GND
-, 4
5
_J
I
I
II
II
II
II
19r-
D
9
D
Y
LE
PRE
CLR
OE
~1a:coa..IUI
rlzzoa: ~
LE
a..
C)
DIP
TOP VIEW
LCC
TOP VIEW
DSR39C841-007
DSR39C841-00B
DSR39C841-003
IDT54174FCT845B/IDT54174FCT846B 8-BIT LATCHES
OE1
Vee
OE2
OE3
Do
Yo
D1
Y1
°
col.n'lw gl~
cooz>o
II
D1
I
I
l.Jl.J
-, 4 3
_J
5
~J
! ! ~~
LJ
1
~
II
LJ
II
LJ
27
26,..251--
Y1
Y2
Y3
D
Y2
D2
24[:
D3
Y3
D3
23[:
D4
Y4
NC
22[:
NC
Ds
Ys
D4
21[:
Y4
20[:
Ys
rr--
Ys
D2
Ds
Ys
Ds
D7
Y7
Ds
CLR
PRE
GND
LE
DIP
TOP VIEW
-,11
_oJ 12
19r--
14 15 16 17
13 r,
,.., ,..,
,..., r1 r'.,
I
I
I
I
II
ola:
c
....I z
OC)
II
I
I
II
° ~f
Z
8
D
8
Y
LE
PRE
CLR
OE1
OE2
~
OE3
LCC
TOP VIEW
DSR39C841...o10
DSR39C841-009
5-187
DSA39C841-004
II
IDT54/74FCT841-46B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARV AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
1/0
NAME
DESCRIPTION
IDT54/74FCT841/43/45B (Non-Inverting)
CLR
I
When CLR is low, the outputs are LOW if OE is
LOW. When CLR is HIGH, data can be entered
into the latch.
Di
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data is
latched on the HIGH-to-LOW transition.
Vi
a
The 3-state latch outputs.
OE
I
The output enable control. When OE is LOW, the
outputs are enabled. When OE is HIGH, the
outputs Vi are in the high-impedance (off) state.
PRE
I
Preset Ii~ When PRE is LOW, the ou~s are
HIGH if OE is LOW. Preset overrides CLR.
IDT54n4FCT842/44/46B (Inverting)
CLR
I
When CLR is low, the outputs are LOW if OE is
LOW. When CLR is HIGH, data can be entered
into the latch.
Di
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data is
latched on the HIGH-to-LOW transition.
Vi
a
The 3-state latch outputs.
OE
I
The output enable control. When OE is LOW, the
outputs are enabled. When OE is HIGH, the
outputs Vi are in the high-impedance (off) state.
PRE
I
Preset line. When PRE is LOW, the oU.!£!!!s are
HIGH if ~is Law. Preset overrides CLR.
FUNCTION TABLES
IDT54/74FCT841/43/45B
CLR
PRE
OE
IDT54174FCT842/44/46B
INTERNAL
OUTPUTS
INPUTS
LE
D,
Q,
V,
INTERNAL
OUTPUTS
INPUTS
FUNCTION
CLR
PRE
OE
LE
D,
Q,
V,
FUNCTION
H
H
H
X
X
X
Z
Hi-Z
H
H
H
X
X
X
Z
Hi-Z
H
H
H
H
L
L
Z
Hi-Z
H
H
H
H
H
L
Z
Hi-Z
H
H
H
H
H
H
Z
Hi-Z
H
H
H
H
L
H
Z
Hi-Z
H
H
H
L
X
NC
Z
Latched
(Hi-Z)
H
H
H
L
X
NC
Z
Latched
(Hi-Z)
H
H
L
H
L
L
L
Transparent
H
H
L
H
H
L
L
Transparent
H
H
L
H
H
H
H
Transparent
H
H
L
H
L
H
H
Transparent
H
H
L
L
X
NC
NC
Latched
H
H
L
L
X
NC
NC
H
L
L
X
X
H
H
Preset
H
L
L
X
X
H
H
Preset
Latched
L
H
L
X
X
L
L
Clear
L
H
L
X
X
L
L
Clear
L
L
L
X
X
H
H
Preset
L
L
L
X
X
H
H
Preset
L
H
H
L
X
L
Z
Latched
(Hi-Z)
L
H
H
L
X
L
Z
Latched
(Hi-Z)
H
L
H
L
X
H
Z
Latched
(Hi-Z)
H
L
H
L
X
H
Z
Latched
(Hi-Z)
5-188
IDT54174FCT841-46B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect
toGND
COMMERCIAL
-0.5 to +7.0
CAPACITANCE (TA = +25°C, f = 1.0MHz)
MILITARY
UNIT
-0.5 to +7.0
PARAMETER(')
CONDITIONS
TYP.
UNIT
C 'N
Input Capacitance
V,N = OV
6
pF
C OUT
Output Capacitance
8
pF
SYMBOL
V
VOUT
= OV
NOTE:
TA
Operating
Temperature
oto +70
-55 to +125
°C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
"C
lOUT
DC Output Current
100
100
mA
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to +70°C
Vcc =5.0V ± 5%
Min.
TA =-55°C to +125°C
Vcc = 5.0V ± 10%
Min.
VLC = 0.2V
VHC = VCC - 0.2V
=4.75V
=4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
MIN.
TYP'(2)
MAX.
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vee
-
5
p.A
Input LOW Current
Vce
-
-
-5
p.A
V,
Clamp Diode Voltage
=Max., V,N =Vee
= Max., V,N = GND
Vee = Min., IN =-18mA
-
I'L
-
-0.7
-1.2
V
-
-
-10
Vee
=MAX
-
loz
Off State (High Impedance)
Output Current
Ise
Short Circuit Current
Vee
= Max. (3)
= 3V, V,N =VLe or VHe,
SYMBOL
TEST CONDITIONS(')
PARAMETER
Vee
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VH
Input Hysteresis on Latch Enable Only
=O.4V
Vo =2.4V
Vo
-75
-120
-
Vee
-
10H
VHe
Vee
-
IOH
2.4
4.0
-
=-32p.A
=-250p.A
= -15mA MIL.
IOH =-24mA COM.
Vee = 3V, V,N =VLe or VHe , 10L = 300p.A
10L =300p.A
Vee = Min.
10L =32mA MIL.
V,N =V,H or V,L
10L =48mA COM.
Vee = Min.
V,N =V,H or V'L
-
3.5
-
-
GND
VLe
-
GND
VLe
-
0.5
-
-
-
200
-
2.0
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-189
p.A
10
VHe
10H
UNIT
mA
V
V
0.5
mV
IDT54/74FCT841-46B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC =O.2V; VHC =vcc - O.2V
SYMBOL
ICCQ
Quiescent Power Supply Current
Vcc: Max.
V,N ", VHC ';; Y'N ,; VlC
Ii: 0
ICCT
Power Supply Current
TTL Inputs HIGH
Vcc: Max.
V ,N : 3.4V(3)
Dynamic Power Supply
Current
Vcc: Max.
Outputs Open
OE: GND
LE: VCC
One Input Toggling
50% Duty Cycle
ICCD
Icc
MIN.
TYP'(2)
MAX.
UNIT
-
0.001
1.5
mA
-
0.5
1.6
mA
V,N'" VHC
Y,N'; VlC
-
0.15
0.25
V,N'" VHC
V,N '; VlC (FCT)
-
1.5
4.0
V,N : 3.4V
V,N : GND
-
1.8
4.8
V,N'" VHC
V,N '; VlC (FCT)
-
3.0
6.5
V,N : 3.4V
V,N : GND
-
5.0
12.9
TEST CONDITIONS(1)
PARAMETER
Vcc: Max.
Outputs Open
Ii: 10MHz
50% Duty Cycle
OE:GND
LE: Vec
One Bit Toggling
Total Power Supply(4)
Current
Vcc: Max.
Outputs Open
Ii: 2.5MHz
50% Duty Cycle
OE: GND
LE: Vcc
Eight Bits Toggling
mA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vee or GND.
4.
Icc = 'QUIESCENT + 'INPUTS
Icc
+ 'DYNAMIC
= 'CGQ + ICCTDHNT + ICCD (fcp/2 + fiNi)
'CGQ = Quiescent Current
ICCT =Power Supply Current for a TTL High Input (V ,N
=3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fep = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fj = Input Frequency
Nj = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
5-190
mAl
MHz
IDT54/74FCT841-46B
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
PARAMETERS
TEST CONDITIONS(1)
DESCRIPTION
tpHL
Data (D;) to Output (Y;)
(LE = HIGH)
tpLH
tpHL
ts
Data to LE Setup Time
tH
Data to LE Hold Time
t pLH
(I DT54/74FCT 42B,44B,46B)
t pHL
tpLH
tpHL
ts
Data to LE Setup Time
tH
Data to LE Hold Time
MAX.
C L = 50pF
RL = 50011
-
6.5
-
7.5
ns
C L = 300pF
RL =50011
-
6.5
-
7.5
ns
2.5
-
2.5
-
ns
2.5
-
2.5
-
ns
C L =50pF
RL =50011
-
8.0
-
9.0
ns
C L = 300pF
RL = 50011
-
8.0
-
9.0
ns
ns
ns
2.5
-
2.5
-
2.5
-
2.5
-
C L = 50pF
RL = 50011
-
8.0
-
10.5
ns
C L = 300pF
RL = 50011
-
ns
C L = 50pF
RL = 50011
tpLH
tpHL
Latch Enab)e (LE) to Y;
t pLH
t pHL
tpLH
Propagation Delay, Preset to Y;
ts
Preset recovery (PRE J) Time
UNITS
MIN.
C L =50pF
RL =50011
Data (D;) to Output (Y;)
(LE = HIGH)
MILITARY
MAX.
tpLH
(I DT54/74FCT41 B,43B,45B)
COMMERCIAL
MIN.
C L =50pF
RL =50011
8.0
-
9.0
-
8.0
-
10.0
ns
-
10.0
-
13.0
ns
-
10.0
tpHL
Propagation;Delay, Clear to Y
-
11.0
ns
ts
Clear Recovery (CLRJ) Time
10.0
-
10.0
-
ns
tPWH
LE Pulse Width
HIGH
4.0
-
4.0
-
ns
t pwL
Preset Pulse Width
LOW
4.0
-
4.0
-
ns
t PWL
Clear Pulse Width
LOW
4.0
-
4.0
-
ns
C L = 300pF
RL =50011
-
8.0
-
8.5
ns
tZH
tZL
C L = 50pF
RL =500ll
-
8.0
-
8.5
ns
tHZ
tLZ
t HZ (2)
tLZ
C L =50pF
RL = 50011
-
7.0
-
7.5
ns
C L = 5pF
RL = 500ll
-
7.0
-
7.5
ns
tZH
tZL
Output Enable Time (OE j ) Time
C L =50pF
RL =50011'
Output Disable Time (OE...r) Time
NOTES:
1. See test circuit and waveforms.
2. This parameter guaranteed but not tested.
5-191
FEATURES:
DESCRIPTION:
• 35'10 faster than AMD's Am29861-64 series
• Equivalent to AM D's Am29861-64 bipolar registers in
pinout/function and output drive over full temperature and
voltage supply extremes
• High-speed symmetrical bidirectional transceivers
-Non-inverting tpo = 3.5ns typo
-Inverting tpo = 4.0ns typo
• 48mA commercialloL, 32mA military IOL
• 200mV (typ.) hysteresis on T and R buses
• Clamp diodes on all inputs for ringing suppression
• ESD protection 5000V (typ.) - MIL-STD-883 Category B
• Low input/output capacitance
• CMOS power levels (5/LW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 series (5/LA max.)
• Military product available 100'10 screened to MIL-STD-883,
Class B
The I DT54174FCT800 Series is built using advanced CEMOS··,
a dual metal CMOS technology.
The IDT54174FCT860 Series bus transceivers provide highperformance bus interface buffering for wide data/address paths
or buses carrying parity. The IDT54/74FCT863B and IDT54/
74FCT864B 9-bit transceivers have NORed output enables for
maximum control flexibility.
All of the IDT54174FCTOOOB high-performance interface family
are designed for high-capacitance load drive capability while
providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes, and all outputs are designed
for low-capacitance bus loading in the high impedance state.
FUNCTIONAL BLOCK DIAGRAM
IDT54!74FCT861 B/IDT54!74FCT862B 10-BIT TRANSCEIVERS
SS039C861-001
PRODUCT SELECTOR GUIDE
DEVICE
I Non-inverting
I Inverting
10-BIT
!l-BIT
IDT54/74FCT861 B
IDT54174FCT863B
I DT54174FCT862B
IDT54174FCT864B
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Cl1986 Integrated Device Technology, Inc.
Printed in the U.S.A.
5-192
IDTS4/74FCT861-64B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
IDT54n4FCT863B/IDT54n4FCT864B 9-BIT TRANSCEIVERS
Ra
Ra
R7
DEll
OET2
55 D39C861-004
LOGIC SYMBOLS
PIN CONFIGURATIONS
IDT54/74FCT861B/IDT54n4FCT862B 10-BIT TRANSCEIVERS
OER
IDT54n4FCT861 B
_ .. lffioHo~
a:a:oZ>1-"1-
Vee
Ro
To
Rl
Tl
R2
-..15
R2
T2
Ra
:J6
R3
Ta
R4
:J 7
R4
T4
NC
Rs
Ts
:J8
Rs :J9
R6
T6
Ra
:J10
20[:
T6
R7
T7
R7
-·,11
-..I 12 13 14 15 16 17
19r181--
T7
Ra
Rg
T8
II
~.1
II
L3.J
II
II II
Lt I : 28
II
DET
II
2~ ~r-
L,J
251..-
T2
24[:
T3
T4
NC
10
R
T
T5
nf1r1rlf1rlfl
T9
OEl
GND
_.,
OER
.mQUII-~.!E
a:a:zzw~~
CI
DIP
TOP VIEW
0
SSD39C861O-002
LCC
TOP VIEW
SSD39CSbt-u05
SSD39C861-006
IDT54n4FCT863B/IDT54/74FCT864B 9-BIT TRANSCEIVERS
OERl
I
i
u
IE~~~~F'~
Vee
To
Ro
II
II
L.J L.J
-] 4
- 5
3
II
LJ
2
II
II
I I L.J
II
L..J
IDT54/74FCT863B
II
LJ
I I 28 27 26rL,J
2245~:
T2
Rl
R2
Tl
R2
T2
R3
:J6
R3
T3
R4
:J 7
R4
T4
NC
Rs
Ts
Rs
:J8
:J9
21[:
T5
R6
T6
R6
:J10
20[:
T8
R7
T7
Ta
R7
:J ~~
13 14 15 16 17 ;:[:
,.., r.,
,., ,., r, ,., ,.,
T7
Ra
OER2
OET2
GND
DETl
DIP
TOP VIEW
SSD39C861-Q07
I
'-_ T3
23[: T4
22[:' NC
1'1
II
II
I
I
II
121~ C'UIt=I~
~ ~ Z ~ ~
T
II
{!
LCC
TOP VIEW
5SUJ9C861-OO8
5-193
9
SSD39C861 003
I
IDT54174FCT861-64B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
NAME
1/0
DESCRIPTION
IDT54174FCT861/62B
OER
I
When LOW in conjunction with OET HIGH
activates the RECEIVE mode.
OET
I
When LOW in conjunction with OER HIGH
activates the TRANSMIT mode.
R;
I/O
la-bit RECEIVE input/output.
T;
I/O
10-pit TRANSMIT input/output.
IDT54174FCT863/64B
OER;
I
When LOW in conjunction with OET; HIGH
activates the RECEIVE mode.
OET;
I
When LOW in conjunction with OER; HIGH
activates the TRANSMIT mode.
R;
I/O
9-bit RECEIVE input/output.
T;
1/0
9-bit TRANSMIT input/output.
FUNCTION TAB ....ES
IDT54174FCT861BIIDT54174FCT863B (Non-inverting)
INPUTS
OER
OER
RI
IDT54174FCT662B/IDT54174FCT864B (Inverting)
INPUTS
OUTPUTS
TI
RI
TI
FUNCTION
OER
OER
RI
OUTPUTS
TI
RI
TI
FUNCTION
L
H
L
N/A
N/A
L
Transmitting
L
H
L
N/A
N/A
H
Transmitting
L
H
H
N/A
N/A
H
Transmitting
L
H
H
N/A
N/A
L
Transmitting
H
L
N/A
L
L
N/A
Receiving
H
L
N/A
L
H
N/A
H
L
N/A
H
H
N/A
Receiving
H
L
N/A
H
L
N/A
H
H
X
X
Z
Z
Hi-Z
H
H
X
X
Z
Z
H; HIGH
L;LOW
Z ; High Impedance
X ; Don't Care
N/A ; Not Applicable
H =HIGH
L=LOW
Z = High Impedance
5-194
Receiving
Receiving
Hi-Z
X = Don't Care
N/A = Not Applicable
IDT54174FCT861-64B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
Terminal Voltage
with Respect
toGND
COMMERCIAL
-0.5 to +7.0
CAPACITANCE (TA ~ +25°C, f ~ 1.0MHz)
MILITARY
-0.5 to +7.0
PARAMETER(')
SYMBOL
UNIT
V
CONDITIONS
V,N
C 'N
Input Capacitance
COUT
Output Capacitance
TYP.
UNIT
6
pF
8
pF
OV
0
VOUT
0
OV
NOTE:
TA
Operating
Temperature
o to +70
-55 to +125
°C
TS1AS
Temperature
Under Bias
-55 to +125
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +155
°C
lOUT
DC Output Current
100
100
mA
1. This parameter is sampled and not 100% tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA ~ O°C to +70°C
Vec ~ 5.0V ± 5%
Min.
TA ~ -55°C to +125°C
Vcc ~ 5.0V ± 10%
Min.
VLC ~ 0.2V
VHC = Vcc - 0.2V
SYMBOL
~
~
4.75V
4.50V
Max. = 5.25V (Commercial)
Max. = 5.50V (Military)
TEST CONDITIONS(')
TYP.(')
MAX.
UNIT
V,H
Input HIGH Level
Guaranteed Logic High Level
2.0
-
-
V
V'L
Input LOW Level
Guaranteed Logic Low Level
-
-
0.8
V
I'H
Input HIGH Current
Vec ~ Max., V,N
=Vce
-
-
5
/J. A
0
PARAMETER
GND
-
-
-5
/J.A
=-18mA
-
-0.7
-1.2
V
-10
-
I'L
Input LOW Current
Vcc = Max., V,N
V,
Clamp Diode Voltage
Vee
loz
Off State (High Impedance)
Output Current
Vce ~ MAX
Isc
Short Circuit Current
Vcc ~ Max. (3)
Vcc
VOH
Output HIGH Voltage
Vce
Output LOW Voltage
VH
Input Hysteresis on Rj and Ti
Min., IN
Va
~
O.4V
-
Va
~
2.4V
-
-
= 3V, V,N ~ VLC or VHC '
I OH ~ -32/J.A
10H ~ -250/J.A
Vec
V1N
VOL
0
MIN.
0
=
~
Min.
V1H or V1L
3V, V,N
-120
Vcc
VHC
Vcc
IOH
~
-15mA MIL.
2.4
4.0
IOH
=-24mA COM.
2.0
IOL
-
GND
VLe
-
GND
VLC
-
0.5
=V LC or VHe ,
0
300/J.A
10L ~ 300/J.A
Vce = Min.
V,N = V,H or V'L
-75
VHC
3.5
IOL
~
32mA MIL.
-
IOL
~
48mA COM.
-
-
0.5
-
200
-
-
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
5-195
10
/J. A
mA
V
V
mV
IDT54/74FCT861-64B
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
vLC = O.2V; VHC = vcc - O.2V
SYMBOL
PARAMETER
Icca
Quiescent Power Supply Current
ICCT
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
Y'N = 3.4v(3)
Dynamic Power Supply
Current
Vcc= Max.
Outputs Open
OE= GND
TiR" = GND or Vcc
One Input Toggling
50% Duty Cycle
ICCD
Icc
Total Power Supply!"
Current
TYP'(2)
MAlt
UNIT
-
0.001
1.5
rnA
-
0.5
1.6
rnA
V,N",VHC
Y,N::; VlC
-
0.15
0.25
V,N",VHC
V,N ::; VlC (FCT)
-
1.5
4.0
Y'N = 3.4V
V,N=GND
-
1.8
4.8
V,N'" VHC
V,N ::; VLC (FCT)
-
3.0
6.5
Y'N = 3.4V
Y'N = GND
-
5.0
12.9
TEST CONDITIONS(')
Vcc= Max.
V,N ", VHC V,N::; VlC
Ii = 0
Vcc = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE =GND
One Bit Toggling
Vec = Max.
Outputs Open
fi = 2.SMHz
50% Duty Cycle
OE=GND
Eight Bits Toggling
MIN.
mAl
MHz
rnA
NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applica"lle device type.
2. Typical values are at Vee = S.OV, +25°C ambient and maximum loading.
=3.4V): all other inputs at Vee or GND.
='aUIESCENT + 'INPUTS + 'DYNAMIC
3. Per TTL driven input (V IN
4.
Icc
Icc = 'CCQ + ICCTDHNT + 'cco (fcp/2 + fjNj)
'CCQ = Quiescent Current
leeT = Power Supply Current for a TTL High Input (V IN = 3.4V)
DH
=
Duty Cycle for TTL Inputs High
NT = NUmber of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni
=Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
COMMERCIAL
PARAMETERS
tplH
tpHl
tpLH
tpHL
tplH
t pHl
tplH
t pHL
tZH
tZl
tZH
tZl
t ZH (2)
tZl
tZH
tZl
DESCRIPTION
TEST CONDITIONS(')
MIN.
MAX.
MILITARY
MIN.
MAX.
UNITS
Propagation Delay from
Rito Tior Ti to Ri
IDTS4174FCT861 B/IDT54/74FCT863B
(Non-inverting)
C L = SOpF
Rl = soon
-
5.0
-
6.5
ns
C l = 300pF
Rl = soon
-
5.0
-
6.5
ns
Propagation Delay from
Rito Ti or Tito Ri
IDTS4174FCT862B/IDT54/74FCT863B
(Inverting)
C l = 50pF
Rl = 500n
-
5.5
-
6.5
ns
C l = 300pF
RL = soon
-
5.5
-
6.5
ns
C L = SOpF
Rl = soon
-
8.0
-
9.0
ns
C L = 300pF
Rl = 500n
-
8.0
-
9.0
ns
C l = 5pF
Rl = 500n
-
7.0
-
8.0
ns
C l = 50pF
RL = soon
-
7.0
-
8.0
ns
Output Enable Time OET to
Ti or OER to Ri
Output Enable Time OET to
Ti or OER to Ri
NOTE:
1. See test circuit and waveforms.
2. This parameter guaranteed but not tested.
5-196
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR THREE-STATE OUTPUTS
Vee
RL
TEST
SWITCH
III
IZl
AllOlher
Closed
Closed
Open
DEFINITIONS
RL = Load resislor: see AC CHARACTERSICS for value.
C l = Load capacitance includes jig and probe capacitance: see AC
CHARACTERISTICS for value.
RT = Termination should be equal to ZOUT of pulse generators.
RL
SSDAHCT645-004
PULSE WIDTH
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
.~JIIlIi-
3V
1.5V
OV
LOW·HIGH·lOW
PULSE
th
TIMING
INPUT
r-~trec
DATA
INPUT
J1IiJ
-
3V
1.SV
HIGH·LOW·HIGH
PULSE
~-
=f-~'.
tpw
OV
_ _ _ 1.5V
3V
SSDAHCT645-007
1.SV
OV
SSDAHCT64S-005
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
DISABLE
ENABLE
~---3V
CONTROL
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
-4PLH
4 LH
INPUT
' -_ _ _
-/-- - - - - - 1.5V
1_ _ _ _ _ OV
~I_--J_
OUTPUT
NORMALLY LOW
1.5V
OUTPUT
NORMALLY HIGH
1.5V
VOL
F_HL :
1..._ _ _ _ __
' ,_ _ _ _
OV
SSDAHCT645-008
SSDAHCT645-006
NOTES:
1. Diagram shown for Input Control Enable-LOW and Input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: tf ~ 2.5ns; tr ~ 2.5ns.
5-197
ORDER PART
NUMBER
IOT39C821P
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
12.0
P24-2
Com'1.
ORDER PART
NUMBER
IOT39C841P
SPEED
(ns)
PACKAGE
TYPE
OPER,
TEMP.
9.5
P24-2
Com'1.
IOT39C821J
J28
IOT39C841J
J28
IOT39C821D
024-2
IDT39C841D
024-2
IOT39C821L
L28-1
IOT39C841L
IOT39C821DB
024-2
IDT39C821 LB
L28-1
IOT39C822P
12.0
P24-2
IOT39C841DB
Mil.
L28-1
11.0
IOT39C841LB
IOT39C842P
Com'1.
024-2
9.5
P24-2
IOT39C822J
J28
IOT39C842J
J28
024-2
IOT39C8220
024-2
IOT39C8420
IOT39C822L
L28-1
IOT39C842L
IDT39C8220B
024-2
IOT39C822LB
L28-1
IOT39C823P
12.0
P24-2
IOT39C8420B
Mil.
IOT39C843P
024-2
9.5
P24-2
J28
IOT39C843J
J28
024-2
IOT39C8230
024-2
IOT39C8430
L28-1
IOT39C843L
IOT39C8230B
024-2
IOT39C823LB
L28-1
IOT39C824P
12.0
P24-2
IOT39C8440
024-2
IOT39C844L
IOT39C8240B
024-2
IOT39C824LB
L28-1
P24-2
IOT39C825J
J28
IOT39C8250
IOT39C825L
IOT39C8250B
024-2
IOT39C825LB
L28-1
12.0
P24-2
L28-1
IOT39C824L
IOT39C826P
9.5
024-2
IOT39C8240
12.0
IOT39C844P
IOT39C8440B
Mil.
IOT39C845P
024-2
9.5
P24-2
J28
024-2
IOT39C8450
024-2
L28-1
IOT39C845L
P24-2
IOT39C8450B
IOT39C846P
024-2
9.5
P24-2
J28
IOT39C846J
J28
IOT39C8260
024-2
IDT39C8460
024-2
IOT39C826L
L28-1
IDT39C846L
IOT39C8260B
024-2
IOT39C826LB
L28-1
IOT39C8460B
IDT39C846LB
5-198
Mil.
L28-1
IOT39C826J
Mil.
Com'1.
L28-1
11.0
IOT39C845LB
Com'l.
Mil.
L28-1
IDT39C845J
Mil.
Com'1.
L28-1
11.0
IOT39C844LB
Com'1.
Mil.
L28-1
IOT39C843LB
Com'1.
024-2
J28
J28
Com'1.
L28-1
11.0
IOT39C844J
IOT39C824J
IOT39C825P
IOT39C8430B
Mil.
Mil.
L28-1
IOT39C823J
IOT39C823L
Com'1.
L28-1
11.0
IOT39C842LB
Com'1.
Mil.
L28-1
Com'1.
L28-1
11.0
024-2
L28-1
Mil.
ORDER PART
NUMBER
IDT39C861P
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
8.0
P24-2
Com'l.
ORDER PART
NUMBER
IDT54AHCTI91DB
SPEED
(ns)
22.0
PACKAGE
TYPE
OPER.
TEMP.
D16
Mil.
IDT39C861J
J28
I DT54AHCTI91 LB
L2D-2
IDT39C861D
D24-2
I DT54AHCTI91 EB
E20
IDT39C861L
L28-1
IDT39C861DB
10.0
IDT39C861LB
IDT39C862P
D24-2
Mil.
I DT54AHCTI93DB
L28-1
8.0
P24-2
19.0
D16
I DT54AHCTI93LB
L2D-2
I DT54AHCTI93EB
E20
Com'l.
IDT39C862J
J28
IDT54AHCT240DB
IDT39C862D
D24-2
IDT54AHCT240LB
L2D-2
IDT54AHCT240EB
E20
IDT39C862L
IDT39C862DB
L28-1
10.0
I DT39C862LB
IDT39C863P
D24-2
P24-2
IDT39C863J
J28
IDT39C863D
D24-2
IDT54AHCT244DB
Com'l.
10.0
IDT39C863LB
D24-2
Mil.
8.0
P24-2
J28
IDT39C864D
D24-2
IDT39C864L
L28-1
10.0
IDT39C864LB
D24-2
27.0
D16
L2D-2
IDT54AHCT138EB
E20
25.0
D16
IDT54AHCTI39LB
L2D-2
IDT54AHCTI39EB
E20
I DT54AHCTI61DB
20.0
D16
IDT54AHCTI61LB
L2D-2
IDT54AHCT161EB
E20
IDT54AHCTI63DB
20.0
D16
IDT54AHCTI63LB
L20-2
I DT54AHCTI63EB
E20
IDT54AHCTI82DB
D20
IDT54AHCT244EB
E20
15.0
020
IOT54AHCT245LB
L2D-2
IDT54AHCT245EB
E20
Mil.
15.0
D20
IDT54AHCTI82LB
L2D-2
IDT54AHCTI82EB
E20
IDT54AHCT273EB
E20
IDT54AHCT299EB
E20
5-199
020
L2D-2
IOT54AHCT373EB
E20
18.0
D20
IDT54AHCT374LB
L2D-2
IDT54AHCT374EB
E20
18.0
D20
I DT54AHCT377LB
L2D-2
IDT54AHCT377EB
E20
18.0
D20
IDT54AHCT521 LB
L20-2
I DT54AHCT521 EB
E20
IDT54AHCT533DB
Mil.
19.0
IDT54AHCT373LB
IDT54AHCT521DB
Mil.
D20
L2D-2
I DT54AHCT377DB
Mil.
20.0
IOT54AHCT299LB
IDT54AHCT374DB
Mil.
020
L2D-2
IDT54AHCT373DB
Mil.
17.0
I DT54AHCT273LB
IDT54AHCT299DB
Consult Factory
IDT54AHCT138LB
IDT54AHCTI39DB
Com'l.
L28-1
IDT49C818
IDT54AHCT138DB
Mil.
Mil.
Mil.
L28-1
IDT39C864J
IDT39C864DB
13.0
L2D-2
IOT54AHCT273DB
IDT39C864P
D20
IDT54AHCT244LB
IDT54AHCT245DB
L28-1
IDT39C863L
IDT39C863DB
12.0
Mil.
L28-1
8.0
Mil.
24.0
D20
IDT54AHCT533LB
L2D-2
I DT54AHCT533EB
E20
Mil.
Mil.
Mil.
Mil.
Mil.
Mil.
Mil.
I
ORDER PART
NUMBER
IOT54AHCT5340B
SPEED
(ns)
18.0
PACKAGE
TYPE
OPER.
TEMP.
020
Mil.
IOT54AHCT534LB
L2o-2
IOT54AHCT534EB
E20
ORDER PART
NUMBER
10T54FCTl82AOB
15.0
020
IOT54AHCT573LB
L2o-2
IOT54AHCT573EB
E20
Mil.
15.0
020
IOT54AHCT574LB
L2o-2
IOT54AHCT574EB
E20
IOT54AHCT6400B
14.0
020
IOT54AHCT640LB
L20-2
IOT54AHCT640EB
E20
Mil.
15.0
020
Mil.
020
L2o-2
10T54FCTl82EB
E20
10.5
IOT54FCT191DB
016
E20
16.0
016
IOT54FCT191LB
L2o-2
IOT54FCT191EB
E20
10T54FCT193AOB
6.9
016
10T54FCTl93AEB
E20
10.5
L2o-2
IOT54FCTl930B
IOT54AHCT645EB
E20
10T54FCT193LB
L2o-2
IOT54FCT193EB
E20
7.8
016
L2o-2
IOT54FCT240AOB
IOT54FCT138AEB
E20
IOT54FCT240ALB
12.0
016
Mil.
IOT54FCT138ALB
IOT54FCT1380B
5.1
020
016
IOT54FCT240AEB
L2o-2
IDT54FCT2400B
IOT54FCT138EB
E20
IOT54FCT240LB
L2o-2
IOT54FCT240EB
E20
7.8
016
L2o-2
IDT54FCT244AOB
IOT54FCT139AEB
E20
IOT54FCT244ALB
12.0
E20
9.0
020
Mil.
IOT54FCT139ALB
IOT54FCT1390B
4.6
020
016
IDT54FCT244AEB
L2o-2
IDT54FCT2440B
IOT54FCT139EB
E20
IOT54FCT244LB
L2o-2
IOT54FCT244EB
E20
7.5
016
L2o-2
IOT54FCT245AOB
IOT54FCT161AEB
E20
IOT54FCT245ALB
016
IOT54FCT245AEB
IOT54FCT161LB
L2o-2
IOT54FCT2450B
IOT54FCT161EB
E20
IOT54FCT163AOB
11.5
7.5
016
020
4.9
020
E20
7.5
020
IOT54FCT245LB
L20-2
E20
Mil.
L20-2
IOT54FCT273AOB
IOT54FCTl63AEB
E20
IDT54FCT273ALB
8.3
020
L2o-2
016
IOT54FCT273AEB
IOT54FCTl63LB
L20-2
IOT54FCT2730B
10T54FCTl63EB
E20
IOT54FCT273LB
L2o-2
IOT54FCT273EB
E20
11.5
Mil.
L2o-2
IOT54FCT245EB
IOT54FCTl63ALB
IOT54FCT1630B
E20
7.0
Mil.
IOT54FCT161ALB
IOT54FCT161DB
Mil.
L2o-2
IOT54FCT139LB
IDT54FCT161 AOB
Mil.
L20-2
IOT54FCT138LB
IOT54FCT139AOB
Mil.
L2o-2
IOT54AHCT645LB
IOT54FCT138AOB
Mil.
L2o-2
IOT54FCT191AEB
Mil.
020
10T54FCTl82LB
IOT54FCT193ALB
IOT54AHCT6450B
OPER.
TEMP.
E20
11.5
IDT54FCT191ALB
Mil.
PACKAGE
TYPE
L2o-2
IDT54FCT182AEB
IOT54FCT191AOB
IOT54AHCT5740B
-
10T54FCT182ALB
IDT54FCTl820B
IOT54AHCT5730B
SPEED
(ns)
5-200
E20
15.0
020
Mil.
ORDER PART
NUMBER
IDT54FCT299ADB
SPEED
(ns)
9.5
IDT54FCT299ALB
IDT54FCT299AEB
PACKAGE
TYPE
OPER.
TEMP.
D20
Mil.
ORDER PART
NUMBER
IDT54FCT573ADB
L2D-2
I DT54FCT573ALB
SPEED
(ns)
5.6
PACKAGE
TYPE
OPER.
TEMP.
D20
Mil.
L2D-2
E20
IDT54FCT573AEB
D20
IDT54FCT573DB
IDT54FCT299LB
L2D-2
IDT54FCT573LB
L2D-2
IDT54FCT299EB
E20
IDT54FCT573EB
E20
IDT54FCT299DB
IDT54FCT373ADB
16.0
5.6
IDT54FCT373ALB
I DT54FCT373AEB
D20
Mil.
IDT54FCT574ADB
L2D-2
IDT54FCT574ALB
E20
8.5
7.2
D20
D20
E20
IDT54FCT574AEB
D20
IDT54FCT574DB
I DT54FCT373LB
L2D-2
IDT54FCT574LB
L2D-2
IDT54FCT373EB
E20
IDT54FCT574EB
E20
IDT54FCT373DB
I DT54FCT37 4ADB
8.5
7.2
I DT54FCT374ALB
IDT54FCT374AEB
D20
Mil.
IDT54FCT640ADB
L2D-2
IDT54FCT640ALB
E20
11.0
5.3
D20
D20
E20
I DT54FCT640AEB
IDT54FCT640DB
IDT54FCT374LB
L2D-2
I DT54FCT640LB
L2D-2
IDT54FCT374EB
E20
IDT54FCT640EB
E20
I DT54FCT377 ADB
11.0
8.3
IDT54FCT377 ALB
D20
IDT54FCT645ADB
Mil.
IDT54FCT377AEB
E20
8.0
4.9
I DT54FCT645ALB
L2D-2
D20
D20
E20
IDT54FCT645AEB
IDT54FCT645DB
I DT54FCT377LB
L20-2
IDT54FCT645LB
L2D-2
I DT54FCT377EB
E20
IDT54FCT645EB
E20
IDT54FCT521ADB
15.0
9.5
IDT54FCT521ALB
IDT54FCT521AEB
IDT54FCT521DB
D20
IDT54FCT821BDB
Mil.
L2D-2
8.5
IDT54FCT822BDB
L2D-2
IDT54FCT822BLB
IDT54FCT521EB
E20
15.0
IDT54FCT823BDB
5.6
I DT54FCT533ALB
D20
12.0
Mil.
L28-1
8.5
D24-2
Mil.
L28-1
8.5
IDT54FCT823BLB
Mil.
E20
IDT54FCT824BDB
D20
IDT54FCT824BLB
IDT54FCT533LB
L2D-2
IDT54FCT533EB
E20
D24-2
Mil.
L28-1
IDT54FCT825BDB
8.5
7.2
D20
Mil.
8.5
D24-2
Mil.
L28-1
Mil.
IDT54FCT534ALB
L2D-2
IDT54FCT826BDB
IDT54FCT534AEB
E20
IDT54FCT826BLB
11.0
D24-2
L28-1
IDT54FCT825BLB
IDT54FCT534DB
D24-2
L2D-2
IDT54FCT533AEB
IDT54FCT534ADB
D20
E20
IDT54FCT521 LB
I DT54FCT533DB
E20
11.0
IDT54FCT821 BLB
D20
I DT54FCT533ADB
Mil.
L2D-2
D20
IDT54FCT377DB
Mil.
L2D-2
D20
IDT54FCT374DB
Mil.
L2D-2
8.5
D24-2
Mil.
L28-1
D20
IDT54FCT534LB
L2D-2
IDT54FCT641 BDB
IDT54FCT534EB
E20
IDT54FCT841 BLB
5-201
7.5
D24-2
L28-1
Mil.
ORDER PART
NUMBER
IDT54FCT842BDB
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
7.5
D24-2
Mil.
ORDER PART
NUMBER
--
IOTl4AHCT163P
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
17.0
Consult
Factory
Com'l.
L28-1
IDT54FCT842BLB
IDT74AHCT163S0
IDT54FCT843BDB
7.5
IOT54FCT843BLB
IOT54FCT344BOB
7.5
024-2
Mil.
7.5
IOT54FCT845BLB
024-2
Mil.
L28-1
7.5
IOT54FCT846BLB
024-2
Consult
Factory
IDTl4AHCT1630
D16
IOTl4AHCT163L
L20-2
IOT74AHCT182P
L28-1
IDT54FCT844BLB
IOT54FCT846BOB
Mil.
L28-1
1---'
IOT54FCT845BOB
D24-2
12.0
J20
IOTl4AHCT182S0
S20
IOTl4AHCT1820
020
I OTl 4AHCT182L
L20-2
Mil.
I OT7 4AHCT191 P
L28-1
18.0
6.5
IOT54FCT861 BLB
IDT54FCT862BOB
6.5
024-2
6.5
024-2
6.5
D24-2
IOT74AHCTI91D
016
IOT74AHCT191L
L20-2
I OTl 4AHCT193P
16.0
IOTl4AHCT1930
016
IDT74AHCT193L
L20-2
22.0
Consult
Factory
I OT74AHCT240P
Com'l.
Consult
Factory
I DTl 4AHCT138S0
IOTl4AHCT1380
D16
IOTl4AHCT138L
L20-2
9.0
I OTl 4AHCT240S0
S20
IDT74AHCT2400
D20
IDT74AHCT240L
L20-2
I OTl 4AHCT244P
10.0
Consult
Factory
Com'l.
P20
D20
L20-2
IDTl4AHCT1390
D16
IOT74AHCT245P
IOTl4AHCT139L
L20-2
IDTl4AHCT245J
IOT74AHCT245S0
S20
IOT74AHCT16l P
Consult
Factory
IOT74AHCT245D
020
IOT74AHCT245L
L20-2
IOTl4AHCT16lSO
17.0
Com'l.
Com'l.
S20
I DTl 4AHCT2440
f--I OT74AHCT244L
Consult
Factory
IOTl4AHCT139S0
Com'l.
J20
I OT74AHCT244S0
20.0
P20
J20
I OTl 4AHCT244J
I OTl 4AHCT139P
Com'l.
Mil.
L28-1
I DTl 4AHCT240J
IDT74AHCT138P
Consult
Factory
Consult
Factory
I OTl 4AHCT193S0
Mil.
L28-1
IOT54FCT864BLB
Com'l.
Mil.
L28-1
IOT54FCT863BLB
IDT54FCT864BDB
Mil.
L28-1
IOT54FCT862BLB
IDT54FCT863BOB
024-2
Consult
Factory
Com'l.
Consult
Factory
IOT74AHCT191S0
IOT54FCT861 BOB
P20
IOTl4AHCT182J
10.0
P20
Com'l.
J20
Consult
Factory
IDTl4AHCTI61D
016
IDTl4AHCT161L
L20-2
I DT74AHCT273P
I OTl4AHCT273J
5-202
15.0
P20
J20
IDTl4AHCT273S0
S20
IDT74AHCT273D
020
I DTl4AHCT273L
L20-2
Com'l.
ORDER PART
NUMBER
10T74AHCT299P
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
14.0
P20
Com'l.
10T74AHCT299J
ORDER PART
NUMBER
10T74AHCT640P
J20
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
11.0
P20
Com'l.
10T74AHCT64OJ
J20
S20
10T74AHCT299S0
820
IOT74AHCT640S0
10T74AHCT2990
020
1DT74AHCT6400
020
10T74AHCT299L
L20-2
10T74AHCT640L
L2D-2
10T74AHCT373P
16.0
P20
Com'l.
10T74AHCT645P
10.0
P20
IOT74AHCT373J
J20
10T74AHCT645J
J20
S20
IOT74AHCT373S0
S20
1DT74AHCT645S0
10T74AHCT3730
020
10T74AHCT6450
020
10T74AHCT373L
L2D-2
IOT74AHCT645L
L20-2
10T74AHCT374P
16.0
P20
10T74AHCT374J
J20
10T74AHCT374S0
S20
10T74AHCT3740
020
10T74AHCT374L
L2D-2
10T74AHCT521P
16.0
P20
I 0T74AHCT521 J
J20
I 0T74AHCT521 SO
820
10T74AHCT521D
020
10T74AHCT521L
L20-2
10T74AHCT533P
14.0
P20
Com'l.
10T74FCT138AP
5.8
10T74FCT138AO
016
10T74FCT138AL
L2D-2
10T74FCT138P
9.0
Consult
Factory
Consult
Factory
IOT74FCT138S0
1DT74FCT1380
016
IOT74FCT138L
L2D-2
IOT74FCT139AP
Com'l.
5.9
Consult
Factory
IOT74AHCT533J
J20
10T74AHCT533S0
S20
IOT74AHCT5330
020
10T74FCT139AO
016
IOT74AHCT533L
L2D-2
10T74FCT139AL
L20-2
19.0
P20
I 0T74AHCT534J
J20
IOT74AHCT534S0
820
10T74AHCT5340
020
10T74AHCT534L
L2D-2
10T74AHCT573P
14.0
P20
10T74AHCT573J
J20
IOT74AHCT573S0
S20
1DT74AHCT5730
020
IOT74AHCT573L
L2D-2
10T74FCT1390
016
IOT74FCT139L
L2D-2
IOT74FCT161AP
14.0
P20
7.2
Consult
Factory
Consult
Factory
IOT74FCT161ASO
IOT74FCT161AO
016
10T74FCT161AL
L2D-2
Com'l.
IOT74FCT161S0
11.0
Consult
Factory
Consult
Factory
10T74AHCT574J
J20
10T74AHCT574S0
S20
IOT74FCT161D
016
10T74AHCT5740
020
IOT74FCT161L
L2D-2
10T74AHCT574L
L2D-2
5-203
I
Consult
Factory
Consult
Factory
10T74FCT139S0
10T74FCT161P
IOT74AHCT574P
9.0
Com'l.
Com'l.
Com'l.
Consult
Factory
10T74FCT139ASO
10T74FCT139P
10T74AHCT534P
Com'l.
Consult
Factory
10T74FCT138ASO
Com'l.
Consult
Factory
Com'!.
Com'l.
ORDER PART
NUMBER
IDT74FCT161P
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
11.0
Consult
Factory
Com'l.
ORDER PART
NUMBER
IDT74FCT193P
Consult
Factory
IDT74FCT16180
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
10.0
Consult
Factory
Com'l
Consult
Factory
IDT74FCT19380
IDT74FCT161D
D16
IDT74FCT193D
D16
IDT74FCT161L
L20-2
IDT74FCT193L
L20-2
IDT74FCT163AP
7.2
Consult
Factory
IDT74FCT163AD
D16
IDT74FCT163AL
L20-2
11.0
IDT74FCT163D
D16
IDT74FCT163L
L20-2
820
IDT74FCT240AD
D20
-
P20
IDT74FCT182AJ
J20
IDT74FCT182A80
820
IDT74FCT182AD
D20
IDT74FCT182AL
L20-2
IDT74FCT182P
9.0
IDT74FCT182J
Com'l.
J20
820
IDT74FCT240D
D20
IDT74FCT240L
L20-2
820
IDT74FCT182D
D20
IDT74FCT182L
L20-2
7.8
Consult
Factory
820
D20
L20-2
6.5
P20
IDT74FCT244J
J20
IDT74FCT24480
820
IDT74FCT244D
D20
IDT74FCT244L
L20-2
4.6
IDT74FCT245AJ
Consult
Factory
IDT74FCT191A80
P20
IDT74FCT245A80
820
IDT74FCT245AD
D20
IDT74FCT191AD
D16
L20-2
IDT74FCT245P
Consult
Factory
IDT74FCT245J
J20
IDT74FCT24580
820
12.0
IDT74FCT245AL
Consult
Factory
IDT74FCT19180
IDT74FCT191D
D16
IDT74FCT191L
L20-2
IDT74FCT193AP
IDT74FCT193A80
6.5
Consult
Factory
Com'l.
D16
IDT74FCT193AL
L20-2
D20
L20-2
7.2
P20
J20
IDT74FCT273A80
820
IDT74FCT273AD
D20
IDT74FCT273AL
IDT74FCT273P
5-204
P20
IDT74FCT245L
IDT74FCT273AJ
Consult
Factory
IDT74FCT193AD
L20-2
7.0
IDT74FCT245D
IDT74FCT273AP
Com'l.
J20
IDT74FCT191AL
IDT74FCT191P
Com'l.
J20
IDT74FCT244AL
Com'l.
P20
IDT74FCT244AD
IDT74FCT245AP
IDT74FCT191AP
4.3
IDT74FCT244A80
IDT74FCT244P
J20
P20
IDT74FCT24OS0
IDT74FCT244AJ
P20
IDT74FCT182S0
L20-2
8.0
IDT74FCT24OJ
IDT74FCT244AP
IDT74FCT182AP
Com'l.
J20
IDT74FCT240AL
Consult
Factory
P20
IDT74FCT240ASO
IDT74FCT240P
Consult
Factory
IDT74FCT16380
4.8
IDT74FCT240AJ
Consult
Factory
IDT74FCT163A80
IDT74FCT163P
IDT74FCT240AP
Com'l.
L20-2
13.0
P20
IDT74FCT273J
J20
IDT74FCT27380
820
IDT74FCT273D
D20
IDT74FCT273L
L20-2
Com'l.
ORDER PART
NUMBER
IDT74FCT299AP
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
7.2
P20
Com'l.
IDT74FCT299AJ
ORDER PART
NUMBER
IDT74FCT521P
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
11.0
P20
Com'l
J20
IDT74FCT521J
IDT74FCT299ASO
S20
IDT74FCT521S0
S20
IDT74FCT299AD
D20
IDT74FCT521D
D20
L2D-2
1DT74FCT521L
L2D-2
IDT74FCT299AL
IDT74FCT299P
10.0
J20
P20
IDT74FCT299J
J20
IDT74FCT533AP
IDT74FCT299S0
S20
IDT74FCT533AJ
J20
IDT74FCT533ASO
S20
IDT74FCT299D
D20
IDT74FCT299L
L2D-2
IDT74FCT373AP
5.2
P20
P20
1DT74FCT533AD
D20
IDT74FCT533AL
L2D-2
IDT74FCT533P
Com'l.
5.2
10.0
P20
IDT74FCT373AJ
J20
IDT74FCT533J
J20
IDT74FCT373ASO
S20
IDT74FCT533S0
S20
IDT74FCT373AD
D20
IDT74FCT533D
D20
IDT74FCT373AL
L20-2
IDT74FCT533L
L2D-2
IDT74FCT373P
8.0
P20
IDT74FCT373J
J20
IDT74FCT534AP
IDT74FCT373S0
S20
IDT74FCT534AJ
IDT74FCT373D
D20
IDT74FCT373L
L2D-2
6.5
6.5
P20
IDT74FCT534ASO
S20
IDT74FCT534AD
D20
IDT74FCT534P
Com'l.
P20
L2D-2
10.0
P20
IDT74FCT374AJ
J20
IDT74FCT534J
J20
IDT74FCT374ASO
S20
IDT74FCT534S0
S20
IDT74FCT374AD
D20
IDT74FCT534D
D20
IDT74FCT374AL
L2D-2
IDT74FCT534L
L2D-2
IDT74FCT374P
10.0
P20
P20
IDT74FCT374J
J20
IDT74FCT573AP
IDT74FCT374S0
S20
IDT74FCT573AJ
J20
IDT74FCT374D
D20
IDT74FCT573ASO
S20
IDT74FCT374L
L2D-2
IDT74FCT377AP
7.2
P20
IDT74FCT573AD
D20
1DT74FCT573AL
L2D-2
IDT74FCT573P
Com'l.
5.2
8.0
J20
1DT74FCT573J
J20
IDT74FCT377ASO
S20
IDT74FCT573S0
S20
1DT74FCT377AD
D20
IDT74FCT573D
D20
IDT74FCT377AL
L2D-2
1DT74FCT573L
L2D-2
13.0
P20
IDT74FCT377J
J20
IDT74FCT574AP
IDT74FCT377S0
S20
IDT74FCT574AJ
IDT74FCT377D
D20
1DT74FCT377L
L2D-2
6.5
7.2
P20
IDT74FCT574ASO
S20
IDT74FCT574AD
D20
IDT74FCT574P
Com'l.
P20
J20
IDT74FCT574AL
IDT74FCT521AP
Com'l.
P20
IDT74FCT377AJ
IDT74FCT377P
Com'l.
J20
IDT74FCT534AL
IDT74FCT374AP
Com'l.
L2D-2
10.0
P20
IDT74FCT521AJ
J20
IDT74FCT574J
J20
IDT74FCT521ASO
S20
IDT74FCT574S0
S20
IDT74FCT521AD
D20
IDT74FCT574D
D20
IDT74FCT521AL
L2D-2
IDT74FCT574L
L2D-2
5-205
Com' I.
II
ORDER PART
NUMBER
10T74FCT640AP
SPEED
(ns)
5.0
PACKAGE
TYPE
OPER.
TEMP.
P20
Com'l.
10T74FCT640AJ
J20
ORDER PART
NUMBER
IOT74FCT826BP
SPEED
(n8)
PACKAGE
TYPE
OPER.
TEMP.
7.5
P24-2
Com'l.
IOT74FCT826BJ
J28
10T74FCT640ASO
S20
10T74FCT826BO
024-2
10T74FCT640AO
020
IOT74FCT826BL
L28-1
IOT74FCT640AL
L20-2
IOT74FCT640P
P20
1DT74FCT841BP
IDT74FCT64OJ
7.0
J20
IOT74FCT841 BJ
J28
IOT74FCT640S0
S20
IOT74FCT841 BO
024-2
IOT74FCT6400
020
IOT74FCT841 BL
L28-1
IOT74FCT64OL
L20-2
10T74FCT842BP
IOT74FCT645AP
4.6
P20
Com'l.
6.5
6.5
P24-2
P24-2
I DT74FCT842BJ
J28
10T74FCT645AJ
J20
IDT74FCT842BD
D24-2
10T74FCT645ASO
S20
IDT74FCT842BL
L28-1
10T74FCT645AO
020
IOT74FCT645AL
L20-2
IDT74FCT843BP
P20
IOT74FCT843BJ
J28
IDT74FCT645J
J20
IDT74FCT843BD
D24-2
IOT74FCT645S0
S20
IDT74FCT843BL
L28-1
IOT74FCT6450
020
IDT74FCT645L
L20-2
IOT74FCT645P
IOT74FCT821BP
9.5
7.5
P24-2
IOT74FCT821BJ
J28
IOT74FCT821BO
024-2
IOT74FCT821BL
L28-1
IOT74FCT822BP
7.5
P24-2
10T74FCT822BJ
J28
IOT74FCT822BO
024-2
IOT74FCT822BL
L28-1
10T74FCT823BP
7.5
P24-2
10T74FCT823BJ
J28
10T74FCT823BO
024-2
10T74FCT823BL
L28-1
IOT74FCT824BP
7.5
P24-2
IOT74FCT824BJ
J28
IOT74FCT824BO
024-2
IOT74FCT824BL
L28-1
IOT74FCT825BP
7.5
P24-2
10T74FCT825BJ
J28
10T74FCT825BO
024-2
IOT74FCT825BL
L28-1
IDT74FCT844BP
Com'l.
IDT74FCT844BD
024-2
IDT74FCT844BL
L28-1
IDT74FCT845BD
D24-2
IDT74FCT845BL
L28-1
6.5
P24-2
IDT74FCT846BJ
J28
IOT74FCT846BD
D24-2
IDT74FCT846BL
L28-1
5.0
P24-2
I DT74FCT861BJ
J28
IDT74FCT861BD
D24-2
I DT74FCT861BL
L28-1
5.0
P24-2
IDT74FCT862BJ
J28
IDT74FCT862BD
D24-2
IDT74FCT862BL
L28-1
IDT74FCT863BP
5-206
P24-2
J28
IDT74FCT862BP
Com'l.
6.5
I DT74FCT845BJ
IDT74FCT861BP
Com'l.
P24-2
J28
IDT74FCT846BP
Com'l.
6.5
P24-2
IDT74FCT844BJ
I DT74FCT845BP
Com'l.
6.5
5.0
P24-2
IDT74FCT863BJ
J28
IDT74FCT863BD
024-2
IDT74FCT863BL
L28-1
Com'l.
Com'l.
Com'l.
Com'l.
Com'l.
Com'l.
Com'l.
Com'l.
Com'l.
ORDER PART
NUMBER
IDT74FCT864BP
--
SPEED
(ns)
PACKAGE
TYPE
OPER.
TEMP.
5.0
P24-2
Com'l.
IDT74FCT864BJ
J28
IDT74FCT864BD
D24-2
IDT74FCT864BL
L28-1
II
5-207
Integrated
Device
Technology
Data Conversion
DATA CONVERSION PRODUCT
TABLE OF CONTENTS
CONTENTS
Data Conversion
PAGE
IDT75C18/28
8-Bit 125MHz Video DAC .......•..........•..............•.................•. 6-1
Ordering Information ....•..•........•............................................................... 6-3
FEATURES:
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The IDT75C18/28 are 70/1001125 MegaSample per Second
(MSPS), 8-bit Digital to Analog Converters, capable of directly
driving a 75(1 load to standard video levels. Most applications
require no extra registering, buffering or deglitching. Four
special level controls simplify the interface for video applicationS. The IDT75C18 has ECl-compatible inputs while the
IDT75C28 is TTL-compatible.
The IDT75C18/28 are built using IDT's high-performance
CEMOS·· process. On chip data registers and precise matching
of propagation delays, as well as an improved segmentingl
decoding architecture, significantly reduce glitch energy. The
IDT75C18/28 offer high-performance and ultra-low-power
in a 24-pin hermetic DIP, 24-pin plastic DIP or 28-pin lCC.
The IDT75C18 is pin and functionally compatible with the
TRW TDC1018, with the advantage of low power due to CMOS
processing. Besides providing higher reliability by running
cooler, power supply requirements are reduced. Another
advantage of the lower power dissipation is that this part may
be packaged in a space-saving, cost-effective, 0.3 inch plastic
package.
The IDT75C18/28 Military DACs are 100% processed in compliance to the test methods of Mll-STD-883, Method 5004,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.
Graphics-ready
Pin-compatible with TRW TDC1018
8 bits, 112 lSB linearity
70, 100, 125MHz models available
ECl-compatible inputs - IDT75C18
TTL-compatible inputs - 1DT75C28
Ultra-low power dissipation < 400mW
Power supply noise rejection> 50dB
Registered data and video controls
Differential current outputs
Flexible video controls
Inherently low glitch energy
Multiplying mode capability
Single 5V power supply
Available in 24-pin hermetic DIP, 24-pin plastic DIP and
28-pin lCC
• Military product is 100% screened to Mll-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
Dl-D8-~~\I
OUT+
-rr-""1/I CONTROL
FH, BLANK
LOGIC
BRT, SYNC -....,..,,-,/1
......__...
OUT-
CON~~~============~
CONY
2
FT--r-----------------~
REF+ REFSSD75C18-OO1
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
JULY 1986
Printed in U.S.A.
1986 Integrated Device Technology, Inc.
6-1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT15C18/28 8-BIT CMOS 125MHz YIDEO DAC
PIN CONFIGURATIONS
a..
t-' liPi
~ U ilI::J!; ..
0
D4
Ds
D.
D3
D7
D.
De
D1
YEEA
YEED
CONY
Q
LJ LJ
D.
FT
REP
REF-
BLANK
! ! ~~
LJ
c U
IIII
LJ LJ
V
26,..-
NC
2SL.-
1
24[: REF'
D4
:J7
23[: REF-
Ds
D,
:J8
22[: SYNC
De
--,11
--' 12
21[: BRT
20C: BLANK
13 14 15
19,..16 17 18'--
II
II
FH
r' ,., r, r, r, ,., r,
II
U
SYNC
BRT
3
t2J
:J9
D7 :J10
AGNO
COMP
YGND
FH
::J;
D3 :J6
OUT'
OUT-
CONY
Z :0:'0 0
II II
Z
,,11
II
III ~ I~ t:
:0:'00
UU
It
DU
~z
Q
SSD75C18-003
SSD75C1&-OO2
LCC
TOPYIEW
DIP
TOPYIEW
6-2
ORDER PART
NUMBER
I
SPEED
(ns)
Icc (MAX.)
(rnA)
PACKAGE
TYPE
IDT75C18
I
Consult Factory
IDT75C28
I
Consult Factory
OPER.
TEMP.
6-3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Integrated
Device
Technology
Subsystems Modules
SUBSYSTEMS MODULES
TABLE OF CONTENTS
PAGE
CONTENTS
Subsystems Modules
IDT7MP624
IDT7M134/135
IDT7M136/137
IDT7M144/145
IDT7M203/204
I DT7M205/206
IDT7M624
IDT7M656
IDT7MS121912
IDT7MS24
IDT7MS56
IDT7MS64/SM864
IDTSMP624/612
IDTSMP656/62S
IDTSMPS24
IDTSM624/612
IDTSM656/62S
IDTSMS24
IDTSMS56
Ordering Information
1 Megabit (64Kx16, 12SKxS or 256Kx4) Plastic Static RAM Module ............... .
64K (SKxS) & 12SK (16KxS) Dual-Port RAM Module .•...•..••••....•.••••...••..
12SK (16KxS) & 256K (32KxS) Dual-Port RAM Module •.•••..•.•...•..•••....••••
64K (SKxS) & 12SK (16KxS) Slave Dual-Port RAM Module ••.••.•....•••••....•.••
2Kx9 & 4Kx9 Parallel In-Out FIFO .................••••...••.....••••......•••.
SKx9 & 16Kx9 Parallel In-Out FIFO ................••••...•......•••••.....••..
1 Megabit (64Kx16, 12SKxS or 256Kx4) Static RAM Module ..........••...........
256K (16Kx16, 32KxS or 64Kx4) Static RAM Module ............................ .
512K (64KxS or 64Kx9) Static RAM Module .........••.•...••.•...•..•......••.•
1 Megabit (12SKxS) Static RAM Module ............••.•.•.••.....••••......••••
256K (32Kx8) Static RAM Module ..................••...........••••......•.••
64K (SKxS) Static RAM Module .•..................................••..........
512K (32Kx16) Plastic Static RAM Module ..................................... .
256K (16Kx16) & 12SK (8Kx16) Plastic Static RAM Module ...•..•.................
1 Megabit (12SKxS) Plastic Static RAM Module ......•.......•....•••.........•..
1 Megabit (64Kx16) & 512K (32Kx16) Static RAM Module ..•.••.....••.........•.•
256K (16Kx16) & 12SK (SKx16) Static RAM Module .........•....................
1 Megabit (12SKxS) Static RAM Module ............•.•••..•.•..............••..
256K (32KxS) Static RAM Module .................••..••.••.•...••••......•...
7-1
7-3
7-13
7-15
7-1S
7-2S
7-29
7-35
7-41
7-46
7-49
7-55
7-60
7-62
7-64
7-66
7-6S
7-75
7-77
7-83
FEATURES:
DESCRIPTION:
• High-density 1024K-bit CMOS static RAM module
The IDT7MP624 is a 1024K-bit high-speed CMOS static RAM
constructed on an epoxy laminate substrate using 16 IDT7187
(64K x 1) static RAMs in plastic surface mount packages. Making
four chip select lines available (one for each group of 4 RAMs)
allows the user to configure the memory into a 64K x 16, 128K x 8
or 256K x 4 organization. In addition, extremely high speeds are
achievable by the use of IDT7187s fabricated in lOT's highperformance, high-reliability technology, CEMOS. This state-ofthe-art technology, combined with innovative circuit design
techniques, provides the fastest 64K static RAMs available.
The IDT7MP624 is available with access times as fast as 30ns
commercial temperature range, with maximum operating power
consumption of only 10.5W (significantly less if organized 128K x
8 or 256K x 4). The module also offers a standby power mode of
4.4W (max.) and a full standby mode of 1.7W (max.).
The IDT7MP624 is offered in a high-density 4D-pin, 900 mil
center plastic 01 P to take full advantage of the compact IDT7187s
in plastic surface mount packages.
All inputs and outputs of the IDT7MP624 are TTL-compatible
and operate from a single 5V supply. (NOTE: Both GND pins need
to be grounded for proper operation.) Fully asynchronous circuitry is used requiring no clocks or refreshing for operation, and
provides equal access times for ease of use.
• Customer-configured to 64K x 16, 128K x 8 or 256K x 4
• Fast access times
-30ns (max.) over commercial temperature range
• Low-power consumption
-Active: 4.8W (typ. in 64K x 16 organization)
-Standby: 1.6mW (typ.)
• Utilizes 16 IDT7187 high-performance 64K x 1 CMOS static
RAMs produced with lOT's advanced CEMOS'· technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Offered in 4D-pin, 900 mil center plastic DIP, achieving very
high memory density
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
FUNCTIONAL BLOCK DIAGRAM
AaA~--~----~--------~--------~--------,
C"S'2.'5
------,..,r-t------.....+-I-----~++_-----,
CEMOS is a trademark of Integrated Device Technology, Inc.
JULY 1986
COMMERCIAL TEMPERATURE RANGE
@1986 Integrated Device Technology, Inc.
7-1
Printed in U.S.A.
COMMERCIAL TEMPERATURE RANGE
IDT7MP624S 1 MEGABIT CMOS STATIC RAM PLASTIC MODULE
PIN CONFIGURATION
(I)GND
0,.
CS('2-'5)
PIN NAMES
Ao - A,S
Vee
ADDRESSES
Do - D,s
DATA INPUT/OUTPUT
CSxx
CHIP SELECTS
WE
WRITE ENABLE
A,
D.
A.
A,.
Vee
POWER
0,.
0,.
GND
GROUND
A.
A,.
D.
WE
0"
CS(B-")
05
0,
A.
A.
A"
A,.
D.
A.
D.
A.
A7
D.
0,.
As
0,
A,
A14
0'2
CS(4-7)
07
A,s
NOTE:
1. Both GND pins need to be grounded for
proper operation.
CS(~)
03
GND(')
7-2
FEATURES:
DESCRIPTION:
• High-density 64K1128K-bit CMOS dual-port RAM module
• 16K x 8 organization (IDT7M135) with 8K x 8
option (IDT7M134)
• Low-power consumption
• CEMOS·· process virtually eliminates alpha particle soft errors
rates (with no organic die coating)
• On-chip port arbitration logic
• BUSY flags
• Fully asynchronous operation from either port
• Single 5V (±10%) power supply
• Dual Vee and GND pins for maximum noise immunity
• On-chip pull up resistors for open-drain BUSY flag option
• Inputs and output directly TTL-compatible
• Fully static operation
• Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures
for all AC and DC parameters as per customer requirement
The IDT7M134/135 are 64K1128K-bit high-speed CMOS dualport static RAM modules constructed on a multi-layered ceramic
substrate using four IDT7132 2K x 8 dual-port RAMs (IDT7M134)
or eight IDT7132 dual-port RAMs (IDT7M135) in lead less chip
carriers. Dual-port function is achieved by utilization of the two
on-board IDT54/74FCT138 decoder circuits that interpret the
higher order addresses AL11-13 and ARI'-13 to select one of the
eight 2K x 8 dual-port RAMs. (On IDT7M134 8K x 8 option, the
AL13 and AR13 need to be externally grounded and the selection
becomes one of the four 2K x 8 dual-port RAMs.) Extremely high
speeds are achieved in this fashion due to the use of the IDT7132
dual-port RAM, fabricated in IDT's high-performance CEMOS
technology.
The IDT7M134/IDT7M135 provide two ports with separate control, address and I/O pins that permit independent access for
reads or writes to any location in the memory. The BUSY flags
are provided for the situation when both ports simultaneously
access the same memory location. The on-Chip arbitration logic will
determine which port has access and sets the BUSY flag of the
delayed port. BUSY is set at speeds that permit the processor to
hold the operation and its respective address and data. The
delayed port will have access when BUSY goes high (inactive).
The IDT7M134/135 are available with access times as fast as
70ns commercial and 90ns military temperature range, with
operating power consumption of only 2.1 W/3.5W (max.). The module
also offers a standby power mode of 1.4W/2.8W (max.) and a full
standby mode of 660mW/1.3W (max.).
AIiIDT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883, Class B, making
them ideally suited to applications demanding the highest level of
performance and reliabi lity.
PIN CONFIGURATION
GNO(1)
CEl
RtWl
R330 l
SUSYl
OEl
AOl
A1l
A2l
A3l
A4l
A5l
A6l
A7L
A8l
A9l
A'0l
Al1l
A12l
A13l(2)
I/OOl
I/O'l
I/02l
I/03l
I/04l
I/05l
I/06l
I/07l
GNO(1)
NOTES
58
57
56
55
54
53
52
51
so
1D
4'
11
48
12
13
14
15
47
46
4S
,.
44
4'
42
41
17
18
,.
40
3.
38
37
36
20
21
22
23
24
25
35
26
33
27
32
31
3D
34
26
2.
VCC(1)
CER
RtWR
R330R
SUSYR
OER
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
A'0R
A11R
A12R
A13R(2)
I/OOR
I/O'R
I/02R
I/03R
I/04R
I/05R
I/06R
I/07R
PIN NAMES
LEFTPORT
NAMES
RIGHT PORT
CE l
CE R
CHIP ENABLE
R/W l
R/W R
READ/WRITE ENABLE
OE l
OE R
OUTPUT ENABLE
BUSYl
BUSYR
BUSY FLAG (OPEN DRAIN)
R330 l
R330 R
PULL-UP RESISTORS for
Open-drain BUSY FLAG option
A OL-A'3L
AOA-A'3R
ADDRESS
1/0 0l-1/0 7l
1/0 0R-1/0 7R
Vee
GND
DATA INPUTIOUTPUT
POWER
GROUND
Vcc(1)
DIP
TOPYIEW
1. Both Vee pins need to be connected to the 5V supply, and both GND pins need
to be grounded for proper operation.
2. On 8Kx8 IOT7M134 option, A'3l and A'3A need to be externally connected to
ground for proper operation.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
7-3
JUNE 1986
Printed in U.S.A.
IDT7M134S/IDT7M135S CMOS DUAL·PORT
RAM MODULE 64K (8K x 8·BIT) & 128K (16K x 8·BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAMS
(A) IDT7M135 (16K x a-BIT)
330n
Vee -JVV\r-R330R
330n
R33DL --ANy--- Vee
RiWR
RiWl
AD-lot.
OEl
.1
I
I
~l:
IDT7132
f-
r--
-
BUSYl
(OPEN DRAIN)
CEl
~1
IDT7132
I-
r-
~J:
IDT7132
-
CEl
CER
CEl
CER
CEl
I
'(
'(
?
?
y
( OPEN DRAIN)
111
6
00010203
IDTFCT138
DECODER
IDTFCT138
DECODER
04 0 5 0 6 0 7
04 0 5 0 6 0 7
CEl
I- CER
r- All-13R
y
r
I/ORO-7
I I
6
6
6
~
~
~
CER
CEL
CER
CEl
CER
CEl
'-
f-
'-
I-
~r
IDT7132
f
- BiJS'YR
CER
00 0 1 0 2 0 3
I
~
-
CER
6
All-13l
IDT7132
f- r--
I
I/OlO-7
I
I
I
AD-lOR
OER
1
IDT7132
-
f-
~f
IDm32
CER
l-
'--
~r
1
IDT7132
1
(B) IDT7M134 (aK x a-BIT)
BUSYl
BUSYR
RtWR
RiWl
AO-lot.
OEl
1
f
I/OlO-7
I
I
IDT7132
CEl
~l:
CER
~J:
IDm32
r
CEl
y
CER
I
I
V
[
:!.J:
IDT7132
CEl
CER
9
9
~ ~
000102031
IDTFCT138
DECODER
CEl
All-12l
I
I
I
IDT7132
CEl
Ao-l0R
OER
J
l-
CER
'(
I10 RO-7
6~
(GROUND A13l AND A13R EXTERNALLY)
(A 13l)
00010203
IDTFCTl38
DECODER
(Al
-
7·4
IDT7M134S/IDT7M135S CMOS DUAL-PORT
RAM MODULE 64K (8K x 8-BIT) & 128K (16K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
Terminal Voltage with
Respect to GND
VTERM
Operating Temperature
TA
TSIAS
VALUE
UNIT
-0.5 to +7.0
V
-55 to +125
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
"C
Commercial
Temperature
Under Bias
-65 to +135
"C
Storage
Temperature
-65 to +150
"C
S.O
W
50
mA
T STG
f - - - - - -PT
Power Dissipation
DC Output Current
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
OV
5.0V
O"C to +70"C
OV
5.0V
Vee
± 10%
± 10%
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.2
-
6.0
V
V IL
Input Low Voltage
-0.5111
-
O.S
V
NOTE:
affect reliability
1. V 1L '" -3.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55"C to +125°C and oDe to
SYMBOL
GND
-55"C to +125°C
RECOMMENDED DC OPERATING CONDITIONS
-- --
lOUT
NOTE:
AMBIENT
TEMPERATURE
PARAMETER
+70°C)
TEST CONDITIONS
=5.5V, VIN =OV to Vee
MIN.
IDT7M134S
TYP.(') MAX.
MIN.
IDT7M135S
TYP.(') MAX.
UNIT
-
-
15
-
-
20
}J.A
-
-
15
-
-
20
}J.A
I n put H ig h Voltage
2.2
-
6.0
2.2
-
6.0
V
VIL
Input Low Voltage
-1.012)
-
O.S
-1.0(2)
-
O.S
V
Ice
Dynamic Operating Current
(Both Ports Active)
-
190
3S0
-
320
640
mA
ISB
Standby Current
(Both Ports Standby)
GEL and GE R :> VIH
-
130
260
-
260
520
mA
188 1
Standby Current
(One Port Standby)
CE l or CE R :> VIH
Active Port Outputs Open
-
160
320
-
290
5S0
mA
18B2
Full Standby Current
(Both Ports Full Standby)
Both Ports
CE l and CE R :> Vee -0.2V
VIN :> Vee -0.2V or VIN S 0.2V
-
4
12013 )
-
10
240( 3)
mA
VOL
Output Low Voltage (110 0
VOL
Open Drain Output Low
Voltage (BUSY)
10lo 16mA, Vee
VOH
Output High Voltage
IOl
IILlI
Input Leakage Current
Vee
IILOI
Output Leakage Current
CE
VIH
GE
0
VIH . VOUT
= Vll'
0
Outputs Open
10l = 3.5mA, Vee
-
1/0 7 )
10l
= SmA,
0
OV to Vee
-
-
0.4
-
-
0.4
V
-
-
0.5
-
-
0.5
V
= 4.5V
-
-
0.5
-
-
0.5
V
= 4.5V
2.4
-
-
2.4
-
-
V
0
4.5V
Vee = 4.5V
-4mA, Vee
NOTES:
1. Vee = 5V, T A=: +25°C.
2. V1L min. ::: -3.5V for pulse width less than 30ns.
3. 18B2 max. of IDT7M134/IDT7M135 at commercial temperature = BOmA/150mA.
7-5
fI
IDT7M134SIIDT7M135S CMOS DUAL·PORT
RAM MODULE 64K (8K x 8-BIT) & 1281< (18K x 8-BIT)
AC CHARACTERISTICS
SYMBOL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vee = 5V ±10%, TA = -55·C to +125·C and O·C to +70·C)
PARAMETER
IDT7M134S70
IDT7M135S70
COM'L.ONLY
MIN.
MAX.
IDT7M134S90
IDT7M135S90
IDT7M134S100 IDT7M134S120 IDT7M134S14O
IDT7M135S100 IDT7M135S120 IDT7M135S140
MIL. ONLY
MIN.
MAX.
MIN.
-
100
MAX.
MIN.
100
UNIT
MAX.
MIN.
120
-
140
-
-
120
-
140
ns
140
ns
70
ns
10
50
-
-
ns
15
50
60
ns
40
-
40
-
50
ns
ns
MAX.
READ CYCLE
tAC
Read Cycle Time
70
-
90
tM
Address Access Time
-
70
90
t ACE
Chip Enable Access Time
-
-
70
-
90
t AOE
Output Enable Access Time
-
40
-
45
-
tOH
Output Hold from Address Change
5
10
-
10
tCLZ
Chip Select to Output in Low Z
10
-
15
-
15
tCHZ
Chip Select to Output in High Z
-
35
-
45
tOHZ
Output Enable to Output in High Z
-
30
-
40
-
100
50
-
10
120
60
15
ns
ns
tOLz
Output Enable to Output in Low Z
5
-
5
-
0
-
0
0
-
5
0
-
5
Chip Enable to Power Up Time
-
5
tpu
0
-
ns
tpo
Chip Disable to Power Down Time
-
50
-
50
-
50
-
50
-
50
ns
90
100
-
120
110
95
110
-
-
120
10
-
-
ns
-
-
140
95
80
-
10
-
ns
-
65
-
75
-
40
10
WRITE CYCLE
twc
Write Cycle Time
70
tcw
Chip Selection to End of Write
60
tAW
Address Valid to End of Write
60
t AS
Address Setup Time
10
-
twp
Write Pulse Width
40
-
50
tWA
Write Recovery Time
5
-
5
tow
Data Valid to End of Write
30
-
40
tOH
Data Hold Time
10
-
10
-
tOHZ
Output Enable to Output In High Z
-
35
-
40
twz
Write Enabled to Output in High Z
-
35
-
-
40
tow
Output Active from End of Write
0
-
0
-
60
10
10
120
ns
ns
-
50
10
10
-
40
-
40
-
40
ns
-
40
-
50
-
60
ns
0
-
0
-
0
-
ns
100
-
120
-
140
100
-
120
-
140
-
50
-
60
-
70
60
-
70
ns
70
ns
70
ns
55
5
40
10
10
ns
ns
ns
ns
BUSY TIMING
tAC
Read Cycle Time
70
-
90
twc
Write Cycle Time
70
-
90
-
tBAA
BUSY Access Time to Address
-
45
BUSY Disable Time to Address
-
45
taoA
45
-
45
t aAc
BUSY Access Time to Chip Enable
-
40
-
-
40
-
taoc
BUSY Disable Time to Chip Enable
teoo
BUSY Disable to Valid Data
50
twoo
Write Pulse to Data Delay
-
10
tO~~
tAPS
Write Data Valid to
. Read Data Delay
Arbitration Priority Set Up Time
50
35
-
50
-
50
-
60
-
100
-
120
-
140
70
-
80
-
100
-
-
10
-
10
-
10
35
90
-
7-6
50
60
60
ns
90
ns
160
ns
120
-
140
ns
-
10
-
ns
60
IDT1M134S/IDT1M13SS CMOS DUAL-PORT
RAM MODULE 64K (8K x 8-BIT) & 128K (16K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDto3.0V
IOns
1.5V
1.5V
See Figs. 1. 2. and 3
+SV
+SV
12S0n
DOUT
+SV
12S0n
-.,----+
77sn
BUSY
SpF"
100pF*
SRD7132-005
-1
330n
I'OOW
SRD7132-006
Figure 1.
Output Load
Figure 2.
Output Load
(lor 'HZ, 'LZ,
Figure 3.
iiUSV OU'pu' Load
'wz, and 'ow)
"Including scope and jig.
CAPACITANCE
(TA ~ +25°C, f = 1.0MHz)
PARAMETER(')
CONDITIONS
7M134S
7M13SS
C 'N
Input Capacitance
Y'N ~ OV
150
180
pF
C OUT
Output Capacitance
VOUT~ OV
40
70
pF
SYMBOL
UNIT
NOTE:
1. This parameter is sampled and not 100% tested.
TIMING WAVEFORM OF READ CYCLE NO.1 EITHER SIDE(1,2,6)
~ ~I-------'RC----+-Il
~~~~-------------------'AA-------~~~~~~:~----------------------~'1'~'OH~
DATAOUT ____P_R_E_V_'O_U_S_D_AT_A_V_A_L_'D__~~~~JI'-------------D-A-TA--VA_L_'D____________-J
SRD7132-008
7-7
IDT7M134S/IDT7Ml35S CMOS DUAL-PORT
RAM MODULE 64K (8K x B-BIT) & 128K (16K x B-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.2 EITHER SIDE(1,3)
~----"'eE----~
~Do~ -----------r--------------~~~-i
ICC ____________I ..__'PU__3-j,,..I:__LZ-'..-------~-'_________________
Vee
CURRENT
_
oru-'p
I..
SRD7132-Q09
TIMING WAVEFORM OF WRITE CYCLE NO.2 EITHER SIDE(4,7)
ADDRESS
Iwe
------..
--
lew
I '~
lAW
IA.
Iwp
\\\
.
I
II Iii
!+---IWA-
IDW
+
y
ID
~'!lI(VALID
'I
\\\
LL{.,DHZ
1• ,
HIGH IMPEDANCE
SR07132-01O
TIMING WAVEFORM OF WRITE CYCLE NO.1 EITHER SIDE(4,7)
Iwe
ADDRESS -----
-
~ \
'ew
.1
\\-\
IA.
AiW
IIJ I I I I
_:AW
J
Iwp_ _IWR-
I
'\:\.
I~ .'DH __
DATA VALID
~'OW
~TAo~ 3>EE>3>::>B>3>EE>3>3:>3>::>B>3>EE>1:}-~H~IGH~IM~PE~DAN~CE:...~_f~X6X~X3X8>
~lWzI')
SA07132-011
7-8
IDT7M134S/IDT7M135S CMOS DUAL-PORT
RAM MODULE 64K (8K x 8-BIT) & 128K (16K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF CONTENTION CYCLE NO.1 CE ARBITRATION
CEl VALID FIRST:
ADOR
LAND R
-v
-A~
____________________ AVADDRESSES MATCH
crL~
~" ~--:jt
BUSYA
r
b ...~
.
.
________
_
---If
SAD7132-012
CER VALID FIRST:
LANDR
ADOR
-V
--"~
AV-
_ _ _ _ _ADDRESSES
_____
________________________
MATCH
~"~-tB~9----+-b-=1====
tBDC
SR07132-013
TIMING WAVEFORM OF CONTENTION CYCLE NO.2 ADDRESS VALID ARBITRATION(S)
LEFT ADDRESS VALID FIRST
-
tRcOA twe
--
lAPS
ADDRSR
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
~tBAA
~
x==
IBDA
SRD7132-Q14
I
RIGHT ADDRESS VALID FIRST
lAC OR twe
(
ADDRSA
lAPS
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
-
I+-
"'C
j.--tBAA
......---laDA
9--)
7-9
SRD7132-015
IDT7Ml34SIIDT7Ml35S
RAM MODULE 64K (8K x 8-BI1) " 128K (16K x 8-BI1)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVJ;:FORM OF READ WITH BUSY(S)
ADDRS LIR)
----..
-
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
. . lAPS"
ADDRS RIL )
_ I_ _
i----lSAA
BUSYRIL )
lAW
_IAS-----00----
IDV==:j
~ DATAoUT VALID
O..;,o---.,;O-8----......\XX-D-,.-:.:-A-0-UT-'l-A-LiD
Iwe
twPW
IWR-
-::-\
l
w 1\
--4r _. ~ ))-I-___~(
!PH
IDS
;;.D;;.o-,;;.D,;;.8_ _ _ _ _
DATAIN VALID
) ..._ __
SSD7M203-005
Figure 3. Asynchronous Wrlle and Raad Operal/on
LAST WRITE
ADDITIONAL
READS
FIRST WRITE
\....-1f-
R
W
FIRST READ
I -
I-
-twFF
-
IRFF
I--
FF
SSD7M203-006
Figure 4. Full Flag From Last Write 10 Flrsl Read
LAST READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
w
twEF
8SD7M203--007
Figure 5. Empty Flag From Last Read to Flrsl WrIte
7-22
IDT1M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t RPE : EFFECTIVE READ PULSE WIDTH AFTER EMPTV FLAG HIGH
w-----"
~
____________________-+__J
NOTE:
SSD7M203-00B
1. (t RPE = t RPW)
Figure 6. Empty Flag Timing
tWPF: EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH
Fi----""\
ff--------------------+---J
NOTE:
1. (t WPF = t wpw).
SSD7M203-009
Figure 7. Full Flag Timing
OPERATING MODES:
SINGLE DEVICE MODE
fI
EXPANSION OUT (XO)
A single IDT7M203/IDT7M204 may be used when the application requirements are for 2048/4096 words or less. The
IDT7M203/1DT7M204 is a Single Device Configuration when the
EXPANSION IN (XI) control input is connected to the
EXPANSION OUT (XO) of the device and the FIRST LOAD (FL.)
control pin is grounded (see Figure 8).
(W)
WRITE
/
FULL FLAG
WIDTH EXPANSION MODE
RESET
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags
(EF, FF) can be detected from anyone device. Figure 9 demonstrates an 18-bitword width by using two I DT7M2031 I DT7M204s.
Any word width can be attained by adding additional
I DT7M203/1 DT7M204s.
-
(R)
~
9
DATA'N
I
(D)
(ff)"
READ
~
9,
lOT
7M203/4
(RS)
EXPANSION IN (XI)
(0) /
DATAoUT
(~) EMPTY FLAGr
>
~F[) FIRST LOAD
•
SSD7M203-010
Figure 8. Block Diagram of Single IDT7M203/1DT7M204 FIFO
7-23
IDT7M203SIIDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
is monitored by each system (i.e. FF is monitored on the device
where Wis used; EF is mon ito red on the device where Ris used).
Both Depth Expansion and Width Expansion may be used in this
mode.
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7M203/IDT7M204 can easily be adapted to applications when the requirements are for greater than 2048/4096
words. Figure 10 demonstrates Depth Expansion using three
IDT7M203/IDT7M204s. Any depth can be attained by adding
additional IDT7M203/IDT7M204s. The IDT7M203/IDT7M204
operates in the Depth Expansion configuration when the
following conditions are met:
DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted with the
I DT7M203/1DT7M204: a read flow-through and write flowthrough mode. For the read flow-through mode (Figure 13), the
FIFO permits a reading of a single word after writing one word of
data into an empty FI FO. The data is enabled on the bus in (tWEF +
tA)ns after the rising edge ofW, called the first write edge, and it
remains on the bus until the R line is raised from low-ta-high,
after which the bus would go into a three-state mode after tRHZns.
The EF line would have a pulse showing temporary deassertion
and then would be asserted. In the interval oftime that R was low,
more words can be written to the FIFO (the subsequent writes
after the first write edgewould deassert the empty flag); however,
the same word (written on the first edge), presented tothe output
bus as the read pointer, would not be incremented when R is low.
On toggling R, the other words that were written to the FIFO will
appear on the output bus as in the read cycle timings.
In a write flow-through mode (Figure 14), the FIFO permits the
writing of a single word of data immediately after reading one
word of data from a full FIFO. The R line causes the FF to be
deasserted, but the W line being low causes it to be asserted
again in anticipation of a new data word. On the rising edge ofw'
a new word is loaded in the FIFO. The W line must be toggled
when FF is not asserted to write new data in the FIFO and
increment the write pointer.
1. The first device must be designed by grounding the FIRST
LOAD (IT) control input.
2. All other devices must have FL in the high state.
3. The EXPANSION OUT (XO) pin of each device must be tied to
the EXPANSION IN (xi) pin of the next device. See Figure 10.
4. External logic is needed to generate a composite FULL FLAG
(FF) and EMPTY FLAG (EF). This requires the ORing of all EFs
and ORing of all FFs (i.e. all must be set to generate the
correct composite FF or EF). See Figure 10.
COMPOUND EXPANSION MODE
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO
arrays. (See Figure 11.)
BIDIRECTIONAL MODE
Applications which require data buffering between two systems (each system capable of READ and WRITE operations) can
be achieved by pairing IDT7M203/1DT7M204s as is shown in
Fi9ure 12. Care must be taken to assure that the appropriate flag
DATA'N(D)
(ii) READ
FULL FLAG
1 - - - - - - (fF) EMPTY FLAG
----""--'-'---+-1
RESET ---(RS)
(Q)DATA oUT
NOTES:
Flag detection is accomplished by monitoring the FF and EF signals on either
(any) device used in the width expansion configuration. Do not connect any
output control signals together.
FIgure 9. Block Diagram 01 2048x18/4096x18 FIFO Memory
Used In Width Expansion Mode
7-24
5SD7M203-011
IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE 12K x 9-BIT .. 4K x 9-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TABLE I - RESET SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INPUT
MODE
INTERNAL STATUS
Read Pointer
RS
OUTPUTS
Write Pointer
EF
FF
Reset
0
Location Zero
Location Zero
0
1
Read/Write
1
Increment l1 )
Increment l1 )
X
X
NOTE:
1. Pointer will increment if flag is high.
TABLE II - RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE
INPUTS
MODE
INTERNAL STATUS
OUTPUTS
RS
FL
XI
Read Pointer
Write Pointer
EF
FF
Reset-First Device
0
0
(1)
Location Zero
Location Zero
0
1
Reset all Other Devices
0
1
(1)
Location Zero
Location Zero
0
1
Read/Write
1
X
(1)
X
X
X
X
NOTES:
1.
XI is connected to XO of previous device. See Figure 10.
RS = Reset Input, IT = First Load, EF = Empty Flag Output, FF = Full Flag Output, Xl = Expansion Input.
XO
R
W
FF
9
D
9
/
...
/
~
IDT
M203t
EF
9
~
/
Q}
7L
, Vee
-~~
Xi
r-~
-
FULL
FF
9 ~
L
..:-t
~
~
IDT ~
M203/ f--
I FL
-~~
I--
Xi
-~
AS
FF
9
1
~
f+=
IDT ~
M203/ f--
r
-r=-
FL
XI
-=SSD7M203-012
Figure 10. Block Diagram 01 6144x9112288x9 FIFO Memory (Depth Expansion)
7-25
IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
09-017
00-08
00-08
."..
0(N-8)-ON
09-017
0(N-8)-ON
ii, Vi, iiS
•••
Do-D8
Do-DN
D9-D17
D9-DN
D18-DN
D(N-8)-DN
•••
D(N-8)-DN
SSD7M203-013
NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 10.
2. For flag detection see WIDTH expansion Section and Figure 9.
Figure 11. Compound FIFO Expansion
RB
EFB
XOB(TO (xi) OF THE
SAME DEVICE)
WA
IDT
7M203/4
FFA
~
DA0-8
OBO-8
r
-=1-FI:
~
SYSTEM A
SYSTEM B
~
DB0-8
1\
OA0-8
RA
IDT
7M203/4
~
Wi!
(TO (Xi) OF THE SAME DEVICE) XO A
EFA
FFB
_1;-= FL
SSD7M203-014
Figure 12. Bidirectional FIFO Mode
7-26
IDT7M203S1IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE 12K
Vi
x 9-BIT • 4K x 9-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
_3V
__~____""
RW
u_W__ ________________+_-----J
~
DATAOUT---+--------------------~
NOTE:
(TRPE
SSD7M203-015
=T RPW)
Figure 13. Read Data Flow-Through Mode
if 3V
_ OV
W--~--------------+_------+_---------JI
FF_W__r-______________+-____- - J
DATA~---+----------------------------~
·d,
DATAOUT--------~-~-~A-O-U-T-~-~-Ll~D~-----------------SSD7M203-016
Figure 14. Write Data Flow-Through Mode
7-27
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT7M205/206 are FIFO memory modules constructed on
a multi-layered ceramic substrate using four IDT7203 (2K x 9) or
four IDT7204 (4Kx 9) FIFOs in lead less chip carriers. Extremely
high speeds are achieved in this fashion due to the use of
IDT7203s and IDT7204s fabricated in IDT's high-performance
CEMOS technology. These devices utilize a special First-In,
First-Out algorithm that loads and empties data on a first-in,
first-out basis. The device uses full and empty flags to prevent
data overflow and underflow and expansion logic to allow for
unlimited expansion capability in both word size and depth.
The reads and writes are internally sequential through the use
of ring pointers, with no address information required to load and
unload data. Data is toggled in and out of the device through the
use of the WRITE (VIi) and READ (Fi) pins. The devices have a
read/write cycle time of 75ns (13MHz) for commercial and 80ns
(12.5MHz) for military temperature ranges.
The devices utilize a 9-bit wide data array to allow for control
and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking.
IDT's military FIFO modules have semiconductor components
100% processed to the test methods of MIL-STD-883, Class B,
making them ideally suited to applications demanding the
highest level of performance and reliability.
First-In, First-Out memory module
8Kx 9 organization (IDT7M205)
16K x 9 organization (IDT7M206)
Low power consumption
-Active: 900mW (typ.)
-Power Down: 50mW (typ.)
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Single 5V (±10%) power supply
• Ml\ster/slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and full warning flags
• High-performance CEMOS'· technology
• Pin compatible with IDT7201 and Mostek MK4501, but with
16 times word depth (IDT7M205) or 32 times (IDT7M206)
• Module available with semiconductor components 100%
screened to MIL-STD-883, Class B
PIN CONFIGURATION
Vi
Vcc
04
05
06
07
08
03
02
01
DO
FUNCTIONAL BLOCK DIAGRAM
Fi:
AS
Xi
FF
00
01
02
03
08
EF
00-08
00-08
XO
Vi
07
06
05
04
Xo
R
l,-L~f-
I II
l~70u
IDT120314
IDT720314
RS
XI-
R
GNO
-XI
SSD7M203-001
XI
~
DIP
TOP VIEW
PIN NAMES
L...
Wo
WRITE
FL 0
FIRST LOAD
XI 0
EXPANSION IN
EF 0
EMPTY FLAG
R0
READ
D=
DATA IN
XO =
EXPANSION
OUT
Vee =
5V
RS 0
RESET
Q=
FF 0
FULL FLAG
GND =
GROUND
DATA OUT
IT
IT
vcc
FF
Xo
Xo
IDT720314
IDT7203/4
XI
IT
~~n
_~U
-
Fi:
~
'- X.!....
~~
+EF
I
K
'---
DUAL 4-INPUT OR GATE
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1986 Integrated Device Technology. Inc.
JULY 1986
Printed in the U.S.A.
7-28
FEATURES:
DESCRIPTION:
• High-density 1024K-bit CMOS static RAM module
• Customer-configured to 64K x 16, 128K x 8 or 256K x 4
• Fast access times
-Military: 45ns (max.)
-Commercial: 30ns (max.)
The IDT7M624 is a 1024K-bit high-speed CMOS static RAM
constructed on a multi-layered ceramic substrate using 16
IDT7187 (64K x 1) static RAMs in lead less chip carriers. Making
four chip select lines available (one for each group of 4 RAMs)
allows the user to configure the memory into a 64K x 16, 128K x 8
or 256K x 4 organization. In addition, extremely high speeds are
achievable by the use of IDT7187s fabricated in lOT's highperformance, high-reliability technology, CEMOS. This state-ofthe-art technology, combined with innovative circuit design
techniques, provides the fastest 64K static RAMs available.
The IDT7M624 is available with access times as fast as 30ns
commercial and 45ns military temperature range, with maximum
operating power consumption of only 10.7W (significantly less
if organized 128K x 8 or 256K x 4). The module also offers a
standby power mode of 4.5W (max.) and a full standby mode
of 1.7W (max.).
The IDT7M624 is offered in a 40-pin, 900 mil center sidebraze
DIP to take advantage of the compact IDT7187s in lead less
chip carriers.
All inputs and outputs of the IDT7M624 are TTL-compatible
and operate from a single 5V supply. (NOTE: Both GND pins
need to be grounded for proper operation.) Fully asynchronous
circuitry is used requiring no clocks or refreshing for operation,
and provides equal access times for ease of use.
All lOT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883, Class B, making
them ideally suited to applications demanding the highest level
of performance and reliability.
•
Low power consumption
- Active 4.8W (typ. in 64K x 16 organization)
- Standby: 1.6mW (typ.)
•
Utilizes 16 IDT7187 high-performance 64K x 1 CMOS static
RAMs produced with lOT's advanced CEMOS" technology
•
CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
•
Assembled with lOT's high-reliability vapor phase solder
reflow process
•
•
Offered in 40-pin, 900 mil center sidebraze DIP, achieving very
high memory density
Pin compatible with IDT7M656 (256K RAM module)
•
•
•
Single 5V (±10%) power supply
Dual GND pins for maximum noise immunity
Inputs and outputs directly TTL-compatible
•
Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters as per
customer requirements
•
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
(')GND
Vcc
D,s
CS(,._,S)
04
0 11
WE
A,
0,4
A.
Os
A3
A4
0'3
As
D.
A.
A'4
0,.
CS(4-7)
07
A,s
CS(8-11)
Do
.Ao
A'3
0'0
A,.
0,
A11
A,o
D.
A.
D.
A.
A7
D.
CS(0-3)
03
GND(')
PIN NAMES
AD-'6
Addresses
1/0,-8
Data Input/Output
CS
Chip Select
WE
Write Enable
Vee
Power
GND
Ground
NOTE:
1. 80th GND pins need to be grounded for
proper operation.
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@
1986 Integrated Device Technology, Inc.
JULY 1986
Printed in U.S.A.
7-29
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M624S 1 MEGABIT CMOS STATIC RAM MDDULE
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Terminal Voltage
with Respecl
toGND
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-10 to +85
-65 to +135
·C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
·C
PT
Power Dissipation
8
8
lOUT
DC Output Current
50
50
Commercial
SYMBOL
PARAMETER
GND
Vee
-55·C to +125·C
OV
S.OV± 10%
O·C to +70·C
OV
S.OV± 10%
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
W
GND
Supply Voltage
0
0
0
V
rnA
VIH
Input High Voltage
2.2
6.0
V
VIL
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation 01 the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS
AMBIENT
TEMPERATURE
NOTE:
1. VIL = -3.0V for pulse width less than 2Ons.
(Vee = +S.OV ± 10%, TA = -SS·C to +12S·C and O·C to +70°C)
TEST CONDITIONS
MIN.
IDT7M624S
MAX.
TYP.")
UNIT
-
-
20
p.A
Output Leakage Current
Vee =5.5V,
CS xx = VIH, VOUT =GND to Vee
-
-
20
p.A
leex16
Operating Current in X16 mode
CS xx =VIL, Output Open
Vee =5.5V, I =IMax.
-
960
1950
rnA
leex.
Operating Current in X8 mode
CS xx =VIL' Output Open
Min. Duty Cycle = 100%
-
720
1380
rnA
Icex.
Operating Current in X4 mode
CS xx = VIL' Output Open
Min. Duty Cycle =100%
-
800
1100
rnA
ISB
Standby Power Supply Current
CS xx '" VIH, (TTL Level),
Vee =5.5V, Output Open
-
480
820
rnA
ISBl
Full Standby Power Supply Current
CSxx '" Vee - 0.2\/,
VIN ", Vee - 0.2V or oS 0.2V (CMOS Level)
-
0.32
320(2)
rnA
Output Low Voltage
10L = lOrnA, Vee
-
V
0.4
V
VOH
Output High Voltage
-
0.5
VOL
-
V
IILlI
IILO I
Input Leakage Current
Vee =5.5V, VIN
=GND to Vee
=4.5V
=4.5V
IOL =-4mA, Vee =4.5V
10L - 8mA, Vee
NOTES:
1. Typical limits are at Vee = 5.0V, +25°C ambient.
2. ISBl max. at commercial temperature = 240 rnA.
7-30
2.4
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
+5V
GNDt03.0V
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
10ns
1.5V
Output Reference Levels
1.5V
4"'"
DOUT-~---i
DOUT---?---+
5pF'"
30pF'"
See Figures 1 and 2
Output Load
+5V
Figure 1. Output Load
Figure 2. Output Load
(for t HZ' t LZ , t wz, and tow)
"Including scope and jig.
AC CHARACTERISTICS (Vcc = 5V ± 10%, TA =-55°C to +125°C and O°C to +70°C)
SYMBOL
PARAMETER
IDT7M624S30
COM'LONLY
MIN.
MAX.
IDT7M624S45
IDT7M624S55
IDT7M624S65
IDT7M624S85
MIN.
MAX.
MIN.
MIN.
MIN.
UNIT
MAX.
MAX.
MAX.
READ CYCLE
t AC
Read Cycle Time
30
-
45
-
55
-
65
-
85
-
ns
tAA
Address Access Time
-
30
-
45
55
-
65
ns
Chip Select Access Time
-
30
-
45
55
-
65
-
85
t ACS
-
85
ns
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
5
Chip Selection to Output in Low Z
5
-
5
-
5
-
5
-
ns
tLZ
-
tHZ
Chip Deselection to Output in High Z
-
25
-
30
-
30
-
30
-
ns
tpu
Chip Selection to Power Up Time
0
-
0
-
0
-
0
-
0
4"
-
t po
Chip Selection to Power Down Time
-
30
-
35
-
35
-
35
-
40
ns
55
-
65
-
85
-
55
-
65
-
ns
50
50
-
55
-
65
-
ns
5
ns
ns
WRITE CYCLE
twc
Write Cycle Time
30
Chip Selection to End of Write
25
-
45
tcw
tAW
Address Valid to End of Write
25
-
40
-
t AS
Address Setup Time
3
-
5
-
5
-
10
-
10
-
ns
twp
Write Pulse Width
20
-
30
35
-
40
-
45
-
ns
tWA
Write Recovery Time
0
-
0
0
-
0
-
0
-
ns
tow
Data Valid to End of Write
20
-
25
25
-
30
-
35
-
ns
toH
Data Hold Time
5
-
5
-
5
-
5
-
5
-
ns
twz
Write Enable to Output in High Z
0
25
0
30
0
30
0
35
0
40
ns
tow
Output Active from End of Write
5
-
5
-
5
-
5
-
5
-
ns
40
7-31
ns
fI
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2)
C
~f.o~------tRC(5)
ADDRESS _ _ _ _ _
-----------'~~::::tO:H::::O::~::::::~------------PREVIOUS DATA VALID
DATA OUT
DATAYALlO
TIMING WAVEFORM OF READ CYCLE NO.2(1,3)
1---------tRC(5)-------~_I
1,-------
CSxx
DATA OUT - - - - - - - - - (
HIGH IMPEDANCE
""j
r-.
I
----ICC
Vee SUPPLY
CURRENT ISB
NOTES:
1. WE is high for READ cycle.
2. CS xx is low for READ cycle.
3. Address valid prior to or coincident with CS xx transition low.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
5. All READ cycle timings are referenced from the last valid address to the first transititioning address.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
ADDRESS
-
twe
--..
--'
'--I,
tew
,\ \\\
0
.:\\ \ \
tAW
\
.\\\\
IWR_
tw.
_ t AS _ } \
0
t o w - -4------IOH--"
DATA IN _ _ _ _ _ _ _ _....;._ _ _ _.Jt=DATAIN VALID
i---twzI4J---
I
I--IQW(2,4)---
,---DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
7·32
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
1---------IWC{3)---------1
ADDRESS
CSxx
-+______to_w_~
________~,I~ tOH
I
DATA IN
DATA OUT
DATA IN VALID
~
---------------~I----'wzl~·)--1~---------------_
~
DATA UNDEFINED
HIGH IMPEDANCE
NOTES:
1. CS xx or WE must be high during address transitions.
2. 11 CSxx goes high simultaneously with WE high, the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
TRUTH TABLE
CAPACITANCE
MODE
CS xx
WE
OUTPUT
POWER
Standby
H
X
High Z
Standby
Read
L
H
DOut
Active
Write
L
L
HighZ
Active
SYMBOL
(TA = +25°C, f = 1.0MHz)
PARAMETER(1)
C 'N
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
V,N
OV
c
VOUT
c
NOTE:
1. This parameter is sampled and not 100% tested.
7-33
OV
TYP.
UNIT
130
pF
35
pF
IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M624
64K X 16 CONFIGURATION
NOTE:
All chips selects tied together since, in a by 16 configuration, all chips are either on or off.
IDT7M624
128K X 8 CONFIGURATION
A.-A,.
Do
D,
D.
D.
D.
D.
D.
D,
eso_.
eS4-7
eSil-1I
CS,,_,.
NOTE:
The chip selects are tied together in groups of two. The decoder uses the new higher order address pin (Ale) to determine which of the two banks of memory are enabled.
IDT7M624
256K X 4 CONFIGURATION
Ao-A,. --.-J'f==================~~~A~o~-~A~'·~~~====~S=====~E===~ll
,
WE
esW
VCC~
>8tJ:;~J~J
D,
NOTE:
Each chip select is now controlled by the two higher order address pins A 16 and An.
7-34
FEATURES:
DESCRIPTION:
• High-density 256K-bit CMOS static RAM Module
• Customer-configured to 16Kx16, 32Kx8 or 64Kx4
• Fast access times
-Commercial - 25ns
-Military - 35ns
• Low-power consumption
-Active: 3.2W (typ.) (in 16K x 16 organization)
-Standby: 0.16mW (typ.)
• Utilizes 161DT6167s - high-performance 16K x 1 CMOS
static RAMs produced with IDT's advanced CEMOS~
technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in 40-pin, 900 mil center sidebraze DIP. achieving
very high memory density
The IDT7M656 is a 256K-bit high-speed CMOS static RAM
constructed on a multilayered ceramic substrate using 16
IDT6167 (16Kxl) static RAMs in leadless chip carriers. Making 4
chip select lines available (one for each group of 4 RAMs) allows
the user to configure the memory into a 16Kx16, 32Kx8 or 64Kx4
organization. In addition, extremely high speeds are achievable
by the use of IDT6167s fabricated in IDT's high-performance,
high-reliability technology, CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques,
provides some of the fastest 16K static RAMs available.
The IDT7M656 is available with access times as fast as 25ns
commercial and 35ns military temperature range, with maximum
operating power consumption of only 7.0W (significantly less if
organized 32K x 8 or 64K x 4). The RAM Module also offers a
maximum standby power mode of 2.2W and a maximum full
standby mode of 82.SmW.
The IDT7M656 is offered in a high-density 4o-pin, 900 mil
center sidebraze DIP to take full advantage of the compact
IDT6167s in leadless chip carriers.
All inputs and outputs of the IDT7M656 are TTL-compatible
and operate from a single5V supply. (NOTE: Both Vee pins need
to be connected to the SV supply and both GND pins need to be
grounded for proper operation.) Full asyncronous circuitry is
used requiring no clocks or refreshing for operation, and provides equal access and cycle times for ease of use.
Alii DT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883, Class B, making
them ideally suited to'llpplications demanding the highest level
of performance and reliability.
•
•
•
•
Single SV (±10%) power supply
Dual Vee and GND pins for maximum noise immunity
Inputs and outputs directly TTL-compatible
Module available with components 100% screened to MILSTD-883, Class B
PIN CONFIGURATION
*GND
D"
Dn
CS(I"')
D,
WE(BOT)
A,
A,
A"
D"
A,
D"
D,
D,
FUNCTIONAL BLOCK DIAGRAM
A"
A,
31
All
A.
30
A,o
D,
D"
A,
A,
D,
D,
A.
A,
WE(TOP)
A,
D"
D,
CS(4'7)
fI
CS(0-31
D,
D,
21
*Vcc
GNO.
WE·BOT
~t:=;:4===::::;+===;::+===:::;l
Gsa 11-++--~+-t--~t-+-t---·-~++-----,
DIP
TDPVIEW
SRD7M656-001
* Both Vee pins need to be connected to the 5V Supply, and both GND pins
need to be grounded for proper operation.
PIN NAMES
Axx
CSxx
WE xx
ADDRESSES
CHIP SELECTS
WRITE ENABLES
Cs'2 15 - -.....+-t--~t-+-t----~++-----,
Dxx
Vee
GND
DATA IN/OUT
POWER
GROUND
SR07M65&002
CEMOS is a trademark of Integrated Device Technology. Incorporated.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
June 1986
~1986
Printed in the U.S.A.
Integrated Device Technology, Incorporated.
7-35
IDT7M858L 258K CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
RECOMMENDED DC OPERATING
CONDITIONS
(TA = -55°C to +125°C and O°C to +70°C)
VTERM
Terminal Voltage
with Respect
toGND
TA
Operating
Temperature
o to +70
-55 to +125
·C
TBIAS
Temperature
Under Bias
-10 to +85
-65 to +135
TSTG
Storage
Temperature
-55 to +125
PT
Power Dissipation
8.0
SYMBOL
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
PARAMETER
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
·C
VIH
Input High Voltage
2.2
6.0
V
Input Low Voltage
-0.5 (1 )
0.8
V
-65 to +150
·C
VIL
NOTE:
-
8.0
W
1. V 1L min = -1.0V for pulse width less than 20ns.
DC Output Current
50
mA
50
lOUT
NOTE:
1. Slresses greater than thoselistect under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This Is a stress rating only and functional operation 01 the deylce at these or any other conditions above those
Indicated in the operational sections of this Specilication Is nol implied. Expo,sure to absolute maximum reting conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
(Vcc = +5.0V
± 10%, TA = -55°C to +125°C and O°C to +70°C)
TEST CONDITIONS
PARAMETER
MIN.
IDT7M656L
TYP.
MAX.
UNIT
leex16
Operating Current in X16 mode
CS xx = VIL ' Output Open, Vee = 5.5V, f = f Max.
-
640
1260
mA
leex6
Operating Current in X8 mode
CS xx = VIL , Output Open, Vee = 5.5V, f = f Max.
-
420
840
mA
leex4
Operating Current in X4 mode
CS xx = VIL ' Output Open, Vee = 5.5V, f = f Max.
620
mA
Standby Power Suppiy Current
CS xx 2: VIH (TTL Level), Vee = 5.5V, Output Open
200
400
mA
ISBI
Full Standby Power Supply
Current
CS xx 2: Vee - 0.2V (CMOS Level)
VIN 2: Vee - 0.2V or!S 0.2V
-
310
ISB
0.032
15(2)
mA
-
0.4
V
-
V
lIul
I n put Leakage Current
Vee =5.5V, VIN=OVtoVee
IILOI
Output Leakage Current
CS = VIH, VOUT = OV to Vee
VOL
Output Low Voltage
10L =8mA
-
VOH
Output High Voltage
10H = -4mA
2.4
-
20
p.A
20
p.A
NOTES
1. Vce =SV. TA =+2SoC
2. ISB1 max. at commercial temperature = 5.0mA
TRUTH TABLE
AC TEST CONDITIONS
MODE
CSxx
WE xx
OUTPUT
POWER
Standby
H
X
HlghZ
Standby
Read
L
H
DOut
Active
Write
L
L
HighZ
Input Pulse Levels
Input Riseand Fal/Tlmes
GNDt03.0V
10ns
Input Timing Reference Levels
1.5V
Output Reference Levels
Active
Output Load
1.5 V
See Figures 1 and 2
~v
CAPACITANCE
SYMBOL
CIN
C OUT(2)
(TA = +25°C, f = 1.0MHz)
PARAMETER(I)
Input CapaCitance
Output Capacitance
~v
DOUT-~---+
CONDITIONS
TYp.
UNIT
V'N=OV
200
pF
VOUT=OV
60
pF
DoUT-~---+
3OpF*
NOTE$:
SA07M656-003
1. This parameter is sampled and not 100% tested.
2. For each output. 16K x 16 mode.
Figure 1. Output Load
SRD7M656-004
Figure 2. Outpul Load
(for 1HZ , t LZ, twz. and tow)
°lncludlng scope and Jig.
7-36
IDT7M656L 256K CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vee = 5V 10%, All Temperature Ranges)
SYMBOL
IDT7M656L25(')
COM'L. ONLY
MIN.
MAX.
PARAMETER
IDT7M856L100
MIL. ONLY
UNIT
MAX. MIN. MAX.
IDT7M656L35 IDT7M656L55 IDT7M656L65 IDT7M658L85
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
READ CYCLE
t AC
Read Cycle Time
25
-
35
-
55
-
65
-
85
-
100
-
ns
tAA
Address Access Time
25
-
65
-
85
-
100
ns
25
35
-
55
Chip Select Access Time
-
35
t Acs
-
55
-
65
-
85
-
100
ns
tOH
Output Hold from
Address Change
5
-
5
-
5
-
5
-
5
-
5
-
ns
tLZ
Chip Selection to
Output in Low Z
5
-
5
-
5
-
5
-
5
-
5
-
ns
tHZ
Chip Deselect to
Output in High Z
-
15
-
20
-
40
-
40
-
50
-
50
ns
t pu
Chip Select to
Power Up Time
0
-
0
-
0
-
0
-
0
-
0
-
ns
t po
Chip Select to
Power Down Time
-
25
-
35
-
55
-
65
-
85
-
100
ns
WRITE CYCLE
twc
Write Cycle Time
25
-
35
-
55
-
65
-
85
-
100
-
ns
tcw
Chip Select to
End of Write
20
-
30
-
45
-
55
-
65
-
80
-
ns
25
-
35
-
45
-
55
-
65
-
80
-
ns
5
5
-
5
-
5
35
-
40
0
-
0
-
0
30
5
-
ns
30
tAW
Address Valid to
End of Write
t As
Address Setup Time
twp
Write Pulse Width
20
tWA
Write Recovery Time
0
-
tow
Data Valid to End of Write
15
-
20
-
25
tOH
Data Hold Time
5
-
5
-
5
-
twz
Write Enable to
Output in High Z
-
10
-
15
-
40
tow
Output Active from
End of Write
0
-
0
-
0
-
5
-
5
45
55
5
-
5
-
-
40
-
50
-
50
ns
0
-
0
-
0
-
ns
0
35
0
40
NOTES:
1. IDT7M656L25 will not have low Vee data retention characteristics.
TIMING WAVEFORM OF READ CYCLE NO.1 (1,2)
ADDRESS
--t=toH_~-d,-t.-.=-~t"-clS)-l-~-_=~-_~_l::::_
_Da_t._v_._,Id___--'i~......I.X~..I.X.Jro...-1K
Data
p_,.._,_....
DATAoUT _ _ _ _
b
IAC(5) _ _ _ _ _
~----::::::::~t.;,c.~::::::::~------~
ILZ
t Hz l4.6)
--..1,,-------"'1.,...------......-----.,
DATAoUT-----------------{~ _______~'-__~D~.:t.~V.~II~d
I
~c_ .1:
NOTES:
VccSUPPLV
CURRENT ISB
:.j
SRD7M656-005
--.J't
TIMING WAVEFORM OF READ CYCLE NO. 2(1,3)
~,~
Valid
'"
___~~;;""';.:;,::-High Impedlnc.
!--tPD--t_ _
p
SRD7M656-006
1. WExx is high for READ cycle.
2. CS xx is low for READ cycle.
3. Address valid prior to or coincident with Csxx transition low.
4. Transition is measured ±500mV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
5. ~II READ cycle timings are referenced from the last valid address to the first transitioning address.
6. For any given speed grade, operating voltage, and temperature, tHZ will be Jess than or equal to t lZ'
7·37
ns
ns
ns
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M656L 256K CMOS STATIC RAM MODULE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
ADDRESS
-
~\
.
'we
I I
'ew
\\\
..:\\\\ .\\\\
twA_
'AW
'w.
\.\
1--,..
--1
L
-l
DATA,. _ _ _ _- - ' -_ _
r'wz(')
)J.-----H-(gh-)m-...
-._----{~.'-___
D.blUndelinMI
DATAOUT
k=
f-- 'OW(2,.):,---_
---'DH __
~,.V.,~ I
tow-----'
SRD7M656-007
.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
.
tWC(3)
.
ADDRESS
-+-IAS
--:-111
.
CSxx
'ew
\.
II
'AW
4--tWR--'"
....--twp----+WExx
,\\ \ \ \ \ \ \ \ \
fDW-
I
DATAoUT
~\\\\\\\\\
<4-tOH
D,'eV.lld
~_'_WZ(.~)-~II--------------
_ __________
Da.a Undefined
_
High Impedance
SAD7M6S6-008
NOTES:
1.
2.
3.
4.
C~ or WExx must be high during address transitions.
If CS xx goes high simultaneously with WExx high, the output remains in a high impedance state.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
LOW Vee DATA RETENTION CHARACTERISTICS (TA = -55°C to +125°C and O°C to +70°C) (Except IDT7M656L25)
VDA
Vcc for Data Retention
ICCDA
Data Retention Current
MIN.
TEST CONDITION
PARAMETER
SYMBOL
tCDA
Chip Deselect to Data Retention Time
tA
Operation Recovery Time
TYP.(1)
2.0
-
CS xx " Vcc -0.2V
-
,01(2)
,02(3)
V(N"VCC -0,2V or .. 0.2V
0
-
tAC(4)
-
c~:'i..
':.~.
-
-
V
2.0(2)
3.0(3)
6,0
9.0
mA
-
-
ns
-
ns
-
NOTES:
1. TA =+25°C
at VCC = 2V
2,
3,
at Vee = 3V
4, t AC
=Read Cycle Time
LOW Vee DATA RETENTION WAVEFORM
...--Oa18 Retenlion Mode ~
Vee
4.SV
r
os
'70w
1\' -____
~V~D~R.~2~V
tCDA .....
v,"
VDR
I
4.5V
______1
_'R_~
I
'
7·38
V'"~'
SRD7M656-009
UNIT
IDT7M656L 256K CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs.
Ambient Temperature
Supply Current vs. Voltage
1.6
1.6
Vcc =5.5V
TA = +25°C
1.4
".;
/'
1.2
./
5
u
Vcc=4.SV
1.4
1.4
OJ
E
~
Address Access TIme vs.
Ambient Temperature
1.6
1.0
.!'
0.8
V
./
V
V
1.2
0
~
u
.!'
1.0
4.75
5.0
5.25
5.5
"
"
"'
0.8
0.6
4.5
".;~
0.6
-75
,;; 1.2
'"
~
~
-25
~
..:'
r--.........
75
1.0
0.8
125
0.6
-75
~
V
-25
/
V
75
125
Vee (volts)
SRD7M656-010
Full Stand-by Power
Supply Current.
Data Retention Current vs.
Ambient Temperature
Stand-by-Power Supply
Current vs. Ambient
Temperature
Stand-by Power Supply
Current vs. Voltage
1.6
1.6
TA = +25°C
1.4
I
SRD7M656-012
SRD7M656-011
/
1.2
OJ
~
~
m 1.0
/
0
0.8
0.6
4.5
V
VCC!5.5V
/
1.4
-"'-
V
0.8
/
4.75
5.0
5.25
1000
5.5
0.6
-75
'"
-25
I"" l'-
25
75
125
T.(OC)
Vee (volts)
SRD7M656-013
SRD7M656-014
Address Access Time vs.
Capacitive Load
1.2
T; = +25°C
V
./
./
/
50
capacitive Load (pi)
L
0
100
SRD7M656-016
7-39
0
1
IL
.1
-50
100
150
SRD7M656-015
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M6S6L 256K CMOS STATIC RAM MODULE
IDT7M656
16K x 16 CONFIGURATION
NOTES:
SRD7M65&-017
1. All chip selects tied together since, in a by 16 configuration, all chips are either on or off.
2. The two write enables are tied together allowing control of the write enable forentire memory at one time (necessary) in a by 16 organization since all chips are either writing or
reading at any given time.
32K
X
8 CONFIGURATION
0,
,"""J I
0,
0,
rf===============~======~fi~:
....
'~~
'Icc CSII "os A'B Oos O,a Olll 038
SRD7M656-018
NOTES:
1. The chip selects are tied together in groups of two. The decoder uses the new higher order address pin (A 14 ) to determine which of the two banks of memory are enabled.
2. The two write enables are tied together for ease of layout. They could be controlled by the decoder similar to the chip selects but would save only a minimal amount of power
and add complexity to the layout.
64K X 4 CONFIGURATION
'''~
Vee CS'8 AoB AlB OOB O'B OHI O.
NOTES:
1. Each chip select is now controlled by the two higher order address pins A14 (necessary in 64K deep memory).
2. Again the two write enables are tied together for ease of layout (the megabit part will only have one write enable pin).
7-40
SRD7M656-019
FEATURES
DESCRIPTION:
• High-density 512K-bit CMOS static RAM module
• 64Kx8 (IDT7M812) or 64Kx9 (IDT7M912) configuration
• Fast access times
- Military: 55ns (max.)
- Commercial: 45ns (max.)
• Low power consumption
-Active 2.4W (typ. in 64K x 8 organization)
-Standby: 240jLW (typ. in 64Kx8 organization)
• Utilizes 8 (IOT7M812) or 9 (IDT7M912) IDT7187 highperformance 64Kxl CMOS static RAMs produced with
lOT's advanced CEMOS'· technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder
reflow process
• Available in 40-pin, 600 mil center sidebraze DIP, achieving
very high memory density
• Single 5V (±10%) power supply
• Dual Vee and GND pins for maximum noise immunity
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters as per
customer requirements
The IDT7M812/1DT7M912 are 512K-bit high-speed CMOS
static RAMs constructed on a multi-layered ceramic substrate
using 8 IDT7187 64Kxl static RAMs (IDT7M812) or 9 IDT7187
static RAMs (IDT7M912) in leadless chip carriers. Extremely high
speeds are achievable by the use of IDT7187s fabricated in lOT's
high-performance, high-reliability technology, CEMOS. This
state-of-the-art technology, combined with innovative circuit
design techniques, provides the fastest64K static RAMs available.
The IDT7M8121IDT7M912 are available with access times as
fast as 45ns commercial and 55ns military temperature range,
with maximum operating power consumption of only 5.9W
(IOT7M912, 64Kx9 option). The module also offers a standby
power mode of less than 2.5W (max.) and a full standby mode of
lW(max.).
The IDT7M8121IDT7M912 are offered in a high-density 40-pin,
600 mil center sidebraze DIP to take full advantage of the
compact IDT7187s in lead less chip carriers. The IDT7M912
(64K x 9) option can provide more flexibility in system application
for error detection, parity bit, etc.
All inputs and outputs of the IDT7M8121IDT7M912 are TTLcompatible and operate from a single 5V supply. (NOTE: Both
Vee pins need to be connected to the 5V supply and both GND
pins need to be grounded for proper operation.) Fully asynchronous circuitry is used requiring no clocks or refreshing for
operation and provides equal access and cycle times for ease of
use.
All lOT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883, Class B, making
them ideally suited to applications demanding the highest level
of performance and reliability.
PIN CONFIGURATION
GNO(1)
Vee(1)
Ao
AUi
A1
A14
Az
A13
A3
A12
A4
A11
Ao - A,s
ADDRESS
As
A6
A10
Ag
Do- D.
DATA INPUT
A7
00
As
Yo
01
Y1
02
Y2
D3
Va
04
Y4
05
06
Y5
V6
07
V7
Da/NCl21
PIN NAMES
Vo -
DATA OUTPUT
CHIP SELECT
WE
WRITE ENABLE
Vee
POWER
GND
GROUND
I
FUNCTIONAL BLOCK DIAGRAM
Ya/NC(2)
WE
v.
CS
Ci
=- Vee
GNO(1) -,c.;.;.._ _ _
(1)
SSD7M812-QOl
DIP
TOP VIEW
NOTES:
1. Both Vee pins need to be connected to the 5V supply, and both GND pins need
to be grounded for proper operation.
2. Pin 18 is D. and pin 23 is Y. in 64K x 9 (IDT7M912) option, and both 18 and 23
are Ne in 64K x 8 (IDT7M812) option.
SS07M812-002
CEMOS is a trademark of Integrated Device Technology. Incorporated.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1985 Integrated Device Technology, Incorporated.
JANUARY 1986
Printed in the US.A.
7-41
IDT7M81211DT7M912
512K (64K x 8-BIT or 64K x 9-Bm c:MOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
COMMERCIAL
MILITARY
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Terminal Voltage
with Respect
toGND
GRADE
Military
TA
Operating
Temperature
Oto +70
-55 to +125
°C
TalAs
Temperature
Under Bias
-10 to +85
-85 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
8
8
IqUT
DC Output Current
50
50
Cqmmercial
AMBIENT
TEMPERATURE
GND
-55°C to +125°C
OV
5.0V
O°C to +70°C
OV
5.0V
Vee
± 10%
± 10%
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN.
TYp.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
W
GND
Supply Voltage
a
a
a
V
mA
V,H
Input High Voltage
2.2
-
6.0
V
V,l
Input Low Voltage
-0.5(1)
-
0.8
V
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
NOTE:
1. V,L = -3.0V for pulse width less than 20ns.
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vee
= +5V ± 10%, T A = -55·C to +125·C and O·C to +70·C)
TEST CONDITIONS
MIN.
IDT7M912
TYp.ll) MAX.
MIN.
IDT7MB12
TYp.(1) MAX.
UNIT
Input Leakage Current
Vee = 5.5V; Y,N
=GND to Vee
-
-
20
-
-
20
p.A
Output Leakage Current
Vee = 5.5V
CS = V,H. VOUT = GND to Vee
-
-
20
-
-
20
p.A
lee1
Operating Power Supply Current
CS = V,l, Output Open
Min. Duty Cycle = 100%
-
540
1080
-
480
960
mA
lec2
Dynamic Operating Current
Min. Duty Cycle = 100%
Output Open
-
540
1080
-
480
960
mA
ISB
Standby Power Supply Current
CS;;'V,H
Min. Duty Cycle = 100%
-
270
450
-
240
400
mA
ISB1
Full Standby Power Supply
Current
CS ;;, Vee - 0.2V
V,N ;;' Vcc - 0.2V or S; 0.2V
-
0.2
180(2)
-
0.05
160(2)
mA
10l = lamA, Vcc = Min.
-
0.5
0.4
-
V
-
-
0.5
10l = 8mA, Vce = Min.
-
0.4
V
2.4
-
-
2.4
-
-
V
IILlI
IILOI
VOL
Output Low Voltage
VOH
Output High Voltage
10H = -4mA, Vee
=Min.
NOTES:
1. Typical limits are at Vee = 5:0\1, +?5°C.
2. ISB1 (max.) of IDT7M8121912 at commercial temperature = 80mA/90mA.
7-42
IDT7M8121IDT7M9I2
512K (64K x 8-BIT or 64K x 9-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
+5V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GNDt03.0V
10ns
1.5V
1.5V
See Figures 1 and 2
+5V
DOUT-~---+
DOUT-~---+
Figure 1. Output Load
Figure 2. Output Load
(for tHZ' t LZ' t wz, and tow)
·Including scope and jig.
AC CHARACTERISTICS
SYMBOL
(Vee
=5V ±10%. TA =-55·C to +125·C and O·C to +70·C)
PARAMETER
IDT7M9I2S45
IDT7M812S4S
COM'LONLY
MIN.
MAlt
IDT7M9I2S55
IDT7M812S15
IDT7M912S15
IDT7M812886
IDT7M912S85
IDT7M812S85
MIN.
MAlt
MIN.
MAX.
MIN.
MAX.
IDT7M9I2S100
IDT7M812S100
MIL. ONLY
MIN.
MAlt
UNIT
READ CYCLE
-
t Re
Read Cycle Time
45
55
-
65
tM
Address Access Time
-
45
-
55
tACS
Chip Select Access Time
-
45
-
55
-
-
85
-
100
-
65
-
85
-
100
ns
65
-
85
-
100
ns
5
5
-
5
-
ns
tOH
Output Hold from Address Change
5
-
Chip Selection to Output In Low Z
5
-
5
tLZ
5
-
5
-
5
5
-
ns
ns
tHZ
Chip Deselectlon to Output in High Z
-
30
-
30
-
30
-
40
-
50
ns
t pu
Chip Selection to Power Up Time
0
0
-
0
-
0
-
0
-
ns
tpo
Chip Selection to Power Down Time
-
35
-
35
-
35
-
40
-
50
ns
-
55
-
65
85
-
100
-
ns
-
-
50
55
-
85
75
-
50
-
55
-
-
65
-
75
10
-
45
-
0
WRITE CYCLE
twe
Write Cycle Time
45
tew
Chip Selection to End of Write
40
tAW
Address valid to End of Write
40
-
ns
-
ns
10
-
ns
55
-
ns
0
-
ns
45
-
ns
5
-
5
35
-
40
0
-
0
-
25
-
30
-
35
5
-
5
-
-
5
-
5
-
5
-
ns
Write Enable to Output in High Z
0
30
0
30
0
35
0
40
0
50
ns
Output Active from End of Write
0
-
0
-
0
-
0
-
0
-
ns
t AS
Address Setup Time
5
twp
Write Pulse Width
30
tWR
Write Recovery Time
0
tow
Data valid to End of Write
25
tOH
Data Hold Time
twz
tow
7-43
fI
IDT7M8121IDT7M9I2
5121< (84K x 8-BIT or 84K x 9-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO.1 (1,2)
_ _Ft;::=:====:!",c===='S)~j_
ADDRESS - - - - -....
~:I.
L-
i
DATA OUT
PREVIOUS DATA
VALI~OH
=-1 X X )K========DA=~="=VA=L=ID======
TIMING WAVEFORM OF READ CYCLE NO.2(1,3)
Ci
b
"'cIS)'---------.,1-~
~....'·'-·1,..---"
I~s----t ,.----.'I--'. .H. -__,.
Z(4)
___
__
~~OUT --ii-----~
~~_~DA~~~~:"~LI~D
.. ~"1
vceu= ~8-
-
-1
-
~
~ .. --j'_GH_IM_P£_DA_NC_E
~
NOTEI:
1.
WE Is high for READ cycle.
2.
Cs Is low for READ cycle.
3. Address valid prior 10 or colncldenl wilh
Cs lransltion low.
4. Transllion Is measured ±200mV from sleady state vollage wilh specified loading In Figure 2. This parameter is sampled, noll00% lesled.
5. All READ cycle limings are referenced from Ihe lasl valid address 10 Ihe first lransililioning address.
TIMING WAVEFORM OF WRITE CYCLE NO.1' (WE CONTROLLED)(1)
I
S
lew
~\\
f - lAs
--1'\:
.~\\\\' .\\\\
..
IWA-
'AW
IwP
f=
OATAIN _______...;.___.....
DATA OUT
.
'we
ADDRESS -I~
~
!---'DHDATA IN VALID I
tDw------
~tOW(Z.4)---+
~--
DATA UNDEFINED
HIGH IMPEDANCE
7-44
IDT7M8121IDT7M912
512K (64K x 1I-81T or 64K x 9-Bln CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
1 - - - - - - - - I W CI3}-------.-1
ADDRESS
...-r___ID_W_____.l:-IDH
DATA IN
DATA IN VALID
~
DATA UNDEFINED
DATA OUT
HIGH IMPEDANCE
NOTES:
1. CS or WE must be high during address transitions.
2. If
CS goes high simultaneously with WE high, the output remains in a high Impedance state.
3. All write cycle timings are referenced from the last valid address
to the first transitioning address.
4. Transition is measured ±200mV from steady state voltage specified loading in Figure 2. This parameter is sampled. not 100% tested.
TRUTH TABLE
CAPACITANCE (TA = +2SoC. f = 1.0 MHz)
MODE
CS
WE
OUTPUT
POWER
Standby
H
X
High Z
Standby
Read
L
H
o Out
Active
Write
L
L
High Z
Active
SYMBOL
TYP.
UNIT
C IN
Input Capacitance
ITEM
CONDITIONS
VIN=OV
80
pF
C OUT
Output Capacitance
VOUT=OV
15
pF
NOTE:
This parameter is sampled and not 100% tested.
I
7-45
FEATURES:
DESCRIPTION:
• High-density 1024K-bit (128K x 8-bit) CMOS static RAM
modules with registered/buffered/latched addresses
and I/Os
• Fast access times: 75ns max. commercial and military
• Low-power consumption (typ.): active 980mW; standby
150mW; full-standby 1.6mW
• Low input capacitance (typ.): input 20pF; output 25pF
The IDT7M824 family is a set of 1024K-bit (128K x 8-bit) highspeed CMOS static RAM modules with registered/buffered/
latched addresses and I/Os. They are constructed on co-fired,
multi-layered ceramic substrates with sidebrazed leads using 16
IDT71981 (16K x 4) static RAMs,lDT logic devices, and decoupling
capacitors. Devices in lead less chip carriers are mounted top and
bottom for maximum density.
-Extremely high speeds are achievable by the use of IDT71981s
and logic devices fabricated in IDT's high-performance, highreliability technology, CEMOS'". This state-of-the-art technology,
combined with innovative circuit design techniques, provides the
fastest circuits possible. The IDT7M824 has access times of 75ns
(max.) over commercial and military temperature ranges, but it
can be operated with cycle times as fast as 50ns if skewed clocks
are used.
Designing with this device can be very flexible because of such
features as module select output and clock enables on all
registers, registered write enable and 8-bit separate inputs and
outputs. Because of the proprietary IDT49CB01, the modules are
cascadable in terms of depth. The write enable can be turned off
when the module is de-selected. Immunity to noise has been
extended with such features as 8-bit separate inputs and outputs;
addresses, inputs, and outputs on separate clocks; internal
decoupling capacitors; five ground pins; and five Vcc pins.
The semiconductor components used on all IDT military
modules are 100% processed to the test methods of MIL-STD-883,
Class B. In addition IDT military modules are qualified to requirements patterned after MIL-STD-883, Method 5005 making them
ideally suited to applications demanding the highest level of perfcirmance and reliability.
• High output drive (min.): IOL =32mA; IOH =-15mA
• 64-pin, 900 mil center sidebraze DIP with LCCs on both
sides, achieving very high memory density
•
•
•
•
Module select output
Separate inputs and outputs
Clear data and clock enables on all registers
Addresses, inputs and outputs on separate clocks or latch
enables
• Registered write enable
• Internal bypass capacitors for minimizing power supply
noise
• TTL compatible; single 5V (±10%) power supply
• Five GND pins for maximum noise immunity, 5 Vee pins
• Military grade module available with semiconductor
components 100% manufactured and screened to
MIL-STD-883, Class B
PIN CONFIGURATION
GNO
Ao
A,
A2
A3
Vec
As
A,o
A"
A'2
GNO
Vcc
A4
As
As
A'3
A'4
A'5
A'6
A7
GNO
As
WE
CS,
CS2
GNO
CS 3
GNO
GNO
CLRDIN
CPDINILEOIN
GNO
ENfiiAII'mmi
DID
Oil
012
013
014
015
016
017
GNO
PRODUCT SELECTOR GUIDE
DATA INPUT
" OUTPUT FEATURE
Vcc
LE/CP
REG/LAT
CE/GNO
0E3
Yo
~/PREOOUT
CPOOUTILEDOUT
CLRDOUT
DE.
DE,
Vcc
SEL
DOD
DO,
ADDRESS
REGISTERED
LATCHED
Input - Registered
Output - Registered
IDT7M824SA
IDT7M824SE
Input - Registered
Output - Latched
IDT7M824SB
IDT7M824SF
Input - Latched
Output - Registered
IDT7M824SC
IDT7M824SG
Input - Latched
Output - Latched
IDT7M824SD
IDT7M824SH
NOTE:
All Vcc pins (33, 43. 49, 54, 59 and 64) need to be connected to the 5V supply.
and all GND pins (1. 6, 11. 16. 18, 19, 22, and 32) need to be grounded for
proper operation.
002
003
004
005
006
007
Vcc
CEMOS is • trademark of Integrated Device Technology, Inc.
DSP7M824S-Q02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 1986
Printed in U.S.A.
111986 Integrated Device Technology, Inc.
7-46
IDT7M824S 1 MEGABIT (128K x 8-BIT)
REGISTERED/BUFFERED/LATCHED CMOS STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
-----------------
14 BIT
'377 REGISTERS
OR
'373 LATCHES
Ao-A'3 ~----7'1~4,-----IDo-13
CE/DE
I
I
I
I
00-131---~714.-----~---t;-;"'==~-----,
LE/CP
RAM 2
RAM 10
RAM 3
00
0,
O.
03
a:
III
C
0
(J
III
C
O.
O.
O.
0,
III
Il.
~
CD
~
CE/GND »--4-t--+-1---'
2
RAM 4
RAM 12
RAM 5
RAM 13
RAM 6
RAM 14
RAM 7
6
RAM
SEL
I~!:.E£T
RAM 15
RAM 16
RAM 8
LE/CP --~-!---H
RAM 11
°0_3
YO- 3
4
4
D O_3 YO-,
4
-----
REG/LAT ---+-+I-------<~-____,
(377/373)1
wE---n+1rl
WEI
I
I
I
____ II
Yo-,
IDT39C825
REG OR
DE, IDT39C845 CLR
DE.
LATCH CPILE
DE,
EN/PRE
8
YG-'
8
°0_7
IDT39C825
REG OR
DE, IDT39C845
DE. LATCH
CE,
CLR
CLRDOUT
CP/LE
~~gg~i'
~______~~O-'~-~EN~/~P~RE~~ENDOU~
Do-,
PREDOUT
ENDIN/PREDIN
CPO IN/LEDIN
CLRDIN
01 0_7
DOo-,
7-47
fI
IDT7M824S 1 MEGABIT (128K x 8-BIT)
REGISTERED/BUFFERED/LATCHED CMOS STATIC RAM MODULES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN NAMES
Ao- A,s
Addresses
01 0 - 01 7
Data input
00 0 - 00 7
Data output
CLRDIN
Data input latch/register .clear
CPDIN/LEDIN
Data input register clock/latch enable
ENDIN/PREDIN
Data input register clock enable/
latch preset
OE,. OE 2 • OE 3
Output enable
CPDOUT/LEDOUT
Data output register clock/latch enable
ENDOUT/PREDOUT
Data output register clock enable/
latch preset
CS,. CS 2 & CS 3
Chip select
WE
Write enable
SEL
Select output
LE/CP
Latch enable/clock pulse control input
CE/GND
Clock enable/ground
REG/LAT
Register/latch (low active) input control
Vee
Power
GND
Ground
7-48
FEATURES:
DESCRIPTION:
• High-density 256K (32K x 8-bit) CMOS static RAM module
• Equivalent to JEOEC standard for future monolithic 32K x 8
static RAMs
The 10T7M856 is a 256K (32,768 x 8-bit) high-speed static RAM
constructed on a co-fired ceramic substrate using four IOT7198
(16,384 x 4) static RAMs in leadless chip carriers. Functional
equivalence to proposed monolithic 256K static RAMs is
achieved by utilization of an on-board decoder, used as an
inverter, that interprets the higher order address A14 to select two
of the four 16K x 4 RAMs. Extremely fast speeds can be achieved
with this technique due to use of 64K static RAMs and the
decoder fabricated in lOT's high-performance, high-reliability
CEMOS technology.
The I OT8M856 is available with maximum access times as fast
as 40ns for commercial and 55ns for military temperature ranges,
with maximum power consumption of only 2 watts. The circuit
also offers a reduced power standby mode. When CS goes high,
the circuit will automatically go to a standby mode with power
consumption of only 1.1mW (max.). Substantially lower power
levels can be achieved in a full standby mode (440mW max.).
The IDT8M856 is offered in a 28-pin, 600 mil center sidebraze
01 P. This provides four times the density olthe IOT7M864 (8K x 8
module) in the same socket with only minor pin assignment
changes. In addition, the JEOEC standard for 256K monolithic
pinouts has been adhered to, allowing for compatibility with
future monolithics.
All inputs and outputs of the IOT7M856 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous
circuitry is used requiring no clocks or refreshing for operation,
and provides equal access and cycle times for ease of use.
Alii OT military module semiconductor components are 100%
processed to the test methods of MIL-STO-883 Class B, making
them ideally suited to applications demanding the highest level
of performance and reliability.
• High-speed - 40ns (max.) commercial; 55ns (max.) military
• Low-power consumption; typically less than 1W operating,
less than 1mW in standby
• Utilizes 10T7198s-high-performance 64K static RAMs
produced with advanced CEMOS'· technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder
reflow process
• Pin compatible with IOT7M864 (8K x 8 SRAM module)
• Offered in the JEOEC standard 28-pin, 600 mil wide ceramic
sidebraze 01 P
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STO-883, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters as per
customer requirements
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
AO-A'3---..-----------,
PIN NAMES
A14 ,
I/o'-1/04~~I§~~~~~~~~l
1/0.-1/0.
AO- A14
ADDRESSES
WE
1/01 - I/0a DATA INPUT/OUTPUT
A6
As
A4
4
5
CS
CHIP SELECT
Vec
POWER
WE
WRITE ENABLE
OE
OUTPUT ENABLE
GND
GROUND
I
OE
A'4
CS - + - . - - - - '
DIP
TDPVIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
JULY 1986
Printed in the U.S.A.
7-49
IDT7M856S 256K (32K
x a-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
VTERM
RATING
COMMERCIAL
Terminal Voltage
with Respect
toGND
Operating
Temperature
TA
-0.5 to +ZO
o to +70
RECOMMENDED OPERATING CONDITIONS
MILITARY
-0.5 to +7.0
-55 to +125
SYMBOL
UNIT
Vee
GND
V,H
V,L
V
°C
PARAMETER
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
MIN.
4.5
0
2.2
-0.5(1)
TYP.
5.0
MAX.
5.5
0
6.0
0.8
0
-
-
UNIT
V
V
V
V
NOTE:
1. V1l min = -3.0V pulse width less than 20n5.
TBIAS
Temperature
Under Bias
-10 to +85
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
4.0
4.0
W
lOUT
DC Output Current
50
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Vee
=5V ± 10%, TA = -55°C to +125°C and O°C to +70°C)
MIN.
TYP.(!)
MAX.
UNIT
Ilul
Input Leakage Current
Vee = 5.5V, V,N = OV to Vee
-
-
15
p.A
IILol
Output Leakage Current
Vee = 5.5V, CS = V,H, VOUT = OV to Vee
-
-
15
p.A
leel
Operating Power Supply Current
CS = VII", Output Open, Vee = 5.5V, f = 0
-
190
380
mA
-
190
380
mA
90
200
mA
0.2
80(2)
mA
-
0.5
0.4
V
-
V
SYMBOL
PARAMETER
TEST CONDITIONS
lee2
Dynamic Operating Current
CS = V,L, Output Open, Vee = 5.5V, f = f Max.
ISB
Standby Power Supply Current
CS;o, V,H (TTL Level), Vee = 5.5V, Output Open
ISBI
Full Standby Power Supply Current
CS;o, Vee - 0.2V (CMOS Level)
v,N;o, Vee - 0.2V or OS; 0.2V
VOL
Output Low Voltage
10L = 10mA, Vee = 4.5V
IOL = 8mA, Vee = 4.5V
-
VOH
Output High Voltage
IOH = -4mA, Vee = 4.5V
2.4
NOTES:
1. Vee
=
5V. TA = +25°C
2. 'sa1 at commercial temperature = 60mA.
7-50
IDT7M856S 256K (32K x 8-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
q
+5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
480!1
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
DOUT-
255!1
DOUT
30pF*
~
255!1
480!1
5pF"
SRD7198S/L-006
SRD7198S/L-OOS
Figure 2. Output Load
(lor tHZ' t lZ' Iwz, and tow)
Figure 1. Output Load
"Including scope and jig
AC CHARACTERISTICS
SYMBOL
(Vee
=5V ±10%, TA =OOG to +70o G)
PARAMETER
IDT7M856S40
MIN. MAX.
IDT7M856S50
MIN.
MAX.
IDT7M856S60
MIN.
MAX.
IDT7M856S70
MIN. MAX.
IDT7M856S85
MIN.
MAX.
UNITS
READ CYCLE
t RC
Read Cycle Time
40
-
50
-
60
-
70
-
85
-
ns
tAA
Address Access Time
-
40
-
50
-
60
-
70
-
85
ns
t ACS
Chip Select Access Time
-
40
-
50
-
55
-
65
-
80
ns
tClZ
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
30
-
35
-
40
-
45
-
55
ns
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tCHZ
Chip Select to Output in High Z
-
15
-
15
-
20
-
25
-
30
ns
tOHZ
Output Disable to Output in High Z
-
15
-
15
-
20
-
25
-
30
ns
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
-
5
-
ns
tpu
Chip Select to Power Up Time
0
-
0
-
0
-
0
-
0
-
ns
tpo
Chip Deselect to Power Down Time
-
40
-
50
-
60
-
70
-
85
ns
WRITE CYCLE
twc
Write Cycle Time
40
-
50
-
60
-
70
-
85
-
ns
tcw
Chip Select to End of Write
35
-
45
-
50
-
60
-
75
-
ns
tAW
Address Valid to End or Write
35
-
45
-
50
-
60
-
75
-
ns
tAS
Address Setup Time
5
-
5
-
10
-
10
-
10
-
ns
twp
Write Pulse Width
30
-
45
-
50
-
ns
0
0
-
40
Write Recovery Time
-
35
tWR
0
-
0
-
0
-
ns
tWHZ
Write Enable to Output High Z
-
20
-
20
-
25
-
30
-
40
ns
tow
Data to Write Time Overlap
20
-
20
-
25
-
30
-
40
-
ns
tOH
Data Hold from Write Time
5
-
5
-
5
-
5
-
5
-
ns
tow
Output Active from End of Write
5
-
5
-
5
-
5
-
5
-
ns
7-51
fI
IDT1M856S 256K (32K x 8-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vee = SV ±10%. TA = -SS·C to +12S·C)
SYMBOL
IDT7M856S55
MAX.
MIN.
PARAMETER
IDT1M856S65
MIN. MAX.
IDT1M656S75
MIN. MAX.
IDT1M856S90
MIN. MAX.
IDT1M856S100
UNITS
MIN.
MAX.
READ CYCLE
tRC
Read Cycle Time
55
-
65
-
75
-
90
-
100
-
tAA
Address Access Time
55
-
65
-
75
-
90
-
100
ns
t ACS
Chip Select Access Time
-
55
-
55
-
65
-
80
-
90
ns
ns
ns
tCLZ
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
tOE
Output Enable to Output Valid
-
40
-
45
-
50
-
60
-
65
ns
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tCHZ
Chip Select to Output in High Z
-
35
-
40
ns
25
-
30
20
-
25
Output Disable to Output in High Z
-
20
tOHZ
30
-
35
-
40
ns
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
-
5
-
ns
tpu
Chip Select to Power Up Time
0
-
0
-
0
-
0
-
0
-
ns
tpo
Chip Deselect to Power Down Time
-
55
-
65
-
75
-
90
-
100
ns
75
-
100
-
ns
75
-
85
-
ns
75
-
85
-
15
0
-
15
0
-
90
65
WRITE CYCLE
twe
Write Cycle Time
55
-
65
tew
Chip Select to End of Write
50
-
55
tAW
Address Valid to End of Write
50
-
55
-
t AS
Address Setup Time
5
-
10
-
10
45
-
45
0
twp
Write Pulse Width
40
tWR
Write Recovery Time
0
-
65
50
ns
ns
55
-
0
-
ns
ns
tWHZ
Write Enable to Output High Z
-
25
-
30
-
40
-
50
-
50
ns
tow
Data to Write Time Overlap
25
30
-
45
-
ns
5
5
-
45
Data Hold from Write Time
5
-
5
Output Active from End of Write
5
5
-
5
-
5
-
ns
tow
-
35
tOH
-
TIMING WAVEFORM OF READ CYCLE NO.
5
5
1(1)
~-------------t~--------------~
ADDRESS
1-----------tACS------t---~
1--------tCLZ(5)--------t
DATAOUT - - - - - - - - - - - - - - {
7-5:1
ns
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT7M856S 256K (32K x 8-BIT) CMOS STATIC RAM MODULE
TIMING WAVEFORM OF READ CYCLE NO.
2(1,2,4)
~~~---------------tRC-----------------~~
ADDRESS
DATA OUT
- -f~ :~-= _-= ~-=-=~-t-O- H~=-~t-A _-_-= _-= ~- - - - - - - -.~-,-----'t-tO-H---PREVIOUS DATA VALID
------------------~~~~
DATA VALID
SI-1D719BS/L-Q06
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
SR07198S/L-009
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS : ;: : V1L.
3. Address valid prior to or coincident with CS transition low.
4. OE =V ,L.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% teSted.
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)
~-------------twc------------~~
ADDRESS
I
I--------tcw--------J
DATA OUT -7-7-7-7~~~~~~---------------_r---------
itOW-+t---tDH--j
DATAIN
---------------(L
JXXX
SRD7198S/L-010
7-53
IDT7M856S 256K (32K x a-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1,6)
~-------------twc--------------~
ADDRESS
~------~w--------~
(7)
DATAOUT ~~~?-~~~?-?-?-?-?-?-~----------+----------{
tDH--j(B)
DATA'N
-----------------------------«
SR07198S/L-011
NOTES:
1. WE or
CS must be high during all address transitions.
CS.
2. A write occurs during the overlap (t wp) of a low
3. tWA is measured from the earlier of C§ or WE going high to the end of the write cycle.
4. During this period, I/O pins Bre in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the
6.
CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
OE is continuously low (OE = V,L).
7. DATA OUT is the same phase of write data of this write cycle.
8. If Os is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
TRUTH TABLE
MODE
Standby
Address Access Time
Capacitive Load
CS
OE
OUTPUT
POWER
WE
H
X
X
HighZ
Standby
Read
L
L
H
DOUT
Active
Read
L
H
H
HighZ
Active
Write
L
X
L
D'N
Active
1.2
va.
T~ = +25'C
./
V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
SYMBOL
PARAMETER(')
C 'N
Input Capacitance
C OUT
Output Capacitance
CONDITIONS
TYP.
UNIT
V,N = OV
35
pF
VOUT = OV
26
pF
./
V
o
NOTE:
1. This parameter is sampled and not 100% tested.
50
100
c.paclave Load (pI)
SR07M65&-016
7-54
• Equivalent to JEDEC standard 8K x 8 monolithic RAM
• 8,192 x 8 CMOS static RAM module complete with decoder
and decoupling capacitor
• High-speed 65 (commercial only) 75/85/120/150/200ns
(equal access and cycle times)
• Low power consumption, less than 1 watt maximum
• Two pinout options (64K EPROM & 64K static RAM)
• Utilizes IDT6116s - high performance 16K RAMs produced
with advanced CEMOS'"I technology
• CEMOS I process virtually eliminates alpha particle soft
error rates (with no organic die coating)
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Military modules available with semiconductor components
100% screened to MIL-STD-883 Class B
The IDT7M864/IDT8M864 are available with access times as
fast as 65ns for commercial and 75ns for military temperature
ranges, with maximum power consumption of only 990mw' The
circuit also offers a reduced power standby mode. When CS ,
high and/or CS2 (7MB64) goes low, the circuit will automatically
go to, and remain in, a standby mode as long as these conditions
are held. In the standby mode, the module consumes less than
440mW. Substantially lower power levels can be achieved in the
ISB1 mode (less than 20mW max.) and 2V data retention mode
(less than 3mW max.) - see "DC Characteristics" and "Data
Retention Characteristics" for details.
Pinout of the IDTBM864 is equivalent to the 64K EPROMs (no
connect on pin 26), ideal for applications requiring easy microcode changes during prototyping. The IDT7M864's pinout is
compatible with monolithic 64K static RAMs (CS 2 on pin 26).
All inputs and outputs of the IDT7M864/IDT8MB64 are TTLcompatible and operate from a single 5V supply, thus simplifying
system designs. Full asyncronous circuitry is used, requiring no
clocks or refreshing for operation, and provides equal access and
cycle times for ease of use.
AIiIDT module semiconductor components are processed in
compliance to the test methods of MIL-STD-883, as shown on
back of data sheet, making them ideally, suited for applications
demanding the highest level of performance and reliability.
DESCRIPTION:
The IDT7M864/IDT8M864 are 64K (8,192 x 8 bit) high speed
static RAMs constructed on a ceramic substrate using 41DT6116
(2,048 x 8) static RAMs in lead less chip carriers. Functional
equivalence to ·a monolithic 64K static RAM is achieved by
utilization of an on-board decoder circuit that interprets the
higher order addresses A" and A'2 to select one of the four 2Kx8
RAMs. Extremely fast speeds can be achieved with this
technique due to use of the IDT6116 fabricated in IDT's high
performance, high-reliability technology - CEMOS'"I. This
state-of-the-art technology, combined with innovative circuit
design techniques, provides the fastest 16K static RAMs
available.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
r----Pin #1 Identifier-,
r;:w====;l
AO·A10
NC
2S
vcc
NC
An
27
WE
An
27
vee
WE
A7
26 CS2
A7
26
NC
25
A.
25
A.
A.
As
A4
A3
A2
A,
A.
1/0 1
- - - - - - 24
,. DO
6
"
11°2 12
1/03 13 [
GND 14 [
0
A.
23 A11
As
A4
liE
A3
21 AiD
CS,
A2
A,
19 110.
A.
,D
18 1/07
1/0 1
",2
22
20
A.
~-----
6
17 IIOe
1/0 2
16 1/05
1103 '3 [
15 1I04
GND 14 [
7M864
DO
0
28
110, ·110.
WE
liE
f--
A 10
20 CS1
IOT6116
2KxB
f- ~ ;T~~I~
1-- ~ ;T~~I~
RAM
RAM
CS
CS
19 1/0.
18 1/07
17 IIOe
.----
16 1/05
L-
15 1/04
L--
8M864
'-----
PIN NAMES
Ao-A,.
ADDRESS
WE
WRITE ENABLE
1/0,-1/0.
DATA INPUTIOUTPUT
OE
OUTPUT ENABLE
CS"CS,
CHIP SELECT
GND GROUND
Vee
POWER
CEMOS is a trademark of Integrated Device Technology, Inc.
-
--
A.
23 A"
22 OE
21
-
~ lOT.".
2Kx8
24
CS1 CSt -
L-
'-----
r-J
AU . Au
~8coder
(7M864 only)
'---
MILITARY AND COMMERCIAL TEMPERATURE_ RANGES
7-55
~
L-
IDTSllS
2KxS
CMOS
STATIC
RAM
IDTS"S
2Kx8
CMOS
STATIC
RAM
T
r
JUNE 1985
fI
IDT7M864/1DT8M864 64K (8K x 8) CMOS STATIC RAMPAK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING
CONDITIONS
TRUTH TABLE
MODE
(TA
cs,
Cs,
OE
WE
1/0 OPERATION
= -55·C to
+ 125·C and O·C to + 70·C)
Standby
H
X
X
SYMBOL
MIN.
TYP.
MAX.
UNIT
X
L
X
X
X
HighZ
Standby
HighZ
Supply Voltage
4.5
5.0
5.5
V
Read
L
H
L
H
Supply Voltage
0
0
0
V
Read
L
H
H
H
DoUT
HighZ
Vee
GND
Input High Voltage
6.0
V
L
H
X
L
DIN
Input Low Voltage
2.2
-0.5 •
3.5
Write
VIH
VIL
CL
Output Load
TTL
'V IL min
PARAMETER
-
-
-
Output Load
-
=-1.0V for pulse width less than 2Ons.
.65
V
100
pF
1
-
DC ELECTRICAL CHARACTERISTICS (Vcc=5V ± 10%, TA= -55·C to + 125·C and O·C to + 70·C)
SYMBOL
PARAMETER
IDT7M86418M864
Typ.(l) MAX.
MIN.
TEST CONDITIONS
UNIT
ICCl
Dynamic Operating Current
CS, " VIl> CS, ~ VIH, Output Open
Min. Duty Cycle = 100%
ISB
Standby Power Supply Current
CS, ~ V IH , or CS,,, V,L
-
ISBl
Full Standby Power Supply
Current
CS, ~ Va:;- 0.2V, andlor CS," 0.2V
Y,N ~ Vcc - 0.2V or" 0.2V
-
.016
3.6(2)
VOL
VOH
Output Low Voltage
10L = 4mA
-
V
Output High Voltage
10H = -lmA
2.4
-
0.4
-
V
Ilul
Input Leakage Current
Vcc = 5.5V, VIN = OV to Vcc
IILOI
Output Leakage Current
OE or CS, ~ VIH, or cs, " VIl> VOUT = OV to Vee
Icc
Operating Power. Supply Current
-
15
15
~A
65
180
rnA
65
180
rnA
20
80
rnA
mA
~A
1. Vcc-5V, TA =25°C
2. 'SBlmax at commercial temperature = 1.0 mA
ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
VTERM
RATING
Terminal Voltage with
Respect to GND
COMMERCIAL
MILITARY
UNIT
-0.5 to + 7.0
-0.5 to +7.0
V
o to
TA
TBIAS
-55 to + 125
·C
Temperature Under Bias
-10 to +85
-65to+135
·C
TSTG
Storage Temperalure
-55to +125
-65 to +150
·C
Pr
Power Dissipation
4.0
4.0
W
lOUT
DC Output Current
50
50
rnA
Operating Temperature
+ 70
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This Is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated In the operational sec~
tlons of this specification is not Implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
AC TEST CON DITIONS
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
GND to 3.0V
Input Pulse Levels
10ns
Input Rise and Fall Times
Input and Output Timing Reference
1.5V
Levels
Output Load
1 TTL Gate and CL = 100pF
(including scope and jig)
SYMBOL
ITEM
CONDITIONS
C'N
Input Capacitance
VIN=OV
COUT
Output Capacitance
VOUT=OV
NOTE: This parameter is sampled and not 100% tested.
7-56
MAX.
28
UNIT
33
pF
pF
IDT7M864/1DT8M864 64K (8K x 8) CMOS STATIC RAMPAK
AC ELECTRICAL CHARACTERISTICS (Vcc=5V
SYMBOL
TEMPERATURE RANGES
± 10%, TA= -55·Cto +125·Cand O·C to +70·C)
IDT7MI
IDT7MI
8M864L65
8M864L75
COMMERCIAL
ONLY
MIN. MAX. MIN. MAX.
PARAMETER
C9M~ERC;:IAL
MILiTARY: AND
IDT7MI
8M864L120
IDT7MI
8M864L150
IDT7MI
8M864L200
MAX.
MIN.
MIN.
MAX.
MIN.
200
IDT7MI
8M864L85
UNIT
MIN.
MAX.
MAX.
READ CYCLE
t AC
Read Cycle Time
65
-
75
-
85
-
120
-
150
-
-
ns
tAA
Address Access Time
-
65
-
75
-
85
-
120
-
150
-
200
ns
tACS
Chip Select Access Time
-
-
75
-
85
-
120
-
150
-
200
ns
tCLZ
Chip Selection to Output in Low Z
5
65
-
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
50
-
55
-
65
-
65
-
80
-
100
ns
tOLZ
Output Enable to Output in Low Z
0
-
0
-
0
-
0
-
0
-
0
-
ns
tCHZ
Output Deselection to
Output in High Z
-
40
-
50
-
55
-
70
-
70
-
80
ns
tOHZ
Chip Disable to Output in High Z
-
30
-
35
-
40
-
40
-
40
-
50
ns
tOH
Output Hold from Address Change
0
-
0
-
0
-
0
-
0
-
0
-
ns
85
-
120
-
150
-
ns
80
-
100
120
-
ns
85
-
100
120
20
70
10
10
-
ns
15
-
200
65
WRITE CYCLE
twc
Write Cycle Time
65
-
75
tcw
Chip Selection to End of Write
55
65
tAW
Address Valid to End of Write
60
-
70
-
t AS
Address Setup Time
10
-
15
-
15
-
twp
Write Pulse Width
40
-
45
-
55
-
55
tWA
Write Recovery Time
5
-
5
-
10
-
10
-
tOHZ
Output Disable to Output in High Z
-
30
-
35
-
40
-
40
-
40
-
50
ns
tWHZ
Write to Output in High Z
0
35
0
40
0
50
0
50
0
60
0
ns
tow
Data to Write Time Overlap
25
-
30
30
-
35
-
40
Data Hold from Write Time
5
-
10
10
-
30
tOH
10
-
10
-
ns
Output Active from End of Write
0
-
0
0
-
0
-
0
-
10
tow
-
60
-
5
-
ns
70
TIMING WAVEFORM OF READ CYCLE NO.1 (1.2.4)
t=~IRC~c
iLd,~~·'.......--i XX
Add....
~
•....... 0.,. V."d
Oat,Out
TIMING WAVEFORM OF READ CYCLE NO.
0.,. V.lld
2(1,3)
TIMING WAVEFORM OF
READ CYCLE NO. 3(1.3,4)
NOTES:
,. WE is high for READ cycle.
_
2. Device is continuously selected, CS1 =V1l • CS2 =V1H (7M864 only).
3. ~dress valid prior to or coincident with CS1 transition low, CS 2 transition high (7M864 only).
4. OE = V'L'
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. For any given speed grade, operating voltage, and temperature, tCHZ will be less than or equal to tell'
7-57
20
90
ns
ns
ns
ns
IDT7MS64/1DTSMS64 64K (SK x S) CMOS STATIC RAMPAK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE CYCLE 211,6)
TIMING WAVEFORMS
OF WRITE CYCLE 1(1)
'we
tWA(3)
III
\\\\
_ _ _ _ k. _ _ _
~
\ \ \ 1\ \ \ \ '"
".
III IIII
(7M864 only)
".
IIIII
(TM864 only)
-I.-',+~.L....L-I.-'
\\\\\
'".
-I'"
\\\\\
I-/
/
10HZ
j
~
(4. ' "
1_--twpI2)--~
/./1
____ tow___.__..._
NOTES: 1. WE or
_tDH_
cs must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS" or high CS, (7M864 only) and a low WE.
3. tWR is measured from the earlier of CSt or WE going high or CS2 going low to the end of write cycle.
4. During this period, 110 pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CSt low transition or CS2 high transition occurs simultaneously with the WE low transitions or after the WE transition, outputs
remain in a high impedance state.
6. OE is continously low (OE = V,u.
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CS, is low or CS2 is high during this period, ItO pins are in the output state. Then the data input signals of opposite phase to the outputs
must not be applied to them.
10. Transition is measured ± 500mV from steady state. This parameter is sampled and not 100% tested.
LOW Vee DATA RETENTION CHARACTERISTICS (TA = -55°e to + 125°e and ooe to + 70°C)
SYMBOL
PARAMETER
TEST CONDITION
MIN.
V OA
Vcc for Data Retention
2.0
ICCOA
Data Retention Current
-
tCOA
Chip Deselect to Data Retention Time
tA
Operation Recovery Time
CS,,, Vcc - 0.2V. CS, ... 0.2V
NOTES: 1. TA =25"C
2. at Vcc = 2.0V
V'N"VCC -0.2Vor';0.2V
3. atVcc=3V
4. tAC = Read Cycle Time
LOW Vee DATA RETENTION WAVEFORM
ICDR_
VOR
* Low Vec data retention achieved by the indicated
CS, waveform or CS2 waveform.
7-58
Typ.ll)
-
-
2.0(2)
4.0(3)
0
t Ac (4)
-
MAX
COMM.
350(2)
500(3)
-
MAX.
MIl.
1200(2)
1800(3)
UNIT
V
I'A
-
ns
-
ns
IDT7M864/IDTBM864 64K 18K x 8) CMOS STATIC RAMPAK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NORMALIZED TYPICAL PERFORMANCE CHARACTERISTICS
1.6
1.6
TA=25"C
Vcc =5.5V
1.4
./
V
~
0
"
1.0
.l'
0.8
/'
V"
./'
:;;
.~ 1.2
~0
./
~
"
.l'
1.4
4.75
4.5
:;;
~ 1.2
"-
"'-
1.0
"ii
~
5.0
5.25
0.6
-75
5.5
-25
~ ............
25
75
Stand-by Power Supply
Current vs. Voltage
1.4
1.0
/
-25
125
Full Stand-by Power
Supply Current.
Data Retention Current vs.
Ambient Temperature
/
1.2
"ii
E
0
~
J
1.0
0.8
4.75
5.0
5.25
1000
5.5
0.6
-75
Ii
~
~
"ii
'"
T.=25"C
1.3
1.2
1.1
/
o
V
100
V
200
300
100
"
10
)
~
~
~
.l'
r--
j
V
r-- r--
75
Address Access Time vs.
Capacitive Load
:I
~
/
0.1
-25
Vee (volls)
0.9
./
."
Vee=5.5V
I
V
/
0.6
4.5
JJ.
0.6
-75
125
1.4
)V
1.2
0.8
i.
0.8
/"
1.6
TA=2j
i:I
1.0
Stand-by Power Supply
Current VB. Ambient
Temperature
1.6
J
J.
V
TA("C)
Vee (volls)
~
/
~
~
0.8
0.6
f
Vce=4.5V
1.4
:;;
~ 1.2
~
Address Access Time vs.
Ambient Temperature
Supply Curreni VS.
Ambient Temperature
Supply Current vs. Vollage
1.6
400
Cap. Load (pi)
7-59
125
-50
100
150
FEATURES:
DESCRIPTION:
• High-density 1024K/512K-bit CMOS static RAM module
• 64K x 16 organization (IDT8MP624) with 32K x 16
option (IDT8MP612)
• Upper byte (1I09-,sl and lower byte (1101-8)
separated control
-Allows flexibility in application
• Equivalent to JEDEC standard for future monolithic
64K x 8/32K x 16 static RAMs
The IDT8MP624/1DT8MP612 are 1024K/512K high-speed
CMOS static RAMs constructed on an epoxy laminate substrate using four IDT71256 32K x 8 static RAMs (IDT8MP624)
or two IDT71256 static RAMs (IDT8MP612) in plastic surfacemount packages. Functional equivalence to proposed monolithic static RAMs is achieved by utilization of an on-board
decoder that interprets the higher order address A,s to select
one of the two 32K x 16 RAMs as the by-16 output and using
LB and UB as two extra chip select functions for lower byte
(1/0,-8) and upper byte (1/09-16) control, respectively. (On the
IDT8MP612 32K x 16 option, A,s needs to be externally
grounded for proper operation.) Extremely high speeds are
achieved by the use of IDT71256s fabricated in IDT's highperformance, high-reliability technology, CEMOS. This stateof-the-art technology, combined with innovative circuit design
techniques, provides the fastest 1024K/512K static RAMs
available.
The IDT8MP624/1DT8MP612 are available with access times
as fast as 60ns over commercial temperatu re range, with maximum operating power consumption of only 1.7W (64K x 16
option). The module also offers a full standby mode of 110mW
(max.).
The IDT8MP624/1DT8MP612 are offered in a 4o-pin plastic
SIP package, as well as a 40-pin DIP which conform to JEDEC
standard pinouts.
All inputs and outputs of the IDT8MP824/1DT8MP612 are
TTL-compatible and operate from a single 5V supply. (NOTE:
Both GND pins need to be grounded for proper operation.)
Fully asynchronous circuitry is used requiring no clocks or
refreshing for operation, and provides equal access and cycle
ti mes for ease of use.
• Fast access times
-60ns (max.) over commercial temperature range
• Low-power consumption
• CEMOS'· process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Offered in both DIP and SIP (single in-line) packages for
maximum space-saving flexibility
• Cost-effective plastic surface-mounted RAM packages on an
epoxy laminate (FR4) substrate
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
FUNCTIONAL BLOCK DIAGRAM
Ao-A,.
1/0,-liD.
110,-110"
WE
DE
----
..---
r--IDm256
32K x8
CMOS
STATIC
RAM
---
~
I--
.--
IDm256
32KxB
CMOS
' - - - - STATIC
RAM
_
A15
:::;!:I:~~g[1~
cs II
LS
DE
-
-=
IDm256
32K x 8
CMOS
STATIC
RAM
IDm256
~~~:
STATIC
RAM
---, r--
DER
~1/2
~~~ 1~t:
DECODER
'1
SSDBMP624-001
CEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
@
1986 Integrated Device Technology, Inc.
JULY 1986
7-60
Printed In U.S.A.
IDTBMP624/1DTBMP6121024K (64K x 16-BIT)
& 512K (32K x 16-BIT) PLASTIC STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN NAMES
A O-'5
Addresses
1/0,_'6
Data Input/Output
CS
Chip Select
WE
Write Enable
Vee
GND
Ground
Power
OE
Output Enable
UB
Upper Byte Control
LB
Lower Byte Control
SSDBMP624-002
SIP
SIDE VIEW
NOTES:
1. Both GND pins need to be grounded for
proper operation.
2. On IDT8MP612, 512K (32K x 16-bit)
option, A,s (pin 1 - DIP; Pin 31 - SIP)
requires external grounding for proper
operation.
7-61
SSD8MP624-003
FEATURES:
DESCRIPTION:
• High-density 256K/12SK CMOS static RAM modules
• 16K x 16 organization (IDTSMP656) with SK x 16
option (IDTSMP62S)
The IDTSMP656/1DTSMP62S are 265K/12SK-bit high-speed
CMOS static RAMs constructed on an epoxy laminate substrate
using four IDT7164 SK x S static RAMs (IDTSMP656) or
two IDT7164 static RAMs (IDTSMP62S) in plastic surface
mount packages.
Functional equivalence to proposed monolithic static RAMs is
aChieved by utilization of an on-board decoder that interprets the
higher order address A'3to select one of the two SK x 16 RAMs as
the by-16 output and using LB and UB as two extra chip select
functions for lower byte (I/O,-al and upper byte (1/0s-,s) control,
respectively. (On IDTSMP62S SK x 16 option, A'3 needs to be
externally grou nded for proper operation.) Extremely hig h speeds
are aChievable by the use of IDT7164s, fabricated in lOT's highperformance, high-reliability CEMOS technology. This state-ofthe-art technology, combined with innovative circuit design
techniques, provides the fastest 256KI12SK static RAMs available.
The IDTSMP656/1DTSMP62S are available with access times
as fast as SOns over the commercial temperature range, with maximum operating power consumption of only 1.SW (IDTSMP656
16K x 16 option). The module also offers a full standby mode
of 440mW (max.).
The IDTSMP656/1DTSMP628 are offered in both a 4o-pin
plastic SIP, as well as a 4o-pin plastic DIP which conform to
JEDEC standard pinouts for future monolithic devices.
All inputs and outputs of the IDT8MP656/IDT8MP628 are
TTL-compatible and operate from a single 5V supply. (NOTE:
Both Vee pins need to be connected to the 5V supply and both
GND pins need to be grounded for proper operation.) Fully
asynchronous ciruitry is used requiring no clocks or refreshing
for operation and provides equal access and cycle times for
ease of use.
• Upper byte (1/Os-,s) and lower byte (I/O,-al
separated control
-Flexibility in application
• Equivalent to JEDEC standard for future monolithic
16K x 16/SK x 16 static RAMs
• Fast access times
-SOns (max.) over commercial temperature range
• Low-power consumption
-Active: less than 1W (typ. in 16K x 16 organization)
-Standby: less than 1mW (typ.)
• Cost-effective plastic surface mounted RAM packages on
an epoxy laminate (FR4) substrate
• Offered in both DIP and SIP (single in-line) packages for
maximum space-saving flexibility
• Utilizes IDT7164s - high-performance 64K static RAMs
produced with advanced CEMOS~ technology
• CEMOS process virtually eliminates alpha particle soft
error rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
FUNCTIONAL BLOCK DIAGRAM
A O- 12 - - - . . - - - - - - - - - . . . ,
1/0,_8 _ _~+_--------,
I/O. -16----1H--t--------...,
WE7.~+++-----------,
OE~+++f----------,
IDT7164
8K x 8
;+-+---1 CMOS
t-t-t--t----I STATIC
RAM
'-+__-1
IDT7164
8K x 8
11~:E=~ STATIC
CMOS
~
RAM
IDT7164
8K x 8
CMOS
STATIC
RAM
A'3
CS
LBTt~~=~
iJij----'
SSD8MP656-001
CEMOS is a trademark of Integrated Device Technology, Inc.
JULY 1986
COMMERCIAL TEMPERATURE RANGE
• 1986 Integrated Device Technology, Inc.
7-62
Printed in U.S,A .
IDT8MP656S/IDT8MP628S CMOS STATIC RAM
PLASTIC MODULES 256K (16K x 16-BIT) & 128K (8K x 16-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN NAMES
Vc~
\!g;(')
CS
1/0,6
I/O,.
I/O,.
1/0,3
1/0,2
I/O"
1/0,0
I/0.
GND(')
1/0.
1/07
1/06
1/05
I/0.
1/03
1/0 2
1/0,
OE -"':':"' _ _""':'J"""
WE
UB
[8
NC
A'3 12 )
A'2
A"
A,o
A.
GND(')
A O-,6
Addresses
1/0,_8
Data Input/Output
CS
Chip Select
Vee
Power
WE
Write Enable
OE
Output Enable
GND
Ground
A.
A7
As
A.
A.
A3
A2
A,
Ao
DIP
TOP VIEW
SSD8MP656-002
SIP
SIDE VIEW
SSD8MP656-003
NOTES:
1. Both Vee pins need to be connected to the 5V supply, and both GND pins need to be grounded for proper operation.
2. A 13 (pin 39 - SIP; pin 35 - DIP) requires external grounding for IDTBMP628128K (BK x 16-Bit) option.
7-63
FEATURES:
DESCRIPTION:
• High-density 1024K (128K x 8) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 128K x 8
static RAMs
The IDT8MP824 is a 1024K (131,072 x 8-bit) high-speed static
RAM constructed on an epoxy laminate substrate using four
IDT7125632K x 8 static RAMs in plastic surface mount packages. Functional equivalence to proposed monolithic one megabit static RAMs is achieved by utilization of an on-board decoder
that interprets the higher order addresses A'5 and A'6 to select
one of the four 32K x 8 RAMs. Extremely fast speeds can be
achieved with this technique due to use of 256K static RAMs and
the decoder fabricated in IDT's high-performance, high-reliability
technology, CEMOS.
The IDT8MP824 is available with maximum access times as
fast as 60ns for commercial range, with maximum power consumption of 1.0 watts. The Circuit also offers a reduced power
standby mode. When CS goes high, the circuit will automatically
go to a substantially lower power mode with maximum power
consumption of only 85mW.
The IDT8MP824 is offered in a30-pin SIP (single in-line) package, as well as a 32-pin DIP which conform to JEDEC standard
pinouts for future monolithic devices.
All inputs and outputs of the IDT8MP824 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry is used requiring no clocks or refreshing for operation, and
provides equal access and cycle times for ease of use.
• Fast access times
-60ns (max.) over commercial temperature range
• Low-power consumption
-Active: less than 500mW (typ.)
-Standby: less than 150!'W (typ.)
• CEMOS·· process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Cost-effective plastic surface-mounted RAM packages on an
epoxy laminate (FR4) substrate
• Offered in both DIP and SIP (single in-line) packages for
maximum space-saving flexibility
• Utilizes IDT71256s - high-performance 256K static RAMs
produced with advanced CEMOS technology
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
-1'
0 , -8
WE
OE
IDT71256
32K x 8
CMOS
STATIC
RAM
cstIDT71256
32K x 8
'-' - - CMOS
' - - - - STATIC
RAM
--<
--<
C~
IDT71256
32K x 8
CMOS
STATIC
RAM
csLIDT71256
32K x 8
'--' - - - CMOS
' - - - STATIC
RAM
CS1
FCT139
DECODER
SSDBMP824-001
CEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
JULY 1986
c 1986 Integrated Device Technology, Inc.
Printed in U.S.A.
7-64
IDTBMPB24S1 MEGABIT
(12BK x B-BIT) CMOS STATIC RAM PLASTIC MODULE
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
NC
PIN NAMES
AD-16
1/0 ,_8
Addresses
CS
Chip Select
Data Input/Output
A"
A,.
Vee
A,s
NC
Vee
Power
A,.
WE
WE
Write Enable
A7
A'3
Aa
OE
Output Enable
As
GND
Ground
As
As
As
A3
A"
OE
A.
A,.
A,
Ci
As
I/0a
1/07
110,
1/0.
1/03
1/0,
II0s
GND
110.
DIP
TOP VIEW
SIP SIDE VIEW
SSDBMP824·003
SSD6MP824-002
7-65
or two IDT71256 static RAMs (IDT8M612) in leadless chip
carriers. Functional equivalence to proposed monolithic static
RAMs is achieved by utilization of an on-board decoder that
interprets the higher order address A,s to select one of the two
32K x 16 RAMs as the by-16 output and using LB and UBastwo
extra chip select functions for lower byte (1/0,_sl and upper byte
(1/09-'6) control, respectively. (On the IDT8M612 32K x 16
option, A,s needs to be externally grounded for proper operation.) Extremely high speeds are aChievable by the use of
IDT71256s fabricated in IDT's high-performance, high-reliability
technology, CEMOS. This state-of-the-art technology, combined
with innovative circuit design techniques, provides the fastest
1024K/512K static RAMs available.
The IDT8M624/1DT8M612 are available with access times as
fast as 60ns commercial and 75ns military temperature range,
with maximum operating power consumption of only 1.7W (max.
-IDT8M624 64K x 16 option). The module also offers a full
standby mode of 110mW (max.).
The IDT8M624/1DT8M612 are offered in a high-density 40-pin,
600 mil center sidebraze DIP to take full advantage of the
compact IDT71256s in lead less chip carriers.
All inputs and outputs of the IDT8M624/1DT8M612 are TTLcompatible and operate from a single 5V supply. (NOTE: Both
GND pins need to be grounded for proper operation.) Fully
asynchronous circuitry is used requiring no clocks or refreshing
for operation and provides equal access and cycle times for ease
of use.
AIiIDT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883, Class B, as well
as being qualified to requirements patterned after Methods 5004
and 5005, making them ideally suited to applications demanding
the highest level of performance and reliability.
FEATURES:
• High-density 1024K1512K-bit CMOS static RAM module
• 64K x 16 organization (IDT8M624) with 32K x 16 option
(IDT8M612)
• Upper byte (1/09-'6) and lower byte (1I0,-sl
separated control
-allows flexibility in application
• Equivalent to JEDEC standard for future monolithic 64K x 161
32K x 16 static RAMs
• High-speed - 60ns (max.) commercial; 75ns (max.) military
• Low-power consumption
• CEMOS'· process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in the JEDEC standard 40-pin, 600 mil wide ceramic
sidebraze DI P
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures for all AC and DC parameters as per customer
requirements
DESCRIPTION:
The IDT8M624/1DT8M612 are 1024K/512K-bit high-speed
CMOS static RAMs constructed on a multi-layered ceramic
substrate using four IDT71256 32K x 8 static RAMs (IDT8M624)
FUNCTIONAL BLOCK DIAGRAM
A"-A,.
1/0,-1/08
I/0g-V0'6
WE
OE
~
~
IDT71256
321< x 8
CMOS
STATIC
RAM
IDT71256
' - - 321< x8
' - - CMOS
' - - - STATIC
RAM
=rfi112 FCT1~1:t
DECODER
y
~
t--
~
'----
IDT71256
32K x 8
CMOS
STATIC
RAM
IDT71256
32Kx8
CMOS
STATIC
RAM
-
L::f1/2 FCT13!f:
DECODER
Of
SRD8M624-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
• 1986 Integrated Device Technology, Inc.
7-66
JULY 1986
Printed in U.S.A.
IDTBM624/1DTBM612 1024K (64K x 16-BIT) &
512K (32K x 16-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN NAMES
PIN CONFIGURATION
A,s(')
CS
Vee
WE
UB
LB
1/0"
1I0,s
1/0,.
1/0'3
1/0,2
1/011
1/0,0
1/0.
1/07
I/0a
1/0.
1/0.
1/03
1/02
1/0,
OE -,..:;;...___-=:;;,s-
Addresses
CS
Chip Select
WE
Write Enable
Data Input/Output
Vee
Power
GND
Ground
A,.
A'3
A,.
OE
Output Enable
A"
UB
Upper Byte Control
LB
Lower Byte Control
A,o
A.
GND(')
I/0 a
AIl-'5
1/0,_,6
GND(')
Aa
A7
As
As
NOTES:
1. Both GND pins need to be grounded for
proper operation.
2. On IDTBM612, 512K (32K x '6-bit) option,
A 15 (pin 1) requires external grounding for
proper operation.
A.
A3
A.
A,
Ao
SRD8M624-oD2
7-67
FEATURES:
DESCRIPTION:
• High-density 256K112BK-bit CMOS static RAM modules
• 16K x 16 organization (IDTBM656) with BK x 16
option (IDTBM62B)
• Upper byte (IIOg _ '6) and lower byte (1/0, _s)
separated control
-Flexibility in application
The IDTBM656/1DTBM62B are 265K112BK-bit high-speed
CMOS static RAMs constructed on a multi-layered ceramic substrate using four IDT7164 BK x B static RAMs (IDTBM656) or two
IDT7164 static RAMs (IDTBM62B) in lead less chip carriers.
Functional equivalence to proposed monolithic static RAMs is
achj,eved by utilization of an on-board decoder that interprets the
higher order address A'3 to select one ofthetwo BK x 16 RAMs as
the by-16 output and using LB and UB as two extra chip select
functions for lower byte (1/0, -s) and upperbyle I/0g_,s) control,
respectively. (On IDTBM62B BK x 16 option, A'3 needs to be
externally grounded for proper operation.) Extremely high speeds
are achievable by the use of IDT7164s fabricated in IDT's highperformance, high-reliability CEMOS technology. This state-ofthe-art technology, combined with innovative circuit design
techniques, provides the fastest 256K112BK static RAMs available.
The IDTBM656/1DTBM62B are available with access times as
fast as 50ns commercial and 60ns military temperature range,
with maximum operating power consumption of only 1.BW
(IDTBM656, 16K x 16 option). The module also offers a full
standby mode of 440mW (max.).
The I DTBM656/1 DTBM62B are offered in a high-density 40-pin,
600 mil center sidebraze DIP to take full advantage of the compact IDT7164s in lead less chip carriers.
All inputs and outputs of the IDTBM656/1DTBM62B are TTLcompatible and operate from a single 5V supply. (NOTE: Both
Vee pins need to be connected to the 5V supply and both GND
pins need to be grounded for proper operation.) Fully asynchronous ciruitry is used requiring no clocks or refreshing for
operation and provides equal access and cycle ti mes for ease of
use.
Alii DT military module semiconductor components are 100%
processed to the test methods of MIL-STD-BB3, Class B, making
them ideally suited to applications demanding the highest level
of performance and reliability.
• Equivalent to JEDEC standard for future monolithic
16K x 16/BK x 16 static RAMs
• High-speed
-Military - 60ns (max.)
-Commercial - 50ns (max.)
• Low-power consumption: typically less than 1W operating
(IDTBM656), less than 1mW in standby
• Utilizes IDT7164s - high-performance 64K static RAMs
produced with advanced CEMOS·· technology
• CEMOS process virtually eliminates alpha particle soft
error rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in the JEDEC standard 40-pin, 600 mil wide ceramic
sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STD-BB3, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters as per
customer requirements
FUNCTIONAL BLOCK DIAGRAM
Ao-12---....- - - - - - - - - ,
I/O,_8 _ _~+_--------,
I/0 9 - 1 . - - 1 r l - + - - - - - - - - - ,
WE-~-rr-------------'
OE~+++1----------,
IDT7164
'+__-I
8Kx8
CMOS
U++==~STATIC
RAM
IDTn64
8K x 8
CMOS
STATIC
RAM
A '3
CS
[8 -ttc:;;;~=:L.
UB--------'
SR08M656-001
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Cl1986 Integrated Device Technology, Inc.
7-68
JUNE 1986
Printed In U.S.A.
IDTBM656S/IDT8M628S
CMOS STATIC RAM MODULE 256K (16K x 16-BIT) & 128K (8K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PIN NAMES
Ve~
~(')
CS
A,.(')
A,.
A"
A,.
1/0,_'6
Data InpuVOutput
CS
Chip Select
Vee
Power
WE
Write Enable
OE
Output Enable
GND
Ground
A.
UB
Upper Byte Control
A7
A.
LB
Lower Byte Control
A.
GND(')
liD.
1/07
liD.
liD.
liD.
liD.
liD.
Addresses
A._'3
WE
UB
[]j
NC
I/O,.
liD,.
liD,.
liD,.
liD,.
liD"
liD,.
liD.
GND(')
A.
A.
A.
A.
A,
I/~
DE -"""-_ _..:.;.JC"""
NOTES:
1. Both Vee pins need to be connected to the 5V supply, and both GND pins need
to be grounded for proper operation.
Au
2. On IDT8M628, 128K (8K x 16-Bit) option, A 13 (Pin 35) is required external
grounding for proper operation.
DIP
TOP VIEW
SRDBM656-o02
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
RATING
RECOMMENDED DC OPERATING CONDITIONS
VALUE
UNIT
Terminal Voltage with
Respect to GND
-0.5 to +7.0
V
TA
Operating Temperature
-55 to +125
'C
TBIAS
Temperature Under Bias
-65 to +135
'C
TSTG
Storage Temperature
-65 to +155
'C
VTERM
PT
Power Dissipation
4.0
W
lOUT
DC Output Current
50
mA
MIN.
TYP.
MAX.
UNIT
Vee
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V,H
Input High Voltage
2.2
-
6.0
V
V,L
Input Low Voltage
-0.5(1)
-
O.B
V
PARAMETER
SYMBOL
NOTE:
1. V1L (min)
=-3.0V for pulse width
less than 20ns.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
GRADE
Military
Commercial
AMBIENT
TEMPERATURE
GND
Vee
-55'C to +125'C
OV
5.0V ± 10%
O'C to +70'C
OV
5.0V ± 10%
DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V
± 10%, Vee (Min.)
SYMBOL
= 4.5V, Vee (Max.) = 5.5V, VLe = 0.2V, VHe = Vee = -0.2V
PARAMETER
!lui
Input Leakage Current
!lLOI
Output Leakage Current
TEST CONDITIONS
=Max.; V,N =GND to Vee
Vee =Max.
Vee
CS
= V,H, VOUT = GND to Vee
IDTBM656S
MIN.
TYP.
MAX.
MIN.
IDTBM628S
TYP.
MAX.
UNIT
-
-
15
-
-
15
I'A
-
-
15
-
-
15
I'A
-
165
330
-
150
300
mA
leex16
Operating Current in X16 Mode
CS, UB & LB = V,L
Vee =Max., Output Open
f =f Max.
leexB
Operating Current in XB Mode
CS =V,L, UB or LB =V,L
Vee = Max., Output Open
f = f Max.
-
100
200
-
BO
170
rnA
ISB &
ISB'
Standby Power Supply Current
CS":V,Hor
UB ": V,H and LB ": V,H
Vee = Max.
Output Open
-
4
BO(2)
-
2
40(2)
mA
VOL
Output Low Voltage
10L
-
-
0.4
-
-
0.4
V
VOH
Output High Voltage
10H
2.4
-
-
2.4
-
-
V
= BmA, Vee = Min.
= -4mA, Vee =Min.
NOTE:
1. Vce = 5V, TA = +25°e
2. Isa and IS81 of IDT8MB56/IDT8MB28 at commercial temperature = BOmA/30mA.
7-69
fI
IDTBM656SIIDT8M628S
CMOS STATIC RAM MODULE 256K (16K x 16-BIT) & 128K (8K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
GND to 3.0V
5ns
1.5V
1.5V
See Figs. 1 & 2
+5V
480fl
480fl
DOUT ---,~---+
--...----1
DOUT
255fl
25Sfl
30pF
Figure 1. Output Load
SpF"
Figure 2. Output Load
(for t CLZ1 , 2' t OLZ' t CHZ1 , 2' t OHZ'
tow, t WHZ)
-Including scope and jig
SR08M656-003
AC ELECTRICAL CHARACTERISTICS (Vee = 5V ±10%, All Temperature Ranges)
SYMBOL
PARAMETER
IDT8M6S6SS0
IDT8M729S50
COM'L. ONLY
IDTBM656S60
IDTBM628S60
I DtBM656S70
IDTBM628S70
MIN.
MAX.
MIN.
MIN.
MAX.
IDT8M6S6S85
IDT8M628S85
MAX.
MIN.
IDT8M656S100
IDT8M628S100
UNITS
MIL. ONLY
MAX.
MIN.
MAX.
READ CYCLE
t RC
Read Cycle Time
50
-
60
-
70
-
85
-
100
-
ns
'AA
Address Access Time
-
50
60
-
85
-
100
ns
Chip Select Access Time
-
50
60
-
70
t ACS
-
70
-
85
-
100
ns
tClZ1.2(1)
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tOE
t OlZ (1)
Output Enable to Output Valid
-
30
-
35
-
40
-
50
-
60
ns
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
t CHZ (1)
Chip Select to Output in High Z
-
20
-
40
ns
20
25
30
-
35
-
-
30
Output Disable to Output in High Z
-
25
t OHZ (1)
35
-
40
ns
tOH
t pU (1)
Output Hold from Address Change
5
-
5
-
5
-
5
-
5
-
ns
Chip Select to Power Up Time
0
-
0
-
0
-
0
-
0
-
ns
t po (1)
Chip Deselect to Power Down Time
-
50
-
60
-
70
-
85
-
100
ns
WRITE CYCLE
twe
Write Cycle Time
50
-
60
-
85
-
100
-
ns
Chip Selection to End of Write
45
-
55
-
70
tew
65
-
75
-
90
-
ns
tAW
Address Valid to End of Write
45
-
55
-
65
-
75
-
90
-
ns
t AS
Address Setup Time
5
10
-
10
-
10
-
10
Write Pulse Width
40
45
-
55
-
65
-
80
-
ns
twp
-
tWR
t WHZ (1)
Write Recovery Time
5
-
5
-
5
-
10
-
10
-
ns
Write Enable to Output in High Z
-
20
-
25
-
30
-
35
-
40
ns
tow
Data to Write Time Overlap
20
-
25
30
-
35
-
40
-
ns
tOH
t oW (1)
Data Hold from Write Time
5
5
5
-
5
-
5
-
ns
Output Active from End of Write
5
-
-
5
-
5
-
5
-
5
-
ns
NOTES:
1. This parameter guaranteed but not tested.
7-70
ns
IDT8M656S/IDTBM628S
CMOS STATIC RAM MODULE 256K (16K x 16-BIT) & 128K (8K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. W)
i---------tRc---------.j
ADDRESS
i------tACS---+-.j
i-----tcLZ(5)1-----i
DOUT - - - - - - - - - - - - - - - {
SAOBM656-004
TIMING WAVEFORM OF READ CYCLE NO.
2(1,2,4)
~~~-------------tRC----------------~~
ADDRESS
DOUT
------'t~I~:~:=~:=_-==_-~=t=O=H~~-t-AA---=-=--~=~---------------~.,-----'~-tO-H---DATA VALID
PREVIOUS DATA VALID
------------------~~~~
SRDBM656-005
TIMING WAVEFORM OF READ CYCLE NO.
UB,La &
Cs
DOUT
3(1,3,4)
-------i-_________________f
L==g
L.,o'lSAOBM656-006
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V1l and UB, IS
=V1l for 16 output active.
3. Address valid prior to or coincident with CS transition low.
4. OE = V'L'
5. Transition is measured ±2QOmV from steady state. This parameter is sampled and not 100% tested.
7-71
I
IDT8M6S6S/IDTBM628S
CMOS STATIC RAM MODULE 2S6K (16K
x 16-BIT) lit 128K (8K x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
I---------IWc---------i
ADDRESS
I----ICW-----.j
UB, LB lit
CS
DOUT -i-i-i-t-t-t~~_.---------------------r----~---------
~IOW
DIN
IDH~
------<¢"+""------.LlXXX~~
SRD8M656 OO7
w
TIMING WAVEFORM OF WRITE CYCLE NO.
2(1.6)
~--------IWC--------~
ADDRESS
i----ICW-----l
(7)
DIN
---------------«
SR08M656-008
NOTES:
1.
WE or CS or US and LB must be high during all address transitions.
2. A write occurs during the overlap (t wp) of a low CS.
3. tWR is measured from the earlier of
CS or WE going high to the end of write cycle.
4. During this period, 1/0 pins are in the output state so that the input signals of oPPosite phase to the outputs must not be applied.
5. If the
es,
US and LB low transition occurs simultaneously with the
WE low transitions or after the WE transition, outputs remain in 8
high impedance state.
6. OE is continuously low (OE = V,L)'
7. Dour is the S8me phase of write data of this write cycle.
8. If CS, UB and I'B are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
7-72
IDTBM656S/IDTBM62BS
CMOS STATIC RAM MODULE 256K (16K x 16-BIT) & 12BK (BK x 16-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE
MODE
CAPACITANCE
CS UB LB OE WE
OUTPUT
POWER
SYMBOL
(TA
=+25°C. f =1.0MHz)
PARAMETER(')
CONDITIONS
TYP.
V,N = OV
TBD
pF
VOUT = OV
TBD
pF
Standby
H
X
X
X
X
High Z
Standby
C 'N
Input Capacitance
Standby
L
H
H
X
X
High Z
Standby
C OUT
Output Capacitance
Read
L
L
L
L
H
DOUT 1-16
Active
Lower Byte Read
L
H
L
L
H
DOUT '·8
Active (X8)
Upper Byte Read
L
L
H
L
H
L
L
L
H
H
DOUT 9-'6
High Z
Active (X8)
Read
Lower Byte Read
L
H
L
H
H
High Z
Active (X8)
UNIT
NOTE:
1. This parameter is sampled and not 100% tested.
Active
Upper Byte Read
L
L
H
H
H
High Z
Active (X8)
Write
L
L
L
X
L
DIN 1-16
Active
Lower Byte Write
L
H
L
X
L
D,N '-8
Active (X8)
Upper Byte Write
L
L
H
X
L
DIN 9-16
Active (X8)
Address Access Time
Capacitive Load
1.2
VB.
T~ = +25·C
./
./
/
/
50
Capaclllve Load -(pi)
100
SRD7M656-016
I
7-73
FEATURES:
DESCRIPTION:
• High-density 1024K-bit (128K x 8) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 128K x 8
static RAMs
• High-speed - 60ns (max.) commercial; 7Sns (max.) military
• Low-power consumption; typically less than SOOmW
operating, less than lS0p.W in standby
• CEMOS~ process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in the JEDEC standard 32-pin, 600 mil wide ceramic
sidebraze DIP
• Single SV (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures for all AC and DC parameters as per customer
requirements
The IDT8M824 is a 1024K (131,072 x 8) bit high-speed static
RAM constructed on a co-fired ceramic substrate using four
IDT712S632K x 8 static RAMs in lead less chip carriers. Functional equivalence to proposed monolithic one megabit static
RAMs is achieved by utilization of an on-board decoder that
interprets the higher order addresses A'5 and A'6 to select one of
the four 32K x 8 RAMs. Extremely fast speeds can be achieved
with this technique due to use of 2S6K static RAMs and the
decoder fabricated in IDT's high-performance, high-reliability
technology, CEMOS.
The IDT8M824 is available with maximum access times as fast
as 60ns for commercial and 7Sns for military temperature ranges,
with maximum power consumption of 1.0 watts. The circuit also
offers a reduced power standby mode. When CS goes high, the
circuit will automatically go to a substantially lower power mode
with maximum power consumption of only 8SmW.
The IDT8M824 is offered in a 32-pin, 600 mil center sidebraze
DIP, adhering to JEDEC standards for one megabit monolithic
pinouts, allowing for compatibility with future monolithics.
All inputs and outputs of the IDT8M824 are TTL-compatible
and operate from a single SV supply. Fully asynchronous circuitry is used. requiring no clocks or refreshing for operation, and
provides equal access and cycle times for ease of use.
AIiIDT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883, Class B, as well
as being qualified to requirements patterned after Methods SOO4
and SOOS, making them ideally suited to applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
.,.
Ao
I10'-8
WE
Of
IDT71256
32K x 8
CMOS
STATIC
RAM
IDT71256
32K x 8
CMOS
STATIC
RAM
csL-
--<:
--<:
'--'--
IDT71256
32K x 8
CMOS
STATIC
RAM
I
csLIDT71256
32K x 8
CMOS
' - - - STATIC
RAM
-
'---
C~
CS1
IDT FCT139
DECODER
SRD8M824-Q01
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JULY 1986
Printed In U.S.A.
II 1986 Integrated Device Technology. Inc.
7-75
IDTBM824 1 MEGABIT
(128K x 8-BIT) CMOS STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGE
PIN NAMES
PIN CONFIGURATrON
Ao-'6
Addresses
1/0'-8
Data Input/Output
CS
Chip Select
NC
Vee
-'16
A,s
NC
Vee
Power
WE
WE
Write Enable
A'3
Aa
OE
Output Enable
GND
Ground
A,.
A'2
A7
As
As
As
As
A11
OE
A3
~
A,
A,o
Cs
Ao
11O,
II0a
1/0 3
1/°7
110.
I/O s
GND
I/0.
1/02
DIP
TOP VIEW
SR08M824-002
7-76
FEATURES:
DESCRIPTION:
• High-density 256K (32K x 8) bit CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 32K x 8
static RAMs
The IDT8M856 is a 256K (32,768 x 8-bit) high-speed static
RAM constructed on a co-fired ceramic substrate using four
IDT7164 (8192 x 8) static RAMs in leadless chip carriers.
Functional equivalence to proposed monolithic 256K static
RAMs is achieved by utilization of an on-board decoder circuit
that interprets the higher order address A 13 and A14 to select
one of the four 8K x 8 RAMs. Extremely fast speeds can be
achieved with this technique due to use of 64K static RAMs
and the decoder fabricated in IDT's high-performance, highreliability CEMOS technology.
The IDT8M856 is available with maximum access times as
fast as 45ns for commercial and 55ns for military temperature
ranges, with maximum power consumption of only 880mW.
The circuit also offers a substantially low-power standby mode.
When CS goes high, the ciruit will automatically go to a
standby mode with power consumption of only 83mW (max.).
The IDT8M856 is offered in a 28-pin, 600 mil center sidebraze
DIP. This provides four times the density of the IDT7M864
(8K x 8 module) in the same socket with only minor pin
assignment changes. In addition, the JEDEC standard for 256K
monolithic pinouts has been adhered to, allowing for compatibility with future monolithics.
All inputs and outputs of the IDT8M856 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous
circuitry is used requiring no clocks or refreshing for operation,
and provides equal access and cycle times for ease of use.
All IDT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883 Class B, making
them ideally suited to applications demanding the highest level
of performance and reliability.
• High-speed - 45ns (max.) commercial; 55ns (max.) military
• Low-power consumption; typically less than 400mW operating,
less than 500JJ'w in full standby
• Utilizes IDT7164s - high-performance 64K static RAMs
produced with advanced CEMOS·· technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Pin compatible with IDT7M864 (8K x 8 SRAM module)
• Offered in the JEDEC standard 28-pin, 600 mil wide ceramic
sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters as per
customer requirements
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
Ao-A'2
PIN NAMES
ADDRESSES
1/01 - II0s DATA INPUTIOUTPUT
CHIP SELECT
CS
AO - A14
Vcc
WE
OE
GND
1/0,-I/Oa
WE
OE
~
POWER
WRITE ENABLE
OUTPUT ENABLE
IDT7164
8Kx8
CMOS
STATIC
RAM
cs,L-
IDT7164
8Kx8
'-CMOS
STATIC
RAM
GROUND
~
~
~
~CS'
1-
'--
~
IDT7164
8Kx8
CMOS
STATIC
RAM
cs,LIDT7164
8Kx8
CMOS
STATIC
RAM
ys,
DECODER
DIP
TOP VIEW
-<
SSDBM856-001
SSD8M856-002
CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.1986 Integrated Device Technology, Inc.
7-77
JULY 1986
Printed In U.S.A.
fI
IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATING(1)
SYMBOL
RATING
COMMERCIAL
VTEAM
Terminal Voltage
with Respect
toGND
TA
RECOMMENDED OPERATING CONDITIONS
MILITARY
SYMBOL
UNIT
-0.5 to +7.0
-0.5 to +7.0
V
Operating
Temperature
o to +70
-55 to +125
°C
TBIAS
Temperature
Under Bias
-10 to +85
-65 to +135
°C
TSTG
Storage
Temperature
-55 to +125
-65 to +150
°C
PT
Power Dissipation
4.0
4.0
W
lOUT
DC Output Current
50
50
mA
Vee
GND
V,H
V,L
NOTE:
1. V1l min
PARAMETER
Supply Voltage
Supply Voltage
Input High Voltage
Input low Voltage
TYR
5.0
0
MIN.
4.5
0
2.2
-0.5(1)
MAX.
5.5
0
6.0
0.8
-
UNIT
V
V
V
V
=-3.0V pulse width less than 20n8.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
(Vcc = 5V
± 10%, TA =
-55°C to +125°C and O°C to +70°C)
MIN.
TYR(l)
MAX.
UNIT
-
-
15
p.A
15
80
160
"A
mA
80
160
mA
8
15
mA
Y,N " Vee - 0.2V or :5 0.2V
-
0.1
12.0(2)
mA
-
0.5
0.4
V
-
V
PARAMETER
TEST CONDITIONS
Ilul
Input Leakage Current
Vee = 5.5V,
IILol
Output Leakage Current
Vee = 5.5V, CS = V,H, VO UT =OV to Vee
leel
Operating Power Supply Current
Vee =5.5V, CS
Y'N = OV to Vee
lee2
Dynamic Operating Current
=V,c. Output Open, I = 0
Vee =5.5V. CS = V,c. Output Open, I =I Max.
ISB
Standby Power Supply Current
CS" V,H (TTL Level), Vee = 5.5V. Output Open
ISBl
Full Standby Power Supply Current
VOL
Output Low Voltage
10L =10mA. Vee = 4.5V
10L =8mA. Vce =4.5V
-
VOH
Output High Voltage
10H = -4mA. Vee = 4.5V
2.4
CS" Vee - 0.2V (CMOS Level)
NOTES:
1. Vee = 5V. TA = +25°C
2. ISB1 at commercial temperature = 5mA.
DATA RETENTION CHARACTERISTICS
MIN.
TYP.I ' )
COM'L
MAX.
MIL
MAX.
UNIT
Vee lor Retention Data
2.0
-
-
-
V
-
6.0(2)
12.0(3)
1000(2)
1500(3)
4000(2)
6000(3)
"A
SYMBOL
VDA
(TA = -55°C to +125°C and DOC to +70°C)
PARAMETER
TEST CONDITIONS
leeDA
Data Retention Current
tCDA
Chip Deselect to Data Retention Time
tA
Operation Recovery Time
CS " Vee - 0.2V
V,N :5 Vee - 0.2V or " 0.2V
0
t Ae (4)
-
-
-
NOTES:
1. TA =25'C
2. at Vee =2V
3. at Vee =3V
4. t AC
=Read Cycle Time
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION
MODE
Vee - - - - - - - - : L . 4 . 5 V VDA" 2V 4.5V
SSD8M856-003
7-78
-
ns
ns
IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
+5V
GNDt03.0V
5ns
1.5V
1.5V
See Figures 1 and 2
DOUT
~
255!l
+5V
480.o
DOUT
3OpF'
~
255.0
480!l
5pF'
SRD7198SIL-006
SRD7198S/L-005
Figure 2. Output Load
(for tHz, tLZt tWZt and tow)
Figure 1. Output Load
'Including scope and jig
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
(Vee = 5V ±10%, TA = O°C to +70°C)
IDTBM856L45
MIN. MAX.
IDTBM856L50
MIN.
MAX.
IDT8M856L60
MIN.
MAX.
IDTBMB56L70
MIN.
MAX.
IDTBM856L85
MIN.
MAX.
UNITS
READ CYCLE
t RC
Read Cycle Time
45
-
50
-
60
-
70
-
85
-
ns
tAA
Address Access Time
-
45
50
ns
45
50
55
65
-
85
-
-
70
Chip Select Access Time
-
60
t Acs
-
85
ns
tCLZ
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
25
-
35
-
40
-
45
-
55
ns
tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tCHz
Chip Select tei Output in High Z
-
20
20
-
20
-
25
ns
Output Disable to Output in High Z
-
20
20
-
20
-
25
-
30
tOHZ
-
30
ns
tOH
Output Hold from Address Change
5
-
5
-
5
-
5
-
5
-
ns
tpu
Chip Select to Power Up Time
0
-
0
-
0
-
0
-
0
-
ns
t po
Chip Deselect to Power Down Time
-
45
-
50
-
60
-
70
-
85
ns
ns
WRITE CYCLE
twc
Write Cycle Time
45
-
50
-
70
40
-
45
50
-
60
-
85
Chip Select to End of Write
-
60
tcw
tAW
Address Valid to End or Write
40
45
-
50
-
60
-
70
t As
Address Setup Time
5
-
-
5
-
10
-
10
-
15
-
ns
twp
Write Pulse Width
35
-
35
-
40
-
45
-
50
-
ns
tWA
Write Recovery Time
0
-
0
-
0
-
0
-
0
-
ns
tWHZ
Write Enable to Output High Z
-
20
-
20
-
25
-
30
-
40
ns
tow
Data to Write Time Overlap
20
-
20
-
25
30
-
40
-
ns
tow
Data Hold from Write Time
5
-
5
-
5
5
-
5
-
ns
tow
Output Active from End of Write
5
-
5
-
5
-
5
-
5
-
ns
7-79
70
ns
ns
I
IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Vee = 5V ± 10%, TA = -SSOC to +125°C)
SYMBOL
IDTBM856L55
MAX.
MIN.
PARAMETER
IDTBM856L65
MIN.
MAX.
IDTBM856L75
MIN.
MAX.
IDTBM856L90
MIN.
MAX.
IDT8M856L100
MIN.
MAX.
UNITS
READ CYCLE
t RC
Read Cycle Time
55
-
65
-
75
-
90
-
100
-
ns
tM
Add ress Access Ti me
55
-
75
-
90
ns
55
55
-
65
-
80
-
100
Chip Select Access Time
-
65
tACS
-
90
ns
tcLZ
Chip Select to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tOE
Output Enable to Output Valid
-
40
-
45
-
50
-
60
-
65
ns
toLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
5
-
5
-
ns
tCHZ
Chip Select to Output in High Z
20
-
25
-
35
-
40
ns
Output Disable to Output in High Z
20
-
25
-
30
tOHz
-
30
35
-
40
ns
tOH
Output Hold from Address Change
5
5
5
0
-
0
0
0
-
ns
0
-
5
Chip Select to Power Up Time
-
5
tpu
-
-
-
t po
Chip Deselect to Power Down Time
-
55
-
65
-
75
-
90
-
100
ns
65
75
-
100
85
-
ns
75
65
-
90
65
55
-
75
-
85
ns
10
-
-
10
-
15
-
15
ns
45
50
-
55
0
-
0
-
0
-
ns
WRITE CYCLE
twc
Write Cycle Time
55
tcw
Chip Select to End of Write
50
tAW
Address Valid to End or Write
50
t AS
Address Setup Time
5
twp
Write Pulse Width
40
-
tWR
Write Recovery Time
0
-
0
-
tWHZ
Write Enable to Output High Z
-
25
-
30
-
40
-
50
-
50
ns
tow
Data to Write Time Overlap
25
-
30
35
-
45
-
ns
Data Hold from Write Time
5
-
5
5
-
5
-
ns
tow
Output Active from End of Write
5
-
5
-
45
tOH
-
5
-
5
-
ns
TIMING WAVEFORM OF READ CYCLE NO.
55
45
5
5
1(1)
;--------IRC--------+j
ADDRESS
;------IACS---+-~
;----ICLZ(S)----!
DOUT-----------------------------{
SSD8M856--004
7-80
ns
ns
ns
IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)
TIMING WAVEFORM OF READ CYCLE NO.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2(1,2,4)
~~~~-------------tRC----------------~~
ADDRESS - - - - - /
DOUT
~ :~-~=- ~=- ~=- ~ tO~H~=-_-tAA~~=_-~=_-~=======~.-,------''t-tO-H----
PREVIOUS DATA VALID
------------------~~~~
DATA VALID
SRD71geSIl 008
TIMING WAVEFORM OF READ CYCLE NO.
3(1,3,4)
SR07198S/l-009
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS ; ; V1L
3. Address valid prior to or coincident with CS transition low.
4. OE = VjL5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
TIMING WAVEFORM OF WRITE CYCLE NO.
1(1)
~---------------twc--------------~
ADDRESS
~------tcw------~
DOUT -4~~~~~~~~~--------------------r----------------
DIN
-----------------------------<
7-81
I
IDTBM856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO.
2(1,6)
~--------------twc----------------~
ADDRESS
~------tcw--------~
(7)
DOUT~~~r-r-~~~~~~-t-t----------+---------~
tOH
DIN
----j (8)
---------------------------«
SRD7198S/l-011
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (t.wf.) of..!..!.ow CS.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4.
5.
6.
7.
8.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
DE is continuously low (DE - V,l).
.
DQ!.!T is the same phase of write data of this write cycle.
If CS is low during this period. 1/0 pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
Address Access Time
Capacitive Load
TRUTH TABLE
1.2
MODE
CS
OE
WE
.OUTPUT
Standby
H
X
X
HighZ
Standby
Read
L
L
H
DOUT
Active
Read
L
H
H
High Z
Active
Write
L
X
L
D'N
Active
POWER
VB.
Tl-
+25'C
./'"
V
./'"
V
CAPACITANCE (TA =+25°C, f =1.0MHz)
PARAMETER(I)
CONDITIONS
TYP.
UNIT
G,N
Input Capacitance
V,N=OV
35
pF
GOUT
Output Capacitance
VOUT - OV
26
pF
SYMBOL
50
Capacitive Load (pf)
100
SAOIM6S6-01B
NOTE:
1. This parameter is s~mpled and not 100% tested_
7-82
ORDER PART
NUMBER
SPEED
(ns)
IDT7MP624S
Icc (MAX.)
(mA)
PACKAGE
TYPE
OPER.
TEMP.
ORDER PART
NUMBER
Consult Factory
IDT7M203S55C
SPEED
(ns)
55
70
IDT7M134S90C
90
380
D58
~
100
380
D58
120
380
D58
140
380
D58
IDT7M134S100CB
IDT7M134S120C
IDT7M135S120CB
IDT7M134S140CB
70
640
D58
IDT7M135S90C
90
640
D58
IDT7M135S90CB
100
640
D58
IDT7M135S100CB
IDT7M135S120C
120
640
D58
140
640
D58
IDT7M135S120CB
IDT7M135S140CB
I DT7M203S1OOC
Com'l.
65
IDT7M203S140C
Com'l.
100
140
IDT7M136
Consult Factory
IDT7M137
Consult Factory
IDT7M144S70C
70
380
D58
IDT7M144S90C
90
380
D58
Mil.
100
380
D58
Com'l.
fMil.
176
D28-1
176
D28-1
IDT7M204S40C
40
176
D28-1
50
176
D28-1
Com'l.
I DT7M204S50CB
Com'l.
IDT7M204S55C
~
Com'l.
~
Com'l.
~
55
Com'l.
IDT7M204S65C
~
I DT7M204S1OOC
r--Mil.
IDT7M204S100CB
Mil.
IDT7M204S140C
120
380
D58
140
380
D58
65
176
D28-1
230
100
176
176
Com'l.
Com'l.
~
Com'l.
r--Mil.
D28-1
Com'l.
~
230
140
D28-1
230
IDT7M205
Consult Factory
IDT7M206
Consult Factory
Com'l.
~
Com'l.
Com'l.
IDT7M624S30C
30
x4= 1100
D40-1
Com'l.
D40-1
Com'l.
x8 = 1380
x16 = 1950
Com'l.
IDT7M624S45C
45
x4= 1100
x8 = 1380
Cem'l.
Mil
IDT7M144S120CB
D28-1
230
IDT7M204S65CB
Com'l.
176
Com'l.
~
230
I DT7M204S55CB
Mil
IDT7M144S100CB
IDT7M144S140CB
D28-1
176
IDT7M204S50C
Mil
IDT7M144S90CB
IDT7M144S120C
Com'l.
fMil.
230
IDT7M204S140CB
IDT7M144S100C
D28-1
230
IDT7M203S140CB
r---
176
230
I DT7M203S1OOCB
~
OPER.
TEMP.
Mil.
IDT7M135S70C
IDT7M135S100C
IDT7M203S65C
I DT7M203S65CB
IDT7M134S90CB
IDT7M134S100C
Com'l.
PACKAGE
TYPE
230
IDT7M203S55CB
IDT7M134S70C
Icc (MAX.)
(mA)
x16 = 1950
Mil.
~
x4 = 1100
IDT7M624S45CB
x8 = 1380
IDT7M145S70C
70
640
D58
IDT7M 145S90C
90
640
D58
100
640
D58
120
640
D58
140
640
D58
55
x4 = 1100
Com'l.
x16 = 1950
I DT7M624S65C
65
x4= 1100
x8 = 1380
40
176
D28-1
Com'l.
50
176
D28-1
Com'l.
IDT7M203S50CB
230
Mil
x4 = 1100
x8 = 1380
Mil.
IDT7M203S40C
Com'l.
x16 = 1950
I DT7M624S55CB
Com'l.
IDT7M203S50C
D40-1
x8 = 1380
Mil
IDT7M145S120CB
IDT7M145S140CB
IDT7M624S55C
Mil
IDT7M145S100CB
IDT7M145S120C
Com'l.
Mil
IDT7M145S90CB
IDT7M145S100C
x16 = 1950
Com'l.
x16 = 1950
~
7-83
D40-1
Com'l.
I
ORDER PART
NUMBER
IOT7M624S65CB
SPEED
(ns)
IcC
Al0-Ao(R)
D7-Do(R)
a:
w
w
C
~
C
r-
D(L)
w
WE(L)
In
OE(L)
..J
~2
w
DUAL-PORT
RAM CHIP
2K x 8
IDT7132
C
w
..J
In
2«
Z
w
CE(R)
BUSY(R)
BUSY(L)
0
uw
OE(R)
CE(L)
"-
C
A(R) I D(R) ~ ~
WE(R)
~ A(L)
0
U
w
"-
:f
u
L....-
A(L)
' - - D(L)
~ WE(L)
OE(L)
A(R)
D(R)
DUAL-PORT
RAM CHIP
2K x 8
IDT7132
'--
I--
OE(R)
CE(R)
BUSY(R)
BUSY(L)
U
WE(R)
CE(L)
3
:f
r-
3300
3
'---
3300
+5
+5
BUSY
SRDAN02-OO7
Figure 7: Depth Expansion of Dual-Port RAMs
8-13
APPLICATION NOTE AN-Q2
DUAL-PORT RAMS SIMPLIFY COMMUNICATION IN COMPUTER SYSTEMS
DUAL-PORT MEMORY EXPANSION:
MAKING BIG ONES OUT OF LITTLE ONES
WIDTH EXPANSION:
THE BUSY LOCK-UP PROBLEM
Dual-port RAM chips can be combined to form large dualport memories. Expansion in memory depth with dual-port
RAMs is similar to expansion in depth for conventional RAMs.
An example of this kind of expansion is shown in Figure 7
where an aK x a dual-port RAM has been made out of 2K x a
dual-port RAM chips.
Dual-port RAMs can also be expanded in width. However in
this case, we have a subtle problem. Expansion in width
implies that several dual-port RAM chips will be active at the
same time. This is a problem if several hardware arbitrators are
active at the same time. If we examine the case of a 16-bit RAM
made out of two a-bit RAMs, we can better understand the
WIDTH EXPANSION WITH SLAVE LOGIC (NOT RECOMMENDED)
A1Q-Ao(L)
A(L)
A(R)
D(L) DUAL-PORT D(R)
WE(L) RAM CHIP WE(R)
__
2Kx8
__
OE(L) IDT7132 OE(R)
CE(L)
CE(R)
D7-Do(L)
WRITE ENABLE TIMING (L)
READ(L)
CHIP ENABLE(L)
BUSY(L)
SLAVE
LOGIC
D1S-Ds(L)
~
READ(R)
CHIP ENABLE(R)
BUSY(R)
BUSY(L)
I
WRITE ENABLE TlMING(R)
330n
330n
I
15
-
A(R)
A(L)
'--
D(L) DUAL-PORT D(R)
WE(L) RAM CHIP WE(R)
__
2Kx8
__
OE(L) IDT7132 OE(R)
CE(L)
CE(R)
NC-< BUSY(L)
t
BUSY(R)
SLAVE
LOGIC
D1S-Ds(R)
BUSY(R) P-NC
WIDTH EXPANSION WITH SLAVE CHIPS (RECOMMENDED)
A1Q-AO(L)
A(L)
D(L)
D7-Do(L)
WRITE ENABLE TIMING (L)
READ(L)
A1o-AO(R)
DUAL-PORT A(R)
RAM CHIP D(R)
D7-Do(R)
WE(L) MASTER WE(R)
WRITE ENABLE TlMING(R)
OE(L)
READ(R)
OE(R)
2K x 8
CE(R)
IDT7132
BUSY(R)
BUSY(L)
--
--
CE(L)
CHIP ENABLE(L)
BUSY(L)
f
330n
330n
CHIP ENABLE(R)
BUSY(R)
1
15
D1S-Ds(L)
~ A(L)
D(L)
WE(L)
DUAL-PORT A(R)
RAM CHIP D(R)
SLAVE
WE(R)
-
D1S-Ds(R)
OE(R)
2K x 8
CE(L) . IDT7142 CE(R)
BUSY(L)
BUSY(R)
OE(L)
--
SRDAN02-00B
Figure 8: Width Expansion of Dual-Port RAMs
8-14
APPLICATION NOTE AN-02
DUAL-PORT RAMS SIMPLIFY COMMUNICATION IN COMPUTER SYSTEMS
problem. If the addresses for both ports arrive simultaneously
at both RAMs, it is possible for one RAM arbitrator to activate
its L busy signal and the other RAM to activate its R busy signal. If both busy signals are used on each side, we now have a
situation where both sides are simultaneously busy. The system is now locked up since both sides will be busy and both
CPUs will wait indefinitely for their port to become free.
internally disable its write enable. Slave chips provide a speed
advantage over systems which use external logic to implement
the slave function. Since the slave logic is built into the slave
RAM chip, it can be designed so that there is no speed penalty
when using slave chips to expand the dual-port RAM width.
WIDTH EXPANSION: WRITE TIMING
When expanding dual-port RAMs in width, the writing of the
slave RAMs must be delayed until after the busy input at the
slave has settled. Otherwise, the slave chip may begin writing
while the busy signal is settling. This is true for systems using
slave chips and for systems using conventional dual-port RAMs
with slave logic. This delay can be accomplished by delaying
the write enable to the slave by the arbitration time of the
master. This is shown in Figure 9.
Note that the write delay is required only in width expanded
systems which use slave RAMs; not in single chip or depth
expanded systems where only one chip is active at a time. This
is because the individual chips have a built-in delay between
the chip select and write enable inputs and the internal write
enable to the RAM. Separate timing must be supplied in the
slave case because this internal delay time can be balanced to
the arbitration time only within a chip and can vary from chip
to chip. If the delay time for the slave is less than the arbitration
time of the master, writing could begin before BUSY became
active, as above. This will increase the write cycle time in most
cases.
THE BUSY LOCK-UP SOLUTION:
USE ONLY ONE ARBITRATOR
The solution to this busy lock-up problem is to use the arbitration logic in only one RAM and to force the other RAM to
follow it. In this case one RAM is dedicated as the arbitration
master and additional RAMs are designated as slaves. Two
solutions to this problem are shown in Figure 8. One solution
is to add external logic to the chip-enables of additional dualport RAM chips. The logic gates shown cause the slave RAM
chip select to be disabled if the master RAM is busy. Since only
one set of arbitration logic is controlling the system, the problem of slave lock-up is avoided.
The second, more desirable solution is to use specially
designed dual-port RAM slave chips, which are part of lOT's
product line. These slave chips incorporate the slave disable
logic internally so that no additional logic is required to make a
master/slave combination. In the slave chip, the busy pin
serves as an input rather than an output. If the master chip
activates BUSY, the slave chip will sense this busy state and
ADDRESS LINES
-
CE
R/W
I
---
I
I--WRITE
DELAY
r
r-
I
---
I----
WRITE
DELAY
___ ARBITRATION
DELAY
SRDAN02-009
Figure 9: Masler/Slave Wrile Timing
8-15
DUAL-PORT RAMS SIMPLIFY COMMUNICATION IN COMPUTER SYSTEMS
APPLICATION NOTE AN-02
A10-A OCR)
07-00(R)
-AO(L)
Do(L)
f- A(L)
015- Da(L)
W-E(L)
TIM ING,--
,--
CE(L)
BLOC K
SELE CT
0
l'
co
'"
1=
0
u.
Ii!:
I-
Q 1
j
-<
A(R)
DUAL-PORT
D(R)
D(L)
RAM CHIP
MASTER
WE(L)
WE(R)P
2K x 8
CE(L)
CE(R)P
IDT7132
BUSY(R)b
BUSY(L)
A(R)
A(L)
DUAL-PORT
D(R)
D(L)
RAM CHIP
MASTER
WE(R) 0--( WE(L)
2K x 8
CE(L)
CE(R) 0IDT7132
--( BUSY(L)
BUSY(R) 0-
~
~
-f
f
~k
k
k
k
A(R)
A(L)
DUAL-PORT
D(R)
D(L)
RAM CHIP
WE(R)
WE(L)
SLAVE
CE(R)
CE(L)
2K x8
BUSY(L)
IDT7142 BUSY(R)b
~
UJ
0
0
f-
f-<:
0
UJ
0
w
...J
III
2
«
z
UJ
"-
J:
0
J
Lc
A(L)
A(R)
DUAL-PORT
D(R)
D(L)
RAM CHIP
MASTER
WE(L)
WE(R)P
2K x 8
CE(L)
CE(R)P
1DT7132
BUSY(L)
BUSY(R)p
l
~IMIN G
0
col-
A(R)
D(R)
A(L)
D(L)
DUAL-PORT
RAM CHIP
WE(R)P.
SLAVE
WE(L)
CE(R)
2K x8
CE(L)
BUSY(L) IDT7142 BUSY(R)b
I
0:
015-0 aIR)
WE(R)
CO)
1=
0
l
~f- CE(R)
LOCK
I-
Q
1
0:
UJ
~ A(L)
f- D(L)
i ~
f-<:
f-<:
k;
B
S ELECT
I
A(R)
DUAL-PORT
D(R)
RAM CHIP
SLAVE
WE(R)P
WE(L)
CE(R)
2K x8
CE(L)
IDT7142 BUSY(R)b
BUSY(L)
0
0
0
UJ
0
j
UJ
...J
III
2
«
z
UJ
-
-
---c
j r------c
A(R)
A(L)
DUAL-PORT
D(R)
D(L)
RAM CHIP
MASTER
WE(L)
WE(R)P2K x 8
CE(L)
CE(R)~
IDT7132
BUSY(R)
BUSY(L)
r-
A(R)
DUAL-PORT
D(R) i-RAM CHIP
SLAVE
WE(R) 0-CE(R)
2K x 8
FCE(L)
BUSY(L)
IDT7142 BUSY(R)
-
--<
A(L)
D(L)
WE(L)
Cr---
3
'-
"-
J:
0
j
~
3300
(L)
+5
+5
B
3300
SADAN02-010
Figure 10: Width and Depth Expansion of Dual-Port RAMs
by the chip enable. The write enable is set-up in advance by
the WR signal from the Z80, and the chip enable is used to
write data into the RAM or to gate the read data onto the Z80
bus. The output enable (not shown) is tied to ground (continuous enable). The write enable is used to disable the output
drivers.
In Figure 12, two 68000 microprocessors communicate
through a pair of dual-port RAMs. An IDT7132/7142 master/slave
pair is used to avoid the busy lock-up problem. Note that the
Address Strobe (AS) from each 68000 is used with an address
decoder to enable the dual-port RAM chips. This is to maintain
the address for read-modify-write cycles so that arbitration is
not lost between the read and the write. This is important for
Test and Set instructions, for example.
In Figure 13, a Z80 and a 68000 communicate using a pair of
IDT7132 dual-port RAMs. No slave logic is required because the
Z80 side chip enable decode insures that only one RAM chip
will be enabled at a time. Otherwise, this ficture is a combination
of the logic from Figures 11 and 12.
WIDTH AND DEPTH EXPANSION: AN EXAMPLE
These techniques for expanding dual-port memories in width
and depth are combined in the example shown in Figure 10. In
this example an 8K x 16 dual-port memory is made from 2K x 8
chips in master/slave combination.
USING THEM: DUAL-PORT
RAM APPLICATION EXAMPLES
Examples of dual-port RAMs used for CPU-to-CPU communication are shown in Figures 11, 12 and 13. In Figure 11 a pair
of 8-bit processors communicate using a single 2K x 8 dualport RAM chip. Figure 12 shows a similar system where a
pair of 16-bit processors communicate using a pair of dual-port
RAM chips and a master-slave configuration. Finally in Figure
13 we have an 8-bit processor communicating with a 16-bit
processor through two 2K x 8 dual-port RAMs.
In Figure 11, two Z80 microprocessors communicate using a
single IDT7132 dual-port RAM chip. The IDT7132 is controlled
8-16
DUAL-PORT RAMS SIMPLIFY COMMUNICATION IN COMPUTER SYSTEMS
A(l)
ADDRS
DATA
"
f---<:l
"p
WAIT
MREO
DUAL-PORT
RAM CHIP
D(l)
WR
Z80: 8-BIT
APPLICATION NOTE AN-02
I
~~
P-
2K x 8
IDT7132
CEIL)
BUSY(l)
WW
Q....Jc
J:c(u
UZ w
wc
-alO
'-~
-
DATA
+~
CE(R)
BUSY(R)
RAM
RAM
-
DATA
-
WE
CE
CE
ADDRS
ADDRS
EPROM
EPROM
CE
DATA
Z80: 8-BIT
"p
WAIT
I
ADDRS
WE
DATA
WR
0-
l[
330n
ADDRS
I-- DATA
f-------
SA DAN02-012
APPLICATION NOTE AN-02
DUAL-PORT RAMS SIMPLIFY COMMUNICATION IN COMPUTER SYSTEMS
DATA BITSS-15
AD DRS
a: DATA
A(L)
Ul
f-Ul
_w
A(R)
DUAL-PORT
RAM CHIP
D(L)
0
WR
r;
!DO
a!. 0
ag:
~~ WAIT
fwEm
WE(R)
MASTER
2K x8
IDT7132
OE(L)
CE(L)
OE(R)
CE(R)
BUSY(L)
BUSY(R)
0
:!iMREQ~
~
DATA BITS7-0
-
A(L)
A(R)
DUAL-PORT
RAM CHIP
D(L)
WE(L)
D-
~
OE(L)
CE(L)
330n
DATA BITSs-15
0
0
w
w
---____o-1
CORRECT D>-------o-l
Figure 4A. Check Bit Generation in the IDT49C460
LEOUT/GENERATE 0 . - - : ; - - - - - ,
OE BYTEQ-3 D':'8-~--'
CB~7 D~._---~~-------------__,
~~3~2~~~~~~
DATAo-311!i
MULTERROR
LEOIAG
CODE 10
DIAG MODE
LEOUT/GENERATE
CORRECT
O~----;==::...--,
D...;2......_-+I
0",2=';-_-+1
D>-----I-I
Cl>-----I..j
Figure 4B. Error Detection and Correction Data Flow in the IDT49C460
MEMORY LOCATION
A
A
HOST COMMAND TO
WRITE BYTE "E"
AT MEMORY LOCATION
B
E
o
'------+I. CHECK
Figure SB. Byte-Write Operation, Step 2: Newly Generated
Check Bits Corresponding To Bytes A, B, E, and 0
Are Written To Memory Along With Bytes.A, B, E, and 0
Figure SA. Byte-Write Operation; Step 1. Read 32-Bit Word
and Correct Any Single-Bit Error
8-22
APPLICATION NOTE AN-03
TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32- OR 64-BIT EDC
The IDT49C460 is expandable to 64-bit wordlengths as shown
in Figure 6A. The external buffer may not be required if Ihe
path from the memory already has a three-state buffer in its
output stage or externally in the data path to the EDC. Figure
68 shows a 2-step operation when an error detection and correction occurs in bit 32-63 of the 64-bit word. The IC on the
first level, with the code ID=10, receives the data bits 0-31 and
the entire check bits. In the example shown, bit 63 has erroneously flipped from a "1" to a "0". The partial syndrome bits are
passed from the first device to the second. (The actual syndrome bits are generated from a table not shown in this article
but are in the IDT49C460 data sheet.) The check input latch of
the second device is open, due to its code ID=ll, and the partial syndrome bits are combined with the data bits to generate
the final syndrome bits. The final syndrome bits indicate that
bit 63 is in error and it is inverted to produce a correct result.
The final syndrome bits are also sent back to the first device,
but the resulting syndrome does not alter any data bits in the
first device. Therefore, the error correction is a 2-step process.
In Figure 6C, an error occurs in bits 0-31. In this case, the partial syndrome is sent to the second device. The second device
generates the final syndrome and sends it back to the first
device. Finally the erroneous bit is flipped over. In this case, a
3-step operation takes place.
>
STEP 2
-
8y virtue of their function, EDC ICs tie in closely with system
memory architectures. Figure 7 shows a host that generates
addresses and accesses a memory system. The memory contains memory elements, error detection logic and interface
circuits. These are needed to start a memory cycle, to send/receive data on the system bus, and to inform the host that it has
completed the memory operation.
One may use EDC for dynamic RAM memories or static
RAM memories. Figures 8A and 88 show general configurations for DRAM arrays. Normally, in DRAM systems, separate
pins exist for the DATAoUT and DATA IN. Therefore, IDTFCT244s
can be used to provide an isolation between the DATA port of
the EDC and the DATAOUT from the RAM. This isolation may
be required after a read operation, and the EDC provides
corrected data to the system and the DRAM. Another buffer is
needed between the DATA port of the EDC and the system
data bus to allow the corrected data to be placed on the
system bus. The DRAM controller can be implemented using
standard off-the-shelf products. An important operation that
has to be supported is byte or word handling. The IDT49C460
EDC configuration shown in Figure 8A has four individual
byte enable controls going to the IDTFCT244s and their
complements to the IDT49C460. The IDT39C60 shown in
Figure 88 has two individual byte controls to the IDTFCT244s
and their complements going to the IDT39C60.
In stalic RAM systems, as shown in Figure 9, there is no
need for a dynamic memory array controller; however, bidirectional buffers are required on the ports of the static RAMs as
RAMs have common I/O lines for data. If the SRAMs had
separate I/O pins for the data, the buffer configuration of the
DRAM array could be used.
The timing controller, common to both DRAM and SRAM
systems, controls the buffers and the EDC ICs. This is an
interesting task to the memory system designer, as a choice of
EDC architectures are available.
Figure 6A. The IDT49C460 In A 64-Bit Configuration
CHECK
30
WRITE
FFFFFFFFFFFFFFFE
30
READ
3O(INPUT CHECK BITS)
ADRS
>
MEMORY
STEP 1
OO(PARTIAL SYNDROME)
CODE=ll FFFFFFFE(BITS 32-63)
FFFFFFFFF(CORRECTED 32-63)
OO(PARTIAL SYNDROME)
STEP 3
HOW THE IDT49C460 FITS IN A SYSTEM
11
FFFFFFFFFFFFFFFF
STEP 1
Figure 6C. Error Correction On A 64-Bit Word, With Error in Bits 0-31
OUTPUT SYNDROME/CHECK BITS
CDDE=10 FFFFFFFF(BITS 0-31)
2F(PARTIAL SYNDROME)
2F(FINAL SYNDROME)
CODE=10 FFFFFFFF(CORRECTED BITS 0-31) 2F(FINAL SYNDROME)
OESC
DATA
>
30(INPUT CHECK BITS)
FFFFFFFF(BITS 32-63)
CODE
ID = 10
CODE ID =
READ
CODE=ll FFFFFFFF(BITS 32-63)
IDT49C460A
DATA
WRITE
30(CHECK)
2F(PARTIAL SYNDROME)
OEsc
DATAo-31
30(CHECK)
FFFFFFFEFFFFFFFF
CODE=10 FFFFFFFE(BITS 0-31)
INPUT CHECK BITS
DATA32-63
CHECK/SYNDROME
DATA
FFFFFFFFFFFFFFFF
>
HOST
STEP 2
AE(FINAL SYNDROME)
DATA
"'CONTROL~
INTERFACEi
EDC
CODE=10 FFFFFFFF(UNCHANGED 0-31)
Figure 6B. Error Correction On A 64-blt Word,
When Error Is In Bits 32-63
Figure 7. A "TYPical High-Reliability Memory System
8-23
TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32- OR 64-BIT EDC
APPLICATION NOTE AN-03
DRAM ARRAY
DRAM ARRAY
DATA BITS
14--I:3"'2;---i DATAoUT
IDT49C460
lOT
FCT244s
IDT39C60
DATA 1---......~--t----,1.;:32
...-fDATA'N
OEO-31+--.f4, - - I - - -....
'2
BYTE
HANDLING
CONTROLS
~
DRAM
CONTROLLER
,---
lOT
FCT24Ss
.....
'----
ADRS CONTROLS
RAS
CAS, WE
t,v
DRAM
CONTROLLER
TIMING
CONTROLLER
(PAL-BASED)
TIMING
CONTROLLER
(PAL-BASED)
DATA BUS
DATA'N
~
t
ADRS CONTROLS
RAS
CAS, WE
DATAoUT
OUT
IN CHECK BITS
SC
iiiiERR ERR
BYTE
HANDLING
CONTROLS
16
/
OEO-1
CB
IN CHECK BITS
16
~
DATA
CBI---~--+----t------10UT
SC
DATA BITS
r----7'
HIGH ADRS
DATA BUS
LOWADRS
HIGH ADRS
LOWADRS
tt
CONTROL BUS
ADDRESS BUS
CONTROL BUS
Figure 8A. EDC Logic In 32-BII DRAM-Based Memory Syslems
Figure 8B. EDC Logic In 16-BII DRAM-Based Memory Systems
BUS-WATCH AND
FLOW-THROUGH EDC ARCHITECTURES
STATIC RAM ARRAY
The architecture of EDC ICs can be categorized as BusWatch and Flow-Through as shown in Figure 10. In a buswatch architecture, there is only one bus to handle the data
and one set of pins that handle incoming data from the
memory, corrected data from the EDC, and incoming data
from the system to be written to the memory. The IDT39C60
and IDT49C460 are based on a bus-watch architecture. In a
flow-through architecture, such as Intel's 8206, there are two
ports that handle data movement. The WD'N/DoUT handle
incoming data from the system, so that the EDC can generate
check bits. The second function of the WD'N/DoUT is to supply
the corrected data to the system and the memory. The second
set of pins, D'N, only handle incoming data from the RAM.
These architectures lend themselves to "Check Only" and
"Correct Always" configurations.
The "Check Only" method is used in high-performance
systems. The memory system always sends data directly to the
host when a read is requested. In the event a single bit error
occurs, one approach is that the read cycle is delayed and a
correction is performed. The corrected data is sent to the host
and written into the memory. In this case, the timing control
circuit would disable the Memory Data Out Buffer (the
IDTFCT244 for the DRAM case and the IDTFCT245 for the
static RAM case) and put corrected data from the EDC IC onto
the system data bus, also writing the corrected data back into
the memory array. For the "Check Only" method, the DATA TO
ERR parameter is of key.concern to designers as this can be
used to generate the DTACK, READY or BERR signals to the
host.
DATA BITS
IDT39C60
OR
IDT49C460
DATAOUTIIN
DATA 1------1
CB I+------..-+--I
CHECK BITS
OUTIIN
lOT
FCT245s
DATA BUS
HIGHADRS
CONTROL BUS
ADDRESS BUS
LOW
ADRS
ADDRESS BUS
Figure g, EDC Logic In 16-, 32- or 64-BII StaUc RAM-Based Systems,
8-24
TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-0R 64-BIT EDC
The other option is that a "Correct Always" method is used.
In this case, the EDC always corrects data (regardless of the
fact that it may be error-free), sends it on the system data bus
and writes it back to the memory. In this case, the cycle time
for the data read includes the "DATA'N TO CORRECTED
DATAOUT" parameter for the EDC. The IDT49C460 and the
IDT39C60 provide the fastest timings for the "DATA'N TO
ERR" and "DATA'N TO CORRECTED DATAOUT" parameters
when compared to other currently available 32-bit and 16-bit
EDCs. This was made possible by using IDT's CEMOS'· 111.21'
process.
The IDT49C460A dissipates only 95mA and the IDT39C60A
dissipates only 85mA over the commercial temperature range.
The quiescent power consumption is only 5mA for the
IDT49C460A and the IDT39C60A.
The delay for the DATAIN TO ERR is only 30ns for the standalone 32-bit IDT49C460A (worst case commercial) and is 46ns
for the 64-bit cascaded case. The delay for the DATAIN TO
CORRECTED DATAOUT is only 36ns for the stand-alone case
and 63ns for the 64-bit cascaded case. These parameters are
very important when considering EDC ICs discussed further in
a later section. They are, however, shown in Tables 4 and 5 for
the 16-bit IDT39C60 and 32-bit IDT49C460, respectively.
The acid test is how a flow-through architecture compares in
performance to a bus-watch architecture in the "Check Only"
mode and the "Correct Always" mode. In Figure 11, a flowthrough EDC device is connected to a DRAM array system for
"Check Only" operations. Data from the memory goes through
the IDTFCT244 buffer to the system bus directly and simultaneously to the EDC device. Within the DATA'N TO ERR of the
device, it is determined if a single-bit error occurred and, if so,
APPLICATION NOTE AN-03
a timing controller would disable the IDTFCT244 and allow
corrected data to be sent on the system bus via the
IDTFCT245.
A bus-watch EDC in a "Check Only" configuration is shown
in Figure 12. The data path from the DRAM to the EDC goes
through one IDTFCT244 delay and is identical to the flowthrough case. After that the DATA'N TO ERR delay determines
whether or not the cycle would be stretched. The data from the
DRAM goes through a IDTFCT244 buffer and an IDTFCT245
buffer in the bus-watch case. One emerging fact is that the
time it takes to make a decision to stretch a memory cycle is
the same for bus-watch and flow-through EDC parts and is
determined by the DATA'N TO ERR of the respective devices.
In the flow-through "Correct Always" configuration, as shown
in Figure 13, data has to always pass through the EDC and any
IDTFCT245 and on to the system bus. In the case of bus-watch
ICs, data from the DRAM goes through an IDTFCT244, in and
out the EDC device and through an IDTFCT245 as shown in
Figure 12. A bus switch has to take place every cycle as
memory data comes into the EDC, is corrected and then
transferred to the system bus. In a practical design this bus
switch may be the longest delay path for "Correct Always".
TABLE 4:
KEY PARAMETERS FOR THE
IDT39C60/-1/A FOR COMMERCIAL RANGE
IDT39C60
IDT39C60-1 IDT39C60A
DATA'N TO ERR
32n5
25n5
20n5
DATA'NTO
CORRECTED DATAoUT
65n5
52n5
30n5
TABLES:
KEY PARAMETERS FOR THE
IDT49C460/A FOR COMMERCIAL RANGE
MEMORY
CONDITIONS
SYSTEM DATA BUS
IDT49C460 IDT49C60A
2-49C460As
FOR
64-BIT EDC
DATA'N TO ERR
40n5
30n5
46n5
DATA'N TO CORRECTED
DATAoUT
49n5
36n5
63n8
CBOUT CB'N
BUS-WATCH EDC
MEMORY
SYSTEM DATA BUS
lOT
FCT244
SYSTEM DATA BUS
lOT
FCT245
DATAIN
CBOUT
CBIN
DOUT
DIN
DIN
DOUT
WD'N/
DIN CBOUT CB'N
DOUT
FLOW-THROUGH EDC
Figure 10. Architecture Of Bus Watch And Flow-Through EDC Logic
Figure 11. The "Check Only" Configuration for Flow-Through EDC ICs
8-25
I
TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32-.0R 64-BIT EDC
lOT
lOT
FCT2451-------r---HFCT244
rected data and the newly generated check bits to the memory.
The memory buffers shown in Figure SA are three-stated, as
the OE MEM BUFF are high from state 7 onwards and the EDC
would be enabling data on the bus. The timing diagram in Figure 14 explains a typical case and users will have to customize
it based on their memory speeds and the time the system has
for receiving valid data.
Other factors that may be a consideration are package count
and board space. The number of packages used in flowthrough and bus-watch implementations are the same for
"Check Only" configurations. In "Correct Always" configurations the bus-watch implementation requires four more
IDTFCT244s than the flow-through implementation. Flow-through
ICs have more pins and therefore leave a larger footprint on
the PC. However, in terms of board space, since the footprint
of the flow-through EDC is larger than the bus-watch, the buswatch approach takes less space for "Check Only" configurations and there is a tie for the "Correct Always" configuration.
Dour
DATA
IDT49C460
OR IDT39C60
DIN
CBIN 1------1 Dour
CHECK
CBour .......- - - - - - 1 DIN
Figure 12. The Bus-Watch EDC In
"Check Only" Or ·Correct Always" Configurations
SYSTEM
DATA
BUS
lOT
FCT245
WDINI
Dour
APPLICATION NOTE AN-03
o
DIN
DATA
Dour
STATE"
RAS
1 2 3 4 5 6 7 8 9 10 11 12 1314 15 0
i
~~
i
iii
ii,
I
ROW/COL ----.
CAS
DIN
CHECK
Dour
OE MEM BUF
,
I
I
Iii
______________________-''----,----,-----
------.'-----...J,..---------
DATA _ _ _ _-==,....~ATAour FROMEDC
DATAIN TO EDC
LEIN------....;;.;---,.\
I
Figure 13. A Flow-Through EDC In "Correct Always" Mode
However, if just the specification is being reviewed, the flowthrough path is shorter by an IDTFCT244 delay. A specification
comparison is that the "DATAIN TO CORRECTED DATAour"
delay of a flow-through EDC part should be compared to the
"DATAIN TO CORRECTED DATAour" delay of the IDT49C460/A,
plus an external 7ns buffer delay (for the IDTFCT244). However,
in an actual system such as the one in Figure SA, a "bus-switch"
has to take place, as explained below.
In a DRAM system that has a bus-watch EDC, a sequence of
events has· to be created by the timing controller that was
shown in Figure SA. The timings that the controller generates
are shown in Figure 14. The example being considered is "Correct Always." The RAS, CAS, WE signals have to be generated
to read data from the DRAM. The read takes place before state
7, and the read data is latched in the DATAIN latch of the EDC.
It is then corrected and the corrected data can be latched in
the DATAoUT latch. The data correction can take place between
states 7 and 10. Any time after state 10, the EDC can place the
corrected data on the bus. The bus that was loading the data in
the EDC has to be turned around as the EDC is going to send
corrected data to the host. The EDC also writes back the cor-
LEour/GEN - - - - - - - - - - - - . . ,
Of ON EDC --------------------\....______..J
READ/WRITE-----------,
-NOTE: A BUS-SWITCH TAKES PLACE BETWEEN STATES 6 AND 10
Figure 14: Timing Diagram For Correct Always In Figure 7A
SUMMARY
This article has covered reliability issues in memory systems
and solutions using EDC devices. In considering EDC devices,
two parameters are critical: the "DATAIN TO ERR" and the
"DATAIN TO CORRECTED DATA our". At Integrated Device
Technology, we have optimized these two parameters and produce ultra fast, TTL-compatible CMOS Error Detection and
Correction devices for high performance 16-, 32- and 64-bit
systems.
CEMOS is a trademark of Integrated Device Technology, Inc.
Integrated Device Technology, Inc.
3236 Scott Blvd., Santa Clara, CA 95054-3090 • Telephone: (408) 727-6116 • TWX 9103382070
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this application note in order to
improve design or performance and to supply the best possible product.
8-26
by Suneel Rajpal
INTRODUCTION
data input registers. If more parallelism is required, a separate
ALU can be used to compute addresses concurrently with an
ALU that is computing data from the previous instruction.
Figure 2 contains the microprogram sequencing and the control store section. This typically consists of a microprogram sequencer, a control store, pipelines, registers, and some MSI for
condition code selection. The IDT39C10B is a 12-bit microprogram sequencer that is plug-compatible with all versions of
the2910. One of four sources can be selected as the next address:
the microprogram address register, the LIFO stack, the internal
register/counter, or the direct D input. An added feature in the
IDT39C10 is the deeper stack with 33 locations instead of nine
provided by the 2910 sequencer. Figure 3 shows a plausible
arrangement of ALUs, multiplier/ multiplier-accumulators and
extended data storage. A computation for worst-case cycle time
for the control path is shown in Figure 4. The corresponding
worst-case delay for the data path is shown in Figure 5. It is an
interesting exerciseto analyze these two delay paths. The control
path has a 64ns delay and the data path has a 49nsdelay, adding
to the I DT 49C402 delay and register propagation delay and setup time. The IDT49C402, shown in Figure 6, is code-compatible
Traditionally, high-speed number-crunching requirements
could only be fulfilled by bipolar (TTL) components. However,
with the advent of advanced CMOS technologies, one can not
only attain higher densities and lower power consumption, but
also attain higher speeds. This paper deals with different building blocks that can be used to build integer or floating-point
processors at speeds greater than 10MHz.
FIXED-POINT PROCESSORS
In order to build a high-speed efficient fixed-point processor,
a number of computational elements are required. A high-speed
ALU and a multiplier are all integral parts of a high-speed
processor. These building blocks must be cascadableor expandable for higher-precision numbers. High-speed memories are
also required for data storage and for control store which essentially drives the system. A typical microcoded system is shown in
Figure 1. It consists of three sections: the control section, the
address generation section and the number-crunching section.
The key elements in the control block and number-crunching
block, shown in Figure 1, are illustrated in Figures 2 and 3. (The
address generation can be supported by the architecture in Figure 3.) An instruction is fetched from the main memory (not
shown). Then the opcode is decoded to cause a jump to the
appropriate address in the control store. This address is the start
address of the microinstructions that emulate the macroinstruction.
The next step may be to fetch the operands; this is done by
putting the address on the address bus and bringing data into the
OPCODE
MAPPING
RAM
IDT71682
DATA
DATA
CALCULATIONS
WRITEABLE CONTROL
STORE IDT71682
DSPANQ4-Q01
DSPAN04-002
Figure 1. A Typical CPU
@
1986 Integrated Device Technology, Inc
Figure 2. The Instruction Decoder and Microprogram Sequencer
8-27
Printed In U.S.A
6/B6
HIGH-SPEED CMOS TTL-COMPATIBLE NUMBER-CRUNCHING ELEMENTS
FOR FIXED- AND FLOATING-POINT ARITHMETIC
APPLICATION NOTE AN-04
Blazing fast speeds of the multipliers are needed in systems
where the operands are of longer wordlength (>16 bits). For
example, if fixed-point 32-bit operands are to be multiplied, four
partial products have to be added, as shown in Figure9. The four
partial products can be generated in parallel using four multipliers
and adding the partial products at their appropriate binary
weighting. Alternately, the partial products can be added using
one multiplier while doing shift and add operations in the
IDT49C402, using the register space efficiently.
to the 2901 and has 64 registers in the register file. There are eight
additional destination functions that allow direct loading ofthe Q
register orthe RAM, thereby enhancing the overall performance.
The additional destination functions are shown in Table 1.
If multipliers are used in the data path, the pipelined delay of
35ns forthe 1DT7216/IDT7217 (16x 16 multipliers) is far less than
the sequencer delays and ALU delays. The other data path of
concern is a multiplier output that is added in the IDT49C402,
shown as Path 2 in Figure 5. It is only 45ns, less than both the
Data Path 1 delay and the Control Path delay. The IDT7216 is pin
and functionally compatible to the TRW MPY-016H/K and
Am29516. The IDT7217 is pin and functionally compatible to the
Am29517. If a multiply-accumulate function is required, an
IDT7210/IDT7243 (16 x 16 MACs) can provide sum-of-products
at 35ns clocked speeds. The IDT721 0/1 DT7243 are pin and functionally compatible to the TRW TDC10l0/l043 multiplieraccumulators. Generic block diagrams for the multipliers and
multiplier-accumulators are shown in Figures 7 and 8.
The multipliers operate on unsigned two's complement or
mixed mode numbers. In every clock cycle, a 32-bit product is
generated and either the least significant or the most significant
half can be read through the output lines. The least significant
of the product is also shared with the YO- 15 input lines. IDT7216/
IDT7217s are capable of running at 35ns clocked multiply rates
over the commercial temperature range and 40ns over the
military temperature range.
The multiplier-accumulator, 1DT721 0, provides the multiply,
multiply-add and multiply-subtract functions. Three bits of overflow are provided, corresponding to a 35-bit accumulator. The
IDT7243 is a trimmed version of the IDT7210 that does internal
accumulates of 35 bits; but only the most significant 19 bits are
available externally. Also, the IDT7243 has no preload capability.
The multiply-accumulate operations can run at 35ns clocked
speeds for the commercial temperature range. The summarized
performance is shown in Table 2.
Pipeline register CLK-Q
Condition MUX (74F251)
IDT49C410: CC to Y
WCS RAM; IDT71682
Pipeline Register Set-Up
10ns
13ns
16ns
25ns
2ns
Total
64ns
Figure 4. The Control Path Delay
Pipeline register ClK-Q
IDT49C402:AlB to F = 0
Status Register Set-Up
10ns
37ns
2ns
Total
49ns
ClK-Q, 1DT7216/IDT7217
Data to RAM, Set-Up
25ns
20ns
Total
45ns
Figure 5. The Data Path Delay
DATAIN
t
I RAM SHIFTER I
<;
A
"
CONTROL BIS
~
:=
ADD~~~- r--
I
R~~RRJ~~- r--
DATA INPUT RGTR
IDTFCT374
vIAMU~
•
t
'+ REGISTER FILE
~~
- :n G
T
R
'--
I
IDT7216/IDT7217
MEMORY
RDRSRGTR
IDTFCT374
I
ADDRESS BUS
PIPELINED
REGISTER
IDTFCT374
•
t
B
t
IDT49C402
II
-
IQSHIFTERI
64 WORD RAM
(64 REGISTERS)
I
D
A
I
QREGISTER
! ILO~col
t
B
0
Q
B LATCH
1
16X 16
MULTIPLIER
PIPE LINED
REGISTER
IDTFCT374
A
A LATCH
ANDALU
I
.-
BDATAIN
DATA BUS
l
STPO:rUS RGTR
(TOS EQUENCER
S
T
A
<;
t
A
I
J
ALU DATA SOURCE SELECTOR
I
R
I
S
+
RINPUT
I
SINPUT
+
a-FUNCTION
ALU
I
t
I OUTPUT DATA SELECTOR AND DRIVERS
"
I
l
DSPAN04-{I03
DATAoUT(Y)
DSPAN04-006
Figure 3. The Address and Data Calculations Unit
Figure 6. The IDT49C402 Block Diagram
8-28
HIGH-SPEED CMOS TTL-COMPATIBLE NUMBER-CRUNCHING ELEMENTS
FOR FIXED- AND FLOATING-POINT ARITHMETIC
APPLICATION NOTE AN-04
the additional of the MS part of the XB·YA and XA-YB. This result
is added tothe LS part of XA·YA. Finally, the sign extension olthe
previous operation is added to the MS part of XA·YA. By using the
register file of the IDT49C402 efficiently, one does not have to
perform 16-bitshifts with each partial product addition, resulting
in a fairly efficient 32 x 32 multiplication.
A high-speed 12MHz fixed-point processor can be built
using the parts shown in Figures 2 and 3-namelythe IDT39Cl0
12-bit sequencer or the IDT49C410 16-bit sequencer, the
IDT49C40216-bit ALU, the IDTFCT374, the IDT71682 RAMs, the
IDT7216/1DT7217 multipliers or the IDT7210/IDT7243 multiplieraccu m u lators.
In the example shown in Figure 9, the partial product XA'YA is
stored in two locations of the register file. The Most Significant
(MS) part of XB·YB is added to the Least Significant (LS) part of
XA-YB; the carry-out is saved forthe next addition to the LS part
of XB·YA. The carry-out again is saved for the next operation for
Vo-,slPO-'5
FLOATING-POINT PROCESSORS
In applications that need a larger dynamic range, floating-point
number representation is used. A discrete solution to a 32-bit
floating-point processor can be at least one board of SSI and MSI.
Most designers prefer an IC or an IC set that implements the IEEE
standard over a discrete solution. The implementation problem
only worsens for double precision 64-bit floating point processors. The IDT72064/1DT72065 and IDT72264/1DT72265 provide
compact, low-powered high-speed solutions to single-, and
double-precision IEEE standard 754 version 10.0 calculations.
The IDT72064/1DT72264 are floating-point multipliers; the
IDT72065/1DT72265 are floating point ALUs. All the parts have
similar 1/0 structures. Data input and output transfers may occur
at twice the maximum pipeline rate, allowing the devices to be
used in a variety of bus configurations without degrading performance. The detailed block diagram of the IDT72264 is shown
in Figure 10. The detailed block diagram for the IDT72265 is
shown in Figure 11. Note that, in Figure 10, the IDT72264 takes
two cycles for 32-bit operations and four cycles for 64-bit
operations. The IDT72064, very similar to the IDT72264, takes
four cycles for a 32-bit operation and eight cycles for a 64-bit
operation.
The multiplier and ALU can operate in two modes: one with
pipelined levels and the other with the pipelined registers made
transparent (called the flow-through operation in the data sheets).
For example, the multiplier in Figure 10 can have the following
registers made transparent: PI PEl and the STREG (Status Register), DM and DL registers. This allows the operands to "ripple"
through the logic circuitry at a slower time, as compared to the
pipelined case. A similar configuration is possible for the ALU,
P'6-31 /PO-'5
IDT7216 HAS SEPARATE CLOCKS FOR THE REGISTERS.
IDT7217 HAS A COMMON CLOCK AND SEPARATE ENABLES.
DSPAN04-()07
Figure 7. The IDT7216/1DT7217 Multiplier Block Diagram
x =32-bits XA =X3,.,., Xa =X'5.0
V
=32-bits VA =V3 ,_,., Va =V'5---L~
"C>-;4f-_~
INSTRUCTION
PLA
CI
0Er->----~~-+_-4_----~
IDT49C410 16-Bit Microprogram Seq!lencer.
microcode, while allowing for more microcode to be added to
the application and taking the program beyond the 4K word
boundary. Because the IDT49C410 is microcode-compatible,
older microcode routines can be incorporated in new designs
utilizing the IDT49C410.
The 16-bit IDT49C410 uses approximately 1/4 the power
consumption of the 2910A (which is a 12-bit sequencer), thus
maintaining the 1/5 power consumption on a bit-by-bit basis.
The IDT49C410 consumes, over frequency and temperature
ranges, 75mA for commercial and 90mA for military. The
2910A compares with 340mA for military and 344mA for
commercial. Because of the. lower power consumption, smaller
packaging may be utilized. While the IDT49C410 is offered in a
standard 600 mil wide package with pins on tenth inch spaces,
it is also offered in a package which is 400 mils wide with pins
on 70 mil centers. This is roughly 1/2 the standard package
with regards to area taken up by each package.
COMPARISON OF
MICROPROGRAM SEQUENCERS
IDT49C410A
IDT49C410
2910A
CC-Y(1)
15ns
24ns
24ns
Stack Depth
33
33
9
Address Range
64K
64K
4K
Dynamic Power(1)
75mA
75mA
340mA
NOTE:
1. Reflects performance over commercial temperature and voltage range.
8-42
16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROSLICE COMPATIBILITY YET INCREASE PERFORMANCE
WORKING TOGETHER
The simplified block diagram of an example Central Processing Unit (CPU) is shown below using devices manufactured
by lOT. This CPU architecture can be viewed as two major
sections which have a MICROSLICE family part at the heart of
each. The major section of the left hand side of the diagram is
the control path. The microprogram sequencer at the heart is
the IOT49C410 which generates the address for the microprogram stored in the writeable control store (WCS). The
output of the WCS is registered by the pipeline register.
Together, the sequencer, WCS and pipeline register make up a
state machine which controls the operation of the entire CPU.
In this CPU, the state machine first fetches a machine instruction and captures it in the instruction register. The instruction
register determines the starting address for each sequence of
microinstructions associated with each machine opcode.
In this example, both the microprogram store and the
instruction mapping memory are formed using RAM. The RAM
has separate OATA 1N and OATA oUT buses (IOT71682). This
allows the input side to be connected conveniently to an 8-bit
bus for initialization at power up.
The second major section is on the right hand side. This
section is called the data path. The heart of this section is the
APPLICATION NOTE AN-06
IOT49C402A. In it is contained all of the working registers and
the arithmetic logic unit for performing data computations.
One of the internal registers always contains the value of the
program counter (PC) which is the address at which the
opcode for the machine instruction is fetched. When an opcode
is fetched, the memory address register (MAR) is loaded with
the value of the PC while, at the same time, the value of the PC
plus one is loaded back into the internal register file. The
OATA 1N and OATA oUT registers are used to buffer data coming
from and going to the memory during execution of the machine
instruction.
CONCLUSION
The MICROSLICE family from lOT provides high-performance
CMOS solutions for microprogrammed applications. Not only
does the family provide for yesterday's designs with plugcompatible devices of the IOT39COOO family, it also provides
solutions for future applications. With the IOT49COOO family, the
designer can take advantage not only of the lower power consumption of CMOS, but utilize higher speeds and smaller board
spacing, yielding smaller packaging concepts required by
today's customers. In the future, the IOT49COOO MICROSLICE
family will provide alternative architectures which will provide
for yet higher performance solutions.
16
16
D
ALU
AND
REGISTER
FILE
IDT49C410
IDT49C402
Y
16
ADDR
WRITABLE CONTROL STORE
IDT71682
CONTROL BUS
Integrated Device Technology, Inc.
3236 Scott Blvd., Santa Clara, CA 95054-3090 • Telephone: (408) 727-6116 • TWX 9103382070
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this appilcation note in order to
improve design or performance and to supply the best possible product.
8-43
By David C. Wyland
ABSTRACT
DESIGN OF A CACHE MEMORY
Cache memories are a widely used tool for increasing the
throughput of computer systems. The IDT7174 Cache Tag RAM is
a new component designed to support direct mapped cache
designs by providing the tag comparison on-chip. This allows
relatively large cache memories to be designed with low chip
count. The application of the IDT7174 to cache memory design is
explored by designing a simple cache memory, reviewing its
operation and performance, discussing methods of extending the
design, and then reviewing the theory behind the design of cache
memories in general.
To understand the application of the IDT7174 to cache memories, we will begin by designing one. A block diagram of a cache
memory system using IDT7174 Cache Tag memory chips is
shown in Figure 2. The cache memory serves a 16-bit microprocessor with a 24-bit address bus and a main memory. In this
system, the 13 least significant bits of the address bus are connected to the address inputs of both the cache tag and the cache
data RAM chips. The upper 11 bits of the address bus are connected to the data 1/0 pins of the cache tag RAMs. The remaining
five 1/0 pins of the cache tag RAMs are connected to a logic
1 (+5).
INTRODUCTION
Cache memories are an important design tool for increasing
computer performance by increasing the effective speed of the
memory. Computer memories are usually implemented with slow,
inexpensive devices such as dynamic RAMs. A cache memory is a
small, high-speed memory that fits between the CPU and the main
memory in a computer system. It increases the effective speed of
the main memory by responding quickly with a copy of the most
frequently used main memory data. When the CPU tries to read
data from the main memory, the high-speed cache memory will
respond first if it has a copy of the requested data. Otherwise, a
normal main memory cycle will take place. In typical systems, the
read data will be supplied by the cache memory over 90% of the
time. The result is thatthe large main memory appears to the CPU
to have the high speed of the cache memory.
The IDT7174 Cache Tag RAM introduced by IDT simplifies the
design of high-speed cache memories. It can be used to make a
high-performance cache memory with a low part count. The
IDT7174 Cache Tag RAM consists of a 64K-bit static RAM organ-
~~~~;
Addrs
I
Figure 2: Cache Memory System Block Diagram
The MATCH outputs of the cache tag rams are tied together
and connected to the WAIT input of the microprocessor. A 330
ohm pull-up resistor is used because the MATCH outputs are
open-drain type. The MATCH outputs are positive-active. The
MATCH output goes high when the contents of the internal RAM
are equal to the data on the 1/0 pins. When several cache tag
RAMs have their MATCH outputs connected together, a wireAND function results: all of the comparators must each register a
match before the common MATCH signal can go high.
I n the system shown, the state of the WAIT input to the microprocessor determines whether the memory data is to come from
the cache or the main memory. If the WAIT input to the microprocessor is high, the microprocessor will accept data immediately from the cache data RAMs; if the WAIT input is low, the
microprocessor will wait for the slower main memory to respond
with the data.
To understand how the cache memory operates, we will follow
its operation from start-up in an initially empty state. When the
system is powered-up, the cache tag RAMs are cleared to zero by
a pulse to the initialize pins of the IDT7174 RAMs. This causes all
cells in the RAM to be simultaneously cleared to logic zero. When
the microprocessor begins its first read cycle, the 13 least significant bits of the address bus select a location in the cache tag
RAMs. The location in the cache tag RAMs is compared against
the upper bits ofthe address bus and againstfive bits of logic one.
-----+-_. .::{/
r-__-+-_Match
(Data Input PIns ~
RAM Data Output)
Comparalnput
Figure 1: IDT7174 Cache Tag RAM Block Diagram
ized as 8K x 8 and an 8-bit comparator, as shown in Figure 1. The
comparator is used in direct mapped cache memories to perform
the address tag comparison, and allows a 16K byte cache for a
68000 microprocessor to be built with four memory chips. The
IDT7174also provides a single pin RAM clear control which clears
all words in the internal RAM to zero when activated. This control
is used to clear the tag bits for all locations at power-on or
system-reset when the cache is empty of data. This allows one of
the comparison bits to be used as a cache data valid bit.
©
Data
Data
Printed
1986 Integrated Device Technology, Incorporated
8-44
In
the U.S.A
7/86
APPLICATION NOTE AN-07
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
The MATCH output of the cache tag RAMs will be ,ow because all
cache tag RAM cells were reset to zero, and the zeros from the
selected cell are being compared against the five bits of logic
one. In this case, the microprocessor waits for the slower main
memory to respond. This is called a cache miss.
When the main memory responds with read data for the
microprocessor, this data is also written into the cache data
memory at the address defined by the 13 least significant bits of
the address bus. At the same time, the upper 11 bits of the
address bus and the five bits of logic one are written into the
cache tag memory. This 11-bit address tag, in combination with
the 13 bits of RAM address select, uniquely identify the copy of
the main memory data that was stored. The five logic one bits
serve as a data valid bits which indicate that the data in the cell is a
valid copy of main memory data.
When the microprocessor requests data from the same location that has been written into the cache, the upper address bits
on the address bus will be the same as the bits which were
previously written into the cache tag RAM and the MATCH signal
will go high. This is called a cache hit. In this case, the cache data
is gated onto the data bus and the memory cycle is complete.
If the microprocessor requests data from an address with the
same 13 least significant bits as a word in the cache, but with
different upper address bits, a cache miss will result and the
current (more recent) data will be written into the cache. In this
manner, the cache is continuously updated with the most
recently used data.
Memory write cycles are treated differently from read cycles.
On write cycles, data is written directly into main memory and
into the cache. This is called the write-through method of cache
updating. Since all data is written immediately into main memory,
it always contains current information. Data is written into the
cache on full word writes or on byte (i.e. partial word) writes if a
match occurred. Writing bytes into the cache only if a cache
match occurs ensures that the full word in the cache is valid. For
example, this ensures valid data for a byte write followed by a
word read.
The design in Figure 2 uses unbuffered writes. In unbuffered
writes, all write cycles occur at main memory speeds. This slows
down the system for all write cycles at the expense of simple
memory controls; however, this may be acceptable since only
1S% of all memory cycles are write cycles in typical programs.
Buffered write is a slightly more complicated method which
improves performance. In buffered write cycles, the write data
and address are loaded into registers, and the main memory write
cycle proceeds in overlap with other processor operations. Since
the nextiew cycles will probably be read cycles and their data will
come from the cache, the result is that buffered write cycles are
as short as cache read cycles.
CACHE MEMORY DESIGN: PERFORMANCE
Even a simple cache memory can improve system performmance. For a simple, 16-bit cache system such as described
above, a hit rate (percentage of read cycles that are from the
cache) of 68% can be expected. If IDT7174 Cache Tag RAMs and
IDT7164 cache data RAMs are used, an access time at the chip
level of 3Sns results and a corresponding system cache read or
write cycle time of SOns is practical. Assuming a system cache
access time of SOns and a main memory system access time of
2S0ns, the average access time of an unbuffered cache would be
134ns and the average access time of a buffered cache would be
104ns. This corresponds to an improvement in access time of
1.9:1 and 2.4:1, respectively.
CACHE DESIGN DETAILS: CONTROL LOGIC
Figure 3 shows a block diagram of a control logic design and a
typical timing diagram for the cache memory of Figure 2. The
vertical lines in the timing diagram represent SOns timing intervals. The microprocessor is assumed to have a SOns clock and a
100ns memory cycle time. In the timing diagram and associated
logic, a Read/Write Timing signal is used to determinewhetherto
use the cache data or to start the main memory. This timing signal
is the memory read/write request signal from the CPU delayed by
37ns; the address-to-match time of the IDT7174. If main memory
is used, this timing signal is used to write the main memory data
into the cache RAMs on both the main memory read and write
cycles. Data is written into the cache on write cycles only if there
is a match or if it is a word write operation. The state of the
MATCH line is latched by the Read/write Timing signal so that it
remains stable during cache write operations.
Address
MATCH
ReadlWri!B Timing
Data RAM Output Enable
f--I -f=::= -
I---'
StarlM31nMomory
Main Memory Busy
-
:= =
OE·OalaRAM
Output Enable
RaadiVllrlle T l m l n g - - ' - - - + - - - + - , - ( J " '
Main Mammy 8 u s y - - - - - 1 - - - + - + - ! . J
StarlM31r'lMem
WA1T(touP)
"WSWrdatoTag
and Data RAMs
Figure 3: Cache Memory Control Timing and
Logic Block Diagrams
CACHE DESIGN DETAILS:
UNCACHED ADDRESSES
In the above cache design, we have assumed that all parts of
memory are cached; however, there are significant exceptions to
this assumption. Hardware I/O addresses should not be cached
because they do not respond in the same way as normal memory
locations. Bits in an I/O register can and must change at any time,
asynchronously, with respect to the rest of the system. A cache
copy of an earlier I/O state is clearly not a valid response to an I/O
read request under these conditions. Also, an I/O register
address may be used for different functions for read and write, so
that what is read will not be the same as what was written. For
example, write-only control bits will not appear when read, and
read-only bits will not be affected by write operations. For these
reasons, hardware I/O addresses must always force cache
misses. This can be accomplished by adding an I/O address
decoder to the memory address bus to force a cache miss. (This
decoder aleady exists in many systems to enable the I/O
subsystem.)
CACHE DESIGN DETAILS: DMA ADDRESSES
Direct Memory Access (DMA) allows I/O devices such as disk
controllers to have direct access to main memory by temporarily
stopping the CPU and taking control of the memory address and
data busses. If DMA devices are allowed to write into main
memory without updating the cache memory, cache data could
become invalidated because it would no longer be a copy of the
8-45
II
:
APPLICATION NOTE AN-07
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
contents of main memory. The simplest solution to this problem
is to have the cache monitor the memory bus and be updated if an
address match occurs in the same manner as CPU write-through
operations. Otherwise, the I/O DMA buffer areas of memory must
be forced to be uncached in the same manner as hardware I/O
addresses.
CACHE DESIGN DETAILS:
EXPANDING THE CACHE IN WIDTH
The cache as described above, can be expanded in both width
and depth. For a 32-bit system, two additional IDT7164 cache
data RAMs (for a total of 4 chips) will be required to store the
32-bit data words. A block diagram of a 32-bit cache system, with
a 32-bit address bus, is shown in Figure 4. Compared with Figure
2, the number of cache data RAMs has been expanded from two
to fourto handle the expansion of the data bus from 16 to 32 bits,
and the number of cache tag RAMs has been expanded from two
to three to handle the expansion of the address bus from 24 to 32
bits.
Data
doubled the effective aCcess time of the main memory but have
cut the miss rate by less than half, yielding a net decrease in
performance.
CACHE DESIGN DETAILS:
EXPANDING THE CACHE IN DEPTH
The cache memory can be expanded in depth by adding
copies of the cache tag and data chips and using upper bits of the
address bus for chip enable selection. An example of an
expanded cache is shown in Figure 5. The primary reason for
increasing the size of the cache memory is to decrease the miss
rate percentage. For example, increasing the cache size from
8Kx 16 to 16Kx 16 decreases the estimated miss rate from 32%
to 22%.
Tag Btts from Address BuS
Data IpI frpID Qata eus
AI4-A23, Logic 1
AO-At
Data
8cK~~: H-----~
T"RAM
2,
Addrs
I
WAIT
IDT7174
Addrs
32
8Kx32
""",
"'"
3-,rl--.pIE
1+-------/0
MATC
I
"""
4,
IDT7164
Figure 5: Depth Expanded Cache Memory System
Figure 4: 32-81t Cache Memory System
Note that the cache memory system uses the memory address
lines corresponding to the 32-bit words stored in the cache. If a
byte addressing memory address convention is used, the least
significant bit of the address lines going to the cache RAM chips
is A2, with A 1 and AO used to select the byte(s) within the word to
be read or written in the cache data RAMs.
There is a benefit to expanding the cache width by adding data
RAMs: the miss rate improves. The miss rate improves because of
the increase in width, as well as in the amount of data stored. The
miss rate for a 8K x 32-bit cache is estimated at 12.4%, as compared to 32% for a 8K x 16-bit cache. Doubling the cache width
by adding RAM chips doubles the amount of data stored. We
would expect an improvement in miss rate due to the increased
probability of finding the data in the cache.
There is an additional improvement in miss rate, however,
specifically due to the increase in width. This is because there is a
high probability that the next word the CPU wants is the next
word after the current one. If the cache width is doubled, there is
a 50% probability that the next word is already in the cache,
fetched from main memory along with the current word.
Studies have shown that the miss rate is cut almost in half for
each doubling of the cache data word width - called line size. in
cache theory - up to 16 bytes and larger (Smith 85). The disadvantage of very wide cache data word width is either a wide main
memory data bus or complex logic to transfer the word to the
cache in a high-speed serial burst. Simply doubling the number
of main memory cycles does not work well because you have
CACHE DESIGN DETAILS:
SET AS$OCIATIVE EXPANSION
A better way to expand the cache memory in depth is called set
associative expansion (shown in Figure 6), and its control logic
(shown in Figure 7). In this example, we have two independent
cache memories which results in a two-way set associative
cache. If a match is found in one of the memories, its data is gated
to the data bus. If no match is found, one of the two memories is
selected and updated. Selection of one of the two memories for
cache write update is done by using an additional8K x 1 memory
to hold a flag for each cache word, indicating which memory was
read last. This way, the least recently used cache word of the pair
is updated.
The cache system described above attacks the problem of
having two frequently used words mapped to the same cache
word. For example, if a program loop included an instruction at
20082 (hexadecimal) and called asubroutine at 80082, the cache
word 0082 would be alternately registered as a cache miss and
updated with memory data from each of these two addresses.
The above design solves this problem by having two independent
memories. One would cache the instruction at 20082 and the
other would cache 80082.
Two way set associative expansion, while more complex in
control logic, achieves a better miss rate. For example, the estimated miss rate for a 16K )( 16 set associative cache is 18% versus
22% for a simple 16K x 16 cache.
8-46
APPLICATION NOTE AN-07
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
DatalolfromQalaB"s
Tag BUslrom Address Bps
WrileEnable
to TagOata RAMs
Cache
Control
Logic
Read - - - - - -.....
Write
WrileWord
called fully associative because access to the data in each
memory cell is through its associated, stored address. This type
of memory is expensive to build because the address cell and
address comparator are generally several times larger, in terms of
chip area or part count, than the data cell. Also, the address
comparator required for each associative memory cell makes the
design of the cell different from that of standard RAM memory
cells. This makes a fully associative memory a custom design,
precluding the use of efficient standard RAM designs.
--------+j
--------+jL____..J
Wr~eEnable
toLRU RAM
Figure 6: 2-Way Set Associative Cache Memory System
Write Enable
Figure 8: Cache Memory Cell Block Diagram
FUNCTDN
MATCH
Yes
Writo
ACOON
CACHE THEORY: WHY IT WORKS
EnablacorraspondingdalaRAMforraad
Enable ooruisponding dala RAM for
wr~8
Write main memory data. into LRU RAM
Wrla data into LRU RAM
'Wrilii"Eii"1o
AUUppor RAMs
~o
All Lower RAMs
LowarWas
-il--++--++,-Do--I
Raadlast
MATCH
UpparRAM
MATCH
Lower RAM
Output Enabieto
Upper DalaRAMs
Output Enablato
lower Data RAMs
A~=====r=========~[)~~~~~
Wnl9
Timing to
All RAMs
Figure 7: 2-Way Set Associative Cache Control LogiC
Block Diagram
CACHE THEORY: HOW IT WORKS
A cache memory cell holds a copy of one word of data corresponding to a particular address in main memory. It will respond
with this word if the address on the main memory address bus
matches the address of the word stored. A cache memory cell
therefore has three components. These components are an
address memory cell, an address comparator, and a data memory
cell, as shown in Figure 8. The data and address memory cells
record the cached data and its corresponding address in main
memory. The address comparator checks the address cell cOntents against the address on the memory address bus. If they
match, the contents of the data cell are placed on the data bus.
An ideal cache memory would have a large number of cache
memory cells with each of them holding a copy of the most
frequently used main memory data. This type of cache memory is
Cache memories work because computer programs spend
most of their memory cycles accessing a very small part of the
memory. This is because most of the time the computer is executing instructions in program loops and using local variables for
calculation. Because of this observation, a 64K byte cache can
have a 90+% hit rate on programs that are megabytes in size.
HOW THE DIRECT MAPPED CACHE WORKS
The direct mapped cache memory is an alternative to the
associative cache memory which uses a single address comparator for the cache memory system and standard RAM cells for the
address and data cells. The direct mapped cache is based on an
idea borrowed from software called hash coding which is a
method for simulating an associative memory. In a hash coding
approach, the memory address space is divided into a number of
sets of words with the goal of each set having no more than one
word of most-frequently-used data. In our case, there are 8K sets
of 2048 words each.
Each set is assigned an index number derived from the main
memory address by a calculation which is called the hashing
algorithm. This algorithm is chosen to maximize the probability
that each set has no morethan one word of most-frequently-used
data. In the direct mapped cache, the hashing algorithm uses the
least significant bits of the memory address as the set number.
This uses the concept of locality, which assumes that the most
often used instructions and data are clustered in memory. If
locality holds, the least significant bits of the address should be
able to divide this cluster into individual words and assign each
one to a separate set.
A memory map of a direct mapped cache of Figure 2 is shown
in Figure 9 as an example of how the main memory words are
related to the cache words. The 16M Word main memory is
divided into 8K word pages, a total of 2048 pages. Each word
within each 8K page is mapped to its corresponding word in the
8K words of the cache; i.e., word 0 of the cache corresponds to
word 0 in each of the 2048 pages (8K sets at 2048 words/set).
8-47
8
APPLICATION NOTE AN-07
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
Each word in the cache stores one word out of its set of 2048
corresponding to one of the 2048 possible pages. Both the data
word and the page number (i.e. upper address bits), are stored.
Since only one word in each set (one of 2048 words in our
case) is assumed to be one of the most-frequently-used words,
each set has a single cache memory cell associated with it. This
cache cell consists of an address cell and a data cell, but no
comparator. One comparator is used for the cache memory system since only one set can be selected for a given memory cycle
and only one comparison need be made. In a memory cycle, one
set is selected, and the single cache address cell for that set is
read and compared against the memory address, and the data
from the cache data cell is placed on the bus if there is a match.
The advantage ofthis scheme is that a single comparator is used,
allowing standard RAM memories to be used to store the cache
address and data for each set.
MAIN
100% cache miss or 100% cache hit for the unbuffered and
buffered cases, respectively.
CACHE SYSTEM PERFORMANCE: MISS RATE
One of the key parameters in a cache memory system is the
miss rate. Miss rate figures are estimates derived from statistical
studies of cache memory systems. The miss rate is an estimate
because it varies, often significantly, with the program being run.
Miss rate estimates for various cache memory configurations are
given in Table 1. Miss rates for one example of two-way set
associative expansion are also shown in this table.
Size:
WordsITag RAM
16
32
64
Notes
128
2K
0.57
0.23
0.10
0.04
4K
0.40
0.18
0.07
<0.04
8K
0.32
0.12
0.05
<0.04
16K
0.22
0.09
<0.04
<0.04
16K (8K +8K)
0.18
0.07
<0.04
<0.04
MEMORY
High
Miss Rate for Cache Data Word Width - Bits
2-way Set Assoc
Table 1.
DIRECT MAPPED
CACHE
ADDRESS TAG
RAM PAGE
DATA
RAM PAGE
The miss rate estimates given in Table 1 are derived from
simulation stUdies. (See references.) These studies covered
cache sizes of up to 32K bytes and cache data word widths
(called line sizes in cache terminology) from 4 bytes through 64
bytes. In the case of 16-bit word width caches, the figures given
are extrapolations from the 32-bit data. Also, the figures for
cache sizes above 32K bytes (i.e., 16K x 32, etc.) are extrapolations
from 32K byte data.
CACHE SYSTEM PERFORMANCE FOR
READ CYCLES
PAGE 1
CACHE DEPTH
'" PAGE SIZE
DATA STORED AT SAME PAGE
OFFSET IN CACHE AS IN MAIN
MEMORY
PAGE 0
Low
Cache memory system performance is determined by the
access time of the main memory, the access time of the cache,
the miss rate (the percentage of memory cycles that are not
serviced by the cache) and the write time. The effective access
time of a cache memory system can be expressed as a fraction of
the main memory access time. This dimensionless number, Ps, is
a measure of cache performance. If we consider read cycles only,
the access time of a cache memory system is:
Ts = {1 - M)Tc + MTm = (1 - M)Tc + MTm
Figure 9: Cache System Memory Map
The cache cell for each set should hold the data that was most
frequently used. However, since we do not know which data was
the most frequently used until after the program is run, we
approximate it by storing the most recently used data and replacing the least recently used (oldest) data. In the direct mapped
cache, this is done by replacing the cache cell contents with the
newer main memory data in the case of a cache miss.
CACHE PERFORMANCE
A cache memory improves a system by making data available
from a small, high-speed memory sooner than would otherwise
be possible from a larger, slower main memory. The performance
of a cache memory system depends upon the speed of the cache
memory relative to the speed of the main memory and on the hit
rate or percentage of memory cycles that are serviced by the
cache.
The cache performance equations below express the idea that
the average speed of the cache memory is the weighted average
of the cycle times for cache hits plus the main memory time for
cache misses, with memory writes dealt with as a special case of
Ps
=TslTm = (1
- M) (TclTm) + M
= (1
- M)Pc + M
Where:
Ts = Cache average system cycle time, averaged over read
and write
M = Miss rate of cache
Tc = Cache cycle time, read or write (assumed to be
equal)
Tm = Main memory cycle time, read or write (assumed to
be equal)
Pc = Cache memory access time as a fraction of main
memory cycle time
Ps = Cache system access time as a fraction of main
memory access time
If the miss rate of a cache memory is 100%, Pc = 1.00. If the
cache memory is infinitely fast corresponding to a cache access
time of zero, Pc will be equal to the miss rate, M. For real cache
memories, the access time of the cache is finite. This means that
the cache system access time will approach the cache access
time as the miss rate approaches zero. This is shown in
Figure 10.
8-48
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
CACHE SYSTEM PERFORMANCE IN TERMS OF
AVERAGE MEMORY ACCESS TIME
1000
CUfVelorcachesystem
wHh PC"O.100
0010
APPLICATION NOTE AN-07
Although cache memory systems can be evaluated in terms of
the dimensionless performance parameter, Ps, you often need to
calculate the actual access time for a specific system. This is
expressed by:
- .... ---------------------PC .. 0.010 line
Ts = R«1 - M) Tcr + MTmr) + WTw
Curve for ideal cache system
Where:
with Pc" Q
(zero access lime cache)
0.001
Ts = Cache average system cycle time, averaged over
read and write
R = Percentage of memory cycles which are read cycles
= 85% typical
W = Percentage of memory cycles which are write cycles
= 15% typical
M = Miss rate of cache = 10+% typical
Tcr = Cache read cycle time
Tmr = Main memory read cycle time
Tw = Write cycle time: main memory for unbuffered write,
cache for buffered
L-----+------t-----"'I
1.00
0.100
0010
Figure 10: Cache Access Time vs Miss Rate lor Read Cycles
CACHE SYSTEM PERFORMANCE FOR
READ AND WRITE CYCLES
Memory write cycles affect the average access time of the
cache system. In a write-through design, unbuffered write cycles
are equivalent to cache misses, while buffered write cycles are
equivalent to cache hits. Unbuffered write cycles take a main
memory cycle to write data for every write. If the main memory
write cycle time is the same as the read cycle time, this is'equivalent to a cache miss. In buffered write, data is written into the
cache and into a register for later off-line write into the memory.
Thus, the write cycle in the buffered write case is equivalent to a
cache cycle. Each write cycle in the buffered case is, therefore,
equivalent to a cache hit. The performance equations for this
case are:
For typical values:
Ts = 0.85(O.9Tcr + 0.1%mr) + 0.15Tw
= 0.765Tcr + 0.085Tmr + 0.15Tw
For unbuffered write and Tcr = 50ns, Tmr = Tw = 250ns:
Ts = 0.765(50) + 0.085(250) + 0.15(250) = 97.0ns
For buffered write and Tcr = Tw = 50ns, Tmr = 250ns:
= 0.765(50) + 0.085(250) + 0.15(50) = 67.0ns
Ts
Ps = R«1 - M)Pc + M) + W(Tw/Tm)
CACHE SYSTEM PERFORMANCE IN
TERMS OF CPU WAIT STATES
For unbuffered writes:
Ps = R«1 - M)Pc + M) + W
For buffered writes:
Ps = R«1 - M)Pc + M) + WPc
Where:
R = Fraction of total memory cycles that are read cycles
W = Fraction of total memory cycles that are write cycles
Tw = Write time = Tm for unbuffered, Tc for buffered writes
In many computer and microprocessor systems, the purpose
of the cache memory system is to eliminate CPU wait states,
clock periods where the processor is stopped waiting for the
memory. The cache performance calculations for this condition
are more properly expressed in terms of processor wait states as
follows:
Ncw = R«1 - M) Ncr + (1 - H)Nmr) + WNw
= RMNmr + WNw
The effect of unbuffered write cycles is to limit the maximum
performance of the cache system. For the average case where
write cycles are approximately 15% of the total number of
memory cycles, this is approximately equivalent to a cache
memory performance of 0.15, as shown in Figure 11.
Ncw = CPU average number of wait states, averaged over
read and write
R = Percentage of memory cycles which are read cycles
= 85% typical
W = Percentage of memory cycles which are write cycles
= 15% typical
M = Miss rate of cache = 10+% typical
Ncr = Cache read cycle time wait states (typically 0)
Nmr = Main memory read cycle wait states
Nw = Write cycle wait states: main memory wait states for
unbuffered write, cache wait states for buffered
1.000
CK!!.t.
0.100
~
~
~
0.010
For unbuffered write and Ncr =0 wait states, Nmr =3 wait states:
Curve lor ideal cache syslem
wKh Pe ..
°
Ncw
(zero access lime cache)
0001
L-----+------t-----"'I
1.00
0.100
If: Ncr = 0 (no wait states for cache)
Where:
0010
0001
=0.085(3)
1m1 .15(3)
=0.535 wait states
For buffered write and Ncr = Nw = 0 wait states, Nmr = 3 wait
states:
M1U...IIIlL.M.
Ncw = 0.085(3) + .15(0) = 0.255 wait states
Figure 11: Cache Access Time vs Miss Rate
tor Buffered and Unbuffered Write Cycles
8-49
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
APPLICATION NOTE AN-07
CACHE SYSTEM PERFORMANCE IN
TERMS OF CPU THROUGHPUT
Throughput Relative to Uncached System
Miss Rate
The reason for adding a cache to a CPU is to improve throughput by eliminating wait states. CPU throughput improvement, as
a result of adding a cache, can be expressed as the ratio of the
speeds before and after adding the cache. For our purposes,
CPU throughput improvement can be equated to memory
throughput improvement. CPU throughput for this case can be
defined as the CPU clock frequency divided by the number of
clock states per memory cycle. The speed improvement provided
by the cache can therefore be expressed as the ratio of the
throughput with the reduced number of wait states provided by
the cache to the throughput with full wait states:
Fc = fclk/(No + Ncw)
fclk/(No + Nm)
= (No + Nm)/(No + Ncw)
Where:
fclk
N
Ncw
Nm
No
= Frequency of processor clock
= Number of clock cycles per memory cycle
= Number of wait states for cache system (average)
= Number of wait states for main memory
= Number of processor states per memory cycle with
no wait states
Fc = Processor throughput relative to throughput without
cache
Fc =
(4 + 2)/(4 + 0.535) = 6/4.535 =
1.32 = 32% throughput increase
This is equivalent to increasing the CPU clock speed from
12.5MHz to 16.5MHz.
CACHE MEMORY PERFORMANCE:
HOW MUCH DO YOU NEED?
A simple, direct mapped j::ache memory system, as described
above, is often the most cost effective design. In many cases, the
effort to decrease the miss rate beyond that of a simple design
may not be worth the increase in system performance.
For example, if Pc is greater than 0.20 corresponding to a
cache access time greater than 20% of the main memory access
time, it may not be cost effective to improve the hit rate above
90%. This is because there is a knee in the curve of performance
improvement versus miss rate at the point where Pc = miss rate,
as shown in Figure 10. In some cases, even the added expense of
buffered write may not be justified. To examine the relationship
between CPU throughput and miss rate, CPU thorughput
improvement versus miss rate for various microprocessors is
shown in Table 2.
68010
Buffered
RISC
Buffered
68020
Buffered
1.00
1.00
1.00
1.00
1.00
0.80
1.06
1.12
1.19
1.27
0.60
1.13
1.20
1.32
1.49
0.40
1.20
1.28
1.49
1.79
0.20
1.29
1.38
1.71
2.24
0.10
1.34
1.44
1.84
2.56
0.05
1.37
1.47
1.92
2.76
0.00
1.40
1.50
2.00
3.00
Table 2.
The data shown is for three CPU/cache systems. The 68010
microprocessor system has a 12.5MHz clock and a cache with
unbuffered write. The 68020 system has a 16MHz clock and a
buffered write cache. The RISC CPU assumes a 10MHz RISC
computer with a 10MHz clock and a buffered write cache, and
assumes one clock per memory cycle with wait states equal to an
integral number of clock cycles.
Using the data in Table 2, we can make an interesting comparison between chip count and performance gained over an
uncached system. Table 3 gives this comparison, showing the
chip counts, miss ratios, and performance improvement gain for
simple, depth expanded, and two-way set associative expanded
caches. The chip counts given are for the cache tag and data
RAM chips required, but do not include chip counts for the
control logic. One RAM chip is added forthe two-way set associative case for the least-recently-used cache flag RAM.
Tag RAM
Size
A 68010 microprocessor requires four clock states per memorycycle, i.e. No =4. Assuming a 12.5MHzclock and 250ns main
memory access time, Nm = 2 wait states. If we use the unbuffered write case from the clock state analysis above, Ncw = 0.535.
The throughput improvement provided by the cache is therefore:
68010
Unbuffered
66010 Unbuffered
RiSe Buffered
68020 Buffered
Chips
Miss
Pert
Chips
Miss
Pert
Chips
Miss
Pert
8K
4
0.32
1.24
7
0.12
1.81
7
0.12
2.49
16K
8
0.22
1.28
14
0.09
1.86
14
0.09
2.60
8K+8K SA
9
0.17
1.31
15
0.07
1.89
15
0.07
2.68
Table 3.
Table 3 shows that the throughput improvement created by
expanding the cache above a minimum chip count design is
small. Thistable can be interpreted in two ways. In small systems
where the goal is to achieve high-performance at minimum chip
count, the table indicates that a mimum chip count cache is best
since it buys the most performance improvement per chip; doubling the cache chip count purchased less than 10% further
increase in performance in all cases. In larger systems where the
goal is to achieve maximum performance at moderate chip
count, the table indicates that a further increase in performance
of 5-8% can be obtained by adding fewer than ten chips.
CACHE DESIGNS:
DIFFERENT WAYS TO MAKE ONE
The cache memory described above is adirect mapped cache.
It is a simple, commonly used design with respectable perfor-
mance. Further investigation into the technology of cache
memories will reveal a wealth of other approaches to cache
design. Much of the variety comes from attempts to maximizethe
performance of relatively small cache memories typical of earlier
technology. Fortunately, there exists some data to help sort out
the relative value of the various approaches. This data is in the
form of studies on cache memory performance as a function of
cache size, organization, word width, etc., such as the excellent
work done by Prof. Alan Jay Smith of the University of California
8-50
APPLICATION NOTE AN-07
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
at Berkeley (see references). These studies provide background
and insight on how to achieve the highest performance out of
cache memory systems, as well as documentation of a wide
variety of cache schemes which do and do not work. The following comments are intended to provide a simplified guide to. and
summary of. some of this data. The following comments are, in
large part, judgments and opinions derived from the data in
various reports and do not necessarily reflect the opinions of the
original authors of the data.
WHAT WE HAVE LEARNED ABOUT
CACHE MEMORY DESIGN
A simple, direct mapped cache as discussed above will give
good performance if it is large enough. The ultimate measure of
cache memory performance is its effect on system cycle time,
which is a function of cache cycle time relative to main memory
cycle time and the hit rate olthe cache. Given a cache cycle time,
miss rate becomes the measure of cache performance. I mproving cache perfomrance, therefore, means improving the hit rate.
However, a simple design with a moderate miss rate may be
sufficient for many applications, giving most of the performance
improvement that could be achieved by a more sophisticated
design.
Much of the work that has been done on cache architecture
and design was aimed at maximizing the performance of relatively small caches, consistent with the capabilities of earlier
technologies. With today's technology, in the form of chips such
as the IDT7174, we can easily make large cache memories at low
chip counts that are at the upper limit of the earliertechnologies.
As a result, much of the sophistication required in smaller cache
designs, in order to achievean acceptable hit rate, is not required
in today's large cache designs.
CACHE ARCHITECTURE: DIRECT MAPPED
vs SET ASSOCIATIVE
A pure cache memory should be an associative memory, where
the cache contains all of the most recently used data words. The
direct mapped and set associative designs are approximations to
this which sometimes exclude recently used words when there is
more than one frequently used word per set. Fortunately, the
difference between associative, set associative and direct mapped
can be quantified. The ratios of miss rates for set associative and
fully associative, relative to the direct n,·.1pped case, are shown in
Table 3A. For example, if the miss rate for a direct mapped design
is estimated at 0.20, the miss rate for a two-way set associative
design of the same size would be (0.78)(0.20) = 0.156.
What this chart tells us is that two-way set associative caches
have a significant performance improvement over simple direct
mapped caches, but there is little additional improvement
beyond four-way set associative designs. As was noted earlier,
the set associative method can often be included in depth
expanded cache designs where the two (or more) sets of cache
hardware required forthe expansion can be arranged to work in a
set associative manner.
Cache Type
Ratio of Miss Rate to
Direct Mapped
Direct Mapped
1.00
2-Way Set Assoc
0.78
4-Way Set Assoc
0.70
a-Way Set Assoc
0.67
Fully Associative
0.66
Table 3a.
CACHE SIZE
Cache sizes on commercial systems have tended to range
from 16K to 64K bytes. Caches smaller than 16K can have significantly higher miss rates, while caches larger than 64K may not
significantly improve the miss rate. This is shown above in Table
1. Much work has been done on the relationship between cache
size and miss rate; however, most of this work is concerned with
small caches, 32K bytes and under. The IDT7164/1DT7174 combination allows 16K byte cache memory design for 16-bit systems and a 32K-byte design for 32-bit systems using a minimum
number of chips, and can be easily expanded to 64K and larger if
desired.
WRITE THROUGH vs COPY BACK
There are two general approaches to handling the memory
write problem: write through and copy back. I n the write through
approach, memory data is written into main memory as it is
received from the CPU. I n the copy back mode, memory data is
written into the cache and flagged with a "dirty write" bit which
indicates that the word has been written into the cache but not
into the main memory. The cache data is copied into main
memory as a separate operation at some later time, and the dirty
write bit is cleared. There appears to be little performance difference between the write through and copy back approaches.
Since the write through approach is simpler in concept and
easier to implement, it is the most often used method.
WRITE BUFFERING
A significant performance increase can be achieved with a
single level of write buffering. Complete write buffering requires
more than one level of buffering to cover the case of two write
cycles closer together than the main memory write cycle time. A
FIFO can be used to buffer more than one word of write data;
however. the FIFO need be no deeper than four words, since no
further performance results from making it deeper.
SPLITTING THE CACHE:
INSTRUCTION/DATA, SUPERVISOR/USER
Splitting the cache into two smaller caches, one for instructions and one for data, seems like it would improve the hit rate;
however, it doesn't. In theory, the CPU spends most of its instruction cycles in a small part of the program. By caching these
separately from the more random data memory, the hit rate on
the instruction portion should be improved. Alas, the studies
show that splitting the cache into two pieces typically does no
better - and in some cases does a lot worse - than leaving the
cache in one piece. This is, perhaps, because the miss rate for
data is degraded by more than the hit rate for instructions is
improved.
LINE SIZE: MAIN MEMORY WORD WIDTH
vs CACHE WORD WIDTH
We have considered cache sizes where the CPU word width,
memory word width and cache data word width are the same
size. Performance improvement can result if the main memory
and cache words are wider than the CPU word. lithe cache word
width (called the line size) is doubledthe miss rate is cut almost in
half. This is because the next word the CPU wants from memory
is often the word adjacent to the one it just used. Increasing the
8-51
CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN
line size by a factor of two will lower the miss rate by almost a
factor of two upto line sizes of 16 bytes and beyond. This is shown
in Table 4.
Cache Size
in Bytes
Miss Ratio Reduction for Increasing Une Size
Une Size (Size of Block From Main Mem to Cache)
4 bytes
S bytes
16 bytes
32 bytes
4K
1.00
0.586
0.364
0.262
8K
1.00
0.581
0.345
0.222
16K
1.00
0.569
0.330
0.203
32K
1.00
0.564
0.324
0.194
Table 4.
There are two approaches to increasing line size in order to
reduce miss rate: by increasing the memory data bus width, and
by fetching a block rather than a word of data from memory.
Increasing the data bus width (from 16 to 32 bits, for example)
may be practical in some systems where additional performance
is desired.
The other alternative is to transfer a block of bytes to the cache
instead of a single word. This becomes significant in systems
where there is a delay before data transfer from main memory,
but where several words can be transferred quickly after the
initial delay. An example of this concept is the page mode in
dynamic RAM designs. In such a system, there may be an initial
latency of 200ns to begin a memory read cycle but, once started,
the memory may be able to transfer words at 1DOns per word for
blocks of up to 256 words. In this case, a line (block) size of 2-4
words may be used to significantly reduce the miss rate with
moderate increase in the main memory cycle time.
APPLICATION NOTE AN-07
SUMMARY
Cache memories have been extensively used in large computer
systems to improve performance. Cache tag RAM chips allow
this technology to be adapted to the small-to-medium system
design at reasonable cost. Simple, direct mapped cache designs
with low chip counts can be used to achieve significant performance improvements. High-performance and low miss rates
are possible with simple designs due to the high speed and
relatively large cache sizes possible with high-speed CMOS
technology.
REFERENCES
[Smith82] Alan Jay Smith, "Cache Memories," Computing Surveys, 14, 3, September 1982, pp. 473-530.
[Smith84] Alan Jay Smith, "CPU Cache Memories," April 1986. To
appear in Handbook for Computer DeSigners, ed. Flynn and
Rossman.
[Smith85] Alan Jay Smith, "Line (Block) Size Selection in CPU
Cache Memories," June 1985. Available as UC Berkeley CS
Report UCBICSD 851239.
[Smith86] Alan Jay Smith, "The Memory Architecture and the
Cache and Memory Management Unitforthe Fairchild CLIPPER'·
Processor," April 1986. Available as UC Berkeley CS Report
UCBICSD 861289.
[Smith86b] Alan Jay Smith, "Bibliography and Readings on CPU
Cache Memories and Related Topics," 1986. from Computer
Science Division, EECS Department, University of California,
Berkeley, CA 94720.
Integrated Device Technology, Inc.
3236 Scott Blvd., Santa Clara, CA 95054-3090 • Telephone: (408) 727-6116 • TWX 9103382070
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in thiS application note in order to
improve design or performance and to supply the best possible product.
8-52
By John R. Mick
3-line-to-8-line decoder. The output of the decoder is then connected to the single chip select of the RAM. This results in the
access time of the memory being equal to the summation olthe 3
devices in series. Figure 1B shows the same devices only the
identity comparator and the 3-line-to-8-line decoder are each
connected to one of the chip selects on the RAM. This results in
the propagation delay of these devices occurring in parallel and
thus improving the overall performance of the system. The comparative speed advantage is 9ns commercial and 12.5ns military,
as shown in Figure 1.
Another method for chip select decoding is shown in Figure 2.
Here we see two I DT74FCT138s connected in a matrix arrangement. By using this technique, we are able to perform decoding
on the equivalent of 64 different rows of RAM. Normally on a
RAM with only one chip select this would require nine
IDT74FCT138s.ln this arrangement, only two IDT74FCT138s are
needed; thus, a savings of seven devices results, with an
improved propagation delay performance of one less device in
the series.
From these design examples, the design engineer can see the
advantages of two chip selects and an output enable.
The IDT7198 is a high-performance 64K CMOS static RAM.
Compared to the standard 16K x 4 static RAM, it features two
active low chip selects and an active low output enable. These
additional features provide the designer with a capability that he
can use to improve system speed.
The output enable can be used in systems to gate the RAM
data onto the bus at the required time. It is independent of the
memory access time and thus can be brought low (enabled) later
in the memory cycle. This means that other bus activity could be
present during the initial part of the access time of the RAM. The
benefit here, of course, is maximum bandwidth on the bus.
The advantages of two chip selects are probably not as
obvious as the use of an output enable control signal. The second
chip select can be used to advantage in high order address
decoding or memory block decoding and provides the opportunity for these events to occur in parallel. This parallelism improves
system speed at no increase in parts count. This is easily demonstrated in Figure 1. Here we see a memory with a single chip
select, shown in Figure 1A, and a memory with two chip selects,
shown in Figure 1B. Figure 1A shows the IDT74FCT521 8-bit
identity comparator connected in series to the IDT74FCT138
A17_23
A17_23
A 14-16
A14-16
A0- 13
IDT7188
A
D
A
AD-13
D
COM'L.
IDT74FCT521
IDT74FCT138
IDT7188
A-O
E-O
CS- Data
COM'L.
--"M.L
11ns
9ns
35ns
12.5ns
14ns
~
71.5n.
55ns
IDT74FCT521
IDT74FCT138
IDT7188
1SPEED SAVINGS
....M.!h..-
11n.
35ns
14ns
45n.
46n5
59n.
9n.
12.5ns
l
Figure 1B. Higher-Speed Memory Design Using Two CSs
Figure 1A. Standard Memory Design Using One CS
@
A-O
E-O
CS - Data
1986 Integrated Device Technology, Incorporated
Printed in the U.S.A
8-53
7186
TECH NOTE
USING TWO CHIP SELECTS ON THE IDT7198
I
1- 3
IDT74FCT138
I I I I I L
I
I
I
J
CS
CS
~
~CS
~es
IDT7198
IDT7198
I
I
• • • • • •
~CS
IDT7198
r--
W
-r
III r~
0
II.
it
I-
e
---
-
r-
-
~
I
CS
es
CS
~es
~es
IDT7198
IDT7198
IDT7198
•
•
•
•
•
•
eses
IDT7198
•
•
-es
•
_es
CS
IDT7198
• • • • • •
'- CS
IDT7198
Figure 2.
Integrated Device Technology, Inc.
3236 Scott Blvd., Santa Clara, CA 95054-3090 • Telephone: (408) 727-6116 • TWX 9103382070
Integrated Device Technology. Inc. reserves the right to make changes to the specifications in this tech note in order to
improve design or performance and to supply the best possible product.
8-54
DESIGN ENTRY
CMOS logic with
bipolar-enhanced 1/0
rivals Fast TTL gates
Octal CMOS devices incorporating bipolar transistors
race neck and neck with the best low-power Schottky packages
on less than a tenth the operating power.
I4
thOUgh the evolving Schottky technology
has progressed mightily in increasing
the operating frequency limits of TTL
devices, in the last reckoning the designer has
been left to resolve the ever present problem of
excess power. On the other hand, CMOS has advanced from its humble beginnings as a lowpower, low-speed technology to the point where
it can replace its TTL counterparts in many applications. The 54HCT (high-speed CMOS TTLcompatible) family, for example, has speed and
output drive-current characteristics similar to
parts in the LS category of TTL devices. Unfortunately, the designer must yet to some degree
grapple with the various power-vs-performance considerations.
A new CMOS collection of octal buffers,
latches, decoders, registers, and transceivers
for supporting high-speed memories and data
buses provides both the speed and output drive
of 74F (Fast) parts at only a fraction of the
operating power (Fig. 1). The IDT 54FCT (Fast
CMOS TTL-compatible) family sports typical
gate delays of 5 to 10 ns and delivers output currents of up to 48 rnA over the full military range
Marcelo Martinez, Integrated Devices Technology
Marcelo Martinez, an expert in the custom design of
CMOS LSI m.icrocom.JYUters and controUers, is currently design engineering manager at Integrated Devices
Technology in Santa Clara, Calif. He has a BS in physics and an MSEE from Berkeley.
Reprinted from ELECTRONIC DESIGN - February 7. 1985
of voltage and temperature. With an average
power consumption of 20 mW (or a few microwatts in the standby mode), it is also a viable alternative to Schottky and advanced Schottky
devices.
The family's enhanced speed and output
drive at low operating power are attributed to a
proprietary 2-llm, dual-metal-gate process
called CEMOS (see "Seeing Mostly Higher
Speeds," p. 119), which is used to fabricate both
input and output stages having the unusual
combination of CMOS and bipolar devices.
These components create stages with low capacitance that minimize input currents and output
voltage swings, thereby creating low-power,
high-speed gates (Fig. 2a). Multiple contacts to
all drains and sources of the p-channel and nchannel devices involved are used to minimize
the gates' internal resistance, thereby allowing
them to drive larger loads than typical CMOS
gates can. Particular attention is paid to keeping the gates' source resistance as low as possible, which has a first-order influence on drive
because of the current-to-voltage feedback arrangement used in this family.
Of prime importance is the push-pull output
stage, which employs two n-channel gates in
parallel with an npn transistor and a smallsignal p-channel device (Fig. 2b). The npn transistor clamps the output voltage to 4.3 V when
loaded by a TTL device (assuming a 5-V supply).
This configuration provides a high noise mar-
Copyright 1985 Hayden Publishing Co., Inc.
8-55
DESIGN ENTRY
High-performance CMOS logic
gin for high-to-low signal transitions, even
when the output is loaded heavily. Furthermore, the switching times are reduced because
of the limited output swing.
case parameters than those commonly quoted
for typical-value operation. The actual values of
course, are determined by the circuit.)
When TTL devices drive a CMOS part, the
latter's input buffer stage will draw power
when the input voltage is other than equal to
the supply voltage. When CMOS devices drive
FCT parts, however, the static power dissipation is much lower. Specifically, in the case of a
374 driver, the maximum current drain is only
0.16 rnA, as compared to 85 rnA when the
374 drives the Fast part and 140 rnA for the
AS part.
Channeling the power
The most significant benefit of the series,
however, is its power-conserving characteristics. The channel length of the 54FCT CMOS
devices is generally less than their 54HCT predecessors and so are the resulting internal gate
capacitances. The dynamic power consumed is
therefore proportionally less. In the FCT family's push-pull output driver stage, the relatively
large cross-over current required to switch a
given device is greatly minimized by deskewing
(offsetting) the predriver circuit. This unbalancing allows the device to switch at a fraction
of the usual dynamic supply current. Even at
10 MHz, the dynamic power drawn by the
IDTFCT 374 register buffer (which is the first
device in the family) is only 6 % of that required
by a Fast 374 and only 3% of the AS374 (Fig. 3).
(Note that worst-case parameters are examined. It is much more useful to compare worst-
Zilching the zaps
Each input has a 500-Q resistor driving the
junction of a grounded-base transistor and a
grounded-gate n-channel device to protect all
FCT devices against electrostatic discharges
that reach 1000 V or more. The n channel is at a
common point with the emitter of the npn transistor, and so the junction capacitances and
input-switching times are minimized.
Latchup, also a concern in CMOS devices, is
virtually eliminated. The FCT family will not
50
o
' - - High-performance CMOS (0.8 mW)
40
f-
Advanced low-power Schottky
Advanced Schottky
20f-
(
\
FaSl\
o
o
o
10-()~
Fast CMOS, TTL-compatible (800 IJ-W)
100
300
500
700
Power per equivalent register (mW)
1. The FCT lamily 01 bipolar-enhanced CMOS parts delivers the speed and
drive current 01 Fast, as well as 01 advanced and advanced low-power
Schottky TTL devices, but consumes less than a hundredth the static operating power. They are at least lour times laster than earlier high-speed
CMOS parts.
8-56
Seeing mostly higher speeds
The CEMOS method uses a 2-IHn, silicon-gate process to allow CMOS parts to work at almost twice
their former speeds, CEMOS IIA, the version used
for the FCT family, employs a two-layer metallization technique (see the figure), Smaller effective
channel lengths make it about 40% faster than the
previously used CEMOS I (2,5 !lm) process,
That process yields, for example, 54HCT138 decoders with propagation delays of 8 ns, 10-mA output drive, and 7-mW power dissipation over the full
military range of temperature and voltage supply
extremes, They operate more than 60% faster than
currently available HCT decoders do and are comparable in speed to 54ALS bipolar devices, CB;MOS
IIB, a 1.5-!lm version, is further expected to offer a
20% increase in speed for both the FCTand a class of
9- and lO-bit-wide devices compatible with the AM
29800 series, which are slated for release later this
year.
, The principal technologies that allow these finer
lines, fewer defects, and higher density are waferstepping printing and the dry etching of thick films.
The most usual approach to fabricating an IC is to
cover a wafer with a photoresist and expose it to
light passing through a mask that is about the same
size as the wafer itself. This 1:1 technique presents
problems in aligning the mask when the tolerances
must be tight and when defects must be reduced to
less than 5/in. 2 .
These masking problems have been largely alleviated by using wafer stepping, in which an image
about the size of a few individual dice is exposed to
only a fradion of the total area of a wafer. The image is plaeed on aglass plate having a 1 X reticle that
eontains 2 to 15 dice in a patterned chrome field.
Then the plate is projected onto the wafer and is
sequentially stepped until the whole wafer is exposed. Recause only a small area of the wafer is exposed at any given time, more precise masks and opties can be used and mask defeets can be greatly
reduced.
In order to scale the process horizontally, a dry
etch method is employed to maintain tighter control
of the nitride, oxide, polysilicon, and aluminum
films used. CEMOS II employs a plasma etcher,
which uses an electric field to control an ion gas that
etches only in the vertical plane. Thus much tighter
geometries are permitted. This technique overcomes
the main objections to the use of wet acids such
as hydrofluoric, which etch laterally as well as vertically, thereby limiting the ability to produce finer
lines.
In practice, CEMOS IIA deposits oxide at low temperature atop an etched pattern on the first metal
layer. This layer is used extensively to reduce the
resistance and inductance effects on internal supply
lines, thus minimizing noise and internal delays. Interconnection vias are then plasma-etched into the
oxide until the metal is exposed. A second layer of
metal is then deposited. This top metal layer is
etched with the pattern characteristic of the desired
circuit.
Second metal layer
Polysilicon
8-57
DESIGN ENTRY
High-performance CMOS logic
latch up, even for forced trigger currents as
high as 300 rnA (for worst-case conditions of
125°C and Vee = 7 V). A second type of latch-up
in CMOS devices, normally associated with excessive substrate current during fast switching,
is also eliminated by judicious selection of
supply voltages. Most CMOS devices suffering
from this malady run at supply voltages of 9 to
12 V; the operating voltages of the FCT family,
being compatible with TTL, run at 7 V.
Noise problems in a high-speed system containing FCT devices will be no worse than in a
system built with Fast parts and will often
Vee
(a)
Vee
yield an improvement. The designer need only
adhere to standard grounding practices. To be
more specific, he should use suitable supply and
ground planes to reduce inductive supply noise
and crosstalk in signal lines. Also, bypass
capacitors should be deployed throughout, one
per buffer and one for every pair of other logictype devices.
The value of the bypass capacitor is equal to
It/V, where I is the output current of the device,
t is the switching time, and V is the variation of
supply voltage due to noise. Assume the dynamic load seen by an octal buffer is 50 fl and the
high-to-Iow output voltage transition is 4 V.
Thus the current demand is 80 rnA. For eight
such devices in the part, each switched every
3 ns., the maximum current demand will be
640 rnA. The required bypass value will thus be
0.02 /-LF, assuming that there is a 0.1-V drop in
Vee with noise.
As an added protection against ground noise,
the FCT family has 300 mV of hysteresis in the
clock and output enable lines. This amount of
swing also guards against slow-rising clock
pulses in heavily loaded enable lines. When the
input voltageis near ground, the device increases VIH by 0.3 V to raise the trip level. Once
the stage switches, the trip level is lowered by 0.3
V. Thus, a slowly changing signal with noise on
it will not falsely trigger the device.
Taking the long route
30
n
~~----------~
(b)
2. A low-impedance RC circuit protects the standard
input circuit of an FCT chip from electrostatic discharges exceeding 1000 V (a). An n-channel gate
npn transistor stage keeps input capacitance low,
and the push-pull output stage is configured to furnish a high noise margin (b). The npn transistor
clamps output swing someWhat, to reduce the
stage's switching times.
Unlike the case with most other logic families, the designer need not perform criticalpath or power-management analysis when
using FCT devices. Furthermore, the power
consumed is virtually a function of only frequency, duty cycle, loading, and the voltage levels ofthe systems. If incoming signals are at low
frequency and at logic levels that switch between the supply-rail values, the FCT devices
will draw a maximum static current approximatelyequal to Icc (that is, 160 /-LA). Whenoperated at higher frequencies or at worst-case TTL
output levels (or both), the device will draw
more power, but the drain will still be well
below the power drawn by the equivalent TTL
device.
Still, several things must be borne in mind in
interfacing these devices, especially with TTL
parts, if the designer is to maximize the power
8-58
DESIGN ENTRY
High-performance CMOS logic
savings and minimize latch-up and noise.
Basically, direct interfacing of FCT parts
with Fast TTL devices yields immediate advantages in noise immunity. The FCT's input stage
exhibits a worst-case level ofV n . = 0.8 V and VIH
= 2.0 V over the entire specified ran~e of temperature and voltage, the same as for TTL parts
(Fig. 4). But the FCT devices draw an input current of less than 1 !lA. When they are united
with TTL devices, therefore, the latter's worstcase VOL and VOl! levels will be close to their unloaded values of VOl! = 3 V, VOL = 0.2 V. Consequently, the noise margin will be VOIITTL
- V1Ht'CT = 1 V and VOI'fTI. - Vn'.- C1: = 0.6 V on
the hIgh and low levels, respectIvely. Comparing these values with the Fast margins of
0.4 V and 0.3 V for TTL-TTL interfaces reveals
that the TTL-FCT interface provides superior
system noise margins.
When FCT parts are connected directly to
Fast devices, the output level will be limited to
about 4 V if lOll is less than 1.5 rnA. The corresponding fan-out is 75. A greater noise margin
(2 V) is thus maintained because the output
impedance of the FCT device is lower. For low
logic levels, the noise margin is at least 3 V.
CMOS parts can be united with conventional
FCT interfaces, too, but at a sacrifice in noise
margin, because the FCT's trip level is much
lower.
Of course, the best noise immunity is
achieved when a complete FCT logic system is
integrated, in which case the noise margins are
2.2 V and 0.6 V. Although the power drain of
FCTs is inherently well below that of TTL, the
designer may utilize several techniques to reduce it further. The total power drawn by an
FCT-TTL interface is given by:
p
=
VcclcccMOS + VCcICCTTL ND
Vcc2fCPD + Vo2fC L
+
where Icc relates to quiescent current values for
the respective CMOS and TTL input requirements, N is the number of TTL inputs above VIH
at any given time, D is the duty cycle, and f is the
operating frequency. The summed internal
capacitance of all stages of the device being
driven is CPD, Vo is the output voltage swing,
and CL is the capacitance of the output stage.
The obvious ways to reduce power dissipation
are thus to lower the frequency of operation, reduce the input duty cycle, or lower the number
of inputs that remain high at TTL levels. Lowlevel input signals, especially those that suffer
from transient ringing, should be limited to
Advanced Schottky
Power (mW)
600
Advanced low-power Schottky
Fast
400
-
Bipolar
-
Bipolar-enhanced CMOS
0.7 mW/MHz
FCT
20
10
30
40
50
Clock frequency {MHz}
3. When an FCT octal register is driven by TTL devices, the dynamic power
drain of each stage is less than 6% that of a Fast register and only 3%
that of AS parts, below 10 MHz. The power consumed by the FCT register
when driven by CMOS parts is less than 1% that of Fast and AS registers.
6-59
DESIGN ENTRY
High-performance CMOS logic
have CPD of 3(15) = 45 pF, and CL = 50(4) =
200 pF. Given that Vee = 5.5, and Va = 3.5, then
P = 47 mW. With Fast or AS devices replacing
the FCT parts, P is found to equal 482 m Wand
713 mW, respectively, given that Va = 3.
The FCT device's output can also be connected directly to CMOS or any other conventional TTL devices. When the output voltage is
below 1 V, the FCT presents an 8-11 impedance
to external buffers. The IOL = 60 rnA at 0.5 V;
therefore the TTL fan-out is relatively high. Between 2 and 4 V, and FCT's npn and n-channel combination provides an IOH of 30 rnA for a
VOH of 2.4 V, and the resulting output impedance is 80 11. For high-level inputs (Vec -0.2u),
the lOB = 100 !lA; the resulting high output
impedance is quite acceptable for interfacing to
CMOS devices. 0
0.5 V below Vss. The input protection afforded
by the FCT npn transistor will limit the voltage
internally, but additional current may flow
through the Vee terminal.
For high-level logic levels, there is no extra
current flow because the n-channel device
breaks down at about 15 V. Nevertheless, input
ringing should be limited if the noise margin is
to be maintained.
Other techniques include reducing rise and
fall times and limiting the number of de current
paths in a given circuit design. No matter what
power-conserving methods taken, the FCTTTL interface will consume no more than one
tenth the power of its FAST-TTL and AS-TTL
counterparts. Consider the case where a 374
shift register drives a 50-pF load on a bus running at 10 MHz. Assume that half of the registers switch at the worst-case VOH value of
2.4 V, which represents a heavy TTL load of
1 rnA. Also assume that the duty cycle is 50%.
Thus IccC,MYs = 160 !lA, IccTTL = 1 rnA, N = 4, D
= 112, and t = 10 7 • In addition, it is known that
CPD = 30 pF, all additional working registers
4.5
4.4
Fast-to-Fast
Fast-to-FCT
FCT-to-Fast
FCT-to-FCT
=::'::F:==1::===~=-=t=·=~~;;d
~
]1
.!1
~
s'"
g
2.4
~S
.5
u
.",
.3
0.8
0.5
0.2
4. FCT -to-FCT interfaces have the greatest immunity to noise, though both FCT -toFast and Fast-to-FCT setups yield acceptable results. Fast-to-Fast links, to date
viewed as having a good noise margin, fall far short of the rest.
8-60
ElE[JRonl[S In DESIGn
High-density modules
suit military applications
Joe Kraus, Marketing Manager/Subsystems, Integrated Device Technology, Inc., Santa Clara, CA
The ability to produce integrated
circuits meeting the high-reliability
specifications associated with military systems has taken a number of
years to develop. Special attention
has always been given to the
semiconductor process and circuit
design techniques to stimulate the
pursuit of the highest density and
speed with the lowest power possible
for monolithic devices.
This approach, however, is of a
one-dimensional nature-an increasing demand in military systems for
portability, miniaturization and battery operation is forcing the industry
to take a closer look at the wide use
of space-inefficient DIP packages.
One of the first approaches was to
use flat packs. However, because of
their highly flexible leads, many
difficulties were incurred in testing
and handling. Additionally, problems associated with manufacturing
and processing increased the cost of
flat packs beyond the budgets of all
but the most area-limited military
programs. Most recently, the apparent solution was the advent of
leadless chip carriers (LCCs).
LCCs come on the scene
Around 1978, LCCs began to
emerge as a viable packaging
technique, allowing substantially
higher board-level IC packing density and overall system weight
reduction (see Figure 1). The
thought was that not only would
LCCs replace the cumbersome-totest flat packs used in high-rel/highdensity military programs, but would
eventually find their way into
commercial applications in which
system size was of major concern.
This obviously did not come
about, since system usage of LCCs is
still small.
One of the main problems that has
kept this idea from culminating as
quickly as planned has been the lack
of a variety of suitable methods to
attach the LCCs to the PC
boards-particularly in military applications requiring system temperature extremes, causing the difference
in thermal coefficient of expansion
(TCE) between the LCC and the
polyimide PC board to dislodge the
LCC (see Figure 2).
New packaging techniques
The solution was to develop
packaging techniques that would
take advantage of high-density LCCs
while presenting a highly reliable'
component that could be mounted
using traditional techniques. Recent
advances in surface mounting techniques, and further understanding of
the dislodged LCC phenomenon has
given rise to a module approach. In a
module, LCCs are mounted, top and
bottom, to a cofired ceramic
substrate matching the TCEs. The
substrate has a dual-in-line pin out
and thus can be mounted into the PC
board using traditional soldering
techniques. The module, therefore,
allows packing density equivalent to,
or higher than, LCCs with none of
the disadvantages, -achieving the
perfect marriage of old and new
packaging methods.
However, since military applications demand the highest level of
reliability, this packaging technique
can be thought of as a viable solution
8-61
only after a thorough understanding
of the problems.
Thermal coemcient of expansion
problems
A better understanding of the
mismatching of TCEs can be
achieved by referring to Figure 3a.
In a case where the system is seeing a
large variation in temperature (temperature cycling), the LCC, constructed of cofired ceramic, will
expand less than will the flexible
polyimide PC board. This difference
in expansion produces stresses that
will be absorbed by the flexible
solder joint. Given enough temperature cycles, though, the solder joints
may fatigue to a point of electrical or
even physical discontinuity. Matching the coefficient of expansion of
the LCCs and the substrate or PC
board can alleviate this concern.
Integrated Device Technology's
modular approach uses a ceramic
substrate constructed of identical
ceramic material and cofired in
exactly the same fashion as the
LCCs. As the system heats up and
cools down, the LCCs and substrate
expand and contract exactly the same
amount (see Figure 4 for substrate
construction).
Although temperature cycling
problems can be lessened in this
manner, a bigger problem can exist.
Figures 3b and 3c represent differences in TCE that result from power
cycling. In a power-up mode, the
LCC will heat up at a much faster
rate than the substrate since it is the
LCC that is generating the heat.
Until the heat can be transferred
through the solder joints and into the
WEIGHT VS. LEAD COUNT
12
~.~",.
:9 10
~
CERDIP
:I:
!2 8
w
31:
w 6
Z--
CI
C
:..:
(.)
300 mil
4
C
It..
2
......-< : , - -
--""
0.300 center
sidebraze
0
8
12
16 20 24 28 3
36
PACKAGE LEAD COUNT
LCC
40
44
AREA VS. LEAD COUNT
:i
..• ..--'. 0.600" center
sidebraze
r:~'"
1.5
_1.4
.5 1.3
f 1.2
-1.1
1.0
a: 0.9
C 0.8
~ 0.7
C 0.6
:..: 0.5
~ 0.4
It.. 0.3
0.2
0.1
0
...-~~"~LCC
......--~
.
8
COFIRED CERAMIC SUBSTRATE
MANUFACTURING PROCES$
THERMAL COEFFICIENTS OF EXPANSION
C.O.E. I(
10-lj oC
Material
White ceramic chip carriers (94-96% alumina)
Black ceramic chip carriers (90% alumina)
Copper clad Invar Porcelain Enameled Metal
Substrates (PEMS)
Steel core PEMS
16 20 24 28 32 36 40 44 48
PACKAGE LEAD COUNT
12
Fig. 1
6.3
6.9
6.8
1) Green Sheet
(Green Taps)
Tooling
2)
3) Punching
13.3
Fig. 2
4)
VI.Hole
5) Cavity
THERMAL COEFFICIENT OF EXPANSION PROBLEM
(Length 01 arrow represents amount 01 stress)
Solder----,
LCC------,
-
6)
Screen Printing
7)
Lamination
8)
Sheplng
11) NIPlaiing
For better wetllng of brazing alloy.
(Before brazing)
Brazing
13) Finish Plallng
Flg.3a.
14) Snap Breaking
15) Edge Grinding
'-
!
W3~1\:1~I~:~~';':~~~~e:e.
Bonding of I,ad frames 10 metallized pads with
atmosphere.
All exposed Metal end melallization surfaces are '
electroless plated with desired melal for functional
purpose and environmental protection.
Separation of aSCh unit from the maeter array along
a predetermined scribe mark.
.
Dlaconnecllon of plellng lie-bar melallizatlon 'With
an abrasive 1001.
HEAT TRANSFER METHODS
120
Flg.3b.
~
-
80
6
20
10
a
POWER DOWN
Immersed
Liquid
Flg.3c.
Fig. 5.
8-62
'C
~!~e;r~~I~:;:~P:O,!~~:I~~~Olc(rn ~u::cm~l~
Fig....
BTU/Hr'FI"F'
POWER UP
~~~.a~f~~~~lr?r~~t:I~"a~e':':r'::.~~
edge 10
To groove surface for enap breaking.
Simuitanaous slnlerlng of ceramic and lu~en
12)
;
In
8) ScrIbing
10) Co-firing
TEMPERATURE CYCLING
A ..
Unslnlered flexible raw ceramic sheet
All necessary manufaclurlng lools such as punch·
Ing tools, screening paltems, brazing flxluree and
electrical tesl probes and flXlures.
Via holes, cavities end other Inside cutting In green
sheet ~ayer by layer).
Holes in ceramic layer filled wllh tungSlen 'ps$18
for elactrlcal connactlon.
Recessed etruclure, such asdlli attach cavity.
Conductor 'lines/planes various peds end mark·
Ings etc. are printed with tungaten paste on green
sheet surface (moly·manganese can also be',
printed aller slnl~lng). '
Each 'ayer of green sheet (WIth screen printed pat·
the design se·
terns and flllea vias) Is stacked
quence and bonded together.
Vapor
Phase
Rellow
ELEnROII[S II DESIIiI
substrate, there will be a mismatch
of temperature and thus a mismatch
of expansion. Likewise, in a powerdown mode, the LCC will cool faster
than the substrate and again pose a
mismatch situation.
Although there is no perfect
solution to this problem, IDT has
minimized its effect by using only
extremely low-power CMOS components, thus reducing the total
amount of heat generated by the
LCC and limiting the mismatching of
expansions.
Surface mounting techniques
No matter how much attention is,
given to the matching of TCEs, if the
LCC is not mounted with the proper
surface mounting technique, the
solder joint will still become a source
of problems. The proper surface
mounting technique is one that will
evenly heat substrate and LCC to the
ideal temperature to flow the
solder-with minimum overshoot.
The ideal process would be easy to
control, would remain clean, and
would produce the most reliable
FIg. e.., I'oor ao/der wlcldng and 'cold' ao/der joints ....ng foroIIcHIIr tllCllnique.
8-63
solder joint possible. Several techniques were evaluated by IDT to
determine the fastest, most efficient
and, above all, most reliable.
Forced air-Either the LCC or
substrate is screened with a tin/lead
solder paste, assembled, then put in
a hot air furnace to heat the module
to the proper temperature, melting
the solder. This technique of heat
transfer is the most inefficient of all
the methods (see Figure 5) and often
leads to inadequate heating of the
module, producing cold solder joints
and inadequate wicking. Figure 6a
shows a typical part using a forced
air method. Notice the lack of solder
on the gold contact of the LCC, and
the appearance of "cold" solder
joints, indicating improper heating.
Infrared-Similarly,
presilkscreened LCCs are assembled onto
the substrate and subjected to an IR
heat source. In addition to being an
inefficient method of heat transfer
(see Figure 5), IR produces a
"shadow" effect, i.e., LCCs shielded
from the heat source by either the
substrate or other LCCs see substantially lower heat than do the
non-shielded LCCs. This produces
temperature gradients in the module, risking the possibility of
overheating some portions of the
module and inadequately heating
other portions.
Liquid immersion-Although a
relatively effective method of heat
transfer, liquid immersion is a very
unclean process, leaving a substantial amount of residue on the module
after solder reflow. Although the
module can be cleaned, this procedure is often so harsh that it attacks
critical areas of the assembly.
Vapor-phase reflow solderVapor-phase reflow solder is the
method of choice. This is the most
efficient method of heat transfer (see
Figure 5) and produces the most
reliable solder connection.
A vapor-phase reflow solder
system (see Figure 7) consists of
vapor chambers with a heating
element at the bottom and a set of
cooling coils located roughly 'II and
211 of the way up the sides. A liquid
fluorinet (Fe70) is brought to its
boiling temperature (419F) to form a
vapor between the bottom of the
chamber and the primary cooling
coils. The primary cooling coils are
kept at 125 to 175F, thus condensing
the vapor to liquid to be reused.
However, when assemblies are
lowered into the vapor, the vapor
"blanket" is disturbed and very
costly FC-70 is lost to the ventilation
system. Th minimize this loss, a
second vapor "blanket" is formed
between the primary and secondary
coils consisting of trifluro ethane.
Since trifluro ethane has a boiling
point of 117F, it will not condense at
the primary coils, but forms a
secondary vapor that will condense
only at the secondary coils kept at
a well- controlled 6OF.
Since the primary vapor (FC-70) is
kept at 419F, when modules with
LCes mounted on them are lowered
in the vapor, the tinllead eutectic
(melting point of 361F) melts and
flows evenly. The principal of
vapor-phase heating relies on the
condensation of saturated vapor on
the module. This condensation is
accompanied by the release of the
latent heat. of vaporization which, in
turn, causes the epol assembly to
heat rapidly (10 to 30 sec) and
uniformly.
Since the vapor condenses on all
sides simultaneously, the shape of
the module is not important. No
temperature gradients are incurred,
eliminating cold solder joints from
too Iowa temperature, or dissolution
of noble metals from too high a
temperature. In fact, the 5SF
difference in temperature from the
FC-70, and melting point of the
tinllead eutectic is ideal for maximum adhesion of the LCC (see
Figure 6b). Studies indicate that in
1.5 million solder connections less
than 0.1% defects were found.
From a manufacturing process
view, vapor-phase reflow has additional advantages. Surprisingly, the
placement of the LCC is not critical.
The high surface tension of the
solder will physically move the LCC,
assuring perfect alignment of the
Lce pad connections to the
tin-plated tungsten traces on the
substrate. IDT has taken advantage
VAPOR PHASE REFLOW SOLDER SYSTEM
AUTOMATIC CYCLE CONTROL
r-___---"~ WATER
SCRUBBER
HEAT
EXCHANGER
Fig. 7.
8-64
ELEETRonlES In DESllin
of this high surface tension to assure
adhesion of LCCs to the bottom of a
substrate, while additional LCCs are
mounted to the top-producing very
high packing density modules.
The use of FC-70 (chemically
inert) in vapor-phase soldering
eliminates the problem of lead and
contact oxidation since the reflow is
done in an oxygen-deprived environment. The inert properties of FC-70
also eliminate any flux charring,
etching, or polymerization, making
cleanup of the final module simple.
Military memory modules
Integrated Device Technology
uses the highly reliable vapor-phase
reflow solder technique in manufacturing extremely fast, low-power
CMOS static RAM modules.
IDT utilizes its existing line of very
fast 16K static RAMs, produced in
the company's 2.5,..,m, double-poly,
proprietary "CEMOS" I process.
Since "CEMOS" I produces the
fastest 16K CMOS static RAMs
available, the memory modules have
the highest performance possible.
The high packing density tech-
nique of mounting LCCs to both top
and bottom of a substrate allows the
construction of 64K RAM modules
with equivalent pinout and function
to proposed monolithic 64K static
RAMs. IDT's volume production of
three organizations (SK x S, 16K x
4 and 64K x 1) allows users to leap
the evolutionary boundaries of
monolithic devices by designing
today with 64K static RAM modules
that can be replaced with monolithic
devices when they become readily
available. In addition, because faster
16K static RAMs are used, speeds of
65 nsec over the full military
temperature range can be achieved,
outperforming the proposed specifications for 64K monolithics.
Parameter matching
Since a memory module is, in
reality, a small subsystem, the
interplay of component parameters
becomes an important consideration. Expertise in manufacturing and
testing of the components becomes
an important asset. IDT takes
advantage of this knowledge of
manufacturing to prescreen each
component, analyzing a variety of
parameters and comparing those
parameters to characterization data
of modules, determining the performance of the module before it is
even constructed. This painstaking
procedure reduces costly rework
and, more importantly, eliminates
the possibility of matching three
high-performance components with
a lower one, thus producing a
module with lower overall performance.
Rework
Rework of module assemblies is
an extremely simple procedure.
After identification of the problem,
the assembly can be reheated to
reflow any inadequate solder joints
or to remove a defective component.
The difficulties arise in identifying
the problem. A thorough understanding of the component interplay
and use of a unique cell pattern test
is critical for minimizing the amount
of rework.
A unique cell pattern test can
identify the exact assembly problem.
If a failure occurs at the same
COMPONENT SCREENING PROCEDURES
FULLY ASSEMBLED MODULE SCREENING
PER MIL·STD·883, METHOD 5004, CLASS B
PER MIL·STD-883, METHOD 5004, CLASS B
SCREEN
Visual and Mechanical
Internal Visual
High·Temperature Storage
Temperature Cycle
Constant Acceleration
Hermeticity Fine and Gross
Burn·ln
Pre·Burn·ln Electrical
Burn·ln
Final Electrical Tests
Static (DC)
Functional
Switching (AC) or Dynamic
External Visual
TEST METHOD
LEVEL
2010, Condition B
1008, Condition C
1010, Condition C
2001
1014
100%
100%
100%
100%
100%
Per Applicable Device
Specification
1015, 160 Hrs. @
+ 125·C or Equivalent
100%
a. At 25·C and Power
Supply Extremes
b. At Temperature and
Power Supply
Extremes
a. At 25·C and Power
Supply Extremes
b. At Temperature and
Power Supply
Extremes
(lOT imposed)
a. At 25·C and Power
Supply Extremes
b. At Temperature and
Power Supply
Extremes
(lOT imposed)
2009
100%
Burn·ln
Temperature Cycle
Hermeticity
Fine and Gross
Final Electrical Tests
Static (DC)
100%
100%
Functional
100%
100%
Switching (AC)
or Dynamic
100%
100%
100%
Fig. 8.
8-65
TEST METHOD
SCREEN
Burn·ln
Pre·Burn·ln Electrical
External Visual
Per Applicable Device
Specification
1015,160 Hrs. @ + 125·C
or E~ivalent
ndition C
1010
1014
a. At 25·C and Power
Supply Extremes
b. At Temperature and
Power Supply
Extremes
a. At 25·C and Power
Supply Extremes
b. At Temperature and
Power Supply
Extremes
(lOT Imposed)
a. At 25·C and Power
Supply Extremes
b. At Tem~erature and
Power upply
Extremes
(lOT imposed)
2009
LEVEL
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
II
address in each device field, the es in surface mounting techniques,
implication is a bad substrate or an and a dedicated approach to
assembly problem with one or more reliability make the module ideal
common address lines. Failure in one for military applications. System
device memory field indicates an employment of modules and familiaassembly problem with one device, rization with its performance advanor a grossly mismatched component. tages will keep the military designer
In a dynamic failure mode, a unique ahead of the competition. Increascell pattern test can mask off all the ingly higher-density modules can be
memory fields but one and charac- generated much faster and more
terize the parameters of that easily than can monolithic devices,
individual device. This is essential to satisfying the higher-density needs of
determining the overall performance today's military systems. In addition,
degradation of having one device because of their lower cost, custom
with lower performance than others. modules are applicable for systems
requiring only moderate quantities.
Screening
To assure the most'reliable module Unique organizations (xl, x9, x16
possible, screening the components outputs), or unique functions (cache
and the module is important. IDT memories, chip set combinations,
processes all components to MIL- etc.), will allow tailoring the
STD-883, Level B for all military components to the system rather
applications. After assembly of the than the system to the component.
module, additional screening is
For additional information, conperformed to test mechanical inte- tact Joe Kraus, Product Marketing
grity and to ensure proper inter- Mgr., Subsystems, Integrated Deplay of the components (see Fig. 8). vice Technology Inc., 3236 Scott
Blvd., Santa Clara, CA 95051,
Right for the military
0
The availability of LCCs, advanc- 408-727-6116.
Reprinted from DESIGN NEWS October 10,1983
@1983CAHNERS PUBLISHING COMPANY
8-66
SYSTEM DESIGN/Integrated Circuits
HIGH·SPEED FIFOs
CONTEND WITH WIDELY
DIFFERING DATA RATES
Dual-port RAM buffer and a dual-pointer system provide
rapid, high-density data storage and reduce overhead.
by Michael J. Miller
Frank l. loth
High-speed multiprocessors, ideally, store large
amounts of sequential data in minimum memory
space. They also transfer data between processors
that are operating at different data rates. One of the
most common buffer/storage architectures developed to meet these needs is the first-in, first-out
(FIFO) RAM buffer. Until now, FIFO storage has
used high-speed, high-power, but relatively lowdensity, bipolar RAMS. Alternately, lower-speed,
higher-density MOS RAMS could be selected. Both
of these solutions, however, require the addition of
control circuitry, such as address counters, bus
buffers, and flag logic.
The Integrated Device Technology IDT 720117202
CMOS FIFO uses a dual-pointer system to provide
high-speed, high-density and low-power sequential
data storage. Model 7201 is a 512-location by 9-bit
wide FIFO. The 7202 FIFO is 1024 location by 9
bits wide. This chip offers an access rate of 50 ns,
and sports a dual-port RAM array with separate read
and write ports. It allows simultaneous asynchronous
reads and writes, eliminating the need for handshakMichael J. Miller is an engineering manager at
Integrated Device Technology (Santa Clara, CA). He
holds a BS in computer science from California
Polytechnic University.
Frank L. Toth is a marketing manager at Integrated
Device Technology. He holds an MBA from the
University of Santa Clara.
ing and bus arbitration. Two pointers within the
FIFO indicate the location within the RAM array
where the read or write will take place. When either
of the pointers reaches the last location in the FIFO
queue, the pointer is reset to the first location.
Three flags provide information about the status
of data within the array: an empty flag (EF), a full
flag (FF), and a half-full flag (HF). These status flags
provide a count of how many valid pieces of data
are in the memory queue.
Traditional FIFO designs have two sets of shift
registers to move data through the FIFO. One set
of registers holds the data. When data is placed in
the top register, it drops down and emerges at the
bottom. There is a second shift register, functioning in parallel, that contains flags. These flags show
whether the associated data element at the same
chronological position on the data queue is valid.
When data is written into the top location of the
data queue, a true flag is placed into the "validbit"queue. The length of the FIFO can be varied
8-67
The empty flag is not activated again until all data
has been read from the array. When the count of
data elements reaches more than half the number
oflocations in the RAM array, the half-full flag (HF)
is activated. If a read reduces the count to just below the half-way count, then the (HF) is deactivated.
The full flag is activated when the count of data elements is exactly equal to the number of locations
in the RAM array.
DATA INPUTS IDD·D8)
flAG lIT)
L~~I==+==: EMPTY
FULL FLAG lFi')
I------DUTPUT
EXPANSION PIN/HAlF·FULL
FLAG IXOiiiF)
Addresses in the dual-point architecture of the IDT
7201 and 7202 are generated internally by the
pointers to perform first-in, first-out functions.
by allowing the data and its associated valid bit to
sink down into the next lowest location-as long as
there is no valid data there. This process forms a
stack of valid data. The timing of data down through
the queue is controlled by an internal clock. The
maximum latency, fall-through time is the product
of the maximum number of locations in the queue
and the clock length cycle. The valid-data bit, which
tells the system that data is present, is brought out
in parallel with the queue data.
Dual·pointer architecture
An alternative to this classic shift-register architecture is one which. uses a RAM array and two
pointers. In this setup, the RAM array is 9 bits wide.
The pointers move sequentially through the data,
rather than data moving through the shift registers.
RAM dual-pointer architecture allows data to be accessed sequentially, eliminating the problem of fallthrough time. The write shows where new data will
be written. The read pointer indicates where data
will be read from the output. When either pointer
accesses its location, it is incremented. When a
pointer is incremented to the last location in the
array, it is reset to the beginning of the array. This
approach shortens the fall-through time and maintains a variable-length queue.
In a typical system cycle, the FIFO is reset, activating the empty flag (EF). As soon as data is written into the RAM array, the empty flag is inactive.
Wider FIFDs
Width and depth requirements vary widely according
to the application. Two expansion pins, one for input
(XI) and one for output (XO), enable unlimited
expansion of FIFO depth. For applications requiring less than 1024 locations, the maximum width of
the IDT FIFO is 9 bits. Wider word width can be
achieved by operating the control signals of two or
more devices in parallel. With devices working in
parallel, status flags can be detected from any device. Two IDT 720117202 devices can configure an
IS-bit word. Traditional FIFO architecture requires
more external circuitry to match the Input Ready
and Output Ready signals. This is necessary to account for the data differences in the internal, selfgenerated clock frequencies.
Traditional FIFO design also increases fall-through
time of data in applications calling for deeper FIFOs.
Since FIFOs are connected end to end in the older
architecture, data takes longer to fall through. Fallthrough time, in fact, increases in direct proportion
to the number of devices.
With the two-pointer approach, however, the data
input and data output bus are connected. This produces a parallel-processing architecture that is
analagous to cascading standard RAM devices to
achieve deeper memories.
Device selection
Since FIFOs do not have chip selects and external decoding mechanisms, the task of selecting
devices must be done internally. This control is
achieved through a unique serial structure. The first
(or master) FIFO is identified by grounding the FL
input. All other FIFOs in the structure must have
the FL input pulled up to Vcc. The XO output of
the first FIFO is connected to the XI input on the
next FIFO in the queue. The XO output of each
FIFO is connect to the XI input of the next, and so
on, until all FIFOs are serially connected. The XO
output of the last FIFO is then connected to the XI
of the first FIFO.
After a reset, the active read and write pointers
are in the first device. When the write pointer has
progressed to the end of the first FIFO device, it outputs a pulse on XO. This pulse activates the write
8-68
pointer at the beginning of the next device, and
simultaneously deactivates the write pointer in the
first device. This passes write enable control to the
second device. The read pointer functions in the
same way, using a pulse on the XO output to activate
the read pointer in the next device while terminating the read pointer of the first device. The two
pointers form a ring structure, with the read pointer
always chasing the write pointer. The pointer enable
crosses the device boundaries by sending an XO
pulse onto the next device.
The read and write pointers are designed so that
they can never cross each other, even in cascade
mode. The XO pulse occurs simultaneously with the
read and write signals. When the last location is read
or written to, the XO output goes low with the read
or write enable input, then goes high when this signal goes high. Even though reads and writes are
asynchronous, there is no conflict between the write
and read pointer.
One special situation occurs when the FIFO is
empty, and the read and write pointers are at the
last location. The system cannot read from the FIFO
until the empty flag is deactivated. To solve this
problem, the empty flag output will go high after
the write pulse goes high. This ensures that the
XO pulse, indicating the write pointer, has been
passed on to the next device. The system will then
read the last location. At this point, another XO
pulse will be issued, transferring the read pointer.
The flow-through mode provides maximum per-
WRITE CONTROL (Vi)
EMPTY FLAG (U)
READ CONTROL
(iii
OUTPUT
EXPANSION
PIN (Xil)
~
;-____
~r----!---'
~
II
I I
-----u--u--
??
li:(
a) REGULAR CASE
WRITE CONTROL (Vi)
EMPTY FLAG (U)
REAO CONTROL
iii)
I
I
L -_ _ _ __
OUTPUT
---,
rT1
.---EXPANSION PIN (ill)
L...J """L---...J
b) THE READ-FlOW-THROUGH CASE
FIFO is empty, and the read and write pulses are
separate and distinct (a). Read-flow-through mode is
invoked while the printers are at the device
boundaries (b).
formance and design simplification for systems
which are pipelined. The read-flow-through mode
is a special case where data is allowed to flow
through and empty the FIFO by lowering the read-
tHi'
iHi'
18
DATAIN1
WRITE
FUll FLAG
RESET
(W)
(FF)
~
v
9
-\
i ,;
101720112
(RS)
IDT720I12.
-
9
~
~
-JJ
-
(ii)
9
11..L
(0) DATA
OUT
Width expansion of the IDT7201 7022 for designs require more storage than 1024 hy 9 hits. The parts
function in parallel, avoiding system performance degradation.
8-69
READ
(H) EMPTY FLAG
The high-speed FIFO solution
In file server applications, high-speed FIFOs offer
lower costs and higher efficiency than other hardware or software approaches. Assume the file
server is connected to a local area network (LAN)
on one side and a Winchester disk on the other.
Both 110 connections demand attention at unpredictable intervals and must be serviced on demand,
or data is lost.
A possible software solution would be to place
data into software FIFO queues as it arrives. When
a full record is buffered, processing begins. To implement this solution, though, the data rates of both
interfaces would have to be low enough so that the
software code could poll the status of either 110
port. Also, the ports would have to be monitored
in case another user on the LAN makes a request.
These time-consuming tasks detract from system
performance.
One hardware approach to moving data in file
server applications uses hardware interrupts. Here,
an interrupt mechanism calls routines to move data
to and from the 110 ports and the software FIFO
queues. Interrupts allow one task to run at a time
and can switch to an 110 service routine at any instant. An interrupt solution, therefore, must be
designed so that the interrupted task's data is not
destroyed. Extra code is required to maintain the
state of the machine. This overhead may prevent
an interrupt during a critical time for a particular
piece of code. This would in turn require code to
disable and re-enable interrupts around the critical
sections. Also, the programmer must spend additional time proving that all possible sequences
caused by random interrupts will produce desirable
results. Typically, these complications outweigh
the faster execution hardware interrupts offer.
Direct memory access (DMA) offers another hardware solution for a file server application. This approach monitors 110 ports with a block of circuitry.
When the port requires attention, the DMA logic interrupts the current task at the bus transfer level
enable input before data is written into the FIFO.
When the empty flag (EF) is finally deactivated, signaling a write from the input side, the receiving
circuitry can terminate the read cycle by reading
after the appropriate access time, then deactivate the
read signaL
The write-flow-through mode is used when the
read signal is full. The sending circuitry can anticipate a read by the receiving circuitry by lowering the
write input before the full flag (FF) is deactivated_
The receiving circuitry knows that the sending circuitry has read a location, freeing up a location to
receive new data. The sending circuitry then activates
the write input, writing data into the RAM array.
This flow-through mode means the full flag does not
have to be monitored before initiating a write cycle_
and steals a memory cycle to transfer the data to
or from the port and the FIFO queue in memory.
Although memory cycles are lost, the effect is
mimimal when contrasted with the hardware interruptscheme, where a whole subroutine of many
cycles was executed to transfer each element of
data. A significant disadvantage of the DMA solution is that the DMA controllers are complex
devices which must be programmed and implemented in the bus structure. In addition, since the
DMA mechanism can only serve one source at any
given instant, they act as a throughput bottleneck.
In file server applications, all of these solutions
move the mechanism that feeds data to or from the
FIFOs into program memory, away from the software and closer to the 110 port. Because both FIFO
queues are in memory, the memory bus remains a
bottleneck. Hardware FIFOs avoid this memory bus
bottleneck and boost system performance.
The processor would still interface to the FIFO
through an 110 port, but the FIFO would now be between the 110 port and the rest of the hardware. The
software could service data at a steady rate with
no loss of data. without the problems or overhead
associated with more complicated schemes such
as interrupts or DMA. Because the queues are between the controller and the peripheral, the
peripheral can load or read the queue without interrupting the controller. Since the controller is not
involved with maintaining both queues, there is no
possibility of lost data because one queue was being serviced while data for the other queue arrived.
Large FIFOs, such as the IDT7202 which is 1024
location by 9 bits, offer a minimum device count.
Assuming that there are two FIFOs (transmit and
receive) for each 110 port, then there will be only four
28-pin devices for the FIFO solution. The DMA approach, however, requires at least one 40-pin device
and several bus buffer/control devices as well. A
similar parts count can be expected with the interrupt solution.
Hardware FIFOs are an economical memory organization to use when lists of data items are to be
buffered_ Because they do not require an address to
access items in the list, there is less overhead in terms
of both circuitry and access time.
Reprinted with permission from Computer DeSign - September 1, 1985 issue.
11-70
DESIGN ENTRY
16-by-16-bit multipliers
fabricated in CMOS
rival the speed of bipolars
A pair of CMOS parallel multipliers sports a 65-ns clock
multiplication time, allowing them to substitute for bipolar
equivalents in digital signal-processing circuits.
T·
he mathematical theories behind digital
signal-processing systems have been
around for decades, but not until the arrival of inexpensive dedicated ICs could designers readily implement complex digital
signal-processing systems. Their availability
opens up a wide variety of applications in such
areas as real-time speech processing and pattern recognition, not to mention radar and
spectrum analysis.
Digital signal processing consists mostly of
a series of multiplications and additionswith the multiplications taking up the most
time. Thus one of the primary building blocks
in any such system is a parallel muitiplier that
handles large numbers quickly. Fortunately,
digital signal processing no longer need depend on power-hungry bipolar multipliers to
obtain the requisite speed. A pair of CMOS
multipliers-which give designers all the ad-
vantages inherent in that process-are now
available that are as fast as many of their bipolar equivalents.
Some specifications
The two paraUeI16-by-16 bit multipliers
operate with a 65-ns clock multiplication time
and a typical power consumption of only 200
m W, which is less than '/12 that of comparable
bipolar devices. This power advantage demands no sacrifice in speed and is achieved
through the use of a CMOS technology known
asCEMOS-1.
The architecture of the duo is relatively simple, with each multiplier consisting of three
sections: An input-register arrangement for
Frank Lee, Chun P. Chiu, and Frank Toth
Integrated Device Technology Inc.
After working on silicon-on-sapphire technology at
Hewlett-Packard's Cupertino Division, Frank Lee
helped to found IDT in Santa Clara, Calij., in 1981. He
is currently director of product development.
Cofounder Chun P. Chiu also came from HP's Cupertino Division; he is now IDT's director of DSP design engineering.
Before joining IDT last January as marketing manager for the DSP Division, Frank Toth was marketing
manager for microprocessors at Synertek.
Reprinted from ELECTRONIC DESIGN- June 14, 1984
Copyright 1984 Hayden Publishing Co .• Inc.
8-71
DESIGN ENTRY
Semiconductor Technology: Fast CMOS multipliers
two 16-bit numbers (X and Y), an asynchronous multiplier array, and an output-register
arrangement. The last includes a multiplexer
that supplies two output paths for the final
product (Fig. 1).
The differences between the two multipliers
show up mainly in their clocking configurations. The IDT7216 features four independent
clocks, one for each of the circuit's two input
and two output registers (CLKX, CLKY,
CLKL, CLKM). The clocks can thus be arranged to simplify the design of a digital
signal-processing system and to maximize its
throughput. The IDT7217, on the other hand,
employs only a single clock for all the registers,
which makes it suitable for pipelined microprogrammed systems. It also furnishes separate register-enable signals (ENX, ENY, and
ENP).
Identical twins, almost
ClKY o - - r t - . - - = - + - t - - - - - '
ClKX O-----<~-H
FA o - - - - - - - - + t
FT
ClKM
e>:=======-.+:..J
ClKlO
MSPSEl
OEP
Except for the different clocking and enabling schemes, the devices are identical. In
both circuits, a multiplication is performed by
an array of adders in accordance with a modified Booth's algorithm with a 4-bit carrylook-ahead circuit, which helps achieve the required high speed. All of the input registers, as
well as the output registers for the least significant product (LSP) and the most significant
product (MSP) use the same positive-edgetriggered D-type flip flops.
In operation, the two numbers to be multiplied are fed into separate X and Y registers,
which also receive two signals (XM and YM) that
identify whether the input is in the form of an
unsigned magnitude or a two's complement.
Consequently, users are able to multiply
mixed-format inputs.
h,"",,""".,--;-=---l
0--------+1
0--------+1
0----------'i7
ClK
ENX <>::~~::f;f'~[jL=-:::
0
ENYo---~--t--_+_+~~
FT
O-----I~~~~
ENPo-------~=t~=t=~
Routing the output
Once the multiplication is carried out, a Format Adjuster (F A) signal converts the 32-bit
output into the desired format: either a full
32-bit product or a left-shifted 31-bit product
with the sign bit replicated in the LSP. The
data then passes into two 16-bit latch registers, one for the LSP and another for the MSP
part of the output. Each 16-bit segment of the
total product can be clocked out separately
through the multiplexer under the control
8-72
MSPSElo-------~
OEP
0----------'17
16
(b)
1. Two nearly identical versions 01 the 16-by-16-bit
parallel multiplier are available. The IDT7216 (a)
supplies lour separate clock-input ports lor the two
16-bit input registers and the two 16-bit output registers. The IDT7217 (b) lurnishes a single clock input
lor all the registers but three separate registerenable signals.
of the Most Significant Product Select
(MSPSEL) signal.
Additionally, the output from the LSP register can be routed to the Y 110 port by means
of the output enable (OEL) signal, which controls a three-state output buffer. When the input and the output data need not be latched, the
Feedthrough (FT) control signal is available to
make the MSP and LSP registers transparent.
The twelvefold power advantage of the new
multipliers is a result of the aforementioned
CEMOS-I process, a 2.5-/otm double-polysilicon,
dual-well technology that employs a lightly
doped substrate and cuts cost by obviating the
need for an epitaxial layer. With the process,
the delay of an inverter is a mere 0.430 ns at5 V.
ture tolerance. Since the CMOS process integrates both n- and p-type devices on one chip,
the data output is able to employ an npn transistor as a pull-up device and an n-channel FET
as a pull-down circuit. Doing so takes advantage of the fact that increasing temperature
slows down FETs but speeds up npn bipolar
transistors. The result is a device whose multiOperand B
(64 bits)
Operand A
(64 bits)
Sign
Exponent
Sign
Fraction
11
52
Exponent
Fraction
11
52
On the level
Moreover, since CMOS devices draw power
only while switching from one level to another,
slowing down the device further decreases the
multipliers' power requirements so that it
drops below the full-speed figure of 200 mW.
Such power savings not only reduce both thermal stress and power supply costs, but equally
importantly they allow the designer the option
of housing a complete system in a smaller
package. That freedom is made possible because elaborate heat-sinking apparatus such
as heat rails, cooling pipes, and fans are usually not required.
At the same time, the size of the printed
circuit board may be significantly reduced.
For example, a system of 12 bipolar multipliers, each in a 64-pin package, takes up 36.84
in.t. Additionally, the thermal expansion and
power dissipation problems of such a 3.5-W device are quite substantial. However, with the
CMOS multipliers housed in 900-milleadless
chip carriers, the same system can be squeezed
into less than 15.36 in.t.
Beat the heat
An added bonns of the leadless chip carriers
is that their lead capacitances are about half
those of a typical DIP, thereby reducing interconnection propagation delays. Also, the chip
carriers weigh approximately 1/10 as much as
an equivalent DIP.
Finally, beyond its low power dissipation,
the CMOS design also ensures a wide tempera-
I Sign (S)
1 bit
Exponent (El
11 bits
I.
Fraction, or significand (F)
•
Implicit
binary point
Nominal value
=
-1 S {1.F) 2E -
52 bits
t023
(b)
2. The multipliera can be put to good uae in highapeed floating-point applicationa auch aa a M-by64-bit circuit (a). The operanda employed follow the
IEEE double-preciaion atandard (b), which deaignatea the firat bit aa the aign, the next 11 bita aa a
number'a exponent (a power of 2), followed by a
53-bit fraction. In the multiplication proceal the
fractiona are multiplied aa integera and the axponenta are merely added.
8-73
DESIGN ENTRY
Semiconductor Technology: Fast CMOS multipliers
plication time varies little over the military
temperature range. Moreover, its output swing
is symmetrical from rail to rail.
Naturally, the self-heating effects of bipolar
devices that produce excessive die-surface
temperatures and lower overall device reliability are absent. Also absent is an old CMOS
problem-Iatch-up. Large input overshoots,
which cause no ill effect in bipolar circuits, can
result in latch -u p wi th some types of CM OS devices. That problem occurs when the close
proximity of p- and n-channel elements form
what is essentially a silicon controlled recti-
fier. In the multiplier designs, latch-up is suppressed through the selective use of guard
rings, which were designed into the chip after a
careful analysis of all possible latch-up paths.
As a result, no adverse latch-up effects should
be observed with as much as 800 mA applied to
the 1/0 pins.
No static
Another significant problem familiar to
users of CMOS, especially in systems operating
in harsh environments, is damage due to electrostatic discharges. However, the several
Operand Y
(64 bits)
LSB
MSBI
Xo 16 bits
Y,
Y,
16 bits
16 bits
X 1 16 bits
Operand
X
(64 bits)
+XoY,
X, 16 bits
+X 1Y2
I
Y,
16 bits
Yo
16 bits
ILSB
l
Partial
+X 1Y3
products
X3 16 bits
+X2 Y1
of
16 multipliers
+x,Y,
+)(,Y,
MSB
+x,y,
I
+x,y,
I
I
+x,Yo
+XoY,
J
LSB
' - - - - 64-blt product ---~
l ' - - - - - - - - - I 0 6 - b l t product
-------~
3. In an array of sixteen 16-bit CMOS multipliers, two 64-bit operands are multiplied
in combinations of 16 by 16 bits and the partial products added 10 produce a 128-bit
output. The six partial products shown in color make no contribution to the 64 MSBS.
8-74
forms of input protection circuitry employed
in the multipliers, such as large-area gatemodulated diodes, protect against electrostatic discharges to 5000 V. Thus with the major problems generally associated with CMOS
solved, especially its speed limitation, applications for the pair of multipliers abound.
Floating-point arithmetic, for instance, demands high-speed multiplication. Virtually all
popular 16-bit microprocessor families have
coprocessors that are able to carry out such
precise floating-point operations. Moreover, a
new standard on binary floating-point arithmetic, IEEE 754, has been widely adopted. It
designates 32-bit single-, 64-bit double-, and
even 80-bit extended-precision output products, all of which are finding wide use in engineering workstations for mechanical and
electrical simulation, matrix inversion, and
a wide variety of other scientific digital signalprocessing applications.
However, although performing an arithmetic operation in tens of microseconds might
be a satisfactory rate for simple problem solving, designers are increasingly faced with the
need to speed up floating-point operations because of the growing complexity of data processing applications, especially interactive design work. Accordingly, the computing power
of large array processors is now required in
small table-top workstations.
The 64-bit question
Even though the 32-bit microprocessors and
related chip sets now emerging offer some
hope of carrying out floating-point operations
at high speed and with single precision-the
64-bit double-precision format is another
matter. In the past, bulky high-power bipolar
devices were the designer's only choice. Now,
the CMOS multipliers supply a more attractive
alternative.
For instance, consider a common configuration for a 64-bit floating-point multiplier
that employs the IEEE double-precision format (Fig. 2). During a multiplication, the
ll-bit exponent field of the format is calculated using just simple addition. Calculating
the fractional (significand) field, on the other
hand, involves the multiplication of two 53-bit
integers, which generates a 106-bit product. If
,8-75
the IEEE standard's precision requirement is
relaxed to allow a 64-bit product, the significand multiplication can be handled by an array
of 10 multipliers.
At first glance it would seem that 16 multipliers are needed (Fig. 3). However, only the 10
most significant partial products contribute to
the 64 MSBs of the final product. Thus the lower 6 partial products do not have to be produced
and added. In that way, six multipliers and 12
adders can be eliminated.
A part in every port
As mentioned earlier, the 32-bit products
from each individual multiplier in the array
can either be multiplexed out of the single
16-bit product port in two parts or both parts
can be delivered simultaneously, one through
the product port and the other through the
shared Y-operahd I/O port. Naturally, for the
greatest speed and the minimum amount of
hardware, the Y 110 port should be shared,
which is easily done merely by disabling the Y
input mode of each circuit after the multiplier
has been loaded.
Also contributing to the high speed of the
multiplier array is the fact that all the multipliers are loaded'simultaneously and produce
their output only one multiplication-delay later: Just the summed partial products propagate through the array. Finally, the rounding
(RND) input signal is not enabled individually
for partial products but is activated at the end
of the overall multiplication based on the
precision requirements for the final output
product.
Indeed, the advantages of the CMOS parallel
multipliers are most dramatically demonstrated wherever large arrays of high-speed
multipliers are needed. It should be kept in
mind, though, that the combination of low
power, small size, and high speed that the 7216
and 7217 offer are important benefits in any
application-even if only a single multiplier is
used. 0
II
QUALITY CONFORMANCE PROGRAM
COMMITMENT TO QUALITY
Integrated Device Technology's monolithic and modular hermetic products
are designed, manufactured and tested in accordance with the strict
controls and procedures required by Military Standards. The
documentation, design, processing and assembly criteria of our Quality and
Reliability Assurance Program were developed using MIL-M-38510 as the
guideline.
Product flow and test procedures for all monolithic hermetic Military Grade
products are in accordance with MIL-STD-883. State-of-the-art production
techniques and computer-based test procedures are coupled with stringent
controls and inspections to ensure that products meet the requirements for
100% screening and quality conformance tests as defined in MIL-STD-883,
Methods 5004 and 5005.
Product flow and test procedures for all modular hermetic products are
patterned after the 100% screening and quality conformance requirements
of MIL-STD-883.
Product flow and test procedures for all plastic products are in accordance
with industry practices for producing highly reliable plastic molded products.
State-of-the-art production techniques and computer-based test procedures
are coupled with stringent controls and inspections to ensure that products
meet the requirements for 100% screening and quality conformance tests.
By maintaining these high standards and rigid controls throughout every
step of the manufacturing process, IDT ensures that our Military and
Standard Grade monolithic and modular hermetic products consistently
meet customer requirements for quality, reliability and performance.
8-76
SUMMARY PLASTIC PRODUCT
PROCESSING FLOW
1.
Wafer Fabrication. Humidity, temperature and particulate
contamination levels are controlled and maintained according to
criteria patterned after Federal Standard 209, Clean Room and
Workstation Requirements. All critical workstations are maintained at
Class 100 levels or better.
Topside passivation is applied to all wafers for better moisture barrier
characteristics.
Wafers from each wafer fabrication area are subjected to scanning
electron microscope analysis on a periodic basis.
2.
Die-Sort Visual Inspection. Wafers are cut and separated and
the individual die are 100% visually inspected to strict internal criteria.
3.
Die Push Test. To ensure die attach integrity, product samples are
routinely subjected to die push tests.
4.
Wire Bond Monitor. Product samples are routinely subjected to
wire bond pull tests to ensure the integrity of the lead bond process.
5.
Pre-cap Visual. Before the package is molded, 100% of the
product is visually inspected to criteria patterned after MIL-STO-883,
Method 2010, Condition B.
6.
Post Mold Cure. Plastic encapsulated devices are baked to insure
an optimum plastic seal so as to enhance moisture barrier
characteristics.
8-77
II
7.
Pre-Burn-In Electrical. Each product is 100% electrically tested at
T A = +25°C to lOT data sheet or customer specifications.
8.
Burn-In. Standard Grade products are burned-in 40 hours or
equivalent on memory devices, 16 hours or equivalent on VLSllogic
devices and may be obtained as an option on MSllogic family
devices (FCT, AHCT and 39C800) utilizing the same burn-in
conditions as the Military Grade product.
9.
post-Burn-In Electrical. After burn-in, 100% of the plastic product
is electrically tested to lOT data sheet or customer specifications at
+25°C and the maximum temperature extreme. The minimum
temperature extreme, is tested periodically on an audit basis.
10.
Mark. All product is marked with product type and lot code
identifiers.
11.
Quality Conformance Inspection. Samples of the plastic product
which have been processed to the 100% screening requirements of
Table I are subjected to the periodic Inspection Program as outlined in
Table II. Where indicated the test methods are patterned after
MIL-STO-883 criteria.
8-78
TABLE I
PLASTIC PACKAGE PRODUCT FLOW
G
100% SAW
= QUALITY INSPECTION
ALL OPERATIONS SHOWN ARE
100% PROCESSING STEPS
UNLESS OTHERWISE INDICATED
OPTICAL INSPECTION
OPTICAL INSPECTION
LTPD SAMPLE
INCOMING
LEAD FRAME
AQLSAMPLE
INCOMING r - - - - - ,
DIEATIACH
EPOXY
AQL SAMPLE L.-_ _...J
FRAME LOAD
EPOXY DIE ATIACH
AND CURE
DIEATIACH
PUSH TEST
SAMPLE
INCOMING GOLD
WIRE AQL SAMPLE
THERMASONIC
WIRE BOND
LEAD BOND
PULL TEST
SAMPLE
8-79
TABLE I
Continued ...
PRE-CAP OPTICAL
INSPECTION
PRE-CAP OPTICAL INSPECTION
LTPD 5/ACC NO.2
INCOMING
MOLDING COMPOUND
AQLSAMPLE
ENCAPSULATION/MOLD
CHEMICAL
DE FLASH
POST MOLD
CURE
MECHANICAL
DE FLASH
TRIM/FORM/
SINGULATION
SOLDER DIP
OPEN/SHORT TEST
LTPD SAMPLE
EXTERNAL
VISUAL
PRE-BURN-IN
ELECTRICAL TEST +25°C
8-80
TABLE I
Continued ...
BURN-IN BIASED/DYNAMIC AT +12SoC
40 HRS OR EQUIVALENT ON MEMORY DEVICES
AND 16 HRS OR EQUIVALENT ON VLSI LOGIC DEVICES
AND MAY BE OBTAINED AS AN OPTION ON MSI LOGIC
FAMILY DEVICES (FCT, AHCT AND 39C800)
POST BURN-IN
ELECTRICAL TEST +70°C
:5:10%
ELECTRICAL TEST QUALITY
SAMPLE LTPD S/ACC NO.1 +70°C
TOPSIDE MARK
LEAD STRAIGHTEN
100"10 ELECTRICAL
QUALITY TEST +2SoC
:;;S%
SHIPPING
INSPECTION GATE
8-81
TABLE II
SUMMARY
PLASTIC QUALIFICATION/PERIODIC INSPECTION PROGRAM
SEQUENCE AND TEST DESCRIPTION
SEQUENCE A:
LTPD
ELECTRICALS
100PPM
P!;BEQBM!;l:!l QQ'M> EAQ!:lIN§PECTION LOT
SEQUENCE B:
QUALITY LEVEL
MAXIMUM
SAMPLE SIZE/ACCEPT NO.
PACKAGE/PROCESS
PERFORMED EACH 8 WEEKS EXCEPT FOR B-6 EQR EAC!:l PACKAG!; FAMILY
'l"
~
B-1
PHYSICAL DIMENSIONS, MIL-STD-883, METHOD 2016
-
B-2
RESISTANCE TO SOLVENTS, MIL-SID-883, METHOD 2015
-
B-3
SOLDERABILITY, MIL-SID-883, METHOD 2003
15
B-4
RESISTANCE TO SOLDERING HEAT, 260·C FOR 10 SECONDS
10
B-5
AUTOCLAVE: UNBIASED, 2 ATM SATURATED STREAM, +121 ·C, 96 HOURS
B-6
ESD SENSITIVITY, MIL-SID-883, METHOD 3015, CAT. A, PERFORMED FOR INITIAL
QUALIFICATION ONLY.
-
SEQUENCE C:
210
8/0
25/1
38/1
10011
15/0
PACKAGE/CHIP
PERFORMED EACH 9 MONTHS MAXIMUM
C-1
STEADY-STATE LIFE TEST, MIL-SID-883, METHOD 1005 +125·C, FULLY DYNAMIC,1000HR.
5
105/2
C-2
MOISTURE LIFE TEST, 85·C/850/0RH, STATIC BIAS, 1000HR.
5
105/2
SEQUENCE D:
PACKAGE DESIGN
I
I
PEBEQBM!;I:! EACH!! MQNTHS MAXIMUM ON EAQt:J PAQIWaE FAMILY EROM EAQ!:l
ASS!;MBLY LOQATIQN
0-1
LEAD FATIGUE, MIL-SID-883, METHOD 2004, CONDITION B2
15
3412
0-2
THERMAL SHOCK, MIL-STD-883, METHOD 1011, CONDITION A, 0-100·C, 15 CYCLES
5
105/2
D-3
TEMPERATURE CYCLING, MIL-STO-883, METHOD 1010, CONDITION 0,
-65·C TO +150·C, 100 CYCLES.
5
105/2
----
SUMMARY OF MONOLITHIC HERMETIC
PRODUCT PROCESSING FLOW·
All test methods refer to MIL-STD-883 unless otherwise stated.
1.
Wafer Fabrication. Humidity, temperature and particulate
contamination levels are controlled and maintained according to
criteria patterned after Federal Standard 209, Clean Room and
Workstation Requirements. All critical workstations are maintained at
Class 100 levels or better.
2.
Die-Sort Visual Inspection. Wafers are cut and separated and
the individual die are 100% visually inspected to strict internal criteria.
3.
Die Shear Monitor. To ensure die attach integrity, product
samples are routinely subjected to a shear strength test per Method
2019.
4.
Wire Bond Monitor. Product samples are routinely subjected to a
strength test per Method 2011, Condition D, to ensure the integrity of
the lead bond process.
5.
Pre-Cap Visual. Before the completed package is sealed, 100% of
the product is visually inspected to Method 2010, Condition B criteria.
6.
Environmental Conditioning. 100% of the sealed product is
subjected to environmental stress tests. These thermal and
mechanical stress tests are designed to eliminate units with marginal
seal, die attach or lead bond integrity.
7.
Hermetic Testing. 100% of the hermetic packages are subjected to
fine and gross leak seal tests to eliminate marginally sealed units or
units whose seals may have become defective as a result of
environmental conditioning tests.
8·83
8.
pre-Bum-In Electrical. Each product is 100% electrically tested at
T A +25°C to lOT data sheet or customer specifications.
9.
Byrn-In. 100% of the Military Grade product is burned-in under
dynamic electrical conditions to the time and temperature
requirements of Method 1015, Condition O.
10.
post-Byrn-In Electrical. After burn-in, 100% of the Class B Military
Grade product is electrically tested to lOT data sheet or customer
specifications over the -55°C to + 125°C temperature range. Standard
Grade products are sample tested to the applicable temperature
extremes.
11.
MItIs.
12.
Qyallty Conformance Jests. Samples of the Military Grade
product which have been processed to the 100% screening tests of
Method 5004 are routinely subjected to the quality conformance
requirements of Method 5005.
=
All product is marked with product type and lot code identifiers.
* For quality requirements beyond Class B levels, such as SEM analysis,
X-ray inspection, particle impact noise detection (PINO) test, Class S
screening or other customer specified screening flows, please contact
your Integrated Device Technology sales representative.
8-84
MILITARY GRADE PROPUCT FLOW
HERMETIC PACKAGES
(SEE NOTE 1)
MIL-SID-BB3
TESIMETHOp
= QUALITY SAMPLE
INSPECTION
VISUAL SORT
VISUAL INSPECTION
VISUAL INSPECTION
LTPD 7/1
SAMPLE
INCOMING
PREFORM
(AQL SAMPLE)
INCOMING
SIDEBRAZE
PACKAGE
(AQL SAMPLE)
DIE ATTACH
DIE ATTACH
PUSH TEST
SAMPLE
2019
>2.5kg
INCOMING WIRE
(AQL SAMPLE)
WIRE BOND
LEAD BOND
PULL TEST
SAMPLE
II
NIA
I
2011
+
8-85
>3.0g
MIL-STP-883
TEST METHOD
PRE-CAP VISUAL
PRE-CAP VISUAL
LTPDS
ACCNO.=2
2010
I
2010
COND.B
COND.B
INCOMING
LIDS
(AQL SAMPLE)
N/A
I
N/A
I
STABILIZATION BAKE
1008
CONDC
TEMP CYCLE
1010
CONDE
CENTRIFUGE
2001
CONDE
I
I
I
FINE LEAK TEST
1014
CONDA
orB
GROSS LEAK TEST
(100%)
1014
CONDC
I
FLATPACK
ONLY
TRIM
N/A
ATTACH BUMPER TOPBRAZE
CHIP
ONLY
8-86
PROVIDES LOT
TRACEABILITY
24HRl1S0°C
10 CYCLES
-6SoC TO +1S0°C
Y1 DIRECTION
30KG (PKG < Sg)
20KG (PKG <:: Sg)
10K
10 B
Enhanced
>30K
NONE
(;e2.4 x 10 '0)
NOTE:
1. This data is for RAMs. Logic circuits are generally higher.
Figure 3.
lOT
xxxxx
A
999
A
A
AA
DEVICE TYPE
POWER
SPEED
PACKAGE
PROCESS
RAD HARD
MIL-STD-883, Class B
MIL-STD-883, Class S
Standard
Radiation Tolerant
Radiation Enhanced
I
I
~
Blank
RT
RE
Figure 4.
8-91
SYSTEM CONSIDERATIONS
IN THE TESTING OF FAST CMOS DEVICES
In order to evaluate or verify the performance of fast CMOS
devices, it is important to implement a measurement environment
that does not degrade device operation. The following article
outlines techniques for system configuration which may alleviate
common degradations of test systems.
Ground Noise is one of the most common and troublesome test
problems. Ground noise is the unwanted voltage fluctuation of
the ground reference due to current spikes required during the
switching of device output logic levels. These voltage variations
in the ground reference can be quite significant, and can cause
an erroneous perception ofthe voltage margin or noise immunity
tolerance of the device under test (OUT). In a memory tester the
ground path incldes handler contacts, connectors and the OUT
load board, thus there may be one long, high inductance ground
path back to the test system ground.
In practice, ground noise may be minimized by using the
following techniques:
• Provide multiple high-quality, high-frequency, ceramic bypass
capacitors as close as possible to the OUT and again on the
OUT load board. This allows the Vee wiring to serve as an extra
AC ground path for high-frequency ground noise.
• Keep the ground path as short as possible; use large diameter
or multi-strand wire and "straight-line" wiring techniques.
(Note: Multi-strand wire is preferred for high frequency applications because of skin resistance effects.)
• Minimize the number of series connections in the OUT ground
path; provide as many parallel ground connections as possible
through each remaining connector.
• If the system uses a Kelvin (force-sense) ground system,
terminate the system by shorting force to sense on the OUT
load board. Kelvin systems provide DC accuracy, but their
response times are much too slow to aid in the suppression of
ground noise althe test site. Terminating Kelvin early sacrifices
a little DC accuracy, but the ability to use the sense line as a
second, low impedance ground path usually improves the
overall test accu racy.
• Reduce the OUT load capacitance (receiver and interconnect
capacitance) as much as possible; avoid using low values of
load resistors. Both techniques reduce the transient currents,
thus improving test accuracy. When necessary, OUT output
drive capability can usually be verified with DC tests.
Reflections, due to impedance mismatch between the OUT
output drivers and the circuitry which connects the outputs to the
test system, are another common problem. This resonance
occurs because the wire connecting the OUT outputs to the
receivers is actually an inductor connected in series with the
comparator input capacitance, forming a series resonant tank
circuit. Uncorrected ringing can cause errors in measuring
output timing and increase cross-talk noise.
Note also that ringing also occurs on input signals to the OUT
from the test system, and these signals should also be matched.
Of particular importance are edge-triggered control lines (e.g.
Write Strobe) which, if ringing excessively, will cause doubletriggers.
In practice, ringing may be minimized by using the following
techniques:
.
• In instances where severe conditions exist, it is best to try to
match the driving source with the transmission line and load. A
series resistor of 20 to 70 ohms is likely to tune most normal
appl ications.
• Use short, low inductance connections from the OUT output to
the receiver; minimize comparator and interconnect capacitance. Both techniques raise the resonant frequency of the
tank circuit which limits the time measurement error and
reduces the OUT's ability to stimulate ringing in the tank
circuit.
• Use twisted pair wiring techniques to connect OUT outputs to
the receivers. Though this raises the capacitance slightly, it
reduces the purely inductive character of the interconnect,
usually tending to reduce ringing.
Cross-Talk between signals on adjacent lines is also a common
problem in high-speed systems. This inductive coupling will tend
to add noise to both input and output lines, causing errors in
measuring input noise margin and output settling times, respectively. Techniques to reduce cross-talk are as follows:
• Physically separate conductors of critical signals and keep
wires as short as possible.
• Reduce output loading to minimize the magnitude of current
transients which could be coupled to adjacent lines.
• Use twisted pair or shielded cable wherever possible; take care
to tie all grounds from these transmission lines together at both
ends.
• Use ground plane or ground mesh techniques in the load
board and the handler interface if possible.
• Use pull-up or pull-down resistors on unused inputs. Without
these safeguards, device inputs are especially susceptible to
cross-talk noise.
Latch-Up is a possiblity with CMOS memories, and good test
procedures will ensure that unwanted latch-up does not occur.
Vee should never exceed the absolute maximum rating, and
input lines should never be taken below ground voltage. Latchup is discussed in more detail elsewhere in this data book.
In conclusion, the issues in desiging a test environment are
identical to designing any high-speed system, but the initial
conditions given in designing a test-system interface-and
importance of correct resultS-dictate a higher degree of dedication to the details outlined above.
8-92
THERMAL PERFORMANCE DATA OF
INTEGRATED DEVICE TECHNOLOGY PACKAGES
When calculating the junction temperature, TJ, at which an
operating integrated circuit functions, it is necessary to know the
thermal resistance of the package, /lJA, measured in "degrees
centigrade per watt." With this data, the following equation
is used:
ization of these variables, a range of values is provided rather
than a single point.
Please note that /I JA is the thermal resistance from the device
junction tothesurrounding environment which, typically, is "still
air" at 25°C with the package inserted into a low cost socket
mounted on a printed circuit card.
Also included in the figures is /lJC, which is junction to case
thermal resistance with the package attached to an "infinite" heat
sink. For surrounding conditions that are different, TJ can
theoretically be calculated using the following equation:
TJ = TA + P [IiJAl
where TA is the ambient temperature and P is the power at which
the device operates.
The figures below represent generic thermal performance data
for standard IDT production packages. Thermal resistance is
influenced by a number of factors, including die size, cavity size,
and die bonding; in order to present a comprehensive character-
TJ=TA + P [/lJc+ /lcAl
where IICA, the case-to-ambient thermal resistance, depends on
the airflow conditions, etc., and must be known.
100
~90
~80
~70
w
~60
~50
iii
l:!40
..J
~30
ffi20
J:
I-
10
0~16:--:20!-:--:!24""""'2:!:8""""'31:-2--:!:36:--4:::0~44""-4:!:8:--:5!::-2--:!:56:--6:::0-:!64':-68-H
LEAD COUNT
LEAD COUNT
THERMAL RESISTANCE OF
THERMAL RESISTANCE OF
PLCC/SOIC PACKAGES
CERAMIC CERDIP PACKAGES
100r------------------------------------,
100
eo
j:"90
lit 80
~80
~
o
~70
i!...70
w
w
060
~ 60
~
fI)
~ 50
50
iiia: 40
iii
..J
..J
l:! 40
~30
~30
a:
!l! 20
ffi 20
10
10
I-
~
o
01620242832364044485256606468
LEAD COUNT
16
20
24
28
32
36
40
44
48
52 56
60
64
LEAD COUNT
THERMAL RESISTANCE OF CERAMIC
SIDEBRAZE PACKAGES
THERMAL RESISTANCE OF
PLASTIC PACKAGES
8-93
68
'OO~~~~~----------------------'
w
U
Z
j!
1/1
iii
~
II:
1520
l:
1-'0
LEAD COUNT
THERMAL RESISTANCE OF CERAMIC LEAD LESS
CHIP CARRIER (LCC) PACKAGES
8-94
PLASTIC DUAL IN-LINE PACKAGES
P20
20-PIN PLASTIC DIP
0.300
0.320
I--':-==~
P22
22-PIN PLASTIC DIP
=-==-1
tE::::::::]]]~:
0.070
~1
0.145
0.200
0.145
0.200
~~~~
~_.O.ooa
\.0 0fkT D.ffi2
~::~ "'-II ~ j
r
1:"rv"""'{'V",f'o",...,,,r?
_15
0.090
0.110
P24-2
0.300
0.320
0.015
0.050
0.310
[.0.370
P24-1
0.008
0.012
15O
1.220
1.25il
-
I
-I
t t::::~:::::ll~
g:g~~1-
-
24-PIN PLASTIC DIP (600 mil.)
I"
1.220
~O
0.310
0.370
24-PIN PLASTIC DIP (300 mil.)
1
A-J
0.145
0.045
1-
0.145
0.120J.!~~~.~~:~~~;~:·~~
-t
T
gBL~
::~(;t::;:;;tt::;;;;;::;:;;;:;:;;;:;
~r
~
JI
~ 'o..frl~>1~
1-
0.160
T
0.160
0.016
0.090
!f.02O
"'!f.'mi
\.. 0.310.j
0.370
8-95
T
~.016
II...
u.u~u --I
0015
~
0 _15"
0
if.o6o -...111":"-- 0.610
I- 0.670 -
O.ooa
0.012
PLASTIC DUAL IN-LINE PACKAGES (Continued)
P28
28-PIN PLASTIC DIP
P48
48-PIN PLASTIC DIP
P40
P64
P68
4o-PIN PLASTIC DIP
64-PIN PLASTIC DIP
68-PIN PLASTIC DIP (Consult Factory)
8-96
DUAL IN-LINE PACKAGES
016
16-PIN CEROIP
r,-- 0.770 ± 0.020 ----l
~:~~::::J
0.305 ± 0.015
'-mrww
L
A,~u~
0.150±0.015M~
0.200 MAX.
0.150~
f
0.100 TYP.,
020
II I~0.025
~ ~ 0.055 TYP.
j
I-
0.375 REF.
20-PIN CEROIP
0.970
'"
022
0.935
"'
22-PIN CEROIP
1,111
'"
1.050
"'
.100
,005 +j L,200
.020
1~--'-M
' Y ..
- ~III- -I r--:mr
~
T
~
'-
I-- ..m
.022
+
090
,160
8-97
~
I- .320 --l
'
008
~
-I
DUAL IN-LINE PACKAGES (Continued)
024-1
24-PIN SIOEBRAZE THINOIP
1 -1.240 ----1
I.n..n..n.,n,.n 1.285 n..n..n..n..n.1
[:O::I~
--I !.- 0.095
0.105
-II- 0.050
0.060
0.125
0.150
--.E 0.190
I~
~rnmMMMl
Til
0.017
-11- 0.019
024-2
_
I~
j.;::
-I
24-PIN THINOIP (CEROIP)
I"
~
1.200 ± 0.020
1
C~ ~ ~ ~ ~ ~ ~ ~ ~ ]3'·'
PIN NO.1 IDENTIFICATION
0.005 MIN':r1
r-
~~"wro~5·"
U
U
JC
I I
0.050 ± 0.010...1
I.- 0.100 TYP.
·l1"w., ~L
0.150
± 0.025
+,."'""
J
0.290
if.32ii
0.018 ± 0.003
8-98
DUAL IN-LINE PACKAGES (Continued)
028-1
28-PIN CEROIP (600 mil.)
I - - -1 . 4 4 0 - - 1
1_ _ _ _ _ _
028-2
1.490 _____
J
28-PIN SIOEBRAZE THINOIP (400 mil.)
D
0·~~·~DL~~nT~~~~=0=.3=60=±~0=.0=0=3~0_·ll20_
t
0.380
-0.3tS
0-15.1]
~\
0
~+
0.100 TVP.
8-99
O.OOSt:
if.iil2 -I
O.400TYP.
DUAL IN-LINE PACKAGES (Continued)
028-3
28-PIN SIOEBRAZE (600 mil.)
1.380-1.420
"I
(35.052-36.068)
15
(14.224-15.240)
+----1---
L~~~~
I-1 I-1
.090-.110
(2.286-2.794)
.100-.200
(2.540-5.080)
.000-.098 ---.J
(.000-2.489) -I
.030-.060
(.762-1.524)
'--1-
.020-.060
L~J{-'''')
SEATING
"I -I r-
.120-.160
C;
~ ~
PLANE
.015-.022 .
(.381-.559)
(.127-
)
(3.048-4.064)
032
32-PIN SIOEBRAZE
[D9:OI~
O.lOOTYP.-ll-
-ll~:=
~[
~~
~ I-I
0.590-+1
ii.62ii
0.015
0.175
0.125
8-100
0.007
DUAL IN-LINE PACKAGES (Continued)
040-1
40-PIN SIOEBRAZE
r
I-
-I
1.980
2.030
I
0.595
0.625
--+-
l
I
I--
~
8
-1r-~
0.060
0.100 TYP.
0.020
~:LffiiKMr ~1'
r
~t:~
-I
O.015
-lrr 0.023
0.125
""ii1"75
040-2
\,
11
"-11-...
0.008
1- 0.012
_
0.600 TYP._
40-PIN CEROIP
I"
"I
0.IB'_8
2.028
2.077
O·t
I
_I
~
L 0.100TYP.
,--
---..I LO.04S
~
10.055
O.090lJmffiIf (jjl::::
illl..l
r~fJ[!
0.140
0.100
0.180
0.015
0.020
0.020
0.060
r--- 0•6OO =:J
I r-- 0.625
~t
O.
15·
Il.,.,t
0.012
DSP72103-0OS
8-101
DUAL IN-LINE PACKAGES (Continued)
D48-1
48-PIN SIDEBRAZE (600 mil.)
48-PIN SHRINK-DIP (400 mil.)
D48-2
C~:~~~==:J
0.100
0.200
O.
~:~:~~
'.090
~
g[]~ ---'----o.to
0.410
~.~:~O
.r~
" ~:~
I
t
r
1
0.030
0.008
0.012
0.120
0.160
=~
0.07ji::0
~::~~
0.005
0.085
L 0.190
t~~m
0'12~j~~'070
TYP.
0.170
0.015
0.038
D.ii6O
D.023
D58
~
0.020
,.06
_ 5 0.070
0.008
~~:O
TYP.
0.005
58-PIN SIDEBRAZE
t rt
,
0.280 MAX.
--.--
[0150+~
.
- 0.02"
:=IT
I ~ II ~ I
~~0.050±0.010
0.018 ± 0.004
~
I'=t....L
I r O•1OO ±0.010
--II If-- 0100TYP.
.
.
0.020±0.015
0.010±0.003-
I
,
8-102
I
•.
0.615 ± 0.020
DUAL IN-LINE PACKAGES (Continued)
D64
64-PIN SIDEBRAZE
I.
·1
3.40 ± 0.040
DDD DDDT
DDDDDDl
CJ D
CJ CJ CJ D
CJ D
0.S90 ± 0.015
PIN #1
[ 0.215 ± 0.017
~~~~~~+rh--o:o150.D15±0.012 ~ 2
23 ~
:JlO.01S:~~~±0.OO3T
1
068
68-PIN SIDEBRAZE SHRINK-DIP
C
~:!:~
==-:J
DO
0~.03S
0.020
--'--0.f95
0.625
~
b~- omo
0.12J~·~.=
O,..060~;:::;;n::n:I:l
"'"
0.170
0.015
0.023
8-103
0.OS5
0.190
o.oOS
0.012
0.&00
"lVP
I
0.900 ± 0. 015
1
PIN GRID ARRAY
G68
68-PIN PGA
1---1MQ.
1~1.18O
1.00TYP.
PIN 1 INDICATOR
0.080
L
MS5
INDEX CORNER
0.100
il.255L
D.14ii
MAX~fl-fl--II rr rr rr lf lf If--II-f t~
0.1OOTYP.-l
0.017
0.020
T
SMALL OUTLINE Ie
S20
2o-PIN SMALL OUTLINE Ie
0.010 x450 .t I-.
0.015
ILl.
8-104
PLASTIC LEADED CHIP CARRIERS
J20
20-PIN PLCC
J28
28-PIN PLCC
J32
32-PIN PLCC
0.008
D.li12
0.045 x 45'
-t t
I
:1
0.580
0.&00
o·r
0.545
Li
~.;;O--
0.J5t"LllJ
BSC!--0.500 -
j
10.395
: 0.405
'~
1--
-J I.-- 0.020
0.035
8-105
PLASTIC LEADED CHIP CARRIERS (Continued)
J52
52-PIN PLCC
~
~~;__
I
0.063
TYP.
:1
iJ
J68
68-PIN PLCC
:1
iT
-11-
8-106
0•015
0.020
I
0.077
-- TYP.
LEADLESS CHIP CARRIERS
L20-1
2o-PIN Lee
1_ -I
-I-11--
±0.290
0.010
0.055 ± 0.010
0.065 ± 0.010
I
-I
0.045TYP.
1- 1
j
--t-
5 EQUAL SPACES
AT 0.050 EACH
II
-"""''''-''''-'''''-'',
± 0.00_6
__ 0.070 TYP.
0.012 R TYP.
4 PLACES
2-PIN Lee
0.055 ± 0.0061
I
~~D
~
4""H",:j ."" . .-.j ~
L22
22-PIN Lee
0.071 + 0.007
- 0.007
--II
r-
0.025 ± 0.003-j
TYP.
J--
.~
0.090 ± 0.007
0.009 R. TYP.
-I
l-
0.060 + 0.003
- 0.006
8-107
0.0875 TYP.
-~
-t-0.025
3 EQUAL SPACES
AT 0.050 EACH
-t
0.008 R
20 PLACES "-...
0.425 ± 0.010
L20-2
-
0.012 R. TYP.
LEADLESS CHIP CARRIERS (Continued)
L28-1
28-PIN Lee
.450± .008
.080± .006
-I
0
I'"
~
.008R
(28 PLACES)
.070± .006
28-PIN Lee
n
-0
0.560
L
~0.342~
0.358
L28-3
.i .025 ± .003
T (28 PLACES)
~I-
"I
4 x 6 EQUAL SPACES
@.050EA.
L28-2
I- .050 ± .008
l-
-1 1-
0.050
0.088
t
-1+
0.045
0.055
0.390
0A10
SIDE
~
0.060~ 1-
0.045
0.007 0.055
0.011
0.120
28-PIN Lee
0.055 ± 0.0061
,~LD
4-±.~~
0.065 ± 0.006
r-
~I.-
-..l
8-108
r
t
LEAD LESS CHIP CARRIERS (Continued)
L32
32-PIN Lee
1~.550 ±
2X8EQUAl
SPACES@
.050 EA.
.008-1
.080 ± .006
--l
T
H
o
~
_.009R
(32 PLACES)
51
~====dU
I'
1
f-.040X45°
(3 PLACES)
44-PIN Lee
0.055
11_ 0.010
__
0.020
,,~--~~--~~
1--
0.500 TYP.
--I
050TYP
1.025± .003
+1
-II-~
L48
r.
T (32 PLACES)
2 X 8 EQUAL SPACES
@.050EA.
L44
.085 ± .010
f---J !:::-:-.015 x 45 - j
-I
1
-I
I-~
0.088
1
1
0.022
0.028
___
0.069
0.120
0.640
I~ 0.660
-I
48-PIN Lee
0.055
0.125
~I
I..
0.434
0.446
~
0.043
orrLl
0.572
0.045
0.090 ~I
8-109
I"
FO.554-1
0.572
II
LEADLESS CHIP CARRIERS (Continued)
L52
52-PIN Lee
ED
0.761
L~
L68-1
0.050 BSC.
T
I-
0.037 I
0.075-1
'-J..I--_----l-V
68-PIN Lee
OJIu
F
L68-2
o.554 ---l
0.566
I
68-PIN Lee
-I-l- 0.022
-+--+..::-;:;;;.--,,_____~
I I 0.028
0.805
i -:Is
""I..L.I..---.J.,.L.I
0072
0:088
t9~04S
-I
I-
~
0.082
0.055 0. 098 -t---t--
8-110
OJI
le
F
O.938 ---l
0.962
- I
CERPAK
E20
20-LEAD CERPACK
-.i
,0.015
0.019
~i=
L__
f
[
0.045 MAX.
0.305 MAX.
~
0.005 MIN.
l~'----"""'~~
t
f
0.010 0.045
0.040 0.092
I.
i
._
• •
0.245
0.300
•
0.250
0.370
1J:a
0.006
FLATPACKS
F20
F24
20-LEAD FLATPACK
PIN NO.1 MARK
PIN NO.1 MARK
1
~+0.002
20
0.050 TYP.
.-L
10
0002
0.005 ± 0:001
L! ·
t j --I
I
0.080 ± 0.010
11
I 0.285 ± 0.015
··
0.350 ± 0.010
I
24-LEAD FLATPACK
·
r
24
0.470
0.490
=rLl
t
I
j
0.045 MAX.
I
1- 0.030 M-;;-t 0.025 ± 0.015
--.l. .050 TYP.
12
.080 ± .010
j
1
*
: .017 ± .002
.600+ .015
i.
j
.285 ± .020
.005/.045
.400 ± .010
1-.025 + .015-1
I :
-j f-.030 MIN .005 + .02
-.001
SRD6167-024
8-111
FLATPACKS (Continued)
F64
64-LEAD FLATPACK
i
D
LEAD #64
"
LEAD #1
INDICATOR
LEAD #1
I-------~
-I!.0.010 ± 0.001
64 LEADS
__
0.050 ±0.005 TYP.
0.018 ± 0.002
r-
0.520 ± 0.015
SQUARE
-j
t
L.f====;=e::~==~F-~
tl
SEATING PLANE I
+
j.0.350
0.900 ± 0.015
---j
MIN.
8-112
0.080 ± 0.010
ORDERING INFORMATION
When ordering by TWX or Telex, the following format must be used:
A.
B.
C.
D.
E.
F.
G.
H.
I.
J.
K.
L.
M.
N.
O.
Complete Bill To.
Complete Ship To.
Purchase Order Number.
Certificate of Conformance. Y or N
Customer Source Inspection. Y or N
Government Source Inspection. Y or N
Government Contract Number and Rating.
Requested Routing.
lOT Part Number Each item ordered must use the complete part number exactly as listed in the price book.
SCD Number.
Customer Part NumberlDrawing Number/Revision LevelSpecify whether part number is for reference only, mark only, or if extended processing to customer specification is
required.
Customer General Specification Numbers/Other Referenced Drawing Numbers/Revision Levels.
Request Date With Exact Quantity.
Unit Price.
Special Instructions, Including Q.A. Clauses.
Federal Supply Code Number - 61772
Dun & Bradstreet Number - 03·814·2600
Federal Tax 1.0. - 94·2669985
TLX# - 887766
FAX# - 408-737·3468
Minimum Order Quantities:
OEM - $500.00/$100 per line item
Distributor - $1,000.00/$100 per line item
100 piece minimum on all Flatpack orders
ORDERING DESCRIPTION
lOT
xxxxx ~
~_A~
DEVICE TYPE
PCWER
999
SPEED
A
PACKAGE
A
PROCESSI
TEMPERATURE
~~~~-
COMMERCIAL
INDUSTRIAL
MILITARY
LBLANK
I
B
L.~~~~~~~_
L._ _
~
L._ _ _ _
~
__
SEE PACKAGE DESCRIPTION TABLE
_ _ _ _ _ _ _ _ _ SPEED
L.~~~~~~~
GUARANTEED MINIMUM PERFORMANCE
MEASURED IN NANOSECONDS
_ _ _ _ _~_ _ _ POWER
~~~~
__
~
O·C to +70"C
·40"C to + 85"C
·55"C to + 125"C
Screened to MIL-STO-883,
Method 5004, Class B
S
L
_ _ _ _ _ _ DEVICE
STANDARD POWER
LOW PCWER
I.E. 6116
TYPE
tOT XX FCT138
lOT XX AHCT138
TEMPERATURE
X
PACKAGE
X
PROCESS
RANGE
Blank
B
I
i:
L......~_ _ _ _ _ _ _ _ _ _
-I
L-~~~~~_ _~~~~_ _~_ _
C
XC
T
PLASTIC DIP
CERDIP
CERAMIC SIOEBRAZE
CERAMIC SIOEBRAZE SHRINK-DIP
THINDIP (300 mil, 24-Pin)
G
PIN GRID ARRAY
SO
PLASTIC SMALL OUTLINE Ie
PLASTIC LEADED CHIP CARRIER
o
PACKAGE
DESCRIPTION
TABLE
Siandard Process;ng 148 Hour Bum·ln)
MtL-STO-883. Class B, Method 5004
SEE PACKAGE DESCRIPTION TABLE
74
54
O"G to +70"C
-55"C to +125"C
XL
Ml
LEADLESS CHIP CARRIER
FINE-PITCH Lee
MEDIUM-PITCH lee
CERPACK
FLATPACK
U
DIE
NOTE,
When a product is available in a package type with more than one pin count or package dimension, please
indicate the package designator when ordering - (i.e. IDT6116L70L28-2 or IDT6116L70L32).
8-113
FACTORY DIRECT OFFICES
CORPORATE HEADQUARTERS
3236 Scoll Boulevard
P.O. Box 58015
Santa Clara, CA 95052·8015
CENTRAL HEADQUARTERS
999 Plaza Dnve
Suite 400
(408) 727·6116
TLX: 887766
NORTHWESTERN HEADQUARTERS
3236 Scott Boulevard
P.O. Box 58015
Santa Clara, CA 95052-6015
(408) 727-6116
TlX: 887766
SOUTH CENTRAL REGIONAL OFFICE
5501 LBJ Freeway
Suite 500
Suile 3SA
(312) 843-1262
Dallas, TX 75240
(214) 458-0466 or 458-0467
Melbourne, FL 32935
(305) 242-1821
TWX: 910·651·1910
TWX: 910-861-4034
TLX: 592163
NORTH CENTRAL REGIONAL OFFICE
3601 W. 77th Street
Suite 860
Minneapolis, MN 55435
(612) 831-5422
TLX: 291013
EAsTERN HEADQUARTERS
15 Pleasant Street Connector
Suite 502
Framingham, MA 01701
EUROPEAN HEADQUARTERS
15 Bridge Street
Leathemead
Surrey, UK KT228BL
44·372·377375
llX: 851-946240
Schaumburg, IL 60195
SOUTHWESTERN REGIONAL OFFICE
12777 Valley View Street
SUite 262
Garden Grove, CA 92645
(714) 891-6651 or (213) 598-3076
(617) 872-4900
TLX: 855249
SOUTHEASTERN REGIONAL OFFICE
478 Ballard Drive
NORTHEASTERN REGIONAL OFFICE
111 Smithtown Bypass
Suite 202
Hauppauge, NY 11787
(516) 360-3370
TlX: 62921896
DOMESTIC SALES REPRESENTATIVES
ALABAMA
Montgomery Marketing
Huntsville, AL
(205) 830-0498
Altamonte Springs, FL
(305) 339-3855
ALASKA
Integrated Device Technology, Inc.
Santa Clara. CA
Lawrence ASSOciates, Inc.
Boca Raton, FL
(305) 368-7373
(408) 727-6116
ARIZONA
Western High Tech Marketing
Scottsdale, AZ
(602) 860-2702
ARKANSAS
Integrated Device Technology, Inc.
Dallas, TX
(214) 458·0466
CALIFORNIA
Bestronics Inc.
Culver City, CA
(213) 870·9191
Bestronics Inc.
Irvine, CA
(714) 261-7233
8estronics Inc.
Woodland Hills, CA
FLORIDA
Lawrence ASSOCIates, Inc.
Lawrence Associates, Inc
Clearwater, FL
(813) 584·8110
lawrence ASSOCiates, Inc.
West Melbourne, FL
Technology Sales Inc.
Mountain View, CA
(415) 960·0600
CANADA (EASTERN)
Bylewide Marketing Inc.
Lachine, Quebec
(514) 636·4121
MASSACHUSETTS
Integrated Device Technology, Inc.
Framingham, MA
(617) 872-4900
MICHIGAN
Rathsburg Associates, Inc.
Southfield, MI
(313) 559-9700
(305) 724·8294
GEORGIA
Montgomery Marketing
Norcross, GA
MINNESOTA
Comprehensive Technical Sales
Eden Prairie, MN
(612) 941·7181
(404) 447·6124
HAWAII
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727-6116
IDAHO
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727-6116
(81B) 704·5616
Integrated Device Technology, Inc.
Garden Grove, CA
(714) 891-6651
MARYLAND
Micro Camp Inc.
Baltimore, MD
(301) 644-5700
Thorson Rocky Mountain
Englewood, CO
(303) 779-0666
ILLINOIS
Synmark Sales
Park Ridge, IL
(312) 390-9696
INDIANA
Arete Sales
Ft. Wayne, IN
(219) 423-1478
MISSISSIPPI
Montgomery Marketing
Huntsville, AL
(205) 830-0498
MISSOURI
Design Solutions Inc.
St. Louis, MO
(314) 961·7170
MONTANA
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727·6116
NEBRASKA
Design Solutions Inc.
Shawnee Mission, KS
(913) 677·4747
NEVADA
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727·6116
Bytewide Marketing Inc.
Mississagua, Ontario
(416) 675·1874
CANADA (WESTERN)
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727·6116
COLORADO
Thorson Rocky Mountain
Englewood, CO
(303) 779-0666
CONNECTICUT
Lindco Associates
Southbury, cr
(203) 264·7200
DELAWARE
Micro Comp Inc.
Baillmore, MD
(301) 644·5700
IOWA
Rep Associates Corp.
Cedar Rapids, IA
(319) 373-0152
KANSAS
DeSign Solutions Inc.
Shawnee Mission, KS
(913) 677·4747
KENTUCKY
Norm Case Associates
Rocky River, OH
(216) 333-0400
LOUISIANA
Integrated Device Technology, Inc.
Dallas, TX
(214) 458·0466
MAINE
Integrated DeVice Technology, Inc.
Framingham, MA
(617) 872-4900
Western High Tech Marketing
(Clark County, NV)
Scottsdale. AZ
(602) 860-2702
NEW HAMPSHIRE
Integrated Device Technology, Inc.
Framingham, MA
(617) 872-4900
NEW YORK, Continued
Quality Components
Manlius, NY
(315) 682-8885
SJ Associates
Jamaica, NY
(718) 291·3232
NORTH CAROLINA
Montgomery Marketing
Cary, NC
(919) 467·6319
OHIO
Norm Case Associates
Rocky River, OH
(216) 333-0400
OKLAHOMA
Ion Associates
Tulsa, OK
(918) 664-0186
OREGON
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727·6116
PENNSYLVANIA
Norm Case Associates
Rocky River, OH
(216) 333-0400
SJ Associates
Jamaica, NY
(718) 291-3232
RHODE ISLAND
Integrated Device Technology, Inc.
Framingham, MA
(617) 872-4900
SOUTH CAROLINA
Montgomery Marketing
Cary, NC
(919) 467·6319
TEXAS
Ion Associates
Austin, TX
(512) 331-7251
Ion Associates
Grand Prairie, TX
(214) 647·8225
Ion Associates
Houston, TX
NEW JERSEY
SJ Associates
Mt. Laurel, NJ
(609) 866-1234
(713) 537·7717
NEW MEXICO
Western High Tech Marketing
Albuquerque, NM
(505) 884-2256
(801) 292·8991
NEW YORK
Quality Components
Buffalo, NY
(716) 837-5430
(617) 872·4900
8-114
UTAH
Anderson Associates
Bountiful, UT
VERMONT
Integrated Device Technology, Inc.
Framingham, MA
VIRGINIA
Micro Camp Inc.
Baltimore, MO
(301) 644-5700
WASHINGTON
Integrated Device Technology, Inc.
Santa Clara, CA
(408) 727-6116
WEST VIRGINIA
Norm Case Associates
Rocky River, OH
(216) 333-0400
WISCONSIN
Comprehensive Technical Sales
Eden Prairie, MN
(612) 941-7181
WVOMING
Thorson Rocky Mountain
Englewood, CO
(303) 779·0666
AUTHORIZED DISTRIBUTORS
ALABAMA
OREGON
Hallmark ElectroniCS
Huntsville, AL
HamlltonfAvnel
Sacramento, CA
Hallmark Electronics
Columbia, MD
(205) 837·8700
(916) 925-2216
(301) 988-9800
Hamilton! Avnet
Huntsville, AL
Hamlltonl Avnet
San Diego, CA
(619) 571-7510
(205) 837·721 0
Hamllton/Avnet
Fairfield. NJ
(201) 575-3390
ARIZONA
MASSACHUSETTS
PENNSYLVANIA
NEW MEXICO
Hallmark Electronics
Phoenix AZ
(602) 437·1200
TEXAS
InSight ElectroniCS
San Diego, CA
(619) 587·0471
HamlltonlAvnet
Temple. AZ
(602) 231-5100
NEW YORK
CANADA
GEORGIA
CALIFORNIA
HamlltonlAvnet
Diplomat Electronics
Chatsworth, CA
(213) 700·8700
(604) 437-6667
HamlitonlAvnet
Norcross, GA
(404) 447-7507
Insight Electronics
Tempe, AZ
(602) 829-1800
Diplomat Electronics
Sunnyvale, CA
(408) 737-0204
Burnaby, Be
HamlltonlAvnet
MISSlssauga, ONT
(416) 677-7432
MICHIGAN
HamlltonlAvnet
Grand Rapids, MI
(616) 243·8805
Hamllton/Avnet
TX
ILLINOIS
Hallmark Electronics
WcxxJale,lL
(312) 860-3800
HamlltonlAvnet
Nepean,ONT
(613) 226·1700
HamlltonlAvnet
Bensenville, IL
(312) 860·7700
HamiltonlAvnet
SI. Laurent, QUE
(514) 335-1000
HamlltonlAvnet
Stafford, TX
(713) 780-1771
MINNESOTA
Hallmark Electronics
Bloomington, MN
(612) 854·3223
UTAH
INDIANA
HamiltonlAvnet
Minnetonka. MN
(612) 932·0600
COLORADO
NORTH CAROLINA
Hallmark Electronics
Canoga Park, CA
(818) 716-7300
HamlltonlAvnet
Carmel, IN
(317) 844·9333
Hamllton/Avnel
Englewood, CO
(303) 740-1000
Hamilton/Avnet
Chatsworth, CA
(818) 700·6500
Hallmark Electronics
Wallingford, CT
(203) 269·0100
HamiltonlAvnet
Danbury, CT
(203) 797·2800
Hamllton/Avnet
Costa Mesa, CA
(714) 641·4100 or
(714) 754·6111
Hamilton! Avnet
Gardena, CA
(213) 217-6700
HamlltonlAvnet
Salt Lake City, UT
(801) 972·2800
IOWA
CONNECTICUT
Diplomat Electronics
Danbury, CT
(203) 797-9674
Hallmark ElectroniCS
Tustin, CA
(714) 669-4700
MISSOURI
Hallmark Electronics
Earth City, MO
(314) 291-5350
WASHINGTON
HamiltonlAvnet
Cedar Rapids, IA
(319) 362-4757
HamiltonlAvnet
Earth City, MO
(314) 344-1200
KANSAS
NEW HAMPSHIRE
OHIO
Hamilton/Avnet
Overland Park, KS
(913) 888·8900
NEW JERSEY
Diplomat Electronics
Totowa, NJ
(201) 785-1830
KENTUCKY
FLORIDA
Hallmark Electronics
Orlando, FL
(305) 855-4020
WISCONSIN
Hallmark Electronics
Lenexa, KS
(913) 888·4747
Hamilton/Avnet
Lexington, KY
(606) 259-1475
Hallmark Electronics
Mt Loral, NJ
(609) 424·7300
MARYLAND
Diplomat Electronics
Columbia, MD
(301) 995-1226
HamlltonlAvnet
Cleveland, OH
(216) 831-3500
HamlltonlAvnet
Dayton,OH
(513) 439·6700
Hamilton!Avnet
Ontario. CA
(714) 989-4602
INTERNATIONAL AUTHORIZED REPRESENTATIVES
AUSTRALIA
GERMANY
JAPAN
SWEDEN
ProtronlCS Ply. Ltd
Adelaide. S,A
Tel 61-8-212-3111
BELGIUM
SWITZERLAN D
BETEA SAINV
Brussels, Belgium
Tel.: 32·2· 736-8050
THE NETHERLANDS
DENMARK
Kokkedal, Denmark
Tel_ 45·2·24-48·88
TAIWAN
ISRAEL
NORWAY
FINLAND
Turlon Oy
HelSinki, Finland
Tel.: 358-90-372-144
FRANCE
REA
Lavallols Perret. France
Tel 33-1-75-81·111
Rep'T rontc SA
Orsay, France
Tet.: 33-1-69·288700
UNITED KINGDOM
ITALY
Mlcroellt SRL
Milan, Italy
Tel __ 39-2·469044
SPAIN
Mlcroelil SRL
Rome. Italy
Tel., 39·6·890892
8-115
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